Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 16
- Kernel Errors: 34
1 06:46:59.761667 lava-dispatcher, installed at version: 2023.10
2 06:46:59.761881 start: 0 validate
3 06:46:59.762014 Start time: 2024-02-03 06:46:59.762007+00:00 (UTC)
4 06:46:59.762132 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:46:59.762267 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 06:47:00.035250 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:47:00.035995 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:47:37.835790 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:47:37.836521 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:47:38.108222 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:47:38.108960 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 06:47:41.878640 validate duration: 42.12
14 06:47:41.879006 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:47:41.879140 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:47:41.879266 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:47:41.879423 Not decompressing ramdisk as can be used compressed.
18 06:47:41.879513 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 06:47:41.879581 saving as /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/ramdisk/rootfs.cpio.gz
20 06:47:41.879666 total size: 43284872 (41 MB)
21 06:47:42.146073 progress 0 % (0 MB)
22 06:47:42.158887 progress 5 % (2 MB)
23 06:47:42.171033 progress 10 % (4 MB)
24 06:47:42.183074 progress 15 % (6 MB)
25 06:47:42.195040 progress 20 % (8 MB)
26 06:47:42.206945 progress 25 % (10 MB)
27 06:47:42.218678 progress 30 % (12 MB)
28 06:47:42.230963 progress 35 % (14 MB)
29 06:47:42.243054 progress 40 % (16 MB)
30 06:47:42.255543 progress 45 % (18 MB)
31 06:47:42.267806 progress 50 % (20 MB)
32 06:47:42.280233 progress 55 % (22 MB)
33 06:47:42.292212 progress 60 % (24 MB)
34 06:47:42.304318 progress 65 % (26 MB)
35 06:47:42.317154 progress 70 % (28 MB)
36 06:47:42.329453 progress 75 % (30 MB)
37 06:47:42.341000 progress 80 % (33 MB)
38 06:47:42.353384 progress 85 % (35 MB)
39 06:47:42.365622 progress 90 % (37 MB)
40 06:47:42.377662 progress 95 % (39 MB)
41 06:47:42.389218 progress 100 % (41 MB)
42 06:47:42.389523 41 MB downloaded in 0.51 s (80.96 MB/s)
43 06:47:42.389739 end: 1.1.1 http-download (duration 00:00:01) [common]
45 06:47:42.390116 end: 1.1 download-retry (duration 00:00:01) [common]
46 06:47:42.390235 start: 1.2 download-retry (timeout 00:09:59) [common]
47 06:47:42.390351 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 06:47:42.390513 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 06:47:42.390584 saving as /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/kernel/Image
50 06:47:42.390674 total size: 51532288 (49 MB)
51 06:47:42.390772 No compression specified
52 06:47:42.425247 progress 0 % (0 MB)
53 06:47:42.439002 progress 5 % (2 MB)
54 06:47:42.453011 progress 10 % (4 MB)
55 06:47:42.467145 progress 15 % (7 MB)
56 06:47:42.481574 progress 20 % (9 MB)
57 06:47:42.496361 progress 25 % (12 MB)
58 06:47:42.511096 progress 30 % (14 MB)
59 06:47:42.525837 progress 35 % (17 MB)
60 06:47:42.540273 progress 40 % (19 MB)
61 06:47:42.554660 progress 45 % (22 MB)
62 06:47:42.568970 progress 50 % (24 MB)
63 06:47:42.583556 progress 55 % (27 MB)
64 06:47:42.598013 progress 60 % (29 MB)
65 06:47:42.612536 progress 65 % (31 MB)
66 06:47:42.627089 progress 70 % (34 MB)
67 06:47:42.641530 progress 75 % (36 MB)
68 06:47:42.655540 progress 80 % (39 MB)
69 06:47:42.669587 progress 85 % (41 MB)
70 06:47:42.683797 progress 90 % (44 MB)
71 06:47:42.698175 progress 95 % (46 MB)
72 06:47:42.712363 progress 100 % (49 MB)
73 06:47:42.712615 49 MB downloaded in 0.32 s (152.65 MB/s)
74 06:47:42.712811 end: 1.2.1 http-download (duration 00:00:00) [common]
76 06:47:42.713047 end: 1.2 download-retry (duration 00:00:00) [common]
77 06:47:42.713139 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:47:42.713255 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:47:42.713437 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 06:47:42.713508 saving as /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/dtb/mt8192-asurada-spherion-r0.dtb
81 06:47:42.713571 total size: 47278 (0 MB)
82 06:47:42.713642 No compression specified
83 06:47:42.715230 progress 69 % (0 MB)
84 06:47:42.715547 progress 100 % (0 MB)
85 06:47:42.715736 0 MB downloaded in 0.00 s (20.86 MB/s)
86 06:47:42.715907 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:47:42.716269 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:47:42.716388 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:47:42.716505 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:47:42.716666 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 06:47:42.716764 saving as /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/modules/modules.tar
93 06:47:42.716855 total size: 8624064 (8 MB)
94 06:47:42.716946 Using unxz to decompress xz
95 06:47:42.721915 progress 0 % (0 MB)
96 06:47:42.752279 progress 5 % (0 MB)
97 06:47:42.789234 progress 10 % (0 MB)
98 06:47:42.826927 progress 15 % (1 MB)
99 06:47:42.856672 progress 20 % (1 MB)
100 06:47:42.882735 progress 25 % (2 MB)
101 06:47:42.910798 progress 30 % (2 MB)
102 06:47:42.939182 progress 35 % (2 MB)
103 06:47:42.964530 progress 40 % (3 MB)
104 06:47:42.991163 progress 45 % (3 MB)
105 06:47:43.018752 progress 50 % (4 MB)
106 06:47:43.045922 progress 55 % (4 MB)
107 06:47:43.073675 progress 60 % (4 MB)
108 06:47:43.104087 progress 65 % (5 MB)
109 06:47:43.132474 progress 70 % (5 MB)
110 06:47:43.158629 progress 75 % (6 MB)
111 06:47:43.188553 progress 80 % (6 MB)
112 06:47:43.217001 progress 85 % (7 MB)
113 06:47:43.244635 progress 90 % (7 MB)
114 06:47:43.279202 progress 95 % (7 MB)
115 06:47:43.309471 progress 100 % (8 MB)
116 06:47:43.314544 8 MB downloaded in 0.60 s (13.76 MB/s)
117 06:47:43.314877 end: 1.4.1 http-download (duration 00:00:01) [common]
119 06:47:43.315313 end: 1.4 download-retry (duration 00:00:01) [common]
120 06:47:43.315440 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 06:47:43.315567 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 06:47:43.315685 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:47:43.315815 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 06:47:43.316087 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll
125 06:47:43.316280 makedir: /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin
126 06:47:43.316426 makedir: /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/tests
127 06:47:43.316562 makedir: /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/results
128 06:47:43.316711 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-add-keys
129 06:47:43.316912 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-add-sources
130 06:47:43.317081 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-background-process-start
131 06:47:43.317244 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-background-process-stop
132 06:47:43.317411 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-common-functions
133 06:47:43.317540 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-echo-ipv4
134 06:47:43.317670 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-install-packages
135 06:47:43.317796 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-installed-packages
136 06:47:43.317923 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-os-build
137 06:47:43.318074 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-probe-channel
138 06:47:43.318205 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-probe-ip
139 06:47:43.318333 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-target-ip
140 06:47:43.318497 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-target-mac
141 06:47:43.318668 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-target-storage
142 06:47:43.318840 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-test-case
143 06:47:43.319003 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-test-event
144 06:47:43.319141 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-test-feedback
145 06:47:43.319271 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-test-raise
146 06:47:43.319399 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-test-reference
147 06:47:43.319534 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-test-runner
148 06:47:43.319661 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-test-set
149 06:47:43.319789 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-test-shell
150 06:47:43.319939 Updating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-install-packages (oe)
151 06:47:43.320152 Updating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/bin/lava-installed-packages (oe)
152 06:47:43.320284 Creating /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/environment
153 06:47:43.320394 LAVA metadata
154 06:47:43.320470 - LAVA_JOB_ID=12694787
155 06:47:43.320544 - LAVA_DISPATCHER_IP=192.168.201.1
156 06:47:43.320658 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 06:47:43.320727 skipped lava-vland-overlay
158 06:47:43.320805 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 06:47:43.320889 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 06:47:43.320965 skipped lava-multinode-overlay
161 06:47:43.321044 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 06:47:43.321127 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 06:47:43.321203 Loading test definitions
164 06:47:43.321296 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 06:47:43.321401 Using /lava-12694787 at stage 0
166 06:47:43.321778 uuid=12694787_1.5.2.3.1 testdef=None
167 06:47:43.321868 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 06:47:43.321953 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 06:47:43.322561 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 06:47:43.322795 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 06:47:43.323518 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 06:47:43.323749 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 06:47:43.324367 runner path: /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/0/tests/0_igt-kms-mediatek test_uuid 12694787_1.5.2.3.1
176 06:47:43.324531 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 06:47:43.324755 Creating lava-test-runner.conf files
179 06:47:43.324821 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694787/lava-overlay-_3nb4mll/lava-12694787/0 for stage 0
180 06:47:43.324957 - 0_igt-kms-mediatek
181 06:47:43.325088 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 06:47:43.325205 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 06:47:43.332720 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 06:47:43.332865 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 06:47:43.332966 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 06:47:43.333055 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 06:47:43.333146 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 06:47:44.850129 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 06:47:44.850527 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 06:47:44.850639 extracting modules file /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694787/extract-overlay-ramdisk-1v883w4k/ramdisk
191 06:47:45.116869 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 06:47:45.117075 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 06:47:45.117224 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694787/compress-overlay-gcvy2jwg/overlay-1.5.2.4.tar.gz to ramdisk
194 06:47:45.117328 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694787/compress-overlay-gcvy2jwg/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694787/extract-overlay-ramdisk-1v883w4k/ramdisk
195 06:47:45.125857 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 06:47:45.126039 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 06:47:45.126170 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 06:47:45.126304 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 06:47:45.126427 Building ramdisk /var/lib/lava/dispatcher/tmp/12694787/extract-overlay-ramdisk-1v883w4k/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694787/extract-overlay-ramdisk-1v883w4k/ramdisk
200 06:47:46.301394 >> 370008 blocks
201 06:47:52.412677 rename /var/lib/lava/dispatcher/tmp/12694787/extract-overlay-ramdisk-1v883w4k/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/ramdisk/ramdisk.cpio.gz
202 06:47:52.413281 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 06:47:52.413474 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 06:47:52.413642 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 06:47:52.413816 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/kernel/Image'
206 06:48:06.563403 Returned 0 in 14 seconds
207 06:48:06.664029 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/kernel/image.itb
208 06:48:07.540040 output: FIT description: Kernel Image image with one or more FDT blobs
209 06:48:07.540428 output: Created: Sat Feb 3 06:48:07 2024
210 06:48:07.540511 output: Image 0 (kernel-1)
211 06:48:07.540581 output: Description:
212 06:48:07.540651 output: Created: Sat Feb 3 06:48:07 2024
213 06:48:07.540716 output: Type: Kernel Image
214 06:48:07.540778 output: Compression: lzma compressed
215 06:48:07.540839 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
216 06:48:07.540897 output: Architecture: AArch64
217 06:48:07.540952 output: OS: Linux
218 06:48:07.541006 output: Load Address: 0x00000000
219 06:48:07.541063 output: Entry Point: 0x00000000
220 06:48:07.541118 output: Hash algo: crc32
221 06:48:07.541172 output: Hash value: 380e7c3c
222 06:48:07.541226 output: Image 1 (fdt-1)
223 06:48:07.541281 output: Description: mt8192-asurada-spherion-r0
224 06:48:07.541335 output: Created: Sat Feb 3 06:48:07 2024
225 06:48:07.541388 output: Type: Flat Device Tree
226 06:48:07.541440 output: Compression: uncompressed
227 06:48:07.541493 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 06:48:07.541546 output: Architecture: AArch64
229 06:48:07.541599 output: Hash algo: crc32
230 06:48:07.541652 output: Hash value: cc4352de
231 06:48:07.541705 output: Image 2 (ramdisk-1)
232 06:48:07.541757 output: Description: unavailable
233 06:48:07.541810 output: Created: Sat Feb 3 06:48:07 2024
234 06:48:07.541863 output: Type: RAMDisk Image
235 06:48:07.541915 output: Compression: Unknown Compression
236 06:48:07.541967 output: Data Size: 56453078 Bytes = 55129.96 KiB = 53.84 MiB
237 06:48:07.542020 output: Architecture: AArch64
238 06:48:07.542073 output: OS: Linux
239 06:48:07.542125 output: Load Address: unavailable
240 06:48:07.542178 output: Entry Point: unavailable
241 06:48:07.542230 output: Hash algo: crc32
242 06:48:07.542282 output: Hash value: 50f20bfb
243 06:48:07.542335 output: Default Configuration: 'conf-1'
244 06:48:07.542388 output: Configuration 0 (conf-1)
245 06:48:07.542454 output: Description: mt8192-asurada-spherion-r0
246 06:48:07.542508 output: Kernel: kernel-1
247 06:48:07.542560 output: Init Ramdisk: ramdisk-1
248 06:48:07.542613 output: FDT: fdt-1
249 06:48:07.542666 output: Loadables: kernel-1
250 06:48:07.542717 output:
251 06:48:07.542914 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 06:48:07.543013 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 06:48:07.543116 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 06:48:07.543209 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:34) [common]
255 06:48:07.543289 No LXC device requested
256 06:48:07.543369 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 06:48:07.543452 start: 1.7 deploy-device-env (timeout 00:09:34) [common]
258 06:48:07.543530 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 06:48:07.543601 Checking files for TFTP limit of 4294967296 bytes.
260 06:48:07.544110 end: 1 tftp-deploy (duration 00:00:26) [common]
261 06:48:07.544213 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 06:48:07.544308 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 06:48:07.544434 substitutions:
264 06:48:07.544499 - {DTB}: 12694787/tftp-deploy-2gqx_yo1/dtb/mt8192-asurada-spherion-r0.dtb
265 06:48:07.544563 - {INITRD}: 12694787/tftp-deploy-2gqx_yo1/ramdisk/ramdisk.cpio.gz
266 06:48:07.544621 - {KERNEL}: 12694787/tftp-deploy-2gqx_yo1/kernel/Image
267 06:48:07.544678 - {LAVA_MAC}: None
268 06:48:07.544733 - {PRESEED_CONFIG}: None
269 06:48:07.544787 - {PRESEED_LOCAL}: None
270 06:48:07.544841 - {RAMDISK}: 12694787/tftp-deploy-2gqx_yo1/ramdisk/ramdisk.cpio.gz
271 06:48:07.544896 - {ROOT_PART}: None
272 06:48:07.544949 - {ROOT}: None
273 06:48:07.545003 - {SERVER_IP}: 192.168.201.1
274 06:48:07.545056 - {TEE}: None
275 06:48:07.545111 Parsed boot commands:
276 06:48:07.545166 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 06:48:07.545346 Parsed boot commands: tftpboot 192.168.201.1 12694787/tftp-deploy-2gqx_yo1/kernel/image.itb 12694787/tftp-deploy-2gqx_yo1/kernel/cmdline
278 06:48:07.545436 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 06:48:07.545522 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 06:48:07.545614 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 06:48:07.545700 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 06:48:07.545768 Not connected, no need to disconnect.
283 06:48:07.545841 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 06:48:07.545919 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 06:48:07.545985 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 06:48:07.550131 Setting prompt string to ['lava-test: # ']
287 06:48:07.550569 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 06:48:07.550690 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 06:48:07.550793 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 06:48:07.550889 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 06:48:07.551097 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 06:48:12.688450 >> Command sent successfully.
293 06:48:12.691356 Returned 0 in 5 seconds
294 06:48:12.791751 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 06:48:12.792069 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 06:48:12.792175 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 06:48:12.792300 Setting prompt string to 'Starting depthcharge on Spherion...'
299 06:48:12.792413 Changing prompt to 'Starting depthcharge on Spherion...'
300 06:48:12.792489 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 06:48:12.792769 [Enter `^Ec?' for help]
302 06:48:12.967112
303 06:48:12.967282
304 06:48:12.967366 F0: 102B 0000
305 06:48:12.967435
306 06:48:12.967498 F3: 1001 0000 [0200]
307 06:48:12.967563
308 06:48:12.971024 F3: 1001 0000
309 06:48:12.971120
310 06:48:12.971194 F7: 102D 0000
311 06:48:12.971255
312 06:48:12.971313 F1: 0000 0000
313 06:48:12.971371
314 06:48:12.975020 V0: 0000 0000 [0001]
315 06:48:12.975139
316 06:48:12.975208 00: 0007 8000
317 06:48:12.975278
318 06:48:12.978423 01: 0000 0000
319 06:48:12.978524
320 06:48:12.978593 BP: 0C00 0209 [0000]
321 06:48:12.978654
322 06:48:12.981961 G0: 1182 0000
323 06:48:12.982069
324 06:48:12.982138 EC: 0000 0021 [4000]
325 06:48:12.982202
326 06:48:12.985920 S7: 0000 0000 [0000]
327 06:48:12.986054
328 06:48:12.986126 CC: 0000 0000 [0001]
329 06:48:12.986189
330 06:48:12.988921 T0: 0000 0040 [010F]
331 06:48:12.989030
332 06:48:12.989100 Jump to BL
333 06:48:12.989171
334 06:48:13.014115
335 06:48:13.014302
336 06:48:13.014423
337 06:48:13.021712 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 06:48:13.025914 ARM64: Exception handlers installed.
339 06:48:13.029048 ARM64: Testing exception
340 06:48:13.032159 ARM64: Done test exception
341 06:48:13.040825 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 06:48:13.047820 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 06:48:13.053757 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 06:48:13.064605 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 06:48:13.071121 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 06:48:13.082008 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 06:48:13.092240 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 06:48:13.098850 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 06:48:13.116772 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 06:48:13.120276 WDT: Last reset was cold boot
351 06:48:13.123447 SPI1(PAD0) initialized at 2873684 Hz
352 06:48:13.126927 SPI5(PAD0) initialized at 992727 Hz
353 06:48:13.130252 VBOOT: Loading verstage.
354 06:48:13.137300 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 06:48:13.140209 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 06:48:13.143958 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 06:48:13.147069 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 06:48:13.154509 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 06:48:13.161267 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 06:48:13.171673 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 06:48:13.171829
362 06:48:13.171899
363 06:48:13.182076 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 06:48:13.185294 ARM64: Exception handlers installed.
365 06:48:13.188850 ARM64: Testing exception
366 06:48:13.188974 ARM64: Done test exception
367 06:48:13.195758 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 06:48:13.198856 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 06:48:13.213287 Probing TPM: . done!
370 06:48:13.213443 TPM ready after 0 ms
371 06:48:13.220583 Connected to device vid:did:rid of 1ae0:0028:00
372 06:48:13.227438 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 06:48:13.283774 Initialized TPM device CR50 revision 0
374 06:48:13.295369 tlcl_send_startup: Startup return code is 0
375 06:48:13.295549 TPM: setup succeeded
376 06:48:13.306757 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 06:48:13.315503 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 06:48:13.326344 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 06:48:13.336447 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 06:48:13.339442 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 06:48:13.348925 in-header: 03 07 00 00 08 00 00 00
382 06:48:13.352429 in-data: aa e4 47 04 13 02 00 00
383 06:48:13.356497 Chrome EC: UHEPI supported
384 06:48:13.363874 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 06:48:13.367671 in-header: 03 ad 00 00 08 00 00 00
386 06:48:13.367857 in-data: 00 20 20 08 00 00 00 00
387 06:48:13.371662 Phase 1
388 06:48:13.374909 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 06:48:13.378581 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 06:48:13.386859 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 06:48:13.390241 Recovery requested (1009000e)
392 06:48:13.397123 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 06:48:13.403055 tlcl_extend: response is 0
394 06:48:13.412464 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 06:48:13.417481 tlcl_extend: response is 0
396 06:48:13.424580 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 06:48:13.444986 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 06:48:13.451294 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 06:48:13.451487
400 06:48:13.451562
401 06:48:13.461956 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 06:48:13.465389 ARM64: Exception handlers installed.
403 06:48:13.465568 ARM64: Testing exception
404 06:48:13.468937 ARM64: Done test exception
405 06:48:13.490016 pmic_efuse_setting: Set efuses in 11 msecs
406 06:48:13.493571 pmwrap_interface_init: Select PMIF_VLD_RDY
407 06:48:13.500050 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 06:48:13.504117 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 06:48:13.510669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 06:48:13.514309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 06:48:13.517807 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 06:48:13.522333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 06:48:13.529606 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 06:48:13.532701 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 06:48:13.536658 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 06:48:13.544134 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 06:48:13.547973 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 06:48:13.551546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 06:48:13.554823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 06:48:13.562842 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 06:48:13.566312 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 06:48:13.573901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 06:48:13.581271 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 06:48:13.584717 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 06:48:13.591924 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 06:48:13.596611 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 06:48:13.603645 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 06:48:13.606811 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 06:48:13.614050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 06:48:13.617886 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 06:48:13.622148 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 06:48:13.629468 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 06:48:13.633392 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 06:48:13.640544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 06:48:13.643939 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 06:48:13.647798 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 06:48:13.655390 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 06:48:13.659071 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 06:48:13.662886 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 06:48:13.670288 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 06:48:13.673672 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 06:48:13.677397 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 06:48:13.684572 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 06:48:13.689213 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 06:48:13.692400 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 06:48:13.695796 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 06:48:13.704237 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 06:48:13.707204 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 06:48:13.710593 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 06:48:13.715273 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 06:48:13.718018 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 06:48:13.726116 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 06:48:13.729505 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 06:48:13.733104 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 06:48:13.736830 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 06:48:13.740616 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 06:48:13.743706 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 06:48:13.752007 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 06:48:13.763141 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 06:48:13.766763 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 06:48:13.774263 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 06:48:13.781232 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 06:48:13.789089 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 06:48:13.792307 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 06:48:13.795838 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 06:48:13.803265 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xc
467 06:48:13.806775 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 06:48:13.814914 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 06:48:13.818377 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 06:48:13.828085 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 06:48:13.837262 [RTC]rtc_get_frequency_meter,154: input=23, output=980
472 06:48:13.846274 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 06:48:13.855999 [RTC]rtc_get_frequency_meter,154: input=17, output=838
474 06:48:13.866200 [RTC]rtc_get_frequency_meter,154: input=16, output=815
475 06:48:13.874467 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 06:48:13.885285 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 06:48:13.888684 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 06:48:13.892873 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 06:48:13.896669 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 06:48:13.904311 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 06:48:13.907455 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 06:48:13.911321 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 06:48:13.915121 ADC[4]: Raw value=901328 ID=7
484 06:48:13.915319 ADC[3]: Raw value=213336 ID=1
485 06:48:13.918390 RAM Code: 0x71
486 06:48:13.922376 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 06:48:13.925779 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 06:48:13.937468 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 06:48:13.940874 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 06:48:13.944715 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 06:48:13.947878 in-header: 03 07 00 00 08 00 00 00
492 06:48:13.952782 in-data: aa e4 47 04 13 02 00 00
493 06:48:13.955867 Chrome EC: UHEPI supported
494 06:48:13.962933 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 06:48:13.966897 in-header: 03 ed 00 00 08 00 00 00
496 06:48:13.970351 in-data: 80 20 60 08 00 00 00 00
497 06:48:13.973889 MRC: failed to locate region type 0.
498 06:48:13.977593 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 06:48:13.981862 DRAM-K: Running full calibration
500 06:48:13.989452 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 06:48:13.989608 header.status = 0x0
502 06:48:13.993446 header.version = 0x6 (expected: 0x6)
503 06:48:13.996700 header.size = 0xd00 (expected: 0xd00)
504 06:48:13.996823 header.flags = 0x0
505 06:48:14.003549 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 06:48:14.022763 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 06:48:14.030180 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 06:48:14.034157 dram_init: ddr_geometry: 2
509 06:48:14.034368 [EMI] MDL number = 2
510 06:48:14.037648 [EMI] Get MDL freq = 0
511 06:48:14.037795 dram_init: ddr_type: 0
512 06:48:14.041718 is_discrete_lpddr4: 1
513 06:48:14.041848 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 06:48:14.045449
515 06:48:14.045570
516 06:48:14.045665 [Bian_co] ETT version 0.0.0.1
517 06:48:14.052225 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 06:48:14.052371
519 06:48:14.055771 dramc_set_vcore_voltage set vcore to 650000
520 06:48:14.055889 Read voltage for 800, 4
521 06:48:14.059917 Vio18 = 0
522 06:48:14.060049 Vcore = 650000
523 06:48:14.060144 Vdram = 0
524 06:48:14.060249 Vddq = 0
525 06:48:14.064343 Vmddr = 0
526 06:48:14.064473 dram_init: config_dvfs: 1
527 06:48:14.071160 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 06:48:14.074615 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 06:48:14.077336 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 06:48:14.080854 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 06:48:14.088131 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 06:48:14.091307 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 06:48:14.091429 MEM_TYPE=3, freq_sel=18
534 06:48:14.094335 sv_algorithm_assistance_LP4_1600
535 06:48:14.101370 ============ PULL DRAM RESETB DOWN ============
536 06:48:14.104280 ========== PULL DRAM RESETB DOWN end =========
537 06:48:14.107815 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 06:48:14.111530 ===================================
539 06:48:14.115129 LPDDR4 DRAM CONFIGURATION
540 06:48:14.117919 ===================================
541 06:48:14.118035 EX_ROW_EN[0] = 0x0
542 06:48:14.121359 EX_ROW_EN[1] = 0x0
543 06:48:14.125156 LP4Y_EN = 0x0
544 06:48:14.125284 WORK_FSP = 0x0
545 06:48:14.128091 WL = 0x2
546 06:48:14.128193 RL = 0x2
547 06:48:14.131489 BL = 0x2
548 06:48:14.131599 RPST = 0x0
549 06:48:14.134551 RD_PRE = 0x0
550 06:48:14.134655 WR_PRE = 0x1
551 06:48:14.138452 WR_PST = 0x0
552 06:48:14.138559 DBI_WR = 0x0
553 06:48:14.141148 DBI_RD = 0x0
554 06:48:14.141251 OTF = 0x1
555 06:48:14.144671 ===================================
556 06:48:14.148130 ===================================
557 06:48:14.151256 ANA top config
558 06:48:14.155314 ===================================
559 06:48:14.155444 DLL_ASYNC_EN = 0
560 06:48:14.158185 ALL_SLAVE_EN = 1
561 06:48:14.161654 NEW_RANK_MODE = 1
562 06:48:14.164804 DLL_IDLE_MODE = 1
563 06:48:14.164924 LP45_APHY_COMB_EN = 1
564 06:48:14.168338 TX_ODT_DIS = 1
565 06:48:14.171620 NEW_8X_MODE = 1
566 06:48:14.175383 ===================================
567 06:48:14.178585 ===================================
568 06:48:14.181976 data_rate = 1600
569 06:48:14.182091 CKR = 1
570 06:48:14.185115 DQ_P2S_RATIO = 8
571 06:48:14.188484 ===================================
572 06:48:14.192044 CA_P2S_RATIO = 8
573 06:48:14.195180 DQ_CA_OPEN = 0
574 06:48:14.198422 DQ_SEMI_OPEN = 0
575 06:48:14.202227 CA_SEMI_OPEN = 0
576 06:48:14.202354 CA_FULL_RATE = 0
577 06:48:14.205590 DQ_CKDIV4_EN = 1
578 06:48:14.208708 CA_CKDIV4_EN = 1
579 06:48:14.212369 CA_PREDIV_EN = 0
580 06:48:14.215358 PH8_DLY = 0
581 06:48:14.215494 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 06:48:14.219061 DQ_AAMCK_DIV = 4
583 06:48:14.222012 CA_AAMCK_DIV = 4
584 06:48:14.225235 CA_ADMCK_DIV = 4
585 06:48:14.228772 DQ_TRACK_CA_EN = 0
586 06:48:14.232098 CA_PICK = 800
587 06:48:14.235626 CA_MCKIO = 800
588 06:48:14.235750 MCKIO_SEMI = 0
589 06:48:14.239209 PLL_FREQ = 3068
590 06:48:14.242933 DQ_UI_PI_RATIO = 32
591 06:48:14.246787 CA_UI_PI_RATIO = 0
592 06:48:14.250349 ===================================
593 06:48:14.250500 ===================================
594 06:48:14.254417 memory_type:LPDDR4
595 06:48:14.257763 GP_NUM : 10
596 06:48:14.257947 SRAM_EN : 1
597 06:48:14.261436 MD32_EN : 0
598 06:48:14.265634 ===================================
599 06:48:14.265762 [ANA_INIT] >>>>>>>>>>>>>>
600 06:48:14.269286 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 06:48:14.272913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 06:48:14.276205 ===================================
603 06:48:14.280041 data_rate = 1600,PCW = 0X7600
604 06:48:14.282959 ===================================
605 06:48:14.286088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 06:48:14.289629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 06:48:14.296197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 06:48:14.300384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 06:48:14.303243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 06:48:14.306677 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 06:48:14.309623 [ANA_INIT] flow start
612 06:48:14.313146 [ANA_INIT] PLL >>>>>>>>
613 06:48:14.313261 [ANA_INIT] PLL <<<<<<<<
614 06:48:14.316633 [ANA_INIT] MIDPI >>>>>>>>
615 06:48:14.319834 [ANA_INIT] MIDPI <<<<<<<<
616 06:48:14.319935 [ANA_INIT] DLL >>>>>>>>
617 06:48:14.323216 [ANA_INIT] flow end
618 06:48:14.326475 ============ LP4 DIFF to SE enter ============
619 06:48:14.329715 ============ LP4 DIFF to SE exit ============
620 06:48:14.333431 [ANA_INIT] <<<<<<<<<<<<<
621 06:48:14.336696 [Flow] Enable top DCM control >>>>>
622 06:48:14.340134 [Flow] Enable top DCM control <<<<<
623 06:48:14.343236 Enable DLL master slave shuffle
624 06:48:14.350531 ==============================================================
625 06:48:14.350691 Gating Mode config
626 06:48:14.356663 ==============================================================
627 06:48:14.356832 Config description:
628 06:48:14.366803 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 06:48:14.373933 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 06:48:14.381032 SELPH_MODE 0: By rank 1: By Phase
631 06:48:14.384322 ==============================================================
632 06:48:14.387022 GAT_TRACK_EN = 1
633 06:48:14.390532 RX_GATING_MODE = 2
634 06:48:14.393673 RX_GATING_TRACK_MODE = 2
635 06:48:14.397090 SELPH_MODE = 1
636 06:48:14.400289 PICG_EARLY_EN = 1
637 06:48:14.403855 VALID_LAT_VALUE = 1
638 06:48:14.407060 ==============================================================
639 06:48:14.410419 Enter into Gating configuration >>>>
640 06:48:14.413772 Exit from Gating configuration <<<<
641 06:48:14.417148 Enter into DVFS_PRE_config >>>>>
642 06:48:14.431250 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 06:48:14.431411 Exit from DVFS_PRE_config <<<<<
644 06:48:14.433616 Enter into PICG configuration >>>>
645 06:48:14.437198 Exit from PICG configuration <<<<
646 06:48:14.440644 [RX_INPUT] configuration >>>>>
647 06:48:14.444292 [RX_INPUT] configuration <<<<<
648 06:48:14.450709 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 06:48:14.453786 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 06:48:14.460776 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 06:48:14.467506 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 06:48:14.474355 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 06:48:14.477719 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 06:48:14.484543 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 06:48:14.487740 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 06:48:14.491082 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 06:48:14.495136 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 06:48:14.501639 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 06:48:14.504752 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 06:48:14.508235 ===================================
661 06:48:14.511361 LPDDR4 DRAM CONFIGURATION
662 06:48:14.514887 ===================================
663 06:48:14.515007 EX_ROW_EN[0] = 0x0
664 06:48:14.518090 EX_ROW_EN[1] = 0x0
665 06:48:14.518216 LP4Y_EN = 0x0
666 06:48:14.521540 WORK_FSP = 0x0
667 06:48:14.521657 WL = 0x2
668 06:48:14.524650 RL = 0x2
669 06:48:14.524758 BL = 0x2
670 06:48:14.527915 RPST = 0x0
671 06:48:14.528015 RD_PRE = 0x0
672 06:48:14.531196 WR_PRE = 0x1
673 06:48:14.531303 WR_PST = 0x0
674 06:48:14.534716 DBI_WR = 0x0
675 06:48:14.534816 DBI_RD = 0x0
676 06:48:14.537977 OTF = 0x1
677 06:48:14.542049 ===================================
678 06:48:14.545453 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 06:48:14.548582 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 06:48:14.554775 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 06:48:14.558123 ===================================
682 06:48:14.558234 LPDDR4 DRAM CONFIGURATION
683 06:48:14.562056 ===================================
684 06:48:14.565543 EX_ROW_EN[0] = 0x10
685 06:48:14.565662 EX_ROW_EN[1] = 0x0
686 06:48:14.568422 LP4Y_EN = 0x0
687 06:48:14.568548 WORK_FSP = 0x0
688 06:48:14.572404 WL = 0x2
689 06:48:14.575414 RL = 0x2
690 06:48:14.575525 BL = 0x2
691 06:48:14.578610 RPST = 0x0
692 06:48:14.578712 RD_PRE = 0x0
693 06:48:14.581812 WR_PRE = 0x1
694 06:48:14.581910 WR_PST = 0x0
695 06:48:14.585234 DBI_WR = 0x0
696 06:48:14.585337 DBI_RD = 0x0
697 06:48:14.588642 OTF = 0x1
698 06:48:14.591912 ===================================
699 06:48:14.595297 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 06:48:14.600673 nWR fixed to 40
701 06:48:14.604177 [ModeRegInit_LP4] CH0 RK0
702 06:48:14.604328 [ModeRegInit_LP4] CH0 RK1
703 06:48:14.607589 [ModeRegInit_LP4] CH1 RK0
704 06:48:14.610864 [ModeRegInit_LP4] CH1 RK1
705 06:48:14.611019 match AC timing 13
706 06:48:14.617282 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 06:48:14.620594 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 06:48:14.624163 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 06:48:14.631180 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 06:48:14.634593 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 06:48:14.634712 [EMI DOE] emi_dcm 0
712 06:48:14.640657 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 06:48:14.640857 ==
714 06:48:14.644160 Dram Type= 6, Freq= 0, CH_0, rank 0
715 06:48:14.647759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 06:48:14.647903 ==
717 06:48:14.654484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 06:48:14.657864 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 06:48:14.668369 [CA 0] Center 37 (7~68) winsize 62
720 06:48:14.671385 [CA 1] Center 37 (6~68) winsize 63
721 06:48:14.674790 [CA 2] Center 35 (5~66) winsize 62
722 06:48:14.678382 [CA 3] Center 34 (4~65) winsize 62
723 06:48:14.681749 [CA 4] Center 34 (4~65) winsize 62
724 06:48:14.684761 [CA 5] Center 34 (4~64) winsize 61
725 06:48:14.684864
726 06:48:14.688107 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 06:48:14.688203
728 06:48:14.691314 [CATrainingPosCal] consider 1 rank data
729 06:48:14.695263 u2DelayCellTimex100 = 270/100 ps
730 06:48:14.698606 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 06:48:14.701599 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
732 06:48:14.705073 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
733 06:48:14.711819 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
734 06:48:14.714865 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
735 06:48:14.718078 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
736 06:48:14.718202
737 06:48:14.721777 CA PerBit enable=1, Macro0, CA PI delay=34
738 06:48:14.721905
739 06:48:14.725066 [CBTSetCACLKResult] CA Dly = 34
740 06:48:14.725183 CS Dly: 5 (0~36)
741 06:48:14.725275 ==
742 06:48:14.728711 Dram Type= 6, Freq= 0, CH_0, rank 1
743 06:48:14.735337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 06:48:14.735484 ==
745 06:48:14.738683 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 06:48:14.745281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 06:48:14.754562 [CA 0] Center 37 (6~68) winsize 63
748 06:48:14.757735 [CA 1] Center 37 (7~68) winsize 62
749 06:48:14.760726 [CA 2] Center 35 (5~66) winsize 62
750 06:48:14.764466 [CA 3] Center 35 (4~66) winsize 63
751 06:48:14.768185 [CA 4] Center 34 (3~65) winsize 63
752 06:48:14.771736 [CA 5] Center 33 (3~64) winsize 62
753 06:48:14.771873
754 06:48:14.774181 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 06:48:14.774296
756 06:48:14.777411 [CATrainingPosCal] consider 2 rank data
757 06:48:14.780885 u2DelayCellTimex100 = 270/100 ps
758 06:48:14.784373 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 06:48:14.787553 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
760 06:48:14.790867 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
761 06:48:14.797829 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
762 06:48:14.801341 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
763 06:48:14.804534 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 06:48:14.804680
765 06:48:14.807774 CA PerBit enable=1, Macro0, CA PI delay=34
766 06:48:14.807888
767 06:48:14.810954 [CBTSetCACLKResult] CA Dly = 34
768 06:48:14.811071 CS Dly: 6 (0~38)
769 06:48:14.811165
770 06:48:14.814176 ----->DramcWriteLeveling(PI) begin...
771 06:48:14.814313 ==
772 06:48:14.817667 Dram Type= 6, Freq= 0, CH_0, rank 0
773 06:48:14.824825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 06:48:14.824994 ==
775 06:48:14.825095 Write leveling (Byte 0): 29 => 29
776 06:48:14.828513 Write leveling (Byte 1): 29 => 29
777 06:48:14.832417 DramcWriteLeveling(PI) end<-----
778 06:48:14.832564
779 06:48:14.832663 ==
780 06:48:14.835860 Dram Type= 6, Freq= 0, CH_0, rank 0
781 06:48:14.839473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 06:48:14.842683 ==
783 06:48:14.842822 [Gating] SW mode calibration
784 06:48:14.849835 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 06:48:14.856597 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 06:48:14.859786 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 06:48:14.862973 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 06:48:14.869871 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 06:48:14.873797 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 06:48:14.877103 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 06:48:14.883189 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 06:48:14.886660 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 06:48:14.889920 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 06:48:14.896815 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 06:48:14.900533 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 06:48:14.903534 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 06:48:14.906764 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 06:48:14.913648 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 06:48:14.916859 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 06:48:14.920559 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 06:48:14.927193 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 06:48:14.930512 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 06:48:14.933678 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 06:48:14.940871 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 06:48:14.943936 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 06:48:14.947405 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 06:48:14.953917 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 06:48:14.957454 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 06:48:14.961169 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 06:48:14.963948 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 06:48:14.970617 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 06:48:14.974032 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 06:48:14.977520 0 9 12 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
814 06:48:14.983900 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 06:48:14.987484 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 06:48:14.990539 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 06:48:14.997259 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 06:48:15.001128 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 06:48:15.003921 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
820 06:48:15.010689 0 10 8 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
821 06:48:15.014163 0 10 12 | B1->B0 | 2d2d 2525 | 0 0 | (0 0) (0 0)
822 06:48:15.017388 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 06:48:15.024218 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 06:48:15.027376 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 06:48:15.031211 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 06:48:15.034382 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 06:48:15.041559 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 06:48:15.045196 0 11 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
829 06:48:15.048246 0 11 12 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
830 06:48:15.054469 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
831 06:48:15.057658 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 06:48:15.061214 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 06:48:15.067659 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 06:48:15.071377 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 06:48:15.074620 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 06:48:15.081570 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 06:48:15.085320 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
838 06:48:15.088662 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 06:48:15.091498 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 06:48:15.097974 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 06:48:15.101592 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 06:48:15.105057 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 06:48:15.111525 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 06:48:15.115208 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 06:48:15.118415 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 06:48:15.124850 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 06:48:15.128540 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 06:48:15.132198 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 06:48:15.138059 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 06:48:15.141579 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 06:48:15.145045 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 06:48:15.148870 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 06:48:15.155309 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
854 06:48:15.158737 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 06:48:15.162109 Total UI for P1: 0, mck2ui 16
856 06:48:15.165634 best dqsien dly found for B0: ( 0, 14, 10)
857 06:48:15.168954 Total UI for P1: 0, mck2ui 16
858 06:48:15.171895 best dqsien dly found for B1: ( 0, 14, 10)
859 06:48:15.175336 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
860 06:48:15.178934 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 06:48:15.179064
862 06:48:15.182290 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 06:48:15.185584 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 06:48:15.189114 [Gating] SW calibration Done
865 06:48:15.189233 ==
866 06:48:15.192110 Dram Type= 6, Freq= 0, CH_0, rank 0
867 06:48:15.195620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 06:48:15.199112 ==
869 06:48:15.199257 RX Vref Scan: 0
870 06:48:15.199365
871 06:48:15.202221 RX Vref 0 -> 0, step: 1
872 06:48:15.202346
873 06:48:15.205454 RX Delay -130 -> 252, step: 16
874 06:48:15.209141 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 06:48:15.212342 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 06:48:15.215417 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 06:48:15.219137 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 06:48:15.222694 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 06:48:15.228855 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 06:48:15.232670 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
881 06:48:15.235943 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
882 06:48:15.239268 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 06:48:15.242613 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 06:48:15.249572 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 06:48:15.252616 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 06:48:15.256454 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 06:48:15.259337 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
888 06:48:15.262808 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 06:48:15.269641 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 06:48:15.269826 ==
891 06:48:15.273243 Dram Type= 6, Freq= 0, CH_0, rank 0
892 06:48:15.276456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 06:48:15.276614 ==
894 06:48:15.276728 DQS Delay:
895 06:48:15.279638 DQS0 = 0, DQS1 = 0
896 06:48:15.279777 DQM Delay:
897 06:48:15.282695 DQM0 = 85, DQM1 = 77
898 06:48:15.282832 DQ Delay:
899 06:48:15.286111 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 06:48:15.289700 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
901 06:48:15.293101 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
902 06:48:15.296633 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
903 06:48:15.296806
904 06:48:15.296921
905 06:48:15.297020 ==
906 06:48:15.299581 Dram Type= 6, Freq= 0, CH_0, rank 0
907 06:48:15.302948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 06:48:15.303062 ==
909 06:48:15.303131
910 06:48:15.303192
911 06:48:15.306298 TX Vref Scan disable
912 06:48:15.310017 == TX Byte 0 ==
913 06:48:15.312985 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
914 06:48:15.316760 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
915 06:48:15.319582 == TX Byte 1 ==
916 06:48:15.323215 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
917 06:48:15.326590 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
918 06:48:15.326714 ==
919 06:48:15.329741 Dram Type= 6, Freq= 0, CH_0, rank 0
920 06:48:15.333468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 06:48:15.333588 ==
922 06:48:15.347453 TX Vref=22, minBit 0, minWin=27, winSum=437
923 06:48:15.351314 TX Vref=24, minBit 0, minWin=27, winSum=441
924 06:48:15.354307 TX Vref=26, minBit 12, minWin=27, winSum=448
925 06:48:15.357841 TX Vref=28, minBit 12, minWin=27, winSum=452
926 06:48:15.361328 TX Vref=30, minBit 12, minWin=27, winSum=452
927 06:48:15.368097 TX Vref=32, minBit 1, minWin=28, winSum=452
928 06:48:15.371798 [TxChooseVref] Worse bit 1, Min win 28, Win sum 452, Final Vref 32
929 06:48:15.371952
930 06:48:15.375059 Final TX Range 1 Vref 32
931 06:48:15.375186
932 06:48:15.375279 ==
933 06:48:15.378026 Dram Type= 6, Freq= 0, CH_0, rank 0
934 06:48:15.381578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 06:48:15.381684 ==
936 06:48:15.381757
937 06:48:15.384495
938 06:48:15.384606 TX Vref Scan disable
939 06:48:15.387676 == TX Byte 0 ==
940 06:48:15.391290 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
941 06:48:15.394845 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
942 06:48:15.397649 == TX Byte 1 ==
943 06:48:15.401317 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
944 06:48:15.405067 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
945 06:48:15.405193
946 06:48:15.407815 [DATLAT]
947 06:48:15.407915 Freq=800, CH0 RK0
948 06:48:15.407985
949 06:48:15.411412 DATLAT Default: 0xa
950 06:48:15.411505 0, 0xFFFF, sum = 0
951 06:48:15.414353 1, 0xFFFF, sum = 0
952 06:48:15.414471 2, 0xFFFF, sum = 0
953 06:48:15.418261 3, 0xFFFF, sum = 0
954 06:48:15.418409 4, 0xFFFF, sum = 0
955 06:48:15.421267 5, 0xFFFF, sum = 0
956 06:48:15.421384 6, 0xFFFF, sum = 0
957 06:48:15.424828 7, 0xFFFF, sum = 0
958 06:48:15.424924 8, 0xFFFF, sum = 0
959 06:48:15.428338 9, 0x0, sum = 1
960 06:48:15.428452 10, 0x0, sum = 2
961 06:48:15.431687 11, 0x0, sum = 3
962 06:48:15.431817 12, 0x0, sum = 4
963 06:48:15.434825 best_step = 10
964 06:48:15.434940
965 06:48:15.435040 ==
966 06:48:15.438334 Dram Type= 6, Freq= 0, CH_0, rank 0
967 06:48:15.441912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 06:48:15.442044 ==
969 06:48:15.444756 RX Vref Scan: 1
970 06:48:15.444889
971 06:48:15.444991 Set Vref Range= 32 -> 127
972 06:48:15.445093
973 06:48:15.448316 RX Vref 32 -> 127, step: 1
974 06:48:15.448417
975 06:48:15.451557 RX Delay -95 -> 252, step: 8
976 06:48:15.451684
977 06:48:15.454683 Set Vref, RX VrefLevel [Byte0]: 32
978 06:48:15.458226 [Byte1]: 32
979 06:48:15.458376
980 06:48:15.462573 Set Vref, RX VrefLevel [Byte0]: 33
981 06:48:15.465319 [Byte1]: 33
982 06:48:15.465488
983 06:48:15.468626 Set Vref, RX VrefLevel [Byte0]: 34
984 06:48:15.471804 [Byte1]: 34
985 06:48:15.476031
986 06:48:15.476154 Set Vref, RX VrefLevel [Byte0]: 35
987 06:48:15.478980 [Byte1]: 35
988 06:48:15.483064
989 06:48:15.483179 Set Vref, RX VrefLevel [Byte0]: 36
990 06:48:15.486585 [Byte1]: 36
991 06:48:15.490512
992 06:48:15.494321 Set Vref, RX VrefLevel [Byte0]: 37
993 06:48:15.494465 [Byte1]: 37
994 06:48:15.498994
995 06:48:15.499125 Set Vref, RX VrefLevel [Byte0]: 38
996 06:48:15.502119 [Byte1]: 38
997 06:48:15.506330
998 06:48:15.506489 Set Vref, RX VrefLevel [Byte0]: 39
999 06:48:15.510015 [Byte1]: 39
1000 06:48:15.514161
1001 06:48:15.514363 Set Vref, RX VrefLevel [Byte0]: 40
1002 06:48:15.517407 [Byte1]: 40
1003 06:48:15.521419
1004 06:48:15.521547 Set Vref, RX VrefLevel [Byte0]: 41
1005 06:48:15.524901 [Byte1]: 41
1006 06:48:15.528679
1007 06:48:15.528832 Set Vref, RX VrefLevel [Byte0]: 42
1008 06:48:15.532031 [Byte1]: 42
1009 06:48:15.536651
1010 06:48:15.536801 Set Vref, RX VrefLevel [Byte0]: 43
1011 06:48:15.540267 [Byte1]: 43
1012 06:48:15.544304
1013 06:48:15.544471 Set Vref, RX VrefLevel [Byte0]: 44
1014 06:48:15.547671 [Byte1]: 44
1015 06:48:15.551669
1016 06:48:15.551794 Set Vref, RX VrefLevel [Byte0]: 45
1017 06:48:15.555284 [Byte1]: 45
1018 06:48:15.559549
1019 06:48:15.559700 Set Vref, RX VrefLevel [Byte0]: 46
1020 06:48:15.562328 [Byte1]: 46
1021 06:48:15.566733
1022 06:48:15.566848 Set Vref, RX VrefLevel [Byte0]: 47
1023 06:48:15.569920 [Byte1]: 47
1024 06:48:15.574363
1025 06:48:15.574497 Set Vref, RX VrefLevel [Byte0]: 48
1026 06:48:15.577755 [Byte1]: 48
1027 06:48:15.582348
1028 06:48:15.582509 Set Vref, RX VrefLevel [Byte0]: 49
1029 06:48:15.585420 [Byte1]: 49
1030 06:48:15.589569
1031 06:48:15.589682 Set Vref, RX VrefLevel [Byte0]: 50
1032 06:48:15.592931 [Byte1]: 50
1033 06:48:15.597139
1034 06:48:15.597279 Set Vref, RX VrefLevel [Byte0]: 51
1035 06:48:15.600620 [Byte1]: 51
1036 06:48:15.605317
1037 06:48:15.605447 Set Vref, RX VrefLevel [Byte0]: 52
1038 06:48:15.608085 [Byte1]: 52
1039 06:48:15.613116
1040 06:48:15.613244 Set Vref, RX VrefLevel [Byte0]: 53
1041 06:48:15.616065 [Byte1]: 53
1042 06:48:15.620126
1043 06:48:15.620244 Set Vref, RX VrefLevel [Byte0]: 54
1044 06:48:15.623425 [Byte1]: 54
1045 06:48:15.628440
1046 06:48:15.628568 Set Vref, RX VrefLevel [Byte0]: 55
1047 06:48:15.631725 [Byte1]: 55
1048 06:48:15.635309
1049 06:48:15.635429 Set Vref, RX VrefLevel [Byte0]: 56
1050 06:48:15.638264 [Byte1]: 56
1051 06:48:15.643115
1052 06:48:15.643237 Set Vref, RX VrefLevel [Byte0]: 57
1053 06:48:15.646350 [Byte1]: 57
1054 06:48:15.650409
1055 06:48:15.650558 Set Vref, RX VrefLevel [Byte0]: 58
1056 06:48:15.653871 [Byte1]: 58
1057 06:48:15.657867
1058 06:48:15.658003 Set Vref, RX VrefLevel [Byte0]: 59
1059 06:48:15.661612 [Byte1]: 59
1060 06:48:15.665721
1061 06:48:15.665846 Set Vref, RX VrefLevel [Byte0]: 60
1062 06:48:15.668970 [Byte1]: 60
1063 06:48:15.673194
1064 06:48:15.673301 Set Vref, RX VrefLevel [Byte0]: 61
1065 06:48:15.676430 [Byte1]: 61
1066 06:48:15.681230
1067 06:48:15.681374 Set Vref, RX VrefLevel [Byte0]: 62
1068 06:48:15.683929 [Byte1]: 62
1069 06:48:15.688386
1070 06:48:15.688494 Set Vref, RX VrefLevel [Byte0]: 63
1071 06:48:15.692082 [Byte1]: 63
1072 06:48:15.695762
1073 06:48:15.695907 Set Vref, RX VrefLevel [Byte0]: 64
1074 06:48:15.699700 [Byte1]: 64
1075 06:48:15.703787
1076 06:48:15.703908 Set Vref, RX VrefLevel [Byte0]: 65
1077 06:48:15.706751 [Byte1]: 65
1078 06:48:15.711512
1079 06:48:15.711642 Set Vref, RX VrefLevel [Byte0]: 66
1080 06:48:15.714572 [Byte1]: 66
1081 06:48:15.718782
1082 06:48:15.718906 Set Vref, RX VrefLevel [Byte0]: 67
1083 06:48:15.722187 [Byte1]: 67
1084 06:48:15.726061
1085 06:48:15.726179 Set Vref, RX VrefLevel [Byte0]: 68
1086 06:48:15.729485 [Byte1]: 68
1087 06:48:15.733824
1088 06:48:15.733945 Set Vref, RX VrefLevel [Byte0]: 69
1089 06:48:15.737363 [Byte1]: 69
1090 06:48:15.741560
1091 06:48:15.741752 Set Vref, RX VrefLevel [Byte0]: 70
1092 06:48:15.744774 [Byte1]: 70
1093 06:48:15.749060
1094 06:48:15.749178 Set Vref, RX VrefLevel [Byte0]: 71
1095 06:48:15.752607 [Byte1]: 71
1096 06:48:15.756845
1097 06:48:15.756963 Set Vref, RX VrefLevel [Byte0]: 72
1098 06:48:15.759807 [Byte1]: 72
1099 06:48:15.764450
1100 06:48:15.764579 Set Vref, RX VrefLevel [Byte0]: 73
1101 06:48:15.767892 [Byte1]: 73
1102 06:48:15.771724
1103 06:48:15.771843 Set Vref, RX VrefLevel [Byte0]: 74
1104 06:48:15.775011 [Byte1]: 74
1105 06:48:15.779261
1106 06:48:15.779384 Set Vref, RX VrefLevel [Byte0]: 75
1107 06:48:15.783123 [Byte1]: 75
1108 06:48:15.787014
1109 06:48:15.787128 Final RX Vref Byte 0 = 62 to rank0
1110 06:48:15.790383 Final RX Vref Byte 1 = 58 to rank0
1111 06:48:15.793946 Final RX Vref Byte 0 = 62 to rank1
1112 06:48:15.797066 Final RX Vref Byte 1 = 58 to rank1==
1113 06:48:15.800823 Dram Type= 6, Freq= 0, CH_0, rank 0
1114 06:48:15.804311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1115 06:48:15.807426 ==
1116 06:48:15.807545 DQS Delay:
1117 06:48:15.807614 DQS0 = 0, DQS1 = 0
1118 06:48:15.810581 DQM Delay:
1119 06:48:15.810679 DQM0 = 87, DQM1 = 79
1120 06:48:15.813811 DQ Delay:
1121 06:48:15.813900 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1122 06:48:15.817297 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1123 06:48:15.820866 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1124 06:48:15.823798 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1125 06:48:15.823907
1126 06:48:15.827440
1127 06:48:15.834215 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1128 06:48:15.837349 CH0 RK0: MR19=606, MR18=260D
1129 06:48:15.844145 CH0_RK0: MR19=0x606, MR18=0x260D, DQSOSC=400, MR23=63, INC=92, DEC=61
1130 06:48:15.844284
1131 06:48:15.847393 ----->DramcWriteLeveling(PI) begin...
1132 06:48:15.847584 ==
1133 06:48:15.850938 Dram Type= 6, Freq= 0, CH_0, rank 1
1134 06:48:15.853913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1135 06:48:15.854012 ==
1136 06:48:15.857565 Write leveling (Byte 0): 29 => 29
1137 06:48:15.860944 Write leveling (Byte 1): 29 => 29
1138 06:48:15.863992 DramcWriteLeveling(PI) end<-----
1139 06:48:15.864147
1140 06:48:15.864283 ==
1141 06:48:15.867950 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 06:48:15.871300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 06:48:15.871406 ==
1144 06:48:15.874121 [Gating] SW mode calibration
1145 06:48:15.880894 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1146 06:48:15.891001 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1147 06:48:15.891444 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1148 06:48:15.894141 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1149 06:48:15.897481 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1150 06:48:15.945119 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 06:48:15.945351 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 06:48:15.945634 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 06:48:15.945717 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 06:48:15.945969 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 06:48:15.946764 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 06:48:15.946836 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 06:48:15.947286 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 06:48:15.948030 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 06:48:15.948306 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 06:48:15.989128 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 06:48:15.989291 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 06:48:15.989561 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 06:48:15.989632 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 06:48:15.989725 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1165 06:48:15.989816 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1166 06:48:15.989878 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 06:48:15.990239 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 06:48:15.990685 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 06:48:15.991346 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 06:48:16.026548 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 06:48:16.026720 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 06:48:16.027022 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 06:48:16.027122 0 9 8 | B1->B0 | 2323 3131 | 1 1 | (0 0) (1 1)
1174 06:48:16.027502 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
1175 06:48:16.027894 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 06:48:16.027969 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 06:48:16.028265 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 06:48:16.028363 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 06:48:16.031806 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 06:48:16.034986 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (1 1)
1181 06:48:16.038098 0 10 8 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 0)
1182 06:48:16.045194 0 10 12 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
1183 06:48:16.048235 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 06:48:16.051509 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 06:48:16.058684 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 06:48:16.061747 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 06:48:16.065271 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 06:48:16.072265 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1189 06:48:16.076246 0 11 8 | B1->B0 | 2d2d 3a3a | 0 0 | (0 0) (0 0)
1190 06:48:16.080223 0 11 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
1191 06:48:16.083691 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 06:48:16.087341 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 06:48:16.093870 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 06:48:16.097304 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 06:48:16.100967 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 06:48:16.104090 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 06:48:16.111131 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1198 06:48:16.115000 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 06:48:16.117620 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 06:48:16.124588 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 06:48:16.127620 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 06:48:16.131024 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 06:48:16.138046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 06:48:16.141712 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 06:48:16.144897 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 06:48:16.148397 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 06:48:16.154642 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 06:48:16.158166 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 06:48:16.161431 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 06:48:16.167937 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 06:48:16.171589 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 06:48:16.175131 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1213 06:48:16.181626 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1214 06:48:16.181763 Total UI for P1: 0, mck2ui 16
1215 06:48:16.188254 best dqsien dly found for B0: ( 0, 14, 4)
1216 06:48:16.191336 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 06:48:16.195072 Total UI for P1: 0, mck2ui 16
1218 06:48:16.198253 best dqsien dly found for B1: ( 0, 14, 6)
1219 06:48:16.201401 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1220 06:48:16.204832 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1221 06:48:16.204943
1222 06:48:16.208279 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1223 06:48:16.211972 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1224 06:48:16.214958 [Gating] SW calibration Done
1225 06:48:16.215078 ==
1226 06:48:16.218552 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 06:48:16.221855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1228 06:48:16.221962 ==
1229 06:48:16.225120 RX Vref Scan: 0
1230 06:48:16.225216
1231 06:48:16.228480 RX Vref 0 -> 0, step: 1
1232 06:48:16.228581
1233 06:48:16.228666 RX Delay -130 -> 252, step: 16
1234 06:48:16.234952 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1235 06:48:16.238335 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1236 06:48:16.241908 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1237 06:48:16.245447 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1238 06:48:16.248470 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1239 06:48:16.255134 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1240 06:48:16.258457 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1241 06:48:16.262260 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1242 06:48:16.265366 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1243 06:48:16.268972 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1244 06:48:16.272157 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1245 06:48:16.278413 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1246 06:48:16.282287 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1247 06:48:16.285154 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1248 06:48:16.288596 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1249 06:48:16.295792 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1250 06:48:16.295946 ==
1251 06:48:16.298754 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 06:48:16.302098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1253 06:48:16.302302 ==
1254 06:48:16.302408 DQS Delay:
1255 06:48:16.305522 DQS0 = 0, DQS1 = 0
1256 06:48:16.305642 DQM Delay:
1257 06:48:16.308885 DQM0 = 87, DQM1 = 73
1258 06:48:16.308974 DQ Delay:
1259 06:48:16.312373 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1260 06:48:16.315787 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =101
1261 06:48:16.319076 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1262 06:48:16.322523 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
1263 06:48:16.322635
1264 06:48:16.322706
1265 06:48:16.322789 ==
1266 06:48:16.325832 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 06:48:16.329168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 06:48:16.329309 ==
1269 06:48:16.329407
1270 06:48:16.329502
1271 06:48:16.333013 TX Vref Scan disable
1272 06:48:16.335660 == TX Byte 0 ==
1273 06:48:16.338761 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1274 06:48:16.342252 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1275 06:48:16.345675 == TX Byte 1 ==
1276 06:48:16.348892 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1277 06:48:16.352367 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1278 06:48:16.352539 ==
1279 06:48:16.355993 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 06:48:16.358857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 06:48:16.362385 ==
1282 06:48:16.373944 TX Vref=22, minBit 2, minWin=27, winSum=442
1283 06:48:16.377219 TX Vref=24, minBit 6, minWin=27, winSum=447
1284 06:48:16.380633 TX Vref=26, minBit 9, minWin=27, winSum=451
1285 06:48:16.383850 TX Vref=28, minBit 9, minWin=27, winSum=451
1286 06:48:16.386905 TX Vref=30, minBit 9, minWin=27, winSum=451
1287 06:48:16.390440 TX Vref=32, minBit 0, minWin=28, winSum=451
1288 06:48:16.397500 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1289 06:48:16.397664
1290 06:48:16.400915 Final TX Range 1 Vref 32
1291 06:48:16.401081
1292 06:48:16.401173 ==
1293 06:48:16.403677 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 06:48:16.407084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 06:48:16.407219 ==
1296 06:48:16.407314
1297 06:48:16.407402
1298 06:48:16.410717 TX Vref Scan disable
1299 06:48:16.414710 == TX Byte 0 ==
1300 06:48:16.417372 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1301 06:48:16.420512 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1302 06:48:16.424289 == TX Byte 1 ==
1303 06:48:16.427358 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1304 06:48:16.430652 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1305 06:48:16.430784
1306 06:48:16.433802 [DATLAT]
1307 06:48:16.433914 Freq=800, CH0 RK1
1308 06:48:16.434005
1309 06:48:16.437693 DATLAT Default: 0xa
1310 06:48:16.437816 0, 0xFFFF, sum = 0
1311 06:48:16.440496 1, 0xFFFF, sum = 0
1312 06:48:16.440593 2, 0xFFFF, sum = 0
1313 06:48:16.444200 3, 0xFFFF, sum = 0
1314 06:48:16.444314 4, 0xFFFF, sum = 0
1315 06:48:16.447332 5, 0xFFFF, sum = 0
1316 06:48:16.447439 6, 0xFFFF, sum = 0
1317 06:48:16.451332 7, 0xFFFF, sum = 0
1318 06:48:16.451467 8, 0xFFFF, sum = 0
1319 06:48:16.454271 9, 0x0, sum = 1
1320 06:48:16.454384 10, 0x0, sum = 2
1321 06:48:16.457751 11, 0x0, sum = 3
1322 06:48:16.457849 12, 0x0, sum = 4
1323 06:48:16.461020 best_step = 10
1324 06:48:16.461121
1325 06:48:16.461189 ==
1326 06:48:16.464167 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 06:48:16.467433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 06:48:16.467537 ==
1329 06:48:16.467602 RX Vref Scan: 0
1330 06:48:16.470849
1331 06:48:16.470934 RX Vref 0 -> 0, step: 1
1332 06:48:16.470994
1333 06:48:16.474360 RX Delay -95 -> 252, step: 8
1334 06:48:16.477939 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1335 06:48:16.484688 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1336 06:48:16.487669 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1337 06:48:16.490746 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1338 06:48:16.494588 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1339 06:48:16.497766 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1340 06:48:16.504578 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1341 06:48:16.507647 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1342 06:48:16.511338 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1343 06:48:16.514568 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1344 06:48:16.517628 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1345 06:48:16.521726 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1346 06:48:16.527991 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1347 06:48:16.531255 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1348 06:48:16.534938 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1349 06:48:16.537803 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1350 06:48:16.537962 ==
1351 06:48:16.541266 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 06:48:16.547993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 06:48:16.548159 ==
1354 06:48:16.548284 DQS Delay:
1355 06:48:16.551436 DQS0 = 0, DQS1 = 0
1356 06:48:16.551563 DQM Delay:
1357 06:48:16.551657 DQM0 = 88, DQM1 = 78
1358 06:48:16.555027 DQ Delay:
1359 06:48:16.558058 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1360 06:48:16.558196 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1361 06:48:16.561410 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1362 06:48:16.564921 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1363 06:48:16.569241
1364 06:48:16.569405
1365 06:48:16.575253 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1366 06:48:16.578663 CH0 RK1: MR19=606, MR18=2D17
1367 06:48:16.584830 CH0_RK1: MR19=0x606, MR18=0x2D17, DQSOSC=398, MR23=63, INC=93, DEC=62
1368 06:48:16.588419 [RxdqsGatingPostProcess] freq 800
1369 06:48:16.591472 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1370 06:48:16.595163 Pre-setting of DQS Precalculation
1371 06:48:16.602117 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1372 06:48:16.602266 ==
1373 06:48:16.604929 Dram Type= 6, Freq= 0, CH_1, rank 0
1374 06:48:16.608498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 06:48:16.608613 ==
1376 06:48:16.615639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1377 06:48:16.618500 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1378 06:48:16.628225 [CA 0] Center 36 (6~66) winsize 61
1379 06:48:16.631607 [CA 1] Center 36 (6~66) winsize 61
1380 06:48:16.634739 [CA 2] Center 34 (4~65) winsize 62
1381 06:48:16.638238 [CA 3] Center 33 (3~64) winsize 62
1382 06:48:16.642034 [CA 4] Center 34 (3~65) winsize 63
1383 06:48:16.644933 [CA 5] Center 33 (3~64) winsize 62
1384 06:48:16.645069
1385 06:48:16.648857 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1386 06:48:16.648999
1387 06:48:16.652043 [CATrainingPosCal] consider 1 rank data
1388 06:48:16.655366 u2DelayCellTimex100 = 270/100 ps
1389 06:48:16.658480 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1390 06:48:16.661892 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1391 06:48:16.665303 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1392 06:48:16.671856 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1393 06:48:16.675139 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1394 06:48:16.678796 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 06:48:16.678949
1396 06:48:16.682121 CA PerBit enable=1, Macro0, CA PI delay=33
1397 06:48:16.682243
1398 06:48:16.685399 [CBTSetCACLKResult] CA Dly = 33
1399 06:48:16.685535 CS Dly: 5 (0~36)
1400 06:48:16.685630 ==
1401 06:48:16.688791 Dram Type= 6, Freq= 0, CH_1, rank 1
1402 06:48:16.695434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 06:48:16.695577 ==
1404 06:48:16.698865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1405 06:48:16.705632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1406 06:48:16.714542 [CA 0] Center 36 (6~66) winsize 61
1407 06:48:16.717867 [CA 1] Center 36 (6~66) winsize 61
1408 06:48:16.721443 [CA 2] Center 34 (4~64) winsize 61
1409 06:48:16.724698 [CA 3] Center 33 (3~64) winsize 62
1410 06:48:16.727961 [CA 4] Center 34 (3~65) winsize 63
1411 06:48:16.730900 [CA 5] Center 33 (3~64) winsize 62
1412 06:48:16.731007
1413 06:48:16.734323 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1414 06:48:16.734455
1415 06:48:16.738154 [CATrainingPosCal] consider 2 rank data
1416 06:48:16.741610 u2DelayCellTimex100 = 270/100 ps
1417 06:48:16.745528 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1418 06:48:16.749464 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1419 06:48:16.754096 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1420 06:48:16.756391 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1421 06:48:16.760394 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1422 06:48:16.764601 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 06:48:16.764746
1424 06:48:16.767796 CA PerBit enable=1, Macro0, CA PI delay=33
1425 06:48:16.767928
1426 06:48:16.771858 [CBTSetCACLKResult] CA Dly = 33
1427 06:48:16.771971 CS Dly: 5 (0~37)
1428 06:48:16.772040
1429 06:48:16.775649 ----->DramcWriteLeveling(PI) begin...
1430 06:48:16.775789 ==
1431 06:48:16.778706 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 06:48:16.782719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 06:48:16.782865 ==
1434 06:48:16.785686 Write leveling (Byte 0): 29 => 29
1435 06:48:16.789040 Write leveling (Byte 1): 29 => 29
1436 06:48:16.792235 DramcWriteLeveling(PI) end<-----
1437 06:48:16.792361
1438 06:48:16.792456 ==
1439 06:48:16.795721 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 06:48:16.798933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 06:48:16.802127 ==
1442 06:48:16.802268 [Gating] SW mode calibration
1443 06:48:16.809510 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1444 06:48:16.816190 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1445 06:48:16.819514 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1446 06:48:16.826033 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1447 06:48:16.829183 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1448 06:48:16.832401 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 06:48:16.839252 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 06:48:16.842303 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 06:48:16.846318 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 06:48:16.849512 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 06:48:16.855568 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 06:48:16.859533 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 06:48:16.862753 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 06:48:16.869253 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 06:48:16.872465 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1458 06:48:16.875882 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 06:48:16.883127 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 06:48:16.885879 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1461 06:48:16.889897 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1462 06:48:16.896703 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (1 1)
1463 06:48:16.899613 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1464 06:48:16.903020 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 06:48:16.906233 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 06:48:16.913812 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 06:48:16.916588 0 8 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1468 06:48:16.919453 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 06:48:16.926531 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 06:48:16.930114 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 06:48:16.933195 0 9 8 | B1->B0 | 2424 2323 | 1 0 | (1 1) (0 0)
1472 06:48:16.939737 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1473 06:48:16.943332 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 06:48:16.946377 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 06:48:16.953104 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 06:48:16.956519 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 06:48:16.959797 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1478 06:48:16.966862 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1479 06:48:16.970035 0 10 8 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (1 1)
1480 06:48:16.973608 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1481 06:48:16.976602 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 06:48:16.983680 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 06:48:16.986739 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 06:48:16.990347 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 06:48:16.996619 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 06:48:17.000351 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1487 06:48:17.003568 0 11 8 | B1->B0 | 3636 3636 | 0 0 | (0 0) (0 0)
1488 06:48:17.010335 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 06:48:17.013546 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 06:48:17.017019 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 06:48:17.023533 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 06:48:17.026889 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 06:48:17.030192 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 06:48:17.033645 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 06:48:17.041039 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 06:48:17.043774 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 06:48:17.047357 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 06:48:17.054218 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 06:48:17.057250 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 06:48:17.060359 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 06:48:17.067244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 06:48:17.070845 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 06:48:17.074319 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 06:48:17.081221 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 06:48:17.084563 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 06:48:17.087820 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 06:48:17.091042 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 06:48:17.098274 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 06:48:17.101106 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 06:48:17.104700 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 06:48:17.111282 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1512 06:48:17.114310 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 06:48:17.117902 Total UI for P1: 0, mck2ui 16
1514 06:48:17.121173 best dqsien dly found for B0: ( 0, 14, 8)
1515 06:48:17.124431 Total UI for P1: 0, mck2ui 16
1516 06:48:17.127687 best dqsien dly found for B1: ( 0, 14, 8)
1517 06:48:17.131573 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1518 06:48:17.134645 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1519 06:48:17.134790
1520 06:48:17.137830 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1521 06:48:17.141923 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1522 06:48:17.144876 [Gating] SW calibration Done
1523 06:48:17.145010 ==
1524 06:48:17.147763 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 06:48:17.151657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 06:48:17.151783 ==
1527 06:48:17.154564 RX Vref Scan: 0
1528 06:48:17.154659
1529 06:48:17.154727 RX Vref 0 -> 0, step: 1
1530 06:48:17.158187
1531 06:48:17.158313 RX Delay -130 -> 252, step: 16
1532 06:48:17.165052 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1533 06:48:17.167957 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1534 06:48:17.171697 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1535 06:48:17.174910 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1536 06:48:17.178262 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1537 06:48:17.181459 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1538 06:48:17.188480 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1539 06:48:17.191890 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1540 06:48:17.195153 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1541 06:48:17.198768 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1542 06:48:17.201908 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1543 06:48:17.208552 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1544 06:48:17.211970 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1545 06:48:17.215010 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1546 06:48:17.218914 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1547 06:48:17.222292 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1548 06:48:17.225674 ==
1549 06:48:17.225787 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 06:48:17.231872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 06:48:17.232033 ==
1552 06:48:17.232108 DQS Delay:
1553 06:48:17.235161 DQS0 = 0, DQS1 = 0
1554 06:48:17.235293 DQM Delay:
1555 06:48:17.238993 DQM0 = 86, DQM1 = 77
1556 06:48:17.239138 DQ Delay:
1557 06:48:17.242160 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1558 06:48:17.245487 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =77
1559 06:48:17.248783 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1560 06:48:17.252081 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1561 06:48:17.252206
1562 06:48:17.252298
1563 06:48:17.252361 ==
1564 06:48:17.255607 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 06:48:17.259116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 06:48:17.259238 ==
1567 06:48:17.259307
1568 06:48:17.259366
1569 06:48:17.262272 TX Vref Scan disable
1570 06:48:17.262386 == TX Byte 0 ==
1571 06:48:17.268885 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1572 06:48:17.272843 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1573 06:48:17.273001 == TX Byte 1 ==
1574 06:48:17.278764 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1575 06:48:17.282739 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1576 06:48:17.282892 ==
1577 06:48:17.285680 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 06:48:17.289554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 06:48:17.289663 ==
1580 06:48:17.302892 TX Vref=22, minBit 11, minWin=26, winSum=437
1581 06:48:17.306310 TX Vref=24, minBit 1, minWin=27, winSum=442
1582 06:48:17.309372 TX Vref=26, minBit 5, minWin=27, winSum=444
1583 06:48:17.313393 TX Vref=28, minBit 1, minWin=27, winSum=448
1584 06:48:17.316433 TX Vref=30, minBit 0, minWin=28, winSum=453
1585 06:48:17.320184 TX Vref=32, minBit 9, minWin=27, winSum=449
1586 06:48:17.327012 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1587 06:48:17.327153
1588 06:48:17.330714 Final TX Range 1 Vref 30
1589 06:48:17.330815
1590 06:48:17.330893 ==
1591 06:48:17.333996 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 06:48:17.337662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 06:48:17.337777 ==
1594 06:48:17.337848
1595 06:48:17.337909
1596 06:48:17.340786 TX Vref Scan disable
1597 06:48:17.344179 == TX Byte 0 ==
1598 06:48:17.347054 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1599 06:48:17.351067 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1600 06:48:17.354327 == TX Byte 1 ==
1601 06:48:17.357838 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1602 06:48:17.360803 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1603 06:48:17.360942
1604 06:48:17.361046 [DATLAT]
1605 06:48:17.363902 Freq=800, CH1 RK0
1606 06:48:17.364022
1607 06:48:17.367596 DATLAT Default: 0xa
1608 06:48:17.367730 0, 0xFFFF, sum = 0
1609 06:48:17.370540 1, 0xFFFF, sum = 0
1610 06:48:17.370631 2, 0xFFFF, sum = 0
1611 06:48:17.373934 3, 0xFFFF, sum = 0
1612 06:48:17.374060 4, 0xFFFF, sum = 0
1613 06:48:17.377422 5, 0xFFFF, sum = 0
1614 06:48:17.377518 6, 0xFFFF, sum = 0
1615 06:48:17.380502 7, 0xFFFF, sum = 0
1616 06:48:17.380596 8, 0xFFFF, sum = 0
1617 06:48:17.384466 9, 0x0, sum = 1
1618 06:48:17.384591 10, 0x0, sum = 2
1619 06:48:17.387686 11, 0x0, sum = 3
1620 06:48:17.387793 12, 0x0, sum = 4
1621 06:48:17.387877 best_step = 10
1622 06:48:17.387967
1623 06:48:17.390943 ==
1624 06:48:17.394354 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 06:48:17.397619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 06:48:17.397747 ==
1627 06:48:17.397846 RX Vref Scan: 1
1628 06:48:17.397939
1629 06:48:17.401274 Set Vref Range= 32 -> 127
1630 06:48:17.401362
1631 06:48:17.404236 RX Vref 32 -> 127, step: 1
1632 06:48:17.404321
1633 06:48:17.407657 RX Delay -111 -> 252, step: 8
1634 06:48:17.407750
1635 06:48:17.411360 Set Vref, RX VrefLevel [Byte0]: 32
1636 06:48:17.414185 [Byte1]: 32
1637 06:48:17.414317
1638 06:48:17.417704 Set Vref, RX VrefLevel [Byte0]: 33
1639 06:48:17.421715 [Byte1]: 33
1640 06:48:17.421860
1641 06:48:17.424196 Set Vref, RX VrefLevel [Byte0]: 34
1642 06:48:17.427986 [Byte1]: 34
1643 06:48:17.431216
1644 06:48:17.431337 Set Vref, RX VrefLevel [Byte0]: 35
1645 06:48:17.434344 [Byte1]: 35
1646 06:48:17.438673
1647 06:48:17.438799 Set Vref, RX VrefLevel [Byte0]: 36
1648 06:48:17.441883 [Byte1]: 36
1649 06:48:17.446849
1650 06:48:17.447000 Set Vref, RX VrefLevel [Byte0]: 37
1651 06:48:17.449593 [Byte1]: 37
1652 06:48:17.453895
1653 06:48:17.454032 Set Vref, RX VrefLevel [Byte0]: 38
1654 06:48:17.457219 [Byte1]: 38
1655 06:48:17.461641
1656 06:48:17.461804 Set Vref, RX VrefLevel [Byte0]: 39
1657 06:48:17.464788 [Byte1]: 39
1658 06:48:17.469200
1659 06:48:17.469323 Set Vref, RX VrefLevel [Byte0]: 40
1660 06:48:17.472599 [Byte1]: 40
1661 06:48:17.477277
1662 06:48:17.477406 Set Vref, RX VrefLevel [Byte0]: 41
1663 06:48:17.480449 [Byte1]: 41
1664 06:48:17.485104
1665 06:48:17.485232 Set Vref, RX VrefLevel [Byte0]: 42
1666 06:48:17.487923 [Byte1]: 42
1667 06:48:17.491874
1668 06:48:17.492014 Set Vref, RX VrefLevel [Byte0]: 43
1669 06:48:17.495364 [Byte1]: 43
1670 06:48:17.499883
1671 06:48:17.500004 Set Vref, RX VrefLevel [Byte0]: 44
1672 06:48:17.503165 [Byte1]: 44
1673 06:48:17.507247
1674 06:48:17.507371 Set Vref, RX VrefLevel [Byte0]: 45
1675 06:48:17.510861 [Byte1]: 45
1676 06:48:17.515116
1677 06:48:17.515237 Set Vref, RX VrefLevel [Byte0]: 46
1678 06:48:17.518364 [Byte1]: 46
1679 06:48:17.522670
1680 06:48:17.522799 Set Vref, RX VrefLevel [Byte0]: 47
1681 06:48:17.526193 [Byte1]: 47
1682 06:48:17.530827
1683 06:48:17.530969 Set Vref, RX VrefLevel [Byte0]: 48
1684 06:48:17.534535 [Byte1]: 48
1685 06:48:17.538189
1686 06:48:17.538326 Set Vref, RX VrefLevel [Byte0]: 49
1687 06:48:17.541401 [Byte1]: 49
1688 06:48:17.545734
1689 06:48:17.545873 Set Vref, RX VrefLevel [Byte0]: 50
1690 06:48:17.552654 [Byte1]: 50
1691 06:48:17.552813
1692 06:48:17.555235 Set Vref, RX VrefLevel [Byte0]: 51
1693 06:48:17.558947 [Byte1]: 51
1694 06:48:17.559082
1695 06:48:17.562138 Set Vref, RX VrefLevel [Byte0]: 52
1696 06:48:17.566003 [Byte1]: 52
1697 06:48:17.566141
1698 06:48:17.569000 Set Vref, RX VrefLevel [Byte0]: 53
1699 06:48:17.572623 [Byte1]: 53
1700 06:48:17.576310
1701 06:48:17.576446 Set Vref, RX VrefLevel [Byte0]: 54
1702 06:48:17.579679 [Byte1]: 54
1703 06:48:17.583965
1704 06:48:17.584098 Set Vref, RX VrefLevel [Byte0]: 55
1705 06:48:17.587274 [Byte1]: 55
1706 06:48:17.592108
1707 06:48:17.592250 Set Vref, RX VrefLevel [Byte0]: 56
1708 06:48:17.595204 [Byte1]: 56
1709 06:48:17.599238
1710 06:48:17.599388 Set Vref, RX VrefLevel [Byte0]: 57
1711 06:48:17.603075 [Byte1]: 57
1712 06:48:17.606947
1713 06:48:17.607090 Set Vref, RX VrefLevel [Byte0]: 58
1714 06:48:17.610494 [Byte1]: 58
1715 06:48:17.614632
1716 06:48:17.614774 Set Vref, RX VrefLevel [Byte0]: 59
1717 06:48:17.617735 [Byte1]: 59
1718 06:48:17.622163
1719 06:48:17.622319 Set Vref, RX VrefLevel [Byte0]: 60
1720 06:48:17.625842 [Byte1]: 60
1721 06:48:17.630004
1722 06:48:17.630157 Set Vref, RX VrefLevel [Byte0]: 61
1723 06:48:17.633445 [Byte1]: 61
1724 06:48:17.637878
1725 06:48:17.638015 Set Vref, RX VrefLevel [Byte0]: 62
1726 06:48:17.640672 [Byte1]: 62
1727 06:48:17.645130
1728 06:48:17.645297 Set Vref, RX VrefLevel [Byte0]: 63
1729 06:48:17.648663 [Byte1]: 63
1730 06:48:17.652804
1731 06:48:17.652967 Set Vref, RX VrefLevel [Byte0]: 64
1732 06:48:17.656044 [Byte1]: 64
1733 06:48:17.660813
1734 06:48:17.660999 Set Vref, RX VrefLevel [Byte0]: 65
1735 06:48:17.663698 [Byte1]: 65
1736 06:48:17.668245
1737 06:48:17.668403 Set Vref, RX VrefLevel [Byte0]: 66
1738 06:48:17.671434 [Byte1]: 66
1739 06:48:17.675823
1740 06:48:17.676006 Set Vref, RX VrefLevel [Byte0]: 67
1741 06:48:17.679156 [Byte1]: 67
1742 06:48:17.683303
1743 06:48:17.683478 Set Vref, RX VrefLevel [Byte0]: 68
1744 06:48:17.686994 [Byte1]: 68
1745 06:48:17.691716
1746 06:48:17.691870 Set Vref, RX VrefLevel [Byte0]: 69
1747 06:48:17.694177 [Byte1]: 69
1748 06:48:17.698659
1749 06:48:17.698836 Set Vref, RX VrefLevel [Byte0]: 70
1750 06:48:17.702272 [Byte1]: 70
1751 06:48:17.706317
1752 06:48:17.706471 Set Vref, RX VrefLevel [Byte0]: 71
1753 06:48:17.709735 [Byte1]: 71
1754 06:48:17.714158
1755 06:48:17.714311 Set Vref, RX VrefLevel [Byte0]: 72
1756 06:48:17.717170 [Byte1]: 72
1757 06:48:17.722236
1758 06:48:17.722385 Set Vref, RX VrefLevel [Byte0]: 73
1759 06:48:17.724968 [Byte1]: 73
1760 06:48:17.729076
1761 06:48:17.729192 Set Vref, RX VrefLevel [Byte0]: 74
1762 06:48:17.732916 [Byte1]: 74
1763 06:48:17.736878
1764 06:48:17.736997 Set Vref, RX VrefLevel [Byte0]: 75
1765 06:48:17.740666 [Byte1]: 75
1766 06:48:17.744666
1767 06:48:17.744791 Set Vref, RX VrefLevel [Byte0]: 76
1768 06:48:17.748415 [Byte1]: 76
1769 06:48:17.752271
1770 06:48:17.752432 Set Vref, RX VrefLevel [Byte0]: 77
1771 06:48:17.755846 [Byte1]: 77
1772 06:48:17.759761
1773 06:48:17.759908 Set Vref, RX VrefLevel [Byte0]: 78
1774 06:48:17.763367 [Byte1]: 78
1775 06:48:17.767559
1776 06:48:17.767720 Set Vref, RX VrefLevel [Byte0]: 79
1777 06:48:17.770864 [Byte1]: 79
1778 06:48:17.775210
1779 06:48:17.775362 Set Vref, RX VrefLevel [Byte0]: 80
1780 06:48:17.778354 [Byte1]: 80
1781 06:48:17.783044
1782 06:48:17.783178 Final RX Vref Byte 0 = 60 to rank0
1783 06:48:17.786667 Final RX Vref Byte 1 = 58 to rank0
1784 06:48:17.789673 Final RX Vref Byte 0 = 60 to rank1
1785 06:48:17.793079 Final RX Vref Byte 1 = 58 to rank1==
1786 06:48:17.796392 Dram Type= 6, Freq= 0, CH_1, rank 0
1787 06:48:17.799387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 06:48:17.802829 ==
1789 06:48:17.802950 DQS Delay:
1790 06:48:17.803048 DQS0 = 0, DQS1 = 0
1791 06:48:17.806393 DQM Delay:
1792 06:48:17.806525 DQM0 = 83, DQM1 = 74
1793 06:48:17.809748 DQ Delay:
1794 06:48:17.809853 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1795 06:48:17.813195 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =76
1796 06:48:17.816556 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1797 06:48:17.819703 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1798 06:48:17.819826
1799 06:48:17.823349
1800 06:48:17.830065 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b00, (MSB)MR19= 0x606, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
1801 06:48:17.833071 CH1 RK0: MR19=606, MR18=2B00
1802 06:48:17.839840 CH1_RK0: MR19=0x606, MR18=0x2B00, DQSOSC=398, MR23=63, INC=93, DEC=62
1803 06:48:17.839993
1804 06:48:17.843203 ----->DramcWriteLeveling(PI) begin...
1805 06:48:17.843321 ==
1806 06:48:17.846597 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 06:48:17.850232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 06:48:17.850371 ==
1809 06:48:17.853518 Write leveling (Byte 0): 29 => 29
1810 06:48:17.857318 Write leveling (Byte 1): 29 => 29
1811 06:48:17.860593 DramcWriteLeveling(PI) end<-----
1812 06:48:17.860721
1813 06:48:17.860818 ==
1814 06:48:17.863759 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 06:48:17.866876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 06:48:17.867055 ==
1817 06:48:17.870364 [Gating] SW mode calibration
1818 06:48:17.876824 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1819 06:48:17.879943 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1820 06:48:17.886789 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1821 06:48:17.890068 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1822 06:48:17.893807 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 06:48:17.900444 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1824 06:48:17.903846 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 06:48:17.906944 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1826 06:48:17.913579 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 06:48:17.917019 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 06:48:17.920694 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 06:48:17.927069 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 06:48:17.930748 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 06:48:17.933716 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 06:48:17.940632 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1833 06:48:17.944083 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 06:48:17.947290 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 06:48:17.950729 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 06:48:17.957204 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1837 06:48:17.960714 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1838 06:48:17.963795 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1839 06:48:17.970765 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1840 06:48:17.973972 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 06:48:17.977064 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 06:48:17.984283 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 06:48:17.987608 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 06:48:17.990553 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 06:48:17.997476 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1846 06:48:18.000780 0 9 8 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
1847 06:48:18.004163 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1848 06:48:18.007807 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 06:48:18.014309 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 06:48:18.017960 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 06:48:18.020927 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 06:48:18.027585 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
1853 06:48:18.031066 0 10 4 | B1->B0 | 2f2f 2a2a | 1 0 | (1 1) (0 0)
1854 06:48:18.034200 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1855 06:48:18.041126 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 06:48:18.044682 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 06:48:18.047898 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 06:48:18.054531 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 06:48:18.058131 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 06:48:18.060892 0 11 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1861 06:48:18.068252 0 11 4 | B1->B0 | 2d2d 3c3c | 0 0 | (1 1) (0 0)
1862 06:48:18.071156 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1863 06:48:18.074582 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 06:48:18.078216 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 06:48:18.084698 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 06:48:18.088379 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 06:48:18.091347 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 06:48:18.098386 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 06:48:18.101466 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1870 06:48:18.104824 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1871 06:48:18.112050 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 06:48:18.115557 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 06:48:18.118488 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 06:48:18.122006 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 06:48:18.128801 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 06:48:18.132039 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 06:48:18.135754 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 06:48:18.142134 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 06:48:18.145675 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 06:48:18.148342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 06:48:18.155332 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 06:48:18.158600 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 06:48:18.161861 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 06:48:18.168559 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 06:48:18.172186 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1886 06:48:18.175388 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 06:48:18.178629 Total UI for P1: 0, mck2ui 16
1888 06:48:18.182195 best dqsien dly found for B0: ( 0, 14, 4)
1889 06:48:18.185352 Total UI for P1: 0, mck2ui 16
1890 06:48:18.188769 best dqsien dly found for B1: ( 0, 14, 6)
1891 06:48:18.192287 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1892 06:48:18.195166 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1893 06:48:18.195280
1894 06:48:18.198850 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1895 06:48:18.202287 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1896 06:48:18.205644 [Gating] SW calibration Done
1897 06:48:18.205753 ==
1898 06:48:18.208980 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 06:48:18.215761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1900 06:48:18.215896 ==
1901 06:48:18.215995 RX Vref Scan: 0
1902 06:48:18.216084
1903 06:48:18.218908 RX Vref 0 -> 0, step: 1
1904 06:48:18.218996
1905 06:48:18.222604 RX Delay -130 -> 252, step: 16
1906 06:48:18.225616 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1907 06:48:18.229157 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1908 06:48:18.232465 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1909 06:48:18.235796 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1910 06:48:18.242976 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1911 06:48:18.245754 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1912 06:48:18.248963 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1913 06:48:18.252382 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1914 06:48:18.255809 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1915 06:48:18.259035 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1916 06:48:18.266562 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1917 06:48:18.269421 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1918 06:48:18.272770 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1919 06:48:18.275906 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1920 06:48:18.279313 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1921 06:48:18.286624 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1922 06:48:18.286771 ==
1923 06:48:18.289489 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 06:48:18.292986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 06:48:18.293092 ==
1926 06:48:18.293156 DQS Delay:
1927 06:48:18.296287 DQS0 = 0, DQS1 = 0
1928 06:48:18.296375 DQM Delay:
1929 06:48:18.299725 DQM0 = 79, DQM1 = 77
1930 06:48:18.299822 DQ Delay:
1931 06:48:18.302742 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1932 06:48:18.306313 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1933 06:48:18.309384 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1934 06:48:18.313164 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1935 06:48:18.313278
1936 06:48:18.313384
1937 06:48:18.313443 ==
1938 06:48:18.316501 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 06:48:18.319516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 06:48:18.319626 ==
1941 06:48:18.319692
1942 06:48:18.319779
1943 06:48:18.322941 TX Vref Scan disable
1944 06:48:18.326425 == TX Byte 0 ==
1945 06:48:18.330276 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1946 06:48:18.333435 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1947 06:48:18.336599 == TX Byte 1 ==
1948 06:48:18.340187 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1949 06:48:18.343170 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1950 06:48:18.343278 ==
1951 06:48:18.346523 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 06:48:18.350618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 06:48:18.353501 ==
1954 06:48:18.364397 TX Vref=22, minBit 3, minWin=27, winSum=444
1955 06:48:18.367894 TX Vref=24, minBit 0, minWin=28, winSum=448
1956 06:48:18.371205 TX Vref=26, minBit 7, minWin=27, winSum=445
1957 06:48:18.374408 TX Vref=28, minBit 0, minWin=28, winSum=452
1958 06:48:18.377993 TX Vref=30, minBit 3, minWin=27, winSum=451
1959 06:48:18.381263 TX Vref=32, minBit 0, minWin=28, winSum=454
1960 06:48:18.387877 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1961 06:48:18.387998
1962 06:48:18.391107 Final TX Range 1 Vref 32
1963 06:48:18.391196
1964 06:48:18.391261 ==
1965 06:48:18.394559 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 06:48:18.398133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 06:48:18.398227 ==
1968 06:48:18.398292
1969 06:48:18.398351
1970 06:48:18.401158 TX Vref Scan disable
1971 06:48:18.404881 == TX Byte 0 ==
1972 06:48:18.407913 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1973 06:48:18.411453 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1974 06:48:18.414568 == TX Byte 1 ==
1975 06:48:18.417948 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1976 06:48:18.421463 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1977 06:48:18.421561
1978 06:48:18.425005 [DATLAT]
1979 06:48:18.425099 Freq=800, CH1 RK1
1980 06:48:18.425165
1981 06:48:18.428367 DATLAT Default: 0xa
1982 06:48:18.428470 0, 0xFFFF, sum = 0
1983 06:48:18.431519 1, 0xFFFF, sum = 0
1984 06:48:18.431606 2, 0xFFFF, sum = 0
1985 06:48:18.434510 3, 0xFFFF, sum = 0
1986 06:48:18.434597 4, 0xFFFF, sum = 0
1987 06:48:18.438379 5, 0xFFFF, sum = 0
1988 06:48:18.438495 6, 0xFFFF, sum = 0
1989 06:48:18.441665 7, 0xFFFF, sum = 0
1990 06:48:18.441753 8, 0xFFFF, sum = 0
1991 06:48:18.444724 9, 0x0, sum = 1
1992 06:48:18.444816 10, 0x0, sum = 2
1993 06:48:18.448361 11, 0x0, sum = 3
1994 06:48:18.448469 12, 0x0, sum = 4
1995 06:48:18.451813 best_step = 10
1996 06:48:18.451910
1997 06:48:18.451975 ==
1998 06:48:18.454671 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 06:48:18.458091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 06:48:18.458208 ==
2001 06:48:18.461561 RX Vref Scan: 0
2002 06:48:18.461656
2003 06:48:18.461722 RX Vref 0 -> 0, step: 1
2004 06:48:18.461783
2005 06:48:18.465037 RX Delay -95 -> 252, step: 8
2006 06:48:18.468213 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2007 06:48:18.475219 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2008 06:48:18.478503 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2009 06:48:18.482107 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2010 06:48:18.485313 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2011 06:48:18.488577 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2012 06:48:18.495421 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2013 06:48:18.498865 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2014 06:48:18.501965 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2015 06:48:18.505235 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2016 06:48:18.508827 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2017 06:48:18.512036 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2018 06:48:18.519072 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2019 06:48:18.522336 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2020 06:48:18.525726 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2021 06:48:18.528761 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2022 06:48:18.528858 ==
2023 06:48:18.532106 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 06:48:18.539164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 06:48:18.539281 ==
2026 06:48:18.539388 DQS Delay:
2027 06:48:18.539449 DQS0 = 0, DQS1 = 0
2028 06:48:18.542132 DQM Delay:
2029 06:48:18.542220 DQM0 = 80, DQM1 = 75
2030 06:48:18.545428 DQ Delay:
2031 06:48:18.549396 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2032 06:48:18.552285 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2033 06:48:18.552387 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2034 06:48:18.559209 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2035 06:48:18.559324
2036 06:48:18.559392
2037 06:48:18.565808 [DQSOSCAuto] RK1, (LSB)MR18= 0x212d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2038 06:48:18.569443 CH1 RK1: MR19=606, MR18=212D
2039 06:48:18.575569 CH1_RK1: MR19=0x606, MR18=0x212D, DQSOSC=398, MR23=63, INC=93, DEC=62
2040 06:48:18.579296 [RxdqsGatingPostProcess] freq 800
2041 06:48:18.582727 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2042 06:48:18.586273 Pre-setting of DQS Precalculation
2043 06:48:18.592547 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2044 06:48:18.599938 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2045 06:48:18.606105 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2046 06:48:18.606229
2047 06:48:18.606298
2048 06:48:18.609456 [Calibration Summary] 1600 Mbps
2049 06:48:18.609546 CH 0, Rank 0
2050 06:48:18.612910 SW Impedance : PASS
2051 06:48:18.612998 DUTY Scan : NO K
2052 06:48:18.616069 ZQ Calibration : PASS
2053 06:48:18.619792 Jitter Meter : NO K
2054 06:48:18.619888 CBT Training : PASS
2055 06:48:18.622581 Write leveling : PASS
2056 06:48:18.625989 RX DQS gating : PASS
2057 06:48:18.626085 RX DQ/DQS(RDDQC) : PASS
2058 06:48:18.629251 TX DQ/DQS : PASS
2059 06:48:18.632502 RX DATLAT : PASS
2060 06:48:18.632605 RX DQ/DQS(Engine): PASS
2061 06:48:18.636272 TX OE : NO K
2062 06:48:18.636369 All Pass.
2063 06:48:18.636434
2064 06:48:18.639412 CH 0, Rank 1
2065 06:48:18.639500 SW Impedance : PASS
2066 06:48:18.642811 DUTY Scan : NO K
2067 06:48:18.642928 ZQ Calibration : PASS
2068 06:48:18.646296 Jitter Meter : NO K
2069 06:48:18.649562 CBT Training : PASS
2070 06:48:18.649684 Write leveling : PASS
2071 06:48:18.653097 RX DQS gating : PASS
2072 06:48:18.656555 RX DQ/DQS(RDDQC) : PASS
2073 06:48:18.656694 TX DQ/DQS : PASS
2074 06:48:18.659986 RX DATLAT : PASS
2075 06:48:18.663361 RX DQ/DQS(Engine): PASS
2076 06:48:18.663493 TX OE : NO K
2077 06:48:18.666289 All Pass.
2078 06:48:18.666431
2079 06:48:18.666543 CH 1, Rank 0
2080 06:48:18.670209 SW Impedance : PASS
2081 06:48:18.670336 DUTY Scan : NO K
2082 06:48:18.673274 ZQ Calibration : PASS
2083 06:48:18.676802 Jitter Meter : NO K
2084 06:48:18.676990 CBT Training : PASS
2085 06:48:18.680367 Write leveling : PASS
2086 06:48:18.680478 RX DQS gating : PASS
2087 06:48:18.683276 RX DQ/DQS(RDDQC) : PASS
2088 06:48:18.687149 TX DQ/DQS : PASS
2089 06:48:18.687271 RX DATLAT : PASS
2090 06:48:18.689766 RX DQ/DQS(Engine): PASS
2091 06:48:18.693435 TX OE : NO K
2092 06:48:18.693536 All Pass.
2093 06:48:18.693624
2094 06:48:18.693704 CH 1, Rank 1
2095 06:48:18.696736 SW Impedance : PASS
2096 06:48:18.699967 DUTY Scan : NO K
2097 06:48:18.700060 ZQ Calibration : PASS
2098 06:48:18.703823 Jitter Meter : NO K
2099 06:48:18.706525 CBT Training : PASS
2100 06:48:18.706618 Write leveling : PASS
2101 06:48:18.709914 RX DQS gating : PASS
2102 06:48:18.710006 RX DQ/DQS(RDDQC) : PASS
2103 06:48:18.713440 TX DQ/DQS : PASS
2104 06:48:18.716940 RX DATLAT : PASS
2105 06:48:18.717033 RX DQ/DQS(Engine): PASS
2106 06:48:18.720347 TX OE : NO K
2107 06:48:18.720438 All Pass.
2108 06:48:18.720505
2109 06:48:18.724194 DramC Write-DBI off
2110 06:48:18.726946 PER_BANK_REFRESH: Hybrid Mode
2111 06:48:18.727038 TX_TRACKING: ON
2112 06:48:18.730259 [GetDramInforAfterCalByMRR] Vendor 6.
2113 06:48:18.733832 [GetDramInforAfterCalByMRR] Revision 606.
2114 06:48:18.737097 [GetDramInforAfterCalByMRR] Revision 2 0.
2115 06:48:18.740401 MR0 0x3b3b
2116 06:48:18.740503 MR8 0x5151
2117 06:48:18.743964 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 06:48:18.744060
2119 06:48:18.744127 MR0 0x3b3b
2120 06:48:18.747214 MR8 0x5151
2121 06:48:18.750667 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 06:48:18.750787
2123 06:48:18.760303 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2124 06:48:18.764594 [FAST_K] Save calibration result to emmc
2125 06:48:18.767205 [FAST_K] Save calibration result to emmc
2126 06:48:18.767298 dram_init: config_dvfs: 1
2127 06:48:18.773913 dramc_set_vcore_voltage set vcore to 662500
2128 06:48:18.774034 Read voltage for 1200, 2
2129 06:48:18.777502 Vio18 = 0
2130 06:48:18.777592 Vcore = 662500
2131 06:48:18.777657 Vdram = 0
2132 06:48:18.777716 Vddq = 0
2133 06:48:18.780233 Vmddr = 0
2134 06:48:18.783959 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2135 06:48:18.790271 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2136 06:48:18.790384 MEM_TYPE=3, freq_sel=15
2137 06:48:18.794783 sv_algorithm_assistance_LP4_1600
2138 06:48:18.800443 ============ PULL DRAM RESETB DOWN ============
2139 06:48:18.804006 ========== PULL DRAM RESETB DOWN end =========
2140 06:48:18.807062 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2141 06:48:18.810557 ===================================
2142 06:48:18.813705 LPDDR4 DRAM CONFIGURATION
2143 06:48:18.816872 ===================================
2144 06:48:18.821225 EX_ROW_EN[0] = 0x0
2145 06:48:18.821335 EX_ROW_EN[1] = 0x0
2146 06:48:18.824203 LP4Y_EN = 0x0
2147 06:48:18.824292 WORK_FSP = 0x0
2148 06:48:18.827185 WL = 0x4
2149 06:48:18.827272 RL = 0x4
2150 06:48:18.830334 BL = 0x2
2151 06:48:18.830445 RPST = 0x0
2152 06:48:18.833702 RD_PRE = 0x0
2153 06:48:18.833788 WR_PRE = 0x1
2154 06:48:18.837559 WR_PST = 0x0
2155 06:48:18.837655 DBI_WR = 0x0
2156 06:48:18.840323 DBI_RD = 0x0
2157 06:48:18.840415 OTF = 0x1
2158 06:48:18.844164 ===================================
2159 06:48:18.847333 ===================================
2160 06:48:18.850629 ANA top config
2161 06:48:18.854173 ===================================
2162 06:48:18.854306 DLL_ASYNC_EN = 0
2163 06:48:18.857540 ALL_SLAVE_EN = 0
2164 06:48:18.860659 NEW_RANK_MODE = 1
2165 06:48:18.864279 DLL_IDLE_MODE = 1
2166 06:48:18.867620 LP45_APHY_COMB_EN = 1
2167 06:48:18.867720 TX_ODT_DIS = 1
2168 06:48:18.870877 NEW_8X_MODE = 1
2169 06:48:18.874259 ===================================
2170 06:48:18.877487 ===================================
2171 06:48:18.881098 data_rate = 2400
2172 06:48:18.884484 CKR = 1
2173 06:48:18.887816 DQ_P2S_RATIO = 8
2174 06:48:18.890780 ===================================
2175 06:48:18.890870 CA_P2S_RATIO = 8
2176 06:48:18.894538 DQ_CA_OPEN = 0
2177 06:48:18.897624 DQ_SEMI_OPEN = 0
2178 06:48:18.901360 CA_SEMI_OPEN = 0
2179 06:48:18.904277 CA_FULL_RATE = 0
2180 06:48:18.904372 DQ_CKDIV4_EN = 0
2181 06:48:18.907917 CA_CKDIV4_EN = 0
2182 06:48:18.911223 CA_PREDIV_EN = 0
2183 06:48:18.914778 PH8_DLY = 17
2184 06:48:18.917803 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2185 06:48:18.921264 DQ_AAMCK_DIV = 4
2186 06:48:18.921366 CA_AAMCK_DIV = 4
2187 06:48:18.924478 CA_ADMCK_DIV = 4
2188 06:48:18.927948 DQ_TRACK_CA_EN = 0
2189 06:48:18.931230 CA_PICK = 1200
2190 06:48:18.934609 CA_MCKIO = 1200
2191 06:48:18.938423 MCKIO_SEMI = 0
2192 06:48:18.941423 PLL_FREQ = 2366
2193 06:48:18.941514 DQ_UI_PI_RATIO = 32
2194 06:48:18.944964 CA_UI_PI_RATIO = 0
2195 06:48:18.948389 ===================================
2196 06:48:18.951806 ===================================
2197 06:48:18.954907 memory_type:LPDDR4
2198 06:48:18.958256 GP_NUM : 10
2199 06:48:18.958378 SRAM_EN : 1
2200 06:48:18.962050 MD32_EN : 0
2201 06:48:18.965353 ===================================
2202 06:48:18.965448 [ANA_INIT] >>>>>>>>>>>>>>
2203 06:48:18.968257 <<<<<< [CONFIGURE PHASE]: ANA_TX
2204 06:48:18.971860 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2205 06:48:18.974773 ===================================
2206 06:48:18.978060 data_rate = 2400,PCW = 0X5b00
2207 06:48:18.981820 ===================================
2208 06:48:18.984996 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2209 06:48:18.991616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 06:48:18.994949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 06:48:19.001464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2212 06:48:19.005558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2213 06:48:19.008204 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2214 06:48:19.008334 [ANA_INIT] flow start
2215 06:48:19.011571 [ANA_INIT] PLL >>>>>>>>
2216 06:48:19.015299 [ANA_INIT] PLL <<<<<<<<
2217 06:48:19.018126 [ANA_INIT] MIDPI >>>>>>>>
2218 06:48:19.018240 [ANA_INIT] MIDPI <<<<<<<<
2219 06:48:19.021711 [ANA_INIT] DLL >>>>>>>>
2220 06:48:19.025105 [ANA_INIT] DLL <<<<<<<<
2221 06:48:19.025222 [ANA_INIT] flow end
2222 06:48:19.028410 ============ LP4 DIFF to SE enter ============
2223 06:48:19.035016 ============ LP4 DIFF to SE exit ============
2224 06:48:19.035186 [ANA_INIT] <<<<<<<<<<<<<
2225 06:48:19.038432 [Flow] Enable top DCM control >>>>>
2226 06:48:19.041768 [Flow] Enable top DCM control <<<<<
2227 06:48:19.045666 Enable DLL master slave shuffle
2228 06:48:19.051688 ==============================================================
2229 06:48:19.051839 Gating Mode config
2230 06:48:19.058813 ==============================================================
2231 06:48:19.062141 Config description:
2232 06:48:19.069141 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2233 06:48:19.075688 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2234 06:48:19.082092 SELPH_MODE 0: By rank 1: By Phase
2235 06:48:19.088674 ==============================================================
2236 06:48:19.088844 GAT_TRACK_EN = 1
2237 06:48:19.091846 RX_GATING_MODE = 2
2238 06:48:19.095378 RX_GATING_TRACK_MODE = 2
2239 06:48:19.098427 SELPH_MODE = 1
2240 06:48:19.101893 PICG_EARLY_EN = 1
2241 06:48:19.105483 VALID_LAT_VALUE = 1
2242 06:48:19.111878 ==============================================================
2243 06:48:19.115279 Enter into Gating configuration >>>>
2244 06:48:19.118989 Exit from Gating configuration <<<<
2245 06:48:19.119104 Enter into DVFS_PRE_config >>>>>
2246 06:48:19.132646 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2247 06:48:19.135908 Exit from DVFS_PRE_config <<<<<
2248 06:48:19.139193 Enter into PICG configuration >>>>
2249 06:48:19.142705 Exit from PICG configuration <<<<
2250 06:48:19.142802 [RX_INPUT] configuration >>>>>
2251 06:48:19.146085 [RX_INPUT] configuration <<<<<
2252 06:48:19.152498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2253 06:48:19.155723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2254 06:48:19.162625 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 06:48:19.169880 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 06:48:19.175662 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 06:48:19.182546 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 06:48:19.185790 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2259 06:48:19.189217 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2260 06:48:19.192772 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2261 06:48:19.200095 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2262 06:48:19.202594 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2263 06:48:19.206163 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 06:48:19.209617 ===================================
2265 06:48:19.213378 LPDDR4 DRAM CONFIGURATION
2266 06:48:19.216442 ===================================
2267 06:48:19.216560 EX_ROW_EN[0] = 0x0
2268 06:48:19.220008 EX_ROW_EN[1] = 0x0
2269 06:48:19.220105 LP4Y_EN = 0x0
2270 06:48:19.222952 WORK_FSP = 0x0
2271 06:48:19.223062 WL = 0x4
2272 06:48:19.226219 RL = 0x4
2273 06:48:19.229825 BL = 0x2
2274 06:48:19.229923 RPST = 0x0
2275 06:48:19.233438 RD_PRE = 0x0
2276 06:48:19.233531 WR_PRE = 0x1
2277 06:48:19.236254 WR_PST = 0x0
2278 06:48:19.236335 DBI_WR = 0x0
2279 06:48:19.240040 DBI_RD = 0x0
2280 06:48:19.240127 OTF = 0x1
2281 06:48:19.243333 ===================================
2282 06:48:19.246340 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2283 06:48:19.249569 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2284 06:48:19.256382 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2285 06:48:19.259903 ===================================
2286 06:48:19.263585 LPDDR4 DRAM CONFIGURATION
2287 06:48:19.267178 ===================================
2288 06:48:19.267323 EX_ROW_EN[0] = 0x10
2289 06:48:19.269916 EX_ROW_EN[1] = 0x0
2290 06:48:19.270030 LP4Y_EN = 0x0
2291 06:48:19.273667 WORK_FSP = 0x0
2292 06:48:19.273780 WL = 0x4
2293 06:48:19.276884 RL = 0x4
2294 06:48:19.276968 BL = 0x2
2295 06:48:19.280740 RPST = 0x0
2296 06:48:19.280851 RD_PRE = 0x0
2297 06:48:19.283679 WR_PRE = 0x1
2298 06:48:19.283795 WR_PST = 0x0
2299 06:48:19.286771 DBI_WR = 0x0
2300 06:48:19.286852 DBI_RD = 0x0
2301 06:48:19.290336 OTF = 0x1
2302 06:48:19.293344 ===================================
2303 06:48:19.300256 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2304 06:48:19.300391 ==
2305 06:48:19.303536 Dram Type= 6, Freq= 0, CH_0, rank 0
2306 06:48:19.307015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2307 06:48:19.307153 ==
2308 06:48:19.310053 [Duty_Offset_Calibration]
2309 06:48:19.310145 B0:2 B1:-1 CA:1
2310 06:48:19.310211
2311 06:48:19.313373 [DutyScan_Calibration_Flow] k_type=0
2312 06:48:19.323436
2313 06:48:19.323563 ==CLK 0==
2314 06:48:19.326360 Final CLK duty delay cell = -4
2315 06:48:19.329359 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2316 06:48:19.332823 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2317 06:48:19.336739 [-4] AVG Duty = 4953%(X100)
2318 06:48:19.336851
2319 06:48:19.339800 CH0 CLK Duty spec in!! Max-Min= 156%
2320 06:48:19.343244 [DutyScan_Calibration_Flow] ====Done====
2321 06:48:19.343350
2322 06:48:19.346903 [DutyScan_Calibration_Flow] k_type=1
2323 06:48:19.361401
2324 06:48:19.361577 ==DQS 0 ==
2325 06:48:19.364249 Final DQS duty delay cell = -4
2326 06:48:19.367987 [-4] MAX Duty = 5000%(X100), DQS PI = 44
2327 06:48:19.370841 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2328 06:48:19.374207 [-4] AVG Duty = 4938%(X100)
2329 06:48:19.374344
2330 06:48:19.374457 ==DQS 1 ==
2331 06:48:19.378605 Final DQS duty delay cell = -4
2332 06:48:19.380968 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2333 06:48:19.384210 [-4] MIN Duty = 5000%(X100), DQS PI = 58
2334 06:48:19.387549 [-4] AVG Duty = 5062%(X100)
2335 06:48:19.387682
2336 06:48:19.390929 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2337 06:48:19.391034
2338 06:48:19.394571 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2339 06:48:19.397760 [DutyScan_Calibration_Flow] ====Done====
2340 06:48:19.397891
2341 06:48:19.401043 [DutyScan_Calibration_Flow] k_type=3
2342 06:48:19.418718
2343 06:48:19.418898 ==DQM 0 ==
2344 06:48:19.421766 Final DQM duty delay cell = 0
2345 06:48:19.425085 [0] MAX Duty = 5000%(X100), DQS PI = 46
2346 06:48:19.428192 [0] MIN Duty = 4907%(X100), DQS PI = 2
2347 06:48:19.428310 [0] AVG Duty = 4953%(X100)
2348 06:48:19.431970
2349 06:48:19.432138 ==DQM 1 ==
2350 06:48:19.435089 Final DQM duty delay cell = 0
2351 06:48:19.438357 [0] MAX Duty = 5156%(X100), DQS PI = 62
2352 06:48:19.442037 [0] MIN Duty = 5000%(X100), DQS PI = 10
2353 06:48:19.442190 [0] AVG Duty = 5078%(X100)
2354 06:48:19.442294
2355 06:48:19.444954 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2356 06:48:19.448386
2357 06:48:19.451927 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2358 06:48:19.455112 [DutyScan_Calibration_Flow] ====Done====
2359 06:48:19.455283
2360 06:48:19.458251 [DutyScan_Calibration_Flow] k_type=2
2361 06:48:19.474017
2362 06:48:19.474202 ==DQ 0 ==
2363 06:48:19.477543 Final DQ duty delay cell = -4
2364 06:48:19.480312 [-4] MAX Duty = 5062%(X100), DQS PI = 56
2365 06:48:19.483637 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2366 06:48:19.487436 [-4] AVG Duty = 4969%(X100)
2367 06:48:19.487551
2368 06:48:19.487645 ==DQ 1 ==
2369 06:48:19.490658 Final DQ duty delay cell = 0
2370 06:48:19.493872 [0] MAX Duty = 5031%(X100), DQS PI = 18
2371 06:48:19.497649 [0] MIN Duty = 4907%(X100), DQS PI = 46
2372 06:48:19.497757 [0] AVG Duty = 4969%(X100)
2373 06:48:19.497850
2374 06:48:19.500539 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2375 06:48:19.504025
2376 06:48:19.507270 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2377 06:48:19.511247 [DutyScan_Calibration_Flow] ====Done====
2378 06:48:19.511358 ==
2379 06:48:19.514371 Dram Type= 6, Freq= 0, CH_1, rank 0
2380 06:48:19.517385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2381 06:48:19.517493 ==
2382 06:48:19.520769 [Duty_Offset_Calibration]
2383 06:48:19.520879 B0:1 B1:1 CA:2
2384 06:48:19.520981
2385 06:48:19.524326 [DutyScan_Calibration_Flow] k_type=0
2386 06:48:19.533774
2387 06:48:19.533901 ==CLK 0==
2388 06:48:19.537464 Final CLK duty delay cell = 0
2389 06:48:19.540811 [0] MAX Duty = 5094%(X100), DQS PI = 56
2390 06:48:19.545002 [0] MIN Duty = 4969%(X100), DQS PI = 8
2391 06:48:19.545118 [0] AVG Duty = 5031%(X100)
2392 06:48:19.545209
2393 06:48:19.547472 CH1 CLK Duty spec in!! Max-Min= 125%
2394 06:48:19.554078 [DutyScan_Calibration_Flow] ====Done====
2395 06:48:19.554204
2396 06:48:19.557502 [DutyScan_Calibration_Flow] k_type=1
2397 06:48:19.573296
2398 06:48:19.573480 ==DQS 0 ==
2399 06:48:19.576733 Final DQS duty delay cell = 0
2400 06:48:19.580167 [0] MAX Duty = 5031%(X100), DQS PI = 50
2401 06:48:19.584099 [0] MIN Duty = 4875%(X100), DQS PI = 16
2402 06:48:19.584203 [0] AVG Duty = 4953%(X100)
2403 06:48:19.584293
2404 06:48:19.586912 ==DQS 1 ==
2405 06:48:19.590528 Final DQS duty delay cell = 0
2406 06:48:19.593880 [0] MAX Duty = 5062%(X100), DQS PI = 28
2407 06:48:19.597284 [0] MIN Duty = 4907%(X100), DQS PI = 0
2408 06:48:19.597388 [0] AVG Duty = 4984%(X100)
2409 06:48:19.597477
2410 06:48:19.600507 CH1 DQS 0 Duty spec in!! Max-Min= 156%
2411 06:48:19.603904
2412 06:48:19.607396 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2413 06:48:19.610342 [DutyScan_Calibration_Flow] ====Done====
2414 06:48:19.610485
2415 06:48:19.613564 [DutyScan_Calibration_Flow] k_type=3
2416 06:48:19.630145
2417 06:48:19.630323 ==DQM 0 ==
2418 06:48:19.633029 Final DQM duty delay cell = 0
2419 06:48:19.636471 [0] MAX Duty = 5093%(X100), DQS PI = 6
2420 06:48:19.640350 [0] MIN Duty = 4907%(X100), DQS PI = 18
2421 06:48:19.640464 [0] AVG Duty = 5000%(X100)
2422 06:48:19.640555
2423 06:48:19.643553 ==DQM 1 ==
2424 06:48:19.646370 Final DQM duty delay cell = 0
2425 06:48:19.650124 [0] MAX Duty = 5156%(X100), DQS PI = 30
2426 06:48:19.653615 [0] MIN Duty = 4938%(X100), DQS PI = 56
2427 06:48:19.653731 [0] AVG Duty = 5047%(X100)
2428 06:48:19.653830
2429 06:48:19.660121 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2430 06:48:19.660241
2431 06:48:19.663654 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2432 06:48:19.666872 [DutyScan_Calibration_Flow] ====Done====
2433 06:48:19.666977
2434 06:48:19.669700 [DutyScan_Calibration_Flow] k_type=2
2435 06:48:19.685816
2436 06:48:19.685986 ==DQ 0 ==
2437 06:48:19.689329 Final DQ duty delay cell = 0
2438 06:48:19.692372 [0] MAX Duty = 5124%(X100), DQS PI = 50
2439 06:48:19.696165 [0] MIN Duty = 4969%(X100), DQS PI = 0
2440 06:48:19.696275 [0] AVG Duty = 5046%(X100)
2441 06:48:19.696375
2442 06:48:19.699104 ==DQ 1 ==
2443 06:48:19.703076 Final DQ duty delay cell = -4
2444 06:48:19.705888 [-4] MAX Duty = 5000%(X100), DQS PI = 26
2445 06:48:19.709210 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2446 06:48:19.709330 [-4] AVG Duty = 4953%(X100)
2447 06:48:19.709425
2448 06:48:19.712481 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2449 06:48:19.715916
2450 06:48:19.716033 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2451 06:48:19.722880 [DutyScan_Calibration_Flow] ====Done====
2452 06:48:19.725734 nWR fixed to 30
2453 06:48:19.725859 [ModeRegInit_LP4] CH0 RK0
2454 06:48:19.729452 [ModeRegInit_LP4] CH0 RK1
2455 06:48:19.732428 [ModeRegInit_LP4] CH1 RK0
2456 06:48:19.732545 [ModeRegInit_LP4] CH1 RK1
2457 06:48:19.735883 match AC timing 7
2458 06:48:19.739458 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2459 06:48:19.742933 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2460 06:48:19.749212 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2461 06:48:19.753140 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2462 06:48:19.759639 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2463 06:48:19.759747 ==
2464 06:48:19.763409 Dram Type= 6, Freq= 0, CH_0, rank 0
2465 06:48:19.766786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2466 06:48:19.766898 ==
2467 06:48:19.769592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2468 06:48:19.776262 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2469 06:48:19.785883 [CA 0] Center 40 (10~71) winsize 62
2470 06:48:19.789032 [CA 1] Center 39 (9~70) winsize 62
2471 06:48:19.792329 [CA 2] Center 36 (6~67) winsize 62
2472 06:48:19.796086 [CA 3] Center 35 (5~66) winsize 62
2473 06:48:19.799271 [CA 4] Center 34 (4~65) winsize 62
2474 06:48:19.802797 [CA 5] Center 34 (4~64) winsize 61
2475 06:48:19.802900
2476 06:48:19.806507 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2477 06:48:19.806646
2478 06:48:19.809736 [CATrainingPosCal] consider 1 rank data
2479 06:48:19.812537 u2DelayCellTimex100 = 270/100 ps
2480 06:48:19.816051 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2481 06:48:19.819285 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2482 06:48:19.826133 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2483 06:48:19.829439 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2484 06:48:19.832922 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2485 06:48:19.836264 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2486 06:48:19.836392
2487 06:48:19.839399 CA PerBit enable=1, Macro0, CA PI delay=34
2488 06:48:19.839480
2489 06:48:19.843071 [CBTSetCACLKResult] CA Dly = 34
2490 06:48:19.843152 CS Dly: 7 (0~38)
2491 06:48:19.843217 ==
2492 06:48:19.846247 Dram Type= 6, Freq= 0, CH_0, rank 1
2493 06:48:19.853090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2494 06:48:19.853211 ==
2495 06:48:19.856431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2496 06:48:19.862951 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2497 06:48:19.871766 [CA 0] Center 39 (9~70) winsize 62
2498 06:48:19.875153 [CA 1] Center 40 (10~70) winsize 61
2499 06:48:19.878269 [CA 2] Center 36 (6~67) winsize 62
2500 06:48:19.881472 [CA 3] Center 35 (5~66) winsize 62
2501 06:48:19.884882 [CA 4] Center 34 (4~65) winsize 62
2502 06:48:19.888336 [CA 5] Center 34 (4~64) winsize 61
2503 06:48:19.888447
2504 06:48:19.892000 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2505 06:48:19.892081
2506 06:48:19.895458 [CATrainingPosCal] consider 2 rank data
2507 06:48:19.898723 u2DelayCellTimex100 = 270/100 ps
2508 06:48:19.902253 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2509 06:48:19.905638 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2510 06:48:19.912461 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2511 06:48:19.915314 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2512 06:48:19.918577 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2513 06:48:19.922507 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2514 06:48:19.922606
2515 06:48:19.925882 CA PerBit enable=1, Macro0, CA PI delay=34
2516 06:48:19.925987
2517 06:48:19.928593 [CBTSetCACLKResult] CA Dly = 34
2518 06:48:19.928705 CS Dly: 8 (0~41)
2519 06:48:19.928802
2520 06:48:19.932423 ----->DramcWriteLeveling(PI) begin...
2521 06:48:19.932529 ==
2522 06:48:19.936260 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 06:48:19.942280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 06:48:19.942402 ==
2525 06:48:19.945767 Write leveling (Byte 0): 31 => 31
2526 06:48:19.945881 Write leveling (Byte 1): 28 => 28
2527 06:48:19.949426 DramcWriteLeveling(PI) end<-----
2528 06:48:19.949538
2529 06:48:19.952796 ==
2530 06:48:19.952878 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 06:48:19.959261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 06:48:19.959375 ==
2533 06:48:19.962973 [Gating] SW mode calibration
2534 06:48:19.969320 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2535 06:48:19.973068 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2536 06:48:19.979251 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 06:48:19.982754 0 15 4 | B1->B0 | 2626 3333 | 1 0 | (1 1) (0 0)
2538 06:48:19.985867 0 15 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2539 06:48:19.989497 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 06:48:19.995994 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 06:48:19.999503 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 06:48:20.002339 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 06:48:20.009598 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 06:48:20.012929 1 0 0 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
2545 06:48:20.015901 1 0 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2546 06:48:20.023058 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 06:48:20.026312 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 06:48:20.029685 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 06:48:20.036139 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 06:48:20.039665 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 06:48:20.042922 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 06:48:20.049700 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2553 06:48:20.054064 1 1 4 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
2554 06:48:20.056311 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 06:48:20.059672 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 06:48:20.066599 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 06:48:20.070049 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 06:48:20.073101 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 06:48:20.080142 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 06:48:20.083441 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2561 06:48:20.086417 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2562 06:48:20.093636 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 06:48:20.096440 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 06:48:20.099604 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 06:48:20.106354 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 06:48:20.109896 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 06:48:20.113595 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 06:48:20.120423 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 06:48:20.123345 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 06:48:20.126465 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 06:48:20.133442 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 06:48:20.136674 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 06:48:20.139926 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 06:48:20.143121 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 06:48:20.149875 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 06:48:20.153594 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2577 06:48:20.156712 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2578 06:48:20.159963 Total UI for P1: 0, mck2ui 16
2579 06:48:20.164071 best dqsien dly found for B0: ( 1, 4, 0)
2580 06:48:20.170565 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 06:48:20.170693 Total UI for P1: 0, mck2ui 16
2582 06:48:20.173845 best dqsien dly found for B1: ( 1, 4, 2)
2583 06:48:20.176960 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2584 06:48:20.183863 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2585 06:48:20.183969
2586 06:48:20.187455 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2587 06:48:20.190306 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2588 06:48:20.193821 [Gating] SW calibration Done
2589 06:48:20.193904 ==
2590 06:48:20.196909 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 06:48:20.200575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 06:48:20.200687 ==
2593 06:48:20.200786 RX Vref Scan: 0
2594 06:48:20.200886
2595 06:48:20.204465 RX Vref 0 -> 0, step: 1
2596 06:48:20.204542
2597 06:48:20.207215 RX Delay -40 -> 252, step: 8
2598 06:48:20.210631 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2599 06:48:20.214217 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2600 06:48:20.221359 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2601 06:48:20.223791 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2602 06:48:20.227806 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2603 06:48:20.230984 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2604 06:48:20.233877 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2605 06:48:20.237580 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2606 06:48:20.244410 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2607 06:48:20.247626 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2608 06:48:20.251548 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2609 06:48:20.254559 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2610 06:48:20.257599 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2611 06:48:20.261095 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2612 06:48:20.267618 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2613 06:48:20.271334 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2614 06:48:20.271437 ==
2615 06:48:20.274908 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 06:48:20.277701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 06:48:20.277792 ==
2618 06:48:20.281355 DQS Delay:
2619 06:48:20.281443 DQS0 = 0, DQS1 = 0
2620 06:48:20.281532 DQM Delay:
2621 06:48:20.285079 DQM0 = 115, DQM1 = 106
2622 06:48:20.285174 DQ Delay:
2623 06:48:20.288214 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2624 06:48:20.291178 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2625 06:48:20.295164 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2626 06:48:20.297995 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2627 06:48:20.301767
2628 06:48:20.301865
2629 06:48:20.301955 ==
2630 06:48:20.304827 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 06:48:20.307899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 06:48:20.307994 ==
2633 06:48:20.308083
2634 06:48:20.308165
2635 06:48:20.311384 TX Vref Scan disable
2636 06:48:20.311477 == TX Byte 0 ==
2637 06:48:20.317980 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2638 06:48:20.321319 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2639 06:48:20.321425 == TX Byte 1 ==
2640 06:48:20.328118 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2641 06:48:20.331433 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2642 06:48:20.331559 ==
2643 06:48:20.334941 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 06:48:20.338691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 06:48:20.338789 ==
2646 06:48:20.350491 TX Vref=22, minBit 1, minWin=25, winSum=419
2647 06:48:20.354207 TX Vref=24, minBit 7, minWin=25, winSum=426
2648 06:48:20.357329 TX Vref=26, minBit 0, minWin=26, winSum=428
2649 06:48:20.360690 TX Vref=28, minBit 0, minWin=26, winSum=432
2650 06:48:20.363903 TX Vref=30, minBit 1, minWin=26, winSum=432
2651 06:48:20.367009 TX Vref=32, minBit 0, minWin=26, winSum=431
2652 06:48:20.373952 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
2653 06:48:20.374092
2654 06:48:20.377552 Final TX Range 1 Vref 28
2655 06:48:20.377669
2656 06:48:20.377746 ==
2657 06:48:20.380459 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 06:48:20.383979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 06:48:20.384089 ==
2660 06:48:20.384157
2661 06:48:20.384218
2662 06:48:20.387787 TX Vref Scan disable
2663 06:48:20.390510 == TX Byte 0 ==
2664 06:48:20.394564 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2665 06:48:20.397790 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2666 06:48:20.400626 == TX Byte 1 ==
2667 06:48:20.404198 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2668 06:48:20.407455 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2669 06:48:20.407574
2670 06:48:20.411079 [DATLAT]
2671 06:48:20.411177 Freq=1200, CH0 RK0
2672 06:48:20.411250
2673 06:48:20.413919 DATLAT Default: 0xd
2674 06:48:20.414021 0, 0xFFFF, sum = 0
2675 06:48:20.417395 1, 0xFFFF, sum = 0
2676 06:48:20.417490 2, 0xFFFF, sum = 0
2677 06:48:20.421388 3, 0xFFFF, sum = 0
2678 06:48:20.421494 4, 0xFFFF, sum = 0
2679 06:48:20.424197 5, 0xFFFF, sum = 0
2680 06:48:20.424285 6, 0xFFFF, sum = 0
2681 06:48:20.427781 7, 0xFFFF, sum = 0
2682 06:48:20.427872 8, 0xFFFF, sum = 0
2683 06:48:20.430898 9, 0xFFFF, sum = 0
2684 06:48:20.430995 10, 0xFFFF, sum = 0
2685 06:48:20.435018 11, 0xFFFF, sum = 0
2686 06:48:20.435122 12, 0x0, sum = 1
2687 06:48:20.437643 13, 0x0, sum = 2
2688 06:48:20.437730 14, 0x0, sum = 3
2689 06:48:20.440972 15, 0x0, sum = 4
2690 06:48:20.441076 best_step = 13
2691 06:48:20.441160
2692 06:48:20.441223 ==
2693 06:48:20.444460 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 06:48:20.451570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 06:48:20.451723 ==
2696 06:48:20.451805 RX Vref Scan: 1
2697 06:48:20.451867
2698 06:48:20.454345 Set Vref Range= 32 -> 127
2699 06:48:20.454442
2700 06:48:20.457707 RX Vref 32 -> 127, step: 1
2701 06:48:20.457797
2702 06:48:20.457863 RX Delay -21 -> 252, step: 4
2703 06:48:20.457923
2704 06:48:20.461401 Set Vref, RX VrefLevel [Byte0]: 32
2705 06:48:20.464225 [Byte1]: 32
2706 06:48:20.468917
2707 06:48:20.469006 Set Vref, RX VrefLevel [Byte0]: 33
2708 06:48:20.472192 [Byte1]: 33
2709 06:48:20.477097
2710 06:48:20.477187 Set Vref, RX VrefLevel [Byte0]: 34
2711 06:48:20.480200 [Byte1]: 34
2712 06:48:20.484490
2713 06:48:20.484571 Set Vref, RX VrefLevel [Byte0]: 35
2714 06:48:20.488103 [Byte1]: 35
2715 06:48:20.492742
2716 06:48:20.492829 Set Vref, RX VrefLevel [Byte0]: 36
2717 06:48:20.496154 [Byte1]: 36
2718 06:48:20.500359
2719 06:48:20.500444 Set Vref, RX VrefLevel [Byte0]: 37
2720 06:48:20.503870 [Byte1]: 37
2721 06:48:20.508281
2722 06:48:20.508372 Set Vref, RX VrefLevel [Byte0]: 38
2723 06:48:20.511613 [Byte1]: 38
2724 06:48:20.516051
2725 06:48:20.516147 Set Vref, RX VrefLevel [Byte0]: 39
2726 06:48:20.519858 [Byte1]: 39
2727 06:48:20.524239
2728 06:48:20.524330 Set Vref, RX VrefLevel [Byte0]: 40
2729 06:48:20.527403 [Byte1]: 40
2730 06:48:20.532253
2731 06:48:20.532351 Set Vref, RX VrefLevel [Byte0]: 41
2732 06:48:20.535639 [Byte1]: 41
2733 06:48:20.541245
2734 06:48:20.541395 Set Vref, RX VrefLevel [Byte0]: 42
2735 06:48:20.543599 [Byte1]: 42
2736 06:48:20.548449
2737 06:48:20.548550 Set Vref, RX VrefLevel [Byte0]: 43
2738 06:48:20.551686 [Byte1]: 43
2739 06:48:20.555894
2740 06:48:20.555997 Set Vref, RX VrefLevel [Byte0]: 44
2741 06:48:20.559171 [Byte1]: 44
2742 06:48:20.564051
2743 06:48:20.564154 Set Vref, RX VrefLevel [Byte0]: 45
2744 06:48:20.567356 [Byte1]: 45
2745 06:48:20.571566
2746 06:48:20.571664 Set Vref, RX VrefLevel [Byte0]: 46
2747 06:48:20.575580 [Byte1]: 46
2748 06:48:20.579778
2749 06:48:20.579905 Set Vref, RX VrefLevel [Byte0]: 47
2750 06:48:20.582984 [Byte1]: 47
2751 06:48:20.587903
2752 06:48:20.588047 Set Vref, RX VrefLevel [Byte0]: 48
2753 06:48:20.591012 [Byte1]: 48
2754 06:48:20.595643
2755 06:48:20.595745 Set Vref, RX VrefLevel [Byte0]: 49
2756 06:48:20.598927 [Byte1]: 49
2757 06:48:20.603496
2758 06:48:20.603611 Set Vref, RX VrefLevel [Byte0]: 50
2759 06:48:20.606970 [Byte1]: 50
2760 06:48:20.611231
2761 06:48:20.611355 Set Vref, RX VrefLevel [Byte0]: 51
2762 06:48:20.615197 [Byte1]: 51
2763 06:48:20.619183
2764 06:48:20.619311 Set Vref, RX VrefLevel [Byte0]: 52
2765 06:48:20.623254 [Byte1]: 52
2766 06:48:20.627279
2767 06:48:20.627415 Set Vref, RX VrefLevel [Byte0]: 53
2768 06:48:20.630861 [Byte1]: 53
2769 06:48:20.635267
2770 06:48:20.635368 Set Vref, RX VrefLevel [Byte0]: 54
2771 06:48:20.638293 [Byte1]: 54
2772 06:48:20.643139
2773 06:48:20.643241 Set Vref, RX VrefLevel [Byte0]: 55
2774 06:48:20.646208 [Byte1]: 55
2775 06:48:20.650924
2776 06:48:20.651020 Set Vref, RX VrefLevel [Byte0]: 56
2777 06:48:20.654204 [Byte1]: 56
2778 06:48:20.658898
2779 06:48:20.659006 Set Vref, RX VrefLevel [Byte0]: 57
2780 06:48:20.662328 [Byte1]: 57
2781 06:48:20.666904
2782 06:48:20.667004 Set Vref, RX VrefLevel [Byte0]: 58
2783 06:48:20.670147 [Byte1]: 58
2784 06:48:20.674822
2785 06:48:20.674926 Set Vref, RX VrefLevel [Byte0]: 59
2786 06:48:20.678361 [Byte1]: 59
2787 06:48:20.682624
2788 06:48:20.682726 Set Vref, RX VrefLevel [Byte0]: 60
2789 06:48:20.686284 [Byte1]: 60
2790 06:48:20.691130
2791 06:48:20.691245 Set Vref, RX VrefLevel [Byte0]: 61
2792 06:48:20.693827 [Byte1]: 61
2793 06:48:20.698342
2794 06:48:20.698455 Set Vref, RX VrefLevel [Byte0]: 62
2795 06:48:20.702180 [Byte1]: 62
2796 06:48:20.706761
2797 06:48:20.706867 Set Vref, RX VrefLevel [Byte0]: 63
2798 06:48:20.709595 [Byte1]: 63
2799 06:48:20.714416
2800 06:48:20.714520 Set Vref, RX VrefLevel [Byte0]: 64
2801 06:48:20.718125 [Byte1]: 64
2802 06:48:20.722556
2803 06:48:20.722658 Set Vref, RX VrefLevel [Byte0]: 65
2804 06:48:20.725629 [Byte1]: 65
2805 06:48:20.730205
2806 06:48:20.730302 Set Vref, RX VrefLevel [Byte0]: 66
2807 06:48:20.733569 [Byte1]: 66
2808 06:48:20.738383
2809 06:48:20.738497 Set Vref, RX VrefLevel [Byte0]: 67
2810 06:48:20.741471 [Byte1]: 67
2811 06:48:20.746086
2812 06:48:20.746190 Set Vref, RX VrefLevel [Byte0]: 68
2813 06:48:20.749719 [Byte1]: 68
2814 06:48:20.754347
2815 06:48:20.754478 Set Vref, RX VrefLevel [Byte0]: 69
2816 06:48:20.757589 [Byte1]: 69
2817 06:48:20.762196
2818 06:48:20.762325 Final RX Vref Byte 0 = 54 to rank0
2819 06:48:20.765374 Final RX Vref Byte 1 = 50 to rank0
2820 06:48:20.768914 Final RX Vref Byte 0 = 54 to rank1
2821 06:48:20.773137 Final RX Vref Byte 1 = 50 to rank1==
2822 06:48:20.775258 Dram Type= 6, Freq= 0, CH_0, rank 0
2823 06:48:20.778963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2824 06:48:20.782013 ==
2825 06:48:20.782137 DQS Delay:
2826 06:48:20.782242 DQS0 = 0, DQS1 = 0
2827 06:48:20.785301 DQM Delay:
2828 06:48:20.785417 DQM0 = 115, DQM1 = 104
2829 06:48:20.788766 DQ Delay:
2830 06:48:20.792182 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =112
2831 06:48:20.795853 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2832 06:48:20.799219 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2833 06:48:20.802230 DQ12 =112, DQ13 =108, DQ14 =118, DQ15 =114
2834 06:48:20.802345
2835 06:48:20.802444
2836 06:48:20.809051 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbeb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
2837 06:48:20.812593 CH0 RK0: MR19=303, MR18=FBEB
2838 06:48:20.818980 CH0_RK0: MR19=0x303, MR18=0xFBEB, DQSOSC=412, MR23=63, INC=38, DEC=25
2839 06:48:20.819124
2840 06:48:20.822348 ----->DramcWriteLeveling(PI) begin...
2841 06:48:20.822479 ==
2842 06:48:20.825949 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 06:48:20.828900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 06:48:20.828985 ==
2845 06:48:20.832303 Write leveling (Byte 0): 35 => 35
2846 06:48:20.835751 Write leveling (Byte 1): 31 => 31
2847 06:48:20.839514 DramcWriteLeveling(PI) end<-----
2848 06:48:20.839621
2849 06:48:20.839713 ==
2850 06:48:20.842837 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 06:48:20.846137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 06:48:20.846233 ==
2853 06:48:20.849498 [Gating] SW mode calibration
2854 06:48:20.855929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2855 06:48:20.862880 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2856 06:48:20.866023 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 06:48:20.869361 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2858 06:48:20.876258 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 06:48:20.880290 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 06:48:20.883307 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 06:48:20.889579 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 06:48:20.892914 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 06:48:20.896386 0 15 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (0 0)
2864 06:48:20.903386 1 0 0 | B1->B0 | 2d2d 2b2b | 1 0 | (1 0) (0 0)
2865 06:48:20.906916 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2866 06:48:20.910119 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 06:48:20.916427 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 06:48:20.919942 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 06:48:20.923329 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 06:48:20.926885 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2871 06:48:20.933272 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2872 06:48:20.936470 1 1 0 | B1->B0 | 3838 4343 | 1 0 | (0 0) (0 0)
2873 06:48:20.940064 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 06:48:20.947185 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 06:48:20.950150 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 06:48:20.953688 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 06:48:20.960423 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 06:48:20.963672 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 06:48:20.966719 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2880 06:48:20.973620 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2881 06:48:20.976714 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 06:48:20.980209 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 06:48:20.983906 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 06:48:20.990338 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 06:48:20.994115 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 06:48:20.997363 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 06:48:21.003935 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 06:48:21.007487 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 06:48:21.010662 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 06:48:21.017735 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 06:48:21.020604 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 06:48:21.024743 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 06:48:21.030418 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 06:48:21.033962 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 06:48:21.037122 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2896 06:48:21.043874 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2897 06:48:21.044007 Total UI for P1: 0, mck2ui 16
2898 06:48:21.047369 best dqsien dly found for B0: ( 1, 3, 28)
2899 06:48:21.053816 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 06:48:21.057766 Total UI for P1: 0, mck2ui 16
2901 06:48:21.060732 best dqsien dly found for B1: ( 1, 4, 0)
2902 06:48:21.063978 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2903 06:48:21.068108 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2904 06:48:21.068225
2905 06:48:21.070814 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2906 06:48:21.074375 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2907 06:48:21.077504 [Gating] SW calibration Done
2908 06:48:21.077616 ==
2909 06:48:21.080840 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 06:48:21.084725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 06:48:21.084836 ==
2912 06:48:21.087722 RX Vref Scan: 0
2913 06:48:21.087833
2914 06:48:21.087924 RX Vref 0 -> 0, step: 1
2915 06:48:21.088018
2916 06:48:21.091052 RX Delay -40 -> 252, step: 8
2917 06:48:21.094172 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2918 06:48:21.101336 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2919 06:48:21.104293 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2920 06:48:21.107839 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2921 06:48:21.111226 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2922 06:48:21.114209 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2923 06:48:21.118016 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2924 06:48:21.124464 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2925 06:48:21.127914 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2926 06:48:21.131276 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2927 06:48:21.134491 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2928 06:48:21.137749 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2929 06:48:21.144884 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2930 06:48:21.148269 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2931 06:48:21.151486 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2932 06:48:21.154380 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2933 06:48:21.154505 ==
2934 06:48:21.158347 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 06:48:21.164855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 06:48:21.164975 ==
2937 06:48:21.165086 DQS Delay:
2938 06:48:21.165180 DQS0 = 0, DQS1 = 0
2939 06:48:21.167981 DQM Delay:
2940 06:48:21.168096 DQM0 = 115, DQM1 = 105
2941 06:48:21.171680 DQ Delay:
2942 06:48:21.174686 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2943 06:48:21.178208 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2944 06:48:21.181534 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2945 06:48:21.185291 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2946 06:48:21.185375
2947 06:48:21.185446
2948 06:48:21.185507 ==
2949 06:48:21.188380 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 06:48:21.191449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 06:48:21.191556 ==
2952 06:48:21.191648
2953 06:48:21.191736
2954 06:48:21.195187 TX Vref Scan disable
2955 06:48:21.198271 == TX Byte 0 ==
2956 06:48:21.201969 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2957 06:48:21.204929 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2958 06:48:21.208425 == TX Byte 1 ==
2959 06:48:21.211815 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2960 06:48:21.215153 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2961 06:48:21.215282 ==
2962 06:48:21.218568 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 06:48:21.221768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 06:48:21.224950 ==
2965 06:48:21.236122 TX Vref=22, minBit 1, minWin=25, winSum=418
2966 06:48:21.238776 TX Vref=24, minBit 3, minWin=25, winSum=422
2967 06:48:21.241984 TX Vref=26, minBit 1, minWin=26, winSum=430
2968 06:48:21.245388 TX Vref=28, minBit 4, minWin=26, winSum=433
2969 06:48:21.248904 TX Vref=30, minBit 4, minWin=26, winSum=434
2970 06:48:21.252062 TX Vref=32, minBit 12, minWin=26, winSum=435
2971 06:48:21.258862 [TxChooseVref] Worse bit 12, Min win 26, Win sum 435, Final Vref 32
2972 06:48:21.258978
2973 06:48:21.262253 Final TX Range 1 Vref 32
2974 06:48:21.262362
2975 06:48:21.262472 ==
2976 06:48:21.265501 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 06:48:21.268925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 06:48:21.269038 ==
2979 06:48:21.269139
2980 06:48:21.269229
2981 06:48:21.272679 TX Vref Scan disable
2982 06:48:21.275354 == TX Byte 0 ==
2983 06:48:21.279252 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2984 06:48:21.282213 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2985 06:48:21.286309 == TX Byte 1 ==
2986 06:48:21.288863 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2987 06:48:21.292506 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2988 06:48:21.292597
2989 06:48:21.296081 [DATLAT]
2990 06:48:21.296190 Freq=1200, CH0 RK1
2991 06:48:21.296287
2992 06:48:21.298864 DATLAT Default: 0xd
2993 06:48:21.298972 0, 0xFFFF, sum = 0
2994 06:48:21.302280 1, 0xFFFF, sum = 0
2995 06:48:21.302389 2, 0xFFFF, sum = 0
2996 06:48:21.305651 3, 0xFFFF, sum = 0
2997 06:48:21.305734 4, 0xFFFF, sum = 0
2998 06:48:21.309117 5, 0xFFFF, sum = 0
2999 06:48:21.309203 6, 0xFFFF, sum = 0
3000 06:48:21.312728 7, 0xFFFF, sum = 0
3001 06:48:21.312811 8, 0xFFFF, sum = 0
3002 06:48:21.316069 9, 0xFFFF, sum = 0
3003 06:48:21.316196 10, 0xFFFF, sum = 0
3004 06:48:21.319100 11, 0xFFFF, sum = 0
3005 06:48:21.319213 12, 0x0, sum = 1
3006 06:48:21.322825 13, 0x0, sum = 2
3007 06:48:21.322959 14, 0x0, sum = 3
3008 06:48:21.325809 15, 0x0, sum = 4
3009 06:48:21.325925 best_step = 13
3010 06:48:21.326021
3011 06:48:21.326125 ==
3012 06:48:21.329264 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 06:48:21.335735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 06:48:21.335874 ==
3015 06:48:21.335978 RX Vref Scan: 0
3016 06:48:21.336070
3017 06:48:21.339749 RX Vref 0 -> 0, step: 1
3018 06:48:21.339866
3019 06:48:21.342986 RX Delay -21 -> 252, step: 4
3020 06:48:21.346816 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3021 06:48:21.349779 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3022 06:48:21.352469 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3023 06:48:21.359309 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3024 06:48:21.362964 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3025 06:48:21.366111 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3026 06:48:21.369420 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3027 06:48:21.372665 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3028 06:48:21.379367 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3029 06:48:21.382762 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3030 06:48:21.386257 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3031 06:48:21.389277 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3032 06:48:21.392612 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3033 06:48:21.399645 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3034 06:48:21.403143 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3035 06:48:21.406590 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3036 06:48:21.406727 ==
3037 06:48:21.409930 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 06:48:21.412947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 06:48:21.413084 ==
3040 06:48:21.416543 DQS Delay:
3041 06:48:21.416673 DQS0 = 0, DQS1 = 0
3042 06:48:21.416771 DQM Delay:
3043 06:48:21.419654 DQM0 = 114, DQM1 = 104
3044 06:48:21.419777 DQ Delay:
3045 06:48:21.422891 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3046 06:48:21.426387 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3047 06:48:21.429847 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3048 06:48:21.436314 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3049 06:48:21.436470
3050 06:48:21.436578
3051 06:48:21.443438 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3052 06:48:21.446162 CH0 RK1: MR19=403, MR18=3F4
3053 06:48:21.453487 CH0_RK1: MR19=0x403, MR18=0x3F4, DQSOSC=408, MR23=63, INC=39, DEC=26
3054 06:48:21.456295 [RxdqsGatingPostProcess] freq 1200
3055 06:48:21.460002 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3056 06:48:21.463426 best DQS0 dly(2T, 0.5T) = (0, 12)
3057 06:48:21.466414 best DQS1 dly(2T, 0.5T) = (0, 12)
3058 06:48:21.469807 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3059 06:48:21.473061 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3060 06:48:21.476743 best DQS0 dly(2T, 0.5T) = (0, 11)
3061 06:48:21.480109 best DQS1 dly(2T, 0.5T) = (0, 12)
3062 06:48:21.483580 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3063 06:48:21.487597 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3064 06:48:21.489884 Pre-setting of DQS Precalculation
3065 06:48:21.493497 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3066 06:48:21.493630 ==
3067 06:48:21.496954 Dram Type= 6, Freq= 0, CH_1, rank 0
3068 06:48:21.500033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 06:48:21.500169 ==
3070 06:48:21.506736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3071 06:48:21.513806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3072 06:48:21.521273 [CA 0] Center 38 (9~68) winsize 60
3073 06:48:21.524504 [CA 1] Center 38 (9~68) winsize 60
3074 06:48:21.527865 [CA 2] Center 35 (6~65) winsize 60
3075 06:48:21.531401 [CA 3] Center 34 (3~65) winsize 63
3076 06:48:21.534489 [CA 4] Center 34 (4~65) winsize 62
3077 06:48:21.538419 [CA 5] Center 34 (4~64) winsize 61
3078 06:48:21.538565
3079 06:48:21.541479 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3080 06:48:21.541606
3081 06:48:21.545180 [CATrainingPosCal] consider 1 rank data
3082 06:48:21.547883 u2DelayCellTimex100 = 270/100 ps
3083 06:48:21.551757 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3084 06:48:21.555298 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3085 06:48:21.558275 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3086 06:48:21.561377 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
3087 06:48:21.568391 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3088 06:48:21.571604 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3089 06:48:21.571757
3090 06:48:21.575208 CA PerBit enable=1, Macro0, CA PI delay=34
3091 06:48:21.575351
3092 06:48:21.578270 [CBTSetCACLKResult] CA Dly = 34
3093 06:48:21.578390 CS Dly: 6 (0~37)
3094 06:48:21.578513 ==
3095 06:48:21.582031 Dram Type= 6, Freq= 0, CH_1, rank 1
3096 06:48:21.585200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 06:48:21.588756 ==
3098 06:48:21.591684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3099 06:48:21.598804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3100 06:48:21.606663 [CA 0] Center 38 (8~68) winsize 61
3101 06:48:21.609851 [CA 1] Center 38 (9~68) winsize 60
3102 06:48:21.613434 [CA 2] Center 34 (4~65) winsize 62
3103 06:48:21.616825 [CA 3] Center 34 (4~65) winsize 62
3104 06:48:21.620372 [CA 4] Center 34 (4~65) winsize 62
3105 06:48:21.623444 [CA 5] Center 33 (3~63) winsize 61
3106 06:48:21.623589
3107 06:48:21.627360 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3108 06:48:21.627495
3109 06:48:21.630259 [CATrainingPosCal] consider 2 rank data
3110 06:48:21.633514 u2DelayCellTimex100 = 270/100 ps
3111 06:48:21.636719 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3112 06:48:21.639985 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3113 06:48:21.643351 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3114 06:48:21.650031 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3115 06:48:21.653862 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3116 06:48:21.656985 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3117 06:48:21.657164
3118 06:48:21.660445 CA PerBit enable=1, Macro0, CA PI delay=33
3119 06:48:21.660574
3120 06:48:21.663975 [CBTSetCACLKResult] CA Dly = 33
3121 06:48:21.664102 CS Dly: 8 (0~41)
3122 06:48:21.664198
3123 06:48:21.667963 ----->DramcWriteLeveling(PI) begin...
3124 06:48:21.668091 ==
3125 06:48:21.670785 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 06:48:21.677451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 06:48:21.677601 ==
3128 06:48:21.680712 Write leveling (Byte 0): 26 => 26
3129 06:48:21.680814 Write leveling (Byte 1): 30 => 30
3130 06:48:21.684265 DramcWriteLeveling(PI) end<-----
3131 06:48:21.684364
3132 06:48:21.684450 ==
3133 06:48:21.687508 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 06:48:21.694240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 06:48:21.694367 ==
3136 06:48:21.697545 [Gating] SW mode calibration
3137 06:48:21.704474 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3138 06:48:21.707585 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3139 06:48:21.714270 0 15 0 | B1->B0 | 2424 2525 | 1 1 | (0 0) (1 1)
3140 06:48:21.717689 0 15 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3141 06:48:21.721061 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 06:48:21.724337 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 06:48:21.731319 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 06:48:21.734624 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 06:48:21.738311 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 06:48:21.744528 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 0)
3147 06:48:21.747912 1 0 0 | B1->B0 | 2323 2323 | 1 1 | (1 0) (1 0)
3148 06:48:21.751343 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 06:48:21.758041 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 06:48:21.761617 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 06:48:21.764982 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 06:48:21.768039 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 06:48:21.775196 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 06:48:21.778376 1 0 28 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
3155 06:48:21.781781 1 1 0 | B1->B0 | 3d3d 2f2f | 0 0 | (0 0) (0 0)
3156 06:48:21.788061 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 06:48:21.791625 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 06:48:21.795148 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 06:48:21.801664 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 06:48:21.804989 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 06:48:21.809013 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 06:48:21.815110 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3163 06:48:21.818718 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3164 06:48:21.821727 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 06:48:21.825141 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 06:48:21.831908 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 06:48:21.835036 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 06:48:21.838610 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 06:48:21.845306 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 06:48:21.848964 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 06:48:21.851858 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 06:48:21.858503 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 06:48:21.862296 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 06:48:21.865342 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 06:48:21.871942 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 06:48:21.875013 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 06:48:21.878526 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 06:48:21.885665 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3179 06:48:21.888532 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3180 06:48:21.892214 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 06:48:21.895537 Total UI for P1: 0, mck2ui 16
3182 06:48:21.899103 best dqsien dly found for B0: ( 1, 3, 30)
3183 06:48:21.901920 Total UI for P1: 0, mck2ui 16
3184 06:48:21.905548 best dqsien dly found for B1: ( 1, 3, 30)
3185 06:48:21.909393 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3186 06:48:21.912698 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3187 06:48:21.912823
3188 06:48:21.915668 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3189 06:48:21.918815 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3190 06:48:21.922023 [Gating] SW calibration Done
3191 06:48:21.922123 ==
3192 06:48:21.925873 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 06:48:21.932815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 06:48:21.932951 ==
3195 06:48:21.933056 RX Vref Scan: 0
3196 06:48:21.933146
3197 06:48:21.935648 RX Vref 0 -> 0, step: 1
3198 06:48:21.935748
3199 06:48:21.938928 RX Delay -40 -> 252, step: 8
3200 06:48:21.942493 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3201 06:48:21.946005 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3202 06:48:21.949123 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3203 06:48:21.952419 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3204 06:48:21.959052 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3205 06:48:21.962039 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3206 06:48:21.965793 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3207 06:48:21.968812 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3208 06:48:21.972747 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3209 06:48:21.975876 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3210 06:48:21.982305 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3211 06:48:21.985733 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3212 06:48:21.989067 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3213 06:48:21.992414 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3214 06:48:21.995702 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3215 06:48:22.002928 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3216 06:48:22.003075 ==
3217 06:48:22.005630 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 06:48:22.009415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 06:48:22.009534 ==
3220 06:48:22.009633 DQS Delay:
3221 06:48:22.012788 DQS0 = 0, DQS1 = 0
3222 06:48:22.012892 DQM Delay:
3223 06:48:22.016225 DQM0 = 116, DQM1 = 108
3224 06:48:22.016334 DQ Delay:
3225 06:48:22.019172 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3226 06:48:22.023090 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3227 06:48:22.026490 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3228 06:48:22.029852 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3229 06:48:22.029967
3230 06:48:22.030067
3231 06:48:22.032881 ==
3232 06:48:22.032983 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 06:48:22.039981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 06:48:22.040105 ==
3235 06:48:22.040209
3236 06:48:22.040302
3237 06:48:22.040390 TX Vref Scan disable
3238 06:48:22.043463 == TX Byte 0 ==
3239 06:48:22.046464 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3240 06:48:22.049782 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3241 06:48:22.053884 == TX Byte 1 ==
3242 06:48:22.057022 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3243 06:48:22.060522 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3244 06:48:22.063700 ==
3245 06:48:22.063808 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 06:48:22.070090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 06:48:22.070224 ==
3248 06:48:22.081525 TX Vref=22, minBit 4, minWin=24, winSum=406
3249 06:48:22.085096 TX Vref=24, minBit 0, minWin=25, winSum=412
3250 06:48:22.088561 TX Vref=26, minBit 1, minWin=25, winSum=417
3251 06:48:22.091582 TX Vref=28, minBit 0, minWin=26, winSum=426
3252 06:48:22.094970 TX Vref=30, minBit 3, minWin=25, winSum=423
3253 06:48:22.098159 TX Vref=32, minBit 3, minWin=25, winSum=420
3254 06:48:22.104981 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
3255 06:48:22.105095
3256 06:48:22.108072 Final TX Range 1 Vref 28
3257 06:48:22.108154
3258 06:48:22.108237 ==
3259 06:48:22.111803 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 06:48:22.114716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 06:48:22.114827 ==
3262 06:48:22.114920
3263 06:48:22.115018
3264 06:48:22.118164 TX Vref Scan disable
3265 06:48:22.121761 == TX Byte 0 ==
3266 06:48:22.124885 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3267 06:48:22.128601 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3268 06:48:22.131886 == TX Byte 1 ==
3269 06:48:22.134988 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3270 06:48:22.138571 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3271 06:48:22.138656
3272 06:48:22.141887 [DATLAT]
3273 06:48:22.141988 Freq=1200, CH1 RK0
3274 06:48:22.142092
3275 06:48:22.145121 DATLAT Default: 0xd
3276 06:48:22.145225 0, 0xFFFF, sum = 0
3277 06:48:22.148168 1, 0xFFFF, sum = 0
3278 06:48:22.148275 2, 0xFFFF, sum = 0
3279 06:48:22.152135 3, 0xFFFF, sum = 0
3280 06:48:22.152241 4, 0xFFFF, sum = 0
3281 06:48:22.154890 5, 0xFFFF, sum = 0
3282 06:48:22.155005 6, 0xFFFF, sum = 0
3283 06:48:22.158676 7, 0xFFFF, sum = 0
3284 06:48:22.158796 8, 0xFFFF, sum = 0
3285 06:48:22.161695 9, 0xFFFF, sum = 0
3286 06:48:22.161800 10, 0xFFFF, sum = 0
3287 06:48:22.165096 11, 0xFFFF, sum = 0
3288 06:48:22.165200 12, 0x0, sum = 1
3289 06:48:22.168315 13, 0x0, sum = 2
3290 06:48:22.168419 14, 0x0, sum = 3
3291 06:48:22.171764 15, 0x0, sum = 4
3292 06:48:22.171875 best_step = 13
3293 06:48:22.171967
3294 06:48:22.172054 ==
3295 06:48:22.175083 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 06:48:22.181776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 06:48:22.181911 ==
3298 06:48:22.182018 RX Vref Scan: 1
3299 06:48:22.182107
3300 06:48:22.185299 Set Vref Range= 32 -> 127
3301 06:48:22.185404
3302 06:48:22.188598 RX Vref 32 -> 127, step: 1
3303 06:48:22.188702
3304 06:48:22.188794 RX Delay -21 -> 252, step: 4
3305 06:48:22.188888
3306 06:48:22.192097 Set Vref, RX VrefLevel [Byte0]: 32
3307 06:48:22.195203 [Byte1]: 32
3308 06:48:22.199523
3309 06:48:22.199640 Set Vref, RX VrefLevel [Byte0]: 33
3310 06:48:22.202952 [Byte1]: 33
3311 06:48:22.207729
3312 06:48:22.207820 Set Vref, RX VrefLevel [Byte0]: 34
3313 06:48:22.210630 [Byte1]: 34
3314 06:48:22.215184
3315 06:48:22.215305 Set Vref, RX VrefLevel [Byte0]: 35
3316 06:48:22.219022 [Byte1]: 35
3317 06:48:22.223216
3318 06:48:22.223303 Set Vref, RX VrefLevel [Byte0]: 36
3319 06:48:22.226638 [Byte1]: 36
3320 06:48:22.231233
3321 06:48:22.231319 Set Vref, RX VrefLevel [Byte0]: 37
3322 06:48:22.235814 [Byte1]: 37
3323 06:48:22.239065
3324 06:48:22.239145 Set Vref, RX VrefLevel [Byte0]: 38
3325 06:48:22.242367 [Byte1]: 38
3326 06:48:22.247054
3327 06:48:22.247153 Set Vref, RX VrefLevel [Byte0]: 39
3328 06:48:22.253330 [Byte1]: 39
3329 06:48:22.253442
3330 06:48:22.257017 Set Vref, RX VrefLevel [Byte0]: 40
3331 06:48:22.259951 [Byte1]: 40
3332 06:48:22.260066
3333 06:48:22.264017 Set Vref, RX VrefLevel [Byte0]: 41
3334 06:48:22.267115 [Byte1]: 41
3335 06:48:22.270703
3336 06:48:22.270809 Set Vref, RX VrefLevel [Byte0]: 42
3337 06:48:22.274219 [Byte1]: 42
3338 06:48:22.279148
3339 06:48:22.279239 Set Vref, RX VrefLevel [Byte0]: 43
3340 06:48:22.281857 [Byte1]: 43
3341 06:48:22.286943
3342 06:48:22.287029 Set Vref, RX VrefLevel [Byte0]: 44
3343 06:48:22.290130 [Byte1]: 44
3344 06:48:22.294472
3345 06:48:22.294553 Set Vref, RX VrefLevel [Byte0]: 45
3346 06:48:22.297654 [Byte1]: 45
3347 06:48:22.302315
3348 06:48:22.302435 Set Vref, RX VrefLevel [Byte0]: 46
3349 06:48:22.305910 [Byte1]: 46
3350 06:48:22.310597
3351 06:48:22.310724 Set Vref, RX VrefLevel [Byte0]: 47
3352 06:48:22.313922 [Byte1]: 47
3353 06:48:22.318380
3354 06:48:22.318494 Set Vref, RX VrefLevel [Byte0]: 48
3355 06:48:22.321553 [Byte1]: 48
3356 06:48:22.326304
3357 06:48:22.326439 Set Vref, RX VrefLevel [Byte0]: 49
3358 06:48:22.329373 [Byte1]: 49
3359 06:48:22.334043
3360 06:48:22.334161 Set Vref, RX VrefLevel [Byte0]: 50
3361 06:48:22.337559 [Byte1]: 50
3362 06:48:22.342135
3363 06:48:22.342257 Set Vref, RX VrefLevel [Byte0]: 51
3364 06:48:22.345859 [Byte1]: 51
3365 06:48:22.349768
3366 06:48:22.349886 Set Vref, RX VrefLevel [Byte0]: 52
3367 06:48:22.353281 [Byte1]: 52
3368 06:48:22.357713
3369 06:48:22.357812 Set Vref, RX VrefLevel [Byte0]: 53
3370 06:48:22.361103 [Byte1]: 53
3371 06:48:22.365626
3372 06:48:22.365755 Set Vref, RX VrefLevel [Byte0]: 54
3373 06:48:22.369350 [Byte1]: 54
3374 06:48:22.373909
3375 06:48:22.374039 Set Vref, RX VrefLevel [Byte0]: 55
3376 06:48:22.377479 [Byte1]: 55
3377 06:48:22.381969
3378 06:48:22.382068 Set Vref, RX VrefLevel [Byte0]: 56
3379 06:48:22.385249 [Byte1]: 56
3380 06:48:22.389620
3381 06:48:22.389746 Set Vref, RX VrefLevel [Byte0]: 57
3382 06:48:22.392625 [Byte1]: 57
3383 06:48:22.397331
3384 06:48:22.397428 Set Vref, RX VrefLevel [Byte0]: 58
3385 06:48:22.400759 [Byte1]: 58
3386 06:48:22.405759
3387 06:48:22.405857 Set Vref, RX VrefLevel [Byte0]: 59
3388 06:48:22.408793 [Byte1]: 59
3389 06:48:22.413344
3390 06:48:22.413464 Set Vref, RX VrefLevel [Byte0]: 60
3391 06:48:22.416677 [Byte1]: 60
3392 06:48:22.421074
3393 06:48:22.421198 Set Vref, RX VrefLevel [Byte0]: 61
3394 06:48:22.424525 [Byte1]: 61
3395 06:48:22.429654
3396 06:48:22.429752 Set Vref, RX VrefLevel [Byte0]: 62
3397 06:48:22.432891 [Byte1]: 62
3398 06:48:22.437082
3399 06:48:22.437172 Set Vref, RX VrefLevel [Byte0]: 63
3400 06:48:22.440842 [Byte1]: 63
3401 06:48:22.444795
3402 06:48:22.444889 Set Vref, RX VrefLevel [Byte0]: 64
3403 06:48:22.448451 [Byte1]: 64
3404 06:48:22.453363
3405 06:48:22.453480 Set Vref, RX VrefLevel [Byte0]: 65
3406 06:48:22.456512 [Byte1]: 65
3407 06:48:22.460741
3408 06:48:22.460875 Set Vref, RX VrefLevel [Byte0]: 66
3409 06:48:22.464021 [Byte1]: 66
3410 06:48:22.468927
3411 06:48:22.469049 Set Vref, RX VrefLevel [Byte0]: 67
3412 06:48:22.471877 [Byte1]: 67
3413 06:48:22.476864
3414 06:48:22.476970 Set Vref, RX VrefLevel [Byte0]: 68
3415 06:48:22.480026 [Byte1]: 68
3416 06:48:22.484535
3417 06:48:22.484625 Set Vref, RX VrefLevel [Byte0]: 69
3418 06:48:22.487978 [Byte1]: 69
3419 06:48:22.492607
3420 06:48:22.492713 Final RX Vref Byte 0 = 59 to rank0
3421 06:48:22.495954 Final RX Vref Byte 1 = 49 to rank0
3422 06:48:22.499601 Final RX Vref Byte 0 = 59 to rank1
3423 06:48:22.502375 Final RX Vref Byte 1 = 49 to rank1==
3424 06:48:22.505827 Dram Type= 6, Freq= 0, CH_1, rank 0
3425 06:48:22.512477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 06:48:22.512573 ==
3427 06:48:22.512639 DQS Delay:
3428 06:48:22.512699 DQS0 = 0, DQS1 = 0
3429 06:48:22.516250 DQM Delay:
3430 06:48:22.516357 DQM0 = 116, DQM1 = 108
3431 06:48:22.519327 DQ Delay:
3432 06:48:22.522712 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =116
3433 06:48:22.526274 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =114
3434 06:48:22.529204 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3435 06:48:22.532906 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3436 06:48:22.533015
3437 06:48:22.533108
3438 06:48:22.539319 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3439 06:48:22.543150 CH1 RK0: MR19=303, MR18=FDE1
3440 06:48:22.549320 CH1_RK0: MR19=0x303, MR18=0xFDE1, DQSOSC=411, MR23=63, INC=38, DEC=25
3441 06:48:22.549425
3442 06:48:22.553159 ----->DramcWriteLeveling(PI) begin...
3443 06:48:22.553256 ==
3444 06:48:22.556550 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 06:48:22.560146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 06:48:22.560268 ==
3447 06:48:22.563212 Write leveling (Byte 0): 27 => 27
3448 06:48:22.566824 Write leveling (Byte 1): 28 => 28
3449 06:48:22.570235 DramcWriteLeveling(PI) end<-----
3450 06:48:22.570341
3451 06:48:22.570436 ==
3452 06:48:22.573261 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 06:48:22.576726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 06:48:22.576818 ==
3455 06:48:22.579723 [Gating] SW mode calibration
3456 06:48:22.587163 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3457 06:48:22.593287 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3458 06:48:22.596662 0 15 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
3459 06:48:22.603379 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 06:48:22.606892 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 06:48:22.610051 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 06:48:22.613363 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 06:48:22.620267 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 06:48:22.623482 0 15 24 | B1->B0 | 3333 2727 | 0 0 | (0 0) (0 0)
3465 06:48:22.626723 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
3466 06:48:22.634092 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 06:48:22.637324 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 06:48:22.640274 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 06:48:22.646542 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 06:48:22.650312 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 06:48:22.653464 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 06:48:22.660643 1 0 24 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
3473 06:48:22.663976 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3474 06:48:22.667089 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 06:48:22.673584 1 1 4 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
3476 06:48:22.677031 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 06:48:22.679870 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 06:48:22.687071 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 06:48:22.689818 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3480 06:48:22.693209 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3481 06:48:22.700222 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3482 06:48:22.703552 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3483 06:48:22.706999 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 06:48:22.710199 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 06:48:22.716533 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 06:48:22.720089 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 06:48:22.723508 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 06:48:22.730033 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 06:48:22.733766 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 06:48:22.736953 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 06:48:22.743381 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 06:48:22.747077 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 06:48:22.750005 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 06:48:22.756848 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 06:48:22.760143 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3496 06:48:22.763489 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3497 06:48:22.770469 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3498 06:48:22.770595 Total UI for P1: 0, mck2ui 16
3499 06:48:22.776911 best dqsien dly found for B0: ( 1, 3, 22)
3500 06:48:22.779980 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 06:48:22.783600 Total UI for P1: 0, mck2ui 16
3502 06:48:22.787292 best dqsien dly found for B1: ( 1, 3, 26)
3503 06:48:22.790272 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3504 06:48:22.793384 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3505 06:48:22.793459
3506 06:48:22.796834 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3507 06:48:22.800020 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3508 06:48:22.803466 [Gating] SW calibration Done
3509 06:48:22.803549 ==
3510 06:48:22.807142 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 06:48:22.810170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 06:48:22.810272 ==
3513 06:48:22.813704 RX Vref Scan: 0
3514 06:48:22.813808
3515 06:48:22.817088 RX Vref 0 -> 0, step: 1
3516 06:48:22.817195
3517 06:48:22.817291 RX Delay -40 -> 252, step: 8
3518 06:48:22.823723 iDelay=192, Bit 0, Center 115 (40 ~ 191) 152
3519 06:48:22.826963 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3520 06:48:22.829971 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3521 06:48:22.833514 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3522 06:48:22.836645 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3523 06:48:22.843512 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3524 06:48:22.847065 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3525 06:48:22.850249 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3526 06:48:22.853984 iDelay=192, Bit 8, Center 99 (32 ~ 167) 136
3527 06:48:22.856980 iDelay=192, Bit 9, Center 99 (32 ~ 167) 136
3528 06:48:22.860386 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3529 06:48:22.866945 iDelay=192, Bit 11, Center 99 (32 ~ 167) 136
3530 06:48:22.870013 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3531 06:48:22.873642 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3532 06:48:22.876689 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3533 06:48:22.879977 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3534 06:48:22.883622 ==
3535 06:48:22.887326 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 06:48:22.890327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 06:48:22.890437 ==
3538 06:48:22.890536 DQS Delay:
3539 06:48:22.893619 DQS0 = 0, DQS1 = 0
3540 06:48:22.893701 DQM Delay:
3541 06:48:22.897075 DQM0 = 112, DQM1 = 110
3542 06:48:22.897176 DQ Delay:
3543 06:48:22.900322 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3544 06:48:22.903471 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3545 06:48:22.907051 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3546 06:48:22.910050 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3547 06:48:22.910155
3548 06:48:22.910250
3549 06:48:22.910339 ==
3550 06:48:22.913669 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 06:48:22.920403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 06:48:22.920513 ==
3553 06:48:22.920618
3554 06:48:22.920708
3555 06:48:22.920807 TX Vref Scan disable
3556 06:48:22.923766 == TX Byte 0 ==
3557 06:48:22.926856 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3558 06:48:22.930177 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3559 06:48:22.933632 == TX Byte 1 ==
3560 06:48:22.936638 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3561 06:48:22.940284 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3562 06:48:22.944146 ==
3563 06:48:22.946993 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 06:48:22.950172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 06:48:22.950277 ==
3566 06:48:22.961678 TX Vref=22, minBit 1, minWin=25, winSum=415
3567 06:48:22.964424 TX Vref=24, minBit 3, minWin=25, winSum=417
3568 06:48:22.968282 TX Vref=26, minBit 7, minWin=25, winSum=424
3569 06:48:22.971700 TX Vref=28, minBit 0, minWin=26, winSum=426
3570 06:48:22.975297 TX Vref=30, minBit 1, minWin=26, winSum=430
3571 06:48:22.978188 TX Vref=32, minBit 1, minWin=26, winSum=428
3572 06:48:22.984700 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3573 06:48:22.984829
3574 06:48:22.988407 Final TX Range 1 Vref 30
3575 06:48:22.988512
3576 06:48:22.988604 ==
3577 06:48:22.991923 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 06:48:22.995267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 06:48:22.995370 ==
3580 06:48:22.995463
3581 06:48:22.995536
3582 06:48:22.998277 TX Vref Scan disable
3583 06:48:23.001942 == TX Byte 0 ==
3584 06:48:23.004718 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3585 06:48:23.008441 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3586 06:48:23.011437 == TX Byte 1 ==
3587 06:48:23.014983 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3588 06:48:23.018359 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3589 06:48:23.018461
3590 06:48:23.021434 [DATLAT]
3591 06:48:23.021535 Freq=1200, CH1 RK1
3592 06:48:23.021601
3593 06:48:23.024942 DATLAT Default: 0xd
3594 06:48:23.025048 0, 0xFFFF, sum = 0
3595 06:48:23.028057 1, 0xFFFF, sum = 0
3596 06:48:23.028162 2, 0xFFFF, sum = 0
3597 06:48:23.031804 3, 0xFFFF, sum = 0
3598 06:48:23.031911 4, 0xFFFF, sum = 0
3599 06:48:23.034976 5, 0xFFFF, sum = 0
3600 06:48:23.035059 6, 0xFFFF, sum = 0
3601 06:48:23.038736 7, 0xFFFF, sum = 0
3602 06:48:23.038815 8, 0xFFFF, sum = 0
3603 06:48:23.041356 9, 0xFFFF, sum = 0
3604 06:48:23.041459 10, 0xFFFF, sum = 0
3605 06:48:23.045074 11, 0xFFFF, sum = 0
3606 06:48:23.045181 12, 0x0, sum = 1
3607 06:48:23.049011 13, 0x0, sum = 2
3608 06:48:23.049116 14, 0x0, sum = 3
3609 06:48:23.052155 15, 0x0, sum = 4
3610 06:48:23.052260 best_step = 13
3611 06:48:23.052352
3612 06:48:23.052444 ==
3613 06:48:23.054939 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 06:48:23.061798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 06:48:23.061922 ==
3616 06:48:23.062020 RX Vref Scan: 0
3617 06:48:23.062110
3618 06:48:23.065174 RX Vref 0 -> 0, step: 1
3619 06:48:23.065277
3620 06:48:23.068419 RX Delay -13 -> 252, step: 4
3621 06:48:23.071362 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3622 06:48:23.074905 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3623 06:48:23.082013 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3624 06:48:23.085242 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3625 06:48:23.088057 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3626 06:48:23.091528 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3627 06:48:23.095109 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3628 06:48:23.098218 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3629 06:48:23.105125 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3630 06:48:23.108272 iDelay=191, Bit 9, Center 96 (31 ~ 162) 132
3631 06:48:23.111902 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3632 06:48:23.114831 iDelay=191, Bit 11, Center 102 (39 ~ 166) 128
3633 06:48:23.118451 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3634 06:48:23.125141 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3635 06:48:23.128258 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3636 06:48:23.131485 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3637 06:48:23.131568 ==
3638 06:48:23.134700 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 06:48:23.138192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 06:48:23.138297 ==
3641 06:48:23.141589 DQS Delay:
3642 06:48:23.141695 DQS0 = 0, DQS1 = 0
3643 06:48:23.144816 DQM Delay:
3644 06:48:23.144928 DQM0 = 113, DQM1 = 109
3645 06:48:23.148457 DQ Delay:
3646 06:48:23.151585 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =112
3647 06:48:23.155235 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =110
3648 06:48:23.158662 DQ8 =96, DQ9 =96, DQ10 =110, DQ11 =102
3649 06:48:23.161463 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3650 06:48:23.161578
3651 06:48:23.161655
3652 06:48:23.168318 [DQSOSCAuto] RK1, (LSB)MR18= 0xf901, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3653 06:48:23.171744 CH1 RK1: MR19=304, MR18=F901
3654 06:48:23.178273 CH1_RK1: MR19=0x304, MR18=0xF901, DQSOSC=409, MR23=63, INC=39, DEC=26
3655 06:48:23.181978 [RxdqsGatingPostProcess] freq 1200
3656 06:48:23.188654 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3657 06:48:23.188777 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 06:48:23.191722 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 06:48:23.194916 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 06:48:23.198447 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 06:48:23.201474 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 06:48:23.204811 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 06:48:23.208619 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 06:48:23.211897 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 06:48:23.214616 Pre-setting of DQS Precalculation
3666 06:48:23.218272 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3667 06:48:23.228184 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3668 06:48:23.234838 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3669 06:48:23.234957
3670 06:48:23.235028
3671 06:48:23.238002 [Calibration Summary] 2400 Mbps
3672 06:48:23.238104 CH 0, Rank 0
3673 06:48:23.241281 SW Impedance : PASS
3674 06:48:23.241406 DUTY Scan : NO K
3675 06:48:23.244712 ZQ Calibration : PASS
3676 06:48:23.248396 Jitter Meter : NO K
3677 06:48:23.248543 CBT Training : PASS
3678 06:48:23.251338 Write leveling : PASS
3679 06:48:23.255082 RX DQS gating : PASS
3680 06:48:23.255219 RX DQ/DQS(RDDQC) : PASS
3681 06:48:23.258080 TX DQ/DQS : PASS
3682 06:48:23.261772 RX DATLAT : PASS
3683 06:48:23.261873 RX DQ/DQS(Engine): PASS
3684 06:48:23.265009 TX OE : NO K
3685 06:48:23.265113 All Pass.
3686 06:48:23.265207
3687 06:48:23.268094 CH 0, Rank 1
3688 06:48:23.268195 SW Impedance : PASS
3689 06:48:23.271843 DUTY Scan : NO K
3690 06:48:23.275567 ZQ Calibration : PASS
3691 06:48:23.275678 Jitter Meter : NO K
3692 06:48:23.278437 CBT Training : PASS
3693 06:48:23.278513 Write leveling : PASS
3694 06:48:23.281646 RX DQS gating : PASS
3695 06:48:23.284946 RX DQ/DQS(RDDQC) : PASS
3696 06:48:23.285065 TX DQ/DQS : PASS
3697 06:48:23.287847 RX DATLAT : PASS
3698 06:48:23.291704 RX DQ/DQS(Engine): PASS
3699 06:48:23.291813 TX OE : NO K
3700 06:48:23.294748 All Pass.
3701 06:48:23.294886
3702 06:48:23.295011 CH 1, Rank 0
3703 06:48:23.298329 SW Impedance : PASS
3704 06:48:23.298442 DUTY Scan : NO K
3705 06:48:23.301946 ZQ Calibration : PASS
3706 06:48:23.304855 Jitter Meter : NO K
3707 06:48:23.304985 CBT Training : PASS
3708 06:48:23.308123 Write leveling : PASS
3709 06:48:23.312138 RX DQS gating : PASS
3710 06:48:23.312285 RX DQ/DQS(RDDQC) : PASS
3711 06:48:23.315021 TX DQ/DQS : PASS
3712 06:48:23.315119 RX DATLAT : PASS
3713 06:48:23.318818 RX DQ/DQS(Engine): PASS
3714 06:48:23.321627 TX OE : NO K
3715 06:48:23.321753 All Pass.
3716 06:48:23.321848
3717 06:48:23.321939 CH 1, Rank 1
3718 06:48:23.324725 SW Impedance : PASS
3719 06:48:23.328363 DUTY Scan : NO K
3720 06:48:23.328497 ZQ Calibration : PASS
3721 06:48:23.331919 Jitter Meter : NO K
3722 06:48:23.335065 CBT Training : PASS
3723 06:48:23.335192 Write leveling : PASS
3724 06:48:23.338115 RX DQS gating : PASS
3725 06:48:23.341807 RX DQ/DQS(RDDQC) : PASS
3726 06:48:23.341930 TX DQ/DQS : PASS
3727 06:48:23.345111 RX DATLAT : PASS
3728 06:48:23.348046 RX DQ/DQS(Engine): PASS
3729 06:48:23.348172 TX OE : NO K
3730 06:48:23.352037 All Pass.
3731 06:48:23.352165
3732 06:48:23.352264 DramC Write-DBI off
3733 06:48:23.355254 PER_BANK_REFRESH: Hybrid Mode
3734 06:48:23.355365 TX_TRACKING: ON
3735 06:48:23.364705 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3736 06:48:23.368572 [FAST_K] Save calibration result to emmc
3737 06:48:23.371417 dramc_set_vcore_voltage set vcore to 650000
3738 06:48:23.374629 Read voltage for 600, 5
3739 06:48:23.374729 Vio18 = 0
3740 06:48:23.378439 Vcore = 650000
3741 06:48:23.378522 Vdram = 0
3742 06:48:23.378591 Vddq = 0
3743 06:48:23.378672 Vmddr = 0
3744 06:48:23.385259 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3745 06:48:23.391552 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3746 06:48:23.391679 MEM_TYPE=3, freq_sel=19
3747 06:48:23.395147 sv_algorithm_assistance_LP4_1600
3748 06:48:23.398053 ============ PULL DRAM RESETB DOWN ============
3749 06:48:23.404761 ========== PULL DRAM RESETB DOWN end =========
3750 06:48:23.408055 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3751 06:48:23.411457 ===================================
3752 06:48:23.415180 LPDDR4 DRAM CONFIGURATION
3753 06:48:23.418313 ===================================
3754 06:48:23.418453 EX_ROW_EN[0] = 0x0
3755 06:48:23.421435 EX_ROW_EN[1] = 0x0
3756 06:48:23.421549 LP4Y_EN = 0x0
3757 06:48:23.424821 WORK_FSP = 0x0
3758 06:48:23.424943 WL = 0x2
3759 06:48:23.428219 RL = 0x2
3760 06:48:23.428302 BL = 0x2
3761 06:48:23.431332 RPST = 0x0
3762 06:48:23.431418 RD_PRE = 0x0
3763 06:48:23.434719 WR_PRE = 0x1
3764 06:48:23.438430 WR_PST = 0x0
3765 06:48:23.438545 DBI_WR = 0x0
3766 06:48:23.441733 DBI_RD = 0x0
3767 06:48:23.441848 OTF = 0x1
3768 06:48:23.444967 ===================================
3769 06:48:23.448344 ===================================
3770 06:48:23.448439 ANA top config
3771 06:48:23.452748 ===================================
3772 06:48:23.455126 DLL_ASYNC_EN = 0
3773 06:48:23.458333 ALL_SLAVE_EN = 1
3774 06:48:23.461547 NEW_RANK_MODE = 1
3775 06:48:23.465170 DLL_IDLE_MODE = 1
3776 06:48:23.465307 LP45_APHY_COMB_EN = 1
3777 06:48:23.468840 TX_ODT_DIS = 1
3778 06:48:23.471770 NEW_8X_MODE = 1
3779 06:48:23.475026 ===================================
3780 06:48:23.478550 ===================================
3781 06:48:23.481602 data_rate = 1200
3782 06:48:23.484966 CKR = 1
3783 06:48:23.485098 DQ_P2S_RATIO = 8
3784 06:48:23.488961 ===================================
3785 06:48:23.492282 CA_P2S_RATIO = 8
3786 06:48:23.495321 DQ_CA_OPEN = 0
3787 06:48:23.498624 DQ_SEMI_OPEN = 0
3788 06:48:23.501731 CA_SEMI_OPEN = 0
3789 06:48:23.501820 CA_FULL_RATE = 0
3790 06:48:23.505008 DQ_CKDIV4_EN = 1
3791 06:48:23.508475 CA_CKDIV4_EN = 1
3792 06:48:23.511799 CA_PREDIV_EN = 0
3793 06:48:23.514888 PH8_DLY = 0
3794 06:48:23.518295 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3795 06:48:23.518384 DQ_AAMCK_DIV = 4
3796 06:48:23.521881 CA_AAMCK_DIV = 4
3797 06:48:23.525206 CA_ADMCK_DIV = 4
3798 06:48:23.528192 DQ_TRACK_CA_EN = 0
3799 06:48:23.531751 CA_PICK = 600
3800 06:48:23.535154 CA_MCKIO = 600
3801 06:48:23.538420 MCKIO_SEMI = 0
3802 06:48:23.538508 PLL_FREQ = 2288
3803 06:48:23.541597 DQ_UI_PI_RATIO = 32
3804 06:48:23.544976 CA_UI_PI_RATIO = 0
3805 06:48:23.548380 ===================================
3806 06:48:23.551554 ===================================
3807 06:48:23.555164 memory_type:LPDDR4
3808 06:48:23.555294 GP_NUM : 10
3809 06:48:23.558693 SRAM_EN : 1
3810 06:48:23.561679 MD32_EN : 0
3811 06:48:23.564797 ===================================
3812 06:48:23.564938 [ANA_INIT] >>>>>>>>>>>>>>
3813 06:48:23.568305 <<<<<< [CONFIGURE PHASE]: ANA_TX
3814 06:48:23.571818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3815 06:48:23.574992 ===================================
3816 06:48:23.578480 data_rate = 1200,PCW = 0X5800
3817 06:48:23.581604 ===================================
3818 06:48:23.584780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3819 06:48:23.591985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 06:48:23.595442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 06:48:23.602006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3822 06:48:23.605851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3823 06:48:23.608370 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3824 06:48:23.608484 [ANA_INIT] flow start
3825 06:48:23.611721 [ANA_INIT] PLL >>>>>>>>
3826 06:48:23.614959 [ANA_INIT] PLL <<<<<<<<
3827 06:48:23.615074 [ANA_INIT] MIDPI >>>>>>>>
3828 06:48:23.618538 [ANA_INIT] MIDPI <<<<<<<<
3829 06:48:23.621499 [ANA_INIT] DLL >>>>>>>>
3830 06:48:23.621625 [ANA_INIT] flow end
3831 06:48:23.628604 ============ LP4 DIFF to SE enter ============
3832 06:48:23.632250 ============ LP4 DIFF to SE exit ============
3833 06:48:23.635614 [ANA_INIT] <<<<<<<<<<<<<
3834 06:48:23.638141 [Flow] Enable top DCM control >>>>>
3835 06:48:23.641545 [Flow] Enable top DCM control <<<<<
3836 06:48:23.641639 Enable DLL master slave shuffle
3837 06:48:23.648262 ==============================================================
3838 06:48:23.651716 Gating Mode config
3839 06:48:23.654911 ==============================================================
3840 06:48:23.658202 Config description:
3841 06:48:23.668931 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3842 06:48:23.675306 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3843 06:48:23.678670 SELPH_MODE 0: By rank 1: By Phase
3844 06:48:23.684707 ==============================================================
3845 06:48:23.688351 GAT_TRACK_EN = 1
3846 06:48:23.691510 RX_GATING_MODE = 2
3847 06:48:23.695023 RX_GATING_TRACK_MODE = 2
3848 06:48:23.698236 SELPH_MODE = 1
3849 06:48:23.698324 PICG_EARLY_EN = 1
3850 06:48:23.701455 VALID_LAT_VALUE = 1
3851 06:48:23.708433 ==============================================================
3852 06:48:23.712036 Enter into Gating configuration >>>>
3853 06:48:23.714846 Exit from Gating configuration <<<<
3854 06:48:23.718220 Enter into DVFS_PRE_config >>>>>
3855 06:48:23.728073 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3856 06:48:23.731550 Exit from DVFS_PRE_config <<<<<
3857 06:48:23.734871 Enter into PICG configuration >>>>
3858 06:48:23.738070 Exit from PICG configuration <<<<
3859 06:48:23.741848 [RX_INPUT] configuration >>>>>
3860 06:48:23.744811 [RX_INPUT] configuration <<<<<
3861 06:48:23.748459 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3862 06:48:23.754772 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3863 06:48:23.762067 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3864 06:48:23.768598 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3865 06:48:23.772128 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 06:48:23.778839 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 06:48:23.782235 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3868 06:48:23.788831 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3869 06:48:23.791629 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3870 06:48:23.795088 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3871 06:48:23.798719 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3872 06:48:23.805115 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 06:48:23.808549 ===================================
3874 06:48:23.808709 LPDDR4 DRAM CONFIGURATION
3875 06:48:23.811974 ===================================
3876 06:48:23.815070 EX_ROW_EN[0] = 0x0
3877 06:48:23.818584 EX_ROW_EN[1] = 0x0
3878 06:48:23.818732 LP4Y_EN = 0x0
3879 06:48:23.821793 WORK_FSP = 0x0
3880 06:48:23.821920 WL = 0x2
3881 06:48:23.825159 RL = 0x2
3882 06:48:23.825304 BL = 0x2
3883 06:48:23.828748 RPST = 0x0
3884 06:48:23.828882 RD_PRE = 0x0
3885 06:48:23.832498 WR_PRE = 0x1
3886 06:48:23.832689 WR_PST = 0x0
3887 06:48:23.835364 DBI_WR = 0x0
3888 06:48:23.835528 DBI_RD = 0x0
3889 06:48:23.838353 OTF = 0x1
3890 06:48:23.842006 ===================================
3891 06:48:23.845709 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3892 06:48:23.848228 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3893 06:48:23.855356 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 06:48:23.858328 ===================================
3895 06:48:23.858457 LPDDR4 DRAM CONFIGURATION
3896 06:48:23.861785 ===================================
3897 06:48:23.865467 EX_ROW_EN[0] = 0x10
3898 06:48:23.865558 EX_ROW_EN[1] = 0x0
3899 06:48:23.868610 LP4Y_EN = 0x0
3900 06:48:23.868727 WORK_FSP = 0x0
3901 06:48:23.871945 WL = 0x2
3902 06:48:23.872071 RL = 0x2
3903 06:48:23.874978 BL = 0x2
3904 06:48:23.878703 RPST = 0x0
3905 06:48:23.878789 RD_PRE = 0x0
3906 06:48:23.881718 WR_PRE = 0x1
3907 06:48:23.881833 WR_PST = 0x0
3908 06:48:23.885694 DBI_WR = 0x0
3909 06:48:23.885804 DBI_RD = 0x0
3910 06:48:23.888764 OTF = 0x1
3911 06:48:23.892203 ===================================
3912 06:48:23.895412 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3913 06:48:23.900631 nWR fixed to 30
3914 06:48:23.903909 [ModeRegInit_LP4] CH0 RK0
3915 06:48:23.904077 [ModeRegInit_LP4] CH0 RK1
3916 06:48:23.907373 [ModeRegInit_LP4] CH1 RK0
3917 06:48:23.910723 [ModeRegInit_LP4] CH1 RK1
3918 06:48:23.910897 match AC timing 17
3919 06:48:23.917405 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3920 06:48:23.920808 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3921 06:48:23.923984 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3922 06:48:23.930820 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3923 06:48:23.934290 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3924 06:48:23.934456 ==
3925 06:48:23.937274 Dram Type= 6, Freq= 0, CH_0, rank 0
3926 06:48:23.940454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 06:48:23.940593 ==
3928 06:48:23.947122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 06:48:23.954046 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3930 06:48:23.957084 [CA 0] Center 36 (6~67) winsize 62
3931 06:48:23.960528 [CA 1] Center 36 (6~66) winsize 61
3932 06:48:23.964310 [CA 2] Center 34 (4~64) winsize 61
3933 06:48:23.967108 [CA 3] Center 34 (4~64) winsize 61
3934 06:48:23.970873 [CA 4] Center 33 (3~64) winsize 62
3935 06:48:23.974290 [CA 5] Center 33 (3~64) winsize 62
3936 06:48:23.974430
3937 06:48:23.977162 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3938 06:48:23.977277
3939 06:48:23.980811 [CATrainingPosCal] consider 1 rank data
3940 06:48:23.984117 u2DelayCellTimex100 = 270/100 ps
3941 06:48:23.987509 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3942 06:48:23.990704 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3943 06:48:23.994429 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3944 06:48:23.997635 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3945 06:48:24.000679 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3946 06:48:24.004192 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3947 06:48:24.004318
3948 06:48:24.007653 CA PerBit enable=1, Macro0, CA PI delay=33
3949 06:48:24.010658
3950 06:48:24.010779 [CBTSetCACLKResult] CA Dly = 33
3951 06:48:24.014096 CS Dly: 3 (0~34)
3952 06:48:24.014260 ==
3953 06:48:24.017686 Dram Type= 6, Freq= 0, CH_0, rank 1
3954 06:48:24.020532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 06:48:24.020656 ==
3956 06:48:24.027695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 06:48:24.034743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3958 06:48:24.037100 [CA 0] Center 36 (6~66) winsize 61
3959 06:48:24.041153 [CA 1] Center 36 (6~66) winsize 61
3960 06:48:24.044032 [CA 2] Center 34 (4~65) winsize 62
3961 06:48:24.047212 [CA 3] Center 34 (4~65) winsize 62
3962 06:48:24.050883 [CA 4] Center 33 (3~64) winsize 62
3963 06:48:24.054127 [CA 5] Center 33 (3~64) winsize 62
3964 06:48:24.054269
3965 06:48:24.057540 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3966 06:48:24.057669
3967 06:48:24.060625 [CATrainingPosCal] consider 2 rank data
3968 06:48:24.064256 u2DelayCellTimex100 = 270/100 ps
3969 06:48:24.067387 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3970 06:48:24.070898 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3971 06:48:24.074311 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3972 06:48:24.077331 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3973 06:48:24.080758 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 06:48:24.084893 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3975 06:48:24.085012
3976 06:48:24.090811 CA PerBit enable=1, Macro0, CA PI delay=33
3977 06:48:24.090902
3978 06:48:24.090973 [CBTSetCACLKResult] CA Dly = 33
3979 06:48:24.094286 CS Dly: 4 (0~36)
3980 06:48:24.094384
3981 06:48:24.097702 ----->DramcWriteLeveling(PI) begin...
3982 06:48:24.097795 ==
3983 06:48:24.100528 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 06:48:24.104336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 06:48:24.104449 ==
3986 06:48:24.107724 Write leveling (Byte 0): 32 => 32
3987 06:48:24.110668 Write leveling (Byte 1): 28 => 28
3988 06:48:24.114318 DramcWriteLeveling(PI) end<-----
3989 06:48:24.114435
3990 06:48:24.114529 ==
3991 06:48:24.117295 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 06:48:24.120690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 06:48:24.124235 ==
3994 06:48:24.124350 [Gating] SW mode calibration
3995 06:48:24.130736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3996 06:48:24.137865 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3997 06:48:24.141078 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 06:48:24.147554 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 06:48:24.151253 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 06:48:24.154160 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 06:48:24.161617 0 9 16 | B1->B0 | 3131 2d2d | 0 1 | (0 1) (1 0)
4002 06:48:24.164560 0 9 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4003 06:48:24.168070 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 06:48:24.170748 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 06:48:24.177607 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 06:48:24.180760 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 06:48:24.184318 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 06:48:24.190761 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 06:48:24.194546 0 10 16 | B1->B0 | 3232 3b3b | 0 0 | (0 0) (0 0)
4010 06:48:24.197430 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4011 06:48:24.204131 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 06:48:24.207634 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 06:48:24.210861 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 06:48:24.217410 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 06:48:24.220765 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 06:48:24.224130 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4017 06:48:24.231251 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4018 06:48:24.234321 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 06:48:24.237670 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 06:48:24.244324 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 06:48:24.247509 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 06:48:24.251053 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 06:48:24.254509 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 06:48:24.261047 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 06:48:24.264134 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 06:48:24.267499 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 06:48:24.274125 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 06:48:24.277709 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 06:48:24.280734 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 06:48:24.287587 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 06:48:24.291175 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 06:48:24.294508 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 06:48:24.300828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4034 06:48:24.304480 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 06:48:24.307897 Total UI for P1: 0, mck2ui 16
4036 06:48:24.310893 best dqsien dly found for B0: ( 0, 13, 16)
4037 06:48:24.314162 Total UI for P1: 0, mck2ui 16
4038 06:48:24.317700 best dqsien dly found for B1: ( 0, 13, 16)
4039 06:48:24.321383 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4040 06:48:24.324454 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4041 06:48:24.324567
4042 06:48:24.327564 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4043 06:48:24.331840 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4044 06:48:24.334514 [Gating] SW calibration Done
4045 06:48:24.334625 ==
4046 06:48:24.338379 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 06:48:24.340941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 06:48:24.341018 ==
4049 06:48:24.344274 RX Vref Scan: 0
4050 06:48:24.344356
4051 06:48:24.347843 RX Vref 0 -> 0, step: 1
4052 06:48:24.347937
4053 06:48:24.351233 RX Delay -230 -> 252, step: 16
4054 06:48:24.354485 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4055 06:48:24.357908 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4056 06:48:24.361726 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4057 06:48:24.364465 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4058 06:48:24.370919 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4059 06:48:24.374608 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4060 06:48:24.377898 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4061 06:48:24.381070 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4062 06:48:24.384463 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4063 06:48:24.390980 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4064 06:48:24.394905 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4065 06:48:24.397707 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4066 06:48:24.400930 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4067 06:48:24.407614 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4068 06:48:24.410971 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4069 06:48:24.414672 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4070 06:48:24.414765 ==
4071 06:48:24.418121 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 06:48:24.421159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 06:48:24.424477 ==
4074 06:48:24.424572 DQS Delay:
4075 06:48:24.424640 DQS0 = 0, DQS1 = 0
4076 06:48:24.428056 DQM Delay:
4077 06:48:24.428144 DQM0 = 42, DQM1 = 36
4078 06:48:24.431614 DQ Delay:
4079 06:48:24.434362 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4080 06:48:24.434472 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4081 06:48:24.437605 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4082 06:48:24.441313 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4083 06:48:24.441395
4084 06:48:24.444666
4085 06:48:24.444749 ==
4086 06:48:24.447921 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 06:48:24.451378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 06:48:24.451460 ==
4089 06:48:24.451533
4090 06:48:24.451601
4091 06:48:24.454714 TX Vref Scan disable
4092 06:48:24.454814 == TX Byte 0 ==
4093 06:48:24.461362 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4094 06:48:24.465001 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4095 06:48:24.465135 == TX Byte 1 ==
4096 06:48:24.471197 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4097 06:48:24.474414 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4098 06:48:24.474518 ==
4099 06:48:24.477809 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 06:48:24.481203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 06:48:24.481306 ==
4102 06:48:24.481374
4103 06:48:24.481434
4104 06:48:24.484358 TX Vref Scan disable
4105 06:48:24.488113 == TX Byte 0 ==
4106 06:48:24.491056 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4107 06:48:24.494706 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4108 06:48:24.498391 == TX Byte 1 ==
4109 06:48:24.501250 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4110 06:48:24.504536 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4111 06:48:24.504627
4112 06:48:24.507648 [DATLAT]
4113 06:48:24.507742 Freq=600, CH0 RK0
4114 06:48:24.507808
4115 06:48:24.511198 DATLAT Default: 0x9
4116 06:48:24.511279 0, 0xFFFF, sum = 0
4117 06:48:24.514957 1, 0xFFFF, sum = 0
4118 06:48:24.515064 2, 0xFFFF, sum = 0
4119 06:48:24.517838 3, 0xFFFF, sum = 0
4120 06:48:24.517942 4, 0xFFFF, sum = 0
4121 06:48:24.521723 5, 0xFFFF, sum = 0
4122 06:48:24.521832 6, 0xFFFF, sum = 0
4123 06:48:24.524660 7, 0xFFFF, sum = 0
4124 06:48:24.524743 8, 0x0, sum = 1
4125 06:48:24.528170 9, 0x0, sum = 2
4126 06:48:24.528260 10, 0x0, sum = 3
4127 06:48:24.531580 11, 0x0, sum = 4
4128 06:48:24.531664 best_step = 9
4129 06:48:24.531728
4130 06:48:24.531788 ==
4131 06:48:24.534936 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 06:48:24.538049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 06:48:24.538135 ==
4134 06:48:24.541691 RX Vref Scan: 1
4135 06:48:24.541779
4136 06:48:24.544625 RX Vref 0 -> 0, step: 1
4137 06:48:24.544707
4138 06:48:24.544771 RX Delay -179 -> 252, step: 8
4139 06:48:24.547996
4140 06:48:24.548078 Set Vref, RX VrefLevel [Byte0]: 54
4141 06:48:24.551365 [Byte1]: 50
4142 06:48:24.556321
4143 06:48:24.556411 Final RX Vref Byte 0 = 54 to rank0
4144 06:48:24.559932 Final RX Vref Byte 1 = 50 to rank0
4145 06:48:24.562834 Final RX Vref Byte 0 = 54 to rank1
4146 06:48:24.566753 Final RX Vref Byte 1 = 50 to rank1==
4147 06:48:24.569525 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 06:48:24.576169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 06:48:24.576284 ==
4150 06:48:24.576355 DQS Delay:
4151 06:48:24.576417 DQS0 = 0, DQS1 = 0
4152 06:48:24.579860 DQM Delay:
4153 06:48:24.579951 DQM0 = 42, DQM1 = 33
4154 06:48:24.582761 DQ Delay:
4155 06:48:24.585909 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4156 06:48:24.585988 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4157 06:48:24.589859 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4158 06:48:24.596161 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4159 06:48:24.596253
4160 06:48:24.596329
4161 06:48:24.602635 [DQSOSCAuto] RK0, (LSB)MR18= 0x4322, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4162 06:48:24.606117 CH0 RK0: MR19=808, MR18=4322
4163 06:48:24.612870 CH0_RK0: MR19=0x808, MR18=0x4322, DQSOSC=397, MR23=63, INC=166, DEC=110
4164 06:48:24.612971
4165 06:48:24.616328 ----->DramcWriteLeveling(PI) begin...
4166 06:48:24.616421 ==
4167 06:48:24.619298 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 06:48:24.623080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 06:48:24.623201 ==
4170 06:48:24.626140 Write leveling (Byte 0): 31 => 31
4171 06:48:24.629877 Write leveling (Byte 1): 29 => 29
4172 06:48:24.632869 DramcWriteLeveling(PI) end<-----
4173 06:48:24.632958
4174 06:48:24.633043 ==
4175 06:48:24.636478 Dram Type= 6, Freq= 0, CH_0, rank 1
4176 06:48:24.639144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 06:48:24.639234 ==
4178 06:48:24.642793 [Gating] SW mode calibration
4179 06:48:24.649455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4180 06:48:24.655872 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4181 06:48:24.659208 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 06:48:24.663106 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 06:48:24.669447 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 06:48:24.672954 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 1)
4185 06:48:24.676494 0 9 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
4186 06:48:24.682673 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 06:48:24.686012 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 06:48:24.689733 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 06:48:24.696042 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 06:48:24.699961 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 06:48:24.702870 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 06:48:24.710036 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
4193 06:48:24.713285 0 10 16 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
4194 06:48:24.716189 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 06:48:24.723064 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 06:48:24.726174 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 06:48:24.729619 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 06:48:24.732741 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 06:48:24.739497 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 06:48:24.743159 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 06:48:24.746085 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4202 06:48:24.752973 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 06:48:24.756291 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 06:48:24.759855 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 06:48:24.766728 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 06:48:24.769996 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 06:48:24.772805 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 06:48:24.779654 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 06:48:24.782777 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 06:48:24.786303 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 06:48:24.793294 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 06:48:24.796175 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 06:48:24.800298 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 06:48:24.803202 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 06:48:24.809805 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 06:48:24.813389 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4217 06:48:24.817015 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4218 06:48:24.819769 Total UI for P1: 0, mck2ui 16
4219 06:48:24.823576 best dqsien dly found for B0: ( 0, 13, 12)
4220 06:48:24.829769 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 06:48:24.829870 Total UI for P1: 0, mck2ui 16
4222 06:48:24.837114 best dqsien dly found for B1: ( 0, 13, 16)
4223 06:48:24.840044 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4224 06:48:24.843606 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4225 06:48:24.843692
4226 06:48:24.846611 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4227 06:48:24.850247 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4228 06:48:24.853825 [Gating] SW calibration Done
4229 06:48:24.853909 ==
4230 06:48:24.856418 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 06:48:24.860283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 06:48:24.860370 ==
4233 06:48:24.863381 RX Vref Scan: 0
4234 06:48:24.863490
4235 06:48:24.863589 RX Vref 0 -> 0, step: 1
4236 06:48:24.863699
4237 06:48:24.866958 RX Delay -230 -> 252, step: 16
4238 06:48:24.873181 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4239 06:48:24.876390 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4240 06:48:24.880123 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4241 06:48:24.883624 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4242 06:48:24.887412 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4243 06:48:24.893397 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4244 06:48:24.896804 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4245 06:48:24.900211 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4246 06:48:24.903342 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4247 06:48:24.906764 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4248 06:48:24.913513 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4249 06:48:24.916475 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4250 06:48:24.919740 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4251 06:48:24.923341 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4252 06:48:24.929889 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4253 06:48:24.933054 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4254 06:48:24.933144 ==
4255 06:48:24.937165 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 06:48:24.940015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 06:48:24.940129 ==
4258 06:48:24.943087 DQS Delay:
4259 06:48:24.943171 DQS0 = 0, DQS1 = 0
4260 06:48:24.943237 DQM Delay:
4261 06:48:24.946506 DQM0 = 43, DQM1 = 32
4262 06:48:24.946589 DQ Delay:
4263 06:48:24.950047 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4264 06:48:24.953758 DQ4 =49, DQ5 =25, DQ6 =57, DQ7 =57
4265 06:48:24.956885 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4266 06:48:24.960061 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4267 06:48:24.960144
4268 06:48:24.960216
4269 06:48:24.960286 ==
4270 06:48:24.963418 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 06:48:24.970232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 06:48:24.970336 ==
4273 06:48:24.970413
4274 06:48:24.970484
4275 06:48:24.970546 TX Vref Scan disable
4276 06:48:24.973329 == TX Byte 0 ==
4277 06:48:24.977238 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4278 06:48:24.980129 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4279 06:48:24.983748 == TX Byte 1 ==
4280 06:48:24.986646 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4281 06:48:24.990206 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4282 06:48:24.993819 ==
4283 06:48:24.996782 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 06:48:25.000122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 06:48:25.000205 ==
4286 06:48:25.000270
4287 06:48:25.000330
4288 06:48:25.003670 TX Vref Scan disable
4289 06:48:25.003743 == TX Byte 0 ==
4290 06:48:25.010387 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4291 06:48:25.013436 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4292 06:48:25.013515 == TX Byte 1 ==
4293 06:48:25.020316 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4294 06:48:25.023849 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4295 06:48:25.023934
4296 06:48:25.024000 [DATLAT]
4297 06:48:25.026806 Freq=600, CH0 RK1
4298 06:48:25.026888
4299 06:48:25.026953 DATLAT Default: 0x9
4300 06:48:25.030622 0, 0xFFFF, sum = 0
4301 06:48:25.030711 1, 0xFFFF, sum = 0
4302 06:48:25.033686 2, 0xFFFF, sum = 0
4303 06:48:25.033759 3, 0xFFFF, sum = 0
4304 06:48:25.036787 4, 0xFFFF, sum = 0
4305 06:48:25.036860 5, 0xFFFF, sum = 0
4306 06:48:25.040173 6, 0xFFFF, sum = 0
4307 06:48:25.043688 7, 0xFFFF, sum = 0
4308 06:48:25.043776 8, 0x0, sum = 1
4309 06:48:25.043842 9, 0x0, sum = 2
4310 06:48:25.047433 10, 0x0, sum = 3
4311 06:48:25.047513 11, 0x0, sum = 4
4312 06:48:25.050365 best_step = 9
4313 06:48:25.050450
4314 06:48:25.050519 ==
4315 06:48:25.053677 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 06:48:25.057196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 06:48:25.057276 ==
4318 06:48:25.060532 RX Vref Scan: 0
4319 06:48:25.060609
4320 06:48:25.060671 RX Vref 0 -> 0, step: 1
4321 06:48:25.060738
4322 06:48:25.063477 RX Delay -195 -> 252, step: 8
4323 06:48:25.070695 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4324 06:48:25.074280 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4325 06:48:25.078112 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4326 06:48:25.080559 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4327 06:48:25.087161 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4328 06:48:25.090857 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4329 06:48:25.093809 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4330 06:48:25.097087 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4331 06:48:25.100406 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4332 06:48:25.107952 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4333 06:48:25.110887 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4334 06:48:25.114394 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4335 06:48:25.117659 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4336 06:48:25.124118 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4337 06:48:25.127354 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4338 06:48:25.131697 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4339 06:48:25.131795 ==
4340 06:48:25.134201 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 06:48:25.137586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 06:48:25.137673 ==
4343 06:48:25.140800 DQS Delay:
4344 06:48:25.140903 DQS0 = 0, DQS1 = 0
4345 06:48:25.144035 DQM Delay:
4346 06:48:25.144145 DQM0 = 39, DQM1 = 33
4347 06:48:25.144239 DQ Delay:
4348 06:48:25.147226 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4349 06:48:25.150887 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4350 06:48:25.154310 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4351 06:48:25.157210 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4352 06:48:25.157297
4353 06:48:25.157362
4354 06:48:25.167303 [DQSOSCAuto] RK1, (LSB)MR18= 0x492b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4355 06:48:25.171031 CH0 RK1: MR19=808, MR18=492B
4356 06:48:25.177375 CH0_RK1: MR19=0x808, MR18=0x492B, DQSOSC=396, MR23=63, INC=167, DEC=111
4357 06:48:25.177494 [RxdqsGatingPostProcess] freq 600
4358 06:48:25.183906 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4359 06:48:25.187496 Pre-setting of DQS Precalculation
4360 06:48:25.190951 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4361 06:48:25.191036 ==
4362 06:48:25.194108 Dram Type= 6, Freq= 0, CH_1, rank 0
4363 06:48:25.201284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 06:48:25.201377 ==
4365 06:48:25.204357 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 06:48:25.210982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4367 06:48:25.214421 [CA 0] Center 35 (5~65) winsize 61
4368 06:48:25.217710 [CA 1] Center 35 (5~65) winsize 61
4369 06:48:25.221123 [CA 2] Center 33 (3~64) winsize 62
4370 06:48:25.224772 [CA 3] Center 33 (3~64) winsize 62
4371 06:48:25.228185 [CA 4] Center 33 (3~64) winsize 62
4372 06:48:25.231409 [CA 5] Center 33 (3~64) winsize 62
4373 06:48:25.231565
4374 06:48:25.234452 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4375 06:48:25.234551
4376 06:48:25.237731 [CATrainingPosCal] consider 1 rank data
4377 06:48:25.241226 u2DelayCellTimex100 = 270/100 ps
4378 06:48:25.244229 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4379 06:48:25.248208 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4380 06:48:25.254824 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4381 06:48:25.257961 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4382 06:48:25.261245 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 06:48:25.264939 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4384 06:48:25.265058
4385 06:48:25.267919 CA PerBit enable=1, Macro0, CA PI delay=33
4386 06:48:25.268015
4387 06:48:25.271030 [CBTSetCACLKResult] CA Dly = 33
4388 06:48:25.271128 CS Dly: 4 (0~35)
4389 06:48:25.271196 ==
4390 06:48:25.274571 Dram Type= 6, Freq= 0, CH_1, rank 1
4391 06:48:25.281508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 06:48:25.281643 ==
4393 06:48:25.284674 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 06:48:25.291189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4395 06:48:25.294997 [CA 0] Center 35 (5~66) winsize 62
4396 06:48:25.298169 [CA 1] Center 36 (6~66) winsize 61
4397 06:48:25.301330 [CA 2] Center 34 (3~65) winsize 63
4398 06:48:25.304684 [CA 3] Center 33 (3~64) winsize 62
4399 06:48:25.308225 [CA 4] Center 34 (4~65) winsize 62
4400 06:48:25.311598 [CA 5] Center 33 (3~64) winsize 62
4401 06:48:25.311691
4402 06:48:25.314741 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4403 06:48:25.314817
4404 06:48:25.317736 [CATrainingPosCal] consider 2 rank data
4405 06:48:25.321275 u2DelayCellTimex100 = 270/100 ps
4406 06:48:25.324674 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4407 06:48:25.328288 CA1 delay=35 (6~65),Diff = 2 PI (19 cell)
4408 06:48:25.331734 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 06:48:25.334632 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4410 06:48:25.341548 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4411 06:48:25.345179 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 06:48:25.345266
4413 06:48:25.347910 CA PerBit enable=1, Macro0, CA PI delay=33
4414 06:48:25.347995
4415 06:48:25.351276 [CBTSetCACLKResult] CA Dly = 33
4416 06:48:25.351361 CS Dly: 5 (0~37)
4417 06:48:25.351428
4418 06:48:25.354590 ----->DramcWriteLeveling(PI) begin...
4419 06:48:25.354676 ==
4420 06:48:25.358014 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 06:48:25.364852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 06:48:25.364946 ==
4423 06:48:25.368509 Write leveling (Byte 0): 29 => 29
4424 06:48:25.371473 Write leveling (Byte 1): 31 => 31
4425 06:48:25.371559 DramcWriteLeveling(PI) end<-----
4426 06:48:25.371625
4427 06:48:25.374945 ==
4428 06:48:25.378122 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 06:48:25.381533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 06:48:25.381619 ==
4431 06:48:25.384812 [Gating] SW mode calibration
4432 06:48:25.391272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4433 06:48:25.395165 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4434 06:48:25.401826 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 06:48:25.405037 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 06:48:25.408305 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 06:48:25.414888 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
4438 06:48:25.418407 0 9 16 | B1->B0 | 2e2d 2525 | 1 0 | (0 0) (0 0)
4439 06:48:25.421450 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 06:48:25.425365 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 06:48:25.431760 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4442 06:48:25.435218 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4443 06:48:25.438426 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4444 06:48:25.444805 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4445 06:48:25.448446 0 10 12 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
4446 06:48:25.451700 0 10 16 | B1->B0 | 3c3c 3f3f | 0 0 | (0 0) (0 0)
4447 06:48:25.458245 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 06:48:25.461766 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 06:48:25.465505 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 06:48:25.471860 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 06:48:25.475090 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 06:48:25.478690 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 06:48:25.485115 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 06:48:25.488550 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4455 06:48:25.492304 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 06:48:25.498640 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 06:48:25.502223 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 06:48:25.505204 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 06:48:25.508290 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 06:48:25.515285 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 06:48:25.518515 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 06:48:25.521952 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 06:48:25.528718 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 06:48:25.532183 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 06:48:25.535158 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 06:48:25.541901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 06:48:25.544897 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 06:48:25.548516 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 06:48:25.555289 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 06:48:25.558824 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 06:48:25.561681 Total UI for P1: 0, mck2ui 16
4472 06:48:25.565323 best dqsien dly found for B0: ( 0, 13, 14)
4473 06:48:25.568618 Total UI for P1: 0, mck2ui 16
4474 06:48:25.571768 best dqsien dly found for B1: ( 0, 13, 14)
4475 06:48:25.575262 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4476 06:48:25.578623 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4477 06:48:25.578709
4478 06:48:25.581654 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4479 06:48:25.585002 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4480 06:48:25.589288 [Gating] SW calibration Done
4481 06:48:25.589376 ==
4482 06:48:25.591797 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 06:48:25.595185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 06:48:25.595271 ==
4485 06:48:25.598278 RX Vref Scan: 0
4486 06:48:25.598367
4487 06:48:25.601717 RX Vref 0 -> 0, step: 1
4488 06:48:25.601853
4489 06:48:25.605119 RX Delay -230 -> 252, step: 16
4490 06:48:25.609027 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4491 06:48:25.611945 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4492 06:48:25.615302 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4493 06:48:25.618534 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4494 06:48:25.625180 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4495 06:48:25.628434 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4496 06:48:25.631691 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4497 06:48:25.635323 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4498 06:48:25.641792 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4499 06:48:25.645324 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4500 06:48:25.648418 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4501 06:48:25.652074 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4502 06:48:25.655306 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4503 06:48:25.662157 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4504 06:48:25.665296 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4505 06:48:25.668896 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4506 06:48:25.668984 ==
4507 06:48:25.671862 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 06:48:25.675263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 06:48:25.678424 ==
4510 06:48:25.678502 DQS Delay:
4511 06:48:25.678566 DQS0 = 0, DQS1 = 0
4512 06:48:25.681876 DQM Delay:
4513 06:48:25.681975 DQM0 = 44, DQM1 = 35
4514 06:48:25.685148 DQ Delay:
4515 06:48:25.685259 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4516 06:48:25.688513 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4517 06:48:25.691920 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4518 06:48:25.695651 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4519 06:48:25.695738
4520 06:48:25.698192
4521 06:48:25.698301 ==
4522 06:48:25.701530 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 06:48:25.705394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 06:48:25.705481 ==
4525 06:48:25.705547
4526 06:48:25.705609
4527 06:48:25.708410 TX Vref Scan disable
4528 06:48:25.708495 == TX Byte 0 ==
4529 06:48:25.715012 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4530 06:48:25.718233 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4531 06:48:25.718356 == TX Byte 1 ==
4532 06:48:25.725251 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4533 06:48:25.728288 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4534 06:48:25.728374 ==
4535 06:48:25.731742 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 06:48:25.735354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 06:48:25.735448 ==
4538 06:48:25.735515
4539 06:48:25.735576
4540 06:48:25.738425 TX Vref Scan disable
4541 06:48:25.741905 == TX Byte 0 ==
4542 06:48:25.745077 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4543 06:48:25.748598 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4544 06:48:25.751769 == TX Byte 1 ==
4545 06:48:25.755397 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 06:48:25.758541 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 06:48:25.758650
4548 06:48:25.762744 [DATLAT]
4549 06:48:25.762844 Freq=600, CH1 RK0
4550 06:48:25.762933
4551 06:48:25.764994 DATLAT Default: 0x9
4552 06:48:25.765094 0, 0xFFFF, sum = 0
4553 06:48:25.768760 1, 0xFFFF, sum = 0
4554 06:48:25.768874 2, 0xFFFF, sum = 0
4555 06:48:25.771566 3, 0xFFFF, sum = 0
4556 06:48:25.771640 4, 0xFFFF, sum = 0
4557 06:48:25.775247 5, 0xFFFF, sum = 0
4558 06:48:25.775355 6, 0xFFFF, sum = 0
4559 06:48:25.778854 7, 0xFFFF, sum = 0
4560 06:48:25.778932 8, 0x0, sum = 1
4561 06:48:25.781868 9, 0x0, sum = 2
4562 06:48:25.781944 10, 0x0, sum = 3
4563 06:48:25.785428 11, 0x0, sum = 4
4564 06:48:25.785515 best_step = 9
4565 06:48:25.785599
4566 06:48:25.785695 ==
4567 06:48:25.788557 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 06:48:25.791949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 06:48:25.795084 ==
4570 06:48:25.795162 RX Vref Scan: 1
4571 06:48:25.795247
4572 06:48:25.798714 RX Vref 0 -> 0, step: 1
4573 06:48:25.798787
4574 06:48:25.801718 RX Delay -195 -> 252, step: 8
4575 06:48:25.801797
4576 06:48:25.805573 Set Vref, RX VrefLevel [Byte0]: 59
4577 06:48:25.805647 [Byte1]: 49
4578 06:48:25.810638
4579 06:48:25.810712 Final RX Vref Byte 0 = 59 to rank0
4580 06:48:25.813934 Final RX Vref Byte 1 = 49 to rank0
4581 06:48:25.816784 Final RX Vref Byte 0 = 59 to rank1
4582 06:48:25.820091 Final RX Vref Byte 1 = 49 to rank1==
4583 06:48:25.823457 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 06:48:25.830206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 06:48:25.830386 ==
4586 06:48:25.830502 DQS Delay:
4587 06:48:25.830583 DQS0 = 0, DQS1 = 0
4588 06:48:25.833101 DQM Delay:
4589 06:48:25.833206 DQM0 = 40, DQM1 = 32
4590 06:48:25.837167 DQ Delay:
4591 06:48:25.840250 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4592 06:48:25.840367 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4593 06:48:25.843548 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =28
4594 06:48:25.846988 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4595 06:48:25.850348
4596 06:48:25.850489
4597 06:48:25.856589 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a10, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
4598 06:48:25.859904 CH1 RK0: MR19=808, MR18=4A10
4599 06:48:25.866930 CH1_RK0: MR19=0x808, MR18=0x4A10, DQSOSC=395, MR23=63, INC=168, DEC=112
4600 06:48:25.867099
4601 06:48:25.870088 ----->DramcWriteLeveling(PI) begin...
4602 06:48:25.870199 ==
4603 06:48:25.873415 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 06:48:25.876558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 06:48:25.876676 ==
4606 06:48:25.880391 Write leveling (Byte 0): 29 => 29
4607 06:48:25.883414 Write leveling (Byte 1): 30 => 30
4608 06:48:25.886715 DramcWriteLeveling(PI) end<-----
4609 06:48:25.886791
4610 06:48:25.886890 ==
4611 06:48:25.889907 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 06:48:25.893500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 06:48:25.893576 ==
4614 06:48:25.896919 [Gating] SW mode calibration
4615 06:48:25.903723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4616 06:48:25.910233 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4617 06:48:25.913437 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4618 06:48:25.916587 0 9 4 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4619 06:48:25.923535 0 9 8 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
4620 06:48:25.926610 0 9 12 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (1 0)
4621 06:48:25.930094 0 9 16 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
4622 06:48:25.937108 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4623 06:48:25.940271 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 06:48:25.943755 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4625 06:48:25.950464 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4626 06:48:25.953406 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4627 06:48:25.956857 0 10 8 | B1->B0 | 2424 2323 | 0 1 | (0 0) (0 0)
4628 06:48:25.960112 0 10 12 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (0 0)
4629 06:48:25.966784 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 06:48:25.970723 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 06:48:25.973606 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 06:48:25.980694 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 06:48:25.983599 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 06:48:25.987112 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 06:48:25.993804 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 06:48:25.996646 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4637 06:48:26.000251 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 06:48:26.007079 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 06:48:26.010111 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 06:48:26.013472 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 06:48:26.020302 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 06:48:26.023753 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 06:48:26.027166 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 06:48:26.033530 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 06:48:26.036711 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 06:48:26.040120 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 06:48:26.046825 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 06:48:26.050349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 06:48:26.053744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 06:48:26.060121 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 06:48:26.064203 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4652 06:48:26.066769 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 06:48:26.070283 Total UI for P1: 0, mck2ui 16
4654 06:48:26.073677 best dqsien dly found for B0: ( 0, 13, 8)
4655 06:48:26.076712 Total UI for P1: 0, mck2ui 16
4656 06:48:26.080477 best dqsien dly found for B1: ( 0, 13, 10)
4657 06:48:26.084117 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4658 06:48:26.087167 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4659 06:48:26.087246
4660 06:48:26.090377 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4661 06:48:26.096803 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4662 06:48:26.096912 [Gating] SW calibration Done
4663 06:48:26.097020 ==
4664 06:48:26.099984 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 06:48:26.106852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 06:48:26.106931 ==
4667 06:48:26.106994 RX Vref Scan: 0
4668 06:48:26.107071
4669 06:48:26.110268 RX Vref 0 -> 0, step: 1
4670 06:48:26.110352
4671 06:48:26.113151 RX Delay -230 -> 252, step: 16
4672 06:48:26.116667 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4673 06:48:26.120213 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4674 06:48:26.123301 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4675 06:48:26.130311 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4676 06:48:26.133881 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4677 06:48:26.136857 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4678 06:48:26.140196 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4679 06:48:26.143533 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4680 06:48:26.150837 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4681 06:48:26.153924 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4682 06:48:26.156775 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4683 06:48:26.160649 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4684 06:48:26.166674 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4685 06:48:26.170467 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4686 06:48:26.173689 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4687 06:48:26.177225 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4688 06:48:26.177306 ==
4689 06:48:26.180545 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 06:48:26.186874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 06:48:26.186963 ==
4692 06:48:26.187028 DQS Delay:
4693 06:48:26.191231 DQS0 = 0, DQS1 = 0
4694 06:48:26.191337 DQM Delay:
4695 06:48:26.191435 DQM0 = 41, DQM1 = 36
4696 06:48:26.193723 DQ Delay:
4697 06:48:26.197281 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4698 06:48:26.200372 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4699 06:48:26.204106 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4700 06:48:26.207865 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4701 06:48:26.208025
4702 06:48:26.208138
4703 06:48:26.208249 ==
4704 06:48:26.210613 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 06:48:26.213514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 06:48:26.213643 ==
4707 06:48:26.213757
4708 06:48:26.213859
4709 06:48:26.216852 TX Vref Scan disable
4710 06:48:26.216971 == TX Byte 0 ==
4711 06:48:26.223555 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4712 06:48:26.227154 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4713 06:48:26.227331 == TX Byte 1 ==
4714 06:48:26.234153 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4715 06:48:26.236825 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4716 06:48:26.236935 ==
4717 06:48:26.240242 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 06:48:26.243948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 06:48:26.244056 ==
4720 06:48:26.244149
4721 06:48:26.244238
4722 06:48:26.247012 TX Vref Scan disable
4723 06:48:26.250502 == TX Byte 0 ==
4724 06:48:26.253785 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4725 06:48:26.257125 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4726 06:48:26.260535 == TX Byte 1 ==
4727 06:48:26.264062 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4728 06:48:26.267089 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4729 06:48:26.270354
4730 06:48:26.270478 [DATLAT]
4731 06:48:26.270573 Freq=600, CH1 RK1
4732 06:48:26.270656
4733 06:48:26.273944 DATLAT Default: 0x9
4734 06:48:26.274092 0, 0xFFFF, sum = 0
4735 06:48:26.277169 1, 0xFFFF, sum = 0
4736 06:48:26.277326 2, 0xFFFF, sum = 0
4737 06:48:26.280410 3, 0xFFFF, sum = 0
4738 06:48:26.280587 4, 0xFFFF, sum = 0
4739 06:48:26.283774 5, 0xFFFF, sum = 0
4740 06:48:26.283923 6, 0xFFFF, sum = 0
4741 06:48:26.286955 7, 0xFFFF, sum = 0
4742 06:48:26.287098 8, 0x0, sum = 1
4743 06:48:26.290762 9, 0x0, sum = 2
4744 06:48:26.290930 10, 0x0, sum = 3
4745 06:48:26.293896 11, 0x0, sum = 4
4746 06:48:26.294104 best_step = 9
4747 06:48:26.294336
4748 06:48:26.294534 ==
4749 06:48:26.297396 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 06:48:26.300674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 06:48:26.304365 ==
4752 06:48:26.304763 RX Vref Scan: 0
4753 06:48:26.305123
4754 06:48:26.307382 RX Vref 0 -> 0, step: 1
4755 06:48:26.307457
4756 06:48:26.310435 RX Delay -179 -> 252, step: 8
4757 06:48:26.313605 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4758 06:48:26.317045 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4759 06:48:26.323808 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4760 06:48:26.326830 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4761 06:48:26.330204 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4762 06:48:26.334014 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4763 06:48:26.340660 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4764 06:48:26.343902 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4765 06:48:26.346903 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4766 06:48:26.350928 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4767 06:48:26.354252 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4768 06:48:26.360743 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4769 06:48:26.363722 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4770 06:48:26.367196 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4771 06:48:26.370283 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4772 06:48:26.377203 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4773 06:48:26.377305 ==
4774 06:48:26.380257 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 06:48:26.383998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 06:48:26.384096 ==
4777 06:48:26.384185 DQS Delay:
4778 06:48:26.387239 DQS0 = 0, DQS1 = 0
4779 06:48:26.387309 DQM Delay:
4780 06:48:26.390307 DQM0 = 39, DQM1 = 33
4781 06:48:26.390426 DQ Delay:
4782 06:48:26.393426 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4783 06:48:26.396689 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4784 06:48:26.400295 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4785 06:48:26.404002 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4786 06:48:26.404098
4787 06:48:26.404185
4788 06:48:26.410111 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a48, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
4789 06:48:26.413701 CH1 RK1: MR19=808, MR18=3A48
4790 06:48:26.420475 CH1_RK1: MR19=0x808, MR18=0x3A48, DQSOSC=396, MR23=63, INC=167, DEC=111
4791 06:48:26.423586 [RxdqsGatingPostProcess] freq 600
4792 06:48:26.430536 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4793 06:48:26.433814 Pre-setting of DQS Precalculation
4794 06:48:26.436740 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4795 06:48:26.443486 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4796 06:48:26.450359 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4797 06:48:26.450470
4798 06:48:26.450537
4799 06:48:26.453636 [Calibration Summary] 1200 Mbps
4800 06:48:26.456853 CH 0, Rank 0
4801 06:48:26.456926 SW Impedance : PASS
4802 06:48:26.460607 DUTY Scan : NO K
4803 06:48:26.463568 ZQ Calibration : PASS
4804 06:48:26.463666 Jitter Meter : NO K
4805 06:48:26.466828 CBT Training : PASS
4806 06:48:26.470149 Write leveling : PASS
4807 06:48:26.470253 RX DQS gating : PASS
4808 06:48:26.473738 RX DQ/DQS(RDDQC) : PASS
4809 06:48:26.473812 TX DQ/DQS : PASS
4810 06:48:26.477160 RX DATLAT : PASS
4811 06:48:26.480548 RX DQ/DQS(Engine): PASS
4812 06:48:26.480655 TX OE : NO K
4813 06:48:26.483764 All Pass.
4814 06:48:26.483862
4815 06:48:26.483952 CH 0, Rank 1
4816 06:48:26.486883 SW Impedance : PASS
4817 06:48:26.486960 DUTY Scan : NO K
4818 06:48:26.490735 ZQ Calibration : PASS
4819 06:48:26.493739 Jitter Meter : NO K
4820 06:48:26.493810 CBT Training : PASS
4821 06:48:26.497099 Write leveling : PASS
4822 06:48:26.500151 RX DQS gating : PASS
4823 06:48:26.500252 RX DQ/DQS(RDDQC) : PASS
4824 06:48:26.503665 TX DQ/DQS : PASS
4825 06:48:26.507231 RX DATLAT : PASS
4826 06:48:26.507305 RX DQ/DQS(Engine): PASS
4827 06:48:26.510259 TX OE : NO K
4828 06:48:26.510358 All Pass.
4829 06:48:26.510472
4830 06:48:26.513561 CH 1, Rank 0
4831 06:48:26.513633 SW Impedance : PASS
4832 06:48:26.517235 DUTY Scan : NO K
4833 06:48:26.517308 ZQ Calibration : PASS
4834 06:48:26.520501 Jitter Meter : NO K
4835 06:48:26.523284 CBT Training : PASS
4836 06:48:26.523387 Write leveling : PASS
4837 06:48:26.526500 RX DQS gating : PASS
4838 06:48:26.529774 RX DQ/DQS(RDDQC) : PASS
4839 06:48:26.529874 TX DQ/DQS : PASS
4840 06:48:26.533220 RX DATLAT : PASS
4841 06:48:26.536952 RX DQ/DQS(Engine): PASS
4842 06:48:26.537054 TX OE : NO K
4843 06:48:26.539855 All Pass.
4844 06:48:26.539927
4845 06:48:26.539987 CH 1, Rank 1
4846 06:48:26.543458 SW Impedance : PASS
4847 06:48:26.543531 DUTY Scan : NO K
4848 06:48:26.546367 ZQ Calibration : PASS
4849 06:48:26.550403 Jitter Meter : NO K
4850 06:48:26.550563 CBT Training : PASS
4851 06:48:26.553047 Write leveling : PASS
4852 06:48:26.556693 RX DQS gating : PASS
4853 06:48:26.556773 RX DQ/DQS(RDDQC) : PASS
4854 06:48:26.559633 TX DQ/DQS : PASS
4855 06:48:26.563154 RX DATLAT : PASS
4856 06:48:26.563254 RX DQ/DQS(Engine): PASS
4857 06:48:26.566508 TX OE : NO K
4858 06:48:26.566609 All Pass.
4859 06:48:26.566699
4860 06:48:26.569947 DramC Write-DBI off
4861 06:48:26.573445 PER_BANK_REFRESH: Hybrid Mode
4862 06:48:26.573545 TX_TRACKING: ON
4863 06:48:26.583041 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4864 06:48:26.586300 [FAST_K] Save calibration result to emmc
4865 06:48:26.589574 dramc_set_vcore_voltage set vcore to 662500
4866 06:48:26.592960 Read voltage for 933, 3
4867 06:48:26.593036 Vio18 = 0
4868 06:48:26.593099 Vcore = 662500
4869 06:48:26.596462 Vdram = 0
4870 06:48:26.596562 Vddq = 0
4871 06:48:26.596651 Vmddr = 0
4872 06:48:26.603507 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4873 06:48:26.606650 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4874 06:48:26.609668 MEM_TYPE=3, freq_sel=17
4875 06:48:26.612848 sv_algorithm_assistance_LP4_1600
4876 06:48:26.616109 ============ PULL DRAM RESETB DOWN ============
4877 06:48:26.619924 ========== PULL DRAM RESETB DOWN end =========
4878 06:48:26.626537 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4879 06:48:26.629874 ===================================
4880 06:48:26.629983 LPDDR4 DRAM CONFIGURATION
4881 06:48:26.632897 ===================================
4882 06:48:26.636469 EX_ROW_EN[0] = 0x0
4883 06:48:26.639863 EX_ROW_EN[1] = 0x0
4884 06:48:26.639962 LP4Y_EN = 0x0
4885 06:48:26.642953 WORK_FSP = 0x0
4886 06:48:26.643041 WL = 0x3
4887 06:48:26.646055 RL = 0x3
4888 06:48:26.646158 BL = 0x2
4889 06:48:26.649727 RPST = 0x0
4890 06:48:26.649800 RD_PRE = 0x0
4891 06:48:26.652598 WR_PRE = 0x1
4892 06:48:26.652699 WR_PST = 0x0
4893 06:48:26.655832 DBI_WR = 0x0
4894 06:48:26.655904 DBI_RD = 0x0
4895 06:48:26.659585 OTF = 0x1
4896 06:48:26.662730 ===================================
4897 06:48:26.666349 ===================================
4898 06:48:26.666479 ANA top config
4899 06:48:26.669600 ===================================
4900 06:48:26.673444 DLL_ASYNC_EN = 0
4901 06:48:26.675974 ALL_SLAVE_EN = 1
4902 06:48:26.676074 NEW_RANK_MODE = 1
4903 06:48:26.679613 DLL_IDLE_MODE = 1
4904 06:48:26.682885 LP45_APHY_COMB_EN = 1
4905 06:48:26.686142 TX_ODT_DIS = 1
4906 06:48:26.689274 NEW_8X_MODE = 1
4907 06:48:26.692444 ===================================
4908 06:48:26.695923 ===================================
4909 06:48:26.695997 data_rate = 1866
4910 06:48:26.699221 CKR = 1
4911 06:48:26.702469 DQ_P2S_RATIO = 8
4912 06:48:26.706055 ===================================
4913 06:48:26.709199 CA_P2S_RATIO = 8
4914 06:48:26.712433 DQ_CA_OPEN = 0
4915 06:48:26.716195 DQ_SEMI_OPEN = 0
4916 06:48:26.716265 CA_SEMI_OPEN = 0
4917 06:48:26.719475 CA_FULL_RATE = 0
4918 06:48:26.722503 DQ_CKDIV4_EN = 1
4919 06:48:26.725703 CA_CKDIV4_EN = 1
4920 06:48:26.729330 CA_PREDIV_EN = 0
4921 06:48:26.732369 PH8_DLY = 0
4922 06:48:26.732469 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4923 06:48:26.736154 DQ_AAMCK_DIV = 4
4924 06:48:26.739155 CA_AAMCK_DIV = 4
4925 06:48:26.742712 CA_ADMCK_DIV = 4
4926 06:48:26.745704 DQ_TRACK_CA_EN = 0
4927 06:48:26.749513 CA_PICK = 933
4928 06:48:26.749614 CA_MCKIO = 933
4929 06:48:26.752711 MCKIO_SEMI = 0
4930 06:48:26.755646 PLL_FREQ = 3732
4931 06:48:26.759160 DQ_UI_PI_RATIO = 32
4932 06:48:26.762208 CA_UI_PI_RATIO = 0
4933 06:48:26.765926 ===================================
4934 06:48:26.769316 ===================================
4935 06:48:26.772779 memory_type:LPDDR4
4936 06:48:26.772878 GP_NUM : 10
4937 06:48:26.776047 SRAM_EN : 1
4938 06:48:26.776142 MD32_EN : 0
4939 06:48:26.778979 ===================================
4940 06:48:26.782547 [ANA_INIT] >>>>>>>>>>>>>>
4941 06:48:26.785896 <<<<<< [CONFIGURE PHASE]: ANA_TX
4942 06:48:26.789107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4943 06:48:26.792571 ===================================
4944 06:48:26.795943 data_rate = 1866,PCW = 0X8f00
4945 06:48:26.799513 ===================================
4946 06:48:26.802486 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4947 06:48:26.805820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4948 06:48:26.812752 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 06:48:26.815902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4950 06:48:26.822711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4951 06:48:26.826641 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4952 06:48:26.826722 [ANA_INIT] flow start
4953 06:48:26.829553 [ANA_INIT] PLL >>>>>>>>
4954 06:48:26.832681 [ANA_INIT] PLL <<<<<<<<
4955 06:48:26.832784 [ANA_INIT] MIDPI >>>>>>>>
4956 06:48:26.836439 [ANA_INIT] MIDPI <<<<<<<<
4957 06:48:26.839540 [ANA_INIT] DLL >>>>>>>>
4958 06:48:26.839640 [ANA_INIT] flow end
4959 06:48:26.842537 ============ LP4 DIFF to SE enter ============
4960 06:48:26.849338 ============ LP4 DIFF to SE exit ============
4961 06:48:26.849422 [ANA_INIT] <<<<<<<<<<<<<
4962 06:48:26.853003 [Flow] Enable top DCM control >>>>>
4963 06:48:26.856210 [Flow] Enable top DCM control <<<<<
4964 06:48:26.859465 Enable DLL master slave shuffle
4965 06:48:26.866283 ==============================================================
4966 06:48:26.866364 Gating Mode config
4967 06:48:26.872832 ==============================================================
4968 06:48:26.876516 Config description:
4969 06:48:26.882660 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4970 06:48:26.889538 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4971 06:48:26.896070 SELPH_MODE 0: By rank 1: By Phase
4972 06:48:26.902752 ==============================================================
4973 06:48:26.902829 GAT_TRACK_EN = 1
4974 06:48:26.906133 RX_GATING_MODE = 2
4975 06:48:26.909329 RX_GATING_TRACK_MODE = 2
4976 06:48:26.913018 SELPH_MODE = 1
4977 06:48:26.916490 PICG_EARLY_EN = 1
4978 06:48:26.919945 VALID_LAT_VALUE = 1
4979 06:48:26.926384 ==============================================================
4980 06:48:26.929575 Enter into Gating configuration >>>>
4981 06:48:26.933445 Exit from Gating configuration <<<<
4982 06:48:26.936436 Enter into DVFS_PRE_config >>>>>
4983 06:48:26.946261 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4984 06:48:26.949728 Exit from DVFS_PRE_config <<<<<
4985 06:48:26.953258 Enter into PICG configuration >>>>
4986 06:48:26.956403 Exit from PICG configuration <<<<
4987 06:48:26.956479 [RX_INPUT] configuration >>>>>
4988 06:48:26.959690 [RX_INPUT] configuration <<<<<
4989 06:48:26.966492 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4990 06:48:26.969660 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4991 06:48:26.976598 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4992 06:48:26.983472 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4993 06:48:26.989829 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 06:48:26.996828 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 06:48:26.999879 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4996 06:48:27.003269 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4997 06:48:27.006488 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4998 06:48:27.013227 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4999 06:48:27.016924 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5000 06:48:27.019757 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 06:48:27.023224 ===================================
5002 06:48:27.026646 LPDDR4 DRAM CONFIGURATION
5003 06:48:27.029820 ===================================
5004 06:48:27.033237 EX_ROW_EN[0] = 0x0
5005 06:48:27.033314 EX_ROW_EN[1] = 0x0
5006 06:48:27.036435 LP4Y_EN = 0x0
5007 06:48:27.036528 WORK_FSP = 0x0
5008 06:48:27.039848 WL = 0x3
5009 06:48:27.039922 RL = 0x3
5010 06:48:27.043263 BL = 0x2
5011 06:48:27.043335 RPST = 0x0
5012 06:48:27.046460 RD_PRE = 0x0
5013 06:48:27.046559 WR_PRE = 0x1
5014 06:48:27.049608 WR_PST = 0x0
5015 06:48:27.049733 DBI_WR = 0x0
5016 06:48:27.053504 DBI_RD = 0x0
5017 06:48:27.053575 OTF = 0x1
5018 06:48:27.056616 ===================================
5019 06:48:27.063196 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5020 06:48:27.066824 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5021 06:48:27.070044 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5022 06:48:27.073097 ===================================
5023 06:48:27.076155 LPDDR4 DRAM CONFIGURATION
5024 06:48:27.080031 ===================================
5025 06:48:27.083145 EX_ROW_EN[0] = 0x10
5026 06:48:27.083218 EX_ROW_EN[1] = 0x0
5027 06:48:27.086320 LP4Y_EN = 0x0
5028 06:48:27.086452 WORK_FSP = 0x0
5029 06:48:27.089547 WL = 0x3
5030 06:48:27.089644 RL = 0x3
5031 06:48:27.093107 BL = 0x2
5032 06:48:27.093184 RPST = 0x0
5033 06:48:27.096412 RD_PRE = 0x0
5034 06:48:27.096482 WR_PRE = 0x1
5035 06:48:27.100076 WR_PST = 0x0
5036 06:48:27.100147 DBI_WR = 0x0
5037 06:48:27.103259 DBI_RD = 0x0
5038 06:48:27.103328 OTF = 0x1
5039 06:48:27.106458 ===================================
5040 06:48:27.113094 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5041 06:48:27.117727 nWR fixed to 30
5042 06:48:27.120735 [ModeRegInit_LP4] CH0 RK0
5043 06:48:27.120809 [ModeRegInit_LP4] CH0 RK1
5044 06:48:27.124016 [ModeRegInit_LP4] CH1 RK0
5045 06:48:27.127854 [ModeRegInit_LP4] CH1 RK1
5046 06:48:27.127978 match AC timing 9
5047 06:48:27.134301 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5048 06:48:27.137686 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5049 06:48:27.141178 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5050 06:48:27.147558 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5051 06:48:27.150821 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5052 06:48:27.150905 ==
5053 06:48:27.154278 Dram Type= 6, Freq= 0, CH_0, rank 0
5054 06:48:27.157284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5055 06:48:27.157368 ==
5056 06:48:27.164479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5057 06:48:27.171035 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5058 06:48:27.174002 [CA 0] Center 38 (7~69) winsize 63
5059 06:48:27.177697 [CA 1] Center 38 (7~69) winsize 63
5060 06:48:27.180887 [CA 2] Center 35 (5~66) winsize 62
5061 06:48:27.184055 [CA 3] Center 34 (4~65) winsize 62
5062 06:48:27.187855 [CA 4] Center 34 (4~65) winsize 62
5063 06:48:27.190811 [CA 5] Center 34 (4~64) winsize 61
5064 06:48:27.190913
5065 06:48:27.194204 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5066 06:48:27.194280
5067 06:48:27.197824 [CATrainingPosCal] consider 1 rank data
5068 06:48:27.201029 u2DelayCellTimex100 = 270/100 ps
5069 06:48:27.204607 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5070 06:48:27.207836 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5071 06:48:27.210868 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5072 06:48:27.214693 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5073 06:48:27.218279 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5074 06:48:27.221250 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5075 06:48:27.221332
5076 06:48:27.224680 CA PerBit enable=1, Macro0, CA PI delay=34
5077 06:48:27.227794
5078 06:48:27.227893 [CBTSetCACLKResult] CA Dly = 34
5079 06:48:27.230696 CS Dly: 6 (0~37)
5080 06:48:27.230771 ==
5081 06:48:27.234580 Dram Type= 6, Freq= 0, CH_0, rank 1
5082 06:48:27.237775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 06:48:27.237862 ==
5084 06:48:27.244050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 06:48:27.251134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5086 06:48:27.254238 [CA 0] Center 38 (8~69) winsize 62
5087 06:48:27.257821 [CA 1] Center 38 (8~69) winsize 62
5088 06:48:27.260835 [CA 2] Center 35 (5~66) winsize 62
5089 06:48:27.264580 [CA 3] Center 35 (4~66) winsize 63
5090 06:48:27.267905 [CA 4] Center 34 (4~65) winsize 62
5091 06:48:27.268023 [CA 5] Center 33 (3~64) winsize 62
5092 06:48:27.271280
5093 06:48:27.274583 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5094 06:48:27.274690
5095 06:48:27.277804 [CATrainingPosCal] consider 2 rank data
5096 06:48:27.280901 u2DelayCellTimex100 = 270/100 ps
5097 06:48:27.284227 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5098 06:48:27.287782 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5099 06:48:27.291331 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5100 06:48:27.294527 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5101 06:48:27.298122 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5102 06:48:27.301552 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5103 06:48:27.301655
5104 06:48:27.304787 CA PerBit enable=1, Macro0, CA PI delay=34
5105 06:48:27.304891
5106 06:48:27.307935 [CBTSetCACLKResult] CA Dly = 34
5107 06:48:27.311247 CS Dly: 7 (0~39)
5108 06:48:27.311349
5109 06:48:27.314329 ----->DramcWriteLeveling(PI) begin...
5110 06:48:27.314455 ==
5111 06:48:27.317687 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 06:48:27.321037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 06:48:27.321110 ==
5114 06:48:27.324800 Write leveling (Byte 0): 32 => 32
5115 06:48:27.327913 Write leveling (Byte 1): 27 => 27
5116 06:48:27.330995 DramcWriteLeveling(PI) end<-----
5117 06:48:27.331077
5118 06:48:27.331177 ==
5119 06:48:27.334775 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 06:48:27.337940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 06:48:27.338022 ==
5122 06:48:27.341242 [Gating] SW mode calibration
5123 06:48:27.348113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5124 06:48:27.354902 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5125 06:48:27.358163 0 14 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5126 06:48:27.361650 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
5127 06:48:27.367872 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 06:48:27.371857 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 06:48:27.375031 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 06:48:27.381686 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 06:48:27.384660 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 06:48:27.388254 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5133 06:48:27.395171 0 15 0 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
5134 06:48:27.398274 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
5135 06:48:27.401586 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 06:48:27.408299 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 06:48:27.411719 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 06:48:27.414767 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 06:48:27.418194 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 06:48:27.425294 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5141 06:48:27.428197 1 0 0 | B1->B0 | 3332 4343 | 1 0 | (0 0) (0 0)
5142 06:48:27.431852 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 06:48:27.438552 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 06:48:27.442103 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 06:48:27.445320 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 06:48:27.451433 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 06:48:27.454708 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 06:48:27.458372 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 06:48:27.465103 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5150 06:48:27.468216 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5151 06:48:27.471865 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 06:48:27.477957 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 06:48:27.481875 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 06:48:27.484590 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 06:48:27.491495 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 06:48:27.494621 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 06:48:27.497892 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 06:48:27.504816 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 06:48:27.507935 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 06:48:27.511344 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 06:48:27.518529 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 06:48:27.521407 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 06:48:27.524563 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 06:48:27.527957 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5165 06:48:27.534644 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5166 06:48:27.538550 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5167 06:48:27.541370 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 06:48:27.544943 Total UI for P1: 0, mck2ui 16
5169 06:48:27.547993 best dqsien dly found for B0: ( 1, 3, 0)
5170 06:48:27.551557 Total UI for P1: 0, mck2ui 16
5171 06:48:27.554790 best dqsien dly found for B1: ( 1, 3, 4)
5172 06:48:27.558715 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5173 06:48:27.562327 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5174 06:48:27.562409
5175 06:48:27.568088 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5176 06:48:27.571636 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5177 06:48:27.571735 [Gating] SW calibration Done
5178 06:48:27.571828 ==
5179 06:48:27.575223 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 06:48:27.581608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 06:48:27.581712 ==
5182 06:48:27.581808 RX Vref Scan: 0
5183 06:48:27.581895
5184 06:48:27.584734 RX Vref 0 -> 0, step: 1
5185 06:48:27.584805
5186 06:48:27.588728 RX Delay -80 -> 252, step: 8
5187 06:48:27.591865 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5188 06:48:27.595356 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5189 06:48:27.598009 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5190 06:48:27.601487 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5191 06:48:27.608413 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5192 06:48:27.611584 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5193 06:48:27.614836 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5194 06:48:27.618813 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5195 06:48:27.621749 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5196 06:48:27.624919 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5197 06:48:27.631704 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5198 06:48:27.634854 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5199 06:48:27.638589 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5200 06:48:27.641379 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5201 06:48:27.645274 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5202 06:48:27.648519 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5203 06:48:27.651889 ==
5204 06:48:27.655384 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 06:48:27.658940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 06:48:27.659017 ==
5207 06:48:27.659081 DQS Delay:
5208 06:48:27.661872 DQS0 = 0, DQS1 = 0
5209 06:48:27.661943 DQM Delay:
5210 06:48:27.665079 DQM0 = 96, DQM1 = 87
5211 06:48:27.665151 DQ Delay:
5212 06:48:27.669269 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5213 06:48:27.671899 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5214 06:48:27.675028 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5215 06:48:27.678109 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5216 06:48:27.678213
5217 06:48:27.678320
5218 06:48:27.678438 ==
5219 06:48:27.681629 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 06:48:27.684913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 06:48:27.684992 ==
5222 06:48:27.685054
5223 06:48:27.685111
5224 06:48:27.688611 TX Vref Scan disable
5225 06:48:27.692052 == TX Byte 0 ==
5226 06:48:27.695052 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5227 06:48:27.698302 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5228 06:48:27.702059 == TX Byte 1 ==
5229 06:48:27.705299 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5230 06:48:27.708280 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5231 06:48:27.708352 ==
5232 06:48:27.712073 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 06:48:27.715171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 06:48:27.718369 ==
5235 06:48:27.718484
5236 06:48:27.718545
5237 06:48:27.718614 TX Vref Scan disable
5238 06:48:27.722085 == TX Byte 0 ==
5239 06:48:27.725957 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5240 06:48:27.729204 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5241 06:48:27.732217 == TX Byte 1 ==
5242 06:48:27.735763 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5243 06:48:27.742472 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5244 06:48:27.742560
5245 06:48:27.742623 [DATLAT]
5246 06:48:27.742682 Freq=933, CH0 RK0
5247 06:48:27.742740
5248 06:48:27.745480 DATLAT Default: 0xd
5249 06:48:27.745561 0, 0xFFFF, sum = 0
5250 06:48:27.749180 1, 0xFFFF, sum = 0
5251 06:48:27.749278 2, 0xFFFF, sum = 0
5252 06:48:27.752131 3, 0xFFFF, sum = 0
5253 06:48:27.752203 4, 0xFFFF, sum = 0
5254 06:48:27.755563 5, 0xFFFF, sum = 0
5255 06:48:27.758806 6, 0xFFFF, sum = 0
5256 06:48:27.758878 7, 0xFFFF, sum = 0
5257 06:48:27.762497 8, 0xFFFF, sum = 0
5258 06:48:27.762621 9, 0xFFFF, sum = 0
5259 06:48:27.765369 10, 0x0, sum = 1
5260 06:48:27.765442 11, 0x0, sum = 2
5261 06:48:27.765502 12, 0x0, sum = 3
5262 06:48:27.768883 13, 0x0, sum = 4
5263 06:48:27.768970 best_step = 11
5264 06:48:27.769030
5265 06:48:27.769086 ==
5266 06:48:27.772584 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 06:48:27.779034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 06:48:27.779108 ==
5269 06:48:27.779169 RX Vref Scan: 1
5270 06:48:27.779227
5271 06:48:27.782043 RX Vref 0 -> 0, step: 1
5272 06:48:27.782132
5273 06:48:27.785381 RX Delay -61 -> 252, step: 4
5274 06:48:27.785500
5275 06:48:27.789125 Set Vref, RX VrefLevel [Byte0]: 54
5276 06:48:27.792192 [Byte1]: 50
5277 06:48:27.792288
5278 06:48:27.795631 Final RX Vref Byte 0 = 54 to rank0
5279 06:48:27.798661 Final RX Vref Byte 1 = 50 to rank0
5280 06:48:27.802731 Final RX Vref Byte 0 = 54 to rank1
5281 06:48:27.805295 Final RX Vref Byte 1 = 50 to rank1==
5282 06:48:27.809095 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 06:48:27.812338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 06:48:27.812420 ==
5285 06:48:27.815853 DQS Delay:
5286 06:48:27.815935 DQS0 = 0, DQS1 = 0
5287 06:48:27.818639 DQM Delay:
5288 06:48:27.818720 DQM0 = 96, DQM1 = 88
5289 06:48:27.818784 DQ Delay:
5290 06:48:27.821894 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5291 06:48:27.825414 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5292 06:48:27.829148 DQ8 =78, DQ9 =74, DQ10 =90, DQ11 =82
5293 06:48:27.832645 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =98
5294 06:48:27.832725
5295 06:48:27.832789
5296 06:48:27.842323 [DQSOSCAuto] RK0, (LSB)MR18= 0x1702, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5297 06:48:27.845551 CH0 RK0: MR19=505, MR18=1702
5298 06:48:27.848936 CH0_RK0: MR19=0x505, MR18=0x1702, DQSOSC=414, MR23=63, INC=63, DEC=42
5299 06:48:27.849017
5300 06:48:27.855801 ----->DramcWriteLeveling(PI) begin...
5301 06:48:27.855883 ==
5302 06:48:27.858573 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 06:48:27.862291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 06:48:27.862372 ==
5305 06:48:27.865588 Write leveling (Byte 0): 30 => 30
5306 06:48:27.868566 Write leveling (Byte 1): 29 => 29
5307 06:48:27.872213 DramcWriteLeveling(PI) end<-----
5308 06:48:27.872294
5309 06:48:27.872357 ==
5310 06:48:27.875411 Dram Type= 6, Freq= 0, CH_0, rank 1
5311 06:48:27.879269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 06:48:27.879350 ==
5313 06:48:27.882137 [Gating] SW mode calibration
5314 06:48:27.888826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5315 06:48:27.895680 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5316 06:48:27.898981 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
5317 06:48:27.902077 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5318 06:48:27.905753 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 06:48:27.912172 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 06:48:27.915913 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 06:48:27.918956 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 06:48:27.925306 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 06:48:27.928736 0 14 28 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (0 0)
5324 06:48:27.932095 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
5325 06:48:27.939076 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 06:48:27.942276 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 06:48:27.945857 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 06:48:27.952271 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 06:48:27.955459 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 06:48:27.959130 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 06:48:27.965615 0 15 28 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
5332 06:48:27.969325 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
5333 06:48:27.972381 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 06:48:27.979003 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 06:48:27.982018 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 06:48:27.985941 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 06:48:27.989355 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 06:48:27.996104 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 06:48:27.998778 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5340 06:48:28.002333 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5341 06:48:28.009215 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 06:48:28.012986 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 06:48:28.016162 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 06:48:28.022524 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 06:48:28.026205 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 06:48:28.029165 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 06:48:28.036423 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 06:48:28.039743 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 06:48:28.042832 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 06:48:28.049450 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 06:48:28.053237 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 06:48:28.056181 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 06:48:28.059846 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 06:48:28.066132 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5355 06:48:28.069527 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5356 06:48:28.073067 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5357 06:48:28.076388 Total UI for P1: 0, mck2ui 16
5358 06:48:28.079623 best dqsien dly found for B0: ( 1, 2, 26)
5359 06:48:28.086248 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5360 06:48:28.089319 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 06:48:28.092964 Total UI for P1: 0, mck2ui 16
5362 06:48:28.096346 best dqsien dly found for B1: ( 1, 3, 2)
5363 06:48:28.099566 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5364 06:48:28.103397 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5365 06:48:28.103779
5366 06:48:28.106357 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5367 06:48:28.109786 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5368 06:48:28.113228 [Gating] SW calibration Done
5369 06:48:28.113643 ==
5370 06:48:28.116808 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 06:48:28.120064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 06:48:28.120491 ==
5373 06:48:28.123259 RX Vref Scan: 0
5374 06:48:28.123673
5375 06:48:28.126709 RX Vref 0 -> 0, step: 1
5376 06:48:28.127124
5377 06:48:28.127452 RX Delay -80 -> 252, step: 8
5378 06:48:28.133532 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5379 06:48:28.136666 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5380 06:48:28.140012 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5381 06:48:28.143247 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5382 06:48:28.146368 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5383 06:48:28.150282 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5384 06:48:28.156636 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5385 06:48:28.160317 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5386 06:48:28.162926 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5387 06:48:28.166467 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5388 06:48:28.169820 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5389 06:48:28.173005 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5390 06:48:28.180003 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5391 06:48:28.182785 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5392 06:48:28.186795 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5393 06:48:28.189801 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5394 06:48:28.190215 ==
5395 06:48:28.192909 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 06:48:28.196199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 06:48:28.199986 ==
5398 06:48:28.200404 DQS Delay:
5399 06:48:28.200731 DQS0 = 0, DQS1 = 0
5400 06:48:28.203032 DQM Delay:
5401 06:48:28.203450 DQM0 = 98, DQM1 = 87
5402 06:48:28.206327 DQ Delay:
5403 06:48:28.209639 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5404 06:48:28.210055 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5405 06:48:28.213046 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5406 06:48:28.219655 DQ12 =87, DQ13 =95, DQ14 =99, DQ15 =95
5407 06:48:28.220112
5408 06:48:28.220490
5409 06:48:28.220812 ==
5410 06:48:28.223176 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 06:48:28.226439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 06:48:28.226890 ==
5413 06:48:28.227248
5414 06:48:28.227720
5415 06:48:28.229937 TX Vref Scan disable
5416 06:48:28.230388 == TX Byte 0 ==
5417 06:48:28.236335 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5418 06:48:28.239804 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5419 06:48:28.240269 == TX Byte 1 ==
5420 06:48:28.246519 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5421 06:48:28.250261 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5422 06:48:28.250804 ==
5423 06:48:28.253595 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 06:48:28.257025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 06:48:28.257549 ==
5426 06:48:28.258012
5427 06:48:28.258601
5428 06:48:28.260109 TX Vref Scan disable
5429 06:48:28.262969 == TX Byte 0 ==
5430 06:48:28.266854 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5431 06:48:28.270074 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5432 06:48:28.273151 == TX Byte 1 ==
5433 06:48:28.276512 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5434 06:48:28.279968 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5435 06:48:28.280392
5436 06:48:28.283290 [DATLAT]
5437 06:48:28.283708 Freq=933, CH0 RK1
5438 06:48:28.284039
5439 06:48:28.286298 DATLAT Default: 0xb
5440 06:48:28.286753 0, 0xFFFF, sum = 0
5441 06:48:28.290345 1, 0xFFFF, sum = 0
5442 06:48:28.290804 2, 0xFFFF, sum = 0
5443 06:48:28.293354 3, 0xFFFF, sum = 0
5444 06:48:28.293778 4, 0xFFFF, sum = 0
5445 06:48:28.296959 5, 0xFFFF, sum = 0
5446 06:48:28.297387 6, 0xFFFF, sum = 0
5447 06:48:28.300296 7, 0xFFFF, sum = 0
5448 06:48:28.300720 8, 0xFFFF, sum = 0
5449 06:48:28.302932 9, 0xFFFF, sum = 0
5450 06:48:28.303356 10, 0x0, sum = 1
5451 06:48:28.306286 11, 0x0, sum = 2
5452 06:48:28.306775 12, 0x0, sum = 3
5453 06:48:28.309724 13, 0x0, sum = 4
5454 06:48:28.310144 best_step = 11
5455 06:48:28.310517
5456 06:48:28.310835 ==
5457 06:48:28.313507 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 06:48:28.316458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 06:48:28.320164 ==
5460 06:48:28.320581 RX Vref Scan: 0
5461 06:48:28.320910
5462 06:48:28.323032 RX Vref 0 -> 0, step: 1
5463 06:48:28.323450
5464 06:48:28.326723 RX Delay -61 -> 252, step: 4
5465 06:48:28.329894 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5466 06:48:28.333092 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5467 06:48:28.336496 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5468 06:48:28.343192 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5469 06:48:28.346845 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5470 06:48:28.349780 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5471 06:48:28.352844 iDelay=199, Bit 6, Center 108 (19 ~ 198) 180
5472 06:48:28.356073 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5473 06:48:28.359914 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5474 06:48:28.366376 iDelay=199, Bit 9, Center 80 (-5 ~ 166) 172
5475 06:48:28.369903 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5476 06:48:28.372963 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5477 06:48:28.376696 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5478 06:48:28.379994 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5479 06:48:28.383078 iDelay=199, Bit 14, Center 100 (19 ~ 182) 164
5480 06:48:28.389881 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5481 06:48:28.390300 ==
5482 06:48:28.393592 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 06:48:28.396684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 06:48:28.397105 ==
5485 06:48:28.397433 DQS Delay:
5486 06:48:28.400252 DQS0 = 0, DQS1 = 0
5487 06:48:28.400668 DQM Delay:
5488 06:48:28.403390 DQM0 = 96, DQM1 = 88
5489 06:48:28.403807 DQ Delay:
5490 06:48:28.407185 DQ0 =98, DQ1 =96, DQ2 =92, DQ3 =94
5491 06:48:28.410366 DQ4 =96, DQ5 =86, DQ6 =108, DQ7 =102
5492 06:48:28.413420 DQ8 =82, DQ9 =80, DQ10 =88, DQ11 =80
5493 06:48:28.416638 DQ12 =92, DQ13 =94, DQ14 =100, DQ15 =94
5494 06:48:28.417054
5495 06:48:28.417381
5496 06:48:28.423533 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5497 06:48:28.427131 CH0 RK1: MR19=505, MR18=1B09
5498 06:48:28.433778 CH0_RK1: MR19=0x505, MR18=0x1B09, DQSOSC=413, MR23=63, INC=63, DEC=42
5499 06:48:28.436966 [RxdqsGatingPostProcess] freq 933
5500 06:48:28.443361 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5501 06:48:28.446538 best DQS0 dly(2T, 0.5T) = (0, 11)
5502 06:48:28.446993 best DQS1 dly(2T, 0.5T) = (0, 11)
5503 06:48:28.450043 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5504 06:48:28.453491 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5505 06:48:28.456426 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 06:48:28.460009 best DQS1 dly(2T, 0.5T) = (0, 11)
5507 06:48:28.463085 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 06:48:28.466853 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5509 06:48:28.470018 Pre-setting of DQS Precalculation
5510 06:48:28.477011 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5511 06:48:28.477447 ==
5512 06:48:28.480665 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 06:48:28.483841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 06:48:28.484280 ==
5515 06:48:28.490233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 06:48:28.493403 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5517 06:48:28.497248 [CA 0] Center 36 (6~67) winsize 62
5518 06:48:28.500725 [CA 1] Center 36 (6~67) winsize 62
5519 06:48:28.503836 [CA 2] Center 34 (4~64) winsize 61
5520 06:48:28.507708 [CA 3] Center 33 (3~64) winsize 62
5521 06:48:28.510856 [CA 4] Center 34 (4~64) winsize 61
5522 06:48:28.514475 [CA 5] Center 33 (3~63) winsize 61
5523 06:48:28.514913
5524 06:48:28.517251 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5525 06:48:28.517684
5526 06:48:28.520495 [CATrainingPosCal] consider 1 rank data
5527 06:48:28.524119 u2DelayCellTimex100 = 270/100 ps
5528 06:48:28.527321 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5529 06:48:28.531213 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 06:48:28.537570 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5531 06:48:28.540544 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5532 06:48:28.543708 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5533 06:48:28.547299 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5534 06:48:28.547758
5535 06:48:28.550682 CA PerBit enable=1, Macro0, CA PI delay=33
5536 06:48:28.551198
5537 06:48:28.553782 [CBTSetCACLKResult] CA Dly = 33
5538 06:48:28.554202 CS Dly: 4 (0~35)
5539 06:48:28.554693 ==
5540 06:48:28.557534 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 06:48:28.563824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 06:48:28.564319 ==
5543 06:48:28.567444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5544 06:48:28.573678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5545 06:48:28.578273 [CA 0] Center 36 (6~67) winsize 62
5546 06:48:28.580530 [CA 1] Center 36 (6~67) winsize 62
5547 06:48:28.584415 [CA 2] Center 34 (4~64) winsize 61
5548 06:48:28.587601 [CA 3] Center 33 (3~64) winsize 62
5549 06:48:28.590757 [CA 4] Center 34 (4~65) winsize 62
5550 06:48:28.593699 [CA 5] Center 32 (2~63) winsize 62
5551 06:48:28.594305
5552 06:48:28.597180 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5553 06:48:28.597767
5554 06:48:28.600417 [CATrainingPosCal] consider 2 rank data
5555 06:48:28.604063 u2DelayCellTimex100 = 270/100 ps
5556 06:48:28.607311 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5557 06:48:28.610883 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5558 06:48:28.617395 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5559 06:48:28.620880 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5560 06:48:28.624007 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5561 06:48:28.627231 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5562 06:48:28.627704
5563 06:48:28.630661 CA PerBit enable=1, Macro0, CA PI delay=33
5564 06:48:28.631154
5565 06:48:28.634093 [CBTSetCACLKResult] CA Dly = 33
5566 06:48:28.634626 CS Dly: 5 (0~38)
5567 06:48:28.635047
5568 06:48:28.637119 ----->DramcWriteLeveling(PI) begin...
5569 06:48:28.640873 ==
5570 06:48:28.641401 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 06:48:28.647217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 06:48:28.647720 ==
5573 06:48:28.650886 Write leveling (Byte 0): 28 => 28
5574 06:48:28.653961 Write leveling (Byte 1): 29 => 29
5575 06:48:28.657451 DramcWriteLeveling(PI) end<-----
5576 06:48:28.657867
5577 06:48:28.658188 ==
5578 06:48:28.660602 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 06:48:28.663708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 06:48:28.664272 ==
5581 06:48:28.667024 [Gating] SW mode calibration
5582 06:48:28.673260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5583 06:48:28.677248 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5584 06:48:28.683478 0 14 0 | B1->B0 | 3131 3434 | 1 0 | (1 1) (0 0)
5585 06:48:28.686699 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 06:48:28.690474 0 14 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5587 06:48:28.696860 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5588 06:48:28.700547 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 06:48:28.703600 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5590 06:48:28.710394 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5591 06:48:28.713635 0 14 28 | B1->B0 | 2f2f 3232 | 1 0 | (1 0) (0 1)
5592 06:48:28.716813 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5593 06:48:28.723427 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 06:48:28.726746 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 06:48:28.730492 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 06:48:28.737010 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5597 06:48:28.740440 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 06:48:28.743332 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 06:48:28.750346 0 15 28 | B1->B0 | 2727 2d2d | 0 0 | (0 0) (0 0)
5600 06:48:28.753733 1 0 0 | B1->B0 | 4141 4242 | 0 0 | (0 0) (0 0)
5601 06:48:28.757325 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 06:48:28.760202 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 06:48:28.767077 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 06:48:28.770452 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 06:48:28.773722 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 06:48:28.780117 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5607 06:48:28.784073 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5608 06:48:28.787258 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 06:48:28.793934 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 06:48:28.797278 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 06:48:28.800237 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 06:48:28.807091 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 06:48:28.810271 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 06:48:28.814113 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 06:48:28.820175 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 06:48:28.823883 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 06:48:28.826950 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 06:48:28.833851 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 06:48:28.836987 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 06:48:28.840462 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 06:48:28.843612 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 06:48:28.850709 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 06:48:28.853499 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5624 06:48:28.856806 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5625 06:48:28.860302 Total UI for P1: 0, mck2ui 16
5626 06:48:28.863893 best dqsien dly found for B0: ( 1, 2, 28)
5627 06:48:28.870249 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 06:48:28.870333 Total UI for P1: 0, mck2ui 16
5629 06:48:28.877082 best dqsien dly found for B1: ( 1, 2, 30)
5630 06:48:28.880709 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5631 06:48:28.883842 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5632 06:48:28.883917
5633 06:48:28.886808 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5634 06:48:28.890553 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5635 06:48:28.893756 [Gating] SW calibration Done
5636 06:48:28.893851 ==
5637 06:48:28.896954 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 06:48:28.900246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 06:48:28.900347 ==
5640 06:48:28.903340 RX Vref Scan: 0
5641 06:48:28.903407
5642 06:48:28.903467 RX Vref 0 -> 0, step: 1
5643 06:48:28.903524
5644 06:48:28.906721 RX Delay -80 -> 252, step: 8
5645 06:48:28.910654 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5646 06:48:28.916811 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5647 06:48:28.920546 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5648 06:48:28.923633 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5649 06:48:28.926902 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5650 06:48:28.930606 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5651 06:48:28.933543 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5652 06:48:28.939916 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5653 06:48:28.943220 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5654 06:48:28.946768 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5655 06:48:28.950149 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5656 06:48:28.953757 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5657 06:48:28.960184 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5658 06:48:28.963501 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5659 06:48:28.966793 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5660 06:48:28.970237 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5661 06:48:28.970333 ==
5662 06:48:28.973428 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 06:48:28.976901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 06:48:28.977011 ==
5665 06:48:28.980131 DQS Delay:
5666 06:48:28.980236 DQS0 = 0, DQS1 = 0
5667 06:48:28.983915 DQM Delay:
5668 06:48:28.984021 DQM0 = 95, DQM1 = 89
5669 06:48:28.984110 DQ Delay:
5670 06:48:28.987308 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =95
5671 06:48:28.990197 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5672 06:48:28.993785 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5673 06:48:28.996804 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5674 06:48:28.996908
5675 06:48:28.996997
5676 06:48:29.000215 ==
5677 06:48:29.000316 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 06:48:29.007271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 06:48:29.007378 ==
5680 06:48:29.007468
5681 06:48:29.007559
5682 06:48:29.010179 TX Vref Scan disable
5683 06:48:29.010275 == TX Byte 0 ==
5684 06:48:29.013808 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5685 06:48:29.020216 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5686 06:48:29.020313 == TX Byte 1 ==
5687 06:48:29.023794 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5688 06:48:29.030401 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5689 06:48:29.030504 ==
5690 06:48:29.033991 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 06:48:29.037306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 06:48:29.037413 ==
5693 06:48:29.037477
5694 06:48:29.037536
5695 06:48:29.040641 TX Vref Scan disable
5696 06:48:29.043726 == TX Byte 0 ==
5697 06:48:29.046844 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5698 06:48:29.050598 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5699 06:48:29.053794 == TX Byte 1 ==
5700 06:48:29.057200 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5701 06:48:29.060112 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5702 06:48:29.060186
5703 06:48:29.060251 [DATLAT]
5704 06:48:29.063728 Freq=933, CH1 RK0
5705 06:48:29.063796
5706 06:48:29.063854 DATLAT Default: 0xd
5707 06:48:29.066929 0, 0xFFFF, sum = 0
5708 06:48:29.070183 1, 0xFFFF, sum = 0
5709 06:48:29.070277 2, 0xFFFF, sum = 0
5710 06:48:29.073803 3, 0xFFFF, sum = 0
5711 06:48:29.073878 4, 0xFFFF, sum = 0
5712 06:48:29.076844 5, 0xFFFF, sum = 0
5713 06:48:29.076941 6, 0xFFFF, sum = 0
5714 06:48:29.080577 7, 0xFFFF, sum = 0
5715 06:48:29.080674 8, 0xFFFF, sum = 0
5716 06:48:29.083946 9, 0xFFFF, sum = 0
5717 06:48:29.084044 10, 0x0, sum = 1
5718 06:48:29.087175 11, 0x0, sum = 2
5719 06:48:29.087271 12, 0x0, sum = 3
5720 06:48:29.087370 13, 0x0, sum = 4
5721 06:48:29.090319 best_step = 11
5722 06:48:29.090423
5723 06:48:29.090511 ==
5724 06:48:29.093566 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 06:48:29.096874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 06:48:29.096980 ==
5727 06:48:29.100435 RX Vref Scan: 1
5728 06:48:29.100535
5729 06:48:29.100624 RX Vref 0 -> 0, step: 1
5730 06:48:29.103874
5731 06:48:29.103943 RX Delay -61 -> 252, step: 4
5732 06:48:29.104005
5733 06:48:29.106879 Set Vref, RX VrefLevel [Byte0]: 59
5734 06:48:29.110497 [Byte1]: 49
5735 06:48:29.114671
5736 06:48:29.114737 Final RX Vref Byte 0 = 59 to rank0
5737 06:48:29.118190 Final RX Vref Byte 1 = 49 to rank0
5738 06:48:29.121410 Final RX Vref Byte 0 = 59 to rank1
5739 06:48:29.125240 Final RX Vref Byte 1 = 49 to rank1==
5740 06:48:29.128015 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 06:48:29.131932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 06:48:29.134788 ==
5743 06:48:29.134887 DQS Delay:
5744 06:48:29.134986 DQS0 = 0, DQS1 = 0
5745 06:48:29.138068 DQM Delay:
5746 06:48:29.138161 DQM0 = 97, DQM1 = 89
5747 06:48:29.141555 DQ Delay:
5748 06:48:29.144902 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =98
5749 06:48:29.148497 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5750 06:48:29.152123 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =84
5751 06:48:29.154834 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =94
5752 06:48:29.154933
5753 06:48:29.155021
5754 06:48:29.161574 [DQSOSCAuto] RK0, (LSB)MR18= 0x14f1, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5755 06:48:29.165072 CH1 RK0: MR19=504, MR18=14F1
5756 06:48:29.171743 CH1_RK0: MR19=0x504, MR18=0x14F1, DQSOSC=415, MR23=63, INC=62, DEC=41
5757 06:48:29.171852
5758 06:48:29.174871 ----->DramcWriteLeveling(PI) begin...
5759 06:48:29.174948 ==
5760 06:48:29.178131 Dram Type= 6, Freq= 0, CH_1, rank 1
5761 06:48:29.181733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 06:48:29.181835 ==
5763 06:48:29.184959 Write leveling (Byte 0): 28 => 28
5764 06:48:29.188858 Write leveling (Byte 1): 27 => 27
5765 06:48:29.192519 DramcWriteLeveling(PI) end<-----
5766 06:48:29.192590
5767 06:48:29.192650 ==
5768 06:48:29.195329 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 06:48:29.198254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 06:48:29.198347 ==
5771 06:48:29.201630 [Gating] SW mode calibration
5772 06:48:29.208217 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5773 06:48:29.215067 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5774 06:48:29.218170 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 06:48:29.221619 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 06:48:29.228136 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 06:48:29.231349 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 06:48:29.234960 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 06:48:29.241617 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5780 06:48:29.244915 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 0)
5781 06:48:29.248152 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5782 06:48:29.255173 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5783 06:48:29.258150 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 06:48:29.261489 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 06:48:29.268351 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 06:48:29.271512 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 06:48:29.274999 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 06:48:29.281462 0 15 24 | B1->B0 | 2c2c 3535 | 0 0 | (0 0) (0 0)
5789 06:48:29.284760 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5790 06:48:29.287930 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 06:48:29.294801 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 06:48:29.298728 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 06:48:29.301337 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 06:48:29.308315 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 06:48:29.311655 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 06:48:29.314665 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5797 06:48:29.318336 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 06:48:29.324848 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5799 06:48:29.327983 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 06:48:29.331455 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 06:48:29.338148 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 06:48:29.341377 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 06:48:29.344984 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 06:48:29.351690 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 06:48:29.354729 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 06:48:29.357772 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 06:48:29.364793 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 06:48:29.368159 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 06:48:29.371266 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 06:48:29.378228 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 06:48:29.381217 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5812 06:48:29.384902 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5813 06:48:29.391525 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5814 06:48:29.391612 Total UI for P1: 0, mck2ui 16
5815 06:48:29.394791 best dqsien dly found for B0: ( 1, 2, 22)
5816 06:48:29.401665 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 06:48:29.404512 Total UI for P1: 0, mck2ui 16
5818 06:48:29.407868 best dqsien dly found for B1: ( 1, 2, 26)
5819 06:48:29.411739 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5820 06:48:29.414748 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5821 06:48:29.414822
5822 06:48:29.417685 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5823 06:48:29.421148 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5824 06:48:29.424664 [Gating] SW calibration Done
5825 06:48:29.424747 ==
5826 06:48:29.427786 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 06:48:29.431534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 06:48:29.431618 ==
5829 06:48:29.434509 RX Vref Scan: 0
5830 06:48:29.434591
5831 06:48:29.437802 RX Vref 0 -> 0, step: 1
5832 06:48:29.437887
5833 06:48:29.437952 RX Delay -80 -> 252, step: 8
5834 06:48:29.444535 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5835 06:48:29.448028 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5836 06:48:29.451305 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5837 06:48:29.454977 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5838 06:48:29.458378 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5839 06:48:29.461481 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5840 06:48:29.464475 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5841 06:48:29.471250 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5842 06:48:29.474558 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5843 06:48:29.477748 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5844 06:48:29.481501 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5845 06:48:29.484586 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5846 06:48:29.491348 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5847 06:48:29.495247 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5848 06:48:29.498155 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5849 06:48:29.501287 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5850 06:48:29.501369 ==
5851 06:48:29.504678 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 06:48:29.508033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 06:48:29.508115 ==
5854 06:48:29.511634 DQS Delay:
5855 06:48:29.511717 DQS0 = 0, DQS1 = 0
5856 06:48:29.514770 DQM Delay:
5857 06:48:29.514851 DQM0 = 94, DQM1 = 89
5858 06:48:29.514916 DQ Delay:
5859 06:48:29.518515 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5860 06:48:29.521904 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5861 06:48:29.524782 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5862 06:48:29.528275 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5863 06:48:29.528357
5864 06:48:29.528421
5865 06:48:29.531900 ==
5866 06:48:29.531988 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 06:48:29.538650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 06:48:29.538731 ==
5869 06:48:29.538802
5870 06:48:29.538863
5871 06:48:29.541752 TX Vref Scan disable
5872 06:48:29.541829 == TX Byte 0 ==
5873 06:48:29.544900 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5874 06:48:29.551280 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5875 06:48:29.551357 == TX Byte 1 ==
5876 06:48:29.555128 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5877 06:48:29.561296 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5878 06:48:29.561372 ==
5879 06:48:29.564683 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 06:48:29.568092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 06:48:29.568197 ==
5882 06:48:29.568269
5883 06:48:29.568328
5884 06:48:29.571703 TX Vref Scan disable
5885 06:48:29.574699 == TX Byte 0 ==
5886 06:48:29.578118 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5887 06:48:29.581604 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5888 06:48:29.584905 == TX Byte 1 ==
5889 06:48:29.588342 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5890 06:48:29.591907 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5891 06:48:29.591992
5892 06:48:29.592058 [DATLAT]
5893 06:48:29.594633 Freq=933, CH1 RK1
5894 06:48:29.594715
5895 06:48:29.594780 DATLAT Default: 0xb
5896 06:48:29.598226 0, 0xFFFF, sum = 0
5897 06:48:29.601654 1, 0xFFFF, sum = 0
5898 06:48:29.601737 2, 0xFFFF, sum = 0
5899 06:48:29.604939 3, 0xFFFF, sum = 0
5900 06:48:29.605022 4, 0xFFFF, sum = 0
5901 06:48:29.608252 5, 0xFFFF, sum = 0
5902 06:48:29.608335 6, 0xFFFF, sum = 0
5903 06:48:29.611457 7, 0xFFFF, sum = 0
5904 06:48:29.611542 8, 0xFFFF, sum = 0
5905 06:48:29.615094 9, 0xFFFF, sum = 0
5906 06:48:29.615178 10, 0x0, sum = 1
5907 06:48:29.618136 11, 0x0, sum = 2
5908 06:48:29.618219 12, 0x0, sum = 3
5909 06:48:29.618285 13, 0x0, sum = 4
5910 06:48:29.621918 best_step = 11
5911 06:48:29.622000
5912 06:48:29.622065 ==
5913 06:48:29.624898 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 06:48:29.628061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 06:48:29.628145 ==
5916 06:48:29.631819 RX Vref Scan: 0
5917 06:48:29.631902
5918 06:48:29.631966 RX Vref 0 -> 0, step: 1
5919 06:48:29.632027
5920 06:48:29.635025 RX Delay -61 -> 252, step: 4
5921 06:48:29.642312 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5922 06:48:29.645668 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5923 06:48:29.649562 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5924 06:48:29.652680 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5925 06:48:29.655714 iDelay=195, Bit 4, Center 98 (7 ~ 190) 184
5926 06:48:29.659009 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5927 06:48:29.665948 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5928 06:48:29.668938 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5929 06:48:29.672607 iDelay=195, Bit 8, Center 78 (-13 ~ 170) 184
5930 06:48:29.675839 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
5931 06:48:29.679698 iDelay=195, Bit 10, Center 92 (3 ~ 182) 180
5932 06:48:29.682653 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5933 06:48:29.689268 iDelay=195, Bit 12, Center 98 (11 ~ 186) 176
5934 06:48:29.692593 iDelay=195, Bit 13, Center 100 (11 ~ 190) 180
5935 06:48:29.695884 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5936 06:48:29.699571 iDelay=195, Bit 15, Center 98 (11 ~ 186) 176
5937 06:48:29.699691 ==
5938 06:48:29.702596 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 06:48:29.709765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 06:48:29.709849 ==
5941 06:48:29.709922 DQS Delay:
5942 06:48:29.709985 DQS0 = 0, DQS1 = 0
5943 06:48:29.712681 DQM Delay:
5944 06:48:29.712757 DQM0 = 95, DQM1 = 91
5945 06:48:29.716322 DQ Delay:
5946 06:48:29.719480 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5947 06:48:29.830714 DQ4 =98, DQ5 =104, DQ6 =102, DQ7 =90
5948 06:48:29.830861 DQ8 =78, DQ9 =78, DQ10 =92, DQ11 =84
5949 06:48:29.830957 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =98
5950 06:48:29.831054
5951 06:48:29.831118
5952 06:48:29.831177 [DQSOSCAuto] RK1, (LSB)MR18= 0xd16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5953 06:48:29.831236 CH1 RK1: MR19=505, MR18=D16
5954 06:48:29.831300 CH1_RK1: MR19=0x505, MR18=0xD16, DQSOSC=414, MR23=63, INC=63, DEC=42
5955 06:48:29.831356 [RxdqsGatingPostProcess] freq 933
5956 06:48:29.831412 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5957 06:48:29.831526 best DQS0 dly(2T, 0.5T) = (0, 10)
5958 06:48:29.831586 best DQS1 dly(2T, 0.5T) = (0, 10)
5959 06:48:29.831640 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5960 06:48:29.831695 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5961 06:48:29.831749 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 06:48:29.831837 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 06:48:29.831939 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 06:48:29.832024 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 06:48:29.832117 Pre-setting of DQS Precalculation
5966 06:48:29.832198 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5967 06:48:29.832273 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5968 06:48:29.832331 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5969 06:48:29.832394
5970 06:48:29.832449
5971 06:48:29.832503 [Calibration Summary] 1866 Mbps
5972 06:48:29.832558 CH 0, Rank 0
5973 06:48:29.832611 SW Impedance : PASS
5974 06:48:29.832672 DUTY Scan : NO K
5975 06:48:29.832725 ZQ Calibration : PASS
5976 06:48:29.832779 Jitter Meter : NO K
5977 06:48:29.832832 CBT Training : PASS
5978 06:48:29.832886 Write leveling : PASS
5979 06:48:29.832946 RX DQS gating : PASS
5980 06:48:29.833000 RX DQ/DQS(RDDQC) : PASS
5981 06:48:29.833053 TX DQ/DQS : PASS
5982 06:48:29.833107 RX DATLAT : PASS
5983 06:48:29.833160 RX DQ/DQS(Engine): PASS
5984 06:48:29.833410 TX OE : NO K
5985 06:48:29.833476 All Pass.
5986 06:48:29.833531
5987 06:48:29.833585 CH 0, Rank 1
5988 06:48:29.836110 SW Impedance : PASS
5989 06:48:29.839270 DUTY Scan : NO K
5990 06:48:29.839361 ZQ Calibration : PASS
5991 06:48:29.843177 Jitter Meter : NO K
5992 06:48:29.843274 CBT Training : PASS
5993 06:48:29.846143 Write leveling : PASS
5994 06:48:29.849361 RX DQS gating : PASS
5995 06:48:29.849453 RX DQ/DQS(RDDQC) : PASS
5996 06:48:29.852620 TX DQ/DQS : PASS
5997 06:48:29.856279 RX DATLAT : PASS
5998 06:48:29.856371 RX DQ/DQS(Engine): PASS
5999 06:48:29.859377 TX OE : NO K
6000 06:48:29.859464 All Pass.
6001 06:48:29.859538
6002 06:48:29.863009 CH 1, Rank 0
6003 06:48:29.863100 SW Impedance : PASS
6004 06:48:29.866262 DUTY Scan : NO K
6005 06:48:29.869514 ZQ Calibration : PASS
6006 06:48:29.869602 Jitter Meter : NO K
6007 06:48:29.872810 CBT Training : PASS
6008 06:48:29.876657 Write leveling : PASS
6009 06:48:29.876752 RX DQS gating : PASS
6010 06:48:29.879705 RX DQ/DQS(RDDQC) : PASS
6011 06:48:29.879829 TX DQ/DQS : PASS
6012 06:48:29.882700 RX DATLAT : PASS
6013 06:48:29.886694 RX DQ/DQS(Engine): PASS
6014 06:48:29.886793 TX OE : NO K
6015 06:48:29.889657 All Pass.
6016 06:48:29.889775
6017 06:48:29.889866 CH 1, Rank 1
6018 06:48:29.893268 SW Impedance : PASS
6019 06:48:29.893388 DUTY Scan : NO K
6020 06:48:29.896636 ZQ Calibration : PASS
6021 06:48:29.899662 Jitter Meter : NO K
6022 06:48:29.899810 CBT Training : PASS
6023 06:48:29.902893 Write leveling : PASS
6024 06:48:29.906776 RX DQS gating : PASS
6025 06:48:29.906939 RX DQ/DQS(RDDQC) : PASS
6026 06:48:29.909791 TX DQ/DQS : PASS
6027 06:48:29.912955 RX DATLAT : PASS
6028 06:48:29.913239 RX DQ/DQS(Engine): PASS
6029 06:48:29.916930 TX OE : NO K
6030 06:48:29.917140 All Pass.
6031 06:48:29.917336
6032 06:48:29.919992 DramC Write-DBI off
6033 06:48:29.923680 PER_BANK_REFRESH: Hybrid Mode
6034 06:48:29.924168 TX_TRACKING: ON
6035 06:48:29.933511 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6036 06:48:29.936846 [FAST_K] Save calibration result to emmc
6037 06:48:29.940010 dramc_set_vcore_voltage set vcore to 650000
6038 06:48:29.943159 Read voltage for 400, 6
6039 06:48:29.943575 Vio18 = 0
6040 06:48:29.943914 Vcore = 650000
6041 06:48:29.946793 Vdram = 0
6042 06:48:29.947196 Vddq = 0
6043 06:48:29.947294 Vmddr = 0
6044 06:48:29.952876 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6045 06:48:29.956672 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6046 06:48:29.959678 MEM_TYPE=3, freq_sel=20
6047 06:48:29.962796 sv_algorithm_assistance_LP4_800
6048 06:48:29.966816 ============ PULL DRAM RESETB DOWN ============
6049 06:48:29.970126 ========== PULL DRAM RESETB DOWN end =========
6050 06:48:29.976491 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6051 06:48:29.979601 ===================================
6052 06:48:29.979683 LPDDR4 DRAM CONFIGURATION
6053 06:48:29.983149 ===================================
6054 06:48:29.986379 EX_ROW_EN[0] = 0x0
6055 06:48:29.986528 EX_ROW_EN[1] = 0x0
6056 06:48:29.989531 LP4Y_EN = 0x0
6057 06:48:29.989611 WORK_FSP = 0x0
6058 06:48:29.993359 WL = 0x2
6059 06:48:29.993433 RL = 0x2
6060 06:48:29.996524 BL = 0x2
6061 06:48:30.000191 RPST = 0x0
6062 06:48:30.000262 RD_PRE = 0x0
6063 06:48:30.003081 WR_PRE = 0x1
6064 06:48:30.003160 WR_PST = 0x0
6065 06:48:30.006686 DBI_WR = 0x0
6066 06:48:30.006759 DBI_RD = 0x0
6067 06:48:30.009707 OTF = 0x1
6068 06:48:30.013398 ===================================
6069 06:48:30.016501 ===================================
6070 06:48:30.016578 ANA top config
6071 06:48:30.019812 ===================================
6072 06:48:30.023537 DLL_ASYNC_EN = 0
6073 06:48:30.023655 ALL_SLAVE_EN = 1
6074 06:48:30.026725 NEW_RANK_MODE = 1
6075 06:48:30.029852 DLL_IDLE_MODE = 1
6076 06:48:30.033071 LP45_APHY_COMB_EN = 1
6077 06:48:30.036716 TX_ODT_DIS = 1
6078 06:48:30.036794 NEW_8X_MODE = 1
6079 06:48:30.039867 ===================================
6080 06:48:30.043660 ===================================
6081 06:48:30.046599 data_rate = 800
6082 06:48:30.050058 CKR = 1
6083 06:48:30.053185 DQ_P2S_RATIO = 4
6084 06:48:30.056857 ===================================
6085 06:48:30.059770 CA_P2S_RATIO = 4
6086 06:48:30.063641 DQ_CA_OPEN = 0
6087 06:48:30.063720 DQ_SEMI_OPEN = 1
6088 06:48:30.066910 CA_SEMI_OPEN = 1
6089 06:48:30.070056 CA_FULL_RATE = 0
6090 06:48:30.073089 DQ_CKDIV4_EN = 0
6091 06:48:30.076970 CA_CKDIV4_EN = 1
6092 06:48:30.077049 CA_PREDIV_EN = 0
6093 06:48:30.080154 PH8_DLY = 0
6094 06:48:30.083353 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6095 06:48:30.087078 DQ_AAMCK_DIV = 0
6096 06:48:30.089858 CA_AAMCK_DIV = 0
6097 06:48:30.093127 CA_ADMCK_DIV = 4
6098 06:48:30.093233 DQ_TRACK_CA_EN = 0
6099 06:48:30.096535 CA_PICK = 800
6100 06:48:30.100491 CA_MCKIO = 400
6101 06:48:30.103656 MCKIO_SEMI = 400
6102 06:48:30.106688 PLL_FREQ = 3016
6103 06:48:30.110546 DQ_UI_PI_RATIO = 32
6104 06:48:30.114154 CA_UI_PI_RATIO = 32
6105 06:48:30.117080 ===================================
6106 06:48:30.120498 ===================================
6107 06:48:30.120569 memory_type:LPDDR4
6108 06:48:30.123837 GP_NUM : 10
6109 06:48:30.126894 SRAM_EN : 1
6110 06:48:30.126967 MD32_EN : 0
6111 06:48:30.129913 ===================================
6112 06:48:30.133253 [ANA_INIT] >>>>>>>>>>>>>>
6113 06:48:30.137081 <<<<<< [CONFIGURE PHASE]: ANA_TX
6114 06:48:30.140068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6115 06:48:30.143250 ===================================
6116 06:48:30.147061 data_rate = 800,PCW = 0X7400
6117 06:48:30.150132 ===================================
6118 06:48:30.153697 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6119 06:48:30.156743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6120 06:48:30.170070 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6121 06:48:30.173801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6122 06:48:30.176717 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6123 06:48:30.179969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6124 06:48:30.183810 [ANA_INIT] flow start
6125 06:48:30.183892 [ANA_INIT] PLL >>>>>>>>
6126 06:48:30.186966 [ANA_INIT] PLL <<<<<<<<
6127 06:48:30.190214 [ANA_INIT] MIDPI >>>>>>>>
6128 06:48:30.190330 [ANA_INIT] MIDPI <<<<<<<<
6129 06:48:30.193434 [ANA_INIT] DLL >>>>>>>>
6130 06:48:30.197119 [ANA_INIT] flow end
6131 06:48:30.200375 ============ LP4 DIFF to SE enter ============
6132 06:48:30.203831 ============ LP4 DIFF to SE exit ============
6133 06:48:30.207103 [ANA_INIT] <<<<<<<<<<<<<
6134 06:48:30.209924 [Flow] Enable top DCM control >>>>>
6135 06:48:30.213687 [Flow] Enable top DCM control <<<<<
6136 06:48:30.217033 Enable DLL master slave shuffle
6137 06:48:30.220432 ==============================================================
6138 06:48:30.223780 Gating Mode config
6139 06:48:30.230225 ==============================================================
6140 06:48:30.230338 Config description:
6141 06:48:30.240405 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6142 06:48:30.247417 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6143 06:48:30.250491 SELPH_MODE 0: By rank 1: By Phase
6144 06:48:30.256867 ==============================================================
6145 06:48:30.260899 GAT_TRACK_EN = 0
6146 06:48:30.263815 RX_GATING_MODE = 2
6147 06:48:30.267077 RX_GATING_TRACK_MODE = 2
6148 06:48:30.270151 SELPH_MODE = 1
6149 06:48:30.273618 PICG_EARLY_EN = 1
6150 06:48:30.273708 VALID_LAT_VALUE = 1
6151 06:48:30.280529 ==============================================================
6152 06:48:30.283686 Enter into Gating configuration >>>>
6153 06:48:30.287282 Exit from Gating configuration <<<<
6154 06:48:30.290137 Enter into DVFS_PRE_config >>>>>
6155 06:48:30.300375 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6156 06:48:30.303626 Exit from DVFS_PRE_config <<<<<
6157 06:48:30.307439 Enter into PICG configuration >>>>
6158 06:48:30.310199 Exit from PICG configuration <<<<
6159 06:48:30.313827 [RX_INPUT] configuration >>>>>
6160 06:48:30.317149 [RX_INPUT] configuration <<<<<
6161 06:48:30.320344 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6162 06:48:30.327218 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6163 06:48:30.333649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 06:48:30.340590 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 06:48:30.346978 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6166 06:48:30.350302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6167 06:48:30.357437 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6168 06:48:30.360407 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6169 06:48:30.363650 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6170 06:48:30.366691 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6171 06:48:30.373613 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6172 06:48:30.376808 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6173 06:48:30.380517 ===================================
6174 06:48:30.383451 LPDDR4 DRAM CONFIGURATION
6175 06:48:30.386769 ===================================
6176 06:48:30.386868 EX_ROW_EN[0] = 0x0
6177 06:48:30.390776 EX_ROW_EN[1] = 0x0
6178 06:48:30.390868 LP4Y_EN = 0x0
6179 06:48:30.394092 WORK_FSP = 0x0
6180 06:48:30.394185 WL = 0x2
6181 06:48:30.397152 RL = 0x2
6182 06:48:30.397239 BL = 0x2
6183 06:48:30.400558 RPST = 0x0
6184 06:48:30.400644 RD_PRE = 0x0
6185 06:48:30.403823 WR_PRE = 0x1
6186 06:48:30.403910 WR_PST = 0x0
6187 06:48:30.407082 DBI_WR = 0x0
6188 06:48:30.410235 DBI_RD = 0x0
6189 06:48:30.410343 OTF = 0x1
6190 06:48:30.413432 ===================================
6191 06:48:30.417150 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6192 06:48:30.420685 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6193 06:48:30.426838 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 06:48:30.430179 ===================================
6195 06:48:30.433791 LPDDR4 DRAM CONFIGURATION
6196 06:48:30.433899 ===================================
6197 06:48:30.436718 EX_ROW_EN[0] = 0x10
6198 06:48:30.440211 EX_ROW_EN[1] = 0x0
6199 06:48:30.440320 LP4Y_EN = 0x0
6200 06:48:30.443819 WORK_FSP = 0x0
6201 06:48:30.443903 WL = 0x2
6202 06:48:30.446882 RL = 0x2
6203 06:48:30.446966 BL = 0x2
6204 06:48:30.450663 RPST = 0x0
6205 06:48:30.450747 RD_PRE = 0x0
6206 06:48:30.453569 WR_PRE = 0x1
6207 06:48:30.453655 WR_PST = 0x0
6208 06:48:30.457159 DBI_WR = 0x0
6209 06:48:30.457246 DBI_RD = 0x0
6210 06:48:30.460543 OTF = 0x1
6211 06:48:30.464288 ===================================
6212 06:48:30.470628 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6213 06:48:30.474209 nWR fixed to 30
6214 06:48:30.474323 [ModeRegInit_LP4] CH0 RK0
6215 06:48:30.477357 [ModeRegInit_LP4] CH0 RK1
6216 06:48:30.480710 [ModeRegInit_LP4] CH1 RK0
6217 06:48:30.483523 [ModeRegInit_LP4] CH1 RK1
6218 06:48:30.483635 match AC timing 19
6219 06:48:30.490418 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6220 06:48:30.494062 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6221 06:48:30.497046 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6222 06:48:30.504444 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6223 06:48:30.507311 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6224 06:48:30.507395 ==
6225 06:48:30.510295 Dram Type= 6, Freq= 0, CH_0, rank 0
6226 06:48:30.513459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6227 06:48:30.513564 ==
6228 06:48:30.520225 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6229 06:48:30.526902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6230 06:48:30.530700 [CA 0] Center 36 (8~64) winsize 57
6231 06:48:30.530786 [CA 1] Center 36 (8~64) winsize 57
6232 06:48:30.533725 [CA 2] Center 36 (8~64) winsize 57
6233 06:48:30.537269 [CA 3] Center 36 (8~64) winsize 57
6234 06:48:30.540226 [CA 4] Center 36 (8~64) winsize 57
6235 06:48:30.543542 [CA 5] Center 36 (8~64) winsize 57
6236 06:48:30.543641
6237 06:48:30.547111 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6238 06:48:30.547196
6239 06:48:30.550608 [CATrainingPosCal] consider 1 rank data
6240 06:48:30.553702 u2DelayCellTimex100 = 270/100 ps
6241 06:48:30.556868 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 06:48:30.560496 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 06:48:30.567062 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 06:48:30.570704 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 06:48:30.573926 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 06:48:30.576961 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 06:48:30.577049
6248 06:48:30.580191 CA PerBit enable=1, Macro0, CA PI delay=36
6249 06:48:30.580275
6250 06:48:30.583422 [CBTSetCACLKResult] CA Dly = 36
6251 06:48:30.583539 CS Dly: 1 (0~32)
6252 06:48:30.583644 ==
6253 06:48:30.587025 Dram Type= 6, Freq= 0, CH_0, rank 1
6254 06:48:30.593659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 06:48:30.593773 ==
6256 06:48:30.597487 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6257 06:48:30.603597 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6258 06:48:30.606894 [CA 0] Center 36 (8~64) winsize 57
6259 06:48:30.610382 [CA 1] Center 36 (8~64) winsize 57
6260 06:48:30.613730 [CA 2] Center 36 (8~64) winsize 57
6261 06:48:30.617047 [CA 3] Center 36 (8~64) winsize 57
6262 06:48:30.620498 [CA 4] Center 36 (8~64) winsize 57
6263 06:48:30.623831 [CA 5] Center 36 (8~64) winsize 57
6264 06:48:30.623918
6265 06:48:30.627229 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6266 06:48:30.627305
6267 06:48:30.630752 [CATrainingPosCal] consider 2 rank data
6268 06:48:30.634082 u2DelayCellTimex100 = 270/100 ps
6269 06:48:30.637606 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 06:48:30.640927 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 06:48:30.643520 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 06:48:30.647647 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 06:48:30.650354 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 06:48:30.654203 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 06:48:30.654315
6276 06:48:30.660311 CA PerBit enable=1, Macro0, CA PI delay=36
6277 06:48:30.660396
6278 06:48:30.663646 [CBTSetCACLKResult] CA Dly = 36
6279 06:48:30.663727 CS Dly: 1 (0~32)
6280 06:48:30.663794
6281 06:48:30.667109 ----->DramcWriteLeveling(PI) begin...
6282 06:48:30.667210 ==
6283 06:48:30.670198 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 06:48:30.673809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 06:48:30.673919 ==
6286 06:48:30.677063 Write leveling (Byte 0): 40 => 8
6287 06:48:30.680719 Write leveling (Byte 1): 32 => 0
6288 06:48:30.683687 DramcWriteLeveling(PI) end<-----
6289 06:48:30.683789
6290 06:48:30.683881 ==
6291 06:48:30.686964 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 06:48:30.690657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 06:48:30.690756 ==
6294 06:48:30.693865 [Gating] SW mode calibration
6295 06:48:30.700688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6296 06:48:30.707793 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6297 06:48:30.711045 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6298 06:48:30.717209 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6299 06:48:30.721025 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 06:48:30.724013 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 06:48:30.730454 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 06:48:30.734652 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 06:48:30.737161 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 06:48:30.740821 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 06:48:30.747277 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 06:48:30.750729 Total UI for P1: 0, mck2ui 16
6307 06:48:30.754494 best dqsien dly found for B0: ( 0, 14, 24)
6308 06:48:30.757218 Total UI for P1: 0, mck2ui 16
6309 06:48:30.760837 best dqsien dly found for B1: ( 0, 14, 24)
6310 06:48:30.763862 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6311 06:48:30.767167 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6312 06:48:30.767270
6313 06:48:30.770850 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6314 06:48:30.774055 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6315 06:48:30.777840 [Gating] SW calibration Done
6316 06:48:30.777929 ==
6317 06:48:30.780814 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 06:48:30.783765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 06:48:30.783869 ==
6320 06:48:30.787363 RX Vref Scan: 0
6321 06:48:30.787466
6322 06:48:30.790246 RX Vref 0 -> 0, step: 1
6323 06:48:30.790347
6324 06:48:30.790463 RX Delay -410 -> 252, step: 16
6325 06:48:30.796934 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6326 06:48:30.800611 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6327 06:48:30.803550 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6328 06:48:30.807058 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6329 06:48:30.813873 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6330 06:48:30.817177 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6331 06:48:30.820816 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6332 06:48:30.826732 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6333 06:48:30.830568 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6334 06:48:30.833656 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6335 06:48:30.836649 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6336 06:48:30.843606 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6337 06:48:30.846958 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6338 06:48:30.850032 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6339 06:48:30.853560 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6340 06:48:30.860027 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6341 06:48:30.860138 ==
6342 06:48:30.864002 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 06:48:30.866888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 06:48:30.867008 ==
6345 06:48:30.867104 DQS Delay:
6346 06:48:30.870040 DQS0 = 35, DQS1 = 51
6347 06:48:30.870118 DQM Delay:
6348 06:48:30.873286 DQM0 = 8, DQM1 = 11
6349 06:48:30.873388 DQ Delay:
6350 06:48:30.876914 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6351 06:48:30.880302 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6352 06:48:30.883621 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6353 06:48:30.886856 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6354 06:48:30.886936
6355 06:48:30.887000
6356 06:48:30.887085 ==
6357 06:48:30.889872 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 06:48:30.893521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 06:48:30.893608 ==
6360 06:48:30.893674
6361 06:48:30.893735
6362 06:48:30.896969 TX Vref Scan disable
6363 06:48:30.897052 == TX Byte 0 ==
6364 06:48:30.903861 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 06:48:30.906909 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 06:48:30.906992 == TX Byte 1 ==
6367 06:48:30.913404 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6368 06:48:30.916658 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6369 06:48:30.916752 ==
6370 06:48:30.920414 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 06:48:30.923823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 06:48:30.923907 ==
6373 06:48:30.923972
6374 06:48:30.924033
6375 06:48:30.926767 TX Vref Scan disable
6376 06:48:30.926849 == TX Byte 0 ==
6377 06:48:30.933819 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 06:48:30.937257 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 06:48:30.937340 == TX Byte 1 ==
6380 06:48:30.943645 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6381 06:48:30.946530 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6382 06:48:30.946608
6383 06:48:30.946672 [DATLAT]
6384 06:48:30.950413 Freq=400, CH0 RK0
6385 06:48:30.950507
6386 06:48:30.950571 DATLAT Default: 0xf
6387 06:48:30.953383 0, 0xFFFF, sum = 0
6388 06:48:30.953473 1, 0xFFFF, sum = 0
6389 06:48:30.957435 2, 0xFFFF, sum = 0
6390 06:48:30.957512 3, 0xFFFF, sum = 0
6391 06:48:30.960586 4, 0xFFFF, sum = 0
6392 06:48:30.960672 5, 0xFFFF, sum = 0
6393 06:48:30.963355 6, 0xFFFF, sum = 0
6394 06:48:30.966590 7, 0xFFFF, sum = 0
6395 06:48:30.966711 8, 0xFFFF, sum = 0
6396 06:48:30.970025 9, 0xFFFF, sum = 0
6397 06:48:30.970100 10, 0xFFFF, sum = 0
6398 06:48:30.973485 11, 0xFFFF, sum = 0
6399 06:48:30.973565 12, 0xFFFF, sum = 0
6400 06:48:30.976574 13, 0x0, sum = 1
6401 06:48:30.976657 14, 0x0, sum = 2
6402 06:48:30.980282 15, 0x0, sum = 3
6403 06:48:30.980381 16, 0x0, sum = 4
6404 06:48:30.980450 best_step = 14
6405 06:48:30.980511
6406 06:48:30.983718 ==
6407 06:48:30.986758 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 06:48:30.990588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 06:48:30.990672 ==
6410 06:48:30.990738 RX Vref Scan: 1
6411 06:48:30.990799
6412 06:48:30.993323 RX Vref 0 -> 0, step: 1
6413 06:48:30.993405
6414 06:48:30.997065 RX Delay -343 -> 252, step: 8
6415 06:48:30.997147
6416 06:48:31.000498 Set Vref, RX VrefLevel [Byte0]: 54
6417 06:48:31.003464 [Byte1]: 50
6418 06:48:31.007478
6419 06:48:31.007577 Final RX Vref Byte 0 = 54 to rank0
6420 06:48:31.010722 Final RX Vref Byte 1 = 50 to rank0
6421 06:48:31.013998 Final RX Vref Byte 0 = 54 to rank1
6422 06:48:31.017136 Final RX Vref Byte 1 = 50 to rank1==
6423 06:48:31.020386 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 06:48:31.024194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 06:48:31.027410 ==
6426 06:48:31.027503 DQS Delay:
6427 06:48:31.027568 DQS0 = 44, DQS1 = 60
6428 06:48:31.030494 DQM Delay:
6429 06:48:31.030576 DQM0 = 11, DQM1 = 15
6430 06:48:31.033658 DQ Delay:
6431 06:48:31.037199 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6432 06:48:31.037282 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6433 06:48:31.040969 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6434 06:48:31.044284 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6435 06:48:31.044366
6436 06:48:31.044440
6437 06:48:31.053913 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6438 06:48:31.057237 CH0 RK0: MR19=C0C, MR18=8B59
6439 06:48:31.064281 CH0_RK0: MR19=0xC0C, MR18=0x8B59, DQSOSC=392, MR23=63, INC=384, DEC=256
6440 06:48:31.064359 ==
6441 06:48:31.067583 Dram Type= 6, Freq= 0, CH_0, rank 1
6442 06:48:31.070570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 06:48:31.070653 ==
6444 06:48:31.074329 [Gating] SW mode calibration
6445 06:48:31.080954 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6446 06:48:31.084394 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6447 06:48:31.090555 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6448 06:48:31.094097 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 06:48:31.097642 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 06:48:31.104114 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 06:48:31.107620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 06:48:31.110992 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 06:48:31.117424 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 06:48:31.121026 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 06:48:31.124129 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 06:48:31.127383 Total UI for P1: 0, mck2ui 16
6457 06:48:31.130845 best dqsien dly found for B0: ( 0, 14, 24)
6458 06:48:31.134412 Total UI for P1: 0, mck2ui 16
6459 06:48:31.137820 best dqsien dly found for B1: ( 0, 14, 24)
6460 06:48:31.141085 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6461 06:48:31.144260 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6462 06:48:31.144343
6463 06:48:31.147304 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6464 06:48:31.153929 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6465 06:48:31.154012 [Gating] SW calibration Done
6466 06:48:31.154076 ==
6467 06:48:31.157299 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 06:48:31.164375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 06:48:31.164457 ==
6470 06:48:31.164522 RX Vref Scan: 0
6471 06:48:31.164581
6472 06:48:31.167597 RX Vref 0 -> 0, step: 1
6473 06:48:31.167679
6474 06:48:31.170975 RX Delay -410 -> 252, step: 16
6475 06:48:31.174594 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6476 06:48:31.177340 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6477 06:48:31.184282 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6478 06:48:31.187454 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6479 06:48:31.190681 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6480 06:48:31.194574 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6481 06:48:31.200446 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6482 06:48:31.204317 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6483 06:48:31.207657 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6484 06:48:31.210821 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6485 06:48:31.217396 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6486 06:48:31.220813 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6487 06:48:31.224332 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6488 06:48:31.227471 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6489 06:48:31.234449 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6490 06:48:31.237705 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6491 06:48:31.237788 ==
6492 06:48:31.240786 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 06:48:31.244053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 06:48:31.244167 ==
6495 06:48:31.247793 DQS Delay:
6496 06:48:31.247876 DQS0 = 43, DQS1 = 51
6497 06:48:31.247941 DQM Delay:
6498 06:48:31.251065 DQM0 = 11, DQM1 = 10
6499 06:48:31.251194 DQ Delay:
6500 06:48:31.254267 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6501 06:48:31.257365 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6502 06:48:31.260514 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6503 06:48:31.264030 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6504 06:48:31.264146
6505 06:48:31.264210
6506 06:48:31.264270 ==
6507 06:48:31.267276 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 06:48:31.270829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 06:48:31.270912 ==
6510 06:48:31.274160
6511 06:48:31.274256
6512 06:48:31.274321 TX Vref Scan disable
6513 06:48:31.277343 == TX Byte 0 ==
6514 06:48:31.280588 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6515 06:48:31.284523 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6516 06:48:31.287235 == TX Byte 1 ==
6517 06:48:31.290418 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6518 06:48:31.293809 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6519 06:48:31.293907 ==
6520 06:48:31.297648 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 06:48:31.300789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 06:48:31.300900 ==
6523 06:48:31.304008
6524 06:48:31.304120
6525 06:48:31.304211 TX Vref Scan disable
6526 06:48:31.307519 == TX Byte 0 ==
6527 06:48:31.310593 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6528 06:48:31.314243 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6529 06:48:31.317503 == TX Byte 1 ==
6530 06:48:31.321309 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6531 06:48:31.324412 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6532 06:48:31.324495
6533 06:48:31.324559 [DATLAT]
6534 06:48:31.327765 Freq=400, CH0 RK1
6535 06:48:31.327861
6536 06:48:31.327926 DATLAT Default: 0xe
6537 06:48:31.330841 0, 0xFFFF, sum = 0
6538 06:48:31.330942 1, 0xFFFF, sum = 0
6539 06:48:31.334436 2, 0xFFFF, sum = 0
6540 06:48:31.334533 3, 0xFFFF, sum = 0
6541 06:48:31.337699 4, 0xFFFF, sum = 0
6542 06:48:31.340664 5, 0xFFFF, sum = 0
6543 06:48:31.340776 6, 0xFFFF, sum = 0
6544 06:48:31.344216 7, 0xFFFF, sum = 0
6545 06:48:31.344309 8, 0xFFFF, sum = 0
6546 06:48:31.347557 9, 0xFFFF, sum = 0
6547 06:48:31.347670 10, 0xFFFF, sum = 0
6548 06:48:31.350865 11, 0xFFFF, sum = 0
6549 06:48:31.350951 12, 0xFFFF, sum = 0
6550 06:48:31.354520 13, 0x0, sum = 1
6551 06:48:31.354606 14, 0x0, sum = 2
6552 06:48:31.357817 15, 0x0, sum = 3
6553 06:48:31.357906 16, 0x0, sum = 4
6554 06:48:31.357982 best_step = 14
6555 06:48:31.360884
6556 06:48:31.360996 ==
6557 06:48:31.364233 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 06:48:31.367568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 06:48:31.367645 ==
6560 06:48:31.367710 RX Vref Scan: 0
6561 06:48:31.367776
6562 06:48:31.371374 RX Vref 0 -> 0, step: 1
6563 06:48:31.371470
6564 06:48:31.373999 RX Delay -343 -> 252, step: 8
6565 06:48:31.381367 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6566 06:48:31.384990 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6567 06:48:31.388350 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6568 06:48:31.391388 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6569 06:48:31.398071 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6570 06:48:31.401340 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6571 06:48:31.405348 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6572 06:48:31.408132 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6573 06:48:31.415056 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6574 06:48:31.418222 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6575 06:48:31.421542 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6576 06:48:31.424690 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6577 06:48:31.431838 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6578 06:48:31.434695 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6579 06:48:31.437916 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6580 06:48:31.441626 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6581 06:48:31.444536 ==
6582 06:48:31.448145 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 06:48:31.451432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 06:48:31.451542 ==
6585 06:48:31.451646 DQS Delay:
6586 06:48:31.455140 DQS0 = 48, DQS1 = 60
6587 06:48:31.455246 DQM Delay:
6588 06:48:31.458418 DQM0 = 13, DQM1 = 13
6589 06:48:31.458524 DQ Delay:
6590 06:48:31.461211 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6591 06:48:31.464811 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6592 06:48:31.468115 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6593 06:48:31.471630 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6594 06:48:31.471715
6595 06:48:31.471781
6596 06:48:31.478361 [DQSOSCAuto] RK1, (LSB)MR18= 0x976a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6597 06:48:31.481842 CH0 RK1: MR19=C0C, MR18=976A
6598 06:48:31.488883 CH0_RK1: MR19=0xC0C, MR18=0x976A, DQSOSC=390, MR23=63, INC=388, DEC=258
6599 06:48:31.491611 [RxdqsGatingPostProcess] freq 400
6600 06:48:31.494371 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6601 06:48:31.498118 best DQS0 dly(2T, 0.5T) = (0, 10)
6602 06:48:31.501392 best DQS1 dly(2T, 0.5T) = (0, 10)
6603 06:48:31.505128 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6604 06:48:31.507779 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6605 06:48:31.511757 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 06:48:31.514941 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 06:48:31.517916 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 06:48:31.521640 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 06:48:31.524859 Pre-setting of DQS Precalculation
6610 06:48:31.528275 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6611 06:48:31.528387 ==
6612 06:48:31.531390 Dram Type= 6, Freq= 0, CH_1, rank 0
6613 06:48:31.538090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 06:48:31.538204 ==
6615 06:48:31.541822 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6616 06:48:31.548153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6617 06:48:31.551880 [CA 0] Center 36 (8~64) winsize 57
6618 06:48:31.554793 [CA 1] Center 36 (8~64) winsize 57
6619 06:48:31.558299 [CA 2] Center 36 (8~64) winsize 57
6620 06:48:31.562157 [CA 3] Center 36 (8~64) winsize 57
6621 06:48:31.565061 [CA 4] Center 36 (8~64) winsize 57
6622 06:48:31.568656 [CA 5] Center 36 (8~64) winsize 57
6623 06:48:31.568759
6624 06:48:31.571918 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6625 06:48:31.572117
6626 06:48:31.575073 [CATrainingPosCal] consider 1 rank data
6627 06:48:31.578183 u2DelayCellTimex100 = 270/100 ps
6628 06:48:31.581839 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 06:48:31.585506 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 06:48:31.588571 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 06:48:31.591863 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 06:48:31.594892 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 06:48:31.598552 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 06:48:31.598632
6635 06:48:31.605405 CA PerBit enable=1, Macro0, CA PI delay=36
6636 06:48:31.605514
6637 06:48:31.605599 [CBTSetCACLKResult] CA Dly = 36
6638 06:48:31.608222 CS Dly: 1 (0~32)
6639 06:48:31.608325 ==
6640 06:48:31.612201 Dram Type= 6, Freq= 0, CH_1, rank 1
6641 06:48:31.615216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 06:48:31.615336 ==
6643 06:48:31.621769 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6644 06:48:31.628296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6645 06:48:31.631613 [CA 0] Center 36 (8~64) winsize 57
6646 06:48:31.635172 [CA 1] Center 36 (8~64) winsize 57
6647 06:48:31.638371 [CA 2] Center 36 (8~64) winsize 57
6648 06:48:31.638467 [CA 3] Center 36 (8~64) winsize 57
6649 06:48:31.641641 [CA 4] Center 36 (8~64) winsize 57
6650 06:48:31.645303 [CA 5] Center 36 (8~64) winsize 57
6651 06:48:31.645386
6652 06:48:31.648262 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6653 06:48:31.652253
6654 06:48:31.654882 [CATrainingPosCal] consider 2 rank data
6655 06:48:31.654951 u2DelayCellTimex100 = 270/100 ps
6656 06:48:31.661736 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 06:48:31.665183 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 06:48:31.668179 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 06:48:31.671966 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 06:48:31.674925 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 06:48:31.678581 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 06:48:31.678661
6663 06:48:31.681936 CA PerBit enable=1, Macro0, CA PI delay=36
6664 06:48:31.682015
6665 06:48:31.685246 [CBTSetCACLKResult] CA Dly = 36
6666 06:48:31.688207 CS Dly: 1 (0~32)
6667 06:48:31.688287
6668 06:48:31.692183 ----->DramcWriteLeveling(PI) begin...
6669 06:48:31.692264 ==
6670 06:48:31.695240 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 06:48:31.698577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 06:48:31.698651 ==
6673 06:48:31.702146 Write leveling (Byte 0): 40 => 8
6674 06:48:31.704997 Write leveling (Byte 1): 40 => 8
6675 06:48:31.708709 DramcWriteLeveling(PI) end<-----
6676 06:48:31.708791
6677 06:48:31.708853 ==
6678 06:48:31.711981 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 06:48:31.715351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 06:48:31.715422 ==
6681 06:48:31.718504 [Gating] SW mode calibration
6682 06:48:31.725379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6683 06:48:31.732131 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6684 06:48:31.735246 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6685 06:48:31.738327 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6686 06:48:31.742070 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 06:48:31.748441 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 06:48:31.751668 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 06:48:31.755231 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 06:48:31.761632 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 06:48:31.765255 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 06:48:31.768415 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 06:48:31.771850 Total UI for P1: 0, mck2ui 16
6694 06:48:31.775461 best dqsien dly found for B0: ( 0, 14, 24)
6695 06:48:31.778570 Total UI for P1: 0, mck2ui 16
6696 06:48:31.781801 best dqsien dly found for B1: ( 0, 14, 24)
6697 06:48:31.784900 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6698 06:48:31.788521 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6699 06:48:31.791848
6700 06:48:31.795170 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6701 06:48:31.799071 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6702 06:48:31.801484 [Gating] SW calibration Done
6703 06:48:31.801558 ==
6704 06:48:31.805234 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 06:48:31.808418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 06:48:31.808499 ==
6707 06:48:31.808562 RX Vref Scan: 0
6708 06:48:31.808627
6709 06:48:31.811528 RX Vref 0 -> 0, step: 1
6710 06:48:31.811609
6711 06:48:31.814789 RX Delay -410 -> 252, step: 16
6712 06:48:31.818253 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6713 06:48:31.825132 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6714 06:48:31.828607 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6715 06:48:31.831816 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6716 06:48:31.835265 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6717 06:48:31.841796 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6718 06:48:31.845263 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6719 06:48:31.848230 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6720 06:48:31.851805 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6721 06:48:31.854907 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6722 06:48:31.861693 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6723 06:48:31.865320 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6724 06:48:31.868170 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6725 06:48:31.875206 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6726 06:48:31.878603 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6727 06:48:31.882137 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6728 06:48:31.882212 ==
6729 06:48:31.885204 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 06:48:31.888954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 06:48:31.889037 ==
6732 06:48:31.892197 DQS Delay:
6733 06:48:31.892280 DQS0 = 51, DQS1 = 59
6734 06:48:31.895302 DQM Delay:
6735 06:48:31.895386 DQM0 = 19, DQM1 = 16
6736 06:48:31.898337 DQ Delay:
6737 06:48:31.898475 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6738 06:48:31.902265 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6739 06:48:31.905305 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6740 06:48:31.908646 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6741 06:48:31.908729
6742 06:48:31.908813
6743 06:48:31.911825 ==
6744 06:48:31.911909 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 06:48:31.918768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 06:48:31.918853 ==
6747 06:48:31.918937
6748 06:48:31.919016
6749 06:48:31.921678 TX Vref Scan disable
6750 06:48:31.921785 == TX Byte 0 ==
6751 06:48:31.924986 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 06:48:31.932103 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 06:48:31.932186 == TX Byte 1 ==
6754 06:48:31.935129 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 06:48:31.941448 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 06:48:31.941532 ==
6757 06:48:31.945088 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 06:48:31.948679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 06:48:31.948764 ==
6760 06:48:31.948884
6761 06:48:31.948980
6762 06:48:31.951796 TX Vref Scan disable
6763 06:48:31.951880 == TX Byte 0 ==
6764 06:48:31.955234 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 06:48:31.962034 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 06:48:31.962149 == TX Byte 1 ==
6767 06:48:31.964877 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 06:48:31.968547 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 06:48:31.968697
6770 06:48:31.971724 [DATLAT]
6771 06:48:31.971830 Freq=400, CH1 RK0
6772 06:48:31.971959
6773 06:48:31.975268 DATLAT Default: 0xf
6774 06:48:31.975375 0, 0xFFFF, sum = 0
6775 06:48:31.979024 1, 0xFFFF, sum = 0
6776 06:48:31.979107 2, 0xFFFF, sum = 0
6777 06:48:31.981948 3, 0xFFFF, sum = 0
6778 06:48:31.982064 4, 0xFFFF, sum = 0
6779 06:48:31.985423 5, 0xFFFF, sum = 0
6780 06:48:31.985542 6, 0xFFFF, sum = 0
6781 06:48:31.988573 7, 0xFFFF, sum = 0
6782 06:48:31.991578 8, 0xFFFF, sum = 0
6783 06:48:31.991687 9, 0xFFFF, sum = 0
6784 06:48:31.995103 10, 0xFFFF, sum = 0
6785 06:48:31.995212 11, 0xFFFF, sum = 0
6786 06:48:31.998104 12, 0xFFFF, sum = 0
6787 06:48:31.998233 13, 0x0, sum = 1
6788 06:48:32.001924 14, 0x0, sum = 2
6789 06:48:32.002032 15, 0x0, sum = 3
6790 06:48:32.005194 16, 0x0, sum = 4
6791 06:48:32.005314 best_step = 14
6792 06:48:32.005406
6793 06:48:32.005490 ==
6794 06:48:32.008482 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 06:48:32.011493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 06:48:32.011586 ==
6797 06:48:32.015056 RX Vref Scan: 1
6798 06:48:32.015180
6799 06:48:32.018664 RX Vref 0 -> 0, step: 1
6800 06:48:32.018773
6801 06:48:32.018872 RX Delay -359 -> 252, step: 8
6802 06:48:32.018967
6803 06:48:32.021766 Set Vref, RX VrefLevel [Byte0]: 59
6804 06:48:32.024936 [Byte1]: 49
6805 06:48:32.030592
6806 06:48:32.030704 Final RX Vref Byte 0 = 59 to rank0
6807 06:48:32.034049 Final RX Vref Byte 1 = 49 to rank0
6808 06:48:32.037366 Final RX Vref Byte 0 = 59 to rank1
6809 06:48:32.040444 Final RX Vref Byte 1 = 49 to rank1==
6810 06:48:32.043701 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 06:48:32.050091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 06:48:32.050210 ==
6813 06:48:32.050310 DQS Delay:
6814 06:48:32.053459 DQS0 = 48, DQS1 = 60
6815 06:48:32.053545 DQM Delay:
6816 06:48:32.053612 DQM0 = 12, DQM1 = 12
6817 06:48:32.056954 DQ Delay:
6818 06:48:32.060132 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6819 06:48:32.060242 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6820 06:48:32.063854 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6821 06:48:32.067035 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =16
6822 06:48:32.067149
6823 06:48:32.067248
6824 06:48:32.077124 [DQSOSCAuto] RK0, (LSB)MR18= 0x872e, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
6825 06:48:32.080607 CH1 RK0: MR19=C0C, MR18=872E
6826 06:48:32.087440 CH1_RK0: MR19=0xC0C, MR18=0x872E, DQSOSC=392, MR23=63, INC=384, DEC=256
6827 06:48:32.087556 ==
6828 06:48:32.090666 Dram Type= 6, Freq= 0, CH_1, rank 1
6829 06:48:32.093800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 06:48:32.093910 ==
6831 06:48:32.096895 [Gating] SW mode calibration
6832 06:48:32.103723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6833 06:48:32.106888 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6834 06:48:32.113397 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6835 06:48:32.117073 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6836 06:48:32.120287 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 06:48:32.127127 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 06:48:32.130211 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 06:48:32.134044 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 06:48:32.140560 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 06:48:32.143817 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 06:48:32.147074 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 06:48:32.150379 Total UI for P1: 0, mck2ui 16
6844 06:48:32.153829 best dqsien dly found for B0: ( 0, 14, 24)
6845 06:48:32.157501 Total UI for P1: 0, mck2ui 16
6846 06:48:32.160549 best dqsien dly found for B1: ( 0, 14, 24)
6847 06:48:32.163833 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6848 06:48:32.167840 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6849 06:48:32.167915
6850 06:48:32.173866 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6851 06:48:32.177445 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6852 06:48:32.177546 [Gating] SW calibration Done
6853 06:48:32.180607 ==
6854 06:48:32.180718 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 06:48:32.187035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 06:48:32.187115 ==
6857 06:48:32.187198 RX Vref Scan: 0
6858 06:48:32.187279
6859 06:48:32.190320 RX Vref 0 -> 0, step: 1
6860 06:48:32.190423
6861 06:48:32.193849 RX Delay -410 -> 252, step: 16
6862 06:48:32.197094 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6863 06:48:32.200863 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6864 06:48:32.207464 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6865 06:48:32.210351 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6866 06:48:32.213574 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6867 06:48:32.217518 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6868 06:48:32.224039 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6869 06:48:32.227303 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6870 06:48:32.230435 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6871 06:48:32.233622 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6872 06:48:32.240768 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6873 06:48:32.243778 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6874 06:48:32.247135 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6875 06:48:32.250525 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6876 06:48:32.257061 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6877 06:48:32.260499 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6878 06:48:32.260623 ==
6879 06:48:32.263806 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 06:48:32.266988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 06:48:32.267073 ==
6882 06:48:32.270715 DQS Delay:
6883 06:48:32.270797 DQS0 = 43, DQS1 = 51
6884 06:48:32.273819 DQM Delay:
6885 06:48:32.273901 DQM0 = 9, DQM1 = 10
6886 06:48:32.273981 DQ Delay:
6887 06:48:32.277236 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6888 06:48:32.280533 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6889 06:48:32.283828 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6890 06:48:32.287070 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6891 06:48:32.287185
6892 06:48:32.287278
6893 06:48:32.287368 ==
6894 06:48:32.290598 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 06:48:32.293821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 06:48:32.296716 ==
6897 06:48:32.296850
6898 06:48:32.296950
6899 06:48:32.297041 TX Vref Scan disable
6900 06:48:32.300198 == TX Byte 0 ==
6901 06:48:32.303320 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6902 06:48:32.306881 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6903 06:48:32.310552 == TX Byte 1 ==
6904 06:48:32.313767 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6905 06:48:32.317170 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6906 06:48:32.317287 ==
6907 06:48:32.320409 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 06:48:32.323765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 06:48:32.326961 ==
6910 06:48:32.327060
6911 06:48:32.327140
6912 06:48:32.327262 TX Vref Scan disable
6913 06:48:32.330320 == TX Byte 0 ==
6914 06:48:32.333386 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6915 06:48:32.337386 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6916 06:48:32.340276 == TX Byte 1 ==
6917 06:48:32.343492 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6918 06:48:32.347115 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6919 06:48:32.347198
6920 06:48:32.347264 [DATLAT]
6921 06:48:32.350583 Freq=400, CH1 RK1
6922 06:48:32.350695
6923 06:48:32.353825 DATLAT Default: 0xe
6924 06:48:32.353949 0, 0xFFFF, sum = 0
6925 06:48:32.357080 1, 0xFFFF, sum = 0
6926 06:48:32.357185 2, 0xFFFF, sum = 0
6927 06:48:32.360575 3, 0xFFFF, sum = 0
6928 06:48:32.360656 4, 0xFFFF, sum = 0
6929 06:48:32.363846 5, 0xFFFF, sum = 0
6930 06:48:32.363933 6, 0xFFFF, sum = 0
6931 06:48:32.367081 7, 0xFFFF, sum = 0
6932 06:48:32.367166 8, 0xFFFF, sum = 0
6933 06:48:32.370342 9, 0xFFFF, sum = 0
6934 06:48:32.370434 10, 0xFFFF, sum = 0
6935 06:48:32.373532 11, 0xFFFF, sum = 0
6936 06:48:32.373615 12, 0xFFFF, sum = 0
6937 06:48:32.377198 13, 0x0, sum = 1
6938 06:48:32.377283 14, 0x0, sum = 2
6939 06:48:32.380262 15, 0x0, sum = 3
6940 06:48:32.380349 16, 0x0, sum = 4
6941 06:48:32.383945 best_step = 14
6942 06:48:32.384030
6943 06:48:32.384095 ==
6944 06:48:32.387224 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 06:48:32.390244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 06:48:32.390354 ==
6947 06:48:32.390444 RX Vref Scan: 0
6948 06:48:32.390507
6949 06:48:32.393951 RX Vref 0 -> 0, step: 1
6950 06:48:32.394039
6951 06:48:32.397029 RX Delay -343 -> 252, step: 8
6952 06:48:32.404692 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6953 06:48:32.407584 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6954 06:48:32.411175 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6955 06:48:32.414657 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6956 06:48:32.420924 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6957 06:48:32.424408 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6958 06:48:32.427911 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6959 06:48:32.431265 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6960 06:48:32.438242 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6961 06:48:32.441495 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6962 06:48:32.444625 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6963 06:48:32.448022 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6964 06:48:32.454327 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6965 06:48:32.458312 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6966 06:48:32.461716 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6967 06:48:32.464377 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6968 06:48:32.467856 ==
6969 06:48:32.467950 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 06:48:32.475112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 06:48:32.475202 ==
6972 06:48:32.475270 DQS Delay:
6973 06:48:32.477704 DQS0 = 52, DQS1 = 60
6974 06:48:32.477782 DQM Delay:
6975 06:48:32.481178 DQM0 = 13, DQM1 = 13
6976 06:48:32.481284 DQ Delay:
6977 06:48:32.484523 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6978 06:48:32.487850 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6979 06:48:32.491168 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6980 06:48:32.494411 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6981 06:48:32.494522
6982 06:48:32.494622
6983 06:48:32.501187 [DQSOSCAuto] RK1, (LSB)MR18= 0x7e94, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 393 ps
6984 06:48:32.504825 CH1 RK1: MR19=C0C, MR18=7E94
6985 06:48:32.511039 CH1_RK1: MR19=0xC0C, MR18=0x7E94, DQSOSC=391, MR23=63, INC=386, DEC=257
6986 06:48:32.514988 [RxdqsGatingPostProcess] freq 400
6987 06:48:32.518206 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6988 06:48:32.521165 best DQS0 dly(2T, 0.5T) = (0, 10)
6989 06:48:32.525081 best DQS1 dly(2T, 0.5T) = (0, 10)
6990 06:48:32.527892 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6991 06:48:32.531393 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6992 06:48:32.534969 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 06:48:32.538342 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 06:48:32.541237 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 06:48:32.544254 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 06:48:32.548098 Pre-setting of DQS Precalculation
6997 06:48:32.551135 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6998 06:48:32.558100 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6999 06:48:32.568151 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7000 06:48:32.568233
7001 06:48:32.568297
7002 06:48:32.571040 [Calibration Summary] 800 Mbps
7003 06:48:32.571121 CH 0, Rank 0
7004 06:48:32.574558 SW Impedance : PASS
7005 06:48:32.574639 DUTY Scan : NO K
7006 06:48:32.577604 ZQ Calibration : PASS
7007 06:48:32.581568 Jitter Meter : NO K
7008 06:48:32.581650 CBT Training : PASS
7009 06:48:32.584738 Write leveling : PASS
7010 06:48:32.584821 RX DQS gating : PASS
7011 06:48:32.587617 RX DQ/DQS(RDDQC) : PASS
7012 06:48:32.591754 TX DQ/DQS : PASS
7013 06:48:32.591835 RX DATLAT : PASS
7014 06:48:32.594381 RX DQ/DQS(Engine): PASS
7015 06:48:32.597901 TX OE : NO K
7016 06:48:32.597983 All Pass.
7017 06:48:32.598068
7018 06:48:32.598158 CH 0, Rank 1
7019 06:48:32.601023 SW Impedance : PASS
7020 06:48:32.604871 DUTY Scan : NO K
7021 06:48:32.604975 ZQ Calibration : PASS
7022 06:48:32.608243 Jitter Meter : NO K
7023 06:48:32.611500 CBT Training : PASS
7024 06:48:32.611574 Write leveling : NO K
7025 06:48:32.614813 RX DQS gating : PASS
7026 06:48:32.617898 RX DQ/DQS(RDDQC) : PASS
7027 06:48:32.617970 TX DQ/DQS : PASS
7028 06:48:32.621406 RX DATLAT : PASS
7029 06:48:32.621482 RX DQ/DQS(Engine): PASS
7030 06:48:32.624501 TX OE : NO K
7031 06:48:32.624574 All Pass.
7032 06:48:32.624636
7033 06:48:32.628409 CH 1, Rank 0
7034 06:48:32.628512 SW Impedance : PASS
7035 06:48:32.631429 DUTY Scan : NO K
7036 06:48:32.634568 ZQ Calibration : PASS
7037 06:48:32.634676 Jitter Meter : NO K
7038 06:48:32.638133 CBT Training : PASS
7039 06:48:32.641679 Write leveling : PASS
7040 06:48:32.641770 RX DQS gating : PASS
7041 06:48:32.644933 RX DQ/DQS(RDDQC) : PASS
7042 06:48:32.647980 TX DQ/DQS : PASS
7043 06:48:32.648094 RX DATLAT : PASS
7044 06:48:32.651040 RX DQ/DQS(Engine): PASS
7045 06:48:32.654971 TX OE : NO K
7046 06:48:32.655054 All Pass.
7047 06:48:32.655118
7048 06:48:32.655177 CH 1, Rank 1
7049 06:48:32.658170 SW Impedance : PASS
7050 06:48:32.661285 DUTY Scan : NO K
7051 06:48:32.661366 ZQ Calibration : PASS
7052 06:48:32.665056 Jitter Meter : NO K
7053 06:48:32.665137 CBT Training : PASS
7054 06:48:32.668243 Write leveling : NO K
7055 06:48:32.671213 RX DQS gating : PASS
7056 06:48:32.671295 RX DQ/DQS(RDDQC) : PASS
7057 06:48:32.674915 TX DQ/DQS : PASS
7058 06:48:32.678008 RX DATLAT : PASS
7059 06:48:32.678133 RX DQ/DQS(Engine): PASS
7060 06:48:32.681598 TX OE : NO K
7061 06:48:32.681683 All Pass.
7062 06:48:32.681762
7063 06:48:32.684749 DramC Write-DBI off
7064 06:48:32.688575 PER_BANK_REFRESH: Hybrid Mode
7065 06:48:32.688658 TX_TRACKING: ON
7066 06:48:32.698607 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7067 06:48:32.701717 [FAST_K] Save calibration result to emmc
7068 06:48:32.705199 dramc_set_vcore_voltage set vcore to 725000
7069 06:48:32.708331 Read voltage for 1600, 0
7070 06:48:32.708412 Vio18 = 0
7071 06:48:32.708476 Vcore = 725000
7072 06:48:32.711506 Vdram = 0
7073 06:48:32.711587 Vddq = 0
7074 06:48:32.711651 Vmddr = 0
7075 06:48:32.718354 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7076 06:48:32.722070 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7077 06:48:32.725369 MEM_TYPE=3, freq_sel=13
7078 06:48:32.728167 sv_algorithm_assistance_LP4_3733
7079 06:48:32.731388 ============ PULL DRAM RESETB DOWN ============
7080 06:48:32.734695 ========== PULL DRAM RESETB DOWN end =========
7081 06:48:32.742084 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7082 06:48:32.744745 ===================================
7083 06:48:32.744827 LPDDR4 DRAM CONFIGURATION
7084 06:48:32.748203 ===================================
7085 06:48:32.751679 EX_ROW_EN[0] = 0x0
7086 06:48:32.754618 EX_ROW_EN[1] = 0x0
7087 06:48:32.754700 LP4Y_EN = 0x0
7088 06:48:32.757919 WORK_FSP = 0x1
7089 06:48:32.758001 WL = 0x5
7090 06:48:32.761461 RL = 0x5
7091 06:48:32.761543 BL = 0x2
7092 06:48:32.765125 RPST = 0x0
7093 06:48:32.765207 RD_PRE = 0x0
7094 06:48:32.768289 WR_PRE = 0x1
7095 06:48:32.768371 WR_PST = 0x1
7096 06:48:32.771588 DBI_WR = 0x0
7097 06:48:32.771670 DBI_RD = 0x0
7098 06:48:32.774638 OTF = 0x1
7099 06:48:32.778185 ===================================
7100 06:48:32.781251 ===================================
7101 06:48:32.781335 ANA top config
7102 06:48:32.785036 ===================================
7103 06:48:32.788183 DLL_ASYNC_EN = 0
7104 06:48:32.791220 ALL_SLAVE_EN = 0
7105 06:48:32.795081 NEW_RANK_MODE = 1
7106 06:48:32.795165 DLL_IDLE_MODE = 1
7107 06:48:32.798318 LP45_APHY_COMB_EN = 1
7108 06:48:32.801257 TX_ODT_DIS = 0
7109 06:48:32.804653 NEW_8X_MODE = 1
7110 06:48:32.808512 ===================================
7111 06:48:32.811502 ===================================
7112 06:48:32.811586 data_rate = 3200
7113 06:48:32.814874 CKR = 1
7114 06:48:32.818372 DQ_P2S_RATIO = 8
7115 06:48:32.822034 ===================================
7116 06:48:32.824697 CA_P2S_RATIO = 8
7117 06:48:32.828288 DQ_CA_OPEN = 0
7118 06:48:32.831603 DQ_SEMI_OPEN = 0
7119 06:48:32.831685 CA_SEMI_OPEN = 0
7120 06:48:32.835395 CA_FULL_RATE = 0
7121 06:48:32.838381 DQ_CKDIV4_EN = 0
7122 06:48:32.841701 CA_CKDIV4_EN = 0
7123 06:48:32.844814 CA_PREDIV_EN = 0
7124 06:48:32.848329 PH8_DLY = 12
7125 06:48:32.848435 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7126 06:48:32.851643 DQ_AAMCK_DIV = 4
7127 06:48:32.855067 CA_AAMCK_DIV = 4
7128 06:48:32.858184 CA_ADMCK_DIV = 4
7129 06:48:32.861761 DQ_TRACK_CA_EN = 0
7130 06:48:32.865364 CA_PICK = 1600
7131 06:48:32.865506 CA_MCKIO = 1600
7132 06:48:32.868564 MCKIO_SEMI = 0
7133 06:48:32.871566 PLL_FREQ = 3068
7134 06:48:32.875122 DQ_UI_PI_RATIO = 32
7135 06:48:32.878284 CA_UI_PI_RATIO = 0
7136 06:48:32.881479 ===================================
7137 06:48:32.885265 ===================================
7138 06:48:32.888388 memory_type:LPDDR4
7139 06:48:32.888465 GP_NUM : 10
7140 06:48:32.891429 SRAM_EN : 1
7141 06:48:32.891503 MD32_EN : 0
7142 06:48:32.895337 ===================================
7143 06:48:32.898352 [ANA_INIT] >>>>>>>>>>>>>>
7144 06:48:32.901539 <<<<<< [CONFIGURE PHASE]: ANA_TX
7145 06:48:32.905514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7146 06:48:32.907943 ===================================
7147 06:48:32.911262 data_rate = 3200,PCW = 0X7600
7148 06:48:32.914897 ===================================
7149 06:48:32.918149 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7150 06:48:32.924620 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7151 06:48:32.927849 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7152 06:48:32.934604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7153 06:48:32.938566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7154 06:48:32.941889 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7155 06:48:32.941971 [ANA_INIT] flow start
7156 06:48:32.944861 [ANA_INIT] PLL >>>>>>>>
7157 06:48:32.948168 [ANA_INIT] PLL <<<<<<<<
7158 06:48:32.948249 [ANA_INIT] MIDPI >>>>>>>>
7159 06:48:32.951799 [ANA_INIT] MIDPI <<<<<<<<
7160 06:48:32.955072 [ANA_INIT] DLL >>>>>>>>
7161 06:48:32.955146 [ANA_INIT] DLL <<<<<<<<
7162 06:48:32.958732 [ANA_INIT] flow end
7163 06:48:32.961807 ============ LP4 DIFF to SE enter ============
7164 06:48:32.965705 ============ LP4 DIFF to SE exit ============
7165 06:48:32.968296 [ANA_INIT] <<<<<<<<<<<<<
7166 06:48:32.971413 [Flow] Enable top DCM control >>>>>
7167 06:48:32.974835 [Flow] Enable top DCM control <<<<<
7168 06:48:32.978692 Enable DLL master slave shuffle
7169 06:48:32.984994 ==============================================================
7170 06:48:32.985103 Gating Mode config
7171 06:48:32.991473 ==============================================================
7172 06:48:32.991553 Config description:
7173 06:48:33.001408 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7174 06:48:33.007983 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7175 06:48:33.015176 SELPH_MODE 0: By rank 1: By Phase
7176 06:48:33.018311 ==============================================================
7177 06:48:33.021593 GAT_TRACK_EN = 1
7178 06:48:33.025497 RX_GATING_MODE = 2
7179 06:48:33.028202 RX_GATING_TRACK_MODE = 2
7180 06:48:33.031813 SELPH_MODE = 1
7181 06:48:33.034656 PICG_EARLY_EN = 1
7182 06:48:33.038529 VALID_LAT_VALUE = 1
7183 06:48:33.041661 ==============================================================
7184 06:48:33.045017 Enter into Gating configuration >>>>
7185 06:48:33.048444 Exit from Gating configuration <<<<
7186 06:48:33.052013 Enter into DVFS_PRE_config >>>>>
7187 06:48:33.064916 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7188 06:48:33.068090 Exit from DVFS_PRE_config <<<<<
7189 06:48:33.071811 Enter into PICG configuration >>>>
7190 06:48:33.071885 Exit from PICG configuration <<<<
7191 06:48:33.075075 [RX_INPUT] configuration >>>>>
7192 06:48:33.078085 [RX_INPUT] configuration <<<<<
7193 06:48:33.084818 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7194 06:48:33.088356 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7195 06:48:33.095078 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 06:48:33.101678 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 06:48:33.108472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7198 06:48:33.115396 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7199 06:48:33.118736 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7200 06:48:33.121822 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7201 06:48:33.125278 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7202 06:48:33.131518 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7203 06:48:33.134845 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7204 06:48:33.138796 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7205 06:48:33.142052 ===================================
7206 06:48:33.145199 LPDDR4 DRAM CONFIGURATION
7207 06:48:33.148193 ===================================
7208 06:48:33.148294 EX_ROW_EN[0] = 0x0
7209 06:48:33.151626 EX_ROW_EN[1] = 0x0
7210 06:48:33.155333 LP4Y_EN = 0x0
7211 06:48:33.155414 WORK_FSP = 0x1
7212 06:48:33.158717 WL = 0x5
7213 06:48:33.158797 RL = 0x5
7214 06:48:33.161695 BL = 0x2
7215 06:48:33.161806 RPST = 0x0
7216 06:48:33.165389 RD_PRE = 0x0
7217 06:48:33.165495 WR_PRE = 0x1
7218 06:48:33.168486 WR_PST = 0x1
7219 06:48:33.168593 DBI_WR = 0x0
7220 06:48:33.171733 DBI_RD = 0x0
7221 06:48:33.171828 OTF = 0x1
7222 06:48:33.175474 ===================================
7223 06:48:33.178318 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7224 06:48:33.185095 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7225 06:48:33.188576 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 06:48:33.191711 ===================================
7227 06:48:33.195331 LPDDR4 DRAM CONFIGURATION
7228 06:48:33.198374 ===================================
7229 06:48:33.198508 EX_ROW_EN[0] = 0x10
7230 06:48:33.201843 EX_ROW_EN[1] = 0x0
7231 06:48:33.201923 LP4Y_EN = 0x0
7232 06:48:33.206027 WORK_FSP = 0x1
7233 06:48:33.206108 WL = 0x5
7234 06:48:33.208493 RL = 0x5
7235 06:48:33.208573 BL = 0x2
7236 06:48:33.212063 RPST = 0x0
7237 06:48:33.212143 RD_PRE = 0x0
7238 06:48:33.215048 WR_PRE = 0x1
7239 06:48:33.218832 WR_PST = 0x1
7240 06:48:33.218913 DBI_WR = 0x0
7241 06:48:33.222216 DBI_RD = 0x0
7242 06:48:33.222322 OTF = 0x1
7243 06:48:33.225158 ===================================
7244 06:48:33.231549 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7245 06:48:33.231658 ==
7246 06:48:33.235016 Dram Type= 6, Freq= 0, CH_0, rank 0
7247 06:48:33.238661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7248 06:48:33.238743 ==
7249 06:48:33.241671 [Duty_Offset_Calibration]
7250 06:48:33.241750 B0:2 B1:-1 CA:1
7251 06:48:33.244898
7252 06:48:33.248575 [DutyScan_Calibration_Flow] k_type=0
7253 06:48:33.255409
7254 06:48:33.255491 ==CLK 0==
7255 06:48:33.259393 Final CLK duty delay cell = -4
7256 06:48:33.262423 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7257 06:48:33.266245 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7258 06:48:33.269469 [-4] AVG Duty = 4937%(X100)
7259 06:48:33.269543
7260 06:48:33.272601 CH0 CLK Duty spec in!! Max-Min= 187%
7261 06:48:33.276105 [DutyScan_Calibration_Flow] ====Done====
7262 06:48:33.276181
7263 06:48:33.279463 [DutyScan_Calibration_Flow] k_type=1
7264 06:48:33.295135
7265 06:48:33.295225 ==DQS 0 ==
7266 06:48:33.298679 Final DQS duty delay cell = 0
7267 06:48:33.302552 [0] MAX Duty = 5125%(X100), DQS PI = 56
7268 06:48:33.305846 [0] MIN Duty = 5000%(X100), DQS PI = 14
7269 06:48:33.308381 [0] AVG Duty = 5062%(X100)
7270 06:48:33.308458
7271 06:48:33.308528 ==DQS 1 ==
7272 06:48:33.312031 Final DQS duty delay cell = -4
7273 06:48:33.315399 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7274 06:48:33.318461 [-4] MIN Duty = 5031%(X100), DQS PI = 20
7275 06:48:33.321770 [-4] AVG Duty = 5062%(X100)
7276 06:48:33.321845
7277 06:48:33.325519 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7278 06:48:33.325622
7279 06:48:33.328836 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7280 06:48:33.331778 [DutyScan_Calibration_Flow] ====Done====
7281 06:48:33.331870
7282 06:48:33.334910 [DutyScan_Calibration_Flow] k_type=3
7283 06:48:33.352558
7284 06:48:33.352679 ==DQM 0 ==
7285 06:48:33.355786 Final DQM duty delay cell = 0
7286 06:48:33.359347 [0] MAX Duty = 5000%(X100), DQS PI = 18
7287 06:48:33.362868 [0] MIN Duty = 4875%(X100), DQS PI = 4
7288 06:48:33.362975 [0] AVG Duty = 4937%(X100)
7289 06:48:33.365736
7290 06:48:33.365841 ==DQM 1 ==
7291 06:48:33.369617 Final DQM duty delay cell = 0
7292 06:48:33.372633 [0] MAX Duty = 5187%(X100), DQS PI = 58
7293 06:48:33.375792 [0] MIN Duty = 4969%(X100), DQS PI = 18
7294 06:48:33.375906 [0] AVG Duty = 5078%(X100)
7295 06:48:33.379434
7296 06:48:33.382831 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7297 06:48:33.382911
7298 06:48:33.386134 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7299 06:48:33.389293 [DutyScan_Calibration_Flow] ====Done====
7300 06:48:33.389404
7301 06:48:33.392816 [DutyScan_Calibration_Flow] k_type=2
7302 06:48:33.409590
7303 06:48:33.409713 ==DQ 0 ==
7304 06:48:33.413623 Final DQ duty delay cell = 0
7305 06:48:33.416465 [0] MAX Duty = 5156%(X100), DQS PI = 0
7306 06:48:33.420001 [0] MIN Duty = 5031%(X100), DQS PI = 12
7307 06:48:33.420114 [0] AVG Duty = 5093%(X100)
7308 06:48:33.420226
7309 06:48:33.423076 ==DQ 1 ==
7310 06:48:33.426313 Final DQ duty delay cell = 0
7311 06:48:33.430222 [0] MAX Duty = 5031%(X100), DQS PI = 30
7312 06:48:33.433195 [0] MIN Duty = 4907%(X100), DQS PI = 26
7313 06:48:33.433272 [0] AVG Duty = 4969%(X100)
7314 06:48:33.433336
7315 06:48:33.436775 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7316 06:48:33.436855
7317 06:48:33.440064 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7318 06:48:33.446873 [DutyScan_Calibration_Flow] ====Done====
7319 06:48:33.446956 ==
7320 06:48:33.450339 Dram Type= 6, Freq= 0, CH_1, rank 0
7321 06:48:33.453295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7322 06:48:33.453370 ==
7323 06:48:33.456678 [Duty_Offset_Calibration]
7324 06:48:33.456757 B0:1 B1:1 CA:2
7325 06:48:33.456846
7326 06:48:33.460241 [DutyScan_Calibration_Flow] k_type=0
7327 06:48:33.470336
7328 06:48:33.470448 ==CLK 0==
7329 06:48:33.473374 Final CLK duty delay cell = 0
7330 06:48:33.477452 [0] MAX Duty = 5156%(X100), DQS PI = 24
7331 06:48:33.480109 [0] MIN Duty = 4938%(X100), DQS PI = 50
7332 06:48:33.480195 [0] AVG Duty = 5047%(X100)
7333 06:48:33.480261
7334 06:48:33.483628 CH1 CLK Duty spec in!! Max-Min= 218%
7335 06:48:33.490240 [DutyScan_Calibration_Flow] ====Done====
7336 06:48:33.490351
7337 06:48:33.493457 [DutyScan_Calibration_Flow] k_type=1
7338 06:48:33.509897
7339 06:48:33.509982 ==DQS 0 ==
7340 06:48:33.513475 Final DQS duty delay cell = 0
7341 06:48:33.516646 [0] MAX Duty = 5062%(X100), DQS PI = 20
7342 06:48:33.519719 [0] MIN Duty = 4813%(X100), DQS PI = 50
7343 06:48:33.523031 [0] AVG Duty = 4937%(X100)
7344 06:48:33.523149
7345 06:48:33.523239 ==DQS 1 ==
7346 06:48:33.526258 Final DQS duty delay cell = 0
7347 06:48:33.530184 [0] MAX Duty = 5062%(X100), DQS PI = 56
7348 06:48:33.533417 [0] MIN Duty = 4938%(X100), DQS PI = 12
7349 06:48:33.536521 [0] AVG Duty = 5000%(X100)
7350 06:48:33.536605
7351 06:48:33.539668 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7352 06:48:33.539750
7353 06:48:33.543346 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7354 06:48:33.546323 [DutyScan_Calibration_Flow] ====Done====
7355 06:48:33.546447
7356 06:48:33.549471 [DutyScan_Calibration_Flow] k_type=3
7357 06:48:33.566566
7358 06:48:33.566652 ==DQM 0 ==
7359 06:48:33.570008 Final DQM duty delay cell = 0
7360 06:48:33.573909 [0] MAX Duty = 5156%(X100), DQS PI = 20
7361 06:48:33.576832 [0] MIN Duty = 4876%(X100), DQS PI = 46
7362 06:48:33.580109 [0] AVG Duty = 5016%(X100)
7363 06:48:33.580212
7364 06:48:33.580279 ==DQM 1 ==
7365 06:48:33.583774 Final DQM duty delay cell = 0
7366 06:48:33.586762 [0] MAX Duty = 5125%(X100), DQS PI = 8
7367 06:48:33.590237 [0] MIN Duty = 4907%(X100), DQS PI = 20
7368 06:48:33.590346 [0] AVG Duty = 5016%(X100)
7369 06:48:33.593224
7370 06:48:33.596760 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7371 06:48:33.596835
7372 06:48:33.600367 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7373 06:48:33.603355 [DutyScan_Calibration_Flow] ====Done====
7374 06:48:33.603431
7375 06:48:33.606625 [DutyScan_Calibration_Flow] k_type=2
7376 06:48:33.624051
7377 06:48:33.624142 ==DQ 0 ==
7378 06:48:33.627062 Final DQ duty delay cell = 0
7379 06:48:33.630316 [0] MAX Duty = 5125%(X100), DQS PI = 20
7380 06:48:33.633387 [0] MIN Duty = 4907%(X100), DQS PI = 52
7381 06:48:33.633459 [0] AVG Duty = 5016%(X100)
7382 06:48:33.636854
7383 06:48:33.636941 ==DQ 1 ==
7384 06:48:33.640006 Final DQ duty delay cell = 0
7385 06:48:33.643415 [0] MAX Duty = 5093%(X100), DQS PI = 8
7386 06:48:33.646948 [0] MIN Duty = 5031%(X100), DQS PI = 0
7387 06:48:33.647030 [0] AVG Duty = 5062%(X100)
7388 06:48:33.647095
7389 06:48:33.650108 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7390 06:48:33.653205
7391 06:48:33.653286 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7392 06:48:33.660561 [DutyScan_Calibration_Flow] ====Done====
7393 06:48:33.663855 nWR fixed to 30
7394 06:48:33.663933 [ModeRegInit_LP4] CH0 RK0
7395 06:48:33.667080 [ModeRegInit_LP4] CH0 RK1
7396 06:48:33.670103 [ModeRegInit_LP4] CH1 RK0
7397 06:48:33.670176 [ModeRegInit_LP4] CH1 RK1
7398 06:48:33.673232 match AC timing 5
7399 06:48:33.676794 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7400 06:48:33.679894 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7401 06:48:33.686873 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7402 06:48:33.689967 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7403 06:48:33.697303 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7404 06:48:33.697386 [MiockJmeterHQA]
7405 06:48:33.697449
7406 06:48:33.700310 [DramcMiockJmeter] u1RxGatingPI = 0
7407 06:48:33.700412 0 : 4368, 4140
7408 06:48:33.703463 4 : 4252, 4027
7409 06:48:33.703538 8 : 4252, 4027
7410 06:48:33.707280 12 : 4252, 4027
7411 06:48:33.707357 16 : 4253, 4026
7412 06:48:33.710333 20 : 4252, 4027
7413 06:48:33.710471 24 : 4255, 4029
7414 06:48:33.713546 28 : 4363, 4137
7415 06:48:33.713617 32 : 4252, 4027
7416 06:48:33.713685 36 : 4253, 4026
7417 06:48:33.716854 40 : 4252, 4027
7418 06:48:33.716928 44 : 4255, 4029
7419 06:48:33.720309 48 : 4252, 4027
7420 06:48:33.720379 52 : 4363, 4137
7421 06:48:33.723304 56 : 4363, 4137
7422 06:48:33.723392 60 : 4250, 4027
7423 06:48:33.723455 64 : 4250, 4027
7424 06:48:33.727289 68 : 4250, 4027
7425 06:48:33.727365 72 : 4360, 4137
7426 06:48:33.730307 76 : 4250, 4027
7427 06:48:33.730436 80 : 4361, 4137
7428 06:48:33.733431 84 : 4249, 4027
7429 06:48:33.733508 88 : 4250, 4027
7430 06:48:33.736849 92 : 4250, 4027
7431 06:48:33.736933 96 : 4253, 3057
7432 06:48:33.736998 100 : 4250, 0
7433 06:48:33.739979 104 : 4252, 0
7434 06:48:33.740049 108 : 4253, 0
7435 06:48:33.743551 112 : 4253, 0
7436 06:48:33.743636 116 : 4252, 0
7437 06:48:33.743700 120 : 4361, 0
7438 06:48:33.746842 124 : 4250, 0
7439 06:48:33.746929 128 : 4361, 0
7440 06:48:33.746995 132 : 4253, 0
7441 06:48:33.750472 136 : 4253, 0
7442 06:48:33.750548 140 : 4250, 0
7443 06:48:33.753598 144 : 4252, 0
7444 06:48:33.753673 148 : 4250, 0
7445 06:48:33.753735 152 : 4250, 0
7446 06:48:33.756800 156 : 4253, 0
7447 06:48:33.756879 160 : 4252, 0
7448 06:48:33.760043 164 : 4361, 0
7449 06:48:33.760131 168 : 4250, 0
7450 06:48:33.760193 172 : 4361, 0
7451 06:48:33.763600 176 : 4360, 0
7452 06:48:33.763684 180 : 4250, 0
7453 06:48:33.766755 184 : 4250, 0
7454 06:48:33.766838 188 : 4250, 0
7455 06:48:33.766906 192 : 4250, 0
7456 06:48:33.770098 196 : 4252, 0
7457 06:48:33.770194 200 : 4250, 0
7458 06:48:33.770274 204 : 4250, 0
7459 06:48:33.773397 208 : 4252, 0
7460 06:48:33.773518 212 : 4360, 352
7461 06:48:33.777327 216 : 4360, 4021
7462 06:48:33.777410 220 : 4250, 4026
7463 06:48:33.780274 224 : 4250, 4027
7464 06:48:33.780366 228 : 4250, 4027
7465 06:48:33.783309 232 : 4252, 4029
7466 06:48:33.783386 236 : 4250, 4027
7467 06:48:33.787308 240 : 4250, 4027
7468 06:48:33.787390 244 : 4360, 4138
7469 06:48:33.787455 248 : 4250, 4027
7470 06:48:33.790545 252 : 4250, 4026
7471 06:48:33.790627 256 : 4361, 4137
7472 06:48:33.793434 260 : 4250, 4027
7473 06:48:33.793515 264 : 4249, 4027
7474 06:48:33.797068 268 : 4363, 4140
7475 06:48:33.797150 272 : 4250, 4026
7476 06:48:33.800267 276 : 4250, 4027
7477 06:48:33.800348 280 : 4249, 4027
7478 06:48:33.804255 284 : 4252, 4029
7479 06:48:33.804338 288 : 4250, 4026
7480 06:48:33.806921 292 : 4250, 4027
7481 06:48:33.807003 296 : 4361, 4138
7482 06:48:33.807068 300 : 4250, 4027
7483 06:48:33.810159 304 : 4250, 4026
7484 06:48:33.810268 308 : 4361, 4137
7485 06:48:33.813901 312 : 4250, 4027
7486 06:48:33.813984 316 : 4250, 4027
7487 06:48:33.817246 320 : 4363, 4140
7488 06:48:33.817328 324 : 4250, 4027
7489 06:48:33.820807 328 : 4250, 4027
7490 06:48:33.820890 332 : 4249, 2935
7491 06:48:33.823452 336 : 4250, 160
7492 06:48:33.823535
7493 06:48:33.823597 MIOCK jitter meter ch=0
7494 06:48:33.823657
7495 06:48:33.827385 1T = (336-100) = 236 dly cells
7496 06:48:33.833803 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7497 06:48:33.833885 ==
7498 06:48:33.837059 Dram Type= 6, Freq= 0, CH_0, rank 0
7499 06:48:33.840258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7500 06:48:33.840404 ==
7501 06:48:33.847023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7502 06:48:33.850191 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7503 06:48:33.853641 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7504 06:48:33.860182 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7505 06:48:33.870253 [CA 0] Center 44 (14~75) winsize 62
7506 06:48:33.873280 [CA 1] Center 44 (14~74) winsize 61
7507 06:48:33.876868 [CA 2] Center 39 (10~68) winsize 59
7508 06:48:33.880023 [CA 3] Center 39 (10~68) winsize 59
7509 06:48:33.883707 [CA 4] Center 37 (7~67) winsize 61
7510 06:48:33.886517 [CA 5] Center 37 (7~67) winsize 61
7511 06:48:33.886598
7512 06:48:33.890221 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7513 06:48:33.890327
7514 06:48:33.893329 [CATrainingPosCal] consider 1 rank data
7515 06:48:33.896822 u2DelayCellTimex100 = 275/100 ps
7516 06:48:33.900420 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7517 06:48:33.906806 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7518 06:48:33.910278 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7519 06:48:33.913492 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7520 06:48:33.917199 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7521 06:48:33.920338 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7522 06:48:33.920421
7523 06:48:33.923504 CA PerBit enable=1, Macro0, CA PI delay=37
7524 06:48:33.923586
7525 06:48:33.927162 [CBTSetCACLKResult] CA Dly = 37
7526 06:48:33.930753 CS Dly: 10 (0~41)
7527 06:48:33.933525 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7528 06:48:33.937198 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7529 06:48:33.937286 ==
7530 06:48:33.940148 Dram Type= 6, Freq= 0, CH_0, rank 1
7531 06:48:33.943890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 06:48:33.943992 ==
7533 06:48:33.950558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7534 06:48:33.953577 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7535 06:48:33.960189 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7536 06:48:33.963545 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7537 06:48:33.974276 [CA 0] Center 43 (13~74) winsize 62
7538 06:48:33.977654 [CA 1] Center 43 (13~74) winsize 62
7539 06:48:33.980286 [CA 2] Center 39 (10~69) winsize 60
7540 06:48:33.983968 [CA 3] Center 38 (9~68) winsize 60
7541 06:48:33.987007 [CA 4] Center 37 (7~67) winsize 61
7542 06:48:33.990562 [CA 5] Center 37 (7~67) winsize 61
7543 06:48:33.990653
7544 06:48:33.993770 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7545 06:48:33.993856
7546 06:48:33.997021 [CATrainingPosCal] consider 2 rank data
7547 06:48:34.000241 u2DelayCellTimex100 = 275/100 ps
7548 06:48:34.003732 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7549 06:48:34.011013 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7550 06:48:34.013755 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7551 06:48:34.017233 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7552 06:48:34.020469 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7553 06:48:34.023622 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7554 06:48:34.023728
7555 06:48:34.027447 CA PerBit enable=1, Macro0, CA PI delay=37
7556 06:48:34.027528
7557 06:48:34.030609 [CBTSetCACLKResult] CA Dly = 37
7558 06:48:34.033557 CS Dly: 11 (0~43)
7559 06:48:34.037139 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7560 06:48:34.040707 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7561 06:48:34.040809
7562 06:48:34.043710 ----->DramcWriteLeveling(PI) begin...
7563 06:48:34.043793 ==
7564 06:48:34.047537 Dram Type= 6, Freq= 0, CH_0, rank 0
7565 06:48:34.054307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7566 06:48:34.054451 ==
7567 06:48:34.057351 Write leveling (Byte 0): 34 => 34
7568 06:48:34.057433 Write leveling (Byte 1): 28 => 28
7569 06:48:34.060829 DramcWriteLeveling(PI) end<-----
7570 06:48:34.060910
7571 06:48:34.060973 ==
7572 06:48:34.064137 Dram Type= 6, Freq= 0, CH_0, rank 0
7573 06:48:34.070339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 06:48:34.070476 ==
7575 06:48:34.073671 [Gating] SW mode calibration
7576 06:48:34.080149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7577 06:48:34.083849 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7578 06:48:34.090455 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 06:48:34.093428 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 06:48:34.097068 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 06:48:34.103792 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 06:48:34.107099 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 06:48:34.110393 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7584 06:48:34.113622 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7585 06:48:34.120280 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 06:48:34.124039 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 06:48:34.127198 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 06:48:34.134067 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 06:48:34.137433 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 06:48:34.140513 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
7591 06:48:34.147127 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7592 06:48:34.150136 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
7593 06:48:34.153996 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 06:48:34.160905 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 06:48:34.163762 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 06:48:34.167364 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 06:48:34.173749 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 06:48:34.177157 1 6 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7599 06:48:34.180875 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7600 06:48:34.186978 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7601 06:48:34.190562 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 06:48:34.194019 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 06:48:34.197269 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 06:48:34.203761 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 06:48:34.207395 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 06:48:34.210798 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7607 06:48:34.217376 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7608 06:48:34.220737 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7609 06:48:34.223703 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 06:48:34.230737 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 06:48:34.233730 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 06:48:34.237362 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 06:48:34.244078 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 06:48:34.247415 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 06:48:34.250990 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 06:48:34.257344 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 06:48:34.261562 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 06:48:34.264233 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 06:48:34.267990 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 06:48:34.274658 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 06:48:34.277881 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 06:48:34.281521 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7623 06:48:34.287860 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7624 06:48:34.287943 Total UI for P1: 0, mck2ui 16
7625 06:48:34.294832 best dqsien dly found for B0: ( 1, 9, 16)
7626 06:48:34.297980 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 06:48:34.301184 Total UI for P1: 0, mck2ui 16
7628 06:48:34.304463 best dqsien dly found for B1: ( 1, 9, 18)
7629 06:48:34.308244 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7630 06:48:34.310996 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7631 06:48:34.311078
7632 06:48:34.314239 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7633 06:48:34.318128 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7634 06:48:34.320967 [Gating] SW calibration Done
7635 06:48:34.321048 ==
7636 06:48:34.324572 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 06:48:34.327755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 06:48:34.327838 ==
7639 06:48:34.331007 RX Vref Scan: 0
7640 06:48:34.331087
7641 06:48:34.334661 RX Vref 0 -> 0, step: 1
7642 06:48:34.334742
7643 06:48:34.334806 RX Delay 0 -> 252, step: 8
7644 06:48:34.341308 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7645 06:48:34.344109 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7646 06:48:34.347868 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7647 06:48:34.351291 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7648 06:48:34.354687 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7649 06:48:34.361135 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7650 06:48:34.364192 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7651 06:48:34.368038 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7652 06:48:34.370989 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7653 06:48:34.374246 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7654 06:48:34.381821 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7655 06:48:34.384517 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7656 06:48:34.387583 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7657 06:48:34.391480 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7658 06:48:34.394586 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7659 06:48:34.401358 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7660 06:48:34.401440 ==
7661 06:48:34.404492 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 06:48:34.408227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 06:48:34.408308 ==
7664 06:48:34.408372 DQS Delay:
7665 06:48:34.411524 DQS0 = 0, DQS1 = 0
7666 06:48:34.411605 DQM Delay:
7667 06:48:34.414812 DQM0 = 132, DQM1 = 123
7668 06:48:34.414893 DQ Delay:
7669 06:48:34.417850 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7670 06:48:34.421173 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7671 06:48:34.424935 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7672 06:48:34.427845 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7673 06:48:34.427925
7674 06:48:34.427988
7675 06:48:34.431146 ==
7676 06:48:34.431234 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 06:48:34.438272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 06:48:34.438380 ==
7679 06:48:34.438464
7680 06:48:34.438525
7681 06:48:34.441335 TX Vref Scan disable
7682 06:48:34.441416 == TX Byte 0 ==
7683 06:48:34.444792 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7684 06:48:34.451396 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7685 06:48:34.451477 == TX Byte 1 ==
7686 06:48:34.454438 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7687 06:48:34.461293 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7688 06:48:34.461379 ==
7689 06:48:34.464577 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 06:48:34.467784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 06:48:34.467867 ==
7692 06:48:34.482933
7693 06:48:34.485937 TX Vref early break, caculate TX vref
7694 06:48:34.489199 TX Vref=16, minBit 1, minWin=22, winSum=368
7695 06:48:34.492668 TX Vref=18, minBit 2, minWin=22, winSum=376
7696 06:48:34.496424 TX Vref=20, minBit 7, minWin=23, winSum=387
7697 06:48:34.499448 TX Vref=22, minBit 1, minWin=24, winSum=395
7698 06:48:34.502606 TX Vref=24, minBit 4, minWin=24, winSum=408
7699 06:48:34.509522 TX Vref=26, minBit 0, minWin=25, winSum=418
7700 06:48:34.512713 TX Vref=28, minBit 2, minWin=26, winSum=427
7701 06:48:34.516026 TX Vref=30, minBit 0, minWin=25, winSum=426
7702 06:48:34.519874 TX Vref=32, minBit 2, minWin=25, winSum=418
7703 06:48:34.522998 TX Vref=34, minBit 9, minWin=24, winSum=407
7704 06:48:34.526168 TX Vref=36, minBit 0, minWin=24, winSum=395
7705 06:48:34.533032 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 28
7706 06:48:34.533118
7707 06:48:34.535946 Final TX Range 0 Vref 28
7708 06:48:34.536021
7709 06:48:34.536099 ==
7710 06:48:34.539708 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 06:48:34.542867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 06:48:34.542944 ==
7713 06:48:34.543025
7714 06:48:34.543104
7715 06:48:34.546345 TX Vref Scan disable
7716 06:48:34.552655 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7717 06:48:34.552732 == TX Byte 0 ==
7718 06:48:34.556100 u2DelayCellOfst[0]=14 cells (4 PI)
7719 06:48:34.559187 u2DelayCellOfst[1]=21 cells (6 PI)
7720 06:48:34.562694 u2DelayCellOfst[2]=10 cells (3 PI)
7721 06:48:34.565662 u2DelayCellOfst[3]=14 cells (4 PI)
7722 06:48:34.569201 u2DelayCellOfst[4]=10 cells (3 PI)
7723 06:48:34.572635 u2DelayCellOfst[5]=0 cells (0 PI)
7724 06:48:34.576004 u2DelayCellOfst[6]=21 cells (6 PI)
7725 06:48:34.579001 u2DelayCellOfst[7]=21 cells (6 PI)
7726 06:48:34.582988 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7727 06:48:34.585674 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7728 06:48:34.589334 == TX Byte 1 ==
7729 06:48:34.592594 u2DelayCellOfst[8]=0 cells (0 PI)
7730 06:48:34.592702 u2DelayCellOfst[9]=0 cells (0 PI)
7731 06:48:34.595639 u2DelayCellOfst[10]=3 cells (1 PI)
7732 06:48:34.599100 u2DelayCellOfst[11]=0 cells (0 PI)
7733 06:48:34.602507 u2DelayCellOfst[12]=10 cells (3 PI)
7734 06:48:34.606131 u2DelayCellOfst[13]=10 cells (3 PI)
7735 06:48:34.609085 u2DelayCellOfst[14]=14 cells (4 PI)
7736 06:48:34.612347 u2DelayCellOfst[15]=10 cells (3 PI)
7737 06:48:34.616277 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7738 06:48:34.622491 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7739 06:48:34.622569 DramC Write-DBI on
7740 06:48:34.622653 ==
7741 06:48:34.626210 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 06:48:34.632562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 06:48:34.632644 ==
7744 06:48:34.632725
7745 06:48:34.632800
7746 06:48:34.632875 TX Vref Scan disable
7747 06:48:34.636103 == TX Byte 0 ==
7748 06:48:34.639640 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7749 06:48:34.642841 == TX Byte 1 ==
7750 06:48:34.646603 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7751 06:48:34.646680 DramC Write-DBI off
7752 06:48:34.649588
7753 06:48:34.649694 [DATLAT]
7754 06:48:34.649786 Freq=1600, CH0 RK0
7755 06:48:34.649873
7756 06:48:34.653071 DATLAT Default: 0xf
7757 06:48:34.653152 0, 0xFFFF, sum = 0
7758 06:48:34.656168 1, 0xFFFF, sum = 0
7759 06:48:34.656250 2, 0xFFFF, sum = 0
7760 06:48:34.659647 3, 0xFFFF, sum = 0
7761 06:48:34.659729 4, 0xFFFF, sum = 0
7762 06:48:34.663409 5, 0xFFFF, sum = 0
7763 06:48:34.666024 6, 0xFFFF, sum = 0
7764 06:48:34.666105 7, 0xFFFF, sum = 0
7765 06:48:34.669837 8, 0xFFFF, sum = 0
7766 06:48:34.669918 9, 0xFFFF, sum = 0
7767 06:48:34.673099 10, 0xFFFF, sum = 0
7768 06:48:34.673181 11, 0xFFFF, sum = 0
7769 06:48:34.676173 12, 0xFFFF, sum = 0
7770 06:48:34.676255 13, 0xFFFF, sum = 0
7771 06:48:34.679815 14, 0x0, sum = 1
7772 06:48:34.679897 15, 0x0, sum = 2
7773 06:48:34.683005 16, 0x0, sum = 3
7774 06:48:34.683087 17, 0x0, sum = 4
7775 06:48:34.686360 best_step = 15
7776 06:48:34.686486
7777 06:48:34.686560 ==
7778 06:48:34.689490 Dram Type= 6, Freq= 0, CH_0, rank 0
7779 06:48:34.692856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 06:48:34.692938 ==
7781 06:48:34.693003 RX Vref Scan: 1
7782 06:48:34.693062
7783 06:48:34.696425 Set Vref Range= 24 -> 127
7784 06:48:34.696508
7785 06:48:34.699618 RX Vref 24 -> 127, step: 1
7786 06:48:34.699695
7787 06:48:34.702823 RX Delay 11 -> 252, step: 4
7788 06:48:34.702903
7789 06:48:34.706125 Set Vref, RX VrefLevel [Byte0]: 24
7790 06:48:34.709894 [Byte1]: 24
7791 06:48:34.709971
7792 06:48:34.713057 Set Vref, RX VrefLevel [Byte0]: 25
7793 06:48:34.716319 [Byte1]: 25
7794 06:48:34.716399
7795 06:48:34.720425 Set Vref, RX VrefLevel [Byte0]: 26
7796 06:48:34.723341 [Byte1]: 26
7797 06:48:34.726369
7798 06:48:34.726461 Set Vref, RX VrefLevel [Byte0]: 27
7799 06:48:34.730008 [Byte1]: 27
7800 06:48:34.734029
7801 06:48:34.734132 Set Vref, RX VrefLevel [Byte0]: 28
7802 06:48:34.737581 [Byte1]: 28
7803 06:48:34.742087
7804 06:48:34.742190 Set Vref, RX VrefLevel [Byte0]: 29
7805 06:48:34.744884 [Byte1]: 29
7806 06:48:34.749779
7807 06:48:34.749858 Set Vref, RX VrefLevel [Byte0]: 30
7808 06:48:34.753042 [Byte1]: 30
7809 06:48:34.757377
7810 06:48:34.757462 Set Vref, RX VrefLevel [Byte0]: 31
7811 06:48:34.760280 [Byte1]: 31
7812 06:48:34.764566
7813 06:48:34.764651 Set Vref, RX VrefLevel [Byte0]: 32
7814 06:48:34.767770 [Byte1]: 32
7815 06:48:34.772473
7816 06:48:34.772557 Set Vref, RX VrefLevel [Byte0]: 33
7817 06:48:34.775591 [Byte1]: 33
7818 06:48:34.780121
7819 06:48:34.780202 Set Vref, RX VrefLevel [Byte0]: 34
7820 06:48:34.783253 [Byte1]: 34
7821 06:48:34.787400
7822 06:48:34.787481 Set Vref, RX VrefLevel [Byte0]: 35
7823 06:48:34.790801 [Byte1]: 35
7824 06:48:34.795363
7825 06:48:34.795445 Set Vref, RX VrefLevel [Byte0]: 36
7826 06:48:34.798370 [Byte1]: 36
7827 06:48:34.802970
7828 06:48:34.803051 Set Vref, RX VrefLevel [Byte0]: 37
7829 06:48:34.805980 [Byte1]: 37
7830 06:48:34.810366
7831 06:48:34.810531 Set Vref, RX VrefLevel [Byte0]: 38
7832 06:48:34.813704 [Byte1]: 38
7833 06:48:34.818047
7834 06:48:34.818127 Set Vref, RX VrefLevel [Byte0]: 39
7835 06:48:34.821376 [Byte1]: 39
7836 06:48:34.825487
7837 06:48:34.825570 Set Vref, RX VrefLevel [Byte0]: 40
7838 06:48:34.828735 [Byte1]: 40
7839 06:48:34.833027
7840 06:48:34.833108 Set Vref, RX VrefLevel [Byte0]: 41
7841 06:48:34.836713 [Byte1]: 41
7842 06:48:34.841152
7843 06:48:34.841294 Set Vref, RX VrefLevel [Byte0]: 42
7844 06:48:34.844358 [Byte1]: 42
7845 06:48:34.848730
7846 06:48:34.848810 Set Vref, RX VrefLevel [Byte0]: 43
7847 06:48:34.851996 [Byte1]: 43
7848 06:48:34.856123
7849 06:48:34.856207 Set Vref, RX VrefLevel [Byte0]: 44
7850 06:48:34.859355 [Byte1]: 44
7851 06:48:34.863697
7852 06:48:34.863787 Set Vref, RX VrefLevel [Byte0]: 45
7853 06:48:34.866767 [Byte1]: 45
7854 06:48:34.871251
7855 06:48:34.871338 Set Vref, RX VrefLevel [Byte0]: 46
7856 06:48:34.874792 [Byte1]: 46
7857 06:48:34.878893
7858 06:48:34.878971 Set Vref, RX VrefLevel [Byte0]: 47
7859 06:48:34.881967 [Byte1]: 47
7860 06:48:34.886369
7861 06:48:34.886494 Set Vref, RX VrefLevel [Byte0]: 48
7862 06:48:34.889523 [Byte1]: 48
7863 06:48:34.894598
7864 06:48:34.894707 Set Vref, RX VrefLevel [Byte0]: 49
7865 06:48:34.897709 [Byte1]: 49
7866 06:48:34.902073
7867 06:48:34.902153 Set Vref, RX VrefLevel [Byte0]: 50
7868 06:48:34.904954 [Byte1]: 50
7869 06:48:34.909681
7870 06:48:34.909799 Set Vref, RX VrefLevel [Byte0]: 51
7871 06:48:34.912964 [Byte1]: 51
7872 06:48:34.917224
7873 06:48:34.917329 Set Vref, RX VrefLevel [Byte0]: 52
7874 06:48:34.920271 [Byte1]: 52
7875 06:48:34.924412
7876 06:48:34.924494 Set Vref, RX VrefLevel [Byte0]: 53
7877 06:48:34.927819 [Byte1]: 53
7878 06:48:34.932182
7879 06:48:34.932258 Set Vref, RX VrefLevel [Byte0]: 54
7880 06:48:34.935689 [Byte1]: 54
7881 06:48:34.939598
7882 06:48:34.939674 Set Vref, RX VrefLevel [Byte0]: 55
7883 06:48:34.943420 [Byte1]: 55
7884 06:48:34.947823
7885 06:48:34.947899 Set Vref, RX VrefLevel [Byte0]: 56
7886 06:48:34.950406 [Byte1]: 56
7887 06:48:34.954801
7888 06:48:34.954881 Set Vref, RX VrefLevel [Byte0]: 57
7889 06:48:34.958251 [Byte1]: 57
7890 06:48:34.962518
7891 06:48:34.962598 Set Vref, RX VrefLevel [Byte0]: 58
7892 06:48:34.966206 [Byte1]: 58
7893 06:48:34.970593
7894 06:48:34.970673 Set Vref, RX VrefLevel [Byte0]: 59
7895 06:48:34.973379 [Byte1]: 59
7896 06:48:34.977811
7897 06:48:34.977891 Set Vref, RX VrefLevel [Byte0]: 60
7898 06:48:34.981514 [Byte1]: 60
7899 06:48:34.985477
7900 06:48:34.985558 Set Vref, RX VrefLevel [Byte0]: 61
7901 06:48:34.989403 [Byte1]: 61
7902 06:48:34.993426
7903 06:48:34.993511 Set Vref, RX VrefLevel [Byte0]: 62
7904 06:48:34.996681 [Byte1]: 62
7905 06:48:35.000746
7906 06:48:35.000853 Set Vref, RX VrefLevel [Byte0]: 63
7907 06:48:35.003764 [Byte1]: 63
7908 06:48:35.008073
7909 06:48:35.008154 Set Vref, RX VrefLevel [Byte0]: 64
7910 06:48:35.011267 [Byte1]: 64
7911 06:48:35.016095
7912 06:48:35.016176 Set Vref, RX VrefLevel [Byte0]: 65
7913 06:48:35.019010 [Byte1]: 65
7914 06:48:35.023504
7915 06:48:35.023587 Set Vref, RX VrefLevel [Byte0]: 66
7916 06:48:35.027057 [Byte1]: 66
7917 06:48:35.031014
7918 06:48:35.031095 Set Vref, RX VrefLevel [Byte0]: 67
7919 06:48:35.034647 [Byte1]: 67
7920 06:48:35.038421
7921 06:48:35.038515 Set Vref, RX VrefLevel [Byte0]: 68
7922 06:48:35.041792 [Byte1]: 68
7923 06:48:35.046293
7924 06:48:35.046417 Set Vref, RX VrefLevel [Byte0]: 69
7925 06:48:35.049723 [Byte1]: 69
7926 06:48:35.054336
7927 06:48:35.054471 Set Vref, RX VrefLevel [Byte0]: 70
7928 06:48:35.057461 [Byte1]: 70
7929 06:48:35.061833
7930 06:48:35.061936 Set Vref, RX VrefLevel [Byte0]: 71
7931 06:48:35.065120 [Byte1]: 71
7932 06:48:35.069338
7933 06:48:35.069439 Set Vref, RX VrefLevel [Byte0]: 72
7934 06:48:35.072401 [Byte1]: 72
7935 06:48:35.077268
7936 06:48:35.077685 Set Vref, RX VrefLevel [Byte0]: 73
7937 06:48:35.080882 [Byte1]: 73
7938 06:48:35.085001
7939 06:48:35.085415 Set Vref, RX VrefLevel [Byte0]: 74
7940 06:48:35.088158 [Byte1]: 74
7941 06:48:35.092186
7942 06:48:35.092635 Set Vref, RX VrefLevel [Byte0]: 75
7943 06:48:35.095875 [Byte1]: 75
7944 06:48:35.100289
7945 06:48:35.100707 Set Vref, RX VrefLevel [Byte0]: 76
7946 06:48:35.103369 [Byte1]: 76
7947 06:48:35.107612
7948 06:48:35.108144 Final RX Vref Byte 0 = 58 to rank0
7949 06:48:35.110813 Final RX Vref Byte 1 = 62 to rank0
7950 06:48:35.114640 Final RX Vref Byte 0 = 58 to rank1
7951 06:48:35.117849 Final RX Vref Byte 1 = 62 to rank1==
7952 06:48:35.120847 Dram Type= 6, Freq= 0, CH_0, rank 0
7953 06:48:35.127542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 06:48:35.128058 ==
7955 06:48:35.128398 DQS Delay:
7956 06:48:35.128757 DQS0 = 0, DQS1 = 0
7957 06:48:35.131163 DQM Delay:
7958 06:48:35.131587 DQM0 = 129, DQM1 = 121
7959 06:48:35.134042 DQ Delay:
7960 06:48:35.137589 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7961 06:48:35.140944 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7962 06:48:35.144619 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116
7963 06:48:35.147964 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7964 06:48:35.148496
7965 06:48:35.148831
7966 06:48:35.149140
7967 06:48:35.150977 [DramC_TX_OE_Calibration] TA2
7968 06:48:35.154761 Original DQ_B0 (3 6) =30, OEN = 27
7969 06:48:35.157354 Original DQ_B1 (3 6) =30, OEN = 27
7970 06:48:35.160798 24, 0x0, End_B0=24 End_B1=24
7971 06:48:35.161230 25, 0x0, End_B0=25 End_B1=25
7972 06:48:35.164271 26, 0x0, End_B0=26 End_B1=26
7973 06:48:35.167700 27, 0x0, End_B0=27 End_B1=27
7974 06:48:35.170678 28, 0x0, End_B0=28 End_B1=28
7975 06:48:35.171105 29, 0x0, End_B0=29 End_B1=29
7976 06:48:35.174215 30, 0x0, End_B0=30 End_B1=30
7977 06:48:35.177442 31, 0x4141, End_B0=30 End_B1=30
7978 06:48:35.181296 Byte0 end_step=30 best_step=27
7979 06:48:35.185035 Byte1 end_step=30 best_step=27
7980 06:48:35.187368 Byte0 TX OE(2T, 0.5T) = (3, 3)
7981 06:48:35.187815 Byte1 TX OE(2T, 0.5T) = (3, 3)
7982 06:48:35.191179
7983 06:48:35.191595
7984 06:48:35.197692 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7985 06:48:35.201109 CH0 RK0: MR19=303, MR18=1509
7986 06:48:35.207865 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7987 06:48:35.208431
7988 06:48:35.211307 ----->DramcWriteLeveling(PI) begin...
7989 06:48:35.211782 ==
7990 06:48:35.214553 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 06:48:35.218065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 06:48:35.218687 ==
7993 06:48:35.221459 Write leveling (Byte 0): 33 => 33
7994 06:48:35.224647 Write leveling (Byte 1): 27 => 27
7995 06:48:35.227584 DramcWriteLeveling(PI) end<-----
7996 06:48:35.228056
7997 06:48:35.228420 ==
7998 06:48:35.230928 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 06:48:35.234624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 06:48:35.235199 ==
8001 06:48:35.238128 [Gating] SW mode calibration
8002 06:48:35.244575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8003 06:48:35.251037 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8004 06:48:35.254465 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 06:48:35.257943 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 06:48:35.264590 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 06:48:35.267821 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8008 06:48:35.271700 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8009 06:48:35.277843 1 4 20 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
8010 06:48:35.281695 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 06:48:35.285239 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 06:48:35.288075 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 06:48:35.295366 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 06:48:35.297830 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8015 06:48:35.301426 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8016 06:48:35.308095 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8017 06:48:35.311610 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8018 06:48:35.314379 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8019 06:48:35.321514 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 06:48:35.324588 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 06:48:35.328253 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 06:48:35.334513 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8023 06:48:35.338386 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8024 06:48:35.341310 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8025 06:48:35.347875 1 6 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8026 06:48:35.350901 1 6 24 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
8027 06:48:35.354841 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 06:48:35.361178 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 06:48:35.364924 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8030 06:48:35.368111 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8031 06:48:35.374929 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 06:48:35.378170 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8033 06:48:35.381319 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8034 06:48:35.384646 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 06:48:35.391812 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 06:48:35.394883 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 06:48:35.397809 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 06:48:35.404692 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 06:48:35.408062 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 06:48:35.411919 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 06:48:35.418581 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 06:48:35.421752 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 06:48:35.425338 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 06:48:35.431498 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 06:48:35.435426 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 06:48:35.438283 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 06:48:35.444660 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8048 06:48:35.445220 Total UI for P1: 0, mck2ui 16
8049 06:48:35.448125 best dqsien dly found for B0: ( 1, 9, 6)
8050 06:48:35.455209 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8051 06:48:35.458302 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8052 06:48:35.461513 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 06:48:35.464760 Total UI for P1: 0, mck2ui 16
8054 06:48:35.468185 best dqsien dly found for B1: ( 1, 9, 18)
8055 06:48:35.471905 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8056 06:48:35.475115 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8057 06:48:35.478612
8058 06:48:35.481581 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8059 06:48:35.485028 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8060 06:48:35.488455 [Gating] SW calibration Done
8061 06:48:35.489017 ==
8062 06:48:35.491462 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 06:48:35.495143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 06:48:35.495612 ==
8065 06:48:35.496049 RX Vref Scan: 0
8066 06:48:35.496404
8067 06:48:35.498156 RX Vref 0 -> 0, step: 1
8068 06:48:35.498681
8069 06:48:35.501431 RX Delay 0 -> 252, step: 8
8070 06:48:35.505037 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8071 06:48:35.508292 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8072 06:48:35.511846 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8073 06:48:35.518114 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8074 06:48:35.521792 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8075 06:48:35.525243 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8076 06:48:35.528542 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8077 06:48:35.531863 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8078 06:48:35.538166 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8079 06:48:35.541803 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8080 06:48:35.544951 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8081 06:48:35.547986 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8082 06:48:35.552006 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8083 06:48:35.557941 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8084 06:48:35.561634 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8085 06:48:35.565259 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8086 06:48:35.565731 ==
8087 06:48:35.568674 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 06:48:35.571353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 06:48:35.575070 ==
8090 06:48:35.575627 DQS Delay:
8091 06:48:35.575999 DQS0 = 0, DQS1 = 0
8092 06:48:35.578316 DQM Delay:
8093 06:48:35.578943 DQM0 = 131, DQM1 = 124
8094 06:48:35.581644 DQ Delay:
8095 06:48:35.584967 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8096 06:48:35.588471 DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139
8097 06:48:35.591284 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8098 06:48:35.595100 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8099 06:48:35.595656
8100 06:48:35.596066
8101 06:48:35.596425 ==
8102 06:48:35.598327 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 06:48:35.601580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 06:48:35.602138 ==
8105 06:48:35.602564
8106 06:48:35.602918
8107 06:48:35.604712 TX Vref Scan disable
8108 06:48:35.608489 == TX Byte 0 ==
8109 06:48:35.611587 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8110 06:48:35.615367 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8111 06:48:35.618174 == TX Byte 1 ==
8112 06:48:35.621744 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8113 06:48:35.625038 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8114 06:48:35.625676 ==
8115 06:48:35.628321 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 06:48:35.631431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 06:48:35.634653 ==
8118 06:48:35.648283
8119 06:48:35.651254 TX Vref early break, caculate TX vref
8120 06:48:35.654459 TX Vref=16, minBit 3, minWin=22, winSum=371
8121 06:48:35.658306 TX Vref=18, minBit 9, minWin=22, winSum=379
8122 06:48:35.661680 TX Vref=20, minBit 8, minWin=23, winSum=389
8123 06:48:35.664504 TX Vref=22, minBit 13, minWin=23, winSum=399
8124 06:48:35.668391 TX Vref=24, minBit 11, minWin=24, winSum=407
8125 06:48:35.675217 TX Vref=26, minBit 4, minWin=25, winSum=417
8126 06:48:35.678225 TX Vref=28, minBit 3, minWin=25, winSum=418
8127 06:48:35.681652 TX Vref=30, minBit 0, minWin=26, winSum=424
8128 06:48:35.684882 TX Vref=32, minBit 8, minWin=25, winSum=416
8129 06:48:35.688002 TX Vref=34, minBit 4, minWin=24, winSum=405
8130 06:48:35.691357 TX Vref=36, minBit 0, minWin=24, winSum=392
8131 06:48:35.698072 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
8132 06:48:35.698675
8133 06:48:35.702053 Final TX Range 0 Vref 30
8134 06:48:35.702677
8135 06:48:35.703055 ==
8136 06:48:35.705325 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 06:48:35.708134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 06:48:35.708696 ==
8139 06:48:35.709059
8140 06:48:35.709397
8141 06:48:35.711635 TX Vref Scan disable
8142 06:48:35.718633 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8143 06:48:35.719211 == TX Byte 0 ==
8144 06:48:35.721643 u2DelayCellOfst[0]=14 cells (4 PI)
8145 06:48:35.725063 u2DelayCellOfst[1]=21 cells (6 PI)
8146 06:48:35.728850 u2DelayCellOfst[2]=10 cells (3 PI)
8147 06:48:35.731803 u2DelayCellOfst[3]=14 cells (4 PI)
8148 06:48:35.734777 u2DelayCellOfst[4]=10 cells (3 PI)
8149 06:48:35.738716 u2DelayCellOfst[5]=0 cells (0 PI)
8150 06:48:35.741877 u2DelayCellOfst[6]=21 cells (6 PI)
8151 06:48:35.745106 u2DelayCellOfst[7]=21 cells (6 PI)
8152 06:48:35.748508 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8153 06:48:35.752046 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8154 06:48:35.752516 == TX Byte 1 ==
8155 06:48:35.755073 u2DelayCellOfst[8]=0 cells (0 PI)
8156 06:48:35.758515 u2DelayCellOfst[9]=0 cells (0 PI)
8157 06:48:35.762292 u2DelayCellOfst[10]=7 cells (2 PI)
8158 06:48:35.765240 u2DelayCellOfst[11]=0 cells (0 PI)
8159 06:48:35.768220 u2DelayCellOfst[12]=10 cells (3 PI)
8160 06:48:35.772262 u2DelayCellOfst[13]=10 cells (3 PI)
8161 06:48:35.775122 u2DelayCellOfst[14]=14 cells (4 PI)
8162 06:48:35.778534 u2DelayCellOfst[15]=10 cells (3 PI)
8163 06:48:35.781775 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8164 06:48:35.788745 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8165 06:48:35.789333 DramC Write-DBI on
8166 06:48:35.789707 ==
8167 06:48:35.791844 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 06:48:35.795082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 06:48:35.795545 ==
8170 06:48:35.795909
8171 06:48:35.798798
8172 06:48:35.799354 TX Vref Scan disable
8173 06:48:35.801562 == TX Byte 0 ==
8174 06:48:35.804812 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8175 06:48:35.808520 == TX Byte 1 ==
8176 06:48:35.811640 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8177 06:48:35.812104 DramC Write-DBI off
8178 06:48:35.812635
8179 06:48:35.815265 [DATLAT]
8180 06:48:35.815725 Freq=1600, CH0 RK1
8181 06:48:35.816090
8182 06:48:35.818595 DATLAT Default: 0xf
8183 06:48:35.819156 0, 0xFFFF, sum = 0
8184 06:48:35.821907 1, 0xFFFF, sum = 0
8185 06:48:35.822520 2, 0xFFFF, sum = 0
8186 06:48:35.825585 3, 0xFFFF, sum = 0
8187 06:48:35.826148 4, 0xFFFF, sum = 0
8188 06:48:35.828696 5, 0xFFFF, sum = 0
8189 06:48:35.829271 6, 0xFFFF, sum = 0
8190 06:48:35.831726 7, 0xFFFF, sum = 0
8191 06:48:35.835808 8, 0xFFFF, sum = 0
8192 06:48:35.836405 9, 0xFFFF, sum = 0
8193 06:48:35.838353 10, 0xFFFF, sum = 0
8194 06:48:35.839075 11, 0xFFFF, sum = 0
8195 06:48:35.841807 12, 0xFFFF, sum = 0
8196 06:48:35.842278 13, 0xFFFF, sum = 0
8197 06:48:35.845133 14, 0x0, sum = 1
8198 06:48:35.845809 15, 0x0, sum = 2
8199 06:48:35.848518 16, 0x0, sum = 3
8200 06:48:35.848989 17, 0x0, sum = 4
8201 06:48:35.849362 best_step = 15
8202 06:48:35.851490
8203 06:48:35.851950 ==
8204 06:48:35.855036 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 06:48:35.858537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 06:48:35.859050 ==
8207 06:48:35.859416 RX Vref Scan: 0
8208 06:48:35.859908
8209 06:48:35.861345 RX Vref 0 -> 0, step: 1
8210 06:48:35.861764
8211 06:48:35.865087 RX Delay 11 -> 252, step: 4
8212 06:48:35.868294 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8213 06:48:35.871672 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8214 06:48:35.878550 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8215 06:48:35.881608 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8216 06:48:35.885129 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8217 06:48:35.888180 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8218 06:48:35.891980 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8219 06:48:35.898883 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8220 06:48:35.901770 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8221 06:48:35.904847 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8222 06:48:35.908763 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8223 06:48:35.911912 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8224 06:48:35.918304 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8225 06:48:35.921853 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8226 06:48:35.925519 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8227 06:48:35.928484 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8228 06:48:35.929041 ==
8229 06:48:35.932439 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 06:48:35.938469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 06:48:35.939032 ==
8232 06:48:35.939526 DQS Delay:
8233 06:48:35.941997 DQS0 = 0, DQS1 = 0
8234 06:48:35.942587 DQM Delay:
8235 06:48:35.942960 DQM0 = 126, DQM1 = 122
8236 06:48:35.944955 DQ Delay:
8237 06:48:35.948677 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8238 06:48:35.951677 DQ4 =124, DQ5 =116, DQ6 =134, DQ7 =134
8239 06:48:35.955188 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8240 06:48:35.958493 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8241 06:48:35.958953
8242 06:48:35.959316
8243 06:48:35.959649
8244 06:48:35.962197 [DramC_TX_OE_Calibration] TA2
8245 06:48:35.965424 Original DQ_B0 (3 6) =30, OEN = 27
8246 06:48:35.968516 Original DQ_B1 (3 6) =30, OEN = 27
8247 06:48:35.972063 24, 0x0, End_B0=24 End_B1=24
8248 06:48:35.972538 25, 0x0, End_B0=25 End_B1=25
8249 06:48:35.975391 26, 0x0, End_B0=26 End_B1=26
8250 06:48:35.978445 27, 0x0, End_B0=27 End_B1=27
8251 06:48:35.981797 28, 0x0, End_B0=28 End_B1=28
8252 06:48:35.985595 29, 0x0, End_B0=29 End_B1=29
8253 06:48:35.986179 30, 0x0, End_B0=30 End_B1=30
8254 06:48:35.988181 31, 0x4545, End_B0=30 End_B1=30
8255 06:48:35.991886 Byte0 end_step=30 best_step=27
8256 06:48:35.995122 Byte1 end_step=30 best_step=27
8257 06:48:35.998210 Byte0 TX OE(2T, 0.5T) = (3, 3)
8258 06:48:35.998733 Byte1 TX OE(2T, 0.5T) = (3, 3)
8259 06:48:36.002240
8260 06:48:36.002881
8261 06:48:36.008383 [DQSOSCAuto] RK1, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8262 06:48:36.012088 CH0 RK1: MR19=303, MR18=180D
8263 06:48:36.018883 CH0_RK1: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8264 06:48:36.022037 [RxdqsGatingPostProcess] freq 1600
8265 06:48:36.025025 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8266 06:48:36.028792 best DQS0 dly(2T, 0.5T) = (1, 1)
8267 06:48:36.031945 best DQS1 dly(2T, 0.5T) = (1, 1)
8268 06:48:36.035051 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8269 06:48:36.038749 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8270 06:48:36.041964 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 06:48:36.045126 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 06:48:36.048866 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 06:48:36.051990 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 06:48:36.052566 Pre-setting of DQS Precalculation
8275 06:48:36.058700 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8276 06:48:36.059256 ==
8277 06:48:36.061650 Dram Type= 6, Freq= 0, CH_1, rank 0
8278 06:48:36.065144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 06:48:36.065611 ==
8280 06:48:36.071811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8281 06:48:36.074780 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8282 06:48:36.078827 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8283 06:48:36.085578 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8284 06:48:36.094661 [CA 0] Center 42 (13~71) winsize 59
8285 06:48:36.098324 [CA 1] Center 42 (13~71) winsize 59
8286 06:48:36.101392 [CA 2] Center 37 (8~66) winsize 59
8287 06:48:36.104925 [CA 3] Center 35 (6~65) winsize 60
8288 06:48:36.108049 [CA 4] Center 37 (7~67) winsize 61
8289 06:48:36.111306 [CA 5] Center 36 (7~66) winsize 60
8290 06:48:36.111861
8291 06:48:36.114506 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8292 06:48:36.115107
8293 06:48:36.117799 [CATrainingPosCal] consider 1 rank data
8294 06:48:36.120963 u2DelayCellTimex100 = 275/100 ps
8295 06:48:36.124911 CA0 delay=42 (13~71),Diff = 7 PI (24 cell)
8296 06:48:36.131352 CA1 delay=42 (13~71),Diff = 7 PI (24 cell)
8297 06:48:36.134517 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8298 06:48:36.137972 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8299 06:48:36.141202 CA4 delay=37 (7~67),Diff = 2 PI (7 cell)
8300 06:48:36.144316 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8301 06:48:36.144810
8302 06:48:36.148299 CA PerBit enable=1, Macro0, CA PI delay=35
8303 06:48:36.148809
8304 06:48:36.151304 [CBTSetCACLKResult] CA Dly = 35
8305 06:48:36.151786 CS Dly: 9 (0~40)
8306 06:48:36.158502 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8307 06:48:36.161454 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8308 06:48:36.161903 ==
8309 06:48:36.164823 Dram Type= 6, Freq= 0, CH_1, rank 1
8310 06:48:36.168476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 06:48:36.168990 ==
8312 06:48:36.174296 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 06:48:36.178042 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 06:48:36.181222 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 06:48:36.187798 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 06:48:36.197648 [CA 0] Center 43 (13~73) winsize 61
8317 06:48:36.201043 [CA 1] Center 43 (15~72) winsize 58
8318 06:48:36.204344 [CA 2] Center 37 (8~67) winsize 60
8319 06:48:36.208238 [CA 3] Center 36 (7~66) winsize 60
8320 06:48:36.211228 [CA 4] Center 38 (8~68) winsize 61
8321 06:48:36.214639 [CA 5] Center 36 (7~66) winsize 60
8322 06:48:36.215193
8323 06:48:36.217733 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8324 06:48:36.218284
8325 06:48:36.221611 [CATrainingPosCal] consider 2 rank data
8326 06:48:36.224802 u2DelayCellTimex100 = 275/100 ps
8327 06:48:36.227512 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8328 06:48:36.234450 CA1 delay=43 (15~71),Diff = 7 PI (24 cell)
8329 06:48:36.238121 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8330 06:48:36.241055 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8331 06:48:36.244685 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8332 06:48:36.247815 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8333 06:48:36.248367
8334 06:48:36.251026 CA PerBit enable=1, Macro0, CA PI delay=36
8335 06:48:36.251574
8336 06:48:36.254799 [CBTSetCACLKResult] CA Dly = 36
8337 06:48:36.258094 CS Dly: 10 (0~43)
8338 06:48:36.261277 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 06:48:36.264414 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 06:48:36.264966
8341 06:48:36.267907 ----->DramcWriteLeveling(PI) begin...
8342 06:48:36.268375 ==
8343 06:48:36.271297 Dram Type= 6, Freq= 0, CH_1, rank 0
8344 06:48:36.274459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 06:48:36.277861 ==
8346 06:48:36.278481 Write leveling (Byte 0): 25 => 25
8347 06:48:36.281252 Write leveling (Byte 1): 29 => 29
8348 06:48:36.284312 DramcWriteLeveling(PI) end<-----
8349 06:48:36.284860
8350 06:48:36.285221 ==
8351 06:48:36.287476 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 06:48:36.294065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 06:48:36.294557 ==
8354 06:48:36.294928 [Gating] SW mode calibration
8355 06:48:36.305007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8356 06:48:36.308098 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8357 06:48:36.310842 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 06:48:36.317878 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 06:48:36.320993 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 06:48:36.324598 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 06:48:36.331397 1 4 16 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
8362 06:48:36.334434 1 4 20 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
8363 06:48:36.337833 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 06:48:36.344764 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 06:48:36.347864 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 06:48:36.351048 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 06:48:36.357500 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 06:48:36.361247 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 06:48:36.364476 1 5 16 | B1->B0 | 2a2a 3030 | 0 0 | (1 0) (1 0)
8370 06:48:36.370926 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8371 06:48:36.374551 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 06:48:36.377711 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 06:48:36.380917 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 06:48:36.387886 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 06:48:36.390896 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 06:48:36.394381 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 06:48:36.400971 1 6 16 | B1->B0 | 3f3f 3030 | 0 0 | (0 0) (0 0)
8378 06:48:36.404339 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 06:48:36.408167 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 06:48:36.414292 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 06:48:36.417801 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 06:48:36.421356 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 06:48:36.427742 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 06:48:36.431272 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8385 06:48:36.434262 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8386 06:48:36.445258 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8387 06:48:36.446068 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 06:48:36.448186 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 06:48:36.454812 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 06:48:36.458111 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 06:48:36.461126 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 06:48:36.464452 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 06:48:36.471510 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 06:48:36.474662 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 06:48:36.477798 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 06:48:36.484224 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 06:48:36.487879 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 06:48:36.490985 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 06:48:36.497936 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 06:48:36.501263 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8401 06:48:36.504463 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8402 06:48:36.511367 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 06:48:36.514318 Total UI for P1: 0, mck2ui 16
8404 06:48:36.517453 best dqsien dly found for B0: ( 1, 9, 14)
8405 06:48:36.517926 Total UI for P1: 0, mck2ui 16
8406 06:48:36.524226 best dqsien dly found for B1: ( 1, 9, 16)
8407 06:48:36.528077 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8408 06:48:36.530868 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8409 06:48:36.531327
8410 06:48:36.534196 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8411 06:48:36.537538 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8412 06:48:36.540763 [Gating] SW calibration Done
8413 06:48:36.541372 ==
8414 06:48:36.543968 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 06:48:36.547485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 06:48:36.548064 ==
8417 06:48:36.550831 RX Vref Scan: 0
8418 06:48:36.551278
8419 06:48:36.551633 RX Vref 0 -> 0, step: 1
8420 06:48:36.551990
8421 06:48:36.554603 RX Delay 0 -> 252, step: 8
8422 06:48:36.557390 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8423 06:48:36.564611 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8424 06:48:36.567424 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8425 06:48:36.571215 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8426 06:48:36.574269 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8427 06:48:36.578157 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8428 06:48:36.584310 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8429 06:48:36.587690 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8430 06:48:36.591233 iDelay=208, Bit 8, Center 115 (64 ~ 167) 104
8431 06:48:36.594543 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8432 06:48:36.597598 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8433 06:48:36.604210 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8434 06:48:36.607900 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8435 06:48:36.611157 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8436 06:48:36.614014 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8437 06:48:36.617858 iDelay=208, Bit 15, Center 131 (80 ~ 183) 104
8438 06:48:36.618280 ==
8439 06:48:36.621168 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 06:48:36.627650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 06:48:36.628072 ==
8442 06:48:36.628405 DQS Delay:
8443 06:48:36.630859 DQS0 = 0, DQS1 = 0
8444 06:48:36.631280 DQM Delay:
8445 06:48:36.634452 DQM0 = 135, DQM1 = 127
8446 06:48:36.634875 DQ Delay:
8447 06:48:36.637684 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8448 06:48:36.641277 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8449 06:48:36.644439 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8450 06:48:36.647821 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8451 06:48:36.648263
8452 06:48:36.648599
8453 06:48:36.648905 ==
8454 06:48:36.651212 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 06:48:36.654744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 06:48:36.658148 ==
8457 06:48:36.658698
8458 06:48:36.659034
8459 06:48:36.659341 TX Vref Scan disable
8460 06:48:36.662102 == TX Byte 0 ==
8461 06:48:36.665159 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8462 06:48:36.667990 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8463 06:48:36.671435 == TX Byte 1 ==
8464 06:48:36.674895 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8465 06:48:36.677870 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8466 06:48:36.678290 ==
8467 06:48:36.681185 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 06:48:36.687947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 06:48:36.688355 ==
8470 06:48:36.701361
8471 06:48:36.704569 TX Vref early break, caculate TX vref
8472 06:48:36.707508 TX Vref=16, minBit 8, minWin=21, winSum=362
8473 06:48:36.711020 TX Vref=18, minBit 8, minWin=21, winSum=370
8474 06:48:36.714823 TX Vref=20, minBit 8, minWin=22, winSum=384
8475 06:48:36.717916 TX Vref=22, minBit 8, minWin=22, winSum=389
8476 06:48:36.721194 TX Vref=24, minBit 5, minWin=24, winSum=407
8477 06:48:36.727897 TX Vref=26, minBit 8, minWin=24, winSum=411
8478 06:48:36.730725 TX Vref=28, minBit 11, minWin=24, winSum=418
8479 06:48:36.734424 TX Vref=30, minBit 8, minWin=24, winSum=413
8480 06:48:36.737716 TX Vref=32, minBit 11, minWin=24, winSum=408
8481 06:48:36.740977 TX Vref=34, minBit 11, minWin=23, winSum=397
8482 06:48:36.744451 TX Vref=36, minBit 8, minWin=23, winSum=387
8483 06:48:36.751212 [TxChooseVref] Worse bit 11, Min win 24, Win sum 418, Final Vref 28
8484 06:48:36.751669
8485 06:48:36.754487 Final TX Range 0 Vref 28
8486 06:48:36.754873
8487 06:48:36.755212 ==
8488 06:48:36.757467 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 06:48:36.760868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 06:48:36.761332 ==
8491 06:48:36.761671
8492 06:48:36.764370
8493 06:48:36.764965 TX Vref Scan disable
8494 06:48:36.770923 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8495 06:48:36.771492 == TX Byte 0 ==
8496 06:48:36.774131 u2DelayCellOfst[0]=14 cells (4 PI)
8497 06:48:36.777417 u2DelayCellOfst[1]=10 cells (3 PI)
8498 06:48:36.781006 u2DelayCellOfst[2]=0 cells (0 PI)
8499 06:48:36.784374 u2DelayCellOfst[3]=7 cells (2 PI)
8500 06:48:36.787963 u2DelayCellOfst[4]=7 cells (2 PI)
8501 06:48:36.791215 u2DelayCellOfst[5]=17 cells (5 PI)
8502 06:48:36.794438 u2DelayCellOfst[6]=17 cells (5 PI)
8503 06:48:36.797462 u2DelayCellOfst[7]=7 cells (2 PI)
8504 06:48:36.801317 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8505 06:48:36.804567 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8506 06:48:36.807690 == TX Byte 1 ==
8507 06:48:36.811050 u2DelayCellOfst[8]=0 cells (0 PI)
8508 06:48:36.811472 u2DelayCellOfst[9]=7 cells (2 PI)
8509 06:48:36.814361 u2DelayCellOfst[10]=10 cells (3 PI)
8510 06:48:36.817688 u2DelayCellOfst[11]=7 cells (2 PI)
8511 06:48:36.821294 u2DelayCellOfst[12]=14 cells (4 PI)
8512 06:48:36.824322 u2DelayCellOfst[13]=17 cells (5 PI)
8513 06:48:36.827431 u2DelayCellOfst[14]=17 cells (5 PI)
8514 06:48:36.830823 u2DelayCellOfst[15]=21 cells (6 PI)
8515 06:48:36.834022 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8516 06:48:36.841051 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8517 06:48:36.841472 DramC Write-DBI on
8518 06:48:36.841871 ==
8519 06:48:36.844065 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 06:48:36.851071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 06:48:36.851493 ==
8522 06:48:36.851828
8523 06:48:36.852136
8524 06:48:36.852432 TX Vref Scan disable
8525 06:48:36.854729 == TX Byte 0 ==
8526 06:48:36.857615 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8527 06:48:36.861232 == TX Byte 1 ==
8528 06:48:36.864276 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8529 06:48:36.864954 DramC Write-DBI off
8530 06:48:36.867633
8531 06:48:36.868002 [DATLAT]
8532 06:48:36.868375 Freq=1600, CH1 RK0
8533 06:48:36.868826
8534 06:48:36.871543 DATLAT Default: 0xf
8535 06:48:36.872098 0, 0xFFFF, sum = 0
8536 06:48:36.874744 1, 0xFFFF, sum = 0
8537 06:48:36.875164 2, 0xFFFF, sum = 0
8538 06:48:36.878233 3, 0xFFFF, sum = 0
8539 06:48:36.878765 4, 0xFFFF, sum = 0
8540 06:48:36.881320 5, 0xFFFF, sum = 0
8541 06:48:36.884505 6, 0xFFFF, sum = 0
8542 06:48:36.885071 7, 0xFFFF, sum = 0
8543 06:48:36.887960 8, 0xFFFF, sum = 0
8544 06:48:36.888399 9, 0xFFFF, sum = 0
8545 06:48:36.891349 10, 0xFFFF, sum = 0
8546 06:48:36.891925 11, 0xFFFF, sum = 0
8547 06:48:36.894486 12, 0xFFFF, sum = 0
8548 06:48:36.894951 13, 0xFFFF, sum = 0
8549 06:48:36.897927 14, 0x0, sum = 1
8550 06:48:36.898525 15, 0x0, sum = 2
8551 06:48:36.901335 16, 0x0, sum = 3
8552 06:48:36.901826 17, 0x0, sum = 4
8553 06:48:36.902179 best_step = 15
8554 06:48:36.904656
8555 06:48:36.905078 ==
8556 06:48:36.908337 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 06:48:36.911554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 06:48:36.911979 ==
8559 06:48:36.912309 RX Vref Scan: 1
8560 06:48:36.912619
8561 06:48:36.914753 Set Vref Range= 24 -> 127
8562 06:48:36.915223
8563 06:48:36.918555 RX Vref 24 -> 127, step: 1
8564 06:48:36.918988
8565 06:48:36.921297 RX Delay 19 -> 252, step: 4
8566 06:48:36.921777
8567 06:48:36.924724 Set Vref, RX VrefLevel [Byte0]: 24
8568 06:48:36.928382 [Byte1]: 24
8569 06:48:36.928979
8570 06:48:36.931442 Set Vref, RX VrefLevel [Byte0]: 25
8571 06:48:36.934684 [Byte1]: 25
8572 06:48:36.935147
8573 06:48:36.938252 Set Vref, RX VrefLevel [Byte0]: 26
8574 06:48:36.941094 [Byte1]: 26
8575 06:48:36.944818
8576 06:48:36.945422 Set Vref, RX VrefLevel [Byte0]: 27
8577 06:48:36.947982 [Byte1]: 27
8578 06:48:36.952303
8579 06:48:36.952767 Set Vref, RX VrefLevel [Byte0]: 28
8580 06:48:36.955880 [Byte1]: 28
8581 06:48:36.959763
8582 06:48:36.960188 Set Vref, RX VrefLevel [Byte0]: 29
8583 06:48:36.963250 [Byte1]: 29
8584 06:48:36.967535
8585 06:48:36.967954 Set Vref, RX VrefLevel [Byte0]: 30
8586 06:48:36.970475 [Byte1]: 30
8587 06:48:36.974958
8588 06:48:36.975583 Set Vref, RX VrefLevel [Byte0]: 31
8589 06:48:36.978071 [Byte1]: 31
8590 06:48:36.982646
8591 06:48:36.983072 Set Vref, RX VrefLevel [Byte0]: 32
8592 06:48:36.985954 [Byte1]: 32
8593 06:48:36.989996
8594 06:48:36.990453 Set Vref, RX VrefLevel [Byte0]: 33
8595 06:48:36.993653 [Byte1]: 33
8596 06:48:36.997881
8597 06:48:36.998308 Set Vref, RX VrefLevel [Byte0]: 34
8598 06:48:37.001011 [Byte1]: 34
8599 06:48:37.005297
8600 06:48:37.005730 Set Vref, RX VrefLevel [Byte0]: 35
8601 06:48:37.009049 [Byte1]: 35
8602 06:48:37.012876
8603 06:48:37.013458 Set Vref, RX VrefLevel [Byte0]: 36
8604 06:48:37.016219 [Byte1]: 36
8605 06:48:37.020390
8606 06:48:37.020808 Set Vref, RX VrefLevel [Byte0]: 37
8607 06:48:37.023541 [Byte1]: 37
8608 06:48:37.028013
8609 06:48:37.028430 Set Vref, RX VrefLevel [Byte0]: 38
8610 06:48:37.031156 [Byte1]: 38
8611 06:48:37.035661
8612 06:48:37.036096 Set Vref, RX VrefLevel [Byte0]: 39
8613 06:48:37.038741 [Byte1]: 39
8614 06:48:37.043435
8615 06:48:37.043832 Set Vref, RX VrefLevel [Byte0]: 40
8616 06:48:37.046836 [Byte1]: 40
8617 06:48:37.050515
8618 06:48:37.050903 Set Vref, RX VrefLevel [Byte0]: 41
8619 06:48:37.053788 [Byte1]: 41
8620 06:48:37.058140
8621 06:48:37.058598 Set Vref, RX VrefLevel [Byte0]: 42
8622 06:48:37.061931 [Byte1]: 42
8623 06:48:37.065595
8624 06:48:37.066166 Set Vref, RX VrefLevel [Byte0]: 43
8625 06:48:37.069674 [Byte1]: 43
8626 06:48:37.073390
8627 06:48:37.073866 Set Vref, RX VrefLevel [Byte0]: 44
8628 06:48:37.076838 [Byte1]: 44
8629 06:48:37.080818
8630 06:48:37.081411 Set Vref, RX VrefLevel [Byte0]: 45
8631 06:48:37.084568 [Byte1]: 45
8632 06:48:37.088277
8633 06:48:37.088692 Set Vref, RX VrefLevel [Byte0]: 46
8634 06:48:37.092236 [Byte1]: 46
8635 06:48:37.095899
8636 06:48:37.096318 Set Vref, RX VrefLevel [Byte0]: 47
8637 06:48:37.099126 [Byte1]: 47
8638 06:48:37.103528
8639 06:48:37.103944 Set Vref, RX VrefLevel [Byte0]: 48
8640 06:48:37.107092 [Byte1]: 48
8641 06:48:37.110949
8642 06:48:37.111368 Set Vref, RX VrefLevel [Byte0]: 49
8643 06:48:37.114961 [Byte1]: 49
8644 06:48:37.119213
8645 06:48:37.119630 Set Vref, RX VrefLevel [Byte0]: 50
8646 06:48:37.121961 [Byte1]: 50
8647 06:48:37.126561
8648 06:48:37.127027 Set Vref, RX VrefLevel [Byte0]: 51
8649 06:48:37.130192 [Byte1]: 51
8650 06:48:37.133626
8651 06:48:37.134082 Set Vref, RX VrefLevel [Byte0]: 52
8652 06:48:37.137105 [Byte1]: 52
8653 06:48:37.141827
8654 06:48:37.142354 Set Vref, RX VrefLevel [Byte0]: 53
8655 06:48:37.144682 [Byte1]: 53
8656 06:48:37.149272
8657 06:48:37.149752 Set Vref, RX VrefLevel [Byte0]: 54
8658 06:48:37.152097 [Byte1]: 54
8659 06:48:37.156739
8660 06:48:37.157197 Set Vref, RX VrefLevel [Byte0]: 55
8661 06:48:37.159858 [Byte1]: 55
8662 06:48:37.164273
8663 06:48:37.164865 Set Vref, RX VrefLevel [Byte0]: 56
8664 06:48:37.167438 [Byte1]: 56
8665 06:48:37.171791
8666 06:48:37.172217 Set Vref, RX VrefLevel [Byte0]: 57
8667 06:48:37.175004 [Byte1]: 57
8668 06:48:37.179960
8669 06:48:37.180531 Set Vref, RX VrefLevel [Byte0]: 58
8670 06:48:37.182905 [Byte1]: 58
8671 06:48:37.186900
8672 06:48:37.187353 Set Vref, RX VrefLevel [Byte0]: 59
8673 06:48:37.190468 [Byte1]: 59
8674 06:48:37.194237
8675 06:48:37.194802 Set Vref, RX VrefLevel [Byte0]: 60
8676 06:48:37.198189 [Byte1]: 60
8677 06:48:37.202106
8678 06:48:37.202690 Set Vref, RX VrefLevel [Byte0]: 61
8679 06:48:37.205739 [Byte1]: 61
8680 06:48:37.209924
8681 06:48:37.210597 Set Vref, RX VrefLevel [Byte0]: 62
8682 06:48:37.213560 [Byte1]: 62
8683 06:48:37.217555
8684 06:48:37.218031 Set Vref, RX VrefLevel [Byte0]: 63
8685 06:48:37.220557 [Byte1]: 63
8686 06:48:37.224815
8687 06:48:37.225344 Set Vref, RX VrefLevel [Byte0]: 64
8688 06:48:37.228623 [Byte1]: 64
8689 06:48:37.232513
8690 06:48:37.233022 Set Vref, RX VrefLevel [Byte0]: 65
8691 06:48:37.236020 [Byte1]: 65
8692 06:48:37.240230
8693 06:48:37.240643 Set Vref, RX VrefLevel [Byte0]: 66
8694 06:48:37.243757 [Byte1]: 66
8695 06:48:37.247790
8696 06:48:37.248218 Set Vref, RX VrefLevel [Byte0]: 67
8697 06:48:37.250867 [Byte1]: 67
8698 06:48:37.255187
8699 06:48:37.255631 Set Vref, RX VrefLevel [Byte0]: 68
8700 06:48:37.258658 [Byte1]: 68
8701 06:48:37.262854
8702 06:48:37.263325 Set Vref, RX VrefLevel [Byte0]: 69
8703 06:48:37.265966 [Byte1]: 69
8704 06:48:37.270000
8705 06:48:37.270451 Set Vref, RX VrefLevel [Byte0]: 70
8706 06:48:37.273258 [Byte1]: 70
8707 06:48:37.277249
8708 06:48:37.277330 Set Vref, RX VrefLevel [Byte0]: 71
8709 06:48:37.281075 [Byte1]: 71
8710 06:48:37.285622
8711 06:48:37.285703 Set Vref, RX VrefLevel [Byte0]: 72
8712 06:48:37.288546 [Byte1]: 72
8713 06:48:37.292565
8714 06:48:37.292646 Set Vref, RX VrefLevel [Byte0]: 73
8715 06:48:37.296025 [Byte1]: 73
8716 06:48:37.300507
8717 06:48:37.300589 Set Vref, RX VrefLevel [Byte0]: 74
8718 06:48:37.303803 [Byte1]: 74
8719 06:48:37.307618
8720 06:48:37.307698 Set Vref, RX VrefLevel [Byte0]: 75
8721 06:48:37.311371 [Byte1]: 75
8722 06:48:37.315595
8723 06:48:37.315677 Final RX Vref Byte 0 = 59 to rank0
8724 06:48:37.318912 Final RX Vref Byte 1 = 56 to rank0
8725 06:48:37.321910 Final RX Vref Byte 0 = 59 to rank1
8726 06:48:37.325019 Final RX Vref Byte 1 = 56 to rank1==
8727 06:48:37.328711 Dram Type= 6, Freq= 0, CH_1, rank 0
8728 06:48:37.335508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 06:48:37.335590 ==
8730 06:48:37.335664 DQS Delay:
8731 06:48:37.335731 DQS0 = 0, DQS1 = 0
8732 06:48:37.338720 DQM Delay:
8733 06:48:37.338815 DQM0 = 131, DQM1 = 124
8734 06:48:37.342311 DQ Delay:
8735 06:48:37.345249 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8736 06:48:37.349129 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8737 06:48:37.352285 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8738 06:48:37.355594 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8739 06:48:37.355676
8740 06:48:37.355740
8741 06:48:37.355799
8742 06:48:37.358751 [DramC_TX_OE_Calibration] TA2
8743 06:48:37.361993 Original DQ_B0 (3 6) =30, OEN = 27
8744 06:48:37.365478 Original DQ_B1 (3 6) =30, OEN = 27
8745 06:48:37.368661 24, 0x0, End_B0=24 End_B1=24
8746 06:48:37.368745 25, 0x0, End_B0=25 End_B1=25
8747 06:48:37.372534 26, 0x0, End_B0=26 End_B1=26
8748 06:48:37.375290 27, 0x0, End_B0=27 End_B1=27
8749 06:48:37.378778 28, 0x0, End_B0=28 End_B1=28
8750 06:48:37.378860 29, 0x0, End_B0=29 End_B1=29
8751 06:48:37.382178 30, 0x0, End_B0=30 End_B1=30
8752 06:48:37.385717 31, 0x4141, End_B0=30 End_B1=30
8753 06:48:37.389157 Byte0 end_step=30 best_step=27
8754 06:48:37.392125 Byte1 end_step=30 best_step=27
8755 06:48:37.395322 Byte0 TX OE(2T, 0.5T) = (3, 3)
8756 06:48:37.395431 Byte1 TX OE(2T, 0.5T) = (3, 3)
8757 06:48:37.395532
8758 06:48:37.395659
8759 06:48:37.405499 [DQSOSCAuto] RK0, (LSB)MR18= 0x1600, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
8760 06:48:37.409034 CH1 RK0: MR19=303, MR18=1600
8761 06:48:37.412487 CH1_RK0: MR19=0x303, MR18=0x1600, DQSOSC=398, MR23=63, INC=23, DEC=15
8762 06:48:37.415862
8763 06:48:37.418787 ----->DramcWriteLeveling(PI) begin...
8764 06:48:37.418871 ==
8765 06:48:37.422531 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 06:48:37.425664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 06:48:37.425745 ==
8768 06:48:37.428938 Write leveling (Byte 0): 26 => 26
8769 06:48:37.432131 Write leveling (Byte 1): 29 => 29
8770 06:48:37.435843 DramcWriteLeveling(PI) end<-----
8771 06:48:37.435927
8772 06:48:37.436004 ==
8773 06:48:37.438715 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 06:48:37.442358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 06:48:37.442492 ==
8776 06:48:37.445572 [Gating] SW mode calibration
8777 06:48:37.452424 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8778 06:48:37.459135 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8779 06:48:37.462029 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 06:48:37.465712 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 06:48:37.472044 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8782 06:48:37.475825 1 4 12 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
8783 06:48:37.478977 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 06:48:37.486027 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 06:48:37.488788 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 06:48:37.492339 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 06:48:37.495863 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 06:48:37.502403 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8789 06:48:37.505590 1 5 8 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 0)
8790 06:48:37.508798 1 5 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
8791 06:48:37.515951 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8792 06:48:37.518593 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 06:48:37.522384 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 06:48:37.528939 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 06:48:37.532339 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 06:48:37.535525 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 06:48:37.542166 1 6 8 | B1->B0 | 2424 3939 | 0 0 | (0 0) (0 0)
8798 06:48:37.545983 1 6 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8799 06:48:37.549014 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 06:48:37.555873 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 06:48:37.558744 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 06:48:37.562404 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 06:48:37.568895 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 06:48:37.572364 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 06:48:37.576052 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8806 06:48:37.579165 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8807 06:48:37.585914 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8808 06:48:37.589124 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 06:48:37.592119 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 06:48:37.598798 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 06:48:37.602157 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 06:48:37.605791 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 06:48:37.612014 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 06:48:37.615775 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 06:48:37.618990 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 06:48:37.625832 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 06:48:37.629194 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 06:48:37.632066 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 06:48:37.639000 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 06:48:37.642483 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8821 06:48:37.645880 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8822 06:48:37.652688 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8823 06:48:37.652769 Total UI for P1: 0, mck2ui 16
8824 06:48:37.655854 best dqsien dly found for B0: ( 1, 9, 6)
8825 06:48:37.662089 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 06:48:37.665875 Total UI for P1: 0, mck2ui 16
8827 06:48:37.668713 best dqsien dly found for B1: ( 1, 9, 10)
8828 06:48:37.672334 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8829 06:48:37.675981 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8830 06:48:37.676060
8831 06:48:37.679180 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8832 06:48:37.682671 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8833 06:48:37.685592 [Gating] SW calibration Done
8834 06:48:37.685667 ==
8835 06:48:37.689178 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 06:48:37.692164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 06:48:37.692242 ==
8838 06:48:37.695644 RX Vref Scan: 0
8839 06:48:37.695727
8840 06:48:37.695812 RX Vref 0 -> 0, step: 1
8841 06:48:37.699066
8842 06:48:37.699154 RX Delay 0 -> 252, step: 8
8843 06:48:37.702596 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8844 06:48:37.708916 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8845 06:48:37.712416 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8846 06:48:37.716195 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8847 06:48:37.719465 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8848 06:48:37.722536 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8849 06:48:37.729620 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8850 06:48:37.732826 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8851 06:48:37.735895 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8852 06:48:37.739383 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8853 06:48:37.742644 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8854 06:48:37.749216 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8855 06:48:37.752422 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8856 06:48:37.755758 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8857 06:48:37.759521 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8858 06:48:37.762586 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8859 06:48:37.765664 ==
8860 06:48:37.769381 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 06:48:37.772387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 06:48:37.772463 ==
8863 06:48:37.772544 DQS Delay:
8864 06:48:37.776054 DQS0 = 0, DQS1 = 0
8865 06:48:37.776129 DQM Delay:
8866 06:48:37.778870 DQM0 = 133, DQM1 = 127
8867 06:48:37.778947 DQ Delay:
8868 06:48:37.782278 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8869 06:48:37.785818 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8870 06:48:37.789153 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8871 06:48:37.792823 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8872 06:48:37.792899
8873 06:48:37.792978
8874 06:48:37.793059 ==
8875 06:48:37.795595 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 06:48:37.802116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 06:48:37.802200 ==
8878 06:48:37.802301
8879 06:48:37.802407
8880 06:48:37.802519 TX Vref Scan disable
8881 06:48:37.806182 == TX Byte 0 ==
8882 06:48:37.809229 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8883 06:48:37.815933 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8884 06:48:37.816011 == TX Byte 1 ==
8885 06:48:37.819538 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8886 06:48:37.822232 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8887 06:48:37.826086 ==
8888 06:48:37.829406 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 06:48:37.832135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 06:48:37.832239 ==
8891 06:48:37.846006
8892 06:48:37.848961 TX Vref early break, caculate TX vref
8893 06:48:37.852543 TX Vref=16, minBit 8, minWin=22, winSum=376
8894 06:48:37.856093 TX Vref=18, minBit 13, minWin=22, winSum=383
8895 06:48:37.859257 TX Vref=20, minBit 8, minWin=22, winSum=388
8896 06:48:37.863152 TX Vref=22, minBit 8, minWin=23, winSum=400
8897 06:48:37.866246 TX Vref=24, minBit 15, minWin=24, winSum=410
8898 06:48:37.872223 TX Vref=26, minBit 8, minWin=24, winSum=414
8899 06:48:37.875579 TX Vref=28, minBit 11, minWin=25, winSum=420
8900 06:48:37.879428 TX Vref=30, minBit 15, minWin=24, winSum=413
8901 06:48:37.882568 TX Vref=32, minBit 0, minWin=24, winSum=411
8902 06:48:37.886262 TX Vref=34, minBit 3, minWin=24, winSum=399
8903 06:48:37.889023 TX Vref=36, minBit 0, minWin=23, winSum=390
8904 06:48:37.895941 [TxChooseVref] Worse bit 11, Min win 25, Win sum 420, Final Vref 28
8905 06:48:37.896024
8906 06:48:37.899136 Final TX Range 0 Vref 28
8907 06:48:37.899218
8908 06:48:37.899282 ==
8909 06:48:37.903023 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 06:48:37.906022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 06:48:37.906107 ==
8912 06:48:37.906172
8913 06:48:37.909286
8914 06:48:37.909379 TX Vref Scan disable
8915 06:48:37.916237 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8916 06:48:37.916319 == TX Byte 0 ==
8917 06:48:37.919193 u2DelayCellOfst[0]=17 cells (5 PI)
8918 06:48:37.922944 u2DelayCellOfst[1]=10 cells (3 PI)
8919 06:48:37.926390 u2DelayCellOfst[2]=0 cells (0 PI)
8920 06:48:37.929113 u2DelayCellOfst[3]=7 cells (2 PI)
8921 06:48:37.932444 u2DelayCellOfst[4]=10 cells (3 PI)
8922 06:48:37.936140 u2DelayCellOfst[5]=17 cells (5 PI)
8923 06:48:37.939269 u2DelayCellOfst[6]=17 cells (5 PI)
8924 06:48:37.942939 u2DelayCellOfst[7]=7 cells (2 PI)
8925 06:48:37.946181 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8926 06:48:37.949377 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8927 06:48:37.952777 == TX Byte 1 ==
8928 06:48:37.956230 u2DelayCellOfst[8]=0 cells (0 PI)
8929 06:48:37.956311 u2DelayCellOfst[9]=3 cells (1 PI)
8930 06:48:37.959186 u2DelayCellOfst[10]=7 cells (2 PI)
8931 06:48:37.962695 u2DelayCellOfst[11]=3 cells (1 PI)
8932 06:48:37.966294 u2DelayCellOfst[12]=10 cells (3 PI)
8933 06:48:37.969470 u2DelayCellOfst[13]=10 cells (3 PI)
8934 06:48:37.972913 u2DelayCellOfst[14]=14 cells (4 PI)
8935 06:48:37.976149 u2DelayCellOfst[15]=14 cells (4 PI)
8936 06:48:37.979226 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8937 06:48:37.986445 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8938 06:48:37.986528 DramC Write-DBI on
8939 06:48:37.986592 ==
8940 06:48:37.989885 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 06:48:37.992841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 06:48:37.995884 ==
8943 06:48:37.995968
8944 06:48:37.996080
8945 06:48:37.996175 TX Vref Scan disable
8946 06:48:37.999576 == TX Byte 0 ==
8947 06:48:38.003010 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8948 06:48:38.006194 == TX Byte 1 ==
8949 06:48:38.009210 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8950 06:48:38.012632 DramC Write-DBI off
8951 06:48:38.012720
8952 06:48:38.012786 [DATLAT]
8953 06:48:38.012845 Freq=1600, CH1 RK1
8954 06:48:38.012907
8955 06:48:38.016225 DATLAT Default: 0xf
8956 06:48:38.016306 0, 0xFFFF, sum = 0
8957 06:48:38.019751 1, 0xFFFF, sum = 0
8958 06:48:38.019834 2, 0xFFFF, sum = 0
8959 06:48:38.022832 3, 0xFFFF, sum = 0
8960 06:48:38.022915 4, 0xFFFF, sum = 0
8961 06:48:38.026154 5, 0xFFFF, sum = 0
8962 06:48:38.029913 6, 0xFFFF, sum = 0
8963 06:48:38.029995 7, 0xFFFF, sum = 0
8964 06:48:38.032937 8, 0xFFFF, sum = 0
8965 06:48:38.033029 9, 0xFFFF, sum = 0
8966 06:48:38.036434 10, 0xFFFF, sum = 0
8967 06:48:38.036516 11, 0xFFFF, sum = 0
8968 06:48:38.039256 12, 0xFFFF, sum = 0
8969 06:48:38.039338 13, 0xFFFF, sum = 0
8970 06:48:38.043208 14, 0x0, sum = 1
8971 06:48:38.043290 15, 0x0, sum = 2
8972 06:48:38.046150 16, 0x0, sum = 3
8973 06:48:38.046232 17, 0x0, sum = 4
8974 06:48:38.049506 best_step = 15
8975 06:48:38.049587
8976 06:48:38.049651 ==
8977 06:48:38.052777 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 06:48:38.056437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 06:48:38.056519 ==
8980 06:48:38.056584 RX Vref Scan: 0
8981 06:48:38.056643
8982 06:48:38.059573 RX Vref 0 -> 0, step: 1
8983 06:48:38.059654
8984 06:48:38.062886 RX Delay 11 -> 252, step: 4
8985 06:48:38.066209 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8986 06:48:38.073151 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8987 06:48:38.076194 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8988 06:48:38.079541 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8989 06:48:38.083009 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8990 06:48:38.086255 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8991 06:48:38.089491 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8992 06:48:38.096067 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8993 06:48:38.099579 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8994 06:48:38.103308 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8995 06:48:38.106275 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8996 06:48:38.109814 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8997 06:48:38.116490 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8998 06:48:38.119988 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8999 06:48:38.123327 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9000 06:48:38.126348 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9001 06:48:38.126469 ==
9002 06:48:38.130056 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 06:48:38.136277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 06:48:38.136357 ==
9005 06:48:38.136441 DQS Delay:
9006 06:48:38.139850 DQS0 = 0, DQS1 = 0
9007 06:48:38.139928 DQM Delay:
9008 06:48:38.140009 DQM0 = 129, DQM1 = 126
9009 06:48:38.142898 DQ Delay:
9010 06:48:38.146563 DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =126
9011 06:48:38.149742 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9012 06:48:38.153115 DQ8 =114, DQ9 =114, DQ10 =128, DQ11 =118
9013 06:48:38.156244 DQ12 =134, DQ13 =136, DQ14 =136, DQ15 =134
9014 06:48:38.156326
9015 06:48:38.156390
9016 06:48:38.156450
9017 06:48:38.159989 [DramC_TX_OE_Calibration] TA2
9018 06:48:38.163112 Original DQ_B0 (3 6) =30, OEN = 27
9019 06:48:38.166201 Original DQ_B1 (3 6) =30, OEN = 27
9020 06:48:38.170043 24, 0x0, End_B0=24 End_B1=24
9021 06:48:38.170126 25, 0x0, End_B0=25 End_B1=25
9022 06:48:38.173207 26, 0x0, End_B0=26 End_B1=26
9023 06:48:38.176251 27, 0x0, End_B0=27 End_B1=27
9024 06:48:38.180200 28, 0x0, End_B0=28 End_B1=28
9025 06:48:38.180285 29, 0x0, End_B0=29 End_B1=29
9026 06:48:38.183330 30, 0x0, End_B0=30 End_B1=30
9027 06:48:38.186784 31, 0x4141, End_B0=30 End_B1=30
9028 06:48:38.189843 Byte0 end_step=30 best_step=27
9029 06:48:38.193318 Byte1 end_step=30 best_step=27
9030 06:48:38.196817 Byte0 TX OE(2T, 0.5T) = (3, 3)
9031 06:48:38.196901 Byte1 TX OE(2T, 0.5T) = (3, 3)
9032 06:48:38.196966
9033 06:48:38.199909
9034 06:48:38.206244 [DQSOSCAuto] RK1, (LSB)MR18= 0x1218, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9035 06:48:38.210208 CH1 RK1: MR19=303, MR18=1218
9036 06:48:38.216349 CH1_RK1: MR19=0x303, MR18=0x1218, DQSOSC=397, MR23=63, INC=23, DEC=15
9037 06:48:38.216430 [RxdqsGatingPostProcess] freq 1600
9038 06:48:38.223035 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9039 06:48:38.226213 best DQS0 dly(2T, 0.5T) = (1, 1)
9040 06:48:38.229670 best DQS1 dly(2T, 0.5T) = (1, 1)
9041 06:48:38.233136 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9042 06:48:38.236345 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9043 06:48:38.240120 best DQS0 dly(2T, 0.5T) = (1, 1)
9044 06:48:38.243132 best DQS1 dly(2T, 0.5T) = (1, 1)
9045 06:48:38.246482 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9046 06:48:38.250214 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9047 06:48:38.250288 Pre-setting of DQS Precalculation
9048 06:48:38.256734 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9049 06:48:38.263501 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9050 06:48:38.269823 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9051 06:48:38.269902
9052 06:48:38.269984
9053 06:48:38.273091 [Calibration Summary] 3200 Mbps
9054 06:48:38.276399 CH 0, Rank 0
9055 06:48:38.276475 SW Impedance : PASS
9056 06:48:38.280344 DUTY Scan : NO K
9057 06:48:38.280419 ZQ Calibration : PASS
9058 06:48:38.283308 Jitter Meter : NO K
9059 06:48:38.286526 CBT Training : PASS
9060 06:48:38.286608 Write leveling : PASS
9061 06:48:38.290184 RX DQS gating : PASS
9062 06:48:38.293002 RX DQ/DQS(RDDQC) : PASS
9063 06:48:38.293076 TX DQ/DQS : PASS
9064 06:48:38.296406 RX DATLAT : PASS
9065 06:48:38.299805 RX DQ/DQS(Engine): PASS
9066 06:48:38.299880 TX OE : PASS
9067 06:48:38.303331 All Pass.
9068 06:48:38.303405
9069 06:48:38.303485 CH 0, Rank 1
9070 06:48:38.306790 SW Impedance : PASS
9071 06:48:38.306866 DUTY Scan : NO K
9072 06:48:38.309975 ZQ Calibration : PASS
9073 06:48:38.313412 Jitter Meter : NO K
9074 06:48:38.313486 CBT Training : PASS
9075 06:48:38.316886 Write leveling : PASS
9076 06:48:38.320210 RX DQS gating : PASS
9077 06:48:38.320282 RX DQ/DQS(RDDQC) : PASS
9078 06:48:38.323030 TX DQ/DQS : PASS
9079 06:48:38.323110 RX DATLAT : PASS
9080 06:48:38.326355 RX DQ/DQS(Engine): PASS
9081 06:48:38.330346 TX OE : PASS
9082 06:48:38.330468 All Pass.
9083 06:48:38.330551
9084 06:48:38.330627 CH 1, Rank 0
9085 06:48:38.333109 SW Impedance : PASS
9086 06:48:38.336534 DUTY Scan : NO K
9087 06:48:38.336609 ZQ Calibration : PASS
9088 06:48:38.340107 Jitter Meter : NO K
9089 06:48:38.343689 CBT Training : PASS
9090 06:48:38.343771 Write leveling : PASS
9091 06:48:38.346861 RX DQS gating : PASS
9092 06:48:38.350417 RX DQ/DQS(RDDQC) : PASS
9093 06:48:38.350490 TX DQ/DQS : PASS
9094 06:48:38.353591 RX DATLAT : PASS
9095 06:48:38.356603 RX DQ/DQS(Engine): PASS
9096 06:48:38.356677 TX OE : PASS
9097 06:48:38.356757 All Pass.
9098 06:48:38.360160
9099 06:48:38.360236 CH 1, Rank 1
9100 06:48:38.363222 SW Impedance : PASS
9101 06:48:38.363296 DUTY Scan : NO K
9102 06:48:38.367088 ZQ Calibration : PASS
9103 06:48:38.367163 Jitter Meter : NO K
9104 06:48:38.370010 CBT Training : PASS
9105 06:48:38.373760 Write leveling : PASS
9106 06:48:38.373836 RX DQS gating : PASS
9107 06:48:38.377124 RX DQ/DQS(RDDQC) : PASS
9108 06:48:38.380084 TX DQ/DQS : PASS
9109 06:48:38.380165 RX DATLAT : PASS
9110 06:48:38.383872 RX DQ/DQS(Engine): PASS
9111 06:48:38.387250 TX OE : PASS
9112 06:48:38.387332 All Pass.
9113 06:48:38.387396
9114 06:48:38.387456 DramC Write-DBI on
9115 06:48:38.390360 PER_BANK_REFRESH: Hybrid Mode
9116 06:48:38.393757 TX_TRACKING: ON
9117 06:48:38.400470 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9118 06:48:38.410373 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9119 06:48:38.416905 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9120 06:48:38.420149 [FAST_K] Save calibration result to emmc
9121 06:48:38.423593 sync common calibartion params.
9122 06:48:38.423743 sync cbt_mode0:1, 1:1
9123 06:48:38.427336 dram_init: ddr_geometry: 2
9124 06:48:38.430298 dram_init: ddr_geometry: 2
9125 06:48:38.433956 dram_init: ddr_geometry: 2
9126 06:48:38.434156 0:dram_rank_size:100000000
9127 06:48:38.436934 1:dram_rank_size:100000000
9128 06:48:38.443924 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9129 06:48:38.444230 DFS_SHUFFLE_HW_MODE: ON
9130 06:48:38.447237 dramc_set_vcore_voltage set vcore to 725000
9131 06:48:38.450781 Read voltage for 1600, 0
9132 06:48:38.451190 Vio18 = 0
9133 06:48:38.454204 Vcore = 725000
9134 06:48:38.454681 Vdram = 0
9135 06:48:38.455147 Vddq = 0
9136 06:48:38.457273 Vmddr = 0
9137 06:48:38.457659 switch to 3200 Mbps bootup
9138 06:48:38.460719 [DramcRunTimeConfig]
9139 06:48:38.461136 PHYPLL
9140 06:48:38.464394 DPM_CONTROL_AFTERK: ON
9141 06:48:38.464826 PER_BANK_REFRESH: ON
9142 06:48:38.467817 REFRESH_OVERHEAD_REDUCTION: ON
9143 06:48:38.470941 CMD_PICG_NEW_MODE: OFF
9144 06:48:38.471387 XRTWTW_NEW_MODE: ON
9145 06:48:38.474513 XRTRTR_NEW_MODE: ON
9146 06:48:38.474979 TX_TRACKING: ON
9147 06:48:38.477666 RDSEL_TRACKING: OFF
9148 06:48:38.480819 DQS Precalculation for DVFS: ON
9149 06:48:38.481278 RX_TRACKING: OFF
9150 06:48:38.484173 HW_GATING DBG: ON
9151 06:48:38.484621 ZQCS_ENABLE_LP4: ON
9152 06:48:38.487934 RX_PICG_NEW_MODE: ON
9153 06:48:38.488396 TX_PICG_NEW_MODE: ON
9154 06:48:38.490954 ENABLE_RX_DCM_DPHY: ON
9155 06:48:38.494264 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9156 06:48:38.497814 DUMMY_READ_FOR_TRACKING: OFF
9157 06:48:38.498235 !!! SPM_CONTROL_AFTERK: OFF
9158 06:48:38.500988 !!! SPM could not control APHY
9159 06:48:38.504907 IMPEDANCE_TRACKING: ON
9160 06:48:38.505327 TEMP_SENSOR: ON
9161 06:48:38.507942 HW_SAVE_FOR_SR: OFF
9162 06:48:38.510981 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9163 06:48:38.514593 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9164 06:48:38.515014 Read ODT Tracking: ON
9165 06:48:38.517836 Refresh Rate DeBounce: ON
9166 06:48:38.521453 DFS_NO_QUEUE_FLUSH: ON
9167 06:48:38.524827 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9168 06:48:38.525285 ENABLE_DFS_RUNTIME_MRW: OFF
9169 06:48:38.528114 DDR_RESERVE_NEW_MODE: ON
9170 06:48:38.531141 MR_CBT_SWITCH_FREQ: ON
9171 06:48:38.531552 =========================
9172 06:48:38.551444 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9173 06:48:38.554500 dram_init: ddr_geometry: 2
9174 06:48:38.572953 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9175 06:48:38.576190 dram_init: dram init end (result: 0)
9176 06:48:38.582529 DRAM-K: Full calibration passed in 24588 msecs
9177 06:48:38.585885 MRC: failed to locate region type 0.
9178 06:48:38.586302 DRAM rank0 size:0x100000000,
9179 06:48:38.589647 DRAM rank1 size=0x100000000
9180 06:48:38.599770 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9181 06:48:38.606011 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9182 06:48:38.612561 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9183 06:48:38.619454 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9184 06:48:38.622368 DRAM rank0 size:0x100000000,
9185 06:48:38.626229 DRAM rank1 size=0x100000000
9186 06:48:38.626310 CBMEM:
9187 06:48:38.629531 IMD: root @ 0xfffff000 254 entries.
9188 06:48:38.633360 IMD: root @ 0xffffec00 62 entries.
9189 06:48:38.635882 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9190 06:48:38.639342 WARNING: RO_VPD is uninitialized or empty.
9191 06:48:38.645879 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9192 06:48:38.652572 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9193 06:48:38.665248 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9194 06:48:38.677118 BS: romstage times (exec / console): total (unknown) / 24093 ms
9195 06:48:38.677203
9196 06:48:38.677268
9197 06:48:38.686555 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9198 06:48:38.689968 ARM64: Exception handlers installed.
9199 06:48:38.693340 ARM64: Testing exception
9200 06:48:38.696663 ARM64: Done test exception
9201 06:48:38.696745 Enumerating buses...
9202 06:48:38.700306 Show all devs... Before device enumeration.
9203 06:48:38.703752 Root Device: enabled 1
9204 06:48:38.707236 CPU_CLUSTER: 0: enabled 1
9205 06:48:38.707318 CPU: 00: enabled 1
9206 06:48:38.710129 Compare with tree...
9207 06:48:38.710210 Root Device: enabled 1
9208 06:48:38.713703 CPU_CLUSTER: 0: enabled 1
9209 06:48:38.716835 CPU: 00: enabled 1
9210 06:48:38.716915 Root Device scanning...
9211 06:48:38.720476 scan_static_bus for Root Device
9212 06:48:38.723477 CPU_CLUSTER: 0 enabled
9213 06:48:38.726718 scan_static_bus for Root Device done
9214 06:48:38.730549 scan_bus: bus Root Device finished in 8 msecs
9215 06:48:38.730631 done
9216 06:48:38.737396 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9217 06:48:38.740449 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9218 06:48:38.746983 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9219 06:48:38.750090 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9220 06:48:38.753360 Allocating resources...
9221 06:48:38.753441 Reading resources...
9222 06:48:38.757353 Root Device read_resources bus 0 link: 0
9223 06:48:38.760064 DRAM rank0 size:0x100000000,
9224 06:48:38.763748 DRAM rank1 size=0x100000000
9225 06:48:38.766905 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9226 06:48:38.770051 CPU: 00 missing read_resources
9227 06:48:38.773828 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9228 06:48:38.780063 Root Device read_resources bus 0 link: 0 done
9229 06:48:38.780160 Done reading resources.
9230 06:48:38.786937 Show resources in subtree (Root Device)...After reading.
9231 06:48:38.790571 Root Device child on link 0 CPU_CLUSTER: 0
9232 06:48:38.793650 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 06:48:38.804030 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 06:48:38.804116 CPU: 00
9235 06:48:38.806668 Root Device assign_resources, bus 0 link: 0
9236 06:48:38.810255 CPU_CLUSTER: 0 missing set_resources
9237 06:48:38.813674 Root Device assign_resources, bus 0 link: 0 done
9238 06:48:38.817126 Done setting resources.
9239 06:48:38.823942 Show resources in subtree (Root Device)...After assigning values.
9240 06:48:38.827246 Root Device child on link 0 CPU_CLUSTER: 0
9241 06:48:38.830237 CPU_CLUSTER: 0 child on link 0 CPU: 00
9242 06:48:38.840944 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9243 06:48:38.841026 CPU: 00
9244 06:48:38.843728 Done allocating resources.
9245 06:48:38.847002 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9246 06:48:38.850723 Enabling resources...
9247 06:48:38.850804 done.
9248 06:48:38.854206 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9249 06:48:38.857714 Initializing devices...
9250 06:48:38.857795 Root Device init
9251 06:48:38.860449 init hardware done!
9252 06:48:38.863907 0x00000018: ctrlr->caps
9253 06:48:38.863990 52.000 MHz: ctrlr->f_max
9254 06:48:38.867210 0.400 MHz: ctrlr->f_min
9255 06:48:38.870785 0x40ff8080: ctrlr->voltages
9256 06:48:38.870868 sclk: 390625
9257 06:48:38.870932 Bus Width = 1
9258 06:48:38.873849 sclk: 390625
9259 06:48:38.873930 Bus Width = 1
9260 06:48:38.877217 Early init status = 3
9261 06:48:38.880972 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9262 06:48:38.885235 in-header: 03 fc 00 00 01 00 00 00
9263 06:48:38.888682 in-data: 00
9264 06:48:38.891666 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9265 06:48:38.897196 in-header: 03 fd 00 00 00 00 00 00
9266 06:48:38.900932 in-data:
9267 06:48:38.904292 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9268 06:48:38.908530 in-header: 03 fc 00 00 01 00 00 00
9269 06:48:38.911603 in-data: 00
9270 06:48:38.915277 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9271 06:48:38.920670 in-header: 03 fd 00 00 00 00 00 00
9272 06:48:38.923937 in-data:
9273 06:48:38.927265 [SSUSB] Setting up USB HOST controller...
9274 06:48:38.930447 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9275 06:48:38.933714 [SSUSB] phy power-on done.
9276 06:48:38.937278 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9277 06:48:38.944164 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9278 06:48:38.946816 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9279 06:48:38.953745 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9280 06:48:38.960500 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9281 06:48:38.966743 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9282 06:48:38.973683 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9283 06:48:38.980185 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9284 06:48:38.983867 SPM: binary array size = 0x9dc
9285 06:48:38.986862 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9286 06:48:38.993792 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9287 06:48:39.000767 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9288 06:48:39.004110 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9289 06:48:39.007060 configure_display: Starting display init
9290 06:48:39.043900 anx7625_power_on_init: Init interface.
9291 06:48:39.047273 anx7625_disable_pd_protocol: Disabled PD feature.
9292 06:48:39.050384 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9293 06:48:39.078336 anx7625_start_dp_work: Secure OCM version=00
9294 06:48:39.081478 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9295 06:48:39.096215 sp_tx_get_edid_block: EDID Block = 1
9296 06:48:39.199334 Extracted contents:
9297 06:48:39.202679 header: 00 ff ff ff ff ff ff 00
9298 06:48:39.205728 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9299 06:48:39.209448 version: 01 04
9300 06:48:39.212825 basic params: 95 1f 11 78 0a
9301 06:48:39.215830 chroma info: 76 90 94 55 54 90 27 21 50 54
9302 06:48:39.219051 established: 00 00 00
9303 06:48:39.225846 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9304 06:48:39.229450 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9305 06:48:39.235728 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9306 06:48:39.242390 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9307 06:48:39.248918 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9308 06:48:39.252056 extensions: 00
9309 06:48:39.252479 checksum: fb
9310 06:48:39.252804
9311 06:48:39.255782 Manufacturer: IVO Model 57d Serial Number 0
9312 06:48:39.258947 Made week 0 of 2020
9313 06:48:39.259372 EDID version: 1.4
9314 06:48:39.262438 Digital display
9315 06:48:39.265316 6 bits per primary color channel
9316 06:48:39.265861 DisplayPort interface
9317 06:48:39.268781 Maximum image size: 31 cm x 17 cm
9318 06:48:39.272324 Gamma: 220%
9319 06:48:39.272822 Check DPMS levels
9320 06:48:39.275728 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9321 06:48:39.278934 First detailed timing is preferred timing
9322 06:48:39.282535 Established timings supported:
9323 06:48:39.285526 Standard timings supported:
9324 06:48:39.286103 Detailed timings
9325 06:48:39.292685 Hex of detail: 383680a07038204018303c0035ae10000019
9326 06:48:39.295702 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9327 06:48:39.301842 0780 0798 07c8 0820 hborder 0
9328 06:48:39.305320 0438 043b 0447 0458 vborder 0
9329 06:48:39.308452 -hsync -vsync
9330 06:48:39.308974 Did detailed timing
9331 06:48:39.315233 Hex of detail: 000000000000000000000000000000000000
9332 06:48:39.315685 Manufacturer-specified data, tag 0
9333 06:48:39.321763 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9334 06:48:39.325300 ASCII string: InfoVision
9335 06:48:39.328441 Hex of detail: 000000fe00523134304e574635205248200a
9336 06:48:39.331826 ASCII string: R140NWF5 RH
9337 06:48:39.332241 Checksum
9338 06:48:39.335228 Checksum: 0xfb (valid)
9339 06:48:39.338284 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9340 06:48:39.341310 DSI data_rate: 832800000 bps
9341 06:48:39.348061 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9342 06:48:39.351716 anx7625_parse_edid: pixelclock(138800).
9343 06:48:39.354800 hactive(1920), hsync(48), hfp(24), hbp(88)
9344 06:48:39.358562 vactive(1080), vsync(12), vfp(3), vbp(17)
9345 06:48:39.361367 anx7625_dsi_config: config dsi.
9346 06:48:39.368226 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9347 06:48:39.381291 anx7625_dsi_config: success to config DSI
9348 06:48:39.384692 anx7625_dp_start: MIPI phy setup OK.
9349 06:48:39.387752 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9350 06:48:39.390917 mtk_ddp_mode_set invalid vrefresh 60
9351 06:48:39.394128 main_disp_path_setup
9352 06:48:39.394211 ovl_layer_smi_id_en
9353 06:48:39.397453 ovl_layer_smi_id_en
9354 06:48:39.397535 ccorr_config
9355 06:48:39.397600 aal_config
9356 06:48:39.400660 gamma_config
9357 06:48:39.400744 postmask_config
9358 06:48:39.404529 dither_config
9359 06:48:39.407692 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9360 06:48:39.414054 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9361 06:48:39.418031 Root Device init finished in 555 msecs
9362 06:48:39.418131 CPU_CLUSTER: 0 init
9363 06:48:39.427418 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9364 06:48:39.430535 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9365 06:48:39.434325 APU_MBOX 0x190000b0 = 0x10001
9366 06:48:39.437478 APU_MBOX 0x190001b0 = 0x10001
9367 06:48:39.440518 APU_MBOX 0x190005b0 = 0x10001
9368 06:48:39.444074 APU_MBOX 0x190006b0 = 0x10001
9369 06:48:39.447072 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9370 06:48:39.459514 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9371 06:48:39.472503 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9372 06:48:39.479278 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9373 06:48:39.490949 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9374 06:48:39.499869 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9375 06:48:39.503061 CPU_CLUSTER: 0 init finished in 81 msecs
9376 06:48:39.506177 Devices initialized
9377 06:48:39.509431 Show all devs... After init.
9378 06:48:39.509514 Root Device: enabled 1
9379 06:48:39.513076 CPU_CLUSTER: 0: enabled 1
9380 06:48:39.516407 CPU: 00: enabled 1
9381 06:48:39.519788 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9382 06:48:39.522824 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9383 06:48:39.526345 ELOG: NV offset 0x57f000 size 0x1000
9384 06:48:39.533073 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9385 06:48:39.540272 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9386 06:48:39.543283 ELOG: Event(17) added with size 13 at 2024-02-03 06:48:45 UTC
9387 06:48:39.546545 out: cmd=0x121: 03 db 21 01 00 00 00 00
9388 06:48:39.551353 in-header: 03 ce 00 00 2c 00 00 00
9389 06:48:39.564806 in-data: 91 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9390 06:48:39.570898 ELOG: Event(A1) added with size 10 at 2024-02-03 06:48:45 UTC
9391 06:48:39.578024 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9392 06:48:39.581282 ELOG: Event(A0) added with size 9 at 2024-02-03 06:48:45 UTC
9393 06:48:39.588409 elog_add_boot_reason: Logged dev mode boot
9394 06:48:39.591309 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9395 06:48:39.594448 Finalize devices...
9396 06:48:39.594531 Devices finalized
9397 06:48:39.601399 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9398 06:48:39.604873 Writing coreboot table at 0xffe64000
9399 06:48:39.607894 0. 000000000010a000-0000000000113fff: RAMSTAGE
9400 06:48:39.611490 1. 0000000040000000-00000000400fffff: RAM
9401 06:48:39.615168 2. 0000000040100000-000000004032afff: RAMSTAGE
9402 06:48:39.618217 3. 000000004032b000-00000000545fffff: RAM
9403 06:48:39.625207 4. 0000000054600000-000000005465ffff: BL31
9404 06:48:39.627759 5. 0000000054660000-00000000ffe63fff: RAM
9405 06:48:39.631571 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9406 06:48:39.634525 7. 0000000100000000-000000023fffffff: RAM
9407 06:48:39.638336 Passing 5 GPIOs to payload:
9408 06:48:39.644830 NAME | PORT | POLARITY | VALUE
9409 06:48:39.648123 EC in RW | 0x000000aa | low | undefined
9410 06:48:39.651419 EC interrupt | 0x00000005 | low | undefined
9411 06:48:39.658166 TPM interrupt | 0x000000ab | high | undefined
9412 06:48:39.661172 SD card detect | 0x00000011 | high | undefined
9413 06:48:39.668481 speaker enable | 0x00000093 | high | undefined
9414 06:48:39.671586 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9415 06:48:39.674534 in-header: 03 f9 00 00 02 00 00 00
9416 06:48:39.674617 in-data: 02 00
9417 06:48:39.678553 ADC[4]: Raw value=900590 ID=7
9418 06:48:39.681455 ADC[3]: Raw value=213336 ID=1
9419 06:48:39.681537 RAM Code: 0x71
9420 06:48:39.684868 ADC[6]: Raw value=74557 ID=0
9421 06:48:39.687831 ADC[5]: Raw value=212229 ID=1
9422 06:48:39.687913 SKU Code: 0x1
9423 06:48:39.694920 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b56e
9424 06:48:39.697588 coreboot table: 964 bytes.
9425 06:48:39.701611 IMD ROOT 0. 0xfffff000 0x00001000
9426 06:48:39.705020 IMD SMALL 1. 0xffffe000 0x00001000
9427 06:48:39.707696 RO MCACHE 2. 0xffffc000 0x00001104
9428 06:48:39.711316 CONSOLE 3. 0xfff7c000 0x00080000
9429 06:48:39.714688 FMAP 4. 0xfff7b000 0x00000452
9430 06:48:39.718283 TIME STAMP 5. 0xfff7a000 0x00000910
9431 06:48:39.721145 VBOOT WORK 6. 0xfff66000 0x00014000
9432 06:48:39.721291 RAMOOPS 7. 0xffe66000 0x00100000
9433 06:48:39.724804 COREBOOT 8. 0xffe64000 0x00002000
9434 06:48:39.727997 IMD small region:
9435 06:48:39.731886 IMD ROOT 0. 0xffffec00 0x00000400
9436 06:48:39.734817 VPD 1. 0xffffeb80 0x0000006c
9437 06:48:39.738123 MMC STATUS 2. 0xffffeb60 0x00000004
9438 06:48:39.744742 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9439 06:48:39.744836 Probing TPM: done!
9440 06:48:39.751759 Connected to device vid:did:rid of 1ae0:0028:00
9441 06:48:39.757996 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9442 06:48:39.761691 Initialized TPM device CR50 revision 0
9443 06:48:39.764805 Checking cr50 for pending updates
9444 06:48:39.770847 Reading cr50 TPM mode
9445 06:48:39.779359 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9446 06:48:39.786133 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9447 06:48:39.825813 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9448 06:48:39.829370 Checking segment from ROM address 0x40100000
9449 06:48:39.832514 Checking segment from ROM address 0x4010001c
9450 06:48:39.839761 Loading segment from ROM address 0x40100000
9451 06:48:39.839841 code (compression=0)
9452 06:48:39.846557 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9453 06:48:39.856218 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9454 06:48:39.856300 it's not compressed!
9455 06:48:39.863099 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9456 06:48:39.866331 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9457 06:48:39.886185 Loading segment from ROM address 0x4010001c
9458 06:48:39.886267 Entry Point 0x80000000
9459 06:48:39.889438 Loaded segments
9460 06:48:39.892933 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9461 06:48:39.899707 Jumping to boot code at 0x80000000(0xffe64000)
9462 06:48:39.906816 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9463 06:48:39.913042 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9464 06:48:39.920832 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9465 06:48:39.923966 Checking segment from ROM address 0x40100000
9466 06:48:39.927493 Checking segment from ROM address 0x4010001c
9467 06:48:39.934306 Loading segment from ROM address 0x40100000
9468 06:48:39.934388 code (compression=1)
9469 06:48:39.941448 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9470 06:48:39.950880 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9471 06:48:39.950961 using LZMA
9472 06:48:39.958903 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9473 06:48:39.965993 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9474 06:48:39.969400 Loading segment from ROM address 0x4010001c
9475 06:48:39.969481 Entry Point 0x54601000
9476 06:48:39.973270 Loaded segments
9477 06:48:39.976024 NOTICE: MT8192 bl31_setup
9478 06:48:39.982938 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9479 06:48:39.985894 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9480 06:48:39.990198 WARNING: region 0:
9481 06:48:39.992883 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 06:48:39.992965 WARNING: region 1:
9483 06:48:39.999697 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9484 06:48:39.999779 WARNING: region 2:
9485 06:48:40.006393 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9486 06:48:40.009863 WARNING: region 3:
9487 06:48:40.013061 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 06:48:40.016483 WARNING: region 4:
9489 06:48:40.019409 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 06:48:40.023394 WARNING: region 5:
9491 06:48:40.026544 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 06:48:40.029547 WARNING: region 6:
9493 06:48:40.033275 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 06:48:40.033357 WARNING: region 7:
9495 06:48:40.040033 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 06:48:40.046699 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9497 06:48:40.050230 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9498 06:48:40.053505 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9499 06:48:40.056564 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9500 06:48:40.063495 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9501 06:48:40.066618 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9502 06:48:40.073278 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9503 06:48:40.076969 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9504 06:48:40.079778 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9505 06:48:40.086634 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9506 06:48:40.090500 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9507 06:48:40.093645 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9508 06:48:40.099943 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9509 06:48:40.103644 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9510 06:48:40.106793 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9511 06:48:40.113605 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9512 06:48:40.117286 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9513 06:48:40.123975 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9514 06:48:40.127114 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9515 06:48:40.130674 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9516 06:48:40.137536 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9517 06:48:40.140638 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9518 06:48:40.143633 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9519 06:48:40.150565 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9520 06:48:40.153918 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9521 06:48:40.160819 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9522 06:48:40.163700 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9523 06:48:40.167341 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9524 06:48:40.173895 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9525 06:48:40.177653 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9526 06:48:40.184364 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9527 06:48:40.187678 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9528 06:48:40.191033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9529 06:48:40.194136 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9530 06:48:40.201033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9531 06:48:40.204270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9532 06:48:40.207658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9533 06:48:40.211457 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9534 06:48:40.214647 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9535 06:48:40.220851 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9536 06:48:40.224490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9537 06:48:40.228038 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9538 06:48:40.231144 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9539 06:48:40.237796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9540 06:48:40.241282 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9541 06:48:40.244429 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9542 06:48:40.247583 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9543 06:48:40.254732 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9544 06:48:40.257966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9545 06:48:40.265188 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9546 06:48:40.268121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9547 06:48:40.271651 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9548 06:48:40.278120 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9549 06:48:40.281268 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9550 06:48:40.287868 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9551 06:48:40.291377 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9552 06:48:40.294693 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9553 06:48:40.301500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9554 06:48:40.304664 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9555 06:48:40.311741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9556 06:48:40.315063 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9557 06:48:40.321994 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9558 06:48:40.325123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9559 06:48:40.331933 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9560 06:48:40.335549 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9561 06:48:40.338660 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9562 06:48:40.344970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9563 06:48:40.348539 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9564 06:48:40.355184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9565 06:48:40.358324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9566 06:48:40.361585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9567 06:48:40.368946 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9568 06:48:40.372344 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9569 06:48:40.378504 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9570 06:48:40.382118 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9571 06:48:40.389079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9572 06:48:40.392243 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9573 06:48:40.395447 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9574 06:48:40.402116 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9575 06:48:40.405281 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9576 06:48:40.412156 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9577 06:48:40.415535 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9578 06:48:40.422407 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9579 06:48:40.425882 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9580 06:48:40.429192 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9581 06:48:40.436038 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9582 06:48:40.439189 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9583 06:48:40.446019 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9584 06:48:40.449424 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9585 06:48:40.452421 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9586 06:48:40.459489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9587 06:48:40.463067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9588 06:48:40.469492 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9589 06:48:40.472959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9590 06:48:40.479697 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9591 06:48:40.483178 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9592 06:48:40.486707 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9593 06:48:40.493480 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9594 06:48:40.496312 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9595 06:48:40.500182 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9596 06:48:40.503203 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9597 06:48:40.509986 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9598 06:48:40.513453 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9599 06:48:40.516963 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9600 06:48:40.523170 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9601 06:48:40.526726 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9602 06:48:40.533860 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9603 06:48:40.537143 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9604 06:48:40.540295 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9605 06:48:40.547058 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9606 06:48:40.550072 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9607 06:48:40.553298 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9608 06:48:40.560323 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9609 06:48:40.563449 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9610 06:48:40.570362 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9611 06:48:40.573625 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9612 06:48:40.577435 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9613 06:48:40.583971 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9614 06:48:40.587098 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9615 06:48:40.590451 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9616 06:48:40.593949 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9617 06:48:40.600572 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9618 06:48:40.603500 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9619 06:48:40.607084 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9620 06:48:40.610317 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9621 06:48:40.617147 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9622 06:48:40.620368 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9623 06:48:40.627017 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9624 06:48:40.630390 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9625 06:48:40.633822 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9626 06:48:40.640989 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9627 06:48:40.644221 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9628 06:48:40.647538 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9629 06:48:40.654589 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9630 06:48:40.657377 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9631 06:48:40.664391 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9632 06:48:40.667374 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9633 06:48:40.670573 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9634 06:48:40.677471 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9635 06:48:40.680730 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9636 06:48:40.684459 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9637 06:48:40.691249 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9638 06:48:40.694351 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9639 06:48:40.701086 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9640 06:48:40.704137 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9641 06:48:40.707564 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9642 06:48:40.714211 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9643 06:48:40.717858 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9644 06:48:40.721517 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9645 06:48:40.728349 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9646 06:48:40.731351 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9647 06:48:40.737862 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9648 06:48:40.741663 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9649 06:48:40.744617 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9650 06:48:40.751671 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9651 06:48:40.754830 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9652 06:48:40.758431 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9653 06:48:40.765081 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9654 06:48:40.768397 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9655 06:48:40.775064 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9656 06:48:40.778145 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9657 06:48:40.781501 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9658 06:48:40.788772 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9659 06:48:40.792042 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9660 06:48:40.795034 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9661 06:48:40.802034 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9662 06:48:40.805160 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9663 06:48:40.811670 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9664 06:48:40.815394 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9665 06:48:40.818854 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9666 06:48:40.824841 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9667 06:48:40.828527 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9668 06:48:40.831629 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9669 06:48:40.838371 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9670 06:48:40.841755 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9671 06:48:40.848595 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9672 06:48:40.851761 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9673 06:48:40.855667 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9674 06:48:40.861956 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9675 06:48:40.865057 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9676 06:48:40.871945 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9677 06:48:40.874969 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9678 06:48:40.878740 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9679 06:48:40.885229 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9680 06:48:40.888310 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9681 06:48:40.895105 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9682 06:48:40.898111 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9683 06:48:40.901505 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9684 06:48:40.908364 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9685 06:48:40.911425 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9686 06:48:40.918292 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9687 06:48:40.921520 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9688 06:48:40.924704 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9689 06:48:40.931560 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9690 06:48:40.935208 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9691 06:48:40.941469 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9692 06:48:40.945036 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9693 06:48:40.948428 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9694 06:48:40.955046 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9695 06:48:40.958451 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9696 06:48:40.965305 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9697 06:48:40.968503 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9698 06:48:40.971909 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9699 06:48:40.978578 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9700 06:48:40.981894 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9701 06:48:40.989402 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9702 06:48:40.992184 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9703 06:48:40.995076 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9704 06:48:41.001977 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9705 06:48:41.005113 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9706 06:48:41.012030 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9707 06:48:41.015083 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9708 06:48:41.021716 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9709 06:48:41.025796 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9710 06:48:41.028945 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9711 06:48:41.035161 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9712 06:48:41.038513 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9713 06:48:41.045752 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9714 06:48:41.048812 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9715 06:48:41.051985 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9716 06:48:41.058885 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9717 06:48:41.062356 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9718 06:48:41.069034 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9719 06:48:41.072008 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9720 06:48:41.075176 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9721 06:48:41.082507 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9722 06:48:41.085759 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9723 06:48:41.092872 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9724 06:48:41.095937 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9725 06:48:41.098914 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9726 06:48:41.102289 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9727 06:48:41.109006 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9728 06:48:41.112051 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9729 06:48:41.115793 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9730 06:48:41.118902 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9731 06:48:41.125850 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9732 06:48:41.128778 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9733 06:48:41.135692 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9734 06:48:41.138919 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9735 06:48:41.141911 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9736 06:48:41.149047 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9737 06:48:41.152421 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9738 06:48:41.155433 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9739 06:48:41.162496 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9740 06:48:41.165653 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9741 06:48:41.168651 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9742 06:48:41.175145 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9743 06:48:41.178615 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9744 06:48:41.185231 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9745 06:48:41.188666 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9746 06:48:41.191889 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9747 06:48:41.198733 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9748 06:48:41.201762 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9749 06:48:41.205654 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9750 06:48:41.212029 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9751 06:48:41.215714 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9752 06:48:41.219039 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9753 06:48:41.225239 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9754 06:48:41.229093 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9755 06:48:41.232553 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9756 06:48:41.238645 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9757 06:48:41.242613 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9758 06:48:41.248887 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9759 06:48:41.251971 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9760 06:48:41.255762 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9761 06:48:41.262009 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9762 06:48:41.265794 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9763 06:48:41.268958 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9764 06:48:41.275327 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9765 06:48:41.278455 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9766 06:48:41.282012 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9767 06:48:41.285139 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9768 06:48:41.292304 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9769 06:48:41.295142 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9770 06:48:41.298945 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9771 06:48:41.302473 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9772 06:48:41.308821 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9773 06:48:41.311693 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9774 06:48:41.315397 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9775 06:48:41.318615 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9776 06:48:41.325107 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9777 06:48:41.328374 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9778 06:48:41.331967 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9779 06:48:41.338689 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9780 06:48:41.341638 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9781 06:48:41.348567 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9782 06:48:41.351641 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9783 06:48:41.355622 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9784 06:48:41.361941 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9785 06:48:41.365007 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9786 06:48:41.368359 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9787 06:48:41.375097 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9788 06:48:41.378568 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9789 06:48:41.385319 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9790 06:48:41.389079 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9791 06:48:41.395770 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9792 06:48:41.398477 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9793 06:48:41.402338 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9794 06:48:41.408823 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9795 06:48:41.412422 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9796 06:48:41.415480 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9797 06:48:41.422517 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9798 06:48:41.425614 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9799 06:48:41.431982 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9800 06:48:41.435816 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9801 06:48:41.438910 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9802 06:48:41.458679 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9803 06:48:41.459448 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9804 06:48:41.459809 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9805 06:48:41.460130 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9806 06:48:41.462653 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9807 06:48:41.468860 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9808 06:48:41.472541 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9809 06:48:41.479008 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9810 06:48:41.482736 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9811 06:48:41.485803 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9812 06:48:41.492444 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9813 06:48:41.495679 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9814 06:48:41.502567 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9815 06:48:41.505545 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9816 06:48:41.512448 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9817 06:48:41.515725 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9818 06:48:41.519076 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9819 06:48:41.525658 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9820 06:48:41.528925 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9821 06:48:41.532343 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9822 06:48:41.539624 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9823 06:48:41.542539 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9824 06:48:41.549542 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9825 06:48:41.552756 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9826 06:48:41.555579 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9827 06:48:41.562504 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9828 06:48:41.565713 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9829 06:48:41.572574 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9830 06:48:41.575965 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9831 06:48:41.583290 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9832 06:48:41.585758 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9833 06:48:41.589197 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9834 06:48:41.596293 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9835 06:48:41.599291 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9836 06:48:41.602478 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9837 06:48:41.609201 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9838 06:48:41.612705 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9839 06:48:41.619808 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9840 06:48:41.622857 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9841 06:48:41.626140 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9842 06:48:41.632680 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9843 06:48:41.635678 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9844 06:48:41.642597 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9845 06:48:41.645737 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9846 06:48:41.652420 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9847 06:48:41.655663 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9848 06:48:41.659080 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9849 06:48:41.665503 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9850 06:48:41.669191 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9851 06:48:41.676203 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9852 06:48:41.678877 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9853 06:48:41.682792 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9854 06:48:41.689282 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9855 06:48:41.692407 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9856 06:48:41.699609 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9857 06:48:41.702690 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9858 06:48:41.709624 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9859 06:48:41.712592 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9860 06:48:41.715855 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9861 06:48:41.722339 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9862 06:48:41.725459 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9863 06:48:41.732406 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9864 06:48:41.735743 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9865 06:48:41.738934 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9866 06:48:41.745374 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9867 06:48:41.749102 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9868 06:48:41.755306 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9869 06:48:41.759312 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9870 06:48:41.765460 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9871 06:48:41.769234 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9872 06:48:41.775446 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9873 06:48:41.779168 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9874 06:48:41.782426 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9875 06:48:41.788693 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9876 06:48:41.792527 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9877 06:48:41.799215 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9878 06:48:41.802432 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9879 06:48:41.808858 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9880 06:48:41.812365 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9881 06:48:41.815887 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9882 06:48:41.822377 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9883 06:48:41.825703 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9884 06:48:41.832265 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9885 06:48:41.835980 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9886 06:48:41.842815 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9887 06:48:41.845600 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9888 06:48:41.848799 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9889 06:48:41.855470 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9890 06:48:41.859274 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9891 06:48:41.865555 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9892 06:48:41.869471 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9893 06:48:41.875621 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9894 06:48:41.879505 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9895 06:48:41.882464 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9896 06:48:41.889367 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9897 06:48:41.892718 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9898 06:48:41.896515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9899 06:48:41.903244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9900 06:48:41.906288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9901 06:48:41.912541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9902 06:48:41.916189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9903 06:48:41.922758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9904 06:48:41.925971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9905 06:48:41.932746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9906 06:48:41.936278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9907 06:48:41.942913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9908 06:48:41.946701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9909 06:48:41.953177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9910 06:48:41.956067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9911 06:48:41.962837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9912 06:48:41.965992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9913 06:48:41.969481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9914 06:48:41.976311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9915 06:48:41.979454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9916 06:48:41.986218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9917 06:48:41.989522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9918 06:48:41.996387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9919 06:48:41.999183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9920 06:48:42.005815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9921 06:48:42.008915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9922 06:48:42.015978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9923 06:48:42.019587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9924 06:48:42.025880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9925 06:48:42.029317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9926 06:48:42.035990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9927 06:48:42.039134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9928 06:48:42.046009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9929 06:48:42.048964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9930 06:48:42.055480 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9931 06:48:42.055563 INFO: [APUAPC] vio 0
9932 06:48:42.062776 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9933 06:48:42.066131 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9934 06:48:42.069400 INFO: [APUAPC] D0_APC_0: 0x400510
9935 06:48:42.072516 INFO: [APUAPC] D0_APC_1: 0x0
9936 06:48:42.075917 INFO: [APUAPC] D0_APC_2: 0x1540
9937 06:48:42.079189 INFO: [APUAPC] D0_APC_3: 0x0
9938 06:48:42.082381 INFO: [APUAPC] D1_APC_0: 0xffffffff
9939 06:48:42.086056 INFO: [APUAPC] D1_APC_1: 0xffffffff
9940 06:48:42.089670 INFO: [APUAPC] D1_APC_2: 0x3fffff
9941 06:48:42.092727 INFO: [APUAPC] D1_APC_3: 0x0
9942 06:48:42.095951 INFO: [APUAPC] D2_APC_0: 0xffffffff
9943 06:48:42.099684 INFO: [APUAPC] D2_APC_1: 0xffffffff
9944 06:48:42.103125 INFO: [APUAPC] D2_APC_2: 0x3fffff
9945 06:48:42.106096 INFO: [APUAPC] D2_APC_3: 0x0
9946 06:48:42.109149 INFO: [APUAPC] D3_APC_0: 0xffffffff
9947 06:48:42.112943 INFO: [APUAPC] D3_APC_1: 0xffffffff
9948 06:48:42.115864 INFO: [APUAPC] D3_APC_2: 0x3fffff
9949 06:48:42.115946 INFO: [APUAPC] D3_APC_3: 0x0
9950 06:48:42.119665 INFO: [APUAPC] D4_APC_0: 0xffffffff
9951 06:48:42.122986 INFO: [APUAPC] D4_APC_1: 0xffffffff
9952 06:48:42.126068 INFO: [APUAPC] D4_APC_2: 0x3fffff
9953 06:48:42.129130 INFO: [APUAPC] D4_APC_3: 0x0
9954 06:48:42.132630 INFO: [APUAPC] D5_APC_0: 0xffffffff
9955 06:48:42.136139 INFO: [APUAPC] D5_APC_1: 0xffffffff
9956 06:48:42.139341 INFO: [APUAPC] D5_APC_2: 0x3fffff
9957 06:48:42.142904 INFO: [APUAPC] D5_APC_3: 0x0
9958 06:48:42.146134 INFO: [APUAPC] D6_APC_0: 0xffffffff
9959 06:48:42.149301 INFO: [APUAPC] D6_APC_1: 0xffffffff
9960 06:48:42.153098 INFO: [APUAPC] D6_APC_2: 0x3fffff
9961 06:48:42.156064 INFO: [APUAPC] D6_APC_3: 0x0
9962 06:48:42.159302 INFO: [APUAPC] D7_APC_0: 0xffffffff
9963 06:48:42.162408 INFO: [APUAPC] D7_APC_1: 0xffffffff
9964 06:48:42.166180 INFO: [APUAPC] D7_APC_2: 0x3fffff
9965 06:48:42.169375 INFO: [APUAPC] D7_APC_3: 0x0
9966 06:48:42.172936 INFO: [APUAPC] D8_APC_0: 0xffffffff
9967 06:48:42.176228 INFO: [APUAPC] D8_APC_1: 0xffffffff
9968 06:48:42.179540 INFO: [APUAPC] D8_APC_2: 0x3fffff
9969 06:48:42.182346 INFO: [APUAPC] D8_APC_3: 0x0
9970 06:48:42.186174 INFO: [APUAPC] D9_APC_0: 0xffffffff
9971 06:48:42.189180 INFO: [APUAPC] D9_APC_1: 0xffffffff
9972 06:48:42.192497 INFO: [APUAPC] D9_APC_2: 0x3fffff
9973 06:48:42.195725 INFO: [APUAPC] D9_APC_3: 0x0
9974 06:48:42.199497 INFO: [APUAPC] D10_APC_0: 0xffffffff
9975 06:48:42.202383 INFO: [APUAPC] D10_APC_1: 0xffffffff
9976 06:48:42.206271 INFO: [APUAPC] D10_APC_2: 0x3fffff
9977 06:48:42.209208 INFO: [APUAPC] D10_APC_3: 0x0
9978 06:48:42.212680 INFO: [APUAPC] D11_APC_0: 0xffffffff
9979 06:48:42.215972 INFO: [APUAPC] D11_APC_1: 0xffffffff
9980 06:48:42.219735 INFO: [APUAPC] D11_APC_2: 0x3fffff
9981 06:48:42.222797 INFO: [APUAPC] D11_APC_3: 0x0
9982 06:48:42.226172 INFO: [APUAPC] D12_APC_0: 0xffffffff
9983 06:48:42.229487 INFO: [APUAPC] D12_APC_1: 0xffffffff
9984 06:48:42.232915 INFO: [APUAPC] D12_APC_2: 0x3fffff
9985 06:48:42.236401 INFO: [APUAPC] D12_APC_3: 0x0
9986 06:48:42.239483 INFO: [APUAPC] D13_APC_0: 0xffffffff
9987 06:48:42.242345 INFO: [APUAPC] D13_APC_1: 0xffffffff
9988 06:48:42.245855 INFO: [APUAPC] D13_APC_2: 0x3fffff
9989 06:48:42.249322 INFO: [APUAPC] D13_APC_3: 0x0
9990 06:48:42.252382 INFO: [APUAPC] D14_APC_0: 0xffffffff
9991 06:48:42.255837 INFO: [APUAPC] D14_APC_1: 0xffffffff
9992 06:48:42.259917 INFO: [APUAPC] D14_APC_2: 0x3fffff
9993 06:48:42.262349 INFO: [APUAPC] D14_APC_3: 0x0
9994 06:48:42.265705 INFO: [APUAPC] D15_APC_0: 0xffffffff
9995 06:48:42.269394 INFO: [APUAPC] D15_APC_1: 0xffffffff
9996 06:48:42.272629 INFO: [APUAPC] D15_APC_2: 0x3fffff
9997 06:48:42.276302 INFO: [APUAPC] D15_APC_3: 0x0
9998 06:48:42.279373 INFO: [APUAPC] APC_CON: 0x4
9999 06:48:42.282321 INFO: [NOCDAPC] D0_APC_0: 0x0
10000 06:48:42.282410 INFO: [NOCDAPC] D0_APC_1: 0x0
10001 06:48:42.286072 INFO: [NOCDAPC] D1_APC_0: 0x0
10002 06:48:42.289167 INFO: [NOCDAPC] D1_APC_1: 0xfff
10003 06:48:42.292644 INFO: [NOCDAPC] D2_APC_0: 0x0
10004 06:48:42.295904 INFO: [NOCDAPC] D2_APC_1: 0xfff
10005 06:48:42.299427 INFO: [NOCDAPC] D3_APC_0: 0x0
10006 06:48:42.302568 INFO: [NOCDAPC] D3_APC_1: 0xfff
10007 06:48:42.306201 INFO: [NOCDAPC] D4_APC_0: 0x0
10008 06:48:42.309389 INFO: [NOCDAPC] D4_APC_1: 0xfff
10009 06:48:42.312911 INFO: [NOCDAPC] D5_APC_0: 0x0
10010 06:48:42.315586 INFO: [NOCDAPC] D5_APC_1: 0xfff
10011 06:48:42.315668 INFO: [NOCDAPC] D6_APC_0: 0x0
10012 06:48:42.319102 INFO: [NOCDAPC] D6_APC_1: 0xfff
10013 06:48:42.322370 INFO: [NOCDAPC] D7_APC_0: 0x0
10014 06:48:42.326042 INFO: [NOCDAPC] D7_APC_1: 0xfff
10015 06:48:42.329383 INFO: [NOCDAPC] D8_APC_0: 0x0
10016 06:48:42.332467 INFO: [NOCDAPC] D8_APC_1: 0xfff
10017 06:48:42.336326 INFO: [NOCDAPC] D9_APC_0: 0x0
10018 06:48:42.339174 INFO: [NOCDAPC] D9_APC_1: 0xfff
10019 06:48:42.342497 INFO: [NOCDAPC] D10_APC_0: 0x0
10020 06:48:42.345785 INFO: [NOCDAPC] D10_APC_1: 0xfff
10021 06:48:42.348825 INFO: [NOCDAPC] D11_APC_0: 0x0
10022 06:48:42.352360 INFO: [NOCDAPC] D11_APC_1: 0xfff
10023 06:48:42.352443 INFO: [NOCDAPC] D12_APC_0: 0x0
10024 06:48:42.355921 INFO: [NOCDAPC] D12_APC_1: 0xfff
10025 06:48:42.358858 INFO: [NOCDAPC] D13_APC_0: 0x0
10026 06:48:42.362252 INFO: [NOCDAPC] D13_APC_1: 0xfff
10027 06:48:42.365925 INFO: [NOCDAPC] D14_APC_0: 0x0
10028 06:48:42.369007 INFO: [NOCDAPC] D14_APC_1: 0xfff
10029 06:48:42.372119 INFO: [NOCDAPC] D15_APC_0: 0x0
10030 06:48:42.375864 INFO: [NOCDAPC] D15_APC_1: 0xfff
10031 06:48:42.378882 INFO: [NOCDAPC] APC_CON: 0x4
10032 06:48:42.382640 INFO: [APUAPC] set_apusys_apc done
10033 06:48:42.385968 INFO: [DEVAPC] devapc_init done
10034 06:48:42.389479 INFO: GICv3 without legacy support detected.
10035 06:48:42.392558 INFO: ARM GICv3 driver initialized in EL3
10036 06:48:42.395952 INFO: Maximum SPI INTID supported: 639
10037 06:48:42.402651 INFO: BL31: Initializing runtime services
10038 06:48:42.405632 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10039 06:48:42.408820 INFO: SPM: enable CPC mode
10040 06:48:42.415521 INFO: mcdi ready for mcusys-off-idle and system suspend
10041 06:48:42.419156 INFO: BL31: Preparing for EL3 exit to normal world
10042 06:48:42.422641 INFO: Entry point address = 0x80000000
10043 06:48:42.425918 INFO: SPSR = 0x8
10044 06:48:42.430799
10045 06:48:42.430884
10046 06:48:42.430949
10047 06:48:42.434029 Starting depthcharge on Spherion...
10048 06:48:42.434112
10049 06:48:42.434176 Wipe memory regions:
10050 06:48:42.434237
10051 06:48:42.434934 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10052 06:48:42.435033 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10053 06:48:42.435116 Setting prompt string to ['asurada:']
10054 06:48:42.435192 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10055 06:48:42.437399 [0x00000040000000, 0x00000054600000)
10056 06:48:42.559624
10057 06:48:42.559745 [0x00000054660000, 0x00000080000000)
10058 06:48:42.820255
10059 06:48:42.820392 [0x000000821a7280, 0x000000ffe64000)
10060 06:48:43.564958
10061 06:48:43.565100 [0x00000100000000, 0x00000240000000)
10062 06:48:45.454430
10063 06:48:45.457501 Initializing XHCI USB controller at 0x11200000.
10064 06:48:46.496082
10065 06:48:46.499292 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10066 06:48:46.499380
10067 06:48:46.499445
10068 06:48:46.499505
10069 06:48:46.499784 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10071 06:48:46.600133 asurada: tftpboot 192.168.201.1 12694787/tftp-deploy-2gqx_yo1/kernel/image.itb 12694787/tftp-deploy-2gqx_yo1/kernel/cmdline
10072 06:48:46.600270 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 06:48:46.600358 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10074 06:48:46.604893 tftpboot 192.168.201.1 12694787/tftp-deploy-2gqx_yo1/kernel/image.ittp-deploy-2gqx_yo1/kernel/cmdline
10075 06:48:46.604977
10076 06:48:46.605041 Waiting for link
10077 06:48:46.765403
10078 06:48:46.765546 R8152: Initializing
10079 06:48:46.765614
10080 06:48:46.768313 Version 6 (ocp_data = 5c30)
10081 06:48:46.768396
10082 06:48:46.771962 R8152: Done initializing
10083 06:48:46.772044
10084 06:48:46.772109 Adding net device
10085 06:48:48.737503
10086 06:48:48.737645 done.
10087 06:48:48.737717
10088 06:48:48.737779 MAC: 00:24:32:30:78:52
10089 06:48:48.737838
10090 06:48:48.741117 Sending DHCP discover... done.
10091 06:48:48.741201
10092 06:48:48.744463 Waiting for reply... done.
10093 06:48:48.744546
10094 06:48:48.747586 Sending DHCP request... done.
10095 06:48:48.747668
10096 06:48:48.751452 Waiting for reply... done.
10097 06:48:48.751535
10098 06:48:48.751599 My ip is 192.168.201.14
10099 06:48:48.751661
10100 06:48:48.754902 The DHCP server ip is 192.168.201.1
10101 06:48:48.754985
10102 06:48:48.761888 TFTP server IP predefined by user: 192.168.201.1
10103 06:48:48.761972
10104 06:48:48.768558 Bootfile predefined by user: 12694787/tftp-deploy-2gqx_yo1/kernel/image.itb
10105 06:48:48.768640
10106 06:48:48.768704 Sending tftp read request... done.
10107 06:48:48.768765
10108 06:48:48.775670 Waiting for the transfer...
10109 06:48:48.775778
10110 06:48:49.321687 00000000 ################################################################
10111 06:48:49.321832
10112 06:48:49.869157 00080000 ################################################################
10113 06:48:49.869325
10114 06:48:50.414585 00100000 ################################################################
10115 06:48:50.414723
10116 06:48:50.954112 00180000 ################################################################
10117 06:48:50.954274
10118 06:48:51.498271 00200000 ################################################################
10119 06:48:51.498432
10120 06:48:52.049004 00280000 ################################################################
10121 06:48:52.049140
10122 06:48:52.588686 00300000 ################################################################
10123 06:48:52.588863
10124 06:48:53.129131 00380000 ################################################################
10125 06:48:53.129301
10126 06:48:53.669348 00400000 ################################################################
10127 06:48:53.669487
10128 06:48:54.231490 00480000 ################################################################
10129 06:48:54.231624
10130 06:48:54.791487 00500000 ################################################################
10131 06:48:54.791623
10132 06:48:55.337380 00580000 ################################################################
10133 06:48:55.337535
10134 06:48:55.881957 00600000 ################################################################
10135 06:48:55.882112
10136 06:48:56.423586 00680000 ################################################################
10137 06:48:56.423750
10138 06:48:56.961266 00700000 ################################################################
10139 06:48:56.961403
10140 06:48:57.489109 00780000 ################################################################
10141 06:48:57.489246
10142 06:48:58.040717 00800000 ################################################################
10143 06:48:58.040892
10144 06:48:58.597532 00880000 ################################################################
10145 06:48:58.597684
10146 06:48:59.153984 00900000 ################################################################
10147 06:48:59.154140
10148 06:48:59.718330 00980000 ################################################################
10149 06:48:59.718501
10150 06:49:00.366508 00a00000 ################################################################
10151 06:49:00.366655
10152 06:49:01.005445 00a80000 ################################################################
10153 06:49:01.005581
10154 06:49:01.589012 00b00000 ################################################################
10155 06:49:01.589150
10156 06:49:02.170554 00b80000 ################################################################
10157 06:49:02.170685
10158 06:49:02.760671 00c00000 ################################################################
10159 06:49:02.760827
10160 06:49:03.305215 00c80000 ################################################################
10161 06:49:03.305343
10162 06:49:03.922098 00d00000 ################################################################
10163 06:49:03.922739
10164 06:49:04.515304 00d80000 ################################################################
10165 06:49:04.515433
10166 06:49:05.112512 00e00000 ################################################################
10167 06:49:05.112651
10168 06:49:05.678798 00e80000 ################################################################
10169 06:49:05.679391
10170 06:49:06.308338 00f00000 ################################################################
10171 06:49:06.308468
10172 06:49:06.883171 00f80000 ################################################################
10173 06:49:06.883304
10174 06:49:07.444471 01000000 ################################################################
10175 06:49:07.444602
10176 06:49:07.992368 01080000 ################################################################
10177 06:49:07.992527
10178 06:49:08.545496 01100000 ################################################################
10179 06:49:08.545655
10180 06:49:09.102192 01180000 ################################################################
10181 06:49:09.102355
10182 06:49:09.648750 01200000 ################################################################
10183 06:49:09.648882
10184 06:49:10.282956 01280000 ################################################################
10185 06:49:10.283097
10186 06:49:10.934086 01300000 ################################################################
10187 06:49:10.934661
10188 06:49:11.565392 01380000 ################################################################
10189 06:49:11.565647
10190 06:49:12.190298 01400000 ################################################################
10191 06:49:12.190468
10192 06:49:12.818854 01480000 ################################################################
10193 06:49:12.818989
10194 06:49:13.398869 01500000 ################################################################
10195 06:49:13.399002
10196 06:49:14.054943 01580000 ################################################################
10197 06:49:14.055447
10198 06:49:14.758928 01600000 ################################################################
10199 06:49:14.759536
10200 06:49:15.485161 01680000 ################################################################
10201 06:49:15.485688
10202 06:49:16.176616 01700000 ################################################################
10203 06:49:16.177131
10204 06:49:16.894790 01780000 ################################################################
10205 06:49:16.894927
10206 06:49:17.617983 01800000 ################################################################
10207 06:49:17.618586
10208 06:49:18.299357 01880000 ################################################################
10209 06:49:18.299528
10210 06:49:18.946799 01900000 ################################################################
10211 06:49:18.947292
10212 06:49:19.649134 01980000 ################################################################
10213 06:49:19.649695
10214 06:49:20.377001 01a00000 ################################################################
10215 06:49:20.377561
10216 06:49:20.977649 01a80000 ################################################################
10217 06:49:20.977802
10218 06:49:21.687146 01b00000 ################################################################
10219 06:49:21.687657
10220 06:49:22.384390 01b80000 ################################################################
10221 06:49:22.384909
10222 06:49:23.085093 01c00000 ################################################################
10223 06:49:23.085618
10224 06:49:23.777474 01c80000 ################################################################
10225 06:49:23.778026
10226 06:49:24.475210 01d00000 ################################################################
10227 06:49:24.475735
10228 06:49:25.179691 01d80000 ################################################################
10229 06:49:25.180270
10230 06:49:25.843185 01e00000 ################################################################
10231 06:49:25.843675
10232 06:49:26.547034 01e80000 ################################################################
10233 06:49:26.547546
10234 06:49:27.121862 01f00000 ################################################################
10235 06:49:27.122012
10236 06:49:27.731956 01f80000 ################################################################
10237 06:49:27.732089
10238 06:49:28.307332 02000000 ################################################################
10239 06:49:28.307468
10240 06:49:28.898773 02080000 ################################################################
10241 06:49:28.899326
10242 06:49:29.555793 02100000 ################################################################
10243 06:49:29.556284
10244 06:49:30.235672 02180000 ################################################################
10245 06:49:30.235830
10246 06:49:30.822874 02200000 ################################################################
10247 06:49:30.823018
10248 06:49:31.372910 02280000 ################################################################
10249 06:49:31.373093
10250 06:49:31.946301 02300000 ################################################################
10251 06:49:31.946538
10252 06:49:32.632058 02380000 ################################################################
10253 06:49:32.632549
10254 06:49:33.298523 02400000 ################################################################
10255 06:49:33.299038
10256 06:49:34.002847 02480000 ################################################################
10257 06:49:34.003339
10258 06:49:34.677793 02500000 ################################################################
10259 06:49:34.678330
10260 06:49:35.310659 02580000 ################################################################
10261 06:49:35.310813
10262 06:49:36.008176 02600000 ################################################################
10263 06:49:36.008323
10264 06:49:36.662227 02680000 ################################################################
10265 06:49:36.662410
10266 06:49:37.256061 02700000 ################################################################
10267 06:49:37.256236
10268 06:49:37.818409 02780000 ################################################################
10269 06:49:37.818568
10270 06:49:38.445074 02800000 ################################################################
10271 06:49:38.445216
10272 06:49:39.123334 02880000 ################################################################
10273 06:49:39.123478
10274 06:49:39.687148 02900000 ################################################################
10275 06:49:39.687329
10276 06:49:40.326624 02980000 ################################################################
10277 06:49:40.327101
10278 06:49:40.938025 02a00000 ################################################################
10279 06:49:40.938167
10280 06:49:41.516685 02a80000 ################################################################
10281 06:49:41.516855
10282 06:49:42.104772 02b00000 ################################################################
10283 06:49:42.104922
10284 06:49:42.709304 02b80000 ################################################################
10285 06:49:42.709926
10286 06:49:43.387089 02c00000 ################################################################
10287 06:49:43.387607
10288 06:49:43.986482 02c80000 ################################################################
10289 06:49:43.986640
10290 06:49:44.692798 02d00000 ################################################################
10291 06:49:44.692953
10292 06:49:45.387872 02d80000 ################################################################
10293 06:49:45.388008
10294 06:49:46.036726 02e00000 ################################################################
10295 06:49:46.036858
10296 06:49:46.630588 02e80000 ################################################################
10297 06:49:46.630723
10298 06:49:47.189512 02f00000 ################################################################
10299 06:49:47.189643
10300 06:49:47.778620 02f80000 ################################################################
10301 06:49:47.778758
10302 06:49:48.412283 03000000 ################################################################
10303 06:49:48.412432
10304 06:49:49.032879 03080000 ################################################################
10305 06:49:49.033027
10306 06:49:49.624815 03100000 ################################################################
10307 06:49:49.624983
10308 06:49:50.276605 03180000 ################################################################
10309 06:49:50.277135
10310 06:49:50.962582 03200000 ################################################################
10311 06:49:50.963348
10312 06:49:51.661205 03280000 ################################################################
10313 06:49:51.661351
10314 06:49:52.366536 03300000 ################################################################
10315 06:49:52.366710
10316 06:49:53.032317 03380000 ################################################################
10317 06:49:53.032991
10318 06:49:53.719077 03400000 ################################################################
10319 06:49:53.719252
10320 06:49:54.351197 03480000 ################################################################
10321 06:49:54.351719
10322 06:49:55.058371 03500000 ################################################################
10323 06:49:55.058929
10324 06:49:55.767641 03580000 ################################################################
10325 06:49:55.768300
10326 06:49:56.469035 03600000 ################################################################
10327 06:49:56.469547
10328 06:49:57.116449 03680000 ################################################################
10329 06:49:57.116596
10330 06:49:57.708723 03700000 ################################################################
10331 06:49:57.709237
10332 06:49:58.399289 03780000 ################################################################
10333 06:49:58.399438
10334 06:49:59.096236 03800000 ################################################################
10335 06:49:59.096769
10336 06:49:59.745115 03880000 ################################################################
10337 06:49:59.745608
10338 06:50:00.423345 03900000 ################################################################
10339 06:50:00.423869
10340 06:50:01.081660 03980000 ################################################################
10341 06:50:01.081797
10342 06:50:01.660769 03a00000 ################################################################
10343 06:50:01.660918
10344 06:50:02.257426 03a80000 ################################################################
10345 06:50:02.257574
10346 06:50:02.835754 03b00000 ################################################################
10347 06:50:02.835908
10348 06:50:03.417784 03b80000 ################################################################
10349 06:50:03.417928
10350 06:50:04.011491 03c00000 ################################################################
10351 06:50:04.011643
10352 06:50:04.601649 03c80000 ################################################################
10353 06:50:04.601796
10354 06:50:05.180609 03d00000 ################################################################
10355 06:50:05.180759
10356 06:50:05.766087 03d80000 ################################################################
10357 06:50:05.766237
10358 06:50:06.341420 03e00000 ################################################################
10359 06:50:06.341563
10360 06:50:06.924159 03e80000 ################################################################
10361 06:50:06.924313
10362 06:50:07.516323 03f00000 ################################################################
10363 06:50:07.516546
10364 06:50:08.091635 03f80000 ################################################################
10365 06:50:08.091787
10366 06:50:08.677427 04000000 ################################################################
10367 06:50:08.677566
10368 06:50:09.261602 04080000 ################################################################
10369 06:50:09.261735
10370 06:50:09.709916 04100000 ################################################# done.
10371 06:50:09.710067
10372 06:50:09.713901 The bootfile was 68552974 bytes long.
10373 06:50:09.713986
10374 06:50:09.716550 Sending tftp read request... done.
10375 06:50:09.716632
10376 06:50:09.720107 Waiting for the transfer...
10377 06:50:09.720189
10378 06:50:09.724555 00000000 # done.
10379 06:50:09.724638
10380 06:50:09.730032 Command line loaded dynamically from TFTP file: 12694787/tftp-deploy-2gqx_yo1/kernel/cmdline
10381 06:50:09.730114
10382 06:50:09.743610 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10383 06:50:09.743695
10384 06:50:09.743759 Loading FIT.
10385 06:50:09.743819
10386 06:50:09.746726 Image ramdisk-1 has 56453078 bytes.
10387 06:50:09.746808
10388 06:50:09.750078 Image fdt-1 has 47278 bytes.
10389 06:50:09.750162
10390 06:50:09.753970 Image kernel-1 has 12050581 bytes.
10391 06:50:09.754051
10392 06:50:09.763751 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10393 06:50:09.763833
10394 06:50:09.780347 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10395 06:50:09.780433
10396 06:50:09.787039 Choosing best match conf-1 for compat google,spherion-rev2.
10397 06:50:09.787121
10398 06:50:09.794442 Connected to device vid:did:rid of 1ae0:0028:00
10399 06:50:09.802687
10400 06:50:09.805645 tpm_get_response: command 0x17b, return code 0x0
10401 06:50:09.805726
10402 06:50:09.809328 ec_init: CrosEC protocol v3 supported (256, 248)
10403 06:50:09.813687
10404 06:50:09.816760 tpm_cleanup: add release locality here.
10405 06:50:09.816842
10406 06:50:09.816905 Shutting down all USB controllers.
10407 06:50:09.816964
10408 06:50:09.819841 Removing current net device
10409 06:50:09.819922
10410 06:50:09.826561 Exiting depthcharge with code 4 at timestamp: 116809160
10411 06:50:09.826643
10412 06:50:09.830249 LZMA decompressing kernel-1 to 0x821a6718
10413 06:50:09.830330
10414 06:50:09.833643 LZMA decompressing kernel-1 to 0x40000000
10415 06:50:11.332185
10416 06:50:11.332336 jumping to kernel
10417 06:50:11.332858 end: 2.2.4 bootloader-commands (duration 00:01:29) [common]
10418 06:50:11.332955 start: 2.2.5 auto-login-action (timeout 00:02:56) [common]
10419 06:50:11.333031 Setting prompt string to ['Linux version [0-9]']
10420 06:50:11.333097 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10421 06:50:11.333163 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10422 06:50:11.413705
10423 06:50:11.416531 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10424 06:50:11.419981 start: 2.2.5.1 login-action (timeout 00:02:56) [common]
10425 06:50:11.420077 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10426 06:50:11.420146 Setting prompt string to []
10427 06:50:11.420224 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10428 06:50:11.420296 Using line separator: #'\n'#
10429 06:50:11.420354 No login prompt set.
10430 06:50:11.420415 Parsing kernel messages
10431 06:50:11.420469 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10432 06:50:11.420565 [login-action] Waiting for messages, (timeout 00:02:56)
10433 06:50:11.440503 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10434 06:50:11.443434 [ 0.000000] random: crng init done
10435 06:50:11.447184 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10436 06:50:11.450331 [ 0.000000] efi: UEFI not found.
10437 06:50:11.460241 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10438 06:50:11.466670 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10439 06:50:11.476983 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10440 06:50:11.486900 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10441 06:50:11.493386 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10442 06:50:11.496626 [ 0.000000] printk: bootconsole [mtk8250] enabled
10443 06:50:11.505078 [ 0.000000] NUMA: No NUMA configuration found
10444 06:50:11.511787 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10445 06:50:11.518927 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10446 06:50:11.519029 [ 0.000000] Zone ranges:
10447 06:50:11.524735 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10448 06:50:11.528358 [ 0.000000] DMA32 empty
10449 06:50:11.535387 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10450 06:50:11.538044 [ 0.000000] Movable zone start for each node
10451 06:50:11.541486 [ 0.000000] Early memory node ranges
10452 06:50:11.548357 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10453 06:50:11.555783 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10454 06:50:11.561703 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10455 06:50:11.568694 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10456 06:50:11.575030 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10457 06:50:11.581706 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10458 06:50:11.637778 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10459 06:50:11.644404 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10460 06:50:11.650967 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10461 06:50:11.654221 [ 0.000000] psci: probing for conduit method from DT.
10462 06:50:11.660870 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10463 06:50:11.664303 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10464 06:50:11.670972 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10465 06:50:11.674196 [ 0.000000] psci: SMC Calling Convention v1.2
10466 06:50:11.681227 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10467 06:50:11.684272 [ 0.000000] Detected VIPT I-cache on CPU0
10468 06:50:11.690966 [ 0.000000] CPU features: detected: GIC system register CPU interface
10469 06:50:11.697494 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10470 06:50:11.704155 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10471 06:50:11.711046 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10472 06:50:11.717406 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10473 06:50:11.727734 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10474 06:50:11.730644 [ 0.000000] alternatives: applying boot alternatives
10475 06:50:11.737545 [ 0.000000] Fallback order for Node 0: 0
10476 06:50:11.744409 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10477 06:50:11.747200 [ 0.000000] Policy zone: Normal
10478 06:50:11.761254 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10479 06:50:11.770392 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10480 06:50:11.781417 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10481 06:50:11.791405 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10482 06:50:11.797893 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10483 06:50:11.801078 <6>[ 0.000000] software IO TLB: area num 8.
10484 06:50:11.857486 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10485 06:50:12.007301 <6>[ 0.000000] Memory: 7912124K/8385536K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 440644K reserved, 32768K cma-reserved)
10486 06:50:12.013248 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10487 06:50:12.020121 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10488 06:50:12.023705 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10489 06:50:12.030064 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10490 06:50:12.036637 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10491 06:50:12.040034 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10492 06:50:12.049833 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10493 06:50:12.056984 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10494 06:50:12.059793 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10495 06:50:12.068265 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10496 06:50:12.071318 <6>[ 0.000000] GICv3: 608 SPIs implemented
10497 06:50:12.077406 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10498 06:50:12.081235 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10499 06:50:12.084166 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10500 06:50:12.094786 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10501 06:50:12.104678 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10502 06:50:12.117844 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10503 06:50:12.124718 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10504 06:50:12.133721 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10505 06:50:12.146223 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10506 06:50:12.153019 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10507 06:50:12.159474 <6>[ 0.009180] Console: colour dummy device 80x25
10508 06:50:12.169833 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10509 06:50:12.176357 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10510 06:50:12.179253 <6>[ 0.029316] LSM: Security Framework initializing
10511 06:50:12.186340 <6>[ 0.034255] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10512 06:50:12.196135 <6>[ 0.042070] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10513 06:50:12.202913 <6>[ 0.051535] cblist_init_generic: Setting adjustable number of callback queues.
10514 06:50:12.209957 <6>[ 0.058979] cblist_init_generic: Setting shift to 3 and lim to 1.
10515 06:50:12.219270 <6>[ 0.065319] cblist_init_generic: Setting adjustable number of callback queues.
10516 06:50:12.226232 <6>[ 0.072792] cblist_init_generic: Setting shift to 3 and lim to 1.
10517 06:50:12.229259 <6>[ 0.079194] rcu: Hierarchical SRCU implementation.
10518 06:50:12.236148 <6>[ 0.084240] rcu: Max phase no-delay instances is 1000.
10519 06:50:12.242869 <6>[ 0.091304] EFI services will not be available.
10520 06:50:12.246023 <6>[ 0.096286] smp: Bringing up secondary CPUs ...
10521 06:50:12.254778 <6>[ 0.101336] Detected VIPT I-cache on CPU1
10522 06:50:12.260999 <6>[ 0.101406] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10523 06:50:12.267881 <6>[ 0.101438] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10524 06:50:12.270669 <6>[ 0.101775] Detected VIPT I-cache on CPU2
10525 06:50:12.277406 <6>[ 0.101825] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10526 06:50:12.284833 <6>[ 0.101841] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10527 06:50:12.291168 <6>[ 0.102100] Detected VIPT I-cache on CPU3
10528 06:50:12.297946 <6>[ 0.102146] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10529 06:50:12.304023 <6>[ 0.102160] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10530 06:50:12.307552 <6>[ 0.102464] CPU features: detected: Spectre-v4
10531 06:50:12.314204 <6>[ 0.102471] CPU features: detected: Spectre-BHB
10532 06:50:12.317951 <6>[ 0.102475] Detected PIPT I-cache on CPU4
10533 06:50:12.324598 <6>[ 0.102533] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10534 06:50:12.332621 <6>[ 0.102549] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10535 06:50:12.334714 <6>[ 0.102844] Detected PIPT I-cache on CPU5
10536 06:50:12.344148 <6>[ 0.102905] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10537 06:50:12.351083 <6>[ 0.102922] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10538 06:50:12.354378 <6>[ 0.103201] Detected PIPT I-cache on CPU6
10539 06:50:12.361075 <6>[ 0.103265] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10540 06:50:12.367728 <6>[ 0.103281] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10541 06:50:12.371725 <6>[ 0.103580] Detected PIPT I-cache on CPU7
10542 06:50:12.377751 <6>[ 0.103645] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10543 06:50:12.387592 <6>[ 0.103662] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10544 06:50:12.390769 <6>[ 0.103709] smp: Brought up 1 node, 8 CPUs
10545 06:50:12.394297 <6>[ 0.245109] SMP: Total of 8 processors activated.
10546 06:50:12.401156 <6>[ 0.250060] CPU features: detected: 32-bit EL0 Support
10547 06:50:12.411706 <6>[ 0.255422] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10548 06:50:12.417463 <6>[ 0.264223] CPU features: detected: Common not Private translations
10549 06:50:12.420806 <6>[ 0.270739] CPU features: detected: CRC32 instructions
10550 06:50:12.427326 <6>[ 0.276091] CPU features: detected: RCpc load-acquire (LDAPR)
10551 06:50:12.434162 <6>[ 0.282051] CPU features: detected: LSE atomic instructions
10552 06:50:12.437270 <6>[ 0.287832] CPU features: detected: Privileged Access Never
10553 06:50:12.444294 <6>[ 0.293648] CPU features: detected: RAS Extension Support
10554 06:50:12.450848 <6>[ 0.299292] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10555 06:50:12.457653 <6>[ 0.306510] CPU: All CPU(s) started at EL2
10556 06:50:12.460938 <6>[ 0.310854] alternatives: applying system-wide alternatives
10557 06:50:12.471967 <6>[ 0.321573] devtmpfs: initialized
10558 06:50:12.484278 <6>[ 0.330312] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10559 06:50:12.494662 <6>[ 0.340275] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10560 06:50:12.500381 <6>[ 0.348463] pinctrl core: initialized pinctrl subsystem
10561 06:50:12.503810 <6>[ 0.355124] DMI not present or invalid.
10562 06:50:12.510945 <6>[ 0.359534] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10563 06:50:12.520381 <6>[ 0.366398] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10564 06:50:12.527142 <6>[ 0.373981] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10565 06:50:12.536976 <6>[ 0.382206] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10566 06:50:12.540415 <6>[ 0.390450] audit: initializing netlink subsys (disabled)
10567 06:50:12.550209 <5>[ 0.396142] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10568 06:50:12.556878 <6>[ 0.396837] thermal_sys: Registered thermal governor 'step_wise'
10569 06:50:12.564141 <6>[ 0.404110] thermal_sys: Registered thermal governor 'power_allocator'
10570 06:50:12.567104 <6>[ 0.410365] cpuidle: using governor menu
10571 06:50:12.573789 <6>[ 0.421323] NET: Registered PF_QIPCRTR protocol family
10572 06:50:12.580436 <6>[ 0.426798] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10573 06:50:12.583749 <6>[ 0.433899] ASID allocator initialised with 32768 entries
10574 06:50:12.590537 <6>[ 0.440467] Serial: AMBA PL011 UART driver
10575 06:50:12.599650 <4>[ 0.449251] Trying to register duplicate clock ID: 134
10576 06:50:12.653350 <6>[ 0.506368] KASLR enabled
10577 06:50:12.667855 <6>[ 0.513996] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10578 06:50:12.674350 <6>[ 0.521007] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10579 06:50:12.681667 <6>[ 0.527498] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10580 06:50:12.687983 <6>[ 0.534501] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10581 06:50:12.694450 <6>[ 0.540987] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10582 06:50:12.701088 <6>[ 0.547993] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10583 06:50:12.707667 <6>[ 0.554477] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10584 06:50:12.714760 <6>[ 0.561482] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10585 06:50:12.717813 <6>[ 0.568943] ACPI: Interpreter disabled.
10586 06:50:12.725610 <6>[ 0.575382] iommu: Default domain type: Translated
10587 06:50:12.732738 <6>[ 0.580493] iommu: DMA domain TLB invalidation policy: strict mode
10588 06:50:12.735861 <5>[ 0.587156] SCSI subsystem initialized
10589 06:50:12.742213 <6>[ 0.591401] usbcore: registered new interface driver usbfs
10590 06:50:12.748970 <6>[ 0.597129] usbcore: registered new interface driver hub
10591 06:50:12.752129 <6>[ 0.602683] usbcore: registered new device driver usb
10592 06:50:12.758847 <6>[ 0.608799] pps_core: LinuxPPS API ver. 1 registered
10593 06:50:12.769896 <6>[ 0.613993] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10594 06:50:12.772935 <6>[ 0.623336] PTP clock support registered
10595 06:50:12.775327 <6>[ 0.627575] EDAC MC: Ver: 3.0.0
10596 06:50:12.783275 <6>[ 0.632730] FPGA manager framework
10597 06:50:12.786226 <6>[ 0.636407] Advanced Linux Sound Architecture Driver Initialized.
10598 06:50:12.790886 <6>[ 0.643170] vgaarb: loaded
10599 06:50:12.796931 <6>[ 0.646318] clocksource: Switched to clocksource arch_sys_counter
10600 06:50:12.803454 <5>[ 0.652757] VFS: Disk quotas dquot_6.6.0
10601 06:50:12.810023 <6>[ 0.656946] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10602 06:50:12.813432 <6>[ 0.664134] pnp: PnP ACPI: disabled
10603 06:50:12.821313 <6>[ 0.670802] NET: Registered PF_INET protocol family
10604 06:50:12.827822 <6>[ 0.676389] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10605 06:50:12.842209 <6>[ 0.688710] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10606 06:50:12.852539 <6>[ 0.697529] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10607 06:50:12.858820 <6>[ 0.705502] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10608 06:50:12.865448 <6>[ 0.714206] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10609 06:50:12.877664 <6>[ 0.723964] TCP: Hash tables configured (established 65536 bind 65536)
10610 06:50:12.884262 <6>[ 0.730835] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10611 06:50:12.891248 <6>[ 0.738035] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10612 06:50:12.897785 <6>[ 0.745739] NET: Registered PF_UNIX/PF_LOCAL protocol family
10613 06:50:12.904284 <6>[ 0.751896] RPC: Registered named UNIX socket transport module.
10614 06:50:12.907512 <6>[ 0.758051] RPC: Registered udp transport module.
10615 06:50:12.914935 <6>[ 0.762982] RPC: Registered tcp transport module.
10616 06:50:12.920944 <6>[ 0.767912] RPC: Registered tcp NFSv4.1 backchannel transport module.
10617 06:50:12.924545 <6>[ 0.774579] PCI: CLS 0 bytes, default 64
10618 06:50:12.927791 <6>[ 0.778933] Unpacking initramfs...
10619 06:50:12.952419 <6>[ 0.798442] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10620 06:50:12.961934 <6>[ 0.807082] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10621 06:50:12.965293 <6>[ 0.815873] kvm [1]: IPA Size Limit: 40 bits
10622 06:50:12.972336 <6>[ 0.820396] kvm [1]: GICv3: no GICV resource entry
10623 06:50:12.975447 <6>[ 0.825416] kvm [1]: disabling GICv2 emulation
10624 06:50:12.982200 <6>[ 0.830098] kvm [1]: GIC system register CPU interface enabled
10625 06:50:12.985767 <6>[ 0.836258] kvm [1]: vgic interrupt IRQ18
10626 06:50:12.992222 <6>[ 0.840608] kvm [1]: VHE mode initialized successfully
10627 06:50:12.998665 <5>[ 0.847083] Initialise system trusted keyrings
10628 06:50:13.005489 <6>[ 0.851921] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10629 06:50:13.012755 <6>[ 0.861918] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10630 06:50:13.019148 <5>[ 0.868318] NFS: Registering the id_resolver key type
10631 06:50:13.022045 <5>[ 0.873613] Key type id_resolver registered
10632 06:50:13.028532 <5>[ 0.878029] Key type id_legacy registered
10633 06:50:13.035602 <6>[ 0.882311] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10634 06:50:13.042381 <6>[ 0.889231] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10635 06:50:13.048612 <6>[ 0.896939] 9p: Installing v9fs 9p2000 file system support
10636 06:50:13.085027 <5>[ 0.935030] Key type asymmetric registered
10637 06:50:13.088436 <5>[ 0.939362] Asymmetric key parser 'x509' registered
10638 06:50:13.098935 <6>[ 0.944505] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10639 06:50:13.102093 <6>[ 0.952119] io scheduler mq-deadline registered
10640 06:50:13.105306 <6>[ 0.956899] io scheduler kyber registered
10641 06:50:13.124339 <6>[ 0.974011] EINJ: ACPI disabled.
10642 06:50:13.156377 <4>[ 0.999457] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 06:50:13.166629 <4>[ 1.010072] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 06:50:13.181143 <6>[ 1.030868] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10645 06:50:13.189082 <6>[ 1.038850] printk: console [ttyS0] disabled
10646 06:50:13.216790 <6>[ 1.063481] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10647 06:50:13.223628 <6>[ 1.072958] printk: console [ttyS0] enabled
10648 06:50:13.226897 <6>[ 1.072958] printk: console [ttyS0] enabled
10649 06:50:13.233701 <6>[ 1.081856] printk: bootconsole [mtk8250] disabled
10650 06:50:13.237431 <6>[ 1.081856] printk: bootconsole [mtk8250] disabled
10651 06:50:13.244057 <6>[ 1.093119] SuperH (H)SCI(F) driver initialized
10652 06:50:13.247185 <6>[ 1.098447] msm_serial: driver initialized
10653 06:50:13.261297 <6>[ 1.107444] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10654 06:50:13.270851 <6>[ 1.115993] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10655 06:50:13.278001 <6>[ 1.124534] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10656 06:50:13.287398 <6>[ 1.133163] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10657 06:50:13.294405 <6>[ 1.141869] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10658 06:50:13.305081 <6>[ 1.150591] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10659 06:50:13.314359 <6>[ 1.159133] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10660 06:50:13.321405 <6>[ 1.167926] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10661 06:50:13.331101 <6>[ 1.176469] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10662 06:50:13.342509 <6>[ 1.192210] loop: module loaded
10663 06:50:13.349207 <6>[ 1.198181] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10664 06:50:13.372340 <4>[ 1.221468] mtk-pmic-keys: Failed to locate of_node [id: -1]
10665 06:50:13.378979 <6>[ 1.228393] megasas: 07.719.03.00-rc1
10666 06:50:13.388016 <6>[ 1.237903] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10667 06:50:13.396226 <6>[ 1.245698] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10668 06:50:13.412973 <6>[ 1.262395] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10669 06:50:13.469720 <6>[ 1.312524] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10670 06:50:15.345893 <6>[ 3.195887] Freeing initrd memory: 55128K
10671 06:50:15.356509 <6>[ 3.206431] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10672 06:50:15.367315 <6>[ 3.217507] tun: Universal TUN/TAP device driver, 1.6
10673 06:50:15.371274 <6>[ 3.223582] thunder_xcv, ver 1.0
10674 06:50:15.374356 <6>[ 3.227087] thunder_bgx, ver 1.0
10675 06:50:15.377488 <6>[ 3.230582] nicpf, ver 1.0
10676 06:50:15.388348 <6>[ 3.234627] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10677 06:50:15.391196 <6>[ 3.242103] hns3: Copyright (c) 2017 Huawei Corporation.
10678 06:50:15.398158 <6>[ 3.247694] hclge is initializing
10679 06:50:15.401288 <6>[ 3.251276] e1000: Intel(R) PRO/1000 Network Driver
10680 06:50:15.408049 <6>[ 3.256404] e1000: Copyright (c) 1999-2006 Intel Corporation.
10681 06:50:15.411369 <6>[ 3.262416] e1000e: Intel(R) PRO/1000 Network Driver
10682 06:50:15.417875 <6>[ 3.267632] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10683 06:50:15.424381 <6>[ 3.273816] igb: Intel(R) Gigabit Ethernet Network Driver
10684 06:50:15.431463 <6>[ 3.279466] igb: Copyright (c) 2007-2014 Intel Corporation.
10685 06:50:15.438014 <6>[ 3.285302] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10686 06:50:15.444583 <6>[ 3.291819] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10687 06:50:15.447680 <6>[ 3.298284] sky2: driver version 1.30
10688 06:50:15.454610 <6>[ 3.303291] VFIO - User Level meta-driver version: 0.3
10689 06:50:15.461714 <6>[ 3.311545] usbcore: registered new interface driver usb-storage
10690 06:50:15.468197 <6>[ 3.317989] usbcore: registered new device driver onboard-usb-hub
10691 06:50:15.477458 <6>[ 3.327175] mt6397-rtc mt6359-rtc: registered as rtc0
10692 06:50:15.487204 <6>[ 3.332664] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:50:21 UTC (1706943021)
10693 06:50:15.490470 <6>[ 3.342251] i2c_dev: i2c /dev entries driver
10694 06:50:15.507021 <6>[ 3.353972] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10695 06:50:15.527821 <6>[ 3.377966] cpu cpu0: EM: created perf domain
10696 06:50:15.530980 <6>[ 3.382928] cpu cpu4: EM: created perf domain
10697 06:50:15.538465 <6>[ 3.388562] sdhci: Secure Digital Host Controller Interface driver
10698 06:50:15.545238 <6>[ 3.394995] sdhci: Copyright(c) Pierre Ossman
10699 06:50:15.552180 <6>[ 3.399952] Synopsys Designware Multimedia Card Interface Driver
10700 06:50:15.558314 <6>[ 3.406615] sdhci-pltfm: SDHCI platform and OF driver helper
10701 06:50:15.562154 <6>[ 3.406664] mmc0: CQHCI version 5.10
10702 06:50:15.569213 <6>[ 3.416906] ledtrig-cpu: registered to indicate activity on CPUs
10703 06:50:15.575488 <6>[ 3.424000] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10704 06:50:15.581702 <6>[ 3.431071] usbcore: registered new interface driver usbhid
10705 06:50:15.585036 <6>[ 3.436893] usbhid: USB HID core driver
10706 06:50:15.591348 <6>[ 3.441107] spi_master spi0: will run message pump with realtime priority
10707 06:50:15.635572 <6>[ 3.478921] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10708 06:50:15.653992 <6>[ 3.493768] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10709 06:50:15.661106 <6>[ 3.509344] cros-ec-spi spi0.0: Chrome EC device registered
10710 06:50:15.664123 <6>[ 3.509399] mmc0: Command Queue Engine enabled
10711 06:50:15.670370 <6>[ 3.519930] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10712 06:50:15.677145 <6>[ 3.527383] mmcblk0: mmc0:0001 DA4128 116 GiB
10713 06:50:15.687150 <6>[ 3.536744] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10714 06:50:15.693252 <6>[ 3.543630] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10715 06:50:15.700391 <6>[ 3.549800] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10716 06:50:15.706995 <6>[ 3.556069] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10717 06:50:15.717025 <6>[ 3.561290] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10718 06:50:15.723637 <6>[ 3.573186] NET: Registered PF_PACKET protocol family
10719 06:50:15.727168 <6>[ 3.578590] 9pnet: Installing 9P2000 support
10720 06:50:15.733753 <5>[ 3.583157] Key type dns_resolver registered
10721 06:50:15.737363 <6>[ 3.588154] registered taskstats version 1
10722 06:50:15.743431 <5>[ 3.592540] Loading compiled-in X.509 certificates
10723 06:50:15.772898 <4>[ 3.616017] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10724 06:50:15.783130 <4>[ 3.626964] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10725 06:50:15.789910 <3>[ 3.637516] debugfs: File 'uA_load' in directory '/' already present!
10726 06:50:15.796108 <3>[ 3.644235] debugfs: File 'min_uV' in directory '/' already present!
10727 06:50:15.803241 <3>[ 3.650868] debugfs: File 'max_uV' in directory '/' already present!
10728 06:50:15.809143 <3>[ 3.657478] debugfs: File 'constraint_flags' in directory '/' already present!
10729 06:50:15.820169 <3>[ 3.666994] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10730 06:50:15.830105 <6>[ 3.680091] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10731 06:50:15.837076 <6>[ 3.687028] xhci-mtk 11200000.usb: xHCI Host Controller
10732 06:50:15.843352 <6>[ 3.692520] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10733 06:50:15.853505 <6>[ 3.700391] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10734 06:50:15.860172 <6>[ 3.709814] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10735 06:50:15.867093 <6>[ 3.715884] xhci-mtk 11200000.usb: xHCI Host Controller
10736 06:50:15.873620 <6>[ 3.721367] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10737 06:50:15.880427 <6>[ 3.729021] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10738 06:50:15.887009 <6>[ 3.736613] hub 1-0:1.0: USB hub found
10739 06:50:15.890590 <6>[ 3.740625] hub 1-0:1.0: 1 port detected
10740 06:50:15.896941 <6>[ 3.744877] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10741 06:50:15.903354 <6>[ 3.753517] hub 2-0:1.0: USB hub found
10742 06:50:15.906659 <6>[ 3.757527] hub 2-0:1.0: 1 port detected
10743 06:50:15.915378 <6>[ 3.765474] mtk-msdc 11f70000.mmc: Got CD GPIO
10744 06:50:15.926100 <6>[ 3.772483] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10745 06:50:15.932362 <6>[ 3.780514] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10746 06:50:15.943085 <4>[ 3.788408] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10747 06:50:15.952464 <6>[ 3.797940] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10748 06:50:15.959372 <6>[ 3.806016] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10749 06:50:15.965986 <6>[ 3.814104] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10750 06:50:15.975915 <6>[ 3.822051] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10751 06:50:15.982093 <6>[ 3.829868] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10752 06:50:15.992678 <6>[ 3.837685] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10753 06:50:16.002011 <6>[ 3.848174] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10754 06:50:16.009139 <6>[ 3.856537] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10755 06:50:16.019078 <6>[ 3.864877] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10756 06:50:16.026858 <6>[ 3.873216] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10757 06:50:16.035881 <6>[ 3.881555] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10758 06:50:16.041921 <6>[ 3.889896] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10759 06:50:16.052092 <6>[ 3.898236] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10760 06:50:16.059066 <6>[ 3.906574] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10761 06:50:16.068663 <6>[ 3.914912] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10762 06:50:16.075498 <6>[ 3.923252] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10763 06:50:16.086033 <6>[ 3.931590] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10764 06:50:16.092443 <6>[ 3.939928] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10765 06:50:16.101789 <6>[ 3.948267] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10766 06:50:16.108427 <6>[ 3.956606] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10767 06:50:16.118303 <6>[ 3.964945] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10768 06:50:16.124952 <6>[ 3.973839] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10769 06:50:16.131371 <6>[ 3.981201] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10770 06:50:16.138211 <6>[ 3.988186] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10771 06:50:16.145732 <6>[ 3.995103] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10772 06:50:16.155673 <6>[ 4.002155] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10773 06:50:16.162113 <6>[ 4.009010] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10774 06:50:16.171861 <6>[ 4.018140] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10775 06:50:16.182411 <6>[ 4.027259] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10776 06:50:16.192464 <6>[ 4.036553] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10777 06:50:16.201482 <6>[ 4.046019] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10778 06:50:16.208778 <6>[ 4.055485] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10779 06:50:16.217997 <6>[ 4.064605] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10780 06:50:16.228340 <6>[ 4.074071] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10781 06:50:16.238328 <6>[ 4.083191] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10782 06:50:16.248625 <6>[ 4.092485] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10783 06:50:16.258369 <6>[ 4.102645] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10784 06:50:16.268456 <6>[ 4.114549] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10785 06:50:16.296005 <6>[ 4.142809] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10786 06:50:16.323835 <6>[ 4.173901] hub 2-1:1.0: USB hub found
10787 06:50:16.327211 <6>[ 4.178461] hub 2-1:1.0: 3 ports detected
10788 06:50:16.335135 <6>[ 4.185346] hub 2-1:1.0: USB hub found
10789 06:50:16.338455 <6>[ 4.189718] hub 2-1:1.0: 3 ports detected
10790 06:50:16.448062 <6>[ 4.294605] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10791 06:50:16.602378 <6>[ 4.452667] hub 1-1:1.0: USB hub found
10792 06:50:16.605919 <6>[ 4.457128] hub 1-1:1.0: 4 ports detected
10793 06:50:16.616389 <6>[ 4.466551] hub 1-1:1.0: USB hub found
10794 06:50:16.619656 <6>[ 4.471073] hub 1-1:1.0: 4 ports detected
10795 06:50:16.688456 <6>[ 4.534791] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10796 06:50:16.939595 <6>[ 4.786647] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10797 06:50:17.072524 <6>[ 4.922491] hub 1-1.4:1.0: USB hub found
10798 06:50:17.075558 <6>[ 4.927154] hub 1-1.4:1.0: 2 ports detected
10799 06:50:17.085488 <6>[ 4.935734] hub 1-1.4:1.0: USB hub found
10800 06:50:17.088945 <6>[ 4.940335] hub 1-1.4:1.0: 2 ports detected
10801 06:50:17.387548 <6>[ 5.234618] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10802 06:50:17.579535 <6>[ 5.426615] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10803 06:50:28.544556 <6>[ 16.399648] ALSA device list:
10804 06:50:28.551312 <6>[ 16.402939] No soundcards found.
10805 06:50:28.559380 <6>[ 16.410916] Freeing unused kernel memory: 8448K
10806 06:50:28.562708 <6>[ 16.415946] Run /init as init process
10807 06:50:28.612444 <6>[ 16.463788] NET: Registered PF_INET6 protocol family
10808 06:50:28.619447 <6>[ 16.470672] Segment Routing with IPv6
10809 06:50:28.622241 <6>[ 16.474643] In-situ OAM (IOAM) with IPv6
10810 06:50:28.656846 <30>[ 16.491861] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10811 06:50:28.664261 <30>[ 16.515833] systemd[1]: Detected architecture arm64.
10812 06:50:28.664345
10813 06:50:28.670649 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10814 06:50:28.670729
10815 06:50:28.683178 <30>[ 16.534607] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10816 06:50:28.850681 <30>[ 16.699137] systemd[1]: Queued start job for default target Graphical Interface.
10817 06:50:28.896050 <30>[ 16.747451] systemd[1]: Created slice system-getty.slice.
10818 06:50:28.902585 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10819 06:50:28.919865 <30>[ 16.771271] systemd[1]: Created slice system-modprobe.slice.
10820 06:50:28.926524 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10821 06:50:28.943658 <30>[ 16.794915] systemd[1]: Created slice system-serial\x2dgetty.slice.
10822 06:50:28.953563 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10823 06:50:28.968195 <30>[ 16.819624] systemd[1]: Created slice User and Session Slice.
10824 06:50:28.974940 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10825 06:50:28.994713 <30>[ 16.843149] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10826 06:50:29.005068 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10827 06:50:29.022879 <30>[ 16.871192] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10828 06:50:29.029490 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10829 06:50:29.054394 <30>[ 16.898683] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10830 06:50:29.060555 <30>[ 16.910817] systemd[1]: Reached target Local Encrypted Volumes.
10831 06:50:29.066807 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10832 06:50:29.083622 <30>[ 16.935096] systemd[1]: Reached target Paths.
10833 06:50:29.087244 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10834 06:50:29.103222 <30>[ 16.954585] systemd[1]: Reached target Remote File Systems.
10835 06:50:29.109711 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10836 06:50:29.123023 <30>[ 16.974580] systemd[1]: Reached target Slices.
10837 06:50:29.126594 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10838 06:50:29.142956 <30>[ 16.994609] systemd[1]: Reached target Swap.
10839 06:50:29.146374 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10840 06:50:29.167334 <30>[ 17.015076] systemd[1]: Listening on initctl Compatibility Named Pipe.
10841 06:50:29.173266 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10842 06:50:29.180031 <30>[ 17.030227] systemd[1]: Listening on Journal Audit Socket.
10843 06:50:29.186796 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10844 06:50:29.199896 <30>[ 17.051049] systemd[1]: Listening on Journal Socket (/dev/log).
10845 06:50:29.206072 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10846 06:50:29.224211 <30>[ 17.075836] systemd[1]: Listening on Journal Socket.
10847 06:50:29.231019 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10848 06:50:29.243818 <30>[ 17.095173] systemd[1]: Listening on udev Control Socket.
10849 06:50:29.250051 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10850 06:50:29.268218 <30>[ 17.119659] systemd[1]: Listening on udev Kernel Socket.
10851 06:50:29.274372 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10852 06:50:29.314850 <30>[ 17.166681] systemd[1]: Mounting Huge Pages File System...
10853 06:50:29.321749 Mounting [0;1;39mHuge Pages File System[0m...
10854 06:50:29.336422 <30>[ 17.188124] systemd[1]: Mounting POSIX Message Queue File System...
10855 06:50:29.343347 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10856 06:50:29.361068 <30>[ 17.212435] systemd[1]: Mounting Kernel Debug File System...
10857 06:50:29.367246 Mounting [0;1;39mKernel Debug File System[0m...
10858 06:50:29.386617 <30>[ 17.234802] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10859 06:50:29.398257 <30>[ 17.246291] systemd[1]: Starting Create list of static device nodes for the current kernel...
10860 06:50:29.404732 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10861 06:50:29.426598 <30>[ 17.278265] systemd[1]: Starting Load Kernel Module configfs...
10862 06:50:29.433278 Starting [0;1;39mLoad Kernel Module configfs[0m...
10863 06:50:29.451500 <30>[ 17.303039] systemd[1]: Starting Load Kernel Module drm...
10864 06:50:29.457769 Starting [0;1;39mLoad Kernel Module drm[0m...
10865 06:50:29.474548 <30>[ 17.322976] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10866 06:50:29.520246 <30>[ 17.371435] systemd[1]: Starting Journal Service...
10867 06:50:29.522960 Starting [0;1;39mJournal Service[0m...
10868 06:50:29.544910 <30>[ 17.396671] systemd[1]: Starting Load Kernel Modules...
10869 06:50:29.551847 Starting [0;1;39mLoad Kernel Modules[0m...
10870 06:50:29.574971 <30>[ 17.423349] systemd[1]: Starting Remount Root and Kernel File Systems...
10871 06:50:29.581873 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10872 06:50:29.598724 <30>[ 17.450595] systemd[1]: Starting Coldplug All udev Devices...
10873 06:50:29.605740 Starting [0;1;39mColdplug All udev Devices[0m...
10874 06:50:29.622316 <30>[ 17.473544] systemd[1]: Started Journal Service.
10875 06:50:29.628708 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10876 06:50:29.645400 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10877 06:50:29.659772 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10878 06:50:29.675787 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10879 06:50:29.695481 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10880 06:50:29.712203 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10881 06:50:29.733167 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10882 06:50:29.756952 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10883 06:50:29.781270 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10884 06:50:29.798960 See 'systemctl status systemd-remount-fs.service' for details.
10885 06:50:29.852274 Mounting [0;1;39mKernel Configuration File System[0m...
10886 06:50:29.873412 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10887 06:50:29.891731 <46>[ 17.739883] systemd-journald[179]: Received client request to flush runtime journal.
10888 06:50:29.900380 Starting [0;1;39mLoad/Save Random Seed[0m...
10889 06:50:29.920723 Starting [0;1;39mApply Kernel Variables[0m...
10890 06:50:29.940529 Starting [0;1;39mCreate System Users[0m...
10891 06:50:29.959919 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10892 06:50:29.975655 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10893 06:50:29.996368 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10894 06:50:30.007796 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10895 06:50:30.024722 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10896 06:50:30.040622 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10897 06:50:30.079343 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10898 06:50:30.099036 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10899 06:50:30.115466 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10900 06:50:30.131253 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10901 06:50:30.168112 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10902 06:50:30.197730 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10903 06:50:30.217167 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10904 06:50:30.229838 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10905 06:50:30.272134 Starting [0;1;39mNetwork Time Synchronization[0m...
10906 06:50:30.291872 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10907 06:50:30.328810 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10908 06:50:30.344299 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10909 06:50:30.365780 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10910 06:50:30.391543 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary <6>[ 18.242169] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10911 06:50:30.394816 Directories[0m.
10912 06:50:30.407019 <6>[ 18.255689] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10913 06:50:30.420940 [[0;32m OK [<6>[ 18.265712] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10914 06:50:30.430315 0m] Reached targ<6>[ 18.276088] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10915 06:50:30.436768 et [0;1;39mSyst<6>[ 18.276836] remoteproc remoteproc0: scp is available
10916 06:50:30.443693 em Time Set[0m.<6>[ 18.291870] usbcore: registered new device driver r8152-cfgselector
10917 06:50:30.446843 <6>[ 18.292400] remoteproc remoteproc0: powering up scp
10918 06:50:30.456788 <4>[ 18.293126] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10919 06:50:30.456870
10920 06:50:30.463747 <4>[ 18.293255] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10921 06:50:30.470295 <3>[ 18.303061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10922 06:50:30.480306 <6>[ 18.305746] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10923 06:50:30.486838 <3>[ 18.313248] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10924 06:50:30.493318 <6>[ 18.320319] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10925 06:50:30.503142 <3>[ 18.330003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10926 06:50:30.507493 <6>[ 18.343132] mc: Linux media interface: v0.10
10927 06:50:30.516709 <3>[ 18.346278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10928 06:50:30.523125 <6>[ 18.355067] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10929 06:50:30.529959 <3>[ 18.360367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10930 06:50:30.539606 <4>[ 18.381251] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10931 06:50:30.543194 <4>[ 18.381251] Fallback method does not support PEC.
10932 06:50:30.552701 <3>[ 18.387545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10933 06:50:30.560788 <6>[ 18.390620] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10934 06:50:30.570142 <6>[ 18.405683] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10935 06:50:30.576724 <6>[ 18.409114] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10936 06:50:30.583366 <6>[ 18.409119] pci_bus 0000:00: root bus resource [bus 00-ff]
10937 06:50:30.590593 <6>[ 18.409123] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10938 06:50:30.600177 <6>[ 18.409126] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10939 06:50:30.606615 <6>[ 18.409152] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10940 06:50:30.613510 <6>[ 18.409166] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10941 06:50:30.617024 <6>[ 18.409232] pci 0000:00:00.0: supports D1 D2
10942 06:50:30.623347 <6>[ 18.409234] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10943 06:50:30.633470 <3>[ 18.409281] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10944 06:50:30.639688 <3>[ 18.409293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10945 06:50:30.650315 <6>[ 18.410375] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10946 06:50:30.657143 <6>[ 18.410486] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10947 06:50:30.663716 <6>[ 18.410514] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10948 06:50:30.669565 <6>[ 18.410531] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10949 06:50:30.679933 <6>[ 18.410546] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10950 06:50:30.683023 <6>[ 18.410655] pci 0000:01:00.0: supports D1 D2
10951 06:50:30.689569 <6>[ 18.410657] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10952 06:50:30.699453 <6>[ 18.414880] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10953 06:50:30.709575 <4>[ 18.414888] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10954 06:50:30.716621 <4>[ 18.414901] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10955 06:50:30.726204 <6>[ 18.416830] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10956 06:50:30.735985 <3>[ 18.417475] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 06:50:30.743173 <6>[ 18.426921] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10958 06:50:30.749222 <6>[ 18.427333] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10959 06:50:30.759735 <3>[ 18.433983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10960 06:50:30.762535 <6>[ 18.435485] videodev: Linux video capture interface: v2.00
10961 06:50:30.773048 <6>[ 18.439879] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10962 06:50:30.779148 <3>[ 18.446931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10963 06:50:30.785996 <6>[ 18.456851] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10964 06:50:30.792475 <6>[ 18.457307] Bluetooth: Core ver 2.22
10965 06:50:30.795700 <6>[ 18.457414] NET: Registered PF_BLUETOOTH protocol family
10966 06:50:30.802907 <6>[ 18.457418] Bluetooth: HCI device and connection manager initialized
10967 06:50:30.809032 <6>[ 18.457452] Bluetooth: HCI socket layer initialized
10968 06:50:30.812636 <6>[ 18.457461] Bluetooth: L2CAP socket layer initialized
10969 06:50:30.819310 <6>[ 18.457476] Bluetooth: SCO socket layer initialized
10970 06:50:30.829172 <6>[ 18.457644] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10971 06:50:30.832593 <6>[ 18.457653] remoteproc remoteproc0: remote processor scp is now up
10972 06:50:30.843295 <6>[ 18.457653] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10973 06:50:30.848989 <3>[ 18.463019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10974 06:50:30.855770 <3>[ 18.463024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10975 06:50:30.865616 <3>[ 18.463087] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10976 06:50:30.872600 <6>[ 18.470572] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10977 06:50:30.881951 <3>[ 18.475020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10978 06:50:30.889311 <3>[ 18.475023] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10979 06:50:30.899023 <3>[ 18.475028] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10980 06:50:30.905646 <3>[ 18.475030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10981 06:50:30.909291 <6>[ 18.475163] r8152 2-1.3:1.0 eth0: v1.12.13
10982 06:50:30.915559 <6>[ 18.475384] usbcore: registered new interface driver r8152
10983 06:50:30.922332 <6>[ 18.481948] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10984 06:50:30.932539 <3>[ 18.489999] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10985 06:50:30.938824 <6>[ 18.492477] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10986 06:50:30.952271 <6>[ 18.493494] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10987 06:50:30.959107 <6>[ 18.493611] usbcore: registered new interface driver uvcvideo
10988 06:50:30.962171 <6>[ 18.498142] pci 0000:00:00.0: PCI bridge to [bus 01]
10989 06:50:30.972123 <6>[ 18.499011] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10990 06:50:30.975489 <6>[ 18.509573] usbcore: registered new interface driver cdc_ether
10991 06:50:30.985218 <6>[ 18.513065] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10992 06:50:30.991724 <6>[ 18.516243] usbcore: registered new interface driver btusb
10993 06:50:30.998671 <6>[ 18.516352] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10994 06:50:31.008603 <4>[ 18.516951] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10995 06:50:31.014812 <3>[ 18.516968] Bluetooth: hci0: Failed to load firmware file (-2)
10996 06:50:31.021584 <3>[ 18.516973] Bluetooth: hci0: Failed to set up firmware (-2)
10997 06:50:31.032074 <4>[ 18.516978] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10998 06:50:31.038755 <6>[ 18.527956] usbcore: registered new interface driver r8153_ecm
10999 06:50:31.045086 <6>[ 18.535367] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11000 06:50:31.051586 <6>[ 18.540609] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11001 06:50:31.055178 <6>[ 18.547231] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11002 06:50:31.061537 <6>[ 18.549769] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11003 06:50:31.071287 [[0;32m OK [<6>[ 18.920250] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11004 06:50:31.074938 0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11005 06:50:31.091382 <5>[ 18.939566] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11006 06:50:31.098356 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11007 06:50:31.104239 <5>[ 18.956038] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11008 06:50:31.115046 <5>[ 18.963189] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11009 06:50:31.124775 <4>[ 18.971699] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11010 06:50:31.128165 <6>[ 18.980579] cfg80211: failed to load regulatory.db
11011 06:50:31.134981 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11012 06:50:31.162795 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message B<3>[ 19.009554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11013 06:50:31.169170 <3>[ 19.011522] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11014 06:50:31.172457 us Socket[0m.
11015 06:50:31.186252 <6>[ 19.034063] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11016 06:50:31.192829 <3>[ 19.037029] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11017 06:50:31.199532 <6>[ 19.041566] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11018 06:50:31.209686 <3>[ 19.051051] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11019 06:50:31.213219 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11020 06:50:31.223829 <3>[ 19.072100] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11021 06:50:31.230300 <6>[ 19.074458] mt7921e 0000:01:00.0: ASIC revision: 79610010
11022 06:50:31.236508 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11023 06:50:31.252519 <3>[ 19.101427] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 06:50:31.283267 <3>[ 19.131401] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11025 06:50:31.289204 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11026 06:50:31.313252 <3>[ 19.162083] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11027 06:50:31.333959 <6>[ 19.182584] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11028 06:50:31.334047 <6>[ 19.182584]
11029 06:50:31.346886 <3>[ 19.195026] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11030 06:50:31.353280 Starting [0;1;39mUser Login Management[0m...
11031 06:50:31.370336 Starting [0;1;39mPermit User Sessions[0m...
11032 06:50:31.388017 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11033 06:50:31.412699 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11034 06:50:31.447037 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11035 06:50:31.603384 <6>[ 19.452044] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11036 06:50:31.623165 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11037 06:50:31.639371 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11038 06:50:31.659272 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11039 06:50:31.695930 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11040 06:50:31.716525 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11041 06:50:31.732323 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11042 06:50:31.747608 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11043 06:50:31.763535 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11044 06:50:31.816143 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11045 06:50:31.839974 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11046 06:50:31.861655 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11047 06:50:31.920722 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11048 06:50:31.936532 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11049 06:50:31.963680 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11050 06:50:31.985182
11051 06:50:31.985308
11052 06:50:31.988250 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11053 06:50:31.988347
11054 06:50:31.991316 debian-bullseye-arm64 login: root (automatic login)
11055 06:50:31.991399
11056 06:50:31.991491
11057 06:50:32.006701 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
11058 06:50:32.006787
11059 06:50:32.013058 The programs included with the Debian GNU/Linux system are free software;
11060 06:50:32.019729 the exact distribution terms for each program are described in the
11061 06:50:32.023391 individual files in /usr/share/doc/*/copyright.
11062 06:50:32.023473
11063 06:50:32.030005 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11064 06:50:32.032977 permitted by applicable law.
11065 06:50:32.033355 Matched prompt #10: / #
11067 06:50:32.033556 Setting prompt string to ['/ #']
11068 06:50:32.033647 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11070 06:50:32.033837 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11071 06:50:32.033921 start: 2.2.6 expect-shell-connection (timeout 00:02:36) [common]
11072 06:50:32.033989 Setting prompt string to ['/ #']
11073 06:50:32.034048 Forcing a shell prompt, looking for ['/ #']
11075 06:50:32.084260 / #
11076 06:50:32.084378 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11077 06:50:32.084456 Waiting using forced prompt support (timeout 00:02:30)
11078 06:50:32.089155
11079 06:50:32.089428 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11080 06:50:32.089519 start: 2.2.7 export-device-env (timeout 00:02:35) [common]
11081 06:50:32.089666 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11082 06:50:32.089785 end: 2.2 depthcharge-retry (duration 00:02:25) [common]
11083 06:50:32.089869 end: 2 depthcharge-action (duration 00:02:25) [common]
11084 06:50:32.089957 start: 3 lava-test-retry (timeout 00:07:10) [common]
11085 06:50:32.090037 start: 3.1 lava-test-shell (timeout 00:07:10) [common]
11086 06:50:32.090111 Using namespace: common
11088 06:50:32.190383 / # #
11089 06:50:32.190563 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11090 06:50:32.195518 #
11091 06:50:32.195789 Using /lava-12694787
11093 06:50:32.296152 / # export SHELL=/bin/sh
11094 06:50:32.301475 export SHELL=/bin/sh
11096 06:50:32.402068 / # . /lava-12694787/environment
11097 06:50:32.407822 . /lava-12694787/environment
11099 06:50:32.508369 / # /lava-12694787/bin/lava-test-runner /lava-12694787/0
11100 06:50:32.508496 Test shell timeout: 10s (minimum of the action and connection timeout)
11101 06:50:32.508810 <6>[ 20.306424] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11102 06:50:32.513892 /lava-12694787/bin/lava-test-runner /lava-12694787/0
11103 06:50:32.554596 + export TESTRUN_I<8>[ 20.391869] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 12694787_1.5.2.3.1>
11104 06:50:32.554686 D=0_igt-kms-mediatek
11105 06:50:32.554750 + cd /lava-12694787/0/tests/0_igt-kms-mediatek
11106 06:50:32.554812 + cat uuid
11107 06:50:32.554870 + UUID=12694787_1.5.2.3.1
11108 06:50:32.554927 + set +x
11109 06:50:32.555156 Received signal: <STARTRUN> 0_igt-kms-mediatek 12694787_1.5.2.3.1
11110 06:50:32.555224 Starting test lava.0_igt-kms-mediatek (12694787_1.5.2.3.1)
11111 06:50:32.555307 Skipping test definition patterns.
11112 06:50:32.575338 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob km<8>[ 20.425737] <LAVA_SIGNAL_TESTSET START core_auth>
11113 06:50:32.575596 Received signal: <TESTSET> START core_auth
11114 06:50:32.575667 Starting test_set core_auth
11115 06:50:32.577820 s_setmode kms_vblank
11116 06:50:32.603465 <14>[ 20.455335] [IGT] core_auth: executing
11117 06:50:32.609945 IGT-Version: 1.2<14>[ 20.459772] [IGT] core_auth: starting subtest getclient-simple
11118 06:50:32.619978 7.1-g621c2d3 (aa<14>[ 20.467633] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11119 06:50:32.623461 rch64) (Linux: 6<14>[ 20.475625] [IGT] core_auth: exiting, ret=0
11120 06:50:32.626985 .1.75-cip14 aarch64)
11121 06:50:32.630351 Starting subtest: getclient-simple
11122 06:50:32.640125 Opened device: /dev/dr<8>[ 20.488269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11123 06:50:32.640207 i/card0
11124 06:50:32.640444 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11126 06:50:32.643764 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11127 06:50:32.666902 <14>[ 20.518427] [IGT] core_auth: executing
11128 06:50:32.673374 IGT-Version: 1.2<14>[ 20.522852] [IGT] core_auth: starting subtest getclient-master-drop
11129 06:50:32.683183 7.1-g621c2d3 (aa<14>[ 20.531097] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11130 06:50:32.689843 rch64) (Linux: 6<14>[ 20.539544] [IGT] core_auth: exiting, ret=0
11131 06:50:32.689925 .1.75-cip14 aarch64)
11132 06:50:32.693532 Starting subtest: getclient-master-drop
11133 06:50:32.699977 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11135 06:50:32.703400 O<8>[ 20.550912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11136 06:50:32.703482 pened device: /dev/dri/card0
11137 06:50:32.709999 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11138 06:50:32.734747 <14>[ 20.586471] [IGT] core_auth: executing
11139 06:50:32.741330 IGT-Version: 1.2<14>[ 20.591122] [IGT] core_auth: starting subtest basic-auth
11140 06:50:32.748005 7.1-g621c2d3 (aa<14>[ 20.598063] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11141 06:50:32.754591 rch64) (Linux: 6<14>[ 20.605861] [IGT] core_auth: exiting, ret=0
11142 06:50:32.757536 .1.75-cip14 aarch64)
11143 06:50:32.757616 Opened device: /dev/dri/card0
11144 06:50:32.760999 Starting subtest: basic-auth
11145 06:50:32.770944 [1mSubtest b<8>[ 20.618957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11146 06:50:32.771197 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11148 06:50:32.774671 asic-auth: SUCCESS (0.000s)[0m
11149 06:50:32.787372 <14>[ 20.639328] [IGT] core_auth: executing
11150 06:50:32.794018 IGT-Version: 1.2<14>[ 20.643721] [IGT] core_auth: starting subtest many-magics
11151 06:50:32.797339 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11152 06:50:32.807403 Opened device: /dev/dri/ca<14>[ 20.657430] [IGT] core_auth: finished subtest many-magics, SUCCESS
11153 06:50:32.807483 rd0
11154 06:50:32.814043 Starting su<14>[ 20.664337] [IGT] core_auth: exiting, ret=0
11155 06:50:32.814123 btest: many-magics
11156 06:50:32.817245 Reopening device failed after 1020 opens
11157 06:50:32.827367 [1mSubtest many-m<8>[ 20.676549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11158 06:50:32.827618 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11160 06:50:32.830426 agics: SUCCESS (0.007s)[0m
11161 06:50:32.834114 <8>[ 20.685445] <LAVA_SIGNAL_TESTSET STOP>
11162 06:50:32.834363 Received signal: <TESTSET> STOP
11163 06:50:32.834463 Closing test_set core_auth
11164 06:50:32.864414 <14>[ 20.716728] [IGT] core_getclient: executing
11165 06:50:32.871822 IGT-Version: 1.2<14>[ 20.721606] [IGT] core_getclient: exiting, ret=0
11166 06:50:32.874680 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11167 06:50:32.884479 Opened dev<8>[ 20.732386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11168 06:50:32.884562 ice: /dev/dri/card0
11169 06:50:32.884796 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11171 06:50:32.887585 SUCCESS (0.006s)
11172 06:50:32.926716 <14>[ 20.779064] [IGT] core_getstats: executing
11173 06:50:32.933626 IGT-Version: 1.2<14>[ 20.783817] [IGT] core_getstats: exiting, ret=0
11174 06:50:32.937000 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11175 06:50:32.946986 Opened dev<8>[ 20.794525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11176 06:50:32.947067 ice: /dev/dri/card0
11177 06:50:32.947306 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11179 06:50:32.949948 SUCCESS (0.006s)
11180 06:50:32.975814 <14>[ 20.827925] [IGT] core_getversion: executing
11181 06:50:32.982722 IGT-Version: 1.2<14>[ 20.832869] [IGT] core_getversion: exiting, ret=0
11182 06:50:32.985933 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11183 06:50:32.995702 Opened dev<8>[ 20.843631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11184 06:50:32.995827 ice: /dev/dri/card0
11185 06:50:32.996088 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11187 06:50:32.998994 SUCCESS (0.006s)
11188 06:50:33.028640 <14>[ 20.881016] [IGT] core_setmaster_vs_auth: executing
11189 06:50:33.035630 IGT-Version: 1.2<14>[ 20.886908] [IGT] core_setmaster_vs_auth: exiting, ret=0
11190 06:50:33.042450 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11191 06:50:33.053060 Opened device: /dev/dri/ca<8>[ 20.900200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11192 06:50:33.053144 rd0
11193 06:50:33.053209 SUCCESS (0.007s)
11194 06:50:33.053444 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11196 06:50:33.070793 <8>[ 20.923121] <LAVA_SIGNAL_TESTSET START drm_read>
11197 06:50:33.071045 Received signal: <TESTSET> START drm_read
11198 06:50:33.071114 Starting test_set drm_read
11199 06:50:33.088409 <14>[ 20.940199] [IGT] drm_read: executing
11200 06:50:33.094684 IGT-Version: 1.2<14>[ 20.944678] [IGT] drm_read: exiting, ret=77
11201 06:50:33.098282 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11202 06:50:33.104983 Opened dev<8>[ 20.955259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11203 06:50:33.105241 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11205 06:50:33.108399 ice: /dev/dri/card0
11206 06:50:33.111446 No KMS driver or no outputs, pipes: 8, outputs: 0
11207 06:50:33.117829 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11208 06:50:33.121771 <14>[ 20.975421] [IGT] drm_read: executing
11209 06:50:33.128218 IGT-Version: 1.2<14>[ 20.979858] [IGT] drm_read: exiting, ret=77
11210 06:50:33.134828 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11211 06:50:33.140972 Opened dev<8>[ 20.990262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11212 06:50:33.141055 ice: /dev/dri/card0
11213 06:50:33.141290 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11215 06:50:33.148481 No KMS driver or no outputs, pipes: 8, outputs: 0
11216 06:50:33.151275 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11217 06:50:33.157942 <14>[ 21.009981] [IGT] drm_read: executing
11218 06:50:33.164593 IGT-Version: 1.2<14>[ 21.014552] [IGT] drm_read: exiting, ret=77
11219 06:50:33.167850 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11220 06:50:33.174916 Opened dev<8>[ 21.024659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11221 06:50:33.175171 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11223 06:50:33.177603 ice: /dev/dri/card0
11224 06:50:33.181003 No KMS driver or no outputs, pipes: 8, outputs: 0
11225 06:50:33.184397 [1mSubtest empty-block: SKIP (0.000s)[0m
11226 06:50:33.192397 <14>[ 21.044607] [IGT] drm_read: executing
11227 06:50:33.199248 IGT-Version: 1.2<14>[ 21.049052] [IGT] drm_read: exiting, ret=77
11228 06:50:33.202898 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11229 06:50:33.209249 Opened dev<8>[ 21.059307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11230 06:50:33.209503 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11232 06:50:33.212887 ice: /dev/dri/card0
11233 06:50:33.215768 No KMS driver or no outputs, pipes: 8, outputs: 0
11234 06:50:33.219364 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11235 06:50:33.227857 <14>[ 21.079947] [IGT] drm_read: executing
11236 06:50:33.235364 IGT-Version: 1.2<14>[ 21.084380] [IGT] drm_read: exiting, ret=77
11237 06:50:33.237474 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11238 06:50:33.244572 Opened dev<8>[ 21.095023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11239 06:50:33.244826 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11241 06:50:33.247786 ice: /dev/dri/card0
11242 06:50:33.251311 No KMS driver or no outputs, pipes: 8, outputs: 0
11243 06:50:33.257907 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11244 06:50:33.261243 <14>[ 21.114811] [IGT] drm_read: executing
11245 06:50:33.267463 IGT-Version: 1.2<14>[ 21.119311] [IGT] drm_read: exiting, ret=77
11246 06:50:33.270982 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11247 06:50:33.280658 Opened dev<8>[ 21.129477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11248 06:50:33.280914 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11250 06:50:33.284236 ice: /dev/dri/card0
11251 06:50:33.287485 No KMS driver or no outputs, pipes: 8, outputs: 0
11252 06:50:33.290599 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11253 06:50:33.298662 <14>[ 21.150431] [IGT] drm_read: executing
11254 06:50:33.305208 IGT-Version: 1.2<14>[ 21.154885] [IGT] drm_read: exiting, ret=77
11255 06:50:33.308822 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11256 06:50:33.314946 Opened dev<8>[ 21.165084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11257 06:50:33.315200 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11259 06:50:33.318375 ice: /dev/dri/card0
11260 06:50:33.321968 Received signal: <TESTSET> STOP
11261 06:50:33.322047 Closing test_set drm_read
11262 06:50:33.325056 No KMS driv<8>[ 21.175293] <LAVA_SIGNAL_TESTSET STOP>
11263 06:50:33.328590 er or no outputs, pipes: 8, outputs: 0
11264 06:50:33.331311 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11265 06:50:33.343963 <8>[ 21.195660] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11266 06:50:33.344214 Received signal: <TESTSET> START kms_addfb_basic
11267 06:50:33.344282 Starting test_set kms_addfb_basic
11268 06:50:33.365479 <14>[ 21.216809] [IGT] kms_addfb_basic: executing
11269 06:50:33.378154 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarc<14>[ 21.225875] [IGT] kms_addfb_basic: starting subtest unused-handle
11270 06:50:33.378237 h64)
11271 06:50:33.384862 Opened dev<14>[ 21.233777] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11272 06:50:33.388253 ice: /dev/dri/card0
11273 06:50:33.392222 Starting subtest: unused-handle
11274 06:50:33.398074 [1mSubtest unused-handle: SUCCESS (0.000s<14>[ 21.250577] [IGT] kms_addfb_basic: exiting, ret=0
11275 06:50:33.398157 )[0m
11276 06:50:33.411491 Test requirement not met in function igt_require_i915, file ../lib/drmtes<8>[ 21.261393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11277 06:50:33.411749 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11279 06:50:33.414652 t.c:720:
11280 06:50:33.418271 Test requirement: is_i915_device(fd)
11281 06:50:33.424833 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11282 06:50:33.431096 Test requirement: is_i915_dev<14>[ 21.282788] [IGT] kms_addfb_basic: executing
11283 06:50:33.431179 ice(fd)
11284 06:50:33.437840 No KMS driver or no outputs, pipes: 8, outputs: 0
11285 06:50:33.444936 IGT-<14>[ 21.292762] [IGT] kms_addfb_basic: starting subtest unused-pitches
11286 06:50:33.450994 Version: 1.27.1-<14>[ 21.300671] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11287 06:50:33.458168 g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11288 06:50:33.458249 Opened device: /dev/dri/card0
11289 06:50:33.464791 Starting subtes<14>[ 21.317311] [IGT] kms_addfb_basic: exiting, ret=0
11290 06:50:33.467886 t: unused-pitches
11291 06:50:33.478005 [1mSubtest unused-pitches: SUCCESS (0.000s)<8>[ 21.328233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11292 06:50:33.478088 [0m
11293 06:50:33.478325 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11295 06:50:33.484787 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11296 06:50:33.487727 Test requirement: is_i915_device(fd)
11297 06:50:33.498421 Test requirement not met in functi<14>[ 21.348146] [IGT] kms_addfb_basic: executing
11298 06:50:33.500965 on igt_require_i915, file ../lib/drmtest.c:720:
11299 06:50:33.507638 Test requiremen<14>[ 21.358326] [IGT] kms_addfb_basic: starting subtest unused-offsets
11300 06:50:33.517756 t: is_i915_devic<14>[ 21.366265] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11301 06:50:33.517838 e(fd)
11302 06:50:33.524566 No KMS driver or no outputs, pipes: 8, outputs: 0
11303 06:50:33.530842 IGT-Version: 1.27.1-g621c2d3 (aarch64)<14>[ 21.382977] [IGT] kms_addfb_basic: exiting, ret=0
11304 06:50:33.534355 (Linux: 6.1.75-cip14 aarch64)
11305 06:50:33.537537 Opened device: /dev/dri/card0
11306 06:50:33.544357 Starting subtest:<8>[ 21.394149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11307 06:50:33.544613 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11309 06:50:33.547359 unused-offsets
11310 06:50:33.550859 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11311 06:50:33.557834 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11312 06:50:33.564119 Test requi<14>[ 21.415531] [IGT] kms_addfb_basic: executing
11313 06:50:33.567418 rement: is_i915_device(fd)
11314 06:50:33.577369 Test requirement not met in function<14>[ 21.425419] [IGT] kms_addfb_basic: starting subtest unused-modifier
11315 06:50:33.584164 igt_require_i91<14>[ 21.433367] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11316 06:50:33.587653 5, file ../lib/drmtest.c:720:
11317 06:50:33.590822 Test requirement: is_i915_device(fd)
11318 06:50:33.597208 No KMS driver or no outputs<14>[ 21.450187] [IGT] kms_addfb_basic: exiting, ret=0
11319 06:50:33.600333 , pipes: 8, outputs: 0
11320 06:50:33.614063 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-ci<8>[ 21.461381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11321 06:50:33.614145 p14 aarch64)
11322 06:50:33.614382 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11324 06:50:33.617058 Opened device: /dev/dri/card0
11325 06:50:33.620699 Starting subtest: unused-modifier
11326 06:50:33.624088 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11327 06:50:33.630940 Test requirement not met in f<14>[ 21.482640] [IGT] kms_addfb_basic: executing
11328 06:50:33.637561 unction igt_require_i915, file ../lib/drmtest.c:720:
11329 06:50:33.643980 Test requi<14>[ 21.492712] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11330 06:50:33.654092 rement: is_i915_<14>[ 21.501050] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11331 06:50:33.654171 device(fd)
11332 06:50:33.660406 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11333 06:50:33.667061 T<14>[ 21.517934] [IGT] kms_addfb_basic: exiting, ret=77
11334 06:50:33.670623 est requirement: is_i915_device(fd)
11335 06:50:33.680518 No KMS driver or no outputs<8>[ 21.527905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11336 06:50:33.680608 , pipes: 8, outputs: 0
11337 06:50:33.680845 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11339 06:50:33.686991 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11340 06:50:33.690528 Opened device: /dev/dri/card0
11341 06:50:33.697383 Starting subtest: c<14>[ 21.548510] [IGT] kms_addfb_basic: executing
11342 06:50:33.697462 lobberred-modifier
11343 06:50:33.710434 Test requirement not met in function igt_req<14>[ 21.558076] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11344 06:50:33.720394 uire_i915, file <14>[ 21.567187] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11345 06:50:33.720474 ../lib/drmtest.c:720:
11346 06:50:33.724002 Test requirement: is_i915_device(fd)
11347 06:50:33.733431 [1mSubtest clobberred-modifier: SK<14>[ 21.584654] [IGT] kms_addfb_basic: exiting, ret=77
11348 06:50:33.733512 IP (0.000s)[0m
11349 06:50:33.746775 Test requirement not met in function igt_require_i915, file ../<8>[ 21.596036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11350 06:50:33.747030 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11352 06:50:33.749697 lib/drmtest.c:720:
11353 06:50:33.753417 Test requirement: is_i915_device(fd)
11354 06:50:33.759937 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11355 06:50:33.766730 Tes<14>[ 21.617813] [IGT] kms_addfb_basic: executing
11356 06:50:33.770091 t requirement: is_i915_device(fd)
11357 06:50:33.776233 No KMS driver or no outputs, <14>[ 21.626924] [IGT] kms_addfb_basic: starting subtest legacy-format
11358 06:50:33.779849 pipes: 8, outputs: 0
11359 06:50:33.793679 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip1<14>[ 21.640976] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11360 06:50:33.793835 4 aarch64)
11361 06:50:33.796282 Opened device: /dev/dri/card0
11362 06:50:33.799575 Starting subtest: invalid-smem-bo-on-discrete
11363 06:50:33.805964 Test r<14>[ 21.657060] [IGT] kms_addfb_basic: exiting, ret=0
11364 06:50:33.812588 equirement not met in function igt_require_intel, file ../lib/drmtest.c:715:
11365 06:50:33.819256 Te<8>[ 21.668061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11366 06:50:33.819512 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11368 06:50:33.822376 st requirement: is_intel_device(fd)
11369 06:50:33.829193 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11370 06:50:33.839296 Test requirement not met in function igt_require_i915, file ../<14>[ 21.688861] [IGT] kms_addfb_basic: executing
11371 06:50:33.839377 lib/drmtest.c:720:
11372 06:50:33.842757 Test requirement: is_i915_device(fd)
11373 06:50:33.849514 Test requirement not m<14>[ 21.701453] [IGT] kms_addfb_basic: starting subtest no-handle
11374 06:50:33.859219 et in function i<14>[ 21.708156] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11375 06:50:33.862498 gt_require_i915, file ../lib/drmtest.c:720:
11376 06:50:33.872392 Test requirement: is_i915_device(fd<14>[ 21.722260] [IGT] kms_addfb_basic: exiting, ret=0
11377 06:50:33.872473 )
11378 06:50:33.875972 No KMS driver or no outputs, pipes: 8, outputs: 0
11379 06:50:33.885844 IGT-Version: 1.27.1-g621c2<8>[ 21.734019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11380 06:50:33.886099 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11382 06:50:33.889296 d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11383 06:50:33.892172 Opened device: /dev/dri/card0
11384 06:50:33.895642 Starting subtest: legacy-format
11385 06:50:33.898805 Successfully fuzzed 10000 {bpp, depth} variations
11386 06:50:33.902359 <14>[ 21.754963] [IGT] kms_addfb_basic: executing
11387 06:50:33.908627 [1mSubtest legacy-format: SUCCESS (0.006s)[0m
11388 06:50:33.915395 Test requirement not met in func<14>[ 21.767236] [IGT] kms_addfb_basic: starting subtest basic
11389 06:50:33.925213 tion igt_require<14>[ 21.773612] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11390 06:50:33.928375 _i915, file ../lib/drmtest.c:720:
11391 06:50:33.932376 Test requirement: is_i915_device(fd)
11392 06:50:33.935425 Test re<14>[ 21.787417] [IGT] kms_addfb_basic: exiting, ret=0
11393 06:50:33.942162 quirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11394 06:50:33.949077 Test<8>[ 21.799411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11395 06:50:33.949331 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11397 06:50:33.951819 requirement: is_i915_device(fd)
11398 06:50:33.958562 No KMS driver or no outputs, pipes: 8, outputs: 0
11399 06:50:33.961798 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11400 06:50:33.968181 Opene<14>[ 21.819550] [IGT] kms_addfb_basic: executing
11401 06:50:33.972011 d device: /dev/dri/card0
11402 06:50:33.972089 Starting subtest: no-handle
11403 06:50:33.981737 [1mSubtest no-handle: SU<14>[ 21.831980] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11404 06:50:33.988569 CCESS (0.000s)[<14>[ 21.838876] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11405 06:50:33.992113 0m
11406 06:50:34.001816 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c<14>[ 21.853053] [IGT] kms_addfb_basic: exiting, ret=0
11407 06:50:34.001899 :720:
11408 06:50:34.005359 Test requirement: is_i915_device(fd)
11409 06:50:34.015045 Test requirement not met in functio<8>[ 21.865094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11410 06:50:34.015313 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11412 06:50:34.018981 n igt_require_i915, file ../lib/drmtest.c:720:
11413 06:50:34.021877 Test requirement: is_i915_device(fd)
11414 06:50:34.028592 No KMS driver or no outputs, pipes: 8, outputs: 0
11415 06:50:34.034930 IGT-Version: 1.27.1-g62<14>[ 21.885862] [IGT] kms_addfb_basic: executing
11416 06:50:34.038653 1c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11417 06:50:34.041789 Opened device: /dev/dri/card0
11418 06:50:34.048578 St<14>[ 21.898062] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11419 06:50:34.054773 arting subtest: <14>[ 21.905196] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11420 06:50:34.058156 basic
11421 06:50:34.061425 [1mSubtest basic: SUCCESS (0.000s)[0m
11422 06:50:34.067980 Test requirement not met in func<14>[ 21.919667] [IGT] kms_addfb_basic: exiting, ret=0
11423 06:50:34.071657 tion igt_require_i915, file ../lib/drmtest.c:720:
11424 06:50:34.081422 Test requirement: is_i915_dev<8>[ 21.931485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11425 06:50:34.081505 ice(fd)
11426 06:50:34.081748 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11428 06:50:34.091452 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11429 06:50:34.094969 Test requirement: is_i915_device(fd)
11430 06:50:34.101702 No KMS driver or no outputs, p<14>[ 21.952136] [IGT] kms_addfb_basic: executing
11431 06:50:34.101784 ipes: 8, outputs: 0
11432 06:50:34.114946 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14<14>[ 21.964768] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11433 06:50:34.115029 aarch64)
11434 06:50:34.121745 Opene<14>[ 21.971677] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11435 06:50:34.124988 d device: /dev/dri/card0
11436 06:50:34.128229 Starting subtest: bad-pitch-0
11437 06:50:34.134617 [1mSubtest bad-pitch-0<14>[ 21.985955] [IGT] kms_addfb_basic: exiting, ret=0
11438 06:50:34.137663 : SUCCESS (0.000s)[0m
11439 06:50:34.147878 Test requirement not met in function igt_require_i915, f<8>[ 21.997896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11440 06:50:34.148135 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11442 06:50:34.151237 ile ../lib/drmtest.c:720:
11443 06:50:34.154570 Test requirement: is_i915_device(fd)
11444 06:50:34.161355 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11445 06:50:34.167961 Test require<14>[ 22.019120] [IGT] kms_addfb_basic: executing
11446 06:50:34.170985 ment: is_i915_device(fd)
11447 06:50:34.174563 No KMS driver or no outputs, pipes: 8, outputs: 0
11448 06:50:34.180903 IGT<14>[ 22.031412] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11449 06:50:34.187981 -Version: 1.27.1<14>[ 22.038158] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11450 06:50:34.194835 -g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11451 06:50:34.201015 Opened device: /dev/dri/card0<14>[ 22.052722] [IGT] kms_addfb_basic: exiting, ret=0
11452 06:50:34.201099
11453 06:50:34.204734 Starting subtest: bad-pitch-32
11454 06:50:34.214909 [1mSubtest bad-pitch-32: SUCC<8>[ 22.064325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11455 06:50:34.215002 ESS (0.000s)[0m
11456 06:50:34.215244 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11458 06:50:34.224336 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11459 06:50:34.227802 Test requirement: is_i915_device(fd)
11460 06:50:34.234040 Test requirement not <14>[ 22.084017] [IGT] kms_addfb_basic: executing
11461 06:50:34.237829 met in function igt_require_i915, file ../lib/drmtest.c:720:
11462 06:50:34.247329 Test requirement: <14>[ 22.096531] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11463 06:50:34.254151 is_i915_device(f<14>[ 22.103614] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11464 06:50:34.254234 d)
11465 06:50:34.260750 No KMS driver or no outputs, pipes: 8, outputs: 0
11466 06:50:34.267383 IGT-Version: 1.27.1-g621c<14>[ 22.118121] [IGT] kms_addfb_basic: exiting, ret=0
11467 06:50:34.270443 2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11468 06:50:34.273803 Opened device: /dev/dri/card0
11469 06:50:34.280738 Star<8>[ 22.130083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11470 06:50:34.281007 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11472 06:50:34.283929 ting subtest: bad-pitch-63
11473 06:50:34.287197 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11474 06:50:34.297153 Test requirement not met in function igt_require_i915, file ../lib/d<14>[ 22.150723] [IGT] kms_addfb_basic: executing
11475 06:50:34.300568 rmtest.c:720:
11476 06:50:34.304067 Test requirement: is_i915_device(fd)
11477 06:50:34.310594 Test requirement not met in<14>[ 22.162001] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11478 06:50:34.320867 function igt_re<14>[ 22.169120] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11479 06:50:34.324453 quire_i915, file ../lib/drmtest.c:720:
11480 06:50:34.327243 Test requirement: is_i915_device(fd)
11481 06:50:34.334241 No<14>[ 22.183705] [IGT] kms_addfb_basic: exiting, ret=0
11482 06:50:34.337046 KMS driver or no outputs, pipes: 8, outputs: 0
11483 06:50:34.348034 IGT-Version: 1.27.1-g621c2d3 (a<8>[ 22.195494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11484 06:50:34.348293 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11486 06:50:34.350376 arch64) (Linux: 6.1.75-cip14 aarch64)
11487 06:50:34.353879 Opened device: /dev/dri/card0
11488 06:50:34.353960 Starting subtest: bad-pitch-128
11489 06:50:34.360405 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11490 06:50:34.363925 Test req<14>[ 22.216488] [IGT] kms_addfb_basic: executing
11491 06:50:34.370511 uirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11492 06:50:34.377253 Test <14>[ 22.229014] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11493 06:50:34.387056 requirement: is_<14>[ 22.236077] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11494 06:50:34.387141 i915_device(fd)
11495 06:50:34.400534 Test requirement not met in function igt_require_i915, file ../<14>[ 22.250619] [IGT] kms_addfb_basic: exiting, ret=0
11496 06:50:34.400618 lib/drmtest.c:720:
11497 06:50:34.403838 Test requirement: is_i915_device(fd)
11498 06:50:34.413888 No KMS driver or no ou<8>[ 22.262439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11499 06:50:34.414145 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11501 06:50:34.417490 tputs, pipes: 8, outputs: 0
11502 06:50:34.420297 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11503 06:50:34.423544 Opened device: /dev/dri/card0
11504 06:50:34.431136 Starting subtest: bad-pitch-25<14>[ 22.283569] [IGT] kms_addfb_basic: executing
11505 06:50:34.433624 6
11506 06:50:34.437144 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11507 06:50:34.446896 Test requirement not met in <14>[ 22.296083] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11508 06:50:34.454009 function igt_req<14>[ 22.303083] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11509 06:50:34.457743 uire_i915, file ../lib/drmtest.c:720:
11510 06:50:34.460490 Test requirement: is_i915_device(fd)
11511 06:50:34.466887 Tes<14>[ 22.317621] [IGT] kms_addfb_basic: exiting, ret=0
11512 06:50:34.473882 t requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11513 06:50:34.480590 <8>[ 22.329545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11514 06:50:34.480847 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11516 06:50:34.483615 Test requirement: is_i915_device(fd)
11517 06:50:34.487025 No KMS driver or no outputs, pipes: 8, outputs: 0
11518 06:50:34.493604 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11519 06:50:34.500629 O<14>[ 22.350945] [IGT] kms_addfb_basic: executing
11520 06:50:34.500711 pened device: /dev/dri/card0
11521 06:50:34.503898 Starting subtest: bad-pitch-1024
11522 06:50:34.517631 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m<14>[ 22.365310] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11523 06:50:34.517715
11524 06:50:34.526771 Test requireme<14>[ 22.373592] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11525 06:50:34.533589 nt not met in function igt_require_i915, file ..<14>[ 22.386872] [IGT] kms_addfb_basic: exiting, ret=0
11526 06:50:34.537306 /lib/drmtest.c:720:
11527 06:50:34.540358 Test requirement: is_i915_device(fd)
11528 06:50:34.550080 Test requirement not <8>[ 22.397911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11529 06:50:34.550337 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11531 06:50:34.553562 met in function igt_require_i915, file ../lib/drmtest.c:720:
11532 06:50:34.556789 Test requirement: is_i915_device(fd)
11533 06:50:34.563987 No KMS driver or no outputs, pipes: 8, outputs: 0
11534 06:50:34.566902 IGT-Versi<14>[ 22.419348] [IGT] kms_addfb_basic: executing
11535 06:50:34.573721 on: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11536 06:50:34.577429 Opened device: /dev/dri/card0
11537 06:50:34.583599 Starting subtest: ba<14>[ 22.433836] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11538 06:50:34.587383 d-pitch-999
11539 06:50:34.593676 [1<14>[ 22.441845] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11540 06:50:34.596831 mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11541 06:50:34.603272 Te<14>[ 22.454739] [IGT] kms_addfb_basic: exiting, ret=0
11542 06:50:34.610253 st requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11543 06:50:34.616707 <8>[ 22.465643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11544 06:50:34.616790
11545 06:50:34.617042 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11547 06:50:34.619854 Test requirement: is_i915_device(fd)
11548 06:50:34.626576 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11549 06:50:34.630361 Test requirement: is_i915_device(fd)
11550 06:50:34.636195 <14>[ 22.486904] [IGT] kms_addfb_basic: executing
11551 06:50:34.639617 No KMS driver or no outputs, pipes: 8, outputs: 0
11552 06:50:34.653651 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 a<14>[ 22.501346] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11553 06:50:34.653734 arch64)
11554 06:50:34.663573 Opened <14>[ 22.509925] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11555 06:50:34.663656 device: /dev/dri/card0
11556 06:50:34.669340 Starting subtest: bad-pi<14>[ 22.523157] [IGT] kms_addfb_basic: exiting, ret=0
11557 06:50:34.672840 tch-65536
11558 06:50:34.676921 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11559 06:50:34.686541 Test requirement n<8>[ 22.534068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11560 06:50:34.686800 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11562 06:50:34.692668 ot met in function igt_require_i915, file ../lib/drmtest.c:720:
11563 06:50:34.696193 Test requirement: is_i915_device(fd)
11564 06:50:34.702826 Test requirement not met in function igt_require_i915, fi<14>[ 22.555791] [IGT] kms_addfb_basic: executing
11565 06:50:34.706088 le ../lib/drmtest.c:720:
11566 06:50:34.709138 Test requirement: is_i915_device(fd)
11567 06:50:34.719586 No KMS driver or no outputs, pipes: 8, outputs: <14>[ 22.570029] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11568 06:50:34.719670 0
11569 06:50:34.729474 IGT-Version: <14>[ 22.578115] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11570 06:50:34.739520 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 a<14>[ 22.590974] [IGT] kms_addfb_basic: exiting, ret=0
11571 06:50:34.739605 arch64)
11572 06:50:34.742833 Opened device: /dev/dri/card0
11573 06:50:34.746045 Starting subtest: invalid-get-prop-any
11574 06:50:34.752579 <8>[ 22.601910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11575 06:50:34.752837 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11577 06:50:34.759681 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11578 06:50:34.766256 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11579 06:50:34.772494 Test requirement: is_<14>[ 22.623461] [IGT] kms_addfb_basic: executing
11580 06:50:34.772575 i915_device(fd)
11581 06:50:34.779019 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11582 06:50:34.789430 Test requirement: is_i915_de<14>[ 22.639543] [IGT] kms_addfb_basic: starting subtest master-rmfb
11583 06:50:34.789514 vice(fd)
11584 06:50:34.799120 No KMS<14>[ 22.646695] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11585 06:50:34.806107 driver or no outputs, pipes: 8,<14>[ 22.657272] [IGT] kms_addfb_basic: exiting, ret=0
11586 06:50:34.806190 outputs: 0
11587 06:50:34.819456 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.<8>[ 22.667407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11588 06:50:34.819539 75-cip14 aarch64)
11589 06:50:34.819812 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11591 06:50:34.822258 Opened device: /dev/dri/card0
11592 06:50:34.825458 Starting subtest: invalid-get-prop
11593 06:50:34.828714 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11594 06:50:34.835931 Test r<14>[ 22.687292] [IGT] kms_addfb_basic: executing
11595 06:50:34.842370 equirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11596 06:50:34.845926 Test requirement: is_i915_device(fd)
11597 06:50:34.855720 Test requirement not met in f<14>[ 22.704946] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11598 06:50:34.865212 unction igt_requ<14>[ 22.712670] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11599 06:50:34.872230 ire_i915, file .<14>[ 22.722496] [IGT] kms_addfb_basic: exiting, ret=0
11600 06:50:34.872312 ./lib/drmtest.c:720:
11601 06:50:34.875361 Test requirement: is_i915_device(fd)
11602 06:50:34.885603 No K<8>[ 22.733140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11603 06:50:34.885862 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11605 06:50:34.888787 MS driver or no outputs, pipes: 8, outputs: 0
11606 06:50:34.895344 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11607 06:50:34.902308 Opened device: /dev/dri/car<14>[ 22.754555] [IGT] kms_addfb_basic: executing
11608 06:50:34.902390 d0
11609 06:50:34.905553 Starting subtest: invalid-set-prop-any
11610 06:50:34.912321 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11611 06:50:34.922047 Test requirement not met in function igt_req<14>[ 22.771992] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11612 06:50:34.925347 uire_i915, file ../lib/drmtest.c:720:
11613 06:50:34.935168 Test requirement: is_i915<14>[ 22.784302] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11614 06:50:34.935251 _device(fd)
11615 06:50:34.942701 Tes<14>[ 22.792497] [IGT] kms_addfb_basic: exiting, ret=98
11616 06:50:34.949094 t requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11617 06:50:34.955592 <8>[ 22.804792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11618 06:50:34.955850 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11620 06:50:34.958613 Test requirement: is_i915_device(fd)
11621 06:50:34.965143 No KMS driver or no outputs, pipes: 8, outputs: 0
11622 06:50:34.968813 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11623 06:50:34.975054 O<14>[ 22.826083] [IGT] kms_addfb_basic: executing
11624 06:50:34.978329 pened device: /dev/dri/card0
11625 06:50:34.982207 Starting subtest: invalid-set-prop
11626 06:50:34.985252 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11627 06:50:34.995226 Test requirement not met in function igt_r<14>[ 22.844720] [IGT] kms_addfb_basic: exiting, ret=77
11628 06:50:34.998889 equire_i915, file ../lib/drmtest.c:720:
11629 06:50:35.009043 Test requirement: is_i9<8>[ 22.855850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11630 06:50:35.009144 15_device(fd)
11631 06:50:35.009397 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11633 06:50:35.015660 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11634 06:50:35.019591 Test requirement: is_i915_device(fd)
11635 06:50:35.025375 No KMS d<14>[ 22.877051] [IGT] kms_addfb_basic: executing
11636 06:50:35.028408 river or no outputs, pipes: 8, outputs: 0
11637 06:50:35.034996 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11638 06:50:35.038196 Opened device: /dev/dri/card0
11639 06:50:35.041524 <14>[ 22.895133] [IGT] kms_addfb_basic: exiting, ret=77
11640 06:50:35.045730 Starting subtest: master-rmfb
11641 06:50:35.055118 [1mSubtest master-rmfb: SUCCESS <8>[ 22.904936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11642 06:50:35.055373 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11644 06:50:35.058318 (0.000s)[0m
11645 06:50:35.065252 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11646 06:50:35.068062 Test requirement: is_i915_device(fd)
11647 06:50:35.074891 Test requ<14>[ 22.926226] [IGT] kms_addfb_basic: executing
11648 06:50:35.078331 irement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11649 06:50:35.082039 Test requirement: is_i915_device(fd)
11650 06:50:35.091938 No KMS driver or no outputs, pip<14>[ 22.943448] [IGT] kms_addfb_basic: exiting, ret=77
11651 06:50:35.092023 es: 8, outputs: 0
11652 06:50:35.105022 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux<8>[ 22.953450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11653 06:50:35.105296 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11655 06:50:35.108078 : 6.1.75-cip14 aarch64)
11656 06:50:35.112067 Opened device: /dev/dri/card0
11657 06:50:35.115189 Starting subtest: addfb25-modifier-no-flag
11658 06:50:35.118688 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11659 06:50:35.124788 <14>[ 22.975674] [IGT] kms_addfb_basic: executing
11660 06:50:35.131785 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11661 06:50:35.134704 Test requirement: is_i915_device(fd)
11662 06:50:35.141620 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11663 06:50:35.144841 Test requirement: is_i915_device(fd)
11664 06:50:35.148399 No KMS driver or no outputs, pipes: 8, outputs: 0
11665 06:50:35.154855 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11666 06:50:35.158145 Opened device: /dev/dri/card0
11667 06:50:35.161489 Starting subtest: addfb25-bad-modifier
11668 06:50:35.171450 (kms_addfb_basic:436) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11669 06:50:35.191329 (kms_addfb_basic:436) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11670 06:50:35.195240 (kms_addfb_basic:436) CRITICAL: error: 0 != -1
11671 06:50:35.195324 Stack trace:
11672 06:50:35.201316 #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11673 06:50:35.201414 #1 [<unknown>+0xb53347e0]
11674 06:50:35.204995 #2 [<unknown>+0xb5336278]
11675 06:50:35.207809 #3 [<unknown>+0xb533167c]
11676 06:50:35.211199 #4 [__libc_start_main+0xe8]
11677 06:50:35.211284 #5 [<unknown>+0xb53316b4]
11678 06:50:35.214322 #6 [<unknown>+0xb53316b4]
11679 06:50:35.217755 Subtest addfb25-bad-modifier failed.
11680 06:50:35.221399 **** DEBUG ****
11681 06:50:35.227693 (kms_addfb_basic:436) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11682 06:50:35.237671 (kms_addfb_basic:436) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11683 06:50:35.254765 (kms_addfb_basic:436) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11684 06:50:35.261327 (kms_addfb_basic:436) CRITICAL: error: 0 != -1
11685 06:50:35.264774 (kms_addfb_basic:436) igt_core-INFO: Stack trace:
11686 06:50:35.271236 (kms_addfb_basic:436) igt_core-INFO: #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11687 06:50:35.277906 (kms_addfb_basic:436) igt_core-INFO: #1 [<unknown>+0xb53347e0]
11688 06:50:35.284710 (kms_addfb_basic:436) igt_core-INFO: #2 [<unknown>+0xb5336278]
11689 06:50:35.287742 (kms_addfb_basic:436) igt_core-INFO: #3 [<unknown>+0xb533167c]
11690 06:50:35.294513 (kms_addfb_basic:436) igt_core-INFO: #4 [__libc_start_main+0xe8]
11691 06:50:35.301099 (kms_addfb_basic:436) igt_core-INFO: #5 [<unknown>+0xb53316b4]
11692 06:50:35.307947 (kms_addfb_basic:436) igt_core-INFO: #6 [<unknown>+0xb53316b4]
11693 06:50:35.308030 **** END ****
11694 06:50:35.311223 [1mSubtest addfb25-bad-modifier: FAIL (0.005s)[0m
11695 06:50:35.321224 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11696 06:50:35.324532 Test requirement: is_i915_device(fd)
11697 06:50:35.331430 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11698 06:50:35.335181 Test requirement: is_i915_device(fd)
11699 06:50:35.338012 No KMS driver or no outputs, pipes: 8, outputs: 0
11700 06:50:35.344466 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11701 06:50:35.347684 Opened device: /dev/dri/card0
11702 06:50:35.354346 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11703 06:50:35.357359 Test requirement: is_i915_device(fd)
11704 06:50:35.363987 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11705 06:50:35.371032 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11706 06:50:35.374051 Test requirement: is_i915_device(fd)
11707 06:50:35.377339 No KMS driver or no outputs, pipes: 8, outputs: 0
11708 06:50:35.384141 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11709 06:50:35.387486 Opened device: /dev/dri/card0
11710 06:50:35.393977 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11711 06:50:35.397159 Test requirement: is_i915_device(fd)
11712 06:50:35.401226 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11713 06:50:35.410556 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11714 06:50:35.414690 Test requirement: is_i915_device(fd)
11715 06:50:35.417892 No KMS driver or no outputs, pipes: 8, outputs: 0
11716 06:50:35.424240 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11717 06:50:35.427610 Opened device: /dev/dri/card0
11718 06:50:35.433842 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11719 06:50:35.437036 Test requirement: is_i915_device(fd)
11720 06:50:35.440875 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11721 06:50:35.450035 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11722 06:50:35.453626 Test requirement: is_i915_device(fd)
11723 06:50:35.456882 No KMS driver or no outputs, pipes: 8, outputs: 0
11724 06:50:35.463937 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11725 06:50:35.466988 Opened device: /dev/dri/card0
11726 06:50:35.476703 Test requirement not met in function igt_require_i915, file ../lib/dr<14>[ 23.327994] [IGT] kms_addfb_basic: exiting, ret=77
11727 06:50:35.476786 mtest.c:720:
11728 06:50:35.480306 Test requirement: is_i915_device(fd)
11729 06:50:35.489760 Test require<8>[ 23.339501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11730 06:50:35.490026 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11732 06:50:35.496479 ment not met in function igt_require_i915, file ../lib/drmtest.c:720:
11733 06:50:35.500268 Test requirement: is_i915_device(fd)
11734 06:50:35.506757 [1mSubtest basic-x-tiled-legacy: S<14>[ 23.359818] [IGT] kms_addfb_basic: executing
11735 06:50:35.509729 KIP (0.000s)[0m
11736 06:50:35.513136 No KMS driver or no outputs, pipes: 8, outputs: 0
11737 06:50:35.520104 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11738 06:50:35.526850 Opened device: /dev/d<14>[ 23.377264] [IGT] kms_addfb_basic: exiting, ret=77
11739 06:50:35.526933 ri/card0
11740 06:50:35.540180 Test requirement not met in function igt_require_i915,<8>[ 23.388259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11741 06:50:35.540436 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11743 06:50:35.543026 file ../lib/drmtest.c:720:
11744 06:50:35.546303 Test requirement: is_i915_device(fd)
11745 06:50:35.556711 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:<14>[ 23.409402] [IGT] kms_addfb_basic: executing
11746 06:50:35.556796 720:
11747 06:50:35.560205 Test requirement: is_i915_device(fd)
11748 06:50:35.566773 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11749 06:50:35.569556 No KMS driver or no outputs, pipes: 8, outputs: 0
11750 06:50:35.576182 IGT-Ver<14>[ 23.427188] [IGT] kms_addfb_basic: exiting, ret=77
11751 06:50:35.582699 sion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11752 06:50:35.589349 O<8>[ 23.438450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11753 06:50:35.589606 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11755 06:50:35.592831 pened device: /dev/dri/card0
11756 06:50:35.599695 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11757 06:50:35.606040 Test requirement: is_i915_devic<14>[ 23.459096] [IGT] kms_addfb_basic: executing
11758 06:50:35.606125 e(fd)
11759 06:50:35.616385 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11760 06:50:35.619646 Test requirement: is_i915_device(fd)
11761 06:50:35.622783 [1mSubtest tile<14>[ 23.476576] [IGT] kms_addfb_basic: exiting, ret=77
11762 06:50:35.626107 -pitch-mismatch: SKIP (0.000s)[0m
11763 06:50:35.636493 No KMS driver or no outputs,<8>[ 23.486729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11764 06:50:35.636750 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11766 06:50:35.639631 pipes: 8, outputs: 0
11767 06:50:35.646036 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11768 06:50:35.649198 Opened device: /dev/dri/card0
11769 06:50:35.655795 Test requirement not<14>[ 23.506995] [IGT] kms_addfb_basic: executing
11770 06:50:35.659085 met in function igt_require_i915, file ../lib/drmtest.c:720:
11771 06:50:35.662543 Test requirement: is_i915_device(fd)
11772 06:50:35.672403 Test requirement not met in function igt_require_i915, file<14>[ 23.525007] [IGT] kms_addfb_basic: exiting, ret=77
11773 06:50:35.675791 ../lib/drmtest.c:720:
11774 06:50:35.679148 Test requirement: is_i915_device(fd)
11775 06:50:35.685753 [<8>[ 23.536113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11776 06:50:35.686011 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11778 06:50:35.689089 1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11779 06:50:35.695772 No KMS driver or no outputs, pipes: 8, outputs: 0
11780 06:50:35.702300 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Li<14>[ 23.555911] [IGT] kms_addfb_basic: executing
11781 06:50:35.705751 nux: 6.1.75-cip14 aarch64)
11782 06:50:35.708643 Opened device: /dev/dri/card0
11783 06:50:35.715316 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11784 06:50:35.722663 Test requirement: <14>[ 23.573507] [IGT] kms_addfb_basic: exiting, ret=77
11785 06:50:35.725464 is_i915_device(fd)
11786 06:50:35.735294 Test requirement not met in function igt_req<8>[ 23.584794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11787 06:50:35.735550 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11789 06:50:35.738596 uire_i915, file ../lib/drmtest.c:720:
11790 06:50:35.742308 Test requirement: is_i915_device(fd)
11791 06:50:35.745181 No KMS driver or no outputs, pipes: 8, outputs: 0
11792 06:50:35.751783 [1mSubtest size<14>[ 23.604380] [IGT] kms_addfb_basic: executing
11793 06:50:35.755102 -max: SKIP (0.000s)[0m
11794 06:50:35.758468 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11795 06:50:35.762084 Opened device: /dev/dri/card0
11796 06:50:35.772344 Test requirement not met in functi<14>[ 23.621964] [IGT] kms_addfb_basic: exiting, ret=77
11797 06:50:35.775067 on igt_require_i915, file ../lib/drmtest.c:720:
11798 06:50:35.781793 Test requiremen<8>[ 23.633051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11799 06:50:35.782048 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11801 06:50:35.785180 t: is_i915_device(fd)
11802 06:50:35.791835 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11803 06:50:35.795982 Test requirement: is_i915_device(fd)
11804 06:50:35.801909 <14>[ 23.652566] [IGT] kms_addfb_basic: executing
11805 06:50:35.804849 No KMS driver or no outputs, pipes: 8, outputs: 0
11806 06:50:35.808201 [1mSubtest too-wide: SKIP (0.000s)[0m
11807 06:50:35.818349 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.7<14>[ 23.670359] [IGT] kms_addfb_basic: exiting, ret=77
11808 06:50:35.818454 5-cip14 aarch64)
11809 06:50:35.821620 Opened device: /dev/dri/card0
11810 06:50:35.832068 Test requiremen<8>[ 23.679959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11811 06:50:35.832322 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11813 06:50:35.835103 t not met in function igt_require_i915, file ../lib/drmtest.c:720:
11814 06:50:35.838705 Test requirement: is_i915_device(fd)
11815 06:50:35.848410 Test requirement not met in function i<14>[ 23.700000] [IGT] kms_addfb_basic: executing
11816 06:50:35.851835 gt_require_i915, file ../lib/drmtest.c:720:
11817 06:50:35.854972 Test requirement: is_i915_device(fd)
11818 06:50:35.858270 No KMS driver or no outputs, pipes: 8, outputs: 0
11819 06:50:35.868612 [1mSubtest too-high: SKIP<14>[ 23.717947] [IGT] kms_addfb_basic: exiting, ret=77
11820 06:50:35.868695 (0.000s)[0m
11821 06:50:35.878636 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.<8>[ 23.729153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11822 06:50:35.878891 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11824 06:50:35.881849 1.75-cip14 aarch64)
11825 06:50:35.885355 Opened device: /dev/dri/card0
11826 06:50:35.891530 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11827 06:50:35.894706 Test requ<14>[ 23.748706] [IGT] kms_addfb_basic: executing
11828 06:50:35.898541 irement: is_i915_device(fd)
11829 06:50:35.904857 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11830 06:50:35.909052 Test requirement: is_i915_device(fd)
11831 06:50:35.915135 No KMS dri<14>[ 23.766524] [IGT] kms_addfb_basic: exiting, ret=77
11832 06:50:35.918283 ver or no outputs, pipes: 8, outputs: 0
11833 06:50:35.927955 [1mSubtest bo-too-smal<8>[ 23.777572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11834 06:50:35.928209 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11836 06:50:35.931216 l: SKIP (0.000s)[0m
11837 06:50:35.937726 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11838 06:50:35.941665 Opened device: /dev/dri/card0
11839 06:50:35.947744 Test requirement not <14>[ 23.799163] [IGT] kms_addfb_basic: executing
11840 06:50:35.950985 met in function igt_require_i915, file ../lib/drmtest.c:720:
11841 06:50:35.954654 Test requirement: is_i915_device(fd)
11842 06:50:35.964290 Test requirement not met in function igt_req<14>[ 23.816460] [IGT] kms_addfb_basic: exiting, ret=77
11843 06:50:35.968239 uire_i915, file ../lib/drmtest.c:720:
11844 06:50:35.977514 Test requirement: is_i915<8>[ 23.826342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11845 06:50:35.977597 _device(fd)
11846 06:50:35.977834 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11848 06:50:35.984540 No KMS driver or no outputs, pipes: 8, outputs: 0
11849 06:50:35.987548 [1mSubtest small-bo: SKIP (0.000s)[0m
11850 06:50:35.994379 IGT-Version: 1.27.1-g621c2d3 (aarch64) <14>[ 23.846987] [IGT] kms_addfb_basic: executing
11851 06:50:35.997757 (Linux: 6.1.75-cip14 aarch64)
11852 06:50:36.001001 Opened device: /dev/dri/card0
11853 06:50:36.007905 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11854 06:50:36.011781 <14>[ 23.864727] [IGT] kms_addfb_basic: exiting, ret=77
11855 06:50:36.011862
11856 06:50:36.014631 Test requirement: is_i915_device(fd)
11857 06:50:36.024536 Test requirement not met <8>[ 23.875050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11858 06:50:36.024791 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11860 06:50:36.030941 in function igt_require_i915, file ../lib/drmtest.c:720:
11861 06:50:36.034655 Test requirement: is_i915_device(fd)
11862 06:50:36.044709 No KMS driver or no outputs, pipes: 8, outputs: <14>[ 23.895715] [IGT] kms_addfb_basic: executing
11863 06:50:36.044792 0
11864 06:50:36.047734 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11865 06:50:36.054378 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11866 06:50:36.061060 Opened devic<14>[ 23.913233] [IGT] kms_addfb_basic: exiting, ret=77
11867 06:50:36.064321 e: /dev/dri/card0
11868 06:50:36.074285 Test requirement not met in function igt_requ<8>[ 23.923068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11869 06:50:36.074555 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11871 06:50:36.077515 ire_i915, file ../lib/drmtest.c:720:
11872 06:50:36.080767 Test requirement: is_i915_device(fd)
11873 06:50:36.091287 Test requirement not met in function igt_require_i915, file ../lib/d<14>[ 23.944283] [IGT] kms_addfb_basic: executing
11874 06:50:36.093940 rmtest.c:720:
11875 06:50:36.097581 Test requirement: is_i915_device(fd)
11876 06:50:36.101129 No KMS driver or no outputs, pipes: 8, outputs: 0
11877 06:50:36.111236 [1mSubtest addfb25-y-tiled-legacy: SKIP<14>[ 23.962116] [IGT] kms_addfb_basic: exiting, ret=77
11878 06:50:36.111319 (0.000s)[0m
11879 06:50:36.124386 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.<8>[ 23.972110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11880 06:50:36.124469 1.75-cip14 aarch64)
11881 06:50:36.124708 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11883 06:50:36.130913 Opened devi<8>[ 23.981550] <LAVA_SIGNAL_TESTSET STOP>
11884 06:50:36.130994 ce: /dev/dri/card0
11885 06:50:36.131228 Received signal: <TESTSET> STOP
11886 06:50:36.131293 Closing test_set kms_addfb_basic
11887 06:50:36.137282 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11888 06:50:36.141112 Test requirement: is_i915_device(fd)
11889 06:50:36.150544 Test requirement not met in functio<8>[ 24.002014] <LAVA_SIGNAL_TESTSET START kms_atomic>
11890 06:50:36.150797 Received signal: <TESTSET> START kms_atomic
11891 06:50:36.150865 Starting test_set kms_atomic
11892 06:50:36.154196 n igt_require_i915, file ../lib/drmtest.c:720:
11893 06:50:36.157079 Test requirement: is_i915_device(fd)
11894 06:50:36.160479 No KMS driver or no outputs, pipes: 8, outputs: 0
11895 06:50:36.167648 [1mSub<14>[ 24.019463] [IGT] kms_atomic: executing
11896 06:50:36.174636 test addfb25-yf-<14>[ 24.024581] [IGT] kms_atomic: exiting, ret=77
11897 06:50:36.177959 tiled-legacy: SKIP (0.000s)[0m
11898 06:50:36.187225 IGT-Version: 1.27.1-g621c2d3 (a<8>[ 24.035209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11899 06:50:36.187512 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11901 06:50:36.190536 arch64) (Linux: 6.1.75-cip14 aarch64)
11902 06:50:36.190616 Opened device: /dev/dri/card0
11903 06:50:36.204311 Test requirement not met in function igt_require_i915, file ../lib/drmtest<14>[ 24.055412] [IGT] kms_atomic: executing
11904 06:50:36.204394 .c:720:
11905 06:50:36.207230 Test re<14>[ 24.060725] [IGT] kms_atomic: exiting, ret=77
11906 06:50:36.210803 quirement: is_i915_device(fd)
11907 06:50:36.221049 Test requirement not met in funct<8>[ 24.071187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11908 06:50:36.221305 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11910 06:50:36.227530 ion igt_require_i915, file ../lib/drmtest.c:720:
11911 06:50:36.230739 Test requirement: is_i915_device(fd)
11912 06:50:36.234217 No KMS driver or no outputs, pipes: 8, outputs: 0
11913 06:50:36.240493 [1mS<14>[ 24.091379] [IGT] kms_atomic: executing
11914 06:50:36.243757 ubtest addfb25-y<14>[ 24.097115] [IGT] kms_atomic: exiting, ret=77
11915 06:50:36.247595 -tiled-small-legacy: SKIP (0.000s)[0m
11916 06:50:36.260322 IGT-Version: 1.27.1-g621<8>[ 24.107492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11917 06:50:36.260591 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11919 06:50:36.263728 c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11920 06:50:36.267141 Opened device: /dev/dri/card0
11921 06:50:36.277282 Test requirement not met in function igt_require_i915, file ../lib/<14>[ 24.128984] [IGT] kms_atomic: executing
11922 06:50:36.277365 drmtest.c:720:
11923 06:50:36.283575 <14>[ 24.134403] [IGT] kms_atomic: exiting, ret=77
11924 06:50:36.286729 Test requirement: is_i915_device(fd)
11925 06:50:36.296687 Test requirement not met i<8>[ 24.144771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11926 06:50:36.296974 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11928 06:50:36.300552 n function igt_require_i915, file ../lib/drmtest.c:720:
11929 06:50:36.303900 Test requirement: is_i915_device(fd)
11930 06:50:36.306845 No KMS driver or no outputs, pipes: 8, outputs: 0
11931 06:50:36.313848 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11932 06:50:36.320250 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11933 06:50:36.320332 Opened device: /dev/dri/card0
11934 06:50:36.326951 No KMS driver or no outputs, pipes: 8, outputs: 0
11935 06:50:36.330418 [1mSu<14>[ 24.182736] [IGT] kms_atomic: executing
11936 06:50:36.337158 btest plane-over<14>[ 24.188599] [IGT] kms_atomic: exiting, ret=77
11937 06:50:36.340303 lay-legacy: SKIP (0.000s)[0m
11938 06:50:36.350924 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.<8>[ 24.199803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11939 06:50:36.351181 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11941 06:50:36.353440 1.75-cip14 aarch64)
11942 06:50:36.353522 Opened device: /dev/dri/card0
11943 06:50:36.360533 No KMS driver or no outputs, pipes: 8, outputs: 0
11944 06:50:36.366584 [1mSubtest plane-primary-legacy: SKIP (0<14>[ 24.220029] [IGT] kms_atomic: executing
11945 06:50:36.366666 .000s)[0m
11946 06:50:36.373749 IGT-<14>[ 24.224897] [IGT] kms_atomic: exiting, ret=77
11947 06:50:36.386765 Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)<8>[ 24.235287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11948 06:50:36.386880
11949 06:50:36.387117 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11951 06:50:36.390012 Opened device: /dev/dri/card0
11952 06:50:36.393340 No KMS driver or no outputs, pipes: 8, outputs: 0
11953 06:50:36.403103 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s<14>[ 24.255890] [IGT] kms_atomic: executing
11954 06:50:36.403186 )[0m
11955 06:50:36.409869 IGT-Versi<14>[ 24.260969] [IGT] kms_atomic: exiting, ret=77
11956 06:50:36.413264 on: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11957 06:50:36.423381 Ope<8>[ 24.271294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11958 06:50:36.423464 ned device: /dev/dri/card0
11959 06:50:36.423700 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11961 06:50:36.430109 No KMS driver or no outputs, pipes: 8, outputs: 0
11962 06:50:36.433287 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11963 06:50:36.440094 IGT-Version:<14>[ 24.292020] [IGT] kms_atomic: executing
11964 06:50:36.446719 1.27.1-g621c2d3<14>[ 24.297123] [IGT] kms_atomic: exiting, ret=77
11965 06:50:36.450792 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11966 06:50:36.459837 Opened device: /dev/dr<8>[ 24.307428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11967 06:50:36.459921 i/card0
11968 06:50:36.460157 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11970 06:50:36.463401 No KMS driver or no outputs, pipes: 8, outputs: 0
11971 06:50:36.466534 [1mSubtest test-only: SKIP (0.000s)[0m
11972 06:50:36.476270 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Li<14>[ 24.328596] [IGT] kms_atomic: executing
11973 06:50:36.482980 nux: 6.1.75-cip1<14>[ 24.333993] [IGT] kms_atomic: exiting, ret=77
11974 06:50:36.483065 4 aarch64)
11975 06:50:36.486129 Opened device: /dev/dri/card0
11976 06:50:36.496158 No KMS driver or no o<8>[ 24.344092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11977 06:50:36.496252 utputs, pipes: 8, outputs: 0
11978 06:50:36.496494 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11980 06:50:36.502778 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11981 06:50:36.509930 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11982 06:50:36.513384 Opened d<14>[ 24.365431] [IGT] kms_atomic: executing
11983 06:50:36.519758 evice: /dev/dri/<14>[ 24.371234] [IGT] kms_atomic: exiting, ret=77
11984 06:50:36.519878 card0
11985 06:50:36.523080 No KMS driver or no outputs, pipes: 8, outputs: 0
11986 06:50:36.532951 [1mSu<8>[ 24.381836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11987 06:50:36.533234 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11989 06:50:36.535966 btest plane-invalid-params: SKIP (0.000s)[0m
11990 06:50:36.543250 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11991 06:50:36.549453 Opened device: /dev/dri/car<14>[ 24.402669] [IGT] kms_atomic: executing
11992 06:50:36.549534 d0
11993 06:50:36.556080 No KMS drive<14>[ 24.407759] [IGT] kms_atomic: exiting, ret=77
11994 06:50:36.559311 r or no outputs, pipes: 8, outputs: 0
11995 06:50:36.569384 [1mSubtest plane-invalid<8>[ 24.417964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11996 06:50:36.569654 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11998 06:50:36.572324 -params-fence: SKIP (0.000s)[0m
11999 06:50:36.579430 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12000 06:50:36.582743 Opened device: /dev/dri/card0
12001 06:50:36.585532 No KMS dr<14>[ 24.439059] [IGT] kms_atomic: executing
12002 06:50:36.592690 iver or no outpu<14>[ 24.444080] [IGT] kms_atomic: exiting, ret=77
12003 06:50:36.595520 ts, pipes: 8, outputs: 0
12004 06:50:36.606043 [1mSubtest crtc-invalid-params: SKIP <8>[ 24.454224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
12005 06:50:36.606161 (0.000s)[0m
12006 06:50:36.606432 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
12008 06:50:36.612606 IGT-Version: 1.27.<8>[ 24.464319] <LAVA_SIGNAL_TESTSET STOP>
12009 06:50:36.612861 Received signal: <TESTSET> STOP
12010 06:50:36.612930 Closing test_set kms_atomic
12011 06:50:36.616301 1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12012 06:50:36.619298 Opened device: /dev/dri/card0
12013 06:50:36.622727 No KMS driver or no outputs, pipes: 8, outputs: 0
12014 06:50:36.632184 [1mSubtest crtc-invalid-params-fence: SKI<8>[ 24.484707] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12015 06:50:36.632458 Received signal: <TESTSET> START kms_flip_event_leak
12016 06:50:36.632531 Starting test_set kms_flip_event_leak
12017 06:50:36.635451 P (0.000s)[0m
12018 06:50:36.642071 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12019 06:50:36.642156 Opened device: /dev/dri/card0
12020 06:50:36.652049 No KMS driver or no outputs, pipes: 8, outp<14>[ 24.504185] [IGT] kms_flip_event_leak: executing
12021 06:50:36.652150 uts: 0
12022 06:50:36.659198 [1mSubt<14>[ 24.510354] [IGT] kms_flip_event_leak: exiting, ret=77
12023 06:50:36.662342 est atomic-invalid-params: SKIP (0.000s)[0m
12024 06:50:36.672353 IGT-Version: 1.27.<8>[ 24.521407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12025 06:50:36.672620 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12027 06:50:36.678827 1-g621c2d3 (aarch64) (Linux: 6.1<8>[ 24.530217] <LAVA_SIGNAL_TESTSET STOP>
12028 06:50:36.678917 .75-cip14 aarch64)
12029 06:50:36.679157 Received signal: <TESTSET> STOP
12030 06:50:36.679231 Closing test_set kms_flip_event_leak
12031 06:50:36.682060 Opened device: /dev/dri/card0
12032 06:50:36.685644 No KMS driver or no outputs, pipes: 8, outputs: 0
12033 06:50:36.692128 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
12034 06:50:36.699212 IGT-Version: 1.27.1-g6<8>[ 24.550376] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12035 06:50:36.699488 Received signal: <TESTSET> START kms_prop_blob
12036 06:50:36.699565 Starting test_set kms_prop_blob
12037 06:50:36.702314 21c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12038 06:50:36.705213 Opened device: /dev/dri/card0
12039 06:50:36.708437 No KMS driver or no outputs, pipes: 8, outputs: 0
12040 06:50:36.715100 [1mSubtest ba<14>[ 24.568468] [IGT] kms_prop_blob: executing
12041 06:50:36.722101 sic: SKIP (0.000<14>[ 24.573590] [IGT] kms_prop_blob: starting subtest basic
12042 06:50:36.722195 s)[0m
12043 06:50:36.728646 IGT-Vers<14>[ 24.580231] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12044 06:50:36.735407 ion: 1.27.1-g621<14>[ 24.588026] [IGT] kms_prop_blob: exiting, ret=0
12045 06:50:36.741879 c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12046 06:50:36.749269 Opened device: /de<8>[ 24.598831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12047 06:50:36.749374 v/dri/card0
12048 06:50:36.749625 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12050 06:50:36.752104 Starting subtest: basic
12051 06:50:36.755112 [1mSubtest basic: SUCCESS (0.000s)[0m
12052 06:50:36.765388 <14>[ 24.617906] [IGT] kms_prop_blob: executing
12053 06:50:36.772140 IGT-Version: 1.2<14>[ 24.622773] [IGT] kms_prop_blob: starting subtest blob-prop-core
12054 06:50:36.782664 7.1-g621c2d3 (aa<14>[ 24.630521] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12055 06:50:36.788546 rch64) (Linux: 6<14>[ 24.638901] [IGT] kms_prop_blob: exiting, ret=0
12056 06:50:36.788657 .1.75-cip14 aarch64)
12057 06:50:36.792145 Opened device: /dev/dri/card0
12058 06:50:36.798679 Starting su<8>[ 24.649643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12059 06:50:36.798970 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12061 06:50:36.802312 btest: blob-prop-core
12062 06:50:36.805412 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12063 06:50:36.817799 <14>[ 24.670145] [IGT] kms_prop_blob: executing
12064 06:50:36.824104 IGT-Version: 1.2<14>[ 24.674894] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12065 06:50:36.834391 7.1-g621c2d3 (aa<14>[ 24.682947] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12066 06:50:36.840727 rch64) (Linux: 6<14>[ 24.691801] [IGT] kms_prop_blob: exiting, ret=0
12067 06:50:36.840825 .1.75-cip14 aarch64)
12068 06:50:36.844468 Opened device: /dev/dri/card0
12069 06:50:36.854142 Starting su<8>[ 24.702560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12070 06:50:36.854424 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12072 06:50:36.857816 btest: blob-prop-validate
12073 06:50:36.860950 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12074 06:50:36.870933 <14>[ 24.723215] [IGT] kms_prop_blob: executing
12075 06:50:36.877255 IGT-Version: 1.2<14>[ 24.727968] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12076 06:50:36.887127 7.1-g621c2d3 (aa<14>[ 24.735987] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12077 06:50:36.894050 rch64) (Linux: 6<14>[ 24.744838] [IGT] kms_prop_blob: exiting, ret=0
12078 06:50:36.894161 .1.75-cip14 aarch64)
12079 06:50:36.897131 Opened device: /dev/dri/card0
12080 06:50:36.907225 Starting su<8>[ 24.755273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12081 06:50:36.907534 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12083 06:50:36.910741 btest: blob-prop-lifetime
12084 06:50:36.913953 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12085 06:50:36.923890 <14>[ 24.776367] [IGT] kms_prop_blob: executing
12086 06:50:36.930918 IGT-Version: 1.2<14>[ 24.781125] [IGT] kms_prop_blob: starting subtest blob-multiple
12087 06:50:36.940814 7.1-g621c2d3 (aa<14>[ 24.788750] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12088 06:50:36.946974 rch64) (Linux: 6<14>[ 24.797240] [IGT] kms_prop_blob: exiting, ret=0
12089 06:50:36.947070 .1.75-cip14 aarch64)
12090 06:50:36.950229 Opened device: /dev/dri/card0
12091 06:50:36.957090 Starting su<8>[ 24.807690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12092 06:50:36.957386 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12094 06:50:36.960816 btest: blob-multiple
12095 06:50:36.963530 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12096 06:50:36.975278 <14>[ 24.827964] [IGT] kms_prop_blob: executing
12097 06:50:36.981903 IGT-Version: 1.2<14>[ 24.832718] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12098 06:50:36.991924 7.1-g621c2d3 (aa<14>[ 24.840875] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12099 06:50:36.998772 rch64) (Linux: 6<14>[ 24.850035] [IGT] kms_prop_blob: exiting, ret=0
12100 06:50:37.002266 .1.75-cip14 aarch64)
12101 06:50:37.002369 Opened device: /dev/dri/card0
12102 06:50:37.011874 Starting su<8>[ 24.860630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12103 06:50:37.012163 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12105 06:50:37.015393 btest: invalid-get-prop-any
12106 06:50:37.019337 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12107 06:50:37.028838 <14>[ 24.881155] [IGT] kms_prop_blob: executing
12108 06:50:37.035016 IGT-Version: 1.2<14>[ 24.885981] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12109 06:50:37.045533 7.1-g621c2d3 (aa<14>[ 24.893853] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12110 06:50:37.051873 rch64) (Linux: 6<14>[ 24.902510] [IGT] kms_prop_blob: exiting, ret=0
12111 06:50:37.051989 .1.75-cip14 aarch64)
12112 06:50:37.055330 Opened device: /dev/dri/card0
12113 06:50:37.065241 Starting su<8>[ 24.913337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12114 06:50:37.065361 btest: invalid-get-prop
12115 06:50:37.065608 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12117 06:50:37.071608 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12118 06:50:37.081054 <14>[ 24.933767] [IGT] kms_prop_blob: executing
12119 06:50:37.088216 IGT-Version: 1.2<14>[ 24.938691] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12120 06:50:37.097873 7.1-g621c2d3 (aa<14>[ 24.946712] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12121 06:50:37.104591 rch64) (Linux: 6<14>[ 24.955784] [IGT] kms_prop_blob: exiting, ret=0
12122 06:50:37.107958 .1.75-cip14 aarch64)
12123 06:50:37.108056 Opened device: /dev/dri/card0
12124 06:50:37.118154 Starting su<8>[ 24.966345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12125 06:50:37.118469 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12127 06:50:37.122514 btest: invalid-set-prop-any
12128 06:50:37.124575 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12129 06:50:37.134646 <14>[ 24.987194] [IGT] kms_prop_blob: executing
12130 06:50:37.141593 IGT-Version: 1.2<14>[ 24.991988] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12131 06:50:37.151487 7.1-g621c2d3 (aa<14>[ 24.999773] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12132 06:50:37.158389 rch64) (Linux: 6<14>[ 25.008489] [IGT] kms_prop_blob: exiting, ret=0
12133 06:50:37.158532 .1.75-cip14 aarch64)
12134 06:50:37.161644 Opened device: /dev/dri/card0
12135 06:50:37.171524 Starting su<8>[ 25.019055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12136 06:50:37.171634 btest: invalid-set-prop
12137 06:50:37.171880 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12139 06:50:37.177955 [1mSub<8>[ 25.029157] <LAVA_SIGNAL_TESTSET STOP>
12140 06:50:37.178217 Received signal: <TESTSET> STOP
12141 06:50:37.178286 Closing test_set kms_prop_blob
12142 06:50:37.181319 test invalid-set-prop: SUCCESS (0.000s)[0m
12143 06:50:37.197247 <8>[ 25.049834] <LAVA_SIGNAL_TESTSET START kms_setmode>
12144 06:50:37.197595 Received signal: <TESTSET> START kms_setmode
12145 06:50:37.197708 Starting test_set kms_setmode
12146 06:50:37.217574 <14>[ 25.070360] [IGT] kms_setmode: executing
12147 06:50:37.224488 IGT-Version: 1.2<14>[ 25.075002] [IGT] kms_setmode: starting subtest basic
12148 06:50:37.231216 7.1-g621c2d3 (aa<14>[ 25.081634] [IGT] kms_setmode: finished subtest basic, SKIP
12149 06:50:37.237951 rch64) (Linux: 6<14>[ 25.089101] [IGT] kms_setmode: exiting, ret=77
12150 06:50:37.238060 .1.75-cip14 aarch64)
12151 06:50:37.241709 Opened device: /dev/dri/card0
12152 06:50:37.249719 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12154 06:50:37.251631 Starting su<8>[ 25.099486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12155 06:50:37.251735 btest: basic
12156 06:50:37.254145 No dynamic tests executed.
12157 06:50:37.257503 [1mSubtest basic: SKIP (0.000s)[0m
12158 06:50:37.266658 <14>[ 25.119433] [IGT] kms_setmode: executing
12159 06:50:37.273852 IGT-Version: 1.2<14>[ 25.124075] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12160 06:50:37.284150 7.1-g621c2d3 (aa<14>[ 25.132253] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12161 06:50:37.290264 rch64) (Linux: 6<14>[ 25.141152] [IGT] kms_setmode: exiting, ret=77
12162 06:50:37.290384 .1.75-cip14 aarch64)
12163 06:50:37.293618 Opened device: /dev/dri/card0
12164 06:50:37.303908 Starting su<8>[ 25.151649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12165 06:50:37.304230 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12167 06:50:37.307572 btest: basic-clone-single-crtc
12168 06:50:37.307666 No dynamic tests executed.
12169 06:50:37.313945 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12170 06:50:37.321082 <14>[ 25.173657] [IGT] kms_setmode: executing
12171 06:50:37.328219 IGT-Version: 1.2<14>[ 25.178303] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12172 06:50:37.337585 7.1-g621c2d3 (aa<14>[ 25.186715] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12173 06:50:37.344456 rch64) (Linux: 6<14>[ 25.195746] [IGT] kms_setmode: exiting, ret=77
12174 06:50:37.347692 .1.75-cip14 aarch64)
12175 06:50:37.347784 Opened device: /dev/dri/card0
12176 06:50:37.357847 Starting su<8>[ 25.206256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12177 06:50:37.358154 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12179 06:50:37.361122 btest: invalid-clone-single-crtc
12180 06:50:37.364303 No dynamic tests executed.
12181 06:50:37.367592 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12182 06:50:37.375122 <14>[ 25.227835] [IGT] kms_setmode: executing
12183 06:50:37.381936 IGT-Version: 1.2<14>[ 25.232453] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12184 06:50:37.391730 7.1-g621c2d3 (aa<14>[ 25.241104] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12185 06:50:37.398300 rch64) (Linux: 6<14>[ 25.250468] [IGT] kms_setmode: exiting, ret=77
12186 06:50:37.402055 .1.75-cip14 aarch64)
12187 06:50:37.405000 Opened device: /dev/dri/card0
12188 06:50:37.411602 Starting su<8>[ 25.260802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12189 06:50:37.411894 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12191 06:50:37.415000 btest: invalid-clone-exclusive-crtc
12192 06:50:37.418283 No dynamic tests executed.
12193 06:50:37.425341 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12194 06:50:37.428036 <14>[ 25.282237] [IGT] kms_setmode: executing
12195 06:50:37.438247 IGT-Version: 1.2<14>[ 25.287058] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12196 06:50:37.444824 7.1-g621c2d3 (aa<14>[ 25.295002] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12197 06:50:37.452504 rch64) (Linux: 6<14>[ 25.303637] [IGT] kms_setmode: exiting, ret=77
12198 06:50:37.455212 .1.75-cip14 aarch64)
12199 06:50:37.458178 Opened device: /dev/dri/card0
12200 06:50:37.464822 Starting su<8>[ 25.314597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12201 06:50:37.465106 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12203 06:50:37.468480 btest: clone-exclusive-crtc
12204 06:50:37.471732 No dynamic tests executed.
12205 06:50:37.474346 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12206 06:50:37.482617 <14>[ 25.335390] [IGT] kms_setmode: executing
12207 06:50:37.492345 IGT-Version: 1.2<14>[ 25.340023] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12208 06:50:37.502452 7.1-g621c2d3 (aa<14>[ 25.349159] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12209 06:50:37.505913 rch64) (Linux: 6<14>[ 25.359009] [IGT] kms_setmode: exiting, ret=77
12210 06:50:37.509599 .1.75-cip14 aarch64)
12211 06:50:37.512722 Opened device: /dev/dri/card0
12212 06:50:37.522172 Starting su<8>[ 25.369601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12213 06:50:37.522426 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12215 06:50:37.525935 btest: invalid-c<8>[ 25.380960] <LAVA_SIGNAL_TESTSET STOP>
12216 06:50:37.526193 Received signal: <TESTSET> STOP
12217 06:50:37.526262 Closing test_set kms_setmode
12218 06:50:37.528836 lone-single-crtc-stealing
12219 06:50:37.532444 No dynamic tests executed.
12220 06:50:37.539222 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12221 06:50:37.547468 <8>[ 25.400165] <LAVA_SIGNAL_TESTSET START kms_vblank>
12222 06:50:37.547764 Received signal: <TESTSET> START kms_vblank
12223 06:50:37.547841 Starting test_set kms_vblank
12224 06:50:37.565092 <14>[ 25.417934] [IGT] kms_vblank: executing
12225 06:50:37.572217 IGT-Version: 1.2<14>[ 25.422875] [IGT] kms_vblank: exiting, ret=77
12226 06:50:37.575416 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12227 06:50:37.582100 Opened dev<8>[ 25.433026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12228 06:50:37.582387 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12230 06:50:37.585271 ice: /dev/dri/card0
12231 06:50:37.588603 No KMS driver or no outputs, pipes: 8, outputs: 0
12232 06:50:37.591805 [1mSubtest invalid: SKIP (0.000s)[0m
12233 06:50:37.600805 <14>[ 25.452987] [IGT] kms_vblank: executing
12234 06:50:37.606778 IGT-Version: 1.2<14>[ 25.457715] [IGT] kms_vblank: exiting, ret=77
12235 06:50:37.610228 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12236 06:50:37.616934 Opened dev<8>[ 25.467904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12237 06:50:37.617223 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12239 06:50:37.620701 ice: /dev/dri/card0
12240 06:50:37.623569 No KMS driver or no outputs, pipes: 8, outputs: 0
12241 06:50:37.626809 [1mSubtest crtc-id: SKIP (0.000s)[0m
12242 06:50:37.635225 <14>[ 25.487480] [IGT] kms_vblank: executing
12243 06:50:37.641320 IGT-Version: 1.2<14>[ 25.492266] [IGT] kms_vblank: exiting, ret=77
12244 06:50:37.644509 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12245 06:50:37.654856 Opened dev<8>[ 25.502743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12246 06:50:37.654980 ice: /dev/dri/card0
12247 06:50:37.655221 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12249 06:50:37.661556 No KMS driver or no outputs, pipes: 8, outputs: 0
12250 06:50:37.664498 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12251 06:50:37.670940 <14>[ 25.523365] [IGT] kms_vblank: executing
12252 06:50:37.674305 IGT-Version: 1.2<14>[ 25.528104] [IGT] kms_vblank: exiting, ret=77
12253 06:50:37.681299 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12254 06:50:37.691691 Opened device: /dev/dri/ca<8>[ 25.540570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12255 06:50:37.691817 rd0
12256 06:50:37.692060 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12258 06:50:37.694243 No KMS driver or no outputs, pipes: 8, outputs: 0
12259 06:50:37.700710 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12260 06:50:37.708235 <14>[ 25.560325] [IGT] kms_vblank: executing
12261 06:50:37.714497 IGT-Version: 1.2<14>[ 25.565147] [IGT] kms_vblank: exiting, ret=77
12262 06:50:37.717970 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12263 06:50:37.727598 Opened dev<8>[ 25.575395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12264 06:50:37.727739 ice: /dev/dri/card0
12265 06:50:37.728013 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12267 06:50:37.734038 No KMS driver or no outputs, pipes: 8, outputs: 0
12268 06:50:37.737458 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12269 06:50:37.743963 <14>[ 25.596384] [IGT] kms_vblank: executing
12270 06:50:37.750906 IGT-Version: 1.2<14>[ 25.601198] [IGT] kms_vblank: exiting, ret=77
12271 06:50:37.754602 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12272 06:50:37.760543 Opened dev<8>[ 25.611458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12273 06:50:37.760820 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12275 06:50:37.763770 ice: /dev/dri/card0
12276 06:50:37.767300 No KMS driver or no outputs, pipes: 8, outputs: 0
12277 06:50:37.774307 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12278 06:50:37.777624 <14>[ 25.632043] [IGT] kms_vblank: executing
12279 06:50:37.784403 IGT-Version: 1.2<14>[ 25.636772] [IGT] kms_vblank: exiting, ret=77
12280 06:50:37.790746 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12281 06:50:37.797638 Opened dev<8>[ 25.647217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12282 06:50:37.797958 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12284 06:50:37.800911 ice: /dev/dri/card0
12285 06:50:37.803991 No KMS driver or no outputs, pipes: 8, outputs: 0
12286 06:50:37.810908 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12287 06:50:37.814407 <14>[ 25.668108] [IGT] kms_vblank: executing
12288 06:50:37.820854 IGT-Version: 1.2<14>[ 25.672832] [IGT] kms_vblank: exiting, ret=77
12289 06:50:37.824035 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12290 06:50:37.827431 Opened device: /dev/dri/card0
12291 06:50:37.834480 No KMS driver or no outputs, pipes: 8, outputs: 0
12292 06:50:37.837285 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12293 06:50:37.844180 <8>[ 25.695793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12294 06:50:37.844457 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12296 06:50:37.863838 <14>[ 25.715937] [IGT] kms_vblank: executing
12297 06:50:37.869778 IGT-Version: 1.2<14>[ 25.720855] [IGT] kms_vblank: exiting, ret=77
12298 06:50:37.873297 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12299 06:50:37.876733 Opened device: /dev/dri/card0
12300 06:50:37.883542 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12302 06:50:37.886599 No KMS driv<8>[ 25.734146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12303 06:50:37.889857 er or no outputs, pipes: 8, outputs: 0
12304 06:50:37.893707 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12305 06:50:37.912008 <14>[ 25.764904] [IGT] kms_vblank: executing
12306 06:50:37.919172 IGT-Version: 1.2<14>[ 25.769903] [IGT] kms_vblank: exiting, ret=77
12307 06:50:37.922287 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12308 06:50:37.931913 Opened device: /dev/dri/ca<8>[ 25.781079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12309 06:50:37.932036 rd0
12310 06:50:37.932280 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12312 06:50:37.938384 No KMS driver or no outputs, pipes: 8, outputs: 0
12313 06:50:37.942160 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12314 06:50:37.950867 <14>[ 25.803392] [IGT] kms_vblank: executing
12315 06:50:37.957369 IGT-Version: 1.2<14>[ 25.808155] [IGT] kms_vblank: exiting, ret=77
12316 06:50:37.961113 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12317 06:50:37.970705 Opened device: /dev/dri/ca<8>[ 25.820441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12318 06:50:37.970855 rd0
12319 06:50:37.971139 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12321 06:50:37.977319 No KMS driver or no outputs, pipes: 8, outputs: 0
12322 06:50:37.980820 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12323 06:50:37.989454 <14>[ 25.841837] [IGT] kms_vblank: executing
12324 06:50:37.995680 IGT-Version: 1.2<14>[ 25.846662] [IGT] kms_vblank: exiting, ret=77
12325 06:50:37.999077 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12326 06:50:38.002789 Opened device: /dev/dri/card0
12327 06:50:38.010361 No KMS driv<8>[ 25.859331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12328 06:50:38.010723 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12330 06:50:38.012593 er or no outputs, pipes: 8, outputs: 0
12331 06:50:38.019577 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12332 06:50:38.027526 <14>[ 25.880111] [IGT] kms_vblank: executing
12333 06:50:38.034023 IGT-Version: 1.2<14>[ 25.884892] [IGT] kms_vblank: exiting, ret=77
12334 06:50:38.037177 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12335 06:50:38.047381 Opened dev<8>[ 25.895348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12336 06:50:38.047509 ice: /dev/dri/card0
12337 06:50:38.047752 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12339 06:50:38.054103 No KMS driver or no outputs, pipes: 8, outputs: 0
12340 06:50:38.057261 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12341 06:50:38.060426 <14>[ 25.915694] [IGT] kms_vblank: executing
12342 06:50:38.067403 IGT-Version: 1.2<14>[ 25.920429] [IGT] kms_vblank: exiting, ret=77
12343 06:50:38.074294 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12344 06:50:38.080636 Opened dev<8>[ 25.930853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12345 06:50:38.080935 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12347 06:50:38.084151 ice: /dev/dri/card0
12348 06:50:38.087719 No KMS driver or no outputs, pipes: 8, outputs: 0
12349 06:50:38.091229 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12350 06:50:38.098586 <14>[ 25.951144] [IGT] kms_vblank: executing
12351 06:50:38.105281 IGT-Version: 1.2<14>[ 25.955971] [IGT] kms_vblank: exiting, ret=77
12352 06:50:38.108261 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12353 06:50:38.118425 Opened dev<8>[ 25.966205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12354 06:50:38.118552 ice: /dev/dri/card0
12355 06:50:38.118820 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12357 06:50:38.124705 No KMS driver or no outputs, pipes: 8, outputs: 0
12358 06:50:38.128522 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12359 06:50:38.146283 <14>[ 25.999051] [IGT] kms_vblank: executing
12360 06:50:38.153272 IGT-Version: 1.2<14>[ 26.004094] [IGT] kms_vblank: exiting, ret=77
12361 06:50:38.156264 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12362 06:50:38.165985 Opened device: /dev/dri/ca<8>[ 26.015327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12363 06:50:38.166104 rd0
12364 06:50:38.166350 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12366 06:50:38.169475 No KMS driver or no outputs, pipes: 8, outputs: 0
12367 06:50:38.176324 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12368 06:50:38.183829 <14>[ 26.036297] [IGT] kms_vblank: executing
12369 06:50:38.190117 IGT-Version: 1.2<14>[ 26.041006] [IGT] kms_vblank: exiting, ret=77
12370 06:50:38.193251 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12371 06:50:38.203077 Opened dev<8>[ 26.051215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12372 06:50:38.203210 ice: /dev/dri/card0
12373 06:50:38.203456 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12375 06:50:38.210435 No KMS driver or no outputs, pipes: 8, outputs: 0
12376 06:50:38.213393 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12377 06:50:38.219893 <14>[ 26.071997] [IGT] kms_vblank: executing
12378 06:50:38.223318 IGT-Version: 1.2<14>[ 26.076715] [IGT] kms_vblank: exiting, ret=77
12379 06:50:38.230195 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12380 06:50:38.236608 Opened dev<8>[ 26.087287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12381 06:50:38.236904 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12383 06:50:38.239888 ice: /dev/dri/card0
12384 06:50:38.243217 No KMS driver or no outputs, pipes: 8, outputs: 0
12385 06:50:38.250020 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12386 06:50:38.253230 <14>[ 26.108173] [IGT] kms_vblank: executing
12387 06:50:38.259789 IGT-Version: 1.2<14>[ 26.112907] [IGT] kms_vblank: exiting, ret=77
12388 06:50:38.266166 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12389 06:50:38.273536 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12391 06:50:38.276475 Opened dev<8>[ 26.123288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12392 06:50:38.276564 ice: /dev/dri/card0
12393 06:50:38.279640 No KMS driver or no outputs, pipes: 8, outputs: 0
12394 06:50:38.286075 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12395 06:50:38.295940 <14>[ 26.148559] [IGT] kms_vblank: executing
12396 06:50:38.303093 IGT-Version: 1.2<14>[ 26.153310] [IGT] kms_vblank: exiting, ret=77
12397 06:50:38.305828 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12398 06:50:38.315679 Opened dev<8>[ 26.163532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12399 06:50:38.315802 ice: /dev/dri/card0
12400 06:50:38.316048 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12402 06:50:38.322594 No KMS driver or no outputs, pipes: 8, outputs: 0
12403 06:50:38.325704 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12404 06:50:38.332268 <14>[ 26.184765] [IGT] kms_vblank: executing
12405 06:50:38.338781 IGT-Version: 1.2<14>[ 26.189480] [IGT] kms_vblank: exiting, ret=77
12406 06:50:38.342469 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12407 06:50:38.351993 Opened dev<8>[ 26.199749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12408 06:50:38.352113 ice: /dev/dri/card0
12409 06:50:38.352359 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12411 06:50:38.358785 No KMS driver or no outputs, pipes: 8, outputs: 0
12412 06:50:38.362141 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12413 06:50:38.369008 <14>[ 26.221210] [IGT] kms_vblank: executing
12414 06:50:38.375508 IGT-Version: 1.2<14>[ 26.226234] [IGT] kms_vblank: exiting, ret=77
12415 06:50:38.378757 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12416 06:50:38.388561 Opened dev<8>[ 26.236707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12417 06:50:38.388704 ice: /dev/dri/card0
12418 06:50:38.388948 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12420 06:50:38.395708 No KMS driver or no outputs, pipes: 8, outputs: 0
12421 06:50:38.398311 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12422 06:50:38.405222 <14>[ 26.258221] [IGT] kms_vblank: executing
12423 06:50:38.412078 IGT-Version: 1.2<14>[ 26.263124] [IGT] kms_vblank: exiting, ret=77
12424 06:50:38.415251 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12425 06:50:38.425429 Opened dev<8>[ 26.273456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12426 06:50:38.425768 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12428 06:50:38.428669 ice: /dev/dri/card0
12429 06:50:38.432524 No KMS driver or no outputs, pipes: 8, outputs: 0
12430 06:50:38.439159 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12431 06:50:38.442364 <14>[ 26.295916] [IGT] kms_vblank: executing
12432 06:50:38.448663 IGT-Version: 1.2<14>[ 26.300637] [IGT] kms_vblank: exiting, ret=77
12433 06:50:38.452839 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12434 06:50:38.461921 Opened dev<8>[ 26.311187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12435 06:50:38.462276 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12437 06:50:38.465340 ice: /dev/dri/card0
12438 06:50:38.469295 No KMS driver or no outputs, pipes: 8, outputs: 0
12439 06:50:38.475358 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12440 06:50:38.478304 <14>[ 26.332471] [IGT] kms_vblank: executing
12441 06:50:38.484929 IGT-Version: 1.2<14>[ 26.337223] [IGT] kms_vblank: exiting, ret=77
12442 06:50:38.488563 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12443 06:50:38.498561 Opened dev<8>[ 26.347618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12444 06:50:38.498869 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12446 06:50:38.501681 ice: /dev/dri/card0
12447 06:50:38.505000 No KMS driver or no outputs, pipes: 8, outputs: 0
12448 06:50:38.511839 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12449 06:50:38.520740 <14>[ 26.373204] [IGT] kms_vblank: executing
12450 06:50:38.527393 IGT-Version: 1.2<14>[ 26.377953] [IGT] kms_vblank: exiting, ret=77
12451 06:50:38.530149 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12452 06:50:38.540423 Opened dev<8>[ 26.388420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12453 06:50:38.540760 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12455 06:50:38.543573 ice: /dev/dri/card0
12456 06:50:38.546679 No KMS driver or no outputs, pipes: 8, outputs: 0
12457 06:50:38.553762 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12458 06:50:38.556923 <14>[ 26.410101] [IGT] kms_vblank: executing
12459 06:50:38.563367 IGT-Version: 1.2<14>[ 26.415128] [IGT] kms_vblank: exiting, ret=77
12460 06:50:38.566589 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12461 06:50:38.576464 Opened dev<8>[ 26.425580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12462 06:50:38.576758 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12464 06:50:38.580622 ice: /dev/dri/card0
12465 06:50:38.583260 No KMS driver or no outputs, pipes: 8, outputs: 0
12466 06:50:38.590009 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12467 06:50:38.594114 <14>[ 26.447079] [IGT] kms_vblank: executing
12468 06:50:38.600275 IGT-Version: 1.2<14>[ 26.452148] [IGT] kms_vblank: exiting, ret=77
12469 06:50:38.603570 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12470 06:50:38.613248 Opened dev<8>[ 26.462472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12471 06:50:38.613575 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12473 06:50:38.616691 ice: /dev/dri/card0
12474 06:50:38.619772 No KMS driver or no outputs, pipes: 8, outputs: 0
12475 06:50:38.623275 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12476 06:50:38.630710 <14>[ 26.483273] [IGT] kms_vblank: executing
12477 06:50:38.637328 IGT-Version: 1.2<14>[ 26.487990] [IGT] kms_vblank: exiting, ret=77
12478 06:50:38.640233 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12479 06:50:38.647015 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12481 06:50:38.650496 Opened dev<8>[ 26.498291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12482 06:50:38.650594 ice: /dev/dri/card0
12483 06:50:38.653552 No KMS driver or no outputs, pipes: 8, outputs: 0
12484 06:50:38.660472 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12485 06:50:38.666789 <14>[ 26.519039] [IGT] kms_vblank: executing
12486 06:50:38.670358 IGT-Version: 1.2<14>[ 26.523753] [IGT] kms_vblank: exiting, ret=77
12487 06:50:38.676518 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12488 06:50:38.683885 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12490 06:50:38.686496 Opened dev<8>[ 26.534184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12491 06:50:38.686588 ice: /dev/dri/card0
12492 06:50:38.690273 No KMS driver or no outputs, pipes: 8, outputs: 0
12493 06:50:38.696769 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12494 06:50:38.699958 <14>[ 26.554916] [IGT] kms_vblank: executing
12495 06:50:38.706617 IGT-Version: 1.2<14>[ 26.559756] [IGT] kms_vblank: exiting, ret=77
12496 06:50:38.713436 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12497 06:50:38.719696 Opened dev<8>[ 26.570161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12498 06:50:38.719973 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12500 06:50:38.723147 ice: /dev/dri/card0
12501 06:50:38.726369 No KMS driver or no outputs, pipes: 8, outputs: 0
12502 06:50:38.733672 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12503 06:50:38.736669 <14>[ 26.590753] [IGT] kms_vblank: executing
12504 06:50:38.743525 IGT-Version: 1.2<14>[ 26.595507] [IGT] kms_vblank: exiting, ret=77
12505 06:50:38.746332 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12506 06:50:38.757076 Opened dev<8>[ 26.605764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12507 06:50:38.757380 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12509 06:50:38.759924 ice: /dev/dri/card0
12510 06:50:38.763147 No KMS driver or no outputs, pipes: 8, outputs: 0
12511 06:50:38.769631 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12512 06:50:38.773301 <14>[ 26.626798] [IGT] kms_vblank: executing
12513 06:50:38.780130 IGT-Version: 1.2<14>[ 26.631529] [IGT] kms_vblank: exiting, ret=77
12514 06:50:38.782975 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12515 06:50:38.793699 Opened dev<8>[ 26.641834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12516 06:50:38.793834 ice: /dev/dri/card0
12517 06:50:38.794080 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12519 06:50:38.800279 No KMS driver or no outputs, pipes: 8, outputs: 0
12520 06:50:38.804021 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12521 06:50:38.810160 <14>[ 26.662352] [IGT] kms_vblank: executing
12522 06:50:38.817341 IGT-Version: 1.2<14>[ 26.667181] [IGT] kms_vblank: exiting, ret=77
12523 06:50:38.819911 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12524 06:50:38.829897 Opened dev<8>[ 26.677640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12525 06:50:38.830021 ice: /dev/dri/card0
12526 06:50:38.830268 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12528 06:50:38.833120 No KMS driver or no outputs, pipes: 8, outputs: 0
12529 06:50:38.840248 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12530 06:50:38.843491 <14>[ 26.698177] [IGT] kms_vblank: executing
12531 06:50:38.849861 IGT-Version: 1.2<14>[ 26.703031] [IGT] kms_vblank: exiting, ret=77
12532 06:50:38.856367 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12533 06:50:38.862878 Opened dev<8>[ 26.713339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12534 06:50:38.863172 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12536 06:50:38.866751 ice: /dev/dri/card0
12537 06:50:38.870093 No KMS driver or no outputs, pipes: 8, outputs: 0
12538 06:50:38.876673 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12539 06:50:38.880128 <14>[ 26.734540] [IGT] kms_vblank: executing
12540 06:50:38.887413 IGT-Version: 1.2<14>[ 26.739275] [IGT] kms_vblank: exiting, ret=77
12541 06:50:38.893426 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12542 06:50:38.899945 Opened dev<8>[ 26.749717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12543 06:50:38.900259 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12545 06:50:38.903176 ice: /dev/dri/card0
12546 06:50:38.906248 No KMS driver or no outputs, pipes: 8, outputs: 0
12547 06:50:38.913815 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12548 06:50:38.916570 <14>[ 26.771058] [IGT] kms_vblank: executing
12549 06:50:38.923346 IGT-Version: 1.2<14>[ 26.775790] [IGT] kms_vblank: exiting, ret=77
12550 06:50:38.929571 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12551 06:50:38.936138 Opened dev<8>[ 26.786156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12552 06:50:38.936442 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12554 06:50:38.939531 ice: /dev/dri/card0
12555 06:50:38.943041 No KMS driver or no outputs, pipes: 8, outputs: 0
12556 06:50:38.946339 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12557 06:50:38.953673 <14>[ 26.806720] [IGT] kms_vblank: executing
12558 06:50:38.960567 IGT-Version: 1.2<14>[ 26.811463] [IGT] kms_vblank: exiting, ret=77
12559 06:50:38.963926 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12560 06:50:38.973414 Opened dev<8>[ 26.821808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12561 06:50:38.973535 ice: /dev/dri/card0
12562 06:50:38.973780 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12564 06:50:38.980305 No KMS driver or no outputs, pipes: 8, outputs: 0
12565 06:50:38.983998 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12566 06:50:38.990011 <14>[ 26.842399] [IGT] kms_vblank: executing
12567 06:50:38.993766 IGT-Version: 1.2<14>[ 26.847139] [IGT] kms_vblank: exiting, ret=77
12568 06:50:39.000241 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12569 06:50:39.007016 Opened dev<8>[ 26.857716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12570 06:50:39.007318 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12572 06:50:39.010334 ice: /dev/dri/card0
12573 06:50:39.013325 No KMS driver or no outputs, pipes: 8, outputs: 0
12574 06:50:39.020175 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12575 06:50:39.023474 <14>[ 26.878005] [IGT] kms_vblank: executing
12576 06:50:39.029883 IGT-Version: 1.2<14>[ 26.882906] [IGT] kms_vblank: exiting, ret=77
12577 06:50:39.036334 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12578 06:50:39.042935 Opened dev<8>[ 26.893055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12579 06:50:39.043233 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12581 06:50:39.046498 ice: /dev/dri/card0
12582 06:50:39.049575 No KMS driver or no outputs, pipes: 8, outputs: 0
12583 06:50:39.056402 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12584 06:50:39.059419 <14>[ 26.914130] [IGT] kms_vblank: executing
12585 06:50:39.066014 IGT-Version: 1.2<14>[ 26.918987] [IGT] kms_vblank: exiting, ret=77
12586 06:50:39.072652 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12587 06:50:39.072772 Opened device: /dev/dri/card0
12588 06:50:39.082390 No KMS driv<8>[ 26.931909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12589 06:50:39.082695 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12591 06:50:39.086137 er or no outputs, pipes: 8, outputs: 0
12592 06:50:39.089529 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12593 06:50:39.099989 <14>[ 26.952817] [IGT] kms_vblank: executing
12594 06:50:39.106752 IGT-Version: 1.2<14>[ 26.957590] [IGT] kms_vblank: exiting, ret=77
12595 06:50:39.110038 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12596 06:50:39.120239 Opened dev<8>[ 26.967817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12597 06:50:39.120394 ice: /dev/dri/card0
12598 06:50:39.120679 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12600 06:50:39.126488 No KMS driver or no outputs, pipes: 8, outputs: 0
12601 06:50:39.129954 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12602 06:50:39.133531 <14>[ 26.988504] [IGT] kms_vblank: executing
12603 06:50:39.139934 IGT-Version: 1.2<14>[ 26.993230] [IGT] kms_vblank: exiting, ret=77
12604 06:50:39.146747 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12605 06:50:39.153375 Opened dev<8>[ 27.003353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12606 06:50:39.153673 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12608 06:50:39.156509 ice: /dev/dri/card0
12609 06:50:39.159593 No KMS driver or no outputs, pipes: 8, outputs: 0
12610 06:50:39.166363 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12611 06:50:39.172736 <14>[ 27.025165] [IGT] kms_vblank: executing
12612 06:50:39.176278 IGT-Version: 1.2<14>[ 27.030004] [IGT] kms_vblank: exiting, ret=77
12613 06:50:39.183036 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12614 06:50:39.193068 Opened dev<8>[ 27.040469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12615 06:50:39.193213 ice: /dev/dri/card0
12616 06:50:39.193458 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12618 06:50:39.199655 No KMS driver or no outputs, pipes: 8, outputs: 0
12619 06:50:39.203049 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12620 06:50:39.210307 <14>[ 27.062462] [IGT] kms_vblank: executing
12621 06:50:39.216142 IGT-Version: 1.2<14>[ 27.067192] [IGT] kms_vblank: exiting, ret=77
12622 06:50:39.219855 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12623 06:50:39.229810 Opened dev<8>[ 27.077564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12624 06:50:39.229949 ice: /dev/dri/card0
12625 06:50:39.230225 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12627 06:50:39.236284 No KMS driver or no outputs, pipes: 8, outputs: 0
12628 06:50:39.239549 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12629 06:50:39.246206 <14>[ 27.099188] [IGT] kms_vblank: executing
12630 06:50:39.253180 IGT-Version: 1.2<14>[ 27.104026] [IGT] kms_vblank: exiting, ret=77
12631 06:50:39.257086 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12632 06:50:39.266244 Opened dev<8>[ 27.114575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12633 06:50:39.266594 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12635 06:50:39.269670 ice: /dev/dri/card0
12636 06:50:39.272816 No KMS driver or no outputs, pipes: 8, outputs: 0
12637 06:50:39.279491 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12638 06:50:39.282669 <14>[ 27.136255] [IGT] kms_vblank: executing
12639 06:50:39.289443 IGT-Version: 1.2<14>[ 27.141067] [IGT] kms_vblank: exiting, ret=77
12640 06:50:39.292924 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12641 06:50:39.302856 Opened dev<8>[ 27.151322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12642 06:50:39.303171 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12644 06:50:39.306236 ice: /dev/dri/card0
12645 06:50:39.309470 No KMS driver or no outputs, pipes: 8, outputs: 0
12646 06:50:39.315782 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12647 06:50:39.319541 <14>[ 27.172634] [IGT] kms_vblank: executing
12648 06:50:39.326176 IGT-Version: 1.2<14>[ 27.177743] [IGT] kms_vblank: exiting, ret=77
12649 06:50:39.329708 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12650 06:50:39.339843 Opened dev<8>[ 27.188160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12651 06:50:39.340155 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12653 06:50:39.343187 ice: /dev/dri/card0
12654 06:50:39.345905 No KMS driver or no outputs, pipes: 8, outputs: 0
12655 06:50:39.352544 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12656 06:50:39.356170 <14>[ 27.209817] [IGT] kms_vblank: executing
12657 06:50:39.363386 IGT-Version: 1.2<14>[ 27.215068] [IGT] kms_vblank: exiting, ret=77
12658 06:50:39.366368 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12659 06:50:39.375882 Opened dev<8>[ 27.225411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12660 06:50:39.376185 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12662 06:50:39.379352 ice: /dev/dri/card0
12663 06:50:39.382756 No KMS driver or no outputs, pipes: 8, outputs: 0
12664 06:50:39.389405 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12665 06:50:39.397089 <14>[ 27.249957] [IGT] kms_vblank: executing
12666 06:50:39.403890 IGT-Version: 1.2<14>[ 27.254832] [IGT] kms_vblank: exiting, ret=77
12667 06:50:39.406883 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12668 06:50:39.417350 Opened dev<8>[ 27.264938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12669 06:50:39.417485 ice: /dev/dri/card0
12670 06:50:39.417733 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12672 06:50:39.424014 No KMS driver or no outputs, pipes: 8, outputs: 0
12673 06:50:39.426599 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12674 06:50:39.433953 <14>[ 27.287020] [IGT] kms_vblank: executing
12675 06:50:39.440979 IGT-Version: 1.2<14>[ 27.291830] [IGT] kms_vblank: exiting, ret=77
12676 06:50:39.444242 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12677 06:50:39.453958 Opened dev<8>[ 27.302139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12678 06:50:39.454264 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12680 06:50:39.457530 ice: /dev/dri/card0
12681 06:50:39.460496 No KMS driver or no outputs, pipes: 8, outputs: 0
12682 06:50:39.467621 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12683 06:50:39.470918 <14>[ 27.324087] [IGT] kms_vblank: executing
12684 06:50:39.477774 IGT-Version: 1.2<14>[ 27.329054] [IGT] kms_vblank: exiting, ret=77
12685 06:50:39.480738 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12686 06:50:39.490629 Opened dev<8>[ 27.339379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12687 06:50:39.490942 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12689 06:50:39.494541 ice: /dev/dri/card0
12690 06:50:39.497252 No KMS driver or no outputs, pipes: 8, outputs: 0
12691 06:50:39.503927 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12692 06:50:39.506909 <14>[ 27.360973] [IGT] kms_vblank: executing
12693 06:50:39.514589 IGT-Version: 1.2<14>[ 27.366082] [IGT] kms_vblank: exiting, ret=77
12694 06:50:39.517246 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12695 06:50:39.527534 Opened dev<8>[ 27.376323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12696 06:50:39.527851 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12698 06:50:39.530345 ice: /dev/dri/card0
12699 06:50:39.533726 No KMS driver or no outputs, pipes: 8, outputs: 0
12700 06:50:39.537040 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12701 06:50:39.544411 <14>[ 27.397173] [IGT] kms_vblank: executing
12702 06:50:39.550834 IGT-Version: 1.2<14>[ 27.401892] [IGT] kms_vblank: exiting, ret=77
12703 06:50:39.554428 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12704 06:50:39.561278 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12706 06:50:39.563983 Opened dev<8>[ 27.412434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12707 06:50:39.564070 ice: /dev/dri/card0
12708 06:50:39.567539 No KMS driver or no outputs, pipes: 8, outputs: 0
12709 06:50:39.574218 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12710 06:50:39.580622 <14>[ 27.432890] [IGT] kms_vblank: executing
12711 06:50:39.583919 IGT-Version: 1.2<14>[ 27.437649] [IGT] kms_vblank: exiting, ret=77
12712 06:50:39.590995 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12713 06:50:39.597350 Opened dev<8>[ 27.448002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12714 06:50:39.597686 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12716 06:50:39.600531 ice: /dev/dri/card0
12717 06:50:39.604162 No KMS driver or no outputs, pipes: 8, outputs: 0
12718 06:50:39.610317 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12719 06:50:39.614789 <14>[ 27.468632] [IGT] kms_vblank: executing
12720 06:50:39.620606 IGT-Version: 1.2<14>[ 27.473368] [IGT] kms_vblank: exiting, ret=77
12721 06:50:39.627210 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12722 06:50:39.633725 Opened dev<8>[ 27.483948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12723 06:50:39.634013 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12725 06:50:39.637386 ice: /dev/dri/card0
12726 06:50:39.640564 No KMS driver or no outputs, pipes: 8, outputs: 0
12727 06:50:39.644259 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12728 06:50:39.651118 <14>[ 27.504011] [IGT] kms_vblank: executing
12729 06:50:39.657519 IGT-Version: 1.2<14>[ 27.508752] [IGT] kms_vblank: exiting, ret=77
12730 06:50:39.660990 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12731 06:50:39.670885 Opened dev<8>[ 27.519242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12732 06:50:39.671036 ice: /dev/dri/card0
12733 06:50:39.671314 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12735 06:50:39.677307 No KMS driver or no outputs, pipes: 8, outputs: 0
12736 06:50:39.680663 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12737 06:50:39.687224 <14>[ 27.539957] [IGT] kms_vblank: executing
12738 06:50:39.693898 IGT-Version: 1.2<14>[ 27.544890] [IGT] kms_vblank: exiting, ret=77
12739 06:50:39.697215 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12740 06:50:39.704600 Opened dev<8>[ 27.555389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12741 06:50:39.704901 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12743 06:50:39.707505 ice: /dev/dri/card0
12744 06:50:39.711150 No KMS driver or no outputs, pipes: 8, outputs: 0
12745 06:50:39.717696 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12746 06:50:39.720611 <14>[ 27.575887] [IGT] kms_vblank: executing
12747 06:50:39.727265 IGT-Version: 1.2<14>[ 27.580723] [IGT] kms_vblank: exiting, ret=77
12748 06:50:39.733948 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12749 06:50:39.740745 Opened dev<8>[ 27.591357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12750 06:50:39.741045 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12752 06:50:39.743970 ice: /dev/dri/card0
12753 06:50:39.747339 No KMS driver or no outputs, pipes: 8, outputs: 0
12754 06:50:39.754078 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12755 06:50:39.757194 <14>[ 27.611807] [IGT] kms_vblank: executing
12756 06:50:39.763642 IGT-Version: 1.2<14>[ 27.616655] [IGT] kms_vblank: exiting, ret=77
12757 06:50:39.770461 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12758 06:50:39.777170 Opened dev<8>[ 27.627321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12759 06:50:39.777465 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12761 06:50:39.780712 ice: /dev/dri/card0
12762 06:50:39.783905 No KMS driver or no outputs, pipes: 8, outputs: 0
12763 06:50:39.791973 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12764 06:50:39.793537 <14>[ 27.647904] [IGT] kms_vblank: executing
12765 06:50:39.801211 IGT-Version: 1.2<14>[ 27.652706] [IGT] kms_vblank: exiting, ret=77
12766 06:50:39.804269 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12767 06:50:39.813378 Opened dev<8>[ 27.663180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12768 06:50:39.813680 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12770 06:50:39.816673 ice: /dev/dri/card0
12771 06:50:39.819988 No KMS driver or no outputs, pipes: 8, outputs: 0
12772 06:50:39.826953 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12773 06:50:39.830362 <14>[ 27.684323] [IGT] kms_vblank: executing
12774 06:50:39.836624 IGT-Version: 1.2<14>[ 27.689053] [IGT] kms_vblank: exiting, ret=77
12775 06:50:39.840203 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12776 06:50:39.849946 Opened dev<8>[ 27.699318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12777 06:50:39.850075 ice: /dev/dri/card0
12778 06:50:39.850321 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12780 06:50:39.856518 No KMS driver or no outputs, pipes: 8, outputs: 0
12781 06:50:39.860122 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12782 06:50:39.866798 <14>[ 27.719699] [IGT] kms_vblank: executing
12783 06:50:39.873344 IGT-Version: 1.2<14>[ 27.724614] [IGT] kms_vblank: exiting, ret=77
12784 06:50:39.876595 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12785 06:50:39.886930 Opened dev<8>[ 27.735027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12786 06:50:39.887065 ice: /dev/dri/card0
12787 06:50:39.887314 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12789 06:50:39.893608 No KMS driver or no outputs, pipes: 8, outputs: 0
12790 06:50:39.896875 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12791 06:50:39.903607 <14>[ 27.755618] [IGT] kms_vblank: executing
12792 06:50:39.906219 IGT-Version: 1.2<14>[ 27.760366] [IGT] kms_vblank: exiting, ret=77
12793 06:50:39.913093 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12794 06:50:39.919526 Opened dev<8>[ 27.770901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12795 06:50:39.919813 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12797 06:50:39.923745 ice: /dev/dri/card0
12798 06:50:39.926347 No KMS driver or no outputs, pipes: 8, outputs: 0
12799 06:50:39.933087 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12800 06:50:39.936085 <14>[ 27.791622] [IGT] kms_vblank: executing
12801 06:50:39.942998 IGT-Version: 1.2<14>[ 27.796406] [IGT] kms_vblank: exiting, ret=77
12802 06:50:39.950037 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12803 06:50:39.956449 Opened dev<8>[ 27.807047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12804 06:50:39.956741 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12806 06:50:39.960065 ice: /dev/dri/card0
12807 06:50:39.962934 No KMS driver or no outputs, pipes: 8, outputs: 0
12808 06:50:39.970074 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12809 06:50:39.973631 <14>[ 27.827415] [IGT] kms_vblank: executing
12810 06:50:39.979835 IGT-Version: 1.2<14>[ 27.832164] [IGT] kms_vblank: exiting, ret=77
12811 06:50:39.983284 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12812 06:50:39.993026 Opened dev<8>[ 27.842508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12813 06:50:39.993345 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12815 06:50:39.996132 ice: /dev/dri/card0
12816 06:50:39.999769 No KMS driver or no outputs, pipes: 8, outputs: 0
12817 06:50:40.003303 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12818 06:50:40.009910 <14>[ 27.862883] [IGT] kms_vblank: executing
12819 06:50:40.016567 IGT-Version: 1.2<14>[ 27.867679] [IGT] kms_vblank: exiting, ret=77
12820 06:50:40.020026 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12821 06:50:40.029796 Opened dev<8>[ 27.877972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12822 06:50:40.029927 ice: /dev/dri/card0
12823 06:50:40.030173 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12825 06:50:40.036537 No KMS driver or no outputs, pipes: 8, outputs: 0
12826 06:50:40.039744 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12827 06:50:40.046935 <14>[ 27.898932] [IGT] kms_vblank: executing
12828 06:50:40.049943 IGT-Version: 1.2<14>[ 27.903659] [IGT] kms_vblank: exiting, ret=77
12829 06:50:40.056359 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12830 06:50:40.063204 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12832 06:50:40.066599 Opened dev<8>[ 27.913939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12833 06:50:40.066689 ice: /dev/dri/card0
12834 06:50:40.069830 No KMS driver or no outputs, pipes: 8, outputs: 0
12835 06:50:40.076339 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12836 06:50:40.079654 <14>[ 27.935050] [IGT] kms_vblank: executing
12837 06:50:40.086394 IGT-Version: 1.2<14>[ 27.939888] [IGT] kms_vblank: exiting, ret=77
12838 06:50:40.092955 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12839 06:50:40.099862 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12841 06:50:40.103267 Opened dev<8>[ 27.950208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12842 06:50:40.103358 ice: /dev/dri/card0
12843 06:50:40.106655 No KMS driver or no outputs, pipes: 8, outputs: 0
12844 06:50:40.113199 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12845 06:50:40.116517 <14>[ 27.971611] [IGT] kms_vblank: executing
12846 06:50:40.123280 IGT-Version: 1.2<14>[ 27.976344] [IGT] kms_vblank: exiting, ret=77
12847 06:50:40.129658 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12848 06:50:40.136115 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12850 06:50:40.139951 Opened dev<8>[ 27.986898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12851 06:50:40.140036 ice: /dev/dri/card0
12852 06:50:40.143066 No KMS driver or no outputs, pipes: 8, outputs: 0
12853 06:50:40.149105 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12854 06:50:40.152480 <14>[ 28.007971] [IGT] kms_vblank: executing
12855 06:50:40.159474 IGT-Version: 1.2<14>[ 28.012738] [IGT] kms_vblank: exiting, ret=77
12856 06:50:40.165793 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12857 06:50:40.176002 Opened dev<8>[ 28.023304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12858 06:50:40.176142 ice: /dev/dri/card0
12859 06:50:40.176390 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12861 06:50:40.182585 No KMS driver or no outputs, pipes: 8, outputs: 0
12862 06:50:40.185936 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12863 06:50:40.192674 <14>[ 28.044640] [IGT] kms_vblank: executing
12864 06:50:40.195482 IGT-Version: 1.2<14>[ 28.049525] [IGT] kms_vblank: exiting, ret=77
12865 06:50:40.202199 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12866 06:50:40.212328 Opened dev<8>[ 28.060081] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12867 06:50:40.212493 ice: /dev/dri/card0
12868 06:50:40.212752 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12870 06:50:40.218661 No KMS driver or no outputs, pipes: 8, outputs: 0
12871 06:50:40.221865 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12872 06:50:40.228818 <14>[ 28.081141] [IGT] kms_vblank: executing
12873 06:50:40.235314 IGT-Version: 1.2<14>[ 28.086192] [IGT] kms_vblank: exiting, ret=77
12874 06:50:40.238571 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12875 06:50:40.248854 Opened dev<8>[ 28.096438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12876 06:50:40.248979 ice: /dev/dri/card0
12877 06:50:40.249225 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12879 06:50:40.255210 No KMS driver or no outputs, pipes: 8, outputs: 0
12880 06:50:40.262038 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12881 06:50:40.265533 <14>[ 28.118280] [IGT] kms_vblank: executing
12882 06:50:40.271814 IGT-Version: 1.2<14>[ 28.123397] [IGT] kms_vblank: exiting, ret=77
12883 06:50:40.275248 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12884 06:50:40.285362 Opened dev<8>[ 28.133790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12885 06:50:40.285679 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12887 06:50:40.288669 ice: /dev/dri/card0
12888 06:50:40.291880 No KMS driver or no outputs, pipes: 8, outputs: 0
12889 06:50:40.298593 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12890 06:50:40.301790 <14>[ 28.155273] [IGT] kms_vblank: executing
12891 06:50:40.308651 IGT-Version: 1.2<14>[ 28.159975] [IGT] kms_vblank: exiting, ret=77
12892 06:50:40.311963 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12893 06:50:40.322136 Opened dev<8>[ 28.170590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12894 06:50:40.322457 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12896 06:50:40.325268 ice: /dev/dri/card0
12897 06:50:40.328846 No KMS driver or no outputs, pipes: 8, outputs: 0
12898 06:50:40.335069 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12899 06:50:40.338748 <14>[ 28.191783] [IGT] kms_vblank: executing
12900 06:50:40.345565 IGT-Version: 1.2<14>[ 28.196600] [IGT] kms_vblank: exiting, ret=77
12901 06:50:40.348721 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12902 06:50:40.358404 Opened dev<8>[ 28.207051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12903 06:50:40.358747 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12905 06:50:40.362333 ice: /dev/dri/card0
12906 06:50:40.365414 No KMS driver or no outputs, pipes: 8, outputs: 0
12907 06:50:40.371756 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12908 06:50:40.375195 <14>[ 28.228748] [IGT] kms_vblank: executing
12909 06:50:40.382190 IGT-Version: 1.2<14>[ 28.233954] [IGT] kms_vblank: exiting, ret=77
12910 06:50:40.385300 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12911 06:50:40.395502 Opened dev<8>[ 28.244366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12912 06:50:40.395825 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12914 06:50:40.398538 ice: /dev/dri/card0
12915 06:50:40.401725 No KMS driver or no outputs, pipes: 8, outputs: 0
12916 06:50:40.408381 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12917 06:50:40.411742 <14>[ 28.265960] [IGT] kms_vblank: executing
12918 06:50:40.418921 IGT-Version: 1.2<14>[ 28.271107] [IGT] kms_vblank: exiting, ret=77
12919 06:50:40.421922 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12920 06:50:40.432222 Opened dev<8>[ 28.281738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12921 06:50:40.432535 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12923 06:50:40.435812 ice: /dev/dri/card0
12924 06:50:40.439220 No KMS driver or no outputs, pipes: 8, outputs: 0
12925 06:50:40.442144 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12926 06:50:40.449375 <14>[ 28.302246] [IGT] kms_vblank: executing
12927 06:50:40.455733 IGT-Version: 1.2<14>[ 28.307020] [IGT] kms_vblank: exiting, ret=77
12928 06:50:40.459501 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12929 06:50:40.469557 Opened dev<8>[ 28.317382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12930 06:50:40.469692 ice: /dev/dri/card0
12931 06:50:40.469942 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12933 06:50:40.472518 No KMS driver or no outputs, pipes: 8, outputs: 0
12934 06:50:40.478900 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12935 06:50:40.482564 <14>[ 28.337570] [IGT] kms_vblank: executing
12936 06:50:40.489270 IGT-Version: 1.2<14>[ 28.342358] [IGT] kms_vblank: exiting, ret=77
12937 06:50:40.495669 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12938 06:50:40.502600 Opened dev<8>[ 28.352641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12939 06:50:40.502916 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12941 06:50:40.505523 ice: /dev/dri/card0
12942 06:50:40.509592 No KMS driver or no outputs, pipes: 8, outputs: 0
12943 06:50:40.515656 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12944 06:50:40.519841 <14>[ 28.373270] [IGT] kms_vblank: executing
12945 06:50:40.525404 IGT-Version: 1.2<14>[ 28.377975] [IGT] kms_vblank: exiting, ret=77
12946 06:50:40.528946 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12947 06:50:40.539462 Opened dev<8>[ 28.388513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12948 06:50:40.539801 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12950 06:50:40.542296 ice: /dev/dri/card0
12951 06:50:40.546182 No KMS driver or no outputs, pipes: 8, outputs: 0
12952 06:50:40.549346 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12953 06:50:40.555397 <14>[ 28.408727] [IGT] kms_vblank: executing
12954 06:50:40.562195 IGT-Version: 1.2<14>[ 28.413494] [IGT] kms_vblank: exiting, ret=77
12955 06:50:40.565627 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12956 06:50:40.575723 Opened dev<8>[ 28.423839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12957 06:50:40.575854 ice: /dev/dri/card0
12958 06:50:40.576128 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12960 06:50:40.582455 No KMS driver or no outputs, pipes: 8, outputs: 0
12961 06:50:40.585519 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12962 06:50:40.591986 <14>[ 28.444764] [IGT] kms_vblank: executing
12963 06:50:40.595688 IGT-Version: 1.2<14>[ 28.449493] [IGT] kms_vblank: exiting, ret=77
12964 06:50:40.602360 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12965 06:50:40.609015 Opened dev<8>[ 28.459870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12966 06:50:40.609317 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12968 06:50:40.613122 ice: /dev/dri/card0
12969 06:50:40.615542 No KMS driver or no outputs, pipes: 8, outputs: 0
12970 06:50:40.622185 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12971 06:50:40.625287 <14>[ 28.480214] [IGT] kms_vblank: executing
12972 06:50:40.631888 IGT-Version: 1.2<14>[ 28.484931] [IGT] kms_vblank: exiting, ret=77
12973 06:50:40.638486 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12974 06:50:40.645582 Opened dev<8>[ 28.495391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12975 06:50:40.645875 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12977 06:50:40.649139 ice: /dev/dri/card0
12978 06:50:40.651925 No KMS driver or no outputs, pipes: 8, outputs: 0
12979 06:50:40.658756 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12980 06:50:40.661580 <14>[ 28.516139] [IGT] kms_vblank: executing
12981 06:50:40.668698 IGT-Version: 1.2<14>[ 28.520846] [IGT] kms_vblank: exiting, ret=77
12982 06:50:40.671889 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12983 06:50:40.682000 Opened dev<8>[ 28.531296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12984 06:50:40.682302 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12986 06:50:40.684998 ice: /dev/dri/card0
12987 06:50:40.689260 No KMS driver or no outputs, pipes: 8, outputs: 0
12988 06:50:40.691682 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12989 06:50:40.699574 <14>[ 28.552170] [IGT] kms_vblank: executing
12990 06:50:40.706043 IGT-Version: 1.2<14>[ 28.556881] [IGT] kms_vblank: exiting, ret=77
12991 06:50:40.709115 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12992 06:50:40.719090 Opened dev<8>[ 28.567367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12993 06:50:40.719222 ice: /dev/dri/card0
12994 06:50:40.719469 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12996 06:50:40.726027 No KMS driver or no outputs, pipes: 8, outputs: 0
12997 06:50:40.729196 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12998 06:50:40.736147 <14>[ 28.588416] [IGT] kms_vblank: executing
12999 06:50:40.742800 IGT-Version: 1.2<14>[ 28.593251] [IGT] kms_vblank: exiting, ret=77
13000 06:50:40.746261 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13001 06:50:40.752406 Opened dev<8>[ 28.603645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
13002 06:50:40.752689 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
13004 06:50:40.755685 ice: /dev/dri/card0
13005 06:50:40.759169 No KMS driver or no outputs, pipes: 8, outputs: 0
13006 06:50:40.765688 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
13007 06:50:40.769155 <14>[ 28.623833] [IGT] kms_vblank: executing
13008 06:50:40.775828 IGT-Version: 1.2<14>[ 28.628567] [IGT] kms_vblank: exiting, ret=77
13009 06:50:40.782314 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13010 06:50:40.789071 Opened dev<8>[ 28.639031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
13011 06:50:40.789367 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
13013 06:50:40.792509 ice: /dev/dri/card0
13014 06:50:40.796025 No KMS driver or no outputs, pipes: 8, outputs: 0
13015 06:50:40.799122 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
13016 06:50:40.806503 <14>[ 28.659453] [IGT] kms_vblank: executing
13017 06:50:40.813826 IGT-Version: 1.2<14>[ 28.664198] [IGT] kms_vblank: exiting, ret=77
13018 06:50:40.816335 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13019 06:50:40.826605 Opened dev<8>[ 28.674654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
13020 06:50:40.826733 ice: /dev/dri/card0
13021 06:50:40.826976 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
13023 06:50:40.829761 No KMS driver or no outputs, pipes: 8, outputs: 0
13024 06:50:40.836033 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
13025 06:50:40.839398 <14>[ 28.694777] [IGT] kms_vblank: executing
13026 06:50:40.846238 IGT-Version: 1.2<14>[ 28.699711] [IGT] kms_vblank: exiting, ret=77
13027 06:50:40.853566 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13028 06:50:40.859667 Opened dev<8>[ 28.709974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
13029 06:50:40.859985 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
13031 06:50:40.862722 ice: /dev/dri/card0
13032 06:50:40.866259 No KMS driver or no outputs, pipes: 8, outputs: 0
13033 06:50:40.872906 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
13034 06:50:40.875947 <14>[ 28.730886] [IGT] kms_vblank: executing
13035 06:50:40.883209 IGT-Version: 1.2<14>[ 28.735639] [IGT] kms_vblank: exiting, ret=77
13036 06:50:40.889308 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13037 06:50:40.895801 Opened dev<8>[ 28.745966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
13038 06:50:40.896103 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
13040 06:50:40.899505 ice: /dev/dri/card0
13041 06:50:40.903125 No KMS driver or no outputs, pipes: 8, outputs: 0
13042 06:50:40.905744 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
13043 06:50:40.913044 <14>[ 28.766186] [IGT] kms_vblank: executing
13044 06:50:40.919954 IGT-Version: 1.2<14>[ 28.771015] [IGT] kms_vblank: exiting, ret=77
13045 06:50:40.923168 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13046 06:50:40.932849 Opened dev<8>[ 28.781262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
13047 06:50:40.932973 ice: /dev/dri/card0
13048 06:50:40.933222 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
13050 06:50:40.939609 No KMS driver or no outputs, pipes: 8, outputs: 0
13051 06:50:40.943161 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
13052 06:50:40.949597 <14>[ 28.802377] [IGT] kms_vblank: executing
13053 06:50:40.956929 IGT-Version: 1.2<14>[ 28.807123] [IGT] kms_vblank: exiting, ret=77
13054 06:50:40.959643 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13055 06:50:40.969786 Opened dev<8>[ 28.817482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
13056 06:50:40.969918 ice: /dev/dri/card0
13057 06:50:40.970162 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
13059 06:50:40.976114 No KMS driver or no outputs, pipes: 8, outputs: 0
13060 06:50:40.980064 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
13061 06:50:40.985990 <14>[ 28.838398] [IGT] kms_vblank: executing
13062 06:50:40.989622 IGT-Version: 1.2<14>[ 28.843342] [IGT] kms_vblank: exiting, ret=77
13063 06:50:40.996290 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13064 06:50:41.005992 Opened dev<8>[ 28.853756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
13065 06:50:41.006114 ice: /dev/dri/card0
13066 06:50:41.006360 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
13068 06:50:41.012611 No KMS driver or no outputs, pipes: 8, outputs: 0
13069 06:50:41.015920 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
13070 06:50:41.022365 <14>[ 28.875115] [IGT] kms_vblank: executing
13071 06:50:41.029100 IGT-Version: 1.2<14>[ 28.879838] [IGT] kms_vblank: exiting, ret=77
13072 06:50:41.032499 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13073 06:50:41.042390 Opened dev<8>[ 28.890236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
13074 06:50:41.042550 ice: /dev/dri/card0
13075 06:50:41.042798 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
13077 06:50:41.049283 No KMS driver or no outputs, pipes: 8, outputs: 0
13078 06:50:41.052611 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
13079 06:50:41.059019 <14>[ 28.911796] [IGT] kms_vblank: executing
13080 06:50:41.065439 IGT-Version: 1.2<14>[ 28.916538] [IGT] kms_vblank: exiting, ret=77
13081 06:50:41.068874 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13082 06:50:41.078832 Opened dev<8>[ 28.927112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13083 06:50:41.078964 ice: /dev/dri/card0
13084 06:50:41.079213 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13086 06:50:41.085622 No KMS driver or no outputs, pipes: 8, outputs: 0
13087 06:50:41.089007 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13088 06:50:41.095815 <14>[ 28.948313] [IGT] kms_vblank: executing
13089 06:50:41.102278 IGT-Version: 1.2<14>[ 28.953235] [IGT] kms_vblank: exiting, ret=77
13090 06:50:41.105670 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13091 06:50:41.115442 Opened dev<8>[ 28.963444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13092 06:50:41.115576 ice: /dev/dri/card0
13093 06:50:41.115822 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13095 06:50:41.121993 No KMS driver or no outputs, pipes: 8, outputs: 0
13096 06:50:41.125335 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13097 06:50:41.132089 <14>[ 28.984804] [IGT] kms_vblank: executing
13098 06:50:41.139150 IGT-Version: 1.2<14>[ 28.989962] [IGT] kms_vblank: exiting, ret=77
13099 06:50:41.142168 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13100 06:50:41.152380 Opened dev<8>[ 29.000284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13101 06:50:41.152686 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13103 06:50:41.155069 ice: /dev/dri/card0
13104 06:50:41.158645 No KMS driver or no outputs, pipes: 8, outputs: 0
13105 06:50:41.165570 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13106 06:50:41.168625 <14>[ 29.023407] [IGT] kms_vblank: executing
13107 06:50:41.175293 IGT-Version: 1.2<14>[ 29.028159] [IGT] kms_vblank: exiting, ret=77
13108 06:50:41.182718 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13109 06:50:41.192059 Opened device: /dev/dri/ca<8>[ 29.040518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13110 06:50:41.192199 rd0
13111 06:50:41.192446 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13113 06:50:41.195260 No KMS driver or no outputs, pipes: 8, outputs: 0
13114 06:50:41.201755 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13115 06:50:41.208761 <14>[ 29.061514] [IGT] kms_vblank: executing
13116 06:50:41.214946 IGT-Version: 1.2<14>[ 29.066541] [IGT] kms_vblank: exiting, ret=77
13117 06:50:41.218880 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13118 06:50:41.228551 Opened dev<8>[ 29.077025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13119 06:50:41.228684 ice: /dev/dri/card0
13120 06:50:41.228931 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13122 06:50:41.235244 No KMS driver or no outputs, pipes: 8, outputs: 0
13123 06:50:41.238182 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13124 06:50:41.244856 <14>[ 29.098036] [IGT] kms_vblank: executing
13125 06:50:41.251586 IGT-Version: 1.2<14>[ 29.102955] [IGT] kms_vblank: exiting, ret=77
13126 06:50:41.255101 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13127 06:50:41.258332 Opened device: /dev/dri/card0
13128 06:50:41.268789 No KMS driv<8>[ 29.115465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13129 06:50:41.269102 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13131 06:50:41.271653 er or no outputs, pipes: 8, outputs: 0
13132 06:50:41.278348 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13133 06:50:41.284819 <14>[ 29.137827] [IGT] kms_vblank: executing
13134 06:50:41.291545 IGT-Version: 1.2<14>[ 29.142636] [IGT] kms_vblank: exiting, ret=77
13135 06:50:41.296063 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13136 06:50:41.305255 Opened dev<8>[ 29.153042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13137 06:50:41.305388 ice: /dev/dri/card0
13138 06:50:41.305636 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13140 06:50:41.311651 No KMS driver or no outputs, pipes: 8, outputs: 0
13141 06:50:41.318185 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13142 06:50:41.321660 <14>[ 29.174620] [IGT] kms_vblank: executing
13143 06:50:41.328341 IGT-Version: 1.2<14>[ 29.179594] [IGT] kms_vblank: exiting, ret=77
13144 06:50:41.331537 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13145 06:50:41.341817 Opened dev<8>[ 29.189829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13146 06:50:41.341954 ice: /dev/dri/card0
13147 06:50:41.342199 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13149 06:50:41.348096 No KMS driver or no outputs, pipes: 8, outputs: 0
13150 06:50:41.351780 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13151 06:50:41.358275 <14>[ 29.210664] [IGT] kms_vblank: executing
13152 06:50:41.361464 IGT-Version: 1.2<14>[ 29.215397] [IGT] kms_vblank: exiting, ret=77
13153 06:50:41.368226 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13154 06:50:41.374566 Opened dev<8>[ 29.225845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13155 06:50:41.374857 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13157 06:50:41.377939 ice: /dev/dri/card0
13158 06:50:41.380996 No KMS driver or no outputs, pipes: 8, outputs: 0
13159 06:50:41.387738 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13160 06:50:41.391019 <14>[ 29.246133] [IGT] kms_vblank: executing
13161 06:50:41.398063 IGT-Version: 1.2<14>[ 29.250990] [IGT] kms_vblank: exiting, ret=77
13162 06:50:41.404431 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13163 06:50:41.411345 Opened dev<8>[ 29.261374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13164 06:50:41.411672 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13166 06:50:41.414381 ice: /dev/dri/card0
13167 06:50:41.417749 No KMS driver or no outputs, pipes: 8, outputs: 0
13168 06:50:41.424184 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13169 06:50:41.427519 <14>[ 29.282162] [IGT] kms_vblank: executing
13170 06:50:41.434038 IGT-Version: 1.2<14>[ 29.287048] [IGT] kms_vblank: exiting, ret=77
13171 06:50:41.437423 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13172 06:50:41.447439 Opened dev<8>[ 29.297336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13173 06:50:41.447741 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13175 06:50:41.450838 ice: /dev/dri/card0
13176 06:50:41.454292 No KMS driver or no outputs, pipes: 8, outputs: 0
13177 06:50:41.457364 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13178 06:50:41.464783 <14>[ 29.317852] [IGT] kms_vblank: executing
13179 06:50:41.471816 IGT-Version: 1.2<14>[ 29.322651] [IGT] kms_vblank: exiting, ret=77
13180 06:50:41.474496 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13181 06:50:41.484433 Opened dev<8>[ 29.332980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13182 06:50:41.484563 ice: /dev/dri/card0
13183 06:50:41.484833 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13185 06:50:41.491540 No KMS driver or no outputs, pipes: 8, outputs: 0
13186 06:50:41.494315 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13187 06:50:41.501974 <14>[ 29.354035] [IGT] kms_vblank: executing
13188 06:50:41.508191 IGT-Version: 1.2<14>[ 29.359019] [IGT] kms_vblank: exiting, ret=77
13189 06:50:41.511206 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13190 06:50:41.518135 Opened dev<8>[ 29.369154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13191 06:50:41.518428 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13193 06:50:41.522100 ice: /dev/dri/card0
13194 06:50:41.524893 No KMS driver or no outputs, pipes: 8, outputs: 0
13195 06:50:41.531184 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13196 06:50:41.534618 <14>[ 29.389274] [IGT] kms_vblank: executing
13197 06:50:41.541028 IGT-Version: 1.2<14>[ 29.394078] [IGT] kms_vblank: exiting, ret=77
13198 06:50:41.548277 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13199 06:50:41.554155 Opened dev<8>[ 29.404409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13200 06:50:41.554427 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13202 06:50:41.557541 ice: /dev/dri/card0
13203 06:50:41.561077 No KMS driver or no outputs, pipes: 8, outputs: 0
13204 06:50:41.567392 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13205 06:50:41.571096 <14>[ 29.425283] [IGT] kms_vblank: executing
13206 06:50:41.577595 IGT-Version: 1.2<14>[ 29.430010] [IGT] kms_vblank: exiting, ret=77
13207 06:50:41.581325 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13208 06:50:41.590922 Opened dev<8>[ 29.440531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13209 06:50:41.591234 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13211 06:50:41.594249 ice: /dev/dri/card0
13212 06:50:41.597592 No KMS driver or no outputs, pipes: 8, outputs: 0
13213 06:50:41.601322 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13214 06:50:41.607782 <14>[ 29.460917] [IGT] kms_vblank: executing
13215 06:50:41.614511 IGT-Version: 1.2<14>[ 29.465656] [IGT] kms_vblank: exiting, ret=77
13216 06:50:41.617896 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13217 06:50:41.627951 Opened dev<8>[ 29.475794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13218 06:50:41.628084 ice: /dev/dri/card0
13219 06:50:41.628355 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13221 06:50:41.634695 No KMS driver or no outputs, pipes: 8, outputs: 0
13222 06:50:41.637639 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13223 06:50:41.648053 <14>[ 29.501320] [IGT] kms_vblank: executing
13224 06:50:41.655131 IGT-Version: 1.2<14>[ 29.506071] [IGT] kms_vblank: exiting, ret=77
13225 06:50:41.658533 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13226 06:50:41.664703 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13228 06:50:41.667875 Opened dev<8>[ 29.516601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13229 06:50:41.667956 ice: /dev/dri/card0
13230 06:50:41.671240 No KMS driver or no outputs, pipes: 8, outputs: 0
13231 06:50:41.678244 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13232 06:50:41.681273 <14>[ 29.536418] [IGT] kms_vblank: executing
13233 06:50:41.688283 IGT-Version: 1.2<14>[ 29.541130] [IGT] kms_vblank: exiting, ret=77
13234 06:50:41.694633 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13235 06:50:41.701543 Opened dev<8>[ 29.551551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13236 06:50:41.701840 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13238 06:50:41.704967 ice: /dev/dri/card0
13239 06:50:41.708417 No KMS driver or no outputs, pipes: 8, outputs: 0
13240 06:50:41.714799 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13241 06:50:41.718293 <14>[ 29.572332] [IGT] kms_vblank: executing
13242 06:50:41.724489 IGT-Version: 1.2<14>[ 29.577042] [IGT] kms_vblank: exiting, ret=77
13243 06:50:41.727888 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13244 06:50:41.738157 Opened dev<8>[ 29.587320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13245 06:50:41.738481 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13247 06:50:41.741007 ice: /dev/dri/card0
13248 06:50:41.744587 No KMS driver or no outputs, pipes: 8, outputs: 0
13249 06:50:41.747606 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13250 06:50:41.754728 <14>[ 29.607969] [IGT] kms_vblank: executing
13251 06:50:41.761252 IGT-Version: 1.2<14>[ 29.612708] [IGT] kms_vblank: exiting, ret=77
13252 06:50:41.764899 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13253 06:50:41.774599 Opened dev<8>[ 29.623316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13254 06:50:41.774724 ice: /dev/dri/card0
13255 06:50:41.774967 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13257 06:50:41.781188 No KMS driver or no outputs, pipes: 8, outputs: 0
13258 06:50:41.784908 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13259 06:50:41.791880 <14>[ 29.643903] [IGT] kms_vblank: executing
13260 06:50:41.795080 IGT-Version: 1.2<14>[ 29.648657] [IGT] kms_vblank: exiting, ret=77
13261 06:50:41.801809 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13262 06:50:41.808391 Opened dev<8>[ 29.659238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13263 06:50:41.808699 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13265 06:50:41.811242 ice: /dev/dri/card0
13266 06:50:41.814846 No KMS driver or no outputs, pipes: 8, outputs: 0
13267 06:50:41.818167 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13268 06:50:41.826916 <14>[ 29.679901] [IGT] kms_vblank: executing
13269 06:50:41.833433 IGT-Version: 1.2<14>[ 29.684631] [IGT] kms_vblank: exiting, ret=77
13270 06:50:41.836712 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13271 06:50:41.846900 Opened dev<8>[ 29.695371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13272 06:50:41.847066 ice: /dev/dri/card0
13273 06:50:41.847343 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13275 06:50:41.853528 No KMS driver or no outputs, pipes: 8, outputs: 0
13276 06:50:41.856856 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13277 06:50:41.860074 <14>[ 29.715535] [IGT] kms_vblank: executing
13278 06:50:41.866979 IGT-Version: 1.2<14>[ 29.720294] [IGT] kms_vblank: exiting, ret=77
13279 06:50:41.873881 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13280 06:50:41.880641 Opened dev<8>[ 29.730859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13281 06:50:41.880968 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13283 06:50:41.883312 ice: /dev/dri/card0
13284 06:50:41.886809 No KMS driver or no outputs, pipes: 8, outputs: 0
13285 06:50:41.893234 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13286 06:50:41.896733 <14>[ 29.751561] [IGT] kms_vblank: executing
13287 06:50:41.903452 IGT-Version: 1.2<14>[ 29.756302] [IGT] kms_vblank: exiting, ret=77
13288 06:50:41.909815 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13289 06:50:41.916848 Opened dev<8>[ 29.766792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13290 06:50:41.917175 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13292 06:50:41.920460 ice: /dev/dri/card0
13293 06:50:41.923166 No KMS driver or no outputs, pipes: 8, outputs: 0
13294 06:50:41.929823 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13295 06:50:41.933224 <14>[ 29.788315] [IGT] kms_vblank: executing
13296 06:50:41.940246 IGT-Version: 1.2<14>[ 29.793108] [IGT] kms_vblank: exiting, ret=77
13297 06:50:41.946582 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13298 06:50:41.953171 Opened dev<8>[ 29.803593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13299 06:50:41.953488 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13301 06:50:41.956293 ice: /dev/dri/card0
13302 06:50:41.959765 No KMS driver or no outputs, pipes: 8, outputs: 0
13303 06:50:41.966488 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13304 06:50:41.969758 <14>[ 29.824683] [IGT] kms_vblank: executing
13305 06:50:41.976262 IGT-Version: 1.2<14>[ 29.829453] [IGT] kms_vblank: exiting, ret=77
13306 06:50:41.983278 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13307 06:50:41.990198 Opened dev<8>[ 29.839657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13308 06:50:41.990521 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13310 06:50:41.993215 ice: /dev/dri/card0
13311 06:50:41.996485 No KMS driver or no outputs, pipes: 8, outputs: 0
13312 06:50:42.002695 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13313 06:50:42.006219 <14>[ 29.860830] [IGT] kms_vblank: executing
13314 06:50:42.012998 IGT-Version: 1.2<14>[ 29.866345] [IGT] kms_vblank: exiting, ret=77
13315 06:50:42.019699 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13316 06:50:42.029566 Opened dev<8>[ 29.876872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13317 06:50:42.029701 ice: /dev/dri/card0
13318 06:50:42.029948 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13320 06:50:42.036153 No KMS driver or no outputs, pipes: 8, outputs: 0
13321 06:50:42.039814 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13322 06:50:42.042604 <14>[ 29.897806] [IGT] kms_vblank: executing
13323 06:50:42.049149 IGT-Version: 1.2<14>[ 29.902976] [IGT] kms_vblank: exiting, ret=77
13324 06:50:42.056246 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13325 06:50:42.065987 Opened dev<8>[ 29.913447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13326 06:50:42.066123 ice: /dev/dri/card0
13327 06:50:42.066371 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13329 06:50:42.072632 No KMS driver or no outputs, pipes: 8, outputs: 0
13330 06:50:42.075813 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13331 06:50:42.093648 <14>[ 29.946798] [IGT] kms_vblank: executing
13332 06:50:42.100706 IGT-Version: 1.2<14>[ 29.951922] [IGT] kms_vblank: exiting, ret=77
13333 06:50:42.103979 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13334 06:50:42.113644 Opened device: /dev/dri/ca<8>[ 29.963746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13335 06:50:42.113779 rd0
13336 06:50:42.114027 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13338 06:50:42.120036 No KMS driver or no outputs, pipes: 8, outputs: 0
13339 06:50:42.123678 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13340 06:50:42.132282 <14>[ 29.985167] [IGT] kms_vblank: executing
13341 06:50:42.138838 IGT-Version: 1.2<14>[ 29.989958] [IGT] kms_vblank: exiting, ret=77
13342 06:50:42.141912 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13343 06:50:42.152654 Opened dev<8>[ 30.000251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13344 06:50:42.152786 ice: /dev/dri/card0
13345 06:50:42.153030 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13347 06:50:42.158239 No KMS driver or no outputs, pipes: 8, outputs: 0
13348 06:50:42.161543 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13349 06:50:42.172064 <14>[ 30.025182] [IGT] kms_vblank: executing
13350 06:50:42.178900 IGT-Version: 1.2<14>[ 30.029923] [IGT] kms_vblank: exiting, ret=77
13351 06:50:42.181787 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13352 06:50:42.192300 Opened dev<8>[ 30.040366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13353 06:50:42.192715 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13355 06:50:42.195115 ice: /dev/dri/card0
13356 06:50:42.199009 No KMS driver or no outputs, pipes: 8, outputs: 0
13357 06:50:42.205289 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13358 06:50:42.208656 <14>[ 30.061652] [IGT] kms_vblank: executing
13359 06:50:42.215849 IGT-Version: 1.2<14>[ 30.067178] [IGT] kms_vblank: exiting, ret=77
13360 06:50:42.218942 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13361 06:50:42.228500 Opened dev<8>[ 30.077501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13362 06:50:42.228828 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13364 06:50:42.232081 ice: /dev/dri/card0
13365 06:50:42.235267 No KMS driver or no outputs, pipes: 8, outputs: 0
13366 06:50:42.241814 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13367 06:50:42.245092 <14>[ 30.099708] [IGT] kms_vblank: executing
13368 06:50:42.251726 IGT-Version: 1.2<14>[ 30.104439] [IGT] kms_vblank: exiting, ret=77
13369 06:50:42.255530 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13370 06:50:42.265088 Opened dev<8>[ 30.115008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13371 06:50:42.265410 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13373 06:50:42.268512 ice: /dev/dri/card0
13374 06:50:42.271960 No KMS driver or no outputs, pipes: 8, outputs: 0
13375 06:50:42.275031 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13376 06:50:42.282168 <14>[ 30.135620] [IGT] kms_vblank: executing
13377 06:50:42.289108 IGT-Version: 1.2<14>[ 30.140377] [IGT] kms_vblank: exiting, ret=77
13378 06:50:42.292746 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13379 06:50:42.299200 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13381 06:50:42.302237 Opened dev<8>[ 30.150865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13382 06:50:42.302347 ice: /dev/dri/card0
13383 06:50:42.305468 No KMS driver or no outputs, pipes: 8, outputs: 0
13384 06:50:42.312388 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13385 06:50:42.318698 <14>[ 30.171524] [IGT] kms_vblank: executing
13386 06:50:42.322140 IGT-Version: 1.2<14>[ 30.176253] [IGT] kms_vblank: exiting, ret=77
13387 06:50:42.328854 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13388 06:50:42.335604 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13390 06:50:42.338531 Opened dev<8>[ 30.186755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13391 06:50:42.338643 ice: /dev/dri/card0
13392 06:50:42.342011 No KMS driver or no outputs, pipes: 8, outputs: 0
13393 06:50:42.348424 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13394 06:50:42.351895 <14>[ 30.207418] [IGT] kms_vblank: executing
13395 06:50:42.358656 IGT-Version: 1.2<14>[ 30.212165] [IGT] kms_vblank: exiting, ret=77
13396 06:50:42.365478 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13397 06:50:42.371601 Opened dev<8>[ 30.222608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13398 06:50:42.371912 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13400 06:50:42.375656 ice: /dev/dri/card0
13401 06:50:42.378377 No KMS driver or no outputs, pipes: 8, outputs: 0
13402 06:50:42.385024 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13403 06:50:42.388390 <14>[ 30.242977] [IGT] kms_vblank: executing
13404 06:50:42.395250 IGT-Version: 1.2<14>[ 30.247884] [IGT] kms_vblank: exiting, ret=77
13405 06:50:42.402153 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13406 06:50:42.408202 Opened dev<8>[ 30.258274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13407 06:50:42.408527 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13409 06:50:42.411628 ice: /dev/dri/card0
13410 06:50:42.414894 No KMS driver or no outputs, pipes: 8, outputs: 0
13411 06:50:42.421634 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13412 06:50:42.424764 <14>[ 30.279427] [IGT] kms_vblank: executing
13413 06:50:42.431615 IGT-Version: 1.2<14>[ 30.284137] [IGT] kms_vblank: exiting, ret=77
13414 06:50:42.434738 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13415 06:50:42.444907 Opened dev<8>[ 30.294809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13416 06:50:42.445245 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13418 06:50:42.447631 ice: /dev/dri/card0
13419 06:50:42.451006 No KMS driver or no outputs, pipes: 8, outputs: 0
13420 06:50:42.454357 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13421 06:50:42.462072 <14>[ 30.315017] [IGT] kms_vblank: executing
13422 06:50:42.468743 IGT-Version: 1.2<14>[ 30.319753] [IGT] kms_vblank: exiting, ret=77
13423 06:50:42.471927 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13424 06:50:42.481863 Opened dev<8>[ 30.330201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13425 06:50:42.482002 ice: /dev/dri/card0
13426 06:50:42.482251 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13428 06:50:42.488258 No KMS driver or no outputs, pipes: 8, outputs: 0
13429 06:50:42.491585 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13430 06:50:42.498586 <14>[ 30.351023] [IGT] kms_vblank: executing
13431 06:50:42.501380 IGT-Version: 1.2<14>[ 30.355757] [IGT] kms_vblank: exiting, ret=77
13432 06:50:42.508418 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13433 06:50:42.517935 Opened dev<8>[ 30.366102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13434 06:50:42.518075 ice: /dev/dri/card0
13435 06:50:42.518321 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13437 06:50:42.522029 No KMS driver or no outputs, pipes: 8, outputs: 0
13438 06:50:42.528594 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13439 06:50:42.532073 <14>[ 30.387077] [IGT] kms_vblank: executing
13440 06:50:42.538385 IGT-Version: 1.2<14>[ 30.391818] [IGT] kms_vblank: exiting, ret=77
13441 06:50:42.544978 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13442 06:50:42.551775 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13444 06:50:42.554993 Opened dev<8>[ 30.402271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13445 06:50:42.555093 ice: /dev/dri/card0
13446 06:50:42.558173 No KMS driver or no outputs, pipes: 8, outputs: 0
13447 06:50:42.565216 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13448 06:50:42.567837 <14>[ 30.423541] [IGT] kms_vblank: executing
13449 06:50:42.574661 IGT-Version: 1.2<14>[ 30.428270] [IGT] kms_vblank: exiting, ret=77
13450 06:50:42.581308 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13451 06:50:42.588024 Opened dev<8>[ 30.438755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13452 06:50:42.588354 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13454 06:50:42.591520 ice: /dev/dri/card0
13455 06:50:42.595045 No KMS driver or no outputs, pipes: 8, outputs: 0
13456 06:50:42.598228 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13457 06:50:42.606077 <14>[ 30.458945] [IGT] kms_vblank: executing
13458 06:50:42.612673 IGT-Version: 1.2<14>[ 30.463700] [IGT] kms_vblank: exiting, ret=77
13459 06:50:42.615414 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13460 06:50:42.625635 Opened dev<8>[ 30.473975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13461 06:50:42.625773 ice: /dev/dri/card0
13462 06:50:42.626019 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13464 06:50:42.632440 No KMS driver or no outputs, pipes: 8, outputs: 0
13465 06:50:42.636115 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13466 06:50:42.641953 <14>[ 30.494784] [IGT] kms_vblank: executing
13467 06:50:42.645462 IGT-Version: 1.2<14>[ 30.499648] [IGT] kms_vblank: exiting, ret=77
13468 06:50:42.652037 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13469 06:50:42.658790 Opened dev<8>[ 30.509942] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13470 06:50:42.659081 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13472 06:50:42.662098 ice: /dev/dri/card0
13473 06:50:42.665689 No KMS driver or no outputs, pipes: 8, outputs: 0
13474 06:50:42.672375 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13475 06:50:42.675436 <14>[ 30.530654] [IGT] kms_vblank: executing
13476 06:50:42.682183 IGT-Version: 1.2<14>[ 30.535404] [IGT] kms_vblank: exiting, ret=77
13477 06:50:42.688936 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13478 06:50:42.695348 Opened dev<8>[ 30.546030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13479 06:50:42.695642 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13481 06:50:42.698317 ice: /dev/dri/card0
13482 06:50:42.702047 No KMS driver or no outputs, pipes: 8, outputs: 0
13483 06:50:42.708969 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13484 06:50:42.712353 <14>[ 30.566898] [IGT] kms_vblank: executing
13485 06:50:42.718517 IGT-Version: 1.2<14>[ 30.571662] [IGT] kms_vblank: exiting, ret=77
13486 06:50:42.724946 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13487 06:50:42.731893 Opened dev<8>[ 30.582022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13488 06:50:42.732198 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13490 06:50:42.735025 ice: /dev/dri/card0
13491 06:50:42.738371 No KMS driver or no outputs, pipes: 8, outputs: 0
13492 06:50:42.741552 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13493 06:50:42.749305 <14>[ 30.602683] [IGT] kms_vblank: executing
13494 06:50:42.755864 IGT-Version: 1.2<14>[ 30.607461] [IGT] kms_vblank: exiting, ret=77
13495 06:50:42.759721 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13496 06:50:42.769278 Opened dev<8>[ 30.617805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13497 06:50:42.769415 ice: /dev/dri/card0
13498 06:50:42.769660 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13500 06:50:42.775901 No KMS driver or no outputs, pipes: 8, outputs: 0
13501 06:50:42.779722 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13502 06:50:42.782786 <14>[ 30.638303] [IGT] kms_vblank: executing
13503 06:50:42.789987 IGT-Version: 1.2<14>[ 30.643187] [IGT] kms_vblank: exiting, ret=77
13504 06:50:42.795837 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13505 06:50:42.803327 Opened dev<8>[ 30.653709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13506 06:50:42.803631 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13508 06:50:42.805948 ice: /dev/dri/card0
13509 06:50:42.809447 No KMS driver or no outputs, pipes: 8, outputs: 0
13510 06:50:42.815978 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13511 06:50:42.819826 <14>[ 30.674448] [IGT] kms_vblank: executing
13512 06:50:42.826160 IGT-Version: 1.2<14>[ 30.679194] [IGT] kms_vblank: exiting, ret=77
13513 06:50:42.833283 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13514 06:50:42.839421 Opened dev<8>[ 30.689652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13515 06:50:42.839718 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13517 06:50:42.842704 ice: /dev/dri/card0
13518 06:50:42.846165 No KMS driver or no outputs, pipes: 8, outputs: 0
13519 06:50:42.852719 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13520 06:50:42.856078 <14>[ 30.710870] [IGT] kms_vblank: executing
13521 06:50:42.862653 IGT-Version: 1.2<14>[ 30.715629] [IGT] kms_vblank: exiting, ret=77
13522 06:50:42.869392 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13523 06:50:42.875904 Opened dev<8>[ 30.725883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13524 06:50:42.876195 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13526 06:50:42.879656 ice: /dev/dri/card0
13527 06:50:42.882947 No KMS driver or no outputs, pipes: 8, outputs: 0
13528 06:50:42.889049 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13529 06:50:42.892527 <14>[ 30.747171] [IGT] kms_vblank: executing
13530 06:50:42.899079 IGT-Version: 1.2<14>[ 30.751925] [IGT] kms_vblank: exiting, ret=77
13531 06:50:42.902629 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13532 06:50:42.912207 Opened dev<8>[ 30.762367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13533 06:50:42.912519 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13535 06:50:42.915423 ice: /dev/dri/card0
13536 06:50:42.919208 No KMS driver or no outputs, pipes: 8, outputs: 0
13537 06:50:42.925773 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13538 06:50:42.929123 <14>[ 30.783931] [IGT] kms_vblank: executing
13539 06:50:42.935454 IGT-Version: 1.2<14>[ 30.788672] [IGT] kms_vblank: exiting, ret=77
13540 06:50:42.941984 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13541 06:50:42.948562 Opened dev<8>[ 30.799164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13542 06:50:42.948864 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13544 06:50:42.952689 ice: /dev/dri/card0
13545 06:50:42.955240 No KMS driver or no outputs, pipes: 8, outputs: 0
13546 06:50:42.962008 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13547 06:50:42.965510 <14>[ 30.820462] [IGT] kms_vblank: executing
13548 06:50:42.971923 IGT-Version: 1.2<14>[ 30.825241] [IGT] kms_vblank: exiting, ret=77
13549 06:50:42.978980 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13550 06:50:42.985453 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13552 06:50:42.988766 Opened dev<8>[ 30.835511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13553 06:50:42.988855 ice: /dev/dri/card0
13554 06:50:42.992472 No KMS driver or no outputs, pipes: 8, outputs: 0
13555 06:50:42.998566 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13556 06:50:43.005217 <14>[ 30.857139] [IGT] kms_vblank: executing
13557 06:50:43.008987 IGT-Version: 1.2<14>[ 30.862561] [IGT] kms_vblank: exiting, ret=77
13558 06:50:43.015370 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13559 06:50:43.025069 Opened dev<8>[ 30.873148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13560 06:50:43.025236 ice: /dev/dri/card0
13561 06:50:43.025485 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13563 06:50:43.032175 No KMS driver or no outputs, pipes: 8, outputs: 0
13564 06:50:43.034993 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13565 06:50:43.038333 <14>[ 30.894191] [IGT] kms_vblank: executing
13566 06:50:43.045034 IGT-Version: 1.2<14>[ 30.899096] [IGT] kms_vblank: exiting, ret=77
13567 06:50:43.052007 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13568 06:50:43.059404 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13570 06:50:43.061936 Opened dev<8>[ 30.909423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13571 06:50:43.062023 ice: /dev/dri/card0
13572 06:50:43.065143 No KMS driver or no outputs, pipes: 8, outputs: 0
13573 06:50:43.071763 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13574 06:50:43.075251 <14>[ 30.931061] [IGT] kms_vblank: executing
13575 06:50:43.082026 IGT-Version: 1.2<14>[ 30.935808] [IGT] kms_vblank: exiting, ret=77
13576 06:50:43.089042 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13577 06:50:43.098779 Opened dev<8>[ 30.946187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13578 06:50:43.098912 ice: /dev/dri/card0
13579 06:50:43.099161 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13581 06:50:43.104881 No KMS driver or no outputs, pipes: 8, outputs: 0
13582 06:50:43.108352 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13583 06:50:43.115436 <14>[ 30.968220] [IGT] kms_vblank: executing
13584 06:50:43.122220 IGT-Version: 1.2<14>[ 30.972950] [IGT] kms_vblank: exiting, ret=77
13585 06:50:43.125119 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13586 06:50:43.134832 Opened dev<8>[ 30.983158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13587 06:50:43.134964 ice: /dev/dri/card0
13588 06:50:43.135210 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13590 06:50:43.141610 No KMS driver or no outputs, pipes: 8, outputs: 0
13591 06:50:43.147887 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13592 06:50:43.151505 <14>[ 31.004356] [IGT] kms_vblank: executing
13593 06:50:43.158177 IGT-Version: 1.2<14>[ 31.010040] [IGT] kms_vblank: exiting, ret=77
13594 06:50:43.161324 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13595 06:50:43.171527 Opened dev<8>[ 31.020312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13596 06:50:43.171660 ice: /dev/dri/card0
13597 06:50:43.171905 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13599 06:50:43.178155 No KMS driver or no outputs, pipes: 8, outputs: 0
13600 06:50:43.182133 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13601 06:50:43.187931 <14>[ 31.040743] [IGT] kms_vblank: executing
13602 06:50:43.190990 IGT-Version: 1.2<14>[ 31.045478] [IGT] kms_vblank: exiting, ret=77
13603 06:50:43.197991 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13604 06:50:43.204388 Opened dev<8>[ 31.055942] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13605 06:50:43.204693 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13607 06:50:43.207865 ice: /dev/dri/card0
13608 06:50:43.211340 No KMS driver or no outputs, pipes: 8, outputs: 0
13609 06:50:43.218003 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13610 06:50:43.220981 <14>[ 31.076032] [IGT] kms_vblank: executing
13611 06:50:43.227987 IGT-Version: 1.2<14>[ 31.080785] [IGT] kms_vblank: exiting, ret=77
13612 06:50:43.231154 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13613 06:50:43.241032 Opened dev<8>[ 31.091269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13614 06:50:43.241339 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13616 06:50:43.244405 ice: /dev/dri/card0
13617 06:50:43.247843 No KMS driver or no outputs, pipes: 8, outputs: 0
13618 06:50:43.251297 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13619 06:50:43.258758 <14>[ 31.111917] [IGT] kms_vblank: executing
13620 06:50:43.266027 IGT-Version: 1.2<14>[ 31.116828] [IGT] kms_vblank: exiting, ret=77
13621 06:50:43.268805 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13622 06:50:43.278568 Opened dev<8>[ 31.127361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13623 06:50:43.278707 ice: /dev/dri/card0
13624 06:50:43.278959 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13626 06:50:43.285256 No KMS driver or no outputs, pipes: 8, outputs: 0
13627 06:50:43.288953 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13628 06:50:43.295349 <14>[ 31.147649] [IGT] kms_vblank: executing
13629 06:50:43.298487 IGT-Version: 1.2<14>[ 31.152353] [IGT] kms_vblank: exiting, ret=77
13630 06:50:43.305136 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13631 06:50:43.312246 Opened dev<8>[ 31.162866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13632 06:50:43.312546 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13634 06:50:43.314947 ice: /dev/dri/card0
13635 06:50:43.318237 No KMS driver or no outputs, pipes: 8, outputs: 0
13636 06:50:43.325286 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13637 06:50:43.328637 <14>[ 31.183873] [IGT] kms_vblank: executing
13638 06:50:43.335380 IGT-Version: 1.2<14>[ 31.188607] [IGT] kms_vblank: exiting, ret=77
13639 06:50:43.341831 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13640 06:50:43.348163 Opened dev<8>[ 31.199075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13641 06:50:43.348457 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13643 06:50:43.351724 ice: /dev/dri/card0
13644 06:50:43.355413 No KMS driver or no outputs, pipes: 8, outputs: 0
13645 06:50:43.358041 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13646 06:50:43.366231 <14>[ 31.219810] [IGT] kms_vblank: executing
13647 06:50:43.373576 IGT-Version: 1.2<14>[ 31.224668] [IGT] kms_vblank: exiting, ret=77
13648 06:50:43.376663 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13649 06:50:43.386607 Opened dev<8>[ 31.235221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13650 06:50:43.386743 ice: /dev/dri/card0
13651 06:50:43.386992 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13653 06:50:43.393044 No KMS driver or no outputs, pipes: 8, outputs: 0
13654 06:50:43.396649 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13655 06:50:43.400281 <14>[ 31.255637] [IGT] kms_vblank: executing
13656 06:50:43.406574 IGT-Version: 1.2<14>[ 31.260441] [IGT] kms_vblank: exiting, ret=77
13657 06:50:43.413827 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13658 06:50:43.420050 Opened dev<8>[ 31.271113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13659 06:50:43.420348 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13661 06:50:43.423114 ice: /dev/dri/card0
13662 06:50:43.426328 No KMS driver or no outputs, pipes: 8, outputs: 0
13663 06:50:43.433151 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13664 06:50:43.436221 <14>[ 31.291586] [IGT] kms_vblank: executing
13665 06:50:43.442795 IGT-Version: 1.2<14>[ 31.296305] [IGT] kms_vblank: exiting, ret=77
13666 06:50:43.449642 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13667 06:50:43.456378 Opened dev<8>[ 31.306820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13668 06:50:43.456672 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13670 06:50:43.459533 ice: /dev/dri/card0
13671 06:50:43.462925 No KMS driver or no outputs, pipes: 8, outputs: 0
13672 06:50:43.469856 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13673 06:50:43.473359 <14>[ 31.327805] [IGT] kms_vblank: executing
13674 06:50:43.480152 IGT-Version: 1.2<14>[ 31.332615] [IGT] kms_vblank: exiting, ret=77
13675 06:50:43.483288 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13676 06:50:43.492964 Opened dev<8>[ 31.343100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13677 06:50:43.493094 ice: /dev/dri/card0
13678 06:50:43.493340 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13680 06:50:43.499532 No KMS driver or no outputs, pipes: 8, outputs: 0
13681 06:50:43.503568 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13682 06:50:43.510241 <14>[ 31.363622] [IGT] kms_vblank: executing
13683 06:50:43.516680 IGT-Version: 1.2<14>[ 31.368426] [IGT] kms_vblank: exiting, ret=77
13684 06:50:43.520211 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13685 06:50:43.530367 Opened dev<8>[ 31.379115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13686 06:50:43.530499 ice: /dev/dri/card0
13687 06:50:43.530742 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13689 06:50:43.536737 No KMS driver or no outputs, pipes: 8, outputs: 0
13690 06:50:43.540083 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13691 06:50:43.543828 <14>[ 31.399301] [IGT] kms_vblank: executing
13692 06:50:43.550272 IGT-Version: 1.2<14>[ 31.404122] [IGT] kms_vblank: exiting, ret=77
13693 06:50:43.557022 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13694 06:50:43.563494 Opened dev<8>[ 31.414767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13695 06:50:43.563771 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13697 06:50:43.567257 ice: /dev/dri/card0
13698 06:50:43.569943 No KMS driver or no outputs, pipes: 8, outputs: 0
13699 06:50:43.576882 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13700 06:50:43.580062 <14>[ 31.434907] [IGT] kms_vblank: executing
13701 06:50:43.586924 IGT-Version: 1.2<14>[ 31.439657] [IGT] kms_vblank: exiting, ret=77
13702 06:50:43.590345 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13703 06:50:43.600609 Opened dev<8>[ 31.449901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13704 06:50:43.600897 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13706 06:50:43.603511 ice: /dev/dri/card0
13707 06:50:43.607089 No KMS driver or no outputs, pipes: 8, outputs: 0
13708 06:50:43.610293 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13709 06:50:43.617302 <14>[ 31.470775] [IGT] kms_vblank: executing
13710 06:50:43.624228 IGT-Version: 1.2<14>[ 31.475620] [IGT] kms_vblank: exiting, ret=77
13711 06:50:43.627426 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13712 06:50:43.634091 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13714 06:50:43.637077 Opened dev<8>[ 31.486000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13715 06:50:43.637161 ice: /dev/dri/card0
13716 06:50:43.640580 No KMS driver or no outputs, pipes: 8, outputs: 0
13717 06:50:43.647451 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13718 06:50:43.654348 <14>[ 31.506686] [IGT] kms_vblank: executing
13719 06:50:43.660320 IGT-Version: 1.2<14>[ 31.511587] [IGT] kms_vblank: exiting, ret=77
13720 06:50:43.663910 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13721 06:50:43.670423 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13723 06:50:43.674045 Opened dev<8>[ 31.522096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13724 06:50:43.674130 ice: /dev/dri/card0
13725 06:50:43.677087 No KMS driver or no outputs, pipes: 8, outputs: 0
13726 06:50:43.684897 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13727 06:50:43.687008 <14>[ 31.542073] [IGT] kms_vblank: executing
13728 06:50:43.693781 IGT-Version: 1.2<14>[ 31.547014] [IGT] kms_vblank: exiting, ret=77
13729 06:50:43.700745 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13730 06:50:43.700834 Opened device: /dev/dri/card0
13731 06:50:43.710628 No KMS driv<8>[ 31.559583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13732 06:50:43.710891 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13734 06:50:43.713891 er or no outputs, pipes: 8, outputs: 0
13735 06:50:43.719969 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13736 06:50:43.727653 <14>[ 31.581188] [IGT] kms_vblank: executing
13737 06:50:43.734731 IGT-Version: 1.2<14>[ 31.585950] [IGT] kms_vblank: exiting, ret=77
13738 06:50:43.738069 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13739 06:50:43.747652 Opened dev<8>[ 31.596349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13740 06:50:43.747741 ice: /dev/dri/card0
13741 06:50:43.747983 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13743 06:50:43.753976 No KMS driver or no outputs, pipes: 8, outputs: 0
13744 06:50:43.757444 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13745 06:50:43.765547 <14>[ 31.618169] [IGT] kms_vblank: executing
13746 06:50:43.771844 IGT-Version: 1.2<14>[ 31.622990] [IGT] kms_vblank: exiting, ret=77
13747 06:50:43.774994 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13748 06:50:43.784617 Opened dev<8>[ 31.633242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13749 06:50:43.784710 ice: /dev/dri/card0
13750 06:50:43.784953 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13752 06:50:43.791315 No KMS driver or no outputs, pipes: 8, outputs: 0
13753 06:50:43.795007 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13754 06:50:43.801740 <14>[ 31.654077] [IGT] kms_vblank: executing
13755 06:50:43.805033 IGT-Version: 1.2<14>[ 31.658962] [IGT] kms_vblank: exiting, ret=77
13756 06:50:43.811417 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13757 06:50:43.821562 Opened dev<8>[ 31.669331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13758 06:50:43.821657 ice: /dev/dri/card0
13759 06:50:43.821899 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13761 06:50:43.828239 No KMS driver or no outputs, pipes: 8, outputs: 0
13762 06:50:43.831198 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13763 06:50:43.840896 <14>[ 31.694316] [IGT] kms_vblank: executing
13764 06:50:43.847306 IGT-Version: 1.2<14>[ 31.699179] [IGT] kms_vblank: exiting, ret=77
13765 06:50:43.850942 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13766 06:50:43.860798 Opened dev<8>[ 31.709379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13767 06:50:43.861061 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13769 06:50:43.863963 ice: /dev/dri/card0
13770 06:50:43.867504 No KMS driver or no outputs, pipes: 8, outputs: 0
13771 06:50:43.873928 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13772 06:50:43.877332 <14>[ 31.730997] [IGT] kms_vblank: executing
13773 06:50:43.883904 IGT-Version: 1.2<14>[ 31.735739] [IGT] kms_vblank: exiting, ret=77
13774 06:50:43.887367 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13775 06:50:43.897280 Opened dev<8>[ 31.746104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13776 06:50:43.897541 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13778 06:50:43.900516 ice: /dev/dri/card0
13779 06:50:43.903806 No KMS driver or no outputs, pipes: 8, outputs: 0
13780 06:50:43.910707 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13781 06:50:43.914566 <14>[ 31.767913] [IGT] kms_vblank: executing
13782 06:50:43.921067 IGT-Version: 1.2<14>[ 31.772949] [IGT] kms_vblank: exiting, ret=77
13783 06:50:43.924133 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13784 06:50:43.933960 Opened dev<8>[ 31.783468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13785 06:50:43.934224 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13787 06:50:43.937462 ice: /dev/dri/card0
13788 06:50:43.940859 No KMS driver or no outputs, pipes: 8, outputs: 0
13789 06:50:43.947120 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13790 06:50:43.950924 <14>[ 31.804705] [IGT] kms_vblank: executing
13791 06:50:43.957344 IGT-Version: 1.2<14>[ 31.809431] [IGT] kms_vblank: exiting, ret=77
13792 06:50:43.960559 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13793 06:50:43.971189 Opened dev<8>[ 31.819642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13794 06:50:43.971457 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13796 06:50:43.973895 ice: /dev/dri/card0
13797 06:50:43.977245 No KMS driver or no outputs, pipes: 8, outputs: 0
13798 06:50:43.984181 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13799 06:50:43.987592 <14>[ 31.841060] [IGT] kms_vblank: executing
13800 06:50:43.994533 IGT-Version: 1.2<14>[ 31.845908] [IGT] kms_vblank: exiting, ret=77
13801 06:50:43.997709 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13802 06:50:44.007537 Opened dev<8>[ 31.856393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13803 06:50:44.007806 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13805 06:50:44.011030 ice: /dev/dri/card0
13806 06:50:44.013840 No KMS driver or no outputs, pipes: 8, outputs: 0
13807 06:50:44.020800 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13808 06:50:44.024163 <14>[ 31.878019] [IGT] kms_vblank: executing
13809 06:50:44.030748 IGT-Version: 1.2<14>[ 31.883175] [IGT] kms_vblank: exiting, ret=77
13810 06:50:44.033798 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13811 06:50:44.043997 Opened dev<8>[ 31.893631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13812 06:50:44.044257 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13814 06:50:44.047186 ice: /dev/dri/card0
13815 06:50:44.050443 No KMS driver or no outputs, pipes: 8, outputs: 0
13816 06:50:44.057110 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13817 06:50:44.060692 <14>[ 31.915254] [IGT] kms_vblank: executing
13818 06:50:44.067651 IGT-Version: 1.2<14>[ 31.920185] [IGT] kms_vblank: exiting, ret=77
13819 06:50:44.070926 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13820 06:50:44.080259 Opened dev<8>[ 31.930845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13821 06:50:44.080528 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13823 06:50:44.084320 ice: /dev/dri/card0
13824 06:50:44.086894 No KMS driver or no outputs, pipes: 8, outputs: 0
13825 06:50:44.090518 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13826 06:50:44.098037 <14>[ 31.951297] [IGT] kms_vblank: executing
13827 06:50:44.105072 IGT-Version: 1.2<14>[ 31.956055] [IGT] kms_vblank: exiting, ret=77
13828 06:50:44.107996 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13829 06:50:44.117631 Opened dev<8>[ 31.966473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13830 06:50:44.117741 ice: /dev/dri/card0
13831 06:50:44.117984 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13833 06:50:44.124315 No KMS driver or no outputs, pipes: 8, outputs: 0
13834 06:50:44.127286 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13835 06:50:44.130613 <14>[ 31.986748] [IGT] kms_vblank: executing
13836 06:50:44.137557 IGT-Version: 1.2<14>[ 31.991461] [IGT] kms_vblank: exiting, ret=77
13837 06:50:44.144261 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13838 06:50:44.151016 Opened dev<8>[ 32.001836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13839 06:50:44.151275 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13841 06:50:44.154110 ice: /dev/dri/card0
13842 06:50:44.157721 No KMS driver or no outputs, pipes: 8, outputs: 0
13843 06:50:44.164266 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13844 06:50:44.167436 <14>[ 32.020957] [IGT] kms_vblank: executing
13845 06:50:44.173911 IGT-Version: 1.2<14>[ 32.026439] [IGT] kms_vblank: exiting, ret=77
13846 06:50:44.177539 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13847 06:50:44.187519 Opened dev<8>[ 32.036814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13848 06:50:44.187617 ice: /dev/dri/card0
13849 06:50:44.187862 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13851 06:50:44.194323 No KMS driver or no outputs, pipes: 8, outputs: 0
13852 06:50:44.197406 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13853 06:50:44.204531 <14>[ 32.057151] [IGT] kms_vblank: executing
13854 06:50:44.207388 IGT-Version: 1.2<14>[ 32.061909] [IGT] kms_vblank: exiting, ret=77
13855 06:50:44.214345 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13856 06:50:44.224593 Opened dev<8>[ 32.072401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13857 06:50:44.224691 ice: /dev/dri/card0
13858 06:50:44.224933 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13860 06:50:44.230880 No KMS driver or no outputs, pipes: 8, outputs: 0
13861 06:50:44.234129 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13862 06:50:44.237169 <14>[ 32.093013] [IGT] kms_vblank: executing
13863 06:50:44.243814 IGT-Version: 1.2<14>[ 32.097866] [IGT] kms_vblank: exiting, ret=77
13864 06:50:44.250807 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13865 06:50:44.257553 Opened dev<8>[ 32.108428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13866 06:50:44.257820 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13868 06:50:44.260776 ice: /dev/dri/card0
13869 06:50:44.264120 No KMS driver or no outputs, pipes: 8, outputs: 0
13870 06:50:44.266967 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13871 06:50:44.275318 <14>[ 32.128813] [IGT] kms_vblank: executing
13872 06:50:44.281700 IGT-Version: 1.2<14>[ 32.133564] [IGT] kms_vblank: exiting, ret=77
13873 06:50:44.285130 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13874 06:50:44.295162 Opened dev<8>[ 32.143898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13875 06:50:44.295272 ice: /dev/dri/card0
13876 06:50:44.295516 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13878 06:50:44.301935 No KMS driver or no outputs, pipes: 8, outputs: 0
13879 06:50:44.305632 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13880 06:50:44.312153 <14>[ 32.164623] [IGT] kms_vblank: executing
13881 06:50:44.315370 IGT-Version: 1.2<14>[ 32.169331] [IGT] kms_vblank: exiting, ret=77
13882 06:50:44.321924 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13883 06:50:44.328809 Opened dev<8>[ 32.179689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13884 06:50:44.329075 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13886 06:50:44.331651 ice: /dev/dri/card0
13887 06:50:44.335004 No KMS driver or no outputs, pipes: 8, outputs: 0
13888 06:50:44.341923 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13889 06:50:44.346147 <14>[ 32.200753] [IGT] kms_vblank: executing
13890 06:50:44.352089 IGT-Version: 1.2<14>[ 32.205483] [IGT] kms_vblank: exiting, ret=77
13891 06:50:44.359254 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13892 06:50:44.365017 Opened dev<8>[ 32.215820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13893 06:50:44.365300 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13895 06:50:44.368459 ice: /dev/dri/card0
13896 06:50:44.371532 No KMS driver or no outputs, pipes: 8, outputs: 0
13897 06:50:44.378250 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13898 06:50:44.381759 <14>[ 32.237173] [IGT] kms_vblank: executing
13899 06:50:44.388607 IGT-Version: 1.2<14>[ 32.241942] [IGT] kms_vblank: exiting, ret=77
13900 06:50:44.394932 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13901 06:50:44.401533 Opened dev<8>[ 32.252242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13902 06:50:44.401841 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13904 06:50:44.404872 ice: /dev/dri/card0
13905 06:50:44.408781 No KMS driver or no outputs, pipes: 8, outputs: 0
13906 06:50:44.411532 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13907 06:50:44.419580 <14>[ 32.272673] [IGT] kms_vblank: executing
13908 06:50:44.426088 IGT-Version: 1.2<14>[ 32.277376] [IGT] kms_vblank: exiting, ret=77
13909 06:50:44.429557 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13910 06:50:44.439240 Opened dev<8>[ 32.287583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13911 06:50:44.439378 ice: /dev/dri/card0
13912 06:50:44.439625 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13914 06:50:44.445730 No KMS driver or no outputs, pipes: 8, outputs: 0
13915 06:50:44.449092 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13916 06:50:44.452360 <14>[ 32.308307] [IGT] kms_vblank: executing
13917 06:50:44.459539 IGT-Version: 1.2<14>[ 32.313137] [IGT] kms_vblank: exiting, ret=77
13918 06:50:44.466320 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13919 06:50:44.472342 Opened dev<8>[ 32.323627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13920 06:50:44.472650 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13922 06:50:44.475613 ice: /dev/dri/card0
13923 06:50:44.479149 No KMS driver or no outputs, pipes: 8, outputs: 0
13924 06:50:44.485654 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13925 06:50:44.489334 <14>[ 32.344713] [IGT] kms_vblank: executing
13926 06:50:44.495605 IGT-Version: 1.2<14>[ 32.349454] [IGT] kms_vblank: exiting, ret=77
13927 06:50:44.502236 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13928 06:50:44.508993 Opened dev<8>[ 32.360115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13929 06:50:44.509261 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13931 06:50:44.512370 ice: /dev/dri/card0
13932 06:50:44.516056 No KMS driver or no outputs, pipes: 8, outputs: 0
13933 06:50:44.522073 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13934 06:50:44.525516 <14>[ 32.380390] [IGT] kms_vblank: executing
13935 06:50:44.532236 IGT-Version: 1.2<14>[ 32.385143] [IGT] kms_vblank: exiting, ret=77
13936 06:50:44.535623 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13937 06:50:44.546091 Opened dev<8>[ 32.395599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13938 06:50:44.546195 ice: /dev/dri/card0
13939 06:50:44.546457 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13941 06:50:44.551930 No KMS driver or no outputs, pipes: 8, outputs: 0
13942 06:50:44.555278 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13943 06:50:44.563148 <14>[ 32.416103] [IGT] kms_vblank: executing
13944 06:50:44.569304 IGT-Version: 1.2<14>[ 32.420873] [IGT] kms_vblank: exiting, ret=77
13945 06:50:44.572782 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13946 06:50:44.582257 Opened dev<8>[ 32.431297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13947 06:50:44.582367 ice: /dev/dri/card0
13948 06:50:44.582652 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13950 06:50:44.589021 No KMS driver or no outputs, pipes: 8, outputs: 0
13951 06:50:44.592432 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13952 06:50:44.599430 <14>[ 32.452019] [IGT] kms_vblank: executing
13953 06:50:44.602132 IGT-Version: 1.2<14>[ 32.456844] [IGT] kms_vblank: exiting, ret=77
13954 06:50:44.609154 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13955 06:50:44.618862 Opened device: /dev/dri/ca<8>[ 32.468833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13956 06:50:44.618989 rd0
13957 06:50:44.619236 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13959 06:50:44.622557 No KMS driver or no outputs, pipes: 8, outputs: 0
13960 06:50:44.628807 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13961 06:50:44.636177 <14>[ 32.489449] [IGT] kms_vblank: executing
13962 06:50:44.643012 IGT-Version: 1.2<14>[ 32.494215] [IGT] kms_vblank: exiting, ret=77
13963 06:50:44.645720 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13964 06:50:44.655820 Opened dev<8>[ 32.504636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13965 06:50:44.655923 ice: /dev/dri/card0
13966 06:50:44.656168 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13968 06:50:44.662338 No KMS driver or no outputs, pipes: 8, outputs: 0
13969 06:50:44.665476 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13970 06:50:44.673185 <14>[ 32.526044] [IGT] kms_vblank: executing
13971 06:50:44.679527 IGT-Version: 1.2<14>[ 32.530939] [IGT] kms_vblank: exiting, ret=77
13972 06:50:44.682702 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13973 06:50:44.692736 Opened dev<8>[ 32.541267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13974 06:50:44.692825 ice: /dev/dri/card0
13975 06:50:44.693054 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13977 06:50:44.699202 No KMS driver or no outputs, pipes: 8, outputs: 0
13978 06:50:44.702536 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13979 06:50:44.709468 <14>[ 32.562549] [IGT] kms_vblank: executing
13980 06:50:44.715927 IGT-Version: 1.2<14>[ 32.567300] [IGT] kms_vblank: exiting, ret=77
13981 06:50:44.719257 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13982 06:50:44.729286 Opened dev<8>[ 32.577543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13983 06:50:44.729383 ice: /dev/dri/card0
13984 06:50:44.729626 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13986 06:50:44.736068 No KMS driver or no outputs, pipes: 8, outputs: 0
13987 06:50:44.739206 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13988 06:50:44.746267 <14>[ 32.599863] [IGT] kms_vblank: executing
13989 06:50:44.752820 IGT-Version: 1.2<14>[ 32.604625] [IGT] kms_vblank: exiting, ret=77
13990 06:50:44.756435 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13991 06:50:44.766080 Opened dev<8>[ 32.615216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13992 06:50:44.766177 ice: /dev/dri/card0
13993 06:50:44.766424 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13995 06:50:44.773120 No KMS driver or no outputs, pipes: 8, outputs: 0
13996 06:50:44.779923 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13997 06:50:44.782985 <14>[ 32.636611] [IGT] kms_vblank: executing
13998 06:50:44.789580 IGT-Version: 1.2<14>[ 32.641368] [IGT] kms_vblank: exiting, ret=77
13999 06:50:44.792917 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
14000 06:50:44.803018 Opened dev<8>[ 32.651760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
14001 06:50:44.803308 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
14003 06:50:44.806030 ice: /dev/dri/card0
14004 06:50:44.809409 No KMS driver or no outputs, pipes: 8, outputs: 0
14005 06:50:44.816104 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
14006 06:50:44.819680 <14>[ 32.673483] [IGT] kms_vblank: executing
14007 06:50:44.826325 IGT-Version: 1.2<14>[ 32.678780] [IGT] kms_vblank: exiting, ret=77
14008 06:50:44.829671 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
14009 06:50:44.839469 Opened dev<8>[ 32.688828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
14010 06:50:44.839737 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
14012 06:50:44.842622 ice: /dev/dri/card0
14013 06:50:44.846213 No KMS driver or no outputs, pipes: 8, outputs: 0
14014 06:50:44.852554 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
14015 06:50:44.856611 <14>[ 32.710462] [IGT] kms_vblank: executing
14016 06:50:44.862810 IGT-Version: 1.2<14>[ 32.715284] [IGT] kms_vblank: exiting, ret=77
14017 06:50:44.866083 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
14018 06:50:44.876390 Opened dev<8>[ 32.725732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
14019 06:50:44.876675 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
14021 06:50:44.879426 ice: /dev/dri/card0
14022 06:50:44.883033 No KMS driver or no outputs, pipes: 8, outputs: 0
14023 06:50:44.889436 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
14024 06:50:44.893943 <14>[ 32.747054] [IGT] kms_vblank: executing
14025 06:50:44.899786 IGT-Version: 1.2<14>[ 32.751799] [IGT] kms_vblank: exiting, ret=77
14026 06:50:44.902670 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
14027 06:50:44.912965 Opened dev<8>[ 32.762158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
14028 06:50:44.913251 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
14030 06:50:44.916229 ice: /dev/dri/card0
14031 06:50:44.919708 No KMS driver or no outputs, pipes: 8, outputs: 0
14032 06:50:44.926102 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
14033 06:50:44.929797 <14>[ 32.784176] [IGT] kms_vblank: executing
14034 06:50:44.937019 IGT-Version: 1.2<14>[ 32.788953] [IGT] kms_vblank: exiting, ret=77
14035 06:50:44.939995 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
14036 06:50:44.949785 Opened dev<8>[ 32.799545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
14037 06:50:44.950051 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
14039 06:50:44.952816 ice: /dev/dri/card0
14040 06:50:44.956647 No KMS driv<8>[ 32.810563] <LAVA_SIGNAL_TESTSET STOP>
14041 06:50:44.956903 Received signal: <TESTSET> STOP
14042 06:50:44.956974 Closing test_set kms_vblank
14043 06:50:44.966291 er or no outputs<8>[ 32.817035] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 12694787_1.5.2.3.1>
14044 06:50:44.966380 , pipes: 8, outputs: 0
14045 06:50:44.966662 Received signal: <ENDRUN> 0_igt-kms-mediatek 12694787_1.5.2.3.1
14046 06:50:44.966748 Ending use of test pattern.
14047 06:50:44.966822 Ending test lava.0_igt-kms-mediatek (12694787_1.5.2.3.1), duration 12.41
14049 06:50:44.973001 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
14050 06:50:44.973085 + set +x
14051 06:50:44.976256 <LAVA_TEST_RUNNER EXIT>
14052 06:50:44.976512 ok: lava_test_shell seems to have completed
14053 06:50:44.980416 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
14054 06:50:44.980652 end: 3.1 lava-test-shell (duration 00:00:13) [common]
14055 06:50:44.980738 end: 3 lava-test-retry (duration 00:00:13) [common]
14056 06:50:44.980825 start: 4 finalize (timeout 00:06:57) [common]
14057 06:50:44.980914 start: 4.1 power-off (timeout 00:00:30) [common]
14058 06:50:44.981060 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
14059 06:50:45.057201 >> Command sent successfully.
14060 06:50:45.059679 Returned 0 in 0 seconds
14061 06:50:45.160084 end: 4.1 power-off (duration 00:00:00) [common]
14063 06:50:45.160399 start: 4.2 read-feedback (timeout 00:06:57) [common]
14064 06:50:45.160668 Listened to connection for namespace 'common' for up to 1s
14065 06:50:46.161616 Finalising connection for namespace 'common'
14066 06:50:46.161793 Disconnecting from shell: Finalise
14067 06:50:46.161867 / #
14068 06:50:46.262199 end: 4.2 read-feedback (duration 00:00:01) [common]
14069 06:50:46.262379 end: 4 finalize (duration 00:00:01) [common]
14070 06:50:46.262532 Cleaning after the job
14071 06:50:46.262635 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/ramdisk
14072 06:50:46.270537 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/kernel
14073 06:50:46.279220 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/dtb
14074 06:50:46.279430 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694787/tftp-deploy-2gqx_yo1/modules
14075 06:50:46.286551 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694787
14076 06:50:46.405251 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694787
14077 06:50:46.405438 Job finished correctly