Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 38
1 06:51:39.538335 lava-dispatcher, installed at version: 2023.10
2 06:51:39.538596 start: 0 validate
3 06:51:39.538736 Start time: 2024-02-03 06:51:39.538728+00:00 (UTC)
4 06:51:39.538861 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:51:39.539001 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 06:51:39.809094 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:51:39.810094 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:51:40.073109 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:51:40.073796 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:51:40.334897 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:51:40.335081 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:51:40.602242 Using caching service: 'http://localhost/cache/?uri=%s'
13 06:51:40.602453 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 06:51:40.870426 validate duration: 1.33
16 06:51:40.870872 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:51:40.871056 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:51:40.871219 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:51:40.871436 Not decompressing ramdisk as can be used compressed.
20 06:51:40.871594 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 06:51:40.871721 saving as /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/ramdisk/initrd.cpio.gz
22 06:51:40.871843 total size: 4665395 (4 MB)
23 06:51:40.873289 progress 0 % (0 MB)
24 06:51:40.874847 progress 5 % (0 MB)
25 06:51:40.876209 progress 10 % (0 MB)
26 06:51:40.877550 progress 15 % (0 MB)
27 06:51:40.878961 progress 20 % (0 MB)
28 06:51:40.880381 progress 25 % (1 MB)
29 06:51:40.881879 progress 30 % (1 MB)
30 06:51:40.883344 progress 35 % (1 MB)
31 06:51:40.884762 progress 40 % (1 MB)
32 06:51:40.886358 progress 45 % (2 MB)
33 06:51:40.887790 progress 50 % (2 MB)
34 06:51:40.889249 progress 55 % (2 MB)
35 06:51:40.890683 progress 60 % (2 MB)
36 06:51:40.892095 progress 65 % (2 MB)
37 06:51:40.893543 progress 70 % (3 MB)
38 06:51:40.894969 progress 75 % (3 MB)
39 06:51:40.896417 progress 80 % (3 MB)
40 06:51:40.898036 progress 85 % (3 MB)
41 06:51:40.899441 progress 90 % (4 MB)
42 06:51:40.900732 progress 95 % (4 MB)
43 06:51:40.902050 progress 100 % (4 MB)
44 06:51:40.902213 4 MB downloaded in 0.03 s (146.48 MB/s)
45 06:51:40.902372 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:51:40.902631 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:51:40.902721 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:51:40.902807 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:51:40.902946 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 06:51:40.903019 saving as /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/kernel/Image
52 06:51:40.903083 total size: 51532288 (49 MB)
53 06:51:40.903146 No compression specified
54 06:51:40.904257 progress 0 % (0 MB)
55 06:51:40.917623 progress 5 % (2 MB)
56 06:51:40.931202 progress 10 % (4 MB)
57 06:51:40.944585 progress 15 % (7 MB)
58 06:51:40.958023 progress 20 % (9 MB)
59 06:51:40.971458 progress 25 % (12 MB)
60 06:51:40.984944 progress 30 % (14 MB)
61 06:51:40.998537 progress 35 % (17 MB)
62 06:51:41.012020 progress 40 % (19 MB)
63 06:51:41.025521 progress 45 % (22 MB)
64 06:51:41.039254 progress 50 % (24 MB)
65 06:51:41.053241 progress 55 % (27 MB)
66 06:51:41.067602 progress 60 % (29 MB)
67 06:51:41.081950 progress 65 % (31 MB)
68 06:51:41.096145 progress 70 % (34 MB)
69 06:51:41.110337 progress 75 % (36 MB)
70 06:51:41.124811 progress 80 % (39 MB)
71 06:51:41.139083 progress 85 % (41 MB)
72 06:51:41.153470 progress 90 % (44 MB)
73 06:51:41.167733 progress 95 % (46 MB)
74 06:51:41.181593 progress 100 % (49 MB)
75 06:51:41.181820 49 MB downloaded in 0.28 s (176.32 MB/s)
76 06:51:41.181985 end: 1.2.1 http-download (duration 00:00:00) [common]
78 06:51:41.182227 end: 1.2 download-retry (duration 00:00:00) [common]
79 06:51:41.182353 start: 1.3 download-retry (timeout 00:10:00) [common]
80 06:51:41.182505 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 06:51:41.182654 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 06:51:41.182729 saving as /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/dtb/mt8192-asurada-spherion-r0.dtb
83 06:51:41.182810 total size: 47278 (0 MB)
84 06:51:41.182874 No compression specified
85 06:51:41.184059 progress 69 % (0 MB)
86 06:51:41.184340 progress 100 % (0 MB)
87 06:51:41.184508 0 MB downloaded in 0.00 s (26.60 MB/s)
88 06:51:41.184633 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:51:41.184980 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:51:41.185108 start: 1.4 download-retry (timeout 00:10:00) [common]
92 06:51:41.185221 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 06:51:41.185375 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 06:51:41.185470 saving as /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/nfsrootfs/full.rootfs.tar
95 06:51:41.185564 total size: 200813988 (191 MB)
96 06:51:41.185659 Using unxz to decompress xz
97 06:51:41.190387 progress 0 % (0 MB)
98 06:51:41.723714 progress 5 % (9 MB)
99 06:51:42.239538 progress 10 % (19 MB)
100 06:51:42.828845 progress 15 % (28 MB)
101 06:51:43.204621 progress 20 % (38 MB)
102 06:51:43.527517 progress 25 % (47 MB)
103 06:51:44.118657 progress 30 % (57 MB)
104 06:51:44.673225 progress 35 % (67 MB)
105 06:51:45.287532 progress 40 % (76 MB)
106 06:51:45.842916 progress 45 % (86 MB)
107 06:51:46.426019 progress 50 % (95 MB)
108 06:51:47.054768 progress 55 % (105 MB)
109 06:51:47.718700 progress 60 % (114 MB)
110 06:51:47.836728 progress 65 % (124 MB)
111 06:51:47.976244 progress 70 % (134 MB)
112 06:51:48.073411 progress 75 % (143 MB)
113 06:51:48.144392 progress 80 % (153 MB)
114 06:51:48.213061 progress 85 % (162 MB)
115 06:51:48.314491 progress 90 % (172 MB)
116 06:51:48.593335 progress 95 % (181 MB)
117 06:51:49.169414 progress 100 % (191 MB)
118 06:51:49.174734 191 MB downloaded in 7.99 s (23.97 MB/s)
119 06:51:49.174990 end: 1.4.1 http-download (duration 00:00:08) [common]
121 06:51:49.175254 end: 1.4 download-retry (duration 00:00:08) [common]
122 06:51:49.175345 start: 1.5 download-retry (timeout 00:09:52) [common]
123 06:51:49.175431 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 06:51:49.175591 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 06:51:49.175660 saving as /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/modules/modules.tar
126 06:51:49.175720 total size: 8624064 (8 MB)
127 06:51:49.175783 Using unxz to decompress xz
128 06:51:49.179835 progress 0 % (0 MB)
129 06:51:49.201042 progress 5 % (0 MB)
130 06:51:49.225843 progress 10 % (0 MB)
131 06:51:49.250431 progress 15 % (1 MB)
132 06:51:49.274607 progress 20 % (1 MB)
133 06:51:49.300939 progress 25 % (2 MB)
134 06:51:49.327479 progress 30 % (2 MB)
135 06:51:49.354170 progress 35 % (2 MB)
136 06:51:49.377724 progress 40 % (3 MB)
137 06:51:49.402932 progress 45 % (3 MB)
138 06:51:49.428771 progress 50 % (4 MB)
139 06:51:49.453656 progress 55 % (4 MB)
140 06:51:49.478382 progress 60 % (4 MB)
141 06:51:49.505623 progress 65 % (5 MB)
142 06:51:49.530297 progress 70 % (5 MB)
143 06:51:49.553606 progress 75 % (6 MB)
144 06:51:49.580513 progress 80 % (6 MB)
145 06:51:49.605950 progress 85 % (7 MB)
146 06:51:49.630853 progress 90 % (7 MB)
147 06:51:49.662111 progress 95 % (7 MB)
148 06:51:49.689795 progress 100 % (8 MB)
149 06:51:49.694718 8 MB downloaded in 0.52 s (15.85 MB/s)
150 06:51:49.694975 end: 1.5.1 http-download (duration 00:00:01) [common]
152 06:51:49.695241 end: 1.5 download-retry (duration 00:00:01) [common]
153 06:51:49.695333 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 06:51:49.695431 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 06:51:53.241388 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12694840/extract-nfsrootfs-kxldhbtm
156 06:51:53.241588 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 06:51:53.241685 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 06:51:53.241857 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j
159 06:51:53.241992 makedir: /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin
160 06:51:53.242096 makedir: /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/tests
161 06:51:53.242197 makedir: /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/results
162 06:51:53.242298 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-add-keys
163 06:51:53.242451 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-add-sources
164 06:51:53.242583 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-background-process-start
165 06:51:53.242713 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-background-process-stop
166 06:51:53.242842 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-common-functions
167 06:51:53.242970 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-echo-ipv4
168 06:51:53.243097 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-install-packages
169 06:51:53.243224 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-installed-packages
170 06:51:53.243351 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-os-build
171 06:51:53.243477 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-probe-channel
172 06:51:53.243604 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-probe-ip
173 06:51:53.243731 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-target-ip
174 06:51:53.243858 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-target-mac
175 06:51:53.243985 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-target-storage
176 06:51:53.244114 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-test-case
177 06:51:53.244242 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-test-event
178 06:51:53.244368 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-test-feedback
179 06:51:53.244493 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-test-raise
180 06:51:53.244617 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-test-reference
181 06:51:53.244742 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-test-runner
182 06:51:53.244870 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-test-set
183 06:51:53.244997 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-test-shell
184 06:51:53.245126 Updating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-add-keys (debian)
185 06:51:53.245280 Updating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-add-sources (debian)
186 06:51:53.245424 Updating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-install-packages (debian)
187 06:51:53.245565 Updating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-installed-packages (debian)
188 06:51:53.245706 Updating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/bin/lava-os-build (debian)
189 06:51:53.245829 Creating /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/environment
190 06:51:53.245926 LAVA metadata
191 06:51:53.246000 - LAVA_JOB_ID=12694840
192 06:51:53.246063 - LAVA_DISPATCHER_IP=192.168.201.1
193 06:51:53.246163 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 06:51:53.246228 skipped lava-vland-overlay
195 06:51:53.246301 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 06:51:53.246379 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 06:51:53.246448 skipped lava-multinode-overlay
198 06:51:53.246597 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 06:51:53.246675 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 06:51:53.246748 Loading test definitions
201 06:51:53.246837 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 06:51:53.246908 Using /lava-12694840 at stage 0
203 06:51:53.247191 uuid=12694840_1.6.2.3.1 testdef=None
204 06:51:53.247278 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 06:51:53.247363 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 06:51:53.247883 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 06:51:53.248105 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 06:51:53.248672 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 06:51:53.248901 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 06:51:53.249446 runner path: /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/0/tests/0_timesync-off test_uuid 12694840_1.6.2.3.1
213 06:51:53.249602 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 06:51:53.249827 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 06:51:53.249899 Using /lava-12694840 at stage 0
217 06:51:53.249994 Fetching tests from https://github.com/kernelci/test-definitions.git
218 06:51:53.250091 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/0/tests/1_kselftest-dt'
219 06:51:55.490743 Running '/usr/bin/git checkout kernelci.org
220 06:51:55.704291 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 06:51:55.705042 uuid=12694840_1.6.2.3.5 testdef=None
222 06:51:55.705202 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 06:51:55.705453 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 06:51:55.706221 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 06:51:55.706490 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 06:51:55.707462 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 06:51:55.707698 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 06:51:55.708632 runner path: /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/0/tests/1_kselftest-dt test_uuid 12694840_1.6.2.3.5
232 06:51:55.708722 BOARD='mt8192-asurada-spherion-r0'
233 06:51:55.708786 BRANCH='cip'
234 06:51:55.708844 SKIPFILE='/dev/null'
235 06:51:55.708901 SKIP_INSTALL='True'
236 06:51:55.708956 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 06:51:55.709015 TST_CASENAME=''
238 06:51:55.709068 TST_CMDFILES='dt'
239 06:51:55.709206 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 06:51:55.709406 Creating lava-test-runner.conf files
242 06:51:55.709469 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694840/lava-overlay-nibu1z4j/lava-12694840/0 for stage 0
243 06:51:55.709561 - 0_timesync-off
244 06:51:55.709630 - 1_kselftest-dt
245 06:51:55.709726 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 06:51:55.709812 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 06:52:03.281900 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 06:52:03.282060 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 06:52:03.282153 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 06:52:03.282254 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 06:52:03.282343 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 06:52:03.401036 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 06:52:03.401419 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 06:52:03.401536 extracting modules file /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694840/extract-nfsrootfs-kxldhbtm
255 06:52:03.621699 extracting modules file /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694840/extract-overlay-ramdisk-qoxie68h/ramdisk
256 06:52:03.847451 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 06:52:03.847626 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 06:52:03.847720 [common] Applying overlay to NFS
259 06:52:03.847795 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694840/compress-overlay-pkzj8g2x/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694840/extract-nfsrootfs-kxldhbtm
260 06:52:04.760720 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 06:52:04.760892 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 06:52:04.760984 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 06:52:04.761073 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 06:52:04.761150 Building ramdisk /var/lib/lava/dispatcher/tmp/12694840/extract-overlay-ramdisk-qoxie68h/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694840/extract-overlay-ramdisk-qoxie68h/ramdisk
265 06:52:05.093901 >> 119430 blocks
266 06:52:07.011395 rename /var/lib/lava/dispatcher/tmp/12694840/extract-overlay-ramdisk-qoxie68h/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/ramdisk/ramdisk.cpio.gz
267 06:52:07.011840 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 06:52:07.011959 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 06:52:07.012070 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 06:52:07.012176 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/kernel/Image'
271 06:52:19.264761 Returned 0 in 12 seconds
272 06:52:19.365842 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/kernel/image.itb
273 06:52:19.721852 output: FIT description: Kernel Image image with one or more FDT blobs
274 06:52:19.722230 output: Created: Sat Feb 3 06:52:19 2024
275 06:52:19.722305 output: Image 0 (kernel-1)
276 06:52:19.722371 output: Description:
277 06:52:19.722488 output: Created: Sat Feb 3 06:52:19 2024
278 06:52:19.722562 output: Type: Kernel Image
279 06:52:19.722620 output: Compression: lzma compressed
280 06:52:19.722675 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
281 06:52:19.722733 output: Architecture: AArch64
282 06:52:19.722786 output: OS: Linux
283 06:52:19.722845 output: Load Address: 0x00000000
284 06:52:19.722902 output: Entry Point: 0x00000000
285 06:52:19.722957 output: Hash algo: crc32
286 06:52:19.723014 output: Hash value: 380e7c3c
287 06:52:19.723070 output: Image 1 (fdt-1)
288 06:52:19.723122 output: Description: mt8192-asurada-spherion-r0
289 06:52:19.723174 output: Created: Sat Feb 3 06:52:19 2024
290 06:52:19.723226 output: Type: Flat Device Tree
291 06:52:19.723278 output: Compression: uncompressed
292 06:52:19.723330 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 06:52:19.723381 output: Architecture: AArch64
294 06:52:19.723433 output: Hash algo: crc32
295 06:52:19.723484 output: Hash value: cc4352de
296 06:52:19.723536 output: Image 2 (ramdisk-1)
297 06:52:19.723586 output: Description: unavailable
298 06:52:19.723637 output: Created: Sat Feb 3 06:52:19 2024
299 06:52:19.723689 output: Type: RAMDisk Image
300 06:52:19.723741 output: Compression: Unknown Compression
301 06:52:19.723792 output: Data Size: 17803024 Bytes = 17385.77 KiB = 16.98 MiB
302 06:52:19.723843 output: Architecture: AArch64
303 06:52:19.723895 output: OS: Linux
304 06:52:19.723946 output: Load Address: unavailable
305 06:52:19.723997 output: Entry Point: unavailable
306 06:52:19.724048 output: Hash algo: crc32
307 06:52:19.724100 output: Hash value: 9b37c5b1
308 06:52:19.724151 output: Default Configuration: 'conf-1'
309 06:52:19.724202 output: Configuration 0 (conf-1)
310 06:52:19.724253 output: Description: mt8192-asurada-spherion-r0
311 06:52:19.724304 output: Kernel: kernel-1
312 06:52:19.724356 output: Init Ramdisk: ramdisk-1
313 06:52:19.724407 output: FDT: fdt-1
314 06:52:19.724459 output: Loadables: kernel-1
315 06:52:19.724510 output:
316 06:52:19.724714 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 06:52:19.724805 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 06:52:19.724909 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 06:52:19.725002 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 06:52:19.725081 No LXC device requested
321 06:52:19.725161 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 06:52:19.725243 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 06:52:19.725318 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 06:52:19.725388 Checking files for TFTP limit of 4294967296 bytes.
325 06:52:19.725893 end: 1 tftp-deploy (duration 00:00:39) [common]
326 06:52:19.725999 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 06:52:19.726094 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 06:52:19.726222 substitutions:
329 06:52:19.726289 - {DTB}: 12694840/tftp-deploy-7407rfg7/dtb/mt8192-asurada-spherion-r0.dtb
330 06:52:19.726354 - {INITRD}: 12694840/tftp-deploy-7407rfg7/ramdisk/ramdisk.cpio.gz
331 06:52:19.726450 - {KERNEL}: 12694840/tftp-deploy-7407rfg7/kernel/Image
332 06:52:19.726508 - {LAVA_MAC}: None
333 06:52:19.726564 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12694840/extract-nfsrootfs-kxldhbtm
334 06:52:19.726619 - {NFS_SERVER_IP}: 192.168.201.1
335 06:52:19.726673 - {PRESEED_CONFIG}: None
336 06:52:19.726727 - {PRESEED_LOCAL}: None
337 06:52:19.726780 - {RAMDISK}: 12694840/tftp-deploy-7407rfg7/ramdisk/ramdisk.cpio.gz
338 06:52:19.726834 - {ROOT_PART}: None
339 06:52:19.726887 - {ROOT}: None
340 06:52:19.726939 - {SERVER_IP}: 192.168.201.1
341 06:52:19.726992 - {TEE}: None
342 06:52:19.727044 Parsed boot commands:
343 06:52:19.727097 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 06:52:19.727280 Parsed boot commands: tftpboot 192.168.201.1 12694840/tftp-deploy-7407rfg7/kernel/image.itb 12694840/tftp-deploy-7407rfg7/kernel/cmdline
345 06:52:19.727367 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 06:52:19.727451 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 06:52:19.727543 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 06:52:19.727629 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 06:52:19.727702 Not connected, no need to disconnect.
350 06:52:19.727774 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 06:52:19.727855 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 06:52:19.727924 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 06:52:19.732004 Setting prompt string to ['lava-test: # ']
354 06:52:19.732391 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 06:52:19.732500 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 06:52:19.732600 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 06:52:19.732690 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 06:52:19.732890 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 06:52:24.878506 >> Command sent successfully.
360 06:52:24.888918 Returned 0 in 5 seconds
361 06:52:24.990292 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 06:52:24.992014 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 06:52:24.992601 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 06:52:24.993112 Setting prompt string to 'Starting depthcharge on Spherion...'
366 06:52:24.993496 Changing prompt to 'Starting depthcharge on Spherion...'
367 06:52:24.993877 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 06:52:24.995392 [Enter `^Ec?' for help]
369 06:52:25.159785
370 06:52:25.160330
371 06:52:25.160694 F0: 102B 0000
372 06:52:25.161023
373 06:52:25.161328 F3: 1001 0000 [0200]
374 06:52:25.161628
375 06:52:25.163031 F3: 1001 0000
376 06:52:25.163392
377 06:52:25.163694 F7: 102D 0000
378 06:52:25.163987
379 06:52:25.164271 F1: 0000 0000
380 06:52:25.164554
381 06:52:25.166061 V0: 0000 0000 [0001]
382 06:52:25.166380
383 06:52:25.166704 00: 0007 8000
384 06:52:25.167010
385 06:52:25.170380 01: 0000 0000
386 06:52:25.171025
387 06:52:25.171375 BP: 0C00 0209 [0000]
388 06:52:25.171695
389 06:52:25.173783 G0: 1182 0000
390 06:52:25.174385
391 06:52:25.174913 EC: 0000 0021 [4000]
392 06:52:25.175251
393 06:52:25.178293 S7: 0000 0000 [0000]
394 06:52:25.178922
395 06:52:25.179275 CC: 0000 0000 [0001]
396 06:52:25.179595
397 06:52:25.180924 T0: 0000 0040 [010F]
398 06:52:25.181556
399 06:52:25.181952 Jump to BL
400 06:52:25.182276
401 06:52:25.205946
402 06:52:25.206513
403 06:52:25.206865
404 06:52:25.213286 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 06:52:25.216216 ARM64: Exception handlers installed.
406 06:52:25.220089 ARM64: Testing exception
407 06:52:25.224308 ARM64: Done test exception
408 06:52:25.231371 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 06:52:25.238659 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 06:52:25.245878 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 06:52:25.256579 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 06:52:25.263556 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 06:52:25.273735 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 06:52:25.284058 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 06:52:25.291100 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 06:52:25.308774 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 06:52:25.312016 WDT: Last reset was cold boot
418 06:52:25.315152 SPI1(PAD0) initialized at 2873684 Hz
419 06:52:25.318703 SPI5(PAD0) initialized at 992727 Hz
420 06:52:25.322578 VBOOT: Loading verstage.
421 06:52:25.328639 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 06:52:25.332561 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 06:52:25.336031 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 06:52:25.338907 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 06:52:25.346635 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 06:52:25.352898 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 06:52:25.363914 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 06:52:25.364503
429 06:52:25.364885
430 06:52:25.373571 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 06:52:25.377271 ARM64: Exception handlers installed.
432 06:52:25.380583 ARM64: Testing exception
433 06:52:25.381160 ARM64: Done test exception
434 06:52:25.387416 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 06:52:25.390679 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 06:52:25.405356 Probing TPM: . done!
437 06:52:25.405925 TPM ready after 0 ms
438 06:52:25.412507 Connected to device vid:did:rid of 1ae0:0028:00
439 06:52:25.418580 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 06:52:25.475256 Initialized TPM device CR50 revision 0
441 06:52:25.486263 tlcl_send_startup: Startup return code is 0
442 06:52:25.486877 TPM: setup succeeded
443 06:52:25.498620 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 06:52:25.507133 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 06:52:25.518292 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 06:52:25.528103 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 06:52:25.531429 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 06:52:25.539000 in-header: 03 07 00 00 08 00 00 00
449 06:52:25.542737 in-data: aa e4 47 04 13 02 00 00
450 06:52:25.546599 Chrome EC: UHEPI supported
451 06:52:25.553477 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 06:52:25.557494 in-header: 03 ad 00 00 08 00 00 00
453 06:52:25.560766 in-data: 00 20 20 08 00 00 00 00
454 06:52:25.561368 Phase 1
455 06:52:25.564283 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 06:52:25.571461 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 06:52:25.575669 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 06:52:25.579450 Recovery requested (1009000e)
459 06:52:25.588282 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 06:52:25.593107 tlcl_extend: response is 0
461 06:52:25.602613 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 06:52:25.608478 tlcl_extend: response is 0
463 06:52:25.615585 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 06:52:25.634587 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 06:52:25.641966 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 06:52:25.642551
467 06:52:25.642932
468 06:52:25.651974 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 06:52:25.656130 ARM64: Exception handlers installed.
470 06:52:25.656574 ARM64: Testing exception
471 06:52:25.658996 ARM64: Done test exception
472 06:52:25.680416 pmic_efuse_setting: Set efuses in 11 msecs
473 06:52:25.684799 pmwrap_interface_init: Select PMIF_VLD_RDY
474 06:52:25.692152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 06:52:25.694642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 06:52:25.697653 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 06:52:25.705241 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 06:52:25.708730 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 06:52:25.712270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 06:52:25.719496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 06:52:25.723673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 06:52:25.727617 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 06:52:25.730944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 06:52:25.738665 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 06:52:25.742666 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 06:52:25.746323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 06:52:25.752896 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 06:52:25.757217 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 06:52:25.763991 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 06:52:25.768591 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 06:52:25.775785 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 06:52:25.779701 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 06:52:25.786602 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 06:52:25.790775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 06:52:25.798178 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 06:52:25.805882 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 06:52:25.809452 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 06:52:25.813915 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 06:52:25.820236 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 06:52:25.824004 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 06:52:25.827677 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 06:52:25.835131 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 06:52:25.839122 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 06:52:25.846474 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 06:52:25.850087 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 06:52:25.854098 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 06:52:25.860780 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 06:52:25.864739 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 06:52:25.868124 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 06:52:25.876469 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 06:52:25.880344 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 06:52:25.883397 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 06:52:25.887251 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 06:52:25.894496 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 06:52:25.898012 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 06:52:25.901471 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 06:52:25.905200 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 06:52:25.909281 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 06:52:25.913303 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 06:52:25.920226 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 06:52:25.924082 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 06:52:25.927922 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 06:52:25.932039 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 06:52:25.935055 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 06:52:25.942944 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 06:52:25.950897 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 06:52:25.957786 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 06:52:25.964882 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 06:52:25.973100 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 06:52:25.975779 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 06:52:25.984349 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 06:52:25.987276 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 06:52:25.994716 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xc
534 06:52:25.998227 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 06:52:26.005397 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 06:52:26.009679 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 06:52:26.017777 [RTC]rtc_get_frequency_meter,154: input=15, output=790
538 06:52:26.027514 [RTC]rtc_get_frequency_meter,154: input=23, output=979
539 06:52:26.036893 [RTC]rtc_get_frequency_meter,154: input=19, output=884
540 06:52:26.046055 [RTC]rtc_get_frequency_meter,154: input=17, output=837
541 06:52:26.055758 [RTC]rtc_get_frequency_meter,154: input=16, output=814
542 06:52:26.065461 [RTC]rtc_get_frequency_meter,154: input=15, output=791
543 06:52:26.076185 [RTC]rtc_get_frequency_meter,154: input=16, output=815
544 06:52:26.079258 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 06:52:26.083488 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 06:52:26.087066 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 06:52:26.094329 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 06:52:26.097929 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 06:52:26.101750 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 06:52:26.105838 ADC[4]: Raw value=901697 ID=7
551 06:52:26.106265 ADC[3]: Raw value=213336 ID=1
552 06:52:26.110247 RAM Code: 0x71
553 06:52:26.113618 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 06:52:26.116803 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 06:52:26.123928 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 06:52:26.131960 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 06:52:26.136218 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 06:52:26.139970 in-header: 03 07 00 00 08 00 00 00
559 06:52:26.143499 in-data: aa e4 47 04 13 02 00 00
560 06:52:26.147290 Chrome EC: UHEPI supported
561 06:52:26.150468 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 06:52:26.155283 in-header: 03 ed 00 00 08 00 00 00
563 06:52:26.158941 in-data: 80 20 60 08 00 00 00 00
564 06:52:26.162499 MRC: failed to locate region type 0.
565 06:52:26.169876 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 06:52:26.173181 DRAM-K: Running full calibration
567 06:52:26.177231 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 06:52:26.180570 header.status = 0x0
569 06:52:26.184814 header.version = 0x6 (expected: 0x6)
570 06:52:26.188262 header.size = 0xd00 (expected: 0xd00)
571 06:52:26.188687 header.flags = 0x0
572 06:52:26.195182 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 06:52:26.213672 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
574 06:52:26.220461 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 06:52:26.221034 dram_init: ddr_geometry: 2
576 06:52:26.224861 [EMI] MDL number = 2
577 06:52:26.227866 [EMI] Get MDL freq = 0
578 06:52:26.228305 dram_init: ddr_type: 0
579 06:52:26.231903 is_discrete_lpddr4: 1
580 06:52:26.235242 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 06:52:26.235679
582 06:52:26.236108
583 06:52:26.236440 [Bian_co] ETT version 0.0.0.1
584 06:52:26.242838 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 06:52:26.243275
586 06:52:26.246370 dramc_set_vcore_voltage set vcore to 650000
587 06:52:26.246891 Read voltage for 800, 4
588 06:52:26.249424 Vio18 = 0
589 06:52:26.249506 Vcore = 650000
590 06:52:26.249571 Vdram = 0
591 06:52:26.249630 Vddq = 0
592 06:52:26.252564 Vmddr = 0
593 06:52:26.252677 dram_init: config_dvfs: 1
594 06:52:26.259947 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 06:52:26.266308 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 06:52:26.270000 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 06:52:26.273384 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 06:52:26.276555 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 06:52:26.280244 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 06:52:26.283500 MEM_TYPE=3, freq_sel=18
601 06:52:26.287241 sv_algorithm_assistance_LP4_1600
602 06:52:26.290137 ============ PULL DRAM RESETB DOWN ============
603 06:52:26.293916 ========== PULL DRAM RESETB DOWN end =========
604 06:52:26.300409 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 06:52:26.303848 ===================================
606 06:52:26.304186 LPDDR4 DRAM CONFIGURATION
607 06:52:26.306753 ===================================
608 06:52:26.310471 EX_ROW_EN[0] = 0x0
609 06:52:26.310969 EX_ROW_EN[1] = 0x0
610 06:52:26.314182 LP4Y_EN = 0x0
611 06:52:26.314798 WORK_FSP = 0x0
612 06:52:26.316835 WL = 0x2
613 06:52:26.317268 RL = 0x2
614 06:52:26.320396 BL = 0x2
615 06:52:26.320831 RPST = 0x0
616 06:52:26.323927 RD_PRE = 0x0
617 06:52:26.324469 WR_PRE = 0x1
618 06:52:26.327677 WR_PST = 0x0
619 06:52:26.328230 DBI_WR = 0x0
620 06:52:26.330541 DBI_RD = 0x0
621 06:52:26.334557 OTF = 0x1
622 06:52:26.335031 ===================================
623 06:52:26.337111 ===================================
624 06:52:26.340636 ANA top config
625 06:52:26.344062 ===================================
626 06:52:26.347797 DLL_ASYNC_EN = 0
627 06:52:26.348231 ALL_SLAVE_EN = 1
628 06:52:26.350871 NEW_RANK_MODE = 1
629 06:52:26.354793 DLL_IDLE_MODE = 1
630 06:52:26.357622 LP45_APHY_COMB_EN = 1
631 06:52:26.358103 TX_ODT_DIS = 1
632 06:52:26.360577 NEW_8X_MODE = 1
633 06:52:26.364300 ===================================
634 06:52:26.367841 ===================================
635 06:52:26.370933 data_rate = 1600
636 06:52:26.374212 CKR = 1
637 06:52:26.377360 DQ_P2S_RATIO = 8
638 06:52:26.380435 ===================================
639 06:52:26.383824 CA_P2S_RATIO = 8
640 06:52:26.384058 DQ_CA_OPEN = 0
641 06:52:26.387063 DQ_SEMI_OPEN = 0
642 06:52:26.390658 CA_SEMI_OPEN = 0
643 06:52:26.393766 CA_FULL_RATE = 0
644 06:52:26.397080 DQ_CKDIV4_EN = 1
645 06:52:26.397238 CA_CKDIV4_EN = 1
646 06:52:26.400481 CA_PREDIV_EN = 0
647 06:52:26.404141 PH8_DLY = 0
648 06:52:26.407592 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 06:52:26.411206 DQ_AAMCK_DIV = 4
650 06:52:26.413889 CA_AAMCK_DIV = 4
651 06:52:26.413989 CA_ADMCK_DIV = 4
652 06:52:26.417602 DQ_TRACK_CA_EN = 0
653 06:52:26.420535 CA_PICK = 800
654 06:52:26.423770 CA_MCKIO = 800
655 06:52:26.427428 MCKIO_SEMI = 0
656 06:52:26.431001 PLL_FREQ = 3068
657 06:52:26.431100 DQ_UI_PI_RATIO = 32
658 06:52:26.434520 CA_UI_PI_RATIO = 0
659 06:52:26.438702 ===================================
660 06:52:26.441693 ===================================
661 06:52:26.445011 memory_type:LPDDR4
662 06:52:26.445103 GP_NUM : 10
663 06:52:26.449039 SRAM_EN : 1
664 06:52:26.449126 MD32_EN : 0
665 06:52:26.452605 ===================================
666 06:52:26.456866 [ANA_INIT] >>>>>>>>>>>>>>
667 06:52:26.460165 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 06:52:26.464126 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 06:52:26.464229 ===================================
670 06:52:26.467565 data_rate = 1600,PCW = 0X7600
671 06:52:26.471034 ===================================
672 06:52:26.474848 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 06:52:26.481173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 06:52:26.484408 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 06:52:26.491564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 06:52:26.494884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 06:52:26.497950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 06:52:26.498035 [ANA_INIT] flow start
679 06:52:26.501381 [ANA_INIT] PLL >>>>>>>>
680 06:52:26.504955 [ANA_INIT] PLL <<<<<<<<
681 06:52:26.507888 [ANA_INIT] MIDPI >>>>>>>>
682 06:52:26.507973 [ANA_INIT] MIDPI <<<<<<<<
683 06:52:26.511562 [ANA_INIT] DLL >>>>>>>>
684 06:52:26.514864 [ANA_INIT] flow end
685 06:52:26.517929 ============ LP4 DIFF to SE enter ============
686 06:52:26.521307 ============ LP4 DIFF to SE exit ============
687 06:52:26.524858 [ANA_INIT] <<<<<<<<<<<<<
688 06:52:26.527912 [Flow] Enable top DCM control >>>>>
689 06:52:26.531252 [Flow] Enable top DCM control <<<<<
690 06:52:26.534727 Enable DLL master slave shuffle
691 06:52:26.538121 ==============================================================
692 06:52:26.542006 Gating Mode config
693 06:52:26.544852 ==============================================================
694 06:52:26.548227 Config description:
695 06:52:26.558081 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 06:52:26.565191 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 06:52:26.569188 SELPH_MODE 0: By rank 1: By Phase
698 06:52:26.575077 ==============================================================
699 06:52:26.578560 GAT_TRACK_EN = 1
700 06:52:26.582343 RX_GATING_MODE = 2
701 06:52:26.585136 RX_GATING_TRACK_MODE = 2
702 06:52:26.585221 SELPH_MODE = 1
703 06:52:26.588348 PICG_EARLY_EN = 1
704 06:52:26.591773 VALID_LAT_VALUE = 1
705 06:52:26.598433 ==============================================================
706 06:52:26.601812 Enter into Gating configuration >>>>
707 06:52:26.605487 Exit from Gating configuration <<<<
708 06:52:26.609229 Enter into DVFS_PRE_config >>>>>
709 06:52:26.619306 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 06:52:26.622219 Exit from DVFS_PRE_config <<<<<
711 06:52:26.625503 Enter into PICG configuration >>>>
712 06:52:26.628720 Exit from PICG configuration <<<<
713 06:52:26.632375 [RX_INPUT] configuration >>>>>
714 06:52:26.635747 [RX_INPUT] configuration <<<<<
715 06:52:26.638600 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 06:52:26.645859 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 06:52:26.649345 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 06:52:26.656342 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 06:52:26.662966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 06:52:26.669570 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 06:52:26.673809 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 06:52:26.676868 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 06:52:26.679919 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 06:52:26.687257 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 06:52:26.689893 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 06:52:26.693537 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 06:52:26.697080 ===================================
728 06:52:26.700652 LPDDR4 DRAM CONFIGURATION
729 06:52:26.703623 ===================================
730 06:52:26.703963 EX_ROW_EN[0] = 0x0
731 06:52:26.706997 EX_ROW_EN[1] = 0x0
732 06:52:26.709843 LP4Y_EN = 0x0
733 06:52:26.710092 WORK_FSP = 0x0
734 06:52:26.713173 WL = 0x2
735 06:52:26.713421 RL = 0x2
736 06:52:26.716916 BL = 0x2
737 06:52:26.717111 RPST = 0x0
738 06:52:26.719975 RD_PRE = 0x0
739 06:52:26.720138 WR_PRE = 0x1
740 06:52:26.723397 WR_PST = 0x0
741 06:52:26.723559 DBI_WR = 0x0
742 06:52:26.726871 DBI_RD = 0x0
743 06:52:26.727011 OTF = 0x1
744 06:52:26.730815 ===================================
745 06:52:26.733368 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 06:52:26.740674 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 06:52:26.743816 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 06:52:26.747121 ===================================
749 06:52:26.750920 LPDDR4 DRAM CONFIGURATION
750 06:52:26.754211 ===================================
751 06:52:26.754696 EX_ROW_EN[0] = 0x10
752 06:52:26.757327 EX_ROW_EN[1] = 0x0
753 06:52:26.757762 LP4Y_EN = 0x0
754 06:52:26.760870 WORK_FSP = 0x0
755 06:52:26.761300 WL = 0x2
756 06:52:26.764217 RL = 0x2
757 06:52:26.764648 BL = 0x2
758 06:52:26.767440 RPST = 0x0
759 06:52:26.767876 RD_PRE = 0x0
760 06:52:26.771225 WR_PRE = 0x1
761 06:52:26.773842 WR_PST = 0x0
762 06:52:26.774074 DBI_WR = 0x0
763 06:52:26.777420 DBI_RD = 0x0
764 06:52:26.777652 OTF = 0x1
765 06:52:26.780487 ===================================
766 06:52:26.786962 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 06:52:26.791336 nWR fixed to 40
768 06:52:26.794110 [ModeRegInit_LP4] CH0 RK0
769 06:52:26.794234 [ModeRegInit_LP4] CH0 RK1
770 06:52:26.797512 [ModeRegInit_LP4] CH1 RK0
771 06:52:26.800964 [ModeRegInit_LP4] CH1 RK1
772 06:52:26.801076 match AC timing 13
773 06:52:26.807627 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 06:52:26.810551 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 06:52:26.813875 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 06:52:26.821039 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 06:52:26.824061 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 06:52:26.824148 [EMI DOE] emi_dcm 0
779 06:52:26.830986 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 06:52:26.831323 ==
781 06:52:26.834600 Dram Type= 6, Freq= 0, CH_0, rank 0
782 06:52:26.837796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 06:52:26.838138 ==
784 06:52:26.844662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 06:52:26.847643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 06:52:26.858162 [CA 0] Center 37 (7~68) winsize 62
787 06:52:26.861408 [CA 1] Center 37 (6~68) winsize 63
788 06:52:26.865120 [CA 2] Center 35 (5~66) winsize 62
789 06:52:26.867821 [CA 3] Center 34 (4~65) winsize 62
790 06:52:26.871285 [CA 4] Center 34 (3~65) winsize 63
791 06:52:26.874559 [CA 5] Center 33 (3~64) winsize 62
792 06:52:26.874681
793 06:52:26.878080 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 06:52:26.878202
795 06:52:26.881523 [CATrainingPosCal] consider 1 rank data
796 06:52:26.884659 u2DelayCellTimex100 = 270/100 ps
797 06:52:26.888051 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 06:52:26.891356 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 06:52:26.899072 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 06:52:26.901199 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 06:52:26.904848 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 06:52:26.908114 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 06:52:26.908197
804 06:52:26.912060 CA PerBit enable=1, Macro0, CA PI delay=33
805 06:52:26.912143
806 06:52:26.914939 [CBTSetCACLKResult] CA Dly = 33
807 06:52:26.915021 CS Dly: 5 (0~36)
808 06:52:26.915087 ==
809 06:52:26.918770 Dram Type= 6, Freq= 0, CH_0, rank 1
810 06:52:26.925284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 06:52:26.925450 ==
812 06:52:26.928764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 06:52:26.934818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 06:52:26.944314 [CA 0] Center 37 (6~68) winsize 63
815 06:52:26.948547 [CA 1] Center 37 (6~68) winsize 63
816 06:52:26.951020 [CA 2] Center 35 (5~66) winsize 62
817 06:52:26.954439 [CA 3] Center 35 (4~66) winsize 63
818 06:52:26.957984 [CA 4] Center 34 (3~65) winsize 63
819 06:52:26.961569 [CA 5] Center 33 (3~64) winsize 62
820 06:52:26.961772
821 06:52:26.964533 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 06:52:26.964769
823 06:52:26.968051 [CATrainingPosCal] consider 2 rank data
824 06:52:26.971780 u2DelayCellTimex100 = 270/100 ps
825 06:52:26.974896 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 06:52:26.978552 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
827 06:52:26.981725 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 06:52:26.988543 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 06:52:26.991861 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
830 06:52:26.995336 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 06:52:26.995918
832 06:52:26.998868 CA PerBit enable=1, Macro0, CA PI delay=33
833 06:52:26.999345
834 06:52:27.001879 [CBTSetCACLKResult] CA Dly = 33
835 06:52:27.002353 CS Dly: 6 (0~38)
836 06:52:27.002770
837 06:52:27.005067 ----->DramcWriteLeveling(PI) begin...
838 06:52:27.005760 ==
839 06:52:27.008716 Dram Type= 6, Freq= 0, CH_0, rank 0
840 06:52:27.016310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 06:52:27.017050 ==
842 06:52:27.017468 Write leveling (Byte 0): 29 => 29
843 06:52:27.019434 Write leveling (Byte 1): 25 => 25
844 06:52:27.023425 DramcWriteLeveling(PI) end<-----
845 06:52:27.023904
846 06:52:27.024280 ==
847 06:52:27.027011 Dram Type= 6, Freq= 0, CH_0, rank 0
848 06:52:27.030238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 06:52:27.030764 ==
850 06:52:27.034019 [Gating] SW mode calibration
851 06:52:27.041247 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 06:52:27.044568 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 06:52:27.052161 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 06:52:27.055053 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 06:52:27.058517 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 06:52:27.065249 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
857 06:52:27.068903 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 06:52:27.071592 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 06:52:27.079028 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 06:52:27.082483 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 06:52:27.085199 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 06:52:27.092105 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 06:52:27.095508 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 06:52:27.098534 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 06:52:27.101855 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 06:52:27.109012 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 06:52:27.111705 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 06:52:27.115710 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 06:52:27.122308 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 06:52:27.125551 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 06:52:27.129124 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
872 06:52:27.135604 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 06:52:27.138789 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 06:52:27.142653 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 06:52:27.145669 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 06:52:27.153116 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 06:52:27.155980 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 06:52:27.159386 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 06:52:27.166376 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 06:52:27.169433 0 9 12 | B1->B0 | 2929 3131 | 1 0 | (1 1) (0 0)
881 06:52:27.172638 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 06:52:27.180052 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 06:52:27.182572 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 06:52:27.186299 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 06:52:27.193141 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 06:52:27.196283 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 06:52:27.199243 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
888 06:52:27.203183 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
889 06:52:27.209682 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 06:52:27.212944 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 06:52:27.216552 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 06:52:27.222848 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 06:52:27.226597 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 06:52:27.229337 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 06:52:27.236341 0 11 8 | B1->B0 | 2929 3232 | 0 0 | (0 0) (0 0)
896 06:52:27.239898 0 11 12 | B1->B0 | 3c3c 4343 | 0 0 | (0 0) (0 0)
897 06:52:27.243568 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 06:52:27.249986 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 06:52:27.253042 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 06:52:27.256414 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 06:52:27.260094 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 06:52:27.267091 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 06:52:27.270116 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 06:52:27.273784 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 06:52:27.280049 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 06:52:27.283875 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 06:52:27.286544 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 06:52:27.293584 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 06:52:27.297225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 06:52:27.300221 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 06:52:27.306842 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 06:52:27.310511 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 06:52:27.313627 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 06:52:27.320598 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 06:52:27.323521 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 06:52:27.326889 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 06:52:27.330024 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 06:52:27.337074 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 06:52:27.340027 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 06:52:27.343937 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 06:52:27.346816 Total UI for P1: 0, mck2ui 16
922 06:52:27.350738 best dqsien dly found for B0: ( 0, 14, 8)
923 06:52:27.354083 Total UI for P1: 0, mck2ui 16
924 06:52:27.357326 best dqsien dly found for B1: ( 0, 14, 10)
925 06:52:27.360346 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 06:52:27.363602 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 06:52:27.364111
928 06:52:27.370822 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 06:52:27.374284 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 06:52:27.374904 [Gating] SW calibration Done
931 06:52:27.377583 ==
932 06:52:27.378057 Dram Type= 6, Freq= 0, CH_0, rank 0
933 06:52:27.383575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 06:52:27.384139 ==
935 06:52:27.384511 RX Vref Scan: 0
936 06:52:27.384860
937 06:52:27.387694 RX Vref 0 -> 0, step: 1
938 06:52:27.388273
939 06:52:27.390770 RX Delay -130 -> 252, step: 16
940 06:52:27.393951 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 06:52:27.397333 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 06:52:27.401333 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 06:52:27.407573 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 06:52:27.410639 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 06:52:27.414232 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 06:52:27.417846 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 06:52:27.420952 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 06:52:27.427772 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 06:52:27.430703 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 06:52:27.434049 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 06:52:27.438026 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 06:52:27.440608 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 06:52:27.447329 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
954 06:52:27.450914 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 06:52:27.454019 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 06:52:27.454525 ==
957 06:52:27.458351 Dram Type= 6, Freq= 0, CH_0, rank 0
958 06:52:27.461064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 06:52:27.461534 ==
960 06:52:27.464152 DQS Delay:
961 06:52:27.464620 DQS0 = 0, DQS1 = 0
962 06:52:27.464991 DQM Delay:
963 06:52:27.467558 DQM0 = 86, DQM1 = 77
964 06:52:27.468033 DQ Delay:
965 06:52:27.470738 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 06:52:27.474848 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
967 06:52:27.477504 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
968 06:52:27.481108 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
969 06:52:27.481753
970 06:52:27.482135
971 06:52:27.482524 ==
972 06:52:27.484770 Dram Type= 6, Freq= 0, CH_0, rank 0
973 06:52:27.491879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 06:52:27.492461 ==
975 06:52:27.492840
976 06:52:27.493188
977 06:52:27.493520 TX Vref Scan disable
978 06:52:27.494953 == TX Byte 0 ==
979 06:52:27.498322 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 06:52:27.504542 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 06:52:27.505013 == TX Byte 1 ==
982 06:52:27.508315 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
983 06:52:27.515480 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
984 06:52:27.515910 ==
985 06:52:27.518157 Dram Type= 6, Freq= 0, CH_0, rank 0
986 06:52:27.521557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 06:52:27.522127 ==
988 06:52:27.534832 TX Vref=22, minBit 5, minWin=26, winSum=434
989 06:52:27.537568 TX Vref=24, minBit 8, minWin=26, winSum=437
990 06:52:27.541367 TX Vref=26, minBit 5, minWin=27, winSum=440
991 06:52:27.544219 TX Vref=28, minBit 3, minWin=27, winSum=444
992 06:52:27.547824 TX Vref=30, minBit 8, minWin=27, winSum=448
993 06:52:27.551033 TX Vref=32, minBit 8, minWin=27, winSum=446
994 06:52:27.557648 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 30
995 06:52:27.558227
996 06:52:27.560904 Final TX Range 1 Vref 30
997 06:52:27.561379
998 06:52:27.561752 ==
999 06:52:27.564542 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 06:52:27.568058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 06:52:27.568640 ==
1002 06:52:27.569017
1003 06:52:27.571394
1004 06:52:27.571880 TX Vref Scan disable
1005 06:52:27.574123 == TX Byte 0 ==
1006 06:52:27.577932 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 06:52:27.581056 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 06:52:27.585267 == TX Byte 1 ==
1009 06:52:27.587985 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1010 06:52:27.591426 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1011 06:52:27.595398
1012 06:52:27.595968 [DATLAT]
1013 06:52:27.596359 Freq=800, CH0 RK0
1014 06:52:27.596707
1015 06:52:27.597670 DATLAT Default: 0xa
1016 06:52:27.598141 0, 0xFFFF, sum = 0
1017 06:52:27.601387 1, 0xFFFF, sum = 0
1018 06:52:27.601976 2, 0xFFFF, sum = 0
1019 06:52:27.604800 3, 0xFFFF, sum = 0
1020 06:52:27.605278 4, 0xFFFF, sum = 0
1021 06:52:27.608839 5, 0xFFFF, sum = 0
1022 06:52:27.609410 6, 0xFFFF, sum = 0
1023 06:52:27.611404 7, 0xFFFF, sum = 0
1024 06:52:27.611887 8, 0xFFFF, sum = 0
1025 06:52:27.615056 9, 0x0, sum = 1
1026 06:52:27.615547 10, 0x0, sum = 2
1027 06:52:27.617859 11, 0x0, sum = 3
1028 06:52:27.618332 12, 0x0, sum = 4
1029 06:52:27.622499 best_step = 10
1030 06:52:27.623053
1031 06:52:27.623421 ==
1032 06:52:27.625219 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 06:52:27.628561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 06:52:27.628982 ==
1035 06:52:27.631409 RX Vref Scan: 1
1036 06:52:27.631825
1037 06:52:27.632156 Set Vref Range= 32 -> 127
1038 06:52:27.632463
1039 06:52:27.634771 RX Vref 32 -> 127, step: 1
1040 06:52:27.635388
1041 06:52:27.638116 RX Delay -95 -> 252, step: 8
1042 06:52:27.638576
1043 06:52:27.641890 Set Vref, RX VrefLevel [Byte0]: 32
1044 06:52:27.645097 [Byte1]: 32
1045 06:52:27.645616
1046 06:52:27.648329 Set Vref, RX VrefLevel [Byte0]: 33
1047 06:52:27.652635 [Byte1]: 33
1048 06:52:27.653054
1049 06:52:27.655517 Set Vref, RX VrefLevel [Byte0]: 34
1050 06:52:27.659221 [Byte1]: 34
1051 06:52:27.659638
1052 06:52:27.662285 Set Vref, RX VrefLevel [Byte0]: 35
1053 06:52:27.666038 [Byte1]: 35
1054 06:52:27.670125
1055 06:52:27.670699 Set Vref, RX VrefLevel [Byte0]: 36
1056 06:52:27.673381 [Byte1]: 36
1057 06:52:27.677817
1058 06:52:27.678233 Set Vref, RX VrefLevel [Byte0]: 37
1059 06:52:27.680984 [Byte1]: 37
1060 06:52:27.685397
1061 06:52:27.685925 Set Vref, RX VrefLevel [Byte0]: 38
1062 06:52:27.688523 [Byte1]: 38
1063 06:52:27.693543
1064 06:52:27.694103 Set Vref, RX VrefLevel [Byte0]: 39
1065 06:52:27.696812 [Byte1]: 39
1066 06:52:27.700764
1067 06:52:27.701232 Set Vref, RX VrefLevel [Byte0]: 40
1068 06:52:27.703828 [Byte1]: 40
1069 06:52:27.707972
1070 06:52:27.708441 Set Vref, RX VrefLevel [Byte0]: 41
1071 06:52:27.711518 [Byte1]: 41
1072 06:52:27.715923
1073 06:52:27.716348 Set Vref, RX VrefLevel [Byte0]: 42
1074 06:52:27.719111 [Byte1]: 42
1075 06:52:27.723303
1076 06:52:27.723860 Set Vref, RX VrefLevel [Byte0]: 43
1077 06:52:27.726787 [Byte1]: 43
1078 06:52:27.731144
1079 06:52:27.731562 Set Vref, RX VrefLevel [Byte0]: 44
1080 06:52:27.736939 [Byte1]: 44
1081 06:52:27.737496
1082 06:52:27.740837 Set Vref, RX VrefLevel [Byte0]: 45
1083 06:52:27.744139 [Byte1]: 45
1084 06:52:27.744845
1085 06:52:27.747475 Set Vref, RX VrefLevel [Byte0]: 46
1086 06:52:27.750995 [Byte1]: 46
1087 06:52:27.751554
1088 06:52:27.754275 Set Vref, RX VrefLevel [Byte0]: 47
1089 06:52:27.757487 [Byte1]: 47
1090 06:52:27.761408
1091 06:52:27.762008 Set Vref, RX VrefLevel [Byte0]: 48
1092 06:52:27.764184 [Byte1]: 48
1093 06:52:27.769420
1094 06:52:27.770070 Set Vref, RX VrefLevel [Byte0]: 49
1095 06:52:27.772497 [Byte1]: 49
1096 06:52:27.776199
1097 06:52:27.776666 Set Vref, RX VrefLevel [Byte0]: 50
1098 06:52:27.779599 [Byte1]: 50
1099 06:52:27.783984
1100 06:52:27.784546 Set Vref, RX VrefLevel [Byte0]: 51
1101 06:52:27.787206 [Byte1]: 51
1102 06:52:27.792006
1103 06:52:27.792566 Set Vref, RX VrefLevel [Byte0]: 52
1104 06:52:27.794701 [Byte1]: 52
1105 06:52:27.799077
1106 06:52:27.799649 Set Vref, RX VrefLevel [Byte0]: 53
1107 06:52:27.802844 [Byte1]: 53
1108 06:52:27.806964
1109 06:52:27.807575 Set Vref, RX VrefLevel [Byte0]: 54
1110 06:52:27.810603 [Byte1]: 54
1111 06:52:27.814491
1112 06:52:27.815082 Set Vref, RX VrefLevel [Byte0]: 55
1113 06:52:27.818230 [Byte1]: 55
1114 06:52:27.821901
1115 06:52:27.822367 Set Vref, RX VrefLevel [Byte0]: 56
1116 06:52:27.825248 [Byte1]: 56
1117 06:52:27.829489
1118 06:52:27.830123 Set Vref, RX VrefLevel [Byte0]: 57
1119 06:52:27.833837 [Byte1]: 57
1120 06:52:27.836890
1121 06:52:27.837357 Set Vref, RX VrefLevel [Byte0]: 58
1122 06:52:27.840621 [Byte1]: 58
1123 06:52:27.844736
1124 06:52:27.845204 Set Vref, RX VrefLevel [Byte0]: 59
1125 06:52:27.847963 [Byte1]: 59
1126 06:52:27.852774
1127 06:52:27.853348 Set Vref, RX VrefLevel [Byte0]: 60
1128 06:52:27.855121 [Byte1]: 60
1129 06:52:27.859580
1130 06:52:27.860053 Set Vref, RX VrefLevel [Byte0]: 61
1131 06:52:27.863367 [Byte1]: 61
1132 06:52:27.867107
1133 06:52:27.867666 Set Vref, RX VrefLevel [Byte0]: 62
1134 06:52:27.870851 [Byte1]: 62
1135 06:52:27.874940
1136 06:52:27.875500 Set Vref, RX VrefLevel [Byte0]: 63
1137 06:52:27.878073 [Byte1]: 63
1138 06:52:27.882824
1139 06:52:27.883407 Set Vref, RX VrefLevel [Byte0]: 64
1140 06:52:27.886502 [Byte1]: 64
1141 06:52:27.889925
1142 06:52:27.890528 Set Vref, RX VrefLevel [Byte0]: 65
1143 06:52:27.893763 [Byte1]: 65
1144 06:52:27.897633
1145 06:52:27.898094 Set Vref, RX VrefLevel [Byte0]: 66
1146 06:52:27.901005 [Byte1]: 66
1147 06:52:27.905559
1148 06:52:27.906114 Set Vref, RX VrefLevel [Byte0]: 67
1149 06:52:27.908608 [Byte1]: 67
1150 06:52:27.913091
1151 06:52:27.913548 Set Vref, RX VrefLevel [Byte0]: 68
1152 06:52:27.916149 [Byte1]: 68
1153 06:52:27.920595
1154 06:52:27.921017 Set Vref, RX VrefLevel [Byte0]: 69
1155 06:52:27.923834 [Byte1]: 69
1156 06:52:27.928529
1157 06:52:27.929040 Set Vref, RX VrefLevel [Byte0]: 70
1158 06:52:27.931489 [Byte1]: 70
1159 06:52:27.935775
1160 06:52:27.936194 Set Vref, RX VrefLevel [Byte0]: 71
1161 06:52:27.939072 [Byte1]: 71
1162 06:52:27.943578
1163 06:52:27.944092 Set Vref, RX VrefLevel [Byte0]: 72
1164 06:52:27.946551 [Byte1]: 72
1165 06:52:27.951325
1166 06:52:27.951846 Set Vref, RX VrefLevel [Byte0]: 73
1167 06:52:27.953911 [Byte1]: 73
1168 06:52:27.958322
1169 06:52:27.958799 Set Vref, RX VrefLevel [Byte0]: 74
1170 06:52:27.962125 [Byte1]: 74
1171 06:52:27.966007
1172 06:52:27.966468 Set Vref, RX VrefLevel [Byte0]: 75
1173 06:52:27.969150 [Byte1]: 75
1174 06:52:27.973454
1175 06:52:27.974061 Set Vref, RX VrefLevel [Byte0]: 76
1176 06:52:27.977091 [Byte1]: 76
1177 06:52:27.981242
1178 06:52:27.981663 Set Vref, RX VrefLevel [Byte0]: 77
1179 06:52:27.984556 [Byte1]: 77
1180 06:52:27.988702
1181 06:52:27.989122 Set Vref, RX VrefLevel [Byte0]: 78
1182 06:52:27.992178 [Byte1]: 78
1183 06:52:27.996274
1184 06:52:27.996693 Final RX Vref Byte 0 = 60 to rank0
1185 06:52:27.999467 Final RX Vref Byte 1 = 58 to rank0
1186 06:52:28.003054 Final RX Vref Byte 0 = 60 to rank1
1187 06:52:28.006289 Final RX Vref Byte 1 = 58 to rank1==
1188 06:52:28.009914 Dram Type= 6, Freq= 0, CH_0, rank 0
1189 06:52:28.016453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 06:52:28.016874 ==
1191 06:52:28.017207 DQS Delay:
1192 06:52:28.017510 DQS0 = 0, DQS1 = 0
1193 06:52:28.019575 DQM Delay:
1194 06:52:28.019991 DQM0 = 87, DQM1 = 79
1195 06:52:28.023638 DQ Delay:
1196 06:52:28.024054 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1197 06:52:28.026490 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1198 06:52:28.029651 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1199 06:52:28.033026 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1200 06:52:28.033444
1201 06:52:28.036791
1202 06:52:28.043387 [DQSOSCAuto] RK0, (LSB)MR18= 0x2810, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1203 06:52:28.046550 CH0 RK0: MR19=606, MR18=2810
1204 06:52:28.053224 CH0_RK0: MR19=0x606, MR18=0x2810, DQSOSC=399, MR23=63, INC=92, DEC=61
1205 06:52:28.053752
1206 06:52:28.056592 ----->DramcWriteLeveling(PI) begin...
1207 06:52:28.057142 ==
1208 06:52:28.060156 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 06:52:28.063418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 06:52:28.063926 ==
1211 06:52:28.067081 Write leveling (Byte 0): 33 => 33
1212 06:52:28.070095 Write leveling (Byte 1): 29 => 29
1213 06:52:28.073425 DramcWriteLeveling(PI) end<-----
1214 06:52:28.073845
1215 06:52:28.074179 ==
1216 06:52:28.077556 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 06:52:28.080641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 06:52:28.081066 ==
1219 06:52:28.083515 [Gating] SW mode calibration
1220 06:52:28.090573 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1221 06:52:28.134764 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1222 06:52:28.135342 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 06:52:28.136078 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1224 06:52:28.136460 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1225 06:52:28.136802 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 06:52:28.137193 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 06:52:28.137551 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 06:52:28.137875 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 06:52:28.138187 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 06:52:28.138623 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 06:52:28.178755 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 06:52:28.179593 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 06:52:28.180035 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 06:52:28.180389 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 06:52:28.180699 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 06:52:28.181085 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 06:52:28.181394 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 06:52:28.181707 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1239 06:52:28.181998 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1240 06:52:28.182338 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1241 06:52:28.218719 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 06:52:28.219471 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 06:52:28.220484 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 06:52:28.220891 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 06:52:28.221218 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 06:52:28.221520 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 06:52:28.221836 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 06:52:28.222130 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1249 06:52:28.222578 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1250 06:52:28.223126 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 06:52:28.226710 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 06:52:28.229999 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 06:52:28.236465 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 06:52:28.240297 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 06:52:28.243714 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1256 06:52:28.250306 0 10 8 | B1->B0 | 3030 2929 | 1 0 | (1 0) (0 0)
1257 06:52:28.253064 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 06:52:28.256604 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 06:52:28.264094 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 06:52:28.267911 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 06:52:28.271756 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 06:52:28.274979 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 06:52:28.279059 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1264 06:52:28.285155 0 11 8 | B1->B0 | 2a2a 4242 | 0 0 | (0 0) (0 0)
1265 06:52:28.288922 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1266 06:52:28.293006 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 06:52:28.296153 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 06:52:28.302716 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 06:52:28.306254 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 06:52:28.310004 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 06:52:28.316615 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1272 06:52:28.319453 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1273 06:52:28.323101 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 06:52:28.329578 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 06:52:28.332797 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 06:52:28.336779 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 06:52:28.339929 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 06:52:28.347057 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 06:52:28.349981 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 06:52:28.353205 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 06:52:28.360405 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 06:52:28.363669 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 06:52:28.367070 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 06:52:28.374018 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 06:52:28.377277 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 06:52:28.380354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 06:52:28.383961 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1288 06:52:28.390572 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1289 06:52:28.394243 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1290 06:52:28.397136 Total UI for P1: 0, mck2ui 16
1291 06:52:28.400304 best dqsien dly found for B0: ( 0, 14, 6)
1292 06:52:28.404329 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1293 06:52:28.407556 Total UI for P1: 0, mck2ui 16
1294 06:52:28.410354 best dqsien dly found for B1: ( 0, 14, 10)
1295 06:52:28.413846 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1296 06:52:28.416784 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1297 06:52:28.417206
1298 06:52:28.423594 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1299 06:52:28.427335 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1300 06:52:28.427850 [Gating] SW calibration Done
1301 06:52:28.430591 ==
1302 06:52:28.433939 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 06:52:28.437496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 06:52:28.438014 ==
1305 06:52:28.438349 RX Vref Scan: 0
1306 06:52:28.438710
1307 06:52:28.440644 RX Vref 0 -> 0, step: 1
1308 06:52:28.441060
1309 06:52:28.444168 RX Delay -130 -> 252, step: 16
1310 06:52:28.447206 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1311 06:52:28.450442 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1312 06:52:28.454257 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1313 06:52:28.460479 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1314 06:52:28.463979 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1315 06:52:28.467386 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1316 06:52:28.471017 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1317 06:52:28.474272 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1318 06:52:28.480895 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1319 06:52:28.484243 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1320 06:52:28.487487 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1321 06:52:28.490911 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1322 06:52:28.494502 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1323 06:52:28.501087 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1324 06:52:28.504502 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1325 06:52:28.507980 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1326 06:52:28.508538 ==
1327 06:52:28.511470 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 06:52:28.514827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 06:52:28.515304 ==
1330 06:52:28.518085 DQS Delay:
1331 06:52:28.518746 DQS0 = 0, DQS1 = 0
1332 06:52:28.519125 DQM Delay:
1333 06:52:28.521217 DQM0 = 85, DQM1 = 75
1334 06:52:28.521689 DQ Delay:
1335 06:52:28.524251 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1336 06:52:28.528128 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1337 06:52:28.531791 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1338 06:52:28.534726 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1339 06:52:28.535289
1340 06:52:28.535657
1341 06:52:28.535995 ==
1342 06:52:28.538282 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 06:52:28.544863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 06:52:28.545451 ==
1345 06:52:28.545825
1346 06:52:28.546160
1347 06:52:28.546525 TX Vref Scan disable
1348 06:52:28.548668 == TX Byte 0 ==
1349 06:52:28.551301 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1350 06:52:28.555110 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1351 06:52:28.557959 == TX Byte 1 ==
1352 06:52:28.561709 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1353 06:52:28.565190 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1354 06:52:28.568589 ==
1355 06:52:28.569123 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 06:52:28.574887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 06:52:28.575424 ==
1358 06:52:28.587948 TX Vref=22, minBit 3, minWin=27, winSum=448
1359 06:52:28.590795 TX Vref=24, minBit 9, minWin=27, winSum=449
1360 06:52:28.594211 TX Vref=26, minBit 2, minWin=28, winSum=452
1361 06:52:28.597519 TX Vref=28, minBit 3, minWin=27, winSum=453
1362 06:52:28.600883 TX Vref=30, minBit 3, minWin=28, winSum=456
1363 06:52:28.603978 TX Vref=32, minBit 4, minWin=28, winSum=458
1364 06:52:28.610854 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 32
1365 06:52:28.611285
1366 06:52:28.614351 Final TX Range 1 Vref 32
1367 06:52:28.614812
1368 06:52:28.615138 ==
1369 06:52:28.617520 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 06:52:28.620919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 06:52:28.621343 ==
1372 06:52:28.621669
1373 06:52:28.622043
1374 06:52:28.624360 TX Vref Scan disable
1375 06:52:28.627963 == TX Byte 0 ==
1376 06:52:28.631071 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1377 06:52:28.635368 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1378 06:52:28.638504 == TX Byte 1 ==
1379 06:52:28.641354 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1380 06:52:28.644826 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1381 06:52:28.645375
1382 06:52:28.647625 [DATLAT]
1383 06:52:28.648037 Freq=800, CH0 RK1
1384 06:52:28.648367
1385 06:52:28.651126 DATLAT Default: 0xa
1386 06:52:28.651539 0, 0xFFFF, sum = 0
1387 06:52:28.654466 1, 0xFFFF, sum = 0
1388 06:52:28.654949 2, 0xFFFF, sum = 0
1389 06:52:28.657695 3, 0xFFFF, sum = 0
1390 06:52:28.658112 4, 0xFFFF, sum = 0
1391 06:52:28.661405 5, 0xFFFF, sum = 0
1392 06:52:28.661825 6, 0xFFFF, sum = 0
1393 06:52:28.665248 7, 0xFFFF, sum = 0
1394 06:52:28.665769 8, 0xFFFF, sum = 0
1395 06:52:28.668039 9, 0x0, sum = 1
1396 06:52:28.668461 10, 0x0, sum = 2
1397 06:52:28.670978 11, 0x0, sum = 3
1398 06:52:28.671397 12, 0x0, sum = 4
1399 06:52:28.674987 best_step = 10
1400 06:52:28.675499
1401 06:52:28.675828 ==
1402 06:52:28.677968 Dram Type= 6, Freq= 0, CH_0, rank 1
1403 06:52:28.681698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 06:52:28.682218 ==
1405 06:52:28.685120 RX Vref Scan: 0
1406 06:52:28.685662
1407 06:52:28.686004 RX Vref 0 -> 0, step: 1
1408 06:52:28.686313
1409 06:52:28.687999 RX Delay -95 -> 252, step: 8
1410 06:52:28.695380 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1411 06:52:28.698356 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1412 06:52:28.701631 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1413 06:52:28.704901 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1414 06:52:28.708941 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1415 06:52:28.711741 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1416 06:52:28.718813 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1417 06:52:28.721866 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1418 06:52:28.725444 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1419 06:52:28.728476 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1420 06:52:28.731732 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1421 06:52:28.738684 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1422 06:52:28.742453 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1423 06:52:28.745641 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1424 06:52:28.748694 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1425 06:52:28.752003 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1426 06:52:28.752556 ==
1427 06:52:28.755100 Dram Type= 6, Freq= 0, CH_0, rank 1
1428 06:52:28.762380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 06:52:28.762985 ==
1430 06:52:28.763362 DQS Delay:
1431 06:52:28.765518 DQS0 = 0, DQS1 = 0
1432 06:52:28.766080 DQM Delay:
1433 06:52:28.766498 DQM0 = 87, DQM1 = 77
1434 06:52:28.769415 DQ Delay:
1435 06:52:28.772450 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1436 06:52:28.775801 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1437 06:52:28.778511 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1438 06:52:28.782087 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1439 06:52:28.782697
1440 06:52:28.783064
1441 06:52:28.788788 [DQSOSCAuto] RK1, (LSB)MR18= 0x331d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1442 06:52:28.792370 CH0 RK1: MR19=606, MR18=331D
1443 06:52:28.799274 CH0_RK1: MR19=0x606, MR18=0x331D, DQSOSC=396, MR23=63, INC=94, DEC=62
1444 06:52:28.802542 [RxdqsGatingPostProcess] freq 800
1445 06:52:28.805745 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1446 06:52:28.808894 Pre-setting of DQS Precalculation
1447 06:52:28.815737 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1448 06:52:28.816299 ==
1449 06:52:28.818979 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 06:52:28.822354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 06:52:28.822945 ==
1452 06:52:28.828804 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 06:52:28.832280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 06:52:28.842485 [CA 0] Center 36 (6~66) winsize 61
1455 06:52:28.845797 [CA 1] Center 36 (6~66) winsize 61
1456 06:52:28.849387 [CA 2] Center 34 (4~65) winsize 62
1457 06:52:28.853312 [CA 3] Center 33 (3~64) winsize 62
1458 06:52:28.856135 [CA 4] Center 34 (4~65) winsize 62
1459 06:52:28.859041 [CA 5] Center 33 (3~64) winsize 62
1460 06:52:28.859498
1461 06:52:28.863019 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1462 06:52:28.863580
1463 06:52:28.865642 [CATrainingPosCal] consider 1 rank data
1464 06:52:28.869929 u2DelayCellTimex100 = 270/100 ps
1465 06:52:28.873165 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1466 06:52:28.876523 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1467 06:52:28.879715 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1468 06:52:28.886767 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1469 06:52:28.889604 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1470 06:52:28.893043 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1471 06:52:28.893499
1472 06:52:28.896030 CA PerBit enable=1, Macro0, CA PI delay=33
1473 06:52:28.896488
1474 06:52:28.899732 [CBTSetCACLKResult] CA Dly = 33
1475 06:52:28.900249 CS Dly: 5 (0~36)
1476 06:52:28.900580 ==
1477 06:52:28.902899 Dram Type= 6, Freq= 0, CH_1, rank 1
1478 06:52:28.906430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 06:52:28.909786 ==
1480 06:52:28.912759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1481 06:52:28.919940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1482 06:52:28.929016 [CA 0] Center 36 (6~67) winsize 62
1483 06:52:28.932341 [CA 1] Center 36 (6~67) winsize 62
1484 06:52:28.936613 [CA 2] Center 34 (4~65) winsize 62
1485 06:52:28.939978 [CA 3] Center 33 (3~64) winsize 62
1486 06:52:28.943615 [CA 4] Center 34 (4~65) winsize 62
1487 06:52:28.944078 [CA 5] Center 33 (3~64) winsize 62
1488 06:52:28.948185
1489 06:52:28.948597 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1490 06:52:28.948926
1491 06:52:28.951853 [CATrainingPosCal] consider 2 rank data
1492 06:52:28.955559 u2DelayCellTimex100 = 270/100 ps
1493 06:52:28.959499 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1494 06:52:28.962626 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1495 06:52:28.966199 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1496 06:52:28.970236 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1497 06:52:28.973322 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1498 06:52:28.976547 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1499 06:52:28.976999
1500 06:52:28.983677 CA PerBit enable=1, Macro0, CA PI delay=33
1501 06:52:28.984199
1502 06:52:28.984533 [CBTSetCACLKResult] CA Dly = 33
1503 06:52:28.986926 CS Dly: 5 (0~37)
1504 06:52:28.987447
1505 06:52:28.989741 ----->DramcWriteLeveling(PI) begin...
1506 06:52:28.990163 ==
1507 06:52:28.993213 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 06:52:28.996505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 06:52:28.997044 ==
1510 06:52:28.999860 Write leveling (Byte 0): 28 => 28
1511 06:52:29.003350 Write leveling (Byte 1): 27 => 27
1512 06:52:29.007102 DramcWriteLeveling(PI) end<-----
1513 06:52:29.007617
1514 06:52:29.007949 ==
1515 06:52:29.009658 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 06:52:29.013512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 06:52:29.014035 ==
1518 06:52:29.016896 [Gating] SW mode calibration
1519 06:52:29.023526 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1520 06:52:29.030459 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1521 06:52:29.033779 0 6 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)
1522 06:52:29.040865 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1523 06:52:29.043345 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1524 06:52:29.047095 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 06:52:29.050509 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 06:52:29.056998 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 06:52:29.060238 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 06:52:29.063676 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 06:52:29.070673 0 7 0 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1530 06:52:29.074194 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 06:52:29.077057 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 06:52:29.084494 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 06:52:29.087605 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 06:52:29.090981 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 06:52:29.097559 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 06:52:29.100836 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 06:52:29.104135 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1538 06:52:29.107386 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1539 06:52:29.114191 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 06:52:29.117456 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 06:52:29.121112 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 06:52:29.127402 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 06:52:29.130909 0 8 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1544 06:52:29.134176 0 8 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1545 06:52:29.140824 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 06:52:29.144131 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 06:52:29.147658 0 9 8 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1548 06:52:29.154343 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 06:52:29.157856 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 06:52:29.161190 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 06:52:29.164325 0 9 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1552 06:52:29.171065 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 06:52:29.174906 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1554 06:52:29.178002 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 06:52:29.184510 0 10 8 | B1->B0 | 2c2c 2c2c | 0 0 | (1 1) (1 1)
1556 06:52:29.188103 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 06:52:29.191081 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1558 06:52:29.197923 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1559 06:52:29.201379 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 06:52:29.204878 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 06:52:29.211980 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 06:52:29.214455 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1563 06:52:29.218216 0 11 8 | B1->B0 | 3838 3333 | 0 0 | (0 0) (0 0)
1564 06:52:29.225025 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 06:52:29.228065 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 06:52:29.231462 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 06:52:29.234865 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 06:52:29.241800 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 06:52:29.245194 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 06:52:29.248549 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 06:52:29.255582 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1572 06:52:29.258618 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 06:52:29.261983 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 06:52:29.268684 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 06:52:29.272327 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 06:52:29.275220 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 06:52:29.281547 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 06:52:29.284948 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 06:52:29.288748 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 06:52:29.295247 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 06:52:29.298170 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 06:52:29.301863 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 06:52:29.308345 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 06:52:29.311712 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 06:52:29.314976 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 06:52:29.318264 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1587 06:52:29.324967 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1588 06:52:29.329095 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1589 06:52:29.331688 Total UI for P1: 0, mck2ui 16
1590 06:52:29.335126 best dqsien dly found for B0: ( 0, 14, 6)
1591 06:52:29.338858 Total UI for P1: 0, mck2ui 16
1592 06:52:29.341794 best dqsien dly found for B1: ( 0, 14, 6)
1593 06:52:29.344933 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1594 06:52:29.348533 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1595 06:52:29.349115
1596 06:52:29.352533 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1597 06:52:29.355527 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1598 06:52:29.358455 [Gating] SW calibration Done
1599 06:52:29.358923 ==
1600 06:52:29.362028 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 06:52:29.365713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 06:52:29.366306 ==
1603 06:52:29.368747 RX Vref Scan: 0
1604 06:52:29.369361
1605 06:52:29.372765 RX Vref 0 -> 0, step: 1
1606 06:52:29.373330
1607 06:52:29.373700 RX Delay -130 -> 252, step: 16
1608 06:52:29.378664 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1609 06:52:29.381796 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1610 06:52:29.385616 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1611 06:52:29.389469 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1612 06:52:29.392221 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1613 06:52:29.399341 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1614 06:52:29.402341 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1615 06:52:29.405970 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1616 06:52:29.408817 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1617 06:52:29.412283 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1618 06:52:29.419025 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1619 06:52:29.422875 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1620 06:52:29.425645 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1621 06:52:29.429414 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1622 06:52:29.432749 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1623 06:52:29.439000 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1624 06:52:29.439561 ==
1625 06:52:29.442545 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 06:52:29.445783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 06:52:29.446249 ==
1628 06:52:29.446707 DQS Delay:
1629 06:52:29.448986 DQS0 = 0, DQS1 = 0
1630 06:52:29.449451 DQM Delay:
1631 06:52:29.452480 DQM0 = 81, DQM1 = 76
1632 06:52:29.453039 DQ Delay:
1633 06:52:29.455668 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1634 06:52:29.459235 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =69
1635 06:52:29.462250 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1636 06:52:29.466452 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1637 06:52:29.466955
1638 06:52:29.467330
1639 06:52:29.467667 ==
1640 06:52:29.469713 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 06:52:29.472337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 06:52:29.472810 ==
1643 06:52:29.473180
1644 06:52:29.473520
1645 06:52:29.476095 TX Vref Scan disable
1646 06:52:29.479521 == TX Byte 0 ==
1647 06:52:29.482944 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1648 06:52:29.486168 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1649 06:52:29.489717 == TX Byte 1 ==
1650 06:52:29.492881 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1651 06:52:29.496546 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1652 06:52:29.497109 ==
1653 06:52:29.499701 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 06:52:29.503120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 06:52:29.503697 ==
1656 06:52:29.517925 TX Vref=22, minBit 10, minWin=26, winSum=436
1657 06:52:29.521497 TX Vref=24, minBit 3, minWin=27, winSum=440
1658 06:52:29.524816 TX Vref=26, minBit 0, minWin=27, winSum=442
1659 06:52:29.527821 TX Vref=28, minBit 1, minWin=27, winSum=445
1660 06:52:29.531593 TX Vref=30, minBit 1, minWin=27, winSum=449
1661 06:52:29.534519 TX Vref=32, minBit 9, minWin=27, winSum=449
1662 06:52:29.541066 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 30
1663 06:52:29.541628
1664 06:52:29.544803 Final TX Range 1 Vref 30
1665 06:52:29.545392
1666 06:52:29.545765 ==
1667 06:52:29.548180 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 06:52:29.551922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 06:52:29.552390 ==
1670 06:52:29.552759
1671 06:52:29.553099
1672 06:52:29.554651 TX Vref Scan disable
1673 06:52:29.558213 == TX Byte 0 ==
1674 06:52:29.561204 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1675 06:52:29.564362 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1676 06:52:29.568373 == TX Byte 1 ==
1677 06:52:29.571246 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1678 06:52:29.574439 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1679 06:52:29.574869
1680 06:52:29.578183 [DATLAT]
1681 06:52:29.578746 Freq=800, CH1 RK0
1682 06:52:29.579085
1683 06:52:29.581387 DATLAT Default: 0xa
1684 06:52:29.581809 0, 0xFFFF, sum = 0
1685 06:52:29.584874 1, 0xFFFF, sum = 0
1686 06:52:29.585403 2, 0xFFFF, sum = 0
1687 06:52:29.588210 3, 0xFFFF, sum = 0
1688 06:52:29.588745 4, 0xFFFF, sum = 0
1689 06:52:29.591924 5, 0xFFFF, sum = 0
1690 06:52:29.592449 6, 0xFFFF, sum = 0
1691 06:52:29.594784 7, 0xFFFF, sum = 0
1692 06:52:29.595208 8, 0xFFFF, sum = 0
1693 06:52:29.598862 9, 0x0, sum = 1
1694 06:52:29.599388 10, 0x0, sum = 2
1695 06:52:29.601735 11, 0x0, sum = 3
1696 06:52:29.602164 12, 0x0, sum = 4
1697 06:52:29.602549 best_step = 10
1698 06:52:29.605245
1699 06:52:29.605758 ==
1700 06:52:29.608796 Dram Type= 6, Freq= 0, CH_1, rank 0
1701 06:52:29.611782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1702 06:52:29.612213 ==
1703 06:52:29.612553 RX Vref Scan: 1
1704 06:52:29.612864
1705 06:52:29.615084 Set Vref Range= 32 -> 127
1706 06:52:29.615504
1707 06:52:29.618539 RX Vref 32 -> 127, step: 1
1708 06:52:29.618961
1709 06:52:29.621682 RX Delay -111 -> 252, step: 8
1710 06:52:29.622104
1711 06:52:29.624996 Set Vref, RX VrefLevel [Byte0]: 32
1712 06:52:29.628731 [Byte1]: 32
1713 06:52:29.629275
1714 06:52:29.631788 Set Vref, RX VrefLevel [Byte0]: 33
1715 06:52:29.635119 [Byte1]: 33
1716 06:52:29.635591
1717 06:52:29.638666 Set Vref, RX VrefLevel [Byte0]: 34
1718 06:52:29.642647 [Byte1]: 34
1719 06:52:29.645632
1720 06:52:29.646187 Set Vref, RX VrefLevel [Byte0]: 35
1721 06:52:29.649062 [Byte1]: 35
1722 06:52:29.653299
1723 06:52:29.653815 Set Vref, RX VrefLevel [Byte0]: 36
1724 06:52:29.656560 [Byte1]: 36
1725 06:52:29.660434
1726 06:52:29.660855 Set Vref, RX VrefLevel [Byte0]: 37
1727 06:52:29.664090 [Byte1]: 37
1728 06:52:29.668378
1729 06:52:29.668893 Set Vref, RX VrefLevel [Byte0]: 38
1730 06:52:29.671637 [Byte1]: 38
1731 06:52:29.675697
1732 06:52:29.676215 Set Vref, RX VrefLevel [Byte0]: 39
1733 06:52:29.679272 [Byte1]: 39
1734 06:52:29.683499
1735 06:52:29.683915 Set Vref, RX VrefLevel [Byte0]: 40
1736 06:52:29.687260 [Byte1]: 40
1737 06:52:29.691006
1738 06:52:29.691426 Set Vref, RX VrefLevel [Byte0]: 41
1739 06:52:29.694645 [Byte1]: 41
1740 06:52:29.698740
1741 06:52:29.699159 Set Vref, RX VrefLevel [Byte0]: 42
1742 06:52:29.702321 [Byte1]: 42
1743 06:52:29.706299
1744 06:52:29.706758 Set Vref, RX VrefLevel [Byte0]: 43
1745 06:52:29.709986 [Byte1]: 43
1746 06:52:29.714843
1747 06:52:29.715427 Set Vref, RX VrefLevel [Byte0]: 44
1748 06:52:29.717778 [Byte1]: 44
1749 06:52:29.722810
1750 06:52:29.723367 Set Vref, RX VrefLevel [Byte0]: 45
1751 06:52:29.724912 [Byte1]: 45
1752 06:52:29.729183
1753 06:52:29.729647 Set Vref, RX VrefLevel [Byte0]: 46
1754 06:52:29.732695 [Byte1]: 46
1755 06:52:29.737197
1756 06:52:29.737759 Set Vref, RX VrefLevel [Byte0]: 47
1757 06:52:29.740756 [Byte1]: 47
1758 06:52:29.745387
1759 06:52:29.745946 Set Vref, RX VrefLevel [Byte0]: 48
1760 06:52:29.748179 [Byte1]: 48
1761 06:52:29.752535
1762 06:52:29.753001 Set Vref, RX VrefLevel [Byte0]: 49
1763 06:52:29.755433 [Byte1]: 49
1764 06:52:29.760162
1765 06:52:29.760706 Set Vref, RX VrefLevel [Byte0]: 50
1766 06:52:29.763340 [Byte1]: 50
1767 06:52:29.767456
1768 06:52:29.767890 Set Vref, RX VrefLevel [Byte0]: 51
1769 06:52:29.771120 [Byte1]: 51
1770 06:52:29.775405
1771 06:52:29.775923 Set Vref, RX VrefLevel [Byte0]: 52
1772 06:52:29.779352 [Byte1]: 52
1773 06:52:29.783063
1774 06:52:29.783584 Set Vref, RX VrefLevel [Byte0]: 53
1775 06:52:29.786219 [Byte1]: 53
1776 06:52:29.790591
1777 06:52:29.791018 Set Vref, RX VrefLevel [Byte0]: 54
1778 06:52:29.794582 [Byte1]: 54
1779 06:52:29.798670
1780 06:52:29.799187 Set Vref, RX VrefLevel [Byte0]: 55
1781 06:52:29.801648 [Byte1]: 55
1782 06:52:29.806321
1783 06:52:29.806894 Set Vref, RX VrefLevel [Byte0]: 56
1784 06:52:29.809200 [Byte1]: 56
1785 06:52:29.813651
1786 06:52:29.814197 Set Vref, RX VrefLevel [Byte0]: 57
1787 06:52:29.818477 [Byte1]: 57
1788 06:52:29.820872
1789 06:52:29.821299 Set Vref, RX VrefLevel [Byte0]: 58
1790 06:52:29.824134 [Byte1]: 58
1791 06:52:29.829682
1792 06:52:29.830105 Set Vref, RX VrefLevel [Byte0]: 59
1793 06:52:29.832130 [Byte1]: 59
1794 06:52:29.836572
1795 06:52:29.837068 Set Vref, RX VrefLevel [Byte0]: 60
1796 06:52:29.839955 [Byte1]: 60
1797 06:52:29.844391
1798 06:52:29.844901 Set Vref, RX VrefLevel [Byte0]: 61
1799 06:52:29.847327 [Byte1]: 61
1800 06:52:29.851933
1801 06:52:29.852450 Set Vref, RX VrefLevel [Byte0]: 62
1802 06:52:29.854991 [Byte1]: 62
1803 06:52:29.859254
1804 06:52:29.859676 Set Vref, RX VrefLevel [Byte0]: 63
1805 06:52:29.862935 [Byte1]: 63
1806 06:52:29.867271
1807 06:52:29.867694 Set Vref, RX VrefLevel [Byte0]: 64
1808 06:52:29.870507 [Byte1]: 64
1809 06:52:29.874492
1810 06:52:29.878269 Set Vref, RX VrefLevel [Byte0]: 65
1811 06:52:29.878853 [Byte1]: 65
1812 06:52:29.882076
1813 06:52:29.882613 Set Vref, RX VrefLevel [Byte0]: 66
1814 06:52:29.886038 [Byte1]: 66
1815 06:52:29.890149
1816 06:52:29.890745 Set Vref, RX VrefLevel [Byte0]: 67
1817 06:52:29.893218 [Byte1]: 67
1818 06:52:29.897435
1819 06:52:29.897854 Set Vref, RX VrefLevel [Byte0]: 68
1820 06:52:29.900994 [Byte1]: 68
1821 06:52:29.905784
1822 06:52:29.906200 Set Vref, RX VrefLevel [Byte0]: 69
1823 06:52:29.908866 [Byte1]: 69
1824 06:52:29.913118
1825 06:52:29.913631 Set Vref, RX VrefLevel [Byte0]: 70
1826 06:52:29.916741 [Byte1]: 70
1827 06:52:29.920647
1828 06:52:29.921204 Set Vref, RX VrefLevel [Byte0]: 71
1829 06:52:29.924106 [Byte1]: 71
1830 06:52:29.927984
1831 06:52:29.928461 Set Vref, RX VrefLevel [Byte0]: 72
1832 06:52:29.931509 [Byte1]: 72
1833 06:52:29.936482
1834 06:52:29.936944 Set Vref, RX VrefLevel [Byte0]: 73
1835 06:52:29.939182 [Byte1]: 73
1836 06:52:29.943860
1837 06:52:29.944378 Set Vref, RX VrefLevel [Byte0]: 74
1838 06:52:29.946602 [Byte1]: 74
1839 06:52:29.951223
1840 06:52:29.951641 Set Vref, RX VrefLevel [Byte0]: 75
1841 06:52:29.954436 [Byte1]: 75
1842 06:52:29.959106
1843 06:52:29.959659 Set Vref, RX VrefLevel [Byte0]: 76
1844 06:52:29.962013 [Byte1]: 76
1845 06:52:29.966072
1846 06:52:29.966534 Set Vref, RX VrefLevel [Byte0]: 77
1847 06:52:29.969938 [Byte1]: 77
1848 06:52:29.974524
1849 06:52:29.975100 Set Vref, RX VrefLevel [Byte0]: 78
1850 06:52:29.977477 [Byte1]: 78
1851 06:52:29.982225
1852 06:52:29.982861 Final RX Vref Byte 0 = 65 to rank0
1853 06:52:29.985534 Final RX Vref Byte 1 = 60 to rank0
1854 06:52:29.988998 Final RX Vref Byte 0 = 65 to rank1
1855 06:52:29.992158 Final RX Vref Byte 1 = 60 to rank1==
1856 06:52:29.995267 Dram Type= 6, Freq= 0, CH_1, rank 0
1857 06:52:29.998855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1858 06:52:30.002519 ==
1859 06:52:30.003103 DQS Delay:
1860 06:52:30.003472 DQS0 = 0, DQS1 = 0
1861 06:52:30.005066 DQM Delay:
1862 06:52:30.005526 DQM0 = 84, DQM1 = 74
1863 06:52:30.008898 DQ Delay:
1864 06:52:30.012005 DQ0 =92, DQ1 =76, DQ2 =72, DQ3 =84
1865 06:52:30.012584 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1866 06:52:30.015206 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1867 06:52:30.018585 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1868 06:52:30.021989
1869 06:52:30.022597
1870 06:52:30.028881 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e03, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1871 06:52:30.032319 CH1 RK0: MR19=606, MR18=2E03
1872 06:52:30.039079 CH1_RK0: MR19=0x606, MR18=0x2E03, DQSOSC=398, MR23=63, INC=93, DEC=62
1873 06:52:30.039670
1874 06:52:30.042372 ----->DramcWriteLeveling(PI) begin...
1875 06:52:30.042985 ==
1876 06:52:30.045668 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 06:52:30.049101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 06:52:30.049719 ==
1879 06:52:30.051895 Write leveling (Byte 0): 26 => 26
1880 06:52:30.055332 Write leveling (Byte 1): 27 => 27
1881 06:52:30.058736 DramcWriteLeveling(PI) end<-----
1882 06:52:30.059202
1883 06:52:30.059565 ==
1884 06:52:30.062184 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 06:52:30.065732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 06:52:30.066203 ==
1887 06:52:30.069522 [Gating] SW mode calibration
1888 06:52:30.076031 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1889 06:52:30.082575 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1890 06:52:30.086512 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1891 06:52:30.089388 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1892 06:52:30.093035 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 06:52:30.099179 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 06:52:30.102568 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 06:52:30.106015 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 06:52:30.112564 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 06:52:30.115828 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 06:52:30.118953 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 06:52:30.125953 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 06:52:30.129645 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 06:52:30.132907 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 06:52:30.139285 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1903 06:52:30.142568 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1904 06:52:30.145840 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1905 06:52:30.152665 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1906 06:52:30.155877 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1907 06:52:30.159682 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1908 06:52:30.166035 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1909 06:52:30.169671 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1910 06:52:30.172676 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 06:52:30.176227 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 06:52:30.182903 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 06:52:30.185817 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 06:52:30.189269 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 06:52:30.196520 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1916 06:52:30.199589 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1917 06:52:30.203277 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1918 06:52:30.209591 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 06:52:30.213220 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 06:52:30.216275 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1921 06:52:30.223102 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 06:52:30.226428 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1923 06:52:30.229409 0 10 4 | B1->B0 | 3232 2f2f | 1 1 | (0 0) (1 0)
1924 06:52:30.233022 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1925 06:52:30.240054 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1926 06:52:30.243015 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 06:52:30.246456 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 06:52:30.253729 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 06:52:30.256943 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 06:52:30.259997 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1931 06:52:30.266889 0 11 4 | B1->B0 | 2b2b 3434 | 1 0 | (0 0) (0 0)
1932 06:52:30.269850 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1933 06:52:30.273567 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 06:52:30.276912 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 06:52:30.283917 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 06:52:30.286676 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 06:52:30.289917 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 06:52:30.297124 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 06:52:30.300315 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1940 06:52:30.303556 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1941 06:52:30.310598 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 06:52:30.314287 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 06:52:30.317348 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 06:52:30.323929 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 06:52:30.326830 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 06:52:30.330701 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 06:52:30.337423 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 06:52:30.341412 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 06:52:30.343819 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 06:52:30.347512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 06:52:30.354268 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 06:52:30.357534 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 06:52:30.360711 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 06:52:30.367761 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 06:52:30.370840 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1956 06:52:30.374003 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1957 06:52:30.377198 Total UI for P1: 0, mck2ui 16
1958 06:52:30.381007 best dqsien dly found for B0: ( 0, 14, 4)
1959 06:52:30.383643 Total UI for P1: 0, mck2ui 16
1960 06:52:30.387873 best dqsien dly found for B1: ( 0, 14, 4)
1961 06:52:30.390931 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1962 06:52:30.394827 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1963 06:52:30.395347
1964 06:52:30.397385 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1965 06:52:30.404144 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1966 06:52:30.404711 [Gating] SW calibration Done
1967 06:52:30.405084 ==
1968 06:52:30.407755 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 06:52:30.414792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 06:52:30.415351 ==
1971 06:52:30.415730 RX Vref Scan: 0
1972 06:52:30.416078
1973 06:52:30.417963 RX Vref 0 -> 0, step: 1
1974 06:52:30.418560
1975 06:52:30.421045 RX Delay -130 -> 252, step: 16
1976 06:52:30.423950 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1977 06:52:30.427575 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1978 06:52:30.431407 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1979 06:52:30.437661 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1980 06:52:30.441171 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1981 06:52:30.444497 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1982 06:52:30.447773 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1983 06:52:30.451115 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1984 06:52:30.454805 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1985 06:52:30.461196 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1986 06:52:30.464304 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1987 06:52:30.468208 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1988 06:52:30.470976 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1989 06:52:30.474499 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1990 06:52:30.481473 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1991 06:52:30.484857 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1992 06:52:30.485420 ==
1993 06:52:30.488067 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 06:52:30.491585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 06:52:30.492096 ==
1996 06:52:30.494941 DQS Delay:
1997 06:52:30.495505 DQS0 = 0, DQS1 = 0
1998 06:52:30.495872 DQM Delay:
1999 06:52:30.497903 DQM0 = 80, DQM1 = 76
2000 06:52:30.498362 DQ Delay:
2001 06:52:30.501236 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
2002 06:52:30.505144 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
2003 06:52:30.508329 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
2004 06:52:30.511774 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2005 06:52:30.512345
2006 06:52:30.512714
2007 06:52:30.513056 ==
2008 06:52:30.514511 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 06:52:30.518144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 06:52:30.521123 ==
2011 06:52:30.521535
2012 06:52:30.521862
2013 06:52:30.522163 TX Vref Scan disable
2014 06:52:30.525162 == TX Byte 0 ==
2015 06:52:30.528365 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2016 06:52:30.531610 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2017 06:52:30.534965 == TX Byte 1 ==
2018 06:52:30.538076 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2019 06:52:30.541699 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2020 06:52:30.542220 ==
2021 06:52:30.545180 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 06:52:30.551565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 06:52:30.552092 ==
2024 06:52:30.563433 TX Vref=22, minBit 1, minWin=27, winSum=441
2025 06:52:30.566623 TX Vref=24, minBit 1, minWin=27, winSum=442
2026 06:52:30.570501 TX Vref=26, minBit 1, minWin=27, winSum=446
2027 06:52:30.573815 TX Vref=28, minBit 11, minWin=27, winSum=447
2028 06:52:30.577247 TX Vref=30, minBit 11, minWin=27, winSum=448
2029 06:52:30.583554 TX Vref=32, minBit 15, minWin=27, winSum=450
2030 06:52:30.587184 [TxChooseVref] Worse bit 15, Min win 27, Win sum 450, Final Vref 32
2031 06:52:30.587642
2032 06:52:30.590644 Final TX Range 1 Vref 32
2033 06:52:30.591209
2034 06:52:30.591575 ==
2035 06:52:30.594103 Dram Type= 6, Freq= 0, CH_1, rank 1
2036 06:52:30.597534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2037 06:52:30.598103 ==
2038 06:52:30.600756
2039 06:52:30.601315
2040 06:52:30.601681 TX Vref Scan disable
2041 06:52:30.603515 == TX Byte 0 ==
2042 06:52:30.607894 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2043 06:52:30.610311 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2044 06:52:30.613890 == TX Byte 1 ==
2045 06:52:30.616905 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2046 06:52:30.620656 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2047 06:52:30.621075
2048 06:52:30.623829 [DATLAT]
2049 06:52:30.624242 Freq=800, CH1 RK1
2050 06:52:30.624569
2051 06:52:30.627237 DATLAT Default: 0xa
2052 06:52:30.627652 0, 0xFFFF, sum = 0
2053 06:52:30.630559 1, 0xFFFF, sum = 0
2054 06:52:30.630983 2, 0xFFFF, sum = 0
2055 06:52:30.633957 3, 0xFFFF, sum = 0
2056 06:52:30.634381 4, 0xFFFF, sum = 0
2057 06:52:30.637966 5, 0xFFFF, sum = 0
2058 06:52:30.638545 6, 0xFFFF, sum = 0
2059 06:52:30.640690 7, 0xFFFF, sum = 0
2060 06:52:30.641113 8, 0xFFFF, sum = 0
2061 06:52:30.644697 9, 0x0, sum = 1
2062 06:52:30.645221 10, 0x0, sum = 2
2063 06:52:30.647265 11, 0x0, sum = 3
2064 06:52:30.647691 12, 0x0, sum = 4
2065 06:52:30.650598 best_step = 10
2066 06:52:30.651018
2067 06:52:30.651352 ==
2068 06:52:30.653913 Dram Type= 6, Freq= 0, CH_1, rank 1
2069 06:52:30.657768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2070 06:52:30.658290 ==
2071 06:52:30.661182 RX Vref Scan: 0
2072 06:52:30.661596
2073 06:52:30.661920 RX Vref 0 -> 0, step: 1
2074 06:52:30.662227
2075 06:52:30.664110 RX Delay -111 -> 252, step: 8
2076 06:52:30.670767 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2077 06:52:30.674342 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2078 06:52:30.677604 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2079 06:52:30.681077 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2080 06:52:30.684006 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2081 06:52:30.687879 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2082 06:52:30.694491 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2083 06:52:30.697973 iDelay=201, Bit 7, Center 76 (-39 ~ 192) 232
2084 06:52:30.701295 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2085 06:52:30.704591 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2086 06:52:30.708187 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2087 06:52:30.714537 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2088 06:52:30.718287 iDelay=201, Bit 12, Center 84 (-31 ~ 200) 232
2089 06:52:30.721473 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2090 06:52:30.724962 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2091 06:52:30.728056 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2092 06:52:30.731128 ==
2093 06:52:30.734801 Dram Type= 6, Freq= 0, CH_1, rank 1
2094 06:52:30.738084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2095 06:52:30.738694 ==
2096 06:52:30.739046 DQS Delay:
2097 06:52:30.741192 DQS0 = 0, DQS1 = 0
2098 06:52:30.741605 DQM Delay:
2099 06:52:30.744584 DQM0 = 79, DQM1 = 76
2100 06:52:30.745102 DQ Delay:
2101 06:52:30.748197 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =76
2102 06:52:30.751346 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
2103 06:52:30.754977 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2104 06:52:30.757960 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2105 06:52:30.758540
2106 06:52:30.758884
2107 06:52:30.764509 [DQSOSCAuto] RK1, (LSB)MR18= 0x2430, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2108 06:52:30.768206 CH1 RK1: MR19=606, MR18=2430
2109 06:52:30.775350 CH1_RK1: MR19=0x606, MR18=0x2430, DQSOSC=397, MR23=63, INC=93, DEC=62
2110 06:52:30.778289 [RxdqsGatingPostProcess] freq 800
2111 06:52:30.782441 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2112 06:52:30.785176 Pre-setting of DQS Precalculation
2113 06:52:30.791832 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2114 06:52:30.798547 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2115 06:52:30.805043 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2116 06:52:30.805466
2117 06:52:30.805793
2118 06:52:30.808508 [Calibration Summary] 1600 Mbps
2119 06:52:30.809000 CH 0, Rank 0
2120 06:52:30.811757 SW Impedance : PASS
2121 06:52:30.814594 DUTY Scan : NO K
2122 06:52:30.815017 ZQ Calibration : PASS
2123 06:52:30.818072 Jitter Meter : NO K
2124 06:52:30.821788 CBT Training : PASS
2125 06:52:30.822211 Write leveling : PASS
2126 06:52:30.824773 RX DQS gating : PASS
2127 06:52:30.825190 RX DQ/DQS(RDDQC) : PASS
2128 06:52:30.828623 TX DQ/DQS : PASS
2129 06:52:30.831833 RX DATLAT : PASS
2130 06:52:30.832253 RX DQ/DQS(Engine): PASS
2131 06:52:30.834662 TX OE : NO K
2132 06:52:30.835080 All Pass.
2133 06:52:30.835410
2134 06:52:30.838210 CH 0, Rank 1
2135 06:52:30.838723 SW Impedance : PASS
2136 06:52:30.841554 DUTY Scan : NO K
2137 06:52:30.845037 ZQ Calibration : PASS
2138 06:52:30.845552 Jitter Meter : NO K
2139 06:52:30.848201 CBT Training : PASS
2140 06:52:30.851199 Write leveling : PASS
2141 06:52:30.851618 RX DQS gating : PASS
2142 06:52:30.854920 RX DQ/DQS(RDDQC) : PASS
2143 06:52:30.858483 TX DQ/DQS : PASS
2144 06:52:30.859060 RX DATLAT : PASS
2145 06:52:30.861579 RX DQ/DQS(Engine): PASS
2146 06:52:30.864827 TX OE : NO K
2147 06:52:30.865285 All Pass.
2148 06:52:30.865623
2149 06:52:30.865956 CH 1, Rank 0
2150 06:52:30.868784 SW Impedance : PASS
2151 06:52:30.869203 DUTY Scan : NO K
2152 06:52:30.871411 ZQ Calibration : PASS
2153 06:52:30.875035 Jitter Meter : NO K
2154 06:52:30.875454 CBT Training : PASS
2155 06:52:30.878527 Write leveling : PASS
2156 06:52:30.881846 RX DQS gating : PASS
2157 06:52:30.882452 RX DQ/DQS(RDDQC) : PASS
2158 06:52:30.885518 TX DQ/DQS : PASS
2159 06:52:30.888884 RX DATLAT : PASS
2160 06:52:30.889303 RX DQ/DQS(Engine): PASS
2161 06:52:30.891732 TX OE : NO K
2162 06:52:30.892153 All Pass.
2163 06:52:30.892481
2164 06:52:30.895047 CH 1, Rank 1
2165 06:52:30.895466 SW Impedance : PASS
2166 06:52:30.898464 DUTY Scan : NO K
2167 06:52:30.902283 ZQ Calibration : PASS
2168 06:52:30.902822 Jitter Meter : NO K
2169 06:52:30.905600 CBT Training : PASS
2170 06:52:30.906019 Write leveling : PASS
2171 06:52:30.908622 RX DQS gating : PASS
2172 06:52:30.912244 RX DQ/DQS(RDDQC) : PASS
2173 06:52:30.912801 TX DQ/DQS : PASS
2174 06:52:30.915547 RX DATLAT : PASS
2175 06:52:30.918457 RX DQ/DQS(Engine): PASS
2176 06:52:30.918881 TX OE : NO K
2177 06:52:30.922001 All Pass.
2178 06:52:30.922448
2179 06:52:30.922782 DramC Write-DBI off
2180 06:52:30.925649 PER_BANK_REFRESH: Hybrid Mode
2181 06:52:30.926141 TX_TRACKING: ON
2182 06:52:30.929072 [GetDramInforAfterCalByMRR] Vendor 6.
2183 06:52:30.934849 [GetDramInforAfterCalByMRR] Revision 606.
2184 06:52:30.938515 [GetDramInforAfterCalByMRR] Revision 2 0.
2185 06:52:30.938934 MR0 0x3b3b
2186 06:52:30.939268 MR8 0x5151
2187 06:52:30.942312 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2188 06:52:30.943025
2189 06:52:30.945170 MR0 0x3b3b
2190 06:52:30.945684 MR8 0x5151
2191 06:52:30.948633 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2192 06:52:30.949277
2193 06:52:30.958930 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2194 06:52:30.962372 [FAST_K] Save calibration result to emmc
2195 06:52:30.965667 [FAST_K] Save calibration result to emmc
2196 06:52:30.968864 dram_init: config_dvfs: 1
2197 06:52:30.972711 dramc_set_vcore_voltage set vcore to 662500
2198 06:52:30.973135 Read voltage for 1200, 2
2199 06:52:30.975454 Vio18 = 0
2200 06:52:30.975876 Vcore = 662500
2201 06:52:30.976211 Vdram = 0
2202 06:52:30.979160 Vddq = 0
2203 06:52:30.979583 Vmddr = 0
2204 06:52:30.982191 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2205 06:52:30.988979 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2206 06:52:30.992460 MEM_TYPE=3, freq_sel=15
2207 06:52:30.995885 sv_algorithm_assistance_LP4_1600
2208 06:52:30.999245 ============ PULL DRAM RESETB DOWN ============
2209 06:52:31.002905 ========== PULL DRAM RESETB DOWN end =========
2210 06:52:31.006530 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2211 06:52:31.009436 ===================================
2212 06:52:31.012757 LPDDR4 DRAM CONFIGURATION
2213 06:52:31.015928 ===================================
2214 06:52:31.019443 EX_ROW_EN[0] = 0x0
2215 06:52:31.019858 EX_ROW_EN[1] = 0x0
2216 06:52:31.023190 LP4Y_EN = 0x0
2217 06:52:31.023607 WORK_FSP = 0x0
2218 06:52:31.026280 WL = 0x4
2219 06:52:31.026757 RL = 0x4
2220 06:52:31.029264 BL = 0x2
2221 06:52:31.029685 RPST = 0x0
2222 06:52:31.033063 RD_PRE = 0x0
2223 06:52:31.033481 WR_PRE = 0x1
2224 06:52:31.035992 WR_PST = 0x0
2225 06:52:31.036410 DBI_WR = 0x0
2226 06:52:31.039507 DBI_RD = 0x0
2227 06:52:31.039930 OTF = 0x1
2228 06:52:31.042894 ===================================
2229 06:52:31.046258 ===================================
2230 06:52:31.050015 ANA top config
2231 06:52:31.053387 ===================================
2232 06:52:31.056191 DLL_ASYNC_EN = 0
2233 06:52:31.056612 ALL_SLAVE_EN = 0
2234 06:52:31.059363 NEW_RANK_MODE = 1
2235 06:52:31.063417 DLL_IDLE_MODE = 1
2236 06:52:31.066532 LP45_APHY_COMB_EN = 1
2237 06:52:31.066954 TX_ODT_DIS = 1
2238 06:52:31.069990 NEW_8X_MODE = 1
2239 06:52:31.073655 ===================================
2240 06:52:31.076328 ===================================
2241 06:52:31.079884 data_rate = 2400
2242 06:52:31.083281 CKR = 1
2243 06:52:31.086517 DQ_P2S_RATIO = 8
2244 06:52:31.089698 ===================================
2245 06:52:31.090121 CA_P2S_RATIO = 8
2246 06:52:31.093416 DQ_CA_OPEN = 0
2247 06:52:31.096765 DQ_SEMI_OPEN = 0
2248 06:52:31.100433 CA_SEMI_OPEN = 0
2249 06:52:31.103510 CA_FULL_RATE = 0
2250 06:52:31.106924 DQ_CKDIV4_EN = 0
2251 06:52:31.107355 CA_CKDIV4_EN = 0
2252 06:52:31.109937 CA_PREDIV_EN = 0
2253 06:52:31.113256 PH8_DLY = 17
2254 06:52:31.116899 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2255 06:52:31.120562 DQ_AAMCK_DIV = 4
2256 06:52:31.123791 CA_AAMCK_DIV = 4
2257 06:52:31.124337 CA_ADMCK_DIV = 4
2258 06:52:31.126702 DQ_TRACK_CA_EN = 0
2259 06:52:31.129939 CA_PICK = 1200
2260 06:52:31.133448 CA_MCKIO = 1200
2261 06:52:31.136982 MCKIO_SEMI = 0
2262 06:52:31.140057 PLL_FREQ = 2366
2263 06:52:31.143666 DQ_UI_PI_RATIO = 32
2264 06:52:31.144085 CA_UI_PI_RATIO = 0
2265 06:52:31.147056 ===================================
2266 06:52:31.150361 ===================================
2267 06:52:31.154168 memory_type:LPDDR4
2268 06:52:31.157460 GP_NUM : 10
2269 06:52:31.157874 SRAM_EN : 1
2270 06:52:31.160185 MD32_EN : 0
2271 06:52:31.163596 ===================================
2272 06:52:31.166956 [ANA_INIT] >>>>>>>>>>>>>>
2273 06:52:31.167404 <<<<<< [CONFIGURE PHASE]: ANA_TX
2274 06:52:31.170674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2275 06:52:31.173776 ===================================
2276 06:52:31.177377 data_rate = 2400,PCW = 0X5b00
2277 06:52:31.180539 ===================================
2278 06:52:31.183657 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2279 06:52:31.190614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2280 06:52:31.197689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2281 06:52:31.201472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2282 06:52:31.203858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2283 06:52:31.207316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2284 06:52:31.211430 [ANA_INIT] flow start
2285 06:52:31.211952 [ANA_INIT] PLL >>>>>>>>
2286 06:52:31.214346 [ANA_INIT] PLL <<<<<<<<
2287 06:52:31.217268 [ANA_INIT] MIDPI >>>>>>>>
2288 06:52:31.217687 [ANA_INIT] MIDPI <<<<<<<<
2289 06:52:31.221171 [ANA_INIT] DLL >>>>>>>>
2290 06:52:31.224239 [ANA_INIT] DLL <<<<<<<<
2291 06:52:31.224654 [ANA_INIT] flow end
2292 06:52:31.227791 ============ LP4 DIFF to SE enter ============
2293 06:52:31.234234 ============ LP4 DIFF to SE exit ============
2294 06:52:31.234685 [ANA_INIT] <<<<<<<<<<<<<
2295 06:52:31.237874 [Flow] Enable top DCM control >>>>>
2296 06:52:31.241235 [Flow] Enable top DCM control <<<<<
2297 06:52:31.244314 Enable DLL master slave shuffle
2298 06:52:31.251369 ==============================================================
2299 06:52:31.251893 Gating Mode config
2300 06:52:31.258104 ==============================================================
2301 06:52:31.261099 Config description:
2302 06:52:31.270704 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2303 06:52:31.274787 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2304 06:52:31.281418 SELPH_MODE 0: By rank 1: By Phase
2305 06:52:31.288238 ==============================================================
2306 06:52:31.288803 GAT_TRACK_EN = 1
2307 06:52:31.292065 RX_GATING_MODE = 2
2308 06:52:31.294975 RX_GATING_TRACK_MODE = 2
2309 06:52:31.298255 SELPH_MODE = 1
2310 06:52:31.301588 PICG_EARLY_EN = 1
2311 06:52:31.305452 VALID_LAT_VALUE = 1
2312 06:52:31.311148 ==============================================================
2313 06:52:31.315149 Enter into Gating configuration >>>>
2314 06:52:31.317841 Exit from Gating configuration <<<<
2315 06:52:31.321002 Enter into DVFS_PRE_config >>>>>
2316 06:52:31.330977 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2317 06:52:31.334631 Exit from DVFS_PRE_config <<<<<
2318 06:52:31.337853 Enter into PICG configuration >>>>
2319 06:52:31.341355 Exit from PICG configuration <<<<
2320 06:52:31.341868 [RX_INPUT] configuration >>>>>
2321 06:52:31.344756 [RX_INPUT] configuration <<<<<
2322 06:52:31.352025 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2323 06:52:31.354964 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2324 06:52:31.361485 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2325 06:52:31.368648 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2326 06:52:31.375022 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2327 06:52:31.381829 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2328 06:52:31.384624 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2329 06:52:31.388411 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2330 06:52:31.391966 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2331 06:52:31.399178 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2332 06:52:31.401867 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2333 06:52:31.405781 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2334 06:52:31.408341 ===================================
2335 06:52:31.412074 LPDDR4 DRAM CONFIGURATION
2336 06:52:31.415973 ===================================
2337 06:52:31.416490 EX_ROW_EN[0] = 0x0
2338 06:52:31.418931 EX_ROW_EN[1] = 0x0
2339 06:52:31.421918 LP4Y_EN = 0x0
2340 06:52:31.422337 WORK_FSP = 0x0
2341 06:52:31.426448 WL = 0x4
2342 06:52:31.426870 RL = 0x4
2343 06:52:31.429034 BL = 0x2
2344 06:52:31.429560 RPST = 0x0
2345 06:52:31.432566 RD_PRE = 0x0
2346 06:52:31.433082 WR_PRE = 0x1
2347 06:52:31.436110 WR_PST = 0x0
2348 06:52:31.436529 DBI_WR = 0x0
2349 06:52:31.439041 DBI_RD = 0x0
2350 06:52:31.439462 OTF = 0x1
2351 06:52:31.442352 ===================================
2352 06:52:31.446001 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2353 06:52:31.452498 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2354 06:52:31.455904 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2355 06:52:31.458865 ===================================
2356 06:52:31.462247 LPDDR4 DRAM CONFIGURATION
2357 06:52:31.465582 ===================================
2358 06:52:31.466006 EX_ROW_EN[0] = 0x10
2359 06:52:31.468961 EX_ROW_EN[1] = 0x0
2360 06:52:31.469378 LP4Y_EN = 0x0
2361 06:52:31.472644 WORK_FSP = 0x0
2362 06:52:31.473106 WL = 0x4
2363 06:52:31.475513 RL = 0x4
2364 06:52:31.475931 BL = 0x2
2365 06:52:31.478899 RPST = 0x0
2366 06:52:31.479349 RD_PRE = 0x0
2367 06:52:31.482490 WR_PRE = 0x1
2368 06:52:31.482909 WR_PST = 0x0
2369 06:52:31.485602 DBI_WR = 0x0
2370 06:52:31.486019 DBI_RD = 0x0
2371 06:52:31.489175 OTF = 0x1
2372 06:52:31.492938 ===================================
2373 06:52:31.499289 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2374 06:52:31.499823 ==
2375 06:52:31.502992 Dram Type= 6, Freq= 0, CH_0, rank 0
2376 06:52:31.506385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 06:52:31.506958 ==
2378 06:52:31.509554 [Duty_Offset_Calibration]
2379 06:52:31.509976 B0:2 B1:-1 CA:1
2380 06:52:31.510310
2381 06:52:31.513316 [DutyScan_Calibration_Flow] k_type=0
2382 06:52:31.522815
2383 06:52:31.523390 ==CLK 0==
2384 06:52:31.525677 Final CLK duty delay cell = -4
2385 06:52:31.529113 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2386 06:52:31.532419 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2387 06:52:31.536266 [-4] AVG Duty = 4953%(X100)
2388 06:52:31.536836
2389 06:52:31.539174 CH0 CLK Duty spec in!! Max-Min= 156%
2390 06:52:31.543422 [DutyScan_Calibration_Flow] ====Done====
2391 06:52:31.543987
2392 06:52:31.546156 [DutyScan_Calibration_Flow] k_type=1
2393 06:52:31.561273
2394 06:52:31.561865 ==DQS 0 ==
2395 06:52:31.564522 Final DQS duty delay cell = 0
2396 06:52:31.567928 [0] MAX Duty = 5125%(X100), DQS PI = 48
2397 06:52:31.571036 [0] MIN Duty = 5000%(X100), DQS PI = 14
2398 06:52:31.571500 [0] AVG Duty = 5062%(X100)
2399 06:52:31.574519
2400 06:52:31.575091 ==DQS 1 ==
2401 06:52:31.577949 Final DQS duty delay cell = -4
2402 06:52:31.581573 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2403 06:52:31.584510 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2404 06:52:31.588531 [-4] AVG Duty = 5062%(X100)
2405 06:52:31.589057
2406 06:52:31.591448 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2407 06:52:31.591966
2408 06:52:31.594991 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2409 06:52:31.598222 [DutyScan_Calibration_Flow] ====Done====
2410 06:52:31.598793
2411 06:52:31.601305 [DutyScan_Calibration_Flow] k_type=3
2412 06:52:31.618588
2413 06:52:31.619152 ==DQM 0 ==
2414 06:52:31.621621 Final DQM duty delay cell = 0
2415 06:52:31.624993 [0] MAX Duty = 5031%(X100), DQS PI = 54
2416 06:52:31.628152 [0] MIN Duty = 4907%(X100), DQS PI = 0
2417 06:52:31.628727 [0] AVG Duty = 4969%(X100)
2418 06:52:31.631218
2419 06:52:31.631676 ==DQM 1 ==
2420 06:52:31.634864 Final DQM duty delay cell = 0
2421 06:52:31.638460 [0] MAX Duty = 5124%(X100), DQS PI = 32
2422 06:52:31.641584 [0] MIN Duty = 5000%(X100), DQS PI = 8
2423 06:52:31.642059 [0] AVG Duty = 5062%(X100)
2424 06:52:31.642475
2425 06:52:31.644838 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2426 06:52:31.649178
2427 06:52:31.651839 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2428 06:52:31.654848 [DutyScan_Calibration_Flow] ====Done====
2429 06:52:31.655315
2430 06:52:31.658477 [DutyScan_Calibration_Flow] k_type=2
2431 06:52:31.673833
2432 06:52:31.674431 ==DQ 0 ==
2433 06:52:31.677288 Final DQ duty delay cell = -4
2434 06:52:31.680758 [-4] MAX Duty = 5093%(X100), DQS PI = 54
2435 06:52:31.683648 [-4] MIN Duty = 4875%(X100), DQS PI = 18
2436 06:52:31.687701 [-4] AVG Duty = 4984%(X100)
2437 06:52:31.688282
2438 06:52:31.688650 ==DQ 1 ==
2439 06:52:31.690216 Final DQ duty delay cell = 0
2440 06:52:31.693842 [0] MAX Duty = 5031%(X100), DQS PI = 18
2441 06:52:31.697162 [0] MIN Duty = 4907%(X100), DQS PI = 46
2442 06:52:31.697689 [0] AVG Duty = 4969%(X100)
2443 06:52:31.698025
2444 06:52:31.700901 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2445 06:52:31.704357
2446 06:52:31.707768 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2447 06:52:31.710674 [DutyScan_Calibration_Flow] ====Done====
2448 06:52:31.711204 ==
2449 06:52:31.715110 Dram Type= 6, Freq= 0, CH_1, rank 0
2450 06:52:31.717385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2451 06:52:31.717939 ==
2452 06:52:31.720972 [Duty_Offset_Calibration]
2453 06:52:31.721530 B0:1 B1:1 CA:2
2454 06:52:31.721898
2455 06:52:31.723687 [DutyScan_Calibration_Flow] k_type=0
2456 06:52:31.733868
2457 06:52:31.734363 ==CLK 0==
2458 06:52:31.737733 Final CLK duty delay cell = 0
2459 06:52:31.740546 [0] MAX Duty = 5187%(X100), DQS PI = 24
2460 06:52:31.744101 [0] MIN Duty = 4969%(X100), DQS PI = 40
2461 06:52:31.744639 [0] AVG Duty = 5078%(X100)
2462 06:52:31.747151
2463 06:52:31.747570 CH1 CLK Duty spec in!! Max-Min= 218%
2464 06:52:31.754097 [DutyScan_Calibration_Flow] ====Done====
2465 06:52:31.754667
2466 06:52:31.757564 [DutyScan_Calibration_Flow] k_type=1
2467 06:52:31.772965
2468 06:52:31.773476 ==DQS 0 ==
2469 06:52:31.776588 Final DQS duty delay cell = 0
2470 06:52:31.780055 [0] MAX Duty = 5031%(X100), DQS PI = 18
2471 06:52:31.783051 [0] MIN Duty = 4844%(X100), DQS PI = 50
2472 06:52:31.783473 [0] AVG Duty = 4937%(X100)
2473 06:52:31.786425
2474 06:52:31.786855 ==DQS 1 ==
2475 06:52:31.789840 Final DQS duty delay cell = 0
2476 06:52:31.793455 [0] MAX Duty = 5062%(X100), DQS PI = 36
2477 06:52:31.796939 [0] MIN Duty = 4907%(X100), DQS PI = 16
2478 06:52:31.797460 [0] AVG Duty = 4984%(X100)
2479 06:52:31.800082
2480 06:52:31.802990 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2481 06:52:31.803416
2482 06:52:31.807191 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2483 06:52:31.809847 [DutyScan_Calibration_Flow] ====Done====
2484 06:52:31.810269
2485 06:52:31.813610 [DutyScan_Calibration_Flow] k_type=3
2486 06:52:31.830028
2487 06:52:31.830573 ==DQM 0 ==
2488 06:52:31.833294 Final DQM duty delay cell = 0
2489 06:52:31.836403 [0] MAX Duty = 5093%(X100), DQS PI = 18
2490 06:52:31.840303 [0] MIN Duty = 4907%(X100), DQS PI = 48
2491 06:52:31.840867 [0] AVG Duty = 5000%(X100)
2492 06:52:31.843744
2493 06:52:31.844300 ==DQM 1 ==
2494 06:52:31.846542 Final DQM duty delay cell = 0
2495 06:52:31.850896 [0] MAX Duty = 5156%(X100), DQS PI = 62
2496 06:52:31.853339 [0] MIN Duty = 4938%(X100), DQS PI = 22
2497 06:52:31.853898 [0] AVG Duty = 5047%(X100)
2498 06:52:31.856728
2499 06:52:31.860043 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2500 06:52:31.860510
2501 06:52:31.863187 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2502 06:52:31.866738 [DutyScan_Calibration_Flow] ====Done====
2503 06:52:31.867203
2504 06:52:31.869936 [DutyScan_Calibration_Flow] k_type=2
2505 06:52:31.886717
2506 06:52:31.887277 ==DQ 0 ==
2507 06:52:31.889624 Final DQ duty delay cell = 0
2508 06:52:31.893380 [0] MAX Duty = 5093%(X100), DQS PI = 18
2509 06:52:31.896555 [0] MIN Duty = 4907%(X100), DQS PI = 50
2510 06:52:31.897117 [0] AVG Duty = 5000%(X100)
2511 06:52:31.897489
2512 06:52:31.900191 ==DQ 1 ==
2513 06:52:31.903571 Final DQ duty delay cell = 0
2514 06:52:31.907136 [0] MAX Duty = 5124%(X100), DQS PI = 58
2515 06:52:31.910036 [0] MIN Duty = 5031%(X100), DQS PI = 2
2516 06:52:31.910585 [0] AVG Duty = 5077%(X100)
2517 06:52:31.910966
2518 06:52:31.912993 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2519 06:52:31.913554
2520 06:52:31.916607 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2521 06:52:31.919845 [DutyScan_Calibration_Flow] ====Done====
2522 06:52:31.925346 nWR fixed to 30
2523 06:52:31.928604 [ModeRegInit_LP4] CH0 RK0
2524 06:52:31.929054 [ModeRegInit_LP4] CH0 RK1
2525 06:52:31.932009 [ModeRegInit_LP4] CH1 RK0
2526 06:52:31.935694 [ModeRegInit_LP4] CH1 RK1
2527 06:52:31.936218 match AC timing 7
2528 06:52:31.942305 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2529 06:52:31.945856 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2530 06:52:31.949011 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2531 06:52:31.955680 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2532 06:52:31.958632 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2533 06:52:31.959065 ==
2534 06:52:31.962671 Dram Type= 6, Freq= 0, CH_0, rank 0
2535 06:52:31.966259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 06:52:31.966733 ==
2537 06:52:31.972030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2538 06:52:31.979120 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2539 06:52:31.986324 [CA 0] Center 40 (10~71) winsize 62
2540 06:52:31.989800 [CA 1] Center 39 (9~70) winsize 62
2541 06:52:31.993401 [CA 2] Center 36 (6~67) winsize 62
2542 06:52:31.996611 [CA 3] Center 36 (6~66) winsize 61
2543 06:52:31.999846 [CA 4] Center 34 (4~65) winsize 62
2544 06:52:32.003458 [CA 5] Center 34 (4~64) winsize 61
2545 06:52:32.004026
2546 06:52:32.007138 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2547 06:52:32.007710
2548 06:52:32.009993 [CATrainingPosCal] consider 1 rank data
2549 06:52:32.013469 u2DelayCellTimex100 = 270/100 ps
2550 06:52:32.017133 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2551 06:52:32.019699 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2552 06:52:32.022973 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2553 06:52:32.030041 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2554 06:52:32.033358 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2555 06:52:32.036808 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2556 06:52:32.037239
2557 06:52:32.040134 CA PerBit enable=1, Macro0, CA PI delay=34
2558 06:52:32.040662
2559 06:52:32.044000 [CBTSetCACLKResult] CA Dly = 34
2560 06:52:32.044523 CS Dly: 7 (0~38)
2561 06:52:32.044867 ==
2562 06:52:32.046918 Dram Type= 6, Freq= 0, CH_0, rank 1
2563 06:52:32.053407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 06:52:32.053931 ==
2565 06:52:32.057666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2566 06:52:32.063496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2567 06:52:32.072014 [CA 0] Center 39 (9~70) winsize 62
2568 06:52:32.075594 [CA 1] Center 39 (9~70) winsize 62
2569 06:52:32.078893 [CA 2] Center 36 (6~67) winsize 62
2570 06:52:32.082572 [CA 3] Center 36 (5~67) winsize 63
2571 06:52:32.085820 [CA 4] Center 34 (4~65) winsize 62
2572 06:52:32.089441 [CA 5] Center 34 (4~64) winsize 61
2573 06:52:32.089969
2574 06:52:32.092214 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2575 06:52:32.092745
2576 06:52:32.095821 [CATrainingPosCal] consider 2 rank data
2577 06:52:32.099355 u2DelayCellTimex100 = 270/100 ps
2578 06:52:32.102463 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2579 06:52:32.105511 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2580 06:52:32.112482 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2581 06:52:32.115798 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2582 06:52:32.119250 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2583 06:52:32.123013 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2584 06:52:32.123634
2585 06:52:32.125764 CA PerBit enable=1, Macro0, CA PI delay=34
2586 06:52:32.126322
2587 06:52:32.128955 [CBTSetCACLKResult] CA Dly = 34
2588 06:52:32.129420 CS Dly: 8 (0~41)
2589 06:52:32.129787
2590 06:52:32.132226 ----->DramcWriteLeveling(PI) begin...
2591 06:52:32.132697 ==
2592 06:52:32.136006 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 06:52:32.142630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 06:52:32.143193 ==
2595 06:52:32.145993 Write leveling (Byte 0): 31 => 31
2596 06:52:32.149774 Write leveling (Byte 1): 28 => 28
2597 06:52:32.150389 DramcWriteLeveling(PI) end<-----
2598 06:52:32.150857
2599 06:52:32.152638 ==
2600 06:52:32.155973 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 06:52:32.159049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 06:52:32.159521 ==
2603 06:52:32.162896 [Gating] SW mode calibration
2604 06:52:32.169409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2605 06:52:32.172404 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2606 06:52:32.179657 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 06:52:32.182532 0 15 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2608 06:52:32.186185 0 15 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2609 06:52:32.193385 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 06:52:32.196461 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 06:52:32.199439 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 06:52:32.203144 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2613 06:52:32.209875 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2614 06:52:32.212930 1 0 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2615 06:52:32.216846 1 0 4 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
2616 06:52:32.222856 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 06:52:32.226286 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 06:52:32.230221 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 06:52:32.236326 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 06:52:32.240282 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 06:52:32.243306 1 0 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2622 06:52:32.249853 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2623 06:52:32.253384 1 1 4 | B1->B0 | 3939 4242 | 1 0 | (0 0) (0 0)
2624 06:52:32.257258 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 06:52:32.260169 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 06:52:32.266965 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 06:52:32.270053 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 06:52:32.273542 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 06:52:32.280236 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 06:52:32.283636 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2631 06:52:32.286730 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 06:52:32.293930 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 06:52:32.296896 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 06:52:32.300644 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 06:52:32.307358 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 06:52:32.310796 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 06:52:32.314560 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 06:52:32.317241 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 06:52:32.324377 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 06:52:32.327778 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 06:52:32.331024 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 06:52:32.337356 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 06:52:32.341158 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 06:52:32.344353 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 06:52:32.350885 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 06:52:32.354323 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2647 06:52:32.357815 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2648 06:52:32.360769 Total UI for P1: 0, mck2ui 16
2649 06:52:32.364021 best dqsien dly found for B0: ( 1, 4, 0)
2650 06:52:32.367187 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2651 06:52:32.370941 Total UI for P1: 0, mck2ui 16
2652 06:52:32.374263 best dqsien dly found for B1: ( 1, 4, 2)
2653 06:52:32.378127 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2654 06:52:32.381067 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2655 06:52:32.384587
2656 06:52:32.387780 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2657 06:52:32.391127 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2658 06:52:32.391567 [Gating] SW calibration Done
2659 06:52:32.394994 ==
2660 06:52:32.397833 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 06:52:32.401088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 06:52:32.401613 ==
2663 06:52:32.401954 RX Vref Scan: 0
2664 06:52:32.402271
2665 06:52:32.404637 RX Vref 0 -> 0, step: 1
2666 06:52:32.405166
2667 06:52:32.408733 RX Delay -40 -> 252, step: 8
2668 06:52:32.411121 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2669 06:52:32.414540 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2670 06:52:32.418050 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2671 06:52:32.424678 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2672 06:52:32.428203 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2673 06:52:32.431190 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2674 06:52:32.434600 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2675 06:52:32.438117 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2676 06:52:32.444817 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2677 06:52:32.447553 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2678 06:52:32.451047 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2679 06:52:32.455086 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2680 06:52:32.458647 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2681 06:52:32.461425 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2682 06:52:32.468282 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2683 06:52:32.471596 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2684 06:52:32.472026 ==
2685 06:52:32.474875 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 06:52:32.478387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 06:52:32.478872 ==
2688 06:52:32.481381 DQS Delay:
2689 06:52:32.481806 DQS0 = 0, DQS1 = 0
2690 06:52:32.482143 DQM Delay:
2691 06:52:32.484898 DQM0 = 116, DQM1 = 107
2692 06:52:32.485335 DQ Delay:
2693 06:52:32.488039 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2694 06:52:32.492156 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2695 06:52:32.494845 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2696 06:52:32.501786 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2697 06:52:32.502314
2698 06:52:32.502715
2699 06:52:32.503035 ==
2700 06:52:32.505019 Dram Type= 6, Freq= 0, CH_0, rank 0
2701 06:52:32.508724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2702 06:52:32.509270 ==
2703 06:52:32.509615
2704 06:52:32.509927
2705 06:52:32.512376 TX Vref Scan disable
2706 06:52:32.512908 == TX Byte 0 ==
2707 06:52:32.518102 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2708 06:52:32.521945 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2709 06:52:32.522372 == TX Byte 1 ==
2710 06:52:32.528423 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2711 06:52:32.532122 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2712 06:52:32.532659 ==
2713 06:52:32.535645 Dram Type= 6, Freq= 0, CH_0, rank 0
2714 06:52:32.538155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2715 06:52:32.538645 ==
2716 06:52:32.550959 TX Vref=22, minBit 1, minWin=24, winSum=418
2717 06:52:32.554626 TX Vref=24, minBit 7, minWin=25, winSum=427
2718 06:52:32.557583 TX Vref=26, minBit 0, minWin=26, winSum=432
2719 06:52:32.560767 TX Vref=28, minBit 0, minWin=26, winSum=432
2720 06:52:32.564411 TX Vref=30, minBit 1, minWin=26, winSum=436
2721 06:52:32.567359 TX Vref=32, minBit 1, minWin=26, winSum=435
2722 06:52:32.574856 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 30
2723 06:52:32.575404
2724 06:52:32.577937 Final TX Range 1 Vref 30
2725 06:52:32.578537
2726 06:52:32.578954 ==
2727 06:52:32.581149 Dram Type= 6, Freq= 0, CH_0, rank 0
2728 06:52:32.584060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2729 06:52:32.584486 ==
2730 06:52:32.584826
2731 06:52:32.585135
2732 06:52:32.587915 TX Vref Scan disable
2733 06:52:32.591470 == TX Byte 0 ==
2734 06:52:32.595334 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2735 06:52:32.598118 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2736 06:52:32.601402 == TX Byte 1 ==
2737 06:52:32.604919 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2738 06:52:32.608686 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2739 06:52:32.609215
2740 06:52:32.611113 [DATLAT]
2741 06:52:32.611673 Freq=1200, CH0 RK0
2742 06:52:32.612138
2743 06:52:32.615014 DATLAT Default: 0xd
2744 06:52:32.615539 0, 0xFFFF, sum = 0
2745 06:52:32.617583 1, 0xFFFF, sum = 0
2746 06:52:32.618009 2, 0xFFFF, sum = 0
2747 06:52:32.621499 3, 0xFFFF, sum = 0
2748 06:52:32.621925 4, 0xFFFF, sum = 0
2749 06:52:32.624565 5, 0xFFFF, sum = 0
2750 06:52:32.624992 6, 0xFFFF, sum = 0
2751 06:52:32.627732 7, 0xFFFF, sum = 0
2752 06:52:32.628159 8, 0xFFFF, sum = 0
2753 06:52:32.631578 9, 0xFFFF, sum = 0
2754 06:52:32.632274 10, 0xFFFF, sum = 0
2755 06:52:32.634840 11, 0xFFFF, sum = 0
2756 06:52:32.635362 12, 0x0, sum = 1
2757 06:52:32.638222 13, 0x0, sum = 2
2758 06:52:32.638691 14, 0x0, sum = 3
2759 06:52:32.641047 15, 0x0, sum = 4
2760 06:52:32.641473 best_step = 13
2761 06:52:32.641808
2762 06:52:32.642119 ==
2763 06:52:32.644895 Dram Type= 6, Freq= 0, CH_0, rank 0
2764 06:52:32.651321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2765 06:52:32.651838 ==
2766 06:52:32.652175 RX Vref Scan: 1
2767 06:52:32.652491
2768 06:52:32.654732 Set Vref Range= 32 -> 127
2769 06:52:32.655154
2770 06:52:32.658746 RX Vref 32 -> 127, step: 1
2771 06:52:32.659261
2772 06:52:32.659598 RX Delay -21 -> 252, step: 4
2773 06:52:32.659914
2774 06:52:32.661348 Set Vref, RX VrefLevel [Byte0]: 32
2775 06:52:32.664551 [Byte1]: 32
2776 06:52:32.669326
2777 06:52:32.669745 Set Vref, RX VrefLevel [Byte0]: 33
2778 06:52:32.672958 [Byte1]: 33
2779 06:52:32.677524
2780 06:52:32.678041 Set Vref, RX VrefLevel [Byte0]: 34
2781 06:52:32.680684 [Byte1]: 34
2782 06:52:32.685344
2783 06:52:32.685874 Set Vref, RX VrefLevel [Byte0]: 35
2784 06:52:32.688124 [Byte1]: 35
2785 06:52:32.694581
2786 06:52:32.695105 Set Vref, RX VrefLevel [Byte0]: 36
2787 06:52:32.695856 [Byte1]: 36
2788 06:52:32.700998
2789 06:52:32.701505 Set Vref, RX VrefLevel [Byte0]: 37
2790 06:52:32.704371 [Byte1]: 37
2791 06:52:32.708885
2792 06:52:32.709403 Set Vref, RX VrefLevel [Byte0]: 38
2793 06:52:32.712630 [Byte1]: 38
2794 06:52:32.717043
2795 06:52:32.717558 Set Vref, RX VrefLevel [Byte0]: 39
2796 06:52:32.720214 [Byte1]: 39
2797 06:52:32.724779
2798 06:52:32.725304 Set Vref, RX VrefLevel [Byte0]: 40
2799 06:52:32.727919 [Byte1]: 40
2800 06:52:32.732463
2801 06:52:32.733036 Set Vref, RX VrefLevel [Byte0]: 41
2802 06:52:32.736207 [Byte1]: 41
2803 06:52:32.740743
2804 06:52:32.741326 Set Vref, RX VrefLevel [Byte0]: 42
2805 06:52:32.743829 [Byte1]: 42
2806 06:52:32.748764
2807 06:52:32.749337 Set Vref, RX VrefLevel [Byte0]: 43
2808 06:52:32.751924 [Byte1]: 43
2809 06:52:32.756554
2810 06:52:32.757124 Set Vref, RX VrefLevel [Byte0]: 44
2811 06:52:32.760017 [Byte1]: 44
2812 06:52:32.764245
2813 06:52:32.764831 Set Vref, RX VrefLevel [Byte0]: 45
2814 06:52:32.767496 [Byte1]: 45
2815 06:52:32.773069
2816 06:52:32.773682 Set Vref, RX VrefLevel [Byte0]: 46
2817 06:52:32.775418 [Byte1]: 46
2818 06:52:32.780094
2819 06:52:32.780647 Set Vref, RX VrefLevel [Byte0]: 47
2820 06:52:32.783155 [Byte1]: 47
2821 06:52:32.787845
2822 06:52:32.788389 Set Vref, RX VrefLevel [Byte0]: 48
2823 06:52:32.791838 [Byte1]: 48
2824 06:52:32.795697
2825 06:52:32.796114 Set Vref, RX VrefLevel [Byte0]: 49
2826 06:52:32.799359 [Byte1]: 49
2827 06:52:32.804344
2828 06:52:32.804862 Set Vref, RX VrefLevel [Byte0]: 50
2829 06:52:32.807407 [Byte1]: 50
2830 06:52:32.811668
2831 06:52:32.812108 Set Vref, RX VrefLevel [Byte0]: 51
2832 06:52:32.815396 [Byte1]: 51
2833 06:52:32.819977
2834 06:52:32.820531 Set Vref, RX VrefLevel [Byte0]: 52
2835 06:52:32.823392 [Byte1]: 52
2836 06:52:32.827783
2837 06:52:32.828339 Set Vref, RX VrefLevel [Byte0]: 53
2838 06:52:32.830917 [Byte1]: 53
2839 06:52:32.835764
2840 06:52:32.836321 Set Vref, RX VrefLevel [Byte0]: 54
2841 06:52:32.838612 [Byte1]: 54
2842 06:52:32.843536
2843 06:52:32.844094 Set Vref, RX VrefLevel [Byte0]: 55
2844 06:52:32.846864 [Byte1]: 55
2845 06:52:32.851737
2846 06:52:32.852295 Set Vref, RX VrefLevel [Byte0]: 56
2847 06:52:32.854780 [Byte1]: 56
2848 06:52:32.859783
2849 06:52:32.860338 Set Vref, RX VrefLevel [Byte0]: 57
2850 06:52:32.862770 [Byte1]: 57
2851 06:52:32.867534
2852 06:52:32.868017 Set Vref, RX VrefLevel [Byte0]: 58
2853 06:52:32.870976 [Byte1]: 58
2854 06:52:32.875522
2855 06:52:32.875974 Set Vref, RX VrefLevel [Byte0]: 59
2856 06:52:32.878715 [Byte1]: 59
2857 06:52:32.883204
2858 06:52:32.883629 Set Vref, RX VrefLevel [Byte0]: 60
2859 06:52:32.886278 [Byte1]: 60
2860 06:52:32.891240
2861 06:52:32.891656 Set Vref, RX VrefLevel [Byte0]: 61
2862 06:52:32.894952 [Byte1]: 61
2863 06:52:32.898932
2864 06:52:32.899348 Set Vref, RX VrefLevel [Byte0]: 62
2865 06:52:32.902111 [Byte1]: 62
2866 06:52:32.907232
2867 06:52:32.907743 Set Vref, RX VrefLevel [Byte0]: 63
2868 06:52:32.910490 [Byte1]: 63
2869 06:52:32.915194
2870 06:52:32.915704 Set Vref, RX VrefLevel [Byte0]: 64
2871 06:52:32.918467 [Byte1]: 64
2872 06:52:32.922701
2873 06:52:32.923216 Set Vref, RX VrefLevel [Byte0]: 65
2874 06:52:32.926456 [Byte1]: 65
2875 06:52:32.930326
2876 06:52:32.930801 Set Vref, RX VrefLevel [Byte0]: 66
2877 06:52:32.933653 [Byte1]: 66
2878 06:52:32.938952
2879 06:52:32.939474 Set Vref, RX VrefLevel [Byte0]: 67
2880 06:52:32.942074 [Byte1]: 67
2881 06:52:32.946641
2882 06:52:32.947063 Set Vref, RX VrefLevel [Byte0]: 68
2883 06:52:32.949924 [Byte1]: 68
2884 06:52:32.954141
2885 06:52:32.954644 Final RX Vref Byte 0 = 52 to rank0
2886 06:52:32.958186 Final RX Vref Byte 1 = 51 to rank0
2887 06:52:32.961150 Final RX Vref Byte 0 = 52 to rank1
2888 06:52:32.964819 Final RX Vref Byte 1 = 51 to rank1==
2889 06:52:32.967640 Dram Type= 6, Freq= 0, CH_0, rank 0
2890 06:52:32.974840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 06:52:32.975362 ==
2892 06:52:32.975700 DQS Delay:
2893 06:52:32.976011 DQS0 = 0, DQS1 = 0
2894 06:52:32.977781 DQM Delay:
2895 06:52:32.978200 DQM0 = 115, DQM1 = 104
2896 06:52:32.981571 DQ Delay:
2897 06:52:32.984629 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2898 06:52:32.987660 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2899 06:52:32.991478 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2900 06:52:32.995339 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2901 06:52:32.995853
2902 06:52:32.996189
2903 06:52:33.001838 [DQSOSCAuto] RK0, (LSB)MR18= 0xffef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2904 06:52:33.005188 CH0 RK0: MR19=303, MR18=FFEF
2905 06:52:33.011440 CH0_RK0: MR19=0x303, MR18=0xFFEF, DQSOSC=410, MR23=63, INC=39, DEC=26
2906 06:52:33.011946
2907 06:52:33.015347 ----->DramcWriteLeveling(PI) begin...
2908 06:52:33.015869 ==
2909 06:52:33.018461 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 06:52:33.021621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 06:52:33.022046 ==
2912 06:52:33.025139 Write leveling (Byte 0): 32 => 32
2913 06:52:33.028261 Write leveling (Byte 1): 29 => 29
2914 06:52:33.031514 DramcWriteLeveling(PI) end<-----
2915 06:52:33.031932
2916 06:52:33.032265 ==
2917 06:52:33.035296 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 06:52:33.038282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 06:52:33.038731 ==
2920 06:52:33.041695 [Gating] SW mode calibration
2921 06:52:33.049254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2922 06:52:33.055229 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2923 06:52:33.058993 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2924 06:52:33.062267 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2925 06:52:33.068789 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 06:52:33.072162 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 06:52:33.075123 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 06:52:33.082236 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 06:52:33.085715 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
2930 06:52:33.088618 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
2931 06:52:33.095902 1 0 0 | B1->B0 | 2f2f 2b2b | 0 0 | (0 1) (1 1)
2932 06:52:33.098761 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 06:52:33.102214 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 06:52:33.109080 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 06:52:33.112566 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 06:52:33.115337 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 06:52:33.121974 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2938 06:52:33.126214 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2939 06:52:33.128711 1 1 0 | B1->B0 | 2929 3636 | 1 1 | (0 0) (0 0)
2940 06:52:33.136033 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 06:52:33.139096 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 06:52:33.142153 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 06:52:33.145558 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 06:52:33.152916 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 06:52:33.155892 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 06:52:33.158923 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2947 06:52:33.165748 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2948 06:52:33.169332 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2949 06:52:33.172381 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 06:52:33.179046 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 06:52:33.182174 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 06:52:33.186453 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 06:52:33.193121 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 06:52:33.196443 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 06:52:33.199124 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 06:52:33.202911 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 06:52:33.209777 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 06:52:33.212610 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 06:52:33.216558 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 06:52:33.222889 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 06:52:33.226297 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2962 06:52:33.230058 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2963 06:52:33.236353 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2964 06:52:33.236918 Total UI for P1: 0, mck2ui 16
2965 06:52:33.242852 best dqsien dly found for B0: ( 1, 3, 26)
2966 06:52:33.246437 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 06:52:33.249650 Total UI for P1: 0, mck2ui 16
2968 06:52:33.253022 best dqsien dly found for B1: ( 1, 4, 0)
2969 06:52:33.256095 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2970 06:52:33.260016 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2971 06:52:33.260577
2972 06:52:33.263361 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2973 06:52:33.265949 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2974 06:52:33.269898 [Gating] SW calibration Done
2975 06:52:33.270364 ==
2976 06:52:33.273338 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 06:52:33.276392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 06:52:33.276861 ==
2979 06:52:33.279812 RX Vref Scan: 0
2980 06:52:33.280432
2981 06:52:33.280809 RX Vref 0 -> 0, step: 1
2982 06:52:33.282832
2983 06:52:33.283294 RX Delay -40 -> 252, step: 8
2984 06:52:33.289431 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2985 06:52:33.293101 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2986 06:52:33.296922 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2987 06:52:33.300141 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2988 06:52:33.303043 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2989 06:52:33.307285 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2990 06:52:33.313457 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2991 06:52:33.317078 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2992 06:52:33.320427 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2993 06:52:33.323256 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2994 06:52:33.326995 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2995 06:52:33.333563 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2996 06:52:33.336988 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2997 06:52:33.340566 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2998 06:52:33.343753 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2999 06:52:33.346597 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3000 06:52:33.347159 ==
3001 06:52:33.350977 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 06:52:33.356686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 06:52:33.357241 ==
3004 06:52:33.357612 DQS Delay:
3005 06:52:33.360086 DQS0 = 0, DQS1 = 0
3006 06:52:33.360642 DQM Delay:
3007 06:52:33.361010 DQM0 = 115, DQM1 = 106
3008 06:52:33.363466 DQ Delay:
3009 06:52:33.367192 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3010 06:52:33.370372 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
3011 06:52:33.373498 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3012 06:52:33.377077 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3013 06:52:33.377670
3014 06:52:33.378045
3015 06:52:33.378386 ==
3016 06:52:33.380164 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 06:52:33.383807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 06:52:33.384419 ==
3019 06:52:33.384798
3020 06:52:33.385140
3021 06:52:33.386904 TX Vref Scan disable
3022 06:52:33.390209 == TX Byte 0 ==
3023 06:52:33.394438 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3024 06:52:33.396940 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3025 06:52:33.400891 == TX Byte 1 ==
3026 06:52:33.403782 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3027 06:52:33.407125 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3028 06:52:33.407591 ==
3029 06:52:33.410911 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 06:52:33.414097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 06:52:33.417431 ==
3032 06:52:33.428061 TX Vref=22, minBit 1, minWin=25, winSum=424
3033 06:52:33.430837 TX Vref=24, minBit 0, minWin=26, winSum=426
3034 06:52:33.434729 TX Vref=26, minBit 3, minWin=26, winSum=434
3035 06:52:33.438555 TX Vref=28, minBit 0, minWin=26, winSum=438
3036 06:52:33.441499 TX Vref=30, minBit 7, minWin=26, winSum=439
3037 06:52:33.444175 TX Vref=32, minBit 12, minWin=26, winSum=436
3038 06:52:33.451173 [TxChooseVref] Worse bit 7, Min win 26, Win sum 439, Final Vref 30
3039 06:52:33.451637
3040 06:52:33.455056 Final TX Range 1 Vref 30
3041 06:52:33.455623
3042 06:52:33.455996 ==
3043 06:52:33.457918 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 06:52:33.461258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 06:52:33.461821 ==
3046 06:52:33.462190
3047 06:52:33.462570
3048 06:52:33.464642 TX Vref Scan disable
3049 06:52:33.467674 == TX Byte 0 ==
3050 06:52:33.471673 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3051 06:52:33.475248 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3052 06:52:33.477781 == TX Byte 1 ==
3053 06:52:33.481474 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3054 06:52:33.484921 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3055 06:52:33.485429
3056 06:52:33.488639 [DATLAT]
3057 06:52:33.489179 Freq=1200, CH0 RK1
3058 06:52:33.489569
3059 06:52:33.491926 DATLAT Default: 0xd
3060 06:52:33.492446 0, 0xFFFF, sum = 0
3061 06:52:33.495105 1, 0xFFFF, sum = 0
3062 06:52:33.495629 2, 0xFFFF, sum = 0
3063 06:52:33.498388 3, 0xFFFF, sum = 0
3064 06:52:33.498956 4, 0xFFFF, sum = 0
3065 06:52:33.502077 5, 0xFFFF, sum = 0
3066 06:52:33.502636 6, 0xFFFF, sum = 0
3067 06:52:33.505125 7, 0xFFFF, sum = 0
3068 06:52:33.505655 8, 0xFFFF, sum = 0
3069 06:52:33.508587 9, 0xFFFF, sum = 0
3070 06:52:33.509107 10, 0xFFFF, sum = 0
3071 06:52:33.511772 11, 0xFFFF, sum = 0
3072 06:52:33.512303 12, 0x0, sum = 1
3073 06:52:33.515242 13, 0x0, sum = 2
3074 06:52:33.515721 14, 0x0, sum = 3
3075 06:52:33.518580 15, 0x0, sum = 4
3076 06:52:33.519040 best_step = 13
3077 06:52:33.519379
3078 06:52:33.519693 ==
3079 06:52:33.521913 Dram Type= 6, Freq= 0, CH_0, rank 1
3080 06:52:33.528646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 06:52:33.529070 ==
3082 06:52:33.529409 RX Vref Scan: 0
3083 06:52:33.529724
3084 06:52:33.531958 RX Vref 0 -> 0, step: 1
3085 06:52:33.532378
3086 06:52:33.534992 RX Delay -21 -> 252, step: 4
3087 06:52:33.538533 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3088 06:52:33.541969 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3089 06:52:33.545013 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3090 06:52:33.552061 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3091 06:52:33.554980 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3092 06:52:33.558715 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3093 06:52:33.562068 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3094 06:52:33.565242 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3095 06:52:33.568513 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3096 06:52:33.575229 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3097 06:52:33.578988 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3098 06:52:33.581831 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3099 06:52:33.586070 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3100 06:52:33.588797 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3101 06:52:33.595345 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3102 06:52:33.598656 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3103 06:52:33.599079 ==
3104 06:52:33.601994 Dram Type= 6, Freq= 0, CH_0, rank 1
3105 06:52:33.605769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 06:52:33.606318 ==
3107 06:52:33.608673 DQS Delay:
3108 06:52:33.609091 DQS0 = 0, DQS1 = 0
3109 06:52:33.609423 DQM Delay:
3110 06:52:33.612035 DQM0 = 114, DQM1 = 104
3111 06:52:33.612459 DQ Delay:
3112 06:52:33.615864 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3113 06:52:33.619062 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =122
3114 06:52:33.622020 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3115 06:52:33.625745 DQ12 =110, DQ13 =112, DQ14 =118, DQ15 =112
3116 06:52:33.628933
3117 06:52:33.629351
3118 06:52:33.636067 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3119 06:52:33.638851 CH0 RK1: MR19=403, MR18=3F5
3120 06:52:33.645862 CH0_RK1: MR19=0x403, MR18=0x3F5, DQSOSC=408, MR23=63, INC=39, DEC=26
3121 06:52:33.646387 [RxdqsGatingPostProcess] freq 1200
3122 06:52:33.652864 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3123 06:52:33.656404 best DQS0 dly(2T, 0.5T) = (0, 12)
3124 06:52:33.659573 best DQS1 dly(2T, 0.5T) = (0, 12)
3125 06:52:33.663204 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3126 06:52:33.665981 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3127 06:52:33.669024 best DQS0 dly(2T, 0.5T) = (0, 11)
3128 06:52:33.672504 best DQS1 dly(2T, 0.5T) = (0, 12)
3129 06:52:33.676756 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3130 06:52:33.679631 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3131 06:52:33.680192 Pre-setting of DQS Precalculation
3132 06:52:33.686311 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3133 06:52:33.686933 ==
3134 06:52:33.689550 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 06:52:33.692873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 06:52:33.693340 ==
3137 06:52:33.699027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3138 06:52:33.706473 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3139 06:52:33.713546 [CA 0] Center 38 (9~68) winsize 60
3140 06:52:33.716744 [CA 1] Center 38 (8~68) winsize 61
3141 06:52:33.720489 [CA 2] Center 35 (5~65) winsize 61
3142 06:52:33.723362 [CA 3] Center 34 (4~65) winsize 62
3143 06:52:33.727721 [CA 4] Center 34 (4~65) winsize 62
3144 06:52:33.730464 [CA 5] Center 33 (3~64) winsize 62
3145 06:52:33.731027
3146 06:52:33.733312 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3147 06:52:33.733847
3148 06:52:33.737061 [CATrainingPosCal] consider 1 rank data
3149 06:52:33.740347 u2DelayCellTimex100 = 270/100 ps
3150 06:52:33.743675 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3151 06:52:33.747124 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3152 06:52:33.750478 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3153 06:52:33.753910 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3154 06:52:33.760841 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3155 06:52:33.764379 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3156 06:52:33.764954
3157 06:52:33.766890 CA PerBit enable=1, Macro0, CA PI delay=33
3158 06:52:33.767354
3159 06:52:33.770730 [CBTSetCACLKResult] CA Dly = 33
3160 06:52:33.771190 CS Dly: 5 (0~36)
3161 06:52:33.771558 ==
3162 06:52:33.773885 Dram Type= 6, Freq= 0, CH_1, rank 1
3163 06:52:33.777281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 06:52:33.780906 ==
3165 06:52:33.784080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3166 06:52:33.790310 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3167 06:52:33.799377 [CA 0] Center 37 (7~68) winsize 62
3168 06:52:33.802770 [CA 1] Center 38 (9~68) winsize 60
3169 06:52:33.805482 [CA 2] Center 34 (4~65) winsize 62
3170 06:52:33.809192 [CA 3] Center 34 (4~64) winsize 61
3171 06:52:33.812294 [CA 4] Center 34 (4~65) winsize 62
3172 06:52:33.815958 [CA 5] Center 33 (3~63) winsize 61
3173 06:52:33.816421
3174 06:52:33.819267 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3175 06:52:33.819825
3176 06:52:33.823368 [CATrainingPosCal] consider 2 rank data
3177 06:52:33.825735 u2DelayCellTimex100 = 270/100 ps
3178 06:52:33.828923 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3179 06:52:33.832508 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3180 06:52:33.835351 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3181 06:52:33.842286 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3182 06:52:33.846028 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3183 06:52:33.848985 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3184 06:52:33.849555
3185 06:52:33.852245 CA PerBit enable=1, Macro0, CA PI delay=33
3186 06:52:33.852803
3187 06:52:33.856245 [CBTSetCACLKResult] CA Dly = 33
3188 06:52:33.856798 CS Dly: 7 (0~40)
3189 06:52:33.857164
3190 06:52:33.859160 ----->DramcWriteLeveling(PI) begin...
3191 06:52:33.859627 ==
3192 06:52:33.863064 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 06:52:33.868964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 06:52:33.869515 ==
3195 06:52:33.872933 Write leveling (Byte 0): 26 => 26
3196 06:52:33.876287 Write leveling (Byte 1): 29 => 29
3197 06:52:33.876751 DramcWriteLeveling(PI) end<-----
3198 06:52:33.877196
3199 06:52:33.879337 ==
3200 06:52:33.879862 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 06:52:33.886210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 06:52:33.886728 ==
3203 06:52:33.889719 [Gating] SW mode calibration
3204 06:52:33.896166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3205 06:52:33.899638 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3206 06:52:33.903626 0 15 0 | B1->B0 | 2c2c 2828 | 1 0 | (0 0) (0 0)
3207 06:52:33.909905 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3208 06:52:33.913561 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 06:52:33.916749 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 06:52:33.923357 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 06:52:33.926531 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 06:52:33.930135 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 06:52:33.936903 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3214 06:52:33.939891 1 0 0 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
3215 06:52:33.943580 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 06:52:33.950570 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 06:52:33.953319 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 06:52:33.956402 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 06:52:33.963128 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 06:52:33.967189 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 06:52:33.969832 1 0 28 | B1->B0 | 3030 2626 | 0 0 | (0 0) (0 0)
3222 06:52:33.974073 1 1 0 | B1->B0 | 4040 3131 | 0 0 | (0 0) (0 0)
3223 06:52:33.980088 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 06:52:33.983175 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 06:52:33.986907 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 06:52:33.993488 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 06:52:33.996854 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 06:52:33.999977 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 06:52:34.007350 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3230 06:52:34.010878 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 06:52:34.019597 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 06:52:34.020391 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 06:52:34.023868 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 06:52:34.027243 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 06:52:34.030640 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 06:52:34.037118 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 06:52:34.040938 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 06:52:34.043544 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 06:52:34.050855 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 06:52:34.054113 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 06:52:34.057322 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 06:52:34.063742 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 06:52:34.067391 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 06:52:34.071003 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 06:52:34.077446 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3246 06:52:34.081406 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3247 06:52:34.084210 Total UI for P1: 0, mck2ui 16
3248 06:52:34.087582 best dqsien dly found for B1: ( 1, 3, 30)
3249 06:52:34.091185 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3250 06:52:34.094112 Total UI for P1: 0, mck2ui 16
3251 06:52:34.098170 best dqsien dly found for B0: ( 1, 3, 30)
3252 06:52:34.101083 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3253 06:52:34.104473 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3254 06:52:34.105033
3255 06:52:34.107867 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3256 06:52:34.111432 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3257 06:52:34.114817 [Gating] SW calibration Done
3258 06:52:34.115377 ==
3259 06:52:34.118011 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 06:52:34.121427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 06:52:34.124306 ==
3262 06:52:34.124772 RX Vref Scan: 0
3263 06:52:34.125140
3264 06:52:34.128599 RX Vref 0 -> 0, step: 1
3265 06:52:34.129159
3266 06:52:34.131372 RX Delay -40 -> 252, step: 8
3267 06:52:34.135162 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3268 06:52:34.137913 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3269 06:52:34.141881 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3270 06:52:34.144516 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3271 06:52:34.151380 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3272 06:52:34.154795 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3273 06:52:34.158354 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3274 06:52:34.161504 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3275 06:52:34.164859 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3276 06:52:34.168339 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3277 06:52:34.175121 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3278 06:52:34.178522 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3279 06:52:34.181959 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3280 06:52:34.185092 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3281 06:52:34.188012 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3282 06:52:34.195320 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3283 06:52:34.195876 ==
3284 06:52:34.198835 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 06:52:34.202285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 06:52:34.202820 ==
3287 06:52:34.203370 DQS Delay:
3288 06:52:34.204696 DQS0 = 0, DQS1 = 0
3289 06:52:34.205155 DQM Delay:
3290 06:52:34.208618 DQM0 = 116, DQM1 = 109
3291 06:52:34.209168 DQ Delay:
3292 06:52:34.211380 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3293 06:52:34.215132 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3294 06:52:34.218291 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3295 06:52:34.221966 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3296 06:52:34.222583
3297 06:52:34.222957
3298 06:52:34.223364 ==
3299 06:52:34.224900 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 06:52:34.232157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 06:52:34.232620 ==
3302 06:52:34.232989
3303 06:52:34.233328
3304 06:52:34.233656 TX Vref Scan disable
3305 06:52:34.236832 == TX Byte 0 ==
3306 06:52:34.238663 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3307 06:52:34.242508 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3308 06:52:34.245467 == TX Byte 1 ==
3309 06:52:34.248916 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3310 06:52:34.252360 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3311 06:52:34.255813 ==
3312 06:52:34.259200 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 06:52:34.262620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 06:52:34.263180 ==
3315 06:52:34.273441 TX Vref=22, minBit 3, minWin=24, winSum=414
3316 06:52:34.276569 TX Vref=24, minBit 0, minWin=26, winSum=419
3317 06:52:34.280141 TX Vref=26, minBit 0, minWin=26, winSum=422
3318 06:52:34.283312 TX Vref=28, minBit 1, minWin=26, winSum=426
3319 06:52:34.287320 TX Vref=30, minBit 1, minWin=26, winSum=433
3320 06:52:34.290021 TX Vref=32, minBit 1, minWin=26, winSum=433
3321 06:52:34.297376 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 30
3322 06:52:34.297938
3323 06:52:34.300544 Final TX Range 1 Vref 30
3324 06:52:34.301006
3325 06:52:34.301387 ==
3326 06:52:34.303954 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 06:52:34.307658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 06:52:34.308217 ==
3329 06:52:34.308586
3330 06:52:34.308921
3331 06:52:34.310346 TX Vref Scan disable
3332 06:52:34.313668 == TX Byte 0 ==
3333 06:52:34.317299 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3334 06:52:34.320719 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3335 06:52:34.323812 == TX Byte 1 ==
3336 06:52:34.327290 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3337 06:52:34.330759 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3338 06:52:34.331571
3339 06:52:34.333795 [DATLAT]
3340 06:52:34.334295 Freq=1200, CH1 RK0
3341 06:52:34.334728
3342 06:52:34.337529 DATLAT Default: 0xd
3343 06:52:34.338113 0, 0xFFFF, sum = 0
3344 06:52:34.340737 1, 0xFFFF, sum = 0
3345 06:52:34.341304 2, 0xFFFF, sum = 0
3346 06:52:34.344802 3, 0xFFFF, sum = 0
3347 06:52:34.345368 4, 0xFFFF, sum = 0
3348 06:52:34.347812 5, 0xFFFF, sum = 0
3349 06:52:34.348286 6, 0xFFFF, sum = 0
3350 06:52:34.351124 7, 0xFFFF, sum = 0
3351 06:52:34.351694 8, 0xFFFF, sum = 0
3352 06:52:34.353963 9, 0xFFFF, sum = 0
3353 06:52:34.354556 10, 0xFFFF, sum = 0
3354 06:52:34.357855 11, 0xFFFF, sum = 0
3355 06:52:34.358497 12, 0x0, sum = 1
3356 06:52:34.361017 13, 0x0, sum = 2
3357 06:52:34.361584 14, 0x0, sum = 3
3358 06:52:34.364590 15, 0x0, sum = 4
3359 06:52:34.365163 best_step = 13
3360 06:52:34.365532
3361 06:52:34.365864 ==
3362 06:52:34.367697 Dram Type= 6, Freq= 0, CH_1, rank 0
3363 06:52:34.371009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3364 06:52:34.371544 ==
3365 06:52:34.374189 RX Vref Scan: 1
3366 06:52:34.374708
3367 06:52:34.377590 Set Vref Range= 32 -> 127
3368 06:52:34.378048
3369 06:52:34.378449 RX Vref 32 -> 127, step: 1
3370 06:52:34.378819
3371 06:52:34.380940 RX Delay -21 -> 252, step: 4
3372 06:52:34.381355
3373 06:52:34.384247 Set Vref, RX VrefLevel [Byte0]: 32
3374 06:52:34.388113 [Byte1]: 32
3375 06:52:34.391528
3376 06:52:34.391932 Set Vref, RX VrefLevel [Byte0]: 33
3377 06:52:34.394559 [Byte1]: 33
3378 06:52:34.399571
3379 06:52:34.399960 Set Vref, RX VrefLevel [Byte0]: 34
3380 06:52:34.402461 [Byte1]: 34
3381 06:52:34.407222
3382 06:52:34.407613 Set Vref, RX VrefLevel [Byte0]: 35
3383 06:52:34.410959 [Byte1]: 35
3384 06:52:34.416200
3385 06:52:34.416589 Set Vref, RX VrefLevel [Byte0]: 36
3386 06:52:34.418602 [Byte1]: 36
3387 06:52:34.423015
3388 06:52:34.423401 Set Vref, RX VrefLevel [Byte0]: 37
3389 06:52:34.426665 [Byte1]: 37
3390 06:52:34.431272
3391 06:52:34.431699 Set Vref, RX VrefLevel [Byte0]: 38
3392 06:52:34.434260 [Byte1]: 38
3393 06:52:34.439106
3394 06:52:34.439618 Set Vref, RX VrefLevel [Byte0]: 39
3395 06:52:34.442511 [Byte1]: 39
3396 06:52:34.447249
3397 06:52:34.447804 Set Vref, RX VrefLevel [Byte0]: 40
3398 06:52:34.450787 [Byte1]: 40
3399 06:52:34.454807
3400 06:52:34.455359 Set Vref, RX VrefLevel [Byte0]: 41
3401 06:52:34.458298 [Byte1]: 41
3402 06:52:34.463341
3403 06:52:34.463906 Set Vref, RX VrefLevel [Byte0]: 42
3404 06:52:34.465864 [Byte1]: 42
3405 06:52:34.470501
3406 06:52:34.470960 Set Vref, RX VrefLevel [Byte0]: 43
3407 06:52:34.474149 [Byte1]: 43
3408 06:52:34.479103
3409 06:52:34.479561 Set Vref, RX VrefLevel [Byte0]: 44
3410 06:52:34.481651 [Byte1]: 44
3411 06:52:34.486729
3412 06:52:34.487282 Set Vref, RX VrefLevel [Byte0]: 45
3413 06:52:34.489952 [Byte1]: 45
3414 06:52:34.494775
3415 06:52:34.495323 Set Vref, RX VrefLevel [Byte0]: 46
3416 06:52:34.498195 [Byte1]: 46
3417 06:52:34.502984
3418 06:52:34.503531 Set Vref, RX VrefLevel [Byte0]: 47
3419 06:52:34.506235 [Byte1]: 47
3420 06:52:34.510775
3421 06:52:34.511323 Set Vref, RX VrefLevel [Byte0]: 48
3422 06:52:34.513576 [Byte1]: 48
3423 06:52:34.518364
3424 06:52:34.519001 Set Vref, RX VrefLevel [Byte0]: 49
3425 06:52:34.521417 [Byte1]: 49
3426 06:52:34.526131
3427 06:52:34.526737 Set Vref, RX VrefLevel [Byte0]: 50
3428 06:52:34.530109 [Byte1]: 50
3429 06:52:34.533952
3430 06:52:34.534451 Set Vref, RX VrefLevel [Byte0]: 51
3431 06:52:34.537785 [Byte1]: 51
3432 06:52:34.542171
3433 06:52:34.542803 Set Vref, RX VrefLevel [Byte0]: 52
3434 06:52:34.545306 [Byte1]: 52
3435 06:52:34.549612
3436 06:52:34.550066 Set Vref, RX VrefLevel [Byte0]: 53
3437 06:52:34.554360 [Byte1]: 53
3438 06:52:34.558046
3439 06:52:34.558653 Set Vref, RX VrefLevel [Byte0]: 54
3440 06:52:34.561349 [Byte1]: 54
3441 06:52:34.565950
3442 06:52:34.566556 Set Vref, RX VrefLevel [Byte0]: 55
3443 06:52:34.568776 [Byte1]: 55
3444 06:52:34.573670
3445 06:52:34.574144 Set Vref, RX VrefLevel [Byte0]: 56
3446 06:52:34.577085 [Byte1]: 56
3447 06:52:34.581906
3448 06:52:34.582500 Set Vref, RX VrefLevel [Byte0]: 57
3449 06:52:34.585034 [Byte1]: 57
3450 06:52:34.589343
3451 06:52:34.589802 Set Vref, RX VrefLevel [Byte0]: 58
3452 06:52:34.592615 [Byte1]: 58
3453 06:52:34.597668
3454 06:52:34.598214 Set Vref, RX VrefLevel [Byte0]: 59
3455 06:52:34.600557 [Byte1]: 59
3456 06:52:34.605610
3457 06:52:34.606225 Set Vref, RX VrefLevel [Byte0]: 60
3458 06:52:34.612240 [Byte1]: 60
3459 06:52:34.612798
3460 06:52:34.615445 Set Vref, RX VrefLevel [Byte0]: 61
3461 06:52:34.618617 [Byte1]: 61
3462 06:52:34.619162
3463 06:52:34.621955 Set Vref, RX VrefLevel [Byte0]: 62
3464 06:52:34.625166 [Byte1]: 62
3465 06:52:34.629011
3466 06:52:34.629471 Set Vref, RX VrefLevel [Byte0]: 63
3467 06:52:34.632535 [Byte1]: 63
3468 06:52:34.637357
3469 06:52:34.637851 Set Vref, RX VrefLevel [Byte0]: 64
3470 06:52:34.640086 [Byte1]: 64
3471 06:52:34.644629
3472 06:52:34.645039 Set Vref, RX VrefLevel [Byte0]: 65
3473 06:52:34.648082 [Byte1]: 65
3474 06:52:34.652384
3475 06:52:34.652803 Set Vref, RX VrefLevel [Byte0]: 66
3476 06:52:34.656668 [Byte1]: 66
3477 06:52:34.661261
3478 06:52:34.661769 Set Vref, RX VrefLevel [Byte0]: 67
3479 06:52:34.664025 [Byte1]: 67
3480 06:52:34.668526
3481 06:52:34.668946 Set Vref, RX VrefLevel [Byte0]: 68
3482 06:52:34.671994 [Byte1]: 68
3483 06:52:34.676915
3484 06:52:34.677692 Set Vref, RX VrefLevel [Byte0]: 69
3485 06:52:34.679677 [Byte1]: 69
3486 06:52:34.684769
3487 06:52:34.685282 Set Vref, RX VrefLevel [Byte0]: 70
3488 06:52:34.688154 [Byte1]: 70
3489 06:52:34.692201
3490 06:52:34.692624 Set Vref, RX VrefLevel [Byte0]: 71
3491 06:52:34.695967 [Byte1]: 71
3492 06:52:34.700440
3493 06:52:34.700905 Final RX Vref Byte 0 = 54 to rank0
3494 06:52:34.704012 Final RX Vref Byte 1 = 51 to rank0
3495 06:52:34.707130 Final RX Vref Byte 0 = 54 to rank1
3496 06:52:34.710487 Final RX Vref Byte 1 = 51 to rank1==
3497 06:52:34.713955 Dram Type= 6, Freq= 0, CH_1, rank 0
3498 06:52:34.717145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 06:52:34.720608 ==
3500 06:52:34.721167 DQS Delay:
3501 06:52:34.721535 DQS0 = 0, DQS1 = 0
3502 06:52:34.724061 DQM Delay:
3503 06:52:34.724634 DQM0 = 115, DQM1 = 108
3504 06:52:34.727377 DQ Delay:
3505 06:52:34.730465 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =112
3506 06:52:34.733948 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =112
3507 06:52:34.738085 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3508 06:52:34.741410 DQ12 =116, DQ13 =118, DQ14 =114, DQ15 =112
3509 06:52:34.741973
3510 06:52:34.742343
3511 06:52:34.747388 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3512 06:52:34.750652 CH1 RK0: MR19=303, MR18=FDE2
3513 06:52:34.757763 CH1_RK0: MR19=0x303, MR18=0xFDE2, DQSOSC=411, MR23=63, INC=38, DEC=25
3514 06:52:34.758326
3515 06:52:34.760871 ----->DramcWriteLeveling(PI) begin...
3516 06:52:34.761429 ==
3517 06:52:34.764874 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 06:52:34.767672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 06:52:34.768138 ==
3520 06:52:34.770591 Write leveling (Byte 0): 26 => 26
3521 06:52:34.773993 Write leveling (Byte 1): 28 => 28
3522 06:52:34.777721 DramcWriteLeveling(PI) end<-----
3523 06:52:34.778183
3524 06:52:34.778600 ==
3525 06:52:34.780789 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 06:52:34.784240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 06:52:34.784799 ==
3528 06:52:34.787673 [Gating] SW mode calibration
3529 06:52:34.794627 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3530 06:52:34.801322 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3531 06:52:34.804600 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3532 06:52:34.811366 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3533 06:52:34.814462 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3534 06:52:34.817960 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3535 06:52:34.821888 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3536 06:52:34.827680 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3537 06:52:34.831155 0 15 24 | B1->B0 | 3434 2323 | 1 1 | (1 1) (1 0)
3538 06:52:34.834626 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3539 06:52:34.841436 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3540 06:52:34.844929 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3541 06:52:34.847830 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3542 06:52:34.854626 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3543 06:52:34.857808 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3544 06:52:34.861201 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3545 06:52:34.868354 1 0 24 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
3546 06:52:34.871147 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3547 06:52:34.874263 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 06:52:34.880817 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 06:52:34.884298 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 06:52:34.887717 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 06:52:34.894469 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 06:52:34.897970 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3553 06:52:34.901034 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3554 06:52:34.907870 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3555 06:52:34.911255 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 06:52:34.914505 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 06:52:34.921395 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 06:52:34.925097 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 06:52:34.927727 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 06:52:34.931463 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 06:52:34.937522 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 06:52:34.941264 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 06:52:34.944472 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 06:52:34.951381 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 06:52:34.954486 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 06:52:34.957601 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 06:52:34.964751 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 06:52:34.967581 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 06:52:34.971671 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3570 06:52:34.977765 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3571 06:52:34.978235 Total UI for P1: 0, mck2ui 16
3572 06:52:34.984776 best dqsien dly found for B0: ( 1, 3, 24)
3573 06:52:34.987864 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3574 06:52:34.990874 Total UI for P1: 0, mck2ui 16
3575 06:52:34.994713 best dqsien dly found for B1: ( 1, 3, 28)
3576 06:52:34.997820 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3577 06:52:35.001346 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3578 06:52:35.001813
3579 06:52:35.004555 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3580 06:52:35.008397 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3581 06:52:35.011390 [Gating] SW calibration Done
3582 06:52:35.011855 ==
3583 06:52:35.014873 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 06:52:35.018218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 06:52:35.018838 ==
3586 06:52:35.021812 RX Vref Scan: 0
3587 06:52:35.022370
3588 06:52:35.025207 RX Vref 0 -> 0, step: 1
3589 06:52:35.025768
3590 06:52:35.026138 RX Delay -40 -> 252, step: 8
3591 06:52:35.031530 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3592 06:52:35.035275 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3593 06:52:35.037853 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3594 06:52:35.041642 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3595 06:52:35.044810 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3596 06:52:35.048374 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3597 06:52:35.055361 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3598 06:52:35.058324 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3599 06:52:35.061528 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3600 06:52:35.064772 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3601 06:52:35.068540 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3602 06:52:35.075081 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3603 06:52:35.077621 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3604 06:52:35.081373 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3605 06:52:35.084440 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3606 06:52:35.091205 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3607 06:52:35.091628 ==
3608 06:52:35.094559 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 06:52:35.097727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 06:52:35.098156 ==
3611 06:52:35.098551 DQS Delay:
3612 06:52:35.100974 DQS0 = 0, DQS1 = 0
3613 06:52:35.101398 DQM Delay:
3614 06:52:35.104215 DQM0 = 113, DQM1 = 108
3615 06:52:35.104671 DQ Delay:
3616 06:52:35.107735 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3617 06:52:35.111063 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3618 06:52:35.114293 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =99
3619 06:52:35.117602 DQ12 =111, DQ13 =119, DQ14 =115, DQ15 =119
3620 06:52:35.118051
3621 06:52:35.118381
3622 06:52:35.118742 ==
3623 06:52:35.121209 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 06:52:35.127512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 06:52:35.127960 ==
3626 06:52:35.128341
3627 06:52:35.128676
3628 06:52:35.129057 TX Vref Scan disable
3629 06:52:35.131555 == TX Byte 0 ==
3630 06:52:35.134663 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3631 06:52:35.137721 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3632 06:52:35.141390 == TX Byte 1 ==
3633 06:52:35.144486 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3634 06:52:35.151024 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3635 06:52:35.151478 ==
3636 06:52:35.154501 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 06:52:35.157842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 06:52:35.158287 ==
3639 06:52:35.168825 TX Vref=22, minBit 1, minWin=25, winSum=416
3640 06:52:35.172123 TX Vref=24, minBit 1, minWin=25, winSum=423
3641 06:52:35.175848 TX Vref=26, minBit 0, minWin=26, winSum=428
3642 06:52:35.179008 TX Vref=28, minBit 0, minWin=26, winSum=429
3643 06:52:35.183020 TX Vref=30, minBit 0, minWin=27, winSum=436
3644 06:52:35.185579 TX Vref=32, minBit 1, minWin=26, winSum=431
3645 06:52:35.192394 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 30
3646 06:52:35.193033
3647 06:52:35.195938 Final TX Range 1 Vref 30
3648 06:52:35.196416
3649 06:52:35.196756 ==
3650 06:52:35.199327 Dram Type= 6, Freq= 0, CH_1, rank 1
3651 06:52:35.202344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3652 06:52:35.202841 ==
3653 06:52:35.203231
3654 06:52:35.203580
3655 06:52:35.206053 TX Vref Scan disable
3656 06:52:35.209636 == TX Byte 0 ==
3657 06:52:35.212838 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3658 06:52:35.216014 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3659 06:52:35.219135 == TX Byte 1 ==
3660 06:52:35.222507 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3661 06:52:35.226318 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3662 06:52:35.226917
3663 06:52:35.229099 [DATLAT]
3664 06:52:35.229547 Freq=1200, CH1 RK1
3665 06:52:35.229900
3666 06:52:35.232574 DATLAT Default: 0xd
3667 06:52:35.233111 0, 0xFFFF, sum = 0
3668 06:52:35.236033 1, 0xFFFF, sum = 0
3669 06:52:35.236465 2, 0xFFFF, sum = 0
3670 06:52:35.239667 3, 0xFFFF, sum = 0
3671 06:52:35.240095 4, 0xFFFF, sum = 0
3672 06:52:35.242645 5, 0xFFFF, sum = 0
3673 06:52:35.243078 6, 0xFFFF, sum = 0
3674 06:52:35.245651 7, 0xFFFF, sum = 0
3675 06:52:35.246086 8, 0xFFFF, sum = 0
3676 06:52:35.249054 9, 0xFFFF, sum = 0
3677 06:52:35.249562 10, 0xFFFF, sum = 0
3678 06:52:35.252327 11, 0xFFFF, sum = 0
3679 06:52:35.252786 12, 0x0, sum = 1
3680 06:52:35.255858 13, 0x0, sum = 2
3681 06:52:35.256320 14, 0x0, sum = 3
3682 06:52:35.259638 15, 0x0, sum = 4
3683 06:52:35.260109 best_step = 13
3684 06:52:35.260455
3685 06:52:35.260769 ==
3686 06:52:35.262391 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 06:52:35.269220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 06:52:35.269665 ==
3689 06:52:35.270001 RX Vref Scan: 0
3690 06:52:35.270318
3691 06:52:35.272758 RX Vref 0 -> 0, step: 1
3692 06:52:35.273258
3693 06:52:35.275731 RX Delay -21 -> 252, step: 4
3694 06:52:35.279147 iDelay=195, Bit 0, Center 112 (43 ~ 182) 140
3695 06:52:35.283052 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3696 06:52:35.289478 iDelay=195, Bit 2, Center 104 (39 ~ 170) 132
3697 06:52:35.292599 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3698 06:52:35.296887 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3699 06:52:35.299111 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3700 06:52:35.302581 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3701 06:52:35.309395 iDelay=195, Bit 7, Center 112 (47 ~ 178) 132
3702 06:52:35.312808 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3703 06:52:35.315734 iDelay=195, Bit 9, Center 98 (35 ~ 162) 128
3704 06:52:35.319670 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3705 06:52:35.322908 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3706 06:52:35.329639 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3707 06:52:35.332934 iDelay=195, Bit 13, Center 118 (51 ~ 186) 136
3708 06:52:35.336103 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3709 06:52:35.339598 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3710 06:52:35.340023 ==
3711 06:52:35.343277 Dram Type= 6, Freq= 0, CH_1, rank 1
3712 06:52:35.346191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3713 06:52:35.349104 ==
3714 06:52:35.349601 DQS Delay:
3715 06:52:35.349950 DQS0 = 0, DQS1 = 0
3716 06:52:35.352694 DQM Delay:
3717 06:52:35.353206 DQM0 = 113, DQM1 = 108
3718 06:52:35.356339 DQ Delay:
3719 06:52:35.359336 DQ0 =112, DQ1 =108, DQ2 =104, DQ3 =112
3720 06:52:35.362666 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3721 06:52:35.366097 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =102
3722 06:52:35.369324 DQ12 =114, DQ13 =118, DQ14 =116, DQ15 =116
3723 06:52:35.369783
3724 06:52:35.370119
3725 06:52:35.376079 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3726 06:52:35.378880 CH1 RK1: MR19=304, MR18=FB02
3727 06:52:35.386486 CH1_RK1: MR19=0x304, MR18=0xFB02, DQSOSC=409, MR23=63, INC=39, DEC=26
3728 06:52:35.389939 [RxdqsGatingPostProcess] freq 1200
3729 06:52:35.396338 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3730 06:52:35.398985 best DQS0 dly(2T, 0.5T) = (0, 11)
3731 06:52:35.399451 best DQS1 dly(2T, 0.5T) = (0, 11)
3732 06:52:35.402992 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3733 06:52:35.405522 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3734 06:52:35.409573 best DQS0 dly(2T, 0.5T) = (0, 11)
3735 06:52:35.412569 best DQS1 dly(2T, 0.5T) = (0, 11)
3736 06:52:35.415985 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3737 06:52:35.419349 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3738 06:52:35.422291 Pre-setting of DQS Precalculation
3739 06:52:35.428914 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3740 06:52:35.435951 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3741 06:52:35.442643 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3742 06:52:35.443167
3743 06:52:35.443503
3744 06:52:35.445938 [Calibration Summary] 2400 Mbps
3745 06:52:35.446487 CH 0, Rank 0
3746 06:52:35.449305 SW Impedance : PASS
3747 06:52:35.452364 DUTY Scan : NO K
3748 06:52:35.452886 ZQ Calibration : PASS
3749 06:52:35.455889 Jitter Meter : NO K
3750 06:52:35.459083 CBT Training : PASS
3751 06:52:35.459600 Write leveling : PASS
3752 06:52:35.462244 RX DQS gating : PASS
3753 06:52:35.462714 RX DQ/DQS(RDDQC) : PASS
3754 06:52:35.465674 TX DQ/DQS : PASS
3755 06:52:35.468904 RX DATLAT : PASS
3756 06:52:35.469329 RX DQ/DQS(Engine): PASS
3757 06:52:35.472192 TX OE : NO K
3758 06:52:35.472627 All Pass.
3759 06:52:35.473006
3760 06:52:35.476127 CH 0, Rank 1
3761 06:52:35.476549 SW Impedance : PASS
3762 06:52:35.478972 DUTY Scan : NO K
3763 06:52:35.482609 ZQ Calibration : PASS
3764 06:52:35.483036 Jitter Meter : NO K
3765 06:52:35.485820 CBT Training : PASS
3766 06:52:35.489278 Write leveling : PASS
3767 06:52:35.489792 RX DQS gating : PASS
3768 06:52:35.492903 RX DQ/DQS(RDDQC) : PASS
3769 06:52:35.495699 TX DQ/DQS : PASS
3770 06:52:35.496218 RX DATLAT : PASS
3771 06:52:35.499207 RX DQ/DQS(Engine): PASS
3772 06:52:35.502138 TX OE : NO K
3773 06:52:35.502697 All Pass.
3774 06:52:35.503039
3775 06:52:35.503353 CH 1, Rank 0
3776 06:52:35.505596 SW Impedance : PASS
3777 06:52:35.509112 DUTY Scan : NO K
3778 06:52:35.509633 ZQ Calibration : PASS
3779 06:52:35.512882 Jitter Meter : NO K
3780 06:52:35.513398 CBT Training : PASS
3781 06:52:35.515897 Write leveling : PASS
3782 06:52:35.519027 RX DQS gating : PASS
3783 06:52:35.519542 RX DQ/DQS(RDDQC) : PASS
3784 06:52:35.522737 TX DQ/DQS : PASS
3785 06:52:35.526202 RX DATLAT : PASS
3786 06:52:35.526766 RX DQ/DQS(Engine): PASS
3787 06:52:35.528989 TX OE : NO K
3788 06:52:35.529509 All Pass.
3789 06:52:35.529851
3790 06:52:35.533038 CH 1, Rank 1
3791 06:52:35.533564 SW Impedance : PASS
3792 06:52:35.535745 DUTY Scan : NO K
3793 06:52:35.539319 ZQ Calibration : PASS
3794 06:52:35.539747 Jitter Meter : NO K
3795 06:52:35.542269 CBT Training : PASS
3796 06:52:35.542746 Write leveling : PASS
3797 06:52:35.545574 RX DQS gating : PASS
3798 06:52:35.549137 RX DQ/DQS(RDDQC) : PASS
3799 06:52:35.549672 TX DQ/DQS : PASS
3800 06:52:35.552476 RX DATLAT : PASS
3801 06:52:35.556206 RX DQ/DQS(Engine): PASS
3802 06:52:35.556728 TX OE : NO K
3803 06:52:35.559017 All Pass.
3804 06:52:35.559439
3805 06:52:35.559775 DramC Write-DBI off
3806 06:52:35.562835 PER_BANK_REFRESH: Hybrid Mode
3807 06:52:35.566268 TX_TRACKING: ON
3808 06:52:35.572130 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3809 06:52:35.575660 [FAST_K] Save calibration result to emmc
3810 06:52:35.579055 dramc_set_vcore_voltage set vcore to 650000
3811 06:52:35.582277 Read voltage for 600, 5
3812 06:52:35.582806 Vio18 = 0
3813 06:52:35.585854 Vcore = 650000
3814 06:52:35.586456 Vdram = 0
3815 06:52:35.586849 Vddq = 0
3816 06:52:35.589283 Vmddr = 0
3817 06:52:35.592602 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3818 06:52:35.599378 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3819 06:52:35.599940 MEM_TYPE=3, freq_sel=19
3820 06:52:35.602150 sv_algorithm_assistance_LP4_1600
3821 06:52:35.608875 ============ PULL DRAM RESETB DOWN ============
3822 06:52:35.612624 ========== PULL DRAM RESETB DOWN end =========
3823 06:52:35.615542 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3824 06:52:35.618841 ===================================
3825 06:52:35.622524 LPDDR4 DRAM CONFIGURATION
3826 06:52:35.625855 ===================================
3827 06:52:35.628647 EX_ROW_EN[0] = 0x0
3828 06:52:35.629115 EX_ROW_EN[1] = 0x0
3829 06:52:35.632337 LP4Y_EN = 0x0
3830 06:52:35.632807 WORK_FSP = 0x0
3831 06:52:35.635538 WL = 0x2
3832 06:52:35.636002 RL = 0x2
3833 06:52:35.639051 BL = 0x2
3834 06:52:35.639650 RPST = 0x0
3835 06:52:35.642586 RD_PRE = 0x0
3836 06:52:35.643133 WR_PRE = 0x1
3837 06:52:35.645790 WR_PST = 0x0
3838 06:52:35.646258 DBI_WR = 0x0
3839 06:52:35.648904 DBI_RD = 0x0
3840 06:52:35.649464 OTF = 0x1
3841 06:52:35.651984 ===================================
3842 06:52:35.655418 ===================================
3843 06:52:35.659110 ANA top config
3844 06:52:35.662781 ===================================
3845 06:52:35.663254 DLL_ASYNC_EN = 0
3846 06:52:35.665906 ALL_SLAVE_EN = 1
3847 06:52:35.669028 NEW_RANK_MODE = 1
3848 06:52:35.672403 DLL_IDLE_MODE = 1
3849 06:52:35.672872 LP45_APHY_COMB_EN = 1
3850 06:52:35.675463 TX_ODT_DIS = 1
3851 06:52:35.679048 NEW_8X_MODE = 1
3852 06:52:35.682131 ===================================
3853 06:52:35.686226 ===================================
3854 06:52:35.689656 data_rate = 1200
3855 06:52:35.692176 CKR = 1
3856 06:52:35.695583 DQ_P2S_RATIO = 8
3857 06:52:35.699451 ===================================
3858 06:52:35.699928 CA_P2S_RATIO = 8
3859 06:52:35.702383 DQ_CA_OPEN = 0
3860 06:52:35.705568 DQ_SEMI_OPEN = 0
3861 06:52:35.709744 CA_SEMI_OPEN = 0
3862 06:52:35.712936 CA_FULL_RATE = 0
3863 06:52:35.713494 DQ_CKDIV4_EN = 1
3864 06:52:35.715882 CA_CKDIV4_EN = 1
3865 06:52:35.719731 CA_PREDIV_EN = 0
3866 06:52:35.723084 PH8_DLY = 0
3867 06:52:35.725959 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3868 06:52:35.729646 DQ_AAMCK_DIV = 4
3869 06:52:35.730217 CA_AAMCK_DIV = 4
3870 06:52:35.733274 CA_ADMCK_DIV = 4
3871 06:52:35.735745 DQ_TRACK_CA_EN = 0
3872 06:52:35.739521 CA_PICK = 600
3873 06:52:35.742489 CA_MCKIO = 600
3874 06:52:35.745832 MCKIO_SEMI = 0
3875 06:52:35.746329 PLL_FREQ = 2288
3876 06:52:35.749337 DQ_UI_PI_RATIO = 32
3877 06:52:35.753414 CA_UI_PI_RATIO = 0
3878 06:52:35.756034 ===================================
3879 06:52:35.759889 ===================================
3880 06:52:35.762647 memory_type:LPDDR4
3881 06:52:35.763117 GP_NUM : 10
3882 06:52:35.766446 SRAM_EN : 1
3883 06:52:35.769460 MD32_EN : 0
3884 06:52:35.773306 ===================================
3885 06:52:35.773778 [ANA_INIT] >>>>>>>>>>>>>>
3886 06:52:35.776018 <<<<<< [CONFIGURE PHASE]: ANA_TX
3887 06:52:35.780149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3888 06:52:35.783127 ===================================
3889 06:52:35.786140 data_rate = 1200,PCW = 0X5800
3890 06:52:35.790140 ===================================
3891 06:52:35.793000 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3892 06:52:35.799715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3893 06:52:35.803333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3894 06:52:35.809528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3895 06:52:35.813444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3896 06:52:35.816512 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3897 06:52:35.816939 [ANA_INIT] flow start
3898 06:52:35.819484 [ANA_INIT] PLL >>>>>>>>
3899 06:52:35.823159 [ANA_INIT] PLL <<<<<<<<
3900 06:52:35.823586 [ANA_INIT] MIDPI >>>>>>>>
3901 06:52:35.826789 [ANA_INIT] MIDPI <<<<<<<<
3902 06:52:35.830039 [ANA_INIT] DLL >>>>>>>>
3903 06:52:35.830583 [ANA_INIT] flow end
3904 06:52:35.836188 ============ LP4 DIFF to SE enter ============
3905 06:52:35.839912 ============ LP4 DIFF to SE exit ============
3906 06:52:35.843122 [ANA_INIT] <<<<<<<<<<<<<
3907 06:52:35.845989 [Flow] Enable top DCM control >>>>>
3908 06:52:35.849475 [Flow] Enable top DCM control <<<<<
3909 06:52:35.849991 Enable DLL master slave shuffle
3910 06:52:35.856052 ==============================================================
3911 06:52:35.859871 Gating Mode config
3912 06:52:35.863096 ==============================================================
3913 06:52:35.866279 Config description:
3914 06:52:35.876129 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3915 06:52:35.882675 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3916 06:52:35.886366 SELPH_MODE 0: By rank 1: By Phase
3917 06:52:35.893488 ==============================================================
3918 06:52:35.896169 GAT_TRACK_EN = 1
3919 06:52:35.899396 RX_GATING_MODE = 2
3920 06:52:35.903199 RX_GATING_TRACK_MODE = 2
3921 06:52:35.903625 SELPH_MODE = 1
3922 06:52:35.906249 PICG_EARLY_EN = 1
3923 06:52:35.909957 VALID_LAT_VALUE = 1
3924 06:52:35.917185 ==============================================================
3925 06:52:35.919696 Enter into Gating configuration >>>>
3926 06:52:35.923721 Exit from Gating configuration <<<<
3927 06:52:35.926295 Enter into DVFS_PRE_config >>>>>
3928 06:52:35.936169 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3929 06:52:35.940501 Exit from DVFS_PRE_config <<<<<
3930 06:52:35.943397 Enter into PICG configuration >>>>
3931 06:52:35.946271 Exit from PICG configuration <<<<
3932 06:52:35.950842 [RX_INPUT] configuration >>>>>
3933 06:52:35.953351 [RX_INPUT] configuration <<<<<
3934 06:52:35.956542 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3935 06:52:35.963041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3936 06:52:35.969534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3937 06:52:35.976440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3938 06:52:35.979617 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3939 06:52:35.986331 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3940 06:52:35.989876 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3941 06:52:35.996751 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3942 06:52:35.999611 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3943 06:52:36.003292 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3944 06:52:36.006972 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3945 06:52:36.013411 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3946 06:52:36.016749 ===================================
3947 06:52:36.017276 LPDDR4 DRAM CONFIGURATION
3948 06:52:36.020348 ===================================
3949 06:52:36.023531 EX_ROW_EN[0] = 0x0
3950 06:52:36.026742 EX_ROW_EN[1] = 0x0
3951 06:52:36.027262 LP4Y_EN = 0x0
3952 06:52:36.029985 WORK_FSP = 0x0
3953 06:52:36.030534 WL = 0x2
3954 06:52:36.033485 RL = 0x2
3955 06:52:36.033910 BL = 0x2
3956 06:52:36.036702 RPST = 0x0
3957 06:52:36.037126 RD_PRE = 0x0
3958 06:52:36.040453 WR_PRE = 0x1
3959 06:52:36.041000 WR_PST = 0x0
3960 06:52:36.043570 DBI_WR = 0x0
3961 06:52:36.043992 DBI_RD = 0x0
3962 06:52:36.047022 OTF = 0x1
3963 06:52:36.049905 ===================================
3964 06:52:36.053906 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3965 06:52:36.056695 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3966 06:52:36.060337 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3967 06:52:36.063930 ===================================
3968 06:52:36.066592 LPDDR4 DRAM CONFIGURATION
3969 06:52:36.070136 ===================================
3970 06:52:36.073452 EX_ROW_EN[0] = 0x10
3971 06:52:36.073971 EX_ROW_EN[1] = 0x0
3972 06:52:36.076854 LP4Y_EN = 0x0
3973 06:52:36.077279 WORK_FSP = 0x0
3974 06:52:36.079948 WL = 0x2
3975 06:52:36.080374 RL = 0x2
3976 06:52:36.083125 BL = 0x2
3977 06:52:36.083549 RPST = 0x0
3978 06:52:36.086239 RD_PRE = 0x0
3979 06:52:36.089990 WR_PRE = 0x1
3980 06:52:36.090557 WR_PST = 0x0
3981 06:52:36.093473 DBI_WR = 0x0
3982 06:52:36.093990 DBI_RD = 0x0
3983 06:52:36.096863 OTF = 0x1
3984 06:52:36.099969 ===================================
3985 06:52:36.103379 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3986 06:52:36.108971 nWR fixed to 30
3987 06:52:36.112434 [ModeRegInit_LP4] CH0 RK0
3988 06:52:36.112950 [ModeRegInit_LP4] CH0 RK1
3989 06:52:36.115164 [ModeRegInit_LP4] CH1 RK0
3990 06:52:36.118810 [ModeRegInit_LP4] CH1 RK1
3991 06:52:36.119333 match AC timing 17
3992 06:52:36.125300 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3993 06:52:36.128609 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3994 06:52:36.131911 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3995 06:52:36.138740 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3996 06:52:36.141870 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3997 06:52:36.142458 ==
3998 06:52:36.145710 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 06:52:36.148409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 06:52:36.149002 ==
4001 06:52:36.155679 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4002 06:52:36.161748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4003 06:52:36.165248 [CA 0] Center 36 (6~67) winsize 62
4004 06:52:36.168853 [CA 1] Center 36 (6~66) winsize 61
4005 06:52:36.172086 [CA 2] Center 34 (4~64) winsize 61
4006 06:52:36.175487 [CA 3] Center 34 (4~64) winsize 61
4007 06:52:36.178362 [CA 4] Center 33 (3~64) winsize 62
4008 06:52:36.181902 [CA 5] Center 33 (3~64) winsize 62
4009 06:52:36.182461
4010 06:52:36.184915 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4011 06:52:36.185519
4012 06:52:36.188592 [CATrainingPosCal] consider 1 rank data
4013 06:52:36.191925 u2DelayCellTimex100 = 270/100 ps
4014 06:52:36.195693 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4015 06:52:36.198211 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4016 06:52:36.202282 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4017 06:52:36.205363 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4018 06:52:36.208173 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4019 06:52:36.212001 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4020 06:52:36.212519
4021 06:52:36.218563 CA PerBit enable=1, Macro0, CA PI delay=33
4022 06:52:36.219082
4023 06:52:36.222172 [CBTSetCACLKResult] CA Dly = 33
4024 06:52:36.222640 CS Dly: 5 (0~36)
4025 06:52:36.222985 ==
4026 06:52:36.225848 Dram Type= 6, Freq= 0, CH_0, rank 1
4027 06:52:36.228829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 06:52:36.229353 ==
4029 06:52:36.235494 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4030 06:52:36.242550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4031 06:52:36.245370 [CA 0] Center 35 (5~66) winsize 62
4032 06:52:36.248155 [CA 1] Center 35 (5~66) winsize 62
4033 06:52:36.251725 [CA 2] Center 34 (4~65) winsize 62
4034 06:52:36.255025 [CA 3] Center 34 (4~65) winsize 62
4035 06:52:36.258238 [CA 4] Center 33 (3~64) winsize 62
4036 06:52:36.261965 [CA 5] Center 33 (3~64) winsize 62
4037 06:52:36.262578
4038 06:52:36.265385 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4039 06:52:36.265950
4040 06:52:36.268498 [CATrainingPosCal] consider 2 rank data
4041 06:52:36.272422 u2DelayCellTimex100 = 270/100 ps
4042 06:52:36.275221 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4043 06:52:36.278354 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4044 06:52:36.282498 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4045 06:52:36.284890 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4046 06:52:36.288586 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4047 06:52:36.291887 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4048 06:52:36.294968
4049 06:52:36.298484 CA PerBit enable=1, Macro0, CA PI delay=33
4050 06:52:36.299002
4051 06:52:36.301727 [CBTSetCACLKResult] CA Dly = 33
4052 06:52:36.302252 CS Dly: 5 (0~37)
4053 06:52:36.302657
4054 06:52:36.305080 ----->DramcWriteLeveling(PI) begin...
4055 06:52:36.305614 ==
4056 06:52:36.308256 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 06:52:36.311795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 06:52:36.312217 ==
4059 06:52:36.315212 Write leveling (Byte 0): 31 => 31
4060 06:52:36.318528 Write leveling (Byte 1): 31 => 31
4061 06:52:36.321791 DramcWriteLeveling(PI) end<-----
4062 06:52:36.322316
4063 06:52:36.322718 ==
4064 06:52:36.325477 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 06:52:36.328857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 06:52:36.332227 ==
4067 06:52:36.332725 [Gating] SW mode calibration
4068 06:52:36.342563 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4069 06:52:36.345475 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4070 06:52:36.348186 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4071 06:52:36.355139 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4072 06:52:36.358538 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4073 06:52:36.361654 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4074 06:52:36.368365 0 9 16 | B1->B0 | 3131 2828 | 0 1 | (0 0) (1 0)
4075 06:52:36.372012 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4076 06:52:36.375013 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4077 06:52:36.382048 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4078 06:52:36.385424 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4079 06:52:36.388894 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4080 06:52:36.395038 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4081 06:52:36.398104 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4082 06:52:36.401734 0 10 16 | B1->B0 | 3232 3c3c | 1 0 | (0 0) (0 0)
4083 06:52:36.408668 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4084 06:52:36.411603 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 06:52:36.415043 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 06:52:36.421797 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 06:52:36.425368 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 06:52:36.428361 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 06:52:36.431792 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 06:52:36.438266 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4091 06:52:36.441611 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4092 06:52:36.445740 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 06:52:36.451735 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 06:52:36.455345 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 06:52:36.458660 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 06:52:36.464674 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 06:52:36.468779 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 06:52:36.471728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 06:52:36.478513 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 06:52:36.482146 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 06:52:36.485339 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 06:52:36.491594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 06:52:36.495029 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 06:52:36.498894 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 06:52:36.505267 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 06:52:36.508774 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4107 06:52:36.511867 Total UI for P1: 0, mck2ui 16
4108 06:52:36.515424 best dqsien dly found for B0: ( 0, 13, 14)
4109 06:52:36.519147 Total UI for P1: 0, mck2ui 16
4110 06:52:36.522839 best dqsien dly found for B1: ( 0, 13, 14)
4111 06:52:36.525597 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4112 06:52:36.528187 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4113 06:52:36.528670
4114 06:52:36.531511 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4115 06:52:36.535399 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4116 06:52:36.538474 [Gating] SW calibration Done
4117 06:52:36.539047 ==
4118 06:52:36.541847 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 06:52:36.545591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 06:52:36.546029 ==
4121 06:52:36.548888 RX Vref Scan: 0
4122 06:52:36.549480
4123 06:52:36.551878 RX Vref 0 -> 0, step: 1
4124 06:52:36.552456
4125 06:52:36.552950 RX Delay -230 -> 252, step: 16
4126 06:52:36.558303 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4127 06:52:36.562013 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4128 06:52:36.565044 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4129 06:52:36.568322 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4130 06:52:36.574946 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4131 06:52:36.578528 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4132 06:52:36.582293 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4133 06:52:36.584971 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4134 06:52:36.589068 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4135 06:52:36.595119 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4136 06:52:36.598591 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4137 06:52:36.601765 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4138 06:52:36.605382 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4139 06:52:36.611999 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4140 06:52:36.615281 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4141 06:52:36.618789 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4142 06:52:36.619346 ==
4143 06:52:36.621702 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 06:52:36.625430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 06:52:36.625990 ==
4146 06:52:36.628919 DQS Delay:
4147 06:52:36.629381 DQS0 = 0, DQS1 = 0
4148 06:52:36.631763 DQM Delay:
4149 06:52:36.632318 DQM0 = 40, DQM1 = 33
4150 06:52:36.632688 DQ Delay:
4151 06:52:36.635132 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4152 06:52:36.638197 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4153 06:52:36.642096 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4154 06:52:36.645397 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4155 06:52:36.645960
4156 06:52:36.646332
4157 06:52:36.648874 ==
4158 06:52:36.649431 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 06:52:36.655018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 06:52:36.655578 ==
4161 06:52:36.655948
4162 06:52:36.656290
4163 06:52:36.658483 TX Vref Scan disable
4164 06:52:36.659046 == TX Byte 0 ==
4165 06:52:36.661661 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4166 06:52:36.668204 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4167 06:52:36.668755 == TX Byte 1 ==
4168 06:52:36.671636 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4169 06:52:36.678061 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4170 06:52:36.678530 ==
4171 06:52:36.682002 Dram Type= 6, Freq= 0, CH_0, rank 0
4172 06:52:36.684753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 06:52:36.685178 ==
4174 06:52:36.685514
4175 06:52:36.685821
4176 06:52:36.688167 TX Vref Scan disable
4177 06:52:36.691334 == TX Byte 0 ==
4178 06:52:36.694861 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4179 06:52:36.698234 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4180 06:52:36.702334 == TX Byte 1 ==
4181 06:52:36.705204 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4182 06:52:36.708711 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4183 06:52:36.709227
4184 06:52:36.711439 [DATLAT]
4185 06:52:36.711961 Freq=600, CH0 RK0
4186 06:52:36.712308
4187 06:52:36.715016 DATLAT Default: 0x9
4188 06:52:36.715498 0, 0xFFFF, sum = 0
4189 06:52:36.718533 1, 0xFFFF, sum = 0
4190 06:52:36.719057 2, 0xFFFF, sum = 0
4191 06:52:36.721468 3, 0xFFFF, sum = 0
4192 06:52:36.721893 4, 0xFFFF, sum = 0
4193 06:52:36.725287 5, 0xFFFF, sum = 0
4194 06:52:36.725816 6, 0xFFFF, sum = 0
4195 06:52:36.728294 7, 0xFFFF, sum = 0
4196 06:52:36.728719 8, 0x0, sum = 1
4197 06:52:36.731821 9, 0x0, sum = 2
4198 06:52:36.732353 10, 0x0, sum = 3
4199 06:52:36.734820 11, 0x0, sum = 4
4200 06:52:36.735248 best_step = 9
4201 06:52:36.735582
4202 06:52:36.735892 ==
4203 06:52:36.738511 Dram Type= 6, Freq= 0, CH_0, rank 0
4204 06:52:36.741969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 06:52:36.742541 ==
4206 06:52:36.745236 RX Vref Scan: 1
4207 06:52:36.745655
4208 06:52:36.748217 RX Vref 0 -> 0, step: 1
4209 06:52:36.748637
4210 06:52:36.748968 RX Delay -179 -> 252, step: 8
4211 06:52:36.749281
4212 06:52:36.752196 Set Vref, RX VrefLevel [Byte0]: 52
4213 06:52:36.755268 [Byte1]: 51
4214 06:52:36.760212
4215 06:52:36.760726 Final RX Vref Byte 0 = 52 to rank0
4216 06:52:36.762953 Final RX Vref Byte 1 = 51 to rank0
4217 06:52:36.766297 Final RX Vref Byte 0 = 52 to rank1
4218 06:52:36.770032 Final RX Vref Byte 1 = 51 to rank1==
4219 06:52:36.772616 Dram Type= 6, Freq= 0, CH_0, rank 0
4220 06:52:36.779516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 06:52:36.779936 ==
4222 06:52:36.780270 DQS Delay:
4223 06:52:36.780579 DQS0 = 0, DQS1 = 0
4224 06:52:36.782979 DQM Delay:
4225 06:52:36.783444 DQM0 = 42, DQM1 = 33
4226 06:52:36.786047 DQ Delay:
4227 06:52:36.789735 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4228 06:52:36.793702 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4229 06:52:36.794297 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4230 06:52:36.799566 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4231 06:52:36.800130
4232 06:52:36.800503
4233 06:52:36.806585 [DQSOSCAuto] RK0, (LSB)MR18= 0x401f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4234 06:52:36.809961 CH0 RK0: MR19=808, MR18=401F
4235 06:52:36.816095 CH0_RK0: MR19=0x808, MR18=0x401F, DQSOSC=397, MR23=63, INC=166, DEC=110
4236 06:52:36.816653
4237 06:52:36.819501 ----->DramcWriteLeveling(PI) begin...
4238 06:52:36.820101 ==
4239 06:52:36.822959 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 06:52:36.826260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 06:52:36.826764 ==
4242 06:52:36.829321 Write leveling (Byte 0): 32 => 32
4243 06:52:36.832863 Write leveling (Byte 1): 31 => 31
4244 06:52:36.835794 DramcWriteLeveling(PI) end<-----
4245 06:52:36.836274
4246 06:52:36.836762 ==
4247 06:52:36.839490 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 06:52:36.842853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 06:52:36.843288 ==
4250 06:52:36.846324 [Gating] SW mode calibration
4251 06:52:36.852727 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4252 06:52:36.859139 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4253 06:52:36.862490 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4254 06:52:36.865855 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4255 06:52:36.873013 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4256 06:52:36.876021 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4257 06:52:36.879479 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4258 06:52:36.885889 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 06:52:36.889262 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 06:52:36.892637 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 06:52:36.899621 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4262 06:52:36.902924 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4263 06:52:36.905747 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4264 06:52:36.912648 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4265 06:52:36.916032 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4266 06:52:36.919339 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 06:52:36.926062 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 06:52:36.929898 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 06:52:36.932592 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 06:52:36.936058 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 06:52:36.942661 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 06:52:36.946539 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4273 06:52:36.949484 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4274 06:52:36.956193 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 06:52:36.959410 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 06:52:36.962489 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 06:52:36.969608 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 06:52:36.973002 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 06:52:36.976350 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 06:52:36.982840 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 06:52:36.985643 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 06:52:36.989547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 06:52:36.996149 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 06:52:36.999555 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 06:52:37.002861 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 06:52:37.009229 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 06:52:37.012712 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 06:52:37.015658 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4289 06:52:37.023125 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4290 06:52:37.023704 Total UI for P1: 0, mck2ui 16
4291 06:52:37.026135 best dqsien dly found for B0: ( 0, 13, 12)
4292 06:52:37.032513 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 06:52:37.036043 Total UI for P1: 0, mck2ui 16
4294 06:52:37.039204 best dqsien dly found for B1: ( 0, 13, 16)
4295 06:52:37.042850 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4296 06:52:37.046474 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4297 06:52:37.047036
4298 06:52:37.049185 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4299 06:52:37.052925 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4300 06:52:37.056937 [Gating] SW calibration Done
4301 06:52:37.057460 ==
4302 06:52:37.059341 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 06:52:37.063041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 06:52:37.063601 ==
4305 06:52:37.066100 RX Vref Scan: 0
4306 06:52:37.066597
4307 06:52:37.069527 RX Vref 0 -> 0, step: 1
4308 06:52:37.070096
4309 06:52:37.070525 RX Delay -230 -> 252, step: 16
4310 06:52:37.075783 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4311 06:52:37.079275 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4312 06:52:37.082553 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4313 06:52:37.086245 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4314 06:52:37.092878 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4315 06:52:37.096083 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4316 06:52:37.099627 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4317 06:52:37.103411 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4318 06:52:37.105923 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4319 06:52:37.112703 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4320 06:52:37.115889 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4321 06:52:37.119453 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4322 06:52:37.122738 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4323 06:52:37.129407 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4324 06:52:37.133121 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4325 06:52:37.135867 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4326 06:52:37.136098 ==
4327 06:52:37.139097 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 06:52:37.142480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 06:52:37.142668 ==
4330 06:52:37.145586 DQS Delay:
4331 06:52:37.145740 DQS0 = 0, DQS1 = 0
4332 06:52:37.148936 DQM Delay:
4333 06:52:37.149090 DQM0 = 44, DQM1 = 31
4334 06:52:37.149210 DQ Delay:
4335 06:52:37.152148 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4336 06:52:37.155883 DQ4 =41, DQ5 =25, DQ6 =57, DQ7 =57
4337 06:52:37.159184 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4338 06:52:37.162563 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4339 06:52:37.162666
4340 06:52:37.162747
4341 06:52:37.165778 ==
4342 06:52:37.169180 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 06:52:37.172163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 06:52:37.172257 ==
4345 06:52:37.172330
4346 06:52:37.172397
4347 06:52:37.175440 TX Vref Scan disable
4348 06:52:37.175536 == TX Byte 0 ==
4349 06:52:37.178869 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4350 06:52:37.185573 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4351 06:52:37.185670 == TX Byte 1 ==
4352 06:52:37.189194 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4353 06:52:37.195635 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4354 06:52:37.195731 ==
4355 06:52:37.199551 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 06:52:37.202049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 06:52:37.202172 ==
4358 06:52:37.202277
4359 06:52:37.202377
4360 06:52:37.205526 TX Vref Scan disable
4361 06:52:37.208977 == TX Byte 0 ==
4362 06:52:37.211929 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4363 06:52:37.215511 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4364 06:52:37.220158 == TX Byte 1 ==
4365 06:52:37.222470 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4366 06:52:37.226267 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4367 06:52:37.226739
4368 06:52:37.229653 [DATLAT]
4369 06:52:37.230070 Freq=600, CH0 RK1
4370 06:52:37.230444
4371 06:52:37.232360 DATLAT Default: 0x9
4372 06:52:37.232782 0, 0xFFFF, sum = 0
4373 06:52:37.236233 1, 0xFFFF, sum = 0
4374 06:52:37.236808 2, 0xFFFF, sum = 0
4375 06:52:37.239107 3, 0xFFFF, sum = 0
4376 06:52:37.239592 4, 0xFFFF, sum = 0
4377 06:52:37.242224 5, 0xFFFF, sum = 0
4378 06:52:37.242570 6, 0xFFFF, sum = 0
4379 06:52:37.245296 7, 0xFFFF, sum = 0
4380 06:52:37.245598 8, 0x0, sum = 1
4381 06:52:37.248638 9, 0x0, sum = 2
4382 06:52:37.248903 10, 0x0, sum = 3
4383 06:52:37.252342 11, 0x0, sum = 4
4384 06:52:37.252528 best_step = 9
4385 06:52:37.252672
4386 06:52:37.252804 ==
4387 06:52:37.255510 Dram Type= 6, Freq= 0, CH_0, rank 1
4388 06:52:37.258358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 06:52:37.261940 ==
4390 06:52:37.262071 RX Vref Scan: 0
4391 06:52:37.262175
4392 06:52:37.265636 RX Vref 0 -> 0, step: 1
4393 06:52:37.265839
4394 06:52:37.268525 RX Delay -195 -> 252, step: 8
4395 06:52:37.272106 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4396 06:52:37.275255 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4397 06:52:37.282347 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4398 06:52:37.285554 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4399 06:52:37.288592 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4400 06:52:37.292034 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4401 06:52:37.298610 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4402 06:52:37.301899 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4403 06:52:37.305593 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4404 06:52:37.308564 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4405 06:52:37.312243 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4406 06:52:37.318442 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4407 06:52:37.322044 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4408 06:52:37.325434 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4409 06:52:37.328916 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4410 06:52:37.335424 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4411 06:52:37.335979 ==
4412 06:52:37.338459 Dram Type= 6, Freq= 0, CH_0, rank 1
4413 06:52:37.342239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 06:52:37.342924 ==
4415 06:52:37.343308 DQS Delay:
4416 06:52:37.345269 DQS0 = 0, DQS1 = 0
4417 06:52:37.345730 DQM Delay:
4418 06:52:37.348576 DQM0 = 39, DQM1 = 33
4419 06:52:37.349114 DQ Delay:
4420 06:52:37.352061 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4421 06:52:37.355534 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4422 06:52:37.358828 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4423 06:52:37.362554 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4424 06:52:37.363064
4425 06:52:37.363396
4426 06:52:37.371898 [DQSOSCAuto] RK1, (LSB)MR18= 0x4729, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4427 06:52:37.372447 CH0 RK1: MR19=808, MR18=4729
4428 06:52:37.378888 CH0_RK1: MR19=0x808, MR18=0x4729, DQSOSC=396, MR23=63, INC=167, DEC=111
4429 06:52:37.381847 [RxdqsGatingPostProcess] freq 600
4430 06:52:37.388947 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4431 06:52:37.392325 Pre-setting of DQS Precalculation
4432 06:52:37.395728 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4433 06:52:37.396152 ==
4434 06:52:37.398986 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 06:52:37.401852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 06:52:37.402277 ==
4437 06:52:37.408586 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4438 06:52:37.415004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4439 06:52:37.419109 [CA 0] Center 35 (5~66) winsize 62
4440 06:52:37.422111 [CA 1] Center 35 (5~66) winsize 62
4441 06:52:37.425431 [CA 2] Center 34 (4~64) winsize 61
4442 06:52:37.428558 [CA 3] Center 33 (3~64) winsize 62
4443 06:52:37.431807 [CA 4] Center 34 (3~65) winsize 63
4444 06:52:37.435043 [CA 5] Center 33 (2~64) winsize 63
4445 06:52:37.435555
4446 06:52:37.439005 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4447 06:52:37.439528
4448 06:52:37.441961 [CATrainingPosCal] consider 1 rank data
4449 06:52:37.445974 u2DelayCellTimex100 = 270/100 ps
4450 06:52:37.448606 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4451 06:52:37.452369 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4452 06:52:37.455444 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4453 06:52:37.459130 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4454 06:52:37.462222 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4455 06:52:37.468977 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4456 06:52:37.469493
4457 06:52:37.471875 CA PerBit enable=1, Macro0, CA PI delay=33
4458 06:52:37.472295
4459 06:52:37.475191 [CBTSetCACLKResult] CA Dly = 33
4460 06:52:37.475611 CS Dly: 5 (0~36)
4461 06:52:37.475949 ==
4462 06:52:37.479449 Dram Type= 6, Freq= 0, CH_1, rank 1
4463 06:52:37.482282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 06:52:37.482758 ==
4465 06:52:37.488465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4466 06:52:37.495306 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4467 06:52:37.498120 [CA 0] Center 35 (5~66) winsize 62
4468 06:52:37.501730 [CA 1] Center 35 (5~66) winsize 62
4469 06:52:37.505628 [CA 2] Center 34 (3~65) winsize 63
4470 06:52:37.508404 [CA 3] Center 34 (3~65) winsize 63
4471 06:52:37.511838 [CA 4] Center 34 (3~65) winsize 63
4472 06:52:37.514964 [CA 5] Center 33 (3~64) winsize 62
4473 06:52:37.515152
4474 06:52:37.518716 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4475 06:52:37.518902
4476 06:52:37.522286 [CATrainingPosCal] consider 2 rank data
4477 06:52:37.525086 u2DelayCellTimex100 = 270/100 ps
4478 06:52:37.528881 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4479 06:52:37.531975 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4480 06:52:37.535503 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4481 06:52:37.538895 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4482 06:52:37.542233 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4483 06:52:37.545924 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4484 06:52:37.548453
4485 06:52:37.552104 CA PerBit enable=1, Macro0, CA PI delay=33
4486 06:52:37.552476
4487 06:52:37.555220 [CBTSetCACLKResult] CA Dly = 33
4488 06:52:37.555697 CS Dly: 5 (0~37)
4489 06:52:37.555990
4490 06:52:37.558950 ----->DramcWriteLeveling(PI) begin...
4491 06:52:37.559461 ==
4492 06:52:37.562497 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 06:52:37.565272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 06:52:37.569451 ==
4495 06:52:37.570011 Write leveling (Byte 0): 30 => 30
4496 06:52:37.572272 Write leveling (Byte 1): 30 => 30
4497 06:52:37.575647 DramcWriteLeveling(PI) end<-----
4498 06:52:37.576121
4499 06:52:37.576492 ==
4500 06:52:37.578849 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 06:52:37.585422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 06:52:37.585850 ==
4503 06:52:37.586187 [Gating] SW mode calibration
4504 06:52:37.595250 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4505 06:52:37.598909 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4506 06:52:37.601931 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4507 06:52:37.608782 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4508 06:52:37.612017 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4509 06:52:37.616169 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4510 06:52:37.622142 0 9 16 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
4511 06:52:37.625844 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4512 06:52:37.628796 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4513 06:52:37.635798 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4514 06:52:37.638916 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4515 06:52:37.642562 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4516 06:52:37.649047 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4517 06:52:37.652661 0 10 12 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (1 1)
4518 06:52:37.655296 0 10 16 | B1->B0 | 4040 4040 | 0 0 | (0 0) (0 0)
4519 06:52:37.662114 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 06:52:37.665120 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 06:52:37.669433 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 06:52:37.675597 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 06:52:37.678799 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 06:52:37.682154 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 06:52:37.685808 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 06:52:37.692159 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 06:52:37.695765 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 06:52:37.699678 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 06:52:37.705926 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 06:52:37.709344 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 06:52:37.712691 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 06:52:37.719126 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 06:52:37.722219 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 06:52:37.725719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 06:52:37.732474 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 06:52:37.735433 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 06:52:37.739273 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 06:52:37.745482 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 06:52:37.748886 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 06:52:37.752647 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 06:52:37.758805 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4542 06:52:37.762254 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4543 06:52:37.765447 Total UI for P1: 0, mck2ui 16
4544 06:52:37.768826 best dqsien dly found for B0: ( 0, 13, 12)
4545 06:52:37.772661 Total UI for P1: 0, mck2ui 16
4546 06:52:37.775555 best dqsien dly found for B1: ( 0, 13, 12)
4547 06:52:37.779046 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4548 06:52:37.782738 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4549 06:52:37.783206
4550 06:52:37.785933 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4551 06:52:37.789145 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4552 06:52:37.792873 [Gating] SW calibration Done
4553 06:52:37.793443 ==
4554 06:52:37.795863 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 06:52:37.798950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 06:52:37.799422 ==
4557 06:52:37.801994 RX Vref Scan: 0
4558 06:52:37.802523
4559 06:52:37.805605 RX Vref 0 -> 0, step: 1
4560 06:52:37.806096
4561 06:52:37.806480 RX Delay -230 -> 252, step: 16
4562 06:52:37.811934 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4563 06:52:37.815352 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4564 06:52:37.818873 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4565 06:52:37.822589 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4566 06:52:37.829318 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4567 06:52:37.832555 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4568 06:52:37.835252 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4569 06:52:37.839001 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4570 06:52:37.842342 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4571 06:52:37.848602 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4572 06:52:37.852294 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4573 06:52:37.855787 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4574 06:52:37.858496 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4575 06:52:37.865429 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4576 06:52:37.868729 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4577 06:52:37.872015 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4578 06:52:37.872508 ==
4579 06:52:37.875320 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 06:52:37.878594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 06:52:37.879172 ==
4582 06:52:37.882014 DQS Delay:
4583 06:52:37.882461 DQS0 = 0, DQS1 = 0
4584 06:52:37.885415 DQM Delay:
4585 06:52:37.885845 DQM0 = 44, DQM1 = 36
4586 06:52:37.886182 DQ Delay:
4587 06:52:37.888860 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4588 06:52:37.891867 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4589 06:52:37.895872 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4590 06:52:37.898703 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4591 06:52:37.899122
4592 06:52:37.899453
4593 06:52:37.902186 ==
4594 06:52:37.902732 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 06:52:37.908875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 06:52:37.909303 ==
4597 06:52:37.909637
4598 06:52:37.909944
4599 06:52:37.911848 TX Vref Scan disable
4600 06:52:37.912343 == TX Byte 0 ==
4601 06:52:37.915374 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4602 06:52:37.922702 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4603 06:52:37.923327 == TX Byte 1 ==
4604 06:52:37.925823 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4605 06:52:37.931748 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4606 06:52:37.932171 ==
4607 06:52:37.935294 Dram Type= 6, Freq= 0, CH_1, rank 0
4608 06:52:37.938872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 06:52:37.939319 ==
4610 06:52:37.939653
4611 06:52:37.939995
4612 06:52:37.942090 TX Vref Scan disable
4613 06:52:37.945231 == TX Byte 0 ==
4614 06:52:37.948912 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4615 06:52:37.951809 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4616 06:52:37.955456 == TX Byte 1 ==
4617 06:52:37.958516 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4618 06:52:37.961930 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4619 06:52:37.962357
4620 06:52:37.965310 [DATLAT]
4621 06:52:37.965728 Freq=600, CH1 RK0
4622 06:52:37.966066
4623 06:52:37.968394 DATLAT Default: 0x9
4624 06:52:37.968821 0, 0xFFFF, sum = 0
4625 06:52:37.972020 1, 0xFFFF, sum = 0
4626 06:52:37.972453 2, 0xFFFF, sum = 0
4627 06:52:37.975842 3, 0xFFFF, sum = 0
4628 06:52:37.976343 4, 0xFFFF, sum = 0
4629 06:52:37.978499 5, 0xFFFF, sum = 0
4630 06:52:37.978935 6, 0xFFFF, sum = 0
4631 06:52:37.982331 7, 0xFFFF, sum = 0
4632 06:52:37.982815 8, 0x0, sum = 1
4633 06:52:37.985286 9, 0x0, sum = 2
4634 06:52:37.985718 10, 0x0, sum = 3
4635 06:52:37.989013 11, 0x0, sum = 4
4636 06:52:37.989615 best_step = 9
4637 06:52:37.990018
4638 06:52:37.990329 ==
4639 06:52:37.992049 Dram Type= 6, Freq= 0, CH_1, rank 0
4640 06:52:37.995680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 06:52:37.996104 ==
4642 06:52:37.999115 RX Vref Scan: 1
4643 06:52:37.999535
4644 06:52:38.002354 RX Vref 0 -> 0, step: 1
4645 06:52:38.002818
4646 06:52:38.003155 RX Delay -179 -> 252, step: 8
4647 06:52:38.003468
4648 06:52:38.005541 Set Vref, RX VrefLevel [Byte0]: 54
4649 06:52:38.008502 [Byte1]: 51
4650 06:52:38.013581
4651 06:52:38.014017 Final RX Vref Byte 0 = 54 to rank0
4652 06:52:38.017515 Final RX Vref Byte 1 = 51 to rank0
4653 06:52:38.020369 Final RX Vref Byte 0 = 54 to rank1
4654 06:52:38.023474 Final RX Vref Byte 1 = 51 to rank1==
4655 06:52:38.026665 Dram Type= 6, Freq= 0, CH_1, rank 0
4656 06:52:38.033570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 06:52:38.033995 ==
4658 06:52:38.034329 DQS Delay:
4659 06:52:38.034730 DQS0 = 0, DQS1 = 0
4660 06:52:38.036468 DQM Delay:
4661 06:52:38.036892 DQM0 = 40, DQM1 = 33
4662 06:52:38.040230 DQ Delay:
4663 06:52:38.042972 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4664 06:52:38.043394 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =36
4665 06:52:38.046555 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4666 06:52:38.052990 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4667 06:52:38.053409
4668 06:52:38.053743
4669 06:52:38.060274 [DQSOSCAuto] RK0, (LSB)MR18= 0x480f, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4670 06:52:38.063104 CH1 RK0: MR19=808, MR18=480F
4671 06:52:38.070054 CH1_RK0: MR19=0x808, MR18=0x480F, DQSOSC=396, MR23=63, INC=167, DEC=111
4672 06:52:38.070509
4673 06:52:38.073334 ----->DramcWriteLeveling(PI) begin...
4674 06:52:38.073763 ==
4675 06:52:38.077119 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 06:52:38.080188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 06:52:38.080634 ==
4678 06:52:38.083537 Write leveling (Byte 0): 31 => 31
4679 06:52:38.086561 Write leveling (Byte 1): 31 => 31
4680 06:52:38.090062 DramcWriteLeveling(PI) end<-----
4681 06:52:38.090521
4682 06:52:38.090864 ==
4683 06:52:38.093065 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 06:52:38.096566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 06:52:38.097007 ==
4686 06:52:38.100367 [Gating] SW mode calibration
4687 06:52:38.106382 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4688 06:52:38.113346 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4689 06:52:38.116286 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4690 06:52:38.119792 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4691 06:52:38.126367 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4692 06:52:38.129721 0 9 12 | B1->B0 | 3030 2d2d | 1 1 | (1 1) (0 1)
4693 06:52:38.133126 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4694 06:52:38.140066 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4695 06:52:38.142879 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 06:52:38.146653 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4697 06:52:38.153572 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4698 06:52:38.156399 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4699 06:52:38.160177 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4700 06:52:38.166356 0 10 12 | B1->B0 | 2f2f 3a3a | 1 0 | (0 0) (0 0)
4701 06:52:38.170145 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 06:52:38.173019 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 06:52:38.180191 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 06:52:38.183095 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 06:52:38.186626 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 06:52:38.192941 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 06:52:38.196791 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 06:52:38.199884 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4709 06:52:38.203304 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 06:52:38.210551 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 06:52:38.213240 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 06:52:38.216633 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 06:52:38.223421 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 06:52:38.226437 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 06:52:38.230335 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 06:52:38.237020 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 06:52:38.239727 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 06:52:38.243147 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 06:52:38.250504 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 06:52:38.253522 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 06:52:38.257077 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 06:52:38.264225 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 06:52:38.266656 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 06:52:38.270229 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4725 06:52:38.273405 Total UI for P1: 0, mck2ui 16
4726 06:52:38.276929 best dqsien dly found for B0: ( 0, 13, 10)
4727 06:52:38.279983 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4728 06:52:38.283228 Total UI for P1: 0, mck2ui 16
4729 06:52:38.286919 best dqsien dly found for B1: ( 0, 13, 12)
4730 06:52:38.290374 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4731 06:52:38.297006 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4732 06:52:38.297439
4733 06:52:38.299831 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4734 06:52:38.303137 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4735 06:52:38.307179 [Gating] SW calibration Done
4736 06:52:38.307709 ==
4737 06:52:38.310060 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 06:52:38.313816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 06:52:38.314348 ==
4740 06:52:38.316940 RX Vref Scan: 0
4741 06:52:38.317367
4742 06:52:38.317706 RX Vref 0 -> 0, step: 1
4743 06:52:38.318024
4744 06:52:38.320354 RX Delay -230 -> 252, step: 16
4745 06:52:38.323836 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4746 06:52:38.330037 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4747 06:52:38.333117 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4748 06:52:38.336494 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4749 06:52:38.340323 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4750 06:52:38.343211 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4751 06:52:38.349932 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4752 06:52:38.353366 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4753 06:52:38.356958 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4754 06:52:38.360713 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4755 06:52:38.366714 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4756 06:52:38.370144 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4757 06:52:38.373675 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4758 06:52:38.376948 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4759 06:52:38.379979 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4760 06:52:38.386773 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4761 06:52:38.387311 ==
4762 06:52:38.390521 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 06:52:38.393167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 06:52:38.393596 ==
4765 06:52:38.393936 DQS Delay:
4766 06:52:38.396521 DQS0 = 0, DQS1 = 0
4767 06:52:38.396946 DQM Delay:
4768 06:52:38.400219 DQM0 = 40, DQM1 = 35
4769 06:52:38.400753 DQ Delay:
4770 06:52:38.404266 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4771 06:52:38.406769 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4772 06:52:38.410132 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4773 06:52:38.413420 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4774 06:52:38.413948
4775 06:52:38.414285
4776 06:52:38.414665 ==
4777 06:52:38.416734 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 06:52:38.420372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 06:52:38.423363 ==
4780 06:52:38.423892
4781 06:52:38.424232
4782 06:52:38.424544 TX Vref Scan disable
4783 06:52:38.427109 == TX Byte 0 ==
4784 06:52:38.429704 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4785 06:52:38.433580 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4786 06:52:38.436682 == TX Byte 1 ==
4787 06:52:38.440401 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4788 06:52:38.443203 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4789 06:52:38.446286 ==
4790 06:52:38.446771 Dram Type= 6, Freq= 0, CH_1, rank 1
4791 06:52:38.453567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4792 06:52:38.454098 ==
4793 06:52:38.454488
4794 06:52:38.454815
4795 06:52:38.456581 TX Vref Scan disable
4796 06:52:38.457006 == TX Byte 0 ==
4797 06:52:38.463511 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4798 06:52:38.466880 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4799 06:52:38.467480 == TX Byte 1 ==
4800 06:52:38.473292 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4801 06:52:38.476686 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4802 06:52:38.477139
4803 06:52:38.477664 [DATLAT]
4804 06:52:38.479667 Freq=600, CH1 RK1
4805 06:52:38.480094
4806 06:52:38.480430 DATLAT Default: 0x9
4807 06:52:38.483667 0, 0xFFFF, sum = 0
4808 06:52:38.484099 1, 0xFFFF, sum = 0
4809 06:52:38.486856 2, 0xFFFF, sum = 0
4810 06:52:38.487400 3, 0xFFFF, sum = 0
4811 06:52:38.489938 4, 0xFFFF, sum = 0
4812 06:52:38.490371 5, 0xFFFF, sum = 0
4813 06:52:38.492967 6, 0xFFFF, sum = 0
4814 06:52:38.493398 7, 0xFFFF, sum = 0
4815 06:52:38.496395 8, 0x0, sum = 1
4816 06:52:38.496830 9, 0x0, sum = 2
4817 06:52:38.500089 10, 0x0, sum = 3
4818 06:52:38.500520 11, 0x0, sum = 4
4819 06:52:38.503297 best_step = 9
4820 06:52:38.503723
4821 06:52:38.504059 ==
4822 06:52:38.506208 Dram Type= 6, Freq= 0, CH_1, rank 1
4823 06:52:38.510186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4824 06:52:38.510765 ==
4825 06:52:38.513126 RX Vref Scan: 0
4826 06:52:38.513655
4827 06:52:38.513995 RX Vref 0 -> 0, step: 1
4828 06:52:38.514309
4829 06:52:38.516492 RX Delay -179 -> 252, step: 8
4830 06:52:38.523901 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4831 06:52:38.526857 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4832 06:52:38.529991 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4833 06:52:38.533327 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4834 06:52:38.540334 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4835 06:52:38.543496 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4836 06:52:38.546810 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4837 06:52:38.550540 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4838 06:52:38.553493 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4839 06:52:38.559809 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4840 06:52:38.563381 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4841 06:52:38.566675 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4842 06:52:38.569959 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4843 06:52:38.576757 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4844 06:52:38.579833 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4845 06:52:38.582980 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4846 06:52:38.583408 ==
4847 06:52:38.586548 Dram Type= 6, Freq= 0, CH_1, rank 1
4848 06:52:38.589745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4849 06:52:38.593301 ==
4850 06:52:38.593725 DQS Delay:
4851 06:52:38.594140 DQS0 = 0, DQS1 = 0
4852 06:52:38.597130 DQM Delay:
4853 06:52:38.597656 DQM0 = 38, DQM1 = 33
4854 06:52:38.597995 DQ Delay:
4855 06:52:38.600327 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4856 06:52:38.603204 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4857 06:52:38.606704 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4858 06:52:38.610324 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4859 06:52:38.610897
4860 06:52:38.611242
4861 06:52:38.620265 [DQSOSCAuto] RK1, (LSB)MR18= 0x3744, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4862 06:52:38.623566 CH1 RK1: MR19=808, MR18=3744
4863 06:52:38.630184 CH1_RK1: MR19=0x808, MR18=0x3744, DQSOSC=396, MR23=63, INC=167, DEC=111
4864 06:52:38.630748 [RxdqsGatingPostProcess] freq 600
4865 06:52:38.637228 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4866 06:52:38.639792 Pre-setting of DQS Precalculation
4867 06:52:38.643624 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4868 06:52:38.653693 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4869 06:52:38.660362 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4870 06:52:38.660896
4871 06:52:38.661237
4872 06:52:38.663739 [Calibration Summary] 1200 Mbps
4873 06:52:38.664210 CH 0, Rank 0
4874 06:52:38.667465 SW Impedance : PASS
4875 06:52:38.667991 DUTY Scan : NO K
4876 06:52:38.670674 ZQ Calibration : PASS
4877 06:52:38.673410 Jitter Meter : NO K
4878 06:52:38.673948 CBT Training : PASS
4879 06:52:38.677008 Write leveling : PASS
4880 06:52:38.679852 RX DQS gating : PASS
4881 06:52:38.680274 RX DQ/DQS(RDDQC) : PASS
4882 06:52:38.683502 TX DQ/DQS : PASS
4883 06:52:38.687237 RX DATLAT : PASS
4884 06:52:38.687768 RX DQ/DQS(Engine): PASS
4885 06:52:38.690135 TX OE : NO K
4886 06:52:38.690767 All Pass.
4887 06:52:38.691125
4888 06:52:38.693373 CH 0, Rank 1
4889 06:52:38.693900 SW Impedance : PASS
4890 06:52:38.696969 DUTY Scan : NO K
4891 06:52:38.697396 ZQ Calibration : PASS
4892 06:52:38.700162 Jitter Meter : NO K
4893 06:52:38.703620 CBT Training : PASS
4894 06:52:38.704047 Write leveling : PASS
4895 06:52:38.706858 RX DQS gating : PASS
4896 06:52:38.710438 RX DQ/DQS(RDDQC) : PASS
4897 06:52:38.710977 TX DQ/DQS : PASS
4898 06:52:38.713417 RX DATLAT : PASS
4899 06:52:38.716836 RX DQ/DQS(Engine): PASS
4900 06:52:38.717361 TX OE : NO K
4901 06:52:38.720937 All Pass.
4902 06:52:38.721467
4903 06:52:38.721807 CH 1, Rank 0
4904 06:52:38.723175 SW Impedance : PASS
4905 06:52:38.723611 DUTY Scan : NO K
4906 06:52:38.726775 ZQ Calibration : PASS
4907 06:52:38.729860 Jitter Meter : NO K
4908 06:52:38.730373 CBT Training : PASS
4909 06:52:38.733248 Write leveling : PASS
4910 06:52:38.736980 RX DQS gating : PASS
4911 06:52:38.737541 RX DQ/DQS(RDDQC) : PASS
4912 06:52:38.740444 TX DQ/DQS : PASS
4913 06:52:38.741009 RX DATLAT : PASS
4914 06:52:38.743343 RX DQ/DQS(Engine): PASS
4915 06:52:38.746804 TX OE : NO K
4916 06:52:38.747365 All Pass.
4917 06:52:38.747740
4918 06:52:38.748084 CH 1, Rank 1
4919 06:52:38.750037 SW Impedance : PASS
4920 06:52:38.753770 DUTY Scan : NO K
4921 06:52:38.754233 ZQ Calibration : PASS
4922 06:52:38.756869 Jitter Meter : NO K
4923 06:52:38.760128 CBT Training : PASS
4924 06:52:38.760596 Write leveling : PASS
4925 06:52:38.763319 RX DQS gating : PASS
4926 06:52:38.766608 RX DQ/DQS(RDDQC) : PASS
4927 06:52:38.767072 TX DQ/DQS : PASS
4928 06:52:38.770267 RX DATLAT : PASS
4929 06:52:38.773828 RX DQ/DQS(Engine): PASS
4930 06:52:38.774428 TX OE : NO K
4931 06:52:38.777417 All Pass.
4932 06:52:38.777954
4933 06:52:38.778330 DramC Write-DBI off
4934 06:52:38.780250 PER_BANK_REFRESH: Hybrid Mode
4935 06:52:38.780716 TX_TRACKING: ON
4936 06:52:38.790206 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4937 06:52:38.793090 [FAST_K] Save calibration result to emmc
4938 06:52:38.796711 dramc_set_vcore_voltage set vcore to 662500
4939 06:52:38.799684 Read voltage for 933, 3
4940 06:52:38.800148 Vio18 = 0
4941 06:52:38.802925 Vcore = 662500
4942 06:52:38.803413 Vdram = 0
4943 06:52:38.803792 Vddq = 0
4944 06:52:38.804141 Vmddr = 0
4945 06:52:38.810102 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4946 06:52:38.816502 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4947 06:52:38.817080 MEM_TYPE=3, freq_sel=17
4948 06:52:38.819906 sv_algorithm_assistance_LP4_1600
4949 06:52:38.823171 ============ PULL DRAM RESETB DOWN ============
4950 06:52:38.829971 ========== PULL DRAM RESETB DOWN end =========
4951 06:52:38.833570 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4952 06:52:38.837226 ===================================
4953 06:52:38.839670 LPDDR4 DRAM CONFIGURATION
4954 06:52:38.843282 ===================================
4955 06:52:38.843861 EX_ROW_EN[0] = 0x0
4956 06:52:38.846805 EX_ROW_EN[1] = 0x0
4957 06:52:38.847372 LP4Y_EN = 0x0
4958 06:52:38.850517 WORK_FSP = 0x0
4959 06:52:38.851074 WL = 0x3
4960 06:52:38.853273 RL = 0x3
4961 06:52:38.853744 BL = 0x2
4962 06:52:38.856836 RPST = 0x0
4963 06:52:38.857397 RD_PRE = 0x0
4964 06:52:38.860171 WR_PRE = 0x1
4965 06:52:38.860728 WR_PST = 0x0
4966 06:52:38.862912 DBI_WR = 0x0
4967 06:52:38.866171 DBI_RD = 0x0
4968 06:52:38.866778 OTF = 0x1
4969 06:52:38.869897 ===================================
4970 06:52:38.873170 ===================================
4971 06:52:38.873733 ANA top config
4972 06:52:38.876569 ===================================
4973 06:52:38.879762 DLL_ASYNC_EN = 0
4974 06:52:38.882944 ALL_SLAVE_EN = 1
4975 06:52:38.886242 NEW_RANK_MODE = 1
4976 06:52:38.890004 DLL_IDLE_MODE = 1
4977 06:52:38.890624 LP45_APHY_COMB_EN = 1
4978 06:52:38.893644 TX_ODT_DIS = 1
4979 06:52:38.896254 NEW_8X_MODE = 1
4980 06:52:38.899847 ===================================
4981 06:52:38.903079 ===================================
4982 06:52:38.906573 data_rate = 1866
4983 06:52:38.910144 CKR = 1
4984 06:52:38.910775 DQ_P2S_RATIO = 8
4985 06:52:38.913864 ===================================
4986 06:52:38.916450 CA_P2S_RATIO = 8
4987 06:52:38.919948 DQ_CA_OPEN = 0
4988 06:52:38.923574 DQ_SEMI_OPEN = 0
4989 06:52:38.926506 CA_SEMI_OPEN = 0
4990 06:52:38.930091 CA_FULL_RATE = 0
4991 06:52:38.930709 DQ_CKDIV4_EN = 1
4992 06:52:38.932923 CA_CKDIV4_EN = 1
4993 06:52:38.936660 CA_PREDIV_EN = 0
4994 06:52:38.940034 PH8_DLY = 0
4995 06:52:38.943015 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4996 06:52:38.943591 DQ_AAMCK_DIV = 4
4997 06:52:38.946473 CA_AAMCK_DIV = 4
4998 06:52:38.949848 CA_ADMCK_DIV = 4
4999 06:52:38.954178 DQ_TRACK_CA_EN = 0
5000 06:52:38.956831 CA_PICK = 933
5001 06:52:38.961063 CA_MCKIO = 933
5002 06:52:38.962898 MCKIO_SEMI = 0
5003 06:52:38.963367 PLL_FREQ = 3732
5004 06:52:38.966219 DQ_UI_PI_RATIO = 32
5005 06:52:38.969820 CA_UI_PI_RATIO = 0
5006 06:52:38.973035 ===================================
5007 06:52:38.976203 ===================================
5008 06:52:38.979767 memory_type:LPDDR4
5009 06:52:38.980354 GP_NUM : 10
5010 06:52:38.983432 SRAM_EN : 1
5011 06:52:38.986906 MD32_EN : 0
5012 06:52:38.990087 ===================================
5013 06:52:38.990710 [ANA_INIT] >>>>>>>>>>>>>>
5014 06:52:38.993388 <<<<<< [CONFIGURE PHASE]: ANA_TX
5015 06:52:38.996903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5016 06:52:38.999607 ===================================
5017 06:52:39.002982 data_rate = 1866,PCW = 0X8f00
5018 06:52:39.007467 ===================================
5019 06:52:39.009910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5020 06:52:39.016836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5021 06:52:39.019889 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5022 06:52:39.026584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5023 06:52:39.029790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5024 06:52:39.033183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5025 06:52:39.033764 [ANA_INIT] flow start
5026 06:52:39.036785 [ANA_INIT] PLL >>>>>>>>
5027 06:52:39.039842 [ANA_INIT] PLL <<<<<<<<
5028 06:52:39.040418 [ANA_INIT] MIDPI >>>>>>>>
5029 06:52:39.043310 [ANA_INIT] MIDPI <<<<<<<<
5030 06:52:39.046838 [ANA_INIT] DLL >>>>>>>>
5031 06:52:39.047307 [ANA_INIT] flow end
5032 06:52:39.053416 ============ LP4 DIFF to SE enter ============
5033 06:52:39.056967 ============ LP4 DIFF to SE exit ============
5034 06:52:39.060493 [ANA_INIT] <<<<<<<<<<<<<
5035 06:52:39.064580 [Flow] Enable top DCM control >>>>>
5036 06:52:39.066747 [Flow] Enable top DCM control <<<<<
5037 06:52:39.067333 Enable DLL master slave shuffle
5038 06:52:39.073325 ==============================================================
5039 06:52:39.076539 Gating Mode config
5040 06:52:39.079517 ==============================================================
5041 06:52:39.082911 Config description:
5042 06:52:39.093533 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5043 06:52:39.100135 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5044 06:52:39.103706 SELPH_MODE 0: By rank 1: By Phase
5045 06:52:39.109960 ==============================================================
5046 06:52:39.113061 GAT_TRACK_EN = 1
5047 06:52:39.116852 RX_GATING_MODE = 2
5048 06:52:39.120301 RX_GATING_TRACK_MODE = 2
5049 06:52:39.120764 SELPH_MODE = 1
5050 06:52:39.123364 PICG_EARLY_EN = 1
5051 06:52:39.126355 VALID_LAT_VALUE = 1
5052 06:52:39.133497 ==============================================================
5053 06:52:39.136527 Enter into Gating configuration >>>>
5054 06:52:39.139567 Exit from Gating configuration <<<<
5055 06:52:39.143334 Enter into DVFS_PRE_config >>>>>
5056 06:52:39.153631 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5057 06:52:39.156663 Exit from DVFS_PRE_config <<<<<
5058 06:52:39.160364 Enter into PICG configuration >>>>
5059 06:52:39.163771 Exit from PICG configuration <<<<
5060 06:52:39.167112 [RX_INPUT] configuration >>>>>
5061 06:52:39.170000 [RX_INPUT] configuration <<<<<
5062 06:52:39.173497 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5063 06:52:39.179716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5064 06:52:39.186270 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5065 06:52:39.193351 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5066 06:52:39.196299 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5067 06:52:39.203048 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5068 06:52:39.206476 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5069 06:52:39.213641 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5070 06:52:39.216680 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5071 06:52:39.220035 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5072 06:52:39.223606 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5073 06:52:39.230091 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5074 06:52:39.232996 ===================================
5075 06:52:39.233421 LPDDR4 DRAM CONFIGURATION
5076 06:52:39.236905 ===================================
5077 06:52:39.240168 EX_ROW_EN[0] = 0x0
5078 06:52:39.243303 EX_ROW_EN[1] = 0x0
5079 06:52:39.243818 LP4Y_EN = 0x0
5080 06:52:39.246562 WORK_FSP = 0x0
5081 06:52:39.247079 WL = 0x3
5082 06:52:39.249993 RL = 0x3
5083 06:52:39.250547 BL = 0x2
5084 06:52:39.253393 RPST = 0x0
5085 06:52:39.253814 RD_PRE = 0x0
5086 06:52:39.256744 WR_PRE = 0x1
5087 06:52:39.257257 WR_PST = 0x0
5088 06:52:39.260025 DBI_WR = 0x0
5089 06:52:39.260446 DBI_RD = 0x0
5090 06:52:39.263825 OTF = 0x1
5091 06:52:39.266841 ===================================
5092 06:52:39.270310 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5093 06:52:39.273453 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5094 06:52:39.279838 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5095 06:52:39.283354 ===================================
5096 06:52:39.283830 LPDDR4 DRAM CONFIGURATION
5097 06:52:39.286347 ===================================
5098 06:52:39.289924 EX_ROW_EN[0] = 0x10
5099 06:52:39.290478 EX_ROW_EN[1] = 0x0
5100 06:52:39.293419 LP4Y_EN = 0x0
5101 06:52:39.296709 WORK_FSP = 0x0
5102 06:52:39.297131 WL = 0x3
5103 06:52:39.299893 RL = 0x3
5104 06:52:39.300317 BL = 0x2
5105 06:52:39.303206 RPST = 0x0
5106 06:52:39.303661 RD_PRE = 0x0
5107 06:52:39.306826 WR_PRE = 0x1
5108 06:52:39.307367 WR_PST = 0x0
5109 06:52:39.310357 DBI_WR = 0x0
5110 06:52:39.310897 DBI_RD = 0x0
5111 06:52:39.313317 OTF = 0x1
5112 06:52:39.316593 ===================================
5113 06:52:39.320054 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5114 06:52:39.325706 nWR fixed to 30
5115 06:52:39.328773 [ModeRegInit_LP4] CH0 RK0
5116 06:52:39.329344 [ModeRegInit_LP4] CH0 RK1
5117 06:52:39.332599 [ModeRegInit_LP4] CH1 RK0
5118 06:52:39.335595 [ModeRegInit_LP4] CH1 RK1
5119 06:52:39.336168 match AC timing 9
5120 06:52:39.342388 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5121 06:52:39.346197 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5122 06:52:39.348481 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5123 06:52:39.355752 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5124 06:52:39.359277 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5125 06:52:39.359920 ==
5126 06:52:39.362088 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 06:52:39.365330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 06:52:39.365799 ==
5129 06:52:39.371893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5130 06:52:39.378722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5131 06:52:39.381771 [CA 0] Center 38 (8~69) winsize 62
5132 06:52:39.385362 [CA 1] Center 38 (7~69) winsize 63
5133 06:52:39.389040 [CA 2] Center 35 (5~66) winsize 62
5134 06:52:39.392605 [CA 3] Center 35 (5~66) winsize 62
5135 06:52:39.396131 [CA 4] Center 33 (3~64) winsize 62
5136 06:52:39.398670 [CA 5] Center 33 (3~64) winsize 62
5137 06:52:39.399139
5138 06:52:39.402460 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5139 06:52:39.403056
5140 06:52:39.405501 [CATrainingPosCal] consider 1 rank data
5141 06:52:39.408649 u2DelayCellTimex100 = 270/100 ps
5142 06:52:39.412389 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5143 06:52:39.415628 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5144 06:52:39.419306 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5145 06:52:39.422311 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5146 06:52:39.425444 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5147 06:52:39.428529 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5148 06:52:39.429096
5149 06:52:39.435492 CA PerBit enable=1, Macro0, CA PI delay=33
5150 06:52:39.435964
5151 06:52:39.436337 [CBTSetCACLKResult] CA Dly = 33
5152 06:52:39.439103 CS Dly: 6 (0~37)
5153 06:52:39.439573 ==
5154 06:52:39.442084 Dram Type= 6, Freq= 0, CH_0, rank 1
5155 06:52:39.445271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 06:52:39.445744 ==
5157 06:52:39.451858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5158 06:52:39.459260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5159 06:52:39.462216 [CA 0] Center 38 (8~69) winsize 62
5160 06:52:39.465594 [CA 1] Center 38 (8~69) winsize 62
5161 06:52:39.468908 [CA 2] Center 35 (5~66) winsize 62
5162 06:52:39.472104 [CA 3] Center 35 (4~66) winsize 63
5163 06:52:39.475391 [CA 4] Center 34 (3~65) winsize 63
5164 06:52:39.478984 [CA 5] Center 33 (3~64) winsize 62
5165 06:52:39.479454
5166 06:52:39.482141 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5167 06:52:39.482704
5168 06:52:39.485450 [CATrainingPosCal] consider 2 rank data
5169 06:52:39.488983 u2DelayCellTimex100 = 270/100 ps
5170 06:52:39.492992 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5171 06:52:39.495343 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5172 06:52:39.498513 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5173 06:52:39.502120 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5174 06:52:39.505986 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5175 06:52:39.509744 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5176 06:52:39.510308
5177 06:52:39.515597 CA PerBit enable=1, Macro0, CA PI delay=33
5178 06:52:39.516159
5179 06:52:39.518962 [CBTSetCACLKResult] CA Dly = 33
5180 06:52:39.519431 CS Dly: 7 (0~39)
5181 06:52:39.519808
5182 06:52:39.522195 ----->DramcWriteLeveling(PI) begin...
5183 06:52:39.522809 ==
5184 06:52:39.525886 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 06:52:39.528821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 06:52:39.529296 ==
5187 06:52:39.531725 Write leveling (Byte 0): 31 => 31
5188 06:52:39.535529 Write leveling (Byte 1): 29 => 29
5189 06:52:39.539046 DramcWriteLeveling(PI) end<-----
5190 06:52:39.539605
5191 06:52:39.539981 ==
5192 06:52:39.541854 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 06:52:39.548751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 06:52:39.549296 ==
5195 06:52:39.549672 [Gating] SW mode calibration
5196 06:52:39.558841 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5197 06:52:39.562749 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5198 06:52:39.565991 0 14 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5199 06:52:39.571981 0 14 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5200 06:52:39.575503 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5201 06:52:39.578602 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5202 06:52:39.585318 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5203 06:52:39.589056 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5204 06:52:39.592515 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5205 06:52:39.598766 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5206 06:52:39.602193 0 15 0 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 0)
5207 06:52:39.605437 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
5208 06:52:39.612234 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 06:52:39.615080 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 06:52:39.618518 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5211 06:52:39.625290 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5212 06:52:39.628737 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5213 06:52:39.631721 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5214 06:52:39.639234 1 0 0 | B1->B0 | 2e2e 3f3f | 0 0 | (1 1) (0 0)
5215 06:52:39.641707 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 06:52:39.644743 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 06:52:39.651743 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 06:52:39.654897 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 06:52:39.659067 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 06:52:39.662028 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 06:52:39.668245 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5222 06:52:39.671579 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5223 06:52:39.675254 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 06:52:39.682232 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 06:52:39.685315 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 06:52:39.688722 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 06:52:39.695518 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 06:52:39.698574 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 06:52:39.701956 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 06:52:39.708848 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 06:52:39.711881 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 06:52:39.715391 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 06:52:39.722264 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 06:52:39.725422 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 06:52:39.728062 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 06:52:39.735311 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 06:52:39.738377 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5238 06:52:39.741776 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5239 06:52:39.745291 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5240 06:52:39.751864 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5241 06:52:39.755244 Total UI for P1: 0, mck2ui 16
5242 06:52:39.758370 best dqsien dly found for B0: ( 1, 3, 0)
5243 06:52:39.761937 Total UI for P1: 0, mck2ui 16
5244 06:52:39.766043 best dqsien dly found for B1: ( 1, 3, 0)
5245 06:52:39.768243 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5246 06:52:39.771559 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5247 06:52:39.772033
5248 06:52:39.775271 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5249 06:52:39.778126 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5250 06:52:39.781693 [Gating] SW calibration Done
5251 06:52:39.782352 ==
5252 06:52:39.785049 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 06:52:39.788509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 06:52:39.788982 ==
5255 06:52:39.792502 RX Vref Scan: 0
5256 06:52:39.792971
5257 06:52:39.793341 RX Vref 0 -> 0, step: 1
5258 06:52:39.793690
5259 06:52:39.795266 RX Delay -80 -> 252, step: 8
5260 06:52:39.798053 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5261 06:52:39.804847 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5262 06:52:39.808856 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5263 06:52:39.811808 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5264 06:52:39.815381 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5265 06:52:39.818674 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5266 06:52:39.822048 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5267 06:52:39.827054 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5268 06:52:39.832453 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5269 06:52:39.835495 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5270 06:52:39.838810 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5271 06:52:39.842119 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5272 06:52:39.845692 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5273 06:52:39.851902 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5274 06:52:39.855305 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5275 06:52:39.859109 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5276 06:52:39.859675 ==
5277 06:52:39.862098 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 06:52:39.864952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 06:52:39.865441 ==
5280 06:52:39.868780 DQS Delay:
5281 06:52:39.869340 DQS0 = 0, DQS1 = 0
5282 06:52:39.869717 DQM Delay:
5283 06:52:39.872005 DQM0 = 99, DQM1 = 87
5284 06:52:39.872638 DQ Delay:
5285 06:52:39.875309 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5286 06:52:39.878930 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5287 06:52:39.881496 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5288 06:52:39.884925 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5289 06:52:39.885394
5290 06:52:39.885762
5291 06:52:39.886127 ==
5292 06:52:39.888809 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 06:52:39.895227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 06:52:39.895790 ==
5295 06:52:39.896162
5296 06:52:39.896504
5297 06:52:39.898256 TX Vref Scan disable
5298 06:52:39.898771 == TX Byte 0 ==
5299 06:52:39.901740 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5300 06:52:39.908559 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5301 06:52:39.909220 == TX Byte 1 ==
5302 06:52:39.911848 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5303 06:52:39.918565 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5304 06:52:39.919128 ==
5305 06:52:39.921925 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 06:52:39.925214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 06:52:39.925776 ==
5308 06:52:39.926150
5309 06:52:39.926532
5310 06:52:39.928911 TX Vref Scan disable
5311 06:52:39.932281 == TX Byte 0 ==
5312 06:52:39.935480 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5313 06:52:39.938391 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5314 06:52:39.942712 == TX Byte 1 ==
5315 06:52:39.945161 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5316 06:52:39.948731 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5317 06:52:39.949367
5318 06:52:39.949745 [DATLAT]
5319 06:52:39.951721 Freq=933, CH0 RK0
5320 06:52:39.952286
5321 06:52:39.952668 DATLAT Default: 0xd
5322 06:52:39.955003 0, 0xFFFF, sum = 0
5323 06:52:39.958924 1, 0xFFFF, sum = 0
5324 06:52:39.959488 2, 0xFFFF, sum = 0
5325 06:52:39.961594 3, 0xFFFF, sum = 0
5326 06:52:39.962069 4, 0xFFFF, sum = 0
5327 06:52:39.965350 5, 0xFFFF, sum = 0
5328 06:52:39.965914 6, 0xFFFF, sum = 0
5329 06:52:39.968375 7, 0xFFFF, sum = 0
5330 06:52:39.968943 8, 0xFFFF, sum = 0
5331 06:52:39.972012 9, 0xFFFF, sum = 0
5332 06:52:39.972580 10, 0x0, sum = 1
5333 06:52:39.975797 11, 0x0, sum = 2
5334 06:52:39.976275 12, 0x0, sum = 3
5335 06:52:39.978960 13, 0x0, sum = 4
5336 06:52:39.979435 best_step = 11
5337 06:52:39.979809
5338 06:52:39.980157 ==
5339 06:52:39.982031 Dram Type= 6, Freq= 0, CH_0, rank 0
5340 06:52:39.985049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 06:52:39.985560 ==
5342 06:52:39.988467 RX Vref Scan: 1
5343 06:52:39.989025
5344 06:52:39.991921 RX Vref 0 -> 0, step: 1
5345 06:52:39.992490
5346 06:52:39.992863 RX Delay -61 -> 252, step: 4
5347 06:52:39.993215
5348 06:52:39.995051 Set Vref, RX VrefLevel [Byte0]: 52
5349 06:52:39.998343 [Byte1]: 51
5350 06:52:40.002868
5351 06:52:40.003338 Final RX Vref Byte 0 = 52 to rank0
5352 06:52:40.006258 Final RX Vref Byte 1 = 51 to rank0
5353 06:52:40.010104 Final RX Vref Byte 0 = 52 to rank1
5354 06:52:40.013210 Final RX Vref Byte 1 = 51 to rank1==
5355 06:52:40.016481 Dram Type= 6, Freq= 0, CH_0, rank 0
5356 06:52:40.022845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 06:52:40.023533 ==
5358 06:52:40.023918 DQS Delay:
5359 06:52:40.024265 DQS0 = 0, DQS1 = 0
5360 06:52:40.026360 DQM Delay:
5361 06:52:40.026863 DQM0 = 97, DQM1 = 88
5362 06:52:40.029888 DQ Delay:
5363 06:52:40.032764 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =96
5364 06:52:40.036104 DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =102
5365 06:52:40.036527 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =82
5366 06:52:40.042928 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =98
5367 06:52:40.043354
5368 06:52:40.043685
5369 06:52:40.049363 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5370 06:52:40.053058 CH0 RK0: MR19=504, MR18=11FD
5371 06:52:40.059608 CH0_RK0: MR19=0x504, MR18=0x11FD, DQSOSC=416, MR23=63, INC=62, DEC=41
5372 06:52:40.060124
5373 06:52:40.063372 ----->DramcWriteLeveling(PI) begin...
5374 06:52:40.063890 ==
5375 06:52:40.066137 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 06:52:40.069591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 06:52:40.070073 ==
5378 06:52:40.073295 Write leveling (Byte 0): 31 => 31
5379 06:52:40.076228 Write leveling (Byte 1): 30 => 30
5380 06:52:40.080055 DramcWriteLeveling(PI) end<-----
5381 06:52:40.080477
5382 06:52:40.080810 ==
5383 06:52:40.082745 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 06:52:40.086344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 06:52:40.086823 ==
5386 06:52:40.090046 [Gating] SW mode calibration
5387 06:52:40.096130 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5388 06:52:40.102502 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5389 06:52:40.106178 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
5390 06:52:40.109453 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5391 06:52:40.115969 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 06:52:40.119557 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 06:52:40.122802 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5394 06:52:40.129361 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5395 06:52:40.133060 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5396 06:52:40.136011 0 14 28 | B1->B0 | 3232 2d2d | 0 1 | (0 0) (1 0)
5397 06:52:40.142778 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5398 06:52:40.145988 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5399 06:52:40.149422 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 06:52:40.155705 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 06:52:40.159299 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 06:52:40.163137 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 06:52:40.169657 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 06:52:40.173062 0 15 28 | B1->B0 | 2727 3535 | 1 0 | (0 0) (1 1)
5405 06:52:40.176042 1 0 0 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
5406 06:52:40.182543 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 06:52:40.186882 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 06:52:40.189164 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 06:52:40.193004 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 06:52:40.199530 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 06:52:40.202750 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 06:52:40.206193 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5413 06:52:40.213263 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5414 06:52:40.216040 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5415 06:52:40.219961 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 06:52:40.225927 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 06:52:40.229760 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 06:52:40.233311 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 06:52:40.239304 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 06:52:40.242717 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 06:52:40.246321 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 06:52:40.253159 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 06:52:40.256131 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 06:52:40.259429 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 06:52:40.265910 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 06:52:40.269818 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5427 06:52:40.273184 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5428 06:52:40.279529 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5429 06:52:40.282462 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5430 06:52:40.285927 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5431 06:52:40.289684 Total UI for P1: 0, mck2ui 16
5432 06:52:40.292891 best dqsien dly found for B0: ( 1, 2, 26)
5433 06:52:40.296400 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 06:52:40.299472 Total UI for P1: 0, mck2ui 16
5435 06:52:40.302488 best dqsien dly found for B1: ( 1, 3, 4)
5436 06:52:40.306524 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5437 06:52:40.309326 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5438 06:52:40.310013
5439 06:52:40.316715 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5440 06:52:40.319270 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5441 06:52:40.323317 [Gating] SW calibration Done
5442 06:52:40.323842 ==
5443 06:52:40.326350 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 06:52:40.329519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 06:52:40.330038 ==
5446 06:52:40.330382 RX Vref Scan: 0
5447 06:52:40.330764
5448 06:52:40.333069 RX Vref 0 -> 0, step: 1
5449 06:52:40.333670
5450 06:52:40.336170 RX Delay -80 -> 252, step: 8
5451 06:52:40.339660 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5452 06:52:40.343374 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5453 06:52:40.346941 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5454 06:52:40.353371 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5455 06:52:40.356160 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5456 06:52:40.359488 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5457 06:52:40.362573 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5458 06:52:40.366178 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5459 06:52:40.369482 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5460 06:52:40.376218 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5461 06:52:40.379483 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5462 06:52:40.382812 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5463 06:52:40.385823 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5464 06:52:40.389801 iDelay=208, Bit 13, Center 87 (-8 ~ 183) 192
5465 06:52:40.396308 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5466 06:52:40.399751 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5467 06:52:40.400218 ==
5468 06:52:40.403140 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 06:52:40.405843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 06:52:40.406315 ==
5471 06:52:40.406751 DQS Delay:
5472 06:52:40.409318 DQS0 = 0, DQS1 = 0
5473 06:52:40.409783 DQM Delay:
5474 06:52:40.413129 DQM0 = 96, DQM1 = 86
5475 06:52:40.413688 DQ Delay:
5476 06:52:40.416373 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5477 06:52:40.419642 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5478 06:52:40.423122 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =75
5479 06:52:40.426277 DQ12 =87, DQ13 =87, DQ14 =95, DQ15 =95
5480 06:52:40.426898
5481 06:52:40.427277
5482 06:52:40.427620 ==
5483 06:52:40.429749 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 06:52:40.433199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 06:52:40.436450 ==
5486 06:52:40.436923
5487 06:52:40.437292
5488 06:52:40.437635 TX Vref Scan disable
5489 06:52:40.440081 == TX Byte 0 ==
5490 06:52:40.442757 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5491 06:52:40.446322 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5492 06:52:40.449585 == TX Byte 1 ==
5493 06:52:40.453390 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5494 06:52:40.456684 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5495 06:52:40.457249 ==
5496 06:52:40.459647 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 06:52:40.466263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 06:52:40.466885 ==
5499 06:52:40.467267
5500 06:52:40.467610
5501 06:52:40.467935 TX Vref Scan disable
5502 06:52:40.470452 == TX Byte 0 ==
5503 06:52:40.473684 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5504 06:52:40.480523 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5505 06:52:40.481069 == TX Byte 1 ==
5506 06:52:40.483418 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5507 06:52:40.490770 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5508 06:52:40.491328
5509 06:52:40.491701 [DATLAT]
5510 06:52:40.492045 Freq=933, CH0 RK1
5511 06:52:40.492382
5512 06:52:40.493541 DATLAT Default: 0xb
5513 06:52:40.494009 0, 0xFFFF, sum = 0
5514 06:52:40.497147 1, 0xFFFF, sum = 0
5515 06:52:40.497620 2, 0xFFFF, sum = 0
5516 06:52:40.500184 3, 0xFFFF, sum = 0
5517 06:52:40.500615 4, 0xFFFF, sum = 0
5518 06:52:40.503625 5, 0xFFFF, sum = 0
5519 06:52:40.506792 6, 0xFFFF, sum = 0
5520 06:52:40.507227 7, 0xFFFF, sum = 0
5521 06:52:40.510099 8, 0xFFFF, sum = 0
5522 06:52:40.510606 9, 0xFFFF, sum = 0
5523 06:52:40.513836 10, 0x0, sum = 1
5524 06:52:40.514261 11, 0x0, sum = 2
5525 06:52:40.514654 12, 0x0, sum = 3
5526 06:52:40.516636 13, 0x0, sum = 4
5527 06:52:40.517066 best_step = 11
5528 06:52:40.517403
5529 06:52:40.517716 ==
5530 06:52:40.520569 Dram Type= 6, Freq= 0, CH_0, rank 1
5531 06:52:40.527139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 06:52:40.527645 ==
5533 06:52:40.527982 RX Vref Scan: 0
5534 06:52:40.528294
5535 06:52:40.530545 RX Vref 0 -> 0, step: 1
5536 06:52:40.530968
5537 06:52:40.533950 RX Delay -61 -> 252, step: 4
5538 06:52:40.537433 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5539 06:52:40.540561 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5540 06:52:40.547020 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5541 06:52:40.550633 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5542 06:52:40.554343 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5543 06:52:40.557147 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5544 06:52:40.560616 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5545 06:52:40.563666 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5546 06:52:40.570323 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5547 06:52:40.574028 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5548 06:52:40.577366 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5549 06:52:40.580493 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5550 06:52:40.583642 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5551 06:52:40.590228 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5552 06:52:40.593809 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5553 06:52:40.597309 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5554 06:52:40.597829 ==
5555 06:52:40.600182 Dram Type= 6, Freq= 0, CH_0, rank 1
5556 06:52:40.603445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 06:52:40.603872 ==
5558 06:52:40.606815 DQS Delay:
5559 06:52:40.607238 DQS0 = 0, DQS1 = 0
5560 06:52:40.607572 DQM Delay:
5561 06:52:40.610015 DQM0 = 96, DQM1 = 88
5562 06:52:40.610372 DQ Delay:
5563 06:52:40.613407 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5564 06:52:40.616836 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =102
5565 06:52:40.620431 DQ8 =82, DQ9 =80, DQ10 =88, DQ11 =80
5566 06:52:40.623920 DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =96
5567 06:52:40.624440
5568 06:52:40.624776
5569 06:52:40.633718 [DQSOSCAuto] RK1, (LSB)MR18= 0x1805, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5570 06:52:40.637036 CH0 RK1: MR19=505, MR18=1805
5571 06:52:40.640264 CH0_RK1: MR19=0x505, MR18=0x1805, DQSOSC=414, MR23=63, INC=63, DEC=42
5572 06:52:40.643485 [RxdqsGatingPostProcess] freq 933
5573 06:52:40.650295 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5574 06:52:40.654080 best DQS0 dly(2T, 0.5T) = (0, 11)
5575 06:52:40.656925 best DQS1 dly(2T, 0.5T) = (0, 11)
5576 06:52:40.660537 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5577 06:52:40.663656 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5578 06:52:40.667148 best DQS0 dly(2T, 0.5T) = (0, 10)
5579 06:52:40.670553 best DQS1 dly(2T, 0.5T) = (0, 11)
5580 06:52:40.673903 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5581 06:52:40.677061 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5582 06:52:40.677567 Pre-setting of DQS Precalculation
5583 06:52:40.683286 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5584 06:52:40.683752 ==
5585 06:52:40.687147 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 06:52:40.690143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 06:52:40.690650 ==
5588 06:52:40.696915 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5589 06:52:40.703882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5590 06:52:40.706606 [CA 0] Center 36 (6~67) winsize 62
5591 06:52:40.710429 [CA 1] Center 36 (6~67) winsize 62
5592 06:52:40.714125 [CA 2] Center 34 (4~64) winsize 61
5593 06:52:40.716949 [CA 3] Center 33 (3~64) winsize 62
5594 06:52:40.720576 [CA 4] Center 33 (3~64) winsize 62
5595 06:52:40.723356 [CA 5] Center 33 (3~63) winsize 61
5596 06:52:40.723823
5597 06:52:40.727285 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5598 06:52:40.727837
5599 06:52:40.730167 [CATrainingPosCal] consider 1 rank data
5600 06:52:40.733551 u2DelayCellTimex100 = 270/100 ps
5601 06:52:40.737033 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5602 06:52:40.740710 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5603 06:52:40.743354 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5604 06:52:40.747173 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5605 06:52:40.750130 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5606 06:52:40.753694 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5607 06:52:40.754284
5608 06:52:40.756706 CA PerBit enable=1, Macro0, CA PI delay=33
5609 06:52:40.760113
5610 06:52:40.760685 [CBTSetCACLKResult] CA Dly = 33
5611 06:52:40.763602 CS Dly: 5 (0~36)
5612 06:52:40.764194 ==
5613 06:52:40.767576 Dram Type= 6, Freq= 0, CH_1, rank 1
5614 06:52:40.770392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 06:52:40.771008 ==
5616 06:52:40.777047 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5617 06:52:40.783905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5618 06:52:40.786741 [CA 0] Center 36 (6~67) winsize 62
5619 06:52:40.790420 [CA 1] Center 36 (6~67) winsize 62
5620 06:52:40.793585 [CA 2] Center 33 (3~64) winsize 62
5621 06:52:40.797049 [CA 3] Center 33 (3~64) winsize 62
5622 06:52:40.800179 [CA 4] Center 33 (3~64) winsize 62
5623 06:52:40.800670 [CA 5] Center 33 (2~64) winsize 63
5624 06:52:40.803799
5625 06:52:40.807293 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5626 06:52:40.807752
5627 06:52:40.810196 [CATrainingPosCal] consider 2 rank data
5628 06:52:40.813744 u2DelayCellTimex100 = 270/100 ps
5629 06:52:40.817070 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5630 06:52:40.820934 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5631 06:52:40.823794 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5632 06:52:40.827652 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5633 06:52:40.830324 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5634 06:52:40.833928 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5635 06:52:40.834539
5636 06:52:40.837145 CA PerBit enable=1, Macro0, CA PI delay=33
5637 06:52:40.837706
5638 06:52:40.840496 [CBTSetCACLKResult] CA Dly = 33
5639 06:52:40.843724 CS Dly: 6 (0~38)
5640 06:52:40.844287
5641 06:52:40.847504 ----->DramcWriteLeveling(PI) begin...
5642 06:52:40.848074 ==
5643 06:52:40.850956 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 06:52:40.854071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 06:52:40.854573 ==
5646 06:52:40.857035 Write leveling (Byte 0): 27 => 27
5647 06:52:40.860670 Write leveling (Byte 1): 30 => 30
5648 06:52:40.864131 DramcWriteLeveling(PI) end<-----
5649 06:52:40.864631
5650 06:52:40.865007 ==
5651 06:52:40.867363 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 06:52:40.870492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 06:52:40.870947 ==
5654 06:52:40.873809 [Gating] SW mode calibration
5655 06:52:40.880786 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5656 06:52:40.887222 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5657 06:52:40.890215 0 14 0 | B1->B0 | 3030 3232 | 0 0 | (0 0) (0 0)
5658 06:52:40.894038 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5659 06:52:40.900561 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5660 06:52:40.904033 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5661 06:52:40.907130 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5662 06:52:40.914179 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5663 06:52:40.917128 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5664 06:52:40.920485 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
5665 06:52:40.927392 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5666 06:52:40.930834 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5667 06:52:40.934708 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5668 06:52:40.940667 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5669 06:52:40.944048 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 06:52:40.947384 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5671 06:52:40.953717 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 06:52:40.957216 0 15 28 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
5673 06:52:40.960794 1 0 0 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (0 0)
5674 06:52:40.967103 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 06:52:40.970854 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 06:52:40.974017 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 06:52:40.977669 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 06:52:40.984141 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 06:52:40.987257 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 06:52:40.990546 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5681 06:52:40.997590 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5682 06:52:41.000460 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 06:52:41.004024 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 06:52:41.010311 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 06:52:41.014169 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 06:52:41.017889 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 06:52:41.024061 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 06:52:41.027593 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 06:52:41.031173 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 06:52:41.037409 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 06:52:41.040970 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 06:52:41.044274 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 06:52:41.050847 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 06:52:41.054283 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 06:52:41.057495 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 06:52:41.060796 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5697 06:52:41.067825 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5698 06:52:41.070789 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5699 06:52:41.073870 Total UI for P1: 0, mck2ui 16
5700 06:52:41.077959 best dqsien dly found for B0: ( 1, 2, 30)
5701 06:52:41.080774 Total UI for P1: 0, mck2ui 16
5702 06:52:41.084071 best dqsien dly found for B1: ( 1, 2, 30)
5703 06:52:41.087249 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5704 06:52:41.090386 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5705 06:52:41.090905
5706 06:52:41.094270 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5707 06:52:41.097498 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5708 06:52:41.100684 [Gating] SW calibration Done
5709 06:52:41.101153 ==
5710 06:52:41.103966 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 06:52:41.110522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 06:52:41.111095 ==
5713 06:52:41.111477 RX Vref Scan: 0
5714 06:52:41.111831
5715 06:52:41.114256 RX Vref 0 -> 0, step: 1
5716 06:52:41.114779
5717 06:52:41.117443 RX Delay -80 -> 252, step: 8
5718 06:52:41.120520 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5719 06:52:41.124141 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5720 06:52:41.128221 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5721 06:52:41.130350 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5722 06:52:41.133947 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5723 06:52:41.140578 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5724 06:52:41.144246 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5725 06:52:41.147329 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5726 06:52:41.151118 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5727 06:52:41.154039 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5728 06:52:41.160625 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5729 06:52:41.164201 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5730 06:52:41.166994 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5731 06:52:41.170714 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5732 06:52:41.174067 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5733 06:52:41.177392 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5734 06:52:41.177965 ==
5735 06:52:41.180387 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 06:52:41.187608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 06:52:41.188081 ==
5738 06:52:41.188453 DQS Delay:
5739 06:52:41.190524 DQS0 = 0, DQS1 = 0
5740 06:52:41.190994 DQM Delay:
5741 06:52:41.194177 DQM0 = 95, DQM1 = 88
5742 06:52:41.194799 DQ Delay:
5743 06:52:41.197830 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =95
5744 06:52:41.200496 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5745 06:52:41.203877 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5746 06:52:41.207642 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5747 06:52:41.208112
5748 06:52:41.208486
5749 06:52:41.208831 ==
5750 06:52:41.210460 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 06:52:41.213692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 06:52:41.214155 ==
5753 06:52:41.214568
5754 06:52:41.214914
5755 06:52:41.217051 TX Vref Scan disable
5756 06:52:41.221079 == TX Byte 0 ==
5757 06:52:41.223893 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5758 06:52:41.227273 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5759 06:52:41.230895 == TX Byte 1 ==
5760 06:52:41.234161 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5761 06:52:41.237263 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5762 06:52:41.237890 ==
5763 06:52:41.240668 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 06:52:41.244711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 06:52:41.245277 ==
5766 06:52:41.246978
5767 06:52:41.247436
5768 06:52:41.247803 TX Vref Scan disable
5769 06:52:41.250602 == TX Byte 0 ==
5770 06:52:41.254618 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5771 06:52:41.257794 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5772 06:52:41.260589 == TX Byte 1 ==
5773 06:52:41.263836 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5774 06:52:41.270059 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5775 06:52:41.270677
5776 06:52:41.271087 [DATLAT]
5777 06:52:41.271471 Freq=933, CH1 RK0
5778 06:52:41.271811
5779 06:52:41.273382 DATLAT Default: 0xd
5780 06:52:41.273841 0, 0xFFFF, sum = 0
5781 06:52:41.277316 1, 0xFFFF, sum = 0
5782 06:52:41.277798 2, 0xFFFF, sum = 0
5783 06:52:41.280342 3, 0xFFFF, sum = 0
5784 06:52:41.283692 4, 0xFFFF, sum = 0
5785 06:52:41.284116 5, 0xFFFF, sum = 0
5786 06:52:41.286689 6, 0xFFFF, sum = 0
5787 06:52:41.287146 7, 0xFFFF, sum = 0
5788 06:52:41.290043 8, 0xFFFF, sum = 0
5789 06:52:41.290637 9, 0xFFFF, sum = 0
5790 06:52:41.293308 10, 0x0, sum = 1
5791 06:52:41.293731 11, 0x0, sum = 2
5792 06:52:41.296901 12, 0x0, sum = 3
5793 06:52:41.297323 13, 0x0, sum = 4
5794 06:52:41.297660 best_step = 11
5795 06:52:41.297967
5796 06:52:41.300047 ==
5797 06:52:41.303254 Dram Type= 6, Freq= 0, CH_1, rank 0
5798 06:52:41.306971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 06:52:41.307390 ==
5800 06:52:41.307735 RX Vref Scan: 1
5801 06:52:41.308063
5802 06:52:41.310708 RX Vref 0 -> 0, step: 1
5803 06:52:41.311144
5804 06:52:41.313688 RX Delay -69 -> 252, step: 4
5805 06:52:41.314116
5806 06:52:41.316771 Set Vref, RX VrefLevel [Byte0]: 54
5807 06:52:41.319823 [Byte1]: 51
5808 06:52:41.320252
5809 06:52:41.323617 Final RX Vref Byte 0 = 54 to rank0
5810 06:52:41.326339 Final RX Vref Byte 1 = 51 to rank0
5811 06:52:41.329624 Final RX Vref Byte 0 = 54 to rank1
5812 06:52:41.333752 Final RX Vref Byte 1 = 51 to rank1==
5813 06:52:41.336434 Dram Type= 6, Freq= 0, CH_1, rank 0
5814 06:52:41.339718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 06:52:41.343230 ==
5816 06:52:41.343660 DQS Delay:
5817 06:52:41.344094 DQS0 = 0, DQS1 = 0
5818 06:52:41.346386 DQM Delay:
5819 06:52:41.346863 DQM0 = 98, DQM1 = 89
5820 06:52:41.349979 DQ Delay:
5821 06:52:41.350442 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =96
5822 06:52:41.353107 DQ4 =98, DQ5 =108, DQ6 =108, DQ7 =92
5823 06:52:41.356539 DQ8 =78, DQ9 =76, DQ10 =92, DQ11 =84
5824 06:52:41.362970 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =92
5825 06:52:41.363395
5826 06:52:41.363825
5827 06:52:41.369862 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5828 06:52:41.372742 CH1 RK0: MR19=504, MR18=17F3
5829 06:52:41.379257 CH1_RK0: MR19=0x504, MR18=0x17F3, DQSOSC=414, MR23=63, INC=63, DEC=42
5830 06:52:41.379366
5831 06:52:41.383098 ----->DramcWriteLeveling(PI) begin...
5832 06:52:41.383183 ==
5833 06:52:41.386358 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 06:52:41.389002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 06:52:41.389088 ==
5836 06:52:41.392881 Write leveling (Byte 0): 30 => 30
5837 06:52:41.395904 Write leveling (Byte 1): 29 => 29
5838 06:52:41.398894 DramcWriteLeveling(PI) end<-----
5839 06:52:41.398976
5840 06:52:41.399041 ==
5841 06:52:41.402371 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 06:52:41.406569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 06:52:41.407042 ==
5844 06:52:41.409973 [Gating] SW mode calibration
5845 06:52:41.416333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5846 06:52:41.422701 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5847 06:52:41.426355 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5848 06:52:41.433564 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5849 06:52:41.435841 0 14 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5850 06:52:41.439461 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5851 06:52:41.442881 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5852 06:52:41.449777 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5853 06:52:41.452769 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5854 06:52:41.456222 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5855 06:52:41.463032 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 06:52:41.466353 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5857 06:52:41.469705 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5858 06:52:41.476128 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5859 06:52:41.480084 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5860 06:52:41.482892 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5861 06:52:41.489071 0 15 24 | B1->B0 | 2929 3434 | 0 1 | (0 0) (0 0)
5862 06:52:41.492938 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5863 06:52:41.496009 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 06:52:41.502735 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 06:52:41.506495 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 06:52:41.509168 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 06:52:41.516222 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 06:52:41.519216 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 06:52:41.522677 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5870 06:52:41.529080 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 06:52:41.533074 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 06:52:41.536436 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 06:52:41.542819 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 06:52:41.546362 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 06:52:41.549735 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 06:52:41.552784 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 06:52:41.559530 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 06:52:41.563095 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 06:52:41.566668 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 06:52:41.573170 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 06:52:41.576502 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 06:52:41.579337 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 06:52:41.586140 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 06:52:41.591352 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5885 06:52:41.592656 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5886 06:52:41.596189 Total UI for P1: 0, mck2ui 16
5887 06:52:41.599279 best dqsien dly found for B0: ( 1, 2, 20)
5888 06:52:41.606012 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5889 06:52:41.606562 Total UI for P1: 0, mck2ui 16
5890 06:52:41.609286 best dqsien dly found for B1: ( 1, 2, 24)
5891 06:52:41.616095 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5892 06:52:41.619423 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5893 06:52:41.619852
5894 06:52:41.623265 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5895 06:52:41.626369 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5896 06:52:41.629707 [Gating] SW calibration Done
5897 06:52:41.630139 ==
5898 06:52:41.632759 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 06:52:41.636535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 06:52:41.637096 ==
5901 06:52:41.639540 RX Vref Scan: 0
5902 06:52:41.639955
5903 06:52:41.640284 RX Vref 0 -> 0, step: 1
5904 06:52:41.640591
5905 06:52:41.643405 RX Delay -80 -> 252, step: 8
5906 06:52:41.646800 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5907 06:52:41.649704 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5908 06:52:41.655923 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5909 06:52:41.659435 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5910 06:52:41.663081 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5911 06:52:41.665930 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5912 06:52:41.669317 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5913 06:52:41.673397 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5914 06:52:41.679866 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5915 06:52:41.683058 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5916 06:52:41.686142 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5917 06:52:41.689578 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5918 06:52:41.692572 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5919 06:52:41.699936 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5920 06:52:41.702502 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5921 06:52:41.706322 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5922 06:52:41.706906 ==
5923 06:52:41.709362 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 06:52:41.712865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 06:52:41.713300 ==
5926 06:52:41.716574 DQS Delay:
5927 06:52:41.717113 DQS0 = 0, DQS1 = 0
5928 06:52:41.717555 DQM Delay:
5929 06:52:41.720023 DQM0 = 93, DQM1 = 88
5930 06:52:41.720450 DQ Delay:
5931 06:52:41.722684 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =95
5932 06:52:41.726591 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5933 06:52:41.730287 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5934 06:52:41.733081 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5935 06:52:41.733617
5936 06:52:41.734057
5937 06:52:41.734590 ==
5938 06:52:41.736322 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 06:52:41.743137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 06:52:41.743573 ==
5941 06:52:41.744007
5942 06:52:41.744414
5943 06:52:41.744813 TX Vref Scan disable
5944 06:52:41.745985 == TX Byte 0 ==
5945 06:52:41.749525 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5946 06:52:41.756016 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5947 06:52:41.756530 == TX Byte 1 ==
5948 06:52:41.759290 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5949 06:52:41.766022 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5950 06:52:41.766584 ==
5951 06:52:41.769648 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 06:52:41.773142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 06:52:41.773664 ==
5954 06:52:41.774108
5955 06:52:41.774620
5956 06:52:41.776394 TX Vref Scan disable
5957 06:52:41.776924 == TX Byte 0 ==
5958 06:52:41.782473 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5959 06:52:41.785800 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5960 06:52:41.786233 == TX Byte 1 ==
5961 06:52:41.792771 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5962 06:52:41.796657 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5963 06:52:41.797086
5964 06:52:41.797422 [DATLAT]
5965 06:52:41.799893 Freq=933, CH1 RK1
5966 06:52:41.800427
5967 06:52:41.800772 DATLAT Default: 0xb
5968 06:52:41.802568 0, 0xFFFF, sum = 0
5969 06:52:41.803012 1, 0xFFFF, sum = 0
5970 06:52:41.806111 2, 0xFFFF, sum = 0
5971 06:52:41.806786 3, 0xFFFF, sum = 0
5972 06:52:41.809427 4, 0xFFFF, sum = 0
5973 06:52:41.809949 5, 0xFFFF, sum = 0
5974 06:52:41.812615 6, 0xFFFF, sum = 0
5975 06:52:41.813189 7, 0xFFFF, sum = 0
5976 06:52:41.815825 8, 0xFFFF, sum = 0
5977 06:52:41.819148 9, 0xFFFF, sum = 0
5978 06:52:41.819622 10, 0x0, sum = 1
5979 06:52:41.820001 11, 0x0, sum = 2
5980 06:52:41.822847 12, 0x0, sum = 3
5981 06:52:41.823321 13, 0x0, sum = 4
5982 06:52:41.826301 best_step = 11
5983 06:52:41.826741
5984 06:52:41.827096 ==
5985 06:52:41.829408 Dram Type= 6, Freq= 0, CH_1, rank 1
5986 06:52:41.833027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5987 06:52:41.833557 ==
5988 06:52:41.835767 RX Vref Scan: 0
5989 06:52:41.836239
5990 06:52:41.836581 RX Vref 0 -> 0, step: 1
5991 06:52:41.836899
5992 06:52:41.839069 RX Delay -61 -> 252, step: 4
5993 06:52:41.846846 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5994 06:52:41.850235 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5995 06:52:41.853032 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5996 06:52:41.856575 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5997 06:52:41.861004 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5998 06:52:41.863248 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5999 06:52:41.870088 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
6000 06:52:41.873174 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
6001 06:52:41.876423 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
6002 06:52:41.880386 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
6003 06:52:41.882888 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
6004 06:52:41.889512 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
6005 06:52:41.892954 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
6006 06:52:41.896179 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
6007 06:52:41.899833 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
6008 06:52:41.903141 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
6009 06:52:41.903572 ==
6010 06:52:41.906093 Dram Type= 6, Freq= 0, CH_1, rank 1
6011 06:52:41.913153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6012 06:52:41.913680 ==
6013 06:52:41.914129 DQS Delay:
6014 06:52:41.915975 DQS0 = 0, DQS1 = 0
6015 06:52:41.916596 DQM Delay:
6016 06:52:41.917032 DQM0 = 94, DQM1 = 90
6017 06:52:41.919806 DQ Delay:
6018 06:52:41.923059 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
6019 06:52:41.926371 DQ4 =98, DQ5 =106, DQ6 =102, DQ7 =90
6020 06:52:41.929887 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
6021 06:52:41.933086 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
6022 06:52:41.933614
6023 06:52:41.934056
6024 06:52:41.939705 [DQSOSCAuto] RK1, (LSB)MR18= 0x121c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 416 ps
6025 06:52:41.943001 CH1 RK1: MR19=505, MR18=121C
6026 06:52:41.949788 CH1_RK1: MR19=0x505, MR18=0x121C, DQSOSC=412, MR23=63, INC=63, DEC=42
6027 06:52:41.952633 [RxdqsGatingPostProcess] freq 933
6028 06:52:41.956594 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6029 06:52:41.959692 best DQS0 dly(2T, 0.5T) = (0, 10)
6030 06:52:41.962944 best DQS1 dly(2T, 0.5T) = (0, 10)
6031 06:52:41.966984 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6032 06:52:41.969668 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6033 06:52:41.973067 best DQS0 dly(2T, 0.5T) = (0, 10)
6034 06:52:41.976089 best DQS1 dly(2T, 0.5T) = (0, 10)
6035 06:52:41.979772 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6036 06:52:41.983004 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6037 06:52:41.986189 Pre-setting of DQS Precalculation
6038 06:52:41.989714 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6039 06:52:41.996699 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6040 06:52:42.006471 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6041 06:52:42.006988
6042 06:52:42.007427
6043 06:52:42.009418 [Calibration Summary] 1866 Mbps
6044 06:52:42.009847 CH 0, Rank 0
6045 06:52:42.012798 SW Impedance : PASS
6046 06:52:42.013225 DUTY Scan : NO K
6047 06:52:42.015850 ZQ Calibration : PASS
6048 06:52:42.019295 Jitter Meter : NO K
6049 06:52:42.019725 CBT Training : PASS
6050 06:52:42.022890 Write leveling : PASS
6051 06:52:42.023321 RX DQS gating : PASS
6052 06:52:42.026191 RX DQ/DQS(RDDQC) : PASS
6053 06:52:42.029543 TX DQ/DQS : PASS
6054 06:52:42.030073 RX DATLAT : PASS
6055 06:52:42.032952 RX DQ/DQS(Engine): PASS
6056 06:52:42.036442 TX OE : NO K
6057 06:52:42.036990 All Pass.
6058 06:52:42.037438
6059 06:52:42.037845 CH 0, Rank 1
6060 06:52:42.039980 SW Impedance : PASS
6061 06:52:42.042894 DUTY Scan : NO K
6062 06:52:42.043324 ZQ Calibration : PASS
6063 06:52:42.046352 Jitter Meter : NO K
6064 06:52:42.049476 CBT Training : PASS
6065 06:52:42.050006 Write leveling : PASS
6066 06:52:42.052978 RX DQS gating : PASS
6067 06:52:42.056709 RX DQ/DQS(RDDQC) : PASS
6068 06:52:42.057241 TX DQ/DQS : PASS
6069 06:52:42.059429 RX DATLAT : PASS
6070 06:52:42.059859 RX DQ/DQS(Engine): PASS
6071 06:52:42.062978 TX OE : NO K
6072 06:52:42.063512 All Pass.
6073 06:52:42.063960
6074 06:52:42.066349 CH 1, Rank 0
6075 06:52:42.066819 SW Impedance : PASS
6076 06:52:42.070107 DUTY Scan : NO K
6077 06:52:42.073121 ZQ Calibration : PASS
6078 06:52:42.073653 Jitter Meter : NO K
6079 06:52:42.076443 CBT Training : PASS
6080 06:52:42.079551 Write leveling : PASS
6081 06:52:42.080078 RX DQS gating : PASS
6082 06:52:42.082942 RX DQ/DQS(RDDQC) : PASS
6083 06:52:42.086463 TX DQ/DQS : PASS
6084 06:52:42.086993 RX DATLAT : PASS
6085 06:52:42.089306 RX DQ/DQS(Engine): PASS
6086 06:52:42.093042 TX OE : NO K
6087 06:52:42.093571 All Pass.
6088 06:52:42.094016
6089 06:52:42.094446 CH 1, Rank 1
6090 06:52:42.096442 SW Impedance : PASS
6091 06:52:42.099898 DUTY Scan : NO K
6092 06:52:42.100445 ZQ Calibration : PASS
6093 06:52:42.103441 Jitter Meter : NO K
6094 06:52:42.106184 CBT Training : PASS
6095 06:52:42.106648 Write leveling : PASS
6096 06:52:42.110256 RX DQS gating : PASS
6097 06:52:42.110888 RX DQ/DQS(RDDQC) : PASS
6098 06:52:42.112932 TX DQ/DQS : PASS
6099 06:52:42.116128 RX DATLAT : PASS
6100 06:52:42.116559 RX DQ/DQS(Engine): PASS
6101 06:52:42.119607 TX OE : NO K
6102 06:52:42.120023 All Pass.
6103 06:52:42.120430
6104 06:52:42.123174 DramC Write-DBI off
6105 06:52:42.126233 PER_BANK_REFRESH: Hybrid Mode
6106 06:52:42.126799 TX_TRACKING: ON
6107 06:52:42.136359 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6108 06:52:42.139626 [FAST_K] Save calibration result to emmc
6109 06:52:42.142936 dramc_set_vcore_voltage set vcore to 650000
6110 06:52:42.146436 Read voltage for 400, 6
6111 06:52:42.147154 Vio18 = 0
6112 06:52:42.147508 Vcore = 650000
6113 06:52:42.149616 Vdram = 0
6114 06:52:42.150030 Vddq = 0
6115 06:52:42.150361 Vmddr = 0
6116 06:52:42.156357 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6117 06:52:42.160020 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6118 06:52:42.163146 MEM_TYPE=3, freq_sel=20
6119 06:52:42.166146 sv_algorithm_assistance_LP4_800
6120 06:52:42.169488 ============ PULL DRAM RESETB DOWN ============
6121 06:52:42.173155 ========== PULL DRAM RESETB DOWN end =========
6122 06:52:42.179884 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6123 06:52:42.183067 ===================================
6124 06:52:42.186456 LPDDR4 DRAM CONFIGURATION
6125 06:52:42.189101 ===================================
6126 06:52:42.189530 EX_ROW_EN[0] = 0x0
6127 06:52:42.192482 EX_ROW_EN[1] = 0x0
6128 06:52:42.192899 LP4Y_EN = 0x0
6129 06:52:42.196198 WORK_FSP = 0x0
6130 06:52:42.196722 WL = 0x2
6131 06:52:42.199872 RL = 0x2
6132 06:52:42.200293 BL = 0x2
6133 06:52:42.202812 RPST = 0x0
6134 06:52:42.203229 RD_PRE = 0x0
6135 06:52:42.206371 WR_PRE = 0x1
6136 06:52:42.206876 WR_PST = 0x0
6137 06:52:42.209846 DBI_WR = 0x0
6138 06:52:42.210438 DBI_RD = 0x0
6139 06:52:42.212596 OTF = 0x1
6140 06:52:42.216121 ===================================
6141 06:52:42.219622 ===================================
6142 06:52:42.220109 ANA top config
6143 06:52:42.223191 ===================================
6144 06:52:42.226468 DLL_ASYNC_EN = 0
6145 06:52:42.229944 ALL_SLAVE_EN = 1
6146 06:52:42.233197 NEW_RANK_MODE = 1
6147 06:52:42.233763 DLL_IDLE_MODE = 1
6148 06:52:42.236671 LP45_APHY_COMB_EN = 1
6149 06:52:42.239570 TX_ODT_DIS = 1
6150 06:52:42.243135 NEW_8X_MODE = 1
6151 06:52:42.246277 ===================================
6152 06:52:42.249793 ===================================
6153 06:52:42.252969 data_rate = 800
6154 06:52:42.253536 CKR = 1
6155 06:52:42.256583 DQ_P2S_RATIO = 4
6156 06:52:42.259427 ===================================
6157 06:52:42.263373 CA_P2S_RATIO = 4
6158 06:52:42.266514 DQ_CA_OPEN = 0
6159 06:52:42.269597 DQ_SEMI_OPEN = 1
6160 06:52:42.273180 CA_SEMI_OPEN = 1
6161 06:52:42.273746 CA_FULL_RATE = 0
6162 06:52:42.276691 DQ_CKDIV4_EN = 0
6163 06:52:42.279540 CA_CKDIV4_EN = 1
6164 06:52:42.283395 CA_PREDIV_EN = 0
6165 06:52:42.285994 PH8_DLY = 0
6166 06:52:42.286491 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6167 06:52:42.289555 DQ_AAMCK_DIV = 0
6168 06:52:42.292919 CA_AAMCK_DIV = 0
6169 06:52:42.296153 CA_ADMCK_DIV = 4
6170 06:52:42.299234 DQ_TRACK_CA_EN = 0
6171 06:52:42.302684 CA_PICK = 800
6172 06:52:42.306319 CA_MCKIO = 400
6173 06:52:42.306973 MCKIO_SEMI = 400
6174 06:52:42.309203 PLL_FREQ = 3016
6175 06:52:42.312906 DQ_UI_PI_RATIO = 32
6176 06:52:42.316195 CA_UI_PI_RATIO = 32
6177 06:52:42.319623 ===================================
6178 06:52:42.322736 ===================================
6179 06:52:42.326698 memory_type:LPDDR4
6180 06:52:42.327270 GP_NUM : 10
6181 06:52:42.329604 SRAM_EN : 1
6182 06:52:42.333323 MD32_EN : 0
6183 06:52:42.333894 ===================================
6184 06:52:42.336660 [ANA_INIT] >>>>>>>>>>>>>>
6185 06:52:42.339595 <<<<<< [CONFIGURE PHASE]: ANA_TX
6186 06:52:42.342893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6187 06:52:42.346593 ===================================
6188 06:52:42.349858 data_rate = 800,PCW = 0X7400
6189 06:52:42.353064 ===================================
6190 06:52:42.356656 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6191 06:52:42.363422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6192 06:52:42.372919 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6193 06:52:42.376246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6194 06:52:42.379912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6195 06:52:42.382879 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6196 06:52:42.386007 [ANA_INIT] flow start
6197 06:52:42.389834 [ANA_INIT] PLL >>>>>>>>
6198 06:52:42.390309 [ANA_INIT] PLL <<<<<<<<
6199 06:52:42.392637 [ANA_INIT] MIDPI >>>>>>>>
6200 06:52:42.395877 [ANA_INIT] MIDPI <<<<<<<<
6201 06:52:42.399632 [ANA_INIT] DLL >>>>>>>>
6202 06:52:42.400206 [ANA_INIT] flow end
6203 06:52:42.402512 ============ LP4 DIFF to SE enter ============
6204 06:52:42.409266 ============ LP4 DIFF to SE exit ============
6205 06:52:42.409863 [ANA_INIT] <<<<<<<<<<<<<
6206 06:52:42.412644 [Flow] Enable top DCM control >>>>>
6207 06:52:42.416091 [Flow] Enable top DCM control <<<<<
6208 06:52:42.419009 Enable DLL master slave shuffle
6209 06:52:42.426050 ==============================================================
6210 06:52:42.426660 Gating Mode config
6211 06:52:42.433193 ==============================================================
6212 06:52:42.436088 Config description:
6213 06:52:42.442922 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6214 06:52:42.449717 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6215 06:52:42.455941 SELPH_MODE 0: By rank 1: By Phase
6216 06:52:42.462485 ==============================================================
6217 06:52:42.465770 GAT_TRACK_EN = 0
6218 06:52:42.466194 RX_GATING_MODE = 2
6219 06:52:42.469350 RX_GATING_TRACK_MODE = 2
6220 06:52:42.472683 SELPH_MODE = 1
6221 06:52:42.475811 PICG_EARLY_EN = 1
6222 06:52:42.478878 VALID_LAT_VALUE = 1
6223 06:52:42.485644 ==============================================================
6224 06:52:42.489185 Enter into Gating configuration >>>>
6225 06:52:42.492385 Exit from Gating configuration <<<<
6226 06:52:42.496122 Enter into DVFS_PRE_config >>>>>
6227 06:52:42.505496 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6228 06:52:42.509116 Exit from DVFS_PRE_config <<<<<
6229 06:52:42.512536 Enter into PICG configuration >>>>
6230 06:52:42.515829 Exit from PICG configuration <<<<
6231 06:52:42.519028 [RX_INPUT] configuration >>>>>
6232 06:52:42.519655 [RX_INPUT] configuration <<<<<
6233 06:52:42.526310 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6234 06:52:42.532589 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6235 06:52:42.535785 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6236 06:52:42.542354 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6237 06:52:42.549345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6238 06:52:42.555912 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6239 06:52:42.559414 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6240 06:52:42.562937 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6241 06:52:42.569260 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6242 06:52:42.572965 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6243 06:52:42.576001 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6244 06:52:42.582483 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6245 06:52:42.585720 ===================================
6246 06:52:42.586259 LPDDR4 DRAM CONFIGURATION
6247 06:52:42.589087 ===================================
6248 06:52:42.592585 EX_ROW_EN[0] = 0x0
6249 06:52:42.593006 EX_ROW_EN[1] = 0x0
6250 06:52:42.595785 LP4Y_EN = 0x0
6251 06:52:42.596209 WORK_FSP = 0x0
6252 06:52:42.599354 WL = 0x2
6253 06:52:42.599881 RL = 0x2
6254 06:52:42.602622 BL = 0x2
6255 06:52:42.605966 RPST = 0x0
6256 06:52:42.606572 RD_PRE = 0x0
6257 06:52:42.608955 WR_PRE = 0x1
6258 06:52:42.609378 WR_PST = 0x0
6259 06:52:42.612537 DBI_WR = 0x0
6260 06:52:42.613064 DBI_RD = 0x0
6261 06:52:42.615566 OTF = 0x1
6262 06:52:42.619300 ===================================
6263 06:52:42.622589 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6264 06:52:42.625893 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6265 06:52:42.629145 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6266 06:52:42.633288 ===================================
6267 06:52:42.635619 LPDDR4 DRAM CONFIGURATION
6268 06:52:42.639095 ===================================
6269 06:52:42.642508 EX_ROW_EN[0] = 0x10
6270 06:52:42.643029 EX_ROW_EN[1] = 0x0
6271 06:52:42.646186 LP4Y_EN = 0x0
6272 06:52:42.646768 WORK_FSP = 0x0
6273 06:52:42.649050 WL = 0x2
6274 06:52:42.649476 RL = 0x2
6275 06:52:42.652803 BL = 0x2
6276 06:52:42.653227 RPST = 0x0
6277 06:52:42.656235 RD_PRE = 0x0
6278 06:52:42.656763 WR_PRE = 0x1
6279 06:52:42.659836 WR_PST = 0x0
6280 06:52:42.660337 DBI_WR = 0x0
6281 06:52:42.662903 DBI_RD = 0x0
6282 06:52:42.663429 OTF = 0x1
6283 06:52:42.666165 ===================================
6284 06:52:42.672727 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6285 06:52:42.677511 nWR fixed to 30
6286 06:52:42.681168 [ModeRegInit_LP4] CH0 RK0
6287 06:52:42.681702 [ModeRegInit_LP4] CH0 RK1
6288 06:52:42.683971 [ModeRegInit_LP4] CH1 RK0
6289 06:52:42.687547 [ModeRegInit_LP4] CH1 RK1
6290 06:52:42.688006 match AC timing 19
6291 06:52:42.694786 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6292 06:52:42.697894 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6293 06:52:42.701003 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6294 06:52:42.707125 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6295 06:52:42.710546 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6296 06:52:42.711086 ==
6297 06:52:42.713872 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 06:52:42.717201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 06:52:42.717734 ==
6300 06:52:42.724636 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6301 06:52:42.730731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6302 06:52:42.733791 [CA 0] Center 36 (8~64) winsize 57
6303 06:52:42.737488 [CA 1] Center 36 (8~64) winsize 57
6304 06:52:42.740254 [CA 2] Center 36 (8~64) winsize 57
6305 06:52:42.740737 [CA 3] Center 36 (8~64) winsize 57
6306 06:52:42.743950 [CA 4] Center 36 (8~64) winsize 57
6307 06:52:42.747122 [CA 5] Center 36 (8~64) winsize 57
6308 06:52:42.747589
6309 06:52:42.750539 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6310 06:52:42.754173
6311 06:52:42.757144 [CATrainingPosCal] consider 1 rank data
6312 06:52:42.757786 u2DelayCellTimex100 = 270/100 ps
6313 06:52:42.763914 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 06:52:42.767156 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 06:52:42.770839 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 06:52:42.774539 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 06:52:42.777296 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 06:52:42.781065 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 06:52:42.781640
6320 06:52:42.783773 CA PerBit enable=1, Macro0, CA PI delay=36
6321 06:52:42.784245
6322 06:52:42.787150 [CBTSetCACLKResult] CA Dly = 36
6323 06:52:42.790440 CS Dly: 1 (0~32)
6324 06:52:42.790911 ==
6325 06:52:42.793779 Dram Type= 6, Freq= 0, CH_0, rank 1
6326 06:52:42.796936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 06:52:42.797404 ==
6328 06:52:42.804212 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6329 06:52:42.807512 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6330 06:52:42.810368 [CA 0] Center 36 (8~64) winsize 57
6331 06:52:42.814389 [CA 1] Center 36 (8~64) winsize 57
6332 06:52:42.817135 [CA 2] Center 36 (8~64) winsize 57
6333 06:52:42.820354 [CA 3] Center 36 (8~64) winsize 57
6334 06:52:42.823944 [CA 4] Center 36 (8~64) winsize 57
6335 06:52:42.826965 [CA 5] Center 36 (8~64) winsize 57
6336 06:52:42.827436
6337 06:52:42.830821 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6338 06:52:42.831385
6339 06:52:42.834160 [CATrainingPosCal] consider 2 rank data
6340 06:52:42.836963 u2DelayCellTimex100 = 270/100 ps
6341 06:52:42.840872 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 06:52:42.843862 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 06:52:42.847262 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 06:52:42.850562 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 06:52:42.856997 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 06:52:42.860454 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 06:52:42.860926
6348 06:52:42.864192 CA PerBit enable=1, Macro0, CA PI delay=36
6349 06:52:42.864759
6350 06:52:42.867678 [CBTSetCACLKResult] CA Dly = 36
6351 06:52:42.868147 CS Dly: 1 (0~32)
6352 06:52:42.868614
6353 06:52:42.871088 ----->DramcWriteLeveling(PI) begin...
6354 06:52:42.871663 ==
6355 06:52:42.874363 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 06:52:42.880317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 06:52:42.880883 ==
6358 06:52:42.884500 Write leveling (Byte 0): 40 => 8
6359 06:52:42.885007 Write leveling (Byte 1): 32 => 0
6360 06:52:42.887082 DramcWriteLeveling(PI) end<-----
6361 06:52:42.887547
6362 06:52:42.887918 ==
6363 06:52:42.890677 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 06:52:42.897271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 06:52:42.897694 ==
6366 06:52:42.898030 [Gating] SW mode calibration
6367 06:52:42.907268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6368 06:52:42.910465 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6369 06:52:42.914093 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6370 06:52:42.920584 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6371 06:52:42.924223 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6372 06:52:42.927562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6373 06:52:42.934306 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6374 06:52:42.937299 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6375 06:52:42.940893 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6376 06:52:42.947267 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6377 06:52:42.950394 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6378 06:52:42.954549 Total UI for P1: 0, mck2ui 16
6379 06:52:42.957406 best dqsien dly found for B0: ( 0, 14, 24)
6380 06:52:42.960970 Total UI for P1: 0, mck2ui 16
6381 06:52:42.964313 best dqsien dly found for B1: ( 0, 14, 24)
6382 06:52:42.967666 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6383 06:52:42.970866 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6384 06:52:42.971388
6385 06:52:42.974176 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6386 06:52:42.977928 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6387 06:52:42.981115 [Gating] SW calibration Done
6388 06:52:42.981635 ==
6389 06:52:42.983773 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 06:52:42.987350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 06:52:42.990591 ==
6392 06:52:42.991016 RX Vref Scan: 0
6393 06:52:42.991351
6394 06:52:42.993983 RX Vref 0 -> 0, step: 1
6395 06:52:42.994550
6396 06:52:42.997542 RX Delay -410 -> 252, step: 16
6397 06:52:43.000614 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6398 06:52:43.003929 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6399 06:52:43.007427 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6400 06:52:43.014338 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6401 06:52:43.017253 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6402 06:52:43.020737 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6403 06:52:43.023843 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6404 06:52:43.030926 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6405 06:52:43.034182 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6406 06:52:43.037478 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6407 06:52:43.040585 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6408 06:52:43.047092 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6409 06:52:43.050498 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6410 06:52:43.054236 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6411 06:52:43.057341 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6412 06:52:43.063754 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6413 06:52:43.064282 ==
6414 06:52:43.066947 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 06:52:43.070647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 06:52:43.071176 ==
6417 06:52:43.071511 DQS Delay:
6418 06:52:43.074146 DQS0 = 35, DQS1 = 51
6419 06:52:43.074708 DQM Delay:
6420 06:52:43.077242 DQM0 = 6, DQM1 = 10
6421 06:52:43.077764 DQ Delay:
6422 06:52:43.080466 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6423 06:52:43.083946 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6424 06:52:43.087127 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6425 06:52:43.090438 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6426 06:52:43.090882
6427 06:52:43.091220
6428 06:52:43.091527 ==
6429 06:52:43.093926 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 06:52:43.097619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 06:52:43.098140 ==
6432 06:52:43.098528
6433 06:52:43.098844
6434 06:52:43.100263 TX Vref Scan disable
6435 06:52:43.104246 == TX Byte 0 ==
6436 06:52:43.107018 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6437 06:52:43.110827 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6438 06:52:43.111428 == TX Byte 1 ==
6439 06:52:43.116844 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6440 06:52:43.120390 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6441 06:52:43.120920 ==
6442 06:52:43.123823 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 06:52:43.127562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 06:52:43.128086 ==
6445 06:52:43.128421
6446 06:52:43.128730
6447 06:52:43.130766 TX Vref Scan disable
6448 06:52:43.134298 == TX Byte 0 ==
6449 06:52:43.137203 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6450 06:52:43.140282 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6451 06:52:43.144197 == TX Byte 1 ==
6452 06:52:43.147414 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6453 06:52:43.150664 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6454 06:52:43.151187
6455 06:52:43.151522 [DATLAT]
6456 06:52:43.153859 Freq=400, CH0 RK0
6457 06:52:43.154383
6458 06:52:43.154800 DATLAT Default: 0xf
6459 06:52:43.156995 0, 0xFFFF, sum = 0
6460 06:52:43.157423 1, 0xFFFF, sum = 0
6461 06:52:43.160299 2, 0xFFFF, sum = 0
6462 06:52:43.160766 3, 0xFFFF, sum = 0
6463 06:52:43.164288 4, 0xFFFF, sum = 0
6464 06:52:43.167259 5, 0xFFFF, sum = 0
6465 06:52:43.167798 6, 0xFFFF, sum = 0
6466 06:52:43.170697 7, 0xFFFF, sum = 0
6467 06:52:43.171131 8, 0xFFFF, sum = 0
6468 06:52:43.174247 9, 0xFFFF, sum = 0
6469 06:52:43.174812 10, 0xFFFF, sum = 0
6470 06:52:43.177709 11, 0xFFFF, sum = 0
6471 06:52:43.178242 12, 0xFFFF, sum = 0
6472 06:52:43.180835 13, 0x0, sum = 1
6473 06:52:43.181365 14, 0x0, sum = 2
6474 06:52:43.183920 15, 0x0, sum = 3
6475 06:52:43.184454 16, 0x0, sum = 4
6476 06:52:43.187132 best_step = 14
6477 06:52:43.187559
6478 06:52:43.187897 ==
6479 06:52:43.190980 Dram Type= 6, Freq= 0, CH_0, rank 0
6480 06:52:43.194710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 06:52:43.195252 ==
6482 06:52:43.195600 RX Vref Scan: 1
6483 06:52:43.195918
6484 06:52:43.197090 RX Vref 0 -> 0, step: 1
6485 06:52:43.197512
6486 06:52:43.200749 RX Delay -343 -> 252, step: 8
6487 06:52:43.201174
6488 06:52:43.203837 Set Vref, RX VrefLevel [Byte0]: 52
6489 06:52:43.206886 [Byte1]: 51
6490 06:52:43.211342
6491 06:52:43.211909 Final RX Vref Byte 0 = 52 to rank0
6492 06:52:43.213994 Final RX Vref Byte 1 = 51 to rank0
6493 06:52:43.217747 Final RX Vref Byte 0 = 52 to rank1
6494 06:52:43.221283 Final RX Vref Byte 1 = 51 to rank1==
6495 06:52:43.224537 Dram Type= 6, Freq= 0, CH_0, rank 0
6496 06:52:43.231160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 06:52:43.231691 ==
6498 06:52:43.232030 DQS Delay:
6499 06:52:43.234159 DQS0 = 40, DQS1 = 60
6500 06:52:43.234622 DQM Delay:
6501 06:52:43.234962 DQM0 = 8, DQM1 = 16
6502 06:52:43.237473 DQ Delay:
6503 06:52:43.240772 DQ0 =12, DQ1 =8, DQ2 =4, DQ3 =4
6504 06:52:43.241262 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6505 06:52:43.244453 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6506 06:52:43.247667 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6507 06:52:43.248091
6508 06:52:43.248428
6509 06:52:43.257752 [DQSOSCAuto] RK0, (LSB)MR18= 0x8855, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
6510 06:52:43.261200 CH0 RK0: MR19=C0C, MR18=8855
6511 06:52:43.265043 CH0_RK0: MR19=0xC0C, MR18=0x8855, DQSOSC=392, MR23=63, INC=384, DEC=256
6512 06:52:43.268463 ==
6513 06:52:43.270984 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 06:52:43.274972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 06:52:43.275583 ==
6516 06:52:43.277935 [Gating] SW mode calibration
6517 06:52:43.284370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6518 06:52:43.288049 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6519 06:52:43.295127 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6520 06:52:43.297938 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6521 06:52:43.300751 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6522 06:52:43.307875 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6523 06:52:43.311370 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6524 06:52:43.314544 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6525 06:52:43.321262 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6526 06:52:43.324653 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6527 06:52:43.327780 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6528 06:52:43.331357 Total UI for P1: 0, mck2ui 16
6529 06:52:43.334973 best dqsien dly found for B0: ( 0, 14, 24)
6530 06:52:43.337642 Total UI for P1: 0, mck2ui 16
6531 06:52:43.341203 best dqsien dly found for B1: ( 0, 14, 24)
6532 06:52:43.344548 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6533 06:52:43.347982 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6534 06:52:43.348504
6535 06:52:43.351333 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6536 06:52:43.358132 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6537 06:52:43.358715 [Gating] SW calibration Done
6538 06:52:43.361597 ==
6539 06:52:43.362122 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 06:52:43.367873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 06:52:43.368409 ==
6542 06:52:43.368854 RX Vref Scan: 0
6543 06:52:43.369267
6544 06:52:43.371218 RX Vref 0 -> 0, step: 1
6545 06:52:43.371647
6546 06:52:43.375022 RX Delay -410 -> 252, step: 16
6547 06:52:43.377676 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6548 06:52:43.381217 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6549 06:52:43.387701 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6550 06:52:43.390972 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6551 06:52:43.394506 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6552 06:52:43.398224 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6553 06:52:43.404582 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6554 06:52:43.407993 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6555 06:52:43.410785 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6556 06:52:43.414766 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6557 06:52:43.421661 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6558 06:52:43.424753 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6559 06:52:43.427684 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6560 06:52:43.431345 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6561 06:52:43.437915 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6562 06:52:43.441292 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6563 06:52:43.441856 ==
6564 06:52:43.444876 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 06:52:43.447806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 06:52:43.448278 ==
6567 06:52:43.451142 DQS Delay:
6568 06:52:43.451608 DQS0 = 43, DQS1 = 51
6569 06:52:43.454109 DQM Delay:
6570 06:52:43.454601 DQM0 = 11, DQM1 = 10
6571 06:52:43.454974 DQ Delay:
6572 06:52:43.458085 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6573 06:52:43.461350 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6574 06:52:43.464479 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6575 06:52:43.468031 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6576 06:52:43.468616
6577 06:52:43.468987
6578 06:52:43.469332 ==
6579 06:52:43.470952 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 06:52:43.475616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 06:52:43.477925 ==
6582 06:52:43.478522
6583 06:52:43.478901
6584 06:52:43.479248 TX Vref Scan disable
6585 06:52:43.480821 == TX Byte 0 ==
6586 06:52:43.484901 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6587 06:52:43.487820 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6588 06:52:43.490937 == TX Byte 1 ==
6589 06:52:43.494270 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6590 06:52:43.497632 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6591 06:52:43.498199 ==
6592 06:52:43.501189 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 06:52:43.504679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 06:52:43.508137 ==
6595 06:52:43.508744
6596 06:52:43.509126
6597 06:52:43.509475 TX Vref Scan disable
6598 06:52:43.510839 == TX Byte 0 ==
6599 06:52:43.514432 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6600 06:52:43.518048 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6601 06:52:43.520979 == TX Byte 1 ==
6602 06:52:43.523932 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6603 06:52:43.527688 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6604 06:52:43.528260
6605 06:52:43.528633 [DATLAT]
6606 06:52:43.530863 Freq=400, CH0 RK1
6607 06:52:43.531332
6608 06:52:43.534551 DATLAT Default: 0xe
6609 06:52:43.535111 0, 0xFFFF, sum = 0
6610 06:52:43.537569 1, 0xFFFF, sum = 0
6611 06:52:43.538043 2, 0xFFFF, sum = 0
6612 06:52:43.540640 3, 0xFFFF, sum = 0
6613 06:52:43.541116 4, 0xFFFF, sum = 0
6614 06:52:43.544869 5, 0xFFFF, sum = 0
6615 06:52:43.545444 6, 0xFFFF, sum = 0
6616 06:52:43.547572 7, 0xFFFF, sum = 0
6617 06:52:43.548049 8, 0xFFFF, sum = 0
6618 06:52:43.551289 9, 0xFFFF, sum = 0
6619 06:52:43.551766 10, 0xFFFF, sum = 0
6620 06:52:43.554138 11, 0xFFFF, sum = 0
6621 06:52:43.554702 12, 0xFFFF, sum = 0
6622 06:52:43.557613 13, 0x0, sum = 1
6623 06:52:43.558043 14, 0x0, sum = 2
6624 06:52:43.561129 15, 0x0, sum = 3
6625 06:52:43.561563 16, 0x0, sum = 4
6626 06:52:43.564099 best_step = 14
6627 06:52:43.564524
6628 06:52:43.564859 ==
6629 06:52:43.567563 Dram Type= 6, Freq= 0, CH_0, rank 1
6630 06:52:43.570975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 06:52:43.571403 ==
6632 06:52:43.571743 RX Vref Scan: 0
6633 06:52:43.572058
6634 06:52:43.574232 RX Vref 0 -> 0, step: 1
6635 06:52:43.574681
6636 06:52:43.577727 RX Delay -343 -> 252, step: 8
6637 06:52:43.585110 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6638 06:52:43.588364 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6639 06:52:43.591706 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6640 06:52:43.595219 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6641 06:52:43.602181 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6642 06:52:43.605489 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6643 06:52:43.608728 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6644 06:52:43.611673 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6645 06:52:43.618034 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6646 06:52:43.621862 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6647 06:52:43.624929 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6648 06:52:43.628043 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6649 06:52:43.635193 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6650 06:52:43.638663 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6651 06:52:43.641753 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6652 06:52:43.648952 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6653 06:52:43.649374 ==
6654 06:52:43.652353 Dram Type= 6, Freq= 0, CH_0, rank 1
6655 06:52:43.654734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 06:52:43.655160 ==
6657 06:52:43.655497 DQS Delay:
6658 06:52:43.659095 DQS0 = 48, DQS1 = 60
6659 06:52:43.659611 DQM Delay:
6660 06:52:43.661321 DQM0 = 13, DQM1 = 14
6661 06:52:43.661753 DQ Delay:
6662 06:52:43.665251 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6663 06:52:43.668712 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6664 06:52:43.671988 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =4
6665 06:52:43.675196 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6666 06:52:43.675751
6667 06:52:43.676116
6668 06:52:43.682573 [DQSOSCAuto] RK1, (LSB)MR18= 0x9c6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6669 06:52:43.685413 CH0 RK1: MR19=C0C, MR18=9C6F
6670 06:52:43.691611 CH0_RK1: MR19=0xC0C, MR18=0x9C6F, DQSOSC=390, MR23=63, INC=388, DEC=258
6671 06:52:43.695462 [RxdqsGatingPostProcess] freq 400
6672 06:52:43.698504 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6673 06:52:43.702139 best DQS0 dly(2T, 0.5T) = (0, 10)
6674 06:52:43.705299 best DQS1 dly(2T, 0.5T) = (0, 10)
6675 06:52:43.708939 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6676 06:52:43.712076 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6677 06:52:43.714899 best DQS0 dly(2T, 0.5T) = (0, 10)
6678 06:52:43.718706 best DQS1 dly(2T, 0.5T) = (0, 10)
6679 06:52:43.722068 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6680 06:52:43.725246 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6681 06:52:43.729189 Pre-setting of DQS Precalculation
6682 06:52:43.732044 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6683 06:52:43.732607 ==
6684 06:52:43.735911 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 06:52:43.742099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 06:52:43.742708 ==
6687 06:52:43.745414 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6688 06:52:43.752224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6689 06:52:43.755651 [CA 0] Center 36 (8~64) winsize 57
6690 06:52:43.759154 [CA 1] Center 36 (8~64) winsize 57
6691 06:52:43.762116 [CA 2] Center 36 (8~64) winsize 57
6692 06:52:43.765527 [CA 3] Center 36 (8~64) winsize 57
6693 06:52:43.768927 [CA 4] Center 36 (8~64) winsize 57
6694 06:52:43.772540 [CA 5] Center 36 (8~64) winsize 57
6695 06:52:43.773098
6696 06:52:43.775234 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6697 06:52:43.775698
6698 06:52:43.779048 [CATrainingPosCal] consider 1 rank data
6699 06:52:43.782358 u2DelayCellTimex100 = 270/100 ps
6700 06:52:43.785872 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 06:52:43.789570 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 06:52:43.792155 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 06:52:43.795341 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 06:52:43.799293 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 06:52:43.802267 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 06:52:43.802864
6707 06:52:43.809100 CA PerBit enable=1, Macro0, CA PI delay=36
6708 06:52:43.809648
6709 06:52:43.810017 [CBTSetCACLKResult] CA Dly = 36
6710 06:52:43.812527 CS Dly: 1 (0~32)
6711 06:52:43.813095 ==
6712 06:52:43.815914 Dram Type= 6, Freq= 0, CH_1, rank 1
6713 06:52:43.819021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 06:52:43.819496 ==
6715 06:52:43.825919 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6716 06:52:43.832636 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6717 06:52:43.836018 [CA 0] Center 36 (8~64) winsize 57
6718 06:52:43.839112 [CA 1] Center 36 (8~64) winsize 57
6719 06:52:43.839684 [CA 2] Center 36 (8~64) winsize 57
6720 06:52:43.842146 [CA 3] Center 36 (8~64) winsize 57
6721 06:52:43.846147 [CA 4] Center 36 (8~64) winsize 57
6722 06:52:43.848734 [CA 5] Center 36 (8~64) winsize 57
6723 06:52:43.849205
6724 06:52:43.852170 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6725 06:52:43.855960
6726 06:52:43.858885 [CATrainingPosCal] consider 2 rank data
6727 06:52:43.859355 u2DelayCellTimex100 = 270/100 ps
6728 06:52:43.865634 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 06:52:43.868750 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 06:52:43.872488 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 06:52:43.876079 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 06:52:43.878933 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 06:52:43.881968 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 06:52:43.882552
6735 06:52:43.885544 CA PerBit enable=1, Macro0, CA PI delay=36
6736 06:52:43.886119
6737 06:52:43.888947 [CBTSetCACLKResult] CA Dly = 36
6738 06:52:43.892388 CS Dly: 1 (0~32)
6739 06:52:43.892853
6740 06:52:43.895479 ----->DramcWriteLeveling(PI) begin...
6741 06:52:43.895954 ==
6742 06:52:43.899266 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 06:52:43.902254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 06:52:43.902860 ==
6745 06:52:43.906281 Write leveling (Byte 0): 40 => 8
6746 06:52:43.909815 Write leveling (Byte 1): 40 => 8
6747 06:52:43.912404 DramcWriteLeveling(PI) end<-----
6748 06:52:43.912963
6749 06:52:43.913334 ==
6750 06:52:43.915550 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 06:52:43.919008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 06:52:43.919476 ==
6753 06:52:43.922260 [Gating] SW mode calibration
6754 06:52:43.929650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6755 06:52:43.932422 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6756 06:52:43.939174 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6757 06:52:43.942287 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6758 06:52:43.945707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6759 06:52:43.952787 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6760 06:52:43.956104 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6761 06:52:43.959154 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6762 06:52:43.965836 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6763 06:52:43.969277 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6764 06:52:43.972173 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6765 06:52:43.976070 Total UI for P1: 0, mck2ui 16
6766 06:52:43.979612 best dqsien dly found for B0: ( 0, 14, 24)
6767 06:52:43.982577 Total UI for P1: 0, mck2ui 16
6768 06:52:43.986146 best dqsien dly found for B1: ( 0, 14, 24)
6769 06:52:43.989431 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6770 06:52:43.993980 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6771 06:52:43.994543
6772 06:52:43.998950 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6773 06:52:44.002663 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6774 06:52:44.003247 [Gating] SW calibration Done
6775 06:52:44.006072 ==
6776 06:52:44.009228 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 06:52:44.012665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 06:52:44.013238 ==
6779 06:52:44.013738 RX Vref Scan: 0
6780 06:52:44.014312
6781 06:52:44.016265 RX Vref 0 -> 0, step: 1
6782 06:52:44.016839
6783 06:52:44.019262 RX Delay -410 -> 252, step: 16
6784 06:52:44.022527 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6785 06:52:44.025702 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6786 06:52:44.032788 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6787 06:52:44.035838 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6788 06:52:44.039044 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6789 06:52:44.042752 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6790 06:52:44.049817 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6791 06:52:44.052634 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6792 06:52:44.055701 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6793 06:52:44.058924 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6794 06:52:44.065522 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6795 06:52:44.069413 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6796 06:52:44.072565 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6797 06:52:44.076094 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6798 06:52:44.082846 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6799 06:52:44.086191 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6800 06:52:44.086732 ==
6801 06:52:44.089155 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 06:52:44.092673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 06:52:44.093146 ==
6804 06:52:44.095963 DQS Delay:
6805 06:52:44.096431 DQS0 = 51, DQS1 = 59
6806 06:52:44.099357 DQM Delay:
6807 06:52:44.099823 DQM0 = 19, DQM1 = 16
6808 06:52:44.100243 DQ Delay:
6809 06:52:44.102389 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6810 06:52:44.106273 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6811 06:52:44.109440 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6812 06:52:44.112212 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6813 06:52:44.112679
6814 06:52:44.113049
6815 06:52:44.113388 ==
6816 06:52:44.116074 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 06:52:44.122540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 06:52:44.123103 ==
6819 06:52:44.123476
6820 06:52:44.123820
6821 06:52:44.124147 TX Vref Scan disable
6822 06:52:44.126009 == TX Byte 0 ==
6823 06:52:44.129419 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6824 06:52:44.132860 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6825 06:52:44.135861 == TX Byte 1 ==
6826 06:52:44.139106 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6827 06:52:44.142579 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6828 06:52:44.143254 ==
6829 06:52:44.145988 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 06:52:44.153049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 06:52:44.153622 ==
6832 06:52:44.153998
6833 06:52:44.154343
6834 06:52:44.154699 TX Vref Scan disable
6835 06:52:44.156017 == TX Byte 0 ==
6836 06:52:44.159494 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6837 06:52:44.162393 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6838 06:52:44.166087 == TX Byte 1 ==
6839 06:52:44.169245 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6840 06:52:44.172504 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6841 06:52:44.173076
6842 06:52:44.176053 [DATLAT]
6843 06:52:44.176630 Freq=400, CH1 RK0
6844 06:52:44.177006
6845 06:52:44.179021 DATLAT Default: 0xf
6846 06:52:44.179491 0, 0xFFFF, sum = 0
6847 06:52:44.182693 1, 0xFFFF, sum = 0
6848 06:52:44.183269 2, 0xFFFF, sum = 0
6849 06:52:44.185385 3, 0xFFFF, sum = 0
6850 06:52:44.185860 4, 0xFFFF, sum = 0
6851 06:52:44.189008 5, 0xFFFF, sum = 0
6852 06:52:44.189595 6, 0xFFFF, sum = 0
6853 06:52:44.192543 7, 0xFFFF, sum = 0
6854 06:52:44.193020 8, 0xFFFF, sum = 0
6855 06:52:44.195730 9, 0xFFFF, sum = 0
6856 06:52:44.199380 10, 0xFFFF, sum = 0
6857 06:52:44.199956 11, 0xFFFF, sum = 0
6858 06:52:44.202382 12, 0xFFFF, sum = 0
6859 06:52:44.202906 13, 0x0, sum = 1
6860 06:52:44.203286 14, 0x0, sum = 2
6861 06:52:44.205847 15, 0x0, sum = 3
6862 06:52:44.206322 16, 0x0, sum = 4
6863 06:52:44.209356 best_step = 14
6864 06:52:44.209823
6865 06:52:44.210196 ==
6866 06:52:44.212493 Dram Type= 6, Freq= 0, CH_1, rank 0
6867 06:52:44.216359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 06:52:44.216930 ==
6869 06:52:44.219517 RX Vref Scan: 1
6870 06:52:44.220087
6871 06:52:44.220460 RX Vref 0 -> 0, step: 1
6872 06:52:44.220813
6873 06:52:44.222996 RX Delay -359 -> 252, step: 8
6874 06:52:44.223466
6875 06:52:44.226239 Set Vref, RX VrefLevel [Byte0]: 54
6876 06:52:44.229280 [Byte1]: 51
6877 06:52:44.234443
6878 06:52:44.235049 Final RX Vref Byte 0 = 54 to rank0
6879 06:52:44.237443 Final RX Vref Byte 1 = 51 to rank0
6880 06:52:44.240954 Final RX Vref Byte 0 = 54 to rank1
6881 06:52:44.244287 Final RX Vref Byte 1 = 51 to rank1==
6882 06:52:44.247875 Dram Type= 6, Freq= 0, CH_1, rank 0
6883 06:52:44.250713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 06:52:44.254529 ==
6885 06:52:44.255093 DQS Delay:
6886 06:52:44.255471 DQS0 = 48, DQS1 = 60
6887 06:52:44.258218 DQM Delay:
6888 06:52:44.258843 DQM0 = 13, DQM1 = 12
6889 06:52:44.261060 DQ Delay:
6890 06:52:44.264431 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6891 06:52:44.265000 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6892 06:52:44.267307 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6893 06:52:44.271076 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6894 06:52:44.271649
6895 06:52:44.272024
6896 06:52:44.280912 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d35, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6897 06:52:44.284427 CH1 RK0: MR19=C0C, MR18=8D35
6898 06:52:44.290917 CH1_RK0: MR19=0xC0C, MR18=0x8D35, DQSOSC=392, MR23=63, INC=384, DEC=256
6899 06:52:44.291501 ==
6900 06:52:44.294185 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 06:52:44.297772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 06:52:44.298344 ==
6903 06:52:44.301235 [Gating] SW mode calibration
6904 06:52:44.307768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6905 06:52:44.311037 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6906 06:52:44.317819 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6907 06:52:44.320810 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6908 06:52:44.324447 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6909 06:52:44.330962 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6910 06:52:44.334513 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6911 06:52:44.337921 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6912 06:52:44.344524 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6913 06:52:44.347554 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6914 06:52:44.351252 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6915 06:52:44.354669 Total UI for P1: 0, mck2ui 16
6916 06:52:44.358299 best dqsien dly found for B0: ( 0, 14, 24)
6917 06:52:44.361299 Total UI for P1: 0, mck2ui 16
6918 06:52:44.364864 best dqsien dly found for B1: ( 0, 14, 24)
6919 06:52:44.368387 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6920 06:52:44.370851 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6921 06:52:44.371321
6922 06:52:44.374751 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6923 06:52:44.381371 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6924 06:52:44.381942 [Gating] SW calibration Done
6925 06:52:44.382319 ==
6926 06:52:44.384490 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 06:52:44.391768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 06:52:44.392345 ==
6929 06:52:44.392775 RX Vref Scan: 0
6930 06:52:44.393144
6931 06:52:44.394349 RX Vref 0 -> 0, step: 1
6932 06:52:44.394838
6933 06:52:44.397874 RX Delay -410 -> 252, step: 16
6934 06:52:44.401084 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6935 06:52:44.404664 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6936 06:52:44.411107 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6937 06:52:44.414656 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6938 06:52:44.417712 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6939 06:52:44.421204 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6940 06:52:44.427620 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6941 06:52:44.431630 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6942 06:52:44.434912 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6943 06:52:44.438052 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6944 06:52:44.441576 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6945 06:52:44.448197 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6946 06:52:44.451257 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6947 06:52:44.454698 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6948 06:52:44.461464 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6949 06:52:44.465309 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6950 06:52:44.465880 ==
6951 06:52:44.468151 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 06:52:44.471495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 06:52:44.472071 ==
6954 06:52:44.475215 DQS Delay:
6955 06:52:44.475780 DQS0 = 43, DQS1 = 59
6956 06:52:44.476156 DQM Delay:
6957 06:52:44.478579 DQM0 = 10, DQM1 = 19
6958 06:52:44.479147 DQ Delay:
6959 06:52:44.481969 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6960 06:52:44.484976 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6961 06:52:44.487992 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =8
6962 06:52:44.491683 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =24
6963 06:52:44.492150
6964 06:52:44.492520
6965 06:52:44.492915 ==
6966 06:52:44.494608 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 06:52:44.498617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 06:52:44.499188 ==
6969 06:52:44.499682
6970 06:52:44.500142
6971 06:52:44.501582 TX Vref Scan disable
6972 06:52:44.504854 == TX Byte 0 ==
6973 06:52:44.508208 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6974 06:52:44.511439 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6975 06:52:44.514927 == TX Byte 1 ==
6976 06:52:44.518876 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6977 06:52:44.521327 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6978 06:52:44.521814 ==
6979 06:52:44.524558 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 06:52:44.528467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 06:52:44.528955 ==
6982 06:52:44.529449
6983 06:52:44.529915
6984 06:52:44.531354 TX Vref Scan disable
6985 06:52:44.535065 == TX Byte 0 ==
6986 06:52:44.538545 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6987 06:52:44.541491 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6988 06:52:44.542077 == TX Byte 1 ==
6989 06:52:44.548226 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6990 06:52:44.551362 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6991 06:52:44.551849
6992 06:52:44.552341 [DATLAT]
6993 06:52:44.554627 Freq=400, CH1 RK1
6994 06:52:44.555114
6995 06:52:44.555602 DATLAT Default: 0xe
6996 06:52:44.558691 0, 0xFFFF, sum = 0
6997 06:52:44.559188 1, 0xFFFF, sum = 0
6998 06:52:44.561834 2, 0xFFFF, sum = 0
6999 06:52:44.562458 3, 0xFFFF, sum = 0
7000 06:52:44.565113 4, 0xFFFF, sum = 0
7001 06:52:44.565693 5, 0xFFFF, sum = 0
7002 06:52:44.567941 6, 0xFFFF, sum = 0
7003 06:52:44.571756 7, 0xFFFF, sum = 0
7004 06:52:44.572301 8, 0xFFFF, sum = 0
7005 06:52:44.574877 9, 0xFFFF, sum = 0
7006 06:52:44.575461 10, 0xFFFF, sum = 0
7007 06:52:44.578568 11, 0xFFFF, sum = 0
7008 06:52:44.579148 12, 0xFFFF, sum = 0
7009 06:52:44.582154 13, 0x0, sum = 1
7010 06:52:44.582794 14, 0x0, sum = 2
7011 06:52:44.584707 15, 0x0, sum = 3
7012 06:52:44.585198 16, 0x0, sum = 4
7013 06:52:44.585694 best_step = 14
7014 06:52:44.588100
7015 06:52:44.588729 ==
7016 06:52:44.591504 Dram Type= 6, Freq= 0, CH_1, rank 1
7017 06:52:44.594916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7018 06:52:44.595404 ==
7019 06:52:44.595899 RX Vref Scan: 0
7020 06:52:44.596376
7021 06:52:44.599283 RX Vref 0 -> 0, step: 1
7022 06:52:44.599858
7023 06:52:44.601116 RX Delay -359 -> 252, step: 8
7024 06:52:44.608311 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7025 06:52:44.611987 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7026 06:52:44.615409 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7027 06:52:44.618269 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7028 06:52:44.625278 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7029 06:52:44.628756 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7030 06:52:44.632122 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7031 06:52:44.635364 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7032 06:52:44.641948 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7033 06:52:44.645044 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7034 06:52:44.648464 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7035 06:52:44.652358 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7036 06:52:44.658647 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7037 06:52:44.662302 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7038 06:52:44.664953 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7039 06:52:44.668831 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7040 06:52:44.671738 ==
7041 06:52:44.674996 Dram Type= 6, Freq= 0, CH_1, rank 1
7042 06:52:44.678455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7043 06:52:44.678929 ==
7044 06:52:44.679304 DQS Delay:
7045 06:52:44.682048 DQS0 = 52, DQS1 = 56
7046 06:52:44.682518 DQM Delay:
7047 06:52:44.684873 DQM0 = 13, DQM1 = 9
7048 06:52:44.685297 DQ Delay:
7049 06:52:44.688432 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7050 06:52:44.691816 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7051 06:52:44.694912 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7052 06:52:44.698881 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7053 06:52:44.699410
7054 06:52:44.699750
7055 06:52:44.705015 [DQSOSCAuto] RK1, (LSB)MR18= 0x748a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
7056 06:52:44.708189 CH1 RK1: MR19=C0C, MR18=748A
7057 06:52:44.715515 CH1_RK1: MR19=0xC0C, MR18=0x748A, DQSOSC=392, MR23=63, INC=384, DEC=256
7058 06:52:44.718293 [RxdqsGatingPostProcess] freq 400
7059 06:52:44.722190 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7060 06:52:44.724806 best DQS0 dly(2T, 0.5T) = (0, 10)
7061 06:52:44.728322 best DQS1 dly(2T, 0.5T) = (0, 10)
7062 06:52:44.731907 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7063 06:52:44.735485 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7064 06:52:44.738288 best DQS0 dly(2T, 0.5T) = (0, 10)
7065 06:52:44.742482 best DQS1 dly(2T, 0.5T) = (0, 10)
7066 06:52:44.745507 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7067 06:52:44.749205 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7068 06:52:44.752116 Pre-setting of DQS Precalculation
7069 06:52:44.755337 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7070 06:52:44.761966 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7071 06:52:44.772203 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7072 06:52:44.772822
7073 06:52:44.773211
7074 06:52:44.775087 [Calibration Summary] 800 Mbps
7075 06:52:44.775557 CH 0, Rank 0
7076 06:52:44.779314 SW Impedance : PASS
7077 06:52:44.779888 DUTY Scan : NO K
7078 06:52:44.782012 ZQ Calibration : PASS
7079 06:52:44.782530 Jitter Meter : NO K
7080 06:52:44.785340 CBT Training : PASS
7081 06:52:44.788708 Write leveling : PASS
7082 06:52:44.789173 RX DQS gating : PASS
7083 06:52:44.791758 RX DQ/DQS(RDDQC) : PASS
7084 06:52:44.795527 TX DQ/DQS : PASS
7085 06:52:44.795955 RX DATLAT : PASS
7086 06:52:44.798796 RX DQ/DQS(Engine): PASS
7087 06:52:44.802052 TX OE : NO K
7088 06:52:44.802524 All Pass.
7089 06:52:44.802870
7090 06:52:44.803182 CH 0, Rank 1
7091 06:52:44.806134 SW Impedance : PASS
7092 06:52:44.808749 DUTY Scan : NO K
7093 06:52:44.809198 ZQ Calibration : PASS
7094 06:52:44.811898 Jitter Meter : NO K
7095 06:52:44.815277 CBT Training : PASS
7096 06:52:44.815704 Write leveling : NO K
7097 06:52:44.818488 RX DQS gating : PASS
7098 06:52:44.822784 RX DQ/DQS(RDDQC) : PASS
7099 06:52:44.823323 TX DQ/DQS : PASS
7100 06:52:44.825270 RX DATLAT : PASS
7101 06:52:44.825749 RX DQ/DQS(Engine): PASS
7102 06:52:44.828842 TX OE : NO K
7103 06:52:44.829268 All Pass.
7104 06:52:44.829609
7105 06:52:44.831747 CH 1, Rank 0
7106 06:52:44.832172 SW Impedance : PASS
7107 06:52:44.835435 DUTY Scan : NO K
7108 06:52:44.839016 ZQ Calibration : PASS
7109 06:52:44.839513 Jitter Meter : NO K
7110 06:52:44.842243 CBT Training : PASS
7111 06:52:44.845245 Write leveling : PASS
7112 06:52:44.845683 RX DQS gating : PASS
7113 06:52:44.848690 RX DQ/DQS(RDDQC) : PASS
7114 06:52:44.852505 TX DQ/DQS : PASS
7115 06:52:44.852930 RX DATLAT : PASS
7116 06:52:44.855367 RX DQ/DQS(Engine): PASS
7117 06:52:44.858267 TX OE : NO K
7118 06:52:44.858741 All Pass.
7119 06:52:44.859190
7120 06:52:44.859515 CH 1, Rank 1
7121 06:52:44.862149 SW Impedance : PASS
7122 06:52:44.865337 DUTY Scan : NO K
7123 06:52:44.865853 ZQ Calibration : PASS
7124 06:52:44.868470 Jitter Meter : NO K
7125 06:52:44.872031 CBT Training : PASS
7126 06:52:44.872568 Write leveling : NO K
7127 06:52:44.875532 RX DQS gating : PASS
7128 06:52:44.876048 RX DQ/DQS(RDDQC) : PASS
7129 06:52:44.878831 TX DQ/DQS : PASS
7130 06:52:44.881909 RX DATLAT : PASS
7131 06:52:44.882477 RX DQ/DQS(Engine): PASS
7132 06:52:44.885287 TX OE : NO K
7133 06:52:44.885805 All Pass.
7134 06:52:44.886229
7135 06:52:44.888250 DramC Write-DBI off
7136 06:52:44.891989 PER_BANK_REFRESH: Hybrid Mode
7137 06:52:44.892404 TX_TRACKING: ON
7138 06:52:44.901681 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7139 06:52:44.905052 [FAST_K] Save calibration result to emmc
7140 06:52:44.908582 dramc_set_vcore_voltage set vcore to 725000
7141 06:52:44.912055 Read voltage for 1600, 0
7142 06:52:44.912471 Vio18 = 0
7143 06:52:44.912798 Vcore = 725000
7144 06:52:44.915338 Vdram = 0
7145 06:52:44.915752 Vddq = 0
7146 06:52:44.916094 Vmddr = 0
7147 06:52:44.921487 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7148 06:52:44.925127 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7149 06:52:44.928002 MEM_TYPE=3, freq_sel=13
7150 06:52:44.931774 sv_algorithm_assistance_LP4_3733
7151 06:52:44.934870 ============ PULL DRAM RESETB DOWN ============
7152 06:52:44.938617 ========== PULL DRAM RESETB DOWN end =========
7153 06:52:44.945482 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7154 06:52:44.948643 ===================================
7155 06:52:44.949211 LPDDR4 DRAM CONFIGURATION
7156 06:52:44.952015 ===================================
7157 06:52:44.955702 EX_ROW_EN[0] = 0x0
7158 06:52:44.958796 EX_ROW_EN[1] = 0x0
7159 06:52:44.959245 LP4Y_EN = 0x0
7160 06:52:44.961947 WORK_FSP = 0x1
7161 06:52:44.962392 WL = 0x5
7162 06:52:44.965879 RL = 0x5
7163 06:52:44.966510 BL = 0x2
7164 06:52:44.968436 RPST = 0x0
7165 06:52:44.968856 RD_PRE = 0x0
7166 06:52:44.972454 WR_PRE = 0x1
7167 06:52:44.973006 WR_PST = 0x1
7168 06:52:44.975535 DBI_WR = 0x0
7169 06:52:44.976091 DBI_RD = 0x0
7170 06:52:44.978804 OTF = 0x1
7171 06:52:44.982147 ===================================
7172 06:52:44.985197 ===================================
7173 06:52:44.985633 ANA top config
7174 06:52:44.988610 ===================================
7175 06:52:44.992197 DLL_ASYNC_EN = 0
7176 06:52:44.995361 ALL_SLAVE_EN = 0
7177 06:52:44.995794 NEW_RANK_MODE = 1
7178 06:52:44.998446 DLL_IDLE_MODE = 1
7179 06:52:45.002185 LP45_APHY_COMB_EN = 1
7180 06:52:45.005619 TX_ODT_DIS = 0
7181 06:52:45.008951 NEW_8X_MODE = 1
7182 06:52:45.012125 ===================================
7183 06:52:45.015348 ===================================
7184 06:52:45.015784 data_rate = 3200
7185 06:52:45.018904 CKR = 1
7186 06:52:45.022046 DQ_P2S_RATIO = 8
7187 06:52:45.025323 ===================================
7188 06:52:45.028646 CA_P2S_RATIO = 8
7189 06:52:45.031990 DQ_CA_OPEN = 0
7190 06:52:45.035280 DQ_SEMI_OPEN = 0
7191 06:52:45.035700 CA_SEMI_OPEN = 0
7192 06:52:45.038638 CA_FULL_RATE = 0
7193 06:52:45.042120 DQ_CKDIV4_EN = 0
7194 06:52:45.045162 CA_CKDIV4_EN = 0
7195 06:52:45.048698 CA_PREDIV_EN = 0
7196 06:52:45.052320 PH8_DLY = 12
7197 06:52:45.052744 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7198 06:52:45.055501 DQ_AAMCK_DIV = 4
7199 06:52:45.058685 CA_AAMCK_DIV = 4
7200 06:52:45.062250 CA_ADMCK_DIV = 4
7201 06:52:45.065614 DQ_TRACK_CA_EN = 0
7202 06:52:45.068599 CA_PICK = 1600
7203 06:52:45.072349 CA_MCKIO = 1600
7204 06:52:45.072872 MCKIO_SEMI = 0
7205 06:52:45.075227 PLL_FREQ = 3068
7206 06:52:45.078741 DQ_UI_PI_RATIO = 32
7207 06:52:45.082297 CA_UI_PI_RATIO = 0
7208 06:52:45.085503 ===================================
7209 06:52:45.088496 ===================================
7210 06:52:45.091855 memory_type:LPDDR4
7211 06:52:45.092272 GP_NUM : 10
7212 06:52:45.095176 SRAM_EN : 1
7213 06:52:45.095591 MD32_EN : 0
7214 06:52:45.099093 ===================================
7215 06:52:45.101897 [ANA_INIT] >>>>>>>>>>>>>>
7216 06:52:45.106155 <<<<<< [CONFIGURE PHASE]: ANA_TX
7217 06:52:45.108408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7218 06:52:45.112295 ===================================
7219 06:52:45.115162 data_rate = 3200,PCW = 0X7600
7220 06:52:45.118611 ===================================
7221 06:52:45.122275 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7222 06:52:45.128796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7223 06:52:45.132171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7224 06:52:45.138248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7225 06:52:45.141872 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7226 06:52:45.145339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7227 06:52:45.145758 [ANA_INIT] flow start
7228 06:52:45.148878 [ANA_INIT] PLL >>>>>>>>
7229 06:52:45.152276 [ANA_INIT] PLL <<<<<<<<
7230 06:52:45.152800 [ANA_INIT] MIDPI >>>>>>>>
7231 06:52:45.155249 [ANA_INIT] MIDPI <<<<<<<<
7232 06:52:45.158893 [ANA_INIT] DLL >>>>>>>>
7233 06:52:45.159309 [ANA_INIT] DLL <<<<<<<<
7234 06:52:45.161637 [ANA_INIT] flow end
7235 06:52:45.165604 ============ LP4 DIFF to SE enter ============
7236 06:52:45.168345 ============ LP4 DIFF to SE exit ============
7237 06:52:45.172034 [ANA_INIT] <<<<<<<<<<<<<
7238 06:52:45.175702 [Flow] Enable top DCM control >>>>>
7239 06:52:45.178529 [Flow] Enable top DCM control <<<<<
7240 06:52:45.181849 Enable DLL master slave shuffle
7241 06:52:45.188828 ==============================================================
7242 06:52:45.189341 Gating Mode config
7243 06:52:45.195006 ==============================================================
7244 06:52:45.195487 Config description:
7245 06:52:45.205559 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7246 06:52:45.212081 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7247 06:52:45.218804 SELPH_MODE 0: By rank 1: By Phase
7248 06:52:45.222138 ==============================================================
7249 06:52:45.225768 GAT_TRACK_EN = 1
7250 06:52:45.229061 RX_GATING_MODE = 2
7251 06:52:45.231845 RX_GATING_TRACK_MODE = 2
7252 06:52:45.235679 SELPH_MODE = 1
7253 06:52:45.238887 PICG_EARLY_EN = 1
7254 06:52:45.242209 VALID_LAT_VALUE = 1
7255 06:52:45.245511 ==============================================================
7256 06:52:45.249373 Enter into Gating configuration >>>>
7257 06:52:45.252562 Exit from Gating configuration <<<<
7258 06:52:45.255624 Enter into DVFS_PRE_config >>>>>
7259 06:52:45.269175 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7260 06:52:45.272188 Exit from DVFS_PRE_config <<<<<
7261 06:52:45.275749 Enter into PICG configuration >>>>
7262 06:52:45.279126 Exit from PICG configuration <<<<
7263 06:52:45.279700 [RX_INPUT] configuration >>>>>
7264 06:52:45.282492 [RX_INPUT] configuration <<<<<
7265 06:52:45.288794 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7266 06:52:45.292143 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7267 06:52:45.298782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7268 06:52:45.305586 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7269 06:52:45.312412 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7270 06:52:45.318529 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7271 06:52:45.321961 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7272 06:52:45.325556 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7273 06:52:45.328950 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7274 06:52:45.335636 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7275 06:52:45.338593 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7276 06:52:45.342536 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7277 06:52:45.345517 ===================================
7278 06:52:45.349323 LPDDR4 DRAM CONFIGURATION
7279 06:52:45.351855 ===================================
7280 06:52:45.355239 EX_ROW_EN[0] = 0x0
7281 06:52:45.355707 EX_ROW_EN[1] = 0x0
7282 06:52:45.359104 LP4Y_EN = 0x0
7283 06:52:45.359676 WORK_FSP = 0x1
7284 06:52:45.362166 WL = 0x5
7285 06:52:45.362670 RL = 0x5
7286 06:52:45.365259 BL = 0x2
7287 06:52:45.365759 RPST = 0x0
7288 06:52:45.369064 RD_PRE = 0x0
7289 06:52:45.369639 WR_PRE = 0x1
7290 06:52:45.371892 WR_PST = 0x1
7291 06:52:45.372359 DBI_WR = 0x0
7292 06:52:45.375239 DBI_RD = 0x0
7293 06:52:45.375708 OTF = 0x1
7294 06:52:45.379162 ===================================
7295 06:52:45.382731 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7296 06:52:45.389500 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7297 06:52:45.391975 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7298 06:52:45.395295 ===================================
7299 06:52:45.398498 LPDDR4 DRAM CONFIGURATION
7300 06:52:45.402422 ===================================
7301 06:52:45.402851 EX_ROW_EN[0] = 0x10
7302 06:52:45.406202 EX_ROW_EN[1] = 0x0
7303 06:52:45.408907 LP4Y_EN = 0x0
7304 06:52:45.409335 WORK_FSP = 0x1
7305 06:52:45.412571 WL = 0x5
7306 06:52:45.412997 RL = 0x5
7307 06:52:45.415319 BL = 0x2
7308 06:52:45.415741 RPST = 0x0
7309 06:52:45.418985 RD_PRE = 0x0
7310 06:52:45.419409 WR_PRE = 0x1
7311 06:52:45.422380 WR_PST = 0x1
7312 06:52:45.422957 DBI_WR = 0x0
7313 06:52:45.425843 DBI_RD = 0x0
7314 06:52:45.426369 OTF = 0x1
7315 06:52:45.428959 ===================================
7316 06:52:45.435187 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7317 06:52:45.435658 ==
7318 06:52:45.438828 Dram Type= 6, Freq= 0, CH_0, rank 0
7319 06:52:45.442148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7320 06:52:45.442606 ==
7321 06:52:45.445654 [Duty_Offset_Calibration]
7322 06:52:45.448867 B0:2 B1:-1 CA:1
7323 06:52:45.449386
7324 06:52:45.451965 [DutyScan_Calibration_Flow] k_type=0
7325 06:52:45.459730
7326 06:52:45.460293 ==CLK 0==
7327 06:52:45.462831 Final CLK duty delay cell = -4
7328 06:52:45.466522 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7329 06:52:45.470539 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7330 06:52:45.473752 [-4] AVG Duty = 4937%(X100)
7331 06:52:45.474352
7332 06:52:45.476616 CH0 CLK Duty spec in!! Max-Min= 187%
7333 06:52:45.479797 [DutyScan_Calibration_Flow] ====Done====
7334 06:52:45.480356
7335 06:52:45.483294 [DutyScan_Calibration_Flow] k_type=1
7336 06:52:45.500156
7337 06:52:45.500729 ==DQS 0 ==
7338 06:52:45.503191 Final DQS duty delay cell = 0
7339 06:52:45.505730 [0] MAX Duty = 5125%(X100), DQS PI = 56
7340 06:52:45.509549 [0] MIN Duty = 5031%(X100), DQS PI = 4
7341 06:52:45.510110 [0] AVG Duty = 5078%(X100)
7342 06:52:45.512492
7343 06:52:45.512962 ==DQS 1 ==
7344 06:52:45.516285 Final DQS duty delay cell = -4
7345 06:52:45.519708 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7346 06:52:45.522707 [-4] MIN Duty = 5031%(X100), DQS PI = 20
7347 06:52:45.526280 [-4] AVG Duty = 5062%(X100)
7348 06:52:45.526897
7349 06:52:45.529107 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7350 06:52:45.529813
7351 06:52:45.533551 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7352 06:52:45.536528 [DutyScan_Calibration_Flow] ====Done====
7353 06:52:45.537127
7354 06:52:45.539131 [DutyScan_Calibration_Flow] k_type=3
7355 06:52:45.556426
7356 06:52:45.557015 ==DQM 0 ==
7357 06:52:45.559688 Final DQM duty delay cell = 0
7358 06:52:45.563107 [0] MAX Duty = 5000%(X100), DQS PI = 18
7359 06:52:45.566729 [0] MIN Duty = 4875%(X100), DQS PI = 6
7360 06:52:45.567196 [0] AVG Duty = 4937%(X100)
7361 06:52:45.570008
7362 06:52:45.570479 ==DQM 1 ==
7363 06:52:45.573749 Final DQM duty delay cell = 0
7364 06:52:45.576300 [0] MAX Duty = 5187%(X100), DQS PI = 58
7365 06:52:45.579740 [0] MIN Duty = 4969%(X100), DQS PI = 18
7366 06:52:45.580162 [0] AVG Duty = 5078%(X100)
7367 06:52:45.583568
7368 06:52:45.586758 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7369 06:52:45.587180
7370 06:52:45.589505 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7371 06:52:45.593046 [DutyScan_Calibration_Flow] ====Done====
7372 06:52:45.593467
7373 06:52:45.596477 [DutyScan_Calibration_Flow] k_type=2
7374 06:52:45.613945
7375 06:52:45.614489 ==DQ 0 ==
7376 06:52:45.617157 Final DQ duty delay cell = 0
7377 06:52:45.620177 [0] MAX Duty = 5156%(X100), DQS PI = 0
7378 06:52:45.623839 [0] MIN Duty = 5031%(X100), DQS PI = 6
7379 06:52:45.624572 [0] AVG Duty = 5093%(X100)
7380 06:52:45.624952
7381 06:52:45.627083 ==DQ 1 ==
7382 06:52:45.630511 Final DQ duty delay cell = 0
7383 06:52:45.633722 [0] MAX Duty = 5031%(X100), DQS PI = 30
7384 06:52:45.637057 [0] MIN Duty = 4907%(X100), DQS PI = 26
7385 06:52:45.637616 [0] AVG Duty = 4969%(X100)
7386 06:52:45.637985
7387 06:52:45.640804 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7388 06:52:45.641359
7389 06:52:45.643789 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7390 06:52:45.650331 [DutyScan_Calibration_Flow] ====Done====
7391 06:52:45.650955 ==
7392 06:52:45.653438 Dram Type= 6, Freq= 0, CH_1, rank 0
7393 06:52:45.656810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7394 06:52:45.657282 ==
7395 06:52:45.660660 [Duty_Offset_Calibration]
7396 06:52:45.661220 B0:1 B1:1 CA:2
7397 06:52:45.661594
7398 06:52:45.664158 [DutyScan_Calibration_Flow] k_type=0
7399 06:52:45.673831
7400 06:52:45.674387 ==CLK 0==
7401 06:52:45.677216 Final CLK duty delay cell = 0
7402 06:52:45.680284 [0] MAX Duty = 5187%(X100), DQS PI = 24
7403 06:52:45.683718 [0] MIN Duty = 4938%(X100), DQS PI = 48
7404 06:52:45.684278 [0] AVG Duty = 5062%(X100)
7405 06:52:45.686996
7406 06:52:45.690231 CH1 CLK Duty spec in!! Max-Min= 249%
7407 06:52:45.693835 [DutyScan_Calibration_Flow] ====Done====
7408 06:52:45.694392
7409 06:52:45.696652 [DutyScan_Calibration_Flow] k_type=1
7410 06:52:45.714017
7411 06:52:45.714613 ==DQS 0 ==
7412 06:52:45.717525 Final DQS duty delay cell = 0
7413 06:52:45.720432 [0] MAX Duty = 5062%(X100), DQS PI = 22
7414 06:52:45.723870 [0] MIN Duty = 4813%(X100), DQS PI = 52
7415 06:52:45.726668 [0] AVG Duty = 4937%(X100)
7416 06:52:45.727222
7417 06:52:45.727594 ==DQS 1 ==
7418 06:52:45.729906 Final DQS duty delay cell = 0
7419 06:52:45.733744 [0] MAX Duty = 5062%(X100), DQS PI = 34
7420 06:52:45.737069 [0] MIN Duty = 4938%(X100), DQS PI = 12
7421 06:52:45.739831 [0] AVG Duty = 5000%(X100)
7422 06:52:45.740451
7423 06:52:45.743156 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7424 06:52:45.743621
7425 06:52:45.747095 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7426 06:52:45.749875 [DutyScan_Calibration_Flow] ====Done====
7427 06:52:45.750340
7428 06:52:45.753719 [DutyScan_Calibration_Flow] k_type=3
7429 06:52:45.770311
7430 06:52:45.771028 ==DQM 0 ==
7431 06:52:45.773821 Final DQM duty delay cell = 0
7432 06:52:45.777114 [0] MAX Duty = 5156%(X100), DQS PI = 22
7433 06:52:45.780693 [0] MIN Duty = 4844%(X100), DQS PI = 50
7434 06:52:45.781217 [0] AVG Duty = 5000%(X100)
7435 06:52:45.783905
7436 06:52:45.784324 ==DQM 1 ==
7437 06:52:45.786691 Final DQM duty delay cell = 0
7438 06:52:45.790385 [0] MAX Duty = 5156%(X100), DQS PI = 60
7439 06:52:45.794299 [0] MIN Duty = 4875%(X100), DQS PI = 22
7440 06:52:45.794950 [0] AVG Duty = 5015%(X100)
7441 06:52:45.796914
7442 06:52:45.800746 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7443 06:52:45.801168
7444 06:52:45.804112 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7445 06:52:45.807330 [DutyScan_Calibration_Flow] ====Done====
7446 06:52:45.807755
7447 06:52:45.810235 [DutyScan_Calibration_Flow] k_type=2
7448 06:52:45.827155
7449 06:52:45.827708 ==DQ 0 ==
7450 06:52:45.830772 Final DQ duty delay cell = 0
7451 06:52:45.834302 [0] MAX Duty = 5156%(X100), DQS PI = 20
7452 06:52:45.837462 [0] MIN Duty = 4907%(X100), DQS PI = 50
7453 06:52:45.838017 [0] AVG Duty = 5031%(X100)
7454 06:52:45.841237
7455 06:52:45.841791 ==DQ 1 ==
7456 06:52:45.844146 Final DQ duty delay cell = 0
7457 06:52:45.847097 [0] MAX Duty = 5093%(X100), DQS PI = 8
7458 06:52:45.850578 [0] MIN Duty = 5031%(X100), DQS PI = 0
7459 06:52:45.851046 [0] AVG Duty = 5062%(X100)
7460 06:52:45.851413
7461 06:52:45.853672 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7462 06:52:45.854137
7463 06:52:45.857518 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7464 06:52:45.864375 [DutyScan_Calibration_Flow] ====Done====
7465 06:52:45.866934 nWR fixed to 30
7466 06:52:45.867407 [ModeRegInit_LP4] CH0 RK0
7467 06:52:45.870301 [ModeRegInit_LP4] CH0 RK1
7468 06:52:45.873513 [ModeRegInit_LP4] CH1 RK0
7469 06:52:45.877046 [ModeRegInit_LP4] CH1 RK1
7470 06:52:45.877602 match AC timing 5
7471 06:52:45.880387 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7472 06:52:45.884472 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7473 06:52:45.890806 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7474 06:52:45.894032 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7475 06:52:45.900481 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7476 06:52:45.900948 [MiockJmeterHQA]
7477 06:52:45.901317
7478 06:52:45.903916 [DramcMiockJmeter] u1RxGatingPI = 0
7479 06:52:45.907603 0 : 4252, 4026
7480 06:52:45.908101 4 : 4363, 4137
7481 06:52:45.908473 8 : 4252, 4027
7482 06:52:45.910142 12 : 4252, 4026
7483 06:52:45.910654 16 : 4253, 4027
7484 06:52:45.913830 20 : 4253, 4027
7485 06:52:45.914431 24 : 4255, 4029
7486 06:52:45.917516 28 : 4252, 4027
7487 06:52:45.918096 32 : 4362, 4137
7488 06:52:45.918513 36 : 4363, 4137
7489 06:52:45.920382 40 : 4253, 4027
7490 06:52:45.920945 44 : 4253, 4027
7491 06:52:45.923644 48 : 4252, 4027
7492 06:52:45.924114 52 : 4252, 4027
7493 06:52:45.927134 56 : 4255, 4029
7494 06:52:45.927690 60 : 4363, 4137
7495 06:52:45.930774 64 : 4252, 4029
7496 06:52:45.931365 68 : 4250, 4027
7497 06:52:45.931829 72 : 4250, 4027
7498 06:52:45.933424 76 : 4253, 4029
7499 06:52:45.933897 80 : 4250, 4027
7500 06:52:45.937246 84 : 4360, 4137
7501 06:52:45.937719 88 : 4361, 4137
7502 06:52:45.941046 92 : 4249, 4027
7503 06:52:45.941604 96 : 4250, 3334
7504 06:52:45.941982 100 : 4250, 0
7505 06:52:45.944036 104 : 4249, 0
7506 06:52:45.944597 108 : 4250, 0
7507 06:52:45.947023 112 : 4250, 0
7508 06:52:45.947587 116 : 4253, 0
7509 06:52:45.947962 120 : 4361, 0
7510 06:52:45.950573 124 : 4360, 0
7511 06:52:45.951141 128 : 4363, 0
7512 06:52:45.953688 132 : 4361, 0
7513 06:52:45.954250 136 : 4249, 0
7514 06:52:45.954691 140 : 4250, 0
7515 06:52:45.957093 144 : 4250, 0
7516 06:52:45.957667 148 : 4252, 0
7517 06:52:45.958047 152 : 4250, 0
7518 06:52:45.960442 156 : 4253, 0
7519 06:52:45.960915 160 : 4249, 0
7520 06:52:45.964079 164 : 4250, 0
7521 06:52:45.964644 168 : 4252, 0
7522 06:52:45.965023 172 : 4250, 0
7523 06:52:45.967614 176 : 4360, 0
7524 06:52:45.968182 180 : 4361, 0
7525 06:52:45.970587 184 : 4250, 0
7526 06:52:45.971155 188 : 4252, 0
7527 06:52:45.971536 192 : 4363, 0
7528 06:52:45.974171 196 : 4250, 0
7529 06:52:45.974781 200 : 4250, 0
7530 06:52:45.977521 204 : 4250, 0
7531 06:52:45.978103 208 : 4253, 0
7532 06:52:45.978533 212 : 4250, 210
7533 06:52:45.980653 216 : 4250, 3569
7534 06:52:45.981133 220 : 4250, 4027
7535 06:52:45.983821 224 : 4250, 4027
7536 06:52:45.984382 228 : 4361, 4137
7537 06:52:45.987123 232 : 4250, 4026
7538 06:52:45.987595 236 : 4250, 4027
7539 06:52:45.990744 240 : 4360, 4138
7540 06:52:45.991332 244 : 4250, 4027
7541 06:52:45.994055 248 : 4250, 4026
7542 06:52:45.994568 252 : 4363, 4139
7543 06:52:45.994949 256 : 4250, 4027
7544 06:52:45.996888 260 : 4249, 4027
7545 06:52:45.997358 264 : 4250, 4026
7546 06:52:46.000875 268 : 4253, 4029
7547 06:52:46.001447 272 : 4250, 4027
7548 06:52:46.004038 276 : 4249, 4027
7549 06:52:46.004508 280 : 4361, 4137
7550 06:52:46.006917 284 : 4250, 4026
7551 06:52:46.007387 288 : 4250, 4027
7552 06:52:46.010439 292 : 4360, 4138
7553 06:52:46.011009 296 : 4249, 4027
7554 06:52:46.013816 300 : 4250, 4027
7555 06:52:46.014287 304 : 4363, 4139
7556 06:52:46.014695 308 : 4250, 4027
7557 06:52:46.017055 312 : 4250, 4027
7558 06:52:46.017580 316 : 4250, 4026
7559 06:52:46.021389 320 : 4253, 4029
7560 06:52:46.021951 324 : 4250, 4027
7561 06:52:46.024021 328 : 4250, 4027
7562 06:52:46.024493 332 : 4361, 2895
7563 06:52:46.027810 336 : 4250, 30
7564 06:52:46.028370
7565 06:52:46.028741 MIOCK jitter meter ch=0
7566 06:52:46.029084
7567 06:52:46.030597 1T = (336-100) = 236 dly cells
7568 06:52:46.037303 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7569 06:52:46.037775 ==
7570 06:52:46.040631 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 06:52:46.044315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 06:52:46.044869 ==
7573 06:52:46.050625 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7574 06:52:46.053933 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7575 06:52:46.057477 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7576 06:52:46.063680 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7577 06:52:46.074293 [CA 0] Center 44 (14~75) winsize 62
7578 06:52:46.077592 [CA 1] Center 44 (14~74) winsize 61
7579 06:52:46.080651 [CA 2] Center 39 (10~68) winsize 59
7580 06:52:46.083930 [CA 3] Center 39 (10~68) winsize 59
7581 06:52:46.087083 [CA 4] Center 37 (7~67) winsize 61
7582 06:52:46.090631 [CA 5] Center 37 (7~67) winsize 61
7583 06:52:46.091240
7584 06:52:46.093884 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7585 06:52:46.094349
7586 06:52:46.096735 [CATrainingPosCal] consider 1 rank data
7587 06:52:46.100340 u2DelayCellTimex100 = 275/100 ps
7588 06:52:46.104034 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7589 06:52:46.110495 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7590 06:52:46.113884 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7591 06:52:46.117414 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7592 06:52:46.121439 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7593 06:52:46.123841 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7594 06:52:46.124308
7595 06:52:46.127489 CA PerBit enable=1, Macro0, CA PI delay=37
7596 06:52:46.127957
7597 06:52:46.131014 [CBTSetCACLKResult] CA Dly = 37
7598 06:52:46.133661 CS Dly: 10 (0~41)
7599 06:52:46.137316 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7600 06:52:46.141088 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7601 06:52:46.141651 ==
7602 06:52:46.144055 Dram Type= 6, Freq= 0, CH_0, rank 1
7603 06:52:46.147477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 06:52:46.147945 ==
7605 06:52:46.154037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7606 06:52:46.157686 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7607 06:52:46.163585 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7608 06:52:46.167231 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7609 06:52:46.177558 [CA 0] Center 44 (14~74) winsize 61
7610 06:52:46.180903 [CA 1] Center 44 (14~74) winsize 61
7611 06:52:46.184400 [CA 2] Center 40 (11~69) winsize 59
7612 06:52:46.187627 [CA 3] Center 39 (10~68) winsize 59
7613 06:52:46.191236 [CA 4] Center 37 (8~67) winsize 60
7614 06:52:46.194561 [CA 5] Center 37 (7~67) winsize 61
7615 06:52:46.195121
7616 06:52:46.197938 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7617 06:52:46.198484
7618 06:52:46.200944 [CATrainingPosCal] consider 2 rank data
7619 06:52:46.205263 u2DelayCellTimex100 = 275/100 ps
7620 06:52:46.208203 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7621 06:52:46.214740 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7622 06:52:46.218152 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7623 06:52:46.221521 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7624 06:52:46.224277 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7625 06:52:46.227948 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7626 06:52:46.228513
7627 06:52:46.231435 CA PerBit enable=1, Macro0, CA PI delay=37
7628 06:52:46.231900
7629 06:52:46.234191 [CBTSetCACLKResult] CA Dly = 37
7630 06:52:46.237818 CS Dly: 11 (0~44)
7631 06:52:46.241146 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7632 06:52:46.244650 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7633 06:52:46.245210
7634 06:52:46.247502 ----->DramcWriteLeveling(PI) begin...
7635 06:52:46.247973 ==
7636 06:52:46.251260 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 06:52:46.254379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 06:52:46.258368 ==
7639 06:52:46.260918 Write leveling (Byte 0): 32 => 32
7640 06:52:46.261481 Write leveling (Byte 1): 26 => 26
7641 06:52:46.264244 DramcWriteLeveling(PI) end<-----
7642 06:52:46.264745
7643 06:52:46.265289 ==
7644 06:52:46.267763 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 06:52:46.274200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 06:52:46.274816 ==
7647 06:52:46.277727 [Gating] SW mode calibration
7648 06:52:46.284458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7649 06:52:46.287591 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7650 06:52:46.293950 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 06:52:46.297387 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 06:52:46.301376 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 06:52:46.307370 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 06:52:46.311141 1 4 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7655 06:52:46.314239 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7656 06:52:46.317322 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7657 06:52:46.323892 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7658 06:52:46.327510 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 06:52:46.330487 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7660 06:52:46.337484 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7661 06:52:46.341517 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7662 06:52:46.344393 1 5 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7663 06:52:46.350957 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
7664 06:52:46.354373 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7665 06:52:46.357713 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 06:52:46.364544 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 06:52:46.367971 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 06:52:46.370786 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7669 06:52:46.378286 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 06:52:46.380844 1 6 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7671 06:52:46.383963 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
7672 06:52:46.390839 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7673 06:52:46.394198 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 06:52:46.397587 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 06:52:46.401017 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 06:52:46.408385 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7677 06:52:46.410585 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 06:52:46.414051 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7679 06:52:46.422052 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7680 06:52:46.424320 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7681 06:52:46.427402 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 06:52:46.434079 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 06:52:46.437957 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 06:52:46.441088 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 06:52:46.447675 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 06:52:46.450919 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 06:52:46.454292 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 06:52:46.460938 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 06:52:46.464133 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 06:52:46.467567 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 06:52:46.474202 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 06:52:46.478028 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 06:52:46.481009 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 06:52:46.488315 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7695 06:52:46.491109 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7696 06:52:46.494554 Total UI for P1: 0, mck2ui 16
7697 06:52:46.497313 best dqsien dly found for B0: ( 1, 9, 16)
7698 06:52:46.501071 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7699 06:52:46.504091 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7700 06:52:46.507801 Total UI for P1: 0, mck2ui 16
7701 06:52:46.510729 best dqsien dly found for B1: ( 1, 9, 22)
7702 06:52:46.514253 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7703 06:52:46.517795 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7704 06:52:46.521468
7705 06:52:46.524357 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7706 06:52:46.528097 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7707 06:52:46.530924 [Gating] SW calibration Done
7708 06:52:46.531445 ==
7709 06:52:46.534174 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 06:52:46.537786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 06:52:46.538342 ==
7712 06:52:46.538765 RX Vref Scan: 0
7713 06:52:46.541144
7714 06:52:46.541691 RX Vref 0 -> 0, step: 1
7715 06:52:46.542063
7716 06:52:46.544053 RX Delay 0 -> 252, step: 8
7717 06:52:46.547860 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7718 06:52:46.550961 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7719 06:52:46.557469 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7720 06:52:46.561070 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7721 06:52:46.564469 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7722 06:52:46.567719 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7723 06:52:46.571644 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7724 06:52:46.574243 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7725 06:52:46.581294 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7726 06:52:46.584146 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7727 06:52:46.587649 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7728 06:52:46.590706 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7729 06:52:46.597360 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7730 06:52:46.601004 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7731 06:52:46.604589 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7732 06:52:46.607843 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7733 06:52:46.608397 ==
7734 06:52:46.611267 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 06:52:46.614026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 06:52:46.617495 ==
7737 06:52:46.618218 DQS Delay:
7738 06:52:46.618663 DQS0 = 0, DQS1 = 0
7739 06:52:46.621959 DQM Delay:
7740 06:52:46.622555 DQM0 = 132, DQM1 = 123
7741 06:52:46.624342 DQ Delay:
7742 06:52:46.627750 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7743 06:52:46.631086 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7744 06:52:46.634234 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7745 06:52:46.637379 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7746 06:52:46.637842
7747 06:52:46.638255
7748 06:52:46.638662 ==
7749 06:52:46.640748 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 06:52:46.644785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 06:52:46.645346 ==
7752 06:52:46.645713
7753 06:52:46.647442
7754 06:52:46.647906 TX Vref Scan disable
7755 06:52:46.650847 == TX Byte 0 ==
7756 06:52:46.654236 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7757 06:52:46.658032 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7758 06:52:46.661389 == TX Byte 1 ==
7759 06:52:46.664885 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7760 06:52:46.668358 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7761 06:52:46.668921 ==
7762 06:52:46.670874 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 06:52:46.674563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 06:52:46.677954 ==
7765 06:52:46.689794
7766 06:52:46.693499 TX Vref early break, caculate TX vref
7767 06:52:46.697083 TX Vref=16, minBit 7, minWin=21, winSum=358
7768 06:52:46.700177 TX Vref=18, minBit 0, minWin=22, winSum=365
7769 06:52:46.703279 TX Vref=20, minBit 8, minWin=22, winSum=377
7770 06:52:46.706800 TX Vref=22, minBit 9, minWin=23, winSum=390
7771 06:52:46.709609 TX Vref=24, minBit 4, minWin=23, winSum=400
7772 06:52:46.716316 TX Vref=26, minBit 3, minWin=24, winSum=405
7773 06:52:46.719978 TX Vref=28, minBit 0, minWin=25, winSum=415
7774 06:52:46.723425 TX Vref=30, minBit 0, minWin=25, winSum=413
7775 06:52:46.726911 TX Vref=32, minBit 0, minWin=24, winSum=405
7776 06:52:46.729513 TX Vref=34, minBit 4, minWin=23, winSum=392
7777 06:52:46.736782 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
7778 06:52:46.737326
7779 06:52:46.739588 Final TX Range 0 Vref 28
7780 06:52:46.739999
7781 06:52:46.740345 ==
7782 06:52:46.742993 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 06:52:46.746543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 06:52:46.747109 ==
7785 06:52:46.747486
7786 06:52:46.747827
7787 06:52:46.749905 TX Vref Scan disable
7788 06:52:46.756211 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7789 06:52:46.756758 == TX Byte 0 ==
7790 06:52:46.760190 u2DelayCellOfst[0]=17 cells (5 PI)
7791 06:52:46.763041 u2DelayCellOfst[1]=21 cells (6 PI)
7792 06:52:46.766532 u2DelayCellOfst[2]=10 cells (3 PI)
7793 06:52:46.769672 u2DelayCellOfst[3]=17 cells (5 PI)
7794 06:52:46.772917 u2DelayCellOfst[4]=10 cells (3 PI)
7795 06:52:46.776647 u2DelayCellOfst[5]=0 cells (0 PI)
7796 06:52:46.777210 u2DelayCellOfst[6]=21 cells (6 PI)
7797 06:52:46.780197 u2DelayCellOfst[7]=21 cells (6 PI)
7798 06:52:46.787310 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7799 06:52:46.790490 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7800 06:52:46.791060 == TX Byte 1 ==
7801 06:52:46.793356 u2DelayCellOfst[8]=0 cells (0 PI)
7802 06:52:46.797148 u2DelayCellOfst[9]=0 cells (0 PI)
7803 06:52:46.800022 u2DelayCellOfst[10]=7 cells (2 PI)
7804 06:52:46.803905 u2DelayCellOfst[11]=0 cells (0 PI)
7805 06:52:46.806435 u2DelayCellOfst[12]=10 cells (3 PI)
7806 06:52:46.810659 u2DelayCellOfst[13]=10 cells (3 PI)
7807 06:52:46.813179 u2DelayCellOfst[14]=14 cells (4 PI)
7808 06:52:46.816883 u2DelayCellOfst[15]=10 cells (3 PI)
7809 06:52:46.820461 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7810 06:52:46.823233 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7811 06:52:46.826234 DramC Write-DBI on
7812 06:52:46.826749 ==
7813 06:52:46.829430 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 06:52:46.833407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 06:52:46.833880 ==
7816 06:52:46.834250
7817 06:52:46.836547
7818 06:52:46.837102 TX Vref Scan disable
7819 06:52:46.839299 == TX Byte 0 ==
7820 06:52:46.842924 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7821 06:52:46.846712 == TX Byte 1 ==
7822 06:52:46.849854 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7823 06:52:46.850275 DramC Write-DBI off
7824 06:52:46.850649
7825 06:52:46.852623 [DATLAT]
7826 06:52:46.853041 Freq=1600, CH0 RK0
7827 06:52:46.853449
7828 06:52:46.856342 DATLAT Default: 0xf
7829 06:52:46.856766 0, 0xFFFF, sum = 0
7830 06:52:46.859604 1, 0xFFFF, sum = 0
7831 06:52:46.860052 2, 0xFFFF, sum = 0
7832 06:52:46.862713 3, 0xFFFF, sum = 0
7833 06:52:46.863137 4, 0xFFFF, sum = 0
7834 06:52:46.866040 5, 0xFFFF, sum = 0
7835 06:52:46.866505 6, 0xFFFF, sum = 0
7836 06:52:46.869468 7, 0xFFFF, sum = 0
7837 06:52:46.872644 8, 0xFFFF, sum = 0
7838 06:52:46.873087 9, 0xFFFF, sum = 0
7839 06:52:46.876109 10, 0xFFFF, sum = 0
7840 06:52:46.876536 11, 0xFFFF, sum = 0
7841 06:52:46.879544 12, 0xFFFF, sum = 0
7842 06:52:46.879970 13, 0xFFFF, sum = 0
7843 06:52:46.883417 14, 0x0, sum = 1
7844 06:52:46.883843 15, 0x0, sum = 2
7845 06:52:46.885725 16, 0x0, sum = 3
7846 06:52:46.886150 17, 0x0, sum = 4
7847 06:52:46.889245 best_step = 15
7848 06:52:46.889661
7849 06:52:46.889987 ==
7850 06:52:46.893056 Dram Type= 6, Freq= 0, CH_0, rank 0
7851 06:52:46.896180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7852 06:52:46.896605 ==
7853 06:52:46.896940 RX Vref Scan: 1
7854 06:52:46.897313
7855 06:52:46.899478 Set Vref Range= 24 -> 127
7856 06:52:46.899901
7857 06:52:46.902552 RX Vref 24 -> 127, step: 1
7858 06:52:46.902975
7859 06:52:46.906152 RX Delay 11 -> 252, step: 4
7860 06:52:46.906614
7861 06:52:46.909475 Set Vref, RX VrefLevel [Byte0]: 24
7862 06:52:46.912925 [Byte1]: 24
7863 06:52:46.913454
7864 06:52:46.915932 Set Vref, RX VrefLevel [Byte0]: 25
7865 06:52:46.919453 [Byte1]: 25
7866 06:52:46.919876
7867 06:52:46.922845 Set Vref, RX VrefLevel [Byte0]: 26
7868 06:52:46.926503 [Byte1]: 26
7869 06:52:46.930138
7870 06:52:46.930712 Set Vref, RX VrefLevel [Byte0]: 27
7871 06:52:46.932982 [Byte1]: 27
7872 06:52:46.937361
7873 06:52:46.937781 Set Vref, RX VrefLevel [Byte0]: 28
7874 06:52:46.940680 [Byte1]: 28
7875 06:52:46.945453
7876 06:52:46.945998 Set Vref, RX VrefLevel [Byte0]: 29
7877 06:52:46.948449 [Byte1]: 29
7878 06:52:46.952795
7879 06:52:46.953346 Set Vref, RX VrefLevel [Byte0]: 30
7880 06:52:46.955913 [Byte1]: 30
7881 06:52:46.960207
7882 06:52:46.960729 Set Vref, RX VrefLevel [Byte0]: 31
7883 06:52:46.964130 [Byte1]: 31
7884 06:52:46.968457
7885 06:52:46.968985 Set Vref, RX VrefLevel [Byte0]: 32
7886 06:52:46.970911 [Byte1]: 32
7887 06:52:46.975707
7888 06:52:46.976127 Set Vref, RX VrefLevel [Byte0]: 33
7889 06:52:46.978544 [Byte1]: 33
7890 06:52:46.983297
7891 06:52:46.983817 Set Vref, RX VrefLevel [Byte0]: 34
7892 06:52:46.986556 [Byte1]: 34
7893 06:52:46.990679
7894 06:52:46.991207 Set Vref, RX VrefLevel [Byte0]: 35
7895 06:52:46.993994 [Byte1]: 35
7896 06:52:46.998324
7897 06:52:46.998981 Set Vref, RX VrefLevel [Byte0]: 36
7898 06:52:47.002068 [Byte1]: 36
7899 06:52:47.006109
7900 06:52:47.006665 Set Vref, RX VrefLevel [Byte0]: 37
7901 06:52:47.010282 [Byte1]: 37
7902 06:52:47.013437
7903 06:52:47.013962 Set Vref, RX VrefLevel [Byte0]: 38
7904 06:52:47.017283 [Byte1]: 38
7905 06:52:47.021344
7906 06:52:47.021868 Set Vref, RX VrefLevel [Byte0]: 39
7907 06:52:47.024663 [Byte1]: 39
7908 06:52:47.028789
7909 06:52:47.029313 Set Vref, RX VrefLevel [Byte0]: 40
7910 06:52:47.032249 [Byte1]: 40
7911 06:52:47.036454
7912 06:52:47.036994 Set Vref, RX VrefLevel [Byte0]: 41
7913 06:52:47.040319 [Byte1]: 41
7914 06:52:47.044326
7915 06:52:47.044850 Set Vref, RX VrefLevel [Byte0]: 42
7916 06:52:47.047235 [Byte1]: 42
7917 06:52:47.051775
7918 06:52:47.052310 Set Vref, RX VrefLevel [Byte0]: 43
7919 06:52:47.055093 [Byte1]: 43
7920 06:52:47.059089
7921 06:52:47.059507 Set Vref, RX VrefLevel [Byte0]: 44
7922 06:52:47.062580 [Byte1]: 44
7923 06:52:47.066943
7924 06:52:47.067462 Set Vref, RX VrefLevel [Byte0]: 45
7925 06:52:47.070562 [Byte1]: 45
7926 06:52:47.074964
7927 06:52:47.075484 Set Vref, RX VrefLevel [Byte0]: 46
7928 06:52:47.077629 [Byte1]: 46
7929 06:52:47.082163
7930 06:52:47.082733 Set Vref, RX VrefLevel [Byte0]: 47
7931 06:52:47.085417 [Byte1]: 47
7932 06:52:47.089752
7933 06:52:47.090292 Set Vref, RX VrefLevel [Byte0]: 48
7934 06:52:47.092757 [Byte1]: 48
7935 06:52:47.097038
7936 06:52:47.097528 Set Vref, RX VrefLevel [Byte0]: 49
7937 06:52:47.100298 [Byte1]: 49
7938 06:52:47.104684
7939 06:52:47.105268 Set Vref, RX VrefLevel [Byte0]: 50
7940 06:52:47.107920 [Byte1]: 50
7941 06:52:47.112744
7942 06:52:47.113309 Set Vref, RX VrefLevel [Byte0]: 51
7943 06:52:47.115782 [Byte1]: 51
7944 06:52:47.120380
7945 06:52:47.120958 Set Vref, RX VrefLevel [Byte0]: 52
7946 06:52:47.123669 [Byte1]: 52
7947 06:52:47.127857
7948 06:52:47.128419 Set Vref, RX VrefLevel [Byte0]: 53
7949 06:52:47.131269 [Byte1]: 53
7950 06:52:47.135155
7951 06:52:47.135723 Set Vref, RX VrefLevel [Byte0]: 54
7952 06:52:47.138820 [Byte1]: 54
7953 06:52:47.142903
7954 06:52:47.143470 Set Vref, RX VrefLevel [Byte0]: 55
7955 06:52:47.146863 [Byte1]: 55
7956 06:52:47.150542
7957 06:52:47.151105 Set Vref, RX VrefLevel [Byte0]: 56
7958 06:52:47.153741 [Byte1]: 56
7959 06:52:47.158569
7960 06:52:47.159191 Set Vref, RX VrefLevel [Byte0]: 57
7961 06:52:47.161215 [Byte1]: 57
7962 06:52:47.165818
7963 06:52:47.166382 Set Vref, RX VrefLevel [Byte0]: 58
7964 06:52:47.169171 [Byte1]: 58
7965 06:52:47.173267
7966 06:52:47.173731 Set Vref, RX VrefLevel [Byte0]: 59
7967 06:52:47.176992 [Byte1]: 59
7968 06:52:47.181173
7969 06:52:47.181736 Set Vref, RX VrefLevel [Byte0]: 60
7970 06:52:47.183877 [Byte1]: 60
7971 06:52:47.188703
7972 06:52:47.189270 Set Vref, RX VrefLevel [Byte0]: 61
7973 06:52:47.191990 [Byte1]: 61
7974 06:52:47.196075
7975 06:52:47.196535 Set Vref, RX VrefLevel [Byte0]: 62
7976 06:52:47.199372 [Byte1]: 62
7977 06:52:47.203703
7978 06:52:47.204268 Set Vref, RX VrefLevel [Byte0]: 63
7979 06:52:47.207888 [Byte1]: 63
7980 06:52:47.212068
7981 06:52:47.212531 Set Vref, RX VrefLevel [Byte0]: 64
7982 06:52:47.214778 [Byte1]: 64
7983 06:52:47.218856
7984 06:52:47.219314 Set Vref, RX VrefLevel [Byte0]: 65
7985 06:52:47.222276 [Byte1]: 65
7986 06:52:47.226541
7987 06:52:47.226962 Set Vref, RX VrefLevel [Byte0]: 66
7988 06:52:47.230204 [Byte1]: 66
7989 06:52:47.234365
7990 06:52:47.234978 Set Vref, RX VrefLevel [Byte0]: 67
7991 06:52:47.237548 [Byte1]: 67
7992 06:52:47.242254
7993 06:52:47.243130 Set Vref, RX VrefLevel [Byte0]: 68
7994 06:52:47.245581 [Byte1]: 68
7995 06:52:47.249538
7996 06:52:47.250110 Set Vref, RX VrefLevel [Byte0]: 69
7997 06:52:47.252682 [Byte1]: 69
7998 06:52:47.257341
7999 06:52:47.257910 Set Vref, RX VrefLevel [Byte0]: 70
8000 06:52:47.260176 [Byte1]: 70
8001 06:52:47.264928
8002 06:52:47.265515 Set Vref, RX VrefLevel [Byte0]: 71
8003 06:52:47.268322 [Byte1]: 71
8004 06:52:47.272391
8005 06:52:47.272954 Set Vref, RX VrefLevel [Byte0]: 72
8006 06:52:47.275746 [Byte1]: 72
8007 06:52:47.279715
8008 06:52:47.280276 Set Vref, RX VrefLevel [Byte0]: 73
8009 06:52:47.283212 [Byte1]: 73
8010 06:52:47.287840
8011 06:52:47.288401 Set Vref, RX VrefLevel [Byte0]: 74
8012 06:52:47.290896 [Byte1]: 74
8013 06:52:47.295341
8014 06:52:47.295975 Set Vref, RX VrefLevel [Byte0]: 75
8015 06:52:47.298639 [Byte1]: 75
8016 06:52:47.302522
8017 06:52:47.302984 Set Vref, RX VrefLevel [Byte0]: 76
8018 06:52:47.305795 [Byte1]: 76
8019 06:52:56.022227
8020 06:52:56.022701 Set Vref, RX VrefLevel [Byte0]: 77
8021 06:52:56.022767 [Byte1]: 77
8022 06:52:56.022827
8023 06:52:56.022888 Final RX Vref Byte 0 = 56 to rank0
8024 06:52:56.022953 Final RX Vref Byte 1 = 63 to rank0
8025 06:52:56.023009 Final RX Vref Byte 0 = 56 to rank1
8026 06:52:56.023076 Final RX Vref Byte 1 = 63 to rank1==
8027 06:52:56.023130 Dram Type= 6, Freq= 0, CH_0, rank 0
8028 06:52:56.023182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 06:52:56.023234 ==
8030 06:52:56.023287 DQS Delay:
8031 06:52:56.023337 DQS0 = 0, DQS1 = 0
8032 06:52:56.023388 DQM Delay:
8033 06:52:56.023439 DQM0 = 129, DQM1 = 121
8034 06:52:56.023490 DQ Delay:
8035 06:52:56.023572 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
8036 06:52:56.023651 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
8037 06:52:56.023702 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116
8038 06:52:56.023753 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8039 06:52:56.023804
8040 06:52:56.023853
8041 06:52:56.023903
8042 06:52:56.023954 [DramC_TX_OE_Calibration] TA2
8043 06:52:56.024004 Original DQ_B0 (3 6) =30, OEN = 27
8044 06:52:56.024056 Original DQ_B1 (3 6) =30, OEN = 27
8045 06:52:56.024106 24, 0x0, End_B0=24 End_B1=24
8046 06:52:56.024158 25, 0x0, End_B0=25 End_B1=25
8047 06:52:56.024209 26, 0x0, End_B0=26 End_B1=26
8048 06:52:56.024261 27, 0x0, End_B0=27 End_B1=27
8049 06:52:56.024312 28, 0x0, End_B0=28 End_B1=28
8050 06:52:56.024363 29, 0x0, End_B0=29 End_B1=29
8051 06:52:56.024432 30, 0x0, End_B0=30 End_B1=30
8052 06:52:56.024496 31, 0x4141, End_B0=30 End_B1=30
8053 06:52:56.024548 Byte0 end_step=30 best_step=27
8054 06:52:56.024598 Byte1 end_step=30 best_step=27
8055 06:52:56.024649 Byte0 TX OE(2T, 0.5T) = (3, 3)
8056 06:52:56.024699 Byte1 TX OE(2T, 0.5T) = (3, 3)
8057 06:52:56.024749
8058 06:52:56.024799
8059 06:52:56.024849 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8060 06:52:56.024930 CH0 RK0: MR19=303, MR18=1509
8061 06:52:56.025020 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
8062 06:52:56.025100
8063 06:52:56.025152 ----->DramcWriteLeveling(PI) begin...
8064 06:52:56.025204 ==
8065 06:52:56.025269 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 06:52:56.025320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 06:52:56.025371 ==
8068 06:52:56.025421 Write leveling (Byte 0): 32 => 32
8069 06:52:56.025472 Write leveling (Byte 1): 27 => 27
8070 06:52:56.025523 DramcWriteLeveling(PI) end<-----
8071 06:52:56.025574
8072 06:52:56.025624 ==
8073 06:52:56.025674 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 06:52:56.025725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 06:52:56.025796 ==
8076 06:52:56.025860 [Gating] SW mode calibration
8077 06:52:56.025910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8078 06:52:56.025962 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8079 06:52:56.026012 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 06:52:56.026064 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 06:52:56.026114 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8082 06:52:56.026165 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8083 06:52:56.026215 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8084 06:52:56.026266 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8085 06:52:56.026316 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8086 06:52:56.026366 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8087 06:52:56.026448 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8088 06:52:56.026526 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8089 06:52:56.026576 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8090 06:52:56.026626 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8091 06:52:56.026677 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8092 06:52:56.026727 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8093 06:52:56.026778 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 06:52:56.026828 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 06:52:56.026882 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 06:52:56.026941 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 06:52:56.027034 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8098 06:52:56.027090 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8099 06:52:56.027192 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8100 06:52:56.027288 1 6 20 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
8101 06:52:56.027369 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 06:52:56.027449 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 06:52:56.027529 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 06:52:56.027609 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 06:52:56.027689 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8106 06:52:56.027769 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8107 06:52:56.027848 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8108 06:52:56.027927 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8109 06:52:56.028007 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 06:52:56.028086 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 06:52:56.028165 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 06:52:56.028244 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 06:52:56.028323 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 06:52:56.028402 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 06:52:56.028481 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 06:52:56.028560 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 06:52:56.028640 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 06:52:56.028719 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 06:52:56.028798 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 06:52:56.028878 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 06:52:56.028958 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8122 06:52:56.029037 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8123 06:52:56.029116 Total UI for P1: 0, mck2ui 16
8124 06:52:56.029197 best dqsien dly found for B0: ( 1, 9, 8)
8125 06:52:56.029501 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8126 06:52:56.029617 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8127 06:52:56.029699 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8128 06:52:56.029781 Total UI for P1: 0, mck2ui 16
8129 06:52:56.029863 best dqsien dly found for B1: ( 1, 9, 20)
8130 06:52:56.029944 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8131 06:52:56.030037 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8132 06:52:56.030116
8133 06:52:56.030195 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8134 06:52:56.030276 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8135 06:52:56.030355 [Gating] SW calibration Done
8136 06:52:56.030492 ==
8137 06:52:56.030572 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 06:52:56.030652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 06:52:56.030764 ==
8140 06:52:56.030845 RX Vref Scan: 0
8141 06:52:56.030924
8142 06:52:56.031004 RX Vref 0 -> 0, step: 1
8143 06:52:56.031083
8144 06:52:56.031162 RX Delay 0 -> 252, step: 8
8145 06:52:56.031241 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8146 06:52:56.031321 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8147 06:52:56.031401 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8148 06:52:56.031481 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8149 06:52:56.031560 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8150 06:52:56.031640 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8151 06:52:56.031719 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8152 06:52:56.031799 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8153 06:52:56.031878 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8154 06:52:56.031958 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8155 06:52:56.032038 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8156 06:52:56.032117 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8157 06:52:56.032197 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8158 06:52:56.032276 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8159 06:52:56.032356 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8160 06:52:56.032435 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8161 06:52:56.032513 ==
8162 06:52:56.032593 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 06:52:56.032660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 06:52:56.032720 ==
8165 06:52:56.032772 DQS Delay:
8166 06:52:56.032822 DQS0 = 0, DQS1 = 0
8167 06:52:56.032873 DQM Delay:
8168 06:52:56.032924 DQM0 = 131, DQM1 = 124
8169 06:52:56.032975 DQ Delay:
8170 06:52:56.033025 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8171 06:52:56.033076 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8172 06:52:56.033127 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8173 06:52:56.033179 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8174 06:52:56.033229
8175 06:52:56.033279
8176 06:52:56.033329 ==
8177 06:52:56.033380 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 06:52:56.033430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 06:52:56.033481 ==
8180 06:52:56.033531
8181 06:52:56.033581
8182 06:52:56.033632 TX Vref Scan disable
8183 06:52:56.033682 == TX Byte 0 ==
8184 06:52:56.033732 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8185 06:52:56.033783 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8186 06:52:56.033834 == TX Byte 1 ==
8187 06:52:56.033884 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8188 06:52:56.033935 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8189 06:52:56.033986 ==
8190 06:52:56.034036 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 06:52:56.034087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 06:52:56.034138 ==
8193 06:52:56.034188
8194 06:52:56.034238 TX Vref early break, caculate TX vref
8195 06:52:56.034290 TX Vref=16, minBit 8, minWin=22, winSum=374
8196 06:52:56.034341 TX Vref=18, minBit 0, minWin=23, winSum=379
8197 06:52:56.034392 TX Vref=20, minBit 9, minWin=23, winSum=391
8198 06:52:56.034483 TX Vref=22, minBit 3, minWin=23, winSum=398
8199 06:52:56.034534 TX Vref=24, minBit 3, minWin=25, winSum=409
8200 06:52:56.034584 TX Vref=26, minBit 4, minWin=25, winSum=417
8201 06:52:56.034639 TX Vref=28, minBit 4, minWin=25, winSum=419
8202 06:52:56.034697 TX Vref=30, minBit 8, minWin=25, winSum=416
8203 06:52:56.034749 TX Vref=32, minBit 8, minWin=24, winSum=409
8204 06:52:56.034800 TX Vref=34, minBit 8, minWin=24, winSum=404
8205 06:52:56.034851 TX Vref=36, minBit 0, minWin=24, winSum=396
8206 06:52:56.034902 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 28
8207 06:52:56.034953
8208 06:52:56.035004 Final TX Range 0 Vref 28
8209 06:52:56.035055
8210 06:52:56.035119 ==
8211 06:52:56.035171 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 06:52:56.035222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 06:52:56.035274 ==
8214 06:52:56.035325
8215 06:52:56.035376
8216 06:52:56.035427 TX Vref Scan disable
8217 06:52:56.035479 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8218 06:52:56.035531 == TX Byte 0 ==
8219 06:52:56.035582 u2DelayCellOfst[0]=10 cells (3 PI)
8220 06:52:56.035633 u2DelayCellOfst[1]=17 cells (5 PI)
8221 06:52:56.035685 u2DelayCellOfst[2]=7 cells (2 PI)
8222 06:52:56.035737 u2DelayCellOfst[3]=10 cells (3 PI)
8223 06:52:56.035788 u2DelayCellOfst[4]=7 cells (2 PI)
8224 06:52:56.035840 u2DelayCellOfst[5]=0 cells (0 PI)
8225 06:52:56.035891 u2DelayCellOfst[6]=17 cells (5 PI)
8226 06:52:56.035942 u2DelayCellOfst[7]=17 cells (5 PI)
8227 06:52:56.035993 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8228 06:52:56.036045 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8229 06:52:56.036097 == TX Byte 1 ==
8230 06:52:56.036148 u2DelayCellOfst[8]=0 cells (0 PI)
8231 06:52:56.036199 u2DelayCellOfst[9]=0 cells (0 PI)
8232 06:52:56.036251 u2DelayCellOfst[10]=7 cells (2 PI)
8233 06:52:56.036302 u2DelayCellOfst[11]=0 cells (0 PI)
8234 06:52:56.036354 u2DelayCellOfst[12]=10 cells (3 PI)
8235 06:52:56.036405 u2DelayCellOfst[13]=10 cells (3 PI)
8236 06:52:56.036457 u2DelayCellOfst[14]=14 cells (4 PI)
8237 06:52:56.036508 u2DelayCellOfst[15]=10 cells (3 PI)
8238 06:52:56.036559 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8239 06:52:56.036611 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8240 06:52:56.036675 DramC Write-DBI on
8241 06:52:56.036771 ==
8242 06:52:56.036872 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 06:52:56.036929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 06:52:56.036982 ==
8245 06:52:56.037035
8246 06:52:56.037086
8247 06:52:56.037138 TX Vref Scan disable
8248 06:52:56.037189 == TX Byte 0 ==
8249 06:52:56.037241 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8250 06:52:56.037293 == TX Byte 1 ==
8251 06:52:56.037344 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8252 06:52:56.037395 DramC Write-DBI off
8253 06:52:56.037446
8254 06:52:56.037497 [DATLAT]
8255 06:52:56.037548 Freq=1600, CH0 RK1
8256 06:52:56.037600
8257 06:52:56.037651 DATLAT Default: 0xf
8258 06:52:56.037702 0, 0xFFFF, sum = 0
8259 06:52:56.037944 1, 0xFFFF, sum = 0
8260 06:52:56.038004 2, 0xFFFF, sum = 0
8261 06:52:56.038058 3, 0xFFFF, sum = 0
8262 06:52:56.038111 4, 0xFFFF, sum = 0
8263 06:52:56.038163 5, 0xFFFF, sum = 0
8264 06:52:56.038216 6, 0xFFFF, sum = 0
8265 06:52:56.038268 7, 0xFFFF, sum = 0
8266 06:52:56.038321 8, 0xFFFF, sum = 0
8267 06:52:56.038373 9, 0xFFFF, sum = 0
8268 06:52:56.038468 10, 0xFFFF, sum = 0
8269 06:52:56.038523 11, 0xFFFF, sum = 0
8270 06:52:56.038576 12, 0xFFFF, sum = 0
8271 06:52:56.038628 13, 0xFFFF, sum = 0
8272 06:52:56.038681 14, 0x0, sum = 1
8273 06:52:56.038733 15, 0x0, sum = 2
8274 06:52:56.038796 16, 0x0, sum = 3
8275 06:52:56.038850 17, 0x0, sum = 4
8276 06:52:56.038902 best_step = 15
8277 06:52:56.038954
8278 06:52:56.039005 ==
8279 06:52:56.039057 Dram Type= 6, Freq= 0, CH_0, rank 1
8280 06:52:56.039110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 06:52:56.039162 ==
8282 06:52:56.039214 RX Vref Scan: 0
8283 06:52:56.039265
8284 06:52:56.039316 RX Vref 0 -> 0, step: 1
8285 06:52:56.039367
8286 06:52:56.039419 RX Delay 11 -> 252, step: 4
8287 06:52:56.039471 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8288 06:52:56.039523 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8289 06:52:56.039575 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8290 06:52:56.039627 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8291 06:52:56.039678 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8292 06:52:56.039729 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8293 06:52:56.039781 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8294 06:52:56.039832 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8295 06:52:56.039884 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8296 06:52:56.039935 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8297 06:52:56.039987 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8298 06:52:56.040039 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8299 06:52:56.040090 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8300 06:52:56.040141 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8301 06:52:56.040192 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8302 06:52:56.040243 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8303 06:52:56.040295 ==
8304 06:52:56.040346 Dram Type= 6, Freq= 0, CH_0, rank 1
8305 06:52:56.040398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 06:52:56.040450 ==
8307 06:52:56.040501 DQS Delay:
8308 06:52:56.040552 DQS0 = 0, DQS1 = 0
8309 06:52:56.040604 DQM Delay:
8310 06:52:56.040657 DQM0 = 126, DQM1 = 123
8311 06:52:56.040709 DQ Delay:
8312 06:52:56.040764 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8313 06:52:56.040822 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =136
8314 06:52:56.040875 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =116
8315 06:52:56.040926 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8316 06:52:56.040977
8317 06:52:56.041028
8318 06:52:56.041079
8319 06:52:56.041129 [DramC_TX_OE_Calibration] TA2
8320 06:52:56.041180 Original DQ_B0 (3 6) =30, OEN = 27
8321 06:52:56.041232 Original DQ_B1 (3 6) =30, OEN = 27
8322 06:52:56.041283 24, 0x0, End_B0=24 End_B1=24
8323 06:52:56.041335 25, 0x0, End_B0=25 End_B1=25
8324 06:52:56.041387 26, 0x0, End_B0=26 End_B1=26
8325 06:52:56.041439 27, 0x0, End_B0=27 End_B1=27
8326 06:52:56.041491 28, 0x0, End_B0=28 End_B1=28
8327 06:52:56.041544 29, 0x0, End_B0=29 End_B1=29
8328 06:52:56.041596 30, 0x0, End_B0=30 End_B1=30
8329 06:52:56.041648 31, 0x5151, End_B0=30 End_B1=30
8330 06:52:56.041700 Byte0 end_step=30 best_step=27
8331 06:52:56.041751 Byte1 end_step=30 best_step=27
8332 06:52:56.041803 Byte0 TX OE(2T, 0.5T) = (3, 3)
8333 06:52:56.041854 Byte1 TX OE(2T, 0.5T) = (3, 3)
8334 06:52:56.041905
8335 06:52:56.041956
8336 06:52:56.042007 [DQSOSCAuto] RK1, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8337 06:52:56.042059 CH0 RK1: MR19=303, MR18=190F
8338 06:52:56.042111 CH0_RK1: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8339 06:52:56.042164 [RxdqsGatingPostProcess] freq 1600
8340 06:52:56.042218 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8341 06:52:56.042270 best DQS0 dly(2T, 0.5T) = (1, 1)
8342 06:52:56.042321 best DQS1 dly(2T, 0.5T) = (1, 1)
8343 06:52:56.042372 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8344 06:52:56.042464 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8345 06:52:56.042516 best DQS0 dly(2T, 0.5T) = (1, 1)
8346 06:52:56.042568 best DQS1 dly(2T, 0.5T) = (1, 1)
8347 06:52:56.042619 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8348 06:52:56.042671 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8349 06:52:56.042722 Pre-setting of DQS Precalculation
8350 06:52:56.042780 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8351 06:52:56.042839 ==
8352 06:52:56.042892 Dram Type= 6, Freq= 0, CH_1, rank 0
8353 06:52:56.042944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8354 06:52:56.042996 ==
8355 06:52:56.043048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8356 06:52:56.043100 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8357 06:52:56.043152 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8358 06:52:56.043203 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8359 06:52:56.043255 [CA 0] Center 42 (14~71) winsize 58
8360 06:52:56.043307 [CA 1] Center 42 (13~71) winsize 59
8361 06:52:56.043358 [CA 2] Center 37 (8~66) winsize 59
8362 06:52:56.043410 [CA 3] Center 36 (7~65) winsize 59
8363 06:52:56.043461 [CA 4] Center 37 (8~67) winsize 60
8364 06:52:56.043512 [CA 5] Center 36 (7~66) winsize 60
8365 06:52:56.043563
8366 06:52:56.043614 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8367 06:52:56.043665
8368 06:52:56.043716 [CATrainingPosCal] consider 1 rank data
8369 06:52:56.043767 u2DelayCellTimex100 = 275/100 ps
8370 06:52:56.043818 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8371 06:52:56.043869 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8372 06:52:56.043920 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8373 06:52:56.043971 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8374 06:52:56.044022 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8375 06:52:56.044073 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8376 06:52:56.044124
8377 06:52:56.044175 CA PerBit enable=1, Macro0, CA PI delay=36
8378 06:52:56.044225
8379 06:52:56.044275 [CBTSetCACLKResult] CA Dly = 36
8380 06:52:56.044326 CS Dly: 9 (0~40)
8381 06:52:56.044377 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8382 06:52:56.044428 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8383 06:52:56.044478 ==
8384 06:52:56.044529 Dram Type= 6, Freq= 0, CH_1, rank 1
8385 06:52:56.044580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8386 06:52:56.044632 ==
8387 06:52:56.044683 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8388 06:52:56.044734 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8389 06:52:56.044987 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8390 06:52:56.045047 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8391 06:52:56.045101 [CA 0] Center 42 (13~72) winsize 60
8392 06:52:56.045154 [CA 1] Center 42 (14~71) winsize 58
8393 06:52:56.045205 [CA 2] Center 37 (8~66) winsize 59
8394 06:52:56.045256 [CA 3] Center 37 (8~66) winsize 59
8395 06:52:56.045308 [CA 4] Center 37 (8~67) winsize 60
8396 06:52:56.045359 [CA 5] Center 36 (7~66) winsize 60
8397 06:52:56.045411
8398 06:52:56.045462 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8399 06:52:56.045513
8400 06:52:56.045566 [CATrainingPosCal] consider 2 rank data
8401 06:52:56.045618 u2DelayCellTimex100 = 275/100 ps
8402 06:52:56.045669 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8403 06:52:56.045721 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8404 06:52:56.045772 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8405 06:52:56.045823 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8406 06:52:56.045875 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8407 06:52:56.045926 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8408 06:52:56.045977
8409 06:52:56.046028 CA PerBit enable=1, Macro0, CA PI delay=36
8410 06:52:56.046079
8411 06:52:56.046130 [CBTSetCACLKResult] CA Dly = 36
8412 06:52:56.046180 CS Dly: 11 (0~45)
8413 06:52:56.046231 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8414 06:52:56.046283 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8415 06:52:56.046334
8416 06:52:56.046385 ----->DramcWriteLeveling(PI) begin...
8417 06:52:56.046454 ==
8418 06:52:56.046548 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 06:52:56.046631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 06:52:56.046711 ==
8421 06:52:56.046798 Write leveling (Byte 0): 25 => 25
8422 06:52:56.046882 Write leveling (Byte 1): 30 => 30
8423 06:52:56.046963 DramcWriteLeveling(PI) end<-----
8424 06:52:56.047042
8425 06:52:56.047122 ==
8426 06:52:56.047202 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 06:52:56.047283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 06:52:56.047363 ==
8429 06:52:56.047444 [Gating] SW mode calibration
8430 06:52:56.047525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8431 06:52:56.047607 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8432 06:52:56.047688 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 06:52:56.047769 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 06:52:56.047851 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 06:52:56.047906 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 06:52:56.047958 1 4 16 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
8437 06:52:56.048009 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8438 06:52:56.048060 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8439 06:52:56.048113 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 06:52:56.048164 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 06:52:56.048216 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 06:52:56.048267 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 06:52:56.048318 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 06:52:56.048369 1 5 16 | B1->B0 | 3131 3333 | 1 1 | (1 0) (1 1)
8445 06:52:56.048419 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8446 06:52:56.048470 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 06:52:56.048521 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 06:52:56.048572 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 06:52:56.048624 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 06:52:56.048675 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 06:52:56.048725 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 06:52:56.048782 1 6 16 | B1->B0 | 3f3f 3838 | 0 0 | (1 1) (0 0)
8453 06:52:56.048868 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8454 06:52:56.048949 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 06:52:56.049003 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 06:52:56.049055 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 06:52:56.049106 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 06:52:56.049157 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 06:52:56.049209 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8460 06:52:56.049260 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8461 06:52:56.049311 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8462 06:52:56.049362 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 06:52:56.049413 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 06:52:56.049465 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 06:52:56.049516 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 06:52:56.049568 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 06:52:56.049618 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 06:52:56.049670 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 06:52:56.049721 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 06:52:56.049771 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 06:52:56.049822 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 06:52:56.049874 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 06:52:56.049926 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 06:52:56.049977 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 06:52:56.050028 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 06:52:56.050079 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8477 06:52:56.050130 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8478 06:52:56.050180 Total UI for P1: 0, mck2ui 16
8479 06:52:56.050231 best dqsien dly found for B0: ( 1, 9, 16)
8480 06:52:56.050282 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8481 06:52:56.050333 Total UI for P1: 0, mck2ui 16
8482 06:52:56.050384 best dqsien dly found for B1: ( 1, 9, 18)
8483 06:52:56.050469 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8484 06:52:56.050534 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8485 06:52:56.050585
8486 06:52:56.050636 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8487 06:52:56.050885 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8488 06:52:56.051018 [Gating] SW calibration Done
8489 06:52:56.051124 ==
8490 06:52:56.051229 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 06:52:56.051335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 06:52:56.051431 ==
8493 06:52:56.051521 RX Vref Scan: 0
8494 06:52:56.051586
8495 06:52:56.051639 RX Vref 0 -> 0, step: 1
8496 06:52:56.051691
8497 06:52:56.051743 RX Delay 0 -> 252, step: 8
8498 06:52:56.051794 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8499 06:52:56.051846 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8500 06:52:56.051898 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8501 06:52:56.051949 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8502 06:52:56.052000 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8503 06:52:56.052051 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8504 06:52:56.052103 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8505 06:52:56.052154 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8506 06:52:56.052205 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8507 06:52:56.052256 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8508 06:52:56.052307 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8509 06:52:56.052358 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8510 06:52:56.052411 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8511 06:52:56.052462 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8512 06:52:56.052513 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8513 06:52:56.052564 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8514 06:52:56.052615 ==
8515 06:52:56.052666 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 06:52:56.052718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 06:52:56.052769 ==
8518 06:52:56.052821 DQS Delay:
8519 06:52:56.052872 DQS0 = 0, DQS1 = 0
8520 06:52:56.052923 DQM Delay:
8521 06:52:56.052974 DQM0 = 134, DQM1 = 127
8522 06:52:56.053025 DQ Delay:
8523 06:52:56.053076 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8524 06:52:56.053127 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8525 06:52:56.053178 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8526 06:52:56.053229 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8527 06:52:56.053280
8528 06:52:56.053330
8529 06:52:56.053381 ==
8530 06:52:56.053432 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 06:52:56.053483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 06:52:56.053534 ==
8533 06:52:56.053585
8534 06:52:56.053635
8535 06:52:56.053686 TX Vref Scan disable
8536 06:52:56.053737 == TX Byte 0 ==
8537 06:52:56.053788 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8538 06:52:56.053839 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8539 06:52:56.053890 == TX Byte 1 ==
8540 06:52:56.053941 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8541 06:52:56.053992 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8542 06:52:56.054042 ==
8543 06:52:56.054093 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 06:52:56.054144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 06:52:56.054195 ==
8546 06:52:56.054246
8547 06:52:56.054297 TX Vref early break, caculate TX vref
8548 06:52:56.054348 TX Vref=16, minBit 5, minWin=21, winSum=361
8549 06:52:56.054406 TX Vref=18, minBit 8, minWin=22, winSum=370
8550 06:52:56.054497 TX Vref=20, minBit 5, minWin=22, winSum=383
8551 06:52:56.054549 TX Vref=22, minBit 8, minWin=22, winSum=394
8552 06:52:56.054601 TX Vref=24, minBit 8, minWin=24, winSum=405
8553 06:52:56.054653 TX Vref=26, minBit 0, minWin=25, winSum=413
8554 06:52:56.054704 TX Vref=28, minBit 0, minWin=25, winSum=417
8555 06:52:56.054755 TX Vref=30, minBit 0, minWin=25, winSum=414
8556 06:52:56.054806 TX Vref=32, minBit 8, minWin=24, winSum=404
8557 06:52:56.054857 TX Vref=34, minBit 11, minWin=23, winSum=397
8558 06:52:56.054908 TX Vref=36, minBit 0, minWin=23, winSum=385
8559 06:52:56.054959 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8560 06:52:56.055011
8561 06:52:56.055061 Final TX Range 0 Vref 28
8562 06:52:56.055112
8563 06:52:56.055163 ==
8564 06:52:56.055213 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 06:52:56.055265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 06:52:56.055316 ==
8567 06:52:56.055367
8568 06:52:56.055417
8569 06:52:56.055467 TX Vref Scan disable
8570 06:52:56.055518 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8571 06:52:56.055569 == TX Byte 0 ==
8572 06:52:56.055620 u2DelayCellOfst[0]=17 cells (5 PI)
8573 06:52:56.055671 u2DelayCellOfst[1]=14 cells (4 PI)
8574 06:52:56.055723 u2DelayCellOfst[2]=0 cells (0 PI)
8575 06:52:56.055774 u2DelayCellOfst[3]=7 cells (2 PI)
8576 06:52:56.055825 u2DelayCellOfst[4]=7 cells (2 PI)
8577 06:52:56.055876 u2DelayCellOfst[5]=21 cells (6 PI)
8578 06:52:56.055927 u2DelayCellOfst[6]=17 cells (5 PI)
8579 06:52:56.055978 u2DelayCellOfst[7]=7 cells (2 PI)
8580 06:52:56.056029 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8581 06:52:56.056080 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8582 06:52:56.056131 == TX Byte 1 ==
8583 06:52:56.056182 u2DelayCellOfst[8]=0 cells (0 PI)
8584 06:52:56.056232 u2DelayCellOfst[9]=3 cells (1 PI)
8585 06:52:56.056283 u2DelayCellOfst[10]=7 cells (2 PI)
8586 06:52:56.056334 u2DelayCellOfst[11]=7 cells (2 PI)
8587 06:52:56.056385 u2DelayCellOfst[12]=10 cells (3 PI)
8588 06:52:56.056435 u2DelayCellOfst[13]=14 cells (4 PI)
8589 06:52:56.056486 u2DelayCellOfst[14]=17 cells (5 PI)
8590 06:52:56.056537 u2DelayCellOfst[15]=14 cells (4 PI)
8591 06:52:56.056588 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8592 06:52:56.056639 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8593 06:52:56.056690 DramC Write-DBI on
8594 06:52:56.056740 ==
8595 06:52:56.056791 Dram Type= 6, Freq= 0, CH_1, rank 0
8596 06:52:56.056842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8597 06:52:56.056894 ==
8598 06:52:56.056946
8599 06:52:56.056996
8600 06:52:56.057046 TX Vref Scan disable
8601 06:52:56.057097 == TX Byte 0 ==
8602 06:52:56.057148 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8603 06:52:56.057198 == TX Byte 1 ==
8604 06:52:56.057249 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8605 06:52:56.057300 DramC Write-DBI off
8606 06:52:56.057351
8607 06:52:56.057402 [DATLAT]
8608 06:52:56.057452 Freq=1600, CH1 RK0
8609 06:52:56.057503
8610 06:52:56.057553 DATLAT Default: 0xf
8611 06:52:56.057604 0, 0xFFFF, sum = 0
8612 06:52:56.057656 1, 0xFFFF, sum = 0
8613 06:52:56.057707 2, 0xFFFF, sum = 0
8614 06:52:56.057760 3, 0xFFFF, sum = 0
8615 06:52:56.057811 4, 0xFFFF, sum = 0
8616 06:52:56.057863 5, 0xFFFF, sum = 0
8617 06:52:56.057915 6, 0xFFFF, sum = 0
8618 06:52:56.057967 7, 0xFFFF, sum = 0
8619 06:52:56.058018 8, 0xFFFF, sum = 0
8620 06:52:56.058070 9, 0xFFFF, sum = 0
8621 06:52:56.058121 10, 0xFFFF, sum = 0
8622 06:52:56.058173 11, 0xFFFF, sum = 0
8623 06:52:56.058225 12, 0xFFFF, sum = 0
8624 06:52:56.058277 13, 0xFFFF, sum = 0
8625 06:52:56.058328 14, 0x0, sum = 1
8626 06:52:56.058379 15, 0x0, sum = 2
8627 06:52:56.058439 16, 0x0, sum = 3
8628 06:52:56.058492 17, 0x0, sum = 4
8629 06:52:56.058543 best_step = 15
8630 06:52:56.058594
8631 06:52:56.058840 ==
8632 06:52:56.058929 Dram Type= 6, Freq= 0, CH_1, rank 0
8633 06:52:56.059035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8634 06:52:56.059141 ==
8635 06:52:56.059245 RX Vref Scan: 1
8636 06:52:56.059342
8637 06:52:56.059431 Set Vref Range= 24 -> 127
8638 06:52:56.059501
8639 06:52:56.059553 RX Vref 24 -> 127, step: 1
8640 06:52:56.059605
8641 06:52:56.059656 RX Delay 11 -> 252, step: 4
8642 06:52:56.059708
8643 06:52:56.059759 Set Vref, RX VrefLevel [Byte0]: 24
8644 06:52:56.059811 [Byte1]: 24
8645 06:52:56.059862
8646 06:52:56.059912 Set Vref, RX VrefLevel [Byte0]: 25
8647 06:52:56.059964 [Byte1]: 25
8648 06:52:56.060014
8649 06:52:56.060065 Set Vref, RX VrefLevel [Byte0]: 26
8650 06:52:56.060116 [Byte1]: 26
8651 06:52:56.060167
8652 06:52:56.060218 Set Vref, RX VrefLevel [Byte0]: 27
8653 06:52:56.060270 [Byte1]: 27
8654 06:52:56.060320
8655 06:52:56.060371 Set Vref, RX VrefLevel [Byte0]: 28
8656 06:52:56.060422 [Byte1]: 28
8657 06:52:56.060473
8658 06:52:56.060524 Set Vref, RX VrefLevel [Byte0]: 29
8659 06:52:56.060575 [Byte1]: 29
8660 06:52:56.060626
8661 06:52:56.060676 Set Vref, RX VrefLevel [Byte0]: 30
8662 06:52:56.060727 [Byte1]: 30
8663 06:52:56.060778
8664 06:52:56.060829 Set Vref, RX VrefLevel [Byte0]: 31
8665 06:52:56.060879 [Byte1]: 31
8666 06:52:56.060930
8667 06:52:56.060981 Set Vref, RX VrefLevel [Byte0]: 32
8668 06:52:56.061032 [Byte1]: 32
8669 06:52:56.061083
8670 06:52:56.061133 Set Vref, RX VrefLevel [Byte0]: 33
8671 06:52:56.061184 [Byte1]: 33
8672 06:52:56.061235
8673 06:52:56.061286 Set Vref, RX VrefLevel [Byte0]: 34
8674 06:52:56.061337 [Byte1]: 34
8675 06:52:56.061388
8676 06:52:56.061438 Set Vref, RX VrefLevel [Byte0]: 35
8677 06:52:56.061490 [Byte1]: 35
8678 06:52:56.061541
8679 06:52:56.061591 Set Vref, RX VrefLevel [Byte0]: 36
8680 06:52:56.061642 [Byte1]: 36
8681 06:52:56.061692
8682 06:52:56.061742 Set Vref, RX VrefLevel [Byte0]: 37
8683 06:52:56.061793 [Byte1]: 37
8684 06:52:56.061844
8685 06:52:56.061894 Set Vref, RX VrefLevel [Byte0]: 38
8686 06:52:56.061945 [Byte1]: 38
8687 06:52:56.061996
8688 06:52:56.062047 Set Vref, RX VrefLevel [Byte0]: 39
8689 06:52:56.062098 [Byte1]: 39
8690 06:52:56.062149
8691 06:52:56.062200 Set Vref, RX VrefLevel [Byte0]: 40
8692 06:52:56.062251 [Byte1]: 40
8693 06:52:56.062302
8694 06:52:56.062352 Set Vref, RX VrefLevel [Byte0]: 41
8695 06:52:56.062412 [Byte1]: 41
8696 06:52:56.062465
8697 06:52:56.062515 Set Vref, RX VrefLevel [Byte0]: 42
8698 06:52:56.062566 [Byte1]: 42
8699 06:52:56.062617
8700 06:52:56.062668 Set Vref, RX VrefLevel [Byte0]: 43
8701 06:52:56.062719 [Byte1]: 43
8702 06:52:56.062770
8703 06:52:56.062821 Set Vref, RX VrefLevel [Byte0]: 44
8704 06:52:56.062872 [Byte1]: 44
8705 06:52:56.062923
8706 06:52:56.062973 Set Vref, RX VrefLevel [Byte0]: 45
8707 06:52:56.063024 [Byte1]: 45
8708 06:52:56.063075
8709 06:52:56.063126 Set Vref, RX VrefLevel [Byte0]: 46
8710 06:52:56.063178 [Byte1]: 46
8711 06:52:56.063229
8712 06:52:56.063279 Set Vref, RX VrefLevel [Byte0]: 47
8713 06:52:56.063330 [Byte1]: 47
8714 06:52:56.063381
8715 06:52:56.063432 Set Vref, RX VrefLevel [Byte0]: 48
8716 06:52:56.063483 [Byte1]: 48
8717 06:52:56.063535
8718 06:52:56.063585 Set Vref, RX VrefLevel [Byte0]: 49
8719 06:52:56.063637 [Byte1]: 49
8720 06:52:56.063689
8721 06:52:56.063739 Set Vref, RX VrefLevel [Byte0]: 50
8722 06:52:56.063790 [Byte1]: 50
8723 06:52:56.063841
8724 06:52:56.063891 Set Vref, RX VrefLevel [Byte0]: 51
8725 06:52:56.063943 [Byte1]: 51
8726 06:52:56.063994
8727 06:52:56.064045 Set Vref, RX VrefLevel [Byte0]: 52
8728 06:52:56.064096 [Byte1]: 52
8729 06:52:56.064147
8730 06:52:56.064198 Set Vref, RX VrefLevel [Byte0]: 53
8731 06:52:56.064249 [Byte1]: 53
8732 06:52:56.064299
8733 06:52:56.064350 Set Vref, RX VrefLevel [Byte0]: 54
8734 06:52:56.064401 [Byte1]: 54
8735 06:52:56.064452
8736 06:52:56.064503 Set Vref, RX VrefLevel [Byte0]: 55
8737 06:52:56.064554 [Byte1]: 55
8738 06:52:56.064605
8739 06:52:56.064655 Set Vref, RX VrefLevel [Byte0]: 56
8740 06:52:56.064706 [Byte1]: 56
8741 06:52:56.064757
8742 06:52:56.064808 Set Vref, RX VrefLevel [Byte0]: 57
8743 06:52:56.064859 [Byte1]: 57
8744 06:52:56.064910
8745 06:52:56.064961 Set Vref, RX VrefLevel [Byte0]: 58
8746 06:52:56.065012 [Byte1]: 58
8747 06:52:56.065062
8748 06:52:56.065113 Set Vref, RX VrefLevel [Byte0]: 59
8749 06:52:56.065163 [Byte1]: 59
8750 06:52:56.065215
8751 06:52:56.065265 Set Vref, RX VrefLevel [Byte0]: 60
8752 06:52:56.065316 [Byte1]: 60
8753 06:52:56.065367
8754 06:52:56.065417 Set Vref, RX VrefLevel [Byte0]: 61
8755 06:52:56.065469 [Byte1]: 61
8756 06:52:56.065520
8757 06:52:56.065570 Set Vref, RX VrefLevel [Byte0]: 62
8758 06:52:56.065621 [Byte1]: 62
8759 06:52:56.065671
8760 06:52:56.065722 Set Vref, RX VrefLevel [Byte0]: 63
8761 06:52:56.065774 [Byte1]: 63
8762 06:52:56.065825
8763 06:52:56.065876 Set Vref, RX VrefLevel [Byte0]: 64
8764 06:52:56.065927 [Byte1]: 64
8765 06:52:56.065977
8766 06:52:56.066028 Set Vref, RX VrefLevel [Byte0]: 65
8767 06:52:56.066079 [Byte1]: 65
8768 06:52:56.066130
8769 06:52:56.066181 Set Vref, RX VrefLevel [Byte0]: 66
8770 06:52:56.066231 [Byte1]: 66
8771 06:52:56.066282
8772 06:52:56.066332 Set Vref, RX VrefLevel [Byte0]: 67
8773 06:52:56.066382 [Byte1]: 67
8774 06:52:56.066438
8775 06:52:56.066488 Set Vref, RX VrefLevel [Byte0]: 68
8776 06:52:56.066539 [Byte1]: 68
8777 06:52:56.066590
8778 06:52:56.066641 Set Vref, RX VrefLevel [Byte0]: 69
8779 06:52:56.066692 [Byte1]: 69
8780 06:52:56.066743
8781 06:52:56.066793 Set Vref, RX VrefLevel [Byte0]: 70
8782 06:52:56.066844 [Byte1]: 70
8783 06:52:56.066896
8784 06:52:56.066946 Set Vref, RX VrefLevel [Byte0]: 71
8785 06:52:56.066998 [Byte1]: 71
8786 06:52:56.067049
8787 06:52:56.067100 Set Vref, RX VrefLevel [Byte0]: 72
8788 06:52:56.067152 [Byte1]: 72
8789 06:52:56.067203
8790 06:52:56.067254 Set Vref, RX VrefLevel [Byte0]: 73
8791 06:52:56.067305 [Byte1]: 73
8792 06:52:56.067356
8793 06:52:56.067406 Final RX Vref Byte 0 = 62 to rank0
8794 06:52:56.067458 Final RX Vref Byte 1 = 57 to rank0
8795 06:52:56.067702 Final RX Vref Byte 0 = 62 to rank1
8796 06:52:56.067791 Final RX Vref Byte 1 = 57 to rank1==
8797 06:52:56.067898 Dram Type= 6, Freq= 0, CH_1, rank 0
8798 06:52:56.068003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8799 06:52:56.068108 ==
8800 06:52:56.068204 DQS Delay:
8801 06:52:56.068293 DQS0 = 0, DQS1 = 0
8802 06:52:56.068361 DQM Delay:
8803 06:52:56.068415 DQM0 = 132, DQM1 = 124
8804 06:52:56.068468 DQ Delay:
8805 06:52:56.068519 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =132
8806 06:52:56.068571 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8807 06:52:56.068623 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8808 06:52:56.068674 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =132
8809 06:52:56.068725
8810 06:52:56.068775
8811 06:52:56.068826
8812 06:52:56.068876 [DramC_TX_OE_Calibration] TA2
8813 06:52:56.068927 Original DQ_B0 (3 6) =30, OEN = 27
8814 06:52:56.068978 Original DQ_B1 (3 6) =30, OEN = 27
8815 06:52:56.069029 24, 0x0, End_B0=24 End_B1=24
8816 06:52:56.069081 25, 0x0, End_B0=25 End_B1=25
8817 06:52:56.069133 26, 0x0, End_B0=26 End_B1=26
8818 06:52:56.069184 27, 0x0, End_B0=27 End_B1=27
8819 06:52:56.069236 28, 0x0, End_B0=28 End_B1=28
8820 06:52:56.069288 29, 0x0, End_B0=29 End_B1=29
8821 06:52:56.069340 30, 0x0, End_B0=30 End_B1=30
8822 06:52:56.069391 31, 0x4141, End_B0=30 End_B1=30
8823 06:52:56.069443 Byte0 end_step=30 best_step=27
8824 06:52:56.069494 Byte1 end_step=30 best_step=27
8825 06:52:56.069544 Byte0 TX OE(2T, 0.5T) = (3, 3)
8826 06:52:56.069595 Byte1 TX OE(2T, 0.5T) = (3, 3)
8827 06:52:56.069646
8828 06:52:56.069696
8829 06:52:56.069747 [DQSOSCAuto] RK0, (LSB)MR18= 0x1701, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8830 06:52:56.069799 CH1 RK0: MR19=303, MR18=1701
8831 06:52:56.069849 CH1_RK0: MR19=0x303, MR18=0x1701, DQSOSC=398, MR23=63, INC=23, DEC=15
8832 06:52:56.069901
8833 06:52:56.069952 ----->DramcWriteLeveling(PI) begin...
8834 06:52:56.070004 ==
8835 06:52:56.070055 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 06:52:56.070105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 06:52:56.070157 ==
8838 06:52:56.070207 Write leveling (Byte 0): 24 => 24
8839 06:52:56.070258 Write leveling (Byte 1): 27 => 27
8840 06:52:56.070309 DramcWriteLeveling(PI) end<-----
8841 06:52:56.070360
8842 06:52:56.070417 ==
8843 06:52:56.070468 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 06:52:56.070521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 06:52:56.070572 ==
8846 06:52:56.070623 [Gating] SW mode calibration
8847 06:52:56.070674 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8848 06:52:56.070726 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8849 06:52:56.070777 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 06:52:56.070828 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 06:52:56.070879 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
8852 06:52:56.070930 1 4 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
8853 06:52:56.070981 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 06:52:56.071032 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8855 06:52:56.071083 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8856 06:52:56.071134 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8857 06:52:56.071184 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8858 06:52:56.071235 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8859 06:52:56.071286 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
8860 06:52:56.071337 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8861 06:52:56.071388 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8862 06:52:56.071439 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 06:52:56.071490 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 06:52:56.071541 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 06:52:56.071592 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 06:52:56.071643 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 06:52:56.071694 1 6 8 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (0 0)
8868 06:52:56.071745 1 6 12 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
8869 06:52:56.071796 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 06:52:56.071847 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 06:52:56.071897 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 06:52:56.071949 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 06:52:56.072000 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 06:52:56.072050 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8875 06:52:56.072101 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8876 06:52:56.072152 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8877 06:52:56.072203 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8878 06:52:56.072255 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 06:52:56.072306 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 06:52:56.072357 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 06:52:56.072408 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 06:52:56.072458 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 06:52:56.072509 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 06:52:56.072560 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 06:52:56.072611 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 06:52:56.072662 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 06:52:56.072713 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 06:52:56.072764 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 06:52:56.072814 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 06:52:56.072865 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8891 06:52:56.072916 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8892 06:52:56.072967 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8893 06:52:56.073017 Total UI for P1: 0, mck2ui 16
8894 06:52:56.073069 best dqsien dly found for B0: ( 1, 9, 6)
8895 06:52:56.073120 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8896 06:52:56.073170 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 06:52:56.073221 Total UI for P1: 0, mck2ui 16
8898 06:52:56.073273 best dqsien dly found for B1: ( 1, 9, 14)
8899 06:52:56.073517 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8900 06:52:56.073608 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8901 06:52:56.073712
8902 06:52:56.073817 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8903 06:52:56.073923 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8904 06:52:56.074020 [Gating] SW calibration Done
8905 06:52:56.074108 ==
8906 06:52:56.074177 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 06:52:56.074230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 06:52:56.074283 ==
8909 06:52:56.074334 RX Vref Scan: 0
8910 06:52:56.074385
8911 06:52:56.074442 RX Vref 0 -> 0, step: 1
8912 06:52:56.074493
8913 06:52:56.074544 RX Delay 0 -> 252, step: 8
8914 06:52:56.074595 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8915 06:52:56.074648 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8916 06:52:56.074699 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8917 06:52:56.074750 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8918 06:52:56.074800 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8919 06:52:56.074851 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8920 06:52:56.074902 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8921 06:52:56.074953 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8922 06:52:56.075004 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8923 06:52:56.075054 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8924 06:52:56.075105 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8925 06:52:56.075156 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8926 06:52:56.075206 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8927 06:52:56.075257 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8928 06:52:56.075308 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8929 06:52:56.075360 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8930 06:52:56.075410 ==
8931 06:52:56.075461 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 06:52:56.075515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 06:52:56.075567 ==
8934 06:52:56.075617 DQS Delay:
8935 06:52:56.075668 DQS0 = 0, DQS1 = 0
8936 06:52:56.075719 DQM Delay:
8937 06:52:56.075770 DQM0 = 132, DQM1 = 128
8938 06:52:56.075821 DQ Delay:
8939 06:52:56.075872 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8940 06:52:56.075923 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8941 06:52:56.075974 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8942 06:52:56.076025 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8943 06:52:56.076076
8944 06:52:56.076126
8945 06:52:56.076177 ==
8946 06:52:56.076228 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 06:52:56.076279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 06:52:56.076330 ==
8949 06:52:56.076381
8950 06:52:56.076432
8951 06:52:56.076482 TX Vref Scan disable
8952 06:52:56.076533 == TX Byte 0 ==
8953 06:52:56.076583 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8954 06:52:56.076635 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8955 06:52:56.076687 == TX Byte 1 ==
8956 06:52:56.076738 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8957 06:52:56.076789 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8958 06:52:56.076840 ==
8959 06:52:56.076891 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 06:52:56.076942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 06:52:56.076994 ==
8962 06:52:56.077044
8963 06:52:56.077095 TX Vref early break, caculate TX vref
8964 06:52:56.077146 TX Vref=16, minBit 11, minWin=22, winSum=378
8965 06:52:56.077198 TX Vref=18, minBit 8, minWin=23, winSum=391
8966 06:52:56.077250 TX Vref=20, minBit 6, minWin=24, winSum=397
8967 06:52:56.077301 TX Vref=22, minBit 0, minWin=25, winSum=408
8968 06:52:56.077352 TX Vref=24, minBit 5, minWin=25, winSum=415
8969 06:52:56.077403 TX Vref=26, minBit 8, minWin=24, winSum=420
8970 06:52:56.077454 TX Vref=28, minBit 0, minWin=25, winSum=424
8971 06:52:56.077505 TX Vref=30, minBit 13, minWin=25, winSum=424
8972 06:52:56.077556 TX Vref=32, minBit 0, minWin=24, winSum=415
8973 06:52:56.077607 TX Vref=34, minBit 0, minWin=24, winSum=409
8974 06:52:56.077659 TX Vref=36, minBit 0, minWin=23, winSum=397
8975 06:52:56.077710 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8976 06:52:56.077762
8977 06:52:56.077813 Final TX Range 0 Vref 28
8978 06:52:56.077865
8979 06:52:56.077916 ==
8980 06:52:56.077966 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 06:52:56.078017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 06:52:56.078069 ==
8983 06:52:56.078120
8984 06:52:56.078170
8985 06:52:56.078220 TX Vref Scan disable
8986 06:52:56.078271 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8987 06:52:56.078323 == TX Byte 0 ==
8988 06:52:56.078374 u2DelayCellOfst[0]=17 cells (5 PI)
8989 06:52:56.078433 u2DelayCellOfst[1]=14 cells (4 PI)
8990 06:52:56.078484 u2DelayCellOfst[2]=0 cells (0 PI)
8991 06:52:56.078535 u2DelayCellOfst[3]=7 cells (2 PI)
8992 06:52:56.078585 u2DelayCellOfst[4]=10 cells (3 PI)
8993 06:52:56.078636 u2DelayCellOfst[5]=21 cells (6 PI)
8994 06:52:56.534286 u2DelayCellOfst[6]=17 cells (5 PI)
8995 06:52:56.534847 u2DelayCellOfst[7]=7 cells (2 PI)
8996 06:52:56.535277 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8997 06:52:56.535627 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8998 06:52:56.535953 == TX Byte 1 ==
8999 06:52:56.536272 u2DelayCellOfst[8]=0 cells (0 PI)
9000 06:52:56.536581 u2DelayCellOfst[9]=7 cells (2 PI)
9001 06:52:56.536883 u2DelayCellOfst[10]=14 cells (4 PI)
9002 06:52:56.537340 u2DelayCellOfst[11]=10 cells (3 PI)
9003 06:52:56.537787 u2DelayCellOfst[12]=17 cells (5 PI)
9004 06:52:56.538103 u2DelayCellOfst[13]=17 cells (5 PI)
9005 06:52:56.538448 u2DelayCellOfst[14]=21 cells (6 PI)
9006 06:52:56.538783 u2DelayCellOfst[15]=17 cells (5 PI)
9007 06:52:56.539082 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9008 06:52:56.539379 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9009 06:52:56.539676 DramC Write-DBI on
9010 06:52:56.539973 ==
9011 06:52:56.540270 Dram Type= 6, Freq= 0, CH_1, rank 1
9012 06:52:56.540566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9013 06:52:56.540862 ==
9014 06:52:56.541158
9015 06:52:56.541447
9016 06:52:56.541735 TX Vref Scan disable
9017 06:52:56.542028 == TX Byte 0 ==
9018 06:52:56.542318 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9019 06:52:56.542662 == TX Byte 1 ==
9020 06:52:56.542957 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9021 06:52:56.543260 DramC Write-DBI off
9022 06:52:56.543554
9023 06:52:56.543847 [DATLAT]
9024 06:52:56.544138 Freq=1600, CH1 RK1
9025 06:52:56.544432
9026 06:52:56.544791 DATLAT Default: 0xf
9027 06:52:56.545092 0, 0xFFFF, sum = 0
9028 06:52:56.545393 1, 0xFFFF, sum = 0
9029 06:52:56.545690 2, 0xFFFF, sum = 0
9030 06:52:56.545986 3, 0xFFFF, sum = 0
9031 06:52:56.546283 4, 0xFFFF, sum = 0
9032 06:52:56.546738 5, 0xFFFF, sum = 0
9033 06:52:56.547179 6, 0xFFFF, sum = 0
9034 06:52:56.547486 7, 0xFFFF, sum = 0
9035 06:52:56.547784 8, 0xFFFF, sum = 0
9036 06:52:56.548080 9, 0xFFFF, sum = 0
9037 06:52:56.548375 10, 0xFFFF, sum = 0
9038 06:52:56.548672 11, 0xFFFF, sum = 0
9039 06:52:56.549368 12, 0xFFFF, sum = 0
9040 06:52:56.549728 13, 0xFFFF, sum = 0
9041 06:52:56.550037 14, 0x0, sum = 1
9042 06:52:56.550339 15, 0x0, sum = 2
9043 06:52:56.550675 16, 0x0, sum = 3
9044 06:52:56.550974 17, 0x0, sum = 4
9045 06:52:56.551269 best_step = 15
9046 06:52:56.551562
9047 06:52:56.551851 ==
9048 06:52:56.552144 Dram Type= 6, Freq= 0, CH_1, rank 1
9049 06:52:56.552435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9050 06:52:56.552727 ==
9051 06:52:56.553018 RX Vref Scan: 0
9052 06:52:56.553308
9053 06:52:56.553597 RX Vref 0 -> 0, step: 1
9054 06:52:56.553885
9055 06:52:56.554172 RX Delay 11 -> 252, step: 4
9056 06:52:56.554482 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
9057 06:52:56.554777 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
9058 06:52:56.555068 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
9059 06:52:56.555358 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
9060 06:52:56.555646 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
9061 06:52:56.555935 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9062 06:52:56.556225 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9063 06:52:56.556513 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
9064 06:52:56.556803 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
9065 06:52:56.557094 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
9066 06:52:56.557383 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
9067 06:52:56.557674 iDelay=191, Bit 11, Center 118 (63 ~ 174) 112
9068 06:52:56.557965 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9069 06:52:56.558255 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
9070 06:52:56.558631 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
9071 06:52:56.558934 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
9072 06:52:56.559227 ==
9073 06:52:56.559519 Dram Type= 6, Freq= 0, CH_1, rank 1
9074 06:52:56.559805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9075 06:52:56.560072 ==
9076 06:52:56.560338 DQS Delay:
9077 06:52:56.560601 DQS0 = 0, DQS1 = 0
9078 06:52:56.560864 DQM Delay:
9079 06:52:56.561128 DQM0 = 130, DQM1 = 125
9080 06:52:56.561391 DQ Delay:
9081 06:52:56.561651 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =128
9082 06:52:56.561917 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9083 06:52:56.562181 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
9084 06:52:56.562515 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9085 06:52:56.562797
9086 06:52:56.563061
9087 06:52:56.563324
9088 06:52:56.563598 [DramC_TX_OE_Calibration] TA2
9089 06:52:56.563788 Original DQ_B0 (3 6) =30, OEN = 27
9090 06:52:56.563977 Original DQ_B1 (3 6) =30, OEN = 27
9091 06:52:56.564168 24, 0x0, End_B0=24 End_B1=24
9092 06:52:56.564361 25, 0x0, End_B0=25 End_B1=25
9093 06:52:56.564593 26, 0x0, End_B0=26 End_B1=26
9094 06:52:56.564791 27, 0x0, End_B0=27 End_B1=27
9095 06:52:56.564984 28, 0x0, End_B0=28 End_B1=28
9096 06:52:56.565175 29, 0x0, End_B0=29 End_B1=29
9097 06:52:56.565366 30, 0x0, End_B0=30 End_B1=30
9098 06:52:56.565556 31, 0x4141, End_B0=30 End_B1=30
9099 06:52:56.565751 Byte0 end_step=30 best_step=27
9100 06:52:56.565941 Byte1 end_step=30 best_step=27
9101 06:52:56.566131 Byte0 TX OE(2T, 0.5T) = (3, 3)
9102 06:52:56.566323 Byte1 TX OE(2T, 0.5T) = (3, 3)
9103 06:52:56.566548
9104 06:52:56.566743
9105 06:52:56.566934 [DQSOSCAuto] RK1, (LSB)MR18= 0x1217, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 400 ps
9106 06:52:56.567132 CH1 RK1: MR19=303, MR18=1217
9107 06:52:56.567324 CH1_RK1: MR19=0x303, MR18=0x1217, DQSOSC=398, MR23=63, INC=23, DEC=15
9108 06:52:56.567516 [RxdqsGatingPostProcess] freq 1600
9109 06:52:56.567706 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9110 06:52:56.567897 best DQS0 dly(2T, 0.5T) = (1, 1)
9111 06:52:56.568088 best DQS1 dly(2T, 0.5T) = (1, 1)
9112 06:52:56.568279 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9113 06:52:56.568467 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9114 06:52:56.568647 best DQS0 dly(2T, 0.5T) = (1, 1)
9115 06:52:56.568791 best DQS1 dly(2T, 0.5T) = (1, 1)
9116 06:52:56.568936 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9117 06:52:56.569079 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9118 06:52:56.569221 Pre-setting of DQS Precalculation
9119 06:52:56.569364 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9120 06:52:56.569516 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9121 06:52:56.569663 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9122 06:52:56.569806
9123 06:52:56.569948
9124 06:52:56.570090 [Calibration Summary] 3200 Mbps
9125 06:52:56.570235 CH 0, Rank 0
9126 06:52:56.570379 SW Impedance : PASS
9127 06:52:56.570535 DUTY Scan : NO K
9128 06:52:56.570678 ZQ Calibration : PASS
9129 06:52:56.570820 Jitter Meter : NO K
9130 06:52:56.570962 CBT Training : PASS
9131 06:52:56.571106 Write leveling : PASS
9132 06:52:56.571247 RX DQS gating : PASS
9133 06:52:56.571390 RX DQ/DQS(RDDQC) : PASS
9134 06:52:56.571533 TX DQ/DQS : PASS
9135 06:52:56.571677 RX DATLAT : PASS
9136 06:52:56.571820 RX DQ/DQS(Engine): PASS
9137 06:52:56.571962 TX OE : PASS
9138 06:52:56.572104 All Pass.
9139 06:52:56.572246
9140 06:52:56.572387 CH 0, Rank 1
9141 06:52:56.572529 SW Impedance : PASS
9142 06:52:56.572672 DUTY Scan : NO K
9143 06:52:56.572812 ZQ Calibration : PASS
9144 06:52:56.572954 Jitter Meter : NO K
9145 06:52:56.573095 CBT Training : PASS
9146 06:52:56.573237 Write leveling : PASS
9147 06:52:56.573378 RX DQS gating : PASS
9148 06:52:56.573519 RX DQ/DQS(RDDQC) : PASS
9149 06:52:56.573660 TX DQ/DQS : PASS
9150 06:52:56.573775 RX DATLAT : PASS
9151 06:52:56.573889 RX DQ/DQS(Engine): PASS
9152 06:52:56.574002 TX OE : PASS
9153 06:52:56.574116 All Pass.
9154 06:52:56.574228
9155 06:52:56.574341 CH 1, Rank 0
9156 06:52:56.574465 SW Impedance : PASS
9157 06:52:56.574580 DUTY Scan : NO K
9158 06:52:56.574695 ZQ Calibration : PASS
9159 06:52:56.574809 Jitter Meter : NO K
9160 06:52:56.574923 CBT Training : PASS
9161 06:52:56.575038 Write leveling : PASS
9162 06:52:56.575151 RX DQS gating : PASS
9163 06:52:56.575266 RX DQ/DQS(RDDQC) : PASS
9164 06:52:56.575380 TX DQ/DQS : PASS
9165 06:52:56.575493 RX DATLAT : PASS
9166 06:52:56.575608 RX DQ/DQS(Engine): PASS
9167 06:52:56.575722 TX OE : PASS
9168 06:52:56.575838 All Pass.
9169 06:52:56.575952
9170 06:52:56.576065 CH 1, Rank 1
9171 06:52:56.576179 SW Impedance : PASS
9172 06:52:56.576314 DUTY Scan : NO K
9173 06:52:56.576440 ZQ Calibration : PASS
9174 06:52:56.576560 Jitter Meter : NO K
9175 06:52:56.576676 CBT Training : PASS
9176 06:52:56.576793 Write leveling : PASS
9177 06:52:56.576907 RX DQS gating : PASS
9178 06:52:56.577022 RX DQ/DQS(RDDQC) : PASS
9179 06:52:56.577136 TX DQ/DQS : PASS
9180 06:52:56.577252 RX DATLAT : PASS
9181 06:52:56.577366 RX DQ/DQS(Engine): PASS
9182 06:52:56.577480 TX OE : PASS
9183 06:52:56.577595 All Pass.
9184 06:52:56.577709
9185 06:52:56.577823 DramC Write-DBI on
9186 06:52:56.578187 PER_BANK_REFRESH: Hybrid Mode
9187 06:52:56.578455 TX_TRACKING: ON
9188 06:52:56.578710 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9189 06:52:56.578919 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9190 06:52:56.579126 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9191 06:52:56.579330 [FAST_K] Save calibration result to emmc
9192 06:52:56.579531 sync common calibartion params.
9193 06:52:56.579731 sync cbt_mode0:1, 1:1
9194 06:52:56.579929 dram_init: ddr_geometry: 2
9195 06:52:56.580097 dram_init: ddr_geometry: 2
9196 06:52:56.580209 dram_init: ddr_geometry: 2
9197 06:52:56.580320 0:dram_rank_size:100000000
9198 06:52:56.580426 1:dram_rank_size:100000000
9199 06:52:56.580526 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9200 06:52:56.580624 DFS_SHUFFLE_HW_MODE: ON
9201 06:52:56.580722 dramc_set_vcore_voltage set vcore to 725000
9202 06:52:56.580818 Read voltage for 1600, 0
9203 06:52:56.580914 Vio18 = 0
9204 06:52:56.581010 Vcore = 725000
9205 06:52:56.581127 Vdram = 0
9206 06:52:56.581228 Vddq = 0
9207 06:52:56.581323 Vmddr = 0
9208 06:52:56.581418 switch to 3200 Mbps bootup
9209 06:52:56.581514 [DramcRunTimeConfig]
9210 06:52:56.581610 PHYPLL
9211 06:52:56.581704 DPM_CONTROL_AFTERK: ON
9212 06:52:56.581799 PER_BANK_REFRESH: ON
9213 06:52:56.581894 REFRESH_OVERHEAD_REDUCTION: ON
9214 06:52:56.581989 CMD_PICG_NEW_MODE: OFF
9215 06:52:56.582083 XRTWTW_NEW_MODE: ON
9216 06:52:56.582178 XRTRTR_NEW_MODE: ON
9217 06:52:56.582295 TX_TRACKING: ON
9218 06:52:56.582461 RDSEL_TRACKING: OFF
9219 06:52:56.582563 DQS Precalculation for DVFS: ON
9220 06:52:56.582659 RX_TRACKING: OFF
9221 06:52:56.582756 HW_GATING DBG: ON
9222 06:52:56.582852 ZQCS_ENABLE_LP4: ON
9223 06:52:56.582947 RX_PICG_NEW_MODE: ON
9224 06:52:56.583043 TX_PICG_NEW_MODE: ON
9225 06:52:56.583139 ENABLE_RX_DCM_DPHY: ON
9226 06:52:56.583236 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9227 06:52:56.583332 DUMMY_READ_FOR_TRACKING: OFF
9228 06:52:56.583427 !!! SPM_CONTROL_AFTERK: OFF
9229 06:52:56.583558 !!! SPM could not control APHY
9230 06:52:56.583643 IMPEDANCE_TRACKING: ON
9231 06:52:56.583726 TEMP_SENSOR: ON
9232 06:52:56.583808 HW_SAVE_FOR_SR: OFF
9233 06:52:56.583890 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9234 06:52:56.583972 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9235 06:52:56.584054 Read ODT Tracking: ON
9236 06:52:56.584136 Refresh Rate DeBounce: ON
9237 06:52:56.584218 DFS_NO_QUEUE_FLUSH: ON
9238 06:52:56.584320 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9239 06:52:56.584404 ENABLE_DFS_RUNTIME_MRW: OFF
9240 06:52:56.584486 DDR_RESERVE_NEW_MODE: ON
9241 06:52:56.584568 MR_CBT_SWITCH_FREQ: ON
9242 06:52:56.584649 =========================
9243 06:52:56.584732 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9244 06:52:56.584815 dram_init: ddr_geometry: 2
9245 06:52:56.584897 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9246 06:52:56.584981 dram_init: dram init end (result: 0)
9247 06:52:56.585063 DRAM-K: Full calibration passed in 24604 msecs
9248 06:52:56.585145 MRC: failed to locate region type 0.
9249 06:52:56.585227 DRAM rank0 size:0x100000000,
9250 06:52:56.585309 DRAM rank1 size=0x100000000
9251 06:52:56.585391 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9252 06:52:56.585475 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9253 06:52:56.585558 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9254 06:52:56.585642 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9255 06:52:56.585725 DRAM rank0 size:0x100000000,
9256 06:52:56.585808 DRAM rank1 size=0x100000000
9257 06:52:56.585890 CBMEM:
9258 06:52:56.585972 IMD: root @ 0xfffff000 254 entries.
9259 06:52:56.586055 IMD: root @ 0xffffec00 62 entries.
9260 06:52:56.586138 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9261 06:52:56.586221 WARNING: RO_VPD is uninitialized or empty.
9262 06:52:56.586351 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9263 06:52:56.586464 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9264 06:52:56.586550 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9265 06:52:56.586633 BS: romstage times (exec / console): total (unknown) / 24103 ms
9266 06:52:56.586716
9267 06:52:56.586798
9268 06:52:56.586880 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9269 06:52:56.586965 ARM64: Exception handlers installed.
9270 06:52:56.587049 ARM64: Testing exception
9271 06:52:56.587131 ARM64: Done test exception
9272 06:52:56.587213 Enumerating buses...
9273 06:52:56.587294 Show all devs... Before device enumeration.
9274 06:52:56.587377 Root Device: enabled 1
9275 06:52:56.587459 CPU_CLUSTER: 0: enabled 1
9276 06:52:56.587541 CPU: 00: enabled 1
9277 06:52:56.587622 Compare with tree...
9278 06:52:56.587704 Root Device: enabled 1
9279 06:52:56.587786 CPU_CLUSTER: 0: enabled 1
9280 06:52:56.587868 CPU: 00: enabled 1
9281 06:52:56.587950 Root Device scanning...
9282 06:52:56.588032 scan_static_bus for Root Device
9283 06:52:56.588114 CPU_CLUSTER: 0 enabled
9284 06:52:56.588196 scan_static_bus for Root Device done
9285 06:52:56.588308 scan_bus: bus Root Device finished in 8 msecs
9286 06:52:56.588444 done
9287 06:52:56.588532 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9288 06:52:56.588621 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9289 06:52:56.588695 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9290 06:52:56.588769 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9291 06:52:56.588842 Allocating resources...
9292 06:52:56.588914 Reading resources...
9293 06:52:56.588986 Root Device read_resources bus 0 link: 0
9294 06:52:56.589063 DRAM rank0 size:0x100000000,
9295 06:52:56.589135 DRAM rank1 size=0x100000000
9296 06:52:56.589208 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9297 06:52:56.589280 CPU: 00 missing read_resources
9298 06:52:56.589402 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9299 06:52:56.589515 Root Device read_resources bus 0 link: 0 done
9300 06:52:56.589622 Done reading resources.
9301 06:52:56.589725 Show resources in subtree (Root Device)...After reading.
9302 06:52:56.590047 Root Device child on link 0 CPU_CLUSTER: 0
9303 06:52:56.590205 CPU_CLUSTER: 0 child on link 0 CPU: 00
9304 06:52:56.590357 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9305 06:52:56.590527 CPU: 00
9306 06:52:56.590656 Root Device assign_resources, bus 0 link: 0
9307 06:52:56.590776 CPU_CLUSTER: 0 missing set_resources
9308 06:52:56.590894 Root Device assign_resources, bus 0 link: 0 done
9309 06:52:56.591010 Done setting resources.
9310 06:52:56.591125 Show resources in subtree (Root Device)...After assigning values.
9311 06:52:56.591240 Root Device child on link 0 CPU_CLUSTER: 0
9312 06:52:56.591355 CPU_CLUSTER: 0 child on link 0 CPU: 00
9313 06:52:56.591470 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9314 06:52:56.591585 CPU: 00
9315 06:52:56.591698 Done allocating resources.
9316 06:52:56.591813 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9317 06:52:56.591926 Enabling resources...
9318 06:52:56.592039 done.
9319 06:52:56.592152 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9320 06:52:56.592274 Initializing devices...
9321 06:52:56.592407 Root Device init
9322 06:52:56.592526 init hardware done!
9323 06:52:56.592640 0x00000018: ctrlr->caps
9324 06:52:56.592758 52.000 MHz: ctrlr->f_max
9325 06:52:56.592875 0.400 MHz: ctrlr->f_min
9326 06:52:56.592992 0x40ff8080: ctrlr->voltages
9327 06:52:56.593108 sclk: 390625
9328 06:52:56.593221 Bus Width = 1
9329 06:52:56.593333 sclk: 390625
9330 06:52:56.593445 Bus Width = 1
9331 06:52:56.593557 Early init status = 3
9332 06:52:56.593675 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9333 06:52:56.593777 in-header: 03 fc 00 00 01 00 00 00
9334 06:52:56.593877 in-data: 00
9335 06:52:56.593979 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9336 06:52:56.594080 in-header: 03 fd 00 00 00 00 00 00
9337 06:52:56.594180 in-data:
9338 06:52:56.594285 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9339 06:52:56.594392 in-header: 03 fc 00 00 01 00 00 00
9340 06:52:56.594475 in-data: 00
9341 06:52:56.594540 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9342 06:52:56.594606 in-header: 03 fd 00 00 00 00 00 00
9343 06:52:56.594670 in-data:
9344 06:52:56.594735 [SSUSB] Setting up USB HOST controller...
9345 06:52:56.594800 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9346 06:52:56.594865 [SSUSB] phy power-on done.
9347 06:52:56.594930 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9348 06:52:56.594995 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9349 06:52:56.595060 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9350 06:52:56.595126 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9351 06:52:56.595191 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9352 06:52:56.595256 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9353 06:52:56.595322 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9354 06:52:56.595388 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9355 06:52:56.595453 SPM: binary array size = 0x9dc
9356 06:52:56.595518 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9357 06:52:56.595584 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9358 06:52:56.595649 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9359 06:52:56.595715 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9360 06:52:56.595779 configure_display: Starting display init
9361 06:52:56.595844 anx7625_power_on_init: Init interface.
9362 06:52:56.595908 anx7625_disable_pd_protocol: Disabled PD feature.
9363 06:52:56.595972 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9364 06:52:56.596036 anx7625_start_dp_work: Secure OCM version=00
9365 06:52:56.596100 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9366 06:52:56.596164 sp_tx_get_edid_block: EDID Block = 1
9367 06:52:56.596228 Extracted contents:
9368 06:52:56.596291 header: 00 ff ff ff ff ff ff 00
9369 06:52:56.596355 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9370 06:52:56.596432 version: 01 04
9371 06:52:56.596501 basic params: 95 1f 11 78 0a
9372 06:52:56.596566 chroma info: 76 90 94 55 54 90 27 21 50 54
9373 06:52:56.596630 established: 00 00 00
9374 06:52:56.596694 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9375 06:52:56.596758 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9376 06:52:56.596823 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 06:52:56.596886 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9378 06:52:56.596951 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9379 06:52:56.597015 extensions: 00
9380 06:52:56.597078 checksum: fb
9381 06:52:56.597141
9382 06:52:56.597204 Manufacturer: IVO Model 57d Serial Number 0
9383 06:52:56.597268 Made week 0 of 2020
9384 06:52:56.597332 EDID version: 1.4
9385 06:52:56.597395 Digital display
9386 06:52:56.597459 6 bits per primary color channel
9387 06:52:56.597524 DisplayPort interface
9388 06:52:56.597587 Maximum image size: 31 cm x 17 cm
9389 06:52:56.597651 Gamma: 220%
9390 06:52:56.597714 Check DPMS levels
9391 06:52:56.597778 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9392 06:52:56.597842 First detailed timing is preferred timing
9393 06:52:56.597906 Established timings supported:
9394 06:52:56.597970 Standard timings supported:
9395 06:52:56.598075 Detailed timings
9396 06:52:56.598177 Hex of detail: 383680a07038204018303c0035ae10000019
9397 06:52:56.598279 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9398 06:52:56.598382 0780 0798 07c8 0820 hborder 0
9399 06:52:56.598466 0438 043b 0447 0458 vborder 0
9400 06:52:56.598532 -hsync -vsync
9401 06:52:56.598606 Did detailed timing
9402 06:52:56.598663 Hex of detail: 000000000000000000000000000000000000
9403 06:52:56.598720 Manufacturer-specified data, tag 0
9404 06:52:56.598974 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9405 06:52:56.599040 ASCII string: InfoVision
9406 06:52:56.599099 Hex of detail: 000000fe00523134304e574635205248200a
9407 06:52:56.599157 ASCII string: R140NWF5 RH
9408 06:52:56.599215 Checksum
9409 06:52:56.599273 Checksum: 0xfb (valid)
9410 06:52:56.599330 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9411 06:52:56.599388 DSI data_rate: 832800000 bps
9412 06:52:56.599445 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9413 06:52:56.599503 anx7625_parse_edid: pixelclock(138800).
9414 06:52:56.599560 hactive(1920), hsync(48), hfp(24), hbp(88)
9415 06:52:56.599618 vactive(1080), vsync(12), vfp(3), vbp(17)
9416 06:52:56.599675 anx7625_dsi_config: config dsi.
9417 06:52:56.599733 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9418 06:52:56.599802 anx7625_dsi_config: success to config DSI
9419 06:52:56.599862 anx7625_dp_start: MIPI phy setup OK.
9420 06:52:56.599920 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9421 06:52:56.599977 mtk_ddp_mode_set invalid vrefresh 60
9422 06:52:56.600035 main_disp_path_setup
9423 06:52:56.600092 ovl_layer_smi_id_en
9424 06:52:56.600150 ovl_layer_smi_id_en
9425 06:52:56.600207 ccorr_config
9426 06:52:56.600264 aal_config
9427 06:52:56.600321 gamma_config
9428 06:52:56.600379 postmask_config
9429 06:52:56.600436 dither_config
9430 06:52:56.600493 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9431 06:52:56.600551 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9432 06:52:56.600610 Root Device init finished in 553 msecs
9433 06:52:56.600667 CPU_CLUSTER: 0 init
9434 06:52:56.600725 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9435 06:52:56.600785 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9436 06:52:56.600843 APU_MBOX 0x190000b0 = 0x10001
9437 06:52:56.600901 APU_MBOX 0x190001b0 = 0x10001
9438 06:52:56.600958 APU_MBOX 0x190005b0 = 0x10001
9439 06:52:56.601015 APU_MBOX 0x190006b0 = 0x10001
9440 06:52:56.601072 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9441 06:52:56.601131 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9442 06:52:56.601188 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9443 06:52:56.601246 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9444 06:52:56.601304 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9445 06:52:56.601362 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9446 06:52:56.601420 CPU_CLUSTER: 0 init finished in 81 msecs
9447 06:52:56.601477 Devices initialized
9448 06:52:56.601533 Show all devs... After init.
9449 06:52:56.601591 Root Device: enabled 1
9450 06:52:56.601647 CPU_CLUSTER: 0: enabled 1
9451 06:52:56.601704 CPU: 00: enabled 1
9452 06:52:56.601772 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9453 06:52:56.601867 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9454 06:52:56.601959 ELOG: NV offset 0x57f000 size 0x1000
9455 06:52:56.602050 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9456 06:52:56.602141 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9457 06:52:56.602233 ELOG: Event(17) added with size 13 at 2024-02-03 06:52:57 UTC
9458 06:52:56.602324 out: cmd=0x121: 03 db 21 01 00 00 00 00
9459 06:52:56.602419 in-header: 03 bd 00 00 2c 00 00 00
9460 06:52:56.602482 in-data: a2 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9461 06:52:56.602544 ELOG: Event(A1) added with size 10 at 2024-02-03 06:52:57 UTC
9462 06:52:56.602603 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9463 06:52:56.602662 ELOG: Event(A0) added with size 9 at 2024-02-03 06:52:57 UTC
9464 06:52:56.602720 elog_add_boot_reason: Logged dev mode boot
9465 06:52:56.602777 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9466 06:52:56.602836 Finalize devices...
9467 06:52:56.602894 Devices finalized
9468 06:52:56.602953 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9469 06:52:56.603010 Writing coreboot table at 0xffe64000
9470 06:52:56.603068 0. 000000000010a000-0000000000113fff: RAMSTAGE
9471 06:52:56.603125 1. 0000000040000000-00000000400fffff: RAM
9472 06:52:56.603182 2. 0000000040100000-000000004032afff: RAMSTAGE
9473 06:52:56.603240 3. 000000004032b000-00000000545fffff: RAM
9474 06:52:56.603298 4. 0000000054600000-000000005465ffff: BL31
9475 06:52:56.603355 5. 0000000054660000-00000000ffe63fff: RAM
9476 06:52:56.603413 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9477 06:52:56.603469 7. 0000000100000000-000000023fffffff: RAM
9478 06:52:56.603526 Passing 5 GPIOs to payload:
9479 06:52:56.603594 NAME | PORT | POLARITY | VALUE
9480 06:52:56.603647 EC in RW | 0x000000aa | low | undefined
9481 06:52:56.603699 EC interrupt | 0x00000005 | low | undefined
9482 06:52:56.603755 TPM interrupt | 0x000000ab | high | undefined
9483 06:52:56.603815 SD card detect | 0x00000011 | high | undefined
9484 06:52:56.603875 speaker enable | 0x00000093 | high | undefined
9485 06:52:56.603928 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9486 06:52:56.603981 in-header: 03 f9 00 00 02 00 00 00
9487 06:52:56.604034 in-data: 02 00
9488 06:52:56.604086 ADC[4]: Raw value=900590 ID=7
9489 06:52:56.604138 ADC[3]: Raw value=213336 ID=1
9490 06:52:56.604190 RAM Code: 0x71
9491 06:52:56.604241 ADC[6]: Raw value=74557 ID=0
9492 06:52:56.604293 ADC[5]: Raw value=212229 ID=1
9493 06:52:56.604345 SKU Code: 0x1
9494 06:52:56.604397 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b56e
9495 06:52:56.604450 coreboot table: 964 bytes.
9496 06:52:56.604502 IMD ROOT 0. 0xfffff000 0x00001000
9497 06:52:56.604554 IMD SMALL 1. 0xffffe000 0x00001000
9498 06:52:56.604606 RO MCACHE 2. 0xffffc000 0x00001104
9499 06:52:56.604852 CONSOLE 3. 0xfff7c000 0x00080000
9500 06:52:56.604911 FMAP 4. 0xfff7b000 0x00000452
9501 06:52:56.604965 TIME STAMP 5. 0xfff7a000 0x00000910
9502 06:52:56.605018 VBOOT WORK 6. 0xfff66000 0x00014000
9503 06:52:56.605070 RAMOOPS 7. 0xffe66000 0x00100000
9504 06:52:56.605122 COREBOOT 8. 0xffe64000 0x00002000
9505 06:52:56.605175 IMD small region:
9506 06:52:56.605227 IMD ROOT 0. 0xffffec00 0x00000400
9507 06:52:56.605279 VPD 1. 0xffffeb80 0x0000006c
9508 06:52:56.605331 MMC STATUS 2. 0xffffeb60 0x00000004
9509 06:52:56.605383 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9510 06:52:56.605435 Probing TPM: done!
9511 06:52:56.605487 Connected to device vid:did:rid of 1ae0:0028:00
9512 06:52:56.605539 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9513 06:52:56.605592 Initialized TPM device CR50 revision 0
9514 06:52:56.605643 Checking cr50 for pending updates
9515 06:52:56.605695 Reading cr50 TPM mode
9516 06:52:56.605747 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9517 06:52:56.605800 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9518 06:52:56.605853 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9519 06:52:56.605905 Checking segment from ROM address 0x40100000
9520 06:52:56.605957 Checking segment from ROM address 0x4010001c
9521 06:52:56.606010 Loading segment from ROM address 0x40100000
9522 06:52:56.606061 code (compression=0)
9523 06:52:56.606113 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9524 06:52:56.606166 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9525 06:52:56.606219 it's not compressed!
9526 06:52:56.606271 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9527 06:52:56.606323 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9528 06:52:56.606375 Loading segment from ROM address 0x4010001c
9529 06:52:56.606443 Entry Point 0x80000000
9530 06:52:56.606496 Loaded segments
9531 06:52:56.606549 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9532 06:52:56.606601 Jumping to boot code at 0x80000000(0xffe64000)
9533 06:52:56.606653 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9534 06:52:56.606706 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9535 06:52:56.606759 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9536 06:52:56.606812 Checking segment from ROM address 0x40100000
9537 06:52:56.606864 Checking segment from ROM address 0x4010001c
9538 06:52:56.606916 Loading segment from ROM address 0x40100000
9539 06:52:56.606969 code (compression=1)
9540 06:52:56.607022 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9541 06:52:56.607075 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9542 06:52:56.607127 using LZMA
9543 06:52:56.607179 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9544 06:52:56.607232 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9545 06:52:56.607285 Loading segment from ROM address 0x4010001c
9546 06:52:56.607337 Entry Point 0x54601000
9547 06:52:56.607388 Loaded segments
9548 06:52:56.607440 NOTICE: MT8192 bl31_setup
9549 06:52:56.607492 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9550 06:52:56.607544 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9551 06:52:56.607597 WARNING: region 0:
9552 06:52:56.607649 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9553 06:52:56.607701 WARNING: region 1:
9554 06:52:56.607752 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9555 06:52:56.607804 WARNING: region 2:
9556 06:52:56.607856 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9557 06:52:56.607909 WARNING: region 3:
9558 06:52:56.607960 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9559 06:52:56.608013 WARNING: region 4:
9560 06:52:56.608064 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9561 06:52:56.608116 WARNING: region 5:
9562 06:52:56.608168 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9563 06:52:56.608219 WARNING: region 6:
9564 06:52:56.608270 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9565 06:52:56.608322 WARNING: region 7:
9566 06:52:56.608374 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9567 06:52:56.608426 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9568 06:52:56.608478 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9569 06:52:56.608530 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9570 06:52:56.608593 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9571 06:52:56.608643 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9572 06:52:56.608692 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9573 06:52:56.608742 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9574 06:52:56.608792 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9575 06:52:56.608844 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9576 06:52:56.608893 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9577 06:52:56.608943 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9578 06:52:56.608993 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9579 06:52:56.609043 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9580 06:52:56.609093 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9581 06:52:56.609143 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9582 06:52:56.609193 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9583 06:52:56.609243 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9584 06:52:56.609293 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9585 06:52:56.609343 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9586 06:52:56.609394 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9587 06:52:56.609633 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9588 06:52:56.609690 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9589 06:52:56.609742 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9590 06:52:56.609792 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9591 06:52:56.609843 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9592 06:52:56.609893 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9593 06:52:56.609943 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9594 06:52:56.609994 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9595 06:52:56.610043 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9596 06:52:56.610094 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9597 06:52:56.610144 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9598 06:52:56.610194 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9599 06:52:56.610244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9600 06:52:56.610294 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9601 06:52:56.610344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9602 06:52:56.610394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9603 06:52:56.610502 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9604 06:52:56.610552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9605 06:52:56.610602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9606 06:52:56.610652 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9607 06:52:56.610701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9608 06:52:56.610752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9609 06:52:56.610803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9610 06:52:56.610853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9611 06:52:56.610903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9612 06:52:56.610953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9613 06:52:56.611002 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9614 06:52:56.611052 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9615 06:52:56.611103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9616 06:52:56.611153 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9617 06:52:56.611203 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9618 06:52:56.611253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9619 06:52:56.611303 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9620 06:52:56.611353 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9621 06:52:56.611403 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9622 06:52:56.611453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9623 06:52:56.611503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9624 06:52:56.611553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9625 06:52:56.611603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9626 06:52:56.611654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9627 06:52:56.611705 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9628 06:52:56.611754 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9629 06:52:56.611805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9630 06:52:56.611855 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9631 06:52:56.611905 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9632 06:52:56.611955 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9633 06:52:56.612005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9634 06:52:56.612055 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9635 06:52:56.612105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9636 06:52:56.612154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9637 06:52:56.612204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9638 06:52:56.612255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9639 06:52:56.612305 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9640 06:52:56.612355 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9641 06:52:56.612406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9642 06:52:56.612456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9643 06:52:56.612506 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9644 06:52:56.612557 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9645 06:52:56.612606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9646 06:52:56.612656 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9647 06:52:56.612706 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9648 06:52:56.612756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9649 06:52:56.612806 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9650 06:52:56.612880 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9651 06:52:56.612949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9652 06:52:56.612999 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9653 06:52:56.613048 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9654 06:52:56.613099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9655 06:52:56.613148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9656 06:52:56.613198 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9657 06:52:56.613248 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9658 06:52:56.613297 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9659 06:52:56.613347 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9660 06:52:56.613397 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9661 06:52:56.613447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9662 06:52:56.613496 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9663 06:52:56.613735 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9664 06:52:56.613791 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9665 06:52:56.613843 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9666 06:52:56.613893 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9667 06:52:56.613944 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9668 06:52:56.613994 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9669 06:52:56.614044 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9670 06:52:56.614094 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9671 06:52:56.614144 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9672 06:52:56.614194 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9673 06:52:56.614245 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9674 06:52:56.614296 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9675 06:52:56.614346 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9676 06:52:56.614405 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9677 06:52:56.614508 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9678 06:52:56.614558 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9679 06:52:56.614609 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9680 06:52:56.614659 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9681 06:52:56.614709 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9682 06:52:56.614759 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9683 06:52:56.614809 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9684 06:52:56.614859 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9685 06:52:56.614909 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9686 06:52:56.614959 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9687 06:52:56.615010 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9688 06:52:56.615060 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9689 06:52:56.615109 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9690 06:52:56.615159 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9691 06:52:56.615209 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9692 06:52:56.615260 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9693 06:52:56.615310 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9694 06:52:56.615360 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9695 06:52:56.615413 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9696 06:52:56.615464 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9697 06:52:56.615513 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9698 06:52:56.615563 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9699 06:52:56.615614 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9700 06:52:56.615663 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9701 06:52:56.615713 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9702 06:52:56.615763 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9703 06:52:56.615813 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9704 06:52:56.615864 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9705 06:52:56.615913 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9706 06:52:56.615964 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9707 06:52:56.616015 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9708 06:52:56.616065 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9709 06:52:56.616115 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9710 06:52:56.616165 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9711 06:52:56.616215 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9712 06:52:56.616265 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9713 06:52:56.616339 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9714 06:52:56.616404 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9715 06:52:56.616454 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9716 06:52:56.616504 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9717 06:52:56.616554 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9718 06:52:56.616604 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9719 06:52:56.616654 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9720 06:52:56.616705 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9721 06:52:56.616754 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9722 06:52:56.616804 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9723 06:52:56.616854 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9724 06:52:56.616904 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9725 06:52:56.616954 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9726 06:52:56.617004 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9727 06:52:56.617054 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9728 06:52:56.617104 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9729 06:52:56.617154 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9730 06:52:56.617204 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9731 06:52:56.617254 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9732 06:52:56.617305 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9733 06:52:56.617355 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9734 06:52:56.617417 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9735 06:52:56.617470 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9736 06:52:56.617520 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9737 06:52:56.617571 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9738 06:52:56.617621 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9739 06:52:56.617672 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9740 06:52:56.617911 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9741 06:52:56.617968 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9742 06:52:56.618019 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9743 06:52:56.618070 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9744 06:52:56.618121 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9745 06:52:56.618171 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9746 06:52:56.618222 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9747 06:52:56.618272 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9748 06:52:56.618322 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9749 06:52:56.618373 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9750 06:52:56.618489 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9751 06:52:56.618541 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9752 06:52:56.618591 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9753 06:52:56.618642 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9754 06:52:56.618692 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9755 06:52:56.618743 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9756 06:52:56.618794 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9757 06:52:56.618844 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9758 06:52:56.618895 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9759 06:52:56.618974 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9760 06:52:56.619024 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9761 06:52:56.619095 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9762 06:52:56.619147 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9763 06:52:56.619197 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9764 06:52:56.619271 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9765 06:52:56.619335 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9766 06:52:56.619391 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9767 06:52:56.619449 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9768 06:52:56.619501 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9769 06:52:56.619551 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9770 06:52:56.619602 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9771 06:52:56.619652 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9772 06:52:56.619703 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9773 06:52:56.619754 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9774 06:52:56.619804 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9775 06:52:56.619854 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9776 06:52:56.619905 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9777 06:52:56.619955 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9778 06:52:56.620005 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9779 06:52:56.620055 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9780 06:52:56.620106 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9781 06:52:56.620156 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9782 06:52:56.620206 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9783 06:52:56.620257 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9784 06:52:56.620307 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9785 06:52:56.620357 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9786 06:52:56.620407 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9787 06:52:56.620457 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9788 06:52:56.620508 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9789 06:52:56.620558 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9790 06:52:56.620608 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9791 06:52:56.620658 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9792 06:52:56.620709 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9793 06:52:56.620758 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9794 06:52:56.620808 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9795 06:52:56.620858 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9796 06:52:56.620908 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9797 06:52:56.620958 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9798 06:52:56.621008 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9799 06:52:56.621058 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9800 06:52:56.621108 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9801 06:52:56.621158 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9802 06:52:56.621208 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9803 06:52:56.621258 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9804 06:52:56.621309 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9805 06:52:56.621360 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9806 06:52:56.621475 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9807 06:52:56.621568 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9808 06:52:56.621620 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9809 06:52:56.621671 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9810 06:52:56.621722 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9811 06:52:56.621772 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9812 06:52:56.621822 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9813 06:52:56.621873 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9814 06:52:56.621923 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9815 06:52:56.621973 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9816 06:52:56.622024 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9817 06:52:56.622270 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9818 06:52:56.622327 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9819 06:52:56.622379 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9820 06:52:56.622496 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9821 06:52:56.622593 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9822 06:52:56.622661 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9823 06:52:56.622713 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9824 06:52:56.622764 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9825 06:52:56.622814 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9826 06:52:56.622865 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9827 06:52:56.622915 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9828 06:52:56.622966 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9829 06:52:56.623016 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9830 06:52:56.623067 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9831 06:52:56.623117 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9832 06:52:56.623167 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9833 06:52:56.623217 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9834 06:52:56.623268 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9835 06:52:56.623318 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9836 06:52:56.623372 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9837 06:52:56.623429 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9838 06:52:56.623481 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9839 06:52:56.623532 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9840 06:52:56.623583 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9841 06:52:56.623633 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9842 06:52:56.623683 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9843 06:52:56.623734 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9844 06:52:56.623784 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9845 06:52:56.623834 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9846 06:52:56.623885 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9847 06:52:56.623936 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9848 06:52:56.623986 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9849 06:52:56.624036 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9850 06:52:56.624086 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9851 06:52:56.624136 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9852 06:52:56.624187 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9853 06:52:56.624237 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9854 06:52:56.624287 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9855 06:52:56.624337 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9856 06:52:56.624388 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9857 06:52:56.624438 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9858 06:52:56.624488 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9859 06:52:56.624539 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9860 06:52:56.624589 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9861 06:52:56.624639 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9862 06:52:56.624689 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9863 06:52:56.624739 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9864 06:52:56.624789 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9865 06:52:56.624839 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9866 06:52:56.624889 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9867 06:52:56.624940 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9868 06:52:56.624990 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9869 06:52:56.625040 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9870 06:52:56.625091 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9871 06:52:56.625142 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9872 06:52:56.625192 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9873 06:52:56.625243 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9874 06:52:56.625293 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9875 06:52:56.625343 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9876 06:52:56.625401 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9877 06:52:56.625452 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9878 06:52:56.625503 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9879 06:52:56.625554 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9880 06:52:56.625604 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9881 06:52:56.625654 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9882 06:52:56.625704 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9883 06:52:56.625754 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9884 06:52:56.625805 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9885 06:52:56.625855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9886 06:52:56.625905 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9887 06:52:56.625955 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9888 06:52:56.626005 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9889 06:52:56.626055 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9890 06:52:56.626105 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9891 06:52:56.626155 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9892 06:52:56.626206 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9893 06:52:56.626256 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9894 06:52:56.626512 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9895 06:52:56.626598 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9896 06:52:56.626679 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9897 06:52:56.626759 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9898 06:52:56.626839 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9899 06:52:56.626918 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9900 06:52:56.626998 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9901 06:52:56.627077 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9902 06:52:56.627157 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9903 06:52:57.108063 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9904 06:52:57.108598 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9905 06:52:57.108959 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9906 06:52:57.109295 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9907 06:52:57.109619 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9908 06:52:57.109937 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9909 06:52:57.110245 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9910 06:52:57.110613 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9911 06:52:57.110924 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9912 06:52:57.111229 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9913 06:52:57.111529 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9914 06:52:57.111828 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9915 06:52:57.112125 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9916 06:52:57.112423 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9917 06:52:57.112720 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9918 06:52:57.113016 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9919 06:52:57.113309 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9920 06:52:57.113602 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9921 06:52:57.113896 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9922 06:52:57.114190 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9923 06:52:57.114533 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9924 06:52:57.114841 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9925 06:52:57.115137 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9926 06:52:57.115433 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9927 06:52:57.115725 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9928 06:52:57.116017 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9929 06:52:57.116313 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9930 06:52:57.116609 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9931 06:52:57.116898 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9932 06:52:57.117189 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9933 06:52:57.117480 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9934 06:52:57.117772 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9935 06:52:57.118063 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9936 06:52:57.118354 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9937 06:52:57.118684 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9938 06:52:57.118978 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9939 06:52:57.119269 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9940 06:52:57.119561 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9941 06:52:57.119851 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9942 06:52:57.120335 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9943 06:52:57.120647 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9944 06:52:57.120941 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9945 06:52:57.121239 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9946 06:52:57.121533 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9947 06:52:57.121825 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9948 06:52:57.122117 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9949 06:52:57.122446 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9950 06:52:57.122753 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9951 06:52:57.123127 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9952 06:52:57.123435 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9953 06:52:57.123816 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9954 06:52:57.124129 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9955 06:52:57.124426 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9956 06:52:57.124721 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9957 06:52:57.125040 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9958 06:52:57.125479 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9959 06:52:57.125959 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9960 06:52:57.126280 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9961 06:52:57.126601 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9962 06:52:57.126897 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9963 06:52:57.127191 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9964 06:52:57.127484 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9965 06:52:57.127778 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9966 06:52:57.128070 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9967 06:52:57.128363 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9968 06:52:57.128655 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9969 06:52:57.129351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9970 06:52:57.129684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9971 06:52:57.129984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9972 06:52:57.130281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9973 06:52:57.130606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9974 06:52:57.130903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9975 06:52:57.131196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9976 06:52:57.131492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9977 06:52:57.131783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9978 06:52:57.132076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9979 06:52:57.132365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9980 06:52:57.132655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9981 06:52:57.132945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9982 06:52:57.133278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9983 06:52:57.133591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9984 06:52:57.133800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9985 06:52:57.134007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9986 06:52:57.134214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9987 06:52:57.134436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9988 06:52:57.134644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9989 06:52:57.134848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9990 06:52:57.135055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9991 06:52:57.135260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9992 06:52:57.135465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9993 06:52:57.135670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9994 06:52:57.135877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9995 06:52:57.136082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9996 06:52:57.136290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9997 06:52:57.136498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9998 06:52:57.136705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9999 06:52:57.136913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10000 06:52:57.137121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10001 06:52:57.137329 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10002 06:52:57.137558 INFO: [APUAPC] vio 0
10003 06:52:57.137766 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10004 06:52:57.137975 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10005 06:52:57.138182 INFO: [APUAPC] D0_APC_0: 0x400510
10006 06:52:57.138389 INFO: [APUAPC] D0_APC_1: 0x0
10007 06:52:57.138623 INFO: [APUAPC] D0_APC_2: 0x1540
10008 06:52:57.138775 INFO: [APUAPC] D0_APC_3: 0x0
10009 06:52:57.138926 INFO: [APUAPC] D1_APC_0: 0xffffffff
10010 06:52:57.139079 INFO: [APUAPC] D1_APC_1: 0xffffffff
10011 06:52:57.139232 INFO: [APUAPC] D1_APC_2: 0x3fffff
10012 06:52:57.139399 INFO: [APUAPC] D1_APC_3: 0x0
10013 06:52:57.139560 INFO: [APUAPC] D2_APC_0: 0xffffffff
10014 06:52:57.139714 INFO: [APUAPC] D2_APC_1: 0xffffffff
10015 06:52:57.139865 INFO: [APUAPC] D2_APC_2: 0x3fffff
10016 06:52:57.140018 INFO: [APUAPC] D2_APC_3: 0x0
10017 06:52:57.140170 INFO: [APUAPC] D3_APC_0: 0xffffffff
10018 06:52:57.140321 INFO: [APUAPC] D3_APC_1: 0xffffffff
10019 06:52:57.140473 INFO: [APUAPC] D3_APC_2: 0x3fffff
10020 06:52:57.140625 INFO: [APUAPC] D3_APC_3: 0x0
10021 06:52:57.140778 INFO: [APUAPC] D4_APC_0: 0xffffffff
10022 06:52:57.140930 INFO: [APUAPC] D4_APC_1: 0xffffffff
10023 06:52:57.141083 INFO: [APUAPC] D4_APC_2: 0x3fffff
10024 06:52:57.141236 INFO: [APUAPC] D4_APC_3: 0x0
10025 06:52:57.141388 INFO: [APUAPC] D5_APC_0: 0xffffffff
10026 06:52:57.141553 INFO: [APUAPC] D5_APC_1: 0xffffffff
10027 06:52:57.141707 INFO: [APUAPC] D5_APC_2: 0x3fffff
10028 06:52:57.141859 INFO: [APUAPC] D5_APC_3: 0x0
10029 06:52:57.142010 INFO: [APUAPC] D6_APC_0: 0xffffffff
10030 06:52:57.142159 INFO: [APUAPC] D6_APC_1: 0xffffffff
10031 06:52:57.142311 INFO: [APUAPC] D6_APC_2: 0x3fffff
10032 06:52:57.142476 INFO: [APUAPC] D6_APC_3: 0x0
10033 06:52:57.142629 INFO: [APUAPC] D7_APC_0: 0xffffffff
10034 06:52:57.142781 INFO: [APUAPC] D7_APC_1: 0xffffffff
10035 06:52:57.142933 INFO: [APUAPC] D7_APC_2: 0x3fffff
10036 06:52:57.143085 INFO: [APUAPC] D7_APC_3: 0x0
10037 06:52:57.143238 INFO: [APUAPC] D8_APC_0: 0xffffffff
10038 06:52:57.143390 INFO: [APUAPC] D8_APC_1: 0xffffffff
10039 06:52:57.143581 INFO: [APUAPC] D8_APC_2: 0x3fffff
10040 06:52:57.143708 INFO: [APUAPC] D8_APC_3: 0x0
10041 06:52:57.143831 INFO: [APUAPC] D9_APC_0: 0xffffffff
10042 06:52:57.143952 INFO: [APUAPC] D9_APC_1: 0xffffffff
10043 06:52:57.144072 INFO: [APUAPC] D9_APC_2: 0x3fffff
10044 06:52:57.144193 INFO: [APUAPC] D9_APC_3: 0x0
10045 06:52:57.144313 INFO: [APUAPC] D10_APC_0: 0xffffffff
10046 06:52:57.144435 INFO: [APUAPC] D10_APC_1: 0xffffffff
10047 06:52:57.144556 INFO: [APUAPC] D10_APC_2: 0x3fffff
10048 06:52:57.144676 INFO: [APUAPC] D10_APC_3: 0x0
10049 06:52:57.144797 INFO: [APUAPC] D11_APC_0: 0xffffffff
10050 06:52:57.144918 INFO: [APUAPC] D11_APC_1: 0xffffffff
10051 06:52:57.145037 INFO: [APUAPC] D11_APC_2: 0x3fffff
10052 06:52:57.145158 INFO: [APUAPC] D11_APC_3: 0x0
10053 06:52:57.145278 INFO: [APUAPC] D12_APC_0: 0xffffffff
10054 06:52:57.145399 INFO: [APUAPC] D12_APC_1: 0xffffffff
10055 06:52:57.145519 INFO: [APUAPC] D12_APC_2: 0x3fffff
10056 06:52:57.145639 INFO: [APUAPC] D12_APC_3: 0x0
10057 06:52:57.145790 INFO: [APUAPC] D13_APC_0: 0xffffffff
10058 06:52:57.145914 INFO: [APUAPC] D13_APC_1: 0xffffffff
10059 06:52:57.146034 INFO: [APUAPC] D13_APC_2: 0x3fffff
10060 06:52:57.146425 INFO: [APUAPC] D13_APC_3: 0x0
10061 06:52:57.146567 INFO: [APUAPC] D14_APC_0: 0xffffffff
10062 06:52:57.146692 INFO: [APUAPC] D14_APC_1: 0xffffffff
10063 06:52:57.146815 INFO: [APUAPC] D14_APC_2: 0x3fffff
10064 06:52:57.146937 INFO: [APUAPC] D14_APC_3: 0x0
10065 06:52:57.147057 INFO: [APUAPC] D15_APC_0: 0xffffffff
10066 06:52:57.147178 INFO: [APUAPC] D15_APC_1: 0xffffffff
10067 06:52:57.147297 INFO: [APUAPC] D15_APC_2: 0x3fffff
10068 06:52:57.147417 INFO: [APUAPC] D15_APC_3: 0x0
10069 06:52:57.147538 INFO: [APUAPC] APC_CON: 0x4
10070 06:52:57.147659 INFO: [NOCDAPC] D0_APC_0: 0x0
10071 06:52:57.147778 INFO: [NOCDAPC] D0_APC_1: 0x0
10072 06:52:57.147898 INFO: [NOCDAPC] D1_APC_0: 0x0
10073 06:52:57.148018 INFO: [NOCDAPC] D1_APC_1: 0xfff
10074 06:52:57.148139 INFO: [NOCDAPC] D2_APC_0: 0x0
10075 06:52:57.148258 INFO: [NOCDAPC] D2_APC_1: 0xfff
10076 06:52:57.148378 INFO: [NOCDAPC] D3_APC_0: 0x0
10077 06:52:57.148499 INFO: [NOCDAPC] D3_APC_1: 0xfff
10078 06:52:57.148623 INFO: [NOCDAPC] D4_APC_0: 0x0
10079 06:52:57.148721 INFO: [NOCDAPC] D4_APC_1: 0xfff
10080 06:52:57.148820 INFO: [NOCDAPC] D5_APC_0: 0x0
10081 06:52:57.148919 INFO: [NOCDAPC] D5_APC_1: 0xfff
10082 06:52:57.149019 INFO: [NOCDAPC] D6_APC_0: 0x0
10083 06:52:57.149118 INFO: [NOCDAPC] D6_APC_1: 0xfff
10084 06:52:57.149218 INFO: [NOCDAPC] D7_APC_0: 0x0
10085 06:52:57.149318 INFO: [NOCDAPC] D7_APC_1: 0xfff
10086 06:52:57.149419 INFO: [NOCDAPC] D8_APC_0: 0x0
10087 06:52:57.149517 INFO: [NOCDAPC] D8_APC_1: 0xfff
10088 06:52:57.149616 INFO: [NOCDAPC] D9_APC_0: 0x0
10089 06:52:57.149715 INFO: [NOCDAPC] D9_APC_1: 0xfff
10090 06:52:57.149815 INFO: [NOCDAPC] D10_APC_0: 0x0
10091 06:52:57.149914 INFO: [NOCDAPC] D10_APC_1: 0xfff
10092 06:52:57.150013 INFO: [NOCDAPC] D11_APC_0: 0x0
10093 06:52:57.150113 INFO: [NOCDAPC] D11_APC_1: 0xfff
10094 06:52:57.150213 INFO: [NOCDAPC] D12_APC_0: 0x0
10095 06:52:57.150313 INFO: [NOCDAPC] D12_APC_1: 0xfff
10096 06:52:57.150419 INFO: [NOCDAPC] D13_APC_0: 0x0
10097 06:52:57.150520 INFO: [NOCDAPC] D13_APC_1: 0xfff
10098 06:52:57.150619 INFO: [NOCDAPC] D14_APC_0: 0x0
10099 06:52:57.150719 INFO: [NOCDAPC] D14_APC_1: 0xfff
10100 06:52:57.150818 INFO: [NOCDAPC] D15_APC_0: 0x0
10101 06:52:57.150918 INFO: [NOCDAPC] D15_APC_1: 0xfff
10102 06:52:57.151016 INFO: [NOCDAPC] APC_CON: 0x4
10103 06:52:57.151116 INFO: [APUAPC] set_apusys_apc done
10104 06:52:57.151215 INFO: [DEVAPC] devapc_init done
10105 06:52:57.151314 INFO: GICv3 without legacy support detected.
10106 06:52:57.151416 INFO: ARM GICv3 driver initialized in EL3
10107 06:52:57.151516 INFO: Maximum SPI INTID supported: 639
10108 06:52:57.151615 INFO: BL31: Initializing runtime services
10109 06:52:57.151714 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10110 06:52:57.151815 INFO: SPM: enable CPC mode
10111 06:52:57.151915 INFO: mcdi ready for mcusys-off-idle and system suspend
10112 06:52:57.152015 INFO: BL31: Preparing for EL3 exit to normal world
10113 06:52:57.152116 INFO: Entry point address = 0x80000000
10114 06:52:57.152216 INFO: SPSR = 0x8
10115 06:52:57.152315
10116 06:52:57.152415
10117 06:52:57.152514
10118 06:52:57.152614 Starting depthcharge on Spherion...
10119 06:52:57.152715
10120 06:52:57.152815 Wipe memory regions:
10121 06:52:57.152915
10122 06:52:57.153015 [0x00000040000000, 0x00000054600000)
10123 06:52:57.153115
10124 06:52:57.153215 [0x00000054660000, 0x00000080000000)
10125 06:52:57.153314
10126 06:52:57.153413 [0x000000821a7280, 0x000000ffe64000)
10127 06:52:57.153513
10128 06:52:57.153618 [0x00000100000000, 0x00000240000000)
10129 06:52:57.154515 end: 2.2.3 depthcharge-start (duration 00:00:32) [common]
10130 06:52:57.154671 start: 2.2.4 bootloader-commands (timeout 00:04:23) [common]
10131 06:52:57.154808 Setting prompt string to ['asurada:']
10132 06:52:57.154941 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:23)
10133 06:52:57.659423
10134 06:52:57.662210 Initializing XHCI USB controller at 0x11200000.
10135 06:52:58.700024
10136 06:52:58.703190 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10137 06:52:58.703844
10138 06:52:58.704221
10139 06:52:58.704563
10140 06:52:58.705393 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10142 06:52:58.806648 asurada: tftpboot 192.168.201.1 12694840/tftp-deploy-7407rfg7/kernel/image.itb 12694840/tftp-deploy-7407rfg7/kernel/cmdline
10143 06:52:58.807278 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10144 06:52:58.807714 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10145 06:52:58.812454 tftpboot 192.168.201.1 12694840/tftp-deploy-7407rfg7/kernel/image.ittp-deploy-7407rfg7/kernel/cmdline
10146 06:52:58.813021
10147 06:52:58.813584 Waiting for link
10148 06:52:58.972928
10149 06:52:58.973470 R8152: Initializing
10150 06:52:58.973841
10151 06:52:58.977143 Version 6 (ocp_data = 5c30)
10152 06:52:58.977717
10153 06:52:58.979567 R8152: Done initializing
10154 06:52:58.980034
10155 06:52:58.980406 Adding net device
10156 06:53:00.847380
10157 06:53:00.847944 done.
10158 06:53:00.848320
10159 06:53:00.848671 MAC: 00:24:32:30:78:52
10160 06:53:00.849021
10161 06:53:00.850184 Sending DHCP discover... done.
10162 06:53:00.850709
10163 06:53:10.567278 Waiting for reply... R8152: Bulk read error 0xffffffbf
10164 06:53:10.567812
10165 06:53:10.570570 Receive failed.
10166 06:53:10.570996
10167 06:53:10.571337 done.
10168 06:53:10.571926
10169 06:53:10.573688 Sending DHCP request... done.
10170 06:53:10.574110
10171 06:53:10.580873 Waiting for reply... done.
10172 06:53:10.581300
10173 06:53:10.581635 My ip is 192.168.201.14
10174 06:53:10.581949
10175 06:53:10.584080 The DHCP server ip is 192.168.201.1
10176 06:53:10.584512
10177 06:53:10.590381 TFTP server IP predefined by user: 192.168.201.1
10178 06:53:10.590930
10179 06:53:10.596920 Bootfile predefined by user: 12694840/tftp-deploy-7407rfg7/kernel/image.itb
10180 06:53:10.597381
10181 06:53:10.597810 Sending tftp read request... done.
10182 06:53:10.598247
10183 06:53:10.606610 Waiting for the transfer...
10184 06:53:10.607041
10185 06:53:11.308190 00000000 ################################################################
10186 06:53:11.308747
10187 06:53:12.036920 00080000 ################################################################
10188 06:53:12.037457
10189 06:53:12.749194 00100000 ################################################################
10190 06:53:12.749720
10191 06:53:13.455305 00180000 ################################################################
10192 06:53:13.455849
10193 06:53:14.180846 00200000 ################################################################
10194 06:53:14.181389
10195 06:53:14.894983 00280000 ################################################################
10196 06:53:14.895768
10197 06:53:15.605815 00300000 ################################################################
10198 06:53:15.606360
10199 06:53:16.326204 00380000 ################################################################
10200 06:53:16.326769
10201 06:53:17.030739 00400000 ################################################################
10202 06:53:17.031272
10203 06:53:17.750183 00480000 ################################################################
10204 06:53:17.750741
10205 06:53:18.473722 00500000 ################################################################
10206 06:53:18.474293
10207 06:53:19.193608 00580000 ################################################################
10208 06:53:19.194153
10209 06:53:19.895857 00600000 ################################################################
10210 06:53:19.896390
10211 06:53:20.571902 00680000 ################################################################
10212 06:53:20.572403
10213 06:53:21.232670 00700000 ################################################################
10214 06:53:21.233197
10215 06:53:21.932381 00780000 ################################################################
10216 06:53:21.932919
10217 06:53:22.617852 00800000 ################################################################
10218 06:53:22.618447
10219 06:53:23.326055 00880000 ################################################################
10220 06:53:23.326755
10221 06:53:24.061826 00900000 ################################################################
10222 06:53:24.062349
10223 06:53:24.785542 00980000 ################################################################
10224 06:53:24.786102
10225 06:53:25.507545 00a00000 ################################################################
10226 06:53:25.508100
10227 06:53:26.207422 00a80000 ################################################################
10228 06:53:26.207954
10229 06:53:26.923106 00b00000 ################################################################
10230 06:53:26.923591
10231 06:53:27.627993 00b80000 ################################################################
10232 06:53:27.628654
10233 06:53:28.333527 00c00000 ################################################################
10234 06:53:28.334066
10235 06:53:29.040095 00c80000 ################################################################
10236 06:53:29.040626
10237 06:53:29.751836 00d00000 ################################################################
10238 06:53:29.752362
10239 06:53:30.417422 00d80000 ################################################################
10240 06:53:30.417954
10241 06:53:31.117128 00e00000 ################################################################
10242 06:53:31.117664
10243 06:53:31.859912 00e80000 ################################################################
10244 06:53:31.860448
10245 06:53:32.581513 00f00000 ################################################################
10246 06:53:32.582057
10247 06:53:33.306832 00f80000 ################################################################
10248 06:53:33.307353
10249 06:53:34.023851 01000000 ################################################################
10250 06:53:34.024344
10251 06:53:34.749491 01080000 ################################################################
10252 06:53:34.750043
10253 06:53:35.461504 01100000 ################################################################
10254 06:53:35.462020
10255 06:53:36.142567 01180000 ################################################################
10256 06:53:36.143128
10257 06:53:36.864414 01200000 ################################################################
10258 06:53:36.865152
10259 06:53:37.588271 01280000 ################################################################
10260 06:53:37.588793
10261 06:53:38.308544 01300000 ################################################################
10262 06:53:38.309193
10263 06:53:39.012865 01380000 ################################################################
10264 06:53:39.013394
10265 06:53:39.745607 01400000 ################################################################
10266 06:53:39.746137
10267 06:53:40.475628 01480000 ################################################################
10268 06:53:40.476166
10269 06:53:41.198585 01500000 ################################################################
10270 06:53:41.199140
10271 06:53:41.909448 01580000 ################################################################
10272 06:53:41.909988
10273 06:53:42.612061 01600000 ################################################################
10274 06:53:42.612668
10275 06:53:43.316093 01680000 ################################################################
10276 06:53:43.316607
10277 06:53:44.054991 01700000 ################################################################
10278 06:53:44.055514
10279 06:53:44.737623 01780000 ################################################################
10280 06:53:44.738165
10281 06:53:45.436556 01800000 ################################################################
10282 06:53:45.437082
10283 06:53:46.163491 01880000 ################################################################
10284 06:53:46.164056
10285 06:53:46.875863 01900000 ################################################################
10286 06:53:46.876406
10287 06:53:47.590575 01980000 ################################################################
10288 06:53:47.591513
10289 06:53:48.314518 01a00000 ################################################################
10290 06:53:48.315129
10291 06:53:49.028917 01a80000 ################################################################
10292 06:53:49.029481
10293 06:53:49.748750 01b00000 ################################################################
10294 06:53:49.749420
10295 06:53:50.471237 01b80000 ################################################################
10296 06:53:50.471966
10297 06:53:51.186318 01c00000 ################################################################
10298 06:53:51.186915
10299 06:53:51.213549 01c80000 ### done.
10300 06:53:51.214075
10301 06:53:51.216519 The bootfile was 29902918 bytes long.
10302 06:53:51.216960
10303 06:53:51.217425 Sending tftp read request... done.
10304 06:53:51.219816
10305 06:53:51.223343 Waiting for the transfer...
10306 06:53:51.223771
10307 06:53:51.224107 00000000 # done.
10308 06:53:51.224427
10309 06:53:51.230096 Command line loaded dynamically from TFTP file: 12694840/tftp-deploy-7407rfg7/kernel/cmdline
10310 06:53:51.230522
10311 06:53:51.253668 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694840/extract-nfsrootfs-kxldhbtm,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10312 06:53:51.254196
10313 06:53:51.254589 Loading FIT.
10314 06:53:51.254928
10315 06:53:51.256848 Image ramdisk-1 has 17803024 bytes.
10316 06:53:51.257271
10317 06:53:51.260014 Image fdt-1 has 47278 bytes.
10318 06:53:51.260440
10319 06:53:51.263975 Image kernel-1 has 12050581 bytes.
10320 06:53:51.264500
10321 06:53:51.273765 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10322 06:53:51.274300
10323 06:53:51.290684 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10324 06:53:51.291240
10325 06:53:51.293836 Choosing best match conf-1 for compat google,spherion-rev2.
10326 06:53:51.299656
10327 06:53:51.304041 Connected to device vid:did:rid of 1ae0:0028:00
10328 06:53:51.312214
10329 06:53:51.315861 tpm_get_response: command 0x17b, return code 0x0
10330 06:53:51.316292
10331 06:53:51.318906 ec_init: CrosEC protocol v3 supported (256, 248)
10332 06:53:51.322472
10333 06:53:51.326268 tpm_cleanup: add release locality here.
10334 06:53:51.326852
10335 06:53:51.327201 Shutting down all USB controllers.
10336 06:53:51.329360
10337 06:53:51.329784 Removing current net device
10338 06:53:51.330120
10339 06:53:51.336360 Exiting depthcharge with code 4 at timestamp: 86127034
10340 06:53:51.336787
10341 06:53:51.339902 LZMA decompressing kernel-1 to 0x821a6718
10342 06:53:51.340417
10343 06:53:51.342598 LZMA decompressing kernel-1 to 0x40000000
10344 06:53:52.841614
10345 06:53:52.842186 jumping to kernel
10346 06:53:52.844445 end: 2.2.4 bootloader-commands (duration 00:00:56) [common]
10347 06:53:52.845002 start: 2.2.5 auto-login-action (timeout 00:03:27) [common]
10348 06:53:52.845416 Setting prompt string to ['Linux version [0-9]']
10349 06:53:52.845795 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10350 06:53:52.846000 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10351 06:53:52.924672
10352 06:53:52.928032 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10353 06:53:52.931631 start: 2.2.5.1 login-action (timeout 00:03:27) [common]
10354 06:53:52.932141 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10355 06:53:52.932541 Setting prompt string to []
10356 06:53:52.932973 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10357 06:53:52.933378 Using line separator: #'\n'#
10358 06:53:52.933712 No login prompt set.
10359 06:53:52.934056 Parsing kernel messages
10360 06:53:52.934369 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10361 06:53:52.935228 [login-action] Waiting for messages, (timeout 00:03:27)
10362 06:53:52.951731 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10363 06:53:52.955253 [ 0.000000] random: crng init done
10364 06:53:52.961507 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10365 06:53:52.962078 [ 0.000000] efi: UEFI not found.
10366 06:53:52.971567 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10367 06:53:52.978337 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10368 06:53:52.988548 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10369 06:53:52.997874 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10370 06:53:53.004668 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10371 06:53:53.008328 [ 0.000000] printk: bootconsole [mtk8250] enabled
10372 06:53:53.016525 [ 0.000000] NUMA: No NUMA configuration found
10373 06:53:53.023481 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10374 06:53:53.030246 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10375 06:53:53.030880 [ 0.000000] Zone ranges:
10376 06:53:53.036701 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10377 06:53:53.040759 [ 0.000000] DMA32 empty
10378 06:53:53.047083 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10379 06:53:53.050531 [ 0.000000] Movable zone start for each node
10380 06:53:53.053625 [ 0.000000] Early memory node ranges
10381 06:53:53.060192 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10382 06:53:53.066874 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10383 06:53:53.074023 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10384 06:53:53.080060 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10385 06:53:53.086930 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10386 06:53:53.093543 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10387 06:53:53.148794 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10388 06:53:53.155769 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10389 06:53:53.162472 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10390 06:53:53.165921 [ 0.000000] psci: probing for conduit method from DT.
10391 06:53:53.172488 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10392 06:53:53.175871 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10393 06:53:53.182431 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10394 06:53:53.185328 [ 0.000000] psci: SMC Calling Convention v1.2
10395 06:53:53.191984 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10396 06:53:53.195186 [ 0.000000] Detected VIPT I-cache on CPU0
10397 06:53:53.202559 [ 0.000000] CPU features: detected: GIC system register CPU interface
10398 06:53:53.209033 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10399 06:53:53.215997 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10400 06:53:53.222025 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10401 06:53:53.228953 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10402 06:53:53.235678 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10403 06:53:53.242217 [ 0.000000] alternatives: applying boot alternatives
10404 06:53:53.245663 [ 0.000000] Fallback order for Node 0: 0
10405 06:53:53.251749 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10406 06:53:53.255433 [ 0.000000] Policy zone: Normal
10407 06:53:53.279017 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694840/extract-nfsrootfs-kxldhbtm,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10408 06:53:53.291835 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10409 06:53:53.302525 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10410 06:53:53.312063 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10411 06:53:53.318589 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10412 06:53:53.322285 <6>[ 0.000000] software IO TLB: area num 8.
10413 06:53:53.378622 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10414 06:53:53.527322 <6>[ 0.000000] Memory: 7949868K/8385536K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 402900K reserved, 32768K cma-reserved)
10415 06:53:53.534529 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10416 06:53:53.541352 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10417 06:53:53.544564 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10418 06:53:53.551222 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10419 06:53:53.557658 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10420 06:53:53.561212 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10421 06:53:53.571233 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10422 06:53:53.578051 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10423 06:53:53.581176 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10424 06:53:53.588361 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10425 06:53:53.591890 <6>[ 0.000000] GICv3: 608 SPIs implemented
10426 06:53:53.598799 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10427 06:53:53.602307 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10428 06:53:53.605485 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10429 06:53:53.615269 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10430 06:53:53.625275 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10431 06:53:53.638281 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10432 06:53:53.645027 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10433 06:53:53.654036 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10434 06:53:53.667669 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10435 06:53:53.673812 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10436 06:53:53.680177 <6>[ 0.009182] Console: colour dummy device 80x25
10437 06:53:53.690433 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10438 06:53:53.697627 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10439 06:53:53.700362 <6>[ 0.029225] LSM: Security Framework initializing
10440 06:53:53.707111 <6>[ 0.034166] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10441 06:53:53.717092 <6>[ 0.042029] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10442 06:53:53.723491 <6>[ 0.051442] cblist_init_generic: Setting adjustable number of callback queues.
10443 06:53:53.730859 <6>[ 0.058884] cblist_init_generic: Setting shift to 3 and lim to 1.
10444 06:53:53.740266 <6>[ 0.065264] cblist_init_generic: Setting adjustable number of callback queues.
10445 06:53:53.747142 <6>[ 0.072691] cblist_init_generic: Setting shift to 3 and lim to 1.
10446 06:53:53.750332 <6>[ 0.079096] rcu: Hierarchical SRCU implementation.
10447 06:53:53.756983 <6>[ 0.084142] rcu: Max phase no-delay instances is 1000.
10448 06:53:53.763487 <6>[ 0.091172] EFI services will not be available.
10449 06:53:53.768466 <6>[ 0.096125] smp: Bringing up secondary CPUs ...
10450 06:53:53.775051 <6>[ 0.101173] Detected VIPT I-cache on CPU1
10451 06:53:53.781527 <6>[ 0.101241] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10452 06:53:53.787722 <6>[ 0.101273] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10453 06:53:53.791127 <6>[ 0.101617] Detected VIPT I-cache on CPU2
10454 06:53:53.798162 <6>[ 0.101668] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10455 06:53:53.805252 <6>[ 0.101686] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10456 06:53:53.811751 <6>[ 0.101948] Detected VIPT I-cache on CPU3
10457 06:53:53.818146 <6>[ 0.101994] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10458 06:53:53.824763 <6>[ 0.102009] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10459 06:53:53.828382 <6>[ 0.102313] CPU features: detected: Spectre-v4
10460 06:53:53.834571 <6>[ 0.102320] CPU features: detected: Spectre-BHB
10461 06:53:53.838795 <6>[ 0.102324] Detected PIPT I-cache on CPU4
10462 06:53:53.845735 <6>[ 0.102385] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10463 06:53:53.851441 <6>[ 0.102401] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10464 06:53:53.855009 <6>[ 0.102692] Detected PIPT I-cache on CPU5
10465 06:53:53.864933 <6>[ 0.102755] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10466 06:53:53.871733 <6>[ 0.102772] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10467 06:53:53.874841 <6>[ 0.103052] Detected PIPT I-cache on CPU6
10468 06:53:53.881306 <6>[ 0.103116] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10469 06:53:53.887781 <6>[ 0.103132] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10470 06:53:53.891219 <6>[ 0.103432] Detected PIPT I-cache on CPU7
10471 06:53:53.901080 <6>[ 0.103498] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10472 06:53:53.908028 <6>[ 0.103515] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10473 06:53:53.911092 <6>[ 0.103561] smp: Brought up 1 node, 8 CPUs
10474 06:53:53.914597 <6>[ 0.244976] SMP: Total of 8 processors activated.
10475 06:53:53.920944 <6>[ 0.249927] CPU features: detected: 32-bit EL0 Support
10476 06:53:53.930815 <6>[ 0.255322] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10477 06:53:53.937884 <6>[ 0.264123] CPU features: detected: Common not Private translations
10478 06:53:53.941461 <6>[ 0.270598] CPU features: detected: CRC32 instructions
10479 06:53:53.948173 <6>[ 0.275950] CPU features: detected: RCpc load-acquire (LDAPR)
10480 06:53:53.954315 <6>[ 0.281910] CPU features: detected: LSE atomic instructions
10481 06:53:53.961218 <6>[ 0.287691] CPU features: detected: Privileged Access Never
10482 06:53:53.964410 <6>[ 0.293471] CPU features: detected: RAS Extension Support
10483 06:53:53.971245 <6>[ 0.299080] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10484 06:53:53.978391 <6>[ 0.306304] CPU: All CPU(s) started at EL2
10485 06:53:53.981561 <6>[ 0.310621] alternatives: applying system-wide alternatives
10486 06:53:53.992398 <6>[ 0.321332] devtmpfs: initialized
10487 06:53:54.008652 <6>[ 0.330336] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10488 06:53:54.014927 <6>[ 0.340293] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10489 06:53:54.021264 <6>[ 0.348394] pinctrl core: initialized pinctrl subsystem
10490 06:53:54.024397 <6>[ 0.355177] DMI not present or invalid.
10491 06:53:54.031030 <6>[ 0.359592] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10492 06:53:54.041204 <6>[ 0.366481] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10493 06:53:54.048091 <6>[ 0.374062] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10494 06:53:54.058479 <6>[ 0.382270] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10495 06:53:54.061114 <6>[ 0.390512] audit: initializing netlink subsys (disabled)
10496 06:53:54.071618 <5>[ 0.396200] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10497 06:53:54.077650 <6>[ 0.396944] thermal_sys: Registered thermal governor 'step_wise'
10498 06:53:54.084530 <6>[ 0.404167] thermal_sys: Registered thermal governor 'power_allocator'
10499 06:53:54.087386 <6>[ 0.410421] cpuidle: using governor menu
10500 06:53:54.094632 <6>[ 0.421384] NET: Registered PF_QIPCRTR protocol family
10501 06:53:54.101852 <6>[ 0.426864] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10502 06:53:54.104721 <6>[ 0.433969] ASID allocator initialised with 32768 entries
10503 06:53:54.111593 <6>[ 0.440591] Serial: AMBA PL011 UART driver
10504 06:53:54.120981 <4>[ 0.449741] Trying to register duplicate clock ID: 134
10505 06:53:54.177254 <6>[ 0.509424] KASLR enabled
10506 06:53:54.191414 <6>[ 0.517068] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10507 06:53:54.198943 <6>[ 0.524084] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10508 06:53:54.206106 <6>[ 0.530571] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10509 06:53:54.211116 <6>[ 0.537579] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10510 06:53:54.217914 <6>[ 0.544069] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10511 06:53:54.224644 <6>[ 0.551073] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10512 06:53:54.231126 <6>[ 0.557559] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10513 06:53:54.238458 <6>[ 0.564561] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10514 06:53:54.241538 <6>[ 0.572026] ACPI: Interpreter disabled.
10515 06:53:54.249598 <6>[ 0.578513] iommu: Default domain type: Translated
10516 06:53:54.256231 <6>[ 0.583661] iommu: DMA domain TLB invalidation policy: strict mode
10517 06:53:54.259863 <5>[ 0.590315] SCSI subsystem initialized
10518 06:53:54.266728 <6>[ 0.594564] usbcore: registered new interface driver usbfs
10519 06:53:54.272958 <6>[ 0.600293] usbcore: registered new interface driver hub
10520 06:53:54.276399 <6>[ 0.605843] usbcore: registered new device driver usb
10521 06:53:54.283541 <6>[ 0.612011] pps_core: LinuxPPS API ver. 1 registered
10522 06:53:54.293544 <6>[ 0.617205] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10523 06:53:54.296727 <6>[ 0.626542] PTP clock support registered
10524 06:53:54.299563 <6>[ 0.630787] EDAC MC: Ver: 3.0.0
10525 06:53:54.307180 <6>[ 0.636020] FPGA manager framework
10526 06:53:54.310515 <6>[ 0.639696] Advanced Linux Sound Architecture Driver Initialized.
10527 06:53:54.314324 <6>[ 0.646457] vgaarb: loaded
10528 06:53:54.321115 <6>[ 0.649609] clocksource: Switched to clocksource arch_sys_counter
10529 06:53:54.327479 <5>[ 0.656051] VFS: Disk quotas dquot_6.6.0
10530 06:53:54.334490 <6>[ 0.660238] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10531 06:53:54.338102 <6>[ 0.667433] pnp: PnP ACPI: disabled
10532 06:53:54.345793 <6>[ 0.674105] NET: Registered PF_INET protocol family
10533 06:53:54.355354 <6>[ 0.679698] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10534 06:53:54.367304 <6>[ 0.692022] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10535 06:53:54.376582 <6>[ 0.700836] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10536 06:53:54.383603 <6>[ 0.708804] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10537 06:53:54.390165 <6>[ 0.717506] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10538 06:53:54.401861 <6>[ 0.727255] TCP: Hash tables configured (established 65536 bind 65536)
10539 06:53:54.408533 <6>[ 0.734055] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10540 06:53:54.415273 <6>[ 0.741250] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10541 06:53:54.421694 <6>[ 0.748956] NET: Registered PF_UNIX/PF_LOCAL protocol family
10542 06:53:54.428317 <6>[ 0.755107] RPC: Registered named UNIX socket transport module.
10543 06:53:54.431709 <6>[ 0.761262] RPC: Registered udp transport module.
10544 06:53:54.438491 <6>[ 0.766196] RPC: Registered tcp transport module.
10545 06:53:54.445019 <6>[ 0.771124] RPC: Registered tcp NFSv4.1 backchannel transport module.
10546 06:53:54.448496 <6>[ 0.777785] PCI: CLS 0 bytes, default 64
10547 06:53:54.451610 <6>[ 0.782128] Unpacking initramfs...
10548 06:53:54.476764 <6>[ 0.801727] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10549 06:53:54.486707 <6>[ 0.810367] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10550 06:53:54.489503 <6>[ 0.819232] kvm [1]: IPA Size Limit: 40 bits
10551 06:53:54.496431 <6>[ 0.823759] kvm [1]: GICv3: no GICV resource entry
10552 06:53:54.500067 <6>[ 0.828779] kvm [1]: disabling GICv2 emulation
10553 06:53:54.506658 <6>[ 0.833464] kvm [1]: GIC system register CPU interface enabled
10554 06:53:54.509748 <6>[ 0.839633] kvm [1]: vgic interrupt IRQ18
10555 06:53:54.516406 <6>[ 0.843985] kvm [1]: VHE mode initialized successfully
10556 06:53:54.523010 <5>[ 0.850437] Initialise system trusted keyrings
10557 06:53:54.529791 <6>[ 0.855333] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10558 06:53:54.537101 <6>[ 0.865404] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10559 06:53:54.543355 <5>[ 0.871771] NFS: Registering the id_resolver key type
10560 06:53:54.546748 <5>[ 0.877073] Key type id_resolver registered
10561 06:53:54.553549 <5>[ 0.881488] Key type id_legacy registered
10562 06:53:54.560049 <6>[ 0.885767] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10563 06:53:54.566640 <6>[ 0.892688] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10564 06:53:54.573458 <6>[ 0.900386] 9p: Installing v9fs 9p2000 file system support
10565 06:53:54.609640 <5>[ 0.938158] Key type asymmetric registered
10566 06:53:54.612854 <5>[ 0.942490] Asymmetric key parser 'x509' registered
10567 06:53:54.622485 <6>[ 0.947631] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10568 06:53:54.626319 <6>[ 0.955248] io scheduler mq-deadline registered
10569 06:53:54.629448 <6>[ 0.960004] io scheduler kyber registered
10570 06:53:54.648231 <6>[ 0.977444] EINJ: ACPI disabled.
10571 06:53:54.681834 <4>[ 1.002985] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10572 06:53:54.690925 <4>[ 1.013642] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10573 06:53:54.706136 <6>[ 1.034831] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10574 06:53:54.713885 <6>[ 1.042871] printk: console [ttyS0] disabled
10575 06:53:54.742006 <6>[ 1.067498] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10576 06:53:54.748848 <6>[ 1.076975] printk: console [ttyS0] enabled
10577 06:53:54.751725 <6>[ 1.076975] printk: console [ttyS0] enabled
10578 06:53:54.759204 <6>[ 1.085870] printk: bootconsole [mtk8250] disabled
10579 06:53:54.761969 <6>[ 1.085870] printk: bootconsole [mtk8250] disabled
10580 06:53:54.768843 <6>[ 1.097209] SuperH (H)SCI(F) driver initialized
10581 06:53:54.771673 <6>[ 1.102509] msm_serial: driver initialized
10582 06:53:54.785856 <6>[ 1.111650] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10583 06:53:54.796671 <6>[ 1.120200] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10584 06:53:54.803310 <6>[ 1.128743] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10585 06:53:54.813032 <6>[ 1.137377] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10586 06:53:54.819400 <6>[ 1.146085] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10587 06:53:54.829335 <6>[ 1.154809] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10588 06:53:54.839307 <6>[ 1.163350] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10589 06:53:54.846336 <6>[ 1.172156] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10590 06:53:54.855816 <6>[ 1.180700] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10591 06:53:54.868418 <6>[ 1.196797] loop: module loaded
10592 06:53:54.875012 <6>[ 1.202851] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10593 06:53:54.897760 <4>[ 1.226332] mtk-pmic-keys: Failed to locate of_node [id: -1]
10594 06:53:54.904261 <6>[ 1.233231] megasas: 07.719.03.00-rc1
10595 06:53:54.914224 <6>[ 1.242901] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10596 06:53:54.920906 <6>[ 1.248994] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10597 06:53:54.936927 <6>[ 1.265787] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10598 06:53:54.993992 <6>[ 1.315971] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10599 06:53:55.200057 <6>[ 1.528560] Freeing initrd memory: 17384K
10600 06:53:55.209990 <6>[ 1.539024] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10601 06:53:55.220972 <6>[ 1.549985] tun: Universal TUN/TAP device driver, 1.6
10602 06:53:55.224277 <6>[ 1.556058] thunder_xcv, ver 1.0
10603 06:53:55.227272 <6>[ 1.559570] thunder_bgx, ver 1.0
10604 06:53:55.230999 <6>[ 1.563063] nicpf, ver 1.0
10605 06:53:55.241924 <6>[ 1.567098] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10606 06:53:55.245387 <6>[ 1.574574] hns3: Copyright (c) 2017 Huawei Corporation.
10607 06:53:55.248427 <6>[ 1.580159] hclge is initializing
10608 06:53:55.255403 <6>[ 1.583738] e1000: Intel(R) PRO/1000 Network Driver
10609 06:53:55.262310 <6>[ 1.588867] e1000: Copyright (c) 1999-2006 Intel Corporation.
10610 06:53:55.265451 <6>[ 1.594879] e1000e: Intel(R) PRO/1000 Network Driver
10611 06:53:55.271953 <6>[ 1.600094] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10612 06:53:55.278611 <6>[ 1.606280] igb: Intel(R) Gigabit Ethernet Network Driver
10613 06:53:55.284840 <6>[ 1.611929] igb: Copyright (c) 2007-2014 Intel Corporation.
10614 06:53:55.291448 <6>[ 1.617767] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10615 06:53:55.295193 <6>[ 1.624285] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10616 06:53:55.302239 <6>[ 1.630750] sky2: driver version 1.30
10617 06:53:55.308274 <6>[ 1.635789] VFIO - User Level meta-driver version: 0.3
10618 06:53:55.315279 <6>[ 1.644093] usbcore: registered new interface driver usb-storage
10619 06:53:55.322252 <6>[ 1.650542] usbcore: registered new device driver onboard-usb-hub
10620 06:53:55.330737 <6>[ 1.659750] mt6397-rtc mt6359-rtc: registered as rtc0
10621 06:53:55.340683 <6>[ 1.665217] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:54:01 UTC (1706943241)
10622 06:53:55.344322 <6>[ 1.674798] i2c_dev: i2c /dev entries driver
10623 06:53:55.362042 <6>[ 1.686694] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10624 06:53:55.381139 <6>[ 1.709687] cpu cpu0: EM: created perf domain
10625 06:53:55.384295 <6>[ 1.714623] cpu cpu4: EM: created perf domain
10626 06:53:55.391631 <6>[ 1.720206] sdhci: Secure Digital Host Controller Interface driver
10627 06:53:55.397971 <6>[ 1.726639] sdhci: Copyright(c) Pierre Ossman
10628 06:53:55.404943 <6>[ 1.731612] Synopsys Designware Multimedia Card Interface Driver
10629 06:53:55.411899 <6>[ 1.738263] sdhci-pltfm: SDHCI platform and OF driver helper
10630 06:53:55.414541 <6>[ 1.738373] mmc0: CQHCI version 5.10
10631 06:53:55.421384 <6>[ 1.748375] ledtrig-cpu: registered to indicate activity on CPUs
10632 06:53:55.428339 <6>[ 1.755458] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10633 06:53:55.435107 <6>[ 1.762522] usbcore: registered new interface driver usbhid
10634 06:53:55.438038 <6>[ 1.768343] usbhid: USB HID core driver
10635 06:53:55.444828 <6>[ 1.772539] spi_master spi0: will run message pump with realtime priority
10636 06:53:55.488432 <6>[ 1.810561] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10637 06:53:55.507160 <6>[ 1.826505] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10638 06:53:55.510956 <6>[ 1.840056] mmc0: Command Queue Engine enabled
10639 06:53:55.518256 <6>[ 1.844820] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10640 06:53:55.524815 <6>[ 1.851752] cros-ec-spi spi0.0: Chrome EC device registered
10641 06:53:55.528151 <6>[ 1.852120] mmcblk0: mmc0:0001 DA4128 116 GiB
10642 06:53:55.537352 <6>[ 1.866112] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10643 06:53:55.544938 <6>[ 1.873439] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10644 06:53:55.551031 <6>[ 1.879370] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10645 06:53:55.558009 <6>[ 1.885271] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10646 06:53:55.575359 <6>[ 1.900178] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10647 06:53:55.581700 <6>[ 1.910638] NET: Registered PF_PACKET protocol family
10648 06:53:55.585146 <6>[ 1.916026] 9pnet: Installing 9P2000 support
10649 06:53:55.591450 <5>[ 1.920583] Key type dns_resolver registered
10650 06:53:55.594958 <6>[ 1.925562] registered taskstats version 1
10651 06:53:55.601545 <5>[ 1.929945] Loading compiled-in X.509 certificates
10652 06:53:55.631221 <4>[ 1.953100] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 06:53:55.641465 <4>[ 1.964032] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10654 06:53:55.647824 <3>[ 1.974601] debugfs: File 'uA_load' in directory '/' already present!
10655 06:53:55.654458 <3>[ 1.981306] debugfs: File 'min_uV' in directory '/' already present!
10656 06:53:55.661267 <3>[ 1.987921] debugfs: File 'max_uV' in directory '/' already present!
10657 06:53:55.668319 <3>[ 1.994530] debugfs: File 'constraint_flags' in directory '/' already present!
10658 06:53:55.678339 <3>[ 2.004174] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10659 06:53:55.693144 <6>[ 2.022128] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10660 06:53:55.699726 <6>[ 2.029019] xhci-mtk 11200000.usb: xHCI Host Controller
10661 06:53:55.706896 <6>[ 2.034534] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10662 06:53:55.717010 <6>[ 2.042422] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10663 06:53:55.723773 <6>[ 2.051864] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10664 06:53:55.730391 <6>[ 2.057960] xhci-mtk 11200000.usb: xHCI Host Controller
10665 06:53:55.736917 <6>[ 2.063463] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10666 06:53:55.743977 <6>[ 2.071120] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10667 06:53:55.750707 <6>[ 2.079019] hub 1-0:1.0: USB hub found
10668 06:53:55.753401 <6>[ 2.083056] hub 1-0:1.0: 1 port detected
10669 06:53:55.760361 <6>[ 2.087392] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10670 06:53:55.767327 <6>[ 2.096231] hub 2-0:1.0: USB hub found
10671 06:53:55.770639 <6>[ 2.100280] hub 2-0:1.0: 1 port detected
10672 06:53:55.779596 <6>[ 2.108212] mtk-msdc 11f70000.mmc: Got CD GPIO
10673 06:53:55.792685 <6>[ 2.118219] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10674 06:53:55.799672 <6>[ 2.126250] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10675 06:53:55.809552 <4>[ 2.134170] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10676 06:53:55.819918 <6>[ 2.143746] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10677 06:53:55.825955 <6>[ 2.151826] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10678 06:53:55.832514 <6>[ 2.159872] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10679 06:53:55.843305 <6>[ 2.167800] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10680 06:53:55.849954 <6>[ 2.175618] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10681 06:53:55.859713 <6>[ 2.183437] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10682 06:53:55.869870 <6>[ 2.194033] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10683 06:53:55.876156 <6>[ 2.202409] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10684 06:53:55.885982 <6>[ 2.210757] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10685 06:53:55.893260 <6>[ 2.219096] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10686 06:53:55.903064 <6>[ 2.227435] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10687 06:53:55.909720 <6>[ 2.235774] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10688 06:53:55.919277 <6>[ 2.244111] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10689 06:53:55.926391 <6>[ 2.252456] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10690 06:53:55.936451 <6>[ 2.260794] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10691 06:53:55.942777 <6>[ 2.269133] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10692 06:53:55.952725 <6>[ 2.277472] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10693 06:53:55.959860 <6>[ 2.285811] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10694 06:53:55.969617 <6>[ 2.294149] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10695 06:53:55.976365 <6>[ 2.302489] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10696 06:53:55.986541 <6>[ 2.310830] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10697 06:53:55.992841 <6>[ 2.319567] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10698 06:53:55.999821 <6>[ 2.326527] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10699 06:53:56.006175 <6>[ 2.333279] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10700 06:53:56.012934 <6>[ 2.340042] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10701 06:53:56.019526 <6>[ 2.346979] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10702 06:53:56.029381 <6>[ 2.353812] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10703 06:53:56.038924 <6>[ 2.362941] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10704 06:53:56.046264 <6>[ 2.372059] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10705 06:53:56.055671 <6>[ 2.381353] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10706 06:53:56.065993 <6>[ 2.390819] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10707 06:53:56.076093 <6>[ 2.400286] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10708 06:53:56.085857 <6>[ 2.409404] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10709 06:53:56.092319 <6>[ 2.418870] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10710 06:53:56.102211 <6>[ 2.427988] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10711 06:53:56.112319 <6>[ 2.437282] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10712 06:53:56.122765 <6>[ 2.447450] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10713 06:53:56.133651 <6>[ 2.459384] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10714 06:53:56.140226 <6>[ 2.469111] Trying to probe devices needed for running init ...
10715 06:53:56.184283 <6>[ 2.509861] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10716 06:53:56.338709 <6>[ 2.667687] hub 1-1:1.0: USB hub found
10717 06:53:56.341860 <6>[ 2.672213] hub 1-1:1.0: 4 ports detected
10718 06:53:56.351805 <6>[ 2.680370] hub 1-1:1.0: USB hub found
10719 06:53:56.354484 <6>[ 2.684675] hub 1-1:1.0: 4 ports detected
10720 06:53:56.464084 <6>[ 2.790238] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10721 06:53:56.490486 <6>[ 2.819557] hub 2-1:1.0: USB hub found
10722 06:53:56.494548 <6>[ 2.824054] hub 2-1:1.0: 3 ports detected
10723 06:53:56.502960 <6>[ 2.832156] hub 2-1:1.0: USB hub found
10724 06:53:56.506430 <6>[ 2.836615] hub 2-1:1.0: 3 ports detected
10725 06:53:56.680089 <6>[ 3.005907] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10726 06:53:56.812913 <6>[ 3.141398] hub 1-1.4:1.0: USB hub found
10727 06:53:56.815836 <6>[ 3.146047] hub 1-1.4:1.0: 2 ports detected
10728 06:53:56.824565 <6>[ 3.153676] hub 1-1.4:1.0: USB hub found
10729 06:53:56.828279 <6>[ 3.158244] hub 1-1.4:1.0: 2 ports detected
10730 06:53:56.896453 <6>[ 3.222019] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10731 06:53:57.123995 <6>[ 3.449927] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10732 06:53:57.316015 <6>[ 3.641911] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10733 06:54:08.432835 <6>[ 14.766888] ALSA device list:
10734 06:54:08.439493 <6>[ 14.770183] No soundcards found.
10735 06:54:08.447342 <6>[ 14.778176] Freeing unused kernel memory: 8448K
10736 06:54:08.450583 <6>[ 14.783169] Run /init as init process
10737 06:54:08.462607 Loading, please wait...
10738 06:54:08.483506 Starting version 247.3-7+deb11u2
10739 06:54:08.723175 <6>[ 15.050376] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10740 06:54:08.754117 <3>[ 15.081208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 06:54:08.760561 <3>[ 15.089374] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 06:54:08.770914 <6>[ 15.095591] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10743 06:54:08.776907 <3>[ 15.097525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 06:54:08.787376 <6>[ 15.105053] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10745 06:54:08.790609 <6>[ 15.105709] remoteproc remoteproc0: scp is available
10746 06:54:08.797555 <6>[ 15.105827] remoteproc remoteproc0: powering up scp
10747 06:54:08.803836 <6>[ 15.105832] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10748 06:54:08.810751 <6>[ 15.105861] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10749 06:54:08.820398 <6>[ 15.146376] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10750 06:54:08.831099 <3>[ 15.158399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 06:54:08.834516 <6>[ 15.165425] mc: Linux media interface: v0.10
10752 06:54:08.844505 <3>[ 15.166625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 06:54:08.851042 <3>[ 15.179503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 06:54:08.861522 <4>[ 15.180652] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10755 06:54:08.864636 <6>[ 15.180797] videodev: Linux video capture interface: v2.00
10756 06:54:08.874122 <6>[ 15.186194] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10757 06:54:08.881121 <3>[ 15.187677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 06:54:08.891206 <3>[ 15.187689] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 06:54:08.897758 <3>[ 15.187857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 06:54:08.904689 <3>[ 15.187936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 06:54:08.915645 <3>[ 15.187944] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 06:54:08.921822 <3>[ 15.187948] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 06:54:08.931607 <3>[ 15.188274] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 06:54:08.938678 <4>[ 15.195904] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10765 06:54:08.944851 <6>[ 15.196999] usbcore: registered new device driver r8152-cfgselector
10766 06:54:08.951222 <3>[ 15.201515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 06:54:08.961671 <4>[ 15.218036] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10768 06:54:08.964408 <4>[ 15.218036] Fallback method does not support PEC.
10769 06:54:08.974435 <3>[ 15.225178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 06:54:08.981365 <3>[ 15.225187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 06:54:08.988268 <6>[ 15.227112] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10772 06:54:08.997890 <6>[ 15.227158] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10773 06:54:09.004391 <6>[ 15.227193] remoteproc remoteproc0: remote processor scp is now up
10774 06:54:09.010634 <6>[ 15.235750] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10775 06:54:09.020710 <3>[ 15.241406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 06:54:09.027045 <3>[ 15.241574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 06:54:09.037923 <3>[ 15.250966] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10778 06:54:09.044866 <6>[ 15.252498] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10779 06:54:09.051414 <6>[ 15.275042] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10780 06:54:09.061516 <6>[ 15.282066] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10781 06:54:09.067985 <6>[ 15.287677] pci_bus 0000:00: root bus resource [bus 00-ff]
10782 06:54:09.074721 <6>[ 15.301506] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10783 06:54:09.084381 <6>[ 15.302115] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10784 06:54:09.091336 <6>[ 15.309342] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10785 06:54:09.101328 <6>[ 15.317822] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10786 06:54:09.111327 <6>[ 15.324467] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10787 06:54:09.121437 <4>[ 15.338666] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10788 06:54:09.128231 <6>[ 15.339489] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10789 06:54:09.134606 <4>[ 15.347671] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10790 06:54:09.141140 <6>[ 15.355808] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10791 06:54:09.151620 <3>[ 15.376334] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10792 06:54:09.154488 <6>[ 15.380955] pci 0000:00:00.0: supports D1 D2
10793 06:54:09.161225 <6>[ 15.381710] Bluetooth: Core ver 2.22
10794 06:54:09.164334 <6>[ 15.381820] NET: Registered PF_BLUETOOTH protocol family
10795 06:54:09.170603 <6>[ 15.381823] Bluetooth: HCI device and connection manager initialized
10796 06:54:09.177802 <6>[ 15.381854] Bluetooth: HCI socket layer initialized
10797 06:54:09.180510 <6>[ 15.381860] Bluetooth: L2CAP socket layer initialized
10798 06:54:09.187620 <6>[ 15.381893] Bluetooth: SCO socket layer initialized
10799 06:54:09.194649 <6>[ 15.413020] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10800 06:54:09.197272 <6>[ 15.413693] r8152 2-1.3:1.0 eth0: v1.12.13
10801 06:54:09.204201 <6>[ 15.413757] usbcore: registered new interface driver r8152
10802 06:54:09.211180 <6>[ 15.420926] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10803 06:54:09.221077 <6>[ 15.422333] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10804 06:54:09.223848 <6>[ 15.448236] usbcore: registered new interface driver btusb
10805 06:54:09.237800 <4>[ 15.448811] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10806 06:54:09.240442 <3>[ 15.448824] Bluetooth: hci0: Failed to load firmware file (-2)
10807 06:54:09.247365 <3>[ 15.448829] Bluetooth: hci0: Failed to set up firmware (-2)
10808 06:54:09.257151 <4>[ 15.448834] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10809 06:54:09.270722 <6>[ 15.450935] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10810 06:54:09.276955 <6>[ 15.451129] usbcore: registered new interface driver uvcvideo
10811 06:54:09.283826 <6>[ 15.456411] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10812 06:54:09.290049 <6>[ 15.456572] usbcore: registered new interface driver cdc_ether
10813 06:54:09.296735 <6>[ 15.457071] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10814 06:54:09.299887 <6>[ 15.462884] usbcore: registered new interface driver r8153_ecm
10815 06:54:09.310579 <6>[ 15.470660] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10816 06:54:09.313493 <6>[ 15.490988] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10817 06:54:09.323471 <6>[ 15.491415] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10818 06:54:09.330137 <6>[ 15.658193] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10819 06:54:09.333777 <6>[ 15.665976] pci 0000:01:00.0: supports D1 D2
10820 06:54:09.343245 <6>[ 15.670515] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10821 06:54:09.358945 <6>[ 15.685803] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10822 06:54:09.365299 <6>[ 15.692699] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10823 06:54:09.371777 <6>[ 15.700779] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10824 06:54:09.381459 <6>[ 15.708776] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10825 06:54:09.388957 <6>[ 15.716777] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10826 06:54:09.398036 <6>[ 15.724778] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10827 06:54:09.401861 <6>[ 15.732778] pci 0000:00:00.0: PCI bridge to [bus 01]
10828 06:54:09.411717 <6>[ 15.737994] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10829 06:54:09.418385 <6>[ 15.746121] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10830 06:54:09.424812 <6>[ 15.752965] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10831 06:54:09.431350 <6>[ 15.759572] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10832 06:54:09.445526 <5>[ 15.772999] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10833 06:54:09.465343 <5>[ 15.792323] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10834 06:54:09.471594 <5>[ 15.799616] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10835 06:54:09.481909 <4>[ 15.808049] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10836 06:54:09.485411 <6>[ 15.816964] cfg80211: failed to load regulatory.db
10837 06:54:09.528919 <6>[ 15.856138] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10838 06:54:09.535375 <6>[ 15.863638] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10839 06:54:09.559520 <6>[ 15.890269] mt7921e 0000:01:00.0: ASIC revision: 79610010
10840 06:54:09.662132 <6>[ 15.989214] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10841 06:54:09.665671 <6>[ 15.989214]
10842 06:54:09.682043 Begin: Loading essential drivers ... done.
10843 06:54:09.684494 Begin: Running /scripts/init-premount ... done.
10844 06:54:09.690955 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10845 06:54:09.701565 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10846 06:54:09.704627 Device /sys/class/net/enx002432307852 found
10847 06:54:09.705182 done.
10848 06:54:09.783346 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10849 06:54:09.931155 <6>[ 16.258211] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10850 06:54:10.710980 <6>[ 17.042015] r8152 2-1.3:1.0 enx002432307852: carrier on
10851 06:54:10.777973 <6>[ 17.108578] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10852 06:54:10.834612 IP-Config: no response after 2 secs - giving up
10853 06:54:10.870990 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:3d mtu 1500 DHCP
10854 06:54:11.558366 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10855 06:54:11.562141 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10856 06:54:11.567758 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10857 06:54:11.578480 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10858 06:54:11.584802 host : mt8192-asurada-spherion-r0-cbg-3
10859 06:54:11.591513 domain : lava-rack
10860 06:54:11.594623 rootserver: 192.168.201.1 rootpath:
10861 06:54:11.595353 filename :
10862 06:54:11.736831 done.
10863 06:54:11.745983 Begin: Running /scripts/nfs-bottom ... done.
10864 06:54:11.766028 Begin: Running /scripts/init-bottom ... done.
10865 06:54:13.027889 <6>[ 19.358698] NET: Registered PF_INET6 protocol family
10866 06:54:13.035746 <6>[ 19.366443] Segment Routing with IPv6
10867 06:54:13.038758 <6>[ 19.370430] In-situ OAM (IOAM) with IPv6
10868 06:54:13.176826 <30>[ 19.490659] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10869 06:54:13.184524 <30>[ 19.515044] systemd[1]: Detected architecture arm64.
10870 06:54:13.206511
10871 06:54:13.210393 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10872 06:54:13.211016
10873 06:54:13.225832 <30>[ 19.556898] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10874 06:54:14.180342 <30>[ 20.508366] systemd[1]: Queued start job for default target Graphical Interface.
10875 06:54:14.217042 <30>[ 20.548271] systemd[1]: Created slice system-getty.slice.
10876 06:54:14.223713 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10877 06:54:14.240304 <30>[ 20.571252] systemd[1]: Created slice system-modprobe.slice.
10878 06:54:14.246782 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10879 06:54:14.265110 <30>[ 20.595935] systemd[1]: Created slice system-serial\x2dgetty.slice.
10880 06:54:14.275430 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10881 06:54:14.288339 <30>[ 20.618962] systemd[1]: Created slice User and Session Slice.
10882 06:54:14.294615 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10883 06:54:14.314894 <30>[ 20.642758] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10884 06:54:14.324985 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10885 06:54:14.343331 <30>[ 20.670661] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10886 06:54:14.349372 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10887 06:54:14.373145 <30>[ 20.698043] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10888 06:54:14.380262 <30>[ 20.710207] systemd[1]: Reached target Local Encrypted Volumes.
10889 06:54:14.387038 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10890 06:54:14.403060 <30>[ 20.734131] systemd[1]: Reached target Paths.
10891 06:54:14.406256 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10892 06:54:14.422902 <30>[ 20.753912] systemd[1]: Reached target Remote File Systems.
10893 06:54:14.429181 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10894 06:54:14.442503 <30>[ 20.773870] systemd[1]: Reached target Slices.
10895 06:54:14.445823 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10896 06:54:14.463004 <30>[ 20.793967] systemd[1]: Reached target Swap.
10897 06:54:14.466371 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10898 06:54:14.486357 <30>[ 20.814309] systemd[1]: Listening on initctl Compatibility Named Pipe.
10899 06:54:14.493195 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10900 06:54:14.499575 <30>[ 20.830637] systemd[1]: Listening on Journal Audit Socket.
10901 06:54:14.506017 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10902 06:54:14.525089 <30>[ 20.855546] systemd[1]: Listening on Journal Socket (/dev/log).
10903 06:54:14.531134 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10904 06:54:14.547097 <30>[ 20.878457] systemd[1]: Listening on Journal Socket.
10905 06:54:14.553606 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10906 06:54:14.568485 <30>[ 20.899597] systemd[1]: Listening on Network Service Netlink Socket.
10907 06:54:14.579005 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10908 06:54:14.594487 <30>[ 20.925306] systemd[1]: Listening on udev Control Socket.
10909 06:54:14.600860 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10910 06:54:14.615563 <30>[ 20.946337] systemd[1]: Listening on udev Kernel Socket.
10911 06:54:14.621674 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10912 06:54:14.674959 <30>[ 21.006124] systemd[1]: Mounting Huge Pages File System...
10913 06:54:14.681338 Mounting [0;1;39mHuge Pages File System[0m...
10914 06:54:14.698893 <30>[ 21.030253] systemd[1]: Mounting POSIX Message Queue File System...
10915 06:54:14.705434 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10916 06:54:14.727047 <30>[ 21.058310] systemd[1]: Mounting Kernel Debug File System...
10917 06:54:14.733536 Mounting [0;1;39mKernel Debug File System[0m...
10918 06:54:14.750114 <30>[ 21.078396] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10919 06:54:14.762630 <30>[ 21.090789] systemd[1]: Starting Create list of static device nodes for the current kernel...
10920 06:54:14.769073 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10921 06:54:14.790425 <30>[ 21.121627] systemd[1]: Starting Load Kernel Module configfs...
10922 06:54:14.796326 Starting [0;1;39mLoad Kernel Module configfs[0m...
10923 06:54:14.815135 <30>[ 21.146450] systemd[1]: Starting Load Kernel Module drm...
10924 06:54:14.821766 Starting [0;1;39mLoad Kernel Module drm[0m...
10925 06:54:14.838381 <30>[ 21.169465] systemd[1]: Starting Load Kernel Module fuse...
10926 06:54:14.844872 Starting [0;1;39mLoad Kernel Module fuse[0m...
10927 06:54:14.877408 <30>[ 21.205315] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10928 06:54:14.884130 <6>[ 21.215511] fuse: init (API version 7.37)
10929 06:54:14.919008 <30>[ 21.250429] systemd[1]: Starting Journal Service...
10930 06:54:14.922632 Starting [0;1;39mJournal Service[0m...
10931 06:54:14.948741 <30>[ 21.280109] systemd[1]: Starting Load Kernel Modules...
10932 06:54:14.955660 Starting [0;1;39mLoad Kernel Modules[0m...
10933 06:54:15.015508 <30>[ 21.343062] systemd[1]: Starting Remount Root and Kernel File Systems...
10934 06:54:15.021633 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10935 06:54:15.039382 <30>[ 21.370762] systemd[1]: Starting Coldplug All udev Devices...
10936 06:54:15.045980 Starting [0;1;39mColdplug All udev Devices[0m...
10937 06:54:15.063072 <30>[ 21.394201] systemd[1]: Mounted Huge Pages File System.
10938 06:54:15.069360 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10939 06:54:15.087155 <3>[ 21.414636] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 06:54:15.094066 <30>[ 21.424310] systemd[1]: Mounted POSIX Message Queue File System.
10941 06:54:15.100191 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10942 06:54:15.115606 <30>[ 21.446063] systemd[1]: Mounted Kernel Debug File System.
10943 06:54:15.125449 <3>[ 21.448582] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 06:54:15.131886 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10945 06:54:15.150657 <30>[ 21.478723] systemd[1]: Finished Create list of static device nodes for the current kernel.
10946 06:54:15.161068 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10947 06:54:15.171879 <3>[ 21.497497] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 06:54:15.177560 <30>[ 21.507644] systemd[1]: modprobe@configfs.service: Succeeded.
10949 06:54:15.184747 <30>[ 21.514357] systemd[1]: Finished Load Kernel Module configfs.
10950 06:54:15.191577 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10951 06:54:15.198196 <3>[ 21.527230] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 06:54:15.207792 <30>[ 21.539033] systemd[1]: modprobe@drm.service: Succeeded.
10953 06:54:15.215223 <30>[ 21.545259] systemd[1]: Finished Load Kernel Module drm.
10954 06:54:15.221301 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10955 06:54:15.228206 <3>[ 21.556734] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 06:54:15.235448 <30>[ 21.566522] systemd[1]: modprobe@fuse.service: Succeeded.
10957 06:54:15.242145 <30>[ 21.572874] systemd[1]: Finished Load Kernel Module fuse.
10958 06:54:15.249952 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10959 06:54:15.259508 <3>[ 21.585761] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 06:54:15.266356 <30>[ 21.596430] systemd[1]: Finished Load Kernel Modules.
10961 06:54:15.272491 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10962 06:54:15.287367 <3>[ 21.615364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 06:54:15.298966 <30>[ 21.626637] systemd[1]: Finished Remount Root and Kernel File Systems.
10964 06:54:15.305304 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10965 06:54:15.318177 <3>[ 21.645522] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 06:54:15.348209 <3>[ 21.676088] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 06:54:15.354917 <30>[ 21.680676] systemd[1]: Mounting FUSE Control File System...
10968 06:54:15.361430 Mounting [0;1;39mFUSE Control File System[0m...
10969 06:54:15.377323 <3>[ 21.705089] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 06:54:15.388642 <30>[ 21.716674] systemd[1]: Mounting Kernel Configuration File System...
10971 06:54:15.392036 Mounting [0;1;39mKernel Configuration File System[0m...
10972 06:54:15.416810 <30>[ 21.744732] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10973 06:54:15.426513 <30>[ 21.754067] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10974 06:54:15.471636 <30>[ 21.802683] systemd[1]: Starting Load/Save Random Seed...
10975 06:54:15.478194 Starting [0;1;39mLoad/Save Random Seed[0m...
10976 06:54:15.501008 <4>[ 21.821679] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10977 06:54:15.506883 <30>[ 21.824537] systemd[1]: Starting Apply Kernel Variables...
10978 06:54:15.513401 <3>[ 21.837379] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10979 06:54:15.520005 Starting [0;1;39mApply Kernel Variables[0m...
10980 06:54:15.539865 <30>[ 21.871172] systemd[1]: Starting Create System Users...
10981 06:54:15.546134 Starting [0;1;39mCreate System Users[0m...
10982 06:54:15.561205 <30>[ 21.892369] systemd[1]: Started Journal Service.
10983 06:54:15.567568 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10984 06:54:15.591325 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10985 06:54:15.606888 See 'systemctl status systemd-udev-trigger.service' for details.
10986 06:54:15.627335 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10987 06:54:15.642740 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10988 06:54:15.660170 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10989 06:54:15.676631 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10990 06:54:15.727673 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10991 06:54:15.743817 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10992 06:54:15.761018 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10993 06:54:15.787425 <46>[ 22.115880] systemd-journald[291]: Received client request to flush runtime journal.
10994 06:54:16.969114 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10995 06:54:16.986366 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10996 06:54:17.006062 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10997 06:54:17.054034 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10998 06:54:17.187740 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10999 06:54:17.235236 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11000 06:54:17.356275 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11001 06:54:17.407850 Starting [0;1;39mNetwork Service[0m...
11002 06:54:17.714110 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11003 06:54:17.736146 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11004 06:54:17.795280 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11005 06:54:18.077959 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11006 06:54:18.097325 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11007 06:54:18.127710 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11008 06:54:18.149313 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11009 06:54:18.170945 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11010 06:54:18.190935 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11011 06:54:18.206861 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11012 06:54:18.287407 Starting [0;1;39mNetwork Name Resolution[0m...
11013 06:54:18.317385 Starting [0;1;39mNetwork Time Synchronization[0m...
11014 06:54:18.339273 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11015 06:54:18.391522 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11016 06:54:18.794969 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11017 06:54:18.810782 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11018 06:54:18.829617 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11019 06:54:18.842915 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11020 06:54:18.858028 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11021 06:54:18.917724 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11022 06:54:18.945805 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11023 06:54:18.964347 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11024 06:54:19.323106 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11025 06:54:19.337857 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11026 06:54:19.594899 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11027 06:54:19.605765 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11028 06:54:19.621640 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11029 06:54:19.678634 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11030 06:54:20.078248 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11031 06:54:20.166329 Starting [0;1;39mUser Login Management[0m...
11032 06:54:20.182935 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11033 06:54:20.200958 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11034 06:54:20.217385 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11035 06:54:20.250441 Starting [0;1;39mPermit User Sessions[0m...
11036 06:54:20.356303 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11037 06:54:20.370141 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11038 06:54:20.407194 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11039 06:54:20.426222 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11040 06:54:20.442167 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11041 06:54:20.463592 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11042 06:54:20.479138 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11043 06:54:20.494759 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11044 06:54:20.560204 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11045 06:54:20.635575 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11046 06:54:20.745439
11047 06:54:20.745967
11048 06:54:20.748400 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11049 06:54:20.748818
11050 06:54:20.751585 debian-bullseye-arm64 login: root (automatic login)
11051 06:54:20.752001
11052 06:54:20.752328
11053 06:54:21.190085 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
11054 06:54:21.190620
11055 06:54:21.197564 The programs included with the Debian GNU/Linux system are free software;
11056 06:54:21.203429 the exact distribution terms for each program are described in the
11057 06:54:21.206970 individual files in /usr/share/doc/*/copyright.
11058 06:54:21.207426
11059 06:54:21.213644 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11060 06:54:21.216473 permitted by applicable law.
11061 06:54:22.292435 Matched prompt #10: / #
11063 06:54:22.293592 Setting prompt string to ['/ #']
11064 06:54:22.294027 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11066 06:54:22.295096 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11067 06:54:22.295552 start: 2.2.6 expect-shell-connection (timeout 00:02:57) [common]
11068 06:54:22.295969 Setting prompt string to ['/ #']
11069 06:54:22.296326 Forcing a shell prompt, looking for ['/ #']
11071 06:54:22.347129 / #
11072 06:54:22.347519 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11073 06:54:22.347768 Waiting using forced prompt support (timeout 00:02:30)
11074 06:54:22.353398
11075 06:54:22.354114 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11076 06:54:22.354514 start: 2.2.7 export-device-env (timeout 00:02:57) [common]
11078 06:54:22.455580 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694840/extract-nfsrootfs-kxldhbtm'
11079 06:54:22.461974 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694840/extract-nfsrootfs-kxldhbtm'
11081 06:54:22.563789 / # export NFS_SERVER_IP='192.168.201.1'
11082 06:54:22.570629 export NFS_SERVER_IP='192.168.201.1'
11083 06:54:22.571636 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11084 06:54:22.572376 end: 2.2 depthcharge-retry (duration 00:02:03) [common]
11085 06:54:22.572913 end: 2 depthcharge-action (duration 00:02:03) [common]
11086 06:54:22.573425 start: 3 lava-test-retry (timeout 00:07:18) [common]
11087 06:54:22.573917 start: 3.1 lava-test-shell (timeout 00:07:18) [common]
11088 06:54:22.574341 Using namespace: common
11090 06:54:22.675664 / # #
11091 06:54:22.676328 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11092 06:54:22.681879 #
11093 06:54:22.682829 Using /lava-12694840
11095 06:54:22.784148 / # export SHELL=/bin/bash
11096 06:54:22.790422 export SHELL=/bin/bash
11098 06:54:22.892057 / # . /lava-12694840/environment
11099 06:54:22.898869 . /lava-12694840/environment
11101 06:54:23.006234 / # /lava-12694840/bin/lava-test-runner /lava-12694840/0
11102 06:54:23.006905 Test shell timeout: 10s (minimum of the action and connection timeout)
11103 06:54:23.013193 /lava-12694840/bin/lava-test-runner /lava-12694840/0
11104 06:54:23.384125 + export TESTRUN_ID=0_timesync-off
11105 06:54:23.386581 + TESTRUN_ID=0_timesync-off
11106 06:54:23.390279 + cd /lava-12694840/0/tests/0_timesync-off
11107 06:54:23.392989 ++ cat uuid
11108 06:54:23.404230 + UUID=12694840_1.6.2.3.1
11109 06:54:23.404800 + set +x
11110 06:54:23.410712 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12694840_1.6.2.3.1>
11111 06:54:23.411400 Received signal: <STARTRUN> 0_timesync-off 12694840_1.6.2.3.1
11112 06:54:23.411781 Starting test lava.0_timesync-off (12694840_1.6.2.3.1)
11113 06:54:23.412193 Skipping test definition patterns.
11114 06:54:23.413722 + systemctl stop systemd-timesyncd
11115 06:54:23.487356 + set +x
11116 06:54:23.490849 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12694840_1.6.2.3.1>
11117 06:54:23.491540 Received signal: <ENDRUN> 0_timesync-off 12694840_1.6.2.3.1
11118 06:54:23.491953 Ending use of test pattern.
11119 06:54:23.492277 Ending test lava.0_timesync-off (12694840_1.6.2.3.1), duration 0.08
11121 06:54:23.598839 + export TESTRUN_ID=1_kselftest-dt
11122 06:54:23.601970 + TESTRUN_ID=1_kselftest-dt
11123 06:54:23.605216 + cd /lava-12694840/0/tests/1_kselftest-dt
11124 06:54:23.608611 ++ cat uuid
11125 06:54:23.619553 + UUID=12694840_1.6.2.3.5
11126 06:54:23.619983 + set +x
11127 06:54:23.626562 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12694840_1.6.2.3.5>
11128 06:54:23.627251 Received signal: <STARTRUN> 1_kselftest-dt 12694840_1.6.2.3.5
11129 06:54:23.627610 Starting test lava.1_kselftest-dt (12694840_1.6.2.3.5)
11130 06:54:23.627996 Skipping test definition patterns.
11131 06:54:23.629528 + cd ./automated/linux/kselftest/
11132 06:54:23.653400 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11133 06:54:23.713530 INFO: install_deps skipped
11134 06:54:23.854459 --2024-02-03 06:54:23-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11135 06:54:23.872659 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11136 06:54:24.006233 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11137 06:54:24.139767 HTTP request sent, awaiting response... 200 OK
11138 06:54:24.143418 Length: 2965368 (2.8M) [application/octet-stream]
11139 06:54:24.146815 Saving to: 'kselftest.tar.xz'
11140 06:54:24.147299
11141 06:54:24.147705
11142 06:54:24.407988 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11143 06:54:24.675609 kselftest.tar.xz 1%[ ] 47.81K 179KB/s
11144 06:54:24.992183 kselftest.tar.xz 7%[> ] 217.50K 408KB/s
11145 06:54:25.209029 kselftest.tar.xz 28%[====> ] 839.68K 987KB/s
11146 06:54:25.372156 kselftest.tar.xz 71%[=============> ] 2.01M 1.89MB/s
11147 06:54:25.378551 kselftest.tar.xz 100%[===================>] 2.83M 2.30MB/s in 1.2s
11148 06:54:25.378984
11149 06:54:25.636958 2024-02-03 06:54:25 (2.30 MB/s) - 'kselftest.tar.xz' saved [2965368/2965368]
11150 06:54:25.637130
11151 06:54:33.220697 skiplist:
11152 06:54:33.223752 ========================================
11153 06:54:33.227374 ========================================
11154 06:54:33.314920 ============== Tests to run ===============
11155 06:54:33.322095 ===========End Tests to run ===============
11156 06:54:33.328474 shardfile-dt fail
11157 06:54:33.357814 ./kselftest.sh: 131: cannot open /lava-12694840/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11158 06:54:33.361205 + ../../utils/send-to-lava.sh ./output/result.txt
11159 06:54:33.468427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11160 06:54:33.468885 + set +x
11161 06:54:33.469510 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11163 06:54:33.476147 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12694840_1.6.2.3.5>
11164 06:54:33.476682 <LAVA_TEST_RUNNER EXIT>
11165 06:54:33.477299 Received signal: <ENDRUN> 1_kselftest-dt 12694840_1.6.2.3.5
11166 06:54:33.477654 Ending use of test pattern.
11167 06:54:33.477957 Ending test lava.1_kselftest-dt (12694840_1.6.2.3.5), duration 9.85
11169 06:54:33.479112 ok: lava_test_shell seems to have completed
11170 06:54:33.479609 shardfile-dt: fail
11171 06:54:33.480010 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11172 06:54:33.480416 end: 3 lava-test-retry (duration 00:00:11) [common]
11173 06:54:33.480842 start: 4 finalize (timeout 00:07:07) [common]
11174 06:54:33.481294 start: 4.1 power-off (timeout 00:00:30) [common]
11175 06:54:33.482039 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11176 06:54:33.602671 >> Command sent successfully.
11177 06:54:33.606429 Returned 0 in 0 seconds
11178 06:54:33.707360 end: 4.1 power-off (duration 00:00:00) [common]
11180 06:54:33.709079 start: 4.2 read-feedback (timeout 00:07:07) [common]
11181 06:54:33.710477 Listened to connection for namespace 'common' for up to 1s
11182 06:54:33.711432 Listened to connection for namespace 'common' for up to 1s
11183 06:54:34.710732 Finalising connection for namespace 'common'
11184 06:54:34.711413 Disconnecting from shell: Finalise
11185 06:54:34.711852 / #
11186 06:54:34.812880 end: 4.2 read-feedback (duration 00:00:01) [common]
11187 06:54:34.813574 end: 4 finalize (duration 00:00:01) [common]
11188 06:54:34.814175 Cleaning after the job
11189 06:54:34.814751 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/ramdisk
11190 06:54:34.828390 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/kernel
11191 06:54:34.859506 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/dtb
11192 06:54:34.859823 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/nfsrootfs
11193 06:54:34.951467 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694840/tftp-deploy-7407rfg7/modules
11194 06:54:34.958679 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694840
11195 06:54:35.586615 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694840
11196 06:54:35.586797 Job finished correctly