Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 33
1 06:50:22.467068 lava-dispatcher, installed at version: 2023.10
2 06:50:22.467312 start: 0 validate
3 06:50:22.467502 Start time: 2024-02-03 06:50:22.467494+00:00 (UTC)
4 06:50:22.467646 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:50:22.467785 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 06:50:22.739547 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:50:22.739726 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:50:23.006404 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:50:23.006580 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:50:23.264994 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:50:23.265187 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:50:23.523272 Using caching service: 'http://localhost/cache/?uri=%s'
13 06:50:23.523472 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 06:50:23.791623 validate duration: 1.32
16 06:50:23.791886 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:50:23.791986 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:50:23.792075 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:50:23.792200 Not decompressing ramdisk as can be used compressed.
20 06:50:23.792286 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 06:50:23.792351 saving as /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/ramdisk/initrd.cpio.gz
22 06:50:23.792417 total size: 4665395 (4 MB)
23 06:50:23.793537 progress 0 % (0 MB)
24 06:50:23.795055 progress 5 % (0 MB)
25 06:50:23.796372 progress 10 % (0 MB)
26 06:50:23.797632 progress 15 % (0 MB)
27 06:50:23.798886 progress 20 % (0 MB)
28 06:50:23.800219 progress 25 % (1 MB)
29 06:50:23.801511 progress 30 % (1 MB)
30 06:50:23.802749 progress 35 % (1 MB)
31 06:50:23.804033 progress 40 % (1 MB)
32 06:50:23.805426 progress 45 % (2 MB)
33 06:50:23.806654 progress 50 % (2 MB)
34 06:50:23.808043 progress 55 % (2 MB)
35 06:50:23.809289 progress 60 % (2 MB)
36 06:50:23.810574 progress 65 % (2 MB)
37 06:50:23.811982 progress 70 % (3 MB)
38 06:50:23.813291 progress 75 % (3 MB)
39 06:50:23.814555 progress 80 % (3 MB)
40 06:50:23.815977 progress 85 % (3 MB)
41 06:50:23.817207 progress 90 % (4 MB)
42 06:50:23.818501 progress 95 % (4 MB)
43 06:50:23.819755 progress 100 % (4 MB)
44 06:50:23.819912 4 MB downloaded in 0.03 s (161.82 MB/s)
45 06:50:23.820073 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:50:23.820317 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:50:23.820407 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:50:23.820492 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:50:23.820634 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 06:50:23.820703 saving as /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/kernel/Image
52 06:50:23.820764 total size: 51532288 (49 MB)
53 06:50:23.820825 No compression specified
54 06:50:23.821957 progress 0 % (0 MB)
55 06:50:23.835232 progress 5 % (2 MB)
56 06:50:23.848932 progress 10 % (4 MB)
57 06:50:23.862381 progress 15 % (7 MB)
58 06:50:23.875927 progress 20 % (9 MB)
59 06:50:23.889397 progress 25 % (12 MB)
60 06:50:23.902732 progress 30 % (14 MB)
61 06:50:23.916466 progress 35 % (17 MB)
62 06:50:23.929983 progress 40 % (19 MB)
63 06:50:23.943550 progress 45 % (22 MB)
64 06:50:23.957173 progress 50 % (24 MB)
65 06:50:23.970818 progress 55 % (27 MB)
66 06:50:23.984349 progress 60 % (29 MB)
67 06:50:23.997822 progress 65 % (31 MB)
68 06:50:24.011054 progress 70 % (34 MB)
69 06:50:24.024578 progress 75 % (36 MB)
70 06:50:24.038152 progress 80 % (39 MB)
71 06:50:24.051670 progress 85 % (41 MB)
72 06:50:24.065337 progress 90 % (44 MB)
73 06:50:24.078952 progress 95 % (46 MB)
74 06:50:24.092342 progress 100 % (49 MB)
75 06:50:24.092608 49 MB downloaded in 0.27 s (180.79 MB/s)
76 06:50:24.092768 end: 1.2.1 http-download (duration 00:00:00) [common]
78 06:50:24.093005 end: 1.2 download-retry (duration 00:00:00) [common]
79 06:50:24.093093 start: 1.3 download-retry (timeout 00:10:00) [common]
80 06:50:24.093183 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 06:50:24.093326 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 06:50:24.093399 saving as /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/dtb/mt8192-asurada-spherion-r0.dtb
83 06:50:24.093462 total size: 47278 (0 MB)
84 06:50:24.093523 No compression specified
85 06:50:24.094675 progress 69 % (0 MB)
86 06:50:24.094951 progress 100 % (0 MB)
87 06:50:24.095107 0 MB downloaded in 0.00 s (27.44 MB/s)
88 06:50:24.095232 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:50:24.095503 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:50:24.095593 start: 1.4 download-retry (timeout 00:10:00) [common]
92 06:50:24.095676 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 06:50:24.095795 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 06:50:24.095863 saving as /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/nfsrootfs/full.rootfs.tar
95 06:50:24.095923 total size: 200813988 (191 MB)
96 06:50:24.095999 Using unxz to decompress xz
97 06:50:24.100119 progress 0 % (0 MB)
98 06:50:24.633311 progress 5 % (9 MB)
99 06:50:25.150137 progress 10 % (19 MB)
100 06:50:25.739683 progress 15 % (28 MB)
101 06:50:26.119239 progress 20 % (38 MB)
102 06:50:26.450430 progress 25 % (47 MB)
103 06:50:27.048892 progress 30 % (57 MB)
104 06:50:27.609643 progress 35 % (67 MB)
105 06:50:28.207479 progress 40 % (76 MB)
106 06:50:28.766790 progress 45 % (86 MB)
107 06:50:29.344454 progress 50 % (95 MB)
108 06:50:29.970663 progress 55 % (105 MB)
109 06:50:30.629066 progress 60 % (114 MB)
110 06:50:30.745599 progress 65 % (124 MB)
111 06:50:30.886199 progress 70 % (134 MB)
112 06:50:30.981689 progress 75 % (143 MB)
113 06:50:31.052094 progress 80 % (153 MB)
114 06:50:31.120365 progress 85 % (162 MB)
115 06:50:31.220337 progress 90 % (172 MB)
116 06:50:31.496255 progress 95 % (181 MB)
117 06:50:32.070124 progress 100 % (191 MB)
118 06:50:32.075279 191 MB downloaded in 7.98 s (24.00 MB/s)
119 06:50:32.075598 end: 1.4.1 http-download (duration 00:00:08) [common]
121 06:50:32.075861 end: 1.4 download-retry (duration 00:00:08) [common]
122 06:50:32.075953 start: 1.5 download-retry (timeout 00:09:52) [common]
123 06:50:32.076041 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 06:50:32.076200 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 06:50:32.076269 saving as /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/modules/modules.tar
126 06:50:32.076332 total size: 8624064 (8 MB)
127 06:50:32.076397 Using unxz to decompress xz
128 06:50:32.080494 progress 0 % (0 MB)
129 06:50:32.101337 progress 5 % (0 MB)
130 06:50:32.124666 progress 10 % (0 MB)
131 06:50:32.147818 progress 15 % (1 MB)
132 06:50:32.171087 progress 20 % (1 MB)
133 06:50:32.195571 progress 25 % (2 MB)
134 06:50:32.221351 progress 30 % (2 MB)
135 06:50:32.247317 progress 35 % (2 MB)
136 06:50:32.270596 progress 40 % (3 MB)
137 06:50:32.669946 progress 45 % (3 MB)
138 06:50:32.695240 progress 50 % (4 MB)
139 06:50:32.719395 progress 55 % (4 MB)
140 06:50:32.744752 progress 60 % (4 MB)
141 06:50:32.772051 progress 65 % (5 MB)
142 06:50:32.796966 progress 70 % (5 MB)
143 06:50:32.820602 progress 75 % (6 MB)
144 06:50:32.852296 progress 80 % (6 MB)
145 06:50:32.883932 progress 85 % (7 MB)
146 06:50:32.911988 progress 90 % (7 MB)
147 06:50:32.943964 progress 95 % (7 MB)
148 06:50:32.972626 progress 100 % (8 MB)
149 06:50:32.977686 8 MB downloaded in 0.90 s (9.12 MB/s)
150 06:50:32.978005 end: 1.5.1 http-download (duration 00:00:01) [common]
152 06:50:32.978400 end: 1.5 download-retry (duration 00:00:01) [common]
153 06:50:32.978524 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 06:50:32.978649 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 06:50:36.558534 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12694815/extract-nfsrootfs-vip9dcsz
156 06:50:36.558721 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 06:50:36.558822 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 06:50:36.558997 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94
159 06:50:36.559129 makedir: /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin
160 06:50:36.559231 makedir: /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/tests
161 06:50:36.559331 makedir: /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/results
162 06:50:36.559687 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-add-keys
163 06:50:36.559864 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-add-sources
164 06:50:36.559993 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-background-process-start
165 06:50:36.560122 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-background-process-stop
166 06:50:36.560248 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-common-functions
167 06:50:36.560374 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-echo-ipv4
168 06:50:36.560500 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-install-packages
169 06:50:36.560671 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-installed-packages
170 06:50:36.560797 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-os-build
171 06:50:36.560922 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-probe-channel
172 06:50:36.561049 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-probe-ip
173 06:50:36.561175 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-target-ip
174 06:50:36.561298 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-target-mac
175 06:50:36.561423 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-target-storage
176 06:50:36.561549 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-test-case
177 06:50:36.561675 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-test-event
178 06:50:36.561859 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-test-feedback
179 06:50:36.562012 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-test-raise
180 06:50:36.562134 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-test-reference
181 06:50:36.562257 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-test-runner
182 06:50:36.562380 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-test-set
183 06:50:36.562503 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-test-shell
184 06:50:36.562630 Updating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-add-keys (debian)
185 06:50:36.562780 Updating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-add-sources (debian)
186 06:50:36.562929 Updating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-install-packages (debian)
187 06:50:36.563069 Updating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-installed-packages (debian)
188 06:50:36.563216 Updating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/bin/lava-os-build (debian)
189 06:50:36.563338 Creating /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/environment
190 06:50:36.563481 LAVA metadata
191 06:50:36.563552 - LAVA_JOB_ID=12694815
192 06:50:36.563616 - LAVA_DISPATCHER_IP=192.168.201.1
193 06:50:36.563716 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 06:50:36.563785 skipped lava-vland-overlay
195 06:50:36.563860 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 06:50:36.563969 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 06:50:36.564029 skipped lava-multinode-overlay
198 06:50:36.564102 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 06:50:36.564179 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 06:50:36.564251 Loading test definitions
201 06:50:36.564339 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 06:50:36.564411 Using /lava-12694815 at stage 0
203 06:50:36.564690 uuid=12694815_1.6.2.3.1 testdef=None
204 06:50:36.564777 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 06:50:36.564864 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 06:50:36.565312 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 06:50:36.565528 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 06:50:36.566078 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 06:50:36.566302 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 06:50:36.566918 runner path: /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/0/tests/0_timesync-off test_uuid 12694815_1.6.2.3.1
213 06:50:36.567071 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 06:50:36.567293 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 06:50:36.567513 Using /lava-12694815 at stage 0
217 06:50:36.567637 Fetching tests from https://github.com/kernelci/test-definitions.git
218 06:50:36.567753 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/0/tests/1_kselftest-rtc'
219 06:50:40.248054 Running '/usr/bin/git checkout kernelci.org
220 06:50:40.394580 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 06:50:40.395336 uuid=12694815_1.6.2.3.5 testdef=None
222 06:50:40.395542 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 06:50:40.395793 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 06:50:40.396542 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 06:50:40.396775 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 06:50:40.397748 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 06:50:40.397994 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 06:50:40.398944 runner path: /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/0/tests/1_kselftest-rtc test_uuid 12694815_1.6.2.3.5
232 06:50:40.399044 BOARD='mt8192-asurada-spherion-r0'
233 06:50:40.399122 BRANCH='cip'
234 06:50:40.399221 SKIPFILE='/dev/null'
235 06:50:40.399318 SKIP_INSTALL='True'
236 06:50:40.399443 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 06:50:40.399545 TST_CASENAME=''
238 06:50:40.399641 TST_CMDFILES='rtc'
239 06:50:40.399842 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 06:50:40.400202 Creating lava-test-runner.conf files
242 06:50:40.400305 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694815/lava-overlay-i1mwzp94/lava-12694815/0 for stage 0
243 06:50:40.400447 - 0_timesync-off
244 06:50:40.400552 - 1_kselftest-rtc
245 06:50:40.400697 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 06:50:40.400829 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 06:50:47.929056 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 06:50:47.929238 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 06:50:47.929360 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 06:50:47.929490 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 06:50:47.929615 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 06:50:48.051930 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 06:50:48.052310 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 06:50:48.052429 extracting modules file /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694815/extract-nfsrootfs-vip9dcsz
255 06:50:48.320655 extracting modules file /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694815/extract-overlay-ramdisk-pqs6s8kp/ramdisk
256 06:50:48.586929 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 06:50:48.587125 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 06:50:48.587248 [common] Applying overlay to NFS
259 06:50:48.587347 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694815/compress-overlay-gnqkqf1c/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694815/extract-nfsrootfs-vip9dcsz
260 06:50:49.558736 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 06:50:49.558904 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 06:50:49.559000 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 06:50:49.559095 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 06:50:49.559177 Building ramdisk /var/lib/lava/dispatcher/tmp/12694815/extract-overlay-ramdisk-pqs6s8kp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694815/extract-overlay-ramdisk-pqs6s8kp/ramdisk
265 06:50:49.863879 >> 119430 blocks
266 06:50:51.831524 rename /var/lib/lava/dispatcher/tmp/12694815/extract-overlay-ramdisk-pqs6s8kp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/ramdisk/ramdisk.cpio.gz
267 06:50:51.831963 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 06:50:51.832088 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 06:50:51.832189 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 06:50:51.832301 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/kernel/Image'
271 06:51:04.428848 Returned 0 in 12 seconds
272 06:51:04.529682 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/kernel/image.itb
273 06:51:04.898019 output: FIT description: Kernel Image image with one or more FDT blobs
274 06:51:04.898383 output: Created: Sat Feb 3 06:51:04 2024
275 06:51:04.898457 output: Image 0 (kernel-1)
276 06:51:04.898523 output: Description:
277 06:51:04.898586 output: Created: Sat Feb 3 06:51:04 2024
278 06:51:04.898648 output: Type: Kernel Image
279 06:51:04.898708 output: Compression: lzma compressed
280 06:51:04.898768 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
281 06:51:04.898826 output: Architecture: AArch64
282 06:51:04.898884 output: OS: Linux
283 06:51:04.898941 output: Load Address: 0x00000000
284 06:51:04.898999 output: Entry Point: 0x00000000
285 06:51:04.899057 output: Hash algo: crc32
286 06:51:04.899113 output: Hash value: 380e7c3c
287 06:51:04.899169 output: Image 1 (fdt-1)
288 06:51:04.899222 output: Description: mt8192-asurada-spherion-r0
289 06:51:04.899275 output: Created: Sat Feb 3 06:51:04 2024
290 06:51:04.899328 output: Type: Flat Device Tree
291 06:51:04.899399 output: Compression: uncompressed
292 06:51:04.899455 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 06:51:04.899509 output: Architecture: AArch64
294 06:51:04.899562 output: Hash algo: crc32
295 06:51:04.899616 output: Hash value: cc4352de
296 06:51:04.899669 output: Image 2 (ramdisk-1)
297 06:51:04.899722 output: Description: unavailable
298 06:51:04.899774 output: Created: Sat Feb 3 06:51:04 2024
299 06:51:04.899828 output: Type: RAMDisk Image
300 06:51:04.899881 output: Compression: Unknown Compression
301 06:51:04.899933 output: Data Size: 17798580 Bytes = 17381.43 KiB = 16.97 MiB
302 06:51:04.899987 output: Architecture: AArch64
303 06:51:04.900040 output: OS: Linux
304 06:51:04.900093 output: Load Address: unavailable
305 06:51:04.900146 output: Entry Point: unavailable
306 06:51:04.900198 output: Hash algo: crc32
307 06:51:04.900251 output: Hash value: 836c7091
308 06:51:04.900304 output: Default Configuration: 'conf-1'
309 06:51:04.900356 output: Configuration 0 (conf-1)
310 06:51:04.900409 output: Description: mt8192-asurada-spherion-r0
311 06:51:04.900462 output: Kernel: kernel-1
312 06:51:04.900515 output: Init Ramdisk: ramdisk-1
313 06:51:04.900567 output: FDT: fdt-1
314 06:51:04.900620 output: Loadables: kernel-1
315 06:51:04.900673 output:
316 06:51:04.900876 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 06:51:04.900972 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 06:51:04.901079 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 06:51:04.901174 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 06:51:04.901256 No LXC device requested
321 06:51:04.901338 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 06:51:04.901421 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 06:51:04.901501 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 06:51:04.901575 Checking files for TFTP limit of 4294967296 bytes.
325 06:51:04.902071 end: 1 tftp-deploy (duration 00:00:41) [common]
326 06:51:04.902175 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 06:51:04.902270 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 06:51:04.902396 substitutions:
329 06:51:04.902466 - {DTB}: 12694815/tftp-deploy-s18jvg7m/dtb/mt8192-asurada-spherion-r0.dtb
330 06:51:04.902533 - {INITRD}: 12694815/tftp-deploy-s18jvg7m/ramdisk/ramdisk.cpio.gz
331 06:51:04.902593 - {KERNEL}: 12694815/tftp-deploy-s18jvg7m/kernel/Image
332 06:51:04.902651 - {LAVA_MAC}: None
333 06:51:04.902709 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12694815/extract-nfsrootfs-vip9dcsz
334 06:51:04.902765 - {NFS_SERVER_IP}: 192.168.201.1
335 06:51:04.902820 - {PRESEED_CONFIG}: None
336 06:51:04.902876 - {PRESEED_LOCAL}: None
337 06:51:04.902932 - {RAMDISK}: 12694815/tftp-deploy-s18jvg7m/ramdisk/ramdisk.cpio.gz
338 06:51:04.902987 - {ROOT_PART}: None
339 06:51:04.903044 - {ROOT}: None
340 06:51:04.903099 - {SERVER_IP}: 192.168.201.1
341 06:51:04.903154 - {TEE}: None
342 06:51:04.903209 Parsed boot commands:
343 06:51:04.903262 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 06:51:04.903454 Parsed boot commands: tftpboot 192.168.201.1 12694815/tftp-deploy-s18jvg7m/kernel/image.itb 12694815/tftp-deploy-s18jvg7m/kernel/cmdline
345 06:51:04.903547 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 06:51:04.903633 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 06:51:04.903728 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 06:51:04.903824 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 06:51:04.903902 Not connected, no need to disconnect.
350 06:51:04.903979 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 06:51:04.904064 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 06:51:04.904135 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 06:51:04.908142 Setting prompt string to ['lava-test: # ']
354 06:51:04.908522 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 06:51:04.908634 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 06:51:04.908780 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 06:51:04.908874 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 06:51:04.909075 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 06:51:10.036552 >> Command sent successfully.
360 06:51:10.042690 Returned 0 in 5 seconds
361 06:51:10.143486 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 06:51:10.144889 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 06:51:10.145492 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 06:51:10.146185 Setting prompt string to 'Starting depthcharge on Spherion...'
366 06:51:10.146544 Changing prompt to 'Starting depthcharge on Spherion...'
367 06:51:10.146923 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 06:51:10.148212 [Enter `^Ec?' for help]
369 06:51:10.314252
370 06:51:10.314851
371 06:51:10.315551 F0: 102B 0000
372 06:51:10.316254
373 06:51:10.316698 F3: 1001 0000 [0200]
374 06:51:10.317401
375 06:51:10.317867 F3: 1001 0000
376 06:51:10.318246
377 06:51:10.318593 F7: 102D 0000
378 06:51:10.318932
379 06:51:10.319685 F1: 0000 0000
380 06:51:10.320055
381 06:51:10.320360 V0: 0000 0000 [0001]
382 06:51:10.320772
383 06:51:10.323931 00: 0007 8000
384 06:51:10.324476
385 06:51:10.324890 01: 0000 0000
386 06:51:10.325226
387 06:51:10.326346 BP: 0C00 0209 [0000]
388 06:51:10.326773
389 06:51:10.327114 G0: 1182 0000
390 06:51:10.327508
391 06:51:10.329889 EC: 0000 0021 [4000]
392 06:51:10.330315
393 06:51:10.330655 S7: 0000 0000 [0000]
394 06:51:10.330974
395 06:51:10.333953 CC: 0000 0000 [0001]
396 06:51:10.334477
397 06:51:10.334821 T0: 0000 0040 [010F]
398 06:51:10.335157
399 06:51:10.335504 Jump to BL
400 06:51:10.335812
401 06:51:10.360401
402 06:51:10.360914
403 06:51:10.361262
404 06:51:10.367451 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 06:51:10.370708 ARM64: Exception handlers installed.
406 06:51:10.374365 ARM64: Testing exception
407 06:51:10.377688 ARM64: Done test exception
408 06:51:10.384021 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 06:51:10.394848 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 06:51:10.401167 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 06:51:10.411122 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 06:51:10.418467 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 06:51:10.428607 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 06:51:10.438444 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 06:51:10.445191 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 06:51:10.463591 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 06:51:10.467018 WDT: Last reset was cold boot
418 06:51:10.470412 SPI1(PAD0) initialized at 2873684 Hz
419 06:51:10.473429 SPI5(PAD0) initialized at 992727 Hz
420 06:51:10.476796 VBOOT: Loading verstage.
421 06:51:10.483426 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 06:51:10.486574 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 06:51:10.489845 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 06:51:10.493413 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 06:51:10.501004 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 06:51:10.507319 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 06:51:10.518953 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 06:51:10.519574
429 06:51:10.519957
430 06:51:10.528963 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 06:51:10.532022 ARM64: Exception handlers installed.
432 06:51:10.535400 ARM64: Testing exception
433 06:51:10.535878 ARM64: Done test exception
434 06:51:10.542591 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 06:51:10.545747 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 06:51:10.559540 Probing TPM: . done!
437 06:51:10.560186 TPM ready after 0 ms
438 06:51:10.567729 Connected to device vid:did:rid of 1ae0:0028:00
439 06:51:10.574422 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 06:51:10.631848 Initialized TPM device CR50 revision 0
441 06:51:10.642408 tlcl_send_startup: Startup return code is 0
442 06:51:10.643040 TPM: setup succeeded
443 06:51:10.654239 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 06:51:10.663203 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 06:51:10.673910 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 06:51:10.683593 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 06:51:10.687208 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 06:51:10.695158 in-header: 03 07 00 00 08 00 00 00
449 06:51:10.698771 in-data: aa e4 47 04 13 02 00 00
450 06:51:10.702055 Chrome EC: UHEPI supported
451 06:51:10.709647 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 06:51:10.713518 in-header: 03 95 00 00 08 00 00 00
453 06:51:10.716497 in-data: 18 20 20 08 00 00 00 00
454 06:51:10.717176 Phase 1
455 06:51:10.720397 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 06:51:10.727826 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 06:51:10.731330 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 06:51:10.734437 Recovery requested (1009000e)
459 06:51:10.743067 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 06:51:10.748601 tlcl_extend: response is 0
461 06:51:10.758328 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 06:51:10.763885 tlcl_extend: response is 0
463 06:51:10.770795 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 06:51:10.790651 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 06:51:10.797166 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 06:51:10.797737
467 06:51:10.798112
468 06:51:10.807335 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 06:51:10.811189 ARM64: Exception handlers installed.
470 06:51:10.813570 ARM64: Testing exception
471 06:51:10.814141 ARM64: Done test exception
472 06:51:10.835789 pmic_efuse_setting: Set efuses in 11 msecs
473 06:51:10.839758 pmwrap_interface_init: Select PMIF_VLD_RDY
474 06:51:10.846406 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 06:51:10.849489 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 06:51:10.856119 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 06:51:10.859878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 06:51:10.862966 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 06:51:10.870024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 06:51:10.874654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 06:51:10.877919 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 06:51:10.885617 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 06:51:10.889174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 06:51:10.892941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 06:51:10.896546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 06:51:10.899658 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 06:51:10.907623 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 06:51:10.915545 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 06:51:10.918709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 06:51:10.926478 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 06:51:10.929593 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 06:51:10.937686 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 06:51:10.940608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 06:51:10.948163 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 06:51:10.951472 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 06:51:10.959140 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 06:51:10.962917 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 06:51:10.970171 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 06:51:10.973841 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 06:51:10.981061 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 06:51:10.984299 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 06:51:10.992093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 06:51:10.995844 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 06:51:10.999657 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 06:51:11.003298 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 06:51:11.010314 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 06:51:11.014064 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 06:51:11.021931 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 06:51:11.025093 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 06:51:11.028956 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 06:51:11.036361 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 06:51:11.040300 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 06:51:11.043848 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 06:51:11.047457 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 06:51:11.051000 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 06:51:11.058531 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 06:51:11.061797 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 06:51:11.065618 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 06:51:11.070008 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 06:51:11.072961 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 06:51:11.080440 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 06:51:11.083505 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 06:51:11.087082 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 06:51:11.090729 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 06:51:11.098248 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 06:51:11.109149 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 06:51:11.112275 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 06:51:11.119894 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 06:51:11.127120 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 06:51:11.134552 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 06:51:11.138376 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 06:51:11.141402 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 06:51:11.149865 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
534 06:51:11.152981 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 06:51:11.161131 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 06:51:11.163925 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 06:51:11.172856 [RTC]rtc_get_frequency_meter,154: input=15, output=853
538 06:51:11.183211 [RTC]rtc_get_frequency_meter,154: input=7, output=725
539 06:51:11.192075 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 06:51:11.201943 [RTC]rtc_get_frequency_meter,154: input=13, output=821
541 06:51:11.211878 [RTC]rtc_get_frequency_meter,154: input=12, output=805
542 06:51:11.221284 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 06:51:11.230580 [RTC]rtc_get_frequency_meter,154: input=12, output=806
544 06:51:11.233764 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 06:51:11.241218 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 06:51:11.244770 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 06:51:11.248679 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 06:51:11.252179 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 06:51:11.256070 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 06:51:11.259207 ADC[4]: Raw value=905172 ID=7
551 06:51:11.263211 ADC[3]: Raw value=213916 ID=1
552 06:51:11.263686 RAM Code: 0x71
553 06:51:11.266763 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 06:51:11.274104 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 06:51:11.281892 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 06:51:11.288627 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 06:51:11.292798 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 06:51:11.295557 in-header: 03 07 00 00 08 00 00 00
559 06:51:11.299098 in-data: aa e4 47 04 13 02 00 00
560 06:51:11.299656 Chrome EC: UHEPI supported
561 06:51:11.306092 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 06:51:11.311061 in-header: 03 95 00 00 08 00 00 00
563 06:51:11.314383 in-data: 18 20 20 08 00 00 00 00
564 06:51:11.317482 MRC: failed to locate region type 0.
565 06:51:11.325178 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 06:51:11.329316 DRAM-K: Running full calibration
567 06:51:11.332545 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 06:51:11.335860 header.status = 0x0
569 06:51:11.340049 header.version = 0x6 (expected: 0x6)
570 06:51:11.343579 header.size = 0xd00 (expected: 0xd00)
571 06:51:11.344165 header.flags = 0x0
572 06:51:11.351177 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 06:51:11.368374 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 06:51:11.376069 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 06:51:11.376528 dram_init: ddr_geometry: 2
576 06:51:11.380090 [EMI] MDL number = 2
577 06:51:11.380521 [EMI] Get MDL freq = 0
578 06:51:11.383840 dram_init: ddr_type: 0
579 06:51:11.387919 is_discrete_lpddr4: 1
580 06:51:11.388483 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 06:51:11.391049
582 06:51:11.391520
583 06:51:11.391870 [Bian_co] ETT version 0.0.0.1
584 06:51:11.398451 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 06:51:11.398882
586 06:51:11.402483 dramc_set_vcore_voltage set vcore to 650000
587 06:51:11.403026 Read voltage for 800, 4
588 06:51:11.405707 Vio18 = 0
589 06:51:11.406138 Vcore = 650000
590 06:51:11.406482 Vdram = 0
591 06:51:11.406804 Vddq = 0
592 06:51:11.409706 Vmddr = 0
593 06:51:11.410251 dram_init: config_dvfs: 1
594 06:51:11.417100 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 06:51:11.420712 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 06:51:11.424628 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 06:51:11.427344 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 06:51:11.431267 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 06:51:11.434537 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 06:51:11.437985 MEM_TYPE=3, freq_sel=18
601 06:51:11.441497 sv_algorithm_assistance_LP4_1600
602 06:51:11.444845 ============ PULL DRAM RESETB DOWN ============
603 06:51:11.448898 ========== PULL DRAM RESETB DOWN end =========
604 06:51:11.455656 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 06:51:11.456087 ===================================
606 06:51:11.459096 LPDDR4 DRAM CONFIGURATION
607 06:51:11.461930 ===================================
608 06:51:11.465767 EX_ROW_EN[0] = 0x0
609 06:51:11.466199 EX_ROW_EN[1] = 0x0
610 06:51:11.468803 LP4Y_EN = 0x0
611 06:51:11.469277 WORK_FSP = 0x0
612 06:51:11.472101 WL = 0x2
613 06:51:11.472532 RL = 0x2
614 06:51:11.475657 BL = 0x2
615 06:51:11.476165 RPST = 0x0
616 06:51:11.479087 RD_PRE = 0x0
617 06:51:11.479546 WR_PRE = 0x1
618 06:51:11.482154 WR_PST = 0x0
619 06:51:11.486302 DBI_WR = 0x0
620 06:51:11.486848 DBI_RD = 0x0
621 06:51:11.488515 OTF = 0x1
622 06:51:11.492251 ===================================
623 06:51:11.495414 ===================================
624 06:51:11.495848 ANA top config
625 06:51:11.498875 ===================================
626 06:51:11.501875 DLL_ASYNC_EN = 0
627 06:51:11.505480 ALL_SLAVE_EN = 1
628 06:51:11.506043 NEW_RANK_MODE = 1
629 06:51:11.508629 DLL_IDLE_MODE = 1
630 06:51:11.512329 LP45_APHY_COMB_EN = 1
631 06:51:11.515564 TX_ODT_DIS = 1
632 06:51:11.516094 NEW_8X_MODE = 1
633 06:51:11.518433 ===================================
634 06:51:11.522254 ===================================
635 06:51:11.525624 data_rate = 1600
636 06:51:11.529247 CKR = 1
637 06:51:11.531886 DQ_P2S_RATIO = 8
638 06:51:11.535235 ===================================
639 06:51:11.539354 CA_P2S_RATIO = 8
640 06:51:11.539927 DQ_CA_OPEN = 0
641 06:51:11.542945 DQ_SEMI_OPEN = 0
642 06:51:11.546193 CA_SEMI_OPEN = 0
643 06:51:11.550248 CA_FULL_RATE = 0
644 06:51:11.553178 DQ_CKDIV4_EN = 1
645 06:51:11.555952 CA_CKDIV4_EN = 1
646 06:51:11.556385 CA_PREDIV_EN = 0
647 06:51:11.559410 PH8_DLY = 0
648 06:51:11.562864 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 06:51:11.566600 DQ_AAMCK_DIV = 4
650 06:51:11.569852 CA_AAMCK_DIV = 4
651 06:51:11.570404 CA_ADMCK_DIV = 4
652 06:51:11.572402 DQ_TRACK_CA_EN = 0
653 06:51:11.575831 CA_PICK = 800
654 06:51:11.579514 CA_MCKIO = 800
655 06:51:11.583298 MCKIO_SEMI = 0
656 06:51:11.586738 PLL_FREQ = 3068
657 06:51:11.590580 DQ_UI_PI_RATIO = 32
658 06:51:11.591102 CA_UI_PI_RATIO = 0
659 06:51:11.593817 ===================================
660 06:51:11.597352 ===================================
661 06:51:11.601087 memory_type:LPDDR4
662 06:51:11.601628 GP_NUM : 10
663 06:51:11.604234 SRAM_EN : 1
664 06:51:11.604808 MD32_EN : 0
665 06:51:11.607805 ===================================
666 06:51:11.611970 [ANA_INIT] >>>>>>>>>>>>>>
667 06:51:11.615974 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 06:51:11.619038 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 06:51:11.622542 ===================================
670 06:51:11.626143 data_rate = 1600,PCW = 0X7600
671 06:51:11.626677 ===================================
672 06:51:11.629678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 06:51:11.636025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 06:51:11.642477 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 06:51:11.646106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 06:51:11.648820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 06:51:11.652839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 06:51:11.655358 [ANA_INIT] flow start
679 06:51:11.659309 [ANA_INIT] PLL >>>>>>>>
680 06:51:11.659942 [ANA_INIT] PLL <<<<<<<<
681 06:51:11.661878 [ANA_INIT] MIDPI >>>>>>>>
682 06:51:11.665854 [ANA_INIT] MIDPI <<<<<<<<
683 06:51:11.666444 [ANA_INIT] DLL >>>>>>>>
684 06:51:11.669042 [ANA_INIT] flow end
685 06:51:11.671966 ============ LP4 DIFF to SE enter ============
686 06:51:11.678587 ============ LP4 DIFF to SE exit ============
687 06:51:11.679443 [ANA_INIT] <<<<<<<<<<<<<
688 06:51:11.682362 [Flow] Enable top DCM control >>>>>
689 06:51:11.685407 [Flow] Enable top DCM control <<<<<
690 06:51:11.688817 Enable DLL master slave shuffle
691 06:51:11.695807 ==============================================================
692 06:51:11.696379 Gating Mode config
693 06:51:11.701954 ==============================================================
694 06:51:11.705064 Config description:
695 06:51:11.712608 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 06:51:11.718539 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 06:51:11.725682 SELPH_MODE 0: By rank 1: By Phase
698 06:51:11.729702 ==============================================================
699 06:51:11.731883 GAT_TRACK_EN = 1
700 06:51:11.735273 RX_GATING_MODE = 2
701 06:51:11.739063 RX_GATING_TRACK_MODE = 2
702 06:51:11.742357 SELPH_MODE = 1
703 06:51:11.744900 PICG_EARLY_EN = 1
704 06:51:11.748643 VALID_LAT_VALUE = 1
705 06:51:11.755302 ==============================================================
706 06:51:11.758074 Enter into Gating configuration >>>>
707 06:51:11.761420 Exit from Gating configuration <<<<
708 06:51:11.764913 Enter into DVFS_PRE_config >>>>>
709 06:51:11.775467 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 06:51:11.778617 Exit from DVFS_PRE_config <<<<<
711 06:51:11.782080 Enter into PICG configuration >>>>
712 06:51:11.785625 Exit from PICG configuration <<<<
713 06:51:11.788103 [RX_INPUT] configuration >>>>>
714 06:51:11.788576 [RX_INPUT] configuration <<<<<
715 06:51:11.795197 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 06:51:11.801396 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 06:51:11.808199 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 06:51:11.811999 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 06:51:11.818101 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 06:51:11.825015 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 06:51:11.828231 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 06:51:11.831122 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 06:51:11.838012 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 06:51:11.841086 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 06:51:11.844540 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 06:51:11.850858 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 06:51:11.854433 ===================================
728 06:51:11.854994 LPDDR4 DRAM CONFIGURATION
729 06:51:11.857278 ===================================
730 06:51:11.860655 EX_ROW_EN[0] = 0x0
731 06:51:11.863956 EX_ROW_EN[1] = 0x0
732 06:51:11.864428 LP4Y_EN = 0x0
733 06:51:11.868255 WORK_FSP = 0x0
734 06:51:11.868846 WL = 0x2
735 06:51:11.871752 RL = 0x2
736 06:51:11.872361 BL = 0x2
737 06:51:11.874230 RPST = 0x0
738 06:51:11.874701 RD_PRE = 0x0
739 06:51:11.878005 WR_PRE = 0x1
740 06:51:11.878490 WR_PST = 0x0
741 06:51:11.881206 DBI_WR = 0x0
742 06:51:11.881794 DBI_RD = 0x0
743 06:51:11.884757 OTF = 0x1
744 06:51:11.887531 ===================================
745 06:51:11.891443 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 06:51:11.894877 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 06:51:11.901263 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 06:51:11.904017 ===================================
749 06:51:11.904451 LPDDR4 DRAM CONFIGURATION
750 06:51:11.907536 ===================================
751 06:51:11.910635 EX_ROW_EN[0] = 0x10
752 06:51:11.911168 EX_ROW_EN[1] = 0x0
753 06:51:11.914429 LP4Y_EN = 0x0
754 06:51:11.917677 WORK_FSP = 0x0
755 06:51:11.918214 WL = 0x2
756 06:51:11.920492 RL = 0x2
757 06:51:11.920922 BL = 0x2
758 06:51:11.924020 RPST = 0x0
759 06:51:11.924554 RD_PRE = 0x0
760 06:51:11.926975 WR_PRE = 0x1
761 06:51:11.927422 WR_PST = 0x0
762 06:51:11.930666 DBI_WR = 0x0
763 06:51:11.931198 DBI_RD = 0x0
764 06:51:11.934012 OTF = 0x1
765 06:51:11.936959 ===================================
766 06:51:11.944123 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 06:51:11.947063 nWR fixed to 40
768 06:51:11.947641 [ModeRegInit_LP4] CH0 RK0
769 06:51:11.950653 [ModeRegInit_LP4] CH0 RK1
770 06:51:11.954305 [ModeRegInit_LP4] CH1 RK0
771 06:51:11.954853 [ModeRegInit_LP4] CH1 RK1
772 06:51:11.957143 match AC timing 13
773 06:51:11.960167 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 06:51:11.964114 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 06:51:11.970860 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 06:51:11.973690 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 06:51:11.980089 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 06:51:11.980520 [EMI DOE] emi_dcm 0
779 06:51:11.984051 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 06:51:11.987507 ==
781 06:51:11.990648 Dram Type= 6, Freq= 0, CH_0, rank 0
782 06:51:11.994311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 06:51:11.994887 ==
784 06:51:11.997288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 06:51:12.003944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 06:51:12.013931 [CA 0] Center 38 (7~69) winsize 63
787 06:51:12.017060 [CA 1] Center 37 (6~68) winsize 63
788 06:51:12.020565 [CA 2] Center 34 (4~65) winsize 62
789 06:51:12.024130 [CA 3] Center 35 (4~66) winsize 63
790 06:51:12.027312 [CA 4] Center 33 (3~64) winsize 62
791 06:51:12.030457 [CA 5] Center 33 (3~64) winsize 62
792 06:51:12.031034
793 06:51:12.033988 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 06:51:12.034597
795 06:51:12.037197 [CATrainingPosCal] consider 1 rank data
796 06:51:12.040314 u2DelayCellTimex100 = 270/100 ps
797 06:51:12.043503 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
798 06:51:12.050676 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 06:51:12.054124 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 06:51:12.057022 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 06:51:12.060144 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 06:51:12.063648 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 06:51:12.064121
804 06:51:12.066715 CA PerBit enable=1, Macro0, CA PI delay=33
805 06:51:12.067189
806 06:51:12.070358 [CBTSetCACLKResult] CA Dly = 33
807 06:51:12.070926 CS Dly: 5 (0~36)
808 06:51:12.073148 ==
809 06:51:12.076833 Dram Type= 6, Freq= 0, CH_0, rank 1
810 06:51:12.079787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 06:51:12.080264 ==
812 06:51:12.083343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 06:51:12.089944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 06:51:12.100197 [CA 0] Center 38 (7~69) winsize 63
815 06:51:12.103744 [CA 1] Center 37 (7~68) winsize 62
816 06:51:12.106912 [CA 2] Center 35 (4~66) winsize 63
817 06:51:12.109851 [CA 3] Center 35 (4~66) winsize 63
818 06:51:12.112966 [CA 4] Center 34 (3~65) winsize 63
819 06:51:12.116349 [CA 5] Center 33 (3~64) winsize 62
820 06:51:12.116869
821 06:51:12.119629 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 06:51:12.120222
823 06:51:12.123590 [CATrainingPosCal] consider 2 rank data
824 06:51:12.126458 u2DelayCellTimex100 = 270/100 ps
825 06:51:12.129524 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
826 06:51:12.136638 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 06:51:12.140178 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 06:51:12.143163 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 06:51:12.146616 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 06:51:12.149727 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 06:51:12.150164
832 06:51:12.153603 CA PerBit enable=1, Macro0, CA PI delay=33
833 06:51:12.154128
834 06:51:12.157118 [CBTSetCACLKResult] CA Dly = 33
835 06:51:12.157807 CS Dly: 6 (0~38)
836 06:51:12.159482
837 06:51:12.162808 ----->DramcWriteLeveling(PI) begin...
838 06:51:12.163257 ==
839 06:51:12.166911 Dram Type= 6, Freq= 0, CH_0, rank 0
840 06:51:12.170396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 06:51:12.170829 ==
842 06:51:12.173935 Write leveling (Byte 0): 30 => 30
843 06:51:12.174366 Write leveling (Byte 1): 30 => 30
844 06:51:12.177931 DramcWriteLeveling(PI) end<-----
845 06:51:12.178394
846 06:51:12.178733 ==
847 06:51:12.181740 Dram Type= 6, Freq= 0, CH_0, rank 0
848 06:51:12.184650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 06:51:12.188107 ==
850 06:51:12.188536 [Gating] SW mode calibration
851 06:51:12.194927 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 06:51:12.201998 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 06:51:12.205346 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 06:51:12.211494 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 06:51:12.215560 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 06:51:12.218394 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 06:51:12.221749 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 06:51:12.228583 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 06:51:12.231637 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 06:51:12.235304 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 06:51:12.242314 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 06:51:12.244768 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 06:51:12.248580 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 06:51:12.255116 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 06:51:12.258579 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 06:51:12.261915 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 06:51:12.268460 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 06:51:12.272019 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 06:51:12.275747 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 06:51:12.281543 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 06:51:12.285544 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 06:51:12.288283 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 06:51:12.295391 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 06:51:12.298409 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 06:51:12.301761 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 06:51:12.308244 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 06:51:12.311467 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 06:51:12.314536 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 06:51:12.321871 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
880 06:51:12.324453 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
881 06:51:12.327963 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 06:51:12.334873 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 06:51:12.338293 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 06:51:12.341183 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 06:51:12.347930 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
886 06:51:12.351065 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
887 06:51:12.354409 0 10 8 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
888 06:51:12.361248 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
889 06:51:12.364164 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 06:51:12.367570 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 06:51:12.374120 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 06:51:12.377459 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 06:51:12.381380 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 06:51:12.387801 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
895 06:51:12.390587 0 11 8 | B1->B0 | 2828 4242 | 0 0 | (0 0) (0 0)
896 06:51:12.394702 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
897 06:51:12.400893 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 06:51:12.403921 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 06:51:12.407521 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 06:51:12.411053 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 06:51:12.417830 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 06:51:12.420388 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
903 06:51:12.423809 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 06:51:12.430664 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 06:51:12.433960 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 06:51:12.437440 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 06:51:12.443624 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 06:51:12.446721 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 06:51:12.450304 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 06:51:12.457042 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 06:51:12.460410 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 06:51:12.463872 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 06:51:12.470641 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 06:51:12.473455 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 06:51:12.476903 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 06:51:12.483423 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 06:51:12.487021 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 06:51:12.490343 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 06:51:12.497764 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 06:51:12.499945 Total UI for P1: 0, mck2ui 16
921 06:51:12.503249 best dqsien dly found for B0: ( 0, 14, 4)
922 06:51:12.506755 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 06:51:12.509967 Total UI for P1: 0, mck2ui 16
924 06:51:12.513239 best dqsien dly found for B1: ( 0, 14, 8)
925 06:51:12.516703 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 06:51:12.520216 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 06:51:12.520964
928 06:51:12.523182 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 06:51:12.526461 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 06:51:12.530121 [Gating] SW calibration Done
931 06:51:12.530672 ==
932 06:51:12.533217 Dram Type= 6, Freq= 0, CH_0, rank 0
933 06:51:12.537127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 06:51:12.537634 ==
935 06:51:12.540353 RX Vref Scan: 0
936 06:51:12.540888
937 06:51:12.541247 RX Vref 0 -> 0, step: 1
938 06:51:12.543892
939 06:51:12.544390 RX Delay -130 -> 252, step: 16
940 06:51:12.550825 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 06:51:12.554169 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 06:51:12.557296 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 06:51:12.560621 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
944 06:51:12.563658 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 06:51:12.570394 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 06:51:12.574135 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 06:51:12.577153 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 06:51:12.580208 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 06:51:12.583589 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
950 06:51:12.590508 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 06:51:12.593892 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 06:51:12.597529 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 06:51:12.600843 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 06:51:12.603495 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 06:51:12.610726 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 06:51:12.611247 ==
957 06:51:12.613951 Dram Type= 6, Freq= 0, CH_0, rank 0
958 06:51:12.616701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 06:51:12.617142 ==
960 06:51:12.617490 DQS Delay:
961 06:51:12.620194 DQS0 = 0, DQS1 = 0
962 06:51:12.620645 DQM Delay:
963 06:51:12.623652 DQM0 = 91, DQM1 = 76
964 06:51:12.624203 DQ Delay:
965 06:51:12.627015 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
966 06:51:12.630539 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
967 06:51:12.633426 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
968 06:51:12.637023 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 06:51:12.637664
970 06:51:12.638019
971 06:51:12.638341 ==
972 06:51:12.639970 Dram Type= 6, Freq= 0, CH_0, rank 0
973 06:51:12.643905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 06:51:12.646606 ==
975 06:51:12.647031
976 06:51:12.647397
977 06:51:12.647725 TX Vref Scan disable
978 06:51:12.650393 == TX Byte 0 ==
979 06:51:12.653572 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 06:51:12.657513 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 06:51:12.660288 == TX Byte 1 ==
982 06:51:12.663849 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
983 06:51:12.666938 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
984 06:51:12.670268 ==
985 06:51:12.670698 Dram Type= 6, Freq= 0, CH_0, rank 0
986 06:51:12.676339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 06:51:12.676773 ==
988 06:51:12.688716 TX Vref=22, minBit 1, minWin=26, winSum=439
989 06:51:12.692327 TX Vref=24, minBit 1, minWin=26, winSum=443
990 06:51:12.695311 TX Vref=26, minBit 1, minWin=26, winSum=446
991 06:51:12.698466 TX Vref=28, minBit 0, minWin=27, winSum=456
992 06:51:12.701696 TX Vref=30, minBit 1, minWin=28, winSum=455
993 06:51:12.708414 TX Vref=32, minBit 2, minWin=27, winSum=446
994 06:51:12.712153 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 30
995 06:51:12.712659
996 06:51:12.715774 Final TX Range 1 Vref 30
997 06:51:12.716308
998 06:51:12.716656 ==
999 06:51:12.718772 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 06:51:12.722281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 06:51:12.722712 ==
1002 06:51:12.725202
1003 06:51:12.725629
1004 06:51:12.725973 TX Vref Scan disable
1005 06:51:12.728671 == TX Byte 0 ==
1006 06:51:12.731858 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 06:51:12.738351 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 06:51:12.738779 == TX Byte 1 ==
1009 06:51:12.741808 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1010 06:51:12.745421 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1011 06:51:12.749079
1012 06:51:12.749610 [DATLAT]
1013 06:51:12.749955 Freq=800, CH0 RK0
1014 06:51:12.750281
1015 06:51:12.752173 DATLAT Default: 0xa
1016 06:51:12.752599 0, 0xFFFF, sum = 0
1017 06:51:12.755679 1, 0xFFFF, sum = 0
1018 06:51:12.756130 2, 0xFFFF, sum = 0
1019 06:51:12.758860 3, 0xFFFF, sum = 0
1020 06:51:12.759508 4, 0xFFFF, sum = 0
1021 06:51:12.761799 5, 0xFFFF, sum = 0
1022 06:51:12.764941 6, 0xFFFF, sum = 0
1023 06:51:12.765432 7, 0xFFFF, sum = 0
1024 06:51:12.765863 8, 0x0, sum = 1
1025 06:51:12.768515 9, 0x0, sum = 2
1026 06:51:12.768943 10, 0x0, sum = 3
1027 06:51:12.771874 11, 0x0, sum = 4
1028 06:51:12.772330 best_step = 9
1029 06:51:12.772684
1030 06:51:12.772999 ==
1031 06:51:12.774988 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 06:51:12.781606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 06:51:12.782127 ==
1034 06:51:12.782467 RX Vref Scan: 1
1035 06:51:12.782783
1036 06:51:12.784693 Set Vref Range= 32 -> 127
1037 06:51:12.785117
1038 06:51:12.788734 RX Vref 32 -> 127, step: 1
1039 06:51:12.789262
1040 06:51:12.791322 RX Delay -111 -> 252, step: 8
1041 06:51:12.791796
1042 06:51:12.795002 Set Vref, RX VrefLevel [Byte0]: 32
1043 06:51:12.798282 [Byte1]: 32
1044 06:51:12.798705
1045 06:51:12.801790 Set Vref, RX VrefLevel [Byte0]: 33
1046 06:51:12.805195 [Byte1]: 33
1047 06:51:12.805616
1048 06:51:12.808656 Set Vref, RX VrefLevel [Byte0]: 34
1049 06:51:12.812002 [Byte1]: 34
1050 06:51:12.815181
1051 06:51:12.815757 Set Vref, RX VrefLevel [Byte0]: 35
1052 06:51:12.817971 [Byte1]: 35
1053 06:51:12.822465
1054 06:51:12.822884 Set Vref, RX VrefLevel [Byte0]: 36
1055 06:51:12.825748 [Byte1]: 36
1056 06:51:12.830762
1057 06:51:12.831297 Set Vref, RX VrefLevel [Byte0]: 37
1058 06:51:12.833526 [Byte1]: 37
1059 06:51:12.838033
1060 06:51:12.838454 Set Vref, RX VrefLevel [Byte0]: 38
1061 06:51:12.841897 [Byte1]: 38
1062 06:51:12.845601
1063 06:51:12.846023 Set Vref, RX VrefLevel [Byte0]: 39
1064 06:51:12.849314 [Byte1]: 39
1065 06:51:12.853479
1066 06:51:12.854005 Set Vref, RX VrefLevel [Byte0]: 40
1067 06:51:12.856812 [Byte1]: 40
1068 06:51:12.860842
1069 06:51:12.861491 Set Vref, RX VrefLevel [Byte0]: 41
1070 06:51:12.864367 [Byte1]: 41
1071 06:51:12.868492
1072 06:51:12.868905 Set Vref, RX VrefLevel [Byte0]: 42
1073 06:51:12.871535 [Byte1]: 42
1074 06:51:12.876101
1075 06:51:12.876704 Set Vref, RX VrefLevel [Byte0]: 43
1076 06:51:12.878996 [Byte1]: 43
1077 06:51:12.883785
1078 06:51:12.884312 Set Vref, RX VrefLevel [Byte0]: 44
1079 06:51:12.887097 [Byte1]: 44
1080 06:51:12.891540
1081 06:51:12.892056 Set Vref, RX VrefLevel [Byte0]: 45
1082 06:51:12.894533 [Byte1]: 45
1083 06:51:12.899239
1084 06:51:12.899818 Set Vref, RX VrefLevel [Byte0]: 46
1085 06:51:12.902334 [Byte1]: 46
1086 06:51:12.906757
1087 06:51:12.907252 Set Vref, RX VrefLevel [Byte0]: 47
1088 06:51:12.910332 [Byte1]: 47
1089 06:51:12.914466
1090 06:51:12.915043 Set Vref, RX VrefLevel [Byte0]: 48
1091 06:51:12.917710 [Byte1]: 48
1092 06:51:12.921719
1093 06:51:12.922139 Set Vref, RX VrefLevel [Byte0]: 49
1094 06:51:12.925330 [Byte1]: 49
1095 06:51:12.929574
1096 06:51:12.929994 Set Vref, RX VrefLevel [Byte0]: 50
1097 06:51:12.932683 [Byte1]: 50
1098 06:51:12.937194
1099 06:51:12.937716 Set Vref, RX VrefLevel [Byte0]: 51
1100 06:51:12.941199 [Byte1]: 51
1101 06:51:12.944849
1102 06:51:12.945411 Set Vref, RX VrefLevel [Byte0]: 52
1103 06:51:12.948245 [Byte1]: 52
1104 06:51:12.952908
1105 06:51:12.953476 Set Vref, RX VrefLevel [Byte0]: 53
1106 06:51:12.956164 [Byte1]: 53
1107 06:51:12.960474
1108 06:51:12.960975 Set Vref, RX VrefLevel [Byte0]: 54
1109 06:51:12.963428 [Byte1]: 54
1110 06:51:12.967817
1111 06:51:12.968231 Set Vref, RX VrefLevel [Byte0]: 55
1112 06:51:12.970904 [Byte1]: 55
1113 06:51:12.975494
1114 06:51:12.976054 Set Vref, RX VrefLevel [Byte0]: 56
1115 06:51:12.978534 [Byte1]: 56
1116 06:51:12.983141
1117 06:51:12.983782 Set Vref, RX VrefLevel [Byte0]: 57
1118 06:51:12.985991 [Byte1]: 57
1119 06:51:12.991088
1120 06:51:12.991701 Set Vref, RX VrefLevel [Byte0]: 58
1121 06:51:12.994444 [Byte1]: 58
1122 06:51:12.998646
1123 06:51:12.999202 Set Vref, RX VrefLevel [Byte0]: 59
1124 06:51:13.001685 [Byte1]: 59
1125 06:51:13.005643
1126 06:51:13.006057 Set Vref, RX VrefLevel [Byte0]: 60
1127 06:51:13.009035 [Byte1]: 60
1128 06:51:13.013604
1129 06:51:13.014109 Set Vref, RX VrefLevel [Byte0]: 61
1130 06:51:13.017105 [Byte1]: 61
1131 06:51:13.021422
1132 06:51:13.021953 Set Vref, RX VrefLevel [Byte0]: 62
1133 06:51:13.024631 [Byte1]: 62
1134 06:51:13.029419
1135 06:51:13.029939 Set Vref, RX VrefLevel [Byte0]: 63
1136 06:51:13.032191 [Byte1]: 63
1137 06:51:13.036410
1138 06:51:13.036931 Set Vref, RX VrefLevel [Byte0]: 64
1139 06:51:13.039924 [Byte1]: 64
1140 06:51:13.044471
1141 06:51:13.044998 Set Vref, RX VrefLevel [Byte0]: 65
1142 06:51:13.047782 [Byte1]: 65
1143 06:51:13.051908
1144 06:51:13.052444 Set Vref, RX VrefLevel [Byte0]: 66
1145 06:51:13.055492 [Byte1]: 66
1146 06:51:13.059650
1147 06:51:13.060278 Set Vref, RX VrefLevel [Byte0]: 67
1148 06:51:13.062460 [Byte1]: 67
1149 06:51:13.066822
1150 06:51:13.067236 Set Vref, RX VrefLevel [Byte0]: 68
1151 06:51:13.070266 [Byte1]: 68
1152 06:51:13.074687
1153 06:51:13.075456 Set Vref, RX VrefLevel [Byte0]: 69
1154 06:51:13.078497 [Byte1]: 69
1155 06:51:13.082821
1156 06:51:13.083242 Set Vref, RX VrefLevel [Byte0]: 70
1157 06:51:13.085873 [Byte1]: 70
1158 06:51:13.090059
1159 06:51:13.090582 Set Vref, RX VrefLevel [Byte0]: 71
1160 06:51:13.093085 [Byte1]: 71
1161 06:51:13.097694
1162 06:51:13.098117 Set Vref, RX VrefLevel [Byte0]: 72
1163 06:51:13.101618 [Byte1]: 72
1164 06:51:13.105418
1165 06:51:13.105839 Set Vref, RX VrefLevel [Byte0]: 73
1166 06:51:13.108598 [Byte1]: 73
1167 06:51:13.113114
1168 06:51:13.113638 Final RX Vref Byte 0 = 57 to rank0
1169 06:51:13.116314 Final RX Vref Byte 1 = 59 to rank0
1170 06:51:13.119862 Final RX Vref Byte 0 = 57 to rank1
1171 06:51:13.122669 Final RX Vref Byte 1 = 59 to rank1==
1172 06:51:13.126179 Dram Type= 6, Freq= 0, CH_0, rank 0
1173 06:51:13.132844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1174 06:51:13.133375 ==
1175 06:51:13.133718 DQS Delay:
1176 06:51:13.135892 DQS0 = 0, DQS1 = 0
1177 06:51:13.136313 DQM Delay:
1178 06:51:13.136651 DQM0 = 88, DQM1 = 77
1179 06:51:13.139614 DQ Delay:
1180 06:51:13.143260 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1181 06:51:13.146153 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1182 06:51:13.149967 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1183 06:51:13.152944 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1184 06:51:13.153468
1185 06:51:13.153897
1186 06:51:13.159775 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1187 06:51:13.162438 CH0 RK0: MR19=606, MR18=2C26
1188 06:51:13.168994 CH0_RK0: MR19=0x606, MR18=0x2C26, DQSOSC=398, MR23=63, INC=93, DEC=62
1189 06:51:13.169418
1190 06:51:13.173304 ----->DramcWriteLeveling(PI) begin...
1191 06:51:13.173838 ==
1192 06:51:13.176300 Dram Type= 6, Freq= 0, CH_0, rank 1
1193 06:51:13.178970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1194 06:51:13.179436 ==
1195 06:51:13.183089 Write leveling (Byte 0): 29 => 29
1196 06:51:13.186038 Write leveling (Byte 1): 27 => 27
1197 06:51:13.189109 DramcWriteLeveling(PI) end<-----
1198 06:51:13.189532
1199 06:51:13.189866 ==
1200 06:51:13.192534 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 06:51:13.195912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 06:51:13.196339 ==
1203 06:51:13.198939 [Gating] SW mode calibration
1204 06:51:13.205914 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1205 06:51:13.212958 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1206 06:51:13.215485 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1207 06:51:13.219238 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1208 06:51:13.226073 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1209 06:51:13.270367 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 06:51:13.270991 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 06:51:13.271453 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 06:51:13.272173 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 06:51:13.272541 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 06:51:13.272875 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 06:51:13.273199 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 06:51:13.273514 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 06:51:13.273887 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 06:51:13.274213 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 06:51:13.314234 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 06:51:13.314817 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 06:51:13.315197 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 06:51:13.315591 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 06:51:13.316309 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1224 06:51:13.316688 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1225 06:51:13.317021 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 06:51:13.317346 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 06:51:13.317666 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 06:51:13.318046 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 06:51:13.332083 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 06:51:13.332667 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 06:51:13.333046 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1232 06:51:13.333921 0 9 8 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
1233 06:51:13.335773 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1234 06:51:13.339268 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 06:51:13.345538 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 06:51:13.348509 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 06:51:13.352329 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 06:51:13.358835 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1239 06:51:13.362241 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1240 06:51:13.365430 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (0 1) (0 0)
1241 06:51:13.368817 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1242 06:51:13.375389 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 06:51:13.378684 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 06:51:13.382165 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 06:51:13.388610 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 06:51:13.392099 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 06:51:13.395203 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
1248 06:51:13.402173 0 11 8 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
1249 06:51:13.405491 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1250 06:51:13.408620 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 06:51:13.415773 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 06:51:13.419654 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 06:51:13.423227 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 06:51:13.426946 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 06:51:13.430443 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1256 06:51:13.436741 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1257 06:51:13.440142 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 06:51:13.444230 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 06:51:13.450819 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 06:51:13.454404 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 06:51:13.457308 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 06:51:13.463837 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 06:51:13.467263 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 06:51:13.470609 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 06:51:13.477333 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 06:51:13.480096 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 06:51:13.483574 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 06:51:13.486946 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 06:51:13.494071 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 06:51:13.497416 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1271 06:51:13.500402 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1272 06:51:13.506976 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1273 06:51:13.511006 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 06:51:13.514211 Total UI for P1: 0, mck2ui 16
1275 06:51:13.517243 best dqsien dly found for B0: ( 0, 14, 4)
1276 06:51:13.520722 Total UI for P1: 0, mck2ui 16
1277 06:51:13.523428 best dqsien dly found for B1: ( 0, 14, 10)
1278 06:51:13.527216 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1279 06:51:13.530743 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1280 06:51:13.531310
1281 06:51:13.533578 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1282 06:51:13.537324 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1283 06:51:13.540113 [Gating] SW calibration Done
1284 06:51:13.540535 ==
1285 06:51:13.543586 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 06:51:13.550209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 06:51:13.550636 ==
1288 06:51:13.550975 RX Vref Scan: 0
1289 06:51:13.551288
1290 06:51:13.554144 RX Vref 0 -> 0, step: 1
1291 06:51:13.554670
1292 06:51:13.556774 RX Delay -130 -> 252, step: 16
1293 06:51:13.560675 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1294 06:51:13.564012 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1295 06:51:13.566697 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1296 06:51:13.570750 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1297 06:51:13.577291 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1298 06:51:13.579981 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1299 06:51:13.583399 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1300 06:51:13.587065 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1301 06:51:13.590740 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1302 06:51:13.596968 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1303 06:51:13.600481 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1304 06:51:13.603340 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1305 06:51:13.606754 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1306 06:51:13.610274 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1307 06:51:13.617635 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1308 06:51:13.619915 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1309 06:51:13.620379 ==
1310 06:51:13.623456 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 06:51:13.626826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 06:51:13.627441 ==
1313 06:51:13.630000 DQS Delay:
1314 06:51:13.630563 DQS0 = 0, DQS1 = 0
1315 06:51:13.630928 DQM Delay:
1316 06:51:13.633687 DQM0 = 85, DQM1 = 76
1317 06:51:13.634284 DQ Delay:
1318 06:51:13.637145 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1319 06:51:13.640052 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1320 06:51:13.644031 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1321 06:51:13.646823 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1322 06:51:13.647343
1323 06:51:13.647717
1324 06:51:13.648026 ==
1325 06:51:13.650288 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 06:51:13.656878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 06:51:13.657460 ==
1328 06:51:13.657810
1329 06:51:13.658119
1330 06:51:13.658415 TX Vref Scan disable
1331 06:51:13.659998 == TX Byte 0 ==
1332 06:51:13.663793 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1333 06:51:13.670692 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1334 06:51:13.671217 == TX Byte 1 ==
1335 06:51:13.673946 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1336 06:51:13.680712 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1337 06:51:13.681485 ==
1338 06:51:13.683897 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 06:51:13.687068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 06:51:13.687535 ==
1341 06:51:13.699293 TX Vref=22, minBit 1, minWin=26, winSum=441
1342 06:51:13.702734 TX Vref=24, minBit 0, minWin=27, winSum=445
1343 06:51:13.705947 TX Vref=26, minBit 3, minWin=27, winSum=449
1344 06:51:13.709280 TX Vref=28, minBit 6, minWin=27, winSum=451
1345 06:51:13.712590 TX Vref=30, minBit 3, minWin=27, winSum=450
1346 06:51:13.719529 TX Vref=32, minBit 6, minWin=27, winSum=448
1347 06:51:13.722265 [TxChooseVref] Worse bit 6, Min win 27, Win sum 451, Final Vref 28
1348 06:51:13.722751
1349 06:51:13.725897 Final TX Range 1 Vref 28
1350 06:51:13.726423
1351 06:51:13.726819 ==
1352 06:51:13.729092 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 06:51:13.733018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 06:51:13.733545 ==
1355 06:51:13.733890
1356 06:51:13.735951
1357 06:51:13.736366 TX Vref Scan disable
1358 06:51:13.739300 == TX Byte 0 ==
1359 06:51:13.742328 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1360 06:51:13.745843 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1361 06:51:13.749477 == TX Byte 1 ==
1362 06:51:13.752562 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1363 06:51:13.755617 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1364 06:51:13.758996
1365 06:51:13.759444 [DATLAT]
1366 06:51:13.759784 Freq=800, CH0 RK1
1367 06:51:13.760096
1368 06:51:13.762536 DATLAT Default: 0x9
1369 06:51:13.762950 0, 0xFFFF, sum = 0
1370 06:51:13.766052 1, 0xFFFF, sum = 0
1371 06:51:13.766352 2, 0xFFFF, sum = 0
1372 06:51:13.768695 3, 0xFFFF, sum = 0
1373 06:51:13.772110 4, 0xFFFF, sum = 0
1374 06:51:13.772515 5, 0xFFFF, sum = 0
1375 06:51:13.776093 6, 0xFFFF, sum = 0
1376 06:51:13.776490 7, 0xFFFF, sum = 0
1377 06:51:13.779050 8, 0xFFFF, sum = 0
1378 06:51:13.779467 9, 0x0, sum = 1
1379 06:51:13.781911 10, 0x0, sum = 2
1380 06:51:13.782211 11, 0x0, sum = 3
1381 06:51:13.782450 12, 0x0, sum = 4
1382 06:51:13.785858 best_step = 10
1383 06:51:13.786249
1384 06:51:13.786488 ==
1385 06:51:13.789376 Dram Type= 6, Freq= 0, CH_0, rank 1
1386 06:51:13.791802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1387 06:51:13.792133 ==
1388 06:51:13.795249 RX Vref Scan: 0
1389 06:51:13.795569
1390 06:51:13.795805 RX Vref 0 -> 0, step: 1
1391 06:51:13.798956
1392 06:51:13.799344 RX Delay -95 -> 252, step: 8
1393 06:51:13.805853 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1394 06:51:13.809324 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1395 06:51:13.812724 iDelay=209, Bit 2, Center 84 (-23 ~ 192) 216
1396 06:51:13.815666 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1397 06:51:13.819011 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1398 06:51:13.825428 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1399 06:51:13.828742 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1400 06:51:13.832046 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1401 06:51:13.835526 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1402 06:51:13.838933 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1403 06:51:13.846018 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1404 06:51:13.849190 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1405 06:51:13.853230 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1406 06:51:13.855796 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1407 06:51:13.862178 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1408 06:51:13.865375 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1409 06:51:13.865976 ==
1410 06:51:13.868798 Dram Type= 6, Freq= 0, CH_0, rank 1
1411 06:51:13.872859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 06:51:13.873418 ==
1413 06:51:13.875646 DQS Delay:
1414 06:51:13.876201 DQS0 = 0, DQS1 = 0
1415 06:51:13.876561 DQM Delay:
1416 06:51:13.878959 DQM0 = 86, DQM1 = 76
1417 06:51:13.879565 DQ Delay:
1418 06:51:13.882096 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1419 06:51:13.885588 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1420 06:51:13.888499 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1421 06:51:13.892157 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1422 06:51:13.892572
1423 06:51:13.892897
1424 06:51:13.901814 [DQSOSCAuto] RK1, (LSB)MR18= 0x2925, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1425 06:51:13.902333 CH0 RK1: MR19=606, MR18=2925
1426 06:51:13.908166 CH0_RK1: MR19=0x606, MR18=0x2925, DQSOSC=399, MR23=63, INC=92, DEC=61
1427 06:51:13.911909 [RxdqsGatingPostProcess] freq 800
1428 06:51:13.918975 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1429 06:51:13.921661 Pre-setting of DQS Precalculation
1430 06:51:13.924855 [DualRankRxdatlatCal] RK0: 9, RK1: 10, Final_Datlat 10
1431 06:51:13.925279 ==
1432 06:51:13.929045 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 06:51:13.934961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 06:51:13.935520 ==
1435 06:51:13.938000 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1436 06:51:13.944676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1437 06:51:13.954374 [CA 0] Center 36 (6~67) winsize 62
1438 06:51:13.957469 [CA 1] Center 37 (6~68) winsize 63
1439 06:51:13.960971 [CA 2] Center 35 (5~65) winsize 61
1440 06:51:13.964260 [CA 3] Center 34 (4~65) winsize 62
1441 06:51:13.967575 [CA 4] Center 34 (4~65) winsize 62
1442 06:51:13.970965 [CA 5] Center 33 (3~64) winsize 62
1443 06:51:13.971561
1444 06:51:13.973742 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1445 06:51:13.974197
1446 06:51:13.978080 [CATrainingPosCal] consider 1 rank data
1447 06:51:13.980376 u2DelayCellTimex100 = 270/100 ps
1448 06:51:13.983682 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1449 06:51:13.990397 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1450 06:51:13.993758 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1451 06:51:13.997190 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1452 06:51:14.000948 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1453 06:51:14.003999 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1454 06:51:14.004557
1455 06:51:14.007026 CA PerBit enable=1, Macro0, CA PI delay=33
1456 06:51:14.007633
1457 06:51:14.010221 [CBTSetCACLKResult] CA Dly = 33
1458 06:51:14.013880 CS Dly: 4 (0~35)
1459 06:51:14.014434 ==
1460 06:51:14.017017 Dram Type= 6, Freq= 0, CH_1, rank 1
1461 06:51:14.020183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 06:51:14.020644 ==
1463 06:51:14.026663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1464 06:51:14.029806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1465 06:51:14.040359 [CA 0] Center 36 (6~67) winsize 62
1466 06:51:14.043858 [CA 1] Center 36 (6~67) winsize 62
1467 06:51:14.046887 [CA 2] Center 34 (4~65) winsize 62
1468 06:51:14.050046 [CA 3] Center 33 (3~64) winsize 62
1469 06:51:14.053742 [CA 4] Center 34 (3~65) winsize 63
1470 06:51:14.056803 [CA 5] Center 33 (3~64) winsize 62
1471 06:51:14.057241
1472 06:51:14.060008 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1473 06:51:14.060424
1474 06:51:14.063832 [CATrainingPosCal] consider 2 rank data
1475 06:51:14.066555 u2DelayCellTimex100 = 270/100 ps
1476 06:51:14.070148 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1477 06:51:14.076631 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1478 06:51:14.080309 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1479 06:51:14.083687 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1480 06:51:14.088700 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1481 06:51:14.091395 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1482 06:51:14.091822
1483 06:51:14.095178 CA PerBit enable=1, Macro0, CA PI delay=33
1484 06:51:14.095699
1485 06:51:14.096215 [CBTSetCACLKResult] CA Dly = 33
1486 06:51:14.098881 CS Dly: 5 (0~37)
1487 06:51:14.099298
1488 06:51:14.102132 ----->DramcWriteLeveling(PI) begin...
1489 06:51:14.102706 ==
1490 06:51:14.106390 Dram Type= 6, Freq= 0, CH_1, rank 0
1491 06:51:14.109481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1492 06:51:14.109936 ==
1493 06:51:14.113236 Write leveling (Byte 0): 26 => 26
1494 06:51:14.116491 Write leveling (Byte 1): 25 => 25
1495 06:51:14.120510 DramcWriteLeveling(PI) end<-----
1496 06:51:14.121028
1497 06:51:14.121358 ==
1498 06:51:14.123257 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 06:51:14.126520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1500 06:51:14.126935 ==
1501 06:51:14.130322 [Gating] SW mode calibration
1502 06:51:14.136989 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1503 06:51:14.140055 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1504 06:51:14.146654 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1505 06:51:14.150157 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1506 06:51:14.153641 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1507 06:51:14.160301 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 06:51:14.163299 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 06:51:14.166321 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 06:51:14.173432 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 06:51:14.176470 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 06:51:14.179787 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 06:51:14.186292 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 06:51:14.189981 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 06:51:14.193547 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 06:51:14.199626 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 06:51:14.202782 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 06:51:14.206089 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 06:51:14.212941 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 06:51:14.216338 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1521 06:51:14.219330 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1522 06:51:14.227185 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1523 06:51:14.229231 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 06:51:14.233036 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 06:51:14.239741 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 06:51:14.242679 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 06:51:14.246350 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 06:51:14.252844 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 06:51:14.256335 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (1 1)
1530 06:51:14.259575 0 9 8 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
1531 06:51:14.266309 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 06:51:14.269550 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 06:51:14.273014 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 06:51:14.279712 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 06:51:14.282758 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 06:51:14.286038 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 06:51:14.292726 0 10 4 | B1->B0 | 3030 2f2f | 1 1 | (1 0) (1 0)
1538 06:51:14.295683 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
1539 06:51:14.299208 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 06:51:14.305972 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 06:51:14.309143 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 06:51:14.312641 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 06:51:14.318892 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 06:51:14.322381 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 06:51:14.325393 0 11 4 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
1546 06:51:14.332236 0 11 8 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
1547 06:51:14.335399 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 06:51:14.339160 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 06:51:14.345432 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 06:51:14.348808 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 06:51:14.352049 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 06:51:14.358952 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 06:51:14.362220 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1554 06:51:14.365403 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1555 06:51:14.371845 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 06:51:14.375548 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 06:51:14.379264 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 06:51:14.385006 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 06:51:14.388657 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 06:51:14.392051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 06:51:14.395120 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 06:51:14.401709 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 06:51:14.405377 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 06:51:14.408263 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 06:51:14.415545 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 06:51:14.418251 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 06:51:14.422149 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 06:51:14.427971 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 06:51:14.431718 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1570 06:51:14.435296 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 06:51:14.438651 Total UI for P1: 0, mck2ui 16
1572 06:51:14.442246 best dqsien dly found for B0: ( 0, 14, 4)
1573 06:51:14.444692 Total UI for P1: 0, mck2ui 16
1574 06:51:14.448039 best dqsien dly found for B1: ( 0, 14, 6)
1575 06:51:14.451734 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1576 06:51:14.454826 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1577 06:51:14.455538
1578 06:51:14.461798 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1579 06:51:14.464504 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1580 06:51:14.464969 [Gating] SW calibration Done
1581 06:51:14.467814 ==
1582 06:51:14.471482 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 06:51:14.474314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 06:51:14.474785 ==
1585 06:51:14.475157 RX Vref Scan: 0
1586 06:51:14.475540
1587 06:51:14.478045 RX Vref 0 -> 0, step: 1
1588 06:51:14.478612
1589 06:51:14.481347 RX Delay -130 -> 252, step: 16
1590 06:51:14.484317 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1591 06:51:14.487674 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1592 06:51:14.494037 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1593 06:51:14.497738 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1594 06:51:14.501314 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1595 06:51:14.504128 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1596 06:51:14.507548 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1597 06:51:14.514834 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1598 06:51:14.517710 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1599 06:51:14.520905 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1600 06:51:14.524518 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1601 06:51:14.528186 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1602 06:51:14.534427 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1603 06:51:14.538070 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1604 06:51:14.540923 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1605 06:51:14.543720 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1606 06:51:14.544182 ==
1607 06:51:14.547393 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 06:51:14.553916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 06:51:14.554402 ==
1610 06:51:14.554845 DQS Delay:
1611 06:51:14.558032 DQS0 = 0, DQS1 = 0
1612 06:51:14.558597 DQM Delay:
1613 06:51:14.559063 DQM0 = 84, DQM1 = 79
1614 06:51:14.560735 DQ Delay:
1615 06:51:14.563870 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1616 06:51:14.566964 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =85
1617 06:51:14.570826 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1618 06:51:14.573764 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1619 06:51:14.574277
1620 06:51:14.574609
1621 06:51:14.574915 ==
1622 06:51:14.577349 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 06:51:14.580744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 06:51:14.581259 ==
1625 06:51:14.581610
1626 06:51:14.581927
1627 06:51:14.583775 TX Vref Scan disable
1628 06:51:14.584195 == TX Byte 0 ==
1629 06:51:14.590513 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1630 06:51:14.593749 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1631 06:51:14.597237 == TX Byte 1 ==
1632 06:51:14.600074 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1633 06:51:14.603685 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1634 06:51:14.604108 ==
1635 06:51:14.607130 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 06:51:14.610522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 06:51:14.611098 ==
1638 06:51:14.624606 TX Vref=22, minBit 0, minWin=27, winSum=442
1639 06:51:14.628300 TX Vref=24, minBit 2, minWin=27, winSum=445
1640 06:51:14.631324 TX Vref=26, minBit 2, minWin=27, winSum=449
1641 06:51:14.634454 TX Vref=28, minBit 5, minWin=27, winSum=454
1642 06:51:14.637724 TX Vref=30, minBit 2, minWin=27, winSum=453
1643 06:51:14.644619 TX Vref=32, minBit 0, minWin=27, winSum=454
1644 06:51:14.647806 [TxChooseVref] Worse bit 5, Min win 27, Win sum 454, Final Vref 28
1645 06:51:14.648379
1646 06:51:14.651556 Final TX Range 1 Vref 28
1647 06:51:14.652121
1648 06:51:14.652491 ==
1649 06:51:14.654868 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 06:51:14.658050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 06:51:14.658616 ==
1652 06:51:14.661187
1653 06:51:14.661950
1654 06:51:14.662339 TX Vref Scan disable
1655 06:51:14.665140 == TX Byte 0 ==
1656 06:51:14.668221 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1657 06:51:14.671977 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1658 06:51:14.674947 == TX Byte 1 ==
1659 06:51:14.678511 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1660 06:51:14.681888 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1661 06:51:14.682457
1662 06:51:14.685350 [DATLAT]
1663 06:51:14.685994 Freq=800, CH1 RK0
1664 06:51:14.686544
1665 06:51:14.688437 DATLAT Default: 0xa
1666 06:51:14.688902 0, 0xFFFF, sum = 0
1667 06:51:14.691439 1, 0xFFFF, sum = 0
1668 06:51:14.691914 2, 0xFFFF, sum = 0
1669 06:51:14.694987 3, 0xFFFF, sum = 0
1670 06:51:14.695607 4, 0xFFFF, sum = 0
1671 06:51:14.698212 5, 0xFFFF, sum = 0
1672 06:51:14.698790 6, 0xFFFF, sum = 0
1673 06:51:14.701550 7, 0xFFFF, sum = 0
1674 06:51:14.702023 8, 0xFFFF, sum = 0
1675 06:51:14.705248 9, 0x0, sum = 1
1676 06:51:14.705817 10, 0x0, sum = 2
1677 06:51:14.708423 11, 0x0, sum = 3
1678 06:51:14.708896 12, 0x0, sum = 4
1679 06:51:14.711338 best_step = 10
1680 06:51:14.711863
1681 06:51:14.712235 ==
1682 06:51:14.715135 Dram Type= 6, Freq= 0, CH_1, rank 0
1683 06:51:14.718494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1684 06:51:14.718966 ==
1685 06:51:14.721460 RX Vref Scan: 1
1686 06:51:14.722043
1687 06:51:14.722421 Set Vref Range= 32 -> 127
1688 06:51:14.722768
1689 06:51:14.724694 RX Vref 32 -> 127, step: 1
1690 06:51:14.725306
1691 06:51:14.727855 RX Delay -95 -> 252, step: 8
1692 06:51:14.728319
1693 06:51:14.731244 Set Vref, RX VrefLevel [Byte0]: 32
1694 06:51:14.734878 [Byte1]: 32
1695 06:51:14.735433
1696 06:51:14.737976 Set Vref, RX VrefLevel [Byte0]: 33
1697 06:51:14.741166 [Byte1]: 33
1698 06:51:14.744912
1699 06:51:14.745425 Set Vref, RX VrefLevel [Byte0]: 34
1700 06:51:14.747886 [Byte1]: 34
1701 06:51:14.752998
1702 06:51:14.753512 Set Vref, RX VrefLevel [Byte0]: 35
1703 06:51:14.755987 [Byte1]: 35
1704 06:51:14.760340
1705 06:51:14.760855 Set Vref, RX VrefLevel [Byte0]: 36
1706 06:51:14.763886 [Byte1]: 36
1707 06:51:14.767353
1708 06:51:14.767845 Set Vref, RX VrefLevel [Byte0]: 37
1709 06:51:14.771177 [Byte1]: 37
1710 06:51:14.774917
1711 06:51:14.775566 Set Vref, RX VrefLevel [Byte0]: 38
1712 06:51:14.778806 [Byte1]: 38
1713 06:51:14.782854
1714 06:51:14.783641 Set Vref, RX VrefLevel [Byte0]: 39
1715 06:51:14.785968 [Byte1]: 39
1716 06:51:14.790478
1717 06:51:14.791032 Set Vref, RX VrefLevel [Byte0]: 40
1718 06:51:14.793884 [Byte1]: 40
1719 06:51:14.798230
1720 06:51:14.798783 Set Vref, RX VrefLevel [Byte0]: 41
1721 06:51:14.801194 [Byte1]: 41
1722 06:51:14.805717
1723 06:51:14.806270 Set Vref, RX VrefLevel [Byte0]: 42
1724 06:51:14.809428 [Byte1]: 42
1725 06:51:14.813136
1726 06:51:14.813692 Set Vref, RX VrefLevel [Byte0]: 43
1727 06:51:14.816654 [Byte1]: 43
1728 06:51:14.821482
1729 06:51:14.822037 Set Vref, RX VrefLevel [Byte0]: 44
1730 06:51:14.824435 [Byte1]: 44
1731 06:51:14.828453
1732 06:51:14.829007 Set Vref, RX VrefLevel [Byte0]: 45
1733 06:51:14.832108 [Byte1]: 45
1734 06:51:14.836133
1735 06:51:14.836695 Set Vref, RX VrefLevel [Byte0]: 46
1736 06:51:14.839515 [Byte1]: 46
1737 06:51:14.843992
1738 06:51:14.844549 Set Vref, RX VrefLevel [Byte0]: 47
1739 06:51:14.847549 [Byte1]: 47
1740 06:51:14.851761
1741 06:51:14.852346 Set Vref, RX VrefLevel [Byte0]: 48
1742 06:51:14.854860 [Byte1]: 48
1743 06:51:14.858737
1744 06:51:14.859295 Set Vref, RX VrefLevel [Byte0]: 49
1745 06:51:14.862056 [Byte1]: 49
1746 06:51:14.866773
1747 06:51:14.867334 Set Vref, RX VrefLevel [Byte0]: 50
1748 06:51:14.869696 [Byte1]: 50
1749 06:51:14.873738
1750 06:51:14.874201 Set Vref, RX VrefLevel [Byte0]: 51
1751 06:51:14.877340 [Byte1]: 51
1752 06:51:14.881989
1753 06:51:14.882563 Set Vref, RX VrefLevel [Byte0]: 52
1754 06:51:14.884805 [Byte1]: 52
1755 06:51:14.889357
1756 06:51:14.889913 Set Vref, RX VrefLevel [Byte0]: 53
1757 06:51:14.892620 [Byte1]: 53
1758 06:51:14.897152
1759 06:51:14.897706 Set Vref, RX VrefLevel [Byte0]: 54
1760 06:51:14.900020 [Byte1]: 54
1761 06:51:14.904794
1762 06:51:14.905348 Set Vref, RX VrefLevel [Byte0]: 55
1763 06:51:14.908140 [Byte1]: 55
1764 06:51:14.911990
1765 06:51:14.912451 Set Vref, RX VrefLevel [Byte0]: 56
1766 06:51:14.915509 [Byte1]: 56
1767 06:51:14.920040
1768 06:51:14.920594 Set Vref, RX VrefLevel [Byte0]: 57
1769 06:51:14.923290 [Byte1]: 57
1770 06:51:14.927614
1771 06:51:14.928173 Set Vref, RX VrefLevel [Byte0]: 58
1772 06:51:14.930602 [Byte1]: 58
1773 06:51:14.934928
1774 06:51:14.935590 Set Vref, RX VrefLevel [Byte0]: 59
1775 06:51:14.938443 [Byte1]: 59
1776 06:51:14.942696
1777 06:51:14.943260 Set Vref, RX VrefLevel [Byte0]: 60
1778 06:51:14.945641 [Byte1]: 60
1779 06:51:14.950004
1780 06:51:14.950563 Set Vref, RX VrefLevel [Byte0]: 61
1781 06:51:14.953561 [Byte1]: 61
1782 06:51:14.957980
1783 06:51:14.958533 Set Vref, RX VrefLevel [Byte0]: 62
1784 06:51:14.961187 [Byte1]: 62
1785 06:51:14.965376
1786 06:51:14.965932 Set Vref, RX VrefLevel [Byte0]: 63
1787 06:51:14.968591 [Byte1]: 63
1788 06:51:14.973171
1789 06:51:14.973729 Set Vref, RX VrefLevel [Byte0]: 64
1790 06:51:14.975761 [Byte1]: 64
1791 06:51:14.980495
1792 06:51:14.981048 Set Vref, RX VrefLevel [Byte0]: 65
1793 06:51:14.983839 [Byte1]: 65
1794 06:51:14.987948
1795 06:51:14.988637 Set Vref, RX VrefLevel [Byte0]: 66
1796 06:51:14.991242 [Byte1]: 66
1797 06:51:14.995997
1798 06:51:14.996571 Set Vref, RX VrefLevel [Byte0]: 67
1799 06:51:14.999240 [Byte1]: 67
1800 06:51:15.003424
1801 06:51:15.003974 Set Vref, RX VrefLevel [Byte0]: 68
1802 06:51:15.007018 [Byte1]: 68
1803 06:51:15.011027
1804 06:51:15.011652 Set Vref, RX VrefLevel [Byte0]: 69
1805 06:51:15.014547 [Byte1]: 69
1806 06:51:15.019068
1807 06:51:15.019691 Set Vref, RX VrefLevel [Byte0]: 70
1808 06:51:15.021845 [Byte1]: 70
1809 06:51:15.025787
1810 06:51:15.026288 Set Vref, RX VrefLevel [Byte0]: 71
1811 06:51:15.029198 [Byte1]: 71
1812 06:51:15.033777
1813 06:51:15.034330 Set Vref, RX VrefLevel [Byte0]: 72
1814 06:51:15.037402 [Byte1]: 72
1815 06:51:15.041309
1816 06:51:15.041868 Set Vref, RX VrefLevel [Byte0]: 73
1817 06:51:15.045112 [Byte1]: 73
1818 06:51:15.048825
1819 06:51:15.049431 Set Vref, RX VrefLevel [Byte0]: 74
1820 06:51:15.051928 [Byte1]: 74
1821 06:51:15.057116
1822 06:51:15.057674 Set Vref, RX VrefLevel [Byte0]: 75
1823 06:51:15.059614 [Byte1]: 75
1824 06:51:15.063957
1825 06:51:15.064545 Set Vref, RX VrefLevel [Byte0]: 76
1826 06:51:15.067812 [Byte1]: 76
1827 06:51:15.071284
1828 06:51:15.071793 Set Vref, RX VrefLevel [Byte0]: 77
1829 06:51:15.074998 [Byte1]: 77
1830 06:51:15.079774
1831 06:51:15.080328 Set Vref, RX VrefLevel [Byte0]: 78
1832 06:51:15.082686 [Byte1]: 78
1833 06:51:15.086954
1834 06:51:15.087554 Final RX Vref Byte 0 = 56 to rank0
1835 06:51:15.089924 Final RX Vref Byte 1 = 57 to rank0
1836 06:51:15.093972 Final RX Vref Byte 0 = 56 to rank1
1837 06:51:15.097145 Final RX Vref Byte 1 = 57 to rank1==
1838 06:51:15.099966 Dram Type= 6, Freq= 0, CH_1, rank 0
1839 06:51:15.106802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 06:51:15.107398 ==
1841 06:51:15.107802 DQS Delay:
1842 06:51:15.108172 DQS0 = 0, DQS1 = 0
1843 06:51:15.109820 DQM Delay:
1844 06:51:15.110283 DQM0 = 86, DQM1 = 80
1845 06:51:15.113055 DQ Delay:
1846 06:51:15.116468 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1847 06:51:15.120742 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =84
1848 06:51:15.122886 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1849 06:51:15.126317 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1850 06:51:15.126782
1851 06:51:15.127149
1852 06:51:15.133558 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1853 06:51:15.136708 CH1 RK0: MR19=606, MR18=1C2F
1854 06:51:15.143292 CH1_RK0: MR19=0x606, MR18=0x1C2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1855 06:51:15.143884
1856 06:51:15.146422 ----->DramcWriteLeveling(PI) begin...
1857 06:51:15.147089 ==
1858 06:51:15.149908 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 06:51:15.153195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 06:51:15.153620 ==
1861 06:51:15.156496 Write leveling (Byte 0): 25 => 25
1862 06:51:15.159645 Write leveling (Byte 1): 28 => 28
1863 06:51:15.162823 DramcWriteLeveling(PI) end<-----
1864 06:51:15.163244
1865 06:51:15.163687 ==
1866 06:51:15.166236 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 06:51:15.169484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 06:51:15.169909 ==
1869 06:51:15.172845 [Gating] SW mode calibration
1870 06:51:15.179604 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1871 06:51:15.185724 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1872 06:51:15.189202 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1873 06:51:15.192707 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1874 06:51:15.200000 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 06:51:15.202659 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 06:51:15.206004 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 06:51:15.212646 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 06:51:15.216120 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 06:51:15.219113 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 06:51:15.225814 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 06:51:15.229558 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 06:51:15.232614 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 06:51:15.239177 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 06:51:15.242481 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 06:51:15.245721 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 06:51:15.252899 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 06:51:15.256103 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 06:51:15.259509 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1889 06:51:15.266573 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1890 06:51:15.269188 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 06:51:15.272869 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 06:51:15.279306 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 06:51:15.282970 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 06:51:15.285954 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 06:51:15.292636 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 06:51:15.296475 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 06:51:15.300072 0 9 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
1898 06:51:15.302573 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1899 06:51:15.309504 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 06:51:15.312767 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 06:51:15.316105 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 06:51:15.322825 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 06:51:15.325793 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 06:51:15.329765 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1905 06:51:15.336209 0 10 4 | B1->B0 | 3333 2a2a | 1 1 | (1 1) (1 0)
1906 06:51:15.339781 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1907 06:51:15.342782 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 06:51:15.349803 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 06:51:15.352951 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 06:51:15.355734 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 06:51:15.362559 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 06:51:15.365892 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1913 06:51:15.368915 0 11 4 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 0)
1914 06:51:15.376021 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1915 06:51:15.379355 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 06:51:15.382603 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 06:51:15.388791 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 06:51:15.392522 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 06:51:15.395770 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 06:51:15.402136 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1921 06:51:15.405407 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1922 06:51:15.408925 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 06:51:15.415471 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 06:51:15.418927 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 06:51:15.422043 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 06:51:15.428893 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 06:51:15.432048 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 06:51:15.435610 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 06:51:15.438529 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 06:51:15.445657 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 06:51:15.448852 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 06:51:15.452159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 06:51:15.458531 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 06:51:15.462540 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 06:51:15.465387 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 06:51:15.471943 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1937 06:51:15.475357 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1938 06:51:15.478770 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 06:51:15.482197 Total UI for P1: 0, mck2ui 16
1940 06:51:15.485343 best dqsien dly found for B0: ( 0, 14, 2)
1941 06:51:15.488762 Total UI for P1: 0, mck2ui 16
1942 06:51:15.491596 best dqsien dly found for B1: ( 0, 14, 6)
1943 06:51:15.495982 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1944 06:51:15.498469 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1945 06:51:15.502238
1946 06:51:15.505160 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1947 06:51:15.508216 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1948 06:51:15.511929 [Gating] SW calibration Done
1949 06:51:15.512392 ==
1950 06:51:15.514877 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 06:51:15.519068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 06:51:15.519692 ==
1953 06:51:15.520067 RX Vref Scan: 0
1954 06:51:15.520414
1955 06:51:15.522026 RX Vref 0 -> 0, step: 1
1956 06:51:15.522557
1957 06:51:15.525240 RX Delay -130 -> 252, step: 16
1958 06:51:15.528527 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1959 06:51:15.533383 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1960 06:51:15.538282 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1961 06:51:15.541110 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1962 06:51:15.544857 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1963 06:51:15.547806 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1964 06:51:15.551445 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1965 06:51:15.557920 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1966 06:51:15.560891 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1967 06:51:15.564616 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1968 06:51:15.567979 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1969 06:51:15.571501 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1970 06:51:15.577551 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1971 06:51:15.581225 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1972 06:51:15.584569 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1973 06:51:15.587667 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1974 06:51:15.588082 ==
1975 06:51:15.590756 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 06:51:15.597633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 06:51:15.597857 ==
1978 06:51:15.598034 DQS Delay:
1979 06:51:15.600805 DQS0 = 0, DQS1 = 0
1980 06:51:15.600983 DQM Delay:
1981 06:51:15.601124 DQM0 = 80, DQM1 = 78
1982 06:51:15.604127 DQ Delay:
1983 06:51:15.607252 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1984 06:51:15.610721 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1985 06:51:15.613769 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1986 06:51:15.617251 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1987 06:51:15.617363
1988 06:51:15.617452
1989 06:51:15.617534 ==
1990 06:51:15.620440 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 06:51:15.624443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 06:51:15.624543 ==
1993 06:51:15.624623
1994 06:51:15.624697
1995 06:51:15.627367 TX Vref Scan disable
1996 06:51:15.627460 == TX Byte 0 ==
1997 06:51:15.633847 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1998 06:51:15.637230 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1999 06:51:15.637311 == TX Byte 1 ==
2000 06:51:15.643761 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2001 06:51:15.647471 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2002 06:51:15.647551 ==
2003 06:51:15.650443 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 06:51:15.653990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 06:51:15.654072 ==
2006 06:51:15.668196 TX Vref=22, minBit 1, minWin=27, winSum=446
2007 06:51:15.671446 TX Vref=24, minBit 0, minWin=27, winSum=448
2008 06:51:15.674718 TX Vref=26, minBit 1, minWin=27, winSum=451
2009 06:51:15.678169 TX Vref=28, minBit 1, minWin=27, winSum=453
2010 06:51:15.681416 TX Vref=30, minBit 1, minWin=27, winSum=453
2011 06:51:15.688405 TX Vref=32, minBit 3, minWin=27, winSum=452
2012 06:51:15.691683 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 28
2013 06:51:15.691840
2014 06:51:15.694616 Final TX Range 1 Vref 28
2015 06:51:15.694773
2016 06:51:15.694847 ==
2017 06:51:15.698145 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 06:51:15.701314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 06:51:15.704382 ==
2020 06:51:15.704532
2021 06:51:15.704623
2022 06:51:15.704697 TX Vref Scan disable
2023 06:51:15.708604 == TX Byte 0 ==
2024 06:51:15.711690 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2025 06:51:15.718488 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2026 06:51:15.718681 == TX Byte 1 ==
2027 06:51:15.721607 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2028 06:51:15.728353 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2029 06:51:15.728570
2030 06:51:15.728711 [DATLAT]
2031 06:51:15.728831 Freq=800, CH1 RK1
2032 06:51:15.728954
2033 06:51:15.731277 DATLAT Default: 0xa
2034 06:51:15.731529 0, 0xFFFF, sum = 0
2035 06:51:15.735393 1, 0xFFFF, sum = 0
2036 06:51:15.735656 2, 0xFFFF, sum = 0
2037 06:51:15.738112 3, 0xFFFF, sum = 0
2038 06:51:15.741766 4, 0xFFFF, sum = 0
2039 06:51:15.742055 5, 0xFFFF, sum = 0
2040 06:51:15.745058 6, 0xFFFF, sum = 0
2041 06:51:15.745288 7, 0xFFFF, sum = 0
2042 06:51:15.748429 8, 0xFFFF, sum = 0
2043 06:51:15.748787 9, 0x0, sum = 1
2044 06:51:15.751716 10, 0x0, sum = 2
2045 06:51:15.752028 11, 0x0, sum = 3
2046 06:51:15.752357 12, 0x0, sum = 4
2047 06:51:15.755055 best_step = 10
2048 06:51:15.755542
2049 06:51:15.755974 ==
2050 06:51:15.758217 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 06:51:15.761986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 06:51:15.762545 ==
2053 06:51:15.765010 RX Vref Scan: 0
2054 06:51:15.765570
2055 06:51:15.765931 RX Vref 0 -> 0, step: 1
2056 06:51:15.768520
2057 06:51:15.768974 RX Delay -95 -> 252, step: 8
2058 06:51:15.775554 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2059 06:51:15.778628 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2060 06:51:15.782496 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2061 06:51:15.785156 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2062 06:51:15.789055 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2063 06:51:15.795085 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2064 06:51:15.798418 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2065 06:51:15.801807 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2066 06:51:15.805157 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2067 06:51:15.808328 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2068 06:51:15.814538 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2069 06:51:15.818584 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2070 06:51:15.821282 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2071 06:51:15.824358 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2072 06:51:15.831255 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2073 06:51:15.834865 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2074 06:51:15.835294 ==
2075 06:51:15.838281 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 06:51:15.841227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 06:51:15.841651 ==
2078 06:51:15.844482 DQS Delay:
2079 06:51:15.844909 DQS0 = 0, DQS1 = 0
2080 06:51:15.845250 DQM Delay:
2081 06:51:15.848233 DQM0 = 86, DQM1 = 82
2082 06:51:15.848668 DQ Delay:
2083 06:51:15.851592 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2084 06:51:15.854729 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2085 06:51:15.857919 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2086 06:51:15.861844 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2087 06:51:15.862266
2088 06:51:15.862600
2089 06:51:15.870910 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2090 06:51:15.871339 CH1 RK1: MR19=606, MR18=1C37
2091 06:51:15.877577 CH1_RK1: MR19=0x606, MR18=0x1C37, DQSOSC=395, MR23=63, INC=94, DEC=63
2092 06:51:15.881488 [RxdqsGatingPostProcess] freq 800
2093 06:51:15.887778 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2094 06:51:15.891302 Pre-setting of DQS Precalculation
2095 06:51:15.894362 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2096 06:51:15.900922 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2097 06:51:15.911347 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2098 06:51:15.911822
2099 06:51:15.912157
2100 06:51:15.914613 [Calibration Summary] 1600 Mbps
2101 06:51:15.915027 CH 0, Rank 0
2102 06:51:15.917494 SW Impedance : PASS
2103 06:51:15.917916 DUTY Scan : NO K
2104 06:51:15.920908 ZQ Calibration : PASS
2105 06:51:15.924172 Jitter Meter : NO K
2106 06:51:15.924591 CBT Training : PASS
2107 06:51:15.927242 Write leveling : PASS
2108 06:51:15.930915 RX DQS gating : PASS
2109 06:51:15.931335 RX DQ/DQS(RDDQC) : PASS
2110 06:51:15.933898 TX DQ/DQS : PASS
2111 06:51:15.937812 RX DATLAT : PASS
2112 06:51:15.938232 RX DQ/DQS(Engine): PASS
2113 06:51:15.940904 TX OE : NO K
2114 06:51:15.941323 All Pass.
2115 06:51:15.941651
2116 06:51:15.944036 CH 0, Rank 1
2117 06:51:15.944451 SW Impedance : PASS
2118 06:51:15.946902 DUTY Scan : NO K
2119 06:51:15.947322 ZQ Calibration : PASS
2120 06:51:15.950321 Jitter Meter : NO K
2121 06:51:15.953597 CBT Training : PASS
2122 06:51:15.954018 Write leveling : PASS
2123 06:51:15.956837 RX DQS gating : PASS
2124 06:51:15.960456 RX DQ/DQS(RDDQC) : PASS
2125 06:51:15.960874 TX DQ/DQS : PASS
2126 06:51:15.963810 RX DATLAT : PASS
2127 06:51:15.966998 RX DQ/DQS(Engine): PASS
2128 06:51:15.967471 TX OE : NO K
2129 06:51:15.970203 All Pass.
2130 06:51:15.970632
2131 06:51:15.970977 CH 1, Rank 0
2132 06:51:15.973485 SW Impedance : PASS
2133 06:51:15.973902 DUTY Scan : NO K
2134 06:51:15.976744 ZQ Calibration : PASS
2135 06:51:15.980076 Jitter Meter : NO K
2136 06:51:15.980498 CBT Training : PASS
2137 06:51:15.983284 Write leveling : PASS
2138 06:51:15.986975 RX DQS gating : PASS
2139 06:51:15.987445 RX DQ/DQS(RDDQC) : PASS
2140 06:51:15.990694 TX DQ/DQS : PASS
2141 06:51:15.993549 RX DATLAT : PASS
2142 06:51:15.994143 RX DQ/DQS(Engine): PASS
2143 06:51:15.996869 TX OE : NO K
2144 06:51:15.997289 All Pass.
2145 06:51:15.997621
2146 06:51:16.000416 CH 1, Rank 1
2147 06:51:16.000833 SW Impedance : PASS
2148 06:51:16.003558 DUTY Scan : NO K
2149 06:51:16.003976 ZQ Calibration : PASS
2150 06:51:16.006839 Jitter Meter : NO K
2151 06:51:16.010223 CBT Training : PASS
2152 06:51:16.010637 Write leveling : PASS
2153 06:51:16.013558 RX DQS gating : PASS
2154 06:51:16.017485 RX DQ/DQS(RDDQC) : PASS
2155 06:51:16.017899 TX DQ/DQS : PASS
2156 06:51:16.019924 RX DATLAT : PASS
2157 06:51:16.023402 RX DQ/DQS(Engine): PASS
2158 06:51:16.023834 TX OE : NO K
2159 06:51:16.027043 All Pass.
2160 06:51:16.027545
2161 06:51:16.027940 DramC Write-DBI off
2162 06:51:16.030150 PER_BANK_REFRESH: Hybrid Mode
2163 06:51:16.030566 TX_TRACKING: ON
2164 06:51:16.033246 [GetDramInforAfterCalByMRR] Vendor 6.
2165 06:51:16.040112 [GetDramInforAfterCalByMRR] Revision 606.
2166 06:51:16.043618 [GetDramInforAfterCalByMRR] Revision 2 0.
2167 06:51:16.044036 MR0 0x3b3b
2168 06:51:16.044368 MR8 0x5151
2169 06:51:16.046910 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 06:51:16.049711
2171 06:51:16.050125 MR0 0x3b3b
2172 06:51:16.050455 MR8 0x5151
2173 06:51:16.052962 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 06:51:16.053380
2175 06:51:16.063088 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2176 06:51:16.066562 [FAST_K] Save calibration result to emmc
2177 06:51:16.069539 [FAST_K] Save calibration result to emmc
2178 06:51:16.073412 dram_init: config_dvfs: 1
2179 06:51:16.076679 dramc_set_vcore_voltage set vcore to 662500
2180 06:51:16.080040 Read voltage for 1200, 2
2181 06:51:16.080457 Vio18 = 0
2182 06:51:16.080787 Vcore = 662500
2183 06:51:16.083306 Vdram = 0
2184 06:51:16.083757 Vddq = 0
2185 06:51:16.084090 Vmddr = 0
2186 06:51:16.089701 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2187 06:51:16.093041 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2188 06:51:16.096299 MEM_TYPE=3, freq_sel=15
2189 06:51:16.099783 sv_algorithm_assistance_LP4_1600
2190 06:51:16.103026 ============ PULL DRAM RESETB DOWN ============
2191 06:51:16.106058 ========== PULL DRAM RESETB DOWN end =========
2192 06:51:16.112751 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2193 06:51:16.115945 ===================================
2194 06:51:16.119412 LPDDR4 DRAM CONFIGURATION
2195 06:51:16.122598 ===================================
2196 06:51:16.123015 EX_ROW_EN[0] = 0x0
2197 06:51:16.126293 EX_ROW_EN[1] = 0x0
2198 06:51:16.126710 LP4Y_EN = 0x0
2199 06:51:16.129174 WORK_FSP = 0x0
2200 06:51:16.129589 WL = 0x4
2201 06:51:16.133599 RL = 0x4
2202 06:51:16.134015 BL = 0x2
2203 06:51:16.136411 RPST = 0x0
2204 06:51:16.136832 RD_PRE = 0x0
2205 06:51:16.139313 WR_PRE = 0x1
2206 06:51:16.139787 WR_PST = 0x0
2207 06:51:16.142473 DBI_WR = 0x0
2208 06:51:16.142890 DBI_RD = 0x0
2209 06:51:16.146130 OTF = 0x1
2210 06:51:16.149480 ===================================
2211 06:51:16.152712 ===================================
2212 06:51:16.153132 ANA top config
2213 06:51:16.155670 ===================================
2214 06:51:16.159430 DLL_ASYNC_EN = 0
2215 06:51:16.162418 ALL_SLAVE_EN = 0
2216 06:51:16.166372 NEW_RANK_MODE = 1
2217 06:51:16.166792 DLL_IDLE_MODE = 1
2218 06:51:16.169376 LP45_APHY_COMB_EN = 1
2219 06:51:16.172660 TX_ODT_DIS = 1
2220 06:51:16.175805 NEW_8X_MODE = 1
2221 06:51:16.179465 ===================================
2222 06:51:16.182482 ===================================
2223 06:51:16.186050 data_rate = 2400
2224 06:51:16.189517 CKR = 1
2225 06:51:16.189935 DQ_P2S_RATIO = 8
2226 06:51:16.192606 ===================================
2227 06:51:16.195808 CA_P2S_RATIO = 8
2228 06:51:16.199105 DQ_CA_OPEN = 0
2229 06:51:16.202244 DQ_SEMI_OPEN = 0
2230 06:51:16.205621 CA_SEMI_OPEN = 0
2231 06:51:16.206036 CA_FULL_RATE = 0
2232 06:51:16.209543 DQ_CKDIV4_EN = 0
2233 06:51:16.212307 CA_CKDIV4_EN = 0
2234 06:51:16.215765 CA_PREDIV_EN = 0
2235 06:51:16.218950 PH8_DLY = 17
2236 06:51:16.222441 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2237 06:51:16.222860 DQ_AAMCK_DIV = 4
2238 06:51:16.225799 CA_AAMCK_DIV = 4
2239 06:51:16.228767 CA_ADMCK_DIV = 4
2240 06:51:16.232083 DQ_TRACK_CA_EN = 0
2241 06:51:16.235962 CA_PICK = 1200
2242 06:51:16.239676 CA_MCKIO = 1200
2243 06:51:16.242236 MCKIO_SEMI = 0
2244 06:51:16.245722 PLL_FREQ = 2366
2245 06:51:16.246165 DQ_UI_PI_RATIO = 32
2246 06:51:16.248648 CA_UI_PI_RATIO = 0
2247 06:51:16.252061 ===================================
2248 06:51:16.255475 ===================================
2249 06:51:16.258791 memory_type:LPDDR4
2250 06:51:16.262060 GP_NUM : 10
2251 06:51:16.262476 SRAM_EN : 1
2252 06:51:16.266058 MD32_EN : 0
2253 06:51:16.268965 ===================================
2254 06:51:16.269386 [ANA_INIT] >>>>>>>>>>>>>>
2255 06:51:16.272151 <<<<<< [CONFIGURE PHASE]: ANA_TX
2256 06:51:16.275844 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2257 06:51:16.278721 ===================================
2258 06:51:16.282164 data_rate = 2400,PCW = 0X5b00
2259 06:51:16.285684 ===================================
2260 06:51:16.288511 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2261 06:51:16.295351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 06:51:16.301777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 06:51:16.305308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2264 06:51:16.308502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2265 06:51:16.312505 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2266 06:51:16.315260 [ANA_INIT] flow start
2267 06:51:16.315712 [ANA_INIT] PLL >>>>>>>>
2268 06:51:16.318932 [ANA_INIT] PLL <<<<<<<<
2269 06:51:16.321726 [ANA_INIT] MIDPI >>>>>>>>
2270 06:51:16.322142 [ANA_INIT] MIDPI <<<<<<<<
2271 06:51:16.325309 [ANA_INIT] DLL >>>>>>>>
2272 06:51:16.328126 [ANA_INIT] DLL <<<<<<<<
2273 06:51:16.328546 [ANA_INIT] flow end
2274 06:51:16.335011 ============ LP4 DIFF to SE enter ============
2275 06:51:16.338216 ============ LP4 DIFF to SE exit ============
2276 06:51:16.341556 [ANA_INIT] <<<<<<<<<<<<<
2277 06:51:16.344784 [Flow] Enable top DCM control >>>>>
2278 06:51:16.348573 [Flow] Enable top DCM control <<<<<
2279 06:51:16.348990 Enable DLL master slave shuffle
2280 06:51:16.354214 ==============================================================
2281 06:51:16.357718 Gating Mode config
2282 06:51:16.361228 ==============================================================
2283 06:51:16.364668 Config description:
2284 06:51:16.374307 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2285 06:51:16.381298 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2286 06:51:16.384338 SELPH_MODE 0: By rank 1: By Phase
2287 06:51:16.391404 ==============================================================
2288 06:51:16.394241 GAT_TRACK_EN = 1
2289 06:51:16.397729 RX_GATING_MODE = 2
2290 06:51:16.400909 RX_GATING_TRACK_MODE = 2
2291 06:51:16.404286 SELPH_MODE = 1
2292 06:51:16.404368 PICG_EARLY_EN = 1
2293 06:51:16.407680 VALID_LAT_VALUE = 1
2294 06:51:16.414309 ==============================================================
2295 06:51:16.417370 Enter into Gating configuration >>>>
2296 06:51:16.420658 Exit from Gating configuration <<<<
2297 06:51:16.424119 Enter into DVFS_PRE_config >>>>>
2298 06:51:16.433873 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2299 06:51:16.437242 Exit from DVFS_PRE_config <<<<<
2300 06:51:16.440840 Enter into PICG configuration >>>>
2301 06:51:16.443775 Exit from PICG configuration <<<<
2302 06:51:16.447716 [RX_INPUT] configuration >>>>>
2303 06:51:16.450765 [RX_INPUT] configuration <<<<<
2304 06:51:16.454219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2305 06:51:16.460310 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2306 06:51:16.467241 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 06:51:16.474126 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 06:51:16.480727 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 06:51:16.487260 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 06:51:16.490273 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2311 06:51:16.493626 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2312 06:51:16.497183 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2313 06:51:16.503860 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2314 06:51:16.507267 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2315 06:51:16.510242 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 06:51:16.513989 ===================================
2317 06:51:16.516965 LPDDR4 DRAM CONFIGURATION
2318 06:51:16.520597 ===================================
2319 06:51:16.520894 EX_ROW_EN[0] = 0x0
2320 06:51:16.523584 EX_ROW_EN[1] = 0x0
2321 06:51:16.523880 LP4Y_EN = 0x0
2322 06:51:16.527084 WORK_FSP = 0x0
2323 06:51:16.527511 WL = 0x4
2324 06:51:16.531124 RL = 0x4
2325 06:51:16.531577 BL = 0x2
2326 06:51:16.534144 RPST = 0x0
2327 06:51:16.536926 RD_PRE = 0x0
2328 06:51:16.537342 WR_PRE = 0x1
2329 06:51:16.540688 WR_PST = 0x0
2330 06:51:16.541103 DBI_WR = 0x0
2331 06:51:16.544659 DBI_RD = 0x0
2332 06:51:16.545075 OTF = 0x1
2333 06:51:16.547232 ===================================
2334 06:51:16.550454 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2335 06:51:16.557167 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2336 06:51:16.560561 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2337 06:51:16.563190 ===================================
2338 06:51:16.566780 LPDDR4 DRAM CONFIGURATION
2339 06:51:16.570099 ===================================
2340 06:51:16.570181 EX_ROW_EN[0] = 0x10
2341 06:51:16.573674 EX_ROW_EN[1] = 0x0
2342 06:51:16.573754 LP4Y_EN = 0x0
2343 06:51:16.576728 WORK_FSP = 0x0
2344 06:51:16.576809 WL = 0x4
2345 06:51:16.580099 RL = 0x4
2346 06:51:16.580180 BL = 0x2
2347 06:51:16.583215 RPST = 0x0
2348 06:51:16.583322 RD_PRE = 0x0
2349 06:51:16.586873 WR_PRE = 0x1
2350 06:51:16.586954 WR_PST = 0x0
2351 06:51:16.590568 DBI_WR = 0x0
2352 06:51:16.593247 DBI_RD = 0x0
2353 06:51:16.593327 OTF = 0x1
2354 06:51:16.596946 ===================================
2355 06:51:16.603072 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2356 06:51:16.603183 ==
2357 06:51:16.606278 Dram Type= 6, Freq= 0, CH_0, rank 0
2358 06:51:16.609892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 06:51:16.609974 ==
2360 06:51:16.613691 [Duty_Offset_Calibration]
2361 06:51:16.613780 B0:2 B1:0 CA:4
2362 06:51:16.613844
2363 06:51:16.616756 [DutyScan_Calibration_Flow] k_type=0
2364 06:51:16.626755
2365 06:51:16.626836 ==CLK 0==
2366 06:51:16.630009 Final CLK duty delay cell = -4
2367 06:51:16.633426 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2368 06:51:16.636438 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2369 06:51:16.639947 [-4] AVG Duty = 4937%(X100)
2370 06:51:16.640028
2371 06:51:16.643118 CH0 CLK Duty spec in!! Max-Min= 187%
2372 06:51:16.646820 [DutyScan_Calibration_Flow] ====Done====
2373 06:51:16.646905
2374 06:51:16.650285 [DutyScan_Calibration_Flow] k_type=1
2375 06:51:16.666158
2376 06:51:16.666238 ==DQS 0 ==
2377 06:51:16.669209 Final DQS duty delay cell = 0
2378 06:51:16.672589 [0] MAX Duty = 5156%(X100), DQS PI = 20
2379 06:51:16.675908 [0] MIN Duty = 5093%(X100), DQS PI = 2
2380 06:51:16.679198 [0] AVG Duty = 5124%(X100)
2381 06:51:16.679278
2382 06:51:16.679341 ==DQS 1 ==
2383 06:51:16.682845 Final DQS duty delay cell = 0
2384 06:51:16.685996 [0] MAX Duty = 5125%(X100), DQS PI = 50
2385 06:51:16.689585 [0] MIN Duty = 4969%(X100), DQS PI = 62
2386 06:51:16.692701 [0] AVG Duty = 5047%(X100)
2387 06:51:16.692781
2388 06:51:16.695806 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2389 06:51:16.695887
2390 06:51:16.699641 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2391 06:51:16.702912 [DutyScan_Calibration_Flow] ====Done====
2392 06:51:16.702991
2393 06:51:16.706354 [DutyScan_Calibration_Flow] k_type=3
2394 06:51:16.722951
2395 06:51:16.723030 ==DQM 0 ==
2396 06:51:16.726321 Final DQM duty delay cell = 0
2397 06:51:16.729182 [0] MAX Duty = 5125%(X100), DQS PI = 20
2398 06:51:16.733051 [0] MIN Duty = 4844%(X100), DQS PI = 52
2399 06:51:16.736208 [0] AVG Duty = 4984%(X100)
2400 06:51:16.736290
2401 06:51:16.736360 ==DQM 1 ==
2402 06:51:16.739377 Final DQM duty delay cell = 0
2403 06:51:16.742592 [0] MAX Duty = 5000%(X100), DQS PI = 8
2404 06:51:16.745787 [0] MIN Duty = 4875%(X100), DQS PI = 12
2405 06:51:16.749059 [0] AVG Duty = 4937%(X100)
2406 06:51:16.749186
2407 06:51:16.752807 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2408 06:51:16.752926
2409 06:51:16.756197 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2410 06:51:16.759312 [DutyScan_Calibration_Flow] ====Done====
2411 06:51:16.759505
2412 06:51:16.762447 [DutyScan_Calibration_Flow] k_type=2
2413 06:51:16.779155
2414 06:51:16.779500 ==DQ 0 ==
2415 06:51:16.783008 Final DQ duty delay cell = 0
2416 06:51:16.786102 [0] MAX Duty = 5125%(X100), DQS PI = 18
2417 06:51:16.789412 [0] MIN Duty = 4969%(X100), DQS PI = 50
2418 06:51:16.793131 [0] AVG Duty = 5047%(X100)
2419 06:51:16.793543
2420 06:51:16.793870 ==DQ 1 ==
2421 06:51:16.795928 Final DQ duty delay cell = 0
2422 06:51:16.799420 [0] MAX Duty = 5156%(X100), DQS PI = 6
2423 06:51:16.802626 [0] MIN Duty = 4938%(X100), DQS PI = 16
2424 06:51:16.803062 [0] AVG Duty = 5047%(X100)
2425 06:51:16.805940
2426 06:51:16.809206 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2427 06:51:16.809623
2428 06:51:16.813056 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2429 06:51:16.816217 [DutyScan_Calibration_Flow] ====Done====
2430 06:51:16.816636 ==
2431 06:51:16.819034 Dram Type= 6, Freq= 0, CH_1, rank 0
2432 06:51:16.822245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2433 06:51:16.822807 ==
2434 06:51:16.825643 [Duty_Offset_Calibration]
2435 06:51:16.826056 B0:0 B1:-1 CA:3
2436 06:51:16.826386
2437 06:51:16.828691 [DutyScan_Calibration_Flow] k_type=0
2438 06:51:16.838457
2439 06:51:16.838873 ==CLK 0==
2440 06:51:16.841999 Final CLK duty delay cell = -4
2441 06:51:16.845618 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2442 06:51:16.848946 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2443 06:51:16.851781 [-4] AVG Duty = 4938%(X100)
2444 06:51:16.852198
2445 06:51:16.855118 CH1 CLK Duty spec in!! Max-Min= 124%
2446 06:51:16.858372 [DutyScan_Calibration_Flow] ====Done====
2447 06:51:16.858784
2448 06:51:16.861599 [DutyScan_Calibration_Flow] k_type=1
2449 06:51:16.877418
2450 06:51:16.877833 ==DQS 0 ==
2451 06:51:16.880557 Final DQS duty delay cell = 0
2452 06:51:16.884122 [0] MAX Duty = 5156%(X100), DQS PI = 28
2453 06:51:16.887538 [0] MIN Duty = 4907%(X100), DQS PI = 38
2454 06:51:16.891060 [0] AVG Duty = 5031%(X100)
2455 06:51:16.891719
2456 06:51:16.892062 ==DQS 1 ==
2457 06:51:16.894478 Final DQS duty delay cell = -4
2458 06:51:16.897053 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2459 06:51:16.900602 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2460 06:51:16.903862 [-4] AVG Duty = 4937%(X100)
2461 06:51:16.904397
2462 06:51:16.907295 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2463 06:51:16.907900
2464 06:51:16.910459 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2465 06:51:16.913835 [DutyScan_Calibration_Flow] ====Done====
2466 06:51:16.914327
2467 06:51:16.917531 [DutyScan_Calibration_Flow] k_type=3
2468 06:51:16.934317
2469 06:51:16.934849 ==DQM 0 ==
2470 06:51:16.937534 Final DQM duty delay cell = 0
2471 06:51:16.940958 [0] MAX Duty = 5031%(X100), DQS PI = 28
2472 06:51:16.944121 [0] MIN Duty = 4782%(X100), DQS PI = 38
2473 06:51:16.947250 [0] AVG Duty = 4906%(X100)
2474 06:51:16.947789
2475 06:51:16.948178 ==DQM 1 ==
2476 06:51:16.950457 Final DQM duty delay cell = 0
2477 06:51:16.954105 [0] MAX Duty = 5000%(X100), DQS PI = 34
2478 06:51:16.957413 [0] MIN Duty = 4844%(X100), DQS PI = 0
2479 06:51:16.961036 [0] AVG Duty = 4922%(X100)
2480 06:51:16.961450
2481 06:51:16.964354 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2482 06:51:16.964769
2483 06:51:16.966911 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2484 06:51:16.970712 [DutyScan_Calibration_Flow] ====Done====
2485 06:51:16.971295
2486 06:51:16.973648 [DutyScan_Calibration_Flow] k_type=2
2487 06:51:16.990201
2488 06:51:16.990717 ==DQ 0 ==
2489 06:51:16.993362 Final DQ duty delay cell = -4
2490 06:51:16.996409 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2491 06:51:17.000004 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2492 06:51:17.003230 [-4] AVG Duty = 4938%(X100)
2493 06:51:17.003680
2494 06:51:17.004017 ==DQ 1 ==
2495 06:51:17.006501 Final DQ duty delay cell = 0
2496 06:51:17.009642 [0] MAX Duty = 5031%(X100), DQS PI = 34
2497 06:51:17.013130 [0] MIN Duty = 4844%(X100), DQS PI = 0
2498 06:51:17.016754 [0] AVG Duty = 4937%(X100)
2499 06:51:17.017175
2500 06:51:17.019890 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2501 06:51:17.020311
2502 06:51:17.023102 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2503 06:51:17.026345 [DutyScan_Calibration_Flow] ====Done====
2504 06:51:17.029889 nWR fixed to 30
2505 06:51:17.033026 [ModeRegInit_LP4] CH0 RK0
2506 06:51:17.033448 [ModeRegInit_LP4] CH0 RK1
2507 06:51:17.036456 [ModeRegInit_LP4] CH1 RK0
2508 06:51:17.039297 [ModeRegInit_LP4] CH1 RK1
2509 06:51:17.039753 match AC timing 7
2510 06:51:17.046370 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2511 06:51:17.049761 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2512 06:51:17.052826 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2513 06:51:17.059650 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2514 06:51:17.063329 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2515 06:51:17.064004 ==
2516 06:51:17.066135 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 06:51:17.069909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 06:51:17.070420 ==
2519 06:51:17.076483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 06:51:17.082673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2521 06:51:17.090031 [CA 0] Center 39 (9~70) winsize 62
2522 06:51:17.093550 [CA 1] Center 39 (9~69) winsize 61
2523 06:51:17.096523 [CA 2] Center 35 (5~66) winsize 62
2524 06:51:17.100333 [CA 3] Center 35 (5~66) winsize 62
2525 06:51:17.103342 [CA 4] Center 33 (3~64) winsize 62
2526 06:51:17.106793 [CA 5] Center 33 (3~63) winsize 61
2527 06:51:17.107328
2528 06:51:17.110283 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2529 06:51:17.110714
2530 06:51:17.113626 [CATrainingPosCal] consider 1 rank data
2531 06:51:17.116777 u2DelayCellTimex100 = 270/100 ps
2532 06:51:17.119944 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2533 06:51:17.126759 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2534 06:51:17.129902 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 06:51:17.133164 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2536 06:51:17.137063 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2537 06:51:17.140113 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2538 06:51:17.140545
2539 06:51:17.143593 CA PerBit enable=1, Macro0, CA PI delay=33
2540 06:51:17.144026
2541 06:51:17.146618 [CBTSetCACLKResult] CA Dly = 33
2542 06:51:17.147081 CS Dly: 7 (0~38)
2543 06:51:17.149507 ==
2544 06:51:17.152879 Dram Type= 6, Freq= 0, CH_0, rank 1
2545 06:51:17.156661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 06:51:17.157083 ==
2547 06:51:17.160290 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2548 06:51:17.166534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2549 06:51:17.176181 [CA 0] Center 39 (9~70) winsize 62
2550 06:51:17.179538 [CA 1] Center 39 (9~70) winsize 62
2551 06:51:17.182754 [CA 2] Center 35 (5~66) winsize 62
2552 06:51:17.186131 [CA 3] Center 35 (5~66) winsize 62
2553 06:51:17.189246 [CA 4] Center 34 (4~65) winsize 62
2554 06:51:17.192563 [CA 5] Center 33 (3~63) winsize 61
2555 06:51:17.193045
2556 06:51:17.195517 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2557 06:51:17.195939
2558 06:51:17.198757 [CATrainingPosCal] consider 2 rank data
2559 06:51:17.202428 u2DelayCellTimex100 = 270/100 ps
2560 06:51:17.205965 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2561 06:51:17.209266 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2562 06:51:17.215762 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 06:51:17.219179 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2564 06:51:17.222556 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2565 06:51:17.225428 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2566 06:51:17.225983
2567 06:51:17.229282 CA PerBit enable=1, Macro0, CA PI delay=33
2568 06:51:17.229750
2569 06:51:17.232097 [CBTSetCACLKResult] CA Dly = 33
2570 06:51:17.232675 CS Dly: 8 (0~41)
2571 06:51:17.233168
2572 06:51:17.236060 ----->DramcWriteLeveling(PI) begin...
2573 06:51:17.239155 ==
2574 06:51:17.242293 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 06:51:17.245377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 06:51:17.245804 ==
2577 06:51:17.248855 Write leveling (Byte 0): 31 => 31
2578 06:51:17.252171 Write leveling (Byte 1): 26 => 26
2579 06:51:17.255548 DramcWriteLeveling(PI) end<-----
2580 06:51:17.255975
2581 06:51:17.256487 ==
2582 06:51:17.258502 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 06:51:17.262077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 06:51:17.262522 ==
2585 06:51:17.265842 [Gating] SW mode calibration
2586 06:51:17.272196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2587 06:51:17.278792 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2588 06:51:17.282487 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2589 06:51:17.285506 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2590 06:51:17.291841 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 06:51:17.295417 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 06:51:17.298696 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 06:51:17.305374 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 06:51:17.308739 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2595 06:51:17.311975 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
2596 06:51:17.315316 1 0 0 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2597 06:51:17.321797 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2598 06:51:17.325875 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 06:51:17.328571 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 06:51:17.334988 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 06:51:17.338337 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 06:51:17.342016 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2603 06:51:17.348910 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2604 06:51:17.352518 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (1 1) (0 0)
2605 06:51:17.355106 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 06:51:17.361956 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 06:51:17.365446 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 06:51:17.369619 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 06:51:17.375029 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 06:51:17.378256 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 06:51:17.381856 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2612 06:51:17.388058 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2613 06:51:17.391991 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2614 06:51:17.395157 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 06:51:17.401470 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 06:51:17.404679 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 06:51:17.407947 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 06:51:17.415127 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 06:51:17.418356 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 06:51:17.421681 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 06:51:17.428010 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 06:51:17.431548 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 06:51:17.434581 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 06:51:17.441490 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 06:51:17.445088 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 06:51:17.448142 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 06:51:17.454614 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2628 06:51:17.458288 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2629 06:51:17.461518 Total UI for P1: 0, mck2ui 16
2630 06:51:17.464637 best dqsien dly found for B0: ( 1, 3, 28)
2631 06:51:17.468285 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 06:51:17.471485 Total UI for P1: 0, mck2ui 16
2633 06:51:17.474777 best dqsien dly found for B1: ( 1, 4, 0)
2634 06:51:17.477876 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2635 06:51:17.481490 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2636 06:51:17.481912
2637 06:51:17.484770 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2638 06:51:17.491124 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2639 06:51:17.491594 [Gating] SW calibration Done
2640 06:51:17.491938 ==
2641 06:51:17.494176 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 06:51:17.501105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 06:51:17.501581 ==
2644 06:51:17.501933 RX Vref Scan: 0
2645 06:51:17.502249
2646 06:51:17.504609 RX Vref 0 -> 0, step: 1
2647 06:51:17.505030
2648 06:51:17.507657 RX Delay -40 -> 252, step: 8
2649 06:51:17.511039 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2650 06:51:17.514411 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2651 06:51:17.517618 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2652 06:51:17.520987 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2653 06:51:17.527851 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2654 06:51:17.531189 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2655 06:51:17.534213 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2656 06:51:17.537901 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2657 06:51:17.541074 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2658 06:51:17.547488 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2659 06:51:17.550860 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2660 06:51:17.554340 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2661 06:51:17.557889 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2662 06:51:17.561178 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2663 06:51:17.568095 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2664 06:51:17.570822 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2665 06:51:17.571238 ==
2666 06:51:17.574290 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 06:51:17.577715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 06:51:17.578137 ==
2669 06:51:17.580748 DQS Delay:
2670 06:51:17.581164 DQS0 = 0, DQS1 = 0
2671 06:51:17.581500 DQM Delay:
2672 06:51:17.584077 DQM0 = 118, DQM1 = 107
2673 06:51:17.584493 DQ Delay:
2674 06:51:17.587898 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2675 06:51:17.590713 DQ4 =123, DQ5 =111, DQ6 =123, DQ7 =127
2676 06:51:17.594322 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2677 06:51:17.601874 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2678 06:51:17.602298
2679 06:51:17.602633
2680 06:51:17.602945 ==
2681 06:51:17.604081 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 06:51:17.607661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 06:51:17.608086 ==
2684 06:51:17.608453
2685 06:51:17.608765
2686 06:51:17.610356 TX Vref Scan disable
2687 06:51:17.610777 == TX Byte 0 ==
2688 06:51:17.617383 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2689 06:51:17.620551 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2690 06:51:17.621059 == TX Byte 1 ==
2691 06:51:17.627630 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2692 06:51:17.630611 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2693 06:51:17.631027 ==
2694 06:51:17.633678 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 06:51:17.637041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 06:51:17.637734 ==
2697 06:51:17.650289 TX Vref=22, minBit 0, minWin=25, winSum=413
2698 06:51:17.653624 TX Vref=24, minBit 1, minWin=25, winSum=412
2699 06:51:17.657458 TX Vref=26, minBit 1, minWin=26, winSum=422
2700 06:51:17.660715 TX Vref=28, minBit 1, minWin=26, winSum=426
2701 06:51:17.663925 TX Vref=30, minBit 5, minWin=26, winSum=428
2702 06:51:17.667190 TX Vref=32, minBit 5, minWin=26, winSum=428
2703 06:51:17.674035 [TxChooseVref] Worse bit 5, Min win 26, Win sum 428, Final Vref 30
2704 06:51:17.674483
2705 06:51:17.677474 Final TX Range 1 Vref 30
2706 06:51:17.677912
2707 06:51:17.678265 ==
2708 06:51:17.681042 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 06:51:17.683444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 06:51:17.684033 ==
2711 06:51:17.687127
2712 06:51:17.687704
2713 06:51:17.688220 TX Vref Scan disable
2714 06:51:17.690082 == TX Byte 0 ==
2715 06:51:17.693464 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2716 06:51:17.700100 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2717 06:51:17.700528 == TX Byte 1 ==
2718 06:51:17.703293 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2719 06:51:17.710275 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2720 06:51:17.710701
2721 06:51:17.711137 [DATLAT]
2722 06:51:17.711510 Freq=1200, CH0 RK0
2723 06:51:17.711827
2724 06:51:17.714003 DATLAT Default: 0xd
2725 06:51:17.714459 0, 0xFFFF, sum = 0
2726 06:51:17.716806 1, 0xFFFF, sum = 0
2727 06:51:17.719895 2, 0xFFFF, sum = 0
2728 06:51:17.720351 3, 0xFFFF, sum = 0
2729 06:51:17.723193 4, 0xFFFF, sum = 0
2730 06:51:17.723705 5, 0xFFFF, sum = 0
2731 06:51:17.726598 6, 0xFFFF, sum = 0
2732 06:51:17.727027 7, 0xFFFF, sum = 0
2733 06:51:17.730082 8, 0xFFFF, sum = 0
2734 06:51:17.730640 9, 0xFFFF, sum = 0
2735 06:51:17.733195 10, 0xFFFF, sum = 0
2736 06:51:17.733622 11, 0xFFFF, sum = 0
2737 06:51:17.736847 12, 0x0, sum = 1
2738 06:51:17.737275 13, 0x0, sum = 2
2739 06:51:17.740314 14, 0x0, sum = 3
2740 06:51:17.740748 15, 0x0, sum = 4
2741 06:51:17.743353 best_step = 13
2742 06:51:17.743845
2743 06:51:17.744181 ==
2744 06:51:17.746501 Dram Type= 6, Freq= 0, CH_0, rank 0
2745 06:51:17.750215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2746 06:51:17.750645 ==
2747 06:51:17.750981 RX Vref Scan: 1
2748 06:51:17.751294
2749 06:51:17.753526 Set Vref Range= 32 -> 127
2750 06:51:17.753983
2751 06:51:17.756650 RX Vref 32 -> 127, step: 1
2752 06:51:17.757221
2753 06:51:17.759997 RX Delay -21 -> 252, step: 4
2754 06:51:17.760443
2755 06:51:17.762899 Set Vref, RX VrefLevel [Byte0]: 32
2756 06:51:17.766464 [Byte1]: 32
2757 06:51:17.766988
2758 06:51:17.769672 Set Vref, RX VrefLevel [Byte0]: 33
2759 06:51:17.772879 [Byte1]: 33
2760 06:51:17.776842
2761 06:51:17.777261 Set Vref, RX VrefLevel [Byte0]: 34
2762 06:51:17.779863 [Byte1]: 34
2763 06:51:17.784441
2764 06:51:17.784863 Set Vref, RX VrefLevel [Byte0]: 35
2765 06:51:17.787815 [Byte1]: 35
2766 06:51:17.792847
2767 06:51:17.793279 Set Vref, RX VrefLevel [Byte0]: 36
2768 06:51:17.795599 [Byte1]: 36
2769 06:51:17.800600
2770 06:51:17.801039 Set Vref, RX VrefLevel [Byte0]: 37
2771 06:51:17.803728 [Byte1]: 37
2772 06:51:17.808778
2773 06:51:17.809228 Set Vref, RX VrefLevel [Byte0]: 38
2774 06:51:17.812225 [Byte1]: 38
2775 06:51:17.816184
2776 06:51:17.816601 Set Vref, RX VrefLevel [Byte0]: 39
2777 06:51:17.819632 [Byte1]: 39
2778 06:51:17.824026
2779 06:51:17.824445 Set Vref, RX VrefLevel [Byte0]: 40
2780 06:51:17.827601 [Byte1]: 40
2781 06:51:17.832267
2782 06:51:17.832720 Set Vref, RX VrefLevel [Byte0]: 41
2783 06:51:17.835342 [Byte1]: 41
2784 06:51:17.840019
2785 06:51:17.840434 Set Vref, RX VrefLevel [Byte0]: 42
2786 06:51:17.843814 [Byte1]: 42
2787 06:51:17.847937
2788 06:51:17.848360 Set Vref, RX VrefLevel [Byte0]: 43
2789 06:51:17.852049 [Byte1]: 43
2790 06:51:17.855856
2791 06:51:17.856283 Set Vref, RX VrefLevel [Byte0]: 44
2792 06:51:17.859594 [Byte1]: 44
2793 06:51:17.864292
2794 06:51:17.864711 Set Vref, RX VrefLevel [Byte0]: 45
2795 06:51:17.867344 [Byte1]: 45
2796 06:51:17.872018
2797 06:51:17.872472 Set Vref, RX VrefLevel [Byte0]: 46
2798 06:51:17.874743 [Byte1]: 46
2799 06:51:17.880343
2800 06:51:17.880761 Set Vref, RX VrefLevel [Byte0]: 47
2801 06:51:17.883300 [Byte1]: 47
2802 06:51:17.888336
2803 06:51:17.888790 Set Vref, RX VrefLevel [Byte0]: 48
2804 06:51:17.891164 [Byte1]: 48
2805 06:51:17.895356
2806 06:51:17.895819 Set Vref, RX VrefLevel [Byte0]: 49
2807 06:51:17.898755 [Byte1]: 49
2808 06:51:17.903680
2809 06:51:17.904102 Set Vref, RX VrefLevel [Byte0]: 50
2810 06:51:17.906789 [Byte1]: 50
2811 06:51:17.911438
2812 06:51:17.911945 Set Vref, RX VrefLevel [Byte0]: 51
2813 06:51:17.914598 [Byte1]: 51
2814 06:51:17.919791
2815 06:51:17.920212 Set Vref, RX VrefLevel [Byte0]: 52
2816 06:51:17.922863 [Byte1]: 52
2817 06:51:17.927130
2818 06:51:17.927663 Set Vref, RX VrefLevel [Byte0]: 53
2819 06:51:17.931019 [Byte1]: 53
2820 06:51:17.934995
2821 06:51:17.935489 Set Vref, RX VrefLevel [Byte0]: 54
2822 06:51:17.938350 [Byte1]: 54
2823 06:51:17.943598
2824 06:51:17.944137 Set Vref, RX VrefLevel [Byte0]: 55
2825 06:51:17.946593 [Byte1]: 55
2826 06:51:17.950896
2827 06:51:17.951315 Set Vref, RX VrefLevel [Byte0]: 56
2828 06:51:17.954116 [Byte1]: 56
2829 06:51:17.958978
2830 06:51:17.959437 Set Vref, RX VrefLevel [Byte0]: 57
2831 06:51:17.962200 [Byte1]: 57
2832 06:51:17.966962
2833 06:51:17.967425 Set Vref, RX VrefLevel [Byte0]: 58
2834 06:51:17.970558 [Byte1]: 58
2835 06:51:17.975016
2836 06:51:17.975598 Set Vref, RX VrefLevel [Byte0]: 59
2837 06:51:17.978149 [Byte1]: 59
2838 06:51:17.982770
2839 06:51:17.983190 Set Vref, RX VrefLevel [Byte0]: 60
2840 06:51:17.985904 [Byte1]: 60
2841 06:51:17.990825
2842 06:51:17.991328 Set Vref, RX VrefLevel [Byte0]: 61
2843 06:51:17.993881 [Byte1]: 61
2844 06:51:17.998469
2845 06:51:17.998892 Set Vref, RX VrefLevel [Byte0]: 62
2846 06:51:18.002335 [Byte1]: 62
2847 06:51:18.006949
2848 06:51:18.007512 Set Vref, RX VrefLevel [Byte0]: 63
2849 06:51:18.009766 [Byte1]: 63
2850 06:51:18.014652
2851 06:51:18.015160 Set Vref, RX VrefLevel [Byte0]: 64
2852 06:51:18.017799 [Byte1]: 64
2853 06:51:18.022671
2854 06:51:18.023095 Set Vref, RX VrefLevel [Byte0]: 65
2855 06:51:18.025946 [Byte1]: 65
2856 06:51:18.030498
2857 06:51:18.031192 Set Vref, RX VrefLevel [Byte0]: 66
2858 06:51:18.033415 [Byte1]: 66
2859 06:51:18.038508
2860 06:51:18.039036 Set Vref, RX VrefLevel [Byte0]: 67
2861 06:51:18.041703 [Byte1]: 67
2862 06:51:18.046507
2863 06:51:18.046990 Final RX Vref Byte 0 = 57 to rank0
2864 06:51:18.049774 Final RX Vref Byte 1 = 44 to rank0
2865 06:51:18.053681 Final RX Vref Byte 0 = 57 to rank1
2866 06:51:18.056102 Final RX Vref Byte 1 = 44 to rank1==
2867 06:51:18.059481 Dram Type= 6, Freq= 0, CH_0, rank 0
2868 06:51:18.063191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 06:51:18.066551 ==
2870 06:51:18.066971 DQS Delay:
2871 06:51:18.067306 DQS0 = 0, DQS1 = 0
2872 06:51:18.069302 DQM Delay:
2873 06:51:18.069723 DQM0 = 117, DQM1 = 102
2874 06:51:18.073148 DQ Delay:
2875 06:51:18.076468 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =112
2876 06:51:18.079709 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =120
2877 06:51:18.082911 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2878 06:51:18.086395 DQ12 =110, DQ13 =106, DQ14 =112, DQ15 =110
2879 06:51:18.086884
2880 06:51:18.087217
2881 06:51:18.093272 [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2882 06:51:18.096279 CH0 RK0: MR19=403, MR18=4FF
2883 06:51:18.102513 CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2884 06:51:18.103127
2885 06:51:18.106177 ----->DramcWriteLeveling(PI) begin...
2886 06:51:18.106708 ==
2887 06:51:18.109388 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 06:51:18.112682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 06:51:18.113107 ==
2890 06:51:18.116134 Write leveling (Byte 0): 31 => 31
2891 06:51:18.119111 Write leveling (Byte 1): 26 => 26
2892 06:51:18.122518 DramcWriteLeveling(PI) end<-----
2893 06:51:18.122938
2894 06:51:18.123273 ==
2895 06:51:18.126112 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 06:51:18.132996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 06:51:18.133523 ==
2898 06:51:18.133864 [Gating] SW mode calibration
2899 06:51:18.142521 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2900 06:51:18.145683 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2901 06:51:18.149291 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
2902 06:51:18.155732 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
2903 06:51:18.158951 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 06:51:18.162638 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 06:51:18.169217 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 06:51:18.172172 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 06:51:18.175549 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2908 06:51:18.182097 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 1)
2909 06:51:18.185582 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
2910 06:51:18.188614 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 06:51:18.195732 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 06:51:18.198528 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 06:51:18.201924 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 06:51:18.208783 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 06:51:18.212339 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2916 06:51:18.215473 1 0 28 | B1->B0 | 2424 4545 | 1 0 | (0 0) (0 0)
2917 06:51:18.222035 1 1 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2918 06:51:18.225172 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 06:51:18.228732 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 06:51:18.235504 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 06:51:18.239012 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 06:51:18.242204 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 06:51:18.249459 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2924 06:51:18.251966 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2925 06:51:18.255339 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2926 06:51:18.262915 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 06:51:18.265345 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 06:51:18.268608 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 06:51:18.275353 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 06:51:18.278675 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 06:51:18.281920 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 06:51:18.288221 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 06:51:18.291644 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 06:51:18.295428 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 06:51:18.301804 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 06:51:18.304889 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 06:51:18.309095 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 06:51:18.311850 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 06:51:18.318122 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2940 06:51:18.321702 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2941 06:51:18.324943 Total UI for P1: 0, mck2ui 16
2942 06:51:18.328800 best dqsien dly found for B0: ( 1, 3, 24)
2943 06:51:18.332549 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 06:51:18.335229 Total UI for P1: 0, mck2ui 16
2945 06:51:18.338558 best dqsien dly found for B1: ( 1, 3, 30)
2946 06:51:18.341532 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2947 06:51:18.345275 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2948 06:51:18.345740
2949 06:51:18.352239 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2950 06:51:18.355203 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2951 06:51:18.358429 [Gating] SW calibration Done
2952 06:51:18.358994 ==
2953 06:51:18.362211 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 06:51:18.364933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 06:51:18.365499 ==
2956 06:51:18.365872 RX Vref Scan: 0
2957 06:51:18.366220
2958 06:51:18.368799 RX Vref 0 -> 0, step: 1
2959 06:51:18.369364
2960 06:51:18.371477 RX Delay -40 -> 252, step: 8
2961 06:51:18.375074 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2962 06:51:18.378460 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2963 06:51:18.384756 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2964 06:51:18.387700 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2965 06:51:18.391168 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2966 06:51:18.394831 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2967 06:51:18.398238 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2968 06:51:18.404851 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2969 06:51:18.407932 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2970 06:51:18.411332 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2971 06:51:18.414698 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2972 06:51:18.417935 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2973 06:51:18.424126 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2974 06:51:18.427594 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2975 06:51:18.430864 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2976 06:51:18.434576 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2977 06:51:18.435137 ==
2978 06:51:18.441966 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 06:51:18.444805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 06:51:18.445232 ==
2981 06:51:18.445565 DQS Delay:
2982 06:51:18.445874 DQS0 = 0, DQS1 = 0
2983 06:51:18.448035 DQM Delay:
2984 06:51:18.448454 DQM0 = 116, DQM1 = 106
2985 06:51:18.451097 DQ Delay:
2986 06:51:18.454598 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2987 06:51:18.457939 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2988 06:51:18.460784 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2989 06:51:18.464707 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2990 06:51:18.465361
2991 06:51:18.465848
2992 06:51:18.466185 ==
2993 06:51:18.467964 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 06:51:18.471254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 06:51:18.471710 ==
2996 06:51:18.472040
2997 06:51:18.474218
2998 06:51:18.474632 TX Vref Scan disable
2999 06:51:18.477752 == TX Byte 0 ==
3000 06:51:18.481325 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3001 06:51:18.484055 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3002 06:51:18.487472 == TX Byte 1 ==
3003 06:51:18.491054 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3004 06:51:18.494089 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3005 06:51:18.494508 ==
3006 06:51:18.497686 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 06:51:18.503905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 06:51:18.504344 ==
3009 06:51:18.515005 TX Vref=22, minBit 2, minWin=25, winSum=408
3010 06:51:18.518399 TX Vref=24, minBit 3, minWin=25, winSum=419
3011 06:51:18.522150 TX Vref=26, minBit 5, minWin=25, winSum=418
3012 06:51:18.524860 TX Vref=28, minBit 0, minWin=26, winSum=423
3013 06:51:18.528755 TX Vref=30, minBit 4, minWin=26, winSum=425
3014 06:51:18.531959 TX Vref=32, minBit 15, minWin=25, winSum=420
3015 06:51:18.539155 [TxChooseVref] Worse bit 4, Min win 26, Win sum 425, Final Vref 30
3016 06:51:18.539770
3017 06:51:18.541971 Final TX Range 1 Vref 30
3018 06:51:18.542428
3019 06:51:18.542789 ==
3020 06:51:18.544801 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 06:51:18.548563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 06:51:18.548981 ==
3023 06:51:18.551347
3024 06:51:18.551786
3025 06:51:18.552118 TX Vref Scan disable
3026 06:51:18.555596 == TX Byte 0 ==
3027 06:51:18.557963 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3028 06:51:18.565057 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3029 06:51:18.565543 == TX Byte 1 ==
3030 06:51:18.568590 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3031 06:51:18.574750 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3032 06:51:18.575200
3033 06:51:18.575618 [DATLAT]
3034 06:51:18.575951 Freq=1200, CH0 RK1
3035 06:51:18.576290
3036 06:51:18.578233 DATLAT Default: 0xd
3037 06:51:18.578770 0, 0xFFFF, sum = 0
3038 06:51:18.581512 1, 0xFFFF, sum = 0
3039 06:51:18.584997 2, 0xFFFF, sum = 0
3040 06:51:18.585531 3, 0xFFFF, sum = 0
3041 06:51:18.588461 4, 0xFFFF, sum = 0
3042 06:51:18.588885 5, 0xFFFF, sum = 0
3043 06:51:18.591473 6, 0xFFFF, sum = 0
3044 06:51:18.591909 7, 0xFFFF, sum = 0
3045 06:51:18.594811 8, 0xFFFF, sum = 0
3046 06:51:18.595412 9, 0xFFFF, sum = 0
3047 06:51:18.598280 10, 0xFFFF, sum = 0
3048 06:51:18.598846 11, 0xFFFF, sum = 0
3049 06:51:18.601666 12, 0x0, sum = 1
3050 06:51:18.602270 13, 0x0, sum = 2
3051 06:51:18.604385 14, 0x0, sum = 3
3052 06:51:18.604954 15, 0x0, sum = 4
3053 06:51:18.608271 best_step = 13
3054 06:51:18.608702
3055 06:51:18.609139 ==
3056 06:51:18.611336 Dram Type= 6, Freq= 0, CH_0, rank 1
3057 06:51:18.614400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 06:51:18.614835 ==
3059 06:51:18.615276 RX Vref Scan: 0
3060 06:51:18.617760
3061 06:51:18.618188 RX Vref 0 -> 0, step: 1
3062 06:51:18.618625
3063 06:51:18.620971 RX Delay -21 -> 252, step: 4
3064 06:51:18.627930 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3065 06:51:18.631330 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3066 06:51:18.634633 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3067 06:51:18.638055 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3068 06:51:18.641164 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3069 06:51:18.645115 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3070 06:51:18.651470 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3071 06:51:18.654525 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3072 06:51:18.657704 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3073 06:51:18.660862 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3074 06:51:18.664507 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3075 06:51:18.670790 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3076 06:51:18.674883 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3077 06:51:18.677635 iDelay=195, Bit 13, Center 108 (43 ~ 174) 132
3078 06:51:18.680919 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3079 06:51:18.685347 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3080 06:51:18.687893 ==
3081 06:51:18.690982 Dram Type= 6, Freq= 0, CH_0, rank 1
3082 06:51:18.694190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 06:51:18.694862 ==
3084 06:51:18.695421 DQS Delay:
3085 06:51:18.697730 DQS0 = 0, DQS1 = 0
3086 06:51:18.698267 DQM Delay:
3087 06:51:18.700899 DQM0 = 116, DQM1 = 104
3088 06:51:18.701439 DQ Delay:
3089 06:51:18.703857 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =114
3090 06:51:18.707076 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =120
3091 06:51:18.710682 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3092 06:51:18.714091 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =112
3093 06:51:18.714513
3094 06:51:18.714847
3095 06:51:18.723953 [DQSOSCAuto] RK1, (LSB)MR18= 0x1ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3096 06:51:18.726941 CH0 RK1: MR19=403, MR18=1FF
3097 06:51:18.730512 CH0_RK1: MR19=0x403, MR18=0x1FF, DQSOSC=409, MR23=63, INC=39, DEC=26
3098 06:51:18.733937 [RxdqsGatingPostProcess] freq 1200
3099 06:51:18.740291 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3100 06:51:18.743738 best DQS0 dly(2T, 0.5T) = (0, 11)
3101 06:51:18.747145 best DQS1 dly(2T, 0.5T) = (0, 12)
3102 06:51:18.750496 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3103 06:51:18.753732 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3104 06:51:18.757241 best DQS0 dly(2T, 0.5T) = (0, 11)
3105 06:51:18.760509 best DQS1 dly(2T, 0.5T) = (0, 11)
3106 06:51:18.763535 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3107 06:51:18.766794 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3108 06:51:18.767215 Pre-setting of DQS Precalculation
3109 06:51:18.773350 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3110 06:51:18.773923 ==
3111 06:51:18.776848 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 06:51:18.780219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 06:51:18.780640 ==
3114 06:51:18.787123 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3115 06:51:18.793276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3116 06:51:18.801233 [CA 0] Center 38 (8~68) winsize 61
3117 06:51:18.804178 [CA 1] Center 37 (7~68) winsize 62
3118 06:51:18.807304 [CA 2] Center 35 (5~65) winsize 61
3119 06:51:18.810622 [CA 3] Center 34 (4~64) winsize 61
3120 06:51:18.814030 [CA 4] Center 34 (4~65) winsize 62
3121 06:51:18.817655 [CA 5] Center 33 (4~63) winsize 60
3122 06:51:18.818088
3123 06:51:18.820633 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3124 06:51:18.821066
3125 06:51:18.824272 [CATrainingPosCal] consider 1 rank data
3126 06:51:18.827477 u2DelayCellTimex100 = 270/100 ps
3127 06:51:18.831012 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3128 06:51:18.837185 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3129 06:51:18.840802 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3130 06:51:18.844384 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3131 06:51:18.847456 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3132 06:51:18.850443 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3133 06:51:18.850862
3134 06:51:18.853952 CA PerBit enable=1, Macro0, CA PI delay=33
3135 06:51:18.854370
3136 06:51:18.857384 [CBTSetCACLKResult] CA Dly = 33
3137 06:51:18.857802 CS Dly: 5 (0~36)
3138 06:51:18.860766 ==
3139 06:51:18.863749 Dram Type= 6, Freq= 0, CH_1, rank 1
3140 06:51:18.867437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 06:51:18.867963 ==
3142 06:51:18.870751 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3143 06:51:18.877148 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3144 06:51:18.886530 [CA 0] Center 37 (7~68) winsize 62
3145 06:51:18.889965 [CA 1] Center 38 (8~68) winsize 61
3146 06:51:18.893226 [CA 2] Center 35 (5~65) winsize 61
3147 06:51:18.896546 [CA 3] Center 33 (3~64) winsize 62
3148 06:51:18.900270 [CA 4] Center 34 (4~64) winsize 61
3149 06:51:18.903232 [CA 5] Center 33 (3~64) winsize 62
3150 06:51:18.903842
3151 06:51:18.906371 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3152 06:51:18.906950
3153 06:51:18.909819 [CATrainingPosCal] consider 2 rank data
3154 06:51:18.913809 u2DelayCellTimex100 = 270/100 ps
3155 06:51:18.917015 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3156 06:51:18.923002 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3157 06:51:18.926438 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3158 06:51:18.929734 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 06:51:18.933365 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 06:51:18.936193 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3161 06:51:18.936615
3162 06:51:18.940165 CA PerBit enable=1, Macro0, CA PI delay=33
3163 06:51:18.940600
3164 06:51:18.942820 [CBTSetCACLKResult] CA Dly = 33
3165 06:51:18.943239 CS Dly: 6 (0~39)
3166 06:51:18.946361
3167 06:51:18.949530 ----->DramcWriteLeveling(PI) begin...
3168 06:51:18.949959 ==
3169 06:51:18.953172 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 06:51:18.956445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 06:51:18.956869 ==
3172 06:51:18.959719 Write leveling (Byte 0): 27 => 27
3173 06:51:18.962976 Write leveling (Byte 1): 27 => 27
3174 06:51:18.965864 DramcWriteLeveling(PI) end<-----
3175 06:51:18.966386
3176 06:51:18.966720 ==
3177 06:51:18.969606 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 06:51:18.972663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 06:51:18.973178 ==
3180 06:51:18.976269 [Gating] SW mode calibration
3181 06:51:18.982535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3182 06:51:18.989766 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3183 06:51:18.992703 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3184 06:51:18.996099 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 06:51:19.002859 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 06:51:19.005797 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 06:51:19.008939 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 06:51:19.015874 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3189 06:51:19.019080 0 15 24 | B1->B0 | 3434 3131 | 0 0 | (0 1) (1 0)
3190 06:51:19.022496 0 15 28 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (1 0)
3191 06:51:19.029090 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 06:51:19.032161 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 06:51:19.036043 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 06:51:19.039058 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 06:51:19.045531 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 06:51:19.049095 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 06:51:19.052155 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
3198 06:51:19.058755 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3199 06:51:19.061792 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 06:51:19.065291 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 06:51:19.072096 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 06:51:19.075354 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 06:51:19.078477 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 06:51:19.085294 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 06:51:19.088513 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3206 06:51:19.091652 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3207 06:51:19.098271 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3208 06:51:19.101407 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 06:51:19.105109 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 06:51:19.111388 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 06:51:19.115087 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 06:51:19.117846 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 06:51:19.124719 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 06:51:19.127665 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 06:51:19.131371 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 06:51:19.138863 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 06:51:19.141922 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 06:51:19.145480 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 06:51:19.151829 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 06:51:19.155059 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 06:51:19.158275 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3222 06:51:19.165000 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3223 06:51:19.167963 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 06:51:19.171505 Total UI for P1: 0, mck2ui 16
3225 06:51:19.174642 best dqsien dly found for B0: ( 1, 3, 26)
3226 06:51:19.178215 Total UI for P1: 0, mck2ui 16
3227 06:51:19.181844 best dqsien dly found for B1: ( 1, 3, 26)
3228 06:51:19.185006 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3229 06:51:19.188281 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3230 06:51:19.188763
3231 06:51:19.191416 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3232 06:51:19.194969 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3233 06:51:19.198290 [Gating] SW calibration Done
3234 06:51:19.198806 ==
3235 06:51:19.201611 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 06:51:19.204887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 06:51:19.208452 ==
3238 06:51:19.208920 RX Vref Scan: 0
3239 06:51:19.209292
3240 06:51:19.211435 RX Vref 0 -> 0, step: 1
3241 06:51:19.212030
3242 06:51:19.212636 RX Delay -40 -> 252, step: 8
3243 06:51:19.218383 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3244 06:51:19.221435 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3245 06:51:19.225362 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3246 06:51:19.227959 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3247 06:51:19.231494 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3248 06:51:19.238430 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3249 06:51:19.241461 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3250 06:51:19.244984 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3251 06:51:19.248853 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3252 06:51:19.251162 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3253 06:51:19.258475 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3254 06:51:19.261134 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3255 06:51:19.264691 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3256 06:51:19.267896 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3257 06:51:19.274295 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3258 06:51:19.277966 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3259 06:51:19.278466 ==
3260 06:51:19.280844 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 06:51:19.284711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 06:51:19.285208 ==
3263 06:51:19.287918 DQS Delay:
3264 06:51:19.288469 DQS0 = 0, DQS1 = 0
3265 06:51:19.288811 DQM Delay:
3266 06:51:19.291230 DQM0 = 115, DQM1 = 112
3267 06:51:19.291863 DQ Delay:
3268 06:51:19.294710 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3269 06:51:19.298314 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3270 06:51:19.301306 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3271 06:51:19.307902 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3272 06:51:19.308631
3273 06:51:19.309148
3274 06:51:19.309482 ==
3275 06:51:19.310869 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 06:51:19.314711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 06:51:19.315136 ==
3278 06:51:19.315536
3279 06:51:19.315862
3280 06:51:19.317746 TX Vref Scan disable
3281 06:51:19.318167 == TX Byte 0 ==
3282 06:51:19.324229 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3283 06:51:19.327425 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3284 06:51:19.327859 == TX Byte 1 ==
3285 06:51:19.334413 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3286 06:51:19.337870 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3287 06:51:19.338255 ==
3288 06:51:19.341146 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 06:51:19.344201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 06:51:19.344627 ==
3291 06:51:19.356298 TX Vref=22, minBit 9, minWin=23, winSum=406
3292 06:51:19.359782 TX Vref=24, minBit 9, minWin=24, winSum=412
3293 06:51:19.362970 TX Vref=26, minBit 3, minWin=25, winSum=418
3294 06:51:19.366317 TX Vref=28, minBit 8, minWin=25, winSum=424
3295 06:51:19.370276 TX Vref=30, minBit 9, minWin=25, winSum=425
3296 06:51:19.376276 TX Vref=32, minBit 9, minWin=25, winSum=423
3297 06:51:19.379273 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 30
3298 06:51:19.379762
3299 06:51:19.382748 Final TX Range 1 Vref 30
3300 06:51:19.383170
3301 06:51:19.383548 ==
3302 06:51:19.386213 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 06:51:19.389584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 06:51:19.390049 ==
3305 06:51:19.392866
3306 06:51:19.393282
3307 06:51:19.393609 TX Vref Scan disable
3308 06:51:19.396017 == TX Byte 0 ==
3309 06:51:19.399522 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3310 06:51:19.406024 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3311 06:51:19.406595 == TX Byte 1 ==
3312 06:51:19.409206 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3313 06:51:19.416017 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3314 06:51:19.416459
3315 06:51:19.416807 [DATLAT]
3316 06:51:19.417135 Freq=1200, CH1 RK0
3317 06:51:19.417467
3318 06:51:19.419631 DATLAT Default: 0xd
3319 06:51:19.420075 0, 0xFFFF, sum = 0
3320 06:51:19.422321 1, 0xFFFF, sum = 0
3321 06:51:19.422752 2, 0xFFFF, sum = 0
3322 06:51:19.426270 3, 0xFFFF, sum = 0
3323 06:51:19.429113 4, 0xFFFF, sum = 0
3324 06:51:19.429566 5, 0xFFFF, sum = 0
3325 06:51:19.432419 6, 0xFFFF, sum = 0
3326 06:51:19.432862 7, 0xFFFF, sum = 0
3327 06:51:19.436416 8, 0xFFFF, sum = 0
3328 06:51:19.436852 9, 0xFFFF, sum = 0
3329 06:51:19.439327 10, 0xFFFF, sum = 0
3330 06:51:19.439793 11, 0xFFFF, sum = 0
3331 06:51:19.442467 12, 0x0, sum = 1
3332 06:51:19.442926 13, 0x0, sum = 2
3333 06:51:19.446052 14, 0x0, sum = 3
3334 06:51:19.446572 15, 0x0, sum = 4
3335 06:51:19.449547 best_step = 13
3336 06:51:19.449968
3337 06:51:19.450301 ==
3338 06:51:19.453085 Dram Type= 6, Freq= 0, CH_1, rank 0
3339 06:51:19.455749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3340 06:51:19.456178 ==
3341 06:51:19.456515 RX Vref Scan: 1
3342 06:51:19.456833
3343 06:51:19.459208 Set Vref Range= 32 -> 127
3344 06:51:19.459675
3345 06:51:19.462915 RX Vref 32 -> 127, step: 1
3346 06:51:19.463335
3347 06:51:19.466192 RX Delay -13 -> 252, step: 4
3348 06:51:19.466704
3349 06:51:19.469191 Set Vref, RX VrefLevel [Byte0]: 32
3350 06:51:19.472498 [Byte1]: 32
3351 06:51:19.473011
3352 06:51:19.475825 Set Vref, RX VrefLevel [Byte0]: 33
3353 06:51:19.479506 [Byte1]: 33
3354 06:51:19.482630
3355 06:51:19.482997 Set Vref, RX VrefLevel [Byte0]: 34
3356 06:51:19.485729 [Byte1]: 34
3357 06:51:19.490417
3358 06:51:19.490833 Set Vref, RX VrefLevel [Byte0]: 35
3359 06:51:19.494000 [Byte1]: 35
3360 06:51:19.498015
3361 06:51:19.498426 Set Vref, RX VrefLevel [Byte0]: 36
3362 06:51:19.501393 [Byte1]: 36
3363 06:51:19.505793
3364 06:51:19.506271 Set Vref, RX VrefLevel [Byte0]: 37
3365 06:51:19.509239 [Byte1]: 37
3366 06:51:19.513966
3367 06:51:19.514380 Set Vref, RX VrefLevel [Byte0]: 38
3368 06:51:19.517728 [Byte1]: 38
3369 06:51:19.521579
3370 06:51:19.521659 Set Vref, RX VrefLevel [Byte0]: 39
3371 06:51:19.525023 [Byte1]: 39
3372 06:51:19.529539
3373 06:51:19.529618 Set Vref, RX VrefLevel [Byte0]: 40
3374 06:51:19.532872 [Byte1]: 40
3375 06:51:19.537426
3376 06:51:19.537863 Set Vref, RX VrefLevel [Byte0]: 41
3377 06:51:19.541116 [Byte1]: 41
3378 06:51:19.544949
3379 06:51:19.545029 Set Vref, RX VrefLevel [Byte0]: 42
3380 06:51:19.548773 [Byte1]: 42
3381 06:51:19.552816
3382 06:51:19.552891 Set Vref, RX VrefLevel [Byte0]: 43
3383 06:51:19.556910 [Byte1]: 43
3384 06:51:19.561066
3385 06:51:19.561142 Set Vref, RX VrefLevel [Byte0]: 44
3386 06:51:19.564082 [Byte1]: 44
3387 06:51:19.568786
3388 06:51:19.568884 Set Vref, RX VrefLevel [Byte0]: 45
3389 06:51:19.572023 [Byte1]: 45
3390 06:51:19.577057
3391 06:51:19.577141 Set Vref, RX VrefLevel [Byte0]: 46
3392 06:51:19.580170 [Byte1]: 46
3393 06:51:19.585013
3394 06:51:19.585091 Set Vref, RX VrefLevel [Byte0]: 47
3395 06:51:19.588071 [Byte1]: 47
3396 06:51:19.592830
3397 06:51:19.592910 Set Vref, RX VrefLevel [Byte0]: 48
3398 06:51:19.595759 [Byte1]: 48
3399 06:51:19.600764
3400 06:51:19.600844 Set Vref, RX VrefLevel [Byte0]: 49
3401 06:51:19.603472 [Byte1]: 49
3402 06:51:19.608397
3403 06:51:19.608483 Set Vref, RX VrefLevel [Byte0]: 50
3404 06:51:19.611520 [Byte1]: 50
3405 06:51:19.616340
3406 06:51:19.616425 Set Vref, RX VrefLevel [Byte0]: 51
3407 06:51:19.619236 [Byte1]: 51
3408 06:51:19.624334
3409 06:51:19.624426 Set Vref, RX VrefLevel [Byte0]: 52
3410 06:51:19.627164 [Byte1]: 52
3411 06:51:19.631865
3412 06:51:19.631973 Set Vref, RX VrefLevel [Byte0]: 53
3413 06:51:19.635072 [Byte1]: 53
3414 06:51:19.639531
3415 06:51:19.639650 Set Vref, RX VrefLevel [Byte0]: 54
3416 06:51:19.643191 [Byte1]: 54
3417 06:51:19.647443
3418 06:51:19.647594 Set Vref, RX VrefLevel [Byte0]: 55
3419 06:51:19.651874 [Byte1]: 55
3420 06:51:19.655717
3421 06:51:19.655998 Set Vref, RX VrefLevel [Byte0]: 56
3422 06:51:19.658901 [Byte1]: 56
3423 06:51:19.663407
3424 06:51:19.663731 Set Vref, RX VrefLevel [Byte0]: 57
3425 06:51:19.666843 [Byte1]: 57
3426 06:51:19.671764
3427 06:51:19.672230 Set Vref, RX VrefLevel [Byte0]: 58
3428 06:51:19.675252 [Byte1]: 58
3429 06:51:19.679831
3430 06:51:19.680395 Set Vref, RX VrefLevel [Byte0]: 59
3431 06:51:19.682912 [Byte1]: 59
3432 06:51:19.687679
3433 06:51:19.688132 Set Vref, RX VrefLevel [Byte0]: 60
3434 06:51:19.691465 [Byte1]: 60
3435 06:51:19.695710
3436 06:51:19.696249 Set Vref, RX VrefLevel [Byte0]: 61
3437 06:51:19.698941 [Byte1]: 61
3438 06:51:19.703545
3439 06:51:19.704099 Set Vref, RX VrefLevel [Byte0]: 62
3440 06:51:19.706327 [Byte1]: 62
3441 06:51:19.710923
3442 06:51:19.711420 Set Vref, RX VrefLevel [Byte0]: 63
3443 06:51:19.715097 [Byte1]: 63
3444 06:51:19.719545
3445 06:51:19.720166 Set Vref, RX VrefLevel [Byte0]: 64
3446 06:51:19.722315 [Byte1]: 64
3447 06:51:19.727104
3448 06:51:19.727680 Set Vref, RX VrefLevel [Byte0]: 65
3449 06:51:19.730417 [Byte1]: 65
3450 06:51:19.734705
3451 06:51:19.735158 Final RX Vref Byte 0 = 50 to rank0
3452 06:51:19.738175 Final RX Vref Byte 1 = 53 to rank0
3453 06:51:19.741245 Final RX Vref Byte 0 = 50 to rank1
3454 06:51:19.744535 Final RX Vref Byte 1 = 53 to rank1==
3455 06:51:19.748253 Dram Type= 6, Freq= 0, CH_1, rank 0
3456 06:51:19.754881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 06:51:19.755476 ==
3458 06:51:19.755847 DQS Delay:
3459 06:51:19.758037 DQS0 = 0, DQS1 = 0
3460 06:51:19.758587 DQM Delay:
3461 06:51:19.758986 DQM0 = 115, DQM1 = 113
3462 06:51:19.761520 DQ Delay:
3463 06:51:19.764687 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3464 06:51:19.767847 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3465 06:51:19.771447 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3466 06:51:19.774501 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =120
3467 06:51:19.775051
3468 06:51:19.775466
3469 06:51:19.784063 [DQSOSCAuto] RK0, (LSB)MR18= 0xf704, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3470 06:51:19.784770 CH1 RK0: MR19=304, MR18=F704
3471 06:51:19.790707 CH1_RK0: MR19=0x304, MR18=0xF704, DQSOSC=408, MR23=63, INC=39, DEC=26
3472 06:51:19.791331
3473 06:51:19.794059 ----->DramcWriteLeveling(PI) begin...
3474 06:51:19.794618 ==
3475 06:51:19.797812 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 06:51:19.803949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 06:51:19.804373 ==
3478 06:51:19.807191 Write leveling (Byte 0): 23 => 23
3479 06:51:19.810269 Write leveling (Byte 1): 29 => 29
3480 06:51:19.810380 DramcWriteLeveling(PI) end<-----
3481 06:51:19.810491
3482 06:51:19.813487 ==
3483 06:51:19.816860 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 06:51:19.820189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 06:51:19.820270 ==
3486 06:51:19.823708 [Gating] SW mode calibration
3487 06:51:19.830529 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3488 06:51:19.833384 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3489 06:51:19.839953 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 06:51:19.843590 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 06:51:19.846477 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 06:51:19.853188 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 06:51:19.856782 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 06:51:19.860441 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3495 06:51:19.866721 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
3496 06:51:19.870193 0 15 28 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
3497 06:51:19.873965 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 06:51:19.880099 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 06:51:19.883800 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 06:51:19.887197 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 06:51:19.893280 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 06:51:19.896849 1 0 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
3503 06:51:19.899984 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3504 06:51:19.906522 1 0 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
3505 06:51:19.909909 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 06:51:19.913531 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 06:51:19.920216 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 06:51:19.923711 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 06:51:19.926835 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 06:51:19.933470 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 06:51:19.936765 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3512 06:51:19.939708 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3513 06:51:19.946465 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 06:51:19.949822 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 06:51:19.953105 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 06:51:19.959929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 06:51:19.962621 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 06:51:19.966067 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 06:51:19.972415 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 06:51:19.975666 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 06:51:19.978911 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 06:51:19.986067 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 06:51:19.989046 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 06:51:19.991896 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 06:51:19.999049 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 06:51:20.002075 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3527 06:51:20.005323 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3528 06:51:20.008769 Total UI for P1: 0, mck2ui 16
3529 06:51:20.011921 best dqsien dly found for B0: ( 1, 3, 20)
3530 06:51:20.018391 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3531 06:51:20.021780 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 06:51:20.025194 Total UI for P1: 0, mck2ui 16
3533 06:51:20.028285 best dqsien dly found for B1: ( 1, 3, 26)
3534 06:51:20.031313 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3535 06:51:20.034639 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3536 06:51:20.034717
3537 06:51:20.038011 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3538 06:51:20.041451 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3539 06:51:20.044815 [Gating] SW calibration Done
3540 06:51:20.044887 ==
3541 06:51:20.048361 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 06:51:20.054638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 06:51:20.054716 ==
3544 06:51:20.054777 RX Vref Scan: 0
3545 06:51:20.054835
3546 06:51:20.057718 RX Vref 0 -> 0, step: 1
3547 06:51:20.057791
3548 06:51:20.060856 RX Delay -40 -> 252, step: 8
3549 06:51:20.064163 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3550 06:51:20.067572 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3551 06:51:20.070821 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3552 06:51:20.077928 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3553 06:51:20.080926 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3554 06:51:20.084349 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3555 06:51:20.087731 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3556 06:51:20.091069 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3557 06:51:20.094356 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3558 06:51:20.100458 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3559 06:51:20.103972 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3560 06:51:20.107519 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3561 06:51:20.110461 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3562 06:51:20.117503 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3563 06:51:20.120450 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3564 06:51:20.123794 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3565 06:51:20.123866 ==
3566 06:51:20.127013 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 06:51:20.130336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 06:51:20.130406 ==
3569 06:51:20.133617 DQS Delay:
3570 06:51:20.133699 DQS0 = 0, DQS1 = 0
3571 06:51:20.136755 DQM Delay:
3572 06:51:20.136836 DQM0 = 115, DQM1 = 111
3573 06:51:20.140305 DQ Delay:
3574 06:51:20.143506 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3575 06:51:20.146558 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =111
3576 06:51:20.149850 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3577 06:51:20.153193 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3578 06:51:20.153265
3579 06:51:20.153335
3580 06:51:20.153392 ==
3581 06:51:20.156368 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 06:51:20.159660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 06:51:20.159733 ==
3584 06:51:20.159800
3585 06:51:20.159859
3586 06:51:20.163215 TX Vref Scan disable
3587 06:51:20.166158 == TX Byte 0 ==
3588 06:51:20.169951 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3589 06:51:20.172764 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3590 06:51:20.176624 == TX Byte 1 ==
3591 06:51:20.179460 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3592 06:51:20.182810 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3593 06:51:20.182884 ==
3594 06:51:20.186021 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 06:51:20.192964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 06:51:20.193041 ==
3597 06:51:20.203463 TX Vref=22, minBit 2, minWin=25, winSum=420
3598 06:51:20.206757 TX Vref=24, minBit 9, minWin=25, winSum=424
3599 06:51:20.210031 TX Vref=26, minBit 2, minWin=25, winSum=421
3600 06:51:20.213244 TX Vref=28, minBit 3, minWin=26, winSum=428
3601 06:51:20.216617 TX Vref=30, minBit 3, minWin=26, winSum=432
3602 06:51:20.223192 TX Vref=32, minBit 2, minWin=26, winSum=430
3603 06:51:20.226735 [TxChooseVref] Worse bit 3, Min win 26, Win sum 432, Final Vref 30
3604 06:51:20.226810
3605 06:51:20.229729 Final TX Range 1 Vref 30
3606 06:51:20.229809
3607 06:51:20.229870 ==
3608 06:51:20.233140 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 06:51:20.239746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 06:51:20.239833 ==
3611 06:51:20.239897
3612 06:51:20.239962
3613 06:51:20.240022 TX Vref Scan disable
3614 06:51:20.243543 == TX Byte 0 ==
3615 06:51:20.247037 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3616 06:51:20.253483 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3617 06:51:20.253559 == TX Byte 1 ==
3618 06:51:20.256306 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3619 06:51:20.263286 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3620 06:51:20.263392
3621 06:51:20.263464 [DATLAT]
3622 06:51:20.263524 Freq=1200, CH1 RK1
3623 06:51:20.263581
3624 06:51:20.266216 DATLAT Default: 0xd
3625 06:51:20.269647 0, 0xFFFF, sum = 0
3626 06:51:20.269786 1, 0xFFFF, sum = 0
3627 06:51:20.273342 2, 0xFFFF, sum = 0
3628 06:51:20.273425 3, 0xFFFF, sum = 0
3629 06:51:20.276258 4, 0xFFFF, sum = 0
3630 06:51:20.276346 5, 0xFFFF, sum = 0
3631 06:51:20.279435 6, 0xFFFF, sum = 0
3632 06:51:20.279509 7, 0xFFFF, sum = 0
3633 06:51:20.283457 8, 0xFFFF, sum = 0
3634 06:51:20.283551 9, 0xFFFF, sum = 0
3635 06:51:20.286125 10, 0xFFFF, sum = 0
3636 06:51:20.286209 11, 0xFFFF, sum = 0
3637 06:51:20.289662 12, 0x0, sum = 1
3638 06:51:20.289745 13, 0x0, sum = 2
3639 06:51:20.293016 14, 0x0, sum = 3
3640 06:51:20.293099 15, 0x0, sum = 4
3641 06:51:20.296512 best_step = 13
3642 06:51:20.296594
3643 06:51:20.296658 ==
3644 06:51:20.299645 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 06:51:20.302991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 06:51:20.303074 ==
3647 06:51:20.305996 RX Vref Scan: 0
3648 06:51:20.306077
3649 06:51:20.306141 RX Vref 0 -> 0, step: 1
3650 06:51:20.306202
3651 06:51:20.309176 RX Delay -13 -> 252, step: 4
3652 06:51:20.316180 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3653 06:51:20.319356 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3654 06:51:20.322633 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3655 06:51:20.325797 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3656 06:51:20.329179 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3657 06:51:20.335247 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3658 06:51:20.339056 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3659 06:51:20.342515 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3660 06:51:20.345242 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3661 06:51:20.351901 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3662 06:51:20.354996 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3663 06:51:20.358288 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3664 06:51:20.361713 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3665 06:51:20.364790 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3666 06:51:20.371511 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3667 06:51:20.375027 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3668 06:51:20.375115 ==
3669 06:51:20.377839 Dram Type= 6, Freq= 0, CH_1, rank 1
3670 06:51:20.381556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3671 06:51:20.381639 ==
3672 06:51:20.385084 DQS Delay:
3673 06:51:20.385160 DQS0 = 0, DQS1 = 0
3674 06:51:20.387759 DQM Delay:
3675 06:51:20.387831 DQM0 = 114, DQM1 = 112
3676 06:51:20.387892 DQ Delay:
3677 06:51:20.394312 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3678 06:51:20.397637 DQ4 =112, DQ5 =122, DQ6 =122, DQ7 =112
3679 06:51:20.401096 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3680 06:51:20.404449 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =122
3681 06:51:20.404528
3682 06:51:20.404592
3683 06:51:20.410720 [DQSOSCAuto] RK1, (LSB)MR18= 0xf809, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3684 06:51:20.414493 CH1 RK1: MR19=304, MR18=F809
3685 06:51:20.420818 CH1_RK1: MR19=0x304, MR18=0xF809, DQSOSC=406, MR23=63, INC=39, DEC=26
3686 06:51:20.424442 [RxdqsGatingPostProcess] freq 1200
3687 06:51:20.430777 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3688 06:51:20.433940 best DQS0 dly(2T, 0.5T) = (0, 11)
3689 06:51:20.437318 best DQS1 dly(2T, 0.5T) = (0, 11)
3690 06:51:20.437406 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3691 06:51:20.440721 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3692 06:51:20.444185 best DQS0 dly(2T, 0.5T) = (0, 11)
3693 06:51:20.447551 best DQS1 dly(2T, 0.5T) = (0, 11)
3694 06:51:20.450504 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3695 06:51:20.453933 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3696 06:51:20.457093 Pre-setting of DQS Precalculation
3697 06:51:20.463544 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3698 06:51:20.470362 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3699 06:51:20.476945 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3700 06:51:20.477022
3701 06:51:20.477084
3702 06:51:20.480191 [Calibration Summary] 2400 Mbps
3703 06:51:20.480261 CH 0, Rank 0
3704 06:51:20.483522 SW Impedance : PASS
3705 06:51:20.486815 DUTY Scan : NO K
3706 06:51:20.486889 ZQ Calibration : PASS
3707 06:51:20.490182 Jitter Meter : NO K
3708 06:51:20.493194 CBT Training : PASS
3709 06:51:20.493268 Write leveling : PASS
3710 06:51:20.496906 RX DQS gating : PASS
3711 06:51:20.500182 RX DQ/DQS(RDDQC) : PASS
3712 06:51:20.500254 TX DQ/DQS : PASS
3713 06:51:20.503285 RX DATLAT : PASS
3714 06:51:20.506345 RX DQ/DQS(Engine): PASS
3715 06:51:20.506418 TX OE : NO K
3716 06:51:20.509923 All Pass.
3717 06:51:20.509992
3718 06:51:20.510052 CH 0, Rank 1
3719 06:51:20.513219 SW Impedance : PASS
3720 06:51:20.513297 DUTY Scan : NO K
3721 06:51:20.516775 ZQ Calibration : PASS
3722 06:51:20.519278 Jitter Meter : NO K
3723 06:51:20.519349 CBT Training : PASS
3724 06:51:20.522897 Write leveling : PASS
3725 06:51:20.526116 RX DQS gating : PASS
3726 06:51:20.526186 RX DQ/DQS(RDDQC) : PASS
3727 06:51:20.529688 TX DQ/DQS : PASS
3728 06:51:20.532682 RX DATLAT : PASS
3729 06:51:20.532751 RX DQ/DQS(Engine): PASS
3730 06:51:20.535838 TX OE : NO K
3731 06:51:20.535909 All Pass.
3732 06:51:20.535968
3733 06:51:20.539264 CH 1, Rank 0
3734 06:51:20.539333 SW Impedance : PASS
3735 06:51:20.543372 DUTY Scan : NO K
3736 06:51:20.546220 ZQ Calibration : PASS
3737 06:51:20.546289 Jitter Meter : NO K
3738 06:51:20.549121 CBT Training : PASS
3739 06:51:20.549192 Write leveling : PASS
3740 06:51:20.552567 RX DQS gating : PASS
3741 06:51:20.555799 RX DQ/DQS(RDDQC) : PASS
3742 06:51:20.555869 TX DQ/DQS : PASS
3743 06:51:20.558902 RX DATLAT : PASS
3744 06:51:20.562799 RX DQ/DQS(Engine): PASS
3745 06:51:20.562869 TX OE : NO K
3746 06:51:20.565655 All Pass.
3747 06:51:20.565729
3748 06:51:20.565789 CH 1, Rank 1
3749 06:51:20.568986 SW Impedance : PASS
3750 06:51:20.569056 DUTY Scan : NO K
3751 06:51:20.572315 ZQ Calibration : PASS
3752 06:51:20.575970 Jitter Meter : NO K
3753 06:51:20.576040 CBT Training : PASS
3754 06:51:20.578647 Write leveling : PASS
3755 06:51:20.582217 RX DQS gating : PASS
3756 06:51:20.582288 RX DQ/DQS(RDDQC) : PASS
3757 06:51:20.585539 TX DQ/DQS : PASS
3758 06:51:20.588797 RX DATLAT : PASS
3759 06:51:20.588879 RX DQ/DQS(Engine): PASS
3760 06:51:20.591990 TX OE : NO K
3761 06:51:20.592066 All Pass.
3762 06:51:20.592129
3763 06:51:20.595517 DramC Write-DBI off
3764 06:51:20.598884 PER_BANK_REFRESH: Hybrid Mode
3765 06:51:20.598985 TX_TRACKING: ON
3766 06:51:20.608502 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3767 06:51:20.612144 [FAST_K] Save calibration result to emmc
3768 06:51:20.615383 dramc_set_vcore_voltage set vcore to 650000
3769 06:51:20.618401 Read voltage for 600, 5
3770 06:51:20.618497 Vio18 = 0
3771 06:51:20.618580 Vcore = 650000
3772 06:51:20.621643 Vdram = 0
3773 06:51:20.621744 Vddq = 0
3774 06:51:20.621833 Vmddr = 0
3775 06:51:20.628666 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3776 06:51:20.631918 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3777 06:51:20.634707 MEM_TYPE=3, freq_sel=19
3778 06:51:20.638432 sv_algorithm_assistance_LP4_1600
3779 06:51:20.641853 ============ PULL DRAM RESETB DOWN ============
3780 06:51:20.648290 ========== PULL DRAM RESETB DOWN end =========
3781 06:51:20.651351 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3782 06:51:20.654557 ===================================
3783 06:51:20.657946 LPDDR4 DRAM CONFIGURATION
3784 06:51:20.661175 ===================================
3785 06:51:20.661248 EX_ROW_EN[0] = 0x0
3786 06:51:20.664732 EX_ROW_EN[1] = 0x0
3787 06:51:20.664805 LP4Y_EN = 0x0
3788 06:51:20.668134 WORK_FSP = 0x0
3789 06:51:20.668205 WL = 0x2
3790 06:51:20.671186 RL = 0x2
3791 06:51:20.674329 BL = 0x2
3792 06:51:20.674400 RPST = 0x0
3793 06:51:20.677703 RD_PRE = 0x0
3794 06:51:20.677774 WR_PRE = 0x1
3795 06:51:20.680693 WR_PST = 0x0
3796 06:51:20.680800 DBI_WR = 0x0
3797 06:51:20.684210 DBI_RD = 0x0
3798 06:51:20.684320 OTF = 0x1
3799 06:51:20.687611 ===================================
3800 06:51:20.690898 ===================================
3801 06:51:20.694261 ANA top config
3802 06:51:20.697577 ===================================
3803 06:51:20.697653 DLL_ASYNC_EN = 0
3804 06:51:20.700486 ALL_SLAVE_EN = 1
3805 06:51:20.703797 NEW_RANK_MODE = 1
3806 06:51:20.707318 DLL_IDLE_MODE = 1
3807 06:51:20.710427 LP45_APHY_COMB_EN = 1
3808 06:51:20.710500 TX_ODT_DIS = 1
3809 06:51:20.713736 NEW_8X_MODE = 1
3810 06:51:20.717292 ===================================
3811 06:51:20.720556 ===================================
3812 06:51:20.724084 data_rate = 1200
3813 06:51:20.727287 CKR = 1
3814 06:51:20.730239 DQ_P2S_RATIO = 8
3815 06:51:20.733599 ===================================
3816 06:51:20.733674 CA_P2S_RATIO = 8
3817 06:51:20.737850 DQ_CA_OPEN = 0
3818 06:51:20.740340 DQ_SEMI_OPEN = 0
3819 06:51:20.743782 CA_SEMI_OPEN = 0
3820 06:51:20.746800 CA_FULL_RATE = 0
3821 06:51:20.750300 DQ_CKDIV4_EN = 1
3822 06:51:20.750374 CA_CKDIV4_EN = 1
3823 06:51:20.753456 CA_PREDIV_EN = 0
3824 06:51:20.756924 PH8_DLY = 0
3825 06:51:20.760122 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3826 06:51:20.763580 DQ_AAMCK_DIV = 4
3827 06:51:20.766694 CA_AAMCK_DIV = 4
3828 06:51:20.769954 CA_ADMCK_DIV = 4
3829 06:51:20.770027 DQ_TRACK_CA_EN = 0
3830 06:51:20.773311 CA_PICK = 600
3831 06:51:20.776830 CA_MCKIO = 600
3832 06:51:20.780528 MCKIO_SEMI = 0
3833 06:51:20.783297 PLL_FREQ = 2288
3834 06:51:20.786658 DQ_UI_PI_RATIO = 32
3835 06:51:20.789612 CA_UI_PI_RATIO = 0
3836 06:51:20.793304 ===================================
3837 06:51:20.796293 ===================================
3838 06:51:20.796378 memory_type:LPDDR4
3839 06:51:20.799519 GP_NUM : 10
3840 06:51:20.803243 SRAM_EN : 1
3841 06:51:20.803349 MD32_EN : 0
3842 06:51:20.806141 ===================================
3843 06:51:20.809602 [ANA_INIT] >>>>>>>>>>>>>>
3844 06:51:20.812745 <<<<<< [CONFIGURE PHASE]: ANA_TX
3845 06:51:20.816229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3846 06:51:20.819015 ===================================
3847 06:51:20.822861 data_rate = 1200,PCW = 0X5800
3848 06:51:20.826038 ===================================
3849 06:51:20.829225 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3850 06:51:20.832223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3851 06:51:20.839031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3852 06:51:20.842336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3853 06:51:20.845419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3854 06:51:20.852125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3855 06:51:20.852212 [ANA_INIT] flow start
3856 06:51:20.855286 [ANA_INIT] PLL >>>>>>>>
3857 06:51:20.858679 [ANA_INIT] PLL <<<<<<<<
3858 06:51:20.858756 [ANA_INIT] MIDPI >>>>>>>>
3859 06:51:20.862288 [ANA_INIT] MIDPI <<<<<<<<
3860 06:51:20.865344 [ANA_INIT] DLL >>>>>>>>
3861 06:51:20.865417 [ANA_INIT] flow end
3862 06:51:20.872088 ============ LP4 DIFF to SE enter ============
3863 06:51:20.875038 ============ LP4 DIFF to SE exit ============
3864 06:51:20.875132 [ANA_INIT] <<<<<<<<<<<<<
3865 06:51:20.878306 [Flow] Enable top DCM control >>>>>
3866 06:51:20.881632 [Flow] Enable top DCM control <<<<<
3867 06:51:20.884986 Enable DLL master slave shuffle
3868 06:51:20.891528 ==============================================================
3869 06:51:20.895188 Gating Mode config
3870 06:51:20.897976 ==============================================================
3871 06:51:20.901675 Config description:
3872 06:51:20.911079 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3873 06:51:20.917577 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3874 06:51:20.920835 SELPH_MODE 0: By rank 1: By Phase
3875 06:51:20.927454 ==============================================================
3876 06:51:20.931259 GAT_TRACK_EN = 1
3877 06:51:20.934004 RX_GATING_MODE = 2
3878 06:51:20.937346 RX_GATING_TRACK_MODE = 2
3879 06:51:20.940860 SELPH_MODE = 1
3880 06:51:20.944137 PICG_EARLY_EN = 1
3881 06:51:20.944217 VALID_LAT_VALUE = 1
3882 06:51:20.950673 ==============================================================
3883 06:51:20.954417 Enter into Gating configuration >>>>
3884 06:51:20.957346 Exit from Gating configuration <<<<
3885 06:51:20.960664 Enter into DVFS_PRE_config >>>>>
3886 06:51:20.971127 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3887 06:51:20.973866 Exit from DVFS_PRE_config <<<<<
3888 06:51:20.977148 Enter into PICG configuration >>>>
3889 06:51:20.980475 Exit from PICG configuration <<<<
3890 06:51:20.983907 [RX_INPUT] configuration >>>>>
3891 06:51:20.986849 [RX_INPUT] configuration <<<<<
3892 06:51:20.993737 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3893 06:51:20.996932 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3894 06:51:21.003976 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3895 06:51:21.010497 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3896 06:51:21.016955 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3897 06:51:21.023611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3898 06:51:21.027077 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3899 06:51:21.029922 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3900 06:51:21.033203 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3901 06:51:21.039678 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3902 06:51:21.043211 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3903 06:51:21.046226 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3904 06:51:21.049712 ===================================
3905 06:51:21.053166 LPDDR4 DRAM CONFIGURATION
3906 06:51:21.056381 ===================================
3907 06:51:21.059831 EX_ROW_EN[0] = 0x0
3908 06:51:21.060278 EX_ROW_EN[1] = 0x0
3909 06:51:21.062654 LP4Y_EN = 0x0
3910 06:51:21.063107 WORK_FSP = 0x0
3911 06:51:21.066417 WL = 0x2
3912 06:51:21.066907 RL = 0x2
3913 06:51:21.069556 BL = 0x2
3914 06:51:21.070012 RPST = 0x0
3915 06:51:21.073132 RD_PRE = 0x0
3916 06:51:21.073580 WR_PRE = 0x1
3917 06:51:21.076169 WR_PST = 0x0
3918 06:51:21.076601 DBI_WR = 0x0
3919 06:51:21.079418 DBI_RD = 0x0
3920 06:51:21.082515 OTF = 0x1
3921 06:51:21.086045 ===================================
3922 06:51:21.089183 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3923 06:51:21.092593 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3924 06:51:21.095551 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3925 06:51:21.099033 ===================================
3926 06:51:21.102165 LPDDR4 DRAM CONFIGURATION
3927 06:51:21.105740 ===================================
3928 06:51:21.109167 EX_ROW_EN[0] = 0x10
3929 06:51:21.109617 EX_ROW_EN[1] = 0x0
3930 06:51:21.112157 LP4Y_EN = 0x0
3931 06:51:21.112639 WORK_FSP = 0x0
3932 06:51:21.115746 WL = 0x2
3933 06:51:21.116414 RL = 0x2
3934 06:51:21.118973 BL = 0x2
3935 06:51:21.119652 RPST = 0x0
3936 06:51:21.122853 RD_PRE = 0x0
3937 06:51:21.123493 WR_PRE = 0x1
3938 06:51:21.125454 WR_PST = 0x0
3939 06:51:21.128955 DBI_WR = 0x0
3940 06:51:21.129525 DBI_RD = 0x0
3941 06:51:21.131703 OTF = 0x1
3942 06:51:21.134954 ===================================
3943 06:51:21.138557 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3944 06:51:21.144082 nWR fixed to 30
3945 06:51:21.146997 [ModeRegInit_LP4] CH0 RK0
3946 06:51:21.147483 [ModeRegInit_LP4] CH0 RK1
3947 06:51:21.150258 [ModeRegInit_LP4] CH1 RK0
3948 06:51:21.153449 [ModeRegInit_LP4] CH1 RK1
3949 06:51:21.153900 match AC timing 17
3950 06:51:21.160413 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3951 06:51:21.163649 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3952 06:51:21.166842 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3953 06:51:21.173208 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3954 06:51:21.176504 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3955 06:51:21.176943 ==
3956 06:51:21.180293 Dram Type= 6, Freq= 0, CH_0, rank 0
3957 06:51:21.183226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 06:51:21.186750 ==
3959 06:51:21.190167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3960 06:51:21.196423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3961 06:51:21.199493 [CA 0] Center 36 (6~67) winsize 62
3962 06:51:21.203217 [CA 1] Center 36 (5~67) winsize 63
3963 06:51:21.206159 [CA 2] Center 34 (4~65) winsize 62
3964 06:51:21.209433 [CA 3] Center 34 (3~65) winsize 63
3965 06:51:21.213178 [CA 4] Center 33 (3~64) winsize 62
3966 06:51:21.216137 [CA 5] Center 33 (3~64) winsize 62
3967 06:51:21.216745
3968 06:51:21.220348 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3969 06:51:21.220908
3970 06:51:21.222528 [CATrainingPosCal] consider 1 rank data
3971 06:51:21.226179 u2DelayCellTimex100 = 270/100 ps
3972 06:51:21.229544 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3973 06:51:21.232459 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3974 06:51:21.239957 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3975 06:51:21.242400 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3976 06:51:21.245648 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3977 06:51:21.248885 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 06:51:21.249458
3979 06:51:21.252379 CA PerBit enable=1, Macro0, CA PI delay=33
3980 06:51:21.252812
3981 06:51:21.255655 [CBTSetCACLKResult] CA Dly = 33
3982 06:51:21.256082 CS Dly: 5 (0~36)
3983 06:51:21.258787 ==
3984 06:51:21.259235 Dram Type= 6, Freq= 0, CH_0, rank 1
3985 06:51:21.265605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 06:51:21.266237 ==
3987 06:51:21.269149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3988 06:51:21.275580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3989 06:51:21.279110 [CA 0] Center 36 (6~67) winsize 62
3990 06:51:21.282903 [CA 1] Center 36 (6~67) winsize 62
3991 06:51:21.285811 [CA 2] Center 34 (4~65) winsize 62
3992 06:51:21.289245 [CA 3] Center 34 (4~65) winsize 62
3993 06:51:21.292381 [CA 4] Center 34 (3~65) winsize 63
3994 06:51:21.295671 [CA 5] Center 33 (3~64) winsize 62
3995 06:51:21.296111
3996 06:51:21.299072 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3997 06:51:21.299580
3998 06:51:21.302609 [CATrainingPosCal] consider 2 rank data
3999 06:51:21.305468 u2DelayCellTimex100 = 270/100 ps
4000 06:51:21.308682 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4001 06:51:21.315614 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4002 06:51:21.319332 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4003 06:51:21.322339 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4004 06:51:21.325216 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4005 06:51:21.328387 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 06:51:21.328926
4007 06:51:21.332105 CA PerBit enable=1, Macro0, CA PI delay=33
4008 06:51:21.332595
4009 06:51:21.335420 [CBTSetCACLKResult] CA Dly = 33
4010 06:51:21.338458 CS Dly: 5 (0~37)
4011 06:51:21.338971
4012 06:51:21.341858 ----->DramcWriteLeveling(PI) begin...
4013 06:51:21.342346 ==
4014 06:51:21.344682 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 06:51:21.347964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 06:51:21.348486 ==
4017 06:51:21.351296 Write leveling (Byte 0): 35 => 35
4018 06:51:21.354513 Write leveling (Byte 1): 31 => 31
4019 06:51:21.357572 DramcWriteLeveling(PI) end<-----
4020 06:51:21.357652
4021 06:51:21.357715 ==
4022 06:51:21.360973 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 06:51:21.364171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 06:51:21.364247 ==
4025 06:51:21.368253 [Gating] SW mode calibration
4026 06:51:21.374137 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4027 06:51:21.380590 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4028 06:51:21.383899 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4029 06:51:21.390673 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 06:51:21.394177 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 06:51:21.397405 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4032 06:51:21.403760 0 9 16 | B1->B0 | 3030 2b2b | 1 0 | (1 0) (0 0)
4033 06:51:21.407170 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 06:51:21.410092 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 06:51:21.416710 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 06:51:21.420076 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 06:51:21.423897 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 06:51:21.430735 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 06:51:21.433386 0 10 12 | B1->B0 | 2424 3030 | 0 0 | (0 0) (1 1)
4040 06:51:21.436929 0 10 16 | B1->B0 | 3a3a 4040 | 0 1 | (0 0) (0 0)
4041 06:51:21.443805 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 06:51:21.446411 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 06:51:21.449914 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 06:51:21.456472 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 06:51:21.459664 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 06:51:21.462754 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 06:51:21.469511 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4048 06:51:21.473094 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4049 06:51:21.476048 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 06:51:21.482714 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 06:51:21.485803 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 06:51:21.489652 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 06:51:21.495734 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 06:51:21.499450 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 06:51:21.502923 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 06:51:21.509161 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 06:51:21.512396 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 06:51:21.515687 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 06:51:21.522290 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 06:51:21.525550 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 06:51:21.528696 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 06:51:21.535323 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 06:51:21.538766 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 06:51:21.542371 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4065 06:51:21.545737 Total UI for P1: 0, mck2ui 16
4066 06:51:21.548576 best dqsien dly found for B0: ( 0, 13, 14)
4067 06:51:21.555458 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 06:51:21.555562 Total UI for P1: 0, mck2ui 16
4069 06:51:21.558342 best dqsien dly found for B1: ( 0, 13, 16)
4070 06:51:21.565007 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4071 06:51:21.568524 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4072 06:51:21.568597
4073 06:51:21.571782 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4074 06:51:21.574904 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4075 06:51:21.578076 [Gating] SW calibration Done
4076 06:51:21.578159 ==
4077 06:51:21.581514 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 06:51:21.584825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 06:51:21.584899 ==
4080 06:51:21.588468 RX Vref Scan: 0
4081 06:51:21.588575
4082 06:51:21.588678 RX Vref 0 -> 0, step: 1
4083 06:51:21.588748
4084 06:51:21.592259 RX Delay -230 -> 252, step: 16
4085 06:51:21.598160 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4086 06:51:21.601607 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4087 06:51:21.604359 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4088 06:51:21.607931 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4089 06:51:21.614280 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4090 06:51:21.617828 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4091 06:51:21.621185 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4092 06:51:21.624613 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4093 06:51:21.627674 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4094 06:51:21.634418 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4095 06:51:21.638037 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4096 06:51:21.640847 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4097 06:51:21.644170 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4098 06:51:21.650879 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4099 06:51:21.654125 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4100 06:51:21.657232 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4101 06:51:21.657316 ==
4102 06:51:21.660732 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 06:51:21.667527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 06:51:21.667610 ==
4105 06:51:21.667673 DQS Delay:
4106 06:51:21.667732 DQS0 = 0, DQS1 = 0
4107 06:51:21.670348 DQM Delay:
4108 06:51:21.670428 DQM0 = 43, DQM1 = 35
4109 06:51:21.673653 DQ Delay:
4110 06:51:21.677065 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4111 06:51:21.680844 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4112 06:51:21.683588 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4113 06:51:21.686749 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4114 06:51:21.686822
4115 06:51:21.686884
4116 06:51:21.686951 ==
4117 06:51:21.689982 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 06:51:21.693416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 06:51:21.693486 ==
4120 06:51:21.693546
4121 06:51:21.693603
4122 06:51:21.697035 TX Vref Scan disable
4123 06:51:21.697109 == TX Byte 0 ==
4124 06:51:21.703333 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4125 06:51:21.706701 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4126 06:51:21.710511 == TX Byte 1 ==
4127 06:51:21.713198 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4128 06:51:21.716829 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4129 06:51:21.716906 ==
4130 06:51:21.720288 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 06:51:21.723154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 06:51:21.726621 ==
4133 06:51:21.726728
4134 06:51:21.726823
4135 06:51:21.726979 TX Vref Scan disable
4136 06:51:21.730627 == TX Byte 0 ==
4137 06:51:21.734278 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4138 06:51:21.740011 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4139 06:51:21.740096 == TX Byte 1 ==
4140 06:51:21.743505 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4141 06:51:21.750295 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4142 06:51:21.750373
4143 06:51:21.750436 [DATLAT]
4144 06:51:21.750503 Freq=600, CH0 RK0
4145 06:51:21.750561
4146 06:51:21.753254 DATLAT Default: 0x9
4147 06:51:21.753326 0, 0xFFFF, sum = 0
4148 06:51:21.756451 1, 0xFFFF, sum = 0
4149 06:51:21.760187 2, 0xFFFF, sum = 0
4150 06:51:21.760259 3, 0xFFFF, sum = 0
4151 06:51:21.763739 4, 0xFFFF, sum = 0
4152 06:51:21.763815 5, 0xFFFF, sum = 0
4153 06:51:21.766552 6, 0xFFFF, sum = 0
4154 06:51:21.766621 7, 0xFFFF, sum = 0
4155 06:51:21.770065 8, 0x0, sum = 1
4156 06:51:21.770148 9, 0x0, sum = 2
4157 06:51:21.770211 10, 0x0, sum = 3
4158 06:51:21.773072 11, 0x0, sum = 4
4159 06:51:21.773149 best_step = 9
4160 06:51:21.773210
4161 06:51:21.776285 ==
4162 06:51:21.776361 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 06:51:21.783084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 06:51:21.783162 ==
4165 06:51:21.783233 RX Vref Scan: 1
4166 06:51:21.783293
4167 06:51:21.786775 RX Vref 0 -> 0, step: 1
4168 06:51:21.786845
4169 06:51:21.789728 RX Delay -195 -> 252, step: 8
4170 06:51:21.789796
4171 06:51:21.793331 Set Vref, RX VrefLevel [Byte0]: 57
4172 06:51:21.796579 [Byte1]: 44
4173 06:51:21.796648
4174 06:51:21.799795 Final RX Vref Byte 0 = 57 to rank0
4175 06:51:21.802836 Final RX Vref Byte 1 = 44 to rank0
4176 06:51:21.806148 Final RX Vref Byte 0 = 57 to rank1
4177 06:51:21.809941 Final RX Vref Byte 1 = 44 to rank1==
4178 06:51:21.813399 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 06:51:21.816069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 06:51:21.819933 ==
4181 06:51:21.820042 DQS Delay:
4182 06:51:21.820123 DQS0 = 0, DQS1 = 0
4183 06:51:21.822835 DQM Delay:
4184 06:51:21.822949 DQM0 = 41, DQM1 = 33
4185 06:51:21.826496 DQ Delay:
4186 06:51:21.826612 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4187 06:51:21.829871 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4188 06:51:21.832883 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4189 06:51:21.836007 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4190 06:51:21.839243
4191 06:51:21.839452
4192 06:51:21.845909 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4193 06:51:21.849209 CH0 RK0: MR19=808, MR18=4E45
4194 06:51:21.855751 CH0_RK0: MR19=0x808, MR18=0x4E45, DQSOSC=395, MR23=63, INC=168, DEC=112
4195 06:51:21.856053
4196 06:51:21.859455 ----->DramcWriteLeveling(PI) begin...
4197 06:51:21.859768 ==
4198 06:51:21.862494 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 06:51:21.866238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 06:51:21.866712 ==
4201 06:51:21.869330 Write leveling (Byte 0): 33 => 33
4202 06:51:21.872830 Write leveling (Byte 1): 28 => 28
4203 06:51:21.876262 DramcWriteLeveling(PI) end<-----
4204 06:51:21.876772
4205 06:51:21.877195 ==
4206 06:51:21.879468 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 06:51:21.882394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 06:51:21.882924 ==
4209 06:51:21.885644 [Gating] SW mode calibration
4210 06:51:21.892651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4211 06:51:21.898990 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4212 06:51:21.902299 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4213 06:51:21.909240 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4214 06:51:21.912443 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4215 06:51:21.915613 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4216 06:51:21.922424 0 9 16 | B1->B0 | 2e2e 2525 | 1 0 | (1 1) (0 0)
4217 06:51:21.925941 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 06:51:21.929102 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 06:51:21.935735 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 06:51:21.939017 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 06:51:21.942620 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 06:51:21.948459 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4223 06:51:21.951866 0 10 12 | B1->B0 | 2d2d 3333 | 0 0 | (1 1) (0 0)
4224 06:51:21.954913 0 10 16 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
4225 06:51:21.961714 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 06:51:21.964939 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 06:51:21.968025 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 06:51:21.974922 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 06:51:21.978308 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 06:51:21.981716 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 06:51:21.987956 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4232 06:51:21.991130 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4233 06:51:21.994601 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 06:51:22.001115 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 06:51:22.005134 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 06:51:22.007977 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 06:51:22.014584 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 06:51:22.017787 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 06:51:22.020769 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 06:51:22.027632 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 06:51:22.030678 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 06:51:22.034103 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 06:51:22.040847 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 06:51:22.043744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 06:51:22.047547 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 06:51:22.054200 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 06:51:22.057162 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4248 06:51:22.060671 Total UI for P1: 0, mck2ui 16
4249 06:51:22.064148 best dqsien dly found for B0: ( 0, 13, 10)
4250 06:51:22.067243 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 06:51:22.070509 Total UI for P1: 0, mck2ui 16
4252 06:51:22.073651 best dqsien dly found for B1: ( 0, 13, 12)
4253 06:51:22.077029 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4254 06:51:22.080102 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4255 06:51:22.080523
4256 06:51:22.087038 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4257 06:51:22.090085 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4258 06:51:22.093628 [Gating] SW calibration Done
4259 06:51:22.094098 ==
4260 06:51:22.096409 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 06:51:22.100568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 06:51:22.100992 ==
4263 06:51:22.101323 RX Vref Scan: 0
4264 06:51:22.101636
4265 06:51:22.103512 RX Vref 0 -> 0, step: 1
4266 06:51:22.103932
4267 06:51:22.106645 RX Delay -230 -> 252, step: 16
4268 06:51:22.110165 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4269 06:51:22.113412 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4270 06:51:22.119874 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4271 06:51:22.123069 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4272 06:51:22.126590 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4273 06:51:22.129774 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4274 06:51:22.136495 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4275 06:51:22.139315 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4276 06:51:22.142713 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4277 06:51:22.146203 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4278 06:51:22.152679 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4279 06:51:22.156656 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4280 06:51:22.159418 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4281 06:51:22.162297 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4282 06:51:22.168971 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4283 06:51:22.172112 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4284 06:51:22.172833 ==
4285 06:51:22.175593 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 06:51:22.179037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 06:51:22.179547 ==
4288 06:51:22.182874 DQS Delay:
4289 06:51:22.183648 DQS0 = 0, DQS1 = 0
4290 06:51:22.184196 DQM Delay:
4291 06:51:22.185377 DQM0 = 49, DQM1 = 35
4292 06:51:22.185797 DQ Delay:
4293 06:51:22.188797 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4294 06:51:22.192057 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4295 06:51:22.195227 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4296 06:51:22.198882 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =49
4297 06:51:22.199511
4298 06:51:22.199919
4299 06:51:22.200265 ==
4300 06:51:22.202080 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 06:51:22.209113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 06:51:22.209692 ==
4303 06:51:22.210213
4304 06:51:22.210659
4305 06:51:22.211595 TX Vref Scan disable
4306 06:51:22.212005 == TX Byte 0 ==
4307 06:51:22.215440 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4308 06:51:22.222115 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4309 06:51:22.222559 == TX Byte 1 ==
4310 06:51:22.228653 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4311 06:51:22.231390 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4312 06:51:22.231821 ==
4313 06:51:22.234506 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 06:51:22.238411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 06:51:22.238872 ==
4316 06:51:22.239208
4317 06:51:22.239635
4318 06:51:22.241421 TX Vref Scan disable
4319 06:51:22.244877 == TX Byte 0 ==
4320 06:51:22.248265 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4321 06:51:22.251038 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4322 06:51:22.254847 == TX Byte 1 ==
4323 06:51:22.258088 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4324 06:51:22.261416 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4325 06:51:22.265217
4326 06:51:22.265626 [DATLAT]
4327 06:51:22.265987 Freq=600, CH0 RK1
4328 06:51:22.266303
4329 06:51:22.268238 DATLAT Default: 0x9
4330 06:51:22.268679 0, 0xFFFF, sum = 0
4331 06:51:22.271155 1, 0xFFFF, sum = 0
4332 06:51:22.271639 2, 0xFFFF, sum = 0
4333 06:51:22.274205 3, 0xFFFF, sum = 0
4334 06:51:22.277407 4, 0xFFFF, sum = 0
4335 06:51:22.277853 5, 0xFFFF, sum = 0
4336 06:51:22.280807 6, 0xFFFF, sum = 0
4337 06:51:22.281245 7, 0xFFFF, sum = 0
4338 06:51:22.284754 8, 0x0, sum = 1
4339 06:51:22.285244 9, 0x0, sum = 2
4340 06:51:22.285582 10, 0x0, sum = 3
4341 06:51:22.287827 11, 0x0, sum = 4
4342 06:51:22.288247 best_step = 9
4343 06:51:22.288574
4344 06:51:22.288878 ==
4345 06:51:22.290923 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 06:51:22.298098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 06:51:22.298641 ==
4348 06:51:22.298994 RX Vref Scan: 0
4349 06:51:22.299307
4350 06:51:22.301355 RX Vref 0 -> 0, step: 1
4351 06:51:22.301765
4352 06:51:22.304029 RX Delay -195 -> 252, step: 8
4353 06:51:22.307316 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4354 06:51:22.314206 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4355 06:51:22.317262 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4356 06:51:22.321406 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4357 06:51:22.323861 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4358 06:51:22.330628 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4359 06:51:22.334083 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4360 06:51:22.337328 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4361 06:51:22.340319 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4362 06:51:22.343688 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4363 06:51:22.350409 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4364 06:51:22.353658 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4365 06:51:22.357048 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4366 06:51:22.360203 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4367 06:51:22.367226 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4368 06:51:22.369965 iDelay=205, Bit 15, Center 36 (-115 ~ 188) 304
4369 06:51:22.370381 ==
4370 06:51:22.373234 Dram Type= 6, Freq= 0, CH_0, rank 1
4371 06:51:22.376908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 06:51:22.377324 ==
4373 06:51:22.380453 DQS Delay:
4374 06:51:22.380866 DQS0 = 0, DQS1 = 0
4375 06:51:22.383145 DQM Delay:
4376 06:51:22.383604 DQM0 = 41, DQM1 = 33
4377 06:51:22.383936 DQ Delay:
4378 06:51:22.386479 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4379 06:51:22.389399 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =44
4380 06:51:22.392836 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4381 06:51:22.396634 DQ12 =36, DQ13 =36, DQ14 =48, DQ15 =36
4382 06:51:22.396713
4383 06:51:22.396776
4384 06:51:22.406426 [DQSOSCAuto] RK1, (LSB)MR18= 0x453e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4385 06:51:22.409673 CH0 RK1: MR19=808, MR18=453E
4386 06:51:22.415996 CH0_RK1: MR19=0x808, MR18=0x453E, DQSOSC=396, MR23=63, INC=167, DEC=111
4387 06:51:22.419095 [RxdqsGatingPostProcess] freq 600
4388 06:51:22.422563 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4389 06:51:22.425874 Pre-setting of DQS Precalculation
4390 06:51:22.429596 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4391 06:51:22.432357 ==
4392 06:51:22.436129 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 06:51:22.439125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 06:51:22.439206 ==
4395 06:51:22.445594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4396 06:51:22.449110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4397 06:51:22.452820 [CA 0] Center 36 (6~66) winsize 61
4398 06:51:22.456158 [CA 1] Center 35 (5~66) winsize 62
4399 06:51:22.459646 [CA 2] Center 34 (4~65) winsize 62
4400 06:51:22.462749 [CA 3] Center 34 (3~65) winsize 63
4401 06:51:22.466020 [CA 4] Center 34 (4~65) winsize 62
4402 06:51:22.469536 [CA 5] Center 33 (3~64) winsize 62
4403 06:51:22.469616
4404 06:51:22.472862 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4405 06:51:22.472942
4406 06:51:22.475973 [CATrainingPosCal] consider 1 rank data
4407 06:51:22.479320 u2DelayCellTimex100 = 270/100 ps
4408 06:51:22.482411 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4409 06:51:22.489236 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4410 06:51:22.492172 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 06:51:22.495506 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4412 06:51:22.499012 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4413 06:51:22.502030 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 06:51:22.502111
4415 06:51:22.505688 CA PerBit enable=1, Macro0, CA PI delay=33
4416 06:51:22.505806
4417 06:51:22.508646 [CBTSetCACLKResult] CA Dly = 33
4418 06:51:22.512234 CS Dly: 4 (0~35)
4419 06:51:22.512314 ==
4420 06:51:22.515895 Dram Type= 6, Freq= 0, CH_1, rank 1
4421 06:51:22.519014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 06:51:22.519096 ==
4423 06:51:22.525453 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4424 06:51:22.529209 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4425 06:51:22.532992 [CA 0] Center 35 (5~66) winsize 62
4426 06:51:22.536128 [CA 1] Center 36 (6~66) winsize 61
4427 06:51:22.539890 [CA 2] Center 34 (4~65) winsize 62
4428 06:51:22.543111 [CA 3] Center 33 (3~64) winsize 62
4429 06:51:22.546368 [CA 4] Center 34 (3~65) winsize 63
4430 06:51:22.549436 [CA 5] Center 33 (3~64) winsize 62
4431 06:51:22.549518
4432 06:51:22.553013 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4433 06:51:22.553094
4434 06:51:22.556405 [CATrainingPosCal] consider 2 rank data
4435 06:51:22.559299 u2DelayCellTimex100 = 270/100 ps
4436 06:51:22.562841 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4437 06:51:22.569150 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4438 06:51:22.572311 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4439 06:51:22.576144 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4440 06:51:22.578895 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4441 06:51:22.582256 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 06:51:22.582337
4443 06:51:22.585694 CA PerBit enable=1, Macro0, CA PI delay=33
4444 06:51:22.585776
4445 06:51:22.588727 [CBTSetCACLKResult] CA Dly = 33
4446 06:51:22.592090 CS Dly: 4 (0~36)
4447 06:51:22.592170
4448 06:51:22.596097 ----->DramcWriteLeveling(PI) begin...
4449 06:51:22.596179 ==
4450 06:51:22.598856 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 06:51:22.602386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 06:51:22.602467 ==
4453 06:51:22.605311 Write leveling (Byte 0): 28 => 28
4454 06:51:22.608832 Write leveling (Byte 1): 30 => 30
4455 06:51:22.612162 DramcWriteLeveling(PI) end<-----
4456 06:51:22.612243
4457 06:51:22.612307 ==
4458 06:51:22.615176 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 06:51:22.618599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 06:51:22.618681 ==
4461 06:51:22.622257 [Gating] SW mode calibration
4462 06:51:22.629083 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4463 06:51:22.635247 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4464 06:51:22.638843 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4465 06:51:22.642273 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4466 06:51:22.648527 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 06:51:22.651564 0 9 12 | B1->B0 | 3030 2d2d | 0 0 | (1 1) (0 0)
4468 06:51:22.655071 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 06:51:22.661877 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 06:51:22.665210 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 06:51:22.668551 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 06:51:22.674756 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 06:51:22.677834 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 06:51:22.681241 0 10 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4475 06:51:22.687818 0 10 12 | B1->B0 | 3737 3838 | 1 1 | (0 0) (0 0)
4476 06:51:22.690922 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 06:51:22.694358 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 06:51:22.701155 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 06:51:22.704250 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 06:51:22.707288 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 06:51:22.713991 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 06:51:22.717469 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 06:51:22.721306 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4484 06:51:22.727497 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 06:51:22.730514 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 06:51:22.733887 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 06:51:22.740244 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 06:51:22.744070 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 06:51:22.747038 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 06:51:22.753602 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 06:51:22.757035 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 06:51:22.763200 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 06:51:22.766658 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 06:51:22.770117 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 06:51:22.776643 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 06:51:22.780124 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 06:51:22.784202 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 06:51:22.790112 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 06:51:22.793118 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4500 06:51:22.796663 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 06:51:22.799611 Total UI for P1: 0, mck2ui 16
4502 06:51:22.802870 best dqsien dly found for B0: ( 0, 13, 12)
4503 06:51:22.806498 Total UI for P1: 0, mck2ui 16
4504 06:51:22.810002 best dqsien dly found for B1: ( 0, 13, 12)
4505 06:51:22.812662 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4506 06:51:22.816024 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4507 06:51:22.816106
4508 06:51:22.822913 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4509 06:51:22.826205 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4510 06:51:22.826287 [Gating] SW calibration Done
4511 06:51:22.829097 ==
4512 06:51:22.832739 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 06:51:22.836528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 06:51:22.836611 ==
4515 06:51:22.836676 RX Vref Scan: 0
4516 06:51:22.836736
4517 06:51:22.840057 RX Vref 0 -> 0, step: 1
4518 06:51:22.840138
4519 06:51:22.842447 RX Delay -230 -> 252, step: 16
4520 06:51:22.845606 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4521 06:51:22.849223 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4522 06:51:22.855529 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4523 06:51:22.859173 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4524 06:51:22.862468 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4525 06:51:22.865496 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4526 06:51:22.872346 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4527 06:51:22.875659 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4528 06:51:22.878964 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4529 06:51:22.881960 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4530 06:51:22.888543 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4531 06:51:22.892052 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4532 06:51:22.895342 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4533 06:51:22.898257 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4534 06:51:22.905428 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4535 06:51:22.908136 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4536 06:51:22.908207 ==
4537 06:51:22.911518 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 06:51:22.914741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 06:51:22.914840 ==
4540 06:51:22.918389 DQS Delay:
4541 06:51:22.918480 DQS0 = 0, DQS1 = 0
4542 06:51:22.918542 DQM Delay:
4543 06:51:22.921073 DQM0 = 46, DQM1 = 40
4544 06:51:22.921158 DQ Delay:
4545 06:51:22.924571 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4546 06:51:22.927951 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4547 06:51:22.930906 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4548 06:51:22.934255 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =41
4549 06:51:22.934338
4550 06:51:22.934410
4551 06:51:22.934471 ==
4552 06:51:22.937688 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 06:51:22.944461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 06:51:22.944544 ==
4555 06:51:22.944609
4556 06:51:22.944668
4557 06:51:22.947448 TX Vref Scan disable
4558 06:51:22.947529 == TX Byte 0 ==
4559 06:51:22.950510 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4560 06:51:22.958007 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4561 06:51:22.958115 == TX Byte 1 ==
4562 06:51:22.964065 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4563 06:51:22.967569 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4564 06:51:22.967652 ==
4565 06:51:22.970523 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 06:51:22.973459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 06:51:22.973546 ==
4568 06:51:22.973611
4569 06:51:22.973670
4570 06:51:22.977130 TX Vref Scan disable
4571 06:51:22.980406 == TX Byte 0 ==
4572 06:51:22.984060 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4573 06:51:22.986634 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4574 06:51:22.989993 == TX Byte 1 ==
4575 06:51:22.993317 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4576 06:51:22.997241 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4577 06:51:22.997322
4578 06:51:22.999980 [DATLAT]
4579 06:51:23.000061 Freq=600, CH1 RK0
4580 06:51:23.000127
4581 06:51:23.003549 DATLAT Default: 0x9
4582 06:51:23.003631 0, 0xFFFF, sum = 0
4583 06:51:23.006535 1, 0xFFFF, sum = 0
4584 06:51:23.006619 2, 0xFFFF, sum = 0
4585 06:51:23.009974 3, 0xFFFF, sum = 0
4586 06:51:23.010058 4, 0xFFFF, sum = 0
4587 06:51:23.013271 5, 0xFFFF, sum = 0
4588 06:51:23.016290 6, 0xFFFF, sum = 0
4589 06:51:23.016373 7, 0xFFFF, sum = 0
4590 06:51:23.016439 8, 0x0, sum = 1
4591 06:51:23.020108 9, 0x0, sum = 2
4592 06:51:23.020191 10, 0x0, sum = 3
4593 06:51:23.023184 11, 0x0, sum = 4
4594 06:51:23.023267 best_step = 9
4595 06:51:23.023332
4596 06:51:23.023434 ==
4597 06:51:23.026592 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 06:51:23.033086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 06:51:23.033169 ==
4600 06:51:23.033234 RX Vref Scan: 1
4601 06:51:23.033294
4602 06:51:23.036552 RX Vref 0 -> 0, step: 1
4603 06:51:23.036633
4604 06:51:23.039651 RX Delay -179 -> 252, step: 8
4605 06:51:23.039732
4606 06:51:23.042871 Set Vref, RX VrefLevel [Byte0]: 50
4607 06:51:23.046305 [Byte1]: 53
4608 06:51:23.046386
4609 06:51:23.049588 Final RX Vref Byte 0 = 50 to rank0
4610 06:51:23.052814 Final RX Vref Byte 1 = 53 to rank0
4611 06:51:23.056147 Final RX Vref Byte 0 = 50 to rank1
4612 06:51:23.059577 Final RX Vref Byte 1 = 53 to rank1==
4613 06:51:23.062648 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 06:51:23.066111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 06:51:23.066193 ==
4616 06:51:23.069183 DQS Delay:
4617 06:51:23.069264 DQS0 = 0, DQS1 = 0
4618 06:51:23.072425 DQM Delay:
4619 06:51:23.072507 DQM0 = 42, DQM1 = 34
4620 06:51:23.072572 DQ Delay:
4621 06:51:23.075864 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4622 06:51:23.079466 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4623 06:51:23.082363 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4624 06:51:23.085991 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4625 06:51:23.086073
4626 06:51:23.086137
4627 06:51:23.095728 [DQSOSCAuto] RK0, (LSB)MR18= 0x324b, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4628 06:51:23.098722 CH1 RK0: MR19=808, MR18=324B
4629 06:51:23.105551 CH1_RK0: MR19=0x808, MR18=0x324B, DQSOSC=395, MR23=63, INC=168, DEC=112
4630 06:51:23.105633
4631 06:51:23.108502 ----->DramcWriteLeveling(PI) begin...
4632 06:51:23.108585 ==
4633 06:51:23.111897 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 06:51:23.115202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 06:51:23.115284 ==
4636 06:51:23.118656 Write leveling (Byte 0): 30 => 30
4637 06:51:23.121660 Write leveling (Byte 1): 30 => 30
4638 06:51:23.125345 DramcWriteLeveling(PI) end<-----
4639 06:51:23.125427
4640 06:51:23.125491 ==
4641 06:51:23.128424 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 06:51:23.132185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 06:51:23.132268 ==
4644 06:51:23.135087 [Gating] SW mode calibration
4645 06:51:23.141721 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4646 06:51:23.148074 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4647 06:51:23.151284 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4648 06:51:23.158794 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4649 06:51:23.161084 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4650 06:51:23.164516 0 9 12 | B1->B0 | 3030 2828 | 1 0 | (1 1) (1 0)
4651 06:51:23.171154 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 06:51:23.174639 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 06:51:23.177629 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 06:51:23.184619 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 06:51:23.188069 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 06:51:23.191002 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 06:51:23.197608 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4658 06:51:23.200752 0 10 12 | B1->B0 | 2f2f 3c3c | 1 0 | (0 0) (1 1)
4659 06:51:23.204258 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4660 06:51:23.210410 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 06:51:23.214569 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 06:51:23.217134 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 06:51:23.223784 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 06:51:23.227140 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 06:51:23.230389 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 06:51:23.237109 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4667 06:51:23.240361 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 06:51:23.243389 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 06:51:23.250309 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 06:51:23.253808 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 06:51:23.256816 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 06:51:23.263240 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 06:51:23.266614 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 06:51:23.270047 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 06:51:23.276478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 06:51:23.280005 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 06:51:23.283282 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 06:51:23.289848 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 06:51:23.293364 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 06:51:23.296411 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 06:51:23.303348 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4682 06:51:23.306481 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4683 06:51:23.309923 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 06:51:23.313005 Total UI for P1: 0, mck2ui 16
4685 06:51:23.316688 best dqsien dly found for B0: ( 0, 13, 10)
4686 06:51:23.319566 Total UI for P1: 0, mck2ui 16
4687 06:51:23.322977 best dqsien dly found for B1: ( 0, 13, 14)
4688 06:51:23.326509 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4689 06:51:23.329970 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4690 06:51:23.330388
4691 06:51:23.336294 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4692 06:51:23.339701 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4693 06:51:23.343196 [Gating] SW calibration Done
4694 06:51:23.343706 ==
4695 06:51:23.346160 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 06:51:23.349313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 06:51:23.349889 ==
4698 06:51:23.350248 RX Vref Scan: 0
4699 06:51:23.350650
4700 06:51:23.352542 RX Vref 0 -> 0, step: 1
4701 06:51:23.352973
4702 06:51:23.356185 RX Delay -230 -> 252, step: 16
4703 06:51:23.359582 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4704 06:51:23.366086 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4705 06:51:23.369658 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4706 06:51:23.372547 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4707 06:51:23.376052 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4708 06:51:23.379522 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4709 06:51:23.385492 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4710 06:51:23.388832 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4711 06:51:23.392364 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4712 06:51:23.395498 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4713 06:51:23.402179 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4714 06:51:23.405540 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4715 06:51:23.408391 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4716 06:51:23.412398 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4717 06:51:23.418857 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4718 06:51:23.421907 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4719 06:51:23.422472 ==
4720 06:51:23.424926 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 06:51:23.428531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 06:51:23.429053 ==
4723 06:51:23.431929 DQS Delay:
4724 06:51:23.432473 DQS0 = 0, DQS1 = 0
4725 06:51:23.432843 DQM Delay:
4726 06:51:23.434811 DQM0 = 40, DQM1 = 38
4727 06:51:23.435311 DQ Delay:
4728 06:51:23.438496 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4729 06:51:23.441951 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4730 06:51:23.444958 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4731 06:51:23.448030 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4732 06:51:23.448483
4733 06:51:23.448816
4734 06:51:23.449129 ==
4735 06:51:23.451248 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 06:51:23.458385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 06:51:23.458901 ==
4738 06:51:23.459237
4739 06:51:23.459639
4740 06:51:23.461340 TX Vref Scan disable
4741 06:51:23.461755 == TX Byte 0 ==
4742 06:51:23.464593 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4743 06:51:23.472291 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4744 06:51:23.472815 == TX Byte 1 ==
4745 06:51:23.474649 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4746 06:51:23.481463 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4747 06:51:23.482057 ==
4748 06:51:23.484659 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 06:51:23.487498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 06:51:23.488116 ==
4751 06:51:23.488541
4752 06:51:23.488944
4753 06:51:23.490968 TX Vref Scan disable
4754 06:51:23.494224 == TX Byte 0 ==
4755 06:51:23.497634 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4756 06:51:23.500592 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4757 06:51:23.504296 == TX Byte 1 ==
4758 06:51:23.507508 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4759 06:51:23.510787 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4760 06:51:23.511481
4761 06:51:23.513721 [DATLAT]
4762 06:51:23.514140 Freq=600, CH1 RK1
4763 06:51:23.514485
4764 06:51:23.517452 DATLAT Default: 0x9
4765 06:51:23.517890 0, 0xFFFF, sum = 0
4766 06:51:23.520500 1, 0xFFFF, sum = 0
4767 06:51:23.521098 2, 0xFFFF, sum = 0
4768 06:51:23.523421 3, 0xFFFF, sum = 0
4769 06:51:23.523845 4, 0xFFFF, sum = 0
4770 06:51:23.526769 5, 0xFFFF, sum = 0
4771 06:51:23.527231 6, 0xFFFF, sum = 0
4772 06:51:23.530613 7, 0xFFFF, sum = 0
4773 06:51:23.531048 8, 0x0, sum = 1
4774 06:51:23.533962 9, 0x0, sum = 2
4775 06:51:23.534413 10, 0x0, sum = 3
4776 06:51:23.537191 11, 0x0, sum = 4
4777 06:51:23.537657 best_step = 9
4778 06:51:23.537983
4779 06:51:23.538347 ==
4780 06:51:23.540111 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 06:51:23.546879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 06:51:23.547297 ==
4783 06:51:23.547689 RX Vref Scan: 0
4784 06:51:23.548007
4785 06:51:23.550411 RX Vref 0 -> 0, step: 1
4786 06:51:23.550843
4787 06:51:23.553222 RX Delay -179 -> 252, step: 8
4788 06:51:23.556809 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4789 06:51:23.563141 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4790 06:51:23.566747 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4791 06:51:23.570217 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4792 06:51:23.573555 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4793 06:51:23.579993 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4794 06:51:23.583069 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4795 06:51:23.586449 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4796 06:51:23.589917 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4797 06:51:23.592989 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4798 06:51:23.599666 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4799 06:51:23.603020 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4800 06:51:23.606009 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4801 06:51:23.610272 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4802 06:51:23.616074 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4803 06:51:23.618988 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4804 06:51:23.619453 ==
4805 06:51:23.622524 Dram Type= 6, Freq= 0, CH_1, rank 1
4806 06:51:23.626053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4807 06:51:23.626471 ==
4808 06:51:23.629010 DQS Delay:
4809 06:51:23.629424 DQS0 = 0, DQS1 = 0
4810 06:51:23.632505 DQM Delay:
4811 06:51:23.632920 DQM0 = 36, DQM1 = 35
4812 06:51:23.633252 DQ Delay:
4813 06:51:23.636109 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4814 06:51:23.639197 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4815 06:51:23.642506 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4816 06:51:23.645631 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4817 06:51:23.646088
4818 06:51:23.646429
4819 06:51:23.656247 [DQSOSCAuto] RK1, (LSB)MR18= 0x395e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4820 06:51:23.658975 CH1 RK1: MR19=808, MR18=395E
4821 06:51:23.665374 CH1_RK1: MR19=0x808, MR18=0x395E, DQSOSC=392, MR23=63, INC=170, DEC=113
4822 06:51:23.668333 [RxdqsGatingPostProcess] freq 600
4823 06:51:23.671635 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4824 06:51:23.674694 Pre-setting of DQS Precalculation
4825 06:51:23.681466 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4826 06:51:23.687833 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4827 06:51:23.694771 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4828 06:51:23.694855
4829 06:51:23.694921
4830 06:51:23.697785 [Calibration Summary] 1200 Mbps
4831 06:51:23.697873 CH 0, Rank 0
4832 06:51:23.701184 SW Impedance : PASS
4833 06:51:23.705165 DUTY Scan : NO K
4834 06:51:23.705260 ZQ Calibration : PASS
4835 06:51:23.708175 Jitter Meter : NO K
4836 06:51:23.711226 CBT Training : PASS
4837 06:51:23.711336 Write leveling : PASS
4838 06:51:23.714624 RX DQS gating : PASS
4839 06:51:23.717728 RX DQ/DQS(RDDQC) : PASS
4840 06:51:23.717850 TX DQ/DQS : PASS
4841 06:51:23.721323 RX DATLAT : PASS
4842 06:51:23.721460 RX DQ/DQS(Engine): PASS
4843 06:51:23.724618 TX OE : NO K
4844 06:51:23.724755 All Pass.
4845 06:51:23.724862
4846 06:51:23.727501 CH 0, Rank 1
4847 06:51:23.727651 SW Impedance : PASS
4848 06:51:23.731147 DUTY Scan : NO K
4849 06:51:23.734385 ZQ Calibration : PASS
4850 06:51:23.734558 Jitter Meter : NO K
4851 06:51:23.737395 CBT Training : PASS
4852 06:51:23.740672 Write leveling : PASS
4853 06:51:23.740753 RX DQS gating : PASS
4854 06:51:23.744394 RX DQ/DQS(RDDQC) : PASS
4855 06:51:23.747261 TX DQ/DQS : PASS
4856 06:51:23.747358 RX DATLAT : PASS
4857 06:51:23.750663 RX DQ/DQS(Engine): PASS
4858 06:51:23.754370 TX OE : NO K
4859 06:51:23.754451 All Pass.
4860 06:51:23.754516
4861 06:51:23.754576 CH 1, Rank 0
4862 06:51:23.757529 SW Impedance : PASS
4863 06:51:23.760540 DUTY Scan : NO K
4864 06:51:23.760622 ZQ Calibration : PASS
4865 06:51:23.764068 Jitter Meter : NO K
4866 06:51:23.767190 CBT Training : PASS
4867 06:51:23.767271 Write leveling : PASS
4868 06:51:23.770431 RX DQS gating : PASS
4869 06:51:23.773694 RX DQ/DQS(RDDQC) : PASS
4870 06:51:23.773775 TX DQ/DQS : PASS
4871 06:51:23.776896 RX DATLAT : PASS
4872 06:51:23.780294 RX DQ/DQS(Engine): PASS
4873 06:51:23.780375 TX OE : NO K
4874 06:51:23.783269 All Pass.
4875 06:51:23.783350
4876 06:51:23.783455 CH 1, Rank 1
4877 06:51:23.787147 SW Impedance : PASS
4878 06:51:23.787229 DUTY Scan : NO K
4879 06:51:23.790453 ZQ Calibration : PASS
4880 06:51:23.793931 Jitter Meter : NO K
4881 06:51:23.794013 CBT Training : PASS
4882 06:51:23.797069 Write leveling : PASS
4883 06:51:23.799934 RX DQS gating : PASS
4884 06:51:23.800078 RX DQ/DQS(RDDQC) : PASS
4885 06:51:23.803235 TX DQ/DQS : PASS
4886 06:51:23.806351 RX DATLAT : PASS
4887 06:51:23.806432 RX DQ/DQS(Engine): PASS
4888 06:51:23.809727 TX OE : NO K
4889 06:51:23.809808 All Pass.
4890 06:51:23.809872
4891 06:51:23.813016 DramC Write-DBI off
4892 06:51:23.816293 PER_BANK_REFRESH: Hybrid Mode
4893 06:51:23.816374 TX_TRACKING: ON
4894 06:51:23.826086 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4895 06:51:23.829682 [FAST_K] Save calibration result to emmc
4896 06:51:23.832921 dramc_set_vcore_voltage set vcore to 662500
4897 06:51:23.835810 Read voltage for 933, 3
4898 06:51:23.835891 Vio18 = 0
4899 06:51:23.835955 Vcore = 662500
4900 06:51:23.839251 Vdram = 0
4901 06:51:23.839366 Vddq = 0
4902 06:51:23.839451 Vmddr = 0
4903 06:51:23.845979 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4904 06:51:23.849353 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4905 06:51:23.852725 MEM_TYPE=3, freq_sel=17
4906 06:51:23.855786 sv_algorithm_assistance_LP4_1600
4907 06:51:23.859264 ============ PULL DRAM RESETB DOWN ============
4908 06:51:23.862703 ========== PULL DRAM RESETB DOWN end =========
4909 06:51:23.869226 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4910 06:51:23.872068 ===================================
4911 06:51:23.875548 LPDDR4 DRAM CONFIGURATION
4912 06:51:23.879283 ===================================
4913 06:51:23.879392 EX_ROW_EN[0] = 0x0
4914 06:51:23.882228 EX_ROW_EN[1] = 0x0
4915 06:51:23.882309 LP4Y_EN = 0x0
4916 06:51:23.885993 WORK_FSP = 0x0
4917 06:51:23.886074 WL = 0x3
4918 06:51:23.888910 RL = 0x3
4919 06:51:23.888991 BL = 0x2
4920 06:51:23.891996 RPST = 0x0
4921 06:51:23.892077 RD_PRE = 0x0
4922 06:51:23.895451 WR_PRE = 0x1
4923 06:51:23.895532 WR_PST = 0x0
4924 06:51:23.898741 DBI_WR = 0x0
4925 06:51:23.898821 DBI_RD = 0x0
4926 06:51:23.901829 OTF = 0x1
4927 06:51:23.905378 ===================================
4928 06:51:23.908938 ===================================
4929 06:51:23.909020 ANA top config
4930 06:51:23.912081 ===================================
4931 06:51:23.914895 DLL_ASYNC_EN = 0
4932 06:51:23.918149 ALL_SLAVE_EN = 1
4933 06:51:23.921793 NEW_RANK_MODE = 1
4934 06:51:23.925406 DLL_IDLE_MODE = 1
4935 06:51:23.925487 LP45_APHY_COMB_EN = 1
4936 06:51:23.928270 TX_ODT_DIS = 1
4937 06:51:23.931879 NEW_8X_MODE = 1
4938 06:51:23.935017 ===================================
4939 06:51:23.938180 ===================================
4940 06:51:23.941271 data_rate = 1866
4941 06:51:23.944958 CKR = 1
4942 06:51:23.945040 DQ_P2S_RATIO = 8
4943 06:51:23.948188 ===================================
4944 06:51:23.951428 CA_P2S_RATIO = 8
4945 06:51:23.954815 DQ_CA_OPEN = 0
4946 06:51:23.958286 DQ_SEMI_OPEN = 0
4947 06:51:23.960977 CA_SEMI_OPEN = 0
4948 06:51:23.964244 CA_FULL_RATE = 0
4949 06:51:23.964325 DQ_CKDIV4_EN = 1
4950 06:51:23.968074 CA_CKDIV4_EN = 1
4951 06:51:23.971091 CA_PREDIV_EN = 0
4952 06:51:23.974557 PH8_DLY = 0
4953 06:51:23.977460 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4954 06:51:23.981059 DQ_AAMCK_DIV = 4
4955 06:51:23.984299 CA_AAMCK_DIV = 4
4956 06:51:23.984384 CA_ADMCK_DIV = 4
4957 06:51:23.987758 DQ_TRACK_CA_EN = 0
4958 06:51:23.990774 CA_PICK = 933
4959 06:51:23.994016 CA_MCKIO = 933
4960 06:51:23.997361 MCKIO_SEMI = 0
4961 06:51:24.000749 PLL_FREQ = 3732
4962 06:51:24.004161 DQ_UI_PI_RATIO = 32
4963 06:51:24.004243 CA_UI_PI_RATIO = 0
4964 06:51:24.007283 ===================================
4965 06:51:24.010515 ===================================
4966 06:51:24.014219 memory_type:LPDDR4
4967 06:51:24.017304 GP_NUM : 10
4968 06:51:24.017385 SRAM_EN : 1
4969 06:51:24.020753 MD32_EN : 0
4970 06:51:24.023727 ===================================
4971 06:51:24.027224 [ANA_INIT] >>>>>>>>>>>>>>
4972 06:51:24.030416 <<<<<< [CONFIGURE PHASE]: ANA_TX
4973 06:51:24.033985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4974 06:51:24.036667 ===================================
4975 06:51:24.036749 data_rate = 1866,PCW = 0X8f00
4976 06:51:24.040677 ===================================
4977 06:51:24.046568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4978 06:51:24.050055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4979 06:51:24.056669 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4980 06:51:24.060091 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4981 06:51:24.063657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4982 06:51:24.067163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4983 06:51:24.069714 [ANA_INIT] flow start
4984 06:51:24.073423 [ANA_INIT] PLL >>>>>>>>
4985 06:51:24.073516 [ANA_INIT] PLL <<<<<<<<
4986 06:51:24.077075 [ANA_INIT] MIDPI >>>>>>>>
4987 06:51:24.080454 [ANA_INIT] MIDPI <<<<<<<<
4988 06:51:24.080918 [ANA_INIT] DLL >>>>>>>>
4989 06:51:24.083454 [ANA_INIT] flow end
4990 06:51:24.086445 ============ LP4 DIFF to SE enter ============
4991 06:51:24.093120 ============ LP4 DIFF to SE exit ============
4992 06:51:24.093541 [ANA_INIT] <<<<<<<<<<<<<
4993 06:51:24.096645 [Flow] Enable top DCM control >>>>>
4994 06:51:24.100329 [Flow] Enable top DCM control <<<<<
4995 06:51:24.103395 Enable DLL master slave shuffle
4996 06:51:24.109725 ==============================================================
4997 06:51:24.110240 Gating Mode config
4998 06:51:24.116340 ==============================================================
4999 06:51:24.119231 Config description:
5000 06:51:24.129447 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5001 06:51:24.135933 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5002 06:51:24.139280 SELPH_MODE 0: By rank 1: By Phase
5003 06:51:24.145713 ==============================================================
5004 06:51:24.148932 GAT_TRACK_EN = 1
5005 06:51:24.152525 RX_GATING_MODE = 2
5006 06:51:24.155850 RX_GATING_TRACK_MODE = 2
5007 06:51:24.156269 SELPH_MODE = 1
5008 06:51:24.158737 PICG_EARLY_EN = 1
5009 06:51:24.162356 VALID_LAT_VALUE = 1
5010 06:51:24.169125 ==============================================================
5011 06:51:24.172211 Enter into Gating configuration >>>>
5012 06:51:24.175604 Exit from Gating configuration <<<<
5013 06:51:24.179348 Enter into DVFS_PRE_config >>>>>
5014 06:51:24.188546 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5015 06:51:24.192179 Exit from DVFS_PRE_config <<<<<
5016 06:51:24.194820 Enter into PICG configuration >>>>
5017 06:51:24.198126 Exit from PICG configuration <<<<
5018 06:51:24.201502 [RX_INPUT] configuration >>>>>
5019 06:51:24.204734 [RX_INPUT] configuration <<<<<
5020 06:51:24.208154 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5021 06:51:24.214859 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5022 06:51:24.221510 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5023 06:51:24.227979 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5024 06:51:24.234325 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5025 06:51:24.240988 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5026 06:51:24.244423 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5027 06:51:24.247421 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5028 06:51:24.250610 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5029 06:51:24.258169 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5030 06:51:24.261068 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5031 06:51:24.264177 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5032 06:51:24.267426 ===================================
5033 06:51:24.270568 LPDDR4 DRAM CONFIGURATION
5034 06:51:24.274091 ===================================
5035 06:51:24.274513 EX_ROW_EN[0] = 0x0
5036 06:51:24.277065 EX_ROW_EN[1] = 0x0
5037 06:51:24.280529 LP4Y_EN = 0x0
5038 06:51:24.280950 WORK_FSP = 0x0
5039 06:51:24.283814 WL = 0x3
5040 06:51:24.284232 RL = 0x3
5041 06:51:24.287325 BL = 0x2
5042 06:51:24.287846 RPST = 0x0
5043 06:51:24.290694 RD_PRE = 0x0
5044 06:51:24.291109 WR_PRE = 0x1
5045 06:51:24.293859 WR_PST = 0x0
5046 06:51:24.294291 DBI_WR = 0x0
5047 06:51:24.297015 DBI_RD = 0x0
5048 06:51:24.297449 OTF = 0x1
5049 06:51:24.300111 ===================================
5050 06:51:24.306803 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5051 06:51:24.310360 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5052 06:51:24.313592 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5053 06:51:24.316576 ===================================
5054 06:51:24.320480 LPDDR4 DRAM CONFIGURATION
5055 06:51:24.323540 ===================================
5056 06:51:24.324178 EX_ROW_EN[0] = 0x10
5057 06:51:24.326640 EX_ROW_EN[1] = 0x0
5058 06:51:24.330204 LP4Y_EN = 0x0
5059 06:51:24.330802 WORK_FSP = 0x0
5060 06:51:24.332990 WL = 0x3
5061 06:51:24.333553 RL = 0x3
5062 06:51:24.336651 BL = 0x2
5063 06:51:24.337212 RPST = 0x0
5064 06:51:24.339651 RD_PRE = 0x0
5065 06:51:24.340209 WR_PRE = 0x1
5066 06:51:24.343565 WR_PST = 0x0
5067 06:51:24.343976 DBI_WR = 0x0
5068 06:51:24.346381 DBI_RD = 0x0
5069 06:51:24.346799 OTF = 0x1
5070 06:51:24.349739 ===================================
5071 06:51:24.356512 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5072 06:51:24.360726 nWR fixed to 30
5073 06:51:24.364396 [ModeRegInit_LP4] CH0 RK0
5074 06:51:24.364848 [ModeRegInit_LP4] CH0 RK1
5075 06:51:24.367681 [ModeRegInit_LP4] CH1 RK0
5076 06:51:24.370750 [ModeRegInit_LP4] CH1 RK1
5077 06:51:24.371209 match AC timing 9
5078 06:51:24.377518 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5079 06:51:24.381192 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5080 06:51:24.384347 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5081 06:51:24.390775 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5082 06:51:24.394141 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5083 06:51:24.394561 ==
5084 06:51:24.397393 Dram Type= 6, Freq= 0, CH_0, rank 0
5085 06:51:24.400224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5086 06:51:24.400645 ==
5087 06:51:24.407137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5088 06:51:24.413622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5089 06:51:24.416685 [CA 0] Center 37 (7~68) winsize 62
5090 06:51:24.420415 [CA 1] Center 37 (7~68) winsize 62
5091 06:51:24.423797 [CA 2] Center 34 (4~65) winsize 62
5092 06:51:24.426699 [CA 3] Center 34 (4~65) winsize 62
5093 06:51:24.430219 [CA 4] Center 33 (2~64) winsize 63
5094 06:51:24.433839 [CA 5] Center 32 (2~63) winsize 62
5095 06:51:24.434260
5096 06:51:24.436718 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5097 06:51:24.437136
5098 06:51:24.440110 [CATrainingPosCal] consider 1 rank data
5099 06:51:24.443069 u2DelayCellTimex100 = 270/100 ps
5100 06:51:24.446361 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5101 06:51:24.449885 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5102 06:51:24.453116 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5103 06:51:24.459793 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5104 06:51:24.463124 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5105 06:51:24.466231 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5106 06:51:24.466680
5107 06:51:24.469777 CA PerBit enable=1, Macro0, CA PI delay=32
5108 06:51:24.470259
5109 06:51:24.473005 [CBTSetCACLKResult] CA Dly = 32
5110 06:51:24.473412 CS Dly: 5 (0~36)
5111 06:51:24.473746 ==
5112 06:51:24.476481 Dram Type= 6, Freq= 0, CH_0, rank 1
5113 06:51:24.482774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 06:51:24.483209 ==
5115 06:51:24.486272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5116 06:51:24.492685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5117 06:51:24.496173 [CA 0] Center 38 (8~69) winsize 62
5118 06:51:24.499441 [CA 1] Center 37 (7~68) winsize 62
5119 06:51:24.503113 [CA 2] Center 34 (4~65) winsize 62
5120 06:51:24.506170 [CA 3] Center 34 (4~65) winsize 62
5121 06:51:24.509788 [CA 4] Center 33 (3~64) winsize 62
5122 06:51:24.513392 [CA 5] Center 32 (2~63) winsize 62
5123 06:51:24.513944
5124 06:51:24.516045 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5125 06:51:24.516120
5126 06:51:24.519590 [CATrainingPosCal] consider 2 rank data
5127 06:51:24.522094 u2DelayCellTimex100 = 270/100 ps
5128 06:51:24.525589 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5129 06:51:24.531983 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5130 06:51:24.535218 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5131 06:51:24.539689 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5132 06:51:24.541861 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5133 06:51:24.545316 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5134 06:51:24.545400
5135 06:51:24.549283 CA PerBit enable=1, Macro0, CA PI delay=32
5136 06:51:24.549356
5137 06:51:24.552202 [CBTSetCACLKResult] CA Dly = 32
5138 06:51:24.555155 CS Dly: 6 (0~39)
5139 06:51:24.555234
5140 06:51:24.558331 ----->DramcWriteLeveling(PI) begin...
5141 06:51:24.558434 ==
5142 06:51:24.562037 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 06:51:24.564821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 06:51:24.564930 ==
5145 06:51:24.568481 Write leveling (Byte 0): 32 => 32
5146 06:51:24.571618 Write leveling (Byte 1): 26 => 26
5147 06:51:24.575414 DramcWriteLeveling(PI) end<-----
5148 06:51:24.575487
5149 06:51:24.575563 ==
5150 06:51:24.577955 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 06:51:24.581651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 06:51:24.581733 ==
5153 06:51:24.584567 [Gating] SW mode calibration
5154 06:51:24.591189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5155 06:51:24.598093 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5156 06:51:24.601225 0 14 0 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
5157 06:51:24.607794 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 06:51:24.610790 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 06:51:24.614073 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 06:51:24.621456 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 06:51:24.624024 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 06:51:24.627607 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5163 06:51:24.634253 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5164 06:51:24.637615 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5165 06:51:24.640843 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5166 06:51:24.647219 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 06:51:24.650794 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 06:51:24.653741 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 06:51:24.660584 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 06:51:24.663825 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
5171 06:51:24.667601 0 15 28 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
5172 06:51:24.673511 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5173 06:51:24.676896 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 06:51:24.680143 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 06:51:24.687059 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 06:51:24.690276 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 06:51:24.693702 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 06:51:24.700396 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 06:51:24.703787 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5180 06:51:24.706946 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5181 06:51:24.713046 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5182 06:51:24.717210 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 06:51:24.719931 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 06:51:24.726862 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 06:51:24.729791 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 06:51:24.732707 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 06:51:24.739263 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 06:51:24.743016 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 06:51:24.746675 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 06:51:24.753061 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 06:51:24.756014 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 06:51:24.759307 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 06:51:24.765840 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 06:51:24.769359 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 06:51:24.772506 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5196 06:51:24.779252 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5197 06:51:24.779382 Total UI for P1: 0, mck2ui 16
5198 06:51:24.785795 best dqsien dly found for B0: ( 1, 2, 28)
5199 06:51:24.788956 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5200 06:51:24.792254 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 06:51:24.795484 Total UI for P1: 0, mck2ui 16
5202 06:51:24.798981 best dqsien dly found for B1: ( 1, 3, 0)
5203 06:51:24.802024 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5204 06:51:24.805435 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5205 06:51:24.805516
5206 06:51:24.811635 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5207 06:51:24.814916 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5208 06:51:24.815030 [Gating] SW calibration Done
5209 06:51:24.818803 ==
5210 06:51:24.818884 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 06:51:24.824977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 06:51:24.825091 ==
5213 06:51:24.825185 RX Vref Scan: 0
5214 06:51:24.825277
5215 06:51:24.828315 RX Vref 0 -> 0, step: 1
5216 06:51:24.828396
5217 06:51:24.831786 RX Delay -80 -> 252, step: 8
5218 06:51:24.834792 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5219 06:51:24.838146 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5220 06:51:24.841394 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5221 06:51:24.847998 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5222 06:51:24.851287 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5223 06:51:24.854984 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5224 06:51:24.857983 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5225 06:51:24.861531 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5226 06:51:24.864552 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5227 06:51:24.871591 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5228 06:51:24.875644 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5229 06:51:24.877768 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5230 06:51:24.881246 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5231 06:51:24.884520 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5232 06:51:24.890924 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5233 06:51:24.894709 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5234 06:51:24.894817 ==
5235 06:51:24.897337 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 06:51:24.901067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 06:51:24.901149 ==
5238 06:51:24.901213 DQS Delay:
5239 06:51:24.904373 DQS0 = 0, DQS1 = 0
5240 06:51:24.904454 DQM Delay:
5241 06:51:24.907985 DQM0 = 99, DQM1 = 88
5242 06:51:24.908065 DQ Delay:
5243 06:51:24.910674 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5244 06:51:24.914390 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =103
5245 06:51:24.917432 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5246 06:51:24.920759 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91
5247 06:51:24.920840
5248 06:51:24.920904
5249 06:51:24.920964 ==
5250 06:51:24.924129 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 06:51:24.930685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 06:51:24.930772 ==
5253 06:51:24.930838
5254 06:51:24.930898
5255 06:51:24.930955 TX Vref Scan disable
5256 06:51:24.934674 == TX Byte 0 ==
5257 06:51:24.937612 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5258 06:51:24.944794 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5259 06:51:24.944877 == TX Byte 1 ==
5260 06:51:24.947476 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5261 06:51:24.953841 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5262 06:51:24.953923 ==
5263 06:51:24.957356 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 06:51:24.960247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 06:51:24.960329 ==
5266 06:51:24.960394
5267 06:51:24.960453
5268 06:51:24.963967 TX Vref Scan disable
5269 06:51:24.966882 == TX Byte 0 ==
5270 06:51:24.970378 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5271 06:51:24.973631 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5272 06:51:24.977084 == TX Byte 1 ==
5273 06:51:24.980178 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5274 06:51:24.983677 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5275 06:51:24.983758
5276 06:51:24.983823 [DATLAT]
5277 06:51:24.986751 Freq=933, CH0 RK0
5278 06:51:24.986832
5279 06:51:24.990318 DATLAT Default: 0xd
5280 06:51:24.990399 0, 0xFFFF, sum = 0
5281 06:51:24.993183 1, 0xFFFF, sum = 0
5282 06:51:24.993332 2, 0xFFFF, sum = 0
5283 06:51:24.996781 3, 0xFFFF, sum = 0
5284 06:51:24.996863 4, 0xFFFF, sum = 0
5285 06:51:25.000024 5, 0xFFFF, sum = 0
5286 06:51:25.000106 6, 0xFFFF, sum = 0
5287 06:51:25.003737 7, 0xFFFF, sum = 0
5288 06:51:25.003819 8, 0xFFFF, sum = 0
5289 06:51:25.007029 9, 0xFFFF, sum = 0
5290 06:51:25.007111 10, 0x0, sum = 1
5291 06:51:25.009779 11, 0x0, sum = 2
5292 06:51:25.009861 12, 0x0, sum = 3
5293 06:51:25.013441 13, 0x0, sum = 4
5294 06:51:25.013523 best_step = 11
5295 06:51:25.013588
5296 06:51:25.013649 ==
5297 06:51:25.016870 Dram Type= 6, Freq= 0, CH_0, rank 0
5298 06:51:25.020304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 06:51:25.022754 ==
5300 06:51:25.022835 RX Vref Scan: 1
5301 06:51:25.022899
5302 06:51:25.026326 RX Vref 0 -> 0, step: 1
5303 06:51:25.026407
5304 06:51:25.029881 RX Delay -61 -> 252, step: 4
5305 06:51:25.029963
5306 06:51:25.033008 Set Vref, RX VrefLevel [Byte0]: 57
5307 06:51:25.036168 [Byte1]: 44
5308 06:51:25.036249
5309 06:51:25.039959 Final RX Vref Byte 0 = 57 to rank0
5310 06:51:25.043114 Final RX Vref Byte 1 = 44 to rank0
5311 06:51:25.046477 Final RX Vref Byte 0 = 57 to rank1
5312 06:51:25.049136 Final RX Vref Byte 1 = 44 to rank1==
5313 06:51:25.052484 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 06:51:25.056219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 06:51:25.056301 ==
5316 06:51:25.059637 DQS Delay:
5317 06:51:25.059718 DQS0 = 0, DQS1 = 0
5318 06:51:25.059782 DQM Delay:
5319 06:51:25.062575 DQM0 = 99, DQM1 = 86
5320 06:51:25.062656 DQ Delay:
5321 06:51:25.065924 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =94
5322 06:51:25.069315 DQ4 =100, DQ5 =90, DQ6 =110, DQ7 =106
5323 06:51:25.072539 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =82
5324 06:51:25.075515 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5325 06:51:25.075595
5326 06:51:25.075659
5327 06:51:25.085622 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
5328 06:51:25.089077 CH0 RK0: MR19=505, MR18=1F19
5329 06:51:25.095964 CH0_RK0: MR19=0x505, MR18=0x1F19, DQSOSC=412, MR23=63, INC=63, DEC=42
5330 06:51:25.096045
5331 06:51:25.098650 ----->DramcWriteLeveling(PI) begin...
5332 06:51:25.098733 ==
5333 06:51:25.102025 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 06:51:25.105694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 06:51:25.105776 ==
5336 06:51:25.109097 Write leveling (Byte 0): 32 => 32
5337 06:51:25.112428 Write leveling (Byte 1): 28 => 28
5338 06:51:25.115545 DramcWriteLeveling(PI) end<-----
5339 06:51:25.115627
5340 06:51:25.115691 ==
5341 06:51:25.118578 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 06:51:25.121874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 06:51:25.121955 ==
5344 06:51:25.125276 [Gating] SW mode calibration
5345 06:51:25.131548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5346 06:51:25.138425 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5347 06:51:25.141710 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5348 06:51:25.145340 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 06:51:25.151625 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 06:51:25.155070 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 06:51:25.158183 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 06:51:25.164555 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 06:51:25.167928 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5354 06:51:25.171281 0 14 28 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
5355 06:51:25.178113 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5356 06:51:25.181800 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 06:51:25.184778 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 06:51:25.191471 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 06:51:25.194612 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 06:51:25.197986 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 06:51:25.204398 0 15 24 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
5362 06:51:25.207882 0 15 28 | B1->B0 | 2424 4242 | 1 0 | (0 0) (0 0)
5363 06:51:25.210880 1 0 0 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
5364 06:51:25.217935 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 06:51:25.221240 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 06:51:25.224428 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 06:51:25.230903 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 06:51:25.233956 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 06:51:25.237263 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5370 06:51:25.244290 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5371 06:51:25.247289 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5372 06:51:25.250588 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 06:51:25.257484 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 06:51:25.260589 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 06:51:25.264484 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 06:51:25.271146 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 06:51:25.273687 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 06:51:25.276818 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 06:51:25.283865 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 06:51:25.286807 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 06:51:25.290261 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 06:51:25.297147 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 06:51:25.300196 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 06:51:25.303604 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 06:51:25.310185 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5386 06:51:25.313008 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5387 06:51:25.316681 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5388 06:51:25.319702 Total UI for P1: 0, mck2ui 16
5389 06:51:25.323144 best dqsien dly found for B0: ( 1, 2, 26)
5390 06:51:25.330003 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 06:51:25.330088 Total UI for P1: 0, mck2ui 16
5392 06:51:25.336362 best dqsien dly found for B1: ( 1, 3, 0)
5393 06:51:25.339775 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5394 06:51:25.342696 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5395 06:51:25.342777
5396 06:51:25.346617 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5397 06:51:25.349663 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5398 06:51:25.352725 [Gating] SW calibration Done
5399 06:51:25.352805 ==
5400 06:51:25.355811 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 06:51:25.359707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 06:51:25.359789 ==
5403 06:51:25.362578 RX Vref Scan: 0
5404 06:51:25.362657
5405 06:51:25.362721 RX Vref 0 -> 0, step: 1
5406 06:51:25.362780
5407 06:51:25.365661 RX Delay -80 -> 252, step: 8
5408 06:51:25.372800 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5409 06:51:25.375530 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5410 06:51:25.378886 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5411 06:51:25.382426 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5412 06:51:25.386077 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5413 06:51:25.388821 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5414 06:51:25.395357 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5415 06:51:25.398615 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5416 06:51:25.401835 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5417 06:51:25.405460 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5418 06:51:25.408701 iDelay=208, Bit 10, Center 87 (0 ~ 175) 176
5419 06:51:25.415115 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5420 06:51:25.418550 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5421 06:51:25.422041 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5422 06:51:25.424975 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5423 06:51:25.428257 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5424 06:51:25.428338 ==
5425 06:51:25.431616 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 06:51:25.438107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 06:51:25.438189 ==
5428 06:51:25.438297 DQS Delay:
5429 06:51:25.438357 DQS0 = 0, DQS1 = 0
5430 06:51:25.441758 DQM Delay:
5431 06:51:25.441839 DQM0 = 97, DQM1 = 88
5432 06:51:25.444914 DQ Delay:
5433 06:51:25.448274 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5434 06:51:25.451195 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5435 06:51:25.455097 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5436 06:51:25.458063 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5437 06:51:25.458144
5438 06:51:25.458208
5439 06:51:25.458268 ==
5440 06:51:25.461147 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 06:51:25.464858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 06:51:25.464939 ==
5443 06:51:25.465004
5444 06:51:25.465064
5445 06:51:25.467742 TX Vref Scan disable
5446 06:51:25.467824 == TX Byte 0 ==
5447 06:51:25.474398 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5448 06:51:25.477989 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5449 06:51:25.481237 == TX Byte 1 ==
5450 06:51:25.484694 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5451 06:51:25.488406 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5452 06:51:25.488488 ==
5453 06:51:25.491326 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 06:51:25.494538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 06:51:25.494620 ==
5456 06:51:25.497766
5457 06:51:25.497846
5458 06:51:25.497910 TX Vref Scan disable
5459 06:51:25.500986 == TX Byte 0 ==
5460 06:51:25.504223 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5461 06:51:25.511004 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5462 06:51:25.511086 == TX Byte 1 ==
5463 06:51:25.514524 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5464 06:51:25.520500 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5465 06:51:25.520582
5466 06:51:25.520646 [DATLAT]
5467 06:51:25.520706 Freq=933, CH0 RK1
5468 06:51:25.520764
5469 06:51:25.523976 DATLAT Default: 0xb
5470 06:51:25.527184 0, 0xFFFF, sum = 0
5471 06:51:25.527267 1, 0xFFFF, sum = 0
5472 06:51:25.531144 2, 0xFFFF, sum = 0
5473 06:51:25.531225 3, 0xFFFF, sum = 0
5474 06:51:25.534001 4, 0xFFFF, sum = 0
5475 06:51:25.534083 5, 0xFFFF, sum = 0
5476 06:51:25.537299 6, 0xFFFF, sum = 0
5477 06:51:25.537381 7, 0xFFFF, sum = 0
5478 06:51:25.540455 8, 0xFFFF, sum = 0
5479 06:51:25.540537 9, 0xFFFF, sum = 0
5480 06:51:25.543517 10, 0x0, sum = 1
5481 06:51:25.543599 11, 0x0, sum = 2
5482 06:51:25.547240 12, 0x0, sum = 3
5483 06:51:25.547323 13, 0x0, sum = 4
5484 06:51:25.550241 best_step = 11
5485 06:51:25.550322
5486 06:51:25.550385 ==
5487 06:51:25.553556 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 06:51:25.556536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 06:51:25.556618 ==
5490 06:51:25.560146 RX Vref Scan: 0
5491 06:51:25.560227
5492 06:51:25.560290 RX Vref 0 -> 0, step: 1
5493 06:51:25.560384
5494 06:51:25.563318 RX Delay -61 -> 252, step: 4
5495 06:51:25.570095 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5496 06:51:25.573180 iDelay=199, Bit 1, Center 100 (11 ~ 190) 180
5497 06:51:25.577211 iDelay=199, Bit 2, Center 92 (3 ~ 182) 180
5498 06:51:25.579954 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5499 06:51:25.583268 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5500 06:51:25.590000 iDelay=199, Bit 5, Center 88 (-1 ~ 178) 180
5501 06:51:25.593137 iDelay=199, Bit 6, Center 108 (19 ~ 198) 180
5502 06:51:25.596450 iDelay=199, Bit 7, Center 106 (19 ~ 194) 176
5503 06:51:25.600112 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5504 06:51:25.602807 iDelay=199, Bit 9, Center 74 (-13 ~ 162) 176
5505 06:51:25.609910 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5506 06:51:25.612717 iDelay=199, Bit 11, Center 82 (-5 ~ 170) 176
5507 06:51:25.615908 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5508 06:51:25.619590 iDelay=199, Bit 13, Center 92 (7 ~ 178) 172
5509 06:51:25.622706 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5510 06:51:25.626442 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5511 06:51:25.630184 ==
5512 06:51:25.632702 Dram Type= 6, Freq= 0, CH_0, rank 1
5513 06:51:25.635726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 06:51:25.635809 ==
5515 06:51:25.635873 DQS Delay:
5516 06:51:25.639300 DQS0 = 0, DQS1 = 0
5517 06:51:25.639420 DQM Delay:
5518 06:51:25.642329 DQM0 = 98, DQM1 = 87
5519 06:51:25.642410 DQ Delay:
5520 06:51:25.646056 DQ0 =96, DQ1 =100, DQ2 =92, DQ3 =94
5521 06:51:25.648917 DQ4 =100, DQ5 =88, DQ6 =108, DQ7 =106
5522 06:51:25.652400 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5523 06:51:25.655626 DQ12 =90, DQ13 =92, DQ14 =98, DQ15 =94
5524 06:51:25.655707
5525 06:51:25.655771
5526 06:51:25.665360 [DQSOSCAuto] RK1, (LSB)MR18= 0x1917, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5527 06:51:25.665442 CH0 RK1: MR19=505, MR18=1917
5528 06:51:25.671967 CH0_RK1: MR19=0x505, MR18=0x1917, DQSOSC=413, MR23=63, INC=63, DEC=42
5529 06:51:25.675255 [RxdqsGatingPostProcess] freq 933
5530 06:51:25.681811 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5531 06:51:25.685409 best DQS0 dly(2T, 0.5T) = (0, 10)
5532 06:51:25.688571 best DQS1 dly(2T, 0.5T) = (0, 11)
5533 06:51:25.691736 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5534 06:51:25.695235 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5535 06:51:25.698688 best DQS0 dly(2T, 0.5T) = (0, 10)
5536 06:51:25.698769 best DQS1 dly(2T, 0.5T) = (0, 11)
5537 06:51:25.702000 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5538 06:51:25.704783 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5539 06:51:25.708417 Pre-setting of DQS Precalculation
5540 06:51:25.714885 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5541 06:51:25.714966 ==
5542 06:51:25.718993 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 06:51:25.721143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 06:51:25.721225 ==
5545 06:51:25.727775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5546 06:51:25.734568 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5547 06:51:25.737773 [CA 0] Center 36 (6~67) winsize 62
5548 06:51:25.741531 [CA 1] Center 36 (6~67) winsize 62
5549 06:51:25.744949 [CA 2] Center 34 (4~65) winsize 62
5550 06:51:25.747810 [CA 3] Center 33 (3~64) winsize 62
5551 06:51:25.751485 [CA 4] Center 34 (3~65) winsize 63
5552 06:51:25.754622 [CA 5] Center 33 (3~64) winsize 62
5553 06:51:25.754703
5554 06:51:25.757639 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5555 06:51:25.757719
5556 06:51:25.760758 [CATrainingPosCal] consider 1 rank data
5557 06:51:25.764108 u2DelayCellTimex100 = 270/100 ps
5558 06:51:25.767428 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5559 06:51:25.770767 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 06:51:25.774053 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5561 06:51:25.777467 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5562 06:51:25.780478 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5563 06:51:25.787631 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 06:51:25.787712
5565 06:51:25.790688 CA PerBit enable=1, Macro0, CA PI delay=33
5566 06:51:25.790769
5567 06:51:25.793695 [CBTSetCACLKResult] CA Dly = 33
5568 06:51:25.793781 CS Dly: 5 (0~36)
5569 06:51:25.793869 ==
5570 06:51:25.797350 Dram Type= 6, Freq= 0, CH_1, rank 1
5571 06:51:25.800297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 06:51:25.803843 ==
5573 06:51:25.807103 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5574 06:51:25.813969 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5575 06:51:25.816802 [CA 0] Center 36 (6~67) winsize 62
5576 06:51:25.820474 [CA 1] Center 36 (6~67) winsize 62
5577 06:51:25.823856 [CA 2] Center 34 (4~64) winsize 61
5578 06:51:25.827096 [CA 3] Center 33 (3~64) winsize 62
5579 06:51:25.830302 [CA 4] Center 34 (4~64) winsize 61
5580 06:51:25.833586 [CA 5] Center 33 (3~64) winsize 62
5581 06:51:25.833679
5582 06:51:25.837273 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5583 06:51:25.837374
5584 06:51:25.840164 [CATrainingPosCal] consider 2 rank data
5585 06:51:25.843237 u2DelayCellTimex100 = 270/100 ps
5586 06:51:25.847066 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5587 06:51:25.850010 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5588 06:51:25.853406 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5589 06:51:25.859607 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5590 06:51:25.863347 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5591 06:51:25.866499 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5592 06:51:25.866676
5593 06:51:25.870036 CA PerBit enable=1, Macro0, CA PI delay=33
5594 06:51:25.870234
5595 06:51:25.873138 [CBTSetCACLKResult] CA Dly = 33
5596 06:51:25.873375 CS Dly: 6 (0~38)
5597 06:51:25.873582
5598 06:51:25.876238 ----->DramcWriteLeveling(PI) begin...
5599 06:51:25.880115 ==
5600 06:51:25.883111 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 06:51:25.886272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 06:51:25.886672 ==
5603 06:51:25.889500 Write leveling (Byte 0): 24 => 24
5604 06:51:25.893246 Write leveling (Byte 1): 30 => 30
5605 06:51:25.896297 DramcWriteLeveling(PI) end<-----
5606 06:51:25.896715
5607 06:51:25.897107 ==
5608 06:51:25.899815 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 06:51:25.902912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 06:51:25.903269 ==
5611 06:51:25.906191 [Gating] SW mode calibration
5612 06:51:25.912598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5613 06:51:25.919632 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5614 06:51:25.922506 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 06:51:25.925864 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 06:51:25.932489 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 06:51:25.935988 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 06:51:25.939662 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 06:51:25.945814 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 06:51:25.949651 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5621 06:51:25.953025 0 14 28 | B1->B0 | 2d2d 2a2a | 0 0 | (0 0) (1 0)
5622 06:51:25.959450 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 06:51:25.962666 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 06:51:25.966162 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 06:51:25.972091 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 06:51:25.975583 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 06:51:25.979408 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 06:51:25.985369 0 15 24 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
5629 06:51:25.988637 0 15 28 | B1->B0 | 3434 3c3c | 0 0 | (0 0) (0 0)
5630 06:51:25.991834 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 06:51:25.998975 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 06:51:26.002360 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 06:51:26.005329 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 06:51:26.011660 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 06:51:26.015134 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 06:51:26.018203 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5637 06:51:26.024923 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5638 06:51:26.028072 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 06:51:26.031735 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 06:51:26.038328 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 06:51:26.041382 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 06:51:26.044896 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 06:51:26.051336 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 06:51:26.054919 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 06:51:26.058187 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 06:51:26.065073 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 06:51:26.067688 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 06:51:26.070882 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 06:51:26.077540 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 06:51:26.081300 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 06:51:26.084630 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 06:51:26.091041 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5653 06:51:26.094403 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 06:51:26.097848 Total UI for P1: 0, mck2ui 16
5655 06:51:26.101081 best dqsien dly found for B0: ( 1, 2, 24)
5656 06:51:26.103886 Total UI for P1: 0, mck2ui 16
5657 06:51:26.107233 best dqsien dly found for B1: ( 1, 2, 26)
5658 06:51:26.110692 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5659 06:51:26.113633 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5660 06:51:26.114051
5661 06:51:26.117201 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5662 06:51:26.120561 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5663 06:51:26.123529 [Gating] SW calibration Done
5664 06:51:26.123949 ==
5665 06:51:26.126921 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 06:51:26.133265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 06:51:26.133685 ==
5668 06:51:26.134016 RX Vref Scan: 0
5669 06:51:26.134321
5670 06:51:26.136945 RX Vref 0 -> 0, step: 1
5671 06:51:26.137363
5672 06:51:26.139815 RX Delay -80 -> 252, step: 8
5673 06:51:26.143258 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5674 06:51:26.146971 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5675 06:51:26.149890 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5676 06:51:26.153204 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5677 06:51:26.159969 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5678 06:51:26.162950 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5679 06:51:26.166589 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5680 06:51:26.169781 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5681 06:51:26.172872 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5682 06:51:26.175927 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5683 06:51:26.182780 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5684 06:51:26.186156 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5685 06:51:26.189567 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5686 06:51:26.192679 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5687 06:51:26.196193 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5688 06:51:26.202336 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5689 06:51:26.202876 ==
5690 06:51:26.205674 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 06:51:26.209385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 06:51:26.209852 ==
5693 06:51:26.210211 DQS Delay:
5694 06:51:26.212625 DQS0 = 0, DQS1 = 0
5695 06:51:26.213132 DQM Delay:
5696 06:51:26.215882 DQM0 = 99, DQM1 = 96
5697 06:51:26.216379 DQ Delay:
5698 06:51:26.218979 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5699 06:51:26.222022 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5700 06:51:26.225705 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5701 06:51:26.229384 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5702 06:51:26.229901
5703 06:51:26.230297
5704 06:51:26.230801 ==
5705 06:51:26.232413 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 06:51:26.238991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 06:51:26.239481 ==
5708 06:51:26.239824
5709 06:51:26.240159
5710 06:51:26.240466 TX Vref Scan disable
5711 06:51:26.242485 == TX Byte 0 ==
5712 06:51:26.245409 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5713 06:51:26.252136 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5714 06:51:26.252552 == TX Byte 1 ==
5715 06:51:26.255587 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5716 06:51:26.262110 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5717 06:51:26.262725 ==
5718 06:51:26.265690 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 06:51:26.268710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 06:51:26.269217 ==
5721 06:51:26.269620
5722 06:51:26.270218
5723 06:51:26.272445 TX Vref Scan disable
5724 06:51:26.272888 == TX Byte 0 ==
5725 06:51:26.278866 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5726 06:51:26.281887 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5727 06:51:26.285323 == TX Byte 1 ==
5728 06:51:26.288489 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5729 06:51:26.292223 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5730 06:51:26.292747
5731 06:51:26.293132 [DATLAT]
5732 06:51:26.295696 Freq=933, CH1 RK0
5733 06:51:26.296148
5734 06:51:26.298403 DATLAT Default: 0xd
5735 06:51:26.298818 0, 0xFFFF, sum = 0
5736 06:51:26.301938 1, 0xFFFF, sum = 0
5737 06:51:26.302362 2, 0xFFFF, sum = 0
5738 06:51:26.305211 3, 0xFFFF, sum = 0
5739 06:51:26.305672 4, 0xFFFF, sum = 0
5740 06:51:26.308343 5, 0xFFFF, sum = 0
5741 06:51:26.308810 6, 0xFFFF, sum = 0
5742 06:51:26.311526 7, 0xFFFF, sum = 0
5743 06:51:26.311942 8, 0xFFFF, sum = 0
5744 06:51:26.315263 9, 0xFFFF, sum = 0
5745 06:51:26.315771 10, 0x0, sum = 1
5746 06:51:26.318175 11, 0x0, sum = 2
5747 06:51:26.318608 12, 0x0, sum = 3
5748 06:51:26.321646 13, 0x0, sum = 4
5749 06:51:26.322090 best_step = 11
5750 06:51:26.322418
5751 06:51:26.322735 ==
5752 06:51:26.325053 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 06:51:26.328079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 06:51:26.331358 ==
5755 06:51:26.331894 RX Vref Scan: 1
5756 06:51:26.332270
5757 06:51:26.334696 RX Vref 0 -> 0, step: 1
5758 06:51:26.335163
5759 06:51:26.338086 RX Delay -53 -> 252, step: 4
5760 06:51:26.338498
5761 06:51:26.340978 Set Vref, RX VrefLevel [Byte0]: 50
5762 06:51:26.345061 [Byte1]: 53
5763 06:51:26.345574
5764 06:51:26.347857 Final RX Vref Byte 0 = 50 to rank0
5765 06:51:26.351438 Final RX Vref Byte 1 = 53 to rank0
5766 06:51:26.354494 Final RX Vref Byte 0 = 50 to rank1
5767 06:51:26.358018 Final RX Vref Byte 1 = 53 to rank1==
5768 06:51:26.360855 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 06:51:26.364244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 06:51:26.364727 ==
5771 06:51:26.367638 DQS Delay:
5772 06:51:26.368069 DQS0 = 0, DQS1 = 0
5773 06:51:26.368402 DQM Delay:
5774 06:51:26.371580 DQM0 = 98, DQM1 = 94
5775 06:51:26.371994 DQ Delay:
5776 06:51:26.374644 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =100
5777 06:51:26.377842 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5778 06:51:26.381220 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =88
5779 06:51:26.384444 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5780 06:51:26.384985
5781 06:51:26.385330
5782 06:51:26.393853 [DQSOSCAuto] RK0, (LSB)MR18= 0xa19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5783 06:51:26.397768 CH1 RK0: MR19=505, MR18=A19
5784 06:51:26.400633 CH1_RK0: MR19=0x505, MR18=0xA19, DQSOSC=413, MR23=63, INC=63, DEC=42
5785 06:51:26.404310
5786 06:51:26.407440 ----->DramcWriteLeveling(PI) begin...
5787 06:51:26.407873 ==
5788 06:51:26.410673 Dram Type= 6, Freq= 0, CH_1, rank 1
5789 06:51:26.414013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 06:51:26.414440 ==
5791 06:51:26.417277 Write leveling (Byte 0): 26 => 26
5792 06:51:26.420472 Write leveling (Byte 1): 27 => 27
5793 06:51:26.423730 DramcWriteLeveling(PI) end<-----
5794 06:51:26.424152
5795 06:51:26.424481 ==
5796 06:51:26.427525 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 06:51:26.430706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 06:51:26.431128 ==
5799 06:51:26.434101 [Gating] SW mode calibration
5800 06:51:26.440914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5801 06:51:26.447053 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5802 06:51:26.450593 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 06:51:26.453765 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 06:51:26.460567 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 06:51:26.463461 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 06:51:26.466699 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 06:51:26.473474 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 06:51:26.477192 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
5809 06:51:26.480348 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5810 06:51:26.486572 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5811 06:51:26.489557 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 06:51:26.493299 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 06:51:26.500199 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 06:51:26.502741 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 06:51:26.506435 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 06:51:26.513207 0 15 24 | B1->B0 | 2929 3535 | 0 1 | (0 0) (0 0)
5817 06:51:26.516545 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5818 06:51:26.519317 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 06:51:26.525905 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 06:51:26.529444 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 06:51:26.532615 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 06:51:26.538831 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 06:51:26.542349 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 06:51:26.545872 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5825 06:51:26.552308 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5826 06:51:26.555641 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5827 06:51:26.559468 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 06:51:26.565369 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 06:51:26.568552 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 06:51:26.572246 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 06:51:26.578385 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 06:51:26.581822 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 06:51:26.585379 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 06:51:26.591710 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 06:51:26.594995 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 06:51:26.598140 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 06:51:26.604771 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 06:51:26.607585 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 06:51:26.610970 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 06:51:26.617725 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5841 06:51:26.620976 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 06:51:26.624373 Total UI for P1: 0, mck2ui 16
5843 06:51:26.627635 best dqsien dly found for B0: ( 1, 2, 24)
5844 06:51:26.630911 Total UI for P1: 0, mck2ui 16
5845 06:51:26.634354 best dqsien dly found for B1: ( 1, 2, 26)
5846 06:51:26.637350 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5847 06:51:26.641006 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5848 06:51:26.641088
5849 06:51:26.644247 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5850 06:51:26.647499 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5851 06:51:26.650693 [Gating] SW calibration Done
5852 06:51:26.650774 ==
5853 06:51:26.654508 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 06:51:26.660476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 06:51:26.660564 ==
5856 06:51:26.660634 RX Vref Scan: 0
5857 06:51:26.660698
5858 06:51:26.663975 RX Vref 0 -> 0, step: 1
5859 06:51:26.664084
5860 06:51:26.667282 RX Delay -80 -> 252, step: 8
5861 06:51:26.670550 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5862 06:51:26.673857 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5863 06:51:26.677736 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5864 06:51:26.680928 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5865 06:51:26.687084 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5866 06:51:26.690453 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5867 06:51:26.694295 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5868 06:51:26.697065 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5869 06:51:26.700944 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5870 06:51:26.703590 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5871 06:51:26.710688 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5872 06:51:26.714123 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5873 06:51:26.717265 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5874 06:51:26.720136 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5875 06:51:26.723416 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5876 06:51:26.730146 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5877 06:51:26.730300 ==
5878 06:51:26.733183 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 06:51:26.736859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 06:51:26.737033 ==
5881 06:51:26.737172 DQS Delay:
5882 06:51:26.740186 DQS0 = 0, DQS1 = 0
5883 06:51:26.740391 DQM Delay:
5884 06:51:26.743221 DQM0 = 97, DQM1 = 94
5885 06:51:26.743483 DQ Delay:
5886 06:51:26.746825 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5887 06:51:26.750639 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5888 06:51:26.753352 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5889 06:51:26.756626 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5890 06:51:26.757021
5891 06:51:26.757324
5892 06:51:26.757609 ==
5893 06:51:26.760127 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 06:51:26.766766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 06:51:26.767189 ==
5896 06:51:26.767576
5897 06:51:26.767894
5898 06:51:26.768236 TX Vref Scan disable
5899 06:51:26.769714 == TX Byte 0 ==
5900 06:51:26.773056 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5901 06:51:26.779923 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5902 06:51:26.780346 == TX Byte 1 ==
5903 06:51:26.782644 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5904 06:51:26.789447 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5905 06:51:26.789882 ==
5906 06:51:26.792819 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 06:51:26.795923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 06:51:26.796349 ==
5909 06:51:26.796683
5910 06:51:26.796992
5911 06:51:26.799339 TX Vref Scan disable
5912 06:51:26.802485 == TX Byte 0 ==
5913 06:51:26.806328 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5914 06:51:26.809163 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5915 06:51:26.812523 == TX Byte 1 ==
5916 06:51:26.815665 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5917 06:51:26.819122 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5918 06:51:26.819575
5919 06:51:26.819910 [DATLAT]
5920 06:51:26.822400 Freq=933, CH1 RK1
5921 06:51:26.822820
5922 06:51:26.825546 DATLAT Default: 0xb
5923 06:51:26.825970 0, 0xFFFF, sum = 0
5924 06:51:26.828724 1, 0xFFFF, sum = 0
5925 06:51:26.829151 2, 0xFFFF, sum = 0
5926 06:51:26.831823 3, 0xFFFF, sum = 0
5927 06:51:26.832292 4, 0xFFFF, sum = 0
5928 06:51:26.835309 5, 0xFFFF, sum = 0
5929 06:51:26.835784 6, 0xFFFF, sum = 0
5930 06:51:26.838890 7, 0xFFFF, sum = 0
5931 06:51:26.839314 8, 0xFFFF, sum = 0
5932 06:51:26.842025 9, 0xFFFF, sum = 0
5933 06:51:26.842449 10, 0x0, sum = 1
5934 06:51:26.845721 11, 0x0, sum = 2
5935 06:51:26.846145 12, 0x0, sum = 3
5936 06:51:26.848551 13, 0x0, sum = 4
5937 06:51:26.848978 best_step = 11
5938 06:51:26.849313
5939 06:51:26.849623 ==
5940 06:51:26.851738 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 06:51:26.854993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 06:51:26.858494 ==
5943 06:51:26.858912 RX Vref Scan: 0
5944 06:51:26.859248
5945 06:51:26.861889 RX Vref 0 -> 0, step: 1
5946 06:51:26.862307
5947 06:51:26.865314 RX Delay -53 -> 252, step: 4
5948 06:51:26.868746 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5949 06:51:26.871671 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5950 06:51:26.878356 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5951 06:51:26.881807 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5952 06:51:26.884575 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5953 06:51:26.888050 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5954 06:51:26.891137 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5955 06:51:26.898198 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5956 06:51:26.901101 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5957 06:51:26.904772 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5958 06:51:26.907431 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5959 06:51:26.910813 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5960 06:51:26.917443 iDelay=199, Bit 12, Center 102 (11 ~ 194) 184
5961 06:51:26.920747 iDelay=199, Bit 13, Center 100 (7 ~ 194) 188
5962 06:51:26.924317 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5963 06:51:26.928004 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5964 06:51:26.928436 ==
5965 06:51:26.930777 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 06:51:26.933824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 06:51:26.937364 ==
5968 06:51:26.937785 DQS Delay:
5969 06:51:26.938119 DQS0 = 0, DQS1 = 0
5970 06:51:26.940395 DQM Delay:
5971 06:51:26.940816 DQM0 = 96, DQM1 = 92
5972 06:51:26.943957 DQ Delay:
5973 06:51:26.946953 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5974 06:51:26.950514 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =92
5975 06:51:26.953703 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5976 06:51:26.956884 DQ12 =102, DQ13 =100, DQ14 =96, DQ15 =102
5977 06:51:26.957372
5978 06:51:26.957833
5979 06:51:26.963671 [DQSOSCAuto] RK1, (LSB)MR18= 0xa21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5980 06:51:26.966907 CH1 RK1: MR19=505, MR18=A21
5981 06:51:26.973429 CH1_RK1: MR19=0x505, MR18=0xA21, DQSOSC=411, MR23=63, INC=64, DEC=42
5982 06:51:26.976335 [RxdqsGatingPostProcess] freq 933
5983 06:51:26.979651 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5984 06:51:26.982765 best DQS0 dly(2T, 0.5T) = (0, 10)
5985 06:51:26.986772 best DQS1 dly(2T, 0.5T) = (0, 10)
5986 06:51:26.989798 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5987 06:51:26.992791 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5988 06:51:26.996169 best DQS0 dly(2T, 0.5T) = (0, 10)
5989 06:51:26.999480 best DQS1 dly(2T, 0.5T) = (0, 10)
5990 06:51:27.002958 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5991 06:51:27.006651 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5992 06:51:27.009494 Pre-setting of DQS Precalculation
5993 06:51:27.012717 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5994 06:51:27.023200 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5995 06:51:27.029562 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5996 06:51:27.029823
5997 06:51:27.029989
5998 06:51:27.032616 [Calibration Summary] 1866 Mbps
5999 06:51:27.032797 CH 0, Rank 0
6000 06:51:27.036153 SW Impedance : PASS
6001 06:51:27.036353 DUTY Scan : NO K
6002 06:51:27.039410 ZQ Calibration : PASS
6003 06:51:27.042728 Jitter Meter : NO K
6004 06:51:27.043064 CBT Training : PASS
6005 06:51:27.046107 Write leveling : PASS
6006 06:51:27.049450 RX DQS gating : PASS
6007 06:51:27.049751 RX DQ/DQS(RDDQC) : PASS
6008 06:51:27.052713 TX DQ/DQS : PASS
6009 06:51:27.056578 RX DATLAT : PASS
6010 06:51:27.056997 RX DQ/DQS(Engine): PASS
6011 06:51:27.059785 TX OE : NO K
6012 06:51:27.060205 All Pass.
6013 06:51:27.060537
6014 06:51:27.062419 CH 0, Rank 1
6015 06:51:27.062876 SW Impedance : PASS
6016 06:51:27.065924 DUTY Scan : NO K
6017 06:51:27.069064 ZQ Calibration : PASS
6018 06:51:27.069507 Jitter Meter : NO K
6019 06:51:27.072409 CBT Training : PASS
6020 06:51:27.075680 Write leveling : PASS
6021 06:51:27.076101 RX DQS gating : PASS
6022 06:51:27.079295 RX DQ/DQS(RDDQC) : PASS
6023 06:51:27.082708 TX DQ/DQS : PASS
6024 06:51:27.083131 RX DATLAT : PASS
6025 06:51:27.085467 RX DQ/DQS(Engine): PASS
6026 06:51:27.089108 TX OE : NO K
6027 06:51:27.089529 All Pass.
6028 06:51:27.089863
6029 06:51:27.090173 CH 1, Rank 0
6030 06:51:27.092614 SW Impedance : PASS
6031 06:51:27.095632 DUTY Scan : NO K
6032 06:51:27.096052 ZQ Calibration : PASS
6033 06:51:27.099084 Jitter Meter : NO K
6034 06:51:27.099533 CBT Training : PASS
6035 06:51:27.102147 Write leveling : PASS
6036 06:51:27.105718 RX DQS gating : PASS
6037 06:51:27.106142 RX DQ/DQS(RDDQC) : PASS
6038 06:51:27.108934 TX DQ/DQS : PASS
6039 06:51:27.112154 RX DATLAT : PASS
6040 06:51:27.112574 RX DQ/DQS(Engine): PASS
6041 06:51:27.115491 TX OE : NO K
6042 06:51:27.115916 All Pass.
6043 06:51:27.116250
6044 06:51:27.118755 CH 1, Rank 1
6045 06:51:27.119172 SW Impedance : PASS
6046 06:51:27.122136 DUTY Scan : NO K
6047 06:51:27.125591 ZQ Calibration : PASS
6048 06:51:27.126013 Jitter Meter : NO K
6049 06:51:27.128518 CBT Training : PASS
6050 06:51:27.131834 Write leveling : PASS
6051 06:51:27.132254 RX DQS gating : PASS
6052 06:51:27.135704 RX DQ/DQS(RDDQC) : PASS
6053 06:51:27.139096 TX DQ/DQS : PASS
6054 06:51:27.139684 RX DATLAT : PASS
6055 06:51:27.141573 RX DQ/DQS(Engine): PASS
6056 06:51:27.144891 TX OE : NO K
6057 06:51:27.145316 All Pass.
6058 06:51:27.145651
6059 06:51:27.148479 DramC Write-DBI off
6060 06:51:27.148898 PER_BANK_REFRESH: Hybrid Mode
6061 06:51:27.151483 TX_TRACKING: ON
6062 06:51:27.161990 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6063 06:51:27.164273 [FAST_K] Save calibration result to emmc
6064 06:51:27.168086 dramc_set_vcore_voltage set vcore to 650000
6065 06:51:27.168507 Read voltage for 400, 6
6066 06:51:27.171643 Vio18 = 0
6067 06:51:27.172067 Vcore = 650000
6068 06:51:27.172431 Vdram = 0
6069 06:51:27.174252 Vddq = 0
6070 06:51:27.174759 Vmddr = 0
6071 06:51:27.180859 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6072 06:51:27.184619 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6073 06:51:27.187691 MEM_TYPE=3, freq_sel=20
6074 06:51:27.191067 sv_algorithm_assistance_LP4_800
6075 06:51:27.194373 ============ PULL DRAM RESETB DOWN ============
6076 06:51:27.197165 ========== PULL DRAM RESETB DOWN end =========
6077 06:51:27.204010 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6078 06:51:27.207496 ===================================
6079 06:51:27.207922 LPDDR4 DRAM CONFIGURATION
6080 06:51:27.210341 ===================================
6081 06:51:27.213620 EX_ROW_EN[0] = 0x0
6082 06:51:27.216928 EX_ROW_EN[1] = 0x0
6083 06:51:27.217345 LP4Y_EN = 0x0
6084 06:51:27.220549 WORK_FSP = 0x0
6085 06:51:27.220966 WL = 0x2
6086 06:51:27.223461 RL = 0x2
6087 06:51:27.223543 BL = 0x2
6088 06:51:27.226668 RPST = 0x0
6089 06:51:27.226749 RD_PRE = 0x0
6090 06:51:27.230907 WR_PRE = 0x1
6091 06:51:27.230988 WR_PST = 0x0
6092 06:51:27.233053 DBI_WR = 0x0
6093 06:51:27.233134 DBI_RD = 0x0
6094 06:51:27.236320 OTF = 0x1
6095 06:51:27.239667 ===================================
6096 06:51:27.242841 ===================================
6097 06:51:27.242923 ANA top config
6098 06:51:27.246292 ===================================
6099 06:51:27.249406 DLL_ASYNC_EN = 0
6100 06:51:27.253188 ALL_SLAVE_EN = 1
6101 06:51:27.256528 NEW_RANK_MODE = 1
6102 06:51:27.256624 DLL_IDLE_MODE = 1
6103 06:51:27.259726 LP45_APHY_COMB_EN = 1
6104 06:51:27.263017 TX_ODT_DIS = 1
6105 06:51:27.266450 NEW_8X_MODE = 1
6106 06:51:27.269625 ===================================
6107 06:51:27.272768 ===================================
6108 06:51:27.276462 data_rate = 800
6109 06:51:27.280109 CKR = 1
6110 06:51:27.280244 DQ_P2S_RATIO = 4
6111 06:51:27.282749 ===================================
6112 06:51:27.286111 CA_P2S_RATIO = 4
6113 06:51:27.289104 DQ_CA_OPEN = 0
6114 06:51:27.292541 DQ_SEMI_OPEN = 1
6115 06:51:27.295867 CA_SEMI_OPEN = 1
6116 06:51:27.299217 CA_FULL_RATE = 0
6117 06:51:27.299470 DQ_CKDIV4_EN = 0
6118 06:51:27.302698 CA_CKDIV4_EN = 1
6119 06:51:27.305908 CA_PREDIV_EN = 0
6120 06:51:27.309460 PH8_DLY = 0
6121 06:51:27.312525 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6122 06:51:27.315735 DQ_AAMCK_DIV = 0
6123 06:51:27.316175 CA_AAMCK_DIV = 0
6124 06:51:27.319087 CA_ADMCK_DIV = 4
6125 06:51:27.322680 DQ_TRACK_CA_EN = 0
6126 06:51:27.325870 CA_PICK = 800
6127 06:51:27.329439 CA_MCKIO = 400
6128 06:51:27.332397 MCKIO_SEMI = 400
6129 06:51:27.335488 PLL_FREQ = 3016
6130 06:51:27.338857 DQ_UI_PI_RATIO = 32
6131 06:51:27.339482 CA_UI_PI_RATIO = 32
6132 06:51:27.342531 ===================================
6133 06:51:27.345507 ===================================
6134 06:51:27.348718 memory_type:LPDDR4
6135 06:51:27.352144 GP_NUM : 10
6136 06:51:27.352571 SRAM_EN : 1
6137 06:51:27.355670 MD32_EN : 0
6138 06:51:27.358399 ===================================
6139 06:51:27.361852 [ANA_INIT] >>>>>>>>>>>>>>
6140 06:51:27.365114 <<<<<< [CONFIGURE PHASE]: ANA_TX
6141 06:51:27.368801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6142 06:51:27.372044 ===================================
6143 06:51:27.372572 data_rate = 800,PCW = 0X7400
6144 06:51:27.375266 ===================================
6145 06:51:27.378180 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6146 06:51:27.385256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6147 06:51:27.398303 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6148 06:51:27.401136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6149 06:51:27.405170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6150 06:51:27.407843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6151 06:51:27.411195 [ANA_INIT] flow start
6152 06:51:27.411749 [ANA_INIT] PLL >>>>>>>>
6153 06:51:27.414439 [ANA_INIT] PLL <<<<<<<<
6154 06:51:27.417894 [ANA_INIT] MIDPI >>>>>>>>
6155 06:51:27.421654 [ANA_INIT] MIDPI <<<<<<<<
6156 06:51:27.422165 [ANA_INIT] DLL >>>>>>>>
6157 06:51:27.424640 [ANA_INIT] flow end
6158 06:51:27.427816 ============ LP4 DIFF to SE enter ============
6159 06:51:27.431524 ============ LP4 DIFF to SE exit ============
6160 06:51:27.434209 [ANA_INIT] <<<<<<<<<<<<<
6161 06:51:27.437642 [Flow] Enable top DCM control >>>>>
6162 06:51:27.441092 [Flow] Enable top DCM control <<<<<
6163 06:51:27.444682 Enable DLL master slave shuffle
6164 06:51:27.450780 ==============================================================
6165 06:51:27.451237 Gating Mode config
6166 06:51:27.457181 ==============================================================
6167 06:51:27.457599 Config description:
6168 06:51:27.466841 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6169 06:51:27.473619 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6170 06:51:27.480440 SELPH_MODE 0: By rank 1: By Phase
6171 06:51:27.487089 ==============================================================
6172 06:51:27.487544 GAT_TRACK_EN = 0
6173 06:51:27.489882 RX_GATING_MODE = 2
6174 06:51:27.493433 RX_GATING_TRACK_MODE = 2
6175 06:51:27.496626 SELPH_MODE = 1
6176 06:51:27.500805 PICG_EARLY_EN = 1
6177 06:51:27.503158 VALID_LAT_VALUE = 1
6178 06:51:27.509692 ==============================================================
6179 06:51:27.513397 Enter into Gating configuration >>>>
6180 06:51:27.516742 Exit from Gating configuration <<<<
6181 06:51:27.519562 Enter into DVFS_PRE_config >>>>>
6182 06:51:27.529822 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6183 06:51:27.532786 Exit from DVFS_PRE_config <<<<<
6184 06:51:27.536296 Enter into PICG configuration >>>>
6185 06:51:27.539334 Exit from PICG configuration <<<<
6186 06:51:27.543099 [RX_INPUT] configuration >>>>>
6187 06:51:27.546071 [RX_INPUT] configuration <<<<<
6188 06:51:27.549299 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6189 06:51:27.556432 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6190 06:51:27.562501 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6191 06:51:27.565827 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6192 06:51:27.572424 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6193 06:51:27.578645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6194 06:51:27.582052 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6195 06:51:27.588777 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6196 06:51:27.592317 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6197 06:51:27.595454 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6198 06:51:27.598471 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6199 06:51:27.605382 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 06:51:27.608470 ===================================
6201 06:51:27.608570 LPDDR4 DRAM CONFIGURATION
6202 06:51:27.612271 ===================================
6203 06:51:27.615441 EX_ROW_EN[0] = 0x0
6204 06:51:27.618314 EX_ROW_EN[1] = 0x0
6205 06:51:27.618443 LP4Y_EN = 0x0
6206 06:51:27.621959 WORK_FSP = 0x0
6207 06:51:27.622091 WL = 0x2
6208 06:51:27.625251 RL = 0x2
6209 06:51:27.625419 BL = 0x2
6210 06:51:27.628779 RPST = 0x0
6211 06:51:27.628854 RD_PRE = 0x0
6212 06:51:27.631671 WR_PRE = 0x1
6213 06:51:27.631743 WR_PST = 0x0
6214 06:51:27.634739 DBI_WR = 0x0
6215 06:51:27.634816 DBI_RD = 0x0
6216 06:51:27.638659 OTF = 0x1
6217 06:51:27.641358 ===================================
6218 06:51:27.644966 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6219 06:51:27.648432 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6220 06:51:27.654793 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6221 06:51:27.658371 ===================================
6222 06:51:27.658441 LPDDR4 DRAM CONFIGURATION
6223 06:51:27.661622 ===================================
6224 06:51:27.664812 EX_ROW_EN[0] = 0x10
6225 06:51:27.668111 EX_ROW_EN[1] = 0x0
6226 06:51:27.668181 LP4Y_EN = 0x0
6227 06:51:27.670994 WORK_FSP = 0x0
6228 06:51:27.671062 WL = 0x2
6229 06:51:27.674412 RL = 0x2
6230 06:51:27.674521 BL = 0x2
6231 06:51:27.677753 RPST = 0x0
6232 06:51:27.677820 RD_PRE = 0x0
6233 06:51:27.681167 WR_PRE = 0x1
6234 06:51:27.681236 WR_PST = 0x0
6235 06:51:27.684629 DBI_WR = 0x0
6236 06:51:27.684696 DBI_RD = 0x0
6237 06:51:27.687567 OTF = 0x1
6238 06:51:27.690824 ===================================
6239 06:51:27.697599 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6240 06:51:27.700647 nWR fixed to 30
6241 06:51:27.704051 [ModeRegInit_LP4] CH0 RK0
6242 06:51:27.704132 [ModeRegInit_LP4] CH0 RK1
6243 06:51:27.707309 [ModeRegInit_LP4] CH1 RK0
6244 06:51:27.710657 [ModeRegInit_LP4] CH1 RK1
6245 06:51:27.710742 match AC timing 19
6246 06:51:27.717810 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6247 06:51:27.720677 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6248 06:51:27.723929 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6249 06:51:27.730716 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6250 06:51:27.734187 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6251 06:51:27.734264 ==
6252 06:51:27.737072 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 06:51:27.740774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 06:51:27.740856 ==
6255 06:51:27.747800 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6256 06:51:27.754380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6257 06:51:27.757243 [CA 0] Center 36 (8~64) winsize 57
6258 06:51:27.760230 [CA 1] Center 36 (8~64) winsize 57
6259 06:51:27.763681 [CA 2] Center 36 (8~64) winsize 57
6260 06:51:27.767199 [CA 3] Center 36 (8~64) winsize 57
6261 06:51:27.770631 [CA 4] Center 36 (8~64) winsize 57
6262 06:51:27.770701 [CA 5] Center 36 (8~64) winsize 57
6263 06:51:27.773416
6264 06:51:27.776690 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6265 06:51:27.776757
6266 06:51:27.780699 [CATrainingPosCal] consider 1 rank data
6267 06:51:27.783181 u2DelayCellTimex100 = 270/100 ps
6268 06:51:27.787123 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 06:51:27.790144 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 06:51:27.793600 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 06:51:27.796510 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 06:51:27.800162 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 06:51:27.802931 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 06:51:27.803035
6275 06:51:27.806459 CA PerBit enable=1, Macro0, CA PI delay=36
6276 06:51:27.806541
6277 06:51:27.809873 [CBTSetCACLKResult] CA Dly = 36
6278 06:51:27.813305 CS Dly: 1 (0~32)
6279 06:51:27.813374 ==
6280 06:51:27.816842 Dram Type= 6, Freq= 0, CH_0, rank 1
6281 06:51:27.819620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 06:51:27.819699 ==
6283 06:51:27.826127 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6284 06:51:27.833103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6285 06:51:27.836434 [CA 0] Center 36 (8~64) winsize 57
6286 06:51:27.839827 [CA 1] Center 36 (8~64) winsize 57
6287 06:51:27.839901 [CA 2] Center 36 (8~64) winsize 57
6288 06:51:27.842922 [CA 3] Center 36 (8~64) winsize 57
6289 06:51:27.846239 [CA 4] Center 36 (8~64) winsize 57
6290 06:51:27.849731 [CA 5] Center 36 (8~64) winsize 57
6291 06:51:27.849806
6292 06:51:27.852703 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6293 06:51:27.856135
6294 06:51:27.859547 [CATrainingPosCal] consider 2 rank data
6295 06:51:27.859621 u2DelayCellTimex100 = 270/100 ps
6296 06:51:27.866196 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 06:51:27.869394 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 06:51:27.872504 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 06:51:27.876192 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 06:51:27.879553 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 06:51:27.882892 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 06:51:27.882961
6303 06:51:27.886047 CA PerBit enable=1, Macro0, CA PI delay=36
6304 06:51:27.886132
6305 06:51:27.889038 [CBTSetCACLKResult] CA Dly = 36
6306 06:51:27.892172 CS Dly: 1 (0~32)
6307 06:51:27.892249
6308 06:51:27.895620 ----->DramcWriteLeveling(PI) begin...
6309 06:51:27.895693 ==
6310 06:51:27.899292 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 06:51:27.902208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 06:51:27.902277 ==
6313 06:51:27.905519 Write leveling (Byte 0): 40 => 8
6314 06:51:27.908580 Write leveling (Byte 1): 40 => 8
6315 06:51:27.911909 DramcWriteLeveling(PI) end<-----
6316 06:51:27.911985
6317 06:51:27.912057 ==
6318 06:51:27.915944 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 06:51:27.918408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 06:51:27.918477 ==
6321 06:51:27.922296 [Gating] SW mode calibration
6322 06:51:27.928427 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6323 06:51:27.935320 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6324 06:51:27.938538 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6325 06:51:27.944998 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6326 06:51:27.948296 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 06:51:27.951663 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 06:51:27.958407 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 06:51:27.961150 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 06:51:27.964646 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 06:51:27.971008 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 06:51:27.974508 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 06:51:27.977612 Total UI for P1: 0, mck2ui 16
6334 06:51:27.980824 best dqsien dly found for B0: ( 0, 14, 24)
6335 06:51:27.984123 Total UI for P1: 0, mck2ui 16
6336 06:51:27.987330 best dqsien dly found for B1: ( 0, 14, 24)
6337 06:51:27.990873 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6338 06:51:27.994231 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6339 06:51:27.994312
6340 06:51:27.997426 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6341 06:51:28.000799 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6342 06:51:28.003704 [Gating] SW calibration Done
6343 06:51:28.003783 ==
6344 06:51:28.007027 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 06:51:28.013980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 06:51:28.014054 ==
6347 06:51:28.014129 RX Vref Scan: 0
6348 06:51:28.014188
6349 06:51:28.017396 RX Vref 0 -> 0, step: 1
6350 06:51:28.017464
6351 06:51:28.020142 RX Delay -410 -> 252, step: 16
6352 06:51:28.023445 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6353 06:51:28.026676 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6354 06:51:28.033324 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6355 06:51:28.037837 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6356 06:51:28.040596 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6357 06:51:28.044522 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6358 06:51:28.050028 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6359 06:51:28.053655 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6360 06:51:28.056631 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6361 06:51:28.059709 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6362 06:51:28.066949 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6363 06:51:28.069620 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6364 06:51:28.073169 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6365 06:51:28.076591 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6366 06:51:28.082903 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6367 06:51:28.086438 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6368 06:51:28.086521 ==
6369 06:51:28.089547 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 06:51:28.092832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 06:51:28.092941 ==
6372 06:51:28.095942 DQS Delay:
6373 06:51:28.096023 DQS0 = 35, DQS1 = 59
6374 06:51:28.099288 DQM Delay:
6375 06:51:28.099390 DQM0 = 7, DQM1 = 19
6376 06:51:28.099464 DQ Delay:
6377 06:51:28.102941 DQ0 =0, DQ1 =8, DQ2 =8, DQ3 =0
6378 06:51:28.106165 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6379 06:51:28.109542 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6380 06:51:28.112497 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =24
6381 06:51:28.112574
6382 06:51:28.112635
6383 06:51:28.112691 ==
6384 06:51:28.115945 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 06:51:28.122872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 06:51:28.122954 ==
6387 06:51:28.123015
6388 06:51:28.123072
6389 06:51:28.123134 TX Vref Scan disable
6390 06:51:28.126122 == TX Byte 0 ==
6391 06:51:28.129457 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 06:51:28.132407 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 06:51:28.135717 == TX Byte 1 ==
6394 06:51:28.139225 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 06:51:28.142219 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 06:51:28.145857 ==
6397 06:51:28.149208 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 06:51:28.152208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 06:51:28.152289 ==
6400 06:51:28.152353
6401 06:51:28.152413
6402 06:51:28.155359 TX Vref Scan disable
6403 06:51:28.155462 == TX Byte 0 ==
6404 06:51:28.158960 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 06:51:28.165565 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 06:51:28.165647 == TX Byte 1 ==
6407 06:51:28.168604 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 06:51:28.175557 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 06:51:28.175638
6410 06:51:28.175702 [DATLAT]
6411 06:51:28.175761 Freq=400, CH0 RK0
6412 06:51:28.175818
6413 06:51:28.179004 DATLAT Default: 0xf
6414 06:51:28.181919 0, 0xFFFF, sum = 0
6415 06:51:28.182002 1, 0xFFFF, sum = 0
6416 06:51:28.185257 2, 0xFFFF, sum = 0
6417 06:51:28.185338 3, 0xFFFF, sum = 0
6418 06:51:28.188805 4, 0xFFFF, sum = 0
6419 06:51:28.188887 5, 0xFFFF, sum = 0
6420 06:51:28.191920 6, 0xFFFF, sum = 0
6421 06:51:28.192001 7, 0xFFFF, sum = 0
6422 06:51:28.195302 8, 0xFFFF, sum = 0
6423 06:51:28.195426 9, 0xFFFF, sum = 0
6424 06:51:28.198430 10, 0xFFFF, sum = 0
6425 06:51:28.198512 11, 0xFFFF, sum = 0
6426 06:51:28.201695 12, 0xFFFF, sum = 0
6427 06:51:28.201776 13, 0x0, sum = 1
6428 06:51:28.204780 14, 0x0, sum = 2
6429 06:51:28.204862 15, 0x0, sum = 3
6430 06:51:28.208061 16, 0x0, sum = 4
6431 06:51:28.208142 best_step = 14
6432 06:51:28.208205
6433 06:51:28.208263 ==
6434 06:51:28.211378 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 06:51:28.218454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 06:51:28.218536 ==
6437 06:51:28.218600 RX Vref Scan: 1
6438 06:51:28.218660
6439 06:51:28.221866 RX Vref 0 -> 0, step: 1
6440 06:51:28.221947
6441 06:51:28.225116 RX Delay -359 -> 252, step: 8
6442 06:51:28.225196
6443 06:51:28.228195 Set Vref, RX VrefLevel [Byte0]: 57
6444 06:51:28.231399 [Byte1]: 44
6445 06:51:28.231480
6446 06:51:28.234412 Final RX Vref Byte 0 = 57 to rank0
6447 06:51:28.237663 Final RX Vref Byte 1 = 44 to rank0
6448 06:51:28.241341 Final RX Vref Byte 0 = 57 to rank1
6449 06:51:28.244551 Final RX Vref Byte 1 = 44 to rank1==
6450 06:51:28.247971 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 06:51:28.250942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 06:51:28.254387 ==
6453 06:51:28.254474 DQS Delay:
6454 06:51:28.254543 DQS0 = 44, DQS1 = 56
6455 06:51:28.257707 DQM Delay:
6456 06:51:28.257800 DQM0 = 10, DQM1 = 13
6457 06:51:28.261005 DQ Delay:
6458 06:51:28.264204 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6459 06:51:28.264304 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6460 06:51:28.267810 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6461 06:51:28.271013 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
6462 06:51:28.273922
6463 06:51:28.274042
6464 06:51:28.280846 [DQSOSCAuto] RK0, (LSB)MR18= 0x9e91, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 390 ps
6465 06:51:28.283741 CH0 RK0: MR19=C0C, MR18=9E91
6466 06:51:28.290941 CH0_RK0: MR19=0xC0C, MR18=0x9E91, DQSOSC=390, MR23=63, INC=388, DEC=258
6467 06:51:28.291140 ==
6468 06:51:28.294367 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 06:51:28.297447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 06:51:28.297686 ==
6471 06:51:28.301345 [Gating] SW mode calibration
6472 06:51:28.306952 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6473 06:51:28.313477 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6474 06:51:28.316703 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6475 06:51:28.320335 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6476 06:51:28.326584 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 06:51:28.330427 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 06:51:28.332782 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 06:51:28.339664 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 06:51:28.342997 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 06:51:28.346524 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 06:51:28.352933 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 06:51:28.356464 Total UI for P1: 0, mck2ui 16
6484 06:51:28.359610 best dqsien dly found for B0: ( 0, 14, 24)
6485 06:51:28.362999 Total UI for P1: 0, mck2ui 16
6486 06:51:28.365803 best dqsien dly found for B1: ( 0, 14, 24)
6487 06:51:28.369223 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6488 06:51:28.373009 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6489 06:51:28.373090
6490 06:51:28.376050 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6491 06:51:28.379353 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6492 06:51:28.382284 [Gating] SW calibration Done
6493 06:51:28.382365 ==
6494 06:51:28.386222 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 06:51:28.388960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 06:51:28.389042 ==
6497 06:51:28.392491 RX Vref Scan: 0
6498 06:51:28.392571
6499 06:51:28.395576 RX Vref 0 -> 0, step: 1
6500 06:51:28.395656
6501 06:51:28.398613 RX Delay -410 -> 252, step: 16
6502 06:51:28.402013 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6503 06:51:28.405710 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6504 06:51:28.408774 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6505 06:51:28.415524 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6506 06:51:28.418616 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6507 06:51:28.421707 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6508 06:51:28.425136 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6509 06:51:28.431663 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6510 06:51:28.435130 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6511 06:51:28.438339 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6512 06:51:28.441637 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6513 06:51:28.448501 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6514 06:51:28.451519 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6515 06:51:28.455019 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6516 06:51:28.461814 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6517 06:51:28.464824 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6518 06:51:28.464946 ==
6519 06:51:28.467786 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 06:51:28.471179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 06:51:28.471330 ==
6522 06:51:28.474594 DQS Delay:
6523 06:51:28.474744 DQS0 = 35, DQS1 = 51
6524 06:51:28.477914 DQM Delay:
6525 06:51:28.477995 DQM0 = 5, DQM1 = 10
6526 06:51:28.478060 DQ Delay:
6527 06:51:28.481021 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6528 06:51:28.484173 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6529 06:51:28.488231 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6530 06:51:28.490908 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6531 06:51:28.491001
6532 06:51:28.491075
6533 06:51:28.491142 ==
6534 06:51:28.494359 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 06:51:28.500651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 06:51:28.500760 ==
6537 06:51:28.500846
6538 06:51:28.500926
6539 06:51:28.501003 TX Vref Scan disable
6540 06:51:28.504516 == TX Byte 0 ==
6541 06:51:28.507350 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6542 06:51:28.511035 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6543 06:51:28.513996 == TX Byte 1 ==
6544 06:51:28.517411 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6545 06:51:28.520698 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6546 06:51:28.521230 ==
6547 06:51:28.524711 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 06:51:28.530842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 06:51:28.531261 ==
6550 06:51:28.531631
6551 06:51:28.531941
6552 06:51:28.532237 TX Vref Scan disable
6553 06:51:28.534117 == TX Byte 0 ==
6554 06:51:28.537399 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6555 06:51:28.540891 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6556 06:51:28.543898 == TX Byte 1 ==
6557 06:51:28.547128 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6558 06:51:28.550825 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6559 06:51:28.551346
6560 06:51:28.553794 [DATLAT]
6561 06:51:28.554229 Freq=400, CH0 RK1
6562 06:51:28.554564
6563 06:51:28.557315 DATLAT Default: 0xe
6564 06:51:28.557728 0, 0xFFFF, sum = 0
6565 06:51:28.560545 1, 0xFFFF, sum = 0
6566 06:51:28.561005 2, 0xFFFF, sum = 0
6567 06:51:28.563952 3, 0xFFFF, sum = 0
6568 06:51:28.564491 4, 0xFFFF, sum = 0
6569 06:51:28.566686 5, 0xFFFF, sum = 0
6570 06:51:28.570961 6, 0xFFFF, sum = 0
6571 06:51:28.571657 7, 0xFFFF, sum = 0
6572 06:51:28.573692 8, 0xFFFF, sum = 0
6573 06:51:28.574339 9, 0xFFFF, sum = 0
6574 06:51:28.576724 10, 0xFFFF, sum = 0
6575 06:51:28.577316 11, 0xFFFF, sum = 0
6576 06:51:28.580137 12, 0xFFFF, sum = 0
6577 06:51:28.580703 13, 0x0, sum = 1
6578 06:51:28.583470 14, 0x0, sum = 2
6579 06:51:28.584132 15, 0x0, sum = 3
6580 06:51:28.586349 16, 0x0, sum = 4
6581 06:51:28.586910 best_step = 14
6582 06:51:28.587312
6583 06:51:28.587805 ==
6584 06:51:28.589732 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 06:51:28.593073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 06:51:28.597489 ==
6587 06:51:28.598154 RX Vref Scan: 0
6588 06:51:28.598714
6589 06:51:28.599559 RX Vref 0 -> 0, step: 1
6590 06:51:28.600010
6591 06:51:28.602953 RX Delay -343 -> 252, step: 8
6592 06:51:28.609222 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6593 06:51:28.613157 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6594 06:51:28.616086 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6595 06:51:28.619456 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6596 06:51:28.626257 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6597 06:51:28.629253 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6598 06:51:28.632719 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6599 06:51:28.635741 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6600 06:51:28.642384 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6601 06:51:28.645824 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6602 06:51:28.648696 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6603 06:51:28.652329 iDelay=217, Bit 11, Center -52 (-287 ~ 184) 472
6604 06:51:28.659022 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6605 06:51:28.662495 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6606 06:51:28.665336 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6607 06:51:28.671649 iDelay=217, Bit 15, Center -36 (-271 ~ 200) 472
6608 06:51:28.672219 ==
6609 06:51:28.675139 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 06:51:28.678585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 06:51:28.679012 ==
6612 06:51:28.679345 DQS Delay:
6613 06:51:28.682043 DQS0 = 40, DQS1 = 60
6614 06:51:28.682461 DQM Delay:
6615 06:51:28.684815 DQM0 = 6, DQM1 = 15
6616 06:51:28.685237 DQ Delay:
6617 06:51:28.688397 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6618 06:51:28.691501 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6619 06:51:28.695179 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6620 06:51:28.698746 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6621 06:51:28.699160
6622 06:51:28.699547
6623 06:51:28.704868 [DQSOSCAuto] RK1, (LSB)MR18= 0x867e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6624 06:51:28.708119 CH0 RK1: MR19=C0C, MR18=867E
6625 06:51:28.714763 CH0_RK1: MR19=0xC0C, MR18=0x867E, DQSOSC=393, MR23=63, INC=382, DEC=254
6626 06:51:28.718528 [RxdqsGatingPostProcess] freq 400
6627 06:51:28.725066 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6628 06:51:28.728284 best DQS0 dly(2T, 0.5T) = (0, 10)
6629 06:51:28.728701 best DQS1 dly(2T, 0.5T) = (0, 10)
6630 06:51:28.731071 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6631 06:51:28.734448 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6632 06:51:28.737741 best DQS0 dly(2T, 0.5T) = (0, 10)
6633 06:51:28.741081 best DQS1 dly(2T, 0.5T) = (0, 10)
6634 06:51:28.744255 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6635 06:51:28.747552 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6636 06:51:28.750682 Pre-setting of DQS Precalculation
6637 06:51:28.758082 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6638 06:51:28.758164 ==
6639 06:51:28.760794 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 06:51:28.763823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 06:51:28.763906 ==
6642 06:51:28.770511 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6643 06:51:28.773831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6644 06:51:28.777274 [CA 0] Center 36 (8~64) winsize 57
6645 06:51:28.780577 [CA 1] Center 36 (8~64) winsize 57
6646 06:51:28.783949 [CA 2] Center 36 (8~64) winsize 57
6647 06:51:28.787185 [CA 3] Center 36 (8~64) winsize 57
6648 06:51:28.791018 [CA 4] Center 36 (8~64) winsize 57
6649 06:51:28.793498 [CA 5] Center 36 (8~64) winsize 57
6650 06:51:28.793580
6651 06:51:28.796672 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6652 06:51:28.796754
6653 06:51:28.799848 [CATrainingPosCal] consider 1 rank data
6654 06:51:28.803656 u2DelayCellTimex100 = 270/100 ps
6655 06:51:28.806563 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 06:51:28.813406 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 06:51:28.816515 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 06:51:28.819853 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 06:51:28.823110 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 06:51:28.826600 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 06:51:28.826672
6662 06:51:28.829676 CA PerBit enable=1, Macro0, CA PI delay=36
6663 06:51:28.829747
6664 06:51:28.833285 [CBTSetCACLKResult] CA Dly = 36
6665 06:51:28.836423 CS Dly: 1 (0~32)
6666 06:51:28.836506 ==
6667 06:51:28.839894 Dram Type= 6, Freq= 0, CH_1, rank 1
6668 06:51:28.842980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 06:51:28.843054 ==
6670 06:51:28.849361 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6671 06:51:28.852910 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6672 06:51:28.856442 [CA 0] Center 36 (8~64) winsize 57
6673 06:51:28.859464 [CA 1] Center 36 (8~64) winsize 57
6674 06:51:28.862516 [CA 2] Center 36 (8~64) winsize 57
6675 06:51:28.865830 [CA 3] Center 36 (8~64) winsize 57
6676 06:51:28.869285 [CA 4] Center 36 (8~64) winsize 57
6677 06:51:28.872694 [CA 5] Center 36 (8~64) winsize 57
6678 06:51:28.872769
6679 06:51:28.875738 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6680 06:51:28.875813
6681 06:51:28.879189 [CATrainingPosCal] consider 2 rank data
6682 06:51:28.882730 u2DelayCellTimex100 = 270/100 ps
6683 06:51:28.885443 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 06:51:28.889321 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 06:51:28.895823 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 06:51:28.898639 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 06:51:28.902209 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 06:51:28.905517 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 06:51:28.905599
6690 06:51:28.908819 CA PerBit enable=1, Macro0, CA PI delay=36
6691 06:51:28.908901
6692 06:51:28.911742 [CBTSetCACLKResult] CA Dly = 36
6693 06:51:28.911823 CS Dly: 1 (0~32)
6694 06:51:28.915185
6695 06:51:28.918568 ----->DramcWriteLeveling(PI) begin...
6696 06:51:28.918651 ==
6697 06:51:28.921554 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 06:51:28.925822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 06:51:28.925905 ==
6700 06:51:28.928144 Write leveling (Byte 0): 40 => 8
6701 06:51:28.931649 Write leveling (Byte 1): 40 => 8
6702 06:51:28.935095 DramcWriteLeveling(PI) end<-----
6703 06:51:28.935176
6704 06:51:28.935241 ==
6705 06:51:28.938118 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 06:51:28.941761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 06:51:28.941842 ==
6708 06:51:28.944778 [Gating] SW mode calibration
6709 06:51:28.951522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6710 06:51:28.958147 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6711 06:51:28.961514 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6712 06:51:28.964270 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6713 06:51:28.970993 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 06:51:28.974529 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 06:51:28.977749 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 06:51:28.984382 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 06:51:28.987555 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 06:51:28.990963 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 06:51:28.997434 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 06:51:28.997541 Total UI for P1: 0, mck2ui 16
6721 06:51:29.004208 best dqsien dly found for B0: ( 0, 14, 24)
6722 06:51:29.004282 Total UI for P1: 0, mck2ui 16
6723 06:51:29.010701 best dqsien dly found for B1: ( 0, 14, 24)
6724 06:51:29.014120 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6725 06:51:29.017652 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6726 06:51:29.017728
6727 06:51:29.021335 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6728 06:51:29.023792 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6729 06:51:29.027257 [Gating] SW calibration Done
6730 06:51:29.027334 ==
6731 06:51:29.030564 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 06:51:29.033856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 06:51:29.033928 ==
6734 06:51:29.037148 RX Vref Scan: 0
6735 06:51:29.037222
6736 06:51:29.037292 RX Vref 0 -> 0, step: 1
6737 06:51:29.040608
6738 06:51:29.040677 RX Delay -410 -> 252, step: 16
6739 06:51:29.047321 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6740 06:51:29.050404 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6741 06:51:29.053752 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6742 06:51:29.060090 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6743 06:51:29.063324 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6744 06:51:29.067069 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6745 06:51:29.070091 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6746 06:51:29.076305 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6747 06:51:29.080310 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6748 06:51:29.083449 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6749 06:51:29.086173 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6750 06:51:29.092934 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6751 06:51:29.096143 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6752 06:51:29.099764 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6753 06:51:29.103159 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6754 06:51:29.109926 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6755 06:51:29.110004 ==
6756 06:51:29.112890 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 06:51:29.116162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 06:51:29.116234 ==
6759 06:51:29.116297 DQS Delay:
6760 06:51:29.119702 DQS0 = 35, DQS1 = 51
6761 06:51:29.119782 DQM Delay:
6762 06:51:29.122805 DQM0 = 6, DQM1 = 13
6763 06:51:29.122885 DQ Delay:
6764 06:51:29.125731 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6765 06:51:29.129042 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6766 06:51:29.132756 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6767 06:51:29.135575 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6768 06:51:29.135646
6769 06:51:29.135707
6770 06:51:29.135764 ==
6771 06:51:29.139315 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 06:51:29.142574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 06:51:29.142645 ==
6774 06:51:29.145373
6775 06:51:29.145441
6776 06:51:29.145509 TX Vref Scan disable
6777 06:51:29.148860 == TX Byte 0 ==
6778 06:51:29.152069 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 06:51:29.155435 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 06:51:29.158876 == TX Byte 1 ==
6781 06:51:29.161836 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 06:51:29.165610 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 06:51:29.165690 ==
6784 06:51:29.168720 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 06:51:29.175531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 06:51:29.175614 ==
6787 06:51:29.175679
6788 06:51:29.175738
6789 06:51:29.175795 TX Vref Scan disable
6790 06:51:29.179089 == TX Byte 0 ==
6791 06:51:29.181657 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 06:51:29.185178 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 06:51:29.188351 == TX Byte 1 ==
6794 06:51:29.192255 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 06:51:29.195232 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 06:51:29.195338
6797 06:51:29.198792 [DATLAT]
6798 06:51:29.198862 Freq=400, CH1 RK0
6799 06:51:29.198926
6800 06:51:29.202228 DATLAT Default: 0xf
6801 06:51:29.202295 0, 0xFFFF, sum = 0
6802 06:51:29.204797 1, 0xFFFF, sum = 0
6803 06:51:29.204865 2, 0xFFFF, sum = 0
6804 06:51:29.208331 3, 0xFFFF, sum = 0
6805 06:51:29.208413 4, 0xFFFF, sum = 0
6806 06:51:29.211408 5, 0xFFFF, sum = 0
6807 06:51:29.211496 6, 0xFFFF, sum = 0
6808 06:51:29.215060 7, 0xFFFF, sum = 0
6809 06:51:29.215142 8, 0xFFFF, sum = 0
6810 06:51:29.218390 9, 0xFFFF, sum = 0
6811 06:51:29.221874 10, 0xFFFF, sum = 0
6812 06:51:29.221956 11, 0xFFFF, sum = 0
6813 06:51:29.224597 12, 0xFFFF, sum = 0
6814 06:51:29.224680 13, 0x0, sum = 1
6815 06:51:29.228142 14, 0x0, sum = 2
6816 06:51:29.228224 15, 0x0, sum = 3
6817 06:51:29.228289 16, 0x0, sum = 4
6818 06:51:29.232247 best_step = 14
6819 06:51:29.232329
6820 06:51:29.232392 ==
6821 06:51:29.234864 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 06:51:29.237932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 06:51:29.238014 ==
6824 06:51:29.241621 RX Vref Scan: 1
6825 06:51:29.241703
6826 06:51:29.241767 RX Vref 0 -> 0, step: 1
6827 06:51:29.244885
6828 06:51:29.244970 RX Delay -343 -> 252, step: 8
6829 06:51:29.245034
6830 06:51:29.248019 Set Vref, RX VrefLevel [Byte0]: 50
6831 06:51:29.251191 [Byte1]: 53
6832 06:51:29.256480
6833 06:51:29.256561 Final RX Vref Byte 0 = 50 to rank0
6834 06:51:29.259653 Final RX Vref Byte 1 = 53 to rank0
6835 06:51:29.262984 Final RX Vref Byte 0 = 50 to rank1
6836 06:51:29.266526 Final RX Vref Byte 1 = 53 to rank1==
6837 06:51:29.269659 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 06:51:29.276224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 06:51:29.276307 ==
6840 06:51:29.276371 DQS Delay:
6841 06:51:29.280139 DQS0 = 44, DQS1 = 52
6842 06:51:29.280220 DQM Delay:
6843 06:51:29.280284 DQM0 = 10, DQM1 = 11
6844 06:51:29.282892 DQ Delay:
6845 06:51:29.286068 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6846 06:51:29.289415 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6847 06:51:29.289496 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6848 06:51:29.292692 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6849 06:51:29.295937
6850 06:51:29.296017
6851 06:51:29.302695 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f96, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 395 ps
6852 06:51:29.305699 CH1 RK0: MR19=C0C, MR18=6F96
6853 06:51:29.312667 CH1_RK0: MR19=0xC0C, MR18=0x6F96, DQSOSC=391, MR23=63, INC=386, DEC=257
6854 06:51:29.312749 ==
6855 06:51:29.316140 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 06:51:29.319187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 06:51:29.319295 ==
6858 06:51:29.322613 [Gating] SW mode calibration
6859 06:51:29.329318 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6860 06:51:29.335358 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6861 06:51:29.339390 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6862 06:51:29.341820 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6863 06:51:29.348784 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 06:51:29.352113 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 06:51:29.355303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 06:51:29.361805 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 06:51:29.365207 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 06:51:29.368070 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 06:51:29.374906 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 06:51:29.378189 Total UI for P1: 0, mck2ui 16
6871 06:51:29.381941 best dqsien dly found for B0: ( 0, 14, 24)
6872 06:51:29.384717 Total UI for P1: 0, mck2ui 16
6873 06:51:29.388096 best dqsien dly found for B1: ( 0, 14, 24)
6874 06:51:29.391082 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6875 06:51:29.394883 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6876 06:51:29.394965
6877 06:51:29.397831 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6878 06:51:29.401294 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6879 06:51:29.404939 [Gating] SW calibration Done
6880 06:51:29.405020 ==
6881 06:51:29.407771 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 06:51:29.411042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 06:51:29.414352 ==
6884 06:51:29.414433 RX Vref Scan: 0
6885 06:51:29.414497
6886 06:51:29.417247 RX Vref 0 -> 0, step: 1
6887 06:51:29.417329
6888 06:51:29.420668 RX Delay -410 -> 252, step: 16
6889 06:51:29.423985 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6890 06:51:29.427233 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6891 06:51:29.430492 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6892 06:51:29.437474 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6893 06:51:29.440799 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6894 06:51:29.443817 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6895 06:51:29.447108 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6896 06:51:29.454211 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6897 06:51:29.456894 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6898 06:51:29.460064 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6899 06:51:29.467045 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6900 06:51:29.469764 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6901 06:51:29.473500 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6902 06:51:29.476715 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6903 06:51:29.483055 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6904 06:51:29.486399 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6905 06:51:29.486474 ==
6906 06:51:29.489826 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 06:51:29.493205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 06:51:29.493307 ==
6909 06:51:29.496325 DQS Delay:
6910 06:51:29.496411 DQS0 = 43, DQS1 = 51
6911 06:51:29.499925 DQM Delay:
6912 06:51:29.499996 DQM0 = 9, DQM1 = 14
6913 06:51:29.500060 DQ Delay:
6914 06:51:29.503056 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6915 06:51:29.505912 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6916 06:51:29.509641 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6917 06:51:29.512872 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6918 06:51:29.512941
6919 06:51:29.513000
6920 06:51:29.513066 ==
6921 06:51:29.515925 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 06:51:29.522398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 06:51:29.522477 ==
6924 06:51:29.522539
6925 06:51:29.522596
6926 06:51:29.522662 TX Vref Scan disable
6927 06:51:29.525513 == TX Byte 0 ==
6928 06:51:29.529087 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6929 06:51:29.532456 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6930 06:51:29.536051 == TX Byte 1 ==
6931 06:51:29.538743 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6932 06:51:29.542060 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6933 06:51:29.542142 ==
6934 06:51:29.545430 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 06:51:29.552860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 06:51:29.553290 ==
6937 06:51:29.553619
6938 06:51:29.553928
6939 06:51:29.555915 TX Vref Scan disable
6940 06:51:29.556335 == TX Byte 0 ==
6941 06:51:29.559228 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6942 06:51:29.565580 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6943 06:51:29.566000 == TX Byte 1 ==
6944 06:51:29.569546 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6945 06:51:29.575522 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6946 06:51:29.575944
6947 06:51:29.576311 [DATLAT]
6948 06:51:29.576625 Freq=400, CH1 RK1
6949 06:51:29.576926
6950 06:51:29.578770 DATLAT Default: 0xe
6951 06:51:29.579182 0, 0xFFFF, sum = 0
6952 06:51:29.581932 1, 0xFFFF, sum = 0
6953 06:51:29.582373 2, 0xFFFF, sum = 0
6954 06:51:29.585263 3, 0xFFFF, sum = 0
6955 06:51:29.588794 4, 0xFFFF, sum = 0
6956 06:51:29.589222 5, 0xFFFF, sum = 0
6957 06:51:29.592061 6, 0xFFFF, sum = 0
6958 06:51:29.592489 7, 0xFFFF, sum = 0
6959 06:51:29.595569 8, 0xFFFF, sum = 0
6960 06:51:29.596001 9, 0xFFFF, sum = 0
6961 06:51:29.598577 10, 0xFFFF, sum = 0
6962 06:51:29.598998 11, 0xFFFF, sum = 0
6963 06:51:29.602090 12, 0xFFFF, sum = 0
6964 06:51:29.602535 13, 0x0, sum = 1
6965 06:51:29.605195 14, 0x0, sum = 2
6966 06:51:29.605617 15, 0x0, sum = 3
6967 06:51:29.608486 16, 0x0, sum = 4
6968 06:51:29.608910 best_step = 14
6969 06:51:29.609238
6970 06:51:29.609544 ==
6971 06:51:29.612043 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 06:51:29.615779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 06:51:29.619015 ==
6974 06:51:29.619475 RX Vref Scan: 0
6975 06:51:29.619814
6976 06:51:29.621650 RX Vref 0 -> 0, step: 1
6977 06:51:29.622067
6978 06:51:29.625128 RX Delay -343 -> 252, step: 8
6979 06:51:29.631794 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6980 06:51:29.634995 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6981 06:51:29.638430 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6982 06:51:29.641646 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6983 06:51:29.648033 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6984 06:51:29.651552 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6985 06:51:29.655002 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6986 06:51:29.657884 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6987 06:51:29.664777 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6988 06:51:29.668313 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6989 06:51:29.671282 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6990 06:51:29.674796 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6991 06:51:29.681683 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6992 06:51:29.684394 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6993 06:51:29.687981 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6994 06:51:29.690945 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6995 06:51:29.694344 ==
6996 06:51:29.697613 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 06:51:29.700899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 06:51:29.701573 ==
6999 06:51:29.702133 DQS Delay:
7000 06:51:29.704282 DQS0 = 48, DQS1 = 52
7001 06:51:29.704699 DQM Delay:
7002 06:51:29.707823 DQM0 = 11, DQM1 = 10
7003 06:51:29.708289 DQ Delay:
7004 06:51:29.711160 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7005 06:51:29.714493 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7006 06:51:29.717310 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7007 06:51:29.720738 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7008 06:51:29.721221
7009 06:51:29.721647
7010 06:51:29.727116 [DQSOSCAuto] RK1, (LSB)MR18= 0x79b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
7011 06:51:29.730600 CH1 RK1: MR19=C0C, MR18=79B1
7012 06:51:29.737075 CH1_RK1: MR19=0xC0C, MR18=0x79B1, DQSOSC=387, MR23=63, INC=394, DEC=262
7013 06:51:29.740816 [RxdqsGatingPostProcess] freq 400
7014 06:51:29.747124 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7015 06:51:29.747721 best DQS0 dly(2T, 0.5T) = (0, 10)
7016 06:51:29.750717 best DQS1 dly(2T, 0.5T) = (0, 10)
7017 06:51:29.754234 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7018 06:51:29.757032 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7019 06:51:29.760418 best DQS0 dly(2T, 0.5T) = (0, 10)
7020 06:51:29.763353 best DQS1 dly(2T, 0.5T) = (0, 10)
7021 06:51:29.767193 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7022 06:51:29.770378 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7023 06:51:29.773426 Pre-setting of DQS Precalculation
7024 06:51:29.780219 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7025 06:51:29.786754 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7026 06:51:29.793640 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7027 06:51:29.794095
7028 06:51:29.794460
7029 06:51:29.796447 [Calibration Summary] 800 Mbps
7030 06:51:29.796974 CH 0, Rank 0
7031 06:51:29.800098 SW Impedance : PASS
7032 06:51:29.803270 DUTY Scan : NO K
7033 06:51:29.803799 ZQ Calibration : PASS
7034 06:51:29.806251 Jitter Meter : NO K
7035 06:51:29.809768 CBT Training : PASS
7036 06:51:29.810282 Write leveling : PASS
7037 06:51:29.813053 RX DQS gating : PASS
7038 06:51:29.816752 RX DQ/DQS(RDDQC) : PASS
7039 06:51:29.817443 TX DQ/DQS : PASS
7040 06:51:29.820241 RX DATLAT : PASS
7041 06:51:29.820652 RX DQ/DQS(Engine): PASS
7042 06:51:29.823324 TX OE : NO K
7043 06:51:29.823828 All Pass.
7044 06:51:29.824202
7045 06:51:29.826663 CH 0, Rank 1
7046 06:51:29.827203 SW Impedance : PASS
7047 06:51:29.829602 DUTY Scan : NO K
7048 06:51:29.832925 ZQ Calibration : PASS
7049 06:51:29.833419 Jitter Meter : NO K
7050 06:51:29.836555 CBT Training : PASS
7051 06:51:29.839424 Write leveling : NO K
7052 06:51:29.839953 RX DQS gating : PASS
7053 06:51:29.843067 RX DQ/DQS(RDDQC) : PASS
7054 06:51:29.846115 TX DQ/DQS : PASS
7055 06:51:29.846573 RX DATLAT : PASS
7056 06:51:29.849598 RX DQ/DQS(Engine): PASS
7057 06:51:29.852759 TX OE : NO K
7058 06:51:29.853198 All Pass.
7059 06:51:29.853561
7060 06:51:29.853884 CH 1, Rank 0
7061 06:51:29.855715 SW Impedance : PASS
7062 06:51:29.859628 DUTY Scan : NO K
7063 06:51:29.860067 ZQ Calibration : PASS
7064 06:51:29.863653 Jitter Meter : NO K
7065 06:51:29.865577 CBT Training : PASS
7066 06:51:29.866011 Write leveling : PASS
7067 06:51:29.868958 RX DQS gating : PASS
7068 06:51:29.872211 RX DQ/DQS(RDDQC) : PASS
7069 06:51:29.872814 TX DQ/DQS : PASS
7070 06:51:29.875796 RX DATLAT : PASS
7071 06:51:29.878909 RX DQ/DQS(Engine): PASS
7072 06:51:29.879327 TX OE : NO K
7073 06:51:29.882294 All Pass.
7074 06:51:29.882729
7075 06:51:29.883078 CH 1, Rank 1
7076 06:51:29.885797 SW Impedance : PASS
7077 06:51:29.886229 DUTY Scan : NO K
7078 06:51:29.889569 ZQ Calibration : PASS
7079 06:51:29.892226 Jitter Meter : NO K
7080 06:51:29.892623 CBT Training : PASS
7081 06:51:29.895444 Write leveling : NO K
7082 06:51:29.898573 RX DQS gating : PASS
7083 06:51:29.898991 RX DQ/DQS(RDDQC) : PASS
7084 06:51:29.901973 TX DQ/DQS : PASS
7085 06:51:29.902389 RX DATLAT : PASS
7086 06:51:29.905276 RX DQ/DQS(Engine): PASS
7087 06:51:29.908555 TX OE : NO K
7088 06:51:29.908971 All Pass.
7089 06:51:29.909299
7090 06:51:29.912484 DramC Write-DBI off
7091 06:51:29.912899 PER_BANK_REFRESH: Hybrid Mode
7092 06:51:29.916249 TX_TRACKING: ON
7093 06:51:29.925319 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7094 06:51:29.928366 [FAST_K] Save calibration result to emmc
7095 06:51:29.931717 dramc_set_vcore_voltage set vcore to 725000
7096 06:51:29.934976 Read voltage for 1600, 0
7097 06:51:29.935442 Vio18 = 0
7098 06:51:29.935840 Vcore = 725000
7099 06:51:29.938513 Vdram = 0
7100 06:51:29.939060 Vddq = 0
7101 06:51:29.939699 Vmddr = 0
7102 06:51:29.944602 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7103 06:51:29.948088 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7104 06:51:29.951611 MEM_TYPE=3, freq_sel=13
7105 06:51:29.954908 sv_algorithm_assistance_LP4_3733
7106 06:51:29.958217 ============ PULL DRAM RESETB DOWN ============
7107 06:51:29.961569 ========== PULL DRAM RESETB DOWN end =========
7108 06:51:29.968345 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7109 06:51:29.971561 ===================================
7110 06:51:29.974295 LPDDR4 DRAM CONFIGURATION
7111 06:51:29.977534 ===================================
7112 06:51:29.977956 EX_ROW_EN[0] = 0x0
7113 06:51:29.980898 EX_ROW_EN[1] = 0x0
7114 06:51:29.981278 LP4Y_EN = 0x0
7115 06:51:29.984530 WORK_FSP = 0x1
7116 06:51:29.984900 WL = 0x5
7117 06:51:29.987294 RL = 0x5
7118 06:51:29.987783 BL = 0x2
7119 06:51:29.990646 RPST = 0x0
7120 06:51:29.991006 RD_PRE = 0x0
7121 06:51:29.994288 WR_PRE = 0x1
7122 06:51:29.994840 WR_PST = 0x1
7123 06:51:29.997362 DBI_WR = 0x0
7124 06:51:29.997802 DBI_RD = 0x0
7125 06:51:30.000609 OTF = 0x1
7126 06:51:30.003872 ===================================
7127 06:51:30.007633 ===================================
7128 06:51:30.008070 ANA top config
7129 06:51:30.010933 ===================================
7130 06:51:30.013937 DLL_ASYNC_EN = 0
7131 06:51:30.017315 ALL_SLAVE_EN = 0
7132 06:51:30.020405 NEW_RANK_MODE = 1
7133 06:51:30.023731 DLL_IDLE_MODE = 1
7134 06:51:30.024129 LP45_APHY_COMB_EN = 1
7135 06:51:30.027287 TX_ODT_DIS = 0
7136 06:51:30.030586 NEW_8X_MODE = 1
7137 06:51:30.034043 ===================================
7138 06:51:30.037139 ===================================
7139 06:51:30.040369 data_rate = 3200
7140 06:51:30.043655 CKR = 1
7141 06:51:30.044095 DQ_P2S_RATIO = 8
7142 06:51:30.046989 ===================================
7143 06:51:30.050541 CA_P2S_RATIO = 8
7144 06:51:30.053240 DQ_CA_OPEN = 0
7145 06:51:30.056788 DQ_SEMI_OPEN = 0
7146 06:51:30.060936 CA_SEMI_OPEN = 0
7147 06:51:30.063324 CA_FULL_RATE = 0
7148 06:51:30.063790 DQ_CKDIV4_EN = 0
7149 06:51:30.067209 CA_CKDIV4_EN = 0
7150 06:51:30.069721 CA_PREDIV_EN = 0
7151 06:51:30.073333 PH8_DLY = 12
7152 06:51:30.076724 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7153 06:51:30.079674 DQ_AAMCK_DIV = 4
7154 06:51:30.083461 CA_AAMCK_DIV = 4
7155 06:51:30.083900 CA_ADMCK_DIV = 4
7156 06:51:30.086482 DQ_TRACK_CA_EN = 0
7157 06:51:30.089904 CA_PICK = 1600
7158 06:51:30.093242 CA_MCKIO = 1600
7159 06:51:30.096446 MCKIO_SEMI = 0
7160 06:51:30.099868 PLL_FREQ = 3068
7161 06:51:30.103144 DQ_UI_PI_RATIO = 32
7162 06:51:30.106212 CA_UI_PI_RATIO = 0
7163 06:51:30.109267 ===================================
7164 06:51:30.112487 ===================================
7165 06:51:30.112904 memory_type:LPDDR4
7166 06:51:30.116394 GP_NUM : 10
7167 06:51:30.116861 SRAM_EN : 1
7168 06:51:30.119460 MD32_EN : 0
7169 06:51:30.122805 ===================================
7170 06:51:30.126297 [ANA_INIT] >>>>>>>>>>>>>>
7171 06:51:30.129396 <<<<<< [CONFIGURE PHASE]: ANA_TX
7172 06:51:30.132441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7173 06:51:30.135283 ===================================
7174 06:51:30.138558 data_rate = 3200,PCW = 0X7600
7175 06:51:30.142282 ===================================
7176 06:51:30.145341 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7177 06:51:30.148778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7178 06:51:30.155027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7179 06:51:30.158981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7180 06:51:30.161991 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7181 06:51:30.164962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7182 06:51:30.168519 [ANA_INIT] flow start
7183 06:51:30.171828 [ANA_INIT] PLL >>>>>>>>
7184 06:51:30.171909 [ANA_INIT] PLL <<<<<<<<
7185 06:51:30.175256 [ANA_INIT] MIDPI >>>>>>>>
7186 06:51:30.177920 [ANA_INIT] MIDPI <<<<<<<<
7187 06:51:30.181290 [ANA_INIT] DLL >>>>>>>>
7188 06:51:30.181371 [ANA_INIT] DLL <<<<<<<<
7189 06:51:30.185413 [ANA_INIT] flow end
7190 06:51:30.187925 ============ LP4 DIFF to SE enter ============
7191 06:51:30.191566 ============ LP4 DIFF to SE exit ============
7192 06:51:30.194701 [ANA_INIT] <<<<<<<<<<<<<
7193 06:51:30.197828 [Flow] Enable top DCM control >>>>>
7194 06:51:30.201153 [Flow] Enable top DCM control <<<<<
7195 06:51:30.204568 Enable DLL master slave shuffle
7196 06:51:30.211700 ==============================================================
7197 06:51:30.211782 Gating Mode config
7198 06:51:30.218404 ==============================================================
7199 06:51:30.218486 Config description:
7200 06:51:30.228111 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7201 06:51:30.235252 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7202 06:51:30.241599 SELPH_MODE 0: By rank 1: By Phase
7203 06:51:30.244323 ==============================================================
7204 06:51:30.248186 GAT_TRACK_EN = 1
7205 06:51:30.251262 RX_GATING_MODE = 2
7206 06:51:30.254159 RX_GATING_TRACK_MODE = 2
7207 06:51:30.257600 SELPH_MODE = 1
7208 06:51:30.260854 PICG_EARLY_EN = 1
7209 06:51:30.264324 VALID_LAT_VALUE = 1
7210 06:51:30.270843 ==============================================================
7211 06:51:30.273982 Enter into Gating configuration >>>>
7212 06:51:30.278052 Exit from Gating configuration <<<<
7213 06:51:30.280556 Enter into DVFS_PRE_config >>>>>
7214 06:51:30.290641 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7215 06:51:30.293900 Exit from DVFS_PRE_config <<<<<
7216 06:51:30.296980 Enter into PICG configuration >>>>
7217 06:51:30.300503 Exit from PICG configuration <<<<
7218 06:51:30.303931 [RX_INPUT] configuration >>>>>
7219 06:51:30.304012 [RX_INPUT] configuration <<<<<
7220 06:51:30.310441 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7221 06:51:30.317082 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7222 06:51:30.320341 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7223 06:51:30.326966 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7224 06:51:30.333397 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7225 06:51:30.340181 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7226 06:51:30.343205 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7227 06:51:30.346950 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7228 06:51:30.353290 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7229 06:51:30.356559 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7230 06:51:30.360211 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7231 06:51:30.366280 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 06:51:30.369515 ===================================
7233 06:51:30.369597 LPDDR4 DRAM CONFIGURATION
7234 06:51:30.372559 ===================================
7235 06:51:30.376249 EX_ROW_EN[0] = 0x0
7236 06:51:30.379350 EX_ROW_EN[1] = 0x0
7237 06:51:30.379457 LP4Y_EN = 0x0
7238 06:51:30.382754 WORK_FSP = 0x1
7239 06:51:30.382834 WL = 0x5
7240 06:51:30.386232 RL = 0x5
7241 06:51:30.386313 BL = 0x2
7242 06:51:30.389733 RPST = 0x0
7243 06:51:30.389813 RD_PRE = 0x0
7244 06:51:30.392603 WR_PRE = 0x1
7245 06:51:30.392683 WR_PST = 0x1
7246 06:51:30.395585 DBI_WR = 0x0
7247 06:51:30.395666 DBI_RD = 0x0
7248 06:51:30.398740 OTF = 0x1
7249 06:51:30.402496 ===================================
7250 06:51:30.405295 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7251 06:51:30.409403 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7252 06:51:30.415490 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7253 06:51:30.418651 ===================================
7254 06:51:30.422890 LPDDR4 DRAM CONFIGURATION
7255 06:51:30.422971 ===================================
7256 06:51:30.425554 EX_ROW_EN[0] = 0x10
7257 06:51:30.428686 EX_ROW_EN[1] = 0x0
7258 06:51:30.428766 LP4Y_EN = 0x0
7259 06:51:30.432538 WORK_FSP = 0x1
7260 06:51:30.432618 WL = 0x5
7261 06:51:30.435272 RL = 0x5
7262 06:51:30.435405 BL = 0x2
7263 06:51:30.438533 RPST = 0x0
7264 06:51:30.438619 RD_PRE = 0x0
7265 06:51:30.445471 WR_PRE = 0x1
7266 06:51:30.445572 WR_PST = 0x1
7267 06:51:30.445652 DBI_WR = 0x0
7268 06:51:30.445726 DBI_RD = 0x0
7269 06:51:30.448170 OTF = 0x1
7270 06:51:30.452459 ===================================
7271 06:51:30.458456 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7272 06:51:30.458656 ==
7273 06:51:30.461989 Dram Type= 6, Freq= 0, CH_0, rank 0
7274 06:51:30.465247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7275 06:51:30.465666 ==
7276 06:51:30.468276 [Duty_Offset_Calibration]
7277 06:51:30.468691 B0:2 B1:0 CA:4
7278 06:51:30.472010
7279 06:51:30.474703 [DutyScan_Calibration_Flow] k_type=0
7280 06:51:30.482009
7281 06:51:30.482090 ==CLK 0==
7282 06:51:30.485280 Final CLK duty delay cell = -4
7283 06:51:30.488374 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7284 06:51:30.491673 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7285 06:51:30.494831 [-4] AVG Duty = 4937%(X100)
7286 06:51:30.494913
7287 06:51:30.498258 CH0 CLK Duty spec in!! Max-Min= 187%
7288 06:51:30.501572 [DutyScan_Calibration_Flow] ====Done====
7289 06:51:30.501679
7290 06:51:30.504658 [DutyScan_Calibration_Flow] k_type=1
7291 06:51:30.522426
7292 06:51:30.522509 ==DQS 0 ==
7293 06:51:30.525511 Final DQS duty delay cell = 0
7294 06:51:30.528642 [0] MAX Duty = 5218%(X100), DQS PI = 22
7295 06:51:30.532189 [0] MIN Duty = 5093%(X100), DQS PI = 8
7296 06:51:30.535351 [0] AVG Duty = 5155%(X100)
7297 06:51:30.535447
7298 06:51:30.535516 ==DQS 1 ==
7299 06:51:30.538967 Final DQS duty delay cell = 0
7300 06:51:30.541895 [0] MAX Duty = 5187%(X100), DQS PI = 46
7301 06:51:30.545438 [0] MIN Duty = 4969%(X100), DQS PI = 12
7302 06:51:30.548661 [0] AVG Duty = 5078%(X100)
7303 06:51:30.548828
7304 06:51:30.551914 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7305 06:51:30.552061
7306 06:51:30.555076 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7307 06:51:30.558500 [DutyScan_Calibration_Flow] ====Done====
7308 06:51:30.558582
7309 06:51:30.561929 [DutyScan_Calibration_Flow] k_type=3
7310 06:51:30.579769
7311 06:51:30.579878 ==DQM 0 ==
7312 06:51:30.582961 Final DQM duty delay cell = 0
7313 06:51:30.586338 [0] MAX Duty = 5124%(X100), DQS PI = 20
7314 06:51:30.588970 [0] MIN Duty = 4875%(X100), DQS PI = 54
7315 06:51:30.592381 [0] AVG Duty = 4999%(X100)
7316 06:51:30.592462
7317 06:51:30.592527 ==DQM 1 ==
7318 06:51:30.595891 Final DQM duty delay cell = 0
7319 06:51:30.599539 [0] MAX Duty = 5000%(X100), DQS PI = 2
7320 06:51:30.602366 [0] MIN Duty = 4844%(X100), DQS PI = 16
7321 06:51:30.605837 [0] AVG Duty = 4922%(X100)
7322 06:51:30.605919
7323 06:51:30.609190 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7324 06:51:30.609272
7325 06:51:30.612720 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7326 06:51:30.615845 [DutyScan_Calibration_Flow] ====Done====
7327 06:51:30.615927
7328 06:51:30.619306 [DutyScan_Calibration_Flow] k_type=2
7329 06:51:30.637794
7330 06:51:30.638303 ==DQ 0 ==
7331 06:51:30.640267 Final DQ duty delay cell = 0
7332 06:51:30.643203 [0] MAX Duty = 5156%(X100), DQS PI = 22
7333 06:51:30.646895 [0] MIN Duty = 4938%(X100), DQS PI = 12
7334 06:51:30.647316 [0] AVG Duty = 5047%(X100)
7335 06:51:30.650058
7336 06:51:30.650493 ==DQ 1 ==
7337 06:51:30.653235 Final DQ duty delay cell = 0
7338 06:51:30.657054 [0] MAX Duty = 5187%(X100), DQS PI = 2
7339 06:51:30.660170 [0] MIN Duty = 4938%(X100), DQS PI = 12
7340 06:51:30.660595 [0] AVG Duty = 5062%(X100)
7341 06:51:30.663591
7342 06:51:30.666354 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7343 06:51:30.666776
7344 06:51:30.669423 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7345 06:51:30.672512 [DutyScan_Calibration_Flow] ====Done====
7346 06:51:30.672593 ==
7347 06:51:30.676078 Dram Type= 6, Freq= 0, CH_1, rank 0
7348 06:51:30.679135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7349 06:51:30.679218 ==
7350 06:51:30.682517 [Duty_Offset_Calibration]
7351 06:51:30.682598 B0:0 B1:-1 CA:3
7352 06:51:30.682663
7353 06:51:30.686074 [DutyScan_Calibration_Flow] k_type=0
7354 06:51:30.697290
7355 06:51:30.697812 ==CLK 0==
7356 06:51:30.700413 Final CLK duty delay cell = 0
7357 06:51:30.703537 [0] MAX Duty = 5187%(X100), DQS PI = 4
7358 06:51:30.706827 [0] MIN Duty = 5000%(X100), DQS PI = 54
7359 06:51:30.710144 [0] AVG Duty = 5093%(X100)
7360 06:51:30.710743
7361 06:51:30.713669 CH1 CLK Duty spec in!! Max-Min= 187%
7362 06:51:30.716593 [DutyScan_Calibration_Flow] ====Done====
7363 06:51:30.717078
7364 06:51:30.719886 [DutyScan_Calibration_Flow] k_type=1
7365 06:51:30.736155
7366 06:51:30.736455 ==DQS 0 ==
7367 06:51:30.739415 Final DQS duty delay cell = 0
7368 06:51:30.742059 [0] MAX Duty = 5250%(X100), DQS PI = 30
7369 06:51:30.746154 [0] MIN Duty = 4907%(X100), DQS PI = 58
7370 06:51:30.748744 [0] AVG Duty = 5078%(X100)
7371 06:51:30.749070
7372 06:51:30.749326 ==DQS 1 ==
7373 06:51:30.752210 Final DQS duty delay cell = -4
7374 06:51:30.755571 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7375 06:51:30.758556 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7376 06:51:30.762184 [-4] AVG Duty = 4922%(X100)
7377 06:51:30.762677
7378 06:51:30.765459 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7379 06:51:30.765871
7380 06:51:30.768653 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7381 06:51:30.772168 [DutyScan_Calibration_Flow] ====Done====
7382 06:51:30.772659
7383 06:51:30.775232 [DutyScan_Calibration_Flow] k_type=3
7384 06:51:30.793081
7385 06:51:30.793651 ==DQM 0 ==
7386 06:51:30.796995 Final DQM duty delay cell = 0
7387 06:51:30.800188 [0] MAX Duty = 5062%(X100), DQS PI = 30
7388 06:51:30.802905 [0] MIN Duty = 4782%(X100), DQS PI = 38
7389 06:51:30.806759 [0] AVG Duty = 4922%(X100)
7390 06:51:30.807427
7391 06:51:30.808082 ==DQM 1 ==
7392 06:51:30.810245 Final DQM duty delay cell = 0
7393 06:51:30.812872 [0] MAX Duty = 5000%(X100), DQS PI = 30
7394 06:51:30.816186 [0] MIN Duty = 4813%(X100), DQS PI = 0
7395 06:51:30.819210 [0] AVG Duty = 4906%(X100)
7396 06:51:30.819829
7397 06:51:30.822587 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7398 06:51:30.823042
7399 06:51:30.826142 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7400 06:51:30.829085 [DutyScan_Calibration_Flow] ====Done====
7401 06:51:30.829556
7402 06:51:30.832357 [DutyScan_Calibration_Flow] k_type=2
7403 06:51:30.849618
7404 06:51:30.850169 ==DQ 0 ==
7405 06:51:30.852856 Final DQ duty delay cell = -4
7406 06:51:30.855758 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7407 06:51:30.859840 [-4] MIN Duty = 4813%(X100), DQS PI = 22
7408 06:51:30.862674 [-4] AVG Duty = 4891%(X100)
7409 06:51:30.863246
7410 06:51:30.863630 ==DQ 1 ==
7411 06:51:30.865810 Final DQ duty delay cell = 0
7412 06:51:30.869192 [0] MAX Duty = 5062%(X100), DQS PI = 32
7413 06:51:30.872100 [0] MIN Duty = 4875%(X100), DQS PI = 0
7414 06:51:30.875451 [0] AVG Duty = 4968%(X100)
7415 06:51:30.875923
7416 06:51:30.878540 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7417 06:51:30.878980
7418 06:51:30.881902 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7419 06:51:30.885387 [DutyScan_Calibration_Flow] ====Done====
7420 06:51:30.888780 nWR fixed to 30
7421 06:51:30.891871 [ModeRegInit_LP4] CH0 RK0
7422 06:51:30.892360 [ModeRegInit_LP4] CH0 RK1
7423 06:51:30.895073 [ModeRegInit_LP4] CH1 RK0
7424 06:51:30.898501 [ModeRegInit_LP4] CH1 RK1
7425 06:51:30.899046 match AC timing 5
7426 06:51:30.904792 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7427 06:51:30.908196 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7428 06:51:30.911314 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7429 06:51:30.918377 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7430 06:51:30.921263 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7431 06:51:30.925632 [MiockJmeterHQA]
7432 06:51:30.926198
7433 06:51:30.928571 [DramcMiockJmeter] u1RxGatingPI = 0
7434 06:51:30.929077 0 : 4363, 4137
7435 06:51:30.929408 4 : 4253, 4027
7436 06:51:30.931272 8 : 4363, 4137
7437 06:51:30.931749 12 : 4363, 4137
7438 06:51:30.934977 16 : 4250, 4024
7439 06:51:30.935542 20 : 4363, 4138
7440 06:51:30.937854 24 : 4252, 4026
7441 06:51:30.938334 28 : 4252, 4027
7442 06:51:30.938671 32 : 4252, 4027
7443 06:51:30.941428 36 : 4255, 4029
7444 06:51:30.941984 40 : 4252, 4027
7445 06:51:30.945038 44 : 4253, 4026
7446 06:51:30.945701 48 : 4365, 4140
7447 06:51:30.947814 52 : 4253, 4027
7448 06:51:30.948332 56 : 4255, 4029
7449 06:51:30.951118 60 : 4250, 4027
7450 06:51:30.951648 64 : 4361, 4137
7451 06:51:30.952074 68 : 4250, 4026
7452 06:51:30.954606 72 : 4360, 4138
7453 06:51:30.955111 76 : 4250, 4026
7454 06:51:30.957942 80 : 4250, 4027
7455 06:51:30.958376 84 : 4249, 4027
7456 06:51:30.961618 88 : 4253, 4029
7457 06:51:30.962078 92 : 4361, 4137
7458 06:51:30.964619 96 : 4250, 3064
7459 06:51:30.965128 100 : 4360, 0
7460 06:51:30.965546 104 : 4250, 0
7461 06:51:30.967737 108 : 4253, 0
7462 06:51:30.968218 112 : 4250, 0
7463 06:51:30.970842 116 : 4253, 0
7464 06:51:30.971298 120 : 4249, 0
7465 06:51:30.971750 124 : 4250, 0
7466 06:51:30.974865 128 : 4252, 0
7467 06:51:30.975414 132 : 4360, 0
7468 06:51:30.975828 136 : 4250, 0
7469 06:51:30.977473 140 : 4250, 0
7470 06:51:30.977948 144 : 4361, 0
7471 06:51:30.980833 148 : 4361, 0
7472 06:51:30.981412 152 : 4363, 0
7473 06:51:30.981845 156 : 4250, 0
7474 06:51:30.984192 160 : 4360, 0
7475 06:51:30.984665 164 : 4361, 0
7476 06:51:30.987722 168 : 4250, 0
7477 06:51:30.988077 172 : 4252, 0
7478 06:51:30.988384 176 : 4250, 0
7479 06:51:30.990884 180 : 4253, 0
7480 06:51:30.991207 184 : 4250, 0
7481 06:51:30.993780 188 : 4360, 0
7482 06:51:30.994076 192 : 4250, 0
7483 06:51:30.994311 196 : 4361, 0
7484 06:51:30.997410 200 : 4361, 0
7485 06:51:30.997757 204 : 4363, 0
7486 06:51:31.001107 208 : 4250, 0
7487 06:51:31.001399 212 : 4250, 0
7488 06:51:31.001632 216 : 4363, 0
7489 06:51:31.004731 220 : 4250, 545
7490 06:51:31.005055 224 : 4250, 3984
7491 06:51:31.007062 228 : 4252, 4030
7492 06:51:31.007485 232 : 4250, 4026
7493 06:51:31.011144 236 : 4253, 4029
7494 06:51:31.011475 240 : 4250, 4027
7495 06:51:31.013462 244 : 4361, 4137
7496 06:51:31.013844 248 : 4362, 4137
7497 06:51:31.016909 252 : 4250, 4026
7498 06:51:31.017255 256 : 4363, 4140
7499 06:51:31.017516 260 : 4361, 4137
7500 06:51:31.020599 264 : 4250, 4027
7501 06:51:31.020997 268 : 4250, 4026
7502 06:51:31.023539 272 : 4253, 4029
7503 06:51:31.023868 276 : 4250, 4027
7504 06:51:31.027046 280 : 4249, 4027
7505 06:51:31.027429 284 : 4250, 4026
7506 06:51:31.030057 288 : 4253, 4029
7507 06:51:31.030138 292 : 4250, 4027
7508 06:51:31.033010 296 : 4360, 4138
7509 06:51:31.033084 300 : 4360, 4137
7510 06:51:31.036782 304 : 4250, 4026
7511 06:51:31.036856 308 : 4363, 4140
7512 06:51:31.039827 312 : 4250, 4027
7513 06:51:31.039910 316 : 4249, 4027
7514 06:51:31.043046 320 : 4250, 4026
7515 06:51:31.043162 324 : 4253, 4029
7516 06:51:31.046570 328 : 4250, 4027
7517 06:51:31.046645 332 : 4249, 4004
7518 06:51:31.046707 336 : 4250, 1867
7519 06:51:31.049235
7520 06:51:31.049315 MIOCK jitter meter ch=0
7521 06:51:31.049376
7522 06:51:31.052546 1T = (336-100) = 236 dly cells
7523 06:51:31.059655 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7524 06:51:31.059731 ==
7525 06:51:31.062889 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 06:51:31.065759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 06:51:31.065839 ==
7528 06:51:31.072452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 06:51:31.076111 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 06:51:31.079178 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 06:51:31.085929 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 06:51:31.095599 [CA 0] Center 43 (13~74) winsize 62
7533 06:51:31.099254 [CA 1] Center 42 (12~73) winsize 62
7534 06:51:31.102022 [CA 2] Center 37 (8~67) winsize 60
7535 06:51:31.105205 [CA 3] Center 37 (8~67) winsize 60
7536 06:51:31.108651 [CA 4] Center 36 (6~66) winsize 61
7537 06:51:31.111830 [CA 5] Center 35 (5~66) winsize 62
7538 06:51:31.111903
7539 06:51:31.115038 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 06:51:31.115110
7541 06:51:31.118262 [CATrainingPosCal] consider 1 rank data
7542 06:51:31.121912 u2DelayCellTimex100 = 275/100 ps
7543 06:51:31.128131 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7544 06:51:31.131511 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7545 06:51:31.135001 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7546 06:51:31.138049 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7547 06:51:31.141803 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7548 06:51:31.144673 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7549 06:51:31.144748
7550 06:51:31.147983 CA PerBit enable=1, Macro0, CA PI delay=35
7551 06:51:31.148053
7552 06:51:31.151551 [CBTSetCACLKResult] CA Dly = 35
7553 06:51:31.154622 CS Dly: 11 (0~42)
7554 06:51:31.158483 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 06:51:31.161450 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 06:51:31.161544 ==
7557 06:51:31.164344 Dram Type= 6, Freq= 0, CH_0, rank 1
7558 06:51:31.171045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 06:51:31.171155 ==
7560 06:51:31.174190 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7561 06:51:31.181081 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7562 06:51:31.184227 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7563 06:51:31.191462 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7564 06:51:31.198976 [CA 0] Center 43 (13~74) winsize 62
7565 06:51:31.202224 [CA 1] Center 43 (13~73) winsize 61
7566 06:51:31.205417 [CA 2] Center 38 (9~68) winsize 60
7567 06:51:31.208838 [CA 3] Center 38 (9~68) winsize 60
7568 06:51:31.212406 [CA 4] Center 36 (6~67) winsize 62
7569 06:51:31.215467 [CA 5] Center 36 (6~66) winsize 61
7570 06:51:31.215541
7571 06:51:31.218495 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7572 06:51:31.218568
7573 06:51:31.225123 [CATrainingPosCal] consider 2 rank data
7574 06:51:31.225205 u2DelayCellTimex100 = 275/100 ps
7575 06:51:31.231367 CA0 delay=43 (13~74),Diff = 7 PI (24 cell)
7576 06:51:31.235169 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7577 06:51:31.239168 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7578 06:51:31.241433 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7579 06:51:31.245430 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7580 06:51:31.248251 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7581 06:51:31.248363
7582 06:51:31.251155 CA PerBit enable=1, Macro0, CA PI delay=36
7583 06:51:31.251336
7584 06:51:31.254453 [CBTSetCACLKResult] CA Dly = 36
7585 06:51:31.257789 CS Dly: 12 (0~44)
7586 06:51:31.261183 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7587 06:51:31.264415 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7588 06:51:31.264578
7589 06:51:31.268001 ----->DramcWriteLeveling(PI) begin...
7590 06:51:31.271217 ==
7591 06:51:31.271537 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 06:51:31.277546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 06:51:31.277870 ==
7594 06:51:31.281174 Write leveling (Byte 0): 34 => 34
7595 06:51:31.284406 Write leveling (Byte 1): 26 => 26
7596 06:51:31.287658 DramcWriteLeveling(PI) end<-----
7597 06:51:31.288114
7598 06:51:31.288427 ==
7599 06:51:31.290982 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 06:51:31.294692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 06:51:31.295173 ==
7602 06:51:31.297584 [Gating] SW mode calibration
7603 06:51:31.304433 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7604 06:51:31.310597 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7605 06:51:31.314174 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 06:51:31.317584 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 06:51:31.323812 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 06:51:31.327521 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7609 06:51:31.330408 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7610 06:51:31.336869 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7611 06:51:31.340891 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 06:51:31.343668 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 06:51:31.350211 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 06:51:31.353698 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7615 06:51:31.356997 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
7616 06:51:31.363762 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
7617 06:51:31.366563 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7618 06:51:31.370652 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7619 06:51:31.376538 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 06:51:31.380129 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 06:51:31.383056 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 06:51:31.389545 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 06:51:31.393185 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7624 06:51:31.396592 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7625 06:51:31.403330 1 6 16 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
7626 06:51:31.406555 1 6 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7627 06:51:31.409502 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 06:51:31.415837 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 06:51:31.419035 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 06:51:31.422492 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 06:51:31.430076 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 06:51:31.432343 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7633 06:51:31.436055 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7634 06:51:31.442688 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7635 06:51:31.445456 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 06:51:31.448775 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 06:51:31.455152 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 06:51:31.458365 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 06:51:31.461993 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 06:51:31.468384 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 06:51:31.471674 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 06:51:31.474852 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 06:51:31.481868 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 06:51:31.485225 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 06:51:31.488595 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 06:51:31.495204 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 06:51:31.498506 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 06:51:31.501918 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7649 06:51:31.505490 Total UI for P1: 0, mck2ui 16
7650 06:51:31.508928 best dqsien dly found for B0: ( 1, 9, 10)
7651 06:51:31.515077 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7652 06:51:31.518145 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7653 06:51:31.521691 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 06:51:31.524603 Total UI for P1: 0, mck2ui 16
7655 06:51:31.528114 best dqsien dly found for B1: ( 1, 9, 20)
7656 06:51:31.531427 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7657 06:51:31.534950 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7658 06:51:31.535505
7659 06:51:31.541625 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7660 06:51:31.544979 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7661 06:51:31.548265 [Gating] SW calibration Done
7662 06:51:31.548657 ==
7663 06:51:31.551111 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 06:51:31.554939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 06:51:31.555503 ==
7666 06:51:31.555944 RX Vref Scan: 0
7667 06:51:31.557801
7668 06:51:31.558311 RX Vref 0 -> 0, step: 1
7669 06:51:31.558922
7670 06:51:31.560895 RX Delay 0 -> 252, step: 8
7671 06:51:31.564574 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7672 06:51:31.567630 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7673 06:51:31.574202 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7674 06:51:31.577678 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7675 06:51:31.581071 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7676 06:51:31.584839 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7677 06:51:31.587700 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7678 06:51:31.594521 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7679 06:51:31.597654 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7680 06:51:31.600373 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7681 06:51:31.603918 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7682 06:51:31.607452 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7683 06:51:31.613732 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7684 06:51:31.617153 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7685 06:51:31.620458 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7686 06:51:31.624139 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7687 06:51:31.624661 ==
7688 06:51:31.627062 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 06:51:31.633404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 06:51:31.633915 ==
7691 06:51:31.634313 DQS Delay:
7692 06:51:31.637325 DQS0 = 0, DQS1 = 0
7693 06:51:31.637791 DQM Delay:
7694 06:51:31.640292 DQM0 = 131, DQM1 = 125
7695 06:51:31.640788 DQ Delay:
7696 06:51:31.643750 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7697 06:51:31.646730 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7698 06:51:31.649914 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7699 06:51:31.653490 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7700 06:51:31.653903
7701 06:51:31.654227
7702 06:51:31.654529 ==
7703 06:51:31.656928 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 06:51:31.663239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 06:51:31.663739 ==
7706 06:51:31.664097
7707 06:51:31.664406
7708 06:51:31.664699 TX Vref Scan disable
7709 06:51:31.666913 == TX Byte 0 ==
7710 06:51:31.670784 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7711 06:51:31.676888 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7712 06:51:31.677340 == TX Byte 1 ==
7713 06:51:31.680140 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7714 06:51:31.686436 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7715 06:51:31.686910 ==
7716 06:51:31.689895 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 06:51:31.692922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 06:51:31.693420 ==
7719 06:51:31.706417
7720 06:51:31.709522 TX Vref early break, caculate TX vref
7721 06:51:31.712644 TX Vref=16, minBit 4, minWin=22, winSum=370
7722 06:51:31.716269 TX Vref=18, minBit 1, minWin=23, winSum=379
7723 06:51:31.719444 TX Vref=20, minBit 1, minWin=23, winSum=384
7724 06:51:31.722778 TX Vref=22, minBit 1, minWin=24, winSum=401
7725 06:51:31.725883 TX Vref=24, minBit 7, minWin=24, winSum=408
7726 06:51:31.732546 TX Vref=26, minBit 4, minWin=25, winSum=417
7727 06:51:31.735859 TX Vref=28, minBit 4, minWin=25, winSum=422
7728 06:51:31.739420 TX Vref=30, minBit 1, minWin=25, winSum=419
7729 06:51:31.742883 TX Vref=32, minBit 4, minWin=24, winSum=408
7730 06:51:31.746134 TX Vref=34, minBit 0, minWin=24, winSum=397
7731 06:51:31.752360 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
7732 06:51:31.752783
7733 06:51:31.755664 Final TX Range 0 Vref 28
7734 06:51:31.756086
7735 06:51:31.756414 ==
7736 06:51:31.759054 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 06:51:31.762213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 06:51:31.762635 ==
7739 06:51:31.762962
7740 06:51:31.765326
7741 06:51:31.765743 TX Vref Scan disable
7742 06:51:31.771832 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7743 06:51:31.772267 == TX Byte 0 ==
7744 06:51:31.775013 u2DelayCellOfst[0]=14 cells (4 PI)
7745 06:51:31.778824 u2DelayCellOfst[1]=17 cells (5 PI)
7746 06:51:31.781678 u2DelayCellOfst[2]=14 cells (4 PI)
7747 06:51:31.785309 u2DelayCellOfst[3]=14 cells (4 PI)
7748 06:51:31.788664 u2DelayCellOfst[4]=10 cells (3 PI)
7749 06:51:31.792537 u2DelayCellOfst[5]=0 cells (0 PI)
7750 06:51:31.795273 u2DelayCellOfst[6]=17 cells (5 PI)
7751 06:51:31.798650 u2DelayCellOfst[7]=17 cells (5 PI)
7752 06:51:31.802143 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7753 06:51:31.804959 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7754 06:51:31.808254 == TX Byte 1 ==
7755 06:51:31.811929 u2DelayCellOfst[8]=0 cells (0 PI)
7756 06:51:31.815068 u2DelayCellOfst[9]=0 cells (0 PI)
7757 06:51:31.818183 u2DelayCellOfst[10]=3 cells (1 PI)
7758 06:51:31.821494 u2DelayCellOfst[11]=0 cells (0 PI)
7759 06:51:31.824941 u2DelayCellOfst[12]=7 cells (2 PI)
7760 06:51:31.825425 u2DelayCellOfst[13]=10 cells (3 PI)
7761 06:51:31.828129 u2DelayCellOfst[14]=14 cells (4 PI)
7762 06:51:31.831554 u2DelayCellOfst[15]=10 cells (3 PI)
7763 06:51:31.837841 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7764 06:51:31.841779 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7765 06:51:31.842319 DramC Write-DBI on
7766 06:51:31.844626 ==
7767 06:51:31.847816 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 06:51:31.851123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 06:51:31.851991 ==
7770 06:51:31.852551
7771 06:51:31.852946
7772 06:51:31.854841 TX Vref Scan disable
7773 06:51:31.855625 == TX Byte 0 ==
7774 06:51:31.860975 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7775 06:51:31.861539 == TX Byte 1 ==
7776 06:51:31.864223 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7777 06:51:31.867495 DramC Write-DBI off
7778 06:51:31.867940
7779 06:51:31.868266 [DATLAT]
7780 06:51:31.870729 Freq=1600, CH0 RK0
7781 06:51:31.871222
7782 06:51:31.871715 DATLAT Default: 0xf
7783 06:51:31.874534 0, 0xFFFF, sum = 0
7784 06:51:31.874955 1, 0xFFFF, sum = 0
7785 06:51:31.877870 2, 0xFFFF, sum = 0
7786 06:51:31.880604 3, 0xFFFF, sum = 0
7787 06:51:31.881023 4, 0xFFFF, sum = 0
7788 06:51:31.884181 5, 0xFFFF, sum = 0
7789 06:51:31.884599 6, 0xFFFF, sum = 0
7790 06:51:31.887133 7, 0xFFFF, sum = 0
7791 06:51:31.887693 8, 0xFFFF, sum = 0
7792 06:51:31.890573 9, 0xFFFF, sum = 0
7793 06:51:31.890991 10, 0xFFFF, sum = 0
7794 06:51:31.893546 11, 0xFFFF, sum = 0
7795 06:51:31.894048 12, 0xFFFF, sum = 0
7796 06:51:31.897332 13, 0xFFFF, sum = 0
7797 06:51:31.897844 14, 0x0, sum = 1
7798 06:51:31.900685 15, 0x0, sum = 2
7799 06:51:31.901186 16, 0x0, sum = 3
7800 06:51:31.903911 17, 0x0, sum = 4
7801 06:51:31.904351 best_step = 15
7802 06:51:31.904686
7803 06:51:31.904995 ==
7804 06:51:31.907028 Dram Type= 6, Freq= 0, CH_0, rank 0
7805 06:51:31.913329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7806 06:51:31.913750 ==
7807 06:51:31.914138 RX Vref Scan: 1
7808 06:51:31.914469
7809 06:51:31.916939 Set Vref Range= 24 -> 127
7810 06:51:31.917354
7811 06:51:31.920274 RX Vref 24 -> 127, step: 1
7812 06:51:31.920692
7813 06:51:31.923482 RX Delay 11 -> 252, step: 4
7814 06:51:31.923901
7815 06:51:31.926403 Set Vref, RX VrefLevel [Byte0]: 24
7816 06:51:31.926821 [Byte1]: 24
7817 06:51:31.930844
7818 06:51:31.931257 Set Vref, RX VrefLevel [Byte0]: 25
7819 06:51:31.934569 [Byte1]: 25
7820 06:51:31.938515
7821 06:51:31.938930 Set Vref, RX VrefLevel [Byte0]: 26
7822 06:51:31.941791 [Byte1]: 26
7823 06:51:31.946030
7824 06:51:31.946448 Set Vref, RX VrefLevel [Byte0]: 27
7825 06:51:31.949471 [Byte1]: 27
7826 06:51:31.953945
7827 06:51:31.954358 Set Vref, RX VrefLevel [Byte0]: 28
7828 06:51:31.957190 [Byte1]: 28
7829 06:51:31.961726
7830 06:51:31.962156 Set Vref, RX VrefLevel [Byte0]: 29
7831 06:51:31.964938 [Byte1]: 29
7832 06:51:31.968946
7833 06:51:31.969372 Set Vref, RX VrefLevel [Byte0]: 30
7834 06:51:31.973167 [Byte1]: 30
7835 06:51:31.977279
7836 06:51:31.977695 Set Vref, RX VrefLevel [Byte0]: 31
7837 06:51:31.980071 [Byte1]: 31
7838 06:51:31.984201
7839 06:51:31.987397 Set Vref, RX VrefLevel [Byte0]: 32
7840 06:51:31.990622 [Byte1]: 32
7841 06:51:31.991036
7842 06:51:31.994196 Set Vref, RX VrefLevel [Byte0]: 33
7843 06:51:31.997519 [Byte1]: 33
7844 06:51:31.997937
7845 06:51:32.000666 Set Vref, RX VrefLevel [Byte0]: 34
7846 06:51:32.004092 [Byte1]: 34
7847 06:51:32.007288
7848 06:51:32.007755 Set Vref, RX VrefLevel [Byte0]: 35
7849 06:51:32.010559 [Byte1]: 35
7850 06:51:32.014784
7851 06:51:32.015199 Set Vref, RX VrefLevel [Byte0]: 36
7852 06:51:32.018500 [Byte1]: 36
7853 06:51:32.022706
7854 06:51:32.023120 Set Vref, RX VrefLevel [Byte0]: 37
7855 06:51:32.025796 [Byte1]: 37
7856 06:51:32.030117
7857 06:51:32.030531 Set Vref, RX VrefLevel [Byte0]: 38
7858 06:51:32.033334 [Byte1]: 38
7859 06:51:32.037291
7860 06:51:32.037704 Set Vref, RX VrefLevel [Byte0]: 39
7861 06:51:32.040696 [Byte1]: 39
7862 06:51:32.044996
7863 06:51:32.045413 Set Vref, RX VrefLevel [Byte0]: 40
7864 06:51:32.048660 [Byte1]: 40
7865 06:51:32.052929
7866 06:51:32.053350 Set Vref, RX VrefLevel [Byte0]: 41
7867 06:51:32.056911 [Byte1]: 41
7868 06:51:32.060833
7869 06:51:32.061250 Set Vref, RX VrefLevel [Byte0]: 42
7870 06:51:32.063546 [Byte1]: 42
7871 06:51:32.068359
7872 06:51:32.068775 Set Vref, RX VrefLevel [Byte0]: 43
7873 06:51:32.071278 [Byte1]: 43
7874 06:51:32.075832
7875 06:51:32.076245 Set Vref, RX VrefLevel [Byte0]: 44
7876 06:51:32.078841 [Byte1]: 44
7877 06:51:32.083430
7878 06:51:32.083845 Set Vref, RX VrefLevel [Byte0]: 45
7879 06:51:32.086314 [Byte1]: 45
7880 06:51:32.090985
7881 06:51:32.091476 Set Vref, RX VrefLevel [Byte0]: 46
7882 06:51:32.094320 [Byte1]: 46
7883 06:51:32.098745
7884 06:51:32.099160 Set Vref, RX VrefLevel [Byte0]: 47
7885 06:51:32.101649 [Byte1]: 47
7886 06:51:32.106037
7887 06:51:32.106452 Set Vref, RX VrefLevel [Byte0]: 48
7888 06:51:32.109311 [Byte1]: 48
7889 06:51:32.113822
7890 06:51:32.114235 Set Vref, RX VrefLevel [Byte0]: 49
7891 06:51:32.116886 [Byte1]: 49
7892 06:51:32.121566
7893 06:51:32.121980 Set Vref, RX VrefLevel [Byte0]: 50
7894 06:51:32.124932 [Byte1]: 50
7895 06:51:32.129071
7896 06:51:32.129497 Set Vref, RX VrefLevel [Byte0]: 51
7897 06:51:32.132158 [Byte1]: 51
7898 06:51:32.136704
7899 06:51:32.137121 Set Vref, RX VrefLevel [Byte0]: 52
7900 06:51:32.139805 [Byte1]: 52
7901 06:51:32.144234
7902 06:51:32.144648 Set Vref, RX VrefLevel [Byte0]: 53
7903 06:51:32.147792 [Byte1]: 53
7904 06:51:32.152090
7905 06:51:32.152508 Set Vref, RX VrefLevel [Byte0]: 54
7906 06:51:32.154970 [Byte1]: 54
7907 06:51:32.159501
7908 06:51:32.159921 Set Vref, RX VrefLevel [Byte0]: 55
7909 06:51:32.162831 [Byte1]: 55
7910 06:51:32.167302
7911 06:51:32.167774 Set Vref, RX VrefLevel [Byte0]: 56
7912 06:51:32.170550 [Byte1]: 56
7913 06:51:32.174701
7914 06:51:32.175155 Set Vref, RX VrefLevel [Byte0]: 57
7915 06:51:32.177995 [Byte1]: 57
7916 06:51:32.182123
7917 06:51:32.182536 Set Vref, RX VrefLevel [Byte0]: 58
7918 06:51:32.186095 [Byte1]: 58
7919 06:51:32.189610
7920 06:51:32.190024 Set Vref, RX VrefLevel [Byte0]: 59
7921 06:51:32.193124 [Byte1]: 59
7922 06:51:32.197834
7923 06:51:32.198245 Set Vref, RX VrefLevel [Byte0]: 60
7924 06:51:32.200633 [Byte1]: 60
7925 06:51:32.205039
7926 06:51:32.205453 Set Vref, RX VrefLevel [Byte0]: 61
7927 06:51:32.208262 [Byte1]: 61
7928 06:51:32.212691
7929 06:51:32.213103 Set Vref, RX VrefLevel [Byte0]: 62
7930 06:51:32.216110 [Byte1]: 62
7931 06:51:32.220314
7932 06:51:32.220729 Set Vref, RX VrefLevel [Byte0]: 63
7933 06:51:32.223899 [Byte1]: 63
7934 06:51:32.228147
7935 06:51:32.228561 Set Vref, RX VrefLevel [Byte0]: 64
7936 06:51:32.230995 [Byte1]: 64
7937 06:51:32.235308
7938 06:51:32.235756 Set Vref, RX VrefLevel [Byte0]: 65
7939 06:51:32.239588 [Byte1]: 65
7940 06:51:32.243161
7941 06:51:32.243593 Set Vref, RX VrefLevel [Byte0]: 66
7942 06:51:32.246256 [Byte1]: 66
7943 06:51:32.251322
7944 06:51:32.251794 Set Vref, RX VrefLevel [Byte0]: 67
7945 06:51:32.254048 [Byte1]: 67
7946 06:51:32.258238
7947 06:51:32.258659 Set Vref, RX VrefLevel [Byte0]: 68
7948 06:51:32.261877 [Byte1]: 68
7949 06:51:32.265721
7950 06:51:32.266142 Set Vref, RX VrefLevel [Byte0]: 69
7951 06:51:32.269041 [Byte1]: 69
7952 06:51:32.274070
7953 06:51:32.274492 Set Vref, RX VrefLevel [Byte0]: 70
7954 06:51:32.276737 [Byte1]: 70
7955 06:51:32.281233
7956 06:51:32.281664 Set Vref, RX VrefLevel [Byte0]: 71
7957 06:51:32.285476 [Byte1]: 71
7958 06:51:32.288684
7959 06:51:32.289110 Set Vref, RX VrefLevel [Byte0]: 72
7960 06:51:32.292008 [Byte1]: 72
7961 06:51:32.296234
7962 06:51:32.296649 Set Vref, RX VrefLevel [Byte0]: 73
7963 06:51:32.299520 [Byte1]: 73
7964 06:51:32.304111
7965 06:51:32.304530 Set Vref, RX VrefLevel [Byte0]: 74
7966 06:51:32.307478 [Byte1]: 74
7967 06:51:32.311543
7968 06:51:32.311969 Final RX Vref Byte 0 = 54 to rank0
7969 06:51:32.315264 Final RX Vref Byte 1 = 59 to rank0
7970 06:51:32.318498 Final RX Vref Byte 0 = 54 to rank1
7971 06:51:32.321576 Final RX Vref Byte 1 = 59 to rank1==
7972 06:51:32.324806 Dram Type= 6, Freq= 0, CH_0, rank 0
7973 06:51:32.331328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7974 06:51:32.331803 ==
7975 06:51:32.332140 DQS Delay:
7976 06:51:32.334916 DQS0 = 0, DQS1 = 0
7977 06:51:32.335333 DQM Delay:
7978 06:51:32.335700 DQM0 = 128, DQM1 = 124
7979 06:51:32.338330 DQ Delay:
7980 06:51:32.341213 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =124
7981 06:51:32.344689 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7982 06:51:32.348264 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7983 06:51:32.351115 DQ12 =132, DQ13 =128, DQ14 =134, DQ15 =130
7984 06:51:32.351676
7985 06:51:32.352012
7986 06:51:32.352323
7987 06:51:32.354975 [DramC_TX_OE_Calibration] TA2
7988 06:51:32.357926 Original DQ_B0 (3 6) =30, OEN = 27
7989 06:51:32.361283 Original DQ_B1 (3 6) =30, OEN = 27
7990 06:51:32.364304 24, 0x0, End_B0=24 End_B1=24
7991 06:51:32.364730 25, 0x0, End_B0=25 End_B1=25
7992 06:51:32.367866 26, 0x0, End_B0=26 End_B1=26
7993 06:51:32.371258 27, 0x0, End_B0=27 End_B1=27
7994 06:51:32.374445 28, 0x0, End_B0=28 End_B1=28
7995 06:51:32.377585 29, 0x0, End_B0=29 End_B1=29
7996 06:51:32.378011 30, 0x0, End_B0=30 End_B1=30
7997 06:51:32.380866 31, 0x4141, End_B0=30 End_B1=30
7998 06:51:32.384258 Byte0 end_step=30 best_step=27
7999 06:51:32.387424 Byte1 end_step=30 best_step=27
8000 06:51:32.390693 Byte0 TX OE(2T, 0.5T) = (3, 3)
8001 06:51:32.394209 Byte1 TX OE(2T, 0.5T) = (3, 3)
8002 06:51:32.394375
8003 06:51:32.394439
8004 06:51:32.400149 [DQSOSCAuto] RK0, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
8005 06:51:32.403391 CH0 RK0: MR19=303, MR18=1815
8006 06:51:32.409894 CH0_RK0: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
8007 06:51:32.409976
8008 06:51:32.413370 ----->DramcWriteLeveling(PI) begin...
8009 06:51:32.413453 ==
8010 06:51:32.416396 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 06:51:32.419743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 06:51:32.419825 ==
8013 06:51:32.423596 Write leveling (Byte 0): 35 => 35
8014 06:51:32.426378 Write leveling (Byte 1): 29 => 29
8015 06:51:32.429892 DramcWriteLeveling(PI) end<-----
8016 06:51:32.429974
8017 06:51:32.430037 ==
8018 06:51:32.433164 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 06:51:32.440340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 06:51:32.440443 ==
8021 06:51:32.440524 [Gating] SW mode calibration
8022 06:51:32.450320 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8023 06:51:32.453036 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8024 06:51:32.460191 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 06:51:32.463490 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 06:51:32.466625 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8027 06:51:32.473011 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8028 06:51:32.476236 1 4 16 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8029 06:51:32.480548 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 06:51:32.483084 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 06:51:32.489808 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 06:51:32.492930 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8033 06:51:32.496279 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8034 06:51:32.502485 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8035 06:51:32.505797 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8036 06:51:32.509423 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8037 06:51:32.516040 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
8038 06:51:32.518980 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 06:51:32.522307 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 06:51:32.529514 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 06:51:32.532216 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
8042 06:51:32.538551 1 6 8 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
8043 06:51:32.541852 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8044 06:51:32.545532 1 6 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8045 06:51:32.551743 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8046 06:51:32.555592 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 06:51:32.558444 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 06:51:32.564964 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 06:51:32.568459 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 06:51:32.572058 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8051 06:51:32.578475 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8052 06:51:32.581441 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8053 06:51:32.584799 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8054 06:51:32.588174 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 06:51:32.594826 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 06:51:32.598168 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 06:51:32.601507 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 06:51:32.608052 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 06:51:32.611842 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 06:51:32.618081 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 06:51:32.620992 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 06:51:32.624312 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 06:51:32.631304 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 06:51:32.634436 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 06:51:32.638008 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8066 06:51:32.644526 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8067 06:51:32.647527 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8068 06:51:32.650949 Total UI for P1: 0, mck2ui 16
8069 06:51:32.654686 best dqsien dly found for B0: ( 1, 9, 6)
8070 06:51:32.658108 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8071 06:51:32.660867 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8072 06:51:32.667420 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 06:51:32.671256 Total UI for P1: 0, mck2ui 16
8074 06:51:32.674365 best dqsien dly found for B1: ( 1, 9, 18)
8075 06:51:32.677653 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8076 06:51:32.680943 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8077 06:51:32.681408
8078 06:51:32.684969 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8079 06:51:32.687401 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8080 06:51:32.690765 [Gating] SW calibration Done
8081 06:51:32.691343 ==
8082 06:51:32.693909 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 06:51:32.697507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 06:51:32.698129 ==
8085 06:51:32.700308 RX Vref Scan: 0
8086 06:51:32.700837
8087 06:51:32.703716 RX Vref 0 -> 0, step: 1
8088 06:51:32.704179
8089 06:51:32.704547 RX Delay 0 -> 252, step: 8
8090 06:51:32.710384 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8091 06:51:32.713776 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8092 06:51:32.717098 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8093 06:51:32.720383 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8094 06:51:32.723483 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8095 06:51:32.729951 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8096 06:51:32.733363 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8097 06:51:32.736287 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8098 06:51:32.739958 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8099 06:51:32.746215 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8100 06:51:32.749393 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8101 06:51:32.752943 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8102 06:51:32.756685 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8103 06:51:32.759125 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8104 06:51:32.765407 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8105 06:51:32.768738 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8106 06:51:32.768820 ==
8107 06:51:32.771967 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 06:51:32.775244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 06:51:32.775341 ==
8110 06:51:32.778839 DQS Delay:
8111 06:51:32.778921 DQS0 = 0, DQS1 = 0
8112 06:51:32.781987 DQM Delay:
8113 06:51:32.782068 DQM0 = 132, DQM1 = 125
8114 06:51:32.782134 DQ Delay:
8115 06:51:32.788378 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8116 06:51:32.791700 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =135
8117 06:51:32.795243 DQ8 =115, DQ9 =111, DQ10 =131, DQ11 =119
8118 06:51:32.798337 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8119 06:51:32.798419
8120 06:51:32.798483
8121 06:51:32.798542 ==
8122 06:51:32.801496 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 06:51:32.805192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 06:51:32.805275 ==
8125 06:51:32.805339
8126 06:51:32.805399
8127 06:51:32.808348 TX Vref Scan disable
8128 06:51:32.811979 == TX Byte 0 ==
8129 06:51:32.815555 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8130 06:51:32.818492 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8131 06:51:32.821673 == TX Byte 1 ==
8132 06:51:32.825143 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8133 06:51:32.828105 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8134 06:51:32.828187 ==
8135 06:51:32.831260 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 06:51:32.837878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 06:51:32.837960 ==
8138 06:51:32.850922
8139 06:51:32.854332 TX Vref early break, caculate TX vref
8140 06:51:32.857753 TX Vref=16, minBit 1, minWin=23, winSum=378
8141 06:51:32.860971 TX Vref=18, minBit 2, minWin=23, winSum=392
8142 06:51:32.864425 TX Vref=20, minBit 2, minWin=24, winSum=400
8143 06:51:32.867328 TX Vref=22, minBit 0, minWin=25, winSum=405
8144 06:51:32.870604 TX Vref=24, minBit 1, minWin=25, winSum=416
8145 06:51:32.877393 TX Vref=26, minBit 3, minWin=25, winSum=421
8146 06:51:32.880540 TX Vref=28, minBit 4, minWin=25, winSum=422
8147 06:51:32.883892 TX Vref=30, minBit 1, minWin=25, winSum=413
8148 06:51:32.887103 TX Vref=32, minBit 6, minWin=24, winSum=405
8149 06:51:32.890892 TX Vref=34, minBit 1, minWin=24, winSum=401
8150 06:51:32.896980 TX Vref=36, minBit 1, minWin=24, winSum=393
8151 06:51:32.900988 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
8152 06:51:32.901101
8153 06:51:32.903984 Final TX Range 0 Vref 28
8154 06:51:32.904066
8155 06:51:32.904131 ==
8156 06:51:32.907285 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 06:51:32.910358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 06:51:32.913436 ==
8159 06:51:32.913536
8160 06:51:32.913626
8161 06:51:32.913713 TX Vref Scan disable
8162 06:51:32.920358 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8163 06:51:32.920459 == TX Byte 0 ==
8164 06:51:32.923963 u2DelayCellOfst[0]=10 cells (3 PI)
8165 06:51:32.926778 u2DelayCellOfst[1]=14 cells (4 PI)
8166 06:51:32.930534 u2DelayCellOfst[2]=10 cells (3 PI)
8167 06:51:32.933317 u2DelayCellOfst[3]=10 cells (3 PI)
8168 06:51:32.936807 u2DelayCellOfst[4]=7 cells (2 PI)
8169 06:51:32.939971 u2DelayCellOfst[5]=0 cells (0 PI)
8170 06:51:32.943241 u2DelayCellOfst[6]=14 cells (4 PI)
8171 06:51:32.946667 u2DelayCellOfst[7]=14 cells (4 PI)
8172 06:51:32.949508 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8173 06:51:32.953109 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8174 06:51:32.956602 == TX Byte 1 ==
8175 06:51:32.959926 u2DelayCellOfst[8]=0 cells (0 PI)
8176 06:51:32.962992 u2DelayCellOfst[9]=0 cells (0 PI)
8177 06:51:32.966150 u2DelayCellOfst[10]=7 cells (2 PI)
8178 06:51:32.969279 u2DelayCellOfst[11]=3 cells (1 PI)
8179 06:51:32.972945 u2DelayCellOfst[12]=10 cells (3 PI)
8180 06:51:32.976226 u2DelayCellOfst[13]=10 cells (3 PI)
8181 06:51:32.979446 u2DelayCellOfst[14]=17 cells (5 PI)
8182 06:51:32.982944 u2DelayCellOfst[15]=10 cells (3 PI)
8183 06:51:32.986005 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8184 06:51:32.989496 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8185 06:51:32.992436 DramC Write-DBI on
8186 06:51:32.992518 ==
8187 06:51:32.995909 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 06:51:32.999109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 06:51:32.999196 ==
8190 06:51:32.999260
8191 06:51:32.999320
8192 06:51:33.002335 TX Vref Scan disable
8193 06:51:33.005746 == TX Byte 0 ==
8194 06:51:33.009173 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8195 06:51:33.009254 == TX Byte 1 ==
8196 06:51:33.015844 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8197 06:51:33.015926 DramC Write-DBI off
8198 06:51:33.015991
8199 06:51:33.016052 [DATLAT]
8200 06:51:33.019279 Freq=1600, CH0 RK1
8201 06:51:33.019366
8202 06:51:33.022328 DATLAT Default: 0xf
8203 06:51:33.022410 0, 0xFFFF, sum = 0
8204 06:51:33.025819 1, 0xFFFF, sum = 0
8205 06:51:33.025902 2, 0xFFFF, sum = 0
8206 06:51:33.029049 3, 0xFFFF, sum = 0
8207 06:51:33.029132 4, 0xFFFF, sum = 0
8208 06:51:33.031902 5, 0xFFFF, sum = 0
8209 06:51:33.031986 6, 0xFFFF, sum = 0
8210 06:51:33.035307 7, 0xFFFF, sum = 0
8211 06:51:33.035415 8, 0xFFFF, sum = 0
8212 06:51:33.039034 9, 0xFFFF, sum = 0
8213 06:51:33.039117 10, 0xFFFF, sum = 0
8214 06:51:33.042156 11, 0xFFFF, sum = 0
8215 06:51:33.042239 12, 0xFFFF, sum = 0
8216 06:51:33.045131 13, 0xFFFF, sum = 0
8217 06:51:33.045214 14, 0x0, sum = 1
8218 06:51:33.048558 15, 0x0, sum = 2
8219 06:51:33.048644 16, 0x0, sum = 3
8220 06:51:33.051697 17, 0x0, sum = 4
8221 06:51:33.051780 best_step = 15
8222 06:51:33.051845
8223 06:51:33.051905 ==
8224 06:51:33.055508 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 06:51:33.061929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 06:51:33.062012 ==
8227 06:51:33.062078 RX Vref Scan: 0
8228 06:51:33.062138
8229 06:51:33.064895 RX Vref 0 -> 0, step: 1
8230 06:51:33.064976
8231 06:51:33.068250 RX Delay 11 -> 252, step: 4
8232 06:51:33.071638 iDelay=187, Bit 0, Center 126 (79 ~ 174) 96
8233 06:51:33.075140 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8234 06:51:33.081847 iDelay=187, Bit 2, Center 126 (75 ~ 178) 104
8235 06:51:33.084969 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8236 06:51:33.088241 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8237 06:51:33.091514 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8238 06:51:33.095034 iDelay=187, Bit 6, Center 138 (91 ~ 186) 96
8239 06:51:33.101283 iDelay=187, Bit 7, Center 136 (87 ~ 186) 100
8240 06:51:33.104856 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8241 06:51:33.108032 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8242 06:51:33.111206 iDelay=187, Bit 10, Center 128 (75 ~ 182) 108
8243 06:51:33.114385 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8244 06:51:33.121190 iDelay=187, Bit 12, Center 128 (75 ~ 182) 108
8245 06:51:33.124437 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8246 06:51:33.128422 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8247 06:51:33.131056 iDelay=187, Bit 15, Center 132 (79 ~ 186) 108
8248 06:51:33.131137 ==
8249 06:51:33.134520 Dram Type= 6, Freq= 0, CH_0, rank 1
8250 06:51:33.140641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8251 06:51:33.140728 ==
8252 06:51:33.140794 DQS Delay:
8253 06:51:33.143976 DQS0 = 0, DQS1 = 0
8254 06:51:33.144058 DQM Delay:
8255 06:51:33.147254 DQM0 = 129, DQM1 = 124
8256 06:51:33.147369 DQ Delay:
8257 06:51:33.151042 DQ0 =126, DQ1 =132, DQ2 =126, DQ3 =126
8258 06:51:33.154164 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
8259 06:51:33.157675 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =118
8260 06:51:33.160798 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132
8261 06:51:33.160880
8262 06:51:33.160944
8263 06:51:33.161003
8264 06:51:33.164241 [DramC_TX_OE_Calibration] TA2
8265 06:51:33.167356 Original DQ_B0 (3 6) =30, OEN = 27
8266 06:51:33.171146 Original DQ_B1 (3 6) =30, OEN = 27
8267 06:51:33.173820 24, 0x0, End_B0=24 End_B1=24
8268 06:51:33.177075 25, 0x0, End_B0=25 End_B1=25
8269 06:51:33.177157 26, 0x0, End_B0=26 End_B1=26
8270 06:51:33.180392 27, 0x0, End_B0=27 End_B1=27
8271 06:51:33.183641 28, 0x0, End_B0=28 End_B1=28
8272 06:51:33.187139 29, 0x0, End_B0=29 End_B1=29
8273 06:51:33.190358 30, 0x0, End_B0=30 End_B1=30
8274 06:51:33.190441 31, 0x4545, End_B0=30 End_B1=30
8275 06:51:33.193815 Byte0 end_step=30 best_step=27
8276 06:51:33.196861 Byte1 end_step=30 best_step=27
8277 06:51:33.200375 Byte0 TX OE(2T, 0.5T) = (3, 3)
8278 06:51:33.204035 Byte1 TX OE(2T, 0.5T) = (3, 3)
8279 06:51:33.204116
8280 06:51:33.204181
8281 06:51:33.210350 [DQSOSCAuto] RK1, (LSB)MR18= 0x1513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8282 06:51:33.213401 CH0 RK1: MR19=303, MR18=1513
8283 06:51:33.219947 CH0_RK1: MR19=0x303, MR18=0x1513, DQSOSC=399, MR23=63, INC=23, DEC=15
8284 06:51:33.222820 [RxdqsGatingPostProcess] freq 1600
8285 06:51:33.229899 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8286 06:51:33.233050 best DQS0 dly(2T, 0.5T) = (1, 1)
8287 06:51:33.233132 best DQS1 dly(2T, 0.5T) = (1, 1)
8288 06:51:33.236232 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8289 06:51:33.239697 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8290 06:51:33.243383 best DQS0 dly(2T, 0.5T) = (1, 1)
8291 06:51:33.246043 best DQS1 dly(2T, 0.5T) = (1, 1)
8292 06:51:33.249525 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8293 06:51:33.252433 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8294 06:51:33.256691 Pre-setting of DQS Precalculation
8295 06:51:33.262843 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8296 06:51:33.262926 ==
8297 06:51:33.265610 Dram Type= 6, Freq= 0, CH_1, rank 0
8298 06:51:33.269158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 06:51:33.269240 ==
8300 06:51:33.275769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8301 06:51:33.279178 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8302 06:51:33.282033 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8303 06:51:33.289014 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8304 06:51:33.297302 [CA 0] Center 42 (12~72) winsize 61
8305 06:51:33.301054 [CA 1] Center 42 (13~72) winsize 60
8306 06:51:33.304106 [CA 2] Center 38 (9~68) winsize 60
8307 06:51:33.307569 [CA 3] Center 37 (8~66) winsize 59
8308 06:51:33.310801 [CA 4] Center 37 (7~68) winsize 62
8309 06:51:33.314048 [CA 5] Center 36 (7~66) winsize 60
8310 06:51:33.314130
8311 06:51:33.317148 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8312 06:51:33.317230
8313 06:51:33.320406 [CATrainingPosCal] consider 1 rank data
8314 06:51:33.323573 u2DelayCellTimex100 = 275/100 ps
8315 06:51:33.330215 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8316 06:51:33.333728 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8317 06:51:33.336706 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
8318 06:51:33.340706 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8319 06:51:33.343685 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8320 06:51:33.346692 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8321 06:51:33.346774
8322 06:51:33.350460 CA PerBit enable=1, Macro0, CA PI delay=36
8323 06:51:33.350575
8324 06:51:33.353735 [CBTSetCACLKResult] CA Dly = 36
8325 06:51:33.356946 CS Dly: 8 (0~39)
8326 06:51:33.359728 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8327 06:51:33.363305 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8328 06:51:33.363425 ==
8329 06:51:33.366694 Dram Type= 6, Freq= 0, CH_1, rank 1
8330 06:51:33.373277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 06:51:33.373360 ==
8332 06:51:33.376749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8333 06:51:33.383104 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8334 06:51:33.386428 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8335 06:51:33.392810 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8336 06:51:33.400578 [CA 0] Center 41 (11~72) winsize 62
8337 06:51:33.403797 [CA 1] Center 42 (13~72) winsize 60
8338 06:51:33.406924 [CA 2] Center 38 (9~68) winsize 60
8339 06:51:33.410384 [CA 3] Center 37 (7~67) winsize 61
8340 06:51:33.413875 [CA 4] Center 38 (8~68) winsize 61
8341 06:51:33.416960 [CA 5] Center 37 (8~67) winsize 60
8342 06:51:33.417041
8343 06:51:33.420334 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8344 06:51:33.420416
8345 06:51:33.427023 [CATrainingPosCal] consider 2 rank data
8346 06:51:33.427105 u2DelayCellTimex100 = 275/100 ps
8347 06:51:33.434092 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8348 06:51:33.437146 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8349 06:51:33.440323 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8350 06:51:33.443289 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8351 06:51:33.446992 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8352 06:51:33.450448 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8353 06:51:33.450530
8354 06:51:33.453536 CA PerBit enable=1, Macro0, CA PI delay=37
8355 06:51:33.453618
8356 06:51:33.456444 [CBTSetCACLKResult] CA Dly = 37
8357 06:51:33.459946 CS Dly: 9 (0~42)
8358 06:51:33.463144 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8359 06:51:33.466044 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8360 06:51:33.466125
8361 06:51:33.469817 ----->DramcWriteLeveling(PI) begin...
8362 06:51:33.469899 ==
8363 06:51:33.473024 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 06:51:33.479758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 06:51:33.479840 ==
8366 06:51:33.482784 Write leveling (Byte 0): 23 => 23
8367 06:51:33.486109 Write leveling (Byte 1): 26 => 26
8368 06:51:33.486189 DramcWriteLeveling(PI) end<-----
8369 06:51:33.489383
8370 06:51:33.489463 ==
8371 06:51:33.492641 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 06:51:33.496100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 06:51:33.496182 ==
8374 06:51:33.499382 [Gating] SW mode calibration
8375 06:51:33.505723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8376 06:51:33.512470 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8377 06:51:33.515982 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 06:51:33.519043 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 06:51:33.526003 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 06:51:33.529093 1 4 12 | B1->B0 | 2524 3434 | 1 0 | (0 0) (0 0)
8381 06:51:33.532060 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 06:51:33.538465 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 06:51:33.541895 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 06:51:33.545397 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 06:51:33.551946 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 06:51:33.555191 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 06:51:33.558687 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8388 06:51:33.565032 1 5 12 | B1->B0 | 2d2d 2626 | 1 0 | (1 0) (1 0)
8389 06:51:33.568265 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8390 06:51:33.571631 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 06:51:33.578801 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 06:51:33.581287 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 06:51:33.584517 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 06:51:33.591177 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 06:51:33.594526 1 6 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8396 06:51:33.597939 1 6 12 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8397 06:51:33.604610 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 06:51:33.608009 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 06:51:33.610944 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 06:51:33.617260 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 06:51:33.621058 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 06:51:33.624040 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 06:51:33.630752 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8404 06:51:33.633904 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8405 06:51:33.637218 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8406 06:51:33.643959 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 06:51:33.647094 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 06:51:33.650459 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 06:51:33.657089 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 06:51:33.660499 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 06:51:33.663658 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 06:51:33.670358 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 06:51:33.673154 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 06:51:33.676871 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 06:51:33.682976 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 06:51:33.686496 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 06:51:33.689622 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 06:51:33.696341 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 06:51:33.699914 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8420 06:51:33.703168 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8421 06:51:33.709682 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8422 06:51:33.709768 Total UI for P1: 0, mck2ui 16
8423 06:51:33.716383 best dqsien dly found for B0: ( 1, 9, 10)
8424 06:51:33.719537 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 06:51:33.722939 Total UI for P1: 0, mck2ui 16
8426 06:51:33.726328 best dqsien dly found for B1: ( 1, 9, 14)
8427 06:51:33.729464 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8428 06:51:33.733009 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8429 06:51:33.733091
8430 06:51:33.736185 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8431 06:51:33.739036 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8432 06:51:33.742830 [Gating] SW calibration Done
8433 06:51:33.742911 ==
8434 06:51:33.746353 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 06:51:33.752563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 06:51:33.752652 ==
8437 06:51:33.752769 RX Vref Scan: 0
8438 06:51:33.752863
8439 06:51:33.756051 RX Vref 0 -> 0, step: 1
8440 06:51:33.756138
8441 06:51:33.758869 RX Delay 0 -> 252, step: 8
8442 06:51:33.762588 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8443 06:51:33.765586 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8444 06:51:33.768718 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8445 06:51:33.772208 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8446 06:51:33.778545 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8447 06:51:33.782050 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8448 06:51:33.785360 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8449 06:51:33.788866 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8450 06:51:33.795322 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8451 06:51:33.798789 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8452 06:51:33.801890 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8453 06:51:33.804891 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8454 06:51:33.808439 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8455 06:51:33.815301 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8456 06:51:33.818508 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8457 06:51:33.821318 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8458 06:51:33.821399 ==
8459 06:51:33.824793 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 06:51:33.827933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 06:51:33.831509 ==
8462 06:51:33.831590 DQS Delay:
8463 06:51:33.831654 DQS0 = 0, DQS1 = 0
8464 06:51:33.834602 DQM Delay:
8465 06:51:33.834683 DQM0 = 135, DQM1 = 130
8466 06:51:33.838010 DQ Delay:
8467 06:51:33.841491 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8468 06:51:33.844607 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8469 06:51:33.847879 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8470 06:51:33.851527 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8471 06:51:33.851608
8472 06:51:33.851672
8473 06:51:33.851731 ==
8474 06:51:33.854187 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 06:51:33.858290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 06:51:33.860928 ==
8477 06:51:33.861009
8478 06:51:33.861072
8479 06:51:33.861132 TX Vref Scan disable
8480 06:51:33.864440 == TX Byte 0 ==
8481 06:51:33.867645 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8482 06:51:33.871030 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8483 06:51:33.874551 == TX Byte 1 ==
8484 06:51:33.877331 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8485 06:51:33.880450 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8486 06:51:33.884123 ==
8487 06:51:33.887225 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 06:51:33.890203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 06:51:33.890284 ==
8490 06:51:33.903739
8491 06:51:33.906936 TX Vref early break, caculate TX vref
8492 06:51:33.910391 TX Vref=16, minBit 8, minWin=22, winSum=370
8493 06:51:33.913760 TX Vref=18, minBit 8, minWin=21, winSum=378
8494 06:51:33.916971 TX Vref=20, minBit 9, minWin=22, winSum=384
8495 06:51:33.920284 TX Vref=22, minBit 8, minWin=23, winSum=397
8496 06:51:33.923534 TX Vref=24, minBit 9, minWin=24, winSum=407
8497 06:51:33.930055 TX Vref=26, minBit 4, minWin=25, winSum=416
8498 06:51:33.933337 TX Vref=28, minBit 9, minWin=25, winSum=420
8499 06:51:33.936907 TX Vref=30, minBit 9, minWin=24, winSum=415
8500 06:51:33.940131 TX Vref=32, minBit 9, minWin=24, winSum=407
8501 06:51:33.943333 TX Vref=34, minBit 0, minWin=24, winSum=399
8502 06:51:33.950101 TX Vref=36, minBit 9, minWin=22, winSum=385
8503 06:51:33.952773 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 28
8504 06:51:33.952855
8505 06:51:33.956177 Final TX Range 0 Vref 28
8506 06:51:33.956259
8507 06:51:33.956323 ==
8508 06:51:33.959707 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 06:51:33.962936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 06:51:33.966270 ==
8511 06:51:33.966350
8512 06:51:33.966414
8513 06:51:33.966473 TX Vref Scan disable
8514 06:51:33.973563 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8515 06:51:33.973645 == TX Byte 0 ==
8516 06:51:33.976493 u2DelayCellOfst[0]=17 cells (5 PI)
8517 06:51:33.979427 u2DelayCellOfst[1]=10 cells (3 PI)
8518 06:51:33.983073 u2DelayCellOfst[2]=0 cells (0 PI)
8519 06:51:33.986036 u2DelayCellOfst[3]=7 cells (2 PI)
8520 06:51:33.989477 u2DelayCellOfst[4]=10 cells (3 PI)
8521 06:51:33.992866 u2DelayCellOfst[5]=17 cells (5 PI)
8522 06:51:33.995934 u2DelayCellOfst[6]=17 cells (5 PI)
8523 06:51:33.999863 u2DelayCellOfst[7]=7 cells (2 PI)
8524 06:51:34.002709 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8525 06:51:34.005794 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8526 06:51:34.009230 == TX Byte 1 ==
8527 06:51:34.012341 u2DelayCellOfst[8]=0 cells (0 PI)
8528 06:51:34.016693 u2DelayCellOfst[9]=3 cells (1 PI)
8529 06:51:34.019274 u2DelayCellOfst[10]=10 cells (3 PI)
8530 06:51:34.022662 u2DelayCellOfst[11]=7 cells (2 PI)
8531 06:51:34.025796 u2DelayCellOfst[12]=14 cells (4 PI)
8532 06:51:34.028993 u2DelayCellOfst[13]=14 cells (4 PI)
8533 06:51:34.029094 u2DelayCellOfst[14]=17 cells (5 PI)
8534 06:51:34.032185 u2DelayCellOfst[15]=17 cells (5 PI)
8535 06:51:34.039175 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8536 06:51:34.042463 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8537 06:51:34.045468 DramC Write-DBI on
8538 06:51:34.045543 ==
8539 06:51:34.048988 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 06:51:34.052791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 06:51:34.052900 ==
8542 06:51:34.053014
8543 06:51:34.053112
8544 06:51:34.055775 TX Vref Scan disable
8545 06:51:34.055849 == TX Byte 0 ==
8546 06:51:34.062062 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8547 06:51:34.062170 == TX Byte 1 ==
8548 06:51:34.065148 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8549 06:51:34.069046 DramC Write-DBI off
8550 06:51:34.069147
8551 06:51:34.069237 [DATLAT]
8552 06:51:34.072057 Freq=1600, CH1 RK0
8553 06:51:34.072131
8554 06:51:34.072191 DATLAT Default: 0xf
8555 06:51:34.075120 0, 0xFFFF, sum = 0
8556 06:51:34.078551 1, 0xFFFF, sum = 0
8557 06:51:34.078625 2, 0xFFFF, sum = 0
8558 06:51:34.082106 3, 0xFFFF, sum = 0
8559 06:51:34.082209 4, 0xFFFF, sum = 0
8560 06:51:34.085002 5, 0xFFFF, sum = 0
8561 06:51:34.085102 6, 0xFFFF, sum = 0
8562 06:51:34.088238 7, 0xFFFF, sum = 0
8563 06:51:34.088311 8, 0xFFFF, sum = 0
8564 06:51:34.091527 9, 0xFFFF, sum = 0
8565 06:51:34.091600 10, 0xFFFF, sum = 0
8566 06:51:34.094678 11, 0xFFFF, sum = 0
8567 06:51:34.094750 12, 0xFFFF, sum = 0
8568 06:51:34.098119 13, 0xFFFF, sum = 0
8569 06:51:34.098194 14, 0x0, sum = 1
8570 06:51:34.101338 15, 0x0, sum = 2
8571 06:51:34.101438 16, 0x0, sum = 3
8572 06:51:34.104925 17, 0x0, sum = 4
8573 06:51:34.104998 best_step = 15
8574 06:51:34.105059
8575 06:51:34.105117 ==
8576 06:51:34.108225 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 06:51:34.114423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 06:51:34.114500 ==
8579 06:51:34.114563 RX Vref Scan: 1
8580 06:51:34.114622
8581 06:51:34.117521 Set Vref Range= 24 -> 127
8582 06:51:34.117597
8583 06:51:34.121133 RX Vref 24 -> 127, step: 1
8584 06:51:34.121231
8585 06:51:34.124208 RX Delay 19 -> 252, step: 4
8586 06:51:34.124281
8587 06:51:34.127722 Set Vref, RX VrefLevel [Byte0]: 24
8588 06:51:34.130712 [Byte1]: 24
8589 06:51:34.130796
8590 06:51:34.134369 Set Vref, RX VrefLevel [Byte0]: 25
8591 06:51:34.137287 [Byte1]: 25
8592 06:51:34.137369
8593 06:51:34.140547 Set Vref, RX VrefLevel [Byte0]: 26
8594 06:51:34.144296 [Byte1]: 26
8595 06:51:34.144379
8596 06:51:34.147490 Set Vref, RX VrefLevel [Byte0]: 27
8597 06:51:34.150689 [Byte1]: 27
8598 06:51:34.155014
8599 06:51:34.155100 Set Vref, RX VrefLevel [Byte0]: 28
8600 06:51:34.158416 [Byte1]: 28
8601 06:51:34.162928
8602 06:51:34.163015 Set Vref, RX VrefLevel [Byte0]: 29
8603 06:51:34.165744 [Byte1]: 29
8604 06:51:34.170617
8605 06:51:34.170718 Set Vref, RX VrefLevel [Byte0]: 30
8606 06:51:34.173326 [Byte1]: 30
8607 06:51:34.177431
8608 06:51:34.177512 Set Vref, RX VrefLevel [Byte0]: 31
8609 06:51:34.180816 [Byte1]: 31
8610 06:51:34.185429
8611 06:51:34.185509 Set Vref, RX VrefLevel [Byte0]: 32
8612 06:51:34.188175 [Byte1]: 32
8613 06:51:34.192770
8614 06:51:34.192851 Set Vref, RX VrefLevel [Byte0]: 33
8615 06:51:34.195895 [Byte1]: 33
8616 06:51:34.200374
8617 06:51:34.200455 Set Vref, RX VrefLevel [Byte0]: 34
8618 06:51:34.203576 [Byte1]: 34
8619 06:51:34.208196
8620 06:51:34.208283 Set Vref, RX VrefLevel [Byte0]: 35
8621 06:51:34.211372 [Byte1]: 35
8622 06:51:34.215573
8623 06:51:34.215654 Set Vref, RX VrefLevel [Byte0]: 36
8624 06:51:34.219026 [Byte1]: 36
8625 06:51:34.223322
8626 06:51:34.223428 Set Vref, RX VrefLevel [Byte0]: 37
8627 06:51:34.226355 [Byte1]: 37
8628 06:51:34.230633
8629 06:51:34.230733 Set Vref, RX VrefLevel [Byte0]: 38
8630 06:51:34.233808 [Byte1]: 38
8631 06:51:34.238304
8632 06:51:34.238490 Set Vref, RX VrefLevel [Byte0]: 39
8633 06:51:34.241893 [Byte1]: 39
8634 06:51:34.246844
8635 06:51:34.247055 Set Vref, RX VrefLevel [Byte0]: 40
8636 06:51:34.249544 [Byte1]: 40
8637 06:51:34.253249
8638 06:51:34.253498 Set Vref, RX VrefLevel [Byte0]: 41
8639 06:51:34.256645 [Byte1]: 41
8640 06:51:34.261437
8641 06:51:34.261720 Set Vref, RX VrefLevel [Byte0]: 42
8642 06:51:34.264342 [Byte1]: 42
8643 06:51:34.268668
8644 06:51:34.268906 Set Vref, RX VrefLevel [Byte0]: 43
8645 06:51:34.271947 [Byte1]: 43
8646 06:51:34.276543
8647 06:51:34.276922 Set Vref, RX VrefLevel [Byte0]: 44
8648 06:51:34.279912 [Byte1]: 44
8649 06:51:34.284114
8650 06:51:34.284622 Set Vref, RX VrefLevel [Byte0]: 45
8651 06:51:34.287153 [Byte1]: 45
8652 06:51:34.291417
8653 06:51:34.291839 Set Vref, RX VrefLevel [Byte0]: 46
8654 06:51:34.295139 [Byte1]: 46
8655 06:51:34.299939
8656 06:51:34.300329 Set Vref, RX VrefLevel [Byte0]: 47
8657 06:51:34.301967 [Byte1]: 47
8658 06:51:34.306084
8659 06:51:34.306165 Set Vref, RX VrefLevel [Byte0]: 48
8660 06:51:34.309660 [Byte1]: 48
8661 06:51:34.314062
8662 06:51:34.314142 Set Vref, RX VrefLevel [Byte0]: 49
8663 06:51:34.316943 [Byte1]: 49
8664 06:51:34.321641
8665 06:51:34.321723 Set Vref, RX VrefLevel [Byte0]: 50
8666 06:51:34.324613 [Byte1]: 50
8667 06:51:34.329291
8668 06:51:34.329371 Set Vref, RX VrefLevel [Byte0]: 51
8669 06:51:34.332133 [Byte1]: 51
8670 06:51:34.336793
8671 06:51:34.336874 Set Vref, RX VrefLevel [Byte0]: 52
8672 06:51:34.340211 [Byte1]: 52
8673 06:51:34.344367
8674 06:51:34.344447 Set Vref, RX VrefLevel [Byte0]: 53
8675 06:51:34.347614 [Byte1]: 53
8676 06:51:34.351678
8677 06:51:34.351764 Set Vref, RX VrefLevel [Byte0]: 54
8678 06:51:34.354920 [Byte1]: 54
8679 06:51:34.359242
8680 06:51:34.359324 Set Vref, RX VrefLevel [Byte0]: 55
8681 06:51:34.362732 [Byte1]: 55
8682 06:51:34.367615
8683 06:51:34.367697 Set Vref, RX VrefLevel [Byte0]: 56
8684 06:51:34.370071 [Byte1]: 56
8685 06:51:34.375413
8686 06:51:34.375495 Set Vref, RX VrefLevel [Byte0]: 57
8687 06:51:34.378166 [Byte1]: 57
8688 06:51:34.382489
8689 06:51:34.382577 Set Vref, RX VrefLevel [Byte0]: 58
8690 06:51:34.385078 [Byte1]: 58
8691 06:51:34.389591
8692 06:51:34.389672 Set Vref, RX VrefLevel [Byte0]: 59
8693 06:51:34.392692 [Byte1]: 59
8694 06:51:34.397101
8695 06:51:34.397182 Set Vref, RX VrefLevel [Byte0]: 60
8696 06:51:34.400714 [Byte1]: 60
8697 06:51:34.404929
8698 06:51:34.405010 Set Vref, RX VrefLevel [Byte0]: 61
8699 06:51:34.408048 [Byte1]: 61
8700 06:51:34.412411
8701 06:51:34.412491 Set Vref, RX VrefLevel [Byte0]: 62
8702 06:51:34.415499 [Byte1]: 62
8703 06:51:34.420219
8704 06:51:34.420308 Set Vref, RX VrefLevel [Byte0]: 63
8705 06:51:34.423310 [Byte1]: 63
8706 06:51:34.427331
8707 06:51:34.427458 Set Vref, RX VrefLevel [Byte0]: 64
8708 06:51:34.430622 [Byte1]: 64
8709 06:51:34.435499
8710 06:51:34.435593 Set Vref, RX VrefLevel [Byte0]: 65
8711 06:51:34.438355 [Byte1]: 65
8712 06:51:34.442786
8713 06:51:34.442930 Set Vref, RX VrefLevel [Byte0]: 66
8714 06:51:34.445886 [Byte1]: 66
8715 06:51:34.450209
8716 06:51:34.450401 Set Vref, RX VrefLevel [Byte0]: 67
8717 06:51:34.453272 [Byte1]: 67
8718 06:51:34.457946
8719 06:51:34.458125 Set Vref, RX VrefLevel [Byte0]: 68
8720 06:51:34.461070 [Byte1]: 68
8721 06:51:34.465413
8722 06:51:34.465586 Set Vref, RX VrefLevel [Byte0]: 69
8723 06:51:34.468714 [Byte1]: 69
8724 06:51:34.473268
8725 06:51:34.473534 Set Vref, RX VrefLevel [Byte0]: 70
8726 06:51:34.476528 [Byte1]: 70
8727 06:51:34.481088
8728 06:51:34.481471 Set Vref, RX VrefLevel [Byte0]: 71
8729 06:51:34.483745 [Byte1]: 71
8730 06:51:34.488203
8731 06:51:34.488687 Set Vref, RX VrefLevel [Byte0]: 72
8732 06:51:34.491695 [Byte1]: 72
8733 06:51:34.495826
8734 06:51:34.496244 Final RX Vref Byte 0 = 59 to rank0
8735 06:51:34.499272 Final RX Vref Byte 1 = 61 to rank0
8736 06:51:34.502494 Final RX Vref Byte 0 = 59 to rank1
8737 06:51:34.506174 Final RX Vref Byte 1 = 61 to rank1==
8738 06:51:34.509201 Dram Type= 6, Freq= 0, CH_1, rank 0
8739 06:51:34.515957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 06:51:34.516375 ==
8741 06:51:34.516733 DQS Delay:
8742 06:51:34.518841 DQS0 = 0, DQS1 = 0
8743 06:51:34.519256 DQM Delay:
8744 06:51:34.519667 DQM0 = 132, DQM1 = 128
8745 06:51:34.522115 DQ Delay:
8746 06:51:34.525396 DQ0 =138, DQ1 =128, DQ2 =118, DQ3 =132
8747 06:51:34.528772 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =128
8748 06:51:34.531926 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8749 06:51:34.535550 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =136
8750 06:51:34.535969
8751 06:51:34.536297
8752 06:51:34.536627
8753 06:51:34.538559 [DramC_TX_OE_Calibration] TA2
8754 06:51:34.541811 Original DQ_B0 (3 6) =30, OEN = 27
8755 06:51:34.545117 Original DQ_B1 (3 6) =30, OEN = 27
8756 06:51:34.548467 24, 0x0, End_B0=24 End_B1=24
8757 06:51:34.552397 25, 0x0, End_B0=25 End_B1=25
8758 06:51:34.552822 26, 0x0, End_B0=26 End_B1=26
8759 06:51:34.555671 27, 0x0, End_B0=27 End_B1=27
8760 06:51:34.558448 28, 0x0, End_B0=28 End_B1=28
8761 06:51:34.562263 29, 0x0, End_B0=29 End_B1=29
8762 06:51:34.562693 30, 0x0, End_B0=30 End_B1=30
8763 06:51:34.564776 31, 0x4141, End_B0=30 End_B1=30
8764 06:51:34.568015 Byte0 end_step=30 best_step=27
8765 06:51:34.571277 Byte1 end_step=30 best_step=27
8766 06:51:34.575050 Byte0 TX OE(2T, 0.5T) = (3, 3)
8767 06:51:34.578261 Byte1 TX OE(2T, 0.5T) = (3, 3)
8768 06:51:34.578686
8769 06:51:34.579099
8770 06:51:34.584688 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8771 06:51:34.588447 CH1 RK0: MR19=303, MR18=E18
8772 06:51:34.594674 CH1_RK0: MR19=0x303, MR18=0xE18, DQSOSC=397, MR23=63, INC=23, DEC=15
8773 06:51:34.595261
8774 06:51:34.598086 ----->DramcWriteLeveling(PI) begin...
8775 06:51:34.598649 ==
8776 06:51:34.601212 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 06:51:34.604748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 06:51:34.605198 ==
8779 06:51:34.607876 Write leveling (Byte 0): 20 => 20
8780 06:51:34.611070 Write leveling (Byte 1): 25 => 25
8781 06:51:34.614374 DramcWriteLeveling(PI) end<-----
8782 06:51:34.614823
8783 06:51:34.615156 ==
8784 06:51:34.617612 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 06:51:34.620912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 06:51:34.625169 ==
8787 06:51:34.625615 [Gating] SW mode calibration
8788 06:51:34.633905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8789 06:51:34.637517 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8790 06:51:34.640878 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 06:51:34.647513 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 06:51:34.650823 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8793 06:51:34.653693 1 4 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8794 06:51:34.660703 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 06:51:34.663532 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 06:51:34.667034 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 06:51:34.673711 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 06:51:34.677005 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 06:51:34.680350 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8800 06:51:34.687318 1 5 8 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8801 06:51:34.690133 1 5 12 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
8802 06:51:34.693469 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 06:51:34.700349 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 06:51:34.703276 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 06:51:34.706719 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 06:51:34.713643 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 06:51:34.716456 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8808 06:51:34.719694 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8809 06:51:34.726719 1 6 12 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8810 06:51:34.729436 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 06:51:34.733355 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 06:51:34.739631 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 06:51:34.742961 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 06:51:34.746362 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 06:51:34.752881 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 06:51:34.755781 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8817 06:51:34.759204 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8818 06:51:34.765977 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 06:51:34.768921 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 06:51:34.772604 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 06:51:34.778723 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 06:51:34.782351 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 06:51:34.788937 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 06:51:34.792023 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 06:51:34.795305 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 06:51:34.799707 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 06:51:34.805830 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 06:51:34.809037 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 06:51:34.814883 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 06:51:34.818528 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 06:51:34.821753 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8832 06:51:34.828402 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8833 06:51:34.831843 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8834 06:51:34.835168 Total UI for P1: 0, mck2ui 16
8835 06:51:34.838386 best dqsien dly found for B0: ( 1, 9, 6)
8836 06:51:34.841690 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 06:51:34.844755 Total UI for P1: 0, mck2ui 16
8838 06:51:34.848232 best dqsien dly found for B1: ( 1, 9, 12)
8839 06:51:34.851493 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8840 06:51:34.854572 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8841 06:51:34.855104
8842 06:51:34.857902 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8843 06:51:34.864539 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8844 06:51:34.864979 [Gating] SW calibration Done
8845 06:51:34.865425 ==
8846 06:51:34.868645 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 06:51:34.874601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 06:51:34.875040 ==
8849 06:51:34.875668 RX Vref Scan: 0
8850 06:51:34.876104
8851 06:51:34.878042 RX Vref 0 -> 0, step: 1
8852 06:51:34.878479
8853 06:51:34.880922 RX Delay 0 -> 252, step: 8
8854 06:51:34.884214 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8855 06:51:34.888113 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8856 06:51:34.891317 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8857 06:51:34.897557 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8858 06:51:34.901107 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8859 06:51:34.903904 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8860 06:51:34.907449 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8861 06:51:34.910622 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8862 06:51:34.916872 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8863 06:51:34.920410 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8864 06:51:34.923429 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8865 06:51:34.927174 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8866 06:51:34.933669 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8867 06:51:34.936645 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8868 06:51:34.939983 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8869 06:51:34.943293 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8870 06:51:34.943742 ==
8871 06:51:34.946852 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 06:51:34.953240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 06:51:34.953660 ==
8874 06:51:34.953998 DQS Delay:
8875 06:51:34.956500 DQS0 = 0, DQS1 = 0
8876 06:51:34.956915 DQM Delay:
8877 06:51:34.959964 DQM0 = 133, DQM1 = 130
8878 06:51:34.960381 DQ Delay:
8879 06:51:34.963509 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =135
8880 06:51:34.966304 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8881 06:51:34.969730 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =123
8882 06:51:34.973558 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8883 06:51:34.973974
8884 06:51:34.974302
8885 06:51:34.974603 ==
8886 06:51:34.976399 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 06:51:34.983705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 06:51:34.984137 ==
8889 06:51:34.984466
8890 06:51:34.984770
8891 06:51:34.985062 TX Vref Scan disable
8892 06:51:34.986426 == TX Byte 0 ==
8893 06:51:34.989393 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8894 06:51:34.995988 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8895 06:51:34.996407 == TX Byte 1 ==
8896 06:51:34.999178 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8897 06:51:35.006030 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8898 06:51:35.006469 ==
8899 06:51:35.009132 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 06:51:35.013034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 06:51:35.013449 ==
8902 06:51:35.026332
8903 06:51:35.030158 TX Vref early break, caculate TX vref
8904 06:51:35.032795 TX Vref=16, minBit 9, minWin=22, winSum=377
8905 06:51:35.036448 TX Vref=18, minBit 9, minWin=22, winSum=381
8906 06:51:35.039609 TX Vref=20, minBit 9, minWin=22, winSum=393
8907 06:51:35.042850 TX Vref=22, minBit 3, minWin=24, winSum=401
8908 06:51:35.046261 TX Vref=24, minBit 9, minWin=24, winSum=409
8909 06:51:35.052796 TX Vref=26, minBit 9, minWin=24, winSum=417
8910 06:51:35.055774 TX Vref=28, minBit 9, minWin=24, winSum=417
8911 06:51:35.059293 TX Vref=30, minBit 3, minWin=25, winSum=413
8912 06:51:35.062466 TX Vref=32, minBit 9, minWin=23, winSum=405
8913 06:51:35.066014 TX Vref=34, minBit 0, minWin=24, winSum=402
8914 06:51:35.072463 TX Vref=36, minBit 9, minWin=23, winSum=393
8915 06:51:35.075810 [TxChooseVref] Worse bit 3, Min win 25, Win sum 413, Final Vref 30
8916 06:51:35.076231
8917 06:51:35.079153 Final TX Range 0 Vref 30
8918 06:51:35.079632
8919 06:51:35.080044 ==
8920 06:51:35.082356 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 06:51:35.085792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 06:51:35.089612 ==
8923 06:51:35.090267
8924 06:51:35.090764
8925 06:51:35.091260 TX Vref Scan disable
8926 06:51:35.095639 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8927 06:51:35.096104 == TX Byte 0 ==
8928 06:51:35.099406 u2DelayCellOfst[0]=14 cells (4 PI)
8929 06:51:35.102593 u2DelayCellOfst[1]=10 cells (3 PI)
8930 06:51:35.105709 u2DelayCellOfst[2]=0 cells (0 PI)
8931 06:51:35.108844 u2DelayCellOfst[3]=7 cells (2 PI)
8932 06:51:35.112126 u2DelayCellOfst[4]=7 cells (2 PI)
8933 06:51:35.115169 u2DelayCellOfst[5]=14 cells (4 PI)
8934 06:51:35.118295 u2DelayCellOfst[6]=14 cells (4 PI)
8935 06:51:35.121969 u2DelayCellOfst[7]=7 cells (2 PI)
8936 06:51:35.125236 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8937 06:51:35.128812 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8938 06:51:35.131579 == TX Byte 1 ==
8939 06:51:35.134940 u2DelayCellOfst[8]=0 cells (0 PI)
8940 06:51:35.138093 u2DelayCellOfst[9]=3 cells (1 PI)
8941 06:51:35.141359 u2DelayCellOfst[10]=14 cells (4 PI)
8942 06:51:35.144700 u2DelayCellOfst[11]=7 cells (2 PI)
8943 06:51:35.148589 u2DelayCellOfst[12]=17 cells (5 PI)
8944 06:51:35.151216 u2DelayCellOfst[13]=21 cells (6 PI)
8945 06:51:35.154849 u2DelayCellOfst[14]=17 cells (5 PI)
8946 06:51:35.154933 u2DelayCellOfst[15]=17 cells (5 PI)
8947 06:51:35.161006 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8948 06:51:35.164774 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8949 06:51:35.167580 DramC Write-DBI on
8950 06:51:35.167682 ==
8951 06:51:35.171240 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 06:51:35.174309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 06:51:35.174432 ==
8954 06:51:35.174542
8955 06:51:35.174636
8956 06:51:35.177730 TX Vref Scan disable
8957 06:51:35.177871 == TX Byte 0 ==
8958 06:51:35.184022 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8959 06:51:35.184173 == TX Byte 1 ==
8960 06:51:35.191470 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8961 06:51:35.191933 DramC Write-DBI off
8962 06:51:35.192269
8963 06:51:35.192579 [DATLAT]
8964 06:51:35.194525 Freq=1600, CH1 RK1
8965 06:51:35.194941
8966 06:51:35.197952 DATLAT Default: 0xf
8967 06:51:35.198407 0, 0xFFFF, sum = 0
8968 06:51:35.201288 1, 0xFFFF, sum = 0
8969 06:51:35.201717 2, 0xFFFF, sum = 0
8970 06:51:35.204334 3, 0xFFFF, sum = 0
8971 06:51:35.204827 4, 0xFFFF, sum = 0
8972 06:51:35.207352 5, 0xFFFF, sum = 0
8973 06:51:35.207825 6, 0xFFFF, sum = 0
8974 06:51:35.210829 7, 0xFFFF, sum = 0
8975 06:51:35.211252 8, 0xFFFF, sum = 0
8976 06:51:35.214329 9, 0xFFFF, sum = 0
8977 06:51:35.214756 10, 0xFFFF, sum = 0
8978 06:51:35.217528 11, 0xFFFF, sum = 0
8979 06:51:35.217955 12, 0xFFFF, sum = 0
8980 06:51:35.220895 13, 0xFFFF, sum = 0
8981 06:51:35.221321 14, 0x0, sum = 1
8982 06:51:35.223960 15, 0x0, sum = 2
8983 06:51:35.224436 16, 0x0, sum = 3
8984 06:51:35.227524 17, 0x0, sum = 4
8985 06:51:35.227949 best_step = 15
8986 06:51:35.228279
8987 06:51:35.228585 ==
8988 06:51:35.230764 Dram Type= 6, Freq= 0, CH_1, rank 1
8989 06:51:35.237307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8990 06:51:35.237748 ==
8991 06:51:35.238081 RX Vref Scan: 0
8992 06:51:35.238390
8993 06:51:35.240948 RX Vref 0 -> 0, step: 1
8994 06:51:35.241361
8995 06:51:35.243940 RX Delay 11 -> 252, step: 4
8996 06:51:35.246976 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8997 06:51:35.250365 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8998 06:51:35.257557 iDelay=195, Bit 2, Center 118 (63 ~ 174) 112
8999 06:51:35.260357 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9000 06:51:35.263951 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
9001 06:51:35.267028 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9002 06:51:35.270163 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9003 06:51:35.277053 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
9004 06:51:35.280195 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9005 06:51:35.283279 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9006 06:51:35.286740 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9007 06:51:35.289969 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9008 06:51:35.296727 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9009 06:51:35.299904 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9010 06:51:35.303453 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9011 06:51:35.306156 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9012 06:51:35.306645 ==
9013 06:51:35.310275 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 06:51:35.317303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 06:51:35.317803 ==
9016 06:51:35.318213 DQS Delay:
9017 06:51:35.319707 DQS0 = 0, DQS1 = 0
9018 06:51:35.320097 DQM Delay:
9019 06:51:35.323048 DQM0 = 130, DQM1 = 128
9020 06:51:35.323612 DQ Delay:
9021 06:51:35.326162 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
9022 06:51:35.329611 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9023 06:51:35.333736 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
9024 06:51:35.336001 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9025 06:51:35.336545
9026 06:51:35.336948
9027 06:51:35.337322
9028 06:51:35.339527 [DramC_TX_OE_Calibration] TA2
9029 06:51:35.342429 Original DQ_B0 (3 6) =30, OEN = 27
9030 06:51:35.346096 Original DQ_B1 (3 6) =30, OEN = 27
9031 06:51:35.349772 24, 0x0, End_B0=24 End_B1=24
9032 06:51:35.352822 25, 0x0, End_B0=25 End_B1=25
9033 06:51:35.353254 26, 0x0, End_B0=26 End_B1=26
9034 06:51:35.356123 27, 0x0, End_B0=27 End_B1=27
9035 06:51:35.359083 28, 0x0, End_B0=28 End_B1=28
9036 06:51:35.362417 29, 0x0, End_B0=29 End_B1=29
9037 06:51:35.365879 30, 0x0, End_B0=30 End_B1=30
9038 06:51:35.366312 31, 0x4141, End_B0=30 End_B1=30
9039 06:51:35.368940 Byte0 end_step=30 best_step=27
9040 06:51:35.371995 Byte1 end_step=30 best_step=27
9041 06:51:35.376009 Byte0 TX OE(2T, 0.5T) = (3, 3)
9042 06:51:35.378865 Byte1 TX OE(2T, 0.5T) = (3, 3)
9043 06:51:35.379333
9044 06:51:35.379738
9045 06:51:35.385882 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9046 06:51:35.388664 CH1 RK1: MR19=303, MR18=E1C
9047 06:51:35.395347 CH1_RK1: MR19=0x303, MR18=0xE1C, DQSOSC=395, MR23=63, INC=23, DEC=15
9048 06:51:35.398681 [RxdqsGatingPostProcess] freq 1600
9049 06:51:35.405048 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9050 06:51:35.405536 best DQS0 dly(2T, 0.5T) = (1, 1)
9051 06:51:35.408486 best DQS1 dly(2T, 0.5T) = (1, 1)
9052 06:51:35.411934 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9053 06:51:35.415433 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9054 06:51:35.418296 best DQS0 dly(2T, 0.5T) = (1, 1)
9055 06:51:35.421953 best DQS1 dly(2T, 0.5T) = (1, 1)
9056 06:51:35.424784 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9057 06:51:35.427940 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9058 06:51:35.431326 Pre-setting of DQS Precalculation
9059 06:51:35.434844 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9060 06:51:35.445193 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9061 06:51:35.451186 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9062 06:51:35.451332
9063 06:51:35.451465
9064 06:51:35.453853 [Calibration Summary] 3200 Mbps
9065 06:51:35.453983 CH 0, Rank 0
9066 06:51:35.457559 SW Impedance : PASS
9067 06:51:35.460623 DUTY Scan : NO K
9068 06:51:35.460724 ZQ Calibration : PASS
9069 06:51:35.464154 Jitter Meter : NO K
9070 06:51:35.464249 CBT Training : PASS
9071 06:51:35.467390 Write leveling : PASS
9072 06:51:35.470886 RX DQS gating : PASS
9073 06:51:35.470966 RX DQ/DQS(RDDQC) : PASS
9074 06:51:35.473883 TX DQ/DQS : PASS
9075 06:51:35.477193 RX DATLAT : PASS
9076 06:51:35.477267 RX DQ/DQS(Engine): PASS
9077 06:51:35.480179 TX OE : PASS
9078 06:51:35.480250 All Pass.
9079 06:51:35.480311
9080 06:51:35.483379 CH 0, Rank 1
9081 06:51:35.483462 SW Impedance : PASS
9082 06:51:35.487142 DUTY Scan : NO K
9083 06:51:35.490189 ZQ Calibration : PASS
9084 06:51:35.490268 Jitter Meter : NO K
9085 06:51:35.493898 CBT Training : PASS
9086 06:51:35.496806 Write leveling : PASS
9087 06:51:35.496878 RX DQS gating : PASS
9088 06:51:35.500239 RX DQ/DQS(RDDQC) : PASS
9089 06:51:35.504122 TX DQ/DQS : PASS
9090 06:51:35.504195 RX DATLAT : PASS
9091 06:51:35.506763 RX DQ/DQS(Engine): PASS
9092 06:51:35.510363 TX OE : PASS
9093 06:51:35.510435 All Pass.
9094 06:51:35.510509
9095 06:51:35.510568 CH 1, Rank 0
9096 06:51:35.513620 SW Impedance : PASS
9097 06:51:35.517004 DUTY Scan : NO K
9098 06:51:35.517075 ZQ Calibration : PASS
9099 06:51:35.520698 Jitter Meter : NO K
9100 06:51:35.523324 CBT Training : PASS
9101 06:51:35.523422 Write leveling : PASS
9102 06:51:35.526660 RX DQS gating : PASS
9103 06:51:35.529560 RX DQ/DQS(RDDQC) : PASS
9104 06:51:35.529631 TX DQ/DQS : PASS
9105 06:51:35.533099 RX DATLAT : PASS
9106 06:51:35.537226 RX DQ/DQS(Engine): PASS
9107 06:51:35.537298 TX OE : PASS
9108 06:51:35.537358 All Pass.
9109 06:51:35.539758
9110 06:51:35.539826 CH 1, Rank 1
9111 06:51:35.542858 SW Impedance : PASS
9112 06:51:35.542936 DUTY Scan : NO K
9113 06:51:35.546398 ZQ Calibration : PASS
9114 06:51:35.549611 Jitter Meter : NO K
9115 06:51:35.549687 CBT Training : PASS
9116 06:51:35.552734 Write leveling : PASS
9117 06:51:35.552803 RX DQS gating : PASS
9118 06:51:35.556195 RX DQ/DQS(RDDQC) : PASS
9119 06:51:35.559335 TX DQ/DQS : PASS
9120 06:51:35.559461 RX DATLAT : PASS
9121 06:51:35.562851 RX DQ/DQS(Engine): PASS
9122 06:51:35.566056 TX OE : PASS
9123 06:51:35.566130 All Pass.
9124 06:51:35.566191
9125 06:51:35.570057 DramC Write-DBI on
9126 06:51:35.570127 PER_BANK_REFRESH: Hybrid Mode
9127 06:51:35.572468 TX_TRACKING: ON
9128 06:51:35.582254 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9129 06:51:35.588948 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9130 06:51:35.595396 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9131 06:51:35.598884 [FAST_K] Save calibration result to emmc
9132 06:51:35.602196 sync common calibartion params.
9133 06:51:35.605489 sync cbt_mode0:1, 1:1
9134 06:51:35.608912 dram_init: ddr_geometry: 2
9135 06:51:35.608987 dram_init: ddr_geometry: 2
9136 06:51:35.612734 dram_init: ddr_geometry: 2
9137 06:51:35.615515 0:dram_rank_size:100000000
9138 06:51:35.615588 1:dram_rank_size:100000000
9139 06:51:35.622154 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9140 06:51:35.625485 DFS_SHUFFLE_HW_MODE: ON
9141 06:51:35.628903 dramc_set_vcore_voltage set vcore to 725000
9142 06:51:35.631985 Read voltage for 1600, 0
9143 06:51:35.632059 Vio18 = 0
9144 06:51:35.632120 Vcore = 725000
9145 06:51:35.635119 Vdram = 0
9146 06:51:35.635188 Vddq = 0
9147 06:51:35.635248 Vmddr = 0
9148 06:51:35.638497 switch to 3200 Mbps bootup
9149 06:51:35.638566 [DramcRunTimeConfig]
9150 06:51:35.641821 PHYPLL
9151 06:51:35.641897 DPM_CONTROL_AFTERK: ON
9152 06:51:35.645255 PER_BANK_REFRESH: ON
9153 06:51:35.648417 REFRESH_OVERHEAD_REDUCTION: ON
9154 06:51:35.648488 CMD_PICG_NEW_MODE: OFF
9155 06:51:35.651970 XRTWTW_NEW_MODE: ON
9156 06:51:35.652040 XRTRTR_NEW_MODE: ON
9157 06:51:35.654940 TX_TRACKING: ON
9158 06:51:35.655009 RDSEL_TRACKING: OFF
9159 06:51:35.658135 DQS Precalculation for DVFS: ON
9160 06:51:35.661465 RX_TRACKING: OFF
9161 06:51:35.661541 HW_GATING DBG: ON
9162 06:51:35.664538 ZQCS_ENABLE_LP4: ON
9163 06:51:35.664607 RX_PICG_NEW_MODE: ON
9164 06:51:35.668047 TX_PICG_NEW_MODE: ON
9165 06:51:35.671232 ENABLE_RX_DCM_DPHY: ON
9166 06:51:35.675389 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9167 06:51:35.675477 DUMMY_READ_FOR_TRACKING: OFF
9168 06:51:35.677810 !!! SPM_CONTROL_AFTERK: OFF
9169 06:51:35.681134 !!! SPM could not control APHY
9170 06:51:35.684654 IMPEDANCE_TRACKING: ON
9171 06:51:35.684735 TEMP_SENSOR: ON
9172 06:51:35.687636 HW_SAVE_FOR_SR: OFF
9173 06:51:35.687706 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9174 06:51:35.694828 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9175 06:51:35.694899 Read ODT Tracking: ON
9176 06:51:35.697914 Refresh Rate DeBounce: ON
9177 06:51:35.701081 DFS_NO_QUEUE_FLUSH: ON
9178 06:51:35.704762 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9179 06:51:35.704836 ENABLE_DFS_RUNTIME_MRW: OFF
9180 06:51:35.707343 DDR_RESERVE_NEW_MODE: ON
9181 06:51:35.710553 MR_CBT_SWITCH_FREQ: ON
9182 06:51:35.710633 =========================
9183 06:51:35.730382 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9184 06:51:35.733608 dram_init: ddr_geometry: 2
9185 06:51:35.752262 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9186 06:51:35.755930 dram_init: dram init end (result: 0)
9187 06:51:35.762309 DRAM-K: Full calibration passed in 24423 msecs
9188 06:51:35.765534 MRC: failed to locate region type 0.
9189 06:51:35.765608 DRAM rank0 size:0x100000000,
9190 06:51:35.769110 DRAM rank1 size=0x100000000
9191 06:51:35.778414 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9192 06:51:35.785132 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9193 06:51:35.795188 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9194 06:51:35.801403 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9195 06:51:35.801485 DRAM rank0 size:0x100000000,
9196 06:51:35.805049 DRAM rank1 size=0x100000000
9197 06:51:35.805146 CBMEM:
9198 06:51:35.808465 IMD: root @ 0xfffff000 254 entries.
9199 06:51:35.811149 IMD: root @ 0xffffec00 62 entries.
9200 06:51:35.818112 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9201 06:51:35.820919 WARNING: RO_VPD is uninitialized or empty.
9202 06:51:35.824358 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9203 06:51:35.831885 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9204 06:51:35.844874 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9205 06:51:35.856383 BS: romstage times (exec / console): total (unknown) / 23950 ms
9206 06:51:35.856476
9207 06:51:35.856542
9208 06:51:35.866233 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9209 06:51:35.870197 ARM64: Exception handlers installed.
9210 06:51:35.873010 ARM64: Testing exception
9211 06:51:35.876399 ARM64: Done test exception
9212 06:51:35.876487 Enumerating buses...
9213 06:51:35.879352 Show all devs... Before device enumeration.
9214 06:51:35.882361 Root Device: enabled 1
9215 06:51:35.886412 CPU_CLUSTER: 0: enabled 1
9216 06:51:35.886486 CPU: 00: enabled 1
9217 06:51:35.889455 Compare with tree...
9218 06:51:35.889525 Root Device: enabled 1
9219 06:51:35.892672 CPU_CLUSTER: 0: enabled 1
9220 06:51:35.896642 CPU: 00: enabled 1
9221 06:51:35.896723 Root Device scanning...
9222 06:51:35.899000 scan_static_bus for Root Device
9223 06:51:35.903757 CPU_CLUSTER: 0 enabled
9224 06:51:35.905615 scan_static_bus for Root Device done
9225 06:51:35.909174 scan_bus: bus Root Device finished in 8 msecs
9226 06:51:35.909254 done
9227 06:51:35.916062 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9228 06:51:35.918694 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9229 06:51:35.925511 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9230 06:51:35.932298 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9231 06:51:35.932379 Allocating resources...
9232 06:51:35.935672 Reading resources...
9233 06:51:35.938479 Root Device read_resources bus 0 link: 0
9234 06:51:35.942139 DRAM rank0 size:0x100000000,
9235 06:51:35.942208 DRAM rank1 size=0x100000000
9236 06:51:35.948732 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9237 06:51:35.948807 CPU: 00 missing read_resources
9238 06:51:35.955826 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9239 06:51:35.958411 Root Device read_resources bus 0 link: 0 done
9240 06:51:35.961757 Done reading resources.
9241 06:51:35.964990 Show resources in subtree (Root Device)...After reading.
9242 06:51:35.968124 Root Device child on link 0 CPU_CLUSTER: 0
9243 06:51:35.971630 CPU_CLUSTER: 0 child on link 0 CPU: 00
9244 06:51:35.981941 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9245 06:51:35.982021 CPU: 00
9246 06:51:35.988091 Root Device assign_resources, bus 0 link: 0
9247 06:51:35.991441 CPU_CLUSTER: 0 missing set_resources
9248 06:51:35.994610 Root Device assign_resources, bus 0 link: 0 done
9249 06:51:35.994681 Done setting resources.
9250 06:51:36.001954 Show resources in subtree (Root Device)...After assigning values.
9251 06:51:36.004367 Root Device child on link 0 CPU_CLUSTER: 0
9252 06:51:36.011350 CPU_CLUSTER: 0 child on link 0 CPU: 00
9253 06:51:36.018415 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9254 06:51:36.018503 CPU: 00
9255 06:51:36.021004 Done allocating resources.
9256 06:51:36.027828 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9257 06:51:36.027914 Enabling resources...
9258 06:51:36.031072 done.
9259 06:51:36.034134 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9260 06:51:36.037285 Initializing devices...
9261 06:51:36.037370 Root Device init
9262 06:51:36.040949 init hardware done!
9263 06:51:36.041039 0x00000018: ctrlr->caps
9264 06:51:36.044136 52.000 MHz: ctrlr->f_max
9265 06:51:36.047154 0.400 MHz: ctrlr->f_min
9266 06:51:36.051124 0x40ff8080: ctrlr->voltages
9267 06:51:36.051210 sclk: 390625
9268 06:51:36.051274 Bus Width = 1
9269 06:51:36.054220 sclk: 390625
9270 06:51:36.054302 Bus Width = 1
9271 06:51:36.057301 Early init status = 3
9272 06:51:36.060420 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9273 06:51:36.064849 in-header: 03 fc 00 00 01 00 00 00
9274 06:51:36.068435 in-data: 00
9275 06:51:36.071353 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9276 06:51:36.077532 in-header: 03 fd 00 00 00 00 00 00
9277 06:51:36.081062 in-data:
9278 06:51:36.083703 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9279 06:51:36.087912 in-header: 03 fc 00 00 01 00 00 00
9280 06:51:36.091640 in-data: 00
9281 06:51:36.094702 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9282 06:51:36.100573 in-header: 03 fd 00 00 00 00 00 00
9283 06:51:36.103798 in-data:
9284 06:51:36.107303 [SSUSB] Setting up USB HOST controller...
9285 06:51:36.110347 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9286 06:51:36.113994 [SSUSB] phy power-on done.
9287 06:51:36.116701 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9288 06:51:36.123446 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9289 06:51:36.126630 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9290 06:51:36.133703 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9291 06:51:36.140316 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9292 06:51:36.146435 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9293 06:51:36.153112 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9294 06:51:36.159622 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9295 06:51:36.162833 SPM: binary array size = 0x9dc
9296 06:51:36.166367 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9297 06:51:36.172819 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9298 06:51:36.179621 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9299 06:51:36.185954 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9300 06:51:36.189387 configure_display: Starting display init
9301 06:51:36.223723 anx7625_power_on_init: Init interface.
9302 06:51:36.227012 anx7625_disable_pd_protocol: Disabled PD feature.
9303 06:51:36.230137 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9304 06:51:36.258307 anx7625_start_dp_work: Secure OCM version=00
9305 06:51:36.261505 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9306 06:51:36.276198 sp_tx_get_edid_block: EDID Block = 1
9307 06:51:36.378994 Extracted contents:
9308 06:51:36.382393 header: 00 ff ff ff ff ff ff 00
9309 06:51:36.385858 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9310 06:51:36.389074 version: 01 04
9311 06:51:36.392206 basic params: 95 1f 11 78 0a
9312 06:51:36.395684 chroma info: 76 90 94 55 54 90 27 21 50 54
9313 06:51:36.398642 established: 00 00 00
9314 06:51:36.405705 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9315 06:51:36.412411 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9316 06:51:36.415004 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9317 06:51:36.421785 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9318 06:51:36.428245 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9319 06:51:36.431566 extensions: 00
9320 06:51:36.432079 checksum: fb
9321 06:51:36.432415
9322 06:51:36.438063 Manufacturer: IVO Model 57d Serial Number 0
9323 06:51:36.438506 Made week 0 of 2020
9324 06:51:36.441588 EDID version: 1.4
9325 06:51:36.442088 Digital display
9326 06:51:36.445277 6 bits per primary color channel
9327 06:51:36.448129 DisplayPort interface
9328 06:51:36.448624 Maximum image size: 31 cm x 17 cm
9329 06:51:36.451718 Gamma: 220%
9330 06:51:36.452137 Check DPMS levels
9331 06:51:36.457761 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9332 06:51:36.461412 First detailed timing is preferred timing
9333 06:51:36.464475 Established timings supported:
9334 06:51:36.464895 Standard timings supported:
9335 06:51:36.467897 Detailed timings
9336 06:51:36.471001 Hex of detail: 383680a07038204018303c0035ae10000019
9337 06:51:36.477909 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9338 06:51:36.481237 0780 0798 07c8 0820 hborder 0
9339 06:51:36.484490 0438 043b 0447 0458 vborder 0
9340 06:51:36.487926 -hsync -vsync
9341 06:51:36.488287 Did detailed timing
9342 06:51:36.494237 Hex of detail: 000000000000000000000000000000000000
9343 06:51:36.497570 Manufacturer-specified data, tag 0
9344 06:51:36.500798 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9345 06:51:36.504140 ASCII string: InfoVision
9346 06:51:36.507355 Hex of detail: 000000fe00523134304e574635205248200a
9347 06:51:36.510736 ASCII string: R140NWF5 RH
9348 06:51:36.511102 Checksum
9349 06:51:36.514151 Checksum: 0xfb (valid)
9350 06:51:36.517091 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9351 06:51:36.520482 DSI data_rate: 832800000 bps
9352 06:51:36.527409 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9353 06:51:36.530558 anx7625_parse_edid: pixelclock(138800).
9354 06:51:36.533547 hactive(1920), hsync(48), hfp(24), hbp(88)
9355 06:51:36.536866 vactive(1080), vsync(12), vfp(3), vbp(17)
9356 06:51:36.540757 anx7625_dsi_config: config dsi.
9357 06:51:36.547281 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9358 06:51:36.561147 anx7625_dsi_config: success to config DSI
9359 06:51:36.564804 anx7625_dp_start: MIPI phy setup OK.
9360 06:51:36.567672 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9361 06:51:36.570844 mtk_ddp_mode_set invalid vrefresh 60
9362 06:51:36.574686 main_disp_path_setup
9363 06:51:36.575154 ovl_layer_smi_id_en
9364 06:51:36.577599 ovl_layer_smi_id_en
9365 06:51:36.578121 ccorr_config
9366 06:51:36.578581 aal_config
9367 06:51:36.580727 gamma_config
9368 06:51:36.581147 postmask_config
9369 06:51:36.584678 dither_config
9370 06:51:36.587568 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9371 06:51:36.593866 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9372 06:51:36.597155 Root Device init finished in 555 msecs
9373 06:51:36.601258 CPU_CLUSTER: 0 init
9374 06:51:36.607106 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9375 06:51:36.613880 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9376 06:51:36.614437 APU_MBOX 0x190000b0 = 0x10001
9377 06:51:36.617330 APU_MBOX 0x190001b0 = 0x10001
9378 06:51:36.620617 APU_MBOX 0x190005b0 = 0x10001
9379 06:51:36.623730 APU_MBOX 0x190006b0 = 0x10001
9380 06:51:36.630346 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9381 06:51:36.640369 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9382 06:51:36.652351 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9383 06:51:36.659018 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9384 06:51:36.670553 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9385 06:51:36.680310 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9386 06:51:36.683013 CPU_CLUSTER: 0 init finished in 81 msecs
9387 06:51:36.686383 Devices initialized
9388 06:51:36.689555 Show all devs... After init.
9389 06:51:36.690024 Root Device: enabled 1
9390 06:51:36.692992 CPU_CLUSTER: 0: enabled 1
9391 06:51:36.696240 CPU: 00: enabled 1
9392 06:51:36.699337 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9393 06:51:36.703031 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9394 06:51:36.706283 ELOG: NV offset 0x57f000 size 0x1000
9395 06:51:36.713309 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9396 06:51:36.719468 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9397 06:51:36.722881 ELOG: Event(17) added with size 13 at 2024-02-03 06:51:40 UTC
9398 06:51:36.729496 ELOG: Event(16) added with size 11 at 2024-02-03 06:51:40 UTC
9399 06:51:36.807668 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9400 06:51:36.810665 out: cmd=0x121: 03 db 21 01 00 00 00 00
9401 06:51:36.814529 in-header: 03 da 00 00 2c 00 00 00
9402 06:51:36.827978 in-data: 85 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9403 06:51:36.834108 ELOG: Event(A1) added with size 10 at 2024-02-03 06:51:40 UTC
9404 06:51:36.841009 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9405 06:51:36.847384 ELOG: Event(A0) added with size 9 at 2024-02-03 06:51:40 UTC
9406 06:51:36.850576 elog_add_boot_reason: Logged dev mode boot
9407 06:51:36.853655 BS: BS_POST_DEVICE entry times (exec / console): 76 / 74 ms
9408 06:51:36.857174 Finalize devices...
9409 06:51:36.857412 Devices finalized
9410 06:51:36.863733 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9411 06:51:36.866946 Writing coreboot table at 0xffe64000
9412 06:51:36.870507 0. 000000000010a000-0000000000113fff: RAMSTAGE
9413 06:51:36.874257 1. 0000000040000000-00000000400fffff: RAM
9414 06:51:36.880406 2. 0000000040100000-000000004032afff: RAMSTAGE
9415 06:51:36.883349 3. 000000004032b000-00000000545fffff: RAM
9416 06:51:36.886962 4. 0000000054600000-000000005465ffff: BL31
9417 06:51:36.889857 5. 0000000054660000-00000000ffe63fff: RAM
9418 06:51:36.897030 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9419 06:51:36.900175 7. 0000000100000000-000000023fffffff: RAM
9420 06:51:36.903419 Passing 5 GPIOs to payload:
9421 06:51:36.906810 NAME | PORT | POLARITY | VALUE
9422 06:51:36.913118 EC in RW | 0x000000aa | low | undefined
9423 06:51:36.916595 EC interrupt | 0x00000005 | low | undefined
9424 06:51:36.919584 TPM interrupt | 0x000000ab | high | undefined
9425 06:51:36.926491 SD card detect | 0x00000011 | high | undefined
9426 06:51:36.929622 speaker enable | 0x00000093 | high | undefined
9427 06:51:36.932910 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9428 06:51:36.936504 in-header: 03 f9 00 00 02 00 00 00
9429 06:51:36.939261 in-data: 02 00
9430 06:51:36.942663 ADC[4]: Raw value=902586 ID=7
9431 06:51:36.943017 ADC[3]: Raw value=213916 ID=1
9432 06:51:36.946155 RAM Code: 0x71
9433 06:51:36.949431 ADC[6]: Raw value=75000 ID=0
9434 06:51:36.949817 ADC[5]: Raw value=213546 ID=1
9435 06:51:36.952525 SKU Code: 0x1
9436 06:51:36.959330 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5ea0
9437 06:51:36.959785 coreboot table: 964 bytes.
9438 06:51:36.963071 IMD ROOT 0. 0xfffff000 0x00001000
9439 06:51:36.966060 IMD SMALL 1. 0xffffe000 0x00001000
9440 06:51:36.969240 RO MCACHE 2. 0xffffc000 0x00001104
9441 06:51:36.972829 CONSOLE 3. 0xfff7c000 0x00080000
9442 06:51:36.975822 FMAP 4. 0xfff7b000 0x00000452
9443 06:51:36.979081 TIME STAMP 5. 0xfff7a000 0x00000910
9444 06:51:36.982197 VBOOT WORK 6. 0xfff66000 0x00014000
9445 06:51:36.985959 RAMOOPS 7. 0xffe66000 0x00100000
9446 06:51:36.989285 COREBOOT 8. 0xffe64000 0x00002000
9447 06:51:36.992310 IMD small region:
9448 06:51:36.995631 IMD ROOT 0. 0xffffec00 0x00000400
9449 06:51:36.998905 VPD 1. 0xffffeb80 0x0000006c
9450 06:51:37.002059 MMC STATUS 2. 0xffffeb60 0x00000004
9451 06:51:37.008294 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9452 06:51:37.008713 Probing TPM: done!
9453 06:51:37.015233 Connected to device vid:did:rid of 1ae0:0028:00
9454 06:51:37.021674 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9455 06:51:37.025382 Initialized TPM device CR50 revision 0
9456 06:51:37.028673 Checking cr50 for pending updates
9457 06:51:37.034300 Reading cr50 TPM mode
9458 06:51:37.042552 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9459 06:51:37.049358 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9460 06:51:37.090254 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9461 06:51:37.092568 Checking segment from ROM address 0x40100000
9462 06:51:37.096267 Checking segment from ROM address 0x4010001c
9463 06:51:37.102936 Loading segment from ROM address 0x40100000
9464 06:51:37.103486 code (compression=0)
9465 06:51:37.112476 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9466 06:51:37.119637 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9467 06:51:37.120170 it's not compressed!
9468 06:51:37.127043 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9469 06:51:37.132327 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9470 06:51:37.149417 Loading segment from ROM address 0x4010001c
9471 06:51:37.149495 Entry Point 0x80000000
9472 06:51:37.152667 Loaded segments
9473 06:51:37.156108 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9474 06:51:37.162986 Jumping to boot code at 0x80000000(0xffe64000)
9475 06:51:37.169883 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9476 06:51:37.176291 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9477 06:51:37.183788 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9478 06:51:37.187515 Checking segment from ROM address 0x40100000
9479 06:51:37.190862 Checking segment from ROM address 0x4010001c
9480 06:51:37.197689 Loading segment from ROM address 0x40100000
9481 06:51:37.197866 code (compression=1)
9482 06:51:37.203895 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9483 06:51:37.213873 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9484 06:51:37.214073 using LZMA
9485 06:51:37.223038 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9486 06:51:37.228969 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9487 06:51:37.231881 Loading segment from ROM address 0x4010001c
9488 06:51:37.231956 Entry Point 0x54601000
9489 06:51:37.235200 Loaded segments
9490 06:51:37.238561 NOTICE: MT8192 bl31_setup
9491 06:51:37.245935 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9492 06:51:37.249366 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9493 06:51:37.252588 WARNING: region 0:
9494 06:51:37.255599 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 06:51:37.255669 WARNING: region 1:
9496 06:51:37.262630 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9497 06:51:37.265603 WARNING: region 2:
9498 06:51:37.269595 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9499 06:51:37.272411 WARNING: region 3:
9500 06:51:37.275652 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9501 06:51:37.278813 WARNING: region 4:
9502 06:51:37.286033 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9503 06:51:37.286120 WARNING: region 5:
9504 06:51:37.289255 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 06:51:37.292737 WARNING: region 6:
9506 06:51:37.295790 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 06:51:37.299563 WARNING: region 7:
9508 06:51:37.302300 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 06:51:37.309537 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9510 06:51:37.312357 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9511 06:51:37.315786 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9512 06:51:37.322393 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9513 06:51:37.325785 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9514 06:51:37.329460 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9515 06:51:37.335972 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9516 06:51:37.339101 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9517 06:51:37.346260 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9518 06:51:37.349250 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9519 06:51:37.352490 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9520 06:51:37.359166 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9521 06:51:37.362810 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9522 06:51:37.365744 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9523 06:51:37.372431 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9524 06:51:37.376115 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9525 06:51:37.382690 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9526 06:51:37.386619 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9527 06:51:37.389183 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9528 06:51:37.395420 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9529 06:51:37.398938 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9530 06:51:37.402375 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9531 06:51:37.409396 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9532 06:51:37.412607 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9533 06:51:37.419302 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9534 06:51:37.423038 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9535 06:51:37.428969 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9536 06:51:37.432251 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9537 06:51:37.436062 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9538 06:51:37.442435 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9539 06:51:37.446623 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9540 06:51:37.449369 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9541 06:51:37.456053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9542 06:51:37.459243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9543 06:51:37.462552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9544 06:51:37.465496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9545 06:51:37.472169 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9546 06:51:37.475392 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9547 06:51:37.478755 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9548 06:51:37.482235 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9549 06:51:37.488825 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9550 06:51:37.492170 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9551 06:51:37.495288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9552 06:51:37.498953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9553 06:51:37.505007 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9554 06:51:37.508629 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9555 06:51:37.512092 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9556 06:51:37.518593 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9557 06:51:37.522613 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9558 06:51:37.525215 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9559 06:51:37.532086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9560 06:51:37.535655 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9561 06:51:37.541852 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9562 06:51:37.544947 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9563 06:51:37.551770 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9564 06:51:37.554933 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9565 06:51:37.558130 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9566 06:51:37.564863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9567 06:51:37.568121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9568 06:51:37.574649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9569 06:51:37.577918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9570 06:51:37.585038 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9571 06:51:37.588331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9572 06:51:37.594578 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9573 06:51:37.597941 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9574 06:51:37.602299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9575 06:51:37.608184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9576 06:51:37.611568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9577 06:51:37.617886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9578 06:51:37.621238 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9579 06:51:37.627725 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9580 06:51:37.631025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9581 06:51:37.637967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9582 06:51:37.641029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9583 06:51:37.644345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9584 06:51:37.650853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9585 06:51:37.654418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9586 06:51:37.661429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9587 06:51:37.664425 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9588 06:51:37.670651 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9589 06:51:37.674171 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9590 06:51:37.680865 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9591 06:51:37.684215 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9592 06:51:37.687432 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9593 06:51:37.694155 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9594 06:51:37.697435 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9595 06:51:37.703893 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9596 06:51:37.706961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9597 06:51:37.713877 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9598 06:51:37.716842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9599 06:51:37.723772 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9600 06:51:37.727435 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9601 06:51:37.730092 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9602 06:51:37.736490 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9603 06:51:37.740117 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9604 06:51:37.747083 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9605 06:51:37.750006 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9606 06:51:37.753226 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9607 06:51:37.759880 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9608 06:51:37.763800 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9609 06:51:37.766748 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9610 06:51:37.770267 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9611 06:51:37.776603 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9612 06:51:37.780312 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9613 06:51:37.786408 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9614 06:51:37.790480 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9615 06:51:37.793237 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9616 06:51:37.799878 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9617 06:51:37.803290 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9618 06:51:37.809826 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9619 06:51:37.813316 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9620 06:51:37.816307 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9621 06:51:37.823036 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9622 06:51:37.826497 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9623 06:51:37.833044 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9624 06:51:37.836616 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9625 06:51:37.840294 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9626 06:51:37.846719 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9627 06:51:37.850352 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9628 06:51:37.853137 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9629 06:51:37.856206 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9630 06:51:37.863488 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9631 06:51:37.866699 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9632 06:51:37.869485 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9633 06:51:37.876109 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9634 06:51:37.879118 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9635 06:51:37.882268 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9636 06:51:37.889200 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9637 06:51:37.892545 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9638 06:51:37.899321 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9639 06:51:37.902562 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9640 06:51:37.905914 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9641 06:51:37.912451 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9642 06:51:37.915913 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9643 06:51:37.923254 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9644 06:51:37.925980 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9645 06:51:37.929412 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9646 06:51:37.936016 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9647 06:51:37.939011 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9648 06:51:37.942300 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9649 06:51:37.948985 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9650 06:51:37.952047 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9651 06:51:37.958868 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9652 06:51:37.962405 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9653 06:51:37.965466 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9654 06:51:37.972717 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9655 06:51:37.976350 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9656 06:51:37.982362 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9657 06:51:37.985750 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9658 06:51:37.988885 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9659 06:51:37.995925 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9660 06:51:38.000121 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9661 06:51:38.005543 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9662 06:51:38.008471 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9663 06:51:38.012192 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9664 06:51:38.018618 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9665 06:51:38.021900 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9666 06:51:38.028654 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9667 06:51:38.032284 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9668 06:51:38.035328 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9669 06:51:38.042179 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9670 06:51:38.045147 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9671 06:51:38.051752 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9672 06:51:38.055216 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9673 06:51:38.058536 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9674 06:51:38.065589 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9675 06:51:38.068687 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9676 06:51:38.072316 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9677 06:51:38.078200 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9678 06:51:38.081580 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9679 06:51:38.087951 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9680 06:51:38.091753 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9681 06:51:38.094459 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9682 06:51:38.101635 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9683 06:51:38.104942 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9684 06:51:38.111011 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9685 06:51:38.114203 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9686 06:51:38.120821 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9687 06:51:38.125016 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9688 06:51:38.128192 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9689 06:51:38.134143 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9690 06:51:38.137607 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9691 06:51:38.141245 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9692 06:51:38.147475 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9693 06:51:38.150828 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9694 06:51:38.157101 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9695 06:51:38.160989 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9696 06:51:38.166727 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9697 06:51:38.170419 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9698 06:51:38.173695 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9699 06:51:38.180441 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9700 06:51:38.183458 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9701 06:51:38.189941 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9702 06:51:38.193412 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9703 06:51:38.196632 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9704 06:51:38.203322 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9705 06:51:38.207658 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9706 06:51:38.214340 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9707 06:51:38.217032 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9708 06:51:38.223538 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9709 06:51:38.226740 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9710 06:51:38.229940 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9711 06:51:38.236394 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9712 06:51:38.239934 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9713 06:51:38.246788 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9714 06:51:38.250083 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9715 06:51:38.255895 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9716 06:51:38.259662 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9717 06:51:38.263123 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9718 06:51:38.269176 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9719 06:51:38.272552 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9720 06:51:38.279290 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9721 06:51:38.282921 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9722 06:51:38.289383 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9723 06:51:38.293296 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9724 06:51:38.296840 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9725 06:51:38.303394 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9726 06:51:38.305855 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9727 06:51:38.312515 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9728 06:51:38.316442 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9729 06:51:38.323201 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9730 06:51:38.325857 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9731 06:51:38.328965 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9732 06:51:38.335909 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9733 06:51:38.339052 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9734 06:51:38.345816 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9735 06:51:38.348729 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9736 06:51:38.356210 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9737 06:51:38.358900 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9738 06:51:38.362748 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9739 06:51:38.365518 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9740 06:51:38.371857 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9741 06:51:38.375572 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9742 06:51:38.378366 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9743 06:51:38.382319 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9744 06:51:38.388858 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9745 06:51:38.391865 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9746 06:51:38.398964 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9747 06:51:38.401586 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9748 06:51:38.404907 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9749 06:51:38.411231 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9750 06:51:38.414861 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9751 06:51:38.421282 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9752 06:51:38.424642 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9753 06:51:38.428451 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9754 06:51:38.434716 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9755 06:51:38.437635 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9756 06:51:38.444829 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9757 06:51:38.447750 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9758 06:51:38.451353 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9759 06:51:38.458439 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9760 06:51:38.460693 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9761 06:51:38.463939 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9762 06:51:38.470441 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9763 06:51:38.473759 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9764 06:51:38.477264 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9765 06:51:38.483585 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9766 06:51:38.487128 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9767 06:51:38.493239 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9768 06:51:38.496528 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9769 06:51:38.499938 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9770 06:51:38.506906 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9771 06:51:38.509715 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9772 06:51:38.513103 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9773 06:51:38.520261 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9774 06:51:38.523421 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9775 06:51:38.529507 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9776 06:51:38.532790 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9777 06:51:38.536587 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9778 06:51:38.539721 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9779 06:51:38.546189 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9780 06:51:38.549726 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9781 06:51:38.552566 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9782 06:51:38.555923 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9783 06:51:38.562648 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9784 06:51:38.565925 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9785 06:51:38.569223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9786 06:51:38.572407 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9787 06:51:38.578799 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9788 06:51:38.582799 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9789 06:51:38.585745 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9790 06:51:38.592503 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9791 06:51:38.595882 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9792 06:51:38.598881 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9793 06:51:38.605485 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9794 06:51:38.608855 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9795 06:51:38.615983 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9796 06:51:38.618629 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9797 06:51:38.624884 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9798 06:51:38.628096 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9799 06:51:38.632006 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9800 06:51:38.638390 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9801 06:51:38.641595 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9802 06:51:38.648116 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9803 06:51:38.651865 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9804 06:51:38.657919 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9805 06:51:38.661360 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9806 06:51:38.664793 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9807 06:51:38.671667 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9808 06:51:38.674723 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9809 06:51:38.681389 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9810 06:51:38.684291 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9811 06:51:38.691640 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9812 06:51:38.694734 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9813 06:51:38.697619 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9814 06:51:38.704420 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9815 06:51:38.707344 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9816 06:51:38.714304 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9817 06:51:38.717911 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9818 06:51:38.721202 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9819 06:51:38.727076 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9820 06:51:38.731118 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9821 06:51:38.737114 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9822 06:51:38.740444 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9823 06:51:38.743844 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9824 06:51:38.750249 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9825 06:51:38.753864 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9826 06:51:38.760848 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9827 06:51:38.763554 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9828 06:51:38.770358 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9829 06:51:38.773775 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9830 06:51:38.777508 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9831 06:51:38.784121 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9832 06:51:38.787012 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9833 06:51:38.793213 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9834 06:51:38.797510 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9835 06:51:38.804067 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9836 06:51:38.806307 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9837 06:51:38.809549 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9838 06:51:38.816297 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9839 06:51:38.819561 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9840 06:51:38.826255 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9841 06:51:38.829376 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9842 06:51:38.832623 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9843 06:51:38.839239 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9844 06:51:38.842544 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9845 06:51:38.849258 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9846 06:51:38.853143 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9847 06:51:38.855892 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9848 06:51:38.862386 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9849 06:51:38.866317 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9850 06:51:38.872407 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9851 06:51:38.876008 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9852 06:51:38.882147 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9853 06:51:38.885868 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9854 06:51:38.888898 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9855 06:51:38.895274 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9856 06:51:38.898798 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9857 06:51:38.905534 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9858 06:51:38.908880 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9859 06:51:38.915190 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9860 06:51:38.919020 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9861 06:51:38.922038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9862 06:51:38.928629 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9863 06:51:38.931683 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9864 06:51:38.938753 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9865 06:51:38.942325 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9866 06:51:38.948533 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9867 06:51:38.951840 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9868 06:51:38.954889 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9869 06:51:38.961525 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9870 06:51:38.964519 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9871 06:51:38.971636 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9872 06:51:38.974694 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9873 06:51:38.980902 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9874 06:51:38.984814 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9875 06:51:38.991560 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9876 06:51:38.994258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9877 06:51:39.000770 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9878 06:51:39.004625 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9879 06:51:39.007824 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9880 06:51:39.014594 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9881 06:51:39.017537 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9882 06:51:39.024426 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9883 06:51:39.027323 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9884 06:51:39.034110 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9885 06:51:39.037105 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9886 06:51:39.040443 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9887 06:51:39.046984 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9888 06:51:39.050359 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9889 06:51:39.057210 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9890 06:51:39.060096 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9891 06:51:39.067120 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9892 06:51:39.069856 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9893 06:51:39.076421 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9894 06:51:39.080813 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9895 06:51:39.083745 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9896 06:51:39.089702 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9897 06:51:39.093593 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9898 06:51:39.099656 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9899 06:51:39.103167 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9900 06:51:39.109830 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9901 06:51:39.112987 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9902 06:51:39.119510 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9903 06:51:39.122782 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9904 06:51:39.126149 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9905 06:51:39.132572 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9906 06:51:39.135748 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9907 06:51:39.142872 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9908 06:51:39.145700 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9909 06:51:39.152059 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9910 06:51:39.155712 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9911 06:51:39.158920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9912 06:51:39.165678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9913 06:51:39.168839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9914 06:51:39.175565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9915 06:51:39.178931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9916 06:51:39.185618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9917 06:51:39.188891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9918 06:51:39.194856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9919 06:51:39.198712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9920 06:51:39.204855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9921 06:51:39.208297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9922 06:51:39.215601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9923 06:51:39.218069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9924 06:51:39.224508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9925 06:51:39.228083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9926 06:51:39.234744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9927 06:51:39.237789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9928 06:51:39.244347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9929 06:51:39.247370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9930 06:51:39.254313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9931 06:51:39.257994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9932 06:51:39.264602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9933 06:51:39.267707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9934 06:51:39.274296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9935 06:51:39.277865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9936 06:51:39.284278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9937 06:51:39.287490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9938 06:51:39.294072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9939 06:51:39.297221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9940 06:51:39.303985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9941 06:51:39.307882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9942 06:51:39.313637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9943 06:51:39.317399 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9944 06:51:39.320792 INFO: [APUAPC] vio 0
9945 06:51:39.323775 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9946 06:51:39.330551 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9947 06:51:39.333739 INFO: [APUAPC] D0_APC_0: 0x400510
9948 06:51:39.336997 INFO: [APUAPC] D0_APC_1: 0x0
9949 06:51:39.340124 INFO: [APUAPC] D0_APC_2: 0x1540
9950 06:51:39.340545 INFO: [APUAPC] D0_APC_3: 0x0
9951 06:51:39.343733 INFO: [APUAPC] D1_APC_0: 0xffffffff
9952 06:51:39.350335 INFO: [APUAPC] D1_APC_1: 0xffffffff
9953 06:51:39.353546 INFO: [APUAPC] D1_APC_2: 0x3fffff
9954 06:51:39.353964 INFO: [APUAPC] D1_APC_3: 0x0
9955 06:51:39.356828 INFO: [APUAPC] D2_APC_0: 0xffffffff
9956 06:51:39.360604 INFO: [APUAPC] D2_APC_1: 0xffffffff
9957 06:51:39.363134 INFO: [APUAPC] D2_APC_2: 0x3fffff
9958 06:51:39.366858 INFO: [APUAPC] D2_APC_3: 0x0
9959 06:51:39.370125 INFO: [APUAPC] D3_APC_0: 0xffffffff
9960 06:51:39.373272 INFO: [APUAPC] D3_APC_1: 0xffffffff
9961 06:51:39.376428 INFO: [APUAPC] D3_APC_2: 0x3fffff
9962 06:51:39.380115 INFO: [APUAPC] D3_APC_3: 0x0
9963 06:51:39.382907 INFO: [APUAPC] D4_APC_0: 0xffffffff
9964 06:51:39.387140 INFO: [APUAPC] D4_APC_1: 0xffffffff
9965 06:51:39.389752 INFO: [APUAPC] D4_APC_2: 0x3fffff
9966 06:51:39.392745 INFO: [APUAPC] D4_APC_3: 0x0
9967 06:51:39.396264 INFO: [APUAPC] D5_APC_0: 0xffffffff
9968 06:51:39.399214 INFO: [APUAPC] D5_APC_1: 0xffffffff
9969 06:51:39.403238 INFO: [APUAPC] D5_APC_2: 0x3fffff
9970 06:51:39.406339 INFO: [APUAPC] D5_APC_3: 0x0
9971 06:51:39.409588 INFO: [APUAPC] D6_APC_0: 0xffffffff
9972 06:51:39.413000 INFO: [APUAPC] D6_APC_1: 0xffffffff
9973 06:51:39.416043 INFO: [APUAPC] D6_APC_2: 0x3fffff
9974 06:51:39.419493 INFO: [APUAPC] D6_APC_3: 0x0
9975 06:51:39.422353 INFO: [APUAPC] D7_APC_0: 0xffffffff
9976 06:51:39.425675 INFO: [APUAPC] D7_APC_1: 0xffffffff
9977 06:51:39.428976 INFO: [APUAPC] D7_APC_2: 0x3fffff
9978 06:51:39.432596 INFO: [APUAPC] D7_APC_3: 0x0
9979 06:51:39.435491 INFO: [APUAPC] D8_APC_0: 0xffffffff
9980 06:51:39.439022 INFO: [APUAPC] D8_APC_1: 0xffffffff
9981 06:51:39.442050 INFO: [APUAPC] D8_APC_2: 0x3fffff
9982 06:51:39.445322 INFO: [APUAPC] D8_APC_3: 0x0
9983 06:51:39.449381 INFO: [APUAPC] D9_APC_0: 0xffffffff
9984 06:51:39.451716 INFO: [APUAPC] D9_APC_1: 0xffffffff
9985 06:51:39.455689 INFO: [APUAPC] D9_APC_2: 0x3fffff
9986 06:51:39.458546 INFO: [APUAPC] D9_APC_3: 0x0
9987 06:51:39.461902 INFO: [APUAPC] D10_APC_0: 0xffffffff
9988 06:51:39.465156 INFO: [APUAPC] D10_APC_1: 0xffffffff
9989 06:51:39.468751 INFO: [APUAPC] D10_APC_2: 0x3fffff
9990 06:51:39.472260 INFO: [APUAPC] D10_APC_3: 0x0
9991 06:51:39.475381 INFO: [APUAPC] D11_APC_0: 0xffffffff
9992 06:51:39.478383 INFO: [APUAPC] D11_APC_1: 0xffffffff
9993 06:51:39.481660 INFO: [APUAPC] D11_APC_2: 0x3fffff
9994 06:51:39.485037 INFO: [APUAPC] D11_APC_3: 0x0
9995 06:51:39.488597 INFO: [APUAPC] D12_APC_0: 0xffffffff
9996 06:51:39.492041 INFO: [APUAPC] D12_APC_1: 0xffffffff
9997 06:51:39.495545 INFO: [APUAPC] D12_APC_2: 0x3fffff
9998 06:51:39.498553 INFO: [APUAPC] D12_APC_3: 0x0
9999 06:51:39.501918 INFO: [APUAPC] D13_APC_0: 0xffffffff
10000 06:51:39.505095 INFO: [APUAPC] D13_APC_1: 0xffffffff
10001 06:51:39.508288 INFO: [APUAPC] D13_APC_2: 0x3fffff
10002 06:51:39.511602 INFO: [APUAPC] D13_APC_3: 0x0
10003 06:51:39.514833 INFO: [APUAPC] D14_APC_0: 0xffffffff
10004 06:51:39.518642 INFO: [APUAPC] D14_APC_1: 0xffffffff
10005 06:51:39.521765 INFO: [APUAPC] D14_APC_2: 0x3fffff
10006 06:51:39.525319 INFO: [APUAPC] D14_APC_3: 0x0
10007 06:51:39.528785 INFO: [APUAPC] D15_APC_0: 0xffffffff
10008 06:51:39.531823 INFO: [APUAPC] D15_APC_1: 0xffffffff
10009 06:51:39.535087 INFO: [APUAPC] D15_APC_2: 0x3fffff
10010 06:51:39.538255 INFO: [APUAPC] D15_APC_3: 0x0
10011 06:51:39.541769 INFO: [APUAPC] APC_CON: 0x4
10012 06:51:39.545135 INFO: [NOCDAPC] D0_APC_0: 0x0
10013 06:51:39.548111 INFO: [NOCDAPC] D0_APC_1: 0x0
10014 06:51:39.551642 INFO: [NOCDAPC] D1_APC_0: 0x0
10015 06:51:39.554884 INFO: [NOCDAPC] D1_APC_1: 0xfff
10016 06:51:39.557694 INFO: [NOCDAPC] D2_APC_0: 0x0
10017 06:51:39.557776 INFO: [NOCDAPC] D2_APC_1: 0xfff
10018 06:51:39.560822 INFO: [NOCDAPC] D3_APC_0: 0x0
10019 06:51:39.564713 INFO: [NOCDAPC] D3_APC_1: 0xfff
10020 06:51:39.567632 INFO: [NOCDAPC] D4_APC_0: 0x0
10021 06:51:39.571331 INFO: [NOCDAPC] D4_APC_1: 0xfff
10022 06:51:39.574718 INFO: [NOCDAPC] D5_APC_0: 0x0
10023 06:51:39.577423 INFO: [NOCDAPC] D5_APC_1: 0xfff
10024 06:51:39.580692 INFO: [NOCDAPC] D6_APC_0: 0x0
10025 06:51:39.584012 INFO: [NOCDAPC] D6_APC_1: 0xfff
10026 06:51:39.587554 INFO: [NOCDAPC] D7_APC_0: 0x0
10027 06:51:39.591115 INFO: [NOCDAPC] D7_APC_1: 0xfff
10028 06:51:39.593790 INFO: [NOCDAPC] D8_APC_0: 0x0
10029 06:51:39.593871 INFO: [NOCDAPC] D8_APC_1: 0xfff
10030 06:51:39.597541 INFO: [NOCDAPC] D9_APC_0: 0x0
10031 06:51:39.600699 INFO: [NOCDAPC] D9_APC_1: 0xfff
10032 06:51:39.604013 INFO: [NOCDAPC] D10_APC_0: 0x0
10033 06:51:39.607156 INFO: [NOCDAPC] D10_APC_1: 0xfff
10034 06:51:39.610436 INFO: [NOCDAPC] D11_APC_0: 0x0
10035 06:51:39.613795 INFO: [NOCDAPC] D11_APC_1: 0xfff
10036 06:51:39.617208 INFO: [NOCDAPC] D12_APC_0: 0x0
10037 06:51:39.620706 INFO: [NOCDAPC] D12_APC_1: 0xfff
10038 06:51:39.624277 INFO: [NOCDAPC] D13_APC_0: 0x0
10039 06:51:39.627384 INFO: [NOCDAPC] D13_APC_1: 0xfff
10040 06:51:39.630769 INFO: [NOCDAPC] D14_APC_0: 0x0
10041 06:51:39.633543 INFO: [NOCDAPC] D14_APC_1: 0xfff
10042 06:51:39.637337 INFO: [NOCDAPC] D15_APC_0: 0x0
10043 06:51:39.640545 INFO: [NOCDAPC] D15_APC_1: 0xfff
10044 06:51:39.640627 INFO: [NOCDAPC] APC_CON: 0x4
10045 06:51:39.643735 INFO: [APUAPC] set_apusys_apc done
10046 06:51:39.647067 INFO: [DEVAPC] devapc_init done
10047 06:51:39.653957 INFO: GICv3 without legacy support detected.
10048 06:51:39.656711 INFO: ARM GICv3 driver initialized in EL3
10049 06:51:39.659925 INFO: Maximum SPI INTID supported: 639
10050 06:51:39.663184 INFO: BL31: Initializing runtime services
10051 06:51:39.669994 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10052 06:51:39.673021 INFO: SPM: enable CPC mode
10053 06:51:39.676361 INFO: mcdi ready for mcusys-off-idle and system suspend
10054 06:51:39.682918 INFO: BL31: Preparing for EL3 exit to normal world
10055 06:51:39.686035 INFO: Entry point address = 0x80000000
10056 06:51:39.686117 INFO: SPSR = 0x8
10057 06:51:39.693678
10058 06:51:39.693760
10059 06:51:39.693826
10060 06:51:39.697540 Starting depthcharge on Spherion...
10061 06:51:39.697622
10062 06:51:39.697686 Wipe memory regions:
10063 06:51:39.697745
10064 06:51:39.698413 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10065 06:51:39.698514 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10066 06:51:39.698597 Setting prompt string to ['asurada:']
10067 06:51:39.698678 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10068 06:51:39.700131 [0x00000040000000, 0x00000054600000)
10069 06:51:39.823116
10070 06:51:39.823263 [0x00000054660000, 0x00000080000000)
10071 06:51:40.083802
10072 06:51:40.084326 [0x000000821a7280, 0x000000ffe64000)
10073 06:51:40.828655
10074 06:51:40.829180 [0x00000100000000, 0x00000240000000)
10075 06:51:42.719024
10076 06:51:42.722227 Initializing XHCI USB controller at 0x11200000.
10077 06:51:43.759944
10078 06:51:43.763051 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10079 06:51:43.763148
10080 06:51:43.763214
10081 06:51:43.763275
10082 06:51:43.763560 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10084 06:51:43.863943 asurada: tftpboot 192.168.201.1 12694815/tftp-deploy-s18jvg7m/kernel/image.itb 12694815/tftp-deploy-s18jvg7m/kernel/cmdline
10085 06:51:43.864132 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 06:51:43.864268 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10087 06:51:43.868491 tftpboot 192.168.201.1 12694815/tftp-deploy-s18jvg7m/kernel/image.ittp-deploy-s18jvg7m/kernel/cmdline
10088 06:51:43.868578
10089 06:51:43.868644 Waiting for link
10090 06:51:44.029632
10091 06:51:44.029783 R8152: Initializing
10092 06:51:44.029853
10093 06:51:44.032691 Version 6 (ocp_data = 5c30)
10094 06:51:44.032775
10095 06:51:44.035550 R8152: Done initializing
10096 06:51:44.035633
10097 06:51:44.035699 Adding net device
10098 06:51:46.316185
10099 06:51:46.316783 done.
10100 06:51:46.317158
10101 06:51:46.317507 MAC: 00:24:32:30:7c:7b
10102 06:51:46.317845
10103 06:51:46.318915 Sending DHCP discover... done.
10104 06:51:46.319415
10105 06:51:46.322495 Waiting for reply... done.
10106 06:51:46.322917
10107 06:51:46.327995 Sending DHCP request... done.
10108 06:51:46.328590
10109 06:51:46.371813 Waiting for reply... done.
10110 06:51:46.372142
10111 06:51:46.372304 My ip is 192.168.201.14
10112 06:51:46.372428
10113 06:51:46.374686 The DHCP server ip is 192.168.201.1
10114 06:51:46.374898
10115 06:51:46.381054 TFTP server IP predefined by user: 192.168.201.1
10116 06:51:46.381268
10117 06:51:46.388141 Bootfile predefined by user: 12694815/tftp-deploy-s18jvg7m/kernel/image.itb
10118 06:51:46.388353
10119 06:51:46.388472 Sending tftp read request... done.
10120 06:51:46.391130
10121 06:51:46.395345 Waiting for the transfer...
10122 06:51:46.395487
10123 06:51:47.111190 00000000 ################################################################
10124 06:51:47.111754
10125 06:51:47.835461 00080000 ################################################################
10126 06:51:47.835987
10127 06:51:48.565615 00100000 ################################################################
10128 06:51:48.566154
10129 06:51:49.308278 00180000 ################################################################
10130 06:51:49.308823
10131 06:51:50.022375 00200000 ################################################################
10132 06:51:50.022910
10133 06:51:50.728600 00280000 ################################################################
10134 06:51:50.729127
10135 06:51:51.457269 00300000 ################################################################
10136 06:51:51.457917
10137 06:51:52.176469 00380000 ################################################################
10138 06:51:52.177029
10139 06:51:52.901171 00400000 ################################################################
10140 06:51:52.901734
10141 06:51:53.633306 00480000 ################################################################
10142 06:51:53.633847
10143 06:51:54.369523 00500000 ################################################################
10144 06:51:54.370085
10145 06:51:55.092762 00580000 ################################################################
10146 06:51:55.093319
10147 06:51:55.812321 00600000 ################################################################
10148 06:51:55.812874
10149 06:51:56.528027 00680000 ################################################################
10150 06:51:56.528544
10151 06:51:57.241627 00700000 ################################################################
10152 06:51:57.242156
10153 06:51:57.956911 00780000 ################################################################
10154 06:51:57.957439
10155 06:51:58.669096 00800000 ################################################################
10156 06:51:58.669691
10157 06:51:59.403011 00880000 ################################################################
10158 06:51:59.403686
10159 06:52:00.131962 00900000 ################################################################
10160 06:52:00.132489
10161 06:52:00.848973 00980000 ################################################################
10162 06:52:00.849521
10163 06:52:01.551591 00a00000 ################################################################
10164 06:52:01.552129
10165 06:52:02.268295 00a80000 ################################################################
10166 06:52:02.268818
10167 06:52:02.927864 00b00000 ################################################################
10168 06:52:02.928401
10169 06:52:03.649628 00b80000 ################################################################
10170 06:52:03.650150
10171 06:52:04.256815 00c00000 ################################################################
10172 06:52:04.256954
10173 06:52:04.847877 00c80000 ################################################################
10174 06:52:04.848042
10175 06:52:05.426502 00d00000 ################################################################
10176 06:52:05.426654
10177 06:52:06.013346 00d80000 ################################################################
10178 06:52:06.013495
10179 06:52:06.600980 00e00000 ################################################################
10180 06:52:06.601137
10181 06:52:07.200530 00e80000 ################################################################
10182 06:52:07.200683
10183 06:52:07.793328 00f00000 ################################################################
10184 06:52:07.793483
10185 06:52:08.387553 00f80000 ################################################################
10186 06:52:08.387705
10187 06:52:08.970541 01000000 ################################################################
10188 06:52:08.970692
10189 06:52:09.554289 01080000 ################################################################
10190 06:52:09.554436
10191 06:52:10.137363 01100000 ################################################################
10192 06:52:10.137512
10193 06:52:10.725035 01180000 ################################################################
10194 06:52:10.725192
10195 06:52:11.317483 01200000 ################################################################
10196 06:52:11.317636
10197 06:52:11.889781 01280000 ################################################################
10198 06:52:11.889948
10199 06:52:12.464152 01300000 ################################################################
10200 06:52:12.464310
10201 06:52:13.065055 01380000 ################################################################
10202 06:52:13.065206
10203 06:52:13.649463 01400000 ################################################################
10204 06:52:13.649622
10205 06:52:14.235765 01480000 ################################################################
10206 06:52:14.235924
10207 06:52:14.839555 01500000 ################################################################
10208 06:52:14.839717
10209 06:52:15.445714 01580000 ################################################################
10210 06:52:15.445877
10211 06:52:16.047867 01600000 ################################################################
10212 06:52:16.048025
10213 06:52:16.650595 01680000 ################################################################
10214 06:52:16.650756
10215 06:52:17.258114 01700000 ################################################################
10216 06:52:17.258276
10217 06:52:17.852747 01780000 ################################################################
10218 06:52:17.852906
10219 06:52:18.412019 01800000 ################################################################
10220 06:52:18.412182
10221 06:52:19.007978 01880000 ################################################################
10222 06:52:19.008132
10223 06:52:19.596039 01900000 ################################################################
10224 06:52:19.596201
10225 06:52:20.196717 01980000 ################################################################
10226 06:52:20.196909
10227 06:52:20.795304 01a00000 ################################################################
10228 06:52:20.795508
10229 06:52:21.400742 01a80000 ################################################################
10230 06:52:21.400924
10231 06:52:22.002703 01b00000 ################################################################
10232 06:52:22.002897
10233 06:52:22.605014 01b80000 ################################################################
10234 06:52:22.605206
10235 06:52:23.183961 01c00000 ################################################################
10236 06:52:23.184152
10237 06:52:23.199834 01c80000 ## done.
10238 06:52:23.199954
10239 06:52:23.203087 The bootfile was 29898474 bytes long.
10240 06:52:23.203198
10241 06:52:23.206277 Sending tftp read request... done.
10242 06:52:23.206385
10243 06:52:23.206479 Waiting for the transfer...
10244 06:52:23.206569
10245 06:52:23.209818 00000000 # done.
10246 06:52:23.209928
10247 06:52:23.217560 Command line loaded dynamically from TFTP file: 12694815/tftp-deploy-s18jvg7m/kernel/cmdline
10248 06:52:23.217671
10249 06:52:23.239551 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694815/extract-nfsrootfs-vip9dcsz,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10250 06:52:23.239700
10251 06:52:23.239797 Loading FIT.
10252 06:52:23.239889
10253 06:52:23.242670 Image ramdisk-1 has 17798580 bytes.
10254 06:52:23.242776
10255 06:52:23.245873 Image fdt-1 has 47278 bytes.
10256 06:52:23.245981
10257 06:52:23.249315 Image kernel-1 has 12050581 bytes.
10258 06:52:23.249422
10259 06:52:23.259456 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10260 06:52:23.259567
10261 06:52:23.276683 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10262 06:52:23.276804
10263 06:52:23.282954 Choosing best match conf-1 for compat google,spherion-rev2.
10264 06:52:23.283063
10265 06:52:23.290063 Connected to device vid:did:rid of 1ae0:0028:00
10266 06:52:23.298478
10267 06:52:23.301977 tpm_get_response: command 0x17b, return code 0x0
10268 06:52:23.302085
10269 06:52:23.305828 ec_init: CrosEC protocol v3 supported (256, 248)
10270 06:52:23.309629
10271 06:52:23.312568 tpm_cleanup: add release locality here.
10272 06:52:23.312675
10273 06:52:23.312769 Shutting down all USB controllers.
10274 06:52:23.315430
10275 06:52:23.315535 Removing current net device
10276 06:52:23.315630
10277 06:52:23.322299 Exiting depthcharge with code 4 at timestamp: 72958798
10278 06:52:23.322409
10279 06:52:23.326443 LZMA decompressing kernel-1 to 0x821a6718
10280 06:52:23.326549
10281 06:52:23.329378 LZMA decompressing kernel-1 to 0x40000000
10282 06:52:24.828172
10283 06:52:24.828368 jumping to kernel
10284 06:52:24.829007 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10285 06:52:24.829145 start: 2.2.5 auto-login-action (timeout 00:03:40) [common]
10286 06:52:24.829253 Setting prompt string to ['Linux version [0-9]']
10287 06:52:24.829352 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10288 06:52:24.829455 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10289 06:52:24.909732
10290 06:52:24.912553 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10291 06:52:24.916580 start: 2.2.5.1 login-action (timeout 00:03:40) [common]
10292 06:52:24.916702 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10293 06:52:24.916804 Setting prompt string to []
10294 06:52:24.916910 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10295 06:52:24.917017 Using line separator: #'\n'#
10296 06:52:24.917107 No login prompt set.
10297 06:52:24.917202 Parsing kernel messages
10298 06:52:24.917290 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10299 06:52:24.917453 [login-action] Waiting for messages, (timeout 00:03:40)
10300 06:52:24.935702 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10301 06:52:24.938919 [ 0.000000] random: crng init done
10302 06:52:24.945495 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10303 06:52:24.949433 [ 0.000000] efi: UEFI not found.
10304 06:52:24.955672 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10305 06:52:24.962689 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10306 06:52:24.972767 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10307 06:52:24.982051 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10308 06:52:24.988679 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10309 06:52:24.995607 [ 0.000000] printk: bootconsole [mtk8250] enabled
10310 06:52:25.001793 [ 0.000000] NUMA: No NUMA configuration found
10311 06:52:25.009195 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10312 06:52:25.011542 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10313 06:52:25.014643 [ 0.000000] Zone ranges:
10314 06:52:25.021571 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10315 06:52:25.024970 [ 0.000000] DMA32 empty
10316 06:52:25.031269 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10317 06:52:25.034627 [ 0.000000] Movable zone start for each node
10318 06:52:25.038000 [ 0.000000] Early memory node ranges
10319 06:52:25.044496 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10320 06:52:25.051188 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10321 06:52:25.058568 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10322 06:52:25.064362 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10323 06:52:25.071039 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10324 06:52:25.077595 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10325 06:52:25.133776 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10326 06:52:25.140542 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10327 06:52:25.146904 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10328 06:52:25.150708 [ 0.000000] psci: probing for conduit method from DT.
10329 06:52:25.156792 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10330 06:52:25.160470 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10331 06:52:25.167312 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10332 06:52:25.170011 [ 0.000000] psci: SMC Calling Convention v1.2
10333 06:52:25.177247 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10334 06:52:25.180144 [ 0.000000] Detected VIPT I-cache on CPU0
10335 06:52:25.186579 [ 0.000000] CPU features: detected: GIC system register CPU interface
10336 06:52:25.193515 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10337 06:52:25.199713 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10338 06:52:25.206069 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10339 06:52:25.216665 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10340 06:52:25.223255 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10341 06:52:25.226607 [ 0.000000] alternatives: applying boot alternatives
10342 06:52:25.232504 [ 0.000000] Fallback order for Node 0: 0
10343 06:52:25.239114 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10344 06:52:25.242286 [ 0.000000] Policy zone: Normal
10345 06:52:25.265342 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694815/extract-nfsrootfs-vip9dcsz,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10346 06:52:25.275185 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10347 06:52:25.286863 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10348 06:52:25.296515 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10349 06:52:25.302944 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10350 06:52:25.307054 <6>[ 0.000000] software IO TLB: area num 8.
10351 06:52:25.362811 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10352 06:52:25.512165 <6>[ 0.000000] Memory: 7949868K/8385536K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 402900K reserved, 32768K cma-reserved)
10353 06:52:25.519110 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10354 06:52:25.525153 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10355 06:52:25.528203 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10356 06:52:25.535462 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10357 06:52:25.541720 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10358 06:52:25.545051 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10359 06:52:25.554933 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10360 06:52:25.561900 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10361 06:52:25.568070 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10362 06:52:25.574871 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10363 06:52:25.578045 <6>[ 0.000000] GICv3: 608 SPIs implemented
10364 06:52:25.581970 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10365 06:52:25.587729 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10366 06:52:25.591676 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10367 06:52:25.597708 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10368 06:52:25.611176 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10369 06:52:25.624589 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10370 06:52:25.630939 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10371 06:52:25.638677 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10372 06:52:25.651955 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10373 06:52:25.658756 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10374 06:52:25.665485 <6>[ 0.009179] Console: colour dummy device 80x25
10375 06:52:25.674802 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10376 06:52:25.682181 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10377 06:52:25.685017 <6>[ 0.029248] LSM: Security Framework initializing
10378 06:52:25.691674 <6>[ 0.034186] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10379 06:52:25.701117 <6>[ 0.042051] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10380 06:52:25.711224 <6>[ 0.051469] cblist_init_generic: Setting adjustable number of callback queues.
10381 06:52:25.717396 <6>[ 0.058912] cblist_init_generic: Setting shift to 3 and lim to 1.
10382 06:52:25.724356 <6>[ 0.065251] cblist_init_generic: Setting adjustable number of callback queues.
10383 06:52:25.730851 <6>[ 0.072724] cblist_init_generic: Setting shift to 3 and lim to 1.
10384 06:52:25.734513 <6>[ 0.079126] rcu: Hierarchical SRCU implementation.
10385 06:52:25.740604 <6>[ 0.084141] rcu: Max phase no-delay instances is 1000.
10386 06:52:25.747110 <6>[ 0.091202] EFI services will not be available.
10387 06:52:25.750348 <6>[ 0.096187] smp: Bringing up secondary CPUs ...
10388 06:52:25.759377 <6>[ 0.101239] Detected VIPT I-cache on CPU1
10389 06:52:25.766085 <6>[ 0.101307] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10390 06:52:25.772440 <6>[ 0.101338] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10391 06:52:25.775806 <6>[ 0.101673] Detected VIPT I-cache on CPU2
10392 06:52:25.786060 <6>[ 0.101723] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10393 06:52:25.792289 <6>[ 0.101743] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10394 06:52:25.796024 <6>[ 0.101992] Detected VIPT I-cache on CPU3
10395 06:52:25.803328 <6>[ 0.102033] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10396 06:52:25.808881 <6>[ 0.102047] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10397 06:52:25.815326 <6>[ 0.102337] CPU features: detected: Spectre-v4
10398 06:52:25.818625 <6>[ 0.102343] CPU features: detected: Spectre-BHB
10399 06:52:25.822309 <6>[ 0.102349] Detected PIPT I-cache on CPU4
10400 06:52:25.828622 <6>[ 0.102405] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10401 06:52:25.835480 <6>[ 0.102421] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10402 06:52:25.841772 <6>[ 0.102714] Detected PIPT I-cache on CPU5
10403 06:52:25.848955 <6>[ 0.102777] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10404 06:52:25.854834 <6>[ 0.102794] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10405 06:52:25.858538 <6>[ 0.103076] Detected PIPT I-cache on CPU6
10406 06:52:25.867996 <6>[ 0.103140] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10407 06:52:25.875088 <6>[ 0.103156] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10408 06:52:25.878042 <6>[ 0.103454] Detected PIPT I-cache on CPU7
10409 06:52:25.884660 <6>[ 0.103517] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10410 06:52:25.891106 <6>[ 0.103533] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10411 06:52:25.894358 <6>[ 0.103580] smp: Brought up 1 node, 8 CPUs
10412 06:52:25.900730 <6>[ 0.245138] SMP: Total of 8 processors activated.
10413 06:52:25.907544 <6>[ 0.250060] CPU features: detected: 32-bit EL0 Support
10414 06:52:25.914633 <6>[ 0.255455] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10415 06:52:25.920746 <6>[ 0.264256] CPU features: detected: Common not Private translations
10416 06:52:25.927598 <6>[ 0.270731] CPU features: detected: CRC32 instructions
10417 06:52:25.933801 <6>[ 0.276083] CPU features: detected: RCpc load-acquire (LDAPR)
10418 06:52:25.937435 <6>[ 0.282043] CPU features: detected: LSE atomic instructions
10419 06:52:25.943834 <6>[ 0.287825] CPU features: detected: Privileged Access Never
10420 06:52:25.950788 <6>[ 0.293604] CPU features: detected: RAS Extension Support
10421 06:52:25.956927 <6>[ 0.299248] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10422 06:52:25.960370 <6>[ 0.306519] CPU: All CPU(s) started at EL2
10423 06:52:25.966846 <6>[ 0.310863] alternatives: applying system-wide alternatives
10424 06:52:25.977500 <6>[ 0.321577] devtmpfs: initialized
10425 06:52:25.989905 <6>[ 0.330507] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10426 06:52:25.999706 <6>[ 0.340467] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10427 06:52:26.006253 <6>[ 0.348679] pinctrl core: initialized pinctrl subsystem
10428 06:52:26.009943 <6>[ 0.355346] DMI not present or invalid.
10429 06:52:26.016113 <6>[ 0.359756] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10430 06:52:26.026082 <6>[ 0.366633] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10431 06:52:26.032516 <6>[ 0.374219] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10432 06:52:26.042265 <6>[ 0.382443] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10433 06:52:26.045941 <6>[ 0.390681] audit: initializing netlink subsys (disabled)
10434 06:52:26.055829 <5>[ 0.396373] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10435 06:52:26.062663 <6>[ 0.397074] thermal_sys: Registered thermal governor 'step_wise'
10436 06:52:26.068879 <6>[ 0.404341] thermal_sys: Registered thermal governor 'power_allocator'
10437 06:52:26.072005 <6>[ 0.410595] cpuidle: using governor menu
10438 06:52:26.079214 <6>[ 0.421558] NET: Registered PF_QIPCRTR protocol family
10439 06:52:26.085313 <6>[ 0.427036] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10440 06:52:26.091842 <6>[ 0.434140] ASID allocator initialised with 32768 entries
10441 06:52:26.095367 <6>[ 0.440718] Serial: AMBA PL011 UART driver
10442 06:52:26.105151 <4>[ 0.449500] Trying to register duplicate clock ID: 134
10443 06:52:26.159540 <6>[ 0.506641] KASLR enabled
10444 06:52:26.173713 <6>[ 0.514401] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10445 06:52:26.179950 <6>[ 0.521414] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10446 06:52:26.186972 <6>[ 0.527902] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10447 06:52:26.193472 <6>[ 0.534909] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10448 06:52:26.199998 <6>[ 0.541396] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10449 06:52:26.206712 <6>[ 0.548400] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10450 06:52:26.213563 <6>[ 0.554890] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10451 06:52:26.219897 <6>[ 0.561899] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10452 06:52:26.222857 <6>[ 0.569405] ACPI: Interpreter disabled.
10453 06:52:26.232084 <6>[ 0.575840] iommu: Default domain type: Translated
10454 06:52:26.238652 <6>[ 0.580950] iommu: DMA domain TLB invalidation policy: strict mode
10455 06:52:26.241937 <5>[ 0.587606] SCSI subsystem initialized
10456 06:52:26.248754 <6>[ 0.591772] usbcore: registered new interface driver usbfs
10457 06:52:26.255352 <6>[ 0.597505] usbcore: registered new interface driver hub
10458 06:52:26.258121 <6>[ 0.603053] usbcore: registered new device driver usb
10459 06:52:26.264703 <6>[ 0.609152] pps_core: LinuxPPS API ver. 1 registered
10460 06:52:26.274732 <6>[ 0.614346] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10461 06:52:26.278389 <6>[ 0.623691] PTP clock support registered
10462 06:52:26.281779 <6>[ 0.627934] EDAC MC: Ver: 3.0.0
10463 06:52:26.289229 <6>[ 0.633084] FPGA manager framework
10464 06:52:26.296341 <6>[ 0.636764] Advanced Linux Sound Architecture Driver Initialized.
10465 06:52:26.298532 <6>[ 0.643536] vgaarb: loaded
10466 06:52:26.305347 <6>[ 0.646694] clocksource: Switched to clocksource arch_sys_counter
10467 06:52:26.308551 <5>[ 0.653135] VFS: Disk quotas dquot_6.6.0
10468 06:52:26.315166 <6>[ 0.657320] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10469 06:52:26.318781 <6>[ 0.664505] pnp: PnP ACPI: disabled
10470 06:52:26.326925 <6>[ 0.671163] NET: Registered PF_INET protocol family
10471 06:52:26.336995 <6>[ 0.676764] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10472 06:52:26.348080 <6>[ 0.689057] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10473 06:52:26.358011 <6>[ 0.697873] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10474 06:52:26.364413 <6>[ 0.705845] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10475 06:52:26.375100 <6>[ 0.714548] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10476 06:52:26.380801 <6>[ 0.724288] TCP: Hash tables configured (established 65536 bind 65536)
10477 06:52:26.387643 <6>[ 0.731151] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10478 06:52:26.397814 <6>[ 0.738347] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10479 06:52:26.404786 <6>[ 0.746047] NET: Registered PF_UNIX/PF_LOCAL protocol family
10480 06:52:26.410818 <6>[ 0.752196] RPC: Registered named UNIX socket transport module.
10481 06:52:26.413930 <6>[ 0.758348] RPC: Registered udp transport module.
10482 06:52:26.420339 <6>[ 0.763282] RPC: Registered tcp transport module.
10483 06:52:26.427104 <6>[ 0.768212] RPC: Registered tcp NFSv4.1 backchannel transport module.
10484 06:52:26.430140 <6>[ 0.774876] PCI: CLS 0 bytes, default 64
10485 06:52:26.433520 <6>[ 0.779208] Unpacking initramfs...
10486 06:52:26.457882 <6>[ 0.798821] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10487 06:52:26.467690 <6>[ 0.807461] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10488 06:52:26.470903 <6>[ 0.816312] kvm [1]: IPA Size Limit: 40 bits
10489 06:52:26.477947 <6>[ 0.820838] kvm [1]: GICv3: no GICV resource entry
10490 06:52:26.481172 <6>[ 0.825858] kvm [1]: disabling GICv2 emulation
10491 06:52:26.487547 <6>[ 0.830543] kvm [1]: GIC system register CPU interface enabled
10492 06:52:26.490696 <6>[ 0.836707] kvm [1]: vgic interrupt IRQ18
10493 06:52:26.497424 <6>[ 0.841064] kvm [1]: VHE mode initialized successfully
10494 06:52:26.504070 <5>[ 0.847559] Initialise system trusted keyrings
10495 06:52:26.510958 <6>[ 0.852387] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10496 06:52:26.517850 <6>[ 0.862387] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10497 06:52:26.524609 <5>[ 0.868768] NFS: Registering the id_resolver key type
10498 06:52:26.528245 <5>[ 0.874065] Key type id_resolver registered
10499 06:52:26.535433 <5>[ 0.878480] Key type id_legacy registered
10500 06:52:26.541168 <6>[ 0.882758] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10501 06:52:26.547805 <6>[ 0.889676] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10502 06:52:26.554715 <6>[ 0.897386] 9p: Installing v9fs 9p2000 file system support
10503 06:52:26.590857 <5>[ 0.934390] Key type asymmetric registered
10504 06:52:26.593726 <5>[ 0.938723] Asymmetric key parser 'x509' registered
10505 06:52:26.603643 <6>[ 0.943865] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10506 06:52:26.607212 <6>[ 0.951483] io scheduler mq-deadline registered
10507 06:52:26.609839 <6>[ 0.956262] io scheduler kyber registered
10508 06:52:26.629261 <6>[ 0.973356] EINJ: ACPI disabled.
10509 06:52:26.661798 <4>[ 0.998829] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10510 06:52:26.671749 <4>[ 1.009451] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10511 06:52:26.686660 <6>[ 1.030292] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10512 06:52:26.694877 <6>[ 1.038343] printk: console [ttyS0] disabled
10513 06:52:26.722594 <6>[ 1.062969] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10514 06:52:26.729083 <6>[ 1.072446] printk: console [ttyS0] enabled
10515 06:52:26.732762 <6>[ 1.072446] printk: console [ttyS0] enabled
10516 06:52:26.739087 <6>[ 1.081339] printk: bootconsole [mtk8250] disabled
10517 06:52:26.742897 <6>[ 1.081339] printk: bootconsole [mtk8250] disabled
10518 06:52:26.749118 <6>[ 1.092562] SuperH (H)SCI(F) driver initialized
10519 06:52:26.752349 <6>[ 1.097852] msm_serial: driver initialized
10520 06:52:26.767082 <6>[ 1.106807] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10521 06:52:26.776109 <6>[ 1.115352] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10522 06:52:26.783044 <6>[ 1.123895] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10523 06:52:26.793608 <6>[ 1.132524] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10524 06:52:26.803095 <6>[ 1.141230] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10525 06:52:26.809168 <6>[ 1.149950] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10526 06:52:26.819958 <6>[ 1.158490] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10527 06:52:26.826053 <6>[ 1.167293] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10528 06:52:26.835914 <6>[ 1.175837] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10529 06:52:26.847335 <6>[ 1.191363] loop: module loaded
10530 06:52:26.854315 <6>[ 1.197413] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10531 06:52:26.876722 <4>[ 1.220875] mtk-pmic-keys: Failed to locate of_node [id: -1]
10532 06:52:26.884158 <6>[ 1.227942] megasas: 07.719.03.00-rc1
10533 06:52:26.894021 <6>[ 1.237752] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10534 06:52:26.902168 <6>[ 1.246072] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10535 06:52:26.919192 <6>[ 1.262835] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10536 06:52:26.975522 <6>[ 1.312723] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10537 06:52:27.185072 <6>[ 1.528564] Freeing initrd memory: 17380K
10538 06:52:27.195178 <6>[ 1.538972] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10539 06:52:27.206330 <6>[ 1.550050] tun: Universal TUN/TAP device driver, 1.6
10540 06:52:27.209809 <6>[ 1.556129] thunder_xcv, ver 1.0
10541 06:52:27.212859 <6>[ 1.559641] thunder_bgx, ver 1.0
10542 06:52:27.216162 <6>[ 1.563134] nicpf, ver 1.0
10543 06:52:27.226580 <6>[ 1.567162] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10544 06:52:27.230228 <6>[ 1.574638] hns3: Copyright (c) 2017 Huawei Corporation.
10545 06:52:27.236635 <6>[ 1.580224] hclge is initializing
10546 06:52:27.239938 <6>[ 1.583805] e1000: Intel(R) PRO/1000 Network Driver
10547 06:52:27.246453 <6>[ 1.588935] e1000: Copyright (c) 1999-2006 Intel Corporation.
10548 06:52:27.250120 <6>[ 1.594946] e1000e: Intel(R) PRO/1000 Network Driver
10549 06:52:27.256346 <6>[ 1.600162] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10550 06:52:27.262862 <6>[ 1.606346] igb: Intel(R) Gigabit Ethernet Network Driver
10551 06:52:27.269525 <6>[ 1.611995] igb: Copyright (c) 2007-2014 Intel Corporation.
10552 06:52:27.276371 <6>[ 1.617835] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10553 06:52:27.283424 <6>[ 1.624353] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10554 06:52:27.285882 <6>[ 1.630819] sky2: driver version 1.30
10555 06:52:27.292767 <6>[ 1.635814] VFIO - User Level meta-driver version: 0.3
10556 06:52:27.300405 <6>[ 1.644045] usbcore: registered new interface driver usb-storage
10557 06:52:27.306844 <6>[ 1.650495] usbcore: registered new device driver onboard-usb-hub
10558 06:52:27.316194 <6>[ 1.659687] mt6397-rtc mt6359-rtc: registered as rtc0
10559 06:52:27.326186 <6>[ 1.665160] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:52:31 UTC (1706943151)
10560 06:52:27.329143 <6>[ 1.674773] i2c_dev: i2c /dev entries driver
10561 06:52:27.345954 <6>[ 1.686422] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10562 06:52:27.366755 <6>[ 1.710432] cpu cpu0: EM: created perf domain
10563 06:52:27.370575 <6>[ 1.715358] cpu cpu4: EM: created perf domain
10564 06:52:27.377258 <6>[ 1.720924] sdhci: Secure Digital Host Controller Interface driver
10565 06:52:27.383868 <6>[ 1.727357] sdhci: Copyright(c) Pierre Ossman
10566 06:52:27.390921 <6>[ 1.732310] Synopsys Designware Multimedia Card Interface Driver
10567 06:52:27.397507 <6>[ 1.738948] sdhci-pltfm: SDHCI platform and OF driver helper
10568 06:52:27.400325 <6>[ 1.739016] mmc0: CQHCI version 5.10
10569 06:52:27.407587 <6>[ 1.749053] ledtrig-cpu: registered to indicate activity on CPUs
10570 06:52:27.413651 <6>[ 1.756022] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10571 06:52:27.420344 <6>[ 1.763094] usbcore: registered new interface driver usbhid
10572 06:52:27.423317 <6>[ 1.768916] usbhid: USB HID core driver
10573 06:52:27.430201 <6>[ 1.773131] spi_master spi0: will run message pump with realtime priority
10574 06:52:27.474904 <6>[ 1.811900] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10575 06:52:27.493353 <6>[ 1.827130] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10576 06:52:27.501047 <6>[ 1.841930] cros-ec-spi spi0.0: Chrome EC device registered
10577 06:52:27.503844 <6>[ 1.847935] mmc0: Command Queue Engine enabled
10578 06:52:27.511094 <6>[ 1.852679] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10579 06:52:27.517420 <6>[ 1.860347] mmcblk0: mmc0:0001 DA4128 116 GiB
10580 06:52:27.524591 <6>[ 1.860794] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10581 06:52:27.530775 <6>[ 1.868952] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10582 06:52:27.537500 <6>[ 1.875539] NET: Registered PF_PACKET protocol family
10583 06:52:27.540421 <6>[ 1.881790] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10584 06:52:27.547164 <6>[ 1.885693] 9pnet: Installing 9P2000 support
10585 06:52:27.550519 <6>[ 1.891543] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10586 06:52:27.557169 <5>[ 1.895373] Key type dns_resolver registered
10587 06:52:27.563639 <6>[ 1.901281] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10588 06:52:27.567077 <6>[ 1.905555] registered taskstats version 1
10589 06:52:27.573208 <5>[ 1.916025] Loading compiled-in X.509 certificates
10590 06:52:27.600230 <4>[ 1.937371] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 06:52:27.610572 <4>[ 1.948113] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 06:52:27.617372 <3>[ 1.958653] debugfs: File 'uA_load' in directory '/' already present!
10593 06:52:27.623605 <3>[ 1.965369] debugfs: File 'min_uV' in directory '/' already present!
10594 06:52:27.630153 <3>[ 1.972037] debugfs: File 'max_uV' in directory '/' already present!
10595 06:52:27.637074 <3>[ 1.978652] debugfs: File 'constraint_flags' in directory '/' already present!
10596 06:52:27.647761 <3>[ 1.988109] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10597 06:52:27.658084 <6>[ 2.001975] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10598 06:52:27.665302 <6>[ 2.008786] xhci-mtk 11200000.usb: xHCI Host Controller
10599 06:52:27.671729 <6>[ 2.014284] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10600 06:52:27.681229 <6>[ 2.022171] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10601 06:52:27.688680 <6>[ 2.031622] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10602 06:52:27.694879 <6>[ 2.037691] xhci-mtk 11200000.usb: xHCI Host Controller
10603 06:52:27.701311 <6>[ 2.043167] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10604 06:52:27.708339 <6>[ 2.050819] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10605 06:52:27.714862 <6>[ 2.058647] hub 1-0:1.0: USB hub found
10606 06:52:27.718089 <6>[ 2.062673] hub 1-0:1.0: 1 port detected
10607 06:52:27.728212 <6>[ 2.066995] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10608 06:52:27.731664 <6>[ 2.075783] hub 2-0:1.0: USB hub found
10609 06:52:27.734785 <6>[ 2.079810] hub 2-0:1.0: 1 port detected
10610 06:52:27.744014 <6>[ 2.087690] mtk-msdc 11f70000.mmc: Got CD GPIO
10611 06:52:27.754400 <6>[ 2.094630] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10612 06:52:27.760998 <6>[ 2.102657] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10613 06:52:27.771133 <4>[ 2.110569] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10614 06:52:27.780552 <6>[ 2.120093] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10615 06:52:27.787011 <6>[ 2.128170] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10616 06:52:27.794055 <6>[ 2.136266] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10617 06:52:27.803492 <6>[ 2.144194] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10618 06:52:27.810096 <6>[ 2.152016] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10619 06:52:27.819760 <6>[ 2.159833] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10620 06:52:27.830530 <6>[ 2.170278] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10621 06:52:27.836722 <6>[ 2.178650] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10622 06:52:27.846783 <6>[ 2.186992] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10623 06:52:27.856746 <6>[ 2.195332] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10624 06:52:27.862952 <6>[ 2.203671] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10625 06:52:27.873153 <6>[ 2.212013] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10626 06:52:27.879813 <6>[ 2.220352] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10627 06:52:27.890260 <6>[ 2.228692] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10628 06:52:27.896181 <6>[ 2.237032] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10629 06:52:27.906168 <6>[ 2.245371] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10630 06:52:27.912911 <6>[ 2.253712] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10631 06:52:27.922969 <6>[ 2.262052] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10632 06:52:27.929396 <6>[ 2.270390] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10633 06:52:27.939734 <6>[ 2.278728] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10634 06:52:27.946172 <6>[ 2.287066] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10635 06:52:27.952839 <6>[ 2.295945] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10636 06:52:27.959081 <6>[ 2.303271] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10637 06:52:27.966519 <6>[ 2.310217] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10638 06:52:27.976588 <6>[ 2.317124] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10639 06:52:27.982809 <6>[ 2.324188] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10640 06:52:27.989913 <6>[ 2.330980] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10641 06:52:27.999233 <6>[ 2.340106] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10642 06:52:28.009705 <6>[ 2.349225] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10643 06:52:28.019849 <6>[ 2.358517] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10644 06:52:28.029631 <6>[ 2.367984] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10645 06:52:28.039086 <6>[ 2.377450] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10646 06:52:28.045898 <6>[ 2.386569] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10647 06:52:28.055313 <6>[ 2.396050] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10648 06:52:28.065569 <6>[ 2.405170] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10649 06:52:28.075326 <6>[ 2.414464] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10650 06:52:28.085046 <6>[ 2.424625] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10651 06:52:28.096549 <6>[ 2.436153] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10652 06:52:28.102042 <6>[ 2.445868] Trying to probe devices needed for running init ...
10653 06:52:28.126950 <6>[ 2.467037] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10654 06:52:28.154487 <6>[ 2.498396] hub 2-1:1.0: USB hub found
10655 06:52:28.158183 <6>[ 2.502937] hub 2-1:1.0: 3 ports detected
10656 06:52:28.167184 <6>[ 2.510370] hub 2-1:1.0: USB hub found
10657 06:52:28.169363 <6>[ 2.514798] hub 2-1:1.0: 3 ports detected
10658 06:52:28.278545 <6>[ 2.618968] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10659 06:52:28.433166 <6>[ 2.777091] hub 1-1:1.0: USB hub found
10660 06:52:28.436698 <6>[ 2.781580] hub 1-1:1.0: 4 ports detected
10661 06:52:28.446212 <6>[ 2.790006] hub 1-1:1.0: USB hub found
10662 06:52:28.449406 <6>[ 2.794348] hub 1-1:1.0: 4 ports detected
10663 06:52:28.510639 <6>[ 2.851082] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10664 06:52:28.769959 <6>[ 3.111010] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10665 06:52:28.902932 <6>[ 3.246849] hub 1-1.4:1.0: USB hub found
10666 06:52:28.906174 <6>[ 3.251513] hub 1-1.4:1.0: 2 ports detected
10667 06:52:28.916214 <6>[ 3.260275] hub 1-1.4:1.0: USB hub found
10668 06:52:28.919523 <6>[ 3.264880] hub 1-1.4:1.0: 2 ports detected
10669 06:52:29.219075 <6>[ 3.558987] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10670 06:52:29.410065 <6>[ 3.750985] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10671 06:52:40.386828 <6>[ 14.735999] ALSA device list:
10672 06:52:40.393563 <6>[ 14.739295] No soundcards found.
10673 06:52:40.401477 <6>[ 14.747251] Freeing unused kernel memory: 8448K
10674 06:52:40.404463 <6>[ 14.752237] Run /init as init process
10675 06:52:40.415883 Loading, please wait...
10676 06:52:40.437023 Starting version 247.3-7+deb11u2
10677 06:52:40.668253 <6>[ 15.010927] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10678 06:52:40.688712 <6>[ 15.034176] remoteproc remoteproc0: scp is available
10679 06:52:40.698381 <6>[ 15.040866] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10680 06:52:40.701560 <6>[ 15.045123] remoteproc remoteproc0: powering up scp
10681 06:52:40.711277 <6>[ 15.049278] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10682 06:52:40.722046 <6>[ 15.053610] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10683 06:52:40.724777 <6>[ 15.053630] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10684 06:52:40.734822 <6>[ 15.076503] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10685 06:52:40.752006 <3>[ 15.094436] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 06:52:40.758263 <3>[ 15.102581] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 06:52:40.768737 <3>[ 15.110674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 06:52:40.775355 <6>[ 15.115820] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10689 06:52:40.785014 <3>[ 15.119697] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 06:52:40.791637 <6>[ 15.127147] usbcore: registered new device driver r8152-cfgselector
10691 06:52:40.798043 <4>[ 15.127617] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10692 06:52:40.804923 <4>[ 15.131727] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10693 06:52:40.811358 <6>[ 15.132302] mc: Linux media interface: v0.10
10694 06:52:40.818044 <3>[ 15.134869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 06:52:40.824532 <6>[ 15.156277] videodev: Linux video capture interface: v2.00
10696 06:52:40.831173 <3>[ 15.160881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 06:52:40.840927 <4>[ 15.169256] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10698 06:52:40.844629 <4>[ 15.169256] Fallback method does not support PEC.
10699 06:52:40.854271 <3>[ 15.175298] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 06:52:40.861251 <6>[ 15.179887] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10701 06:52:40.868363 <6>[ 15.179901] remoteproc remoteproc0: remote processor scp is now up
10702 06:52:40.875279 <6>[ 15.179913] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10703 06:52:40.884921 <6>[ 15.184594] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10704 06:52:40.892578 <3>[ 15.196869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 06:52:40.902599 <3>[ 15.197018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 06:52:40.908623 <6>[ 15.209223] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10707 06:52:40.915781 <6>[ 15.210400] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10708 06:52:40.921880 <6>[ 15.210408] pci_bus 0000:00: root bus resource [bus 00-ff]
10709 06:52:40.928592 <6>[ 15.210419] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10710 06:52:40.938419 <6>[ 15.210423] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10711 06:52:40.944763 <6>[ 15.210463] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10712 06:52:40.951943 <6>[ 15.210480] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10713 06:52:40.958495 <6>[ 15.210545] pci 0000:00:00.0: supports D1 D2
10714 06:52:40.964859 <6>[ 15.210547] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10715 06:52:40.971406 <6>[ 15.211561] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10716 06:52:40.977801 <6>[ 15.211651] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10717 06:52:40.984698 <6>[ 15.211676] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10718 06:52:40.993986 <6>[ 15.211693] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10719 06:52:41.001112 <6>[ 15.211709] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10720 06:52:41.004602 <6>[ 15.211818] pci 0000:01:00.0: supports D1 D2
10721 06:52:41.011040 <6>[ 15.211820] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10722 06:52:41.020838 <3>[ 15.213578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 06:52:41.030732 <3>[ 15.216345] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10724 06:52:41.037161 <6>[ 15.222819] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10725 06:52:41.043667 <3>[ 15.227022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 06:52:41.053687 <3>[ 15.227026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 06:52:41.059971 <6>[ 15.235295] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10728 06:52:41.070683 <3>[ 15.238949] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10729 06:52:41.077061 <3>[ 15.243389] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 06:52:41.087039 <6>[ 15.243650] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10731 06:52:41.093141 <6>[ 15.251428] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10732 06:52:41.099730 <6>[ 15.251438] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10733 06:52:41.109862 <3>[ 15.259684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 06:52:41.119447 <6>[ 15.264396] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10735 06:52:41.129351 <6>[ 15.264789] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10736 06:52:41.136189 <6>[ 15.266554] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10737 06:52:41.146084 <4>[ 15.266941] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10738 06:52:41.152497 <4>[ 15.266950] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10739 06:52:41.162271 <3>[ 15.272278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 06:52:41.172889 <6>[ 15.274542] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10741 06:52:41.179639 <6>[ 15.279411] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10742 06:52:41.185852 <3>[ 15.289317] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 06:52:41.192421 <6>[ 15.295587] pci 0000:00:00.0: PCI bridge to [bus 01]
10744 06:52:41.198584 <6>[ 15.295597] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10745 06:52:41.205276 <6>[ 15.295944] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10746 06:52:41.215284 <3>[ 15.303202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 06:52:41.221669 <6>[ 15.308686] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10748 06:52:41.228599 <3>[ 15.314631] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 06:52:41.231651 <6>[ 15.315562] Bluetooth: Core ver 2.22
10750 06:52:41.238697 <6>[ 15.315664] NET: Registered PF_BLUETOOTH protocol family
10751 06:52:41.244788 <6>[ 15.315668] Bluetooth: HCI device and connection manager initialized
10752 06:52:41.251329 <6>[ 15.315689] Bluetooth: HCI socket layer initialized
10753 06:52:41.254886 <6>[ 15.315699] Bluetooth: L2CAP socket layer initialized
10754 06:52:41.261594 <6>[ 15.315720] Bluetooth: SCO socket layer initialized
10755 06:52:41.264585 <6>[ 15.323093] r8152 2-1.3:1.0 eth0: v1.12.13
10756 06:52:41.271266 <6>[ 15.323406] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10757 06:52:41.278184 <6>[ 15.324199] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10758 06:52:41.291629 <6>[ 15.325443] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10759 06:52:41.294849 <6>[ 15.325565] usbcore: registered new interface driver uvcvideo
10760 06:52:41.301437 <6>[ 15.346127] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10761 06:52:41.311173 <5>[ 15.346907] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10762 06:52:41.317946 <6>[ 15.351986] usbcore: registered new interface driver r8152
10763 06:52:41.320791 <6>[ 15.357149] usbcore: registered new interface driver btusb
10764 06:52:41.334141 <4>[ 15.357626] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10765 06:52:41.338360 <3>[ 15.357637] Bluetooth: hci0: Failed to load firmware file (-2)
10766 06:52:41.344255 <3>[ 15.357639] Bluetooth: hci0: Failed to set up firmware (-2)
10767 06:52:41.353943 <4>[ 15.357643] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10768 06:52:41.361178 <5>[ 15.360004] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10769 06:52:41.370165 <5>[ 15.360498] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10770 06:52:41.380402 <4>[ 15.360574] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10771 06:52:41.383542 <6>[ 15.360582] cfg80211: failed to load regulatory.db
10772 06:52:41.390286 <6>[ 15.380106] usbcore: registered new interface driver cdc_ether
10773 06:52:41.397253 <6>[ 15.455411] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10774 06:52:41.403578 <6>[ 15.470584] usbcore: registered new interface driver r8153_ecm
10775 06:52:41.409957 <6>[ 15.479530] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10776 06:52:41.416720 <6>[ 15.496880] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10777 06:52:41.419599 <6>[ 15.524976] mt7921e 0000:01:00.0: ASIC revision: 79610010
10778 06:52:41.524543 <6>[ 15.866480] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10779 06:52:41.527055 <6>[ 15.866480]
10780 06:52:41.534289 Begin: Loading essential drivers ... done.
10781 06:52:41.537434 Begin: Running /scripts/init-premount ... done.
10782 06:52:41.544527 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10783 06:52:41.553988 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10784 06:52:41.557185 Device /sys/class/net/enx002432307c7b found
10785 06:52:41.557267 done.
10786 06:52:41.616001 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10787 06:52:41.795627 <6>[ 16.138410] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10788 06:52:42.637791 <6>[ 16.983881] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10789 06:52:42.675450 <6>[ 17.021507] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10790 06:52:42.819835 IP-Config: no response after 2 secs - giving up
10791 06:52:42.851910 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10792 06:52:42.881156 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10793 06:52:43.602250 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10794 06:52:43.608654 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10795 06:52:43.615267 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10796 06:52:43.621958 host : mt8192-asurada-spherion-r0-cbg-2
10797 06:52:43.628559 domain : lava-rack
10798 06:52:43.634814 rootserver: 192.168.201.1 rootpath:
10799 06:52:43.634906 filename :
10800 06:52:43.706557 done.
10801 06:52:43.714282 Begin: Running /scripts/nfs-bottom ... done.
10802 06:52:43.733112 Begin: Running /scripts/init-bottom ... done.
10803 06:52:44.960667 <6>[ 19.306942] NET: Registered PF_INET6 protocol family
10804 06:52:44.968189 <6>[ 19.314639] Segment Routing with IPv6
10805 06:52:44.971399 <6>[ 19.318635] In-situ OAM (IOAM) with IPv6
10806 06:52:45.113921 <30>[ 19.440021] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10807 06:52:45.120134 <30>[ 19.464498] systemd[1]: Detected architecture arm64.
10808 06:52:45.139723
10809 06:52:45.142590 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10810 06:52:45.142674
10811 06:52:45.159205 <30>[ 19.505680] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10812 06:52:46.039894 <30>[ 20.383237] systemd[1]: Queued start job for default target Graphical Interface.
10813 06:52:46.062747 <30>[ 20.409375] systemd[1]: Created slice system-getty.slice.
10814 06:52:46.069281 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10815 06:52:46.085791 <30>[ 20.432356] systemd[1]: Created slice system-modprobe.slice.
10816 06:52:46.092929 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10817 06:52:46.109517 <30>[ 20.456222] systemd[1]: Created slice system-serial\x2dgetty.slice.
10818 06:52:46.120148 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10819 06:52:46.133835 <30>[ 20.480045] systemd[1]: Created slice User and Session Slice.
10820 06:52:46.140213 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10821 06:52:46.159986 <30>[ 20.503259] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10822 06:52:46.170084 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10823 06:52:46.188149 <30>[ 20.531184] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10824 06:52:46.194504 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10825 06:52:46.214978 <30>[ 20.555071] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10826 06:52:46.221995 <30>[ 20.567217] systemd[1]: Reached target Local Encrypted Volumes.
10827 06:52:46.228064 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10828 06:52:46.244764 <30>[ 20.591571] systemd[1]: Reached target Paths.
10829 06:52:46.251769 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10830 06:52:46.264533 <30>[ 20.610990] systemd[1]: Reached target Remote File Systems.
10831 06:52:46.271233 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10832 06:52:46.288743 <30>[ 20.635344] systemd[1]: Reached target Slices.
10833 06:52:46.296252 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10834 06:52:46.308957 <30>[ 20.655013] systemd[1]: Reached target Swap.
10835 06:52:46.312110 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10836 06:52:46.333204 <30>[ 20.675495] systemd[1]: Listening on initctl Compatibility Named Pipe.
10837 06:52:46.339075 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10838 06:52:46.346009 <30>[ 20.691803] systemd[1]: Listening on Journal Audit Socket.
10839 06:52:46.352269 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10840 06:52:46.370293 <30>[ 20.716420] systemd[1]: Listening on Journal Socket (/dev/log).
10841 06:52:46.376958 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10842 06:52:46.393314 <30>[ 20.739533] systemd[1]: Listening on Journal Socket.
10843 06:52:46.399883 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10844 06:52:46.417454 <30>[ 20.760541] systemd[1]: Listening on Network Service Netlink Socket.
10845 06:52:46.424403 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10846 06:52:46.440732 <30>[ 20.786170] systemd[1]: Listening on udev Control Socket.
10847 06:52:46.446697 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10848 06:52:46.461052 <30>[ 20.807426] systemd[1]: Listening on udev Kernel Socket.
10849 06:52:46.468347 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10850 06:52:46.509086 <30>[ 20.855385] systemd[1]: Mounting Huge Pages File System...
10851 06:52:46.516150 Mounting [0;1;39mHuge Pages File System[0m...
10852 06:52:46.532701 <30>[ 20.878967] systemd[1]: Mounting POSIX Message Queue File System...
10853 06:52:46.539472 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10854 06:52:46.559193 <30>[ 20.906123] systemd[1]: Mounting Kernel Debug File System...
10855 06:52:46.566393 Mounting [0;1;39mKernel Debug File System[0m...
10856 06:52:46.583836 <30>[ 20.927185] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10857 06:52:46.620419 <30>[ 20.963578] systemd[1]: Starting Create list of static device nodes for the current kernel...
10858 06:52:46.626722 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10859 06:52:46.648510 <30>[ 20.995191] systemd[1]: Starting Load Kernel Module configfs...
10860 06:52:46.654982 Starting [0;1;39mLoad Kernel Module configfs[0m...
10861 06:52:46.673340 <30>[ 21.019627] systemd[1]: Starting Load Kernel Module drm...
10862 06:52:46.679647 Starting [0;1;39mLoad Kernel Module drm[0m...
10863 06:52:46.698042 <30>[ 21.043828] systemd[1]: Starting Load Kernel Module fuse...
10864 06:52:46.703748 Starting [0;1;39mLoad Kernel Module fuse[0m...
10865 06:52:46.734551 <30>[ 21.077978] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10866 06:52:46.741190 <6>[ 21.088163] fuse: init (API version 7.37)
10867 06:52:46.769359 <30>[ 21.115961] systemd[1]: Starting Journal Service...
10868 06:52:46.775577 Starting [0;1;39mJournal Service[0m...
10869 06:52:46.799917 <30>[ 21.146476] systemd[1]: Starting Load Kernel Modules...
10870 06:52:46.806292 Starting [0;1;39mLoad Kernel Modules[0m...
10871 06:52:46.829266 <30>[ 21.172037] systemd[1]: Starting Remount Root and Kernel File Systems...
10872 06:52:46.835840 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10873 06:52:46.854518 <30>[ 21.200866] systemd[1]: Starting Coldplug All udev Devices...
10874 06:52:46.860646 Starting [0;1;39mColdplug All udev Devices[0m...
10875 06:52:46.883283 <30>[ 21.230198] systemd[1]: Mounted Huge Pages File System.
10876 06:52:46.890138 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10877 06:52:46.905850 <30>[ 21.251859] systemd[1]: Mounted POSIX Message Queue File System.
10878 06:52:46.915985 <3>[ 21.255434] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 06:52:46.922505 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10880 06:52:46.937526 <30>[ 21.283266] systemd[1]: Mounted Kernel Debug File System.
10881 06:52:46.947227 [[0;32m OK [<3>[ 21.289528] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 06:52:46.950484 0m] Mounted [0;1;39mKernel Debug File System[0m.
10883 06:52:46.973227 <30>[ 21.315743] systemd[1]: Finished Create list of static device nodes for the current kernel.
10884 06:52:46.982609 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10885 06:52:46.989054 <3>[ 21.333005] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 06:52:46.997261 <30>[ 21.344128] systemd[1]: modprobe@configfs.service: Succeeded.
10887 06:52:47.005496 <30>[ 21.350854] systemd[1]: Finished Load Kernel Module configfs.
10888 06:52:47.021456 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configf<3>[ 21.362108] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 06:52:47.021543 s[0m.
10890 06:52:47.038542 <30>[ 21.384970] systemd[1]: modprobe@drm.service: Succeeded.
10891 06:52:47.045592 <30>[ 21.392249] systemd[1]: Finished Load Kernel Module drm.
10892 06:52:47.061925 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m<3>[ 21.402382] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 06:52:47.062009 .
10894 06:52:47.077747 <30>[ 21.424082] systemd[1]: modprobe@fuse.service: Succeeded.
10895 06:52:47.084772 <30>[ 21.430443] systemd[1]: Finished Load Kernel Module fuse.
10896 06:52:47.098319 [[0;32m OK [0m] Finished [0<3>[ 21.437752] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 06:52:47.098403 ;1;39mLoad Kernel Module fuse[0m.
10898 06:52:47.118256 <30>[ 21.464286] systemd[1]: Finished Load Kernel Modules.
10899 06:52:47.127963 [[0;32m OK [<3>[ 21.470943] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 06:52:47.131292 0m] Finished [0;1;39mLoad Kernel Modules[0m.
10901 06:52:47.154615 <30>[ 21.499765] systemd[1]: Finished Remount Root and Kernel File Systems.
10902 06:52:47.163958 <3>[ 21.505303] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 06:52:47.170565 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10904 06:52:47.194975 <3>[ 21.537989] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 06:52:47.226823 <3>[ 21.570090] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 06:52:47.237660 <30>[ 21.583681] systemd[1]: Mounting FUSE Control File System...
10907 06:52:47.244123 Mounting [0;1;39mFUSE Control File System[0m...
10908 06:52:47.262135 <30>[ 21.605667] systemd[1]: Mounting Kernel Configuration File System...
10909 06:52:47.265732 Mounting [0;1;39mKernel Configuration File System[0m...
10910 06:52:47.288273 <30>[ 21.631764] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10911 06:52:47.298135 <30>[ 21.640972] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10912 06:52:47.329379 <30>[ 21.676369] systemd[1]: Starting Load/Save Random Seed...
10913 06:52:47.336197 Starting [0;1;39mLoad/Save Random Seed[0m...
10914 06:52:47.353002 <30>[ 21.699036] systemd[1]: Starting Apply Kernel Variables...
10915 06:52:47.359733 Starting [0;1;39mApply Kernel Variables[0m...
10916 06:52:47.377305 <30>[ 21.723974] systemd[1]: Starting Create System Users...
10917 06:52:47.384194 Starting [0;1;39mCreate System Users[0m...
10918 06:52:47.398721 <30>[ 21.745024] systemd[1]: Started Journal Service.
10919 06:52:47.414965 <4>[ 21.747808] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10920 06:52:47.421665 <3>[ 21.765679] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10921 06:52:47.428579 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10922 06:52:47.446705 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10923 06:52:47.460109 See 'systemctl status systemd-udev-trigger.service' for details.
10924 06:52:47.476979 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10925 06:52:47.492892 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10926 06:52:47.509897 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10927 06:52:47.526732 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10928 06:52:47.546150 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10929 06:52:47.589399 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10930 06:52:47.610667 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10931 06:52:47.646018 <46>[ 21.989716] systemd-journald[298]: Received client request to flush runtime journal.
10932 06:52:48.746306 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10933 06:52:48.765697 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10934 06:52:48.779942 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10935 06:52:48.816861 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10936 06:52:49.061563 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10937 06:52:49.117126 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10938 06:52:49.204142 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10939 06:52:49.281724 Starting [0;1;39mNetwork Service[0m...
10940 06:52:49.465767 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10941 06:52:49.702043 Starting [0;1;39mNetwork Time Synchronization[0m...
10942 06:52:49.769230 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10943 06:52:49.911395 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10944 06:52:50.018249 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10945 06:52:50.044840 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10946 06:52:50.110357 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10947 06:52:50.124104 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10948 06:52:50.143608 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10949 06:52:50.172304 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10950 06:52:50.203266 Starting [0;1;39mNetwork Name Resolution[0m...
10951 06:52:50.217951 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10952 06:52:50.226349 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10953 06:52:50.248779 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10954 06:52:50.280978 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10955 06:52:50.301799 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10956 06:52:50.317191 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10957 06:52:51.024502 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10958 06:52:51.368768 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10959 06:52:51.389631 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10960 06:52:51.410518 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10961 06:52:51.427444 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10962 06:52:51.439468 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10963 06:52:51.470370 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10964 06:52:51.484003 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10965 06:52:51.499681 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10966 06:52:51.537125 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10967 06:52:51.692942 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10968 06:52:51.842692 Starting [0;1;39mUser Login Management[0m...
10969 06:52:51.856998 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10970 06:52:52.104193 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10971 06:52:52.126903 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10972 06:52:52.146894 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10973 06:52:52.200437 Starting [0;1;39mPermit User Sessions[0m...
10974 06:52:52.215498 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10975 06:52:52.238500 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10976 06:52:52.258667 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10977 06:52:52.275576 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10978 06:52:52.304781 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10979 06:52:52.323508 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10980 06:52:52.338052 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10981 06:52:52.361095 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10982 06:52:52.428205 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10983 06:52:52.470573 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10984 06:52:52.534402
10985 06:52:52.534510
10986 06:52:52.537702 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10987 06:52:52.537786
10988 06:52:52.541459 debian-bullseye-arm64 login: root (automatic login)
10989 06:52:52.541544
10990 06:52:52.541608
10991 06:52:52.903714 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
10992 06:52:52.910910
10993 06:52:52.917572 The programs included with the Debian GNU/Linux system are free software;
10994 06:52:52.920569 the exact distribution terms for each program are described in the
10995 06:52:52.927097 individual files in /usr/share/doc/*/copyright.
10996 06:52:52.927179
10997 06:52:52.930333 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10998 06:52:52.933528 permitted by applicable law.
10999 06:52:53.975127 Matched prompt #10: / #
11001 06:52:53.975448 Setting prompt string to ['/ #']
11002 06:52:53.975543 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11004 06:52:53.975734 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11005 06:52:53.975824 start: 2.2.6 expect-shell-connection (timeout 00:03:11) [common]
11006 06:52:53.975893 Setting prompt string to ['/ #']
11007 06:52:53.975952 Forcing a shell prompt, looking for ['/ #']
11009 06:52:54.026225 / #
11010 06:52:54.026326 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11011 06:52:54.026403 Waiting using forced prompt support (timeout 00:02:30)
11012 06:52:54.031173
11013 06:52:54.031434 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11014 06:52:54.031529 start: 2.2.7 export-device-env (timeout 00:03:11) [common]
11016 06:52:54.131869 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694815/extract-nfsrootfs-vip9dcsz'
11017 06:52:54.137213 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694815/extract-nfsrootfs-vip9dcsz'
11019 06:52:54.237829 / # export NFS_SERVER_IP='192.168.201.1'
11020 06:52:54.243174 export NFS_SERVER_IP='192.168.201.1'
11021 06:52:54.243479 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11022 06:52:54.243581 end: 2.2 depthcharge-retry (duration 00:01:49) [common]
11023 06:52:54.243671 end: 2 depthcharge-action (duration 00:01:49) [common]
11024 06:52:54.243760 start: 3 lava-test-retry (timeout 00:07:30) [common]
11025 06:52:54.243851 start: 3.1 lava-test-shell (timeout 00:07:30) [common]
11026 06:52:54.243926 Using namespace: common
11028 06:52:54.344232 / # #
11029 06:52:54.344353 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11030 06:52:54.349182 #
11031 06:52:54.349449 Using /lava-12694815
11033 06:52:54.449714 / # export SHELL=/bin/bash
11034 06:52:54.454976 export SHELL=/bin/bash
11036 06:52:54.555464 / # . /lava-12694815/environment
11037 06:52:54.560972 . /lava-12694815/environment
11039 06:52:54.667324 / # /lava-12694815/bin/lava-test-runner /lava-12694815/0
11040 06:52:54.667454 Test shell timeout: 10s (minimum of the action and connection timeout)
11041 06:52:54.672162 /lava-12694815/bin/lava-test-runner /lava-12694815/0
11042 06:52:54.974387 + export TESTRUN_ID=0_timesync-off
11043 06:52:54.978243 + TESTRUN_ID=0_timesync-off
11044 06:52:54.980680 + cd /lava-12694815/0/tests/0_timesync-off
11045 06:52:54.983955 ++ cat uuid
11046 06:52:54.990468 + UUID=12694815_1.6.2.3.1
11047 06:52:54.990550 + set +x
11048 06:52:54.997103 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12694815_1.6.2.3.1>
11049 06:52:54.997360 Received signal: <STARTRUN> 0_timesync-off 12694815_1.6.2.3.1
11050 06:52:54.997437 Starting test lava.0_timesync-off (12694815_1.6.2.3.1)
11051 06:52:54.997527 Skipping test definition patterns.
11052 06:52:55.000443 + systemctl stop systemd-timesyncd
11053 06:52:55.063145 + set +x
11054 06:52:55.065921 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12694815_1.6.2.3.1>
11055 06:52:55.066180 Received signal: <ENDRUN> 0_timesync-off 12694815_1.6.2.3.1
11056 06:52:55.066264 Ending use of test pattern.
11057 06:52:55.066325 Ending test lava.0_timesync-off (12694815_1.6.2.3.1), duration 0.07
11059 06:52:55.151577 + export TESTRUN_ID=1_kselftest-rtc
11060 06:52:55.155261 + TESTRUN_ID=1_kselftest-rtc
11061 06:52:55.158209 + cd /lava-12694815/0/tests/1_kselftest-rtc
11062 06:52:55.161811 ++ cat uuid
11063 06:52:55.168019 + UUID=12694815_1.6.2.3.5
11064 06:52:55.168102 + set +x
11065 06:52:55.175056 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12694815_1.6.2.3.5>
11066 06:52:55.175312 Received signal: <STARTRUN> 1_kselftest-rtc 12694815_1.6.2.3.5
11067 06:52:55.175392 Starting test lava.1_kselftest-rtc (12694815_1.6.2.3.5)
11068 06:52:55.175472 Skipping test definition patterns.
11069 06:52:55.178535 + cd ./automated/linux/kselftest/
11070 06:52:55.200739 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11071 06:52:55.247036 INFO: install_deps skipped
11072 06:52:55.373564 --2024-02-03 06:52:55-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11073 06:52:55.383399 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11074 06:52:55.517048 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11075 06:52:55.650288 HTTP request sent, awaiting response... 200 OK
11076 06:52:55.653735 Length: 2965368 (2.8M) [application/octet-stream]
11077 06:52:55.656693 Saving to: 'kselftest.tar.xz'
11078 06:52:55.656776
11079 06:52:55.656842
11080 06:52:55.916341 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11081 06:52:56.184543 kselftest.tar.xz 1%[ ] 47.81K 180KB/s
11082 06:52:56.584695 kselftest.tar.xz 7%[> ] 217.50K 408KB/s
11083 06:52:56.857259 kselftest.tar.xz 29%[====> ] 862.31K 924KB/s
11084 06:52:56.984823 kselftest.tar.xz 68%[============> ] 1.93M 1.60MB/s
11085 06:52:56.991266 kselftest.tar.xz 100%[===================>] 2.83M 2.12MB/s in 1.3s
11086 06:52:56.991358
11087 06:52:57.248584 2024-02-03 06:52:57 (2.12 MB/s) - 'kselftest.tar.xz' saved [2965368/2965368]
11088 06:52:57.248725
11089 06:53:03.340575 skiplist:
11090 06:53:03.343982 ========================================
11091 06:53:03.347913 ========================================
11092 06:53:03.397902 rtc:rtctest
11093 06:53:03.419688 ============== Tests to run ===============
11094 06:53:03.419782 rtc:rtctest
11095 06:53:03.426377 ===========End Tests to run ===============
11096 06:53:03.430003 shardfile-rtc pass
11097 06:53:03.539598 <12>[ 37.888025] kselftest: Running tests in rtc
11098 06:53:03.550433 TAP version 13
11099 06:53:03.564575 1..1
11100 06:53:03.601592 # selftests: rtc: rtctest
11101 06:53:04.047787 # TAP version 13
11102 06:53:04.047927 # 1..8
11103 06:53:04.051290 # # Starting 8 tests from 2 test cases.
11104 06:53:04.054244 # # RUN rtc.date_read ...
11105 06:53:04.060856 # # rtctest.c:49:date_read:Current RTC date/time is 03/02/2024 06:53:03.
11106 06:53:04.063809 # # OK rtc.date_read
11107 06:53:04.067352 # ok 1 rtc.date_read
11108 06:53:04.070735 # # RUN rtc.date_read_loop ...
11109 06:53:04.081112 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11110 06:53:11.806695 <6>[ 46.158958] vpu: disabling
11111 06:53:11.809740 <6>[ 46.162060] vproc2: disabling
11112 06:53:11.813988 <6>[ 46.165968] vproc1: disabling
11113 06:53:11.818215 <6>[ 46.169990] vaud18: disabling
11114 06:53:11.824489 <6>[ 46.173728] vsram_others: disabling
11115 06:53:11.827829 <6>[ 46.177929] va09: disabling
11116 06:53:11.830926 <6>[ 46.181325] vsram_md: disabling
11117 06:53:11.834788 <6>[ 46.185114] Vgpu: disabling
11118 06:53:34.016252 # # rtctest.c:115:date_read_loop:Performed 2631 RTC time reads.
11119 06:53:34.019735 # # OK rtc.date_read_loop
11120 06:53:34.023309 # ok 2 rtc.date_read_loop
11121 06:53:34.026918 # # RUN rtc.uie_read ...
11122 06:53:36.994694 # # OK rtc.uie_read
11123 06:53:36.995249 # ok 3 rtc.uie_read
11124 06:53:36.997922 # # RUN rtc.uie_select ...
11125 06:53:39.991639 # # OK rtc.uie_select
11126 06:53:39.994672 # ok 4 rtc.uie_select
11127 06:53:39.998644 # # RUN rtc.alarm_alm_set ...
11128 06:53:40.004908 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 06:53:43.
11129 06:53:40.007840 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11130 06:53:40.014651 # # alarm_alm_set: Test terminated by assertion
11131 06:53:40.017950 # # FAIL rtc.alarm_alm_set
11132 06:53:40.021157 # not ok 5 rtc.alarm_alm_set
11133 06:53:40.024801 # # RUN rtc.alarm_wkalm_set ...
11134 06:53:40.031420 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 03/02/2024 06:53:43.
11135 06:53:42.993649 # # OK rtc.alarm_wkalm_set
11136 06:53:42.994205 # ok 6 rtc.alarm_wkalm_set
11137 06:53:43.000701 # # RUN rtc.alarm_alm_set_minute ...
11138 06:53:43.003888 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 06:54:00.
11139 06:53:43.010821 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11140 06:53:43.017042 # # alarm_alm_set_minute: Test terminated by assertion
11141 06:53:43.020789 # # FAIL rtc.alarm_alm_set_minute
11142 06:53:43.023530 # not ok 7 rtc.alarm_alm_set_minute
11143 06:53:43.027445 # # RUN rtc.alarm_wkalm_set_minute ...
11144 06:53:43.033442 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 03/02/2024 06:54:00.
11145 06:53:59.991718 # # OK rtc.alarm_wkalm_set_minute
11146 06:53:59.994964 # ok 8 rtc.alarm_wkalm_set_minute
11147 06:53:59.998421 # # FAILED: 6 / 8 tests passed.
11148 06:54:00.001519 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11149 06:54:00.005570 not ok 1 selftests: rtc: rtctest # exit=1
11150 06:54:00.675522 rtc_rtctest_rtc_date_read pass
11151 06:54:00.678619 rtc_rtctest_rtc_date_read_loop pass
11152 06:54:00.682102 rtc_rtctest_rtc_uie_read pass
11153 06:54:00.685605 rtc_rtctest_rtc_uie_select pass
11154 06:54:00.688969 rtc_rtctest_rtc_alarm_alm_set fail
11155 06:54:00.692021 rtc_rtctest_rtc_alarm_wkalm_set pass
11156 06:54:00.695091 rtc_rtctest_rtc_alarm_alm_set_minute fail
11157 06:54:00.698668 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11158 06:54:00.701806 rtc_rtctest fail
11159 06:54:00.708879 + ../../utils/send-to-lava.sh ./output/result.txt
11160 06:54:00.808727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11161 06:54:00.809533 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11163 06:54:00.877697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11164 06:54:00.878470 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11166 06:54:00.953527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11167 06:54:00.954344 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11169 06:54:01.024972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11170 06:54:01.025779 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11172 06:54:01.094956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11173 06:54:01.095349 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11175 06:54:01.165813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11176 06:54:01.166123 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11178 06:54:01.234978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11179 06:54:01.235669 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11181 06:54:01.313619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11182 06:54:01.314400 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11184 06:54:01.390211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11185 06:54:01.391017 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11187 06:54:01.463953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11188 06:54:01.464474 + set +x
11189 06:54:01.465080 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11191 06:54:01.471212 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12694815_1.6.2.3.5>
11192 06:54:01.471938 Received signal: <ENDRUN> 1_kselftest-rtc 12694815_1.6.2.3.5
11193 06:54:01.472313 Ending use of test pattern.
11194 06:54:01.472634 Ending test lava.1_kselftest-rtc (12694815_1.6.2.3.5), duration 66.30
11196 06:54:01.473730 ok: lava_test_shell seems to have completed
11197 06:54:01.474407 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11198 06:54:01.474848 end: 3.1 lava-test-shell (duration 00:01:07) [common]
11199 06:54:01.475284 end: 3 lava-test-retry (duration 00:01:07) [common]
11200 06:54:01.475774 start: 4 finalize (timeout 00:06:22) [common]
11201 06:54:01.476228 start: 4.1 power-off (timeout 00:00:30) [common]
11202 06:54:01.476984 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11203 06:54:01.596184 >> Command sent successfully.
11204 06:54:01.600022 Returned 0 in 0 seconds
11205 06:54:01.700969 end: 4.1 power-off (duration 00:00:00) [common]
11207 06:54:01.702542 start: 4.2 read-feedback (timeout 00:06:22) [common]
11209 06:54:01.704881 Listened to connection for namespace 'common' for up to 1s
11210 06:54:02.703466 Finalising connection for namespace 'common'
11211 06:54:02.703637 Disconnecting from shell: Finalise
11212 06:54:02.703714 / #
11213 06:54:02.804330 end: 4.2 read-feedback (duration 00:00:01) [common]
11214 06:54:02.804976 end: 4 finalize (duration 00:00:01) [common]
11215 06:54:02.805720 Cleaning after the job
11216 06:54:02.806338 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/ramdisk
11217 06:54:02.820074 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/kernel
11218 06:54:02.855276 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/dtb
11219 06:54:02.855596 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/nfsrootfs
11220 06:54:02.948501 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694815/tftp-deploy-s18jvg7m/modules
11221 06:54:02.955909 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694815
11222 06:54:03.593221 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694815
11223 06:54:03.593406 Job finished correctly