Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 16
- Kernel Errors: 32
1 06:49:41.615233 lava-dispatcher, installed at version: 2023.10
2 06:49:41.615449 start: 0 validate
3 06:49:41.615581 Start time: 2024-02-03 06:49:41.615573+00:00 (UTC)
4 06:49:41.615697 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:49:41.615831 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 06:49:41.891079 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:49:41.891792 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:49:42.161500 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:49:42.162173 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:50:11.918774 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:50:11.918941 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 06:50:12.446934 validate duration: 30.83
14 06:50:12.447429 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:50:12.447552 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:50:12.447733 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:50:12.447911 Not decompressing ramdisk as can be used compressed.
18 06:50:12.448035 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 06:50:12.448142 saving as /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/ramdisk/rootfs.cpio.gz
20 06:50:12.448250 total size: 26246609 (25 MB)
21 06:50:16.148405 progress 0 % (0 MB)
22 06:50:16.158269 progress 5 % (1 MB)
23 06:50:16.165122 progress 10 % (2 MB)
24 06:50:16.171932 progress 15 % (3 MB)
25 06:50:16.178813 progress 20 % (5 MB)
26 06:50:16.185781 progress 25 % (6 MB)
27 06:50:16.192682 progress 30 % (7 MB)
28 06:50:16.199508 progress 35 % (8 MB)
29 06:50:16.206352 progress 40 % (10 MB)
30 06:50:16.213198 progress 45 % (11 MB)
31 06:50:16.220005 progress 50 % (12 MB)
32 06:50:16.226854 progress 55 % (13 MB)
33 06:50:16.233666 progress 60 % (15 MB)
34 06:50:16.240747 progress 65 % (16 MB)
35 06:50:16.247782 progress 70 % (17 MB)
36 06:50:16.254801 progress 75 % (18 MB)
37 06:50:16.261890 progress 80 % (20 MB)
38 06:50:16.268900 progress 85 % (21 MB)
39 06:50:16.275815 progress 90 % (22 MB)
40 06:50:16.282790 progress 95 % (23 MB)
41 06:50:16.289830 progress 100 % (25 MB)
42 06:50:16.290118 25 MB downloaded in 3.84 s (6.52 MB/s)
43 06:50:16.290317 end: 1.1.1 http-download (duration 00:00:04) [common]
45 06:50:16.290562 end: 1.1 download-retry (duration 00:00:04) [common]
46 06:50:16.290652 start: 1.2 download-retry (timeout 00:09:56) [common]
47 06:50:16.290759 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 06:50:16.290920 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 06:50:16.290990 saving as /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/kernel/Image
50 06:50:16.291050 total size: 51532288 (49 MB)
51 06:50:16.291112 No compression specified
52 06:50:16.292248 progress 0 % (0 MB)
53 06:50:16.306168 progress 5 % (2 MB)
54 06:50:16.319800 progress 10 % (4 MB)
55 06:50:16.333165 progress 15 % (7 MB)
56 06:50:16.346807 progress 20 % (9 MB)
57 06:50:16.360421 progress 25 % (12 MB)
58 06:50:16.374431 progress 30 % (14 MB)
59 06:50:16.388193 progress 35 % (17 MB)
60 06:50:16.401945 progress 40 % (19 MB)
61 06:50:16.415501 progress 45 % (22 MB)
62 06:50:16.429204 progress 50 % (24 MB)
63 06:50:16.442626 progress 55 % (27 MB)
64 06:50:16.456340 progress 60 % (29 MB)
65 06:50:16.469959 progress 65 % (31 MB)
66 06:50:16.483473 progress 70 % (34 MB)
67 06:50:16.497203 progress 75 % (36 MB)
68 06:50:16.510911 progress 80 % (39 MB)
69 06:50:16.524399 progress 85 % (41 MB)
70 06:50:16.538218 progress 90 % (44 MB)
71 06:50:16.551737 progress 95 % (46 MB)
72 06:50:16.565148 progress 100 % (49 MB)
73 06:50:16.565438 49 MB downloaded in 0.27 s (179.11 MB/s)
74 06:50:16.565629 end: 1.2.1 http-download (duration 00:00:00) [common]
76 06:50:16.565911 end: 1.2 download-retry (duration 00:00:00) [common]
77 06:50:16.566036 start: 1.3 download-retry (timeout 00:09:56) [common]
78 06:50:16.566155 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 06:50:16.566322 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 06:50:16.566396 saving as /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/dtb/mt8192-asurada-spherion-r0.dtb
81 06:50:16.566460 total size: 47278 (0 MB)
82 06:50:16.566522 No compression specified
83 06:50:16.567672 progress 69 % (0 MB)
84 06:50:16.568023 progress 100 % (0 MB)
85 06:50:16.568183 0 MB downloaded in 0.00 s (26.20 MB/s)
86 06:50:16.568325 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:50:16.568554 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:50:16.568671 start: 1.4 download-retry (timeout 00:09:56) [common]
90 06:50:16.568782 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 06:50:16.568954 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 06:50:16.569039 saving as /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/modules/modules.tar
93 06:50:16.569116 total size: 8624064 (8 MB)
94 06:50:16.569192 Using unxz to decompress xz
95 06:50:16.573728 progress 0 % (0 MB)
96 06:50:16.596452 progress 5 % (0 MB)
97 06:50:16.622089 progress 10 % (0 MB)
98 06:50:16.646968 progress 15 % (1 MB)
99 06:50:16.672371 progress 20 % (1 MB)
100 06:50:16.698448 progress 25 % (2 MB)
101 06:50:16.726166 progress 30 % (2 MB)
102 06:50:16.754576 progress 35 % (2 MB)
103 06:50:16.780006 progress 40 % (3 MB)
104 06:50:16.806537 progress 45 % (3 MB)
105 06:50:16.832675 progress 50 % (4 MB)
106 06:50:16.858893 progress 55 % (4 MB)
107 06:50:16.885710 progress 60 % (4 MB)
108 06:50:16.915234 progress 65 % (5 MB)
109 06:50:16.942038 progress 70 % (5 MB)
110 06:50:16.967302 progress 75 % (6 MB)
111 06:50:16.996774 progress 80 % (6 MB)
112 06:50:17.024948 progress 85 % (7 MB)
113 06:50:17.052813 progress 90 % (7 MB)
114 06:50:17.086003 progress 95 % (7 MB)
115 06:50:17.115752 progress 100 % (8 MB)
116 06:50:17.120896 8 MB downloaded in 0.55 s (14.91 MB/s)
117 06:50:17.121262 end: 1.4.1 http-download (duration 00:00:01) [common]
119 06:50:17.121684 end: 1.4 download-retry (duration 00:00:01) [common]
120 06:50:17.121822 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 06:50:17.121970 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 06:50:17.122104 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:50:17.122238 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 06:50:17.122556 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s
125 06:50:17.122767 makedir: /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin
126 06:50:17.122935 makedir: /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/tests
127 06:50:17.123092 makedir: /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/results
128 06:50:17.123262 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-add-keys
129 06:50:17.123482 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-add-sources
130 06:50:17.123683 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-background-process-start
131 06:50:17.123875 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-background-process-stop
132 06:50:17.124064 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-common-functions
133 06:50:17.124257 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-echo-ipv4
134 06:50:17.124464 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-install-packages
135 06:50:17.124657 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-installed-packages
136 06:50:17.124850 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-os-build
137 06:50:17.125043 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-probe-channel
138 06:50:17.125235 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-probe-ip
139 06:50:17.125430 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-target-ip
140 06:50:17.125619 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-target-mac
141 06:50:17.125808 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-target-storage
142 06:50:17.125999 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-test-case
143 06:50:17.126192 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-test-event
144 06:50:17.126380 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-test-feedback
145 06:50:17.126569 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-test-raise
146 06:50:17.126762 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-test-reference
147 06:50:17.126951 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-test-runner
148 06:50:17.127142 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-test-set
149 06:50:17.127335 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-test-shell
150 06:50:17.127533 Updating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-install-packages (oe)
151 06:50:17.127758 Updating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/bin/lava-installed-packages (oe)
152 06:50:17.127949 Creating /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/environment
153 06:50:17.128106 LAVA metadata
154 06:50:17.128222 - LAVA_JOB_ID=12694793
155 06:50:17.128335 - LAVA_DISPATCHER_IP=192.168.201.1
156 06:50:17.128491 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 06:50:17.128601 skipped lava-vland-overlay
158 06:50:17.128718 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 06:50:17.128848 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 06:50:17.128957 skipped lava-multinode-overlay
161 06:50:17.129077 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 06:50:17.129212 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 06:50:17.129336 Loading test definitions
164 06:50:17.129488 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 06:50:17.129617 Using /lava-12694793 at stage 0
166 06:50:17.130107 uuid=12694793_1.5.2.3.1 testdef=None
167 06:50:17.130239 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 06:50:17.130380 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 06:50:17.131150 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 06:50:17.131500 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 06:50:17.132446 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 06:50:17.132821 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 06:50:17.133730 runner path: /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12694793_1.5.2.3.1
176 06:50:17.133951 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 06:50:17.134298 Creating lava-test-runner.conf files
179 06:50:17.134397 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694793/lava-overlay-huwo6u4s/lava-12694793/0 for stage 0
180 06:50:17.134556 - 0_v4l2-compliance-mtk-vcodec-enc
181 06:50:17.134705 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 06:50:17.134850 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
183 06:50:17.144584 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 06:50:17.144723 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
185 06:50:17.144821 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 06:50:17.144913 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 06:50:17.145005 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
188 06:50:17.896156 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 06:50:17.896590 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
190 06:50:17.896740 extracting modules file /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694793/extract-overlay-ramdisk-aus95vv5/ramdisk
191 06:50:18.209865 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 06:50:18.210088 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
193 06:50:18.210198 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694793/compress-overlay-ab2o8epr/overlay-1.5.2.4.tar.gz to ramdisk
194 06:50:18.210272 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694793/compress-overlay-ab2o8epr/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694793/extract-overlay-ramdisk-aus95vv5/ramdisk
195 06:50:18.217391 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 06:50:18.217530 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
197 06:50:18.217628 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 06:50:18.217732 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
199 06:50:18.217812 Building ramdisk /var/lib/lava/dispatcher/tmp/12694793/extract-overlay-ramdisk-aus95vv5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694793/extract-overlay-ramdisk-aus95vv5/ramdisk
200 06:50:18.832329 >> 228459 blocks
201 06:50:22.943719 rename /var/lib/lava/dispatcher/tmp/12694793/extract-overlay-ramdisk-aus95vv5/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/ramdisk/ramdisk.cpio.gz
202 06:50:22.944195 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 06:50:22.944336 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 06:50:22.944448 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 06:50:22.944564 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/kernel/Image'
206 06:50:37.022116 Returned 0 in 14 seconds
207 06:50:37.122848 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/kernel/image.itb
208 06:50:37.865554 output: FIT description: Kernel Image image with one or more FDT blobs
209 06:50:37.865936 output: Created: Sat Feb 3 06:50:37 2024
210 06:50:37.866017 output: Image 0 (kernel-1)
211 06:50:37.866086 output: Description:
212 06:50:37.866154 output: Created: Sat Feb 3 06:50:37 2024
213 06:50:37.866221 output: Type: Kernel Image
214 06:50:37.866282 output: Compression: lzma compressed
215 06:50:37.866342 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
216 06:50:37.866400 output: Architecture: AArch64
217 06:50:37.866459 output: OS: Linux
218 06:50:37.866516 output: Load Address: 0x00000000
219 06:50:37.866575 output: Entry Point: 0x00000000
220 06:50:37.866630 output: Hash algo: crc32
221 06:50:37.866683 output: Hash value: 380e7c3c
222 06:50:37.866741 output: Image 1 (fdt-1)
223 06:50:37.866797 output: Description: mt8192-asurada-spherion-r0
224 06:50:37.866850 output: Created: Sat Feb 3 06:50:37 2024
225 06:50:37.866904 output: Type: Flat Device Tree
226 06:50:37.866957 output: Compression: uncompressed
227 06:50:37.867010 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 06:50:37.867064 output: Architecture: AArch64
229 06:50:37.867117 output: Hash algo: crc32
230 06:50:37.867171 output: Hash value: cc4352de
231 06:50:37.867224 output: Image 2 (ramdisk-1)
232 06:50:37.867276 output: Description: unavailable
233 06:50:37.867329 output: Created: Sat Feb 3 06:50:37 2024
234 06:50:37.867382 output: Type: RAMDisk Image
235 06:50:37.867435 output: Compression: Unknown Compression
236 06:50:37.867488 output: Data Size: 39359858 Bytes = 38437.36 KiB = 37.54 MiB
237 06:50:37.867542 output: Architecture: AArch64
238 06:50:37.867595 output: OS: Linux
239 06:50:37.867648 output: Load Address: unavailable
240 06:50:37.867701 output: Entry Point: unavailable
241 06:50:37.867753 output: Hash algo: crc32
242 06:50:37.867806 output: Hash value: dac31e1d
243 06:50:37.867858 output: Default Configuration: 'conf-1'
244 06:50:37.867912 output: Configuration 0 (conf-1)
245 06:50:37.867964 output: Description: mt8192-asurada-spherion-r0
246 06:50:37.868017 output: Kernel: kernel-1
247 06:50:37.868070 output: Init Ramdisk: ramdisk-1
248 06:50:37.868123 output: FDT: fdt-1
249 06:50:37.868176 output: Loadables: kernel-1
250 06:50:37.868228 output:
251 06:50:37.868486 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 06:50:37.868588 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 06:50:37.868695 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 06:50:37.868791 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 06:50:37.868866 No LXC device requested
256 06:50:37.868947 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 06:50:37.869031 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 06:50:37.869110 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 06:50:37.869180 Checking files for TFTP limit of 4294967296 bytes.
260 06:50:37.869688 end: 1 tftp-deploy (duration 00:00:25) [common]
261 06:50:37.869795 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 06:50:37.869887 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 06:50:37.870009 substitutions:
264 06:50:37.870077 - {DTB}: 12694793/tftp-deploy-3scfsdto/dtb/mt8192-asurada-spherion-r0.dtb
265 06:50:37.870143 - {INITRD}: 12694793/tftp-deploy-3scfsdto/ramdisk/ramdisk.cpio.gz
266 06:50:37.870203 - {KERNEL}: 12694793/tftp-deploy-3scfsdto/kernel/Image
267 06:50:37.870260 - {LAVA_MAC}: None
268 06:50:37.870317 - {PRESEED_CONFIG}: None
269 06:50:37.870372 - {PRESEED_LOCAL}: None
270 06:50:37.870427 - {RAMDISK}: 12694793/tftp-deploy-3scfsdto/ramdisk/ramdisk.cpio.gz
271 06:50:37.870481 - {ROOT_PART}: None
272 06:50:37.870553 - {ROOT}: None
273 06:50:37.870622 - {SERVER_IP}: 192.168.201.1
274 06:50:37.870675 - {TEE}: None
275 06:50:37.870729 Parsed boot commands:
276 06:50:37.870783 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 06:50:37.870971 Parsed boot commands: tftpboot 192.168.201.1 12694793/tftp-deploy-3scfsdto/kernel/image.itb 12694793/tftp-deploy-3scfsdto/kernel/cmdline
278 06:50:37.871061 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 06:50:37.871154 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 06:50:37.871250 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 06:50:37.871335 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 06:50:37.871406 Not connected, no need to disconnect.
283 06:50:37.871481 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 06:50:37.871563 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 06:50:37.871629 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 06:50:37.875663 Setting prompt string to ['lava-test: # ']
287 06:50:37.876054 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 06:50:37.876169 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 06:50:37.876303 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 06:50:37.876436 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 06:50:37.876685 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 06:50:43.011664 >> Command sent successfully.
293 06:50:43.014251 Returned 0 in 5 seconds
294 06:50:43.114658 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 06:50:43.115036 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 06:50:43.115134 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 06:50:43.115226 Setting prompt string to 'Starting depthcharge on Spherion...'
299 06:50:43.115296 Changing prompt to 'Starting depthcharge on Spherion...'
300 06:50:43.115363 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 06:50:43.115626 [Enter `^Ec?' for help]
302 06:50:43.286706
303 06:50:43.286867
304 06:50:43.286941 F0: 102B 0000
305 06:50:43.287011
306 06:50:43.287071 F3: 1001 0000 [0200]
307 06:50:43.290889
308 06:50:43.290975 F3: 1001 0000
309 06:50:43.291043
310 06:50:43.291105 F7: 102D 0000
311 06:50:43.291166
312 06:50:43.291225 F1: 0000 0000
313 06:50:43.294090
314 06:50:43.294175 V0: 0000 0000 [0001]
315 06:50:43.294246
316 06:50:43.294309 00: 0007 8000
317 06:50:43.294374
318 06:50:43.297865 01: 0000 0000
319 06:50:43.297955
320 06:50:43.298023 BP: 0C00 0209 [0000]
321 06:50:43.298086
322 06:50:43.301606 G0: 1182 0000
323 06:50:43.301691
324 06:50:43.301758 EC: 0000 0021 [4000]
325 06:50:43.301820
326 06:50:43.305219 S7: 0000 0000 [0000]
327 06:50:43.305305
328 06:50:43.305372 CC: 0000 0000 [0001]
329 06:50:43.305434
330 06:50:43.308613 T0: 0000 0040 [010F]
331 06:50:43.308699
332 06:50:43.308767 Jump to BL
333 06:50:43.308830
334 06:50:43.333972
335 06:50:43.334156
336 06:50:43.334229
337 06:50:43.341519 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 06:50:43.345648 ARM64: Exception handlers installed.
339 06:50:43.349074 ARM64: Testing exception
340 06:50:43.349164 ARM64: Done test exception
341 06:50:43.356614 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 06:50:43.367223 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 06:50:43.373948 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 06:50:43.384534 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 06:50:43.391272 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 06:50:43.401614 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 06:50:43.411964 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 06:50:43.418471 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 06:50:43.436259 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 06:50:43.439833 WDT: Last reset was cold boot
351 06:50:43.443299 SPI1(PAD0) initialized at 2873684 Hz
352 06:50:43.446773 SPI5(PAD0) initialized at 992727 Hz
353 06:50:43.449527 VBOOT: Loading verstage.
354 06:50:43.456902 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 06:50:43.460975 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 06:50:43.464714 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 06:50:43.467904 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 06:50:43.474628 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 06:50:43.481459 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 06:50:43.491674 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 06:50:43.491780
362 06:50:43.491850
363 06:50:43.502036 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 06:50:43.505508 ARM64: Exception handlers installed.
365 06:50:43.508947 ARM64: Testing exception
366 06:50:43.509034 ARM64: Done test exception
367 06:50:43.515215 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 06:50:43.518643 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 06:50:43.532716 Probing TPM: . done!
370 06:50:43.532845 TPM ready after 0 ms
371 06:50:43.539489 Connected to device vid:did:rid of 1ae0:0028:00
372 06:50:43.546301 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 06:50:43.605908 Initialized TPM device CR50 revision 0
374 06:50:43.617983 tlcl_send_startup: Startup return code is 0
375 06:50:43.618125 TPM: setup succeeded
376 06:50:43.629181 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 06:50:43.638386 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 06:50:43.651945 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 06:50:43.659285 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 06:50:43.663494 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 06:50:43.666965 in-header: 03 07 00 00 08 00 00 00
382 06:50:43.670396 in-data: aa e4 47 04 13 02 00 00
383 06:50:43.674522 Chrome EC: UHEPI supported
384 06:50:43.678042 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 06:50:43.682272 in-header: 03 95 00 00 08 00 00 00
386 06:50:43.685672 in-data: 18 20 20 08 00 00 00 00
387 06:50:43.685763 Phase 1
388 06:50:43.689126 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 06:50:43.696402 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 06:50:43.703889 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 06:50:43.707252 Recovery requested (1009000e)
392 06:50:43.717015 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 06:50:43.720918 tlcl_extend: response is 0
394 06:50:43.729774 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 06:50:43.734906 tlcl_extend: response is 0
396 06:50:43.742308 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 06:50:43.761716 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 06:50:43.768752 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 06:50:43.768915
400 06:50:43.768990
401 06:50:43.778393 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 06:50:43.781961 ARM64: Exception handlers installed.
403 06:50:43.785421 ARM64: Testing exception
404 06:50:43.785536 ARM64: Done test exception
405 06:50:43.807212 pmic_efuse_setting: Set efuses in 11 msecs
406 06:50:43.810716 pmwrap_interface_init: Select PMIF_VLD_RDY
407 06:50:43.817420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 06:50:43.820789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 06:50:43.828322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 06:50:43.832437 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 06:50:43.836213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 06:50:43.840251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 06:50:43.847452 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 06:50:43.851284 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 06:50:43.855554 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 06:50:43.859054 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 06:50:43.863080 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 06:50:43.870076 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 06:50:43.874292 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 06:50:43.881421 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 06:50:43.885634 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 06:50:43.892703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 06:50:43.896876 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 06:50:43.903813 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 06:50:43.907434 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 06:50:43.915384 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 06:50:43.918796 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 06:50:43.926290 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 06:50:43.930496 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 06:50:43.938099 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 06:50:43.941583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 06:50:43.948665 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 06:50:43.952469 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 06:50:43.955956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 06:50:43.963242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 06:50:43.966786 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 06:50:43.971120 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 06:50:43.978540 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 06:50:43.981648 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 06:50:43.985088 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 06:50:43.992468 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 06:50:43.996044 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 06:50:44.003900 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 06:50:44.007822 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 06:50:44.011285 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 06:50:44.014769 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 06:50:44.018872 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 06:50:44.026306 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 06:50:44.029814 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 06:50:44.033970 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 06:50:44.037451 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 06:50:44.040898 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 06:50:44.044888 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 06:50:44.048273 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 06:50:44.055846 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 06:50:44.059314 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 06:50:44.063588 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 06:50:44.071265 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 06:50:44.078887 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 06:50:44.082417 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 06:50:44.092845 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 06:50:44.100706 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 06:50:44.104185 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 06:50:44.107982 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 06:50:44.111685 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 06:50:44.121348 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde71, sec=0x0
467 06:50:44.124775 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 06:50:44.132690 [RTC]rtc_osc_init,62: osc32con val = 0xde71
469 06:50:44.136165 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 06:50:44.145059 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 06:50:44.154462 [RTC]rtc_get_frequency_meter,154: input=23, output=941
472 06:50:44.164066 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 06:50:44.173970 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 06:50:44.183107 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 06:50:44.192909 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 06:50:44.202498 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 06:50:44.206400 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 06:50:44.210445 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 06:50:44.214001 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 06:50:44.221140 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 06:50:44.225338 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 06:50:44.228776 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 06:50:44.232604 ADC[4]: Raw value=906203 ID=7
484 06:50:44.232707 ADC[3]: Raw value=213441 ID=1
485 06:50:44.236803 RAM Code: 0x71
486 06:50:44.240917 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 06:50:44.244217 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 06:50:44.251850 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 06:50:44.259416 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 06:50:44.262796 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 06:50:44.266691 in-header: 03 07 00 00 08 00 00 00
492 06:50:44.270477 in-data: aa e4 47 04 13 02 00 00
493 06:50:44.274323 Chrome EC: UHEPI supported
494 06:50:44.278105 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 06:50:44.282250 in-header: 03 95 00 00 08 00 00 00
496 06:50:44.285756 in-data: 18 20 20 08 00 00 00 00
497 06:50:44.289411 MRC: failed to locate region type 0.
498 06:50:44.296788 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 06:50:44.301008 DRAM-K: Running full calibration
500 06:50:44.304598 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 06:50:44.308104 header.status = 0x0
502 06:50:44.311547 header.version = 0x6 (expected: 0x6)
503 06:50:44.314941 header.size = 0xd00 (expected: 0xd00)
504 06:50:44.315029 header.flags = 0x0
505 06:50:44.322323 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 06:50:44.340508 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 06:50:44.348146 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 06:50:44.348255 dram_init: ddr_geometry: 2
509 06:50:44.351732 [EMI] MDL number = 2
510 06:50:44.351822 [EMI] Get MDL freq = 0
511 06:50:44.355976 dram_init: ddr_type: 0
512 06:50:44.356065 is_discrete_lpddr4: 1
513 06:50:44.360273 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 06:50:44.360397
515 06:50:44.360514
516 06:50:44.363757 [Bian_co] ETT version 0.0.0.1
517 06:50:44.367337 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 06:50:44.367449
519 06:50:44.371653 dramc_set_vcore_voltage set vcore to 650000
520 06:50:44.375191 Read voltage for 800, 4
521 06:50:44.375279 Vio18 = 0
522 06:50:44.375348 Vcore = 650000
523 06:50:44.378697 Vdram = 0
524 06:50:44.378783 Vddq = 0
525 06:50:44.378852 Vmddr = 0
526 06:50:44.382603 dram_init: config_dvfs: 1
527 06:50:44.386335 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 06:50:44.393599 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 06:50:44.397101 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 06:50:44.401116 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 06:50:44.404258 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 06:50:44.407746 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 06:50:44.411189 MEM_TYPE=3, freq_sel=18
534 06:50:44.411275 sv_algorithm_assistance_LP4_1600
535 06:50:44.417490 ============ PULL DRAM RESETB DOWN ============
536 06:50:44.421500 ========== PULL DRAM RESETB DOWN end =========
537 06:50:44.424855 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 06:50:44.428818 ===================================
539 06:50:44.432244 LPDDR4 DRAM CONFIGURATION
540 06:50:44.435819 ===================================
541 06:50:44.435923 EX_ROW_EN[0] = 0x0
542 06:50:44.439444 EX_ROW_EN[1] = 0x0
543 06:50:44.439544 LP4Y_EN = 0x0
544 06:50:44.443680 WORK_FSP = 0x0
545 06:50:44.443769 WL = 0x2
546 06:50:44.446473 RL = 0x2
547 06:50:44.446590 BL = 0x2
548 06:50:44.449708 RPST = 0x0
549 06:50:44.449824 RD_PRE = 0x0
550 06:50:44.453019 WR_PRE = 0x1
551 06:50:44.453104 WR_PST = 0x0
552 06:50:44.456505 DBI_WR = 0x0
553 06:50:44.456591 DBI_RD = 0x0
554 06:50:44.459964 OTF = 0x1
555 06:50:44.463601 ===================================
556 06:50:44.466787 ===================================
557 06:50:44.466891 ANA top config
558 06:50:44.470209 ===================================
559 06:50:44.474213 DLL_ASYNC_EN = 0
560 06:50:44.474296 ALL_SLAVE_EN = 1
561 06:50:44.477692 NEW_RANK_MODE = 1
562 06:50:44.481100 DLL_IDLE_MODE = 1
563 06:50:44.484570 LP45_APHY_COMB_EN = 1
564 06:50:44.484676 TX_ODT_DIS = 1
565 06:50:44.487928 NEW_8X_MODE = 1
566 06:50:44.491463 ===================================
567 06:50:44.494986 ===================================
568 06:50:44.498364 data_rate = 1600
569 06:50:44.501787 CKR = 1
570 06:50:44.501895 DQ_P2S_RATIO = 8
571 06:50:44.505101 ===================================
572 06:50:44.508269 CA_P2S_RATIO = 8
573 06:50:44.511638 DQ_CA_OPEN = 0
574 06:50:44.515327 DQ_SEMI_OPEN = 0
575 06:50:44.518241 CA_SEMI_OPEN = 0
576 06:50:44.521974 CA_FULL_RATE = 0
577 06:50:44.522093 DQ_CKDIV4_EN = 1
578 06:50:44.525173 CA_CKDIV4_EN = 1
579 06:50:44.528526 CA_PREDIV_EN = 0
580 06:50:44.531957 PH8_DLY = 0
581 06:50:44.535424 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 06:50:44.538681 DQ_AAMCK_DIV = 4
583 06:50:44.538769 CA_AAMCK_DIV = 4
584 06:50:44.542252 CA_ADMCK_DIV = 4
585 06:50:44.545176 DQ_TRACK_CA_EN = 0
586 06:50:44.548725 CA_PICK = 800
587 06:50:44.552257 CA_MCKIO = 800
588 06:50:44.555722 MCKIO_SEMI = 0
589 06:50:44.555809 PLL_FREQ = 3068
590 06:50:44.559735 DQ_UI_PI_RATIO = 32
591 06:50:44.563081 CA_UI_PI_RATIO = 0
592 06:50:44.567285 ===================================
593 06:50:44.570874 ===================================
594 06:50:44.570964 memory_type:LPDDR4
595 06:50:44.574400 GP_NUM : 10
596 06:50:44.574485 SRAM_EN : 1
597 06:50:44.578508 MD32_EN : 0
598 06:50:44.582574 ===================================
599 06:50:44.582676 [ANA_INIT] >>>>>>>>>>>>>>
600 06:50:44.586011 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 06:50:44.589735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 06:50:44.593379 ===================================
603 06:50:44.596223 data_rate = 1600,PCW = 0X7600
604 06:50:44.599765 ===================================
605 06:50:44.603106 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 06:50:44.606493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 06:50:44.613563 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 06:50:44.616459 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 06:50:44.619936 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 06:50:44.623166 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 06:50:44.626543 [ANA_INIT] flow start
612 06:50:44.630217 [ANA_INIT] PLL >>>>>>>>
613 06:50:44.630305 [ANA_INIT] PLL <<<<<<<<
614 06:50:44.633204 [ANA_INIT] MIDPI >>>>>>>>
615 06:50:44.636705 [ANA_INIT] MIDPI <<<<<<<<
616 06:50:44.640186 [ANA_INIT] DLL >>>>>>>>
617 06:50:44.640273 [ANA_INIT] flow end
618 06:50:44.643079 ============ LP4 DIFF to SE enter ============
619 06:50:44.649788 ============ LP4 DIFF to SE exit ============
620 06:50:44.649880 [ANA_INIT] <<<<<<<<<<<<<
621 06:50:44.653217 [Flow] Enable top DCM control >>>>>
622 06:50:44.656664 [Flow] Enable top DCM control <<<<<
623 06:50:44.659878 Enable DLL master slave shuffle
624 06:50:44.667096 ==============================================================
625 06:50:44.667192 Gating Mode config
626 06:50:44.673271 ==============================================================
627 06:50:44.677214 Config description:
628 06:50:44.683467 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 06:50:44.690263 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 06:50:44.696632 SELPH_MODE 0: By rank 1: By Phase
631 06:50:44.703408 ==============================================================
632 06:50:44.703499 GAT_TRACK_EN = 1
633 06:50:44.706521 RX_GATING_MODE = 2
634 06:50:44.710003 RX_GATING_TRACK_MODE = 2
635 06:50:44.713374 SELPH_MODE = 1
636 06:50:44.716876 PICG_EARLY_EN = 1
637 06:50:44.720366 VALID_LAT_VALUE = 1
638 06:50:44.726553 ==============================================================
639 06:50:44.729905 Enter into Gating configuration >>>>
640 06:50:44.733404 Exit from Gating configuration <<<<
641 06:50:44.733497 Enter into DVFS_PRE_config >>>>>
642 06:50:44.746945 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 06:50:44.750375 Exit from DVFS_PRE_config <<<<<
644 06:50:44.753906 Enter into PICG configuration >>>>
645 06:50:44.757155 Exit from PICG configuration <<<<
646 06:50:44.757245 [RX_INPUT] configuration >>>>>
647 06:50:44.760683 [RX_INPUT] configuration <<<<<
648 06:50:44.766726 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 06:50:44.770134 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 06:50:44.777209 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 06:50:44.783648 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 06:50:44.790689 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 06:50:44.797095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 06:50:44.800858 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 06:50:44.803920 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 06:50:44.807087 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 06:50:44.813513 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 06:50:44.817066 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 06:50:44.820551 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 06:50:44.824200 ===================================
661 06:50:44.826964 LPDDR4 DRAM CONFIGURATION
662 06:50:44.830621 ===================================
663 06:50:44.830721 EX_ROW_EN[0] = 0x0
664 06:50:44.834190 EX_ROW_EN[1] = 0x0
665 06:50:44.837665 LP4Y_EN = 0x0
666 06:50:44.837756 WORK_FSP = 0x0
667 06:50:44.840976 WL = 0x2
668 06:50:44.841064 RL = 0x2
669 06:50:44.843834 BL = 0x2
670 06:50:44.843929 RPST = 0x0
671 06:50:44.847595 RD_PRE = 0x0
672 06:50:44.847712 WR_PRE = 0x1
673 06:50:44.850980 WR_PST = 0x0
674 06:50:44.851070 DBI_WR = 0x0
675 06:50:44.853835 DBI_RD = 0x0
676 06:50:44.853950 OTF = 0x1
677 06:50:44.857475 ===================================
678 06:50:44.860920 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 06:50:44.867662 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 06:50:44.871057 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 06:50:44.873859 ===================================
682 06:50:44.877388 LPDDR4 DRAM CONFIGURATION
683 06:50:44.880938 ===================================
684 06:50:44.881027 EX_ROW_EN[0] = 0x10
685 06:50:44.884488 EX_ROW_EN[1] = 0x0
686 06:50:44.884594 LP4Y_EN = 0x0
687 06:50:44.887313 WORK_FSP = 0x0
688 06:50:44.887400 WL = 0x2
689 06:50:44.890859 RL = 0x2
690 06:50:44.890948 BL = 0x2
691 06:50:44.894186 RPST = 0x0
692 06:50:44.897406 RD_PRE = 0x0
693 06:50:44.897503 WR_PRE = 0x1
694 06:50:44.901010 WR_PST = 0x0
695 06:50:44.901129 DBI_WR = 0x0
696 06:50:44.904359 DBI_RD = 0x0
697 06:50:44.904474 OTF = 0x1
698 06:50:44.907611 ===================================
699 06:50:44.914332 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 06:50:44.918186 nWR fixed to 40
701 06:50:44.921029 [ModeRegInit_LP4] CH0 RK0
702 06:50:44.921157 [ModeRegInit_LP4] CH0 RK1
703 06:50:44.924740 [ModeRegInit_LP4] CH1 RK0
704 06:50:44.927712 [ModeRegInit_LP4] CH1 RK1
705 06:50:44.927805 match AC timing 13
706 06:50:44.934627 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 06:50:44.938159 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 06:50:44.941547 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 06:50:44.947860 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 06:50:44.951378 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 06:50:44.951474 [EMI DOE] emi_dcm 0
712 06:50:44.958243 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 06:50:44.958334 ==
714 06:50:44.961619 Dram Type= 6, Freq= 0, CH_0, rank 0
715 06:50:44.964982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 06:50:44.965070 ==
717 06:50:44.971334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 06:50:44.974720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 06:50:44.985130 [CA 0] Center 36 (6~67) winsize 62
720 06:50:44.988677 [CA 1] Center 36 (6~67) winsize 62
721 06:50:44.992211 [CA 2] Center 34 (4~65) winsize 62
722 06:50:44.995135 [CA 3] Center 34 (4~64) winsize 61
723 06:50:44.998721 [CA 4] Center 33 (2~64) winsize 63
724 06:50:45.002132 [CA 5] Center 32 (3~62) winsize 60
725 06:50:45.002244
726 06:50:45.004905 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 06:50:45.004988
728 06:50:45.008547 [CATrainingPosCal] consider 1 rank data
729 06:50:45.011878 u2DelayCellTimex100 = 270/100 ps
730 06:50:45.015441 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 06:50:45.018416 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 06:50:45.025427 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 06:50:45.028846 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 06:50:45.032213 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
735 06:50:45.035155 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 06:50:45.035275
737 06:50:45.038747 CA PerBit enable=1, Macro0, CA PI delay=32
738 06:50:45.038860
739 06:50:45.041961 [CBTSetCACLKResult] CA Dly = 32
740 06:50:45.042076 CS Dly: 5 (0~36)
741 06:50:45.042175 ==
742 06:50:45.045185 Dram Type= 6, Freq= 0, CH_0, rank 1
743 06:50:45.051909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 06:50:45.052002 ==
745 06:50:45.055225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 06:50:45.061873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 06:50:45.071699 [CA 0] Center 36 (6~67) winsize 62
748 06:50:45.074510 [CA 1] Center 36 (6~67) winsize 62
749 06:50:45.078046 [CA 2] Center 34 (4~65) winsize 62
750 06:50:45.081441 [CA 3] Center 34 (3~65) winsize 63
751 06:50:45.084898 [CA 4] Center 33 (3~64) winsize 62
752 06:50:45.088230 [CA 5] Center 32 (2~63) winsize 62
753 06:50:45.088329
754 06:50:45.091808 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 06:50:45.091897
756 06:50:45.094754 [CATrainingPosCal] consider 2 rank data
757 06:50:45.098250 u2DelayCellTimex100 = 270/100 ps
758 06:50:45.101885 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 06:50:45.104701 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 06:50:45.111504 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 06:50:45.114862 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 06:50:45.118533 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
763 06:50:45.121462 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 06:50:45.121581
765 06:50:45.124948 CA PerBit enable=1, Macro0, CA PI delay=32
766 06:50:45.125061
767 06:50:45.128445 [CBTSetCACLKResult] CA Dly = 32
768 06:50:45.128532 CS Dly: 5 (0~36)
769 06:50:45.128600
770 06:50:45.132067 ----->DramcWriteLeveling(PI) begin...
771 06:50:45.132158 ==
772 06:50:45.135751 Dram Type= 6, Freq= 0, CH_0, rank 0
773 06:50:45.142249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 06:50:45.142351 ==
775 06:50:45.145731 Write leveling (Byte 0): 33 => 33
776 06:50:45.145821 Write leveling (Byte 1): 29 => 29
777 06:50:45.149987 DramcWriteLeveling(PI) end<-----
778 06:50:45.150077
779 06:50:45.150145 ==
780 06:50:45.152847 Dram Type= 6, Freq= 0, CH_0, rank 0
781 06:50:45.156283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 06:50:45.160193 ==
783 06:50:45.160318 [Gating] SW mode calibration
784 06:50:45.167446 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 06:50:45.173857 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 06:50:45.177522 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 06:50:45.180694 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 06:50:45.186955 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 06:50:45.190946 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 06:50:45.194218 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 06:50:45.200787 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 06:50:45.204187 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 06:50:45.207043 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 06:50:45.213855 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 06:50:45.217204 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 06:50:45.220923 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 06:50:45.227115 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 06:50:45.230514 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 06:50:45.233866 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 06:50:45.237276 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 06:50:45.244069 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 06:50:45.247447 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 06:50:45.251020 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 06:50:45.257679 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 06:50:45.260994 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 06:50:45.264247 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 06:50:45.271159 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 06:50:45.274703 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 06:50:45.277817 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 06:50:45.283980 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 06:50:45.287356 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 06:50:45.291109 0 9 8 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
813 06:50:45.297274 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
814 06:50:45.300905 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 06:50:45.303927 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 06:50:45.310935 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 06:50:45.314225 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 06:50:45.317775 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 06:50:45.320660 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
820 06:50:45.327421 0 10 8 | B1->B0 | 3131 2424 | 1 0 | (1 1) (0 0)
821 06:50:45.331109 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 06:50:45.334250 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 06:50:45.341005 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 06:50:45.344424 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 06:50:45.347889 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 06:50:45.354242 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 06:50:45.357597 0 11 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
828 06:50:45.360819 0 11 8 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (0 0)
829 06:50:45.367527 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
830 06:50:45.370913 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 06:50:45.374499 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 06:50:45.381299 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 06:50:45.384563 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 06:50:45.387955 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 06:50:45.394170 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 06:50:45.397511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 06:50:45.400968 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 06:50:45.404223 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 06:50:45.411151 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 06:50:45.414449 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 06:50:45.417718 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 06:50:45.424423 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 06:50:45.427610 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 06:50:45.431342 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 06:50:45.437725 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 06:50:45.440971 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 06:50:45.444904 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 06:50:45.451470 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 06:50:45.454424 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 06:50:45.457874 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 06:50:45.464729 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 06:50:45.468174 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 06:50:45.471505 Total UI for P1: 0, mck2ui 16
854 06:50:45.474879 best dqsien dly found for B0: ( 0, 14, 4)
855 06:50:45.477790 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 06:50:45.481171 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 06:50:45.484628 Total UI for P1: 0, mck2ui 16
858 06:50:45.488670 best dqsien dly found for B1: ( 0, 14, 10)
859 06:50:45.491966 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
860 06:50:45.495486 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 06:50:45.495596
862 06:50:45.498269 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
863 06:50:45.505240 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 06:50:45.505340 [Gating] SW calibration Done
865 06:50:45.505438 ==
866 06:50:45.508691 Dram Type= 6, Freq= 0, CH_0, rank 0
867 06:50:45.515154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 06:50:45.515271 ==
869 06:50:45.515394 RX Vref Scan: 0
870 06:50:45.515489
871 06:50:45.518783 RX Vref 0 -> 0, step: 1
872 06:50:45.518899
873 06:50:45.522434 RX Delay -130 -> 252, step: 16
874 06:50:45.525177 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
875 06:50:45.528665 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
876 06:50:45.532160 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 06:50:45.538947 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 06:50:45.542282 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
879 06:50:45.545244 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 06:50:45.548539 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
881 06:50:45.552226 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
882 06:50:45.558854 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
883 06:50:45.562180 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
884 06:50:45.565664 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
885 06:50:45.568549 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
886 06:50:45.571816 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
887 06:50:45.578655 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
888 06:50:45.582281 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
889 06:50:45.585131 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 06:50:45.585211 ==
891 06:50:45.588723 Dram Type= 6, Freq= 0, CH_0, rank 0
892 06:50:45.592193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 06:50:45.592316 ==
894 06:50:45.595512 DQS Delay:
895 06:50:45.595590 DQS0 = 0, DQS1 = 0
896 06:50:45.598947 DQM Delay:
897 06:50:45.599041 DQM0 = 90, DQM1 = 85
898 06:50:45.599158 DQ Delay:
899 06:50:45.601783 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
900 06:50:45.605465 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
901 06:50:45.608915 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
902 06:50:45.612426 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
903 06:50:45.612537
904 06:50:45.612662
905 06:50:45.612777 ==
906 06:50:45.615326 Dram Type= 6, Freq= 0, CH_0, rank 0
907 06:50:45.621815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 06:50:45.621906 ==
909 06:50:45.622040
910 06:50:45.622142
911 06:50:45.622242 TX Vref Scan disable
912 06:50:45.626077 == TX Byte 0 ==
913 06:50:45.629573 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 06:50:45.632406 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 06:50:45.636103 == TX Byte 1 ==
916 06:50:45.638956 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
917 06:50:45.646011 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
918 06:50:45.646128 ==
919 06:50:45.649465 Dram Type= 6, Freq= 0, CH_0, rank 0
920 06:50:45.652798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 06:50:45.652912 ==
922 06:50:45.665706 TX Vref=22, minBit 5, minWin=27, winSum=447
923 06:50:45.668976 TX Vref=24, minBit 8, minWin=27, winSum=451
924 06:50:45.672211 TX Vref=26, minBit 10, minWin=27, winSum=452
925 06:50:45.675288 TX Vref=28, minBit 4, minWin=28, winSum=457
926 06:50:45.678908 TX Vref=30, minBit 4, minWin=28, winSum=456
927 06:50:45.682175 TX Vref=32, minBit 6, minWin=27, winSum=450
928 06:50:45.688504 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 28
929 06:50:45.688626
930 06:50:45.692373 Final TX Range 1 Vref 28
931 06:50:45.692467
932 06:50:45.692539 ==
933 06:50:45.695692 Dram Type= 6, Freq= 0, CH_0, rank 0
934 06:50:45.698581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 06:50:45.698673 ==
936 06:50:45.698751
937 06:50:45.702017
938 06:50:45.702100 TX Vref Scan disable
939 06:50:45.705275 == TX Byte 0 ==
940 06:50:45.708810 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
941 06:50:45.712225 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
942 06:50:45.715686 == TX Byte 1 ==
943 06:50:45.719055 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
944 06:50:45.722661 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
945 06:50:45.722792
946 06:50:45.725526 [DATLAT]
947 06:50:45.725618 Freq=800, CH0 RK0
948 06:50:45.725717
949 06:50:45.729126 DATLAT Default: 0xa
950 06:50:45.729231 0, 0xFFFF, sum = 0
951 06:50:45.732748 1, 0xFFFF, sum = 0
952 06:50:45.732848 2, 0xFFFF, sum = 0
953 06:50:45.735392 3, 0xFFFF, sum = 0
954 06:50:45.735505 4, 0xFFFF, sum = 0
955 06:50:45.738800 5, 0xFFFF, sum = 0
956 06:50:45.738919 6, 0xFFFF, sum = 0
957 06:50:45.742407 7, 0xFFFF, sum = 0
958 06:50:45.742516 8, 0xFFFF, sum = 0
959 06:50:45.745471 9, 0x0, sum = 1
960 06:50:45.745579 10, 0x0, sum = 2
961 06:50:45.748860 11, 0x0, sum = 3
962 06:50:45.748936 12, 0x0, sum = 4
963 06:50:45.752498 best_step = 10
964 06:50:45.752583
965 06:50:45.752649 ==
966 06:50:45.755304 Dram Type= 6, Freq= 0, CH_0, rank 0
967 06:50:45.758808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 06:50:45.758920 ==
969 06:50:45.762350 RX Vref Scan: 1
970 06:50:45.762462
971 06:50:45.762563 Set Vref Range= 32 -> 127
972 06:50:45.762659
973 06:50:45.765793 RX Vref 32 -> 127, step: 1
974 06:50:45.765907
975 06:50:45.769339 RX Delay -79 -> 252, step: 8
976 06:50:45.769449
977 06:50:45.772395 Set Vref, RX VrefLevel [Byte0]: 32
978 06:50:45.775912 [Byte1]: 32
979 06:50:45.776023
980 06:50:45.779512 Set Vref, RX VrefLevel [Byte0]: 33
981 06:50:45.782288 [Byte1]: 33
982 06:50:45.782394
983 06:50:45.786384 Set Vref, RX VrefLevel [Byte0]: 34
984 06:50:45.789117 [Byte1]: 34
985 06:50:45.793465
986 06:50:45.793579 Set Vref, RX VrefLevel [Byte0]: 35
987 06:50:45.796538 [Byte1]: 35
988 06:50:45.800718
989 06:50:45.800842 Set Vref, RX VrefLevel [Byte0]: 36
990 06:50:45.804722 [Byte1]: 36
991 06:50:45.808920
992 06:50:45.809009 Set Vref, RX VrefLevel [Byte0]: 37
993 06:50:45.812104 [Byte1]: 37
994 06:50:45.816546
995 06:50:45.816667 Set Vref, RX VrefLevel [Byte0]: 38
996 06:50:45.819786 [Byte1]: 38
997 06:50:45.823053
998 06:50:45.826896 Set Vref, RX VrefLevel [Byte0]: 39
999 06:50:45.827016 [Byte1]: 39
1000 06:50:45.831232
1001 06:50:45.831351 Set Vref, RX VrefLevel [Byte0]: 40
1002 06:50:45.834719 [Byte1]: 40
1003 06:50:45.838256
1004 06:50:45.838374 Set Vref, RX VrefLevel [Byte0]: 41
1005 06:50:45.841703 [Byte1]: 41
1006 06:50:45.846106
1007 06:50:45.846224 Set Vref, RX VrefLevel [Byte0]: 42
1008 06:50:45.849409 [Byte1]: 42
1009 06:50:45.853607
1010 06:50:45.853717 Set Vref, RX VrefLevel [Byte0]: 43
1011 06:50:45.857116 [Byte1]: 43
1012 06:50:45.861348
1013 06:50:45.861462 Set Vref, RX VrefLevel [Byte0]: 44
1014 06:50:45.864703 [Byte1]: 44
1015 06:50:45.868863
1016 06:50:45.868959 Set Vref, RX VrefLevel [Byte0]: 45
1017 06:50:45.872341 [Byte1]: 45
1018 06:50:45.876375
1019 06:50:45.876489 Set Vref, RX VrefLevel [Byte0]: 46
1020 06:50:45.879927 [Byte1]: 46
1021 06:50:45.884051
1022 06:50:45.884164 Set Vref, RX VrefLevel [Byte0]: 47
1023 06:50:45.887375 [Byte1]: 47
1024 06:50:45.891045
1025 06:50:45.891156 Set Vref, RX VrefLevel [Byte0]: 48
1026 06:50:45.894863 [Byte1]: 48
1027 06:50:45.899166
1028 06:50:45.899282 Set Vref, RX VrefLevel [Byte0]: 49
1029 06:50:45.901993 [Byte1]: 49
1030 06:50:45.906234
1031 06:50:45.906345 Set Vref, RX VrefLevel [Byte0]: 50
1032 06:50:45.909864 [Byte1]: 50
1033 06:50:45.913988
1034 06:50:45.914098 Set Vref, RX VrefLevel [Byte0]: 51
1035 06:50:45.917358 [Byte1]: 51
1036 06:50:45.921337
1037 06:50:45.921436 Set Vref, RX VrefLevel [Byte0]: 52
1038 06:50:45.924793 [Byte1]: 52
1039 06:50:45.928825
1040 06:50:45.928910 Set Vref, RX VrefLevel [Byte0]: 53
1041 06:50:45.932349 [Byte1]: 53
1042 06:50:45.937124
1043 06:50:45.937250 Set Vref, RX VrefLevel [Byte0]: 54
1044 06:50:45.940308 [Byte1]: 54
1045 06:50:45.943973
1046 06:50:45.944084 Set Vref, RX VrefLevel [Byte0]: 55
1047 06:50:45.947665 [Byte1]: 55
1048 06:50:45.951622
1049 06:50:45.951708 Set Vref, RX VrefLevel [Byte0]: 56
1050 06:50:45.955169 [Byte1]: 56
1051 06:50:45.959375
1052 06:50:45.959458 Set Vref, RX VrefLevel [Byte0]: 57
1053 06:50:45.962223 [Byte1]: 57
1054 06:50:45.967237
1055 06:50:45.967357 Set Vref, RX VrefLevel [Byte0]: 58
1056 06:50:45.969919 [Byte1]: 58
1057 06:50:45.974217
1058 06:50:45.974330 Set Vref, RX VrefLevel [Byte0]: 59
1059 06:50:45.977724 [Byte1]: 59
1060 06:50:45.982107
1061 06:50:45.982196 Set Vref, RX VrefLevel [Byte0]: 60
1062 06:50:45.984988 [Byte1]: 60
1063 06:50:45.989375
1064 06:50:45.989461 Set Vref, RX VrefLevel [Byte0]: 61
1065 06:50:45.992713 [Byte1]: 61
1066 06:50:45.996708
1067 06:50:45.996823 Set Vref, RX VrefLevel [Byte0]: 62
1068 06:50:46.000210 [Byte1]: 62
1069 06:50:46.005011
1070 06:50:46.005099 Set Vref, RX VrefLevel [Byte0]: 63
1071 06:50:46.007754 [Byte1]: 63
1072 06:50:46.011873
1073 06:50:46.011959 Set Vref, RX VrefLevel [Byte0]: 64
1074 06:50:46.015261 [Byte1]: 64
1075 06:50:46.019588
1076 06:50:46.019701 Set Vref, RX VrefLevel [Byte0]: 65
1077 06:50:46.023151 [Byte1]: 65
1078 06:50:46.027183
1079 06:50:46.027273 Set Vref, RX VrefLevel [Byte0]: 66
1080 06:50:46.030454 [Byte1]: 66
1081 06:50:46.035210
1082 06:50:46.035304 Set Vref, RX VrefLevel [Byte0]: 67
1083 06:50:46.037911 [Byte1]: 67
1084 06:50:46.042724
1085 06:50:46.042818 Set Vref, RX VrefLevel [Byte0]: 68
1086 06:50:46.045565 [Byte1]: 68
1087 06:50:46.049831
1088 06:50:46.049941 Set Vref, RX VrefLevel [Byte0]: 69
1089 06:50:46.053376 [Byte1]: 69
1090 06:50:46.057184
1091 06:50:46.057292 Set Vref, RX VrefLevel [Byte0]: 70
1092 06:50:46.060388 [Byte1]: 70
1093 06:50:46.065318
1094 06:50:46.065394 Set Vref, RX VrefLevel [Byte0]: 71
1095 06:50:46.068055 [Byte1]: 71
1096 06:50:46.072209
1097 06:50:46.072328 Set Vref, RX VrefLevel [Byte0]: 72
1098 06:50:46.076197 [Byte1]: 72
1099 06:50:46.080405
1100 06:50:46.080491 Set Vref, RX VrefLevel [Byte0]: 73
1101 06:50:46.083165 [Byte1]: 73
1102 06:50:46.087875
1103 06:50:46.087963 Set Vref, RX VrefLevel [Byte0]: 74
1104 06:50:46.090718 [Byte1]: 74
1105 06:50:46.094906
1106 06:50:46.094990 Set Vref, RX VrefLevel [Byte0]: 75
1107 06:50:46.098288 [Byte1]: 75
1108 06:50:46.102929
1109 06:50:46.103013 Set Vref, RX VrefLevel [Byte0]: 76
1110 06:50:46.106421 [Byte1]: 76
1111 06:50:46.110236
1112 06:50:46.110341 Set Vref, RX VrefLevel [Byte0]: 77
1113 06:50:46.113732 [Byte1]: 77
1114 06:50:46.117949
1115 06:50:46.118033 Set Vref, RX VrefLevel [Byte0]: 78
1116 06:50:46.121485 [Byte1]: 78
1117 06:50:46.125655
1118 06:50:46.125761 Final RX Vref Byte 0 = 57 to rank0
1119 06:50:46.129146 Final RX Vref Byte 1 = 58 to rank0
1120 06:50:46.131938 Final RX Vref Byte 0 = 57 to rank1
1121 06:50:46.135308 Final RX Vref Byte 1 = 58 to rank1==
1122 06:50:46.138754 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 06:50:46.145234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 06:50:46.145327 ==
1125 06:50:46.145431 DQS Delay:
1126 06:50:46.145534 DQS0 = 0, DQS1 = 0
1127 06:50:46.149160 DQM Delay:
1128 06:50:46.149242 DQM0 = 92, DQM1 = 85
1129 06:50:46.151758 DQ Delay:
1130 06:50:46.155057 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1131 06:50:46.158857 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1132 06:50:46.162174 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1133 06:50:46.165730 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1134 06:50:46.165820
1135 06:50:46.165886
1136 06:50:46.172280 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1137 06:50:46.175010 CH0 RK0: MR19=606, MR18=4A3F
1138 06:50:46.181753 CH0_RK0: MR19=0x606, MR18=0x4A3F, DQSOSC=391, MR23=63, INC=96, DEC=64
1139 06:50:46.181846
1140 06:50:46.185119 ----->DramcWriteLeveling(PI) begin...
1141 06:50:46.185207 ==
1142 06:50:46.188542 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 06:50:46.191829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 06:50:46.191911 ==
1145 06:50:46.195314 Write leveling (Byte 0): 34 => 34
1146 06:50:46.198731 Write leveling (Byte 1): 32 => 32
1147 06:50:46.202002 DramcWriteLeveling(PI) end<-----
1148 06:50:46.202080
1149 06:50:46.202162 ==
1150 06:50:46.205445 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 06:50:46.208704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 06:50:46.208807 ==
1153 06:50:46.252785 [Gating] SW mode calibration
1154 06:50:46.253445 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 06:50:46.254131 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 06:50:46.254534 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 06:50:46.254646 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 06:50:46.254749 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1159 06:50:46.254848 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 06:50:46.254945 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 06:50:46.255058 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 06:50:46.296988 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 06:50:46.297239 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 06:50:46.297568 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 06:50:46.297685 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 06:50:46.297791 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 06:50:46.297892 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 06:50:46.297995 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 06:50:46.298094 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 06:50:46.298209 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 06:50:46.298309 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 06:50:46.321413 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 06:50:46.321638 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1174 06:50:46.321983 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1175 06:50:46.322098 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 06:50:46.322192 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 06:50:46.325035 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 06:50:46.325138 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 06:50:46.328349 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 06:50:46.335025 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 06:50:46.338432 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 06:50:46.341917 0 9 8 | B1->B0 | 2d2d 2c2c | 0 0 | (0 0) (0 0)
1183 06:50:46.348331 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 06:50:46.351600 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 06:50:46.355071 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 06:50:46.361927 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 06:50:46.365424 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 06:50:46.368307 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 06:50:46.374751 0 10 4 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
1190 06:50:46.378190 0 10 8 | B1->B0 | 2a2a 2b2b | 0 0 | (0 0) (0 0)
1191 06:50:46.382134 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 06:50:46.386174 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 06:50:46.390075 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 06:50:46.397844 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 06:50:46.400778 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 06:50:46.403865 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 06:50:46.407513 0 11 4 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
1198 06:50:46.414974 0 11 8 | B1->B0 | 3d3d 3939 | 0 1 | (0 0) (0 0)
1199 06:50:46.418212 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 06:50:46.421594 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 06:50:46.428073 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 06:50:46.431602 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 06:50:46.435087 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 06:50:46.441238 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 06:50:46.444679 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 06:50:46.448105 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 06:50:46.451616 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 06:50:46.458394 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 06:50:46.461820 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 06:50:46.464543 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 06:50:46.471429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 06:50:46.474932 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 06:50:46.478370 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 06:50:46.484521 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 06:50:46.487916 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 06:50:46.491326 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 06:50:46.497986 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 06:50:46.501349 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 06:50:46.504707 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 06:50:46.511383 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 06:50:46.514806 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 06:50:46.517948 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1223 06:50:46.524912 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 06:50:46.525024 Total UI for P1: 0, mck2ui 16
1225 06:50:46.528008 best dqsien dly found for B0: ( 0, 14, 8)
1226 06:50:46.531667 Total UI for P1: 0, mck2ui 16
1227 06:50:46.534595 best dqsien dly found for B1: ( 0, 14, 8)
1228 06:50:46.538133 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1229 06:50:46.541499 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1230 06:50:46.545162
1231 06:50:46.548196 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 06:50:46.551877 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1233 06:50:46.555127 [Gating] SW calibration Done
1234 06:50:46.555237 ==
1235 06:50:46.558561 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 06:50:46.562040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 06:50:46.562152 ==
1238 06:50:46.562246 RX Vref Scan: 0
1239 06:50:46.562351
1240 06:50:46.564827 RX Vref 0 -> 0, step: 1
1241 06:50:46.564901
1242 06:50:46.568282 RX Delay -130 -> 252, step: 16
1243 06:50:46.571718 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1244 06:50:46.575204 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1245 06:50:46.582183 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1246 06:50:46.584895 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1247 06:50:46.588363 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1248 06:50:46.591746 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1249 06:50:46.595245 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1250 06:50:46.598632 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1251 06:50:46.605236 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1252 06:50:46.608749 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1253 06:50:46.612175 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1254 06:50:46.615613 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1255 06:50:46.618980 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1256 06:50:46.625266 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1257 06:50:46.628676 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1258 06:50:46.632106 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1259 06:50:46.632213 ==
1260 06:50:46.635358 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 06:50:46.638964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 06:50:46.639074 ==
1263 06:50:46.642439 DQS Delay:
1264 06:50:46.642541 DQS0 = 0, DQS1 = 0
1265 06:50:46.645760 DQM Delay:
1266 06:50:46.645835 DQM0 = 95, DQM1 = 85
1267 06:50:46.645898 DQ Delay:
1268 06:50:46.649167 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1269 06:50:46.652373 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1270 06:50:46.655581 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
1271 06:50:46.658610 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1272 06:50:46.658716
1273 06:50:46.658808
1274 06:50:46.662211 ==
1275 06:50:46.665467 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 06:50:46.668967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 06:50:46.669045 ==
1278 06:50:46.669113
1279 06:50:46.669174
1280 06:50:46.672410 TX Vref Scan disable
1281 06:50:46.672492 == TX Byte 0 ==
1282 06:50:46.675283 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1283 06:50:46.682267 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1284 06:50:46.682381 == TX Byte 1 ==
1285 06:50:46.685610 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1286 06:50:46.692468 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1287 06:50:46.692601 ==
1288 06:50:46.695280 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 06:50:46.698714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 06:50:46.698821 ==
1291 06:50:46.712325 TX Vref=22, minBit 10, minWin=27, winSum=447
1292 06:50:46.715769 TX Vref=24, minBit 12, minWin=27, winSum=449
1293 06:50:46.718550 TX Vref=26, minBit 1, minWin=28, winSum=452
1294 06:50:46.722004 TX Vref=28, minBit 4, minWin=28, winSum=458
1295 06:50:46.725457 TX Vref=30, minBit 4, minWin=28, winSum=455
1296 06:50:46.732452 TX Vref=32, minBit 15, minWin=27, winSum=451
1297 06:50:46.735251 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 28
1298 06:50:46.735365
1299 06:50:46.739216 Final TX Range 1 Vref 28
1300 06:50:46.739337
1301 06:50:46.739412 ==
1302 06:50:46.741977 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 06:50:46.745473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 06:50:46.745549 ==
1305 06:50:46.745611
1306 06:50:46.748906
1307 06:50:46.748984 TX Vref Scan disable
1308 06:50:46.752510 == TX Byte 0 ==
1309 06:50:46.755375 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1310 06:50:46.762288 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1311 06:50:46.762399 == TX Byte 1 ==
1312 06:50:46.765710 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1313 06:50:46.772529 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1314 06:50:46.772634
1315 06:50:46.772729 [DATLAT]
1316 06:50:46.772826 Freq=800, CH0 RK1
1317 06:50:46.772915
1318 06:50:46.775908 DATLAT Default: 0xa
1319 06:50:46.776005 0, 0xFFFF, sum = 0
1320 06:50:46.779136 1, 0xFFFF, sum = 0
1321 06:50:46.779213 2, 0xFFFF, sum = 0
1322 06:50:46.782201 3, 0xFFFF, sum = 0
1323 06:50:46.782273 4, 0xFFFF, sum = 0
1324 06:50:46.785411 5, 0xFFFF, sum = 0
1325 06:50:46.788668 6, 0xFFFF, sum = 0
1326 06:50:46.788772 7, 0xFFFF, sum = 0
1327 06:50:46.792403 8, 0xFFFF, sum = 0
1328 06:50:46.792490 9, 0x0, sum = 1
1329 06:50:46.792555 10, 0x0, sum = 2
1330 06:50:46.795449 11, 0x0, sum = 3
1331 06:50:46.795537 12, 0x0, sum = 4
1332 06:50:46.798612 best_step = 10
1333 06:50:46.798718
1334 06:50:46.798810 ==
1335 06:50:46.802351 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 06:50:46.805369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 06:50:46.805447 ==
1338 06:50:46.809076 RX Vref Scan: 0
1339 06:50:46.809146
1340 06:50:46.809210 RX Vref 0 -> 0, step: 1
1341 06:50:46.809270
1342 06:50:46.812346 RX Delay -95 -> 252, step: 8
1343 06:50:46.819341 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1344 06:50:46.822098 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1345 06:50:46.825643 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1346 06:50:46.829178 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1347 06:50:46.832591 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1348 06:50:46.838861 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1349 06:50:46.842170 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1350 06:50:46.845468 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1351 06:50:46.848887 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1352 06:50:46.852399 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1353 06:50:46.855879 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1354 06:50:46.862769 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1355 06:50:46.866217 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1356 06:50:46.869004 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1357 06:50:46.872268 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1358 06:50:46.879344 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1359 06:50:46.879448 ==
1360 06:50:46.882792 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 06:50:46.886101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 06:50:46.886199 ==
1363 06:50:46.886301 DQS Delay:
1364 06:50:46.889404 DQS0 = 0, DQS1 = 0
1365 06:50:46.889502 DQM Delay:
1366 06:50:46.892506 DQM0 = 93, DQM1 = 84
1367 06:50:46.892603 DQ Delay:
1368 06:50:46.895875 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1369 06:50:46.899353 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1370 06:50:46.902745 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1371 06:50:46.906110 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1372 06:50:46.906207
1373 06:50:46.906308
1374 06:50:46.913165 [DQSOSCAuto] RK1, (LSB)MR18= 0x4112, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1375 06:50:46.915867 CH0 RK1: MR19=606, MR18=4112
1376 06:50:46.922539 CH0_RK1: MR19=0x606, MR18=0x4112, DQSOSC=393, MR23=63, INC=95, DEC=63
1377 06:50:46.926284 [RxdqsGatingPostProcess] freq 800
1378 06:50:46.932707 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1379 06:50:46.932787 Pre-setting of DQS Precalculation
1380 06:50:46.939348 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1381 06:50:46.939431 ==
1382 06:50:46.942730 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 06:50:46.946100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 06:50:46.946176 ==
1385 06:50:46.952629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1386 06:50:46.959469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1387 06:50:46.967104 [CA 0] Center 36 (6~67) winsize 62
1388 06:50:46.970638 [CA 1] Center 36 (6~67) winsize 62
1389 06:50:46.974068 [CA 2] Center 35 (5~65) winsize 61
1390 06:50:46.977448 [CA 3] Center 34 (4~65) winsize 62
1391 06:50:46.980292 [CA 4] Center 34 (4~65) winsize 62
1392 06:50:46.983643 [CA 5] Center 34 (4~64) winsize 61
1393 06:50:46.983740
1394 06:50:46.987190 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1395 06:50:46.987295
1396 06:50:46.990728 [CATrainingPosCal] consider 1 rank data
1397 06:50:46.994200 u2DelayCellTimex100 = 270/100 ps
1398 06:50:46.997620 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 06:50:47.001074 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1400 06:50:47.004360 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1401 06:50:47.010906 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 06:50:47.014243 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 06:50:47.017669 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1404 06:50:47.017743
1405 06:50:47.020900 CA PerBit enable=1, Macro0, CA PI delay=34
1406 06:50:47.021005
1407 06:50:47.024375 [CBTSetCACLKResult] CA Dly = 34
1408 06:50:47.024460 CS Dly: 6 (0~37)
1409 06:50:47.024542 ==
1410 06:50:47.027197 Dram Type= 6, Freq= 0, CH_1, rank 1
1411 06:50:47.034085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 06:50:47.034194 ==
1413 06:50:47.037566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 06:50:47.044193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 06:50:47.053976 [CA 0] Center 36 (6~67) winsize 62
1416 06:50:47.057553 [CA 1] Center 37 (6~68) winsize 63
1417 06:50:47.061423 [CA 2] Center 35 (4~66) winsize 63
1418 06:50:47.064791 [CA 3] Center 34 (4~65) winsize 62
1419 06:50:47.068826 [CA 4] Center 35 (5~65) winsize 61
1420 06:50:47.068910 [CA 5] Center 34 (4~65) winsize 62
1421 06:50:47.072707
1422 06:50:47.076263 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1423 06:50:47.076410
1424 06:50:47.076518 [CATrainingPosCal] consider 2 rank data
1425 06:50:47.080950 u2DelayCellTimex100 = 270/100 ps
1426 06:50:47.083652 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 06:50:47.087121 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1428 06:50:47.090648 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1429 06:50:47.096844 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 06:50:47.100336 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1431 06:50:47.103832 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1432 06:50:47.103931
1433 06:50:47.107269 CA PerBit enable=1, Macro0, CA PI delay=34
1434 06:50:47.107368
1435 06:50:47.110728 [CBTSetCACLKResult] CA Dly = 34
1436 06:50:47.110830 CS Dly: 6 (0~38)
1437 06:50:47.110925
1438 06:50:47.113960 ----->DramcWriteLeveling(PI) begin...
1439 06:50:47.114034 ==
1440 06:50:47.117262 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 06:50:47.123955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 06:50:47.124062 ==
1443 06:50:47.127199 Write leveling (Byte 0): 26 => 26
1444 06:50:47.127302 Write leveling (Byte 1): 31 => 31
1445 06:50:47.130539 DramcWriteLeveling(PI) end<-----
1446 06:50:47.130651
1447 06:50:47.133924 ==
1448 06:50:47.134028 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 06:50:47.140665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 06:50:47.140775 ==
1451 06:50:47.144209 [Gating] SW mode calibration
1452 06:50:47.150904 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1453 06:50:47.154272 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1454 06:50:47.161089 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1455 06:50:47.164419 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 06:50:47.167239 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 06:50:47.170675 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 06:50:47.177395 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 06:50:47.180595 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 06:50:47.184529 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 06:50:47.190877 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 06:50:47.194126 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 06:50:47.197388 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 06:50:47.204233 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 06:50:47.207762 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 06:50:47.210527 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 06:50:47.217398 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 06:50:47.220717 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 06:50:47.223834 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 06:50:47.230962 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1471 06:50:47.234310 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1472 06:50:47.237497 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 06:50:47.244351 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 06:50:47.247828 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 06:50:47.251352 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 06:50:47.254051 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 06:50:47.261182 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 06:50:47.264501 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 06:50:47.267341 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1480 06:50:47.274291 0 9 8 | B1->B0 | 2f2f 3434 | 1 0 | (1 1) (0 0)
1481 06:50:47.277686 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 06:50:47.281207 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 06:50:47.287443 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 06:50:47.291024 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 06:50:47.294488 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 06:50:47.301366 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 1)
1487 06:50:47.304633 0 10 4 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (1 0)
1488 06:50:47.307784 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1489 06:50:47.314197 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 06:50:47.317736 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 06:50:47.321154 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 06:50:47.327550 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 06:50:47.331013 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 06:50:47.334478 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 06:50:47.338013 0 11 4 | B1->B0 | 2727 3535 | 0 0 | (0 0) (1 1)
1496 06:50:47.344507 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1497 06:50:47.347721 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 06:50:47.350887 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 06:50:47.357978 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 06:50:47.361096 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 06:50:47.364474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 06:50:47.371237 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 06:50:47.374678 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1504 06:50:47.378203 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 06:50:47.384405 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 06:50:47.387837 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 06:50:47.391431 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 06:50:47.397792 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 06:50:47.401229 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 06:50:47.404655 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 06:50:47.408170 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 06:50:47.414566 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 06:50:47.417978 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 06:50:47.421464 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 06:50:47.428301 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 06:50:47.431619 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 06:50:47.434840 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 06:50:47.441539 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 06:50:47.444854 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 06:50:47.447908 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 06:50:47.451630 Total UI for P1: 0, mck2ui 16
1522 06:50:47.455146 best dqsien dly found for B0: ( 0, 14, 4)
1523 06:50:47.458057 Total UI for P1: 0, mck2ui 16
1524 06:50:47.461958 best dqsien dly found for B1: ( 0, 14, 4)
1525 06:50:47.464599 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1526 06:50:47.468339 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1527 06:50:47.468461
1528 06:50:47.471558 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 06:50:47.478220 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1530 06:50:47.478356 [Gating] SW calibration Done
1531 06:50:47.478429 ==
1532 06:50:47.481403 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 06:50:47.488183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 06:50:47.488362 ==
1535 06:50:47.488450 RX Vref Scan: 0
1536 06:50:47.488521
1537 06:50:47.491256 RX Vref 0 -> 0, step: 1
1538 06:50:47.491367
1539 06:50:47.494720 RX Delay -130 -> 252, step: 16
1540 06:50:47.498136 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1541 06:50:47.501668 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1542 06:50:47.505251 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1543 06:50:47.511675 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1544 06:50:47.515026 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1545 06:50:47.518475 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1546 06:50:47.521812 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1547 06:50:47.525369 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1548 06:50:47.528044 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1549 06:50:47.534903 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1550 06:50:47.538283 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1551 06:50:47.541477 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1552 06:50:47.544945 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1553 06:50:47.551879 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1554 06:50:47.554662 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1555 06:50:47.558138 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1556 06:50:47.558214 ==
1557 06:50:47.561353 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 06:50:47.564739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 06:50:47.564824 ==
1560 06:50:47.568089 DQS Delay:
1561 06:50:47.568191 DQS0 = 0, DQS1 = 0
1562 06:50:47.571466 DQM Delay:
1563 06:50:47.571553 DQM0 = 93, DQM1 = 87
1564 06:50:47.571616 DQ Delay:
1565 06:50:47.574902 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1566 06:50:47.578248 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1567 06:50:47.581398 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1568 06:50:47.585124 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1569 06:50:47.585228
1570 06:50:47.585324
1571 06:50:47.585416 ==
1572 06:50:47.588115 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 06:50:47.595016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 06:50:47.595094 ==
1575 06:50:47.595171
1576 06:50:47.595231
1577 06:50:47.595289 TX Vref Scan disable
1578 06:50:47.598787 == TX Byte 0 ==
1579 06:50:47.602301 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1580 06:50:47.605405 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1581 06:50:47.608874 == TX Byte 1 ==
1582 06:50:47.611898 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1583 06:50:47.615616 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1584 06:50:47.619256 ==
1585 06:50:47.622676 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 06:50:47.625468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 06:50:47.625564 ==
1588 06:50:47.638563 TX Vref=22, minBit 1, minWin=26, winSum=434
1589 06:50:47.642138 TX Vref=24, minBit 1, minWin=27, winSum=441
1590 06:50:47.644796 TX Vref=26, minBit 1, minWin=27, winSum=442
1591 06:50:47.648113 TX Vref=28, minBit 1, minWin=27, winSum=444
1592 06:50:47.651574 TX Vref=30, minBit 0, minWin=27, winSum=443
1593 06:50:47.654957 TX Vref=32, minBit 7, minWin=26, winSum=443
1594 06:50:47.661904 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 28
1595 06:50:47.661991
1596 06:50:47.665296 Final TX Range 1 Vref 28
1597 06:50:47.665381
1598 06:50:47.665447 ==
1599 06:50:47.668167 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 06:50:47.671629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 06:50:47.671714 ==
1602 06:50:47.671779
1603 06:50:47.671840
1604 06:50:47.674970 TX Vref Scan disable
1605 06:50:47.678451 == TX Byte 0 ==
1606 06:50:47.681770 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1607 06:50:47.685294 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1608 06:50:47.688694 == TX Byte 1 ==
1609 06:50:47.691992 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1610 06:50:47.695194 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1611 06:50:47.695277
1612 06:50:47.698337 [DATLAT]
1613 06:50:47.698421 Freq=800, CH1 RK0
1614 06:50:47.698487
1615 06:50:47.702138 DATLAT Default: 0xa
1616 06:50:47.702221 0, 0xFFFF, sum = 0
1617 06:50:47.705521 1, 0xFFFF, sum = 0
1618 06:50:47.705606 2, 0xFFFF, sum = 0
1619 06:50:47.708799 3, 0xFFFF, sum = 0
1620 06:50:47.708884 4, 0xFFFF, sum = 0
1621 06:50:47.712158 5, 0xFFFF, sum = 0
1622 06:50:47.712269 6, 0xFFFF, sum = 0
1623 06:50:47.715526 7, 0xFFFF, sum = 0
1624 06:50:47.715612 8, 0xFFFF, sum = 0
1625 06:50:47.718774 9, 0x0, sum = 1
1626 06:50:47.718859 10, 0x0, sum = 2
1627 06:50:47.721998 11, 0x0, sum = 3
1628 06:50:47.722082 12, 0x0, sum = 4
1629 06:50:47.725375 best_step = 10
1630 06:50:47.725485
1631 06:50:47.725590 ==
1632 06:50:47.728760 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 06:50:47.731921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 06:50:47.731999 ==
1635 06:50:47.735124 RX Vref Scan: 1
1636 06:50:47.735201
1637 06:50:47.735265 Set Vref Range= 32 -> 127
1638 06:50:47.735326
1639 06:50:47.738547 RX Vref 32 -> 127, step: 1
1640 06:50:47.738642
1641 06:50:47.742040 RX Delay -79 -> 252, step: 8
1642 06:50:47.742146
1643 06:50:47.745419 Set Vref, RX VrefLevel [Byte0]: 32
1644 06:50:47.748860 [Byte1]: 32
1645 06:50:47.748938
1646 06:50:47.752183 Set Vref, RX VrefLevel [Byte0]: 33
1647 06:50:47.755427 [Byte1]: 33
1648 06:50:47.758925
1649 06:50:47.759005 Set Vref, RX VrefLevel [Byte0]: 34
1650 06:50:47.761713 [Byte1]: 34
1651 06:50:47.765876
1652 06:50:47.765953 Set Vref, RX VrefLevel [Byte0]: 35
1653 06:50:47.769319 [Byte1]: 35
1654 06:50:47.773425
1655 06:50:47.773507 Set Vref, RX VrefLevel [Byte0]: 36
1656 06:50:47.776703 [Byte1]: 36
1657 06:50:47.781430
1658 06:50:47.781510 Set Vref, RX VrefLevel [Byte0]: 37
1659 06:50:47.784306 [Byte1]: 37
1660 06:50:47.788451
1661 06:50:47.788525 Set Vref, RX VrefLevel [Byte0]: 38
1662 06:50:47.791892 [Byte1]: 38
1663 06:50:47.796164
1664 06:50:47.796240 Set Vref, RX VrefLevel [Byte0]: 39
1665 06:50:47.799444 [Byte1]: 39
1666 06:50:47.803595
1667 06:50:47.803685 Set Vref, RX VrefLevel [Byte0]: 40
1668 06:50:47.806966 [Byte1]: 40
1669 06:50:47.811604
1670 06:50:47.811735 Set Vref, RX VrefLevel [Byte0]: 41
1671 06:50:47.814917 [Byte1]: 41
1672 06:50:47.818756
1673 06:50:47.818878 Set Vref, RX VrefLevel [Byte0]: 42
1674 06:50:47.822240 [Byte1]: 42
1675 06:50:47.826210
1676 06:50:47.826300 Set Vref, RX VrefLevel [Byte0]: 43
1677 06:50:47.829677 [Byte1]: 43
1678 06:50:47.834228
1679 06:50:47.834352 Set Vref, RX VrefLevel [Byte0]: 44
1680 06:50:47.836945 [Byte1]: 44
1681 06:50:47.841878
1682 06:50:47.841998 Set Vref, RX VrefLevel [Byte0]: 45
1683 06:50:47.844999 [Byte1]: 45
1684 06:50:47.848678
1685 06:50:47.848789 Set Vref, RX VrefLevel [Byte0]: 46
1686 06:50:47.852547 [Byte1]: 46
1687 06:50:47.856662
1688 06:50:47.856769 Set Vref, RX VrefLevel [Byte0]: 47
1689 06:50:47.860092 [Byte1]: 47
1690 06:50:47.864189
1691 06:50:47.864316 Set Vref, RX VrefLevel [Byte0]: 48
1692 06:50:47.867692 [Byte1]: 48
1693 06:50:47.871937
1694 06:50:47.872051 Set Vref, RX VrefLevel [Byte0]: 49
1695 06:50:47.874762 [Byte1]: 49
1696 06:50:47.878993
1697 06:50:47.879105 Set Vref, RX VrefLevel [Byte0]: 50
1698 06:50:47.882310 [Byte1]: 50
1699 06:50:47.886987
1700 06:50:47.887064 Set Vref, RX VrefLevel [Byte0]: 51
1701 06:50:47.889725 [Byte1]: 51
1702 06:50:47.894640
1703 06:50:47.894724 Set Vref, RX VrefLevel [Byte0]: 52
1704 06:50:47.897410 [Byte1]: 52
1705 06:50:47.901626
1706 06:50:47.901717 Set Vref, RX VrefLevel [Byte0]: 53
1707 06:50:47.905024 [Byte1]: 53
1708 06:50:47.909188
1709 06:50:47.909270 Set Vref, RX VrefLevel [Byte0]: 54
1710 06:50:47.912569 [Byte1]: 54
1711 06:50:47.916668
1712 06:50:47.916746 Set Vref, RX VrefLevel [Byte0]: 55
1713 06:50:47.920149 [Byte1]: 55
1714 06:50:47.924730
1715 06:50:47.924808 Set Vref, RX VrefLevel [Byte0]: 56
1716 06:50:47.927949 [Byte1]: 56
1717 06:50:47.931924
1718 06:50:47.932033 Set Vref, RX VrefLevel [Byte0]: 57
1719 06:50:47.935070 [Byte1]: 57
1720 06:50:47.939623
1721 06:50:47.939778 Set Vref, RX VrefLevel [Byte0]: 58
1722 06:50:47.942708 [Byte1]: 58
1723 06:50:47.947177
1724 06:50:47.947308 Set Vref, RX VrefLevel [Byte0]: 59
1725 06:50:47.950627 [Byte1]: 59
1726 06:50:47.954788
1727 06:50:47.954894 Set Vref, RX VrefLevel [Byte0]: 60
1728 06:50:47.958154 [Byte1]: 60
1729 06:50:47.961973
1730 06:50:47.962087 Set Vref, RX VrefLevel [Byte0]: 61
1731 06:50:47.965676 [Byte1]: 61
1732 06:50:47.970247
1733 06:50:47.970367 Set Vref, RX VrefLevel [Byte0]: 62
1734 06:50:47.973370 [Byte1]: 62
1735 06:50:47.977543
1736 06:50:47.977652 Set Vref, RX VrefLevel [Byte0]: 63
1737 06:50:47.980941 [Byte1]: 63
1738 06:50:47.984963
1739 06:50:47.985096 Set Vref, RX VrefLevel [Byte0]: 64
1740 06:50:47.988568 [Byte1]: 64
1741 06:50:47.992497
1742 06:50:47.992622 Set Vref, RX VrefLevel [Byte0]: 65
1743 06:50:47.995933 [Byte1]: 65
1744 06:50:48.000227
1745 06:50:48.000365 Set Vref, RX VrefLevel [Byte0]: 66
1746 06:50:48.003118 [Byte1]: 66
1747 06:50:48.007253
1748 06:50:48.007364 Set Vref, RX VrefLevel [Byte0]: 67
1749 06:50:48.010760 [Byte1]: 67
1750 06:50:48.014729
1751 06:50:48.014823 Set Vref, RX VrefLevel [Byte0]: 68
1752 06:50:48.018417 [Byte1]: 68
1753 06:50:48.022439
1754 06:50:48.022594 Set Vref, RX VrefLevel [Byte0]: 69
1755 06:50:48.025696 [Byte1]: 69
1756 06:50:48.029908
1757 06:50:48.030043 Set Vref, RX VrefLevel [Byte0]: 70
1758 06:50:48.033182 [Byte1]: 70
1759 06:50:48.037351
1760 06:50:48.037483 Set Vref, RX VrefLevel [Byte0]: 71
1761 06:50:48.040739 [Byte1]: 71
1762 06:50:48.045300
1763 06:50:48.045414 Set Vref, RX VrefLevel [Byte0]: 72
1764 06:50:48.048663 [Byte1]: 72
1765 06:50:48.052571
1766 06:50:48.052657 Set Vref, RX VrefLevel [Byte0]: 73
1767 06:50:48.056471 [Byte1]: 73
1768 06:50:48.060203
1769 06:50:48.060322 Final RX Vref Byte 0 = 56 to rank0
1770 06:50:48.063624 Final RX Vref Byte 1 = 55 to rank0
1771 06:50:48.067040 Final RX Vref Byte 0 = 56 to rank1
1772 06:50:48.070465 Final RX Vref Byte 1 = 55 to rank1==
1773 06:50:48.073844 Dram Type= 6, Freq= 0, CH_1, rank 0
1774 06:50:48.080258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1775 06:50:48.080380 ==
1776 06:50:48.080490 DQS Delay:
1777 06:50:48.080587 DQS0 = 0, DQS1 = 0
1778 06:50:48.084107 DQM Delay:
1779 06:50:48.084212 DQM0 = 95, DQM1 = 90
1780 06:50:48.087103 DQ Delay:
1781 06:50:48.090614 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1782 06:50:48.090704 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1783 06:50:48.093859 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1784 06:50:48.100597 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1785 06:50:48.100694
1786 06:50:48.100761
1787 06:50:48.106821 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1788 06:50:48.110373 CH1 RK0: MR19=606, MR18=2A47
1789 06:50:48.117475 CH1_RK0: MR19=0x606, MR18=0x2A47, DQSOSC=392, MR23=63, INC=96, DEC=64
1790 06:50:48.117630
1791 06:50:48.120657 ----->DramcWriteLeveling(PI) begin...
1792 06:50:48.120780 ==
1793 06:50:48.123857 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 06:50:48.127167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 06:50:48.127286 ==
1796 06:50:48.130688 Write leveling (Byte 0): 25 => 25
1797 06:50:48.134108 Write leveling (Byte 1): 28 => 28
1798 06:50:48.137525 DramcWriteLeveling(PI) end<-----
1799 06:50:48.137638
1800 06:50:48.137734 ==
1801 06:50:48.140308 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 06:50:48.143816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 06:50:48.143923 ==
1804 06:50:48.147272 [Gating] SW mode calibration
1805 06:50:48.153923 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1806 06:50:48.160326 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1807 06:50:48.164169 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1808 06:50:48.167397 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1809 06:50:48.173722 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 06:50:48.177190 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 06:50:48.180730 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 06:50:48.187159 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 06:50:48.190411 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 06:50:48.193779 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 06:50:48.200277 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 06:50:48.204225 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 06:50:48.207156 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 06:50:48.210661 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 06:50:48.217176 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 06:50:48.220651 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 06:50:48.224328 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 06:50:48.230554 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 06:50:48.234063 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1824 06:50:48.237544 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1825 06:50:48.243559 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1826 06:50:48.247147 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 06:50:48.250508 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 06:50:48.257527 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 06:50:48.260227 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 06:50:48.263737 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 06:50:48.270610 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 06:50:48.273946 0 9 4 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
1833 06:50:48.277129 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1834 06:50:48.283913 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 06:50:48.287348 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 06:50:48.290792 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 06:50:48.297618 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 06:50:48.300430 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 06:50:48.303857 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 06:50:48.307373 0 10 4 | B1->B0 | 2b2b 2e2e | 0 0 | (1 0) (0 0)
1841 06:50:48.314375 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1842 06:50:48.317125 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 06:50:48.320496 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 06:50:48.327433 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 06:50:48.331128 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 06:50:48.334355 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 06:50:48.340831 0 11 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1848 06:50:48.344066 0 11 4 | B1->B0 | 3d3d 2b2b | 0 0 | (0 0) (0 0)
1849 06:50:48.347417 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1850 06:50:48.354186 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 06:50:48.357226 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 06:50:48.360525 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 06:50:48.367536 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 06:50:48.371008 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 06:50:48.374327 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 06:50:48.377788 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1857 06:50:48.384057 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 06:50:48.387478 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 06:50:48.390760 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 06:50:48.397532 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 06:50:48.400705 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 06:50:48.404186 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 06:50:48.411247 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 06:50:48.414689 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 06:50:48.417434 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 06:50:48.424368 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 06:50:48.427713 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 06:50:48.431207 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 06:50:48.438102 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 06:50:48.440919 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 06:50:48.444420 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 06:50:48.447759 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1873 06:50:48.451203 Total UI for P1: 0, mck2ui 16
1874 06:50:48.454524 best dqsien dly found for B1: ( 0, 14, 2)
1875 06:50:48.461427 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 06:50:48.464672 Total UI for P1: 0, mck2ui 16
1877 06:50:48.467650 best dqsien dly found for B0: ( 0, 14, 4)
1878 06:50:48.471074 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1879 06:50:48.474448 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1880 06:50:48.474561
1881 06:50:48.478024 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1882 06:50:48.481252 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1883 06:50:48.484234 [Gating] SW calibration Done
1884 06:50:48.484343 ==
1885 06:50:48.487926 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 06:50:48.491365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 06:50:48.491480 ==
1888 06:50:48.494789 RX Vref Scan: 0
1889 06:50:48.494892
1890 06:50:48.494985 RX Vref 0 -> 0, step: 1
1891 06:50:48.495078
1892 06:50:48.497513 RX Delay -130 -> 252, step: 16
1893 06:50:48.504156 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1894 06:50:48.507958 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1895 06:50:48.511258 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1896 06:50:48.514737 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1897 06:50:48.518095 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1898 06:50:48.521506 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1899 06:50:48.527887 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1900 06:50:48.531416 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1901 06:50:48.534844 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1902 06:50:48.538304 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1903 06:50:48.541079 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1904 06:50:48.547828 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1905 06:50:48.551354 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1906 06:50:48.554736 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1907 06:50:48.558217 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1908 06:50:48.561994 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1909 06:50:48.564719 ==
1910 06:50:48.564795 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 06:50:48.571661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 06:50:48.571791 ==
1913 06:50:48.571900 DQS Delay:
1914 06:50:48.574408 DQS0 = 0, DQS1 = 0
1915 06:50:48.574522 DQM Delay:
1916 06:50:48.577899 DQM0 = 93, DQM1 = 88
1917 06:50:48.578008 DQ Delay:
1918 06:50:48.581442 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1919 06:50:48.584669 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1920 06:50:48.588331 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1921 06:50:48.591402 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1922 06:50:48.591514
1923 06:50:48.591606
1924 06:50:48.591695 ==
1925 06:50:48.594816 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 06:50:48.598578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 06:50:48.598697 ==
1928 06:50:48.598791
1929 06:50:48.598886
1930 06:50:48.601339 TX Vref Scan disable
1931 06:50:48.604907 == TX Byte 0 ==
1932 06:50:48.608037 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1933 06:50:48.611600 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1934 06:50:48.614911 == TX Byte 1 ==
1935 06:50:48.618399 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1936 06:50:48.621816 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1937 06:50:48.621895 ==
1938 06:50:48.624785 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 06:50:48.628333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 06:50:48.628448 ==
1941 06:50:48.643203 TX Vref=22, minBit 0, minWin=27, winSum=443
1942 06:50:48.646051 TX Vref=24, minBit 1, minWin=26, winSum=444
1943 06:50:48.649369 TX Vref=26, minBit 0, minWin=27, winSum=449
1944 06:50:48.652885 TX Vref=28, minBit 2, minWin=27, winSum=450
1945 06:50:48.656327 TX Vref=30, minBit 0, minWin=27, winSum=448
1946 06:50:48.659577 TX Vref=32, minBit 0, minWin=27, winSum=448
1947 06:50:48.666470 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 28
1948 06:50:48.666578
1949 06:50:48.669214 Final TX Range 1 Vref 28
1950 06:50:48.669289
1951 06:50:48.669353 ==
1952 06:50:48.673244 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 06:50:48.675905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 06:50:48.676004 ==
1955 06:50:48.676100
1956 06:50:48.676189
1957 06:50:48.679471 TX Vref Scan disable
1958 06:50:48.682982 == TX Byte 0 ==
1959 06:50:48.686363 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1960 06:50:48.690042 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1961 06:50:48.692844 == TX Byte 1 ==
1962 06:50:48.696275 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1963 06:50:48.699774 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1964 06:50:48.699848
1965 06:50:48.703220 [DATLAT]
1966 06:50:48.703295 Freq=800, CH1 RK1
1967 06:50:48.703367
1968 06:50:48.706464 DATLAT Default: 0xa
1969 06:50:48.706536 0, 0xFFFF, sum = 0
1970 06:50:48.709680 1, 0xFFFF, sum = 0
1971 06:50:48.709757 2, 0xFFFF, sum = 0
1972 06:50:48.712835 3, 0xFFFF, sum = 0
1973 06:50:48.712911 4, 0xFFFF, sum = 0
1974 06:50:48.716625 5, 0xFFFF, sum = 0
1975 06:50:48.716745 6, 0xFFFF, sum = 0
1976 06:50:48.719476 7, 0xFFFF, sum = 0
1977 06:50:48.719578 8, 0xFFFF, sum = 0
1978 06:50:48.722802 9, 0x0, sum = 1
1979 06:50:48.722886 10, 0x0, sum = 2
1980 06:50:48.726200 11, 0x0, sum = 3
1981 06:50:48.726303 12, 0x0, sum = 4
1982 06:50:48.729647 best_step = 10
1983 06:50:48.729754
1984 06:50:48.729847 ==
1985 06:50:48.733493 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 06:50:48.736653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 06:50:48.736738 ==
1988 06:50:48.739697 RX Vref Scan: 0
1989 06:50:48.739790
1990 06:50:48.739856 RX Vref 0 -> 0, step: 1
1991 06:50:48.739920
1992 06:50:48.742946 RX Delay -79 -> 252, step: 8
1993 06:50:48.749394 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1994 06:50:48.752916 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1995 06:50:48.756095 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1996 06:50:48.759636 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1997 06:50:48.763032 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1998 06:50:48.766376 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1999 06:50:48.773189 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2000 06:50:48.776575 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2001 06:50:48.779872 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2002 06:50:48.783275 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2003 06:50:48.786184 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2004 06:50:48.789785 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2005 06:50:48.796177 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2006 06:50:48.799692 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2007 06:50:48.803154 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2008 06:50:48.806766 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2009 06:50:48.806882 ==
2010 06:50:48.809620 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 06:50:48.816567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 06:50:48.816658 ==
2013 06:50:48.816730 DQS Delay:
2014 06:50:48.816802 DQS0 = 0, DQS1 = 0
2015 06:50:48.820070 DQM Delay:
2016 06:50:48.820169 DQM0 = 97, DQM1 = 90
2017 06:50:48.823366 DQ Delay:
2018 06:50:48.826597 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2019 06:50:48.829935 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2020 06:50:48.833318 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2021 06:50:48.836849 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2022 06:50:48.836954
2023 06:50:48.837045
2024 06:50:48.843193 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
2025 06:50:48.846549 CH1 RK1: MR19=606, MR18=4C15
2026 06:50:48.852917 CH1_RK1: MR19=0x606, MR18=0x4C15, DQSOSC=390, MR23=63, INC=97, DEC=64
2027 06:50:48.856279 [RxdqsGatingPostProcess] freq 800
2028 06:50:48.859743 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2029 06:50:48.863060 Pre-setting of DQS Precalculation
2030 06:50:48.869817 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2031 06:50:48.876252 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2032 06:50:48.883169 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2033 06:50:48.883250
2034 06:50:48.883321
2035 06:50:48.886317 [Calibration Summary] 1600 Mbps
2036 06:50:48.886407 CH 0, Rank 0
2037 06:50:48.889896 SW Impedance : PASS
2038 06:50:48.893010 DUTY Scan : NO K
2039 06:50:48.893093 ZQ Calibration : PASS
2040 06:50:48.896881 Jitter Meter : NO K
2041 06:50:48.899626 CBT Training : PASS
2042 06:50:48.899708 Write leveling : PASS
2043 06:50:48.903257 RX DQS gating : PASS
2044 06:50:48.906695 RX DQ/DQS(RDDQC) : PASS
2045 06:50:48.906771 TX DQ/DQS : PASS
2046 06:50:48.909626 RX DATLAT : PASS
2047 06:50:48.909696 RX DQ/DQS(Engine): PASS
2048 06:50:48.913130 TX OE : NO K
2049 06:50:48.913234 All Pass.
2050 06:50:48.913325
2051 06:50:48.916555 CH 0, Rank 1
2052 06:50:48.916655 SW Impedance : PASS
2053 06:50:48.920046 DUTY Scan : NO K
2054 06:50:48.923496 ZQ Calibration : PASS
2055 06:50:48.923601 Jitter Meter : NO K
2056 06:50:48.927003 CBT Training : PASS
2057 06:50:48.929807 Write leveling : PASS
2058 06:50:48.929881 RX DQS gating : PASS
2059 06:50:48.933231 RX DQ/DQS(RDDQC) : PASS
2060 06:50:48.936555 TX DQ/DQS : PASS
2061 06:50:48.936668 RX DATLAT : PASS
2062 06:50:48.939735 RX DQ/DQS(Engine): PASS
2063 06:50:48.943237 TX OE : NO K
2064 06:50:48.943337 All Pass.
2065 06:50:48.943440
2066 06:50:48.943529 CH 1, Rank 0
2067 06:50:48.946707 SW Impedance : PASS
2068 06:50:48.950093 DUTY Scan : NO K
2069 06:50:48.950193 ZQ Calibration : PASS
2070 06:50:48.953485 Jitter Meter : NO K
2071 06:50:48.953594 CBT Training : PASS
2072 06:50:48.956351 Write leveling : PASS
2073 06:50:48.959821 RX DQS gating : PASS
2074 06:50:48.959928 RX DQ/DQS(RDDQC) : PASS
2075 06:50:48.963373 TX DQ/DQS : PASS
2076 06:50:48.966919 RX DATLAT : PASS
2077 06:50:48.967032 RX DQ/DQS(Engine): PASS
2078 06:50:48.969813 TX OE : NO K
2079 06:50:48.969920 All Pass.
2080 06:50:48.970012
2081 06:50:48.973244 CH 1, Rank 1
2082 06:50:48.973341 SW Impedance : PASS
2083 06:50:48.976715 DUTY Scan : NO K
2084 06:50:48.980235 ZQ Calibration : PASS
2085 06:50:48.980344 Jitter Meter : NO K
2086 06:50:48.982939 CBT Training : PASS
2087 06:50:48.986374 Write leveling : PASS
2088 06:50:48.986453 RX DQS gating : PASS
2089 06:50:48.990107 RX DQ/DQS(RDDQC) : PASS
2090 06:50:48.993163 TX DQ/DQS : PASS
2091 06:50:48.993270 RX DATLAT : PASS
2092 06:50:48.996360 RX DQ/DQS(Engine): PASS
2093 06:50:48.996442 TX OE : NO K
2094 06:50:49.000108 All Pass.
2095 06:50:49.000246
2096 06:50:49.000381 DramC Write-DBI off
2097 06:50:49.003555 PER_BANK_REFRESH: Hybrid Mode
2098 06:50:49.006734 TX_TRACKING: ON
2099 06:50:49.010330 [GetDramInforAfterCalByMRR] Vendor 6.
2100 06:50:49.013649 [GetDramInforAfterCalByMRR] Revision 606.
2101 06:50:49.016492 [GetDramInforAfterCalByMRR] Revision 2 0.
2102 06:50:49.016566 MR0 0x3b3b
2103 06:50:49.016627 MR8 0x5151
2104 06:50:49.020014 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 06:50:49.023547
2106 06:50:49.023629 MR0 0x3b3b
2107 06:50:49.023694 MR8 0x5151
2108 06:50:49.026918 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 06:50:49.027020
2110 06:50:49.036653 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2111 06:50:49.040008 [FAST_K] Save calibration result to emmc
2112 06:50:49.043286 [FAST_K] Save calibration result to emmc
2113 06:50:49.046719 dram_init: config_dvfs: 1
2114 06:50:49.049909 dramc_set_vcore_voltage set vcore to 662500
2115 06:50:49.053396 Read voltage for 1200, 2
2116 06:50:49.053503 Vio18 = 0
2117 06:50:49.053601 Vcore = 662500
2118 06:50:49.056873 Vdram = 0
2119 06:50:49.056973 Vddq = 0
2120 06:50:49.057075 Vmddr = 0
2121 06:50:49.063848 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2122 06:50:49.066735 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2123 06:50:49.070198 MEM_TYPE=3, freq_sel=15
2124 06:50:49.073631 sv_algorithm_assistance_LP4_1600
2125 06:50:49.077224 ============ PULL DRAM RESETB DOWN ============
2126 06:50:49.080073 ========== PULL DRAM RESETB DOWN end =========
2127 06:50:49.087197 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2128 06:50:49.090680 ===================================
2129 06:50:49.090783 LPDDR4 DRAM CONFIGURATION
2130 06:50:49.094178 ===================================
2131 06:50:49.096896 EX_ROW_EN[0] = 0x0
2132 06:50:49.100278 EX_ROW_EN[1] = 0x0
2133 06:50:49.100380 LP4Y_EN = 0x0
2134 06:50:49.103859 WORK_FSP = 0x0
2135 06:50:49.103980 WL = 0x4
2136 06:50:49.107150 RL = 0x4
2137 06:50:49.107288 BL = 0x2
2138 06:50:49.110383 RPST = 0x0
2139 06:50:49.110456 RD_PRE = 0x0
2140 06:50:49.113600 WR_PRE = 0x1
2141 06:50:49.113688 WR_PST = 0x0
2142 06:50:49.116930 DBI_WR = 0x0
2143 06:50:49.117039 DBI_RD = 0x0
2144 06:50:49.120304 OTF = 0x1
2145 06:50:49.123739 ===================================
2146 06:50:49.127255 ===================================
2147 06:50:49.127357 ANA top config
2148 06:50:49.130857 ===================================
2149 06:50:49.134084 DLL_ASYNC_EN = 0
2150 06:50:49.137430 ALL_SLAVE_EN = 0
2151 06:50:49.137528 NEW_RANK_MODE = 1
2152 06:50:49.140564 DLL_IDLE_MODE = 1
2153 06:50:49.144174 LP45_APHY_COMB_EN = 1
2154 06:50:49.147295 TX_ODT_DIS = 1
2155 06:50:49.147403 NEW_8X_MODE = 1
2156 06:50:49.150440 ===================================
2157 06:50:49.153832 ===================================
2158 06:50:49.157250 data_rate = 2400
2159 06:50:49.160810 CKR = 1
2160 06:50:49.164191 DQ_P2S_RATIO = 8
2161 06:50:49.167576 ===================================
2162 06:50:49.170486 CA_P2S_RATIO = 8
2163 06:50:49.173934 DQ_CA_OPEN = 0
2164 06:50:49.174052 DQ_SEMI_OPEN = 0
2165 06:50:49.177621 CA_SEMI_OPEN = 0
2166 06:50:49.181149 CA_FULL_RATE = 0
2167 06:50:49.183931 DQ_CKDIV4_EN = 0
2168 06:50:49.187417 CA_CKDIV4_EN = 0
2169 06:50:49.190857 CA_PREDIV_EN = 0
2170 06:50:49.190971 PH8_DLY = 17
2171 06:50:49.194372 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2172 06:50:49.197904 DQ_AAMCK_DIV = 4
2173 06:50:49.200749 CA_AAMCK_DIV = 4
2174 06:50:49.204136 CA_ADMCK_DIV = 4
2175 06:50:49.207518 DQ_TRACK_CA_EN = 0
2176 06:50:49.207627 CA_PICK = 1200
2177 06:50:49.210998 CA_MCKIO = 1200
2178 06:50:49.214487 MCKIO_SEMI = 0
2179 06:50:49.217784 PLL_FREQ = 2366
2180 06:50:49.221327 DQ_UI_PI_RATIO = 32
2181 06:50:49.224817 CA_UI_PI_RATIO = 0
2182 06:50:49.228061 ===================================
2183 06:50:49.230958 ===================================
2184 06:50:49.231062 memory_type:LPDDR4
2185 06:50:49.234399 GP_NUM : 10
2186 06:50:49.238159 SRAM_EN : 1
2187 06:50:49.238276 MD32_EN : 0
2188 06:50:49.240831 ===================================
2189 06:50:49.244399 [ANA_INIT] >>>>>>>>>>>>>>
2190 06:50:49.247953 <<<<<< [CONFIGURE PHASE]: ANA_TX
2191 06:50:49.251419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2192 06:50:49.254368 ===================================
2193 06:50:49.257729 data_rate = 2400,PCW = 0X5b00
2194 06:50:49.261088 ===================================
2195 06:50:49.264345 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2196 06:50:49.267833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 06:50:49.274359 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 06:50:49.277573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2199 06:50:49.280787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2200 06:50:49.284525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2201 06:50:49.287665 [ANA_INIT] flow start
2202 06:50:49.291031 [ANA_INIT] PLL >>>>>>>>
2203 06:50:49.291118 [ANA_INIT] PLL <<<<<<<<
2204 06:50:49.294389 [ANA_INIT] MIDPI >>>>>>>>
2205 06:50:49.297446 [ANA_INIT] MIDPI <<<<<<<<
2206 06:50:49.297533 [ANA_INIT] DLL >>>>>>>>
2207 06:50:49.301324 [ANA_INIT] DLL <<<<<<<<
2208 06:50:49.304691 [ANA_INIT] flow end
2209 06:50:49.307522 ============ LP4 DIFF to SE enter ============
2210 06:50:49.311023 ============ LP4 DIFF to SE exit ============
2211 06:50:49.314595 [ANA_INIT] <<<<<<<<<<<<<
2212 06:50:49.317370 [Flow] Enable top DCM control >>>>>
2213 06:50:49.320809 [Flow] Enable top DCM control <<<<<
2214 06:50:49.324344 Enable DLL master slave shuffle
2215 06:50:49.327720 ==============================================================
2216 06:50:49.331315 Gating Mode config
2217 06:50:49.338097 ==============================================================
2218 06:50:49.338181 Config description:
2219 06:50:49.347937 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2220 06:50:49.354315 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2221 06:50:49.357751 SELPH_MODE 0: By rank 1: By Phase
2222 06:50:49.364247 ==============================================================
2223 06:50:49.367936 GAT_TRACK_EN = 1
2224 06:50:49.371274 RX_GATING_MODE = 2
2225 06:50:49.374686 RX_GATING_TRACK_MODE = 2
2226 06:50:49.377998 SELPH_MODE = 1
2227 06:50:49.381161 PICG_EARLY_EN = 1
2228 06:50:49.384497 VALID_LAT_VALUE = 1
2229 06:50:49.387868 ==============================================================
2230 06:50:49.391432 Enter into Gating configuration >>>>
2231 06:50:49.394195 Exit from Gating configuration <<<<
2232 06:50:49.397654 Enter into DVFS_PRE_config >>>>>
2233 06:50:49.408154 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2234 06:50:49.411198 Exit from DVFS_PRE_config <<<<<
2235 06:50:49.414850 Enter into PICG configuration >>>>
2236 06:50:49.417835 Exit from PICG configuration <<<<
2237 06:50:49.420896 [RX_INPUT] configuration >>>>>
2238 06:50:49.424267 [RX_INPUT] configuration <<<<<
2239 06:50:49.431328 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2240 06:50:49.434479 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2241 06:50:49.441495 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 06:50:49.448173 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 06:50:49.454353 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 06:50:49.461452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 06:50:49.464227 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2246 06:50:49.467783 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2247 06:50:49.471308 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2248 06:50:49.474727 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2249 06:50:49.480911 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2250 06:50:49.484442 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2251 06:50:49.487878 ===================================
2252 06:50:49.491312 LPDDR4 DRAM CONFIGURATION
2253 06:50:49.494522 ===================================
2254 06:50:49.494605 EX_ROW_EN[0] = 0x0
2255 06:50:49.497912 EX_ROW_EN[1] = 0x0
2256 06:50:49.497991 LP4Y_EN = 0x0
2257 06:50:49.500799 WORK_FSP = 0x0
2258 06:50:49.500876 WL = 0x4
2259 06:50:49.504317 RL = 0x4
2260 06:50:49.504393 BL = 0x2
2261 06:50:49.507816 RPST = 0x0
2262 06:50:49.507901 RD_PRE = 0x0
2263 06:50:49.511321 WR_PRE = 0x1
2264 06:50:49.511407 WR_PST = 0x0
2265 06:50:49.514771 DBI_WR = 0x0
2266 06:50:49.518077 DBI_RD = 0x0
2267 06:50:49.518159 OTF = 0x1
2268 06:50:49.521621 ===================================
2269 06:50:49.524802 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2270 06:50:49.527594 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2271 06:50:49.534574 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2272 06:50:49.537796 ===================================
2273 06:50:49.541201 LPDDR4 DRAM CONFIGURATION
2274 06:50:49.541332 ===================================
2275 06:50:49.544329 EX_ROW_EN[0] = 0x10
2276 06:50:49.547801 EX_ROW_EN[1] = 0x0
2277 06:50:49.547880 LP4Y_EN = 0x0
2278 06:50:49.551309 WORK_FSP = 0x0
2279 06:50:49.551390 WL = 0x4
2280 06:50:49.554576 RL = 0x4
2281 06:50:49.554660 BL = 0x2
2282 06:50:49.558104 RPST = 0x0
2283 06:50:49.558186 RD_PRE = 0x0
2284 06:50:49.561441 WR_PRE = 0x1
2285 06:50:49.561522 WR_PST = 0x0
2286 06:50:49.564706 DBI_WR = 0x0
2287 06:50:49.564805 DBI_RD = 0x0
2288 06:50:49.567835 OTF = 0x1
2289 06:50:49.571239 ===================================
2290 06:50:49.577698 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2291 06:50:49.577782 ==
2292 06:50:49.581198 Dram Type= 6, Freq= 0, CH_0, rank 0
2293 06:50:49.584524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2294 06:50:49.584606 ==
2295 06:50:49.587746 [Duty_Offset_Calibration]
2296 06:50:49.587824 B0:2 B1:1 CA:1
2297 06:50:49.587888
2298 06:50:49.591208 [DutyScan_Calibration_Flow] k_type=0
2299 06:50:49.601976
2300 06:50:49.602058 ==CLK 0==
2301 06:50:49.605115 Final CLK duty delay cell = 0
2302 06:50:49.608009 [0] MAX Duty = 5218%(X100), DQS PI = 24
2303 06:50:49.611481 [0] MIN Duty = 4844%(X100), DQS PI = 48
2304 06:50:49.611567 [0] AVG Duty = 5031%(X100)
2305 06:50:49.614905
2306 06:50:49.617851 CH0 CLK Duty spec in!! Max-Min= 374%
2307 06:50:49.621299 [DutyScan_Calibration_Flow] ====Done====
2308 06:50:49.621376
2309 06:50:49.624607 [DutyScan_Calibration_Flow] k_type=1
2310 06:50:49.640147
2311 06:50:49.640244 ==DQS 0 ==
2312 06:50:49.643547 Final DQS duty delay cell = -4
2313 06:50:49.647019 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2314 06:50:49.649926 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2315 06:50:49.653207 [-4] AVG Duty = 4937%(X100)
2316 06:50:49.653286
2317 06:50:49.653351 ==DQS 1 ==
2318 06:50:49.656818 Final DQS duty delay cell = 0
2319 06:50:49.660159 [0] MAX Duty = 5156%(X100), DQS PI = 0
2320 06:50:49.663728 [0] MIN Duty = 5031%(X100), DQS PI = 32
2321 06:50:49.667197 [0] AVG Duty = 5093%(X100)
2322 06:50:49.667275
2323 06:50:49.670649 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2324 06:50:49.670728
2325 06:50:49.673390 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2326 06:50:49.677168 [DutyScan_Calibration_Flow] ====Done====
2327 06:50:49.677245
2328 06:50:49.680290 [DutyScan_Calibration_Flow] k_type=3
2329 06:50:49.697191
2330 06:50:49.697275 ==DQM 0 ==
2331 06:50:49.700090 Final DQM duty delay cell = 0
2332 06:50:49.704052 [0] MAX Duty = 5156%(X100), DQS PI = 28
2333 06:50:49.707312 [0] MIN Duty = 4938%(X100), DQS PI = 0
2334 06:50:49.707397 [0] AVG Duty = 5047%(X100)
2335 06:50:49.710648
2336 06:50:49.710733 ==DQM 1 ==
2337 06:50:49.713410 Final DQM duty delay cell = 0
2338 06:50:49.716657 [0] MAX Duty = 5093%(X100), DQS PI = 0
2339 06:50:49.720230 [0] MIN Duty = 5031%(X100), DQS PI = 16
2340 06:50:49.720355 [0] AVG Duty = 5062%(X100)
2341 06:50:49.723789
2342 06:50:49.727201 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2343 06:50:49.727306
2344 06:50:49.730099 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2345 06:50:49.733465 [DutyScan_Calibration_Flow] ====Done====
2346 06:50:49.733552
2347 06:50:49.736832 [DutyScan_Calibration_Flow] k_type=2
2348 06:50:49.753315
2349 06:50:49.753435 ==DQ 0 ==
2350 06:50:49.756764 Final DQ duty delay cell = 0
2351 06:50:49.760173 [0] MAX Duty = 5031%(X100), DQS PI = 24
2352 06:50:49.763567 [0] MIN Duty = 4906%(X100), DQS PI = 0
2353 06:50:49.763651 [0] AVG Duty = 4968%(X100)
2354 06:50:49.763739
2355 06:50:49.767011 ==DQ 1 ==
2356 06:50:49.769820 Final DQ duty delay cell = 0
2357 06:50:49.773392 [0] MAX Duty = 5093%(X100), DQS PI = 24
2358 06:50:49.776924 [0] MIN Duty = 4938%(X100), DQS PI = 36
2359 06:50:49.777007 [0] AVG Duty = 5015%(X100)
2360 06:50:49.777073
2361 06:50:49.780255 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2362 06:50:49.780354
2363 06:50:49.783694 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2364 06:50:49.789995 [DutyScan_Calibration_Flow] ====Done====
2365 06:50:49.790100 ==
2366 06:50:49.793588 Dram Type= 6, Freq= 0, CH_1, rank 0
2367 06:50:49.796986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 06:50:49.797064 ==
2369 06:50:49.800440 [Duty_Offset_Calibration]
2370 06:50:49.800544 B0:1 B1:0 CA:0
2371 06:50:49.800637
2372 06:50:49.803814 [DutyScan_Calibration_Flow] k_type=0
2373 06:50:49.812348
2374 06:50:49.812452 ==CLK 0==
2375 06:50:49.815923 Final CLK duty delay cell = -4
2376 06:50:49.819104 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2377 06:50:49.822718 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2378 06:50:49.825579 [-4] AVG Duty = 4953%(X100)
2379 06:50:49.825686
2380 06:50:49.829073 CH1 CLK Duty spec in!! Max-Min= 93%
2381 06:50:49.832607 [DutyScan_Calibration_Flow] ====Done====
2382 06:50:49.832689
2383 06:50:49.835417 [DutyScan_Calibration_Flow] k_type=1
2384 06:50:49.852005
2385 06:50:49.852123 ==DQS 0 ==
2386 06:50:49.855396 Final DQS duty delay cell = 0
2387 06:50:49.858796 [0] MAX Duty = 5094%(X100), DQS PI = 24
2388 06:50:49.862395 [0] MIN Duty = 4875%(X100), DQS PI = 0
2389 06:50:49.862501 [0] AVG Duty = 4984%(X100)
2390 06:50:49.862597
2391 06:50:49.865852 ==DQS 1 ==
2392 06:50:49.869116 Final DQS duty delay cell = 0
2393 06:50:49.872739 [0] MAX Duty = 5187%(X100), DQS PI = 18
2394 06:50:49.875555 [0] MIN Duty = 4969%(X100), DQS PI = 8
2395 06:50:49.875657 [0] AVG Duty = 5078%(X100)
2396 06:50:49.875753
2397 06:50:49.879161 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2398 06:50:49.882736
2399 06:50:49.885531 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2400 06:50:49.889047 [DutyScan_Calibration_Flow] ====Done====
2401 06:50:49.889150
2402 06:50:49.892566 [DutyScan_Calibration_Flow] k_type=3
2403 06:50:49.908909
2404 06:50:49.909016 ==DQM 0 ==
2405 06:50:49.911783 Final DQM duty delay cell = 0
2406 06:50:49.915358 [0] MAX Duty = 5187%(X100), DQS PI = 8
2407 06:50:49.918786 [0] MIN Duty = 5031%(X100), DQS PI = 0
2408 06:50:49.918889 [0] AVG Duty = 5109%(X100)
2409 06:50:49.918988
2410 06:50:49.922203 ==DQM 1 ==
2411 06:50:49.925624 Final DQM duty delay cell = 0
2412 06:50:49.928537 [0] MAX Duty = 5031%(X100), DQS PI = 16
2413 06:50:49.931842 [0] MIN Duty = 4907%(X100), DQS PI = 36
2414 06:50:49.931950 [0] AVG Duty = 4969%(X100)
2415 06:50:49.932042
2416 06:50:49.939189 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2417 06:50:49.939276
2418 06:50:49.942407 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2419 06:50:49.945686 [DutyScan_Calibration_Flow] ====Done====
2420 06:50:49.945777
2421 06:50:49.948803 [DutyScan_Calibration_Flow] k_type=2
2422 06:50:49.964684
2423 06:50:49.964809 ==DQ 0 ==
2424 06:50:49.967821 Final DQ duty delay cell = -4
2425 06:50:49.971216 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2426 06:50:49.974716 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2427 06:50:49.974821 [-4] AVG Duty = 5000%(X100)
2428 06:50:49.977682
2429 06:50:49.977768 ==DQ 1 ==
2430 06:50:49.981145 Final DQ duty delay cell = 0
2431 06:50:49.984871 [0] MAX Duty = 5125%(X100), DQS PI = 20
2432 06:50:49.988123 [0] MIN Duty = 4969%(X100), DQS PI = 10
2433 06:50:49.988237 [0] AVG Duty = 5047%(X100)
2434 06:50:49.988333
2435 06:50:49.991546 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2436 06:50:49.991650
2437 06:50:49.997791 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2438 06:50:50.001378 [DutyScan_Calibration_Flow] ====Done====
2439 06:50:50.004897 nWR fixed to 30
2440 06:50:50.004992 [ModeRegInit_LP4] CH0 RK0
2441 06:50:50.007765 [ModeRegInit_LP4] CH0 RK1
2442 06:50:50.011294 [ModeRegInit_LP4] CH1 RK0
2443 06:50:50.011398 [ModeRegInit_LP4] CH1 RK1
2444 06:50:50.014755 match AC timing 7
2445 06:50:50.018326 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2446 06:50:50.021081 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2447 06:50:50.028192 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2448 06:50:50.031466 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2449 06:50:50.037955 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2450 06:50:50.038071 ==
2451 06:50:50.041438 Dram Type= 6, Freq= 0, CH_0, rank 0
2452 06:50:50.044738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2453 06:50:50.044817 ==
2454 06:50:50.051690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2455 06:50:50.055094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2456 06:50:50.064582 [CA 0] Center 39 (8~70) winsize 63
2457 06:50:50.068037 [CA 1] Center 39 (8~70) winsize 63
2458 06:50:50.071614 [CA 2] Center 35 (4~66) winsize 63
2459 06:50:50.074400 [CA 3] Center 34 (4~65) winsize 62
2460 06:50:50.077828 [CA 4] Center 33 (3~64) winsize 62
2461 06:50:50.081210 [CA 5] Center 32 (3~62) winsize 60
2462 06:50:50.081308
2463 06:50:50.084677 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2464 06:50:50.084755
2465 06:50:50.087938 [CATrainingPosCal] consider 1 rank data
2466 06:50:50.091169 u2DelayCellTimex100 = 270/100 ps
2467 06:50:50.094906 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2468 06:50:50.098186 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2469 06:50:50.105007 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2470 06:50:50.108202 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2471 06:50:50.111487 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2472 06:50:50.114375 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2473 06:50:50.114462
2474 06:50:50.117893 CA PerBit enable=1, Macro0, CA PI delay=32
2475 06:50:50.117966
2476 06:50:50.121439 [CBTSetCACLKResult] CA Dly = 32
2477 06:50:50.121514 CS Dly: 6 (0~37)
2478 06:50:50.121581 ==
2479 06:50:50.125040 Dram Type= 6, Freq= 0, CH_0, rank 1
2480 06:50:50.131262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 06:50:50.131366 ==
2482 06:50:50.134867 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 06:50:50.141615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2484 06:50:50.150511 [CA 0] Center 38 (8~69) winsize 62
2485 06:50:50.153936 [CA 1] Center 38 (8~69) winsize 62
2486 06:50:50.157476 [CA 2] Center 35 (4~66) winsize 63
2487 06:50:50.160214 [CA 3] Center 34 (4~65) winsize 62
2488 06:50:50.163805 [CA 4] Center 33 (3~64) winsize 62
2489 06:50:50.167311 [CA 5] Center 32 (3~62) winsize 60
2490 06:50:50.167398
2491 06:50:50.170103 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2492 06:50:50.170179
2493 06:50:50.173439 [CATrainingPosCal] consider 2 rank data
2494 06:50:50.176754 u2DelayCellTimex100 = 270/100 ps
2495 06:50:50.180185 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2496 06:50:50.183777 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2497 06:50:50.190514 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2498 06:50:50.194206 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2499 06:50:50.196876 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2500 06:50:50.200307 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2501 06:50:50.200410
2502 06:50:50.203825 CA PerBit enable=1, Macro0, CA PI delay=32
2503 06:50:50.203924
2504 06:50:50.207403 [CBTSetCACLKResult] CA Dly = 32
2505 06:50:50.207503 CS Dly: 6 (0~38)
2506 06:50:50.207594
2507 06:50:50.210208 ----->DramcWriteLeveling(PI) begin...
2508 06:50:50.213662 ==
2509 06:50:50.213736 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 06:50:50.220235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 06:50:50.220347 ==
2512 06:50:50.224121 Write leveling (Byte 0): 33 => 33
2513 06:50:50.227049 Write leveling (Byte 1): 29 => 29
2514 06:50:50.230662 DramcWriteLeveling(PI) end<-----
2515 06:50:50.230763
2516 06:50:50.230854 ==
2517 06:50:50.233646 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 06:50:50.237278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 06:50:50.237357 ==
2520 06:50:50.240373 [Gating] SW mode calibration
2521 06:50:50.247180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2522 06:50:50.250500 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2523 06:50:50.257384 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2524 06:50:50.260695 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2525 06:50:50.264128 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 06:50:50.270525 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 06:50:50.273989 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 06:50:50.276800 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 06:50:50.284224 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2530 06:50:50.287326 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2531 06:50:50.290665 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2532 06:50:50.296935 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 06:50:50.300508 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 06:50:50.303903 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 06:50:50.310844 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 06:50:50.313693 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 06:50:50.317203 1 0 24 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
2538 06:50:50.320701 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2539 06:50:50.327566 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2540 06:50:50.331102 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 06:50:50.333924 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 06:50:50.340415 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 06:50:50.344189 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 06:50:50.347188 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 06:50:50.354183 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 06:50:50.357187 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2547 06:50:50.360828 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2548 06:50:50.367656 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 06:50:50.371067 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 06:50:50.373873 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 06:50:50.380838 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 06:50:50.384401 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 06:50:50.387261 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 06:50:50.390851 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 06:50:50.397469 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 06:50:50.400775 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 06:50:50.404151 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 06:50:50.411196 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 06:50:50.414127 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 06:50:50.417640 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 06:50:50.424575 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2562 06:50:50.427375 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2563 06:50:50.430901 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 06:50:50.434295 Total UI for P1: 0, mck2ui 16
2565 06:50:50.437651 best dqsien dly found for B0: ( 1, 3, 26)
2566 06:50:50.441215 Total UI for P1: 0, mck2ui 16
2567 06:50:50.444095 best dqsien dly found for B1: ( 1, 3, 28)
2568 06:50:50.447464 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2569 06:50:50.451017 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2570 06:50:50.451132
2571 06:50:50.454356 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2572 06:50:50.460704 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2573 06:50:50.460786 [Gating] SW calibration Done
2574 06:50:50.464162 ==
2575 06:50:50.464292 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 06:50:50.470926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 06:50:50.471035 ==
2578 06:50:50.471158 RX Vref Scan: 0
2579 06:50:50.471254
2580 06:50:50.474492 RX Vref 0 -> 0, step: 1
2581 06:50:50.474621
2582 06:50:50.477891 RX Delay -40 -> 252, step: 8
2583 06:50:50.481386 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2584 06:50:50.484745 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2585 06:50:50.487904 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2586 06:50:50.491158 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2587 06:50:50.498222 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2588 06:50:50.501172 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2589 06:50:50.504712 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2590 06:50:50.507794 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2591 06:50:50.511533 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2592 06:50:50.517800 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2593 06:50:50.521424 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2594 06:50:50.524550 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2595 06:50:50.527749 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2596 06:50:50.531241 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2597 06:50:50.538238 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2598 06:50:50.541738 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2599 06:50:50.541844 ==
2600 06:50:50.544494 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 06:50:50.548081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 06:50:50.548187 ==
2603 06:50:50.551590 DQS Delay:
2604 06:50:50.551664 DQS0 = 0, DQS1 = 0
2605 06:50:50.551745 DQM Delay:
2606 06:50:50.554452 DQM0 = 121, DQM1 = 113
2607 06:50:50.554527 DQ Delay:
2608 06:50:50.558417 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2609 06:50:50.561675 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2610 06:50:50.564474 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2611 06:50:50.571275 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2612 06:50:50.571360
2613 06:50:50.571426
2614 06:50:50.571487 ==
2615 06:50:50.574639 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 06:50:50.578072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 06:50:50.578163 ==
2618 06:50:50.578230
2619 06:50:50.578292
2620 06:50:50.581645 TX Vref Scan disable
2621 06:50:50.581745 == TX Byte 0 ==
2622 06:50:50.588000 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2623 06:50:50.591396 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2624 06:50:50.591499 == TX Byte 1 ==
2625 06:50:50.598262 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2626 06:50:50.601841 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2627 06:50:50.601918 ==
2628 06:50:50.604681 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 06:50:50.608109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 06:50:50.608211 ==
2631 06:50:50.620930 TX Vref=22, minBit 1, minWin=25, winSum=404
2632 06:50:50.624280 TX Vref=24, minBit 4, minWin=25, winSum=414
2633 06:50:50.627408 TX Vref=26, minBit 3, minWin=25, winSum=419
2634 06:50:50.630570 TX Vref=28, minBit 13, minWin=25, winSum=422
2635 06:50:50.634198 TX Vref=30, minBit 0, minWin=26, winSum=423
2636 06:50:50.640760 TX Vref=32, minBit 10, minWin=25, winSum=422
2637 06:50:50.644453 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
2638 06:50:50.644540
2639 06:50:50.647597 Final TX Range 1 Vref 30
2640 06:50:50.647705
2641 06:50:50.647808 ==
2642 06:50:50.650790 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 06:50:50.654168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 06:50:50.654252 ==
2645 06:50:50.657738
2646 06:50:50.657817
2647 06:50:50.657905 TX Vref Scan disable
2648 06:50:50.661179 == TX Byte 0 ==
2649 06:50:50.663867 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2650 06:50:50.667827 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2651 06:50:50.670660 == TX Byte 1 ==
2652 06:50:50.674194 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2653 06:50:50.677641 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2654 06:50:50.677742
2655 06:50:50.681125 [DATLAT]
2656 06:50:50.681203 Freq=1200, CH0 RK0
2657 06:50:50.681269
2658 06:50:50.684517 DATLAT Default: 0xd
2659 06:50:50.684590 0, 0xFFFF, sum = 0
2660 06:50:50.687394 1, 0xFFFF, sum = 0
2661 06:50:50.687472 2, 0xFFFF, sum = 0
2662 06:50:50.690901 3, 0xFFFF, sum = 0
2663 06:50:50.691002 4, 0xFFFF, sum = 0
2664 06:50:50.694361 5, 0xFFFF, sum = 0
2665 06:50:50.694463 6, 0xFFFF, sum = 0
2666 06:50:50.697897 7, 0xFFFF, sum = 0
2667 06:50:50.697997 8, 0xFFFF, sum = 0
2668 06:50:50.701308 9, 0xFFFF, sum = 0
2669 06:50:50.704777 10, 0xFFFF, sum = 0
2670 06:50:50.704858 11, 0xFFFF, sum = 0
2671 06:50:50.708175 12, 0x0, sum = 1
2672 06:50:50.708263 13, 0x0, sum = 2
2673 06:50:50.708346 14, 0x0, sum = 3
2674 06:50:50.710920 15, 0x0, sum = 4
2675 06:50:50.710992 best_step = 13
2676 06:50:50.711073
2677 06:50:50.711136 ==
2678 06:50:50.714410 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 06:50:50.721331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 06:50:50.721412 ==
2681 06:50:50.721479 RX Vref Scan: 1
2682 06:50:50.721548
2683 06:50:50.724786 Set Vref Range= 32 -> 127
2684 06:50:50.724888
2685 06:50:50.727549 RX Vref 32 -> 127, step: 1
2686 06:50:50.727625
2687 06:50:50.730925 RX Delay -13 -> 252, step: 4
2688 06:50:50.731029
2689 06:50:50.734412 Set Vref, RX VrefLevel [Byte0]: 32
2690 06:50:50.737896 [Byte1]: 32
2691 06:50:50.737997
2692 06:50:50.741252 Set Vref, RX VrefLevel [Byte0]: 33
2693 06:50:50.744737 [Byte1]: 33
2694 06:50:50.744845
2695 06:50:50.748066 Set Vref, RX VrefLevel [Byte0]: 34
2696 06:50:50.751188 [Byte1]: 34
2697 06:50:50.754990
2698 06:50:50.755070 Set Vref, RX VrefLevel [Byte0]: 35
2699 06:50:50.758675 [Byte1]: 35
2700 06:50:50.762981
2701 06:50:50.763087 Set Vref, RX VrefLevel [Byte0]: 36
2702 06:50:50.766165 [Byte1]: 36
2703 06:50:50.770890
2704 06:50:50.770993 Set Vref, RX VrefLevel [Byte0]: 37
2705 06:50:50.773965 [Byte1]: 37
2706 06:50:50.790632
2707 06:50:50.790808 Set Vref, RX VrefLevel [Byte0]: 38
2708 06:50:50.790914 [Byte1]: 38
2709 06:50:50.791010
2710 06:50:50.791112 Set Vref, RX VrefLevel [Byte0]: 39
2711 06:50:50.791207 [Byte1]: 39
2712 06:50:50.794748
2713 06:50:50.794857 Set Vref, RX VrefLevel [Byte0]: 40
2714 06:50:50.797536 [Byte1]: 40
2715 06:50:50.802597
2716 06:50:50.802702 Set Vref, RX VrefLevel [Byte0]: 41
2717 06:50:50.806048 [Byte1]: 41
2718 06:50:50.810240
2719 06:50:50.810361 Set Vref, RX VrefLevel [Byte0]: 42
2720 06:50:50.813791 [Byte1]: 42
2721 06:50:50.818096
2722 06:50:50.818198 Set Vref, RX VrefLevel [Byte0]: 43
2723 06:50:50.821488 [Byte1]: 43
2724 06:50:50.826297
2725 06:50:50.826417 Set Vref, RX VrefLevel [Byte0]: 44
2726 06:50:50.829171 [Byte1]: 44
2727 06:50:50.834103
2728 06:50:50.834213 Set Vref, RX VrefLevel [Byte0]: 45
2729 06:50:50.836920 [Byte1]: 45
2730 06:50:50.841928
2731 06:50:50.842036 Set Vref, RX VrefLevel [Byte0]: 46
2732 06:50:50.844881 [Byte1]: 46
2733 06:50:50.849686
2734 06:50:50.849789 Set Vref, RX VrefLevel [Byte0]: 47
2735 06:50:50.853198 [Byte1]: 47
2736 06:50:50.857342
2737 06:50:50.857443 Set Vref, RX VrefLevel [Byte0]: 48
2738 06:50:50.860791 [Byte1]: 48
2739 06:50:50.865891
2740 06:50:50.865995 Set Vref, RX VrefLevel [Byte0]: 49
2741 06:50:50.868801 [Byte1]: 49
2742 06:50:50.873243
2743 06:50:50.873342 Set Vref, RX VrefLevel [Byte0]: 50
2744 06:50:50.876497 [Byte1]: 50
2745 06:50:50.881272
2746 06:50:50.881371 Set Vref, RX VrefLevel [Byte0]: 51
2747 06:50:50.884652 [Byte1]: 51
2748 06:50:50.889270
2749 06:50:50.889377 Set Vref, RX VrefLevel [Byte0]: 52
2750 06:50:50.892397 [Byte1]: 52
2751 06:50:50.896863
2752 06:50:50.896965 Set Vref, RX VrefLevel [Byte0]: 53
2753 06:50:50.900589 [Byte1]: 53
2754 06:50:50.904700
2755 06:50:50.904816 Set Vref, RX VrefLevel [Byte0]: 54
2756 06:50:50.908199 [Byte1]: 54
2757 06:50:50.913087
2758 06:50:50.913171 Set Vref, RX VrefLevel [Byte0]: 55
2759 06:50:50.915900 [Byte1]: 55
2760 06:50:50.920730
2761 06:50:50.920821 Set Vref, RX VrefLevel [Byte0]: 56
2762 06:50:50.924188 [Byte1]: 56
2763 06:50:50.928835
2764 06:50:50.928919 Set Vref, RX VrefLevel [Byte0]: 57
2765 06:50:50.932324 [Byte1]: 57
2766 06:50:50.936473
2767 06:50:50.936557 Set Vref, RX VrefLevel [Byte0]: 58
2768 06:50:50.939989 [Byte1]: 58
2769 06:50:50.944892
2770 06:50:50.944978 Set Vref, RX VrefLevel [Byte0]: 59
2771 06:50:50.947681 [Byte1]: 59
2772 06:50:50.952593
2773 06:50:50.952696 Set Vref, RX VrefLevel [Byte0]: 60
2774 06:50:50.955372 [Byte1]: 60
2775 06:50:50.960184
2776 06:50:50.960308 Set Vref, RX VrefLevel [Byte0]: 61
2777 06:50:50.963749 [Byte1]: 61
2778 06:50:50.967821
2779 06:50:50.967920 Set Vref, RX VrefLevel [Byte0]: 62
2780 06:50:50.971245 [Byte1]: 62
2781 06:50:50.976070
2782 06:50:50.976171 Set Vref, RX VrefLevel [Byte0]: 63
2783 06:50:50.979382 [Byte1]: 63
2784 06:50:50.983961
2785 06:50:50.984046 Set Vref, RX VrefLevel [Byte0]: 64
2786 06:50:50.987389 [Byte1]: 64
2787 06:50:50.991588
2788 06:50:50.991672 Set Vref, RX VrefLevel [Byte0]: 65
2789 06:50:50.995094 [Byte1]: 65
2790 06:50:50.999907
2791 06:50:50.999990 Set Vref, RX VrefLevel [Byte0]: 66
2792 06:50:51.002692 [Byte1]: 66
2793 06:50:51.007497
2794 06:50:51.007584 Set Vref, RX VrefLevel [Byte0]: 67
2795 06:50:51.010695 [Byte1]: 67
2796 06:50:51.015526
2797 06:50:51.015610 Set Vref, RX VrefLevel [Byte0]: 68
2798 06:50:51.018854 [Byte1]: 68
2799 06:50:51.023269
2800 06:50:51.023356 Set Vref, RX VrefLevel [Byte0]: 69
2801 06:50:51.026685 [Byte1]: 69
2802 06:50:51.030990
2803 06:50:51.031075 Set Vref, RX VrefLevel [Byte0]: 70
2804 06:50:51.034222 [Byte1]: 70
2805 06:50:51.039069
2806 06:50:51.039154 Final RX Vref Byte 0 = 55 to rank0
2807 06:50:51.042594 Final RX Vref Byte 1 = 53 to rank0
2808 06:50:51.046262 Final RX Vref Byte 0 = 55 to rank1
2809 06:50:51.049155 Final RX Vref Byte 1 = 53 to rank1==
2810 06:50:51.052729 Dram Type= 6, Freq= 0, CH_0, rank 0
2811 06:50:51.056197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2812 06:50:51.059063 ==
2813 06:50:51.059145 DQS Delay:
2814 06:50:51.059211 DQS0 = 0, DQS1 = 0
2815 06:50:51.062534 DQM Delay:
2816 06:50:51.062616 DQM0 = 120, DQM1 = 112
2817 06:50:51.065984 DQ Delay:
2818 06:50:51.069379 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2819 06:50:51.072835 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2820 06:50:51.076229 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2821 06:50:51.079507 DQ12 =120, DQ13 =116, DQ14 =124, DQ15 =122
2822 06:50:51.079589
2823 06:50:51.079654
2824 06:50:51.085778 [DQSOSCAuto] RK0, (LSB)MR18= 0x1710, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2825 06:50:51.089337 CH0 RK0: MR19=404, MR18=1710
2826 06:50:51.096144 CH0_RK0: MR19=0x404, MR18=0x1710, DQSOSC=401, MR23=63, INC=40, DEC=27
2827 06:50:51.096232
2828 06:50:51.099015 ----->DramcWriteLeveling(PI) begin...
2829 06:50:51.099119 ==
2830 06:50:51.102600 Dram Type= 6, Freq= 0, CH_0, rank 1
2831 06:50:51.106004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2832 06:50:51.109529 ==
2833 06:50:51.109642 Write leveling (Byte 0): 33 => 33
2834 06:50:51.112331 Write leveling (Byte 1): 29 => 29
2835 06:50:51.115706 DramcWriteLeveling(PI) end<-----
2836 06:50:51.115805
2837 06:50:51.115874 ==
2838 06:50:51.119141 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 06:50:51.125841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 06:50:51.125924 ==
2841 06:50:51.126005 [Gating] SW mode calibration
2842 06:50:51.136064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2843 06:50:51.139289 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2844 06:50:51.142455 0 15 0 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
2845 06:50:51.149293 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 06:50:51.152397 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 06:50:51.155702 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 06:50:51.162317 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 06:50:51.165749 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 06:50:51.169337 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 06:50:51.176205 0 15 28 | B1->B0 | 2c2c 2b2b | 0 1 | (0 1) (1 0)
2852 06:50:51.179570 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 06:50:51.182301 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 06:50:51.188935 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 06:50:51.192467 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 06:50:51.195875 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 06:50:51.202726 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 06:50:51.206285 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2859 06:50:51.209718 1 0 28 | B1->B0 | 4242 3f3f | 0 0 | (0 0) (0 0)
2860 06:50:51.215758 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2861 06:50:51.219299 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 06:50:51.222674 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 06:50:51.226116 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 06:50:51.232960 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 06:50:51.236430 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 06:50:51.239260 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 06:50:51.246246 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2868 06:50:51.249523 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 06:50:51.252821 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 06:50:51.259425 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 06:50:51.262910 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 06:50:51.265958 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 06:50:51.273098 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 06:50:51.276181 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 06:50:51.279674 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 06:50:51.286582 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 06:50:51.289316 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 06:50:51.293307 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 06:50:51.295907 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 06:50:51.302846 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 06:50:51.306299 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 06:50:51.309751 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 06:50:51.316078 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2884 06:50:51.319489 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 06:50:51.322913 Total UI for P1: 0, mck2ui 16
2886 06:50:51.326269 best dqsien dly found for B0: ( 1, 3, 28)
2887 06:50:51.329683 Total UI for P1: 0, mck2ui 16
2888 06:50:51.333341 best dqsien dly found for B1: ( 1, 3, 28)
2889 06:50:51.336062 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2890 06:50:51.339365 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2891 06:50:51.339449
2892 06:50:51.342858 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2893 06:50:51.346380 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2894 06:50:51.349856 [Gating] SW calibration Done
2895 06:50:51.349940 ==
2896 06:50:51.352636 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 06:50:51.356233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 06:50:51.359683 ==
2899 06:50:51.359766 RX Vref Scan: 0
2900 06:50:51.359833
2901 06:50:51.363288 RX Vref 0 -> 0, step: 1
2902 06:50:51.363374
2903 06:50:51.366054 RX Delay -40 -> 252, step: 8
2904 06:50:51.369305 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2905 06:50:51.372617 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2906 06:50:51.375886 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2907 06:50:51.379419 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2908 06:50:51.385985 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2909 06:50:51.389772 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2910 06:50:51.393150 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2911 06:50:51.396537 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2912 06:50:51.399304 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2913 06:50:51.402583 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2914 06:50:51.409712 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2915 06:50:51.413126 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2916 06:50:51.416530 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2917 06:50:51.419909 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2918 06:50:51.426182 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2919 06:50:51.429545 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2920 06:50:51.429622 ==
2921 06:50:51.432867 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 06:50:51.436433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 06:50:51.436548 ==
2924 06:50:51.436631 DQS Delay:
2925 06:50:51.439808 DQS0 = 0, DQS1 = 0
2926 06:50:51.439921 DQM Delay:
2927 06:50:51.443183 DQM0 = 121, DQM1 = 114
2928 06:50:51.443267 DQ Delay:
2929 06:50:51.446735 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2930 06:50:51.449594 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2931 06:50:51.453187 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
2932 06:50:51.456562 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2933 06:50:51.459835
2934 06:50:51.459935
2935 06:50:51.460001 ==
2936 06:50:51.463293 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 06:50:51.466804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 06:50:51.466887 ==
2939 06:50:51.466953
2940 06:50:51.467014
2941 06:50:51.469682 TX Vref Scan disable
2942 06:50:51.469763 == TX Byte 0 ==
2943 06:50:51.476540 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2944 06:50:51.479944 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2945 06:50:51.480026 == TX Byte 1 ==
2946 06:50:51.486891 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2947 06:50:51.489687 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2948 06:50:51.489770 ==
2949 06:50:51.493544 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 06:50:51.496503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 06:50:51.496586 ==
2952 06:50:51.508825 TX Vref=22, minBit 1, minWin=25, winSum=409
2953 06:50:51.512572 TX Vref=24, minBit 3, minWin=25, winSum=417
2954 06:50:51.515854 TX Vref=26, minBit 3, minWin=25, winSum=422
2955 06:50:51.518970 TX Vref=28, minBit 12, minWin=25, winSum=420
2956 06:50:51.522085 TX Vref=30, minBit 12, minWin=25, winSum=427
2957 06:50:51.529002 TX Vref=32, minBit 12, minWin=25, winSum=421
2958 06:50:51.532271 [TxChooseVref] Worse bit 12, Min win 25, Win sum 427, Final Vref 30
2959 06:50:51.532380
2960 06:50:51.536231 Final TX Range 1 Vref 30
2961 06:50:51.536382
2962 06:50:51.536476 ==
2963 06:50:51.538956 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 06:50:51.542422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 06:50:51.542543 ==
2966 06:50:51.545884
2967 06:50:51.545991
2968 06:50:51.546115 TX Vref Scan disable
2969 06:50:51.549447 == TX Byte 0 ==
2970 06:50:51.552194 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2971 06:50:51.555752 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2972 06:50:51.559294 == TX Byte 1 ==
2973 06:50:51.562266 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2974 06:50:51.569320 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2975 06:50:51.569423
2976 06:50:51.569514 [DATLAT]
2977 06:50:51.569607 Freq=1200, CH0 RK1
2978 06:50:51.569694
2979 06:50:51.572093 DATLAT Default: 0xd
2980 06:50:51.572193 0, 0xFFFF, sum = 0
2981 06:50:51.575710 1, 0xFFFF, sum = 0
2982 06:50:51.575814 2, 0xFFFF, sum = 0
2983 06:50:51.579286 3, 0xFFFF, sum = 0
2984 06:50:51.582181 4, 0xFFFF, sum = 0
2985 06:50:51.582254 5, 0xFFFF, sum = 0
2986 06:50:51.586161 6, 0xFFFF, sum = 0
2987 06:50:51.586266 7, 0xFFFF, sum = 0
2988 06:50:51.589427 8, 0xFFFF, sum = 0
2989 06:50:51.589530 9, 0xFFFF, sum = 0
2990 06:50:51.592667 10, 0xFFFF, sum = 0
2991 06:50:51.592776 11, 0xFFFF, sum = 0
2992 06:50:51.596135 12, 0x0, sum = 1
2993 06:50:51.596240 13, 0x0, sum = 2
2994 06:50:51.598991 14, 0x0, sum = 3
2995 06:50:51.599107 15, 0x0, sum = 4
2996 06:50:51.599201 best_step = 13
2997 06:50:51.602515
2998 06:50:51.602618 ==
2999 06:50:51.605988 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 06:50:51.609321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 06:50:51.609434 ==
3002 06:50:51.609530 RX Vref Scan: 0
3003 06:50:51.609638
3004 06:50:51.612755 RX Vref 0 -> 0, step: 1
3005 06:50:51.612845
3006 06:50:51.615831 RX Delay -13 -> 252, step: 4
3007 06:50:51.619225 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3008 06:50:51.625879 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3009 06:50:51.629268 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3010 06:50:51.632833 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3011 06:50:51.635479 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3012 06:50:51.639308 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3013 06:50:51.642399 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3014 06:50:51.649336 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3015 06:50:51.652531 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3016 06:50:51.655675 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3017 06:50:51.659039 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3018 06:50:51.662556 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3019 06:50:51.669345 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3020 06:50:51.672177 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3021 06:50:51.675673 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3022 06:50:51.679147 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3023 06:50:51.679256 ==
3024 06:50:51.682572 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 06:50:51.689004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 06:50:51.689079 ==
3027 06:50:51.689143 DQS Delay:
3028 06:50:51.692308 DQS0 = 0, DQS1 = 0
3029 06:50:51.692385 DQM Delay:
3030 06:50:51.695726 DQM0 = 121, DQM1 = 111
3031 06:50:51.695827 DQ Delay:
3032 06:50:51.698985 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3033 06:50:51.702279 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3034 06:50:51.705546 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
3035 06:50:51.709169 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =120
3036 06:50:51.709250
3037 06:50:51.709313
3038 06:50:51.718970 [DQSOSCAuto] RK1, (LSB)MR18= 0xdee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3039 06:50:51.719077 CH0 RK1: MR19=403, MR18=DEE
3040 06:50:51.725790 CH0_RK1: MR19=0x403, MR18=0xDEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3041 06:50:51.729138 [RxdqsGatingPostProcess] freq 1200
3042 06:50:51.735909 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3043 06:50:51.739324 best DQS0 dly(2T, 0.5T) = (0, 11)
3044 06:50:51.742894 best DQS1 dly(2T, 0.5T) = (0, 11)
3045 06:50:51.742996 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3046 06:50:51.745712 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3047 06:50:51.748976 best DQS0 dly(2T, 0.5T) = (0, 11)
3048 06:50:51.752885 best DQS1 dly(2T, 0.5T) = (0, 11)
3049 06:50:51.756112 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3050 06:50:51.759314 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3051 06:50:51.762382 Pre-setting of DQS Precalculation
3052 06:50:51.769212 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3053 06:50:51.769324 ==
3054 06:50:51.772997 Dram Type= 6, Freq= 0, CH_1, rank 0
3055 06:50:51.776359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 06:50:51.776464 ==
3057 06:50:51.782618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3058 06:50:51.786221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3059 06:50:51.795377 [CA 0] Center 37 (7~68) winsize 62
3060 06:50:51.798792 [CA 1] Center 37 (7~68) winsize 62
3061 06:50:51.802287 [CA 2] Center 35 (6~65) winsize 60
3062 06:50:51.805597 [CA 3] Center 34 (4~64) winsize 61
3063 06:50:51.808809 [CA 4] Center 34 (4~64) winsize 61
3064 06:50:51.812221 [CA 5] Center 33 (3~63) winsize 61
3065 06:50:51.812331
3066 06:50:51.815541 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3067 06:50:51.815624
3068 06:50:51.818965 [CATrainingPosCal] consider 1 rank data
3069 06:50:51.822468 u2DelayCellTimex100 = 270/100 ps
3070 06:50:51.825913 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3071 06:50:51.829365 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3072 06:50:51.835604 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3073 06:50:51.839019 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3074 06:50:51.842466 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3075 06:50:51.845830 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3076 06:50:51.845954
3077 06:50:51.849312 CA PerBit enable=1, Macro0, CA PI delay=33
3078 06:50:51.849392
3079 06:50:51.852188 [CBTSetCACLKResult] CA Dly = 33
3080 06:50:51.852314 CS Dly: 7 (0~38)
3081 06:50:51.852382 ==
3082 06:50:51.855858 Dram Type= 6, Freq= 0, CH_1, rank 1
3083 06:50:51.862674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 06:50:51.862780 ==
3085 06:50:51.866107 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3086 06:50:51.872149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3087 06:50:51.881586 [CA 0] Center 37 (7~68) winsize 62
3088 06:50:51.884896 [CA 1] Center 37 (7~68) winsize 62
3089 06:50:51.888224 [CA 2] Center 35 (5~65) winsize 61
3090 06:50:51.891690 [CA 3] Center 34 (4~65) winsize 62
3091 06:50:51.894567 [CA 4] Center 34 (4~65) winsize 62
3092 06:50:51.898114 [CA 5] Center 34 (4~64) winsize 61
3093 06:50:51.898193
3094 06:50:51.901670 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3095 06:50:51.901751
3096 06:50:51.904300 [CATrainingPosCal] consider 2 rank data
3097 06:50:51.907832 u2DelayCellTimex100 = 270/100 ps
3098 06:50:51.911348 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3099 06:50:51.914605 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3100 06:50:51.917932 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3101 06:50:51.924560 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3102 06:50:51.928133 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3103 06:50:51.931496 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3104 06:50:51.931588
3105 06:50:51.934800 CA PerBit enable=1, Macro0, CA PI delay=33
3106 06:50:51.934898
3107 06:50:51.938208 [CBTSetCACLKResult] CA Dly = 33
3108 06:50:51.938330 CS Dly: 8 (0~40)
3109 06:50:51.938425
3110 06:50:51.941553 ----->DramcWriteLeveling(PI) begin...
3111 06:50:51.941653 ==
3112 06:50:51.945091 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 06:50:51.951281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 06:50:51.951377 ==
3115 06:50:51.954894 Write leveling (Byte 0): 26 => 26
3116 06:50:51.958478 Write leveling (Byte 1): 30 => 30
3117 06:50:51.958584 DramcWriteLeveling(PI) end<-----
3118 06:50:51.961812
3119 06:50:51.961899 ==
3120 06:50:51.964576 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 06:50:51.967966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 06:50:51.968068 ==
3123 06:50:51.971390 [Gating] SW mode calibration
3124 06:50:51.978249 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3125 06:50:51.981670 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3126 06:50:51.988212 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 06:50:51.991368 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 06:50:51.994522 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 06:50:52.001272 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 06:50:52.004727 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 06:50:52.008193 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 06:50:52.014590 0 15 24 | B1->B0 | 3131 2828 | 0 0 | (0 1) (1 0)
3133 06:50:52.017974 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3134 06:50:52.021369 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 06:50:52.028205 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 06:50:52.031548 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 06:50:52.034391 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 06:50:52.041208 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 06:50:52.044630 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3140 06:50:52.047984 1 0 24 | B1->B0 | 3131 4242 | 0 1 | (1 1) (0 0)
3141 06:50:52.054228 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 06:50:52.057660 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 06:50:52.061207 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 06:50:52.067584 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 06:50:52.071092 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 06:50:52.074653 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 06:50:52.077982 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 06:50:52.084522 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3149 06:50:52.088146 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3150 06:50:52.091514 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 06:50:52.097610 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 06:50:52.101548 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 06:50:52.104665 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 06:50:52.111527 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 06:50:52.115011 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 06:50:52.117778 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 06:50:52.124615 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 06:50:52.128010 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 06:50:52.131346 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 06:50:52.138102 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 06:50:52.141655 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 06:50:52.145056 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 06:50:52.151662 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 06:50:52.154918 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3165 06:50:52.158327 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3166 06:50:52.161166 Total UI for P1: 0, mck2ui 16
3167 06:50:52.164726 best dqsien dly found for B0: ( 1, 3, 24)
3168 06:50:52.168163 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 06:50:52.171637 Total UI for P1: 0, mck2ui 16
3170 06:50:52.175157 best dqsien dly found for B1: ( 1, 3, 26)
3171 06:50:52.177976 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3172 06:50:52.181475 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3173 06:50:52.181549
3174 06:50:52.188226 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3175 06:50:52.191491 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3176 06:50:52.194847 [Gating] SW calibration Done
3177 06:50:52.194938 ==
3178 06:50:52.198308 Dram Type= 6, Freq= 0, CH_1, rank 0
3179 06:50:52.201717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3180 06:50:52.201802 ==
3181 06:50:52.201871 RX Vref Scan: 0
3182 06:50:52.201932
3183 06:50:52.205396 RX Vref 0 -> 0, step: 1
3184 06:50:52.205478
3185 06:50:52.208238 RX Delay -40 -> 252, step: 8
3186 06:50:52.211768 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3187 06:50:52.214961 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3188 06:50:52.218187 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3189 06:50:52.224846 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3190 06:50:52.228493 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3191 06:50:52.231341 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3192 06:50:52.235334 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3193 06:50:52.238243 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3194 06:50:52.244936 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3195 06:50:52.248541 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3196 06:50:52.251310 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3197 06:50:52.254619 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3198 06:50:52.258088 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3199 06:50:52.264795 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3200 06:50:52.268283 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3201 06:50:52.271778 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3202 06:50:52.271875 ==
3203 06:50:52.275248 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 06:50:52.278632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 06:50:52.278706 ==
3206 06:50:52.281486 DQS Delay:
3207 06:50:52.281567 DQS0 = 0, DQS1 = 0
3208 06:50:52.284915 DQM Delay:
3209 06:50:52.285013 DQM0 = 119, DQM1 = 116
3210 06:50:52.288383 DQ Delay:
3211 06:50:52.291837 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3212 06:50:52.295346 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3213 06:50:52.298044 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3214 06:50:52.301941 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3215 06:50:52.302016
3216 06:50:52.302080
3217 06:50:52.302144 ==
3218 06:50:52.304923 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 06:50:52.308186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 06:50:52.308332 ==
3221 06:50:52.308410
3222 06:50:52.308476
3223 06:50:52.311663 TX Vref Scan disable
3224 06:50:52.315219 == TX Byte 0 ==
3225 06:50:52.318625 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3226 06:50:52.321442 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3227 06:50:52.324919 == TX Byte 1 ==
3228 06:50:52.328241 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3229 06:50:52.331929 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3230 06:50:52.332008 ==
3231 06:50:52.335218 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 06:50:52.338386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 06:50:52.338465 ==
3234 06:50:52.351916 TX Vref=22, minBit 9, minWin=24, winSum=410
3235 06:50:52.355363 TX Vref=24, minBit 9, minWin=25, winSum=419
3236 06:50:52.358137 TX Vref=26, minBit 9, minWin=25, winSum=422
3237 06:50:52.361441 TX Vref=28, minBit 1, minWin=26, winSum=429
3238 06:50:52.364883 TX Vref=30, minBit 10, minWin=25, winSum=431
3239 06:50:52.371769 TX Vref=32, minBit 9, minWin=26, winSum=431
3240 06:50:52.374853 [TxChooseVref] Worse bit 9, Min win 26, Win sum 431, Final Vref 32
3241 06:50:52.374936
3242 06:50:52.378246 Final TX Range 1 Vref 32
3243 06:50:52.378331
3244 06:50:52.378396 ==
3245 06:50:52.381744 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 06:50:52.385406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 06:50:52.385499 ==
3248 06:50:52.385570
3249 06:50:52.388255
3250 06:50:52.388349 TX Vref Scan disable
3251 06:50:52.391701 == TX Byte 0 ==
3252 06:50:52.395249 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3253 06:50:52.398797 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3254 06:50:52.401880 == TX Byte 1 ==
3255 06:50:52.405178 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3256 06:50:52.408543 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3257 06:50:52.408636
3258 06:50:52.411741 [DATLAT]
3259 06:50:52.411817 Freq=1200, CH1 RK0
3260 06:50:52.411887
3261 06:50:52.415490 DATLAT Default: 0xd
3262 06:50:52.415572 0, 0xFFFF, sum = 0
3263 06:50:52.418321 1, 0xFFFF, sum = 0
3264 06:50:52.418418 2, 0xFFFF, sum = 0
3265 06:50:52.421770 3, 0xFFFF, sum = 0
3266 06:50:52.421851 4, 0xFFFF, sum = 0
3267 06:50:52.425217 5, 0xFFFF, sum = 0
3268 06:50:52.425297 6, 0xFFFF, sum = 0
3269 06:50:52.428666 7, 0xFFFF, sum = 0
3270 06:50:52.428755 8, 0xFFFF, sum = 0
3271 06:50:52.432140 9, 0xFFFF, sum = 0
3272 06:50:52.432250 10, 0xFFFF, sum = 0
3273 06:50:52.435642 11, 0xFFFF, sum = 0
3274 06:50:52.438915 12, 0x0, sum = 1
3275 06:50:52.439021 13, 0x0, sum = 2
3276 06:50:52.439126 14, 0x0, sum = 3
3277 06:50:52.442263 15, 0x0, sum = 4
3278 06:50:52.442375 best_step = 13
3279 06:50:52.442440
3280 06:50:52.442512 ==
3281 06:50:52.445692 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 06:50:52.452209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 06:50:52.452328 ==
3284 06:50:52.452402 RX Vref Scan: 1
3285 06:50:52.452464
3286 06:50:52.455393 Set Vref Range= 32 -> 127
3287 06:50:52.455468
3288 06:50:52.458522 RX Vref 32 -> 127, step: 1
3289 06:50:52.458598
3290 06:50:52.461838 RX Delay -5 -> 252, step: 4
3291 06:50:52.461921
3292 06:50:52.461985 Set Vref, RX VrefLevel [Byte0]: 32
3293 06:50:52.465402 [Byte1]: 32
3294 06:50:52.469944
3295 06:50:52.470031 Set Vref, RX VrefLevel [Byte0]: 33
3296 06:50:52.473373 [Byte1]: 33
3297 06:50:52.478066
3298 06:50:52.478141 Set Vref, RX VrefLevel [Byte0]: 34
3299 06:50:52.481240 [Byte1]: 34
3300 06:50:52.485847
3301 06:50:52.485931 Set Vref, RX VrefLevel [Byte0]: 35
3302 06:50:52.489296 [Byte1]: 35
3303 06:50:52.493638
3304 06:50:52.493720 Set Vref, RX VrefLevel [Byte0]: 36
3305 06:50:52.497134 [Byte1]: 36
3306 06:50:52.501316
3307 06:50:52.501392 Set Vref, RX VrefLevel [Byte0]: 37
3308 06:50:52.504819 [Byte1]: 37
3309 06:50:52.509086
3310 06:50:52.509172 Set Vref, RX VrefLevel [Byte0]: 38
3311 06:50:52.512601 [Byte1]: 38
3312 06:50:52.516747
3313 06:50:52.516836 Set Vref, RX VrefLevel [Byte0]: 39
3314 06:50:52.520118 [Byte1]: 39
3315 06:50:52.524669
3316 06:50:52.524756 Set Vref, RX VrefLevel [Byte0]: 40
3317 06:50:52.527925 [Byte1]: 40
3318 06:50:52.532726
3319 06:50:52.532819 Set Vref, RX VrefLevel [Byte0]: 41
3320 06:50:52.536338 [Byte1]: 41
3321 06:50:52.540634
3322 06:50:52.540719 Set Vref, RX VrefLevel [Byte0]: 42
3323 06:50:52.543938 [Byte1]: 42
3324 06:50:52.548672
3325 06:50:52.548753 Set Vref, RX VrefLevel [Byte0]: 43
3326 06:50:52.551587 [Byte1]: 43
3327 06:50:52.556496
3328 06:50:52.556580 Set Vref, RX VrefLevel [Byte0]: 44
3329 06:50:52.559295 [Byte1]: 44
3330 06:50:52.564064
3331 06:50:52.564150 Set Vref, RX VrefLevel [Byte0]: 45
3332 06:50:52.567336 [Byte1]: 45
3333 06:50:52.572052
3334 06:50:52.572138 Set Vref, RX VrefLevel [Byte0]: 46
3335 06:50:52.575307 [Byte1]: 46
3336 06:50:52.579519
3337 06:50:52.579596 Set Vref, RX VrefLevel [Byte0]: 47
3338 06:50:52.582958 [Byte1]: 47
3339 06:50:52.587768
3340 06:50:52.587846 Set Vref, RX VrefLevel [Byte0]: 48
3341 06:50:52.591032 [Byte1]: 48
3342 06:50:52.595689
3343 06:50:52.595770 Set Vref, RX VrefLevel [Byte0]: 49
3344 06:50:52.599165 [Byte1]: 49
3345 06:50:52.603504
3346 06:50:52.603584 Set Vref, RX VrefLevel [Byte0]: 50
3347 06:50:52.607044 [Byte1]: 50
3348 06:50:52.611156
3349 06:50:52.611231 Set Vref, RX VrefLevel [Byte0]: 51
3350 06:50:52.614588 [Byte1]: 51
3351 06:50:52.619369
3352 06:50:52.619450 Set Vref, RX VrefLevel [Byte0]: 52
3353 06:50:52.622119 [Byte1]: 52
3354 06:50:52.627067
3355 06:50:52.627143 Set Vref, RX VrefLevel [Byte0]: 53
3356 06:50:52.630437 [Byte1]: 53
3357 06:50:52.634950
3358 06:50:52.635030 Set Vref, RX VrefLevel [Byte0]: 54
3359 06:50:52.638152 [Byte1]: 54
3360 06:50:52.642309
3361 06:50:52.642393 Set Vref, RX VrefLevel [Byte0]: 55
3362 06:50:52.645872 [Byte1]: 55
3363 06:50:52.650686
3364 06:50:52.650767 Set Vref, RX VrefLevel [Byte0]: 56
3365 06:50:52.654000 [Byte1]: 56
3366 06:50:52.658805
3367 06:50:52.658879 Set Vref, RX VrefLevel [Byte0]: 57
3368 06:50:52.661962 [Byte1]: 57
3369 06:50:52.666056
3370 06:50:52.666139 Set Vref, RX VrefLevel [Byte0]: 58
3371 06:50:52.669194 [Byte1]: 58
3372 06:50:52.674107
3373 06:50:52.674194 Set Vref, RX VrefLevel [Byte0]: 59
3374 06:50:52.677578 [Byte1]: 59
3375 06:50:52.682218
3376 06:50:52.682298 Set Vref, RX VrefLevel [Byte0]: 60
3377 06:50:52.685377 [Byte1]: 60
3378 06:50:52.689928
3379 06:50:52.690006 Set Vref, RX VrefLevel [Byte0]: 61
3380 06:50:52.693099 [Byte1]: 61
3381 06:50:52.697563
3382 06:50:52.697648 Set Vref, RX VrefLevel [Byte0]: 62
3383 06:50:52.700872 [Byte1]: 62
3384 06:50:52.705762
3385 06:50:52.705843 Set Vref, RX VrefLevel [Byte0]: 63
3386 06:50:52.709036 [Byte1]: 63
3387 06:50:52.713268
3388 06:50:52.713355 Set Vref, RX VrefLevel [Byte0]: 64
3389 06:50:52.716694 [Byte1]: 64
3390 06:50:52.720836
3391 06:50:52.720916 Set Vref, RX VrefLevel [Byte0]: 65
3392 06:50:52.724372 [Byte1]: 65
3393 06:50:52.729282
3394 06:50:52.729358 Set Vref, RX VrefLevel [Byte0]: 66
3395 06:50:52.732116 [Byte1]: 66
3396 06:50:52.736929
3397 06:50:52.737013 Set Vref, RX VrefLevel [Byte0]: 67
3398 06:50:52.740393 [Byte1]: 67
3399 06:50:52.744864
3400 06:50:52.744945 Set Vref, RX VrefLevel [Byte0]: 68
3401 06:50:52.747964 [Byte1]: 68
3402 06:50:52.752377
3403 06:50:52.752464 Set Vref, RX VrefLevel [Byte0]: 69
3404 06:50:52.756066 [Byte1]: 69
3405 06:50:52.760367
3406 06:50:52.760451 Final RX Vref Byte 0 = 52 to rank0
3407 06:50:52.763791 Final RX Vref Byte 1 = 53 to rank0
3408 06:50:52.767166 Final RX Vref Byte 0 = 52 to rank1
3409 06:50:52.770351 Final RX Vref Byte 1 = 53 to rank1==
3410 06:50:52.773581 Dram Type= 6, Freq= 0, CH_1, rank 0
3411 06:50:52.777058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 06:50:52.780670 ==
3413 06:50:52.780748 DQS Delay:
3414 06:50:52.780820 DQS0 = 0, DQS1 = 0
3415 06:50:52.784115 DQM Delay:
3416 06:50:52.784195 DQM0 = 120, DQM1 = 117
3417 06:50:52.787075 DQ Delay:
3418 06:50:52.790624 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3419 06:50:52.794110 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3420 06:50:52.797330 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3421 06:50:52.800668 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3422 06:50:52.800749
3423 06:50:52.800817
3424 06:50:52.807216 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3425 06:50:52.810460 CH1 RK0: MR19=304, MR18=FF12
3426 06:50:52.817322 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3427 06:50:52.817444
3428 06:50:52.820711 ----->DramcWriteLeveling(PI) begin...
3429 06:50:52.820810 ==
3430 06:50:52.824139 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 06:50:52.827562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 06:50:52.830429 ==
3433 06:50:52.830503 Write leveling (Byte 0): 26 => 26
3434 06:50:52.833939 Write leveling (Byte 1): 28 => 28
3435 06:50:52.837331 DramcWriteLeveling(PI) end<-----
3436 06:50:52.837431
3437 06:50:52.837540 ==
3438 06:50:52.840806 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 06:50:52.847237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 06:50:52.847322 ==
3441 06:50:52.847388 [Gating] SW mode calibration
3442 06:50:52.857081 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3443 06:50:52.860357 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3444 06:50:52.864167 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 06:50:52.870442 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 06:50:52.873858 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 06:50:52.877234 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 06:50:52.884438 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 06:50:52.887345 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3450 06:50:52.890735 0 15 24 | B1->B0 | 2828 3333 | 0 0 | (0 1) (0 1)
3451 06:50:52.897107 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3452 06:50:52.900612 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 06:50:52.904023 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 06:50:52.910891 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 06:50:52.914429 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 06:50:52.917234 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 06:50:52.923956 1 0 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3458 06:50:52.927224 1 0 24 | B1->B0 | 4444 2b2b | 0 0 | (0 0) (0 0)
3459 06:50:52.930779 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3460 06:50:52.934370 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 06:50:52.940847 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 06:50:52.944240 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 06:50:52.947026 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 06:50:52.954114 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 06:50:52.957512 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 06:50:52.960857 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3467 06:50:52.967421 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3468 06:50:52.970201 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 06:50:52.974133 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 06:50:52.980768 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 06:50:52.984315 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 06:50:52.987023 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 06:50:52.993596 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 06:50:52.996878 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 06:50:53.000357 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 06:50:53.007313 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 06:50:53.010783 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 06:50:53.013477 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 06:50:53.020339 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 06:50:53.023881 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 06:50:53.027371 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3482 06:50:53.033613 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3483 06:50:53.033691 Total UI for P1: 0, mck2ui 16
3484 06:50:53.040346 best dqsien dly found for B1: ( 1, 3, 20)
3485 06:50:53.043658 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 06:50:53.046764 Total UI for P1: 0, mck2ui 16
3487 06:50:53.050372 best dqsien dly found for B0: ( 1, 3, 24)
3488 06:50:53.053503 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3489 06:50:53.057179 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3490 06:50:53.057262
3491 06:50:53.060293 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3492 06:50:53.063636 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3493 06:50:53.067182 [Gating] SW calibration Done
3494 06:50:53.067281 ==
3495 06:50:53.070549 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 06:50:53.073810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 06:50:53.073885 ==
3498 06:50:53.077104 RX Vref Scan: 0
3499 06:50:53.077181
3500 06:50:53.080354 RX Vref 0 -> 0, step: 1
3501 06:50:53.080439
3502 06:50:53.080503 RX Delay -40 -> 252, step: 8
3503 06:50:53.086926 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3504 06:50:53.090430 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3505 06:50:53.093240 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3506 06:50:53.096499 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3507 06:50:53.099871 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3508 06:50:53.106795 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3509 06:50:53.110278 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3510 06:50:53.113038 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3511 06:50:53.116440 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3512 06:50:53.119838 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3513 06:50:53.126716 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3514 06:50:53.130251 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3515 06:50:53.132997 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3516 06:50:53.136641 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3517 06:50:53.142971 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3518 06:50:53.146385 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3519 06:50:53.146470 ==
3520 06:50:53.149870 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 06:50:53.153286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 06:50:53.153368 ==
3523 06:50:53.156616 DQS Delay:
3524 06:50:53.156694 DQS0 = 0, DQS1 = 0
3525 06:50:53.156789 DQM Delay:
3526 06:50:53.159872 DQM0 = 120, DQM1 = 117
3527 06:50:53.159948 DQ Delay:
3528 06:50:53.163131 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3529 06:50:53.166470 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3530 06:50:53.169662 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3531 06:50:53.176703 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3532 06:50:53.176795
3533 06:50:53.176860
3534 06:50:53.176932 ==
3535 06:50:53.179742 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 06:50:53.182948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 06:50:53.183023 ==
3538 06:50:53.183086
3539 06:50:53.183172
3540 06:50:53.186113 TX Vref Scan disable
3541 06:50:53.186199 == TX Byte 0 ==
3542 06:50:53.193289 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3543 06:50:53.196467 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3544 06:50:53.196588 == TX Byte 1 ==
3545 06:50:53.202591 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3546 06:50:53.206040 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3547 06:50:53.206155 ==
3548 06:50:53.209312 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 06:50:53.212868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 06:50:53.212956 ==
3551 06:50:53.225410 TX Vref=22, minBit 10, minWin=25, winSum=420
3552 06:50:53.228694 TX Vref=24, minBit 2, minWin=26, winSum=426
3553 06:50:53.232242 TX Vref=26, minBit 8, minWin=26, winSum=430
3554 06:50:53.235057 TX Vref=28, minBit 2, minWin=26, winSum=433
3555 06:50:53.238524 TX Vref=30, minBit 9, minWin=26, winSum=434
3556 06:50:53.245395 TX Vref=32, minBit 9, minWin=26, winSum=433
3557 06:50:53.248910 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3558 06:50:53.249007
3559 06:50:53.251769 Final TX Range 1 Vref 30
3560 06:50:53.251880
3561 06:50:53.251975 ==
3562 06:50:53.255337 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 06:50:53.258874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 06:50:53.258982 ==
3565 06:50:53.261671
3566 06:50:53.261775
3567 06:50:53.261867 TX Vref Scan disable
3568 06:50:53.264893 == TX Byte 0 ==
3569 06:50:53.268263 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3570 06:50:53.271865 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3571 06:50:53.275312 == TX Byte 1 ==
3572 06:50:53.278631 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3573 06:50:53.282070 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3574 06:50:53.285448
3575 06:50:53.285529 [DATLAT]
3576 06:50:53.285594 Freq=1200, CH1 RK1
3577 06:50:53.285671
3578 06:50:53.288795 DATLAT Default: 0xd
3579 06:50:53.288871 0, 0xFFFF, sum = 0
3580 06:50:53.291992 1, 0xFFFF, sum = 0
3581 06:50:53.292065 2, 0xFFFF, sum = 0
3582 06:50:53.295321 3, 0xFFFF, sum = 0
3583 06:50:53.295399 4, 0xFFFF, sum = 0
3584 06:50:53.298441 5, 0xFFFF, sum = 0
3585 06:50:53.301550 6, 0xFFFF, sum = 0
3586 06:50:53.301628 7, 0xFFFF, sum = 0
3587 06:50:53.305158 8, 0xFFFF, sum = 0
3588 06:50:53.305248 9, 0xFFFF, sum = 0
3589 06:50:53.308475 10, 0xFFFF, sum = 0
3590 06:50:53.308592 11, 0xFFFF, sum = 0
3591 06:50:53.311684 12, 0x0, sum = 1
3592 06:50:53.311799 13, 0x0, sum = 2
3593 06:50:53.315444 14, 0x0, sum = 3
3594 06:50:53.315519 15, 0x0, sum = 4
3595 06:50:53.315584 best_step = 13
3596 06:50:53.318414
3597 06:50:53.318519 ==
3598 06:50:53.321790 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 06:50:53.325328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 06:50:53.325410 ==
3601 06:50:53.325477 RX Vref Scan: 0
3602 06:50:53.325538
3603 06:50:53.328025 RX Vref 0 -> 0, step: 1
3604 06:50:53.328121
3605 06:50:53.331401 RX Delay -5 -> 252, step: 4
3606 06:50:53.334782 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3607 06:50:53.341715 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3608 06:50:53.345278 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3609 06:50:53.347990 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3610 06:50:53.351552 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3611 06:50:53.355052 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3612 06:50:53.361417 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3613 06:50:53.364921 iDelay=195, Bit 7, Center 118 (55 ~ 182) 128
3614 06:50:53.368386 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3615 06:50:53.371710 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3616 06:50:53.375184 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3617 06:50:53.381404 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3618 06:50:53.384765 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3619 06:50:53.388304 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3620 06:50:53.391853 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3621 06:50:53.394602 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3622 06:50:53.394716 ==
3623 06:50:53.398074 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 06:50:53.404795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 06:50:53.404878 ==
3626 06:50:53.404947 DQS Delay:
3627 06:50:53.408280 DQS0 = 0, DQS1 = 0
3628 06:50:53.408368 DQM Delay:
3629 06:50:53.411588 DQM0 = 120, DQM1 = 118
3630 06:50:53.411699 DQ Delay:
3631 06:50:53.415093 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3632 06:50:53.418030 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =118
3633 06:50:53.421379 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3634 06:50:53.424771 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3635 06:50:53.424880
3636 06:50:53.424976
3637 06:50:53.434711 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3638 06:50:53.434850 CH1 RK1: MR19=403, MR18=11EE
3639 06:50:53.441176 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3640 06:50:53.444864 [RxdqsGatingPostProcess] freq 1200
3641 06:50:53.451615 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3642 06:50:53.455027 best DQS0 dly(2T, 0.5T) = (0, 11)
3643 06:50:53.457888 best DQS1 dly(2T, 0.5T) = (0, 11)
3644 06:50:53.461413 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3645 06:50:53.464943 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3646 06:50:53.467738 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 06:50:53.471288 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 06:50:53.471397 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 06:50:53.474656 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 06:50:53.478136 Pre-setting of DQS Precalculation
3651 06:50:53.484814 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3652 06:50:53.491333 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3653 06:50:53.497793 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3654 06:50:53.497900
3655 06:50:53.497999
3656 06:50:53.501267 [Calibration Summary] 2400 Mbps
3657 06:50:53.504654 CH 0, Rank 0
3658 06:50:53.504766 SW Impedance : PASS
3659 06:50:53.508215 DUTY Scan : NO K
3660 06:50:53.511019 ZQ Calibration : PASS
3661 06:50:53.511124 Jitter Meter : NO K
3662 06:50:53.514511 CBT Training : PASS
3663 06:50:53.514620 Write leveling : PASS
3664 06:50:53.518070 RX DQS gating : PASS
3665 06:50:53.521370 RX DQ/DQS(RDDQC) : PASS
3666 06:50:53.521480 TX DQ/DQS : PASS
3667 06:50:53.524639 RX DATLAT : PASS
3668 06:50:53.528056 RX DQ/DQS(Engine): PASS
3669 06:50:53.528185 TX OE : NO K
3670 06:50:53.531239 All Pass.
3671 06:50:53.531345
3672 06:50:53.531442 CH 0, Rank 1
3673 06:50:53.534618 SW Impedance : PASS
3674 06:50:53.534723 DUTY Scan : NO K
3675 06:50:53.538072 ZQ Calibration : PASS
3676 06:50:53.541259 Jitter Meter : NO K
3677 06:50:53.541372 CBT Training : PASS
3678 06:50:53.544545 Write leveling : PASS
3679 06:50:53.547724 RX DQS gating : PASS
3680 06:50:53.547834 RX DQ/DQS(RDDQC) : PASS
3681 06:50:53.551065 TX DQ/DQS : PASS
3682 06:50:53.554389 RX DATLAT : PASS
3683 06:50:53.554496 RX DQ/DQS(Engine): PASS
3684 06:50:53.558037 TX OE : NO K
3685 06:50:53.558152 All Pass.
3686 06:50:53.558246
3687 06:50:53.561112 CH 1, Rank 0
3688 06:50:53.561229 SW Impedance : PASS
3689 06:50:53.564455 DUTY Scan : NO K
3690 06:50:53.564580 ZQ Calibration : PASS
3691 06:50:53.567955 Jitter Meter : NO K
3692 06:50:53.570791 CBT Training : PASS
3693 06:50:53.570893 Write leveling : PASS
3694 06:50:53.574252 RX DQS gating : PASS
3695 06:50:53.577712 RX DQ/DQS(RDDQC) : PASS
3696 06:50:53.577817 TX DQ/DQS : PASS
3697 06:50:53.581271 RX DATLAT : PASS
3698 06:50:53.584125 RX DQ/DQS(Engine): PASS
3699 06:50:53.584228 TX OE : NO K
3700 06:50:53.587439 All Pass.
3701 06:50:53.587545
3702 06:50:53.587637 CH 1, Rank 1
3703 06:50:53.590685 SW Impedance : PASS
3704 06:50:53.590768 DUTY Scan : NO K
3705 06:50:53.594147 ZQ Calibration : PASS
3706 06:50:53.597533 Jitter Meter : NO K
3707 06:50:53.597639 CBT Training : PASS
3708 06:50:53.600773 Write leveling : PASS
3709 06:50:53.604242 RX DQS gating : PASS
3710 06:50:53.604369 RX DQ/DQS(RDDQC) : PASS
3711 06:50:53.607387 TX DQ/DQS : PASS
3712 06:50:53.610558 RX DATLAT : PASS
3713 06:50:53.610696 RX DQ/DQS(Engine): PASS
3714 06:50:53.613921 TX OE : NO K
3715 06:50:53.614046 All Pass.
3716 06:50:53.614140
3717 06:50:53.617416 DramC Write-DBI off
3718 06:50:53.620939 PER_BANK_REFRESH: Hybrid Mode
3719 06:50:53.621046 TX_TRACKING: ON
3720 06:50:53.630694 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3721 06:50:53.634007 [FAST_K] Save calibration result to emmc
3722 06:50:53.637438 dramc_set_vcore_voltage set vcore to 650000
3723 06:50:53.640741 Read voltage for 600, 5
3724 06:50:53.640823 Vio18 = 0
3725 06:50:53.640890 Vcore = 650000
3726 06:50:53.644226 Vdram = 0
3727 06:50:53.644335 Vddq = 0
3728 06:50:53.644429 Vmddr = 0
3729 06:50:53.650881 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3730 06:50:53.654241 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3731 06:50:53.657667 MEM_TYPE=3, freq_sel=19
3732 06:50:53.660578 sv_algorithm_assistance_LP4_1600
3733 06:50:53.663903 ============ PULL DRAM RESETB DOWN ============
3734 06:50:53.667289 ========== PULL DRAM RESETB DOWN end =========
3735 06:50:53.673876 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3736 06:50:53.677530 ===================================
3737 06:50:53.677646 LPDDR4 DRAM CONFIGURATION
3738 06:50:53.680682 ===================================
3739 06:50:53.684198 EX_ROW_EN[0] = 0x0
3740 06:50:53.687090 EX_ROW_EN[1] = 0x0
3741 06:50:53.687210 LP4Y_EN = 0x0
3742 06:50:53.690566 WORK_FSP = 0x0
3743 06:50:53.690674 WL = 0x2
3744 06:50:53.694053 RL = 0x2
3745 06:50:53.694156 BL = 0x2
3746 06:50:53.697364 RPST = 0x0
3747 06:50:53.697465 RD_PRE = 0x0
3748 06:50:53.700736 WR_PRE = 0x1
3749 06:50:53.700820 WR_PST = 0x0
3750 06:50:53.704202 DBI_WR = 0x0
3751 06:50:53.704313 DBI_RD = 0x0
3752 06:50:53.706902 OTF = 0x1
3753 06:50:53.710284 ===================================
3754 06:50:53.713974 ===================================
3755 06:50:53.714077 ANA top config
3756 06:50:53.717192 ===================================
3757 06:50:53.720517 DLL_ASYNC_EN = 0
3758 06:50:53.724070 ALL_SLAVE_EN = 1
3759 06:50:53.724176 NEW_RANK_MODE = 1
3760 06:50:53.726916 DLL_IDLE_MODE = 1
3761 06:50:53.730416 LP45_APHY_COMB_EN = 1
3762 06:50:53.733867 TX_ODT_DIS = 1
3763 06:50:53.737195 NEW_8X_MODE = 1
3764 06:50:53.740011 ===================================
3765 06:50:53.743426 ===================================
3766 06:50:53.743531 data_rate = 1200
3767 06:50:53.746895 CKR = 1
3768 06:50:53.750466 DQ_P2S_RATIO = 8
3769 06:50:53.753845 ===================================
3770 06:50:53.757266 CA_P2S_RATIO = 8
3771 06:50:53.759930 DQ_CA_OPEN = 0
3772 06:50:53.763293 DQ_SEMI_OPEN = 0
3773 06:50:53.763397 CA_SEMI_OPEN = 0
3774 06:50:53.766926 CA_FULL_RATE = 0
3775 06:50:53.770512 DQ_CKDIV4_EN = 1
3776 06:50:53.774053 CA_CKDIV4_EN = 1
3777 06:50:53.777496 CA_PREDIV_EN = 0
3778 06:50:53.777581 PH8_DLY = 0
3779 06:50:53.780318 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3780 06:50:53.783737 DQ_AAMCK_DIV = 4
3781 06:50:53.787472 CA_AAMCK_DIV = 4
3782 06:50:53.790622 CA_ADMCK_DIV = 4
3783 06:50:53.793740 DQ_TRACK_CA_EN = 0
3784 06:50:53.797240 CA_PICK = 600
3785 06:50:53.797318 CA_MCKIO = 600
3786 06:50:53.800701 MCKIO_SEMI = 0
3787 06:50:53.804119 PLL_FREQ = 2288
3788 06:50:53.806658 DQ_UI_PI_RATIO = 32
3789 06:50:53.809973 CA_UI_PI_RATIO = 0
3790 06:50:53.813332 ===================================
3791 06:50:53.816724 ===================================
3792 06:50:53.820157 memory_type:LPDDR4
3793 06:50:53.820274 GP_NUM : 10
3794 06:50:53.823526 SRAM_EN : 1
3795 06:50:53.823634 MD32_EN : 0
3796 06:50:53.827139 ===================================
3797 06:50:53.830486 [ANA_INIT] >>>>>>>>>>>>>>
3798 06:50:53.833340 <<<<<< [CONFIGURE PHASE]: ANA_TX
3799 06:50:53.836843 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3800 06:50:53.840368 ===================================
3801 06:50:53.843758 data_rate = 1200,PCW = 0X5800
3802 06:50:53.847272 ===================================
3803 06:50:53.850553 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3804 06:50:53.853369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 06:50:53.860195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3806 06:50:53.866678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3807 06:50:53.869960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3808 06:50:53.873302 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3809 06:50:53.873424 [ANA_INIT] flow start
3810 06:50:53.877083 [ANA_INIT] PLL >>>>>>>>
3811 06:50:53.880019 [ANA_INIT] PLL <<<<<<<<
3812 06:50:53.880101 [ANA_INIT] MIDPI >>>>>>>>
3813 06:50:53.883713 [ANA_INIT] MIDPI <<<<<<<<
3814 06:50:53.886596 [ANA_INIT] DLL >>>>>>>>
3815 06:50:53.886711 [ANA_INIT] flow end
3816 06:50:53.890381 ============ LP4 DIFF to SE enter ============
3817 06:50:53.897129 ============ LP4 DIFF to SE exit ============
3818 06:50:53.897250 [ANA_INIT] <<<<<<<<<<<<<
3819 06:50:53.900014 [Flow] Enable top DCM control >>>>>
3820 06:50:53.903461 [Flow] Enable top DCM control <<<<<
3821 06:50:53.906845 Enable DLL master slave shuffle
3822 06:50:53.913245 ==============================================================
3823 06:50:53.913366 Gating Mode config
3824 06:50:53.920398 ==============================================================
3825 06:50:53.923632 Config description:
3826 06:50:53.933673 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3827 06:50:53.940412 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3828 06:50:53.943994 SELPH_MODE 0: By rank 1: By Phase
3829 06:50:53.950187 ==============================================================
3830 06:50:53.953504 GAT_TRACK_EN = 1
3831 06:50:53.953589 RX_GATING_MODE = 2
3832 06:50:53.956993 RX_GATING_TRACK_MODE = 2
3833 06:50:53.960299 SELPH_MODE = 1
3834 06:50:53.963898 PICG_EARLY_EN = 1
3835 06:50:53.966799 VALID_LAT_VALUE = 1
3836 06:50:53.973593 ==============================================================
3837 06:50:53.977047 Enter into Gating configuration >>>>
3838 06:50:53.980187 Exit from Gating configuration <<<<
3839 06:50:53.983612 Enter into DVFS_PRE_config >>>>>
3840 06:50:53.993534 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3841 06:50:53.996433 Exit from DVFS_PRE_config <<<<<
3842 06:50:54.000220 Enter into PICG configuration >>>>
3843 06:50:54.003162 Exit from PICG configuration <<<<
3844 06:50:54.006950 [RX_INPUT] configuration >>>>>
3845 06:50:54.010031 [RX_INPUT] configuration <<<<<
3846 06:50:54.013667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3847 06:50:54.020239 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3848 06:50:54.026846 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3849 06:50:54.030223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3850 06:50:54.036670 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3851 06:50:54.043732 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3852 06:50:54.046498 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3853 06:50:54.049760 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3854 06:50:54.056368 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3855 06:50:54.060067 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3856 06:50:54.063483 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3857 06:50:54.070148 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3858 06:50:54.073153 ===================================
3859 06:50:54.073236 LPDDR4 DRAM CONFIGURATION
3860 06:50:54.076213 ===================================
3861 06:50:54.079612 EX_ROW_EN[0] = 0x0
3862 06:50:54.083040 EX_ROW_EN[1] = 0x0
3863 06:50:54.083129 LP4Y_EN = 0x0
3864 06:50:54.086441 WORK_FSP = 0x0
3865 06:50:54.086520 WL = 0x2
3866 06:50:54.089760 RL = 0x2
3867 06:50:54.089849 BL = 0x2
3868 06:50:54.093325 RPST = 0x0
3869 06:50:54.093404 RD_PRE = 0x0
3870 06:50:54.096834 WR_PRE = 0x1
3871 06:50:54.096913 WR_PST = 0x0
3872 06:50:54.099576 DBI_WR = 0x0
3873 06:50:54.099660 DBI_RD = 0x0
3874 06:50:54.102990 OTF = 0x1
3875 06:50:54.106490 ===================================
3876 06:50:54.109934 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3877 06:50:54.113486 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3878 06:50:54.119775 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3879 06:50:54.119854 ===================================
3880 06:50:54.123320 LPDDR4 DRAM CONFIGURATION
3881 06:50:54.126738 ===================================
3882 06:50:54.129614 EX_ROW_EN[0] = 0x10
3883 06:50:54.129690 EX_ROW_EN[1] = 0x0
3884 06:50:54.133368 LP4Y_EN = 0x0
3885 06:50:54.133458 WORK_FSP = 0x0
3886 06:50:54.136412 WL = 0x2
3887 06:50:54.139303 RL = 0x2
3888 06:50:54.139420 BL = 0x2
3889 06:50:54.142870 RPST = 0x0
3890 06:50:54.142953 RD_PRE = 0x0
3891 06:50:54.146365 WR_PRE = 0x1
3892 06:50:54.146446 WR_PST = 0x0
3893 06:50:54.149834 DBI_WR = 0x0
3894 06:50:54.149915 DBI_RD = 0x0
3895 06:50:54.152502 OTF = 0x1
3896 06:50:54.155898 ===================================
3897 06:50:54.162437 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3898 06:50:54.165702 nWR fixed to 30
3899 06:50:54.165790 [ModeRegInit_LP4] CH0 RK0
3900 06:50:54.169276 [ModeRegInit_LP4] CH0 RK1
3901 06:50:54.172740 [ModeRegInit_LP4] CH1 RK0
3902 06:50:54.172818 [ModeRegInit_LP4] CH1 RK1
3903 06:50:54.175792 match AC timing 17
3904 06:50:54.179291 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3905 06:50:54.185797 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3906 06:50:54.189122 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3907 06:50:54.192620 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3908 06:50:54.199054 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3909 06:50:54.199137 ==
3910 06:50:54.202554 Dram Type= 6, Freq= 0, CH_0, rank 0
3911 06:50:54.205913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3912 06:50:54.205990 ==
3913 06:50:54.212553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3914 06:50:54.215885 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3915 06:50:54.220171 [CA 0] Center 35 (5~66) winsize 62
3916 06:50:54.223748 [CA 1] Center 35 (5~66) winsize 62
3917 06:50:54.226610 [CA 2] Center 33 (3~64) winsize 62
3918 06:50:54.230282 [CA 3] Center 33 (2~64) winsize 63
3919 06:50:54.233932 [CA 4] Center 33 (2~64) winsize 63
3920 06:50:54.236949 [CA 5] Center 32 (2~63) winsize 62
3921 06:50:54.237038
3922 06:50:54.239890 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3923 06:50:54.239974
3924 06:50:54.243394 [CATrainingPosCal] consider 1 rank data
3925 06:50:54.247239 u2DelayCellTimex100 = 270/100 ps
3926 06:50:54.250395 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3927 06:50:54.253742 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3928 06:50:54.260137 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3929 06:50:54.263648 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3930 06:50:54.267228 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3931 06:50:54.270078 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3932 06:50:54.270152
3933 06:50:54.273659 CA PerBit enable=1, Macro0, CA PI delay=32
3934 06:50:54.273748
3935 06:50:54.277118 [CBTSetCACLKResult] CA Dly = 32
3936 06:50:54.277240 CS Dly: 5 (0~36)
3937 06:50:54.280441 ==
3938 06:50:54.280512 Dram Type= 6, Freq= 0, CH_0, rank 1
3939 06:50:54.286427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3940 06:50:54.286565 ==
3941 06:50:54.289892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3942 06:50:54.296663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3943 06:50:54.300147 [CA 0] Center 35 (5~66) winsize 62
3944 06:50:54.303512 [CA 1] Center 35 (5~66) winsize 62
3945 06:50:54.306858 [CA 2] Center 34 (3~65) winsize 63
3946 06:50:54.310125 [CA 3] Center 33 (3~64) winsize 62
3947 06:50:54.313420 [CA 4] Center 33 (2~64) winsize 63
3948 06:50:54.316810 [CA 5] Center 32 (2~63) winsize 62
3949 06:50:54.316898
3950 06:50:54.320120 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3951 06:50:54.320223
3952 06:50:54.323383 [CATrainingPosCal] consider 2 rank data
3953 06:50:54.326718 u2DelayCellTimex100 = 270/100 ps
3954 06:50:54.330297 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3955 06:50:54.334042 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3956 06:50:54.340376 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3957 06:50:54.343985 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3958 06:50:54.346899 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3959 06:50:54.350468 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3960 06:50:54.350553
3961 06:50:54.354065 CA PerBit enable=1, Macro0, CA PI delay=32
3962 06:50:54.354148
3963 06:50:54.356890 [CBTSetCACLKResult] CA Dly = 32
3964 06:50:54.356973 CS Dly: 4 (0~35)
3965 06:50:54.357039
3966 06:50:54.360409 ----->DramcWriteLeveling(PI) begin...
3967 06:50:54.363359 ==
3968 06:50:54.366938 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 06:50:54.370506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 06:50:54.370603 ==
3971 06:50:54.373351 Write leveling (Byte 0): 34 => 34
3972 06:50:54.376914 Write leveling (Byte 1): 31 => 31
3973 06:50:54.379794 DramcWriteLeveling(PI) end<-----
3974 06:50:54.379894
3975 06:50:54.379962 ==
3976 06:50:54.383296 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 06:50:54.386913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 06:50:54.386997 ==
3979 06:50:54.389837 [Gating] SW mode calibration
3980 06:50:54.396516 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3981 06:50:54.403251 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3982 06:50:54.406684 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 06:50:54.410046 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 06:50:54.413497 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3985 06:50:54.419876 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)
3986 06:50:54.423508 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
3987 06:50:54.426384 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 06:50:54.433454 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 06:50:54.436295 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 06:50:54.439865 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 06:50:54.446239 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 06:50:54.449993 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 06:50:54.453306 0 10 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
3994 06:50:54.459764 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
3995 06:50:54.463365 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 06:50:54.466301 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 06:50:54.472868 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 06:50:54.476563 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 06:50:54.479549 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 06:50:54.486025 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 06:50:54.489536 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4002 06:50:54.493110 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4003 06:50:54.499528 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 06:50:54.502797 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 06:50:54.506201 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 06:50:54.512696 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 06:50:54.516054 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 06:50:54.519248 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 06:50:54.526192 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 06:50:54.529562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 06:50:54.532451 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 06:50:54.539507 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 06:50:54.542361 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 06:50:54.545807 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 06:50:54.552889 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 06:50:54.556264 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 06:50:54.559122 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4018 06:50:54.565826 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 06:50:54.565939 Total UI for P1: 0, mck2ui 16
4020 06:50:54.569174 best dqsien dly found for B0: ( 0, 13, 12)
4021 06:50:54.572595 Total UI for P1: 0, mck2ui 16
4022 06:50:54.576064 best dqsien dly found for B1: ( 0, 13, 12)
4023 06:50:54.582865 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4024 06:50:54.585640 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4025 06:50:54.585739
4026 06:50:54.589220 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4027 06:50:54.592657 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4028 06:50:54.596098 [Gating] SW calibration Done
4029 06:50:54.596204 ==
4030 06:50:54.598917 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 06:50:54.602525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 06:50:54.602623 ==
4033 06:50:54.606009 RX Vref Scan: 0
4034 06:50:54.606106
4035 06:50:54.606204 RX Vref 0 -> 0, step: 1
4036 06:50:54.606293
4037 06:50:54.609324 RX Delay -230 -> 252, step: 16
4038 06:50:54.612127 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4039 06:50:54.618960 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4040 06:50:54.622322 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4041 06:50:54.625621 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4042 06:50:54.629143 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4043 06:50:54.635573 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4044 06:50:54.638634 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4045 06:50:54.642619 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4046 06:50:54.645468 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4047 06:50:54.648858 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4048 06:50:54.655511 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4049 06:50:54.659096 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4050 06:50:54.662595 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4051 06:50:54.665396 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4052 06:50:54.672294 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4053 06:50:54.675496 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4054 06:50:54.675593 ==
4055 06:50:54.678721 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 06:50:54.682333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 06:50:54.682415 ==
4058 06:50:54.682481 DQS Delay:
4059 06:50:54.685491 DQS0 = 0, DQS1 = 0
4060 06:50:54.685602 DQM Delay:
4061 06:50:54.688697 DQM0 = 55, DQM1 = 46
4062 06:50:54.688821 DQ Delay:
4063 06:50:54.692380 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4064 06:50:54.695259 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4065 06:50:54.698841 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4066 06:50:54.702391 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4067 06:50:54.702468
4068 06:50:54.702539
4069 06:50:54.702609 ==
4070 06:50:54.705292 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 06:50:54.708829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 06:50:54.712362 ==
4073 06:50:54.712446
4074 06:50:54.712538
4075 06:50:54.712637 TX Vref Scan disable
4076 06:50:54.715289 == TX Byte 0 ==
4077 06:50:54.718549 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4078 06:50:54.722100 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4079 06:50:54.725653 == TX Byte 1 ==
4080 06:50:54.729069 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4081 06:50:54.735339 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4082 06:50:54.735426 ==
4083 06:50:54.738796 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 06:50:54.742240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 06:50:54.742318 ==
4086 06:50:54.742400
4087 06:50:54.742467
4088 06:50:54.745597 TX Vref Scan disable
4089 06:50:54.748831 == TX Byte 0 ==
4090 06:50:54.751963 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4091 06:50:54.755113 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4092 06:50:54.758840 == TX Byte 1 ==
4093 06:50:54.761799 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4094 06:50:54.765524 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4095 06:50:54.765636
4096 06:50:54.765737 [DATLAT]
4097 06:50:54.768591 Freq=600, CH0 RK0
4098 06:50:54.768673
4099 06:50:54.768735 DATLAT Default: 0x9
4100 06:50:54.772183 0, 0xFFFF, sum = 0
4101 06:50:54.775082 1, 0xFFFF, sum = 0
4102 06:50:54.775164 2, 0xFFFF, sum = 0
4103 06:50:54.778514 3, 0xFFFF, sum = 0
4104 06:50:54.778617 4, 0xFFFF, sum = 0
4105 06:50:54.781811 5, 0xFFFF, sum = 0
4106 06:50:54.781888 6, 0xFFFF, sum = 0
4107 06:50:54.785359 7, 0xFFFF, sum = 0
4108 06:50:54.785440 8, 0x0, sum = 1
4109 06:50:54.788640 9, 0x0, sum = 2
4110 06:50:54.788749 10, 0x0, sum = 3
4111 06:50:54.788848 11, 0x0, sum = 4
4112 06:50:54.791894 best_step = 9
4113 06:50:54.791972
4114 06:50:54.792032 ==
4115 06:50:54.795054 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 06:50:54.798423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 06:50:54.798514 ==
4118 06:50:54.801848 RX Vref Scan: 1
4119 06:50:54.801932
4120 06:50:54.802008 RX Vref 0 -> 0, step: 1
4121 06:50:54.802069
4122 06:50:54.805486 RX Delay -163 -> 252, step: 8
4123 06:50:54.805557
4124 06:50:54.808356 Set Vref, RX VrefLevel [Byte0]: 55
4125 06:50:54.811909 [Byte1]: 53
4126 06:50:54.816214
4127 06:50:54.816323 Final RX Vref Byte 0 = 55 to rank0
4128 06:50:54.818971 Final RX Vref Byte 1 = 53 to rank0
4129 06:50:54.822237 Final RX Vref Byte 0 = 55 to rank1
4130 06:50:54.826099 Final RX Vref Byte 1 = 53 to rank1==
4131 06:50:54.829289 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 06:50:54.835528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 06:50:54.835616 ==
4134 06:50:54.835704 DQS Delay:
4135 06:50:54.835787 DQS0 = 0, DQS1 = 0
4136 06:50:54.838916 DQM Delay:
4137 06:50:54.839003 DQM0 = 53, DQM1 = 46
4138 06:50:54.842464 DQ Delay:
4139 06:50:54.845926 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4140 06:50:54.846038 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4141 06:50:54.849398 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4142 06:50:54.852356 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4143 06:50:54.855991
4144 06:50:54.856101
4145 06:50:54.862608 [DQSOSCAuto] RK0, (LSB)MR18= 0x7164, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4146 06:50:54.865936 CH0 RK0: MR19=808, MR18=7164
4147 06:50:54.872117 CH0_RK0: MR19=0x808, MR18=0x7164, DQSOSC=388, MR23=63, INC=174, DEC=116
4148 06:50:54.872228
4149 06:50:54.875668 ----->DramcWriteLeveling(PI) begin...
4150 06:50:54.875770 ==
4151 06:50:54.879084 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 06:50:54.882569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 06:50:54.882672 ==
4154 06:50:54.885516 Write leveling (Byte 0): 33 => 33
4155 06:50:54.889044 Write leveling (Byte 1): 32 => 32
4156 06:50:54.892425 DramcWriteLeveling(PI) end<-----
4157 06:50:54.892505
4158 06:50:54.892590 ==
4159 06:50:54.896034 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 06:50:54.898817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 06:50:54.898905 ==
4162 06:50:54.902162 [Gating] SW mode calibration
4163 06:50:54.908599 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4164 06:50:54.915310 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4165 06:50:54.918857 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 06:50:54.922364 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 06:50:54.928898 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 06:50:54.932409 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4169 06:50:54.935658 0 9 16 | B1->B0 | 2b2b 2828 | 0 0 | (0 0) (0 0)
4170 06:50:54.942427 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 06:50:54.945883 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 06:50:54.948743 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 06:50:54.955162 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 06:50:54.958746 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 06:50:54.962317 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 06:50:54.968709 0 10 12 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
4177 06:50:54.972218 0 10 16 | B1->B0 | 3c3c 4343 | 0 0 | (0 0) (0 0)
4178 06:50:54.975666 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 06:50:54.982416 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 06:50:54.985450 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 06:50:54.988797 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 06:50:54.995231 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 06:50:54.998531 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 06:50:55.001853 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4185 06:50:55.008532 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 06:50:55.011619 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 06:50:55.015085 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 06:50:55.021803 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 06:50:55.025204 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 06:50:55.028632 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 06:50:55.035034 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 06:50:55.038554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 06:50:55.041971 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 06:50:55.045307 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 06:50:55.051982 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 06:50:55.055307 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 06:50:55.058966 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 06:50:55.065415 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 06:50:55.068950 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4200 06:50:55.071761 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4201 06:50:55.078249 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 06:50:55.081917 Total UI for P1: 0, mck2ui 16
4203 06:50:55.085510 best dqsien dly found for B0: ( 0, 13, 14)
4204 06:50:55.085616 Total UI for P1: 0, mck2ui 16
4205 06:50:55.091620 best dqsien dly found for B1: ( 0, 13, 10)
4206 06:50:55.094893 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4207 06:50:55.098298 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4208 06:50:55.098394
4209 06:50:55.101686 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4210 06:50:55.105090 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4211 06:50:55.108571 [Gating] SW calibration Done
4212 06:50:55.108672 ==
4213 06:50:55.111789 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 06:50:55.114633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 06:50:55.114746 ==
4216 06:50:55.118165 RX Vref Scan: 0
4217 06:50:55.118267
4218 06:50:55.118371 RX Vref 0 -> 0, step: 1
4219 06:50:55.121858
4220 06:50:55.121961 RX Delay -230 -> 252, step: 16
4221 06:50:55.128447 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4222 06:50:55.131556 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4223 06:50:55.135038 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4224 06:50:55.138504 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4225 06:50:55.144924 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4226 06:50:55.148492 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4227 06:50:55.151205 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4228 06:50:55.155336 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4229 06:50:55.158196 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4230 06:50:55.165028 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4231 06:50:55.167923 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4232 06:50:55.171351 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4233 06:50:55.174954 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4234 06:50:55.181424 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4235 06:50:55.185033 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4236 06:50:55.187882 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4237 06:50:55.187982 ==
4238 06:50:55.191590 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 06:50:55.195062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 06:50:55.195137 ==
4241 06:50:55.197873 DQS Delay:
4242 06:50:55.197974 DQS0 = 0, DQS1 = 0
4243 06:50:55.201275 DQM Delay:
4244 06:50:55.201370 DQM0 = 51, DQM1 = 43
4245 06:50:55.201434 DQ Delay:
4246 06:50:55.204841 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4247 06:50:55.208185 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4248 06:50:55.211735 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4249 06:50:55.214561 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4250 06:50:55.214661
4251 06:50:55.214759
4252 06:50:55.217973 ==
4253 06:50:55.221336 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 06:50:55.224732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 06:50:55.224837 ==
4256 06:50:55.224938
4257 06:50:55.225028
4258 06:50:55.228031 TX Vref Scan disable
4259 06:50:55.228112 == TX Byte 0 ==
4260 06:50:55.234470 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4261 06:50:55.238004 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4262 06:50:55.238090 == TX Byte 1 ==
4263 06:50:55.244807 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4264 06:50:55.248063 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4265 06:50:55.248183 ==
4266 06:50:55.251462 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 06:50:55.254262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 06:50:55.254383 ==
4269 06:50:55.254479
4270 06:50:55.254571
4271 06:50:55.257778 TX Vref Scan disable
4272 06:50:55.261149 == TX Byte 0 ==
4273 06:50:55.264121 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4274 06:50:55.267660 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4275 06:50:55.271058 == TX Byte 1 ==
4276 06:50:55.274488 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4277 06:50:55.277904 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4278 06:50:55.277985
4279 06:50:55.280779 [DATLAT]
4280 06:50:55.280856 Freq=600, CH0 RK1
4281 06:50:55.280965
4282 06:50:55.284295 DATLAT Default: 0x9
4283 06:50:55.284391 0, 0xFFFF, sum = 0
4284 06:50:55.287854 1, 0xFFFF, sum = 0
4285 06:50:55.287958 2, 0xFFFF, sum = 0
4286 06:50:55.290761 3, 0xFFFF, sum = 0
4287 06:50:55.290880 4, 0xFFFF, sum = 0
4288 06:50:55.294269 5, 0xFFFF, sum = 0
4289 06:50:55.294390 6, 0xFFFF, sum = 0
4290 06:50:55.297934 7, 0xFFFF, sum = 0
4291 06:50:55.298059 8, 0x0, sum = 1
4292 06:50:55.300881 9, 0x0, sum = 2
4293 06:50:55.300985 10, 0x0, sum = 3
4294 06:50:55.304492 11, 0x0, sum = 4
4295 06:50:55.304590 best_step = 9
4296 06:50:55.304655
4297 06:50:55.304738 ==
4298 06:50:55.307973 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 06:50:55.310668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 06:50:55.314156 ==
4301 06:50:55.314231 RX Vref Scan: 0
4302 06:50:55.314302
4303 06:50:55.317430 RX Vref 0 -> 0, step: 1
4304 06:50:55.317531
4305 06:50:55.320562 RX Delay -163 -> 252, step: 8
4306 06:50:55.324109 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4307 06:50:55.327593 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4308 06:50:55.333689 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4309 06:50:55.337161 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4310 06:50:55.340905 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4311 06:50:55.343745 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4312 06:50:55.347239 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4313 06:50:55.353962 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4314 06:50:55.357287 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4315 06:50:55.360629 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4316 06:50:55.363956 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4317 06:50:55.367406 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4318 06:50:55.374232 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4319 06:50:55.377185 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4320 06:50:55.380631 iDelay=197, Bit 14, Center 52 (-91 ~ 196) 288
4321 06:50:55.383943 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4322 06:50:55.384049 ==
4323 06:50:55.387419 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 06:50:55.393932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 06:50:55.394040 ==
4326 06:50:55.394136 DQS Delay:
4327 06:50:55.397499 DQS0 = 0, DQS1 = 0
4328 06:50:55.397575 DQM Delay:
4329 06:50:55.397638 DQM0 = 53, DQM1 = 46
4330 06:50:55.400255 DQ Delay:
4331 06:50:55.403891 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4332 06:50:55.407442 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4333 06:50:55.410436 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4334 06:50:55.414126 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4335 06:50:55.414201
4336 06:50:55.414264
4337 06:50:55.420354 [DQSOSCAuto] RK1, (LSB)MR18= 0x6322, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4338 06:50:55.423803 CH0 RK1: MR19=808, MR18=6322
4339 06:50:55.430501 CH0_RK1: MR19=0x808, MR18=0x6322, DQSOSC=391, MR23=63, INC=171, DEC=114
4340 06:50:55.434172 [RxdqsGatingPostProcess] freq 600
4341 06:50:55.436958 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4342 06:50:55.440248 Pre-setting of DQS Precalculation
4343 06:50:55.447326 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4344 06:50:55.447411 ==
4345 06:50:55.450224 Dram Type= 6, Freq= 0, CH_1, rank 0
4346 06:50:55.453664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 06:50:55.453749 ==
4348 06:50:55.460526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4349 06:50:55.463920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4350 06:50:55.467969 [CA 0] Center 35 (5~66) winsize 62
4351 06:50:55.471422 [CA 1] Center 36 (5~67) winsize 63
4352 06:50:55.474819 [CA 2] Center 34 (4~65) winsize 62
4353 06:50:55.478260 [CA 3] Center 34 (3~65) winsize 63
4354 06:50:55.481606 [CA 4] Center 34 (4~65) winsize 62
4355 06:50:55.484841 [CA 5] Center 34 (3~65) winsize 63
4356 06:50:55.484925
4357 06:50:55.488314 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4358 06:50:55.488400
4359 06:50:55.491707 [CATrainingPosCal] consider 1 rank data
4360 06:50:55.495133 u2DelayCellTimex100 = 270/100 ps
4361 06:50:55.497956 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4362 06:50:55.501608 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4363 06:50:55.508149 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4364 06:50:55.511734 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4365 06:50:55.514629 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4366 06:50:55.518362 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4367 06:50:55.518443
4368 06:50:55.521041 CA PerBit enable=1, Macro0, CA PI delay=34
4369 06:50:55.521116
4370 06:50:55.524519 [CBTSetCACLKResult] CA Dly = 34
4371 06:50:55.524627 CS Dly: 5 (0~36)
4372 06:50:55.528258 ==
4373 06:50:55.528379 Dram Type= 6, Freq= 0, CH_1, rank 1
4374 06:50:55.534539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 06:50:55.534619 ==
4376 06:50:55.538104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4377 06:50:55.544850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4378 06:50:55.548194 [CA 0] Center 36 (5~67) winsize 63
4379 06:50:55.551508 [CA 1] Center 36 (5~67) winsize 63
4380 06:50:55.554881 [CA 2] Center 34 (4~65) winsize 62
4381 06:50:55.558341 [CA 3] Center 34 (3~65) winsize 63
4382 06:50:55.561685 [CA 4] Center 35 (4~66) winsize 63
4383 06:50:55.564973 [CA 5] Center 34 (3~65) winsize 63
4384 06:50:55.565073
4385 06:50:55.568303 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4386 06:50:55.568379
4387 06:50:55.571859 [CATrainingPosCal] consider 2 rank data
4388 06:50:55.574705 u2DelayCellTimex100 = 270/100 ps
4389 06:50:55.578200 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4390 06:50:55.581629 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4391 06:50:55.587980 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 06:50:55.591174 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4393 06:50:55.594389 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4394 06:50:55.598310 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4395 06:50:55.598388
4396 06:50:55.601054 CA PerBit enable=1, Macro0, CA PI delay=34
4397 06:50:55.601139
4398 06:50:55.604425 [CBTSetCACLKResult] CA Dly = 34
4399 06:50:55.604500 CS Dly: 5 (0~37)
4400 06:50:55.604563
4401 06:50:55.607925 ----->DramcWriteLeveling(PI) begin...
4402 06:50:55.611476 ==
4403 06:50:55.614422 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 06:50:55.618164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 06:50:55.618250 ==
4406 06:50:55.621010 Write leveling (Byte 0): 30 => 30
4407 06:50:55.624475 Write leveling (Byte 1): 30 => 30
4408 06:50:55.627981 DramcWriteLeveling(PI) end<-----
4409 06:50:55.628093
4410 06:50:55.628193 ==
4411 06:50:55.631548 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 06:50:55.634432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 06:50:55.634549 ==
4414 06:50:55.638018 [Gating] SW mode calibration
4415 06:50:55.644548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4416 06:50:55.647783 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4417 06:50:55.654488 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 06:50:55.658006 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 06:50:55.661321 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 06:50:55.668051 0 9 12 | B1->B0 | 2e2e 2c2c | 1 1 | (1 0) (1 0)
4421 06:50:55.671335 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 06:50:55.674714 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 06:50:55.681293 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 06:50:55.684720 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 06:50:55.688045 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 06:50:55.694536 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 06:50:55.698056 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4428 06:50:55.701484 0 10 12 | B1->B0 | 3737 3d3d | 0 0 | (0 0) (0 0)
4429 06:50:55.707691 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 06:50:55.711147 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 06:50:55.714327 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 06:50:55.721330 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 06:50:55.724212 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 06:50:55.727850 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 06:50:55.734369 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 06:50:55.737837 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 06:50:55.741425 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 06:50:55.747800 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 06:50:55.750684 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 06:50:55.754290 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 06:50:55.760763 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 06:50:55.764061 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 06:50:55.767665 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 06:50:55.774079 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 06:50:55.777545 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 06:50:55.780876 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 06:50:55.784108 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 06:50:55.791126 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 06:50:55.793854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 06:50:55.797872 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 06:50:55.804274 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 06:50:55.807837 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4453 06:50:55.810626 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 06:50:55.814243 Total UI for P1: 0, mck2ui 16
4455 06:50:55.817175 best dqsien dly found for B0: ( 0, 13, 12)
4456 06:50:55.820521 Total UI for P1: 0, mck2ui 16
4457 06:50:55.824448 best dqsien dly found for B1: ( 0, 13, 14)
4458 06:50:55.827832 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4459 06:50:55.830650 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4460 06:50:55.830765
4461 06:50:55.837662 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4462 06:50:55.840479 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4463 06:50:55.843860 [Gating] SW calibration Done
4464 06:50:55.843972 ==
4465 06:50:55.847527 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 06:50:55.850390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 06:50:55.850471 ==
4468 06:50:55.850545 RX Vref Scan: 0
4469 06:50:55.850608
4470 06:50:55.853976 RX Vref 0 -> 0, step: 1
4471 06:50:55.854082
4472 06:50:55.857506 RX Delay -230 -> 252, step: 16
4473 06:50:55.860421 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4474 06:50:55.863890 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4475 06:50:55.870651 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4476 06:50:55.873726 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4477 06:50:55.877150 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4478 06:50:55.880691 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4479 06:50:55.887339 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4480 06:50:55.890629 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4481 06:50:55.893919 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4482 06:50:55.897168 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4483 06:50:55.900594 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4484 06:50:55.907405 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4485 06:50:55.910496 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4486 06:50:55.913774 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4487 06:50:55.917403 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4488 06:50:55.923699 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4489 06:50:55.923805 ==
4490 06:50:55.927290 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 06:50:55.930804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 06:50:55.930884 ==
4493 06:50:55.930953 DQS Delay:
4494 06:50:55.933928 DQS0 = 0, DQS1 = 0
4495 06:50:55.934035 DQM Delay:
4496 06:50:55.937286 DQM0 = 51, DQM1 = 48
4497 06:50:55.937367 DQ Delay:
4498 06:50:55.940833 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4499 06:50:55.944332 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4500 06:50:55.947151 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4501 06:50:55.950628 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4502 06:50:55.950712
4503 06:50:55.950777
4504 06:50:55.950838 ==
4505 06:50:55.954230 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 06:50:55.957182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 06:50:55.957259 ==
4508 06:50:55.957327
4509 06:50:55.960658
4510 06:50:55.960732 TX Vref Scan disable
4511 06:50:55.963594 == TX Byte 0 ==
4512 06:50:55.967210 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4513 06:50:55.970780 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4514 06:50:55.973495 == TX Byte 1 ==
4515 06:50:55.976936 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4516 06:50:55.980331 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4517 06:50:55.980406 ==
4518 06:50:55.983638 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 06:50:55.990461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 06:50:55.990568 ==
4521 06:50:55.990665
4522 06:50:55.990756
4523 06:50:55.990844 TX Vref Scan disable
4524 06:50:55.994707 == TX Byte 0 ==
4525 06:50:55.997937 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4526 06:50:56.005242 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4527 06:50:56.005342 == TX Byte 1 ==
4528 06:50:56.007908 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4529 06:50:56.014620 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4530 06:50:56.014713
4531 06:50:56.014787 [DATLAT]
4532 06:50:56.014851 Freq=600, CH1 RK0
4533 06:50:56.014912
4534 06:50:56.018384 DATLAT Default: 0x9
4535 06:50:56.018495 0, 0xFFFF, sum = 0
4536 06:50:56.021580 1, 0xFFFF, sum = 0
4537 06:50:56.024394 2, 0xFFFF, sum = 0
4538 06:50:56.024475 3, 0xFFFF, sum = 0
4539 06:50:56.028124 4, 0xFFFF, sum = 0
4540 06:50:56.028242 5, 0xFFFF, sum = 0
4541 06:50:56.031588 6, 0xFFFF, sum = 0
4542 06:50:56.031704 7, 0xFFFF, sum = 0
4543 06:50:56.034436 8, 0x0, sum = 1
4544 06:50:56.034542 9, 0x0, sum = 2
4545 06:50:56.034650 10, 0x0, sum = 3
4546 06:50:56.037942 11, 0x0, sum = 4
4547 06:50:56.038027 best_step = 9
4548 06:50:56.038091
4549 06:50:56.038176 ==
4550 06:50:56.041418 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 06:50:56.047956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 06:50:56.048080 ==
4553 06:50:56.048175 RX Vref Scan: 1
4554 06:50:56.048275
4555 06:50:56.051526 RX Vref 0 -> 0, step: 1
4556 06:50:56.051633
4557 06:50:56.054237 RX Delay -163 -> 252, step: 8
4558 06:50:56.054336
4559 06:50:56.057794 Set Vref, RX VrefLevel [Byte0]: 52
4560 06:50:56.061357 [Byte1]: 53
4561 06:50:56.061465
4562 06:50:56.064280 Final RX Vref Byte 0 = 52 to rank0
4563 06:50:56.067780 Final RX Vref Byte 1 = 53 to rank0
4564 06:50:56.071343 Final RX Vref Byte 0 = 52 to rank1
4565 06:50:56.074257 Final RX Vref Byte 1 = 53 to rank1==
4566 06:50:56.077777 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 06:50:56.081374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 06:50:56.081475 ==
4569 06:50:56.084195 DQS Delay:
4570 06:50:56.084307 DQS0 = 0, DQS1 = 0
4571 06:50:56.087806 DQM Delay:
4572 06:50:56.087877 DQM0 = 48, DQM1 = 44
4573 06:50:56.087948 DQ Delay:
4574 06:50:56.091276 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4575 06:50:56.094586 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4576 06:50:56.097844 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4577 06:50:56.101166 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4578 06:50:56.101246
4579 06:50:56.101311
4580 06:50:56.110904 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4581 06:50:56.114221 CH1 RK0: MR19=808, MR18=4A70
4582 06:50:56.120913 CH1_RK0: MR19=0x808, MR18=0x4A70, DQSOSC=388, MR23=63, INC=174, DEC=116
4583 06:50:56.121036
4584 06:50:56.124248 ----->DramcWriteLeveling(PI) begin...
4585 06:50:56.124343 ==
4586 06:50:56.127475 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 06:50:56.130547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 06:50:56.130646 ==
4589 06:50:56.134421 Write leveling (Byte 0): 28 => 28
4590 06:50:56.137284 Write leveling (Byte 1): 31 => 31
4591 06:50:56.140749 DramcWriteLeveling(PI) end<-----
4592 06:50:56.140824
4593 06:50:56.140907 ==
4594 06:50:56.144368 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 06:50:56.147272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 06:50:56.147371 ==
4597 06:50:56.150772 [Gating] SW mode calibration
4598 06:50:56.157409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4599 06:50:56.164301 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4600 06:50:56.167849 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 06:50:56.170701 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 06:50:56.177244 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 06:50:56.180819 0 9 12 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (1 1)
4604 06:50:56.184366 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
4605 06:50:56.190694 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 06:50:56.194298 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 06:50:56.197061 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 06:50:56.200542 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 06:50:56.207178 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 06:50:56.210570 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 06:50:56.214103 0 10 12 | B1->B0 | 3a3a 3737 | 1 0 | (0 0) (0 0)
4612 06:50:56.220656 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4613 06:50:56.224157 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 06:50:56.227496 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 06:50:56.234605 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 06:50:56.237154 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 06:50:56.240925 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 06:50:56.247563 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 06:50:56.250820 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4620 06:50:56.253669 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 06:50:56.260648 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 06:50:56.264107 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 06:50:56.267611 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 06:50:56.274143 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 06:50:56.277286 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 06:50:56.280263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 06:50:56.287280 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 06:50:56.290779 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 06:50:56.293613 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 06:50:56.300703 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 06:50:56.303454 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 06:50:56.306842 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 06:50:56.313691 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 06:50:56.317106 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4635 06:50:56.320573 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4636 06:50:56.323345 Total UI for P1: 0, mck2ui 16
4637 06:50:56.326774 best dqsien dly found for B1: ( 0, 13, 8)
4638 06:50:56.330298 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 06:50:56.333609 Total UI for P1: 0, mck2ui 16
4640 06:50:56.336764 best dqsien dly found for B0: ( 0, 13, 12)
4641 06:50:56.343423 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4642 06:50:56.346943 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4643 06:50:56.347016
4644 06:50:56.350575 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4645 06:50:56.353754 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4646 06:50:56.356912 [Gating] SW calibration Done
4647 06:50:56.356983 ==
4648 06:50:56.360072 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 06:50:56.363913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 06:50:56.363990 ==
4651 06:50:56.364052 RX Vref Scan: 0
4652 06:50:56.367214
4653 06:50:56.367290 RX Vref 0 -> 0, step: 1
4654 06:50:56.367353
4655 06:50:56.370640 RX Delay -230 -> 252, step: 16
4656 06:50:56.374134 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4657 06:50:56.377584 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4658 06:50:56.384278 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4659 06:50:56.387436 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4660 06:50:56.390808 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4661 06:50:56.394034 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4662 06:50:56.396887 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4663 06:50:56.403864 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4664 06:50:56.407453 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4665 06:50:56.410271 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4666 06:50:56.413710 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4667 06:50:56.420486 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4668 06:50:56.423881 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4669 06:50:56.426580 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4670 06:50:56.430053 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4671 06:50:56.436982 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4672 06:50:56.437094 ==
4673 06:50:56.439757 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 06:50:56.443221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 06:50:56.443333 ==
4676 06:50:56.443425 DQS Delay:
4677 06:50:56.446834 DQS0 = 0, DQS1 = 0
4678 06:50:56.446951 DQM Delay:
4679 06:50:56.450241 DQM0 = 50, DQM1 = 48
4680 06:50:56.450346 DQ Delay:
4681 06:50:56.453178 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4682 06:50:56.456385 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4683 06:50:56.459895 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4684 06:50:56.463459 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4685 06:50:56.463570
4686 06:50:56.463673
4687 06:50:56.463770 ==
4688 06:50:56.466644 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 06:50:56.470052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 06:50:56.473306 ==
4691 06:50:56.473382
4692 06:50:56.473455
4693 06:50:56.473533 TX Vref Scan disable
4694 06:50:56.476434 == TX Byte 0 ==
4695 06:50:56.479811 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4696 06:50:56.486157 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4697 06:50:56.486264 == TX Byte 1 ==
4698 06:50:56.489638 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4699 06:50:56.496498 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4700 06:50:56.496602 ==
4701 06:50:56.499815 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 06:50:56.503225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 06:50:56.503327 ==
4704 06:50:56.503420
4705 06:50:56.503513
4706 06:50:56.506393 TX Vref Scan disable
4707 06:50:56.509885 == TX Byte 0 ==
4708 06:50:56.512753 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4709 06:50:56.516123 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4710 06:50:56.519788 == TX Byte 1 ==
4711 06:50:56.523070 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4712 06:50:56.526348 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4713 06:50:56.526523
4714 06:50:56.526634 [DATLAT]
4715 06:50:56.529206 Freq=600, CH1 RK1
4716 06:50:56.529322
4717 06:50:56.529422 DATLAT Default: 0x9
4718 06:50:56.532605 0, 0xFFFF, sum = 0
4719 06:50:56.536122 1, 0xFFFF, sum = 0
4720 06:50:56.536232 2, 0xFFFF, sum = 0
4721 06:50:56.538953 3, 0xFFFF, sum = 0
4722 06:50:56.539055 4, 0xFFFF, sum = 0
4723 06:50:56.542334 5, 0xFFFF, sum = 0
4724 06:50:56.542438 6, 0xFFFF, sum = 0
4725 06:50:56.545837 7, 0xFFFF, sum = 0
4726 06:50:56.545939 8, 0x0, sum = 1
4727 06:50:56.549298 9, 0x0, sum = 2
4728 06:50:56.549416 10, 0x0, sum = 3
4729 06:50:56.552047 11, 0x0, sum = 4
4730 06:50:56.552153 best_step = 9
4731 06:50:56.552257
4732 06:50:56.552371 ==
4733 06:50:56.556040 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 06:50:56.559303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 06:50:56.559382 ==
4736 06:50:56.562449 RX Vref Scan: 0
4737 06:50:56.562554
4738 06:50:56.565869 RX Vref 0 -> 0, step: 1
4739 06:50:56.565974
4740 06:50:56.566072 RX Delay -163 -> 252, step: 8
4741 06:50:56.573585 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4742 06:50:56.576501 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4743 06:50:56.579879 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4744 06:50:56.583369 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4745 06:50:56.586727 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4746 06:50:56.593080 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4747 06:50:56.596536 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4748 06:50:56.600101 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4749 06:50:56.603585 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4750 06:50:56.606331 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4751 06:50:56.613464 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4752 06:50:56.616512 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4753 06:50:56.619757 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4754 06:50:56.623066 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4755 06:50:56.629744 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4756 06:50:56.633320 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4757 06:50:56.633426 ==
4758 06:50:56.636641 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 06:50:56.639926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 06:50:56.640032 ==
4761 06:50:56.643423 DQS Delay:
4762 06:50:56.643509 DQS0 = 0, DQS1 = 0
4763 06:50:56.643576 DQM Delay:
4764 06:50:56.646821 DQM0 = 48, DQM1 = 45
4765 06:50:56.646923 DQ Delay:
4766 06:50:56.650392 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4767 06:50:56.653243 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4768 06:50:56.656687 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4769 06:50:56.660119 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4770 06:50:56.660221
4771 06:50:56.660320
4772 06:50:56.670153 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4773 06:50:56.670264 CH1 RK1: MR19=808, MR18=6A21
4774 06:50:56.676490 CH1_RK1: MR19=0x808, MR18=0x6A21, DQSOSC=389, MR23=63, INC=173, DEC=115
4775 06:50:56.679816 [RxdqsGatingPostProcess] freq 600
4776 06:50:56.686708 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4777 06:50:56.690170 Pre-setting of DQS Precalculation
4778 06:50:56.693612 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4779 06:50:56.700057 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4780 06:50:56.706899 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4781 06:50:56.706981
4782 06:50:56.710363
4783 06:50:56.710439 [Calibration Summary] 1200 Mbps
4784 06:50:56.713194 CH 0, Rank 0
4785 06:50:56.713266 SW Impedance : PASS
4786 06:50:56.716655 DUTY Scan : NO K
4787 06:50:56.720173 ZQ Calibration : PASS
4788 06:50:56.720273 Jitter Meter : NO K
4789 06:50:56.723432 CBT Training : PASS
4790 06:50:56.726799 Write leveling : PASS
4791 06:50:56.726876 RX DQS gating : PASS
4792 06:50:56.730082 RX DQ/DQS(RDDQC) : PASS
4793 06:50:56.733236 TX DQ/DQS : PASS
4794 06:50:56.733349 RX DATLAT : PASS
4795 06:50:56.736616 RX DQ/DQS(Engine): PASS
4796 06:50:56.739781 TX OE : NO K
4797 06:50:56.739862 All Pass.
4798 06:50:56.739985
4799 06:50:56.740073 CH 0, Rank 1
4800 06:50:56.743103 SW Impedance : PASS
4801 06:50:56.746452 DUTY Scan : NO K
4802 06:50:56.746537 ZQ Calibration : PASS
4803 06:50:56.749814 Jitter Meter : NO K
4804 06:50:56.749893 CBT Training : PASS
4805 06:50:56.753336 Write leveling : PASS
4806 06:50:56.756892 RX DQS gating : PASS
4807 06:50:56.756968 RX DQ/DQS(RDDQC) : PASS
4808 06:50:56.759688 TX DQ/DQS : PASS
4809 06:50:56.763126 RX DATLAT : PASS
4810 06:50:56.763227 RX DQ/DQS(Engine): PASS
4811 06:50:56.766758 TX OE : NO K
4812 06:50:56.766857 All Pass.
4813 06:50:56.766950
4814 06:50:56.770234 CH 1, Rank 0
4815 06:50:56.770313 SW Impedance : PASS
4816 06:50:56.773030 DUTY Scan : NO K
4817 06:50:56.776497 ZQ Calibration : PASS
4818 06:50:56.776576 Jitter Meter : NO K
4819 06:50:56.779913 CBT Training : PASS
4820 06:50:56.783256 Write leveling : PASS
4821 06:50:56.783356 RX DQS gating : PASS
4822 06:50:56.786533 RX DQ/DQS(RDDQC) : PASS
4823 06:50:56.789730 TX DQ/DQS : PASS
4824 06:50:56.789807 RX DATLAT : PASS
4825 06:50:56.792783 RX DQ/DQS(Engine): PASS
4826 06:50:56.796678 TX OE : NO K
4827 06:50:56.796785 All Pass.
4828 06:50:56.796881
4829 06:50:56.796945 CH 1, Rank 1
4830 06:50:56.799497 SW Impedance : PASS
4831 06:50:56.803051 DUTY Scan : NO K
4832 06:50:56.803165 ZQ Calibration : PASS
4833 06:50:56.806469 Jitter Meter : NO K
4834 06:50:56.806567 CBT Training : PASS
4835 06:50:56.809732 Write leveling : PASS
4836 06:50:56.812858 RX DQS gating : PASS
4837 06:50:56.812956 RX DQ/DQS(RDDQC) : PASS
4838 06:50:56.815929 TX DQ/DQS : PASS
4839 06:50:56.819276 RX DATLAT : PASS
4840 06:50:56.819394 RX DQ/DQS(Engine): PASS
4841 06:50:56.822763 TX OE : NO K
4842 06:50:56.822873 All Pass.
4843 06:50:56.822995
4844 06:50:56.826297 DramC Write-DBI off
4845 06:50:56.829762 PER_BANK_REFRESH: Hybrid Mode
4846 06:50:56.829860 TX_TRACKING: ON
4847 06:50:56.839679 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4848 06:50:56.842398 [FAST_K] Save calibration result to emmc
4849 06:50:56.845733 dramc_set_vcore_voltage set vcore to 662500
4850 06:50:56.849412 Read voltage for 933, 3
4851 06:50:56.849534 Vio18 = 0
4852 06:50:56.849642 Vcore = 662500
4853 06:50:56.852614 Vdram = 0
4854 06:50:56.852722 Vddq = 0
4855 06:50:56.852832 Vmddr = 0
4856 06:50:56.859032 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4857 06:50:56.862532 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4858 06:50:56.866267 MEM_TYPE=3, freq_sel=17
4859 06:50:56.868960 sv_algorithm_assistance_LP4_1600
4860 06:50:56.872421 ============ PULL DRAM RESETB DOWN ============
4861 06:50:56.875859 ========== PULL DRAM RESETB DOWN end =========
4862 06:50:56.882839 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4863 06:50:56.885698 ===================================
4864 06:50:56.889320 LPDDR4 DRAM CONFIGURATION
4865 06:50:56.892799 ===================================
4866 06:50:56.892895 EX_ROW_EN[0] = 0x0
4867 06:50:56.895979 EX_ROW_EN[1] = 0x0
4868 06:50:56.896066 LP4Y_EN = 0x0
4869 06:50:56.899305 WORK_FSP = 0x0
4870 06:50:56.899422 WL = 0x3
4871 06:50:56.902612 RL = 0x3
4872 06:50:56.902686 BL = 0x2
4873 06:50:56.905769 RPST = 0x0
4874 06:50:56.905874 RD_PRE = 0x0
4875 06:50:56.909165 WR_PRE = 0x1
4876 06:50:56.909240 WR_PST = 0x0
4877 06:50:56.912649 DBI_WR = 0x0
4878 06:50:56.912720 DBI_RD = 0x0
4879 06:50:56.915388 OTF = 0x1
4880 06:50:56.918702 ===================================
4881 06:50:56.922573 ===================================
4882 06:50:56.922673 ANA top config
4883 06:50:56.925741 ===================================
4884 06:50:56.929025 DLL_ASYNC_EN = 0
4885 06:50:56.932410 ALL_SLAVE_EN = 1
4886 06:50:56.935909 NEW_RANK_MODE = 1
4887 06:50:56.936048 DLL_IDLE_MODE = 1
4888 06:50:56.938852 LP45_APHY_COMB_EN = 1
4889 06:50:56.942420 TX_ODT_DIS = 1
4890 06:50:56.946029 NEW_8X_MODE = 1
4891 06:50:56.948823 ===================================
4892 06:50:56.952264 ===================================
4893 06:50:56.955854 data_rate = 1866
4894 06:50:56.955997 CKR = 1
4895 06:50:56.958866 DQ_P2S_RATIO = 8
4896 06:50:56.962322 ===================================
4897 06:50:56.965702 CA_P2S_RATIO = 8
4898 06:50:56.969140 DQ_CA_OPEN = 0
4899 06:50:56.972429 DQ_SEMI_OPEN = 0
4900 06:50:56.975476 CA_SEMI_OPEN = 0
4901 06:50:56.975556 CA_FULL_RATE = 0
4902 06:50:56.979167 DQ_CKDIV4_EN = 1
4903 06:50:56.982091 CA_CKDIV4_EN = 1
4904 06:50:56.985228 CA_PREDIV_EN = 0
4905 06:50:56.988747 PH8_DLY = 0
4906 06:50:56.992032 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4907 06:50:56.992152 DQ_AAMCK_DIV = 4
4908 06:50:56.995490 CA_AAMCK_DIV = 4
4909 06:50:56.999011 CA_ADMCK_DIV = 4
4910 06:50:57.002420 DQ_TRACK_CA_EN = 0
4911 06:50:57.005165 CA_PICK = 933
4912 06:50:57.008621 CA_MCKIO = 933
4913 06:50:57.012040 MCKIO_SEMI = 0
4914 06:50:57.012111 PLL_FREQ = 3732
4915 06:50:57.015204 DQ_UI_PI_RATIO = 32
4916 06:50:57.019035 CA_UI_PI_RATIO = 0
4917 06:50:57.021825 ===================================
4918 06:50:57.025252 ===================================
4919 06:50:57.028649 memory_type:LPDDR4
4920 06:50:57.028751 GP_NUM : 10
4921 06:50:57.032072 SRAM_EN : 1
4922 06:50:57.035287 MD32_EN : 0
4923 06:50:57.038526 ===================================
4924 06:50:57.038603 [ANA_INIT] >>>>>>>>>>>>>>
4925 06:50:57.041806 <<<<<< [CONFIGURE PHASE]: ANA_TX
4926 06:50:57.045432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4927 06:50:57.048225 ===================================
4928 06:50:57.051750 data_rate = 1866,PCW = 0X8f00
4929 06:50:57.055252 ===================================
4930 06:50:57.058731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4931 06:50:57.065174 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 06:50:57.068692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 06:50:57.074865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4934 06:50:57.078293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4935 06:50:57.081637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4936 06:50:57.081722 [ANA_INIT] flow start
4937 06:50:57.085024 [ANA_INIT] PLL >>>>>>>>
4938 06:50:57.088485 [ANA_INIT] PLL <<<<<<<<
4939 06:50:57.092036 [ANA_INIT] MIDPI >>>>>>>>
4940 06:50:57.092108 [ANA_INIT] MIDPI <<<<<<<<
4941 06:50:57.095385 [ANA_INIT] DLL >>>>>>>>
4942 06:50:57.098128 [ANA_INIT] flow end
4943 06:50:57.101392 ============ LP4 DIFF to SE enter ============
4944 06:50:57.105053 ============ LP4 DIFF to SE exit ============
4945 06:50:57.108057 [ANA_INIT] <<<<<<<<<<<<<
4946 06:50:57.111750 [Flow] Enable top DCM control >>>>>
4947 06:50:57.114867 [Flow] Enable top DCM control <<<<<
4948 06:50:57.118627 Enable DLL master slave shuffle
4949 06:50:57.121273 ==============================================================
4950 06:50:57.124606 Gating Mode config
4951 06:50:57.131806 ==============================================================
4952 06:50:57.131887 Config description:
4953 06:50:57.141627 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4954 06:50:57.148231 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4955 06:50:57.151537 SELPH_MODE 0: By rank 1: By Phase
4956 06:50:57.158576 ==============================================================
4957 06:50:57.161391 GAT_TRACK_EN = 1
4958 06:50:57.164936 RX_GATING_MODE = 2
4959 06:50:57.167789 RX_GATING_TRACK_MODE = 2
4960 06:50:57.171320 SELPH_MODE = 1
4961 06:50:57.174765 PICG_EARLY_EN = 1
4962 06:50:57.178363 VALID_LAT_VALUE = 1
4963 06:50:57.181123 ==============================================================
4964 06:50:57.184471 Enter into Gating configuration >>>>
4965 06:50:57.187911 Exit from Gating configuration <<<<
4966 06:50:57.191284 Enter into DVFS_PRE_config >>>>>
4967 06:50:57.201150 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4968 06:50:57.204615 Exit from DVFS_PRE_config <<<<<
4969 06:50:57.208145 Enter into PICG configuration >>>>
4970 06:50:57.210926 Exit from PICG configuration <<<<
4971 06:50:57.214257 [RX_INPUT] configuration >>>>>
4972 06:50:57.217664 [RX_INPUT] configuration <<<<<
4973 06:50:57.224120 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4974 06:50:57.227889 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4975 06:50:57.234163 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 06:50:57.241071 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 06:50:57.247406 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 06:50:57.254272 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 06:50:57.257650 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4980 06:50:57.260675 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4981 06:50:57.263808 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4982 06:50:57.271142 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4983 06:50:57.273834 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4984 06:50:57.277312 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4985 06:50:57.280808 ===================================
4986 06:50:57.284406 LPDDR4 DRAM CONFIGURATION
4987 06:50:57.287168 ===================================
4988 06:50:57.287267 EX_ROW_EN[0] = 0x0
4989 06:50:57.290685 EX_ROW_EN[1] = 0x0
4990 06:50:57.293979 LP4Y_EN = 0x0
4991 06:50:57.294085 WORK_FSP = 0x0
4992 06:50:57.297490 WL = 0x3
4993 06:50:57.297576 RL = 0x3
4994 06:50:57.300275 BL = 0x2
4995 06:50:57.300380 RPST = 0x0
4996 06:50:57.303910 RD_PRE = 0x0
4997 06:50:57.304008 WR_PRE = 0x1
4998 06:50:57.307335 WR_PST = 0x0
4999 06:50:57.307415 DBI_WR = 0x0
5000 06:50:57.310812 DBI_RD = 0x0
5001 06:50:57.310911 OTF = 0x1
5002 06:50:57.314222 ===================================
5003 06:50:57.317080 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5004 06:50:57.323976 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5005 06:50:57.327469 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 06:50:57.330272 ===================================
5007 06:50:57.333612 LPDDR4 DRAM CONFIGURATION
5008 06:50:57.337002 ===================================
5009 06:50:57.337108 EX_ROW_EN[0] = 0x10
5010 06:50:57.340395 EX_ROW_EN[1] = 0x0
5011 06:50:57.343280 LP4Y_EN = 0x0
5012 06:50:57.343357 WORK_FSP = 0x0
5013 06:50:57.346910 WL = 0x3
5014 06:50:57.346989 RL = 0x3
5015 06:50:57.350343 BL = 0x2
5016 06:50:57.350415 RPST = 0x0
5017 06:50:57.353681 RD_PRE = 0x0
5018 06:50:57.353756 WR_PRE = 0x1
5019 06:50:57.356700 WR_PST = 0x0
5020 06:50:57.356773 DBI_WR = 0x0
5021 06:50:57.360411 DBI_RD = 0x0
5022 06:50:57.360488 OTF = 0x1
5023 06:50:57.363600 ===================================
5024 06:50:57.370305 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5025 06:50:57.374410 nWR fixed to 30
5026 06:50:57.377528 [ModeRegInit_LP4] CH0 RK0
5027 06:50:57.377613 [ModeRegInit_LP4] CH0 RK1
5028 06:50:57.381111 [ModeRegInit_LP4] CH1 RK0
5029 06:50:57.384337 [ModeRegInit_LP4] CH1 RK1
5030 06:50:57.384411 match AC timing 9
5031 06:50:57.391032 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5032 06:50:57.394650 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5033 06:50:57.397868 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5034 06:50:57.404118 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5035 06:50:57.407558 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5036 06:50:57.407632 ==
5037 06:50:57.411036 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 06:50:57.414611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 06:50:57.414694 ==
5040 06:50:57.420953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 06:50:57.427774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5042 06:50:57.430654 [CA 0] Center 37 (6~68) winsize 63
5043 06:50:57.434249 [CA 1] Center 37 (6~68) winsize 63
5044 06:50:57.437834 [CA 2] Center 34 (4~65) winsize 62
5045 06:50:57.440584 [CA 3] Center 34 (3~65) winsize 63
5046 06:50:57.443938 [CA 4] Center 33 (3~64) winsize 62
5047 06:50:57.447247 [CA 5] Center 32 (2~62) winsize 61
5048 06:50:57.447333
5049 06:50:57.450633 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5050 06:50:57.450706
5051 06:50:57.454094 [CATrainingPosCal] consider 1 rank data
5052 06:50:57.457644 u2DelayCellTimex100 = 270/100 ps
5053 06:50:57.461119 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5054 06:50:57.463774 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5055 06:50:57.467223 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5056 06:50:57.470497 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5057 06:50:57.473935 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5058 06:50:57.477512 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5059 06:50:57.480950
5060 06:50:57.484352 CA PerBit enable=1, Macro0, CA PI delay=32
5061 06:50:57.484428
5062 06:50:57.486963 [CBTSetCACLKResult] CA Dly = 32
5063 06:50:57.487043 CS Dly: 5 (0~36)
5064 06:50:57.487107 ==
5065 06:50:57.490329 Dram Type= 6, Freq= 0, CH_0, rank 1
5066 06:50:57.494431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5067 06:50:57.494515 ==
5068 06:50:57.500457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5069 06:50:57.507092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5070 06:50:57.510567 [CA 0] Center 37 (6~68) winsize 63
5071 06:50:57.514259 [CA 1] Center 37 (6~68) winsize 63
5072 06:50:57.517351 [CA 2] Center 34 (4~65) winsize 62
5073 06:50:57.520441 [CA 3] Center 34 (3~65) winsize 63
5074 06:50:57.524348 [CA 4] Center 32 (2~63) winsize 62
5075 06:50:57.527137 [CA 5] Center 32 (2~62) winsize 61
5076 06:50:57.527236
5077 06:50:57.530442 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5078 06:50:57.530515
5079 06:50:57.534116 [CATrainingPosCal] consider 2 rank data
5080 06:50:57.536889 u2DelayCellTimex100 = 270/100 ps
5081 06:50:57.540446 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5082 06:50:57.544052 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5083 06:50:57.546821 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5084 06:50:57.550269 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5085 06:50:57.556893 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5086 06:50:57.560368 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5087 06:50:57.560505
5088 06:50:57.563852 CA PerBit enable=1, Macro0, CA PI delay=32
5089 06:50:57.563948
5090 06:50:57.566587 [CBTSetCACLKResult] CA Dly = 32
5091 06:50:57.566677 CS Dly: 5 (0~37)
5092 06:50:57.566743
5093 06:50:57.569999 ----->DramcWriteLeveling(PI) begin...
5094 06:50:57.570091 ==
5095 06:50:57.573541 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 06:50:57.580157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 06:50:57.580245 ==
5098 06:50:57.583492 Write leveling (Byte 0): 31 => 31
5099 06:50:57.586965 Write leveling (Byte 1): 30 => 30
5100 06:50:57.587050 DramcWriteLeveling(PI) end<-----
5101 06:50:57.587117
5102 06:50:57.590440 ==
5103 06:50:57.593212 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 06:50:57.596733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 06:50:57.596818 ==
5106 06:50:57.600168 [Gating] SW mode calibration
5107 06:50:57.606412 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5108 06:50:57.609765 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5109 06:50:57.616640 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5110 06:50:57.619893 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 06:50:57.623324 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 06:50:57.629970 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 06:50:57.633142 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 06:50:57.636380 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 06:50:57.643318 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5116 06:50:57.646215 0 14 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
5117 06:50:57.649609 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5118 06:50:57.656527 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 06:50:57.660018 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 06:50:57.663270 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 06:50:57.670109 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 06:50:57.673579 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 06:50:57.676534 0 15 24 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
5124 06:50:57.679762 0 15 28 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
5125 06:50:57.686726 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5126 06:50:57.690096 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 06:50:57.693429 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 06:50:57.700077 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 06:50:57.703442 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 06:50:57.706837 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 06:50:57.713245 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5132 06:50:57.716686 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5133 06:50:57.720311 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5134 06:50:57.726904 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 06:50:57.729712 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 06:50:57.733063 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 06:50:57.740127 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 06:50:57.743528 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 06:50:57.746491 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 06:50:57.753354 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 06:50:57.756663 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 06:50:57.760185 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 06:50:57.766486 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 06:50:57.769904 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 06:50:57.773283 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 06:50:57.776524 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 06:50:57.783511 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5148 06:50:57.786480 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5149 06:50:57.790054 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5150 06:50:57.793536 Total UI for P1: 0, mck2ui 16
5151 06:50:57.796408 best dqsien dly found for B0: ( 1, 2, 26)
5152 06:50:57.803292 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 06:50:57.803377 Total UI for P1: 0, mck2ui 16
5154 06:50:57.809899 best dqsien dly found for B1: ( 1, 2, 30)
5155 06:50:57.813219 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5156 06:50:57.816722 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5157 06:50:57.816808
5158 06:50:57.819485 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5159 06:50:57.823159 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5160 06:50:57.826725 [Gating] SW calibration Done
5161 06:50:57.826799 ==
5162 06:50:57.829472 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 06:50:57.833432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 06:50:57.833508 ==
5165 06:50:57.836023 RX Vref Scan: 0
5166 06:50:57.836105
5167 06:50:57.836168 RX Vref 0 -> 0, step: 1
5168 06:50:57.839818
5169 06:50:57.839891 RX Delay -80 -> 252, step: 8
5170 06:50:57.846181 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5171 06:50:57.849670 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5172 06:50:57.853327 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5173 06:50:57.856040 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5174 06:50:57.859656 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5175 06:50:57.862880 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5176 06:50:57.869837 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5177 06:50:57.873107 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5178 06:50:57.875871 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5179 06:50:57.879364 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5180 06:50:57.882807 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5181 06:50:57.886243 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5182 06:50:57.892515 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5183 06:50:57.895951 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5184 06:50:57.899450 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5185 06:50:57.903148 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5186 06:50:57.903225 ==
5187 06:50:57.905886 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 06:50:57.909260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 06:50:57.909341 ==
5190 06:50:57.912644 DQS Delay:
5191 06:50:57.912719 DQS0 = 0, DQS1 = 0
5192 06:50:57.915837 DQM Delay:
5193 06:50:57.915911 DQM0 = 104, DQM1 = 93
5194 06:50:57.915975 DQ Delay:
5195 06:50:57.919300 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5196 06:50:57.926074 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5197 06:50:57.929601 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5198 06:50:57.932399 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5199 06:50:57.932484
5200 06:50:57.932551
5201 06:50:57.932613 ==
5202 06:50:57.935934 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 06:50:57.938858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 06:50:57.938943 ==
5205 06:50:57.939010
5206 06:50:57.939072
5207 06:50:57.942325 TX Vref Scan disable
5208 06:50:57.942409 == TX Byte 0 ==
5209 06:50:57.949316 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5210 06:50:57.952626 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5211 06:50:57.952712 == TX Byte 1 ==
5212 06:50:57.959509 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5213 06:50:57.962324 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5214 06:50:57.962410 ==
5215 06:50:57.965773 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 06:50:57.969448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 06:50:57.969533 ==
5218 06:50:57.969599
5219 06:50:57.969660
5220 06:50:57.972203 TX Vref Scan disable
5221 06:50:57.976131 == TX Byte 0 ==
5222 06:50:57.979415 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5223 06:50:57.982591 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5224 06:50:57.985821 == TX Byte 1 ==
5225 06:50:57.989100 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5226 06:50:57.992422 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5227 06:50:57.992510
5228 06:50:57.995651 [DATLAT]
5229 06:50:57.995754 Freq=933, CH0 RK0
5230 06:50:57.995846
5231 06:50:57.999057 DATLAT Default: 0xd
5232 06:50:57.999165 0, 0xFFFF, sum = 0
5233 06:50:58.002634 1, 0xFFFF, sum = 0
5234 06:50:58.002721 2, 0xFFFF, sum = 0
5235 06:50:58.005404 3, 0xFFFF, sum = 0
5236 06:50:58.005492 4, 0xFFFF, sum = 0
5237 06:50:58.008923 5, 0xFFFF, sum = 0
5238 06:50:58.008998 6, 0xFFFF, sum = 0
5239 06:50:58.012323 7, 0xFFFF, sum = 0
5240 06:50:58.012398 8, 0xFFFF, sum = 0
5241 06:50:58.015713 9, 0xFFFF, sum = 0
5242 06:50:58.015798 10, 0x0, sum = 1
5243 06:50:58.019106 11, 0x0, sum = 2
5244 06:50:58.019191 12, 0x0, sum = 3
5245 06:50:58.022538 13, 0x0, sum = 4
5246 06:50:58.022623 best_step = 11
5247 06:50:58.022690
5248 06:50:58.022751 ==
5249 06:50:58.025446 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 06:50:58.032368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 06:50:58.032452 ==
5252 06:50:58.032540 RX Vref Scan: 1
5253 06:50:58.032604
5254 06:50:58.035764 RX Vref 0 -> 0, step: 1
5255 06:50:58.035847
5256 06:50:58.039010 RX Delay -53 -> 252, step: 4
5257 06:50:58.039093
5258 06:50:58.042458 Set Vref, RX VrefLevel [Byte0]: 55
5259 06:50:58.045327 [Byte1]: 53
5260 06:50:58.045410
5261 06:50:58.048772 Final RX Vref Byte 0 = 55 to rank0
5262 06:50:58.052226 Final RX Vref Byte 1 = 53 to rank0
5263 06:50:58.055550 Final RX Vref Byte 0 = 55 to rank1
5264 06:50:58.058887 Final RX Vref Byte 1 = 53 to rank1==
5265 06:50:58.062412 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 06:50:58.065190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 06:50:58.065274 ==
5268 06:50:58.068643 DQS Delay:
5269 06:50:58.068727 DQS0 = 0, DQS1 = 0
5270 06:50:58.068793 DQM Delay:
5271 06:50:58.072139 DQM0 = 104, DQM1 = 97
5272 06:50:58.072222 DQ Delay:
5273 06:50:58.075627 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5274 06:50:58.079166 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5275 06:50:58.081877 DQ8 =88, DQ9 =90, DQ10 =96, DQ11 =92
5276 06:50:58.088585 DQ12 =102, DQ13 =102, DQ14 =106, DQ15 =104
5277 06:50:58.088665
5278 06:50:58.088747
5279 06:50:58.095142 [DQSOSCAuto] RK0, (LSB)MR18= 0x342c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5280 06:50:58.098456 CH0 RK0: MR19=505, MR18=342C
5281 06:50:58.105475 CH0_RK0: MR19=0x505, MR18=0x342C, DQSOSC=405, MR23=63, INC=66, DEC=44
5282 06:50:58.105555
5283 06:50:58.108620 ----->DramcWriteLeveling(PI) begin...
5284 06:50:58.108716 ==
5285 06:50:58.112050 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 06:50:58.115548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 06:50:58.115644 ==
5288 06:50:58.118352 Write leveling (Byte 0): 33 => 33
5289 06:50:58.121980 Write leveling (Byte 1): 28 => 28
5290 06:50:58.125431 DramcWriteLeveling(PI) end<-----
5291 06:50:58.125506
5292 06:50:58.125570 ==
5293 06:50:58.129029 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 06:50:58.131734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 06:50:58.131826 ==
5296 06:50:58.135379 [Gating] SW mode calibration
5297 06:50:58.142290 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5298 06:50:58.148448 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5299 06:50:58.151654 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5300 06:50:58.155093 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 06:50:58.162312 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 06:50:58.165036 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 06:50:58.168389 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 06:50:58.175371 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 06:50:58.178199 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5306 06:50:58.181828 0 14 28 | B1->B0 | 2929 2b2b | 0 1 | (0 0) (1 0)
5307 06:50:58.188152 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5308 06:50:58.191653 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 06:50:58.195267 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 06:50:58.201704 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 06:50:58.205115 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 06:50:58.208482 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 06:50:58.215072 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5314 06:50:58.218246 0 15 28 | B1->B0 | 3a3a 3535 | 0 1 | (0 0) (0 0)
5315 06:50:58.221536 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5316 06:50:58.228043 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 06:50:58.231362 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 06:50:58.234985 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 06:50:58.241921 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 06:50:58.244749 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 06:50:58.248271 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 06:50:58.255157 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5323 06:50:58.258022 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5324 06:50:58.261399 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 06:50:58.267917 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 06:50:58.271719 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 06:50:58.274839 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 06:50:58.278242 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 06:50:58.284745 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 06:50:58.288346 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 06:50:58.291851 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 06:50:58.298145 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 06:50:58.301736 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 06:50:58.305139 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 06:50:58.311745 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 06:50:58.314618 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 06:50:58.318132 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5338 06:50:58.324987 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5339 06:50:58.328216 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 06:50:58.331949 Total UI for P1: 0, mck2ui 16
5341 06:50:58.335192 best dqsien dly found for B0: ( 1, 2, 26)
5342 06:50:58.338360 Total UI for P1: 0, mck2ui 16
5343 06:50:58.341436 best dqsien dly found for B1: ( 1, 2, 28)
5344 06:50:58.344833 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5345 06:50:58.348404 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5346 06:50:58.348507
5347 06:50:58.351890 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5348 06:50:58.354814 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5349 06:50:58.358324 [Gating] SW calibration Done
5350 06:50:58.358400 ==
5351 06:50:58.361859 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 06:50:58.364679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 06:50:58.364765 ==
5354 06:50:58.368142 RX Vref Scan: 0
5355 06:50:58.368240
5356 06:50:58.371572 RX Vref 0 -> 0, step: 1
5357 06:50:58.371642
5358 06:50:58.371702 RX Delay -80 -> 252, step: 8
5359 06:50:58.378453 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5360 06:50:58.381674 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5361 06:50:58.384814 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5362 06:50:58.388111 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5363 06:50:58.391399 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5364 06:50:58.394700 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5365 06:50:58.401550 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5366 06:50:58.405152 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5367 06:50:58.407897 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5368 06:50:58.411436 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5369 06:50:58.414911 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5370 06:50:58.421573 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5371 06:50:58.424450 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5372 06:50:58.427967 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5373 06:50:58.431453 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5374 06:50:58.434963 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5375 06:50:58.435075 ==
5376 06:50:58.438181 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 06:50:58.444740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 06:50:58.444851 ==
5379 06:50:58.444970 DQS Delay:
5380 06:50:58.445078 DQS0 = 0, DQS1 = 0
5381 06:50:58.448156 DQM Delay:
5382 06:50:58.448276 DQM0 = 104, DQM1 = 94
5383 06:50:58.451473 DQ Delay:
5384 06:50:58.454639 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5385 06:50:58.457945 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5386 06:50:58.461349 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5387 06:50:58.464880 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5388 06:50:58.464996
5389 06:50:58.465095
5390 06:50:58.465199 ==
5391 06:50:58.467752 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 06:50:58.471207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 06:50:58.471314 ==
5394 06:50:58.471428
5395 06:50:58.471519
5396 06:50:58.474660 TX Vref Scan disable
5397 06:50:58.478172 == TX Byte 0 ==
5398 06:50:58.480979 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5399 06:50:58.484380 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5400 06:50:58.487854 == TX Byte 1 ==
5401 06:50:58.491244 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5402 06:50:58.494640 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5403 06:50:58.494730 ==
5404 06:50:58.497918 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 06:50:58.501200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 06:50:58.504244 ==
5407 06:50:58.504334
5408 06:50:58.504415
5409 06:50:58.504487 TX Vref Scan disable
5410 06:50:58.508298 == TX Byte 0 ==
5411 06:50:58.511728 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5412 06:50:58.517904 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5413 06:50:58.517982 == TX Byte 1 ==
5414 06:50:58.521333 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5415 06:50:58.528026 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5416 06:50:58.528113
5417 06:50:58.528187 [DATLAT]
5418 06:50:58.528256 Freq=933, CH0 RK1
5419 06:50:58.528324
5420 06:50:58.531329 DATLAT Default: 0xb
5421 06:50:58.531416 0, 0xFFFF, sum = 0
5422 06:50:58.534862 1, 0xFFFF, sum = 0
5423 06:50:58.534944 2, 0xFFFF, sum = 0
5424 06:50:58.537682 3, 0xFFFF, sum = 0
5425 06:50:58.541040 4, 0xFFFF, sum = 0
5426 06:50:58.541128 5, 0xFFFF, sum = 0
5427 06:50:58.544627 6, 0xFFFF, sum = 0
5428 06:50:58.544714 7, 0xFFFF, sum = 0
5429 06:50:58.548052 8, 0xFFFF, sum = 0
5430 06:50:58.548141 9, 0xFFFF, sum = 0
5431 06:50:58.551455 10, 0x0, sum = 1
5432 06:50:58.551548 11, 0x0, sum = 2
5433 06:50:58.551615 12, 0x0, sum = 3
5434 06:50:58.554879 13, 0x0, sum = 4
5435 06:50:58.554958 best_step = 11
5436 06:50:58.555036
5437 06:50:58.557656 ==
5438 06:50:58.557739 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 06:50:58.564780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 06:50:58.564860 ==
5441 06:50:58.564936 RX Vref Scan: 0
5442 06:50:58.565010
5443 06:50:58.568043 RX Vref 0 -> 0, step: 1
5444 06:50:58.568129
5445 06:50:58.571459 RX Delay -45 -> 252, step: 4
5446 06:50:58.574360 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5447 06:50:58.581387 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5448 06:50:58.584786 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5449 06:50:58.587684 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5450 06:50:58.591157 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5451 06:50:58.594484 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5452 06:50:58.601312 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5453 06:50:58.604741 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5454 06:50:58.607637 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5455 06:50:58.611051 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5456 06:50:58.614386 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5457 06:50:58.617625 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5458 06:50:58.624824 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5459 06:50:58.627592 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5460 06:50:58.631049 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5461 06:50:58.634481 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5462 06:50:58.634557 ==
5463 06:50:58.637994 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 06:50:58.644341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 06:50:58.644458 ==
5466 06:50:58.644563 DQS Delay:
5467 06:50:58.644647 DQS0 = 0, DQS1 = 0
5468 06:50:58.647792 DQM Delay:
5469 06:50:58.647900 DQM0 = 104, DQM1 = 95
5470 06:50:58.651249 DQ Delay:
5471 06:50:58.654676 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =102
5472 06:50:58.658139 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5473 06:50:58.660767 DQ8 =88, DQ9 =86, DQ10 =94, DQ11 =88
5474 06:50:58.664268 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =102
5475 06:50:58.664382
5476 06:50:58.664476
5477 06:50:58.671189 [DQSOSCAuto] RK1, (LSB)MR18= 0x2801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5478 06:50:58.674443 CH0 RK1: MR19=505, MR18=2801
5479 06:50:58.681189 CH0_RK1: MR19=0x505, MR18=0x2801, DQSOSC=409, MR23=63, INC=64, DEC=43
5480 06:50:58.684576 [RxdqsGatingPostProcess] freq 933
5481 06:50:58.690911 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5482 06:50:58.690991 best DQS0 dly(2T, 0.5T) = (0, 10)
5483 06:50:58.694278 best DQS1 dly(2T, 0.5T) = (0, 10)
5484 06:50:58.697786 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5485 06:50:58.701107 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5486 06:50:58.704666 best DQS0 dly(2T, 0.5T) = (0, 10)
5487 06:50:58.707558 best DQS1 dly(2T, 0.5T) = (0, 10)
5488 06:50:58.711045 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5489 06:50:58.714551 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5490 06:50:58.717403 Pre-setting of DQS Precalculation
5491 06:50:58.720903 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5492 06:50:58.724421 ==
5493 06:50:58.727775 Dram Type= 6, Freq= 0, CH_1, rank 0
5494 06:50:58.731150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 06:50:58.731225 ==
5496 06:50:58.734356 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5497 06:50:58.740675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5498 06:50:58.744437 [CA 0] Center 36 (6~67) winsize 62
5499 06:50:58.747741 [CA 1] Center 37 (6~68) winsize 63
5500 06:50:58.751066 [CA 2] Center 35 (5~65) winsize 61
5501 06:50:58.754379 [CA 3] Center 34 (4~65) winsize 62
5502 06:50:58.757902 [CA 4] Center 34 (4~64) winsize 61
5503 06:50:58.761477 [CA 5] Center 33 (3~64) winsize 62
5504 06:50:58.761565
5505 06:50:58.764766 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5506 06:50:58.764851
5507 06:50:58.767604 [CATrainingPosCal] consider 1 rank data
5508 06:50:58.771276 u2DelayCellTimex100 = 270/100 ps
5509 06:50:58.774156 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5510 06:50:58.781121 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5511 06:50:58.784538 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5512 06:50:58.787784 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5513 06:50:58.791280 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5514 06:50:58.794734 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5515 06:50:58.794830
5516 06:50:58.797663 CA PerBit enable=1, Macro0, CA PI delay=33
5517 06:50:58.797761
5518 06:50:58.800902 [CBTSetCACLKResult] CA Dly = 33
5519 06:50:58.800986 CS Dly: 6 (0~37)
5520 06:50:58.804371 ==
5521 06:50:58.807588 Dram Type= 6, Freq= 0, CH_1, rank 1
5522 06:50:58.811136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 06:50:58.811236 ==
5524 06:50:58.814696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 06:50:58.821141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5526 06:50:58.824722 [CA 0] Center 36 (6~67) winsize 62
5527 06:50:58.828181 [CA 1] Center 37 (6~68) winsize 63
5528 06:50:58.831125 [CA 2] Center 35 (5~66) winsize 62
5529 06:50:58.834445 [CA 3] Center 34 (4~65) winsize 62
5530 06:50:58.837873 [CA 4] Center 34 (4~65) winsize 62
5531 06:50:58.841451 [CA 5] Center 34 (4~64) winsize 61
5532 06:50:58.841557
5533 06:50:58.844922 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5534 06:50:58.845022
5535 06:50:58.848350 [CATrainingPosCal] consider 2 rank data
5536 06:50:58.851584 u2DelayCellTimex100 = 270/100 ps
5537 06:50:58.854751 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5538 06:50:58.857895 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5539 06:50:58.864731 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5540 06:50:58.867880 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5541 06:50:58.871720 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5542 06:50:58.874935 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5543 06:50:58.875009
5544 06:50:58.878186 CA PerBit enable=1, Macro0, CA PI delay=34
5545 06:50:58.878287
5546 06:50:58.881690 [CBTSetCACLKResult] CA Dly = 34
5547 06:50:58.881764 CS Dly: 7 (0~40)
5548 06:50:58.881827
5549 06:50:58.884476 ----->DramcWriteLeveling(PI) begin...
5550 06:50:58.888080 ==
5551 06:50:58.891555 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 06:50:58.894823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 06:50:58.894895 ==
5554 06:50:58.897922 Write leveling (Byte 0): 25 => 25
5555 06:50:58.901282 Write leveling (Byte 1): 29 => 29
5556 06:50:58.904597 DramcWriteLeveling(PI) end<-----
5557 06:50:58.904707
5558 06:50:58.904824 ==
5559 06:50:58.908071 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 06:50:58.911396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 06:50:58.911492 ==
5562 06:50:58.914700 [Gating] SW mode calibration
5563 06:50:58.921552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5564 06:50:58.924392 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5565 06:50:58.931451 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 06:50:58.934330 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 06:50:58.937847 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 06:50:58.944167 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 06:50:58.947643 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 06:50:58.951115 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
5571 06:50:58.957510 0 14 24 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 1)
5572 06:50:58.960880 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5573 06:50:58.964357 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5574 06:50:58.971309 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 06:50:58.974478 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 06:50:58.977681 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 06:50:58.984251 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 06:50:58.987473 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 06:50:58.990652 0 15 24 | B1->B0 | 2727 3333 | 0 1 | (1 1) (0 0)
5580 06:50:58.997305 0 15 28 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
5581 06:50:59.000747 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 06:50:59.004113 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 06:50:59.011303 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 06:50:59.014593 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 06:50:59.017331 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 06:50:59.024176 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 06:50:59.027651 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5588 06:50:59.031212 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5589 06:50:59.037741 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 06:50:59.040687 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 06:50:59.044136 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 06:50:59.051028 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 06:50:59.053909 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 06:50:59.057535 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 06:50:59.061152 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 06:50:59.067429 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 06:50:59.070879 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 06:50:59.073800 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 06:50:59.080799 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 06:50:59.084035 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 06:50:59.087302 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 06:50:59.094034 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 06:50:59.097484 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5604 06:50:59.100729 Total UI for P1: 0, mck2ui 16
5605 06:50:59.104100 best dqsien dly found for B0: ( 1, 2, 22)
5606 06:50:59.107409 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 06:50:59.110725 Total UI for P1: 0, mck2ui 16
5608 06:50:59.113863 best dqsien dly found for B1: ( 1, 2, 24)
5609 06:50:59.117295 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5610 06:50:59.120689 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5611 06:50:59.120774
5612 06:50:59.127224 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5613 06:50:59.130583 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5614 06:50:59.134001 [Gating] SW calibration Done
5615 06:50:59.134079 ==
5616 06:50:59.137423 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 06:50:59.140338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 06:50:59.140415 ==
5619 06:50:59.140480 RX Vref Scan: 0
5620 06:50:59.140540
5621 06:50:59.143950 RX Vref 0 -> 0, step: 1
5622 06:50:59.144048
5623 06:50:59.147327 RX Delay -80 -> 252, step: 8
5624 06:50:59.150825 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5625 06:50:59.153582 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5626 06:50:59.157062 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5627 06:50:59.164034 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5628 06:50:59.166789 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5629 06:50:59.170261 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5630 06:50:59.173746 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5631 06:50:59.177350 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5632 06:50:59.180223 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5633 06:50:59.187386 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5634 06:50:59.190205 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5635 06:50:59.193547 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5636 06:50:59.196811 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5637 06:50:59.200100 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5638 06:50:59.206724 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5639 06:50:59.210179 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5640 06:50:59.210262 ==
5641 06:50:59.213546 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 06:50:59.216717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 06:50:59.216813 ==
5644 06:50:59.220412 DQS Delay:
5645 06:50:59.220504 DQS0 = 0, DQS1 = 0
5646 06:50:59.220570 DQM Delay:
5647 06:50:59.223545 DQM0 = 102, DQM1 = 99
5648 06:50:59.223642 DQ Delay:
5649 06:50:59.226826 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5650 06:50:59.230078 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5651 06:50:59.233414 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5652 06:50:59.236793 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5653 06:50:59.236885
5654 06:50:59.236971
5655 06:50:59.240125 ==
5656 06:50:59.240200 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 06:50:59.247035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 06:50:59.247115 ==
5659 06:50:59.247194
5660 06:50:59.247258
5661 06:50:59.250406 TX Vref Scan disable
5662 06:50:59.250494 == TX Byte 0 ==
5663 06:50:59.253255 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5664 06:50:59.260279 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5665 06:50:59.260366 == TX Byte 1 ==
5666 06:50:59.263755 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5667 06:50:59.270140 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5668 06:50:59.270227 ==
5669 06:50:59.273416 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 06:50:59.276970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 06:50:59.277044 ==
5672 06:50:59.277120
5673 06:50:59.277182
5674 06:50:59.279724 TX Vref Scan disable
5675 06:50:59.283451 == TX Byte 0 ==
5676 06:50:59.286941 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5677 06:50:59.289792 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5678 06:50:59.293358 == TX Byte 1 ==
5679 06:50:59.296959 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5680 06:50:59.299693 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5681 06:50:59.299779
5682 06:50:59.299843 [DATLAT]
5683 06:50:59.303199 Freq=933, CH1 RK0
5684 06:50:59.303274
5685 06:50:59.306529 DATLAT Default: 0xd
5686 06:50:59.306641 0, 0xFFFF, sum = 0
5687 06:50:59.309823 1, 0xFFFF, sum = 0
5688 06:50:59.309910 2, 0xFFFF, sum = 0
5689 06:50:59.313270 3, 0xFFFF, sum = 0
5690 06:50:59.313362 4, 0xFFFF, sum = 0
5691 06:50:59.316833 5, 0xFFFF, sum = 0
5692 06:50:59.316912 6, 0xFFFF, sum = 0
5693 06:50:59.319640 7, 0xFFFF, sum = 0
5694 06:50:59.319725 8, 0xFFFF, sum = 0
5695 06:50:59.323172 9, 0xFFFF, sum = 0
5696 06:50:59.323246 10, 0x0, sum = 1
5697 06:50:59.326535 11, 0x0, sum = 2
5698 06:50:59.326619 12, 0x0, sum = 3
5699 06:50:59.329864 13, 0x0, sum = 4
5700 06:50:59.329979 best_step = 11
5701 06:50:59.330085
5702 06:50:59.330150 ==
5703 06:50:59.333151 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 06:50:59.336219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 06:50:59.339861 ==
5706 06:50:59.339937 RX Vref Scan: 1
5707 06:50:59.340001
5708 06:50:59.343252 RX Vref 0 -> 0, step: 1
5709 06:50:59.343335
5710 06:50:59.343401 RX Delay -45 -> 252, step: 4
5711 06:50:59.346669
5712 06:50:59.346748 Set Vref, RX VrefLevel [Byte0]: 52
5713 06:50:59.349776 [Byte1]: 53
5714 06:50:59.354336
5715 06:50:59.354416 Final RX Vref Byte 0 = 52 to rank0
5716 06:50:59.357744 Final RX Vref Byte 1 = 53 to rank0
5717 06:50:59.361496 Final RX Vref Byte 0 = 52 to rank1
5718 06:50:59.364639 Final RX Vref Byte 1 = 53 to rank1==
5719 06:50:59.367824 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 06:50:59.374508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 06:50:59.374624 ==
5722 06:50:59.374720 DQS Delay:
5723 06:50:59.374820 DQS0 = 0, DQS1 = 0
5724 06:50:59.378060 DQM Delay:
5725 06:50:59.378167 DQM0 = 102, DQM1 = 99
5726 06:50:59.381474 DQ Delay:
5727 06:50:59.384263 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5728 06:50:59.387673 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =102
5729 06:50:59.391248 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =92
5730 06:50:59.394655 DQ12 =104, DQ13 =106, DQ14 =106, DQ15 =106
5731 06:50:59.394753
5732 06:50:59.394846
5733 06:50:59.401010 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5734 06:50:59.404470 CH1 RK0: MR19=505, MR18=1B32
5735 06:50:59.410795 CH1_RK0: MR19=0x505, MR18=0x1B32, DQSOSC=406, MR23=63, INC=65, DEC=43
5736 06:50:59.410875
5737 06:50:59.414151 ----->DramcWriteLeveling(PI) begin...
5738 06:50:59.414239 ==
5739 06:50:59.417940 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 06:50:59.421290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 06:50:59.424636 ==
5742 06:50:59.424714 Write leveling (Byte 0): 29 => 29
5743 06:50:59.427427 Write leveling (Byte 1): 27 => 27
5744 06:50:59.430864 DramcWriteLeveling(PI) end<-----
5745 06:50:59.430938
5746 06:50:59.431000 ==
5747 06:50:59.434425 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 06:50:59.440683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 06:50:59.440762 ==
5750 06:50:59.440827 [Gating] SW mode calibration
5751 06:50:59.450931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5752 06:50:59.454130 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5753 06:50:59.457321 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 06:50:59.464166 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 06:50:59.467195 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 06:50:59.470708 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 06:50:59.477233 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 06:50:59.481075 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5759 06:50:59.484177 0 14 24 | B1->B0 | 2c2c 3434 | 1 0 | (1 0) (0 0)
5760 06:50:59.490642 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 06:50:59.493801 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 06:50:59.497519 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 06:50:59.504248 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 06:50:59.507108 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 06:50:59.510631 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 06:50:59.517660 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 06:50:59.520496 0 15 24 | B1->B0 | 3434 2626 | 1 1 | (0 0) (0 0)
5768 06:50:59.523926 0 15 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
5769 06:50:59.530507 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 06:50:59.534417 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 06:50:59.537381 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 06:50:59.544387 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 06:50:59.547279 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 06:50:59.550725 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 06:50:59.557106 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5776 06:50:59.560534 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5777 06:50:59.563945 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 06:50:59.567229 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 06:50:59.574100 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 06:50:59.576907 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 06:50:59.580343 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 06:50:59.587323 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 06:50:59.590659 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 06:50:59.594121 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 06:50:59.600628 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 06:50:59.603828 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 06:50:59.607169 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 06:50:59.613549 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 06:50:59.617341 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 06:50:59.620583 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5791 06:50:59.626880 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5792 06:50:59.630361 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 06:50:59.633905 Total UI for P1: 0, mck2ui 16
5794 06:50:59.637162 best dqsien dly found for B0: ( 1, 2, 24)
5795 06:50:59.640401 Total UI for P1: 0, mck2ui 16
5796 06:50:59.643777 best dqsien dly found for B1: ( 1, 2, 22)
5797 06:50:59.647326 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5798 06:50:59.650917 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5799 06:50:59.651022
5800 06:50:59.653857 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5801 06:50:59.657408 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5802 06:50:59.660252 [Gating] SW calibration Done
5803 06:50:59.660373 ==
5804 06:50:59.663841 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 06:50:59.667424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 06:50:59.670147 ==
5807 06:50:59.670255 RX Vref Scan: 0
5808 06:50:59.670350
5809 06:50:59.673441 RX Vref 0 -> 0, step: 1
5810 06:50:59.673527
5811 06:50:59.673592 RX Delay -80 -> 252, step: 8
5812 06:50:59.680425 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5813 06:50:59.684087 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5814 06:50:59.687450 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5815 06:50:59.690221 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5816 06:50:59.694326 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5817 06:50:59.697277 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5818 06:50:59.703973 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5819 06:50:59.707215 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5820 06:50:59.710545 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5821 06:50:59.714051 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5822 06:50:59.716887 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5823 06:50:59.720725 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5824 06:50:59.727481 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5825 06:50:59.730164 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5826 06:50:59.733460 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5827 06:50:59.736926 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5828 06:50:59.737030 ==
5829 06:50:59.740375 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 06:50:59.747114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 06:50:59.747220 ==
5832 06:50:59.747325 DQS Delay:
5833 06:50:59.747417 DQS0 = 0, DQS1 = 0
5834 06:50:59.750358 DQM Delay:
5835 06:50:59.750433 DQM0 = 102, DQM1 = 99
5836 06:50:59.753795 DQ Delay:
5837 06:50:59.756623 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5838 06:50:59.760095 DQ4 =95, DQ5 =119, DQ6 =111, DQ7 =99
5839 06:50:59.763633 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5840 06:50:59.767163 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5841 06:50:59.767240
5842 06:50:59.767304
5843 06:50:59.767363 ==
5844 06:50:59.770053 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 06:50:59.773574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 06:50:59.773658 ==
5847 06:50:59.773725
5848 06:50:59.773787
5849 06:50:59.776877 TX Vref Scan disable
5850 06:50:59.780352 == TX Byte 0 ==
5851 06:50:59.783931 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5852 06:50:59.786818 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5853 06:50:59.790239 == TX Byte 1 ==
5854 06:50:59.793842 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5855 06:50:59.796726 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5856 06:50:59.796832 ==
5857 06:50:59.800175 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 06:50:59.803573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 06:50:59.806757 ==
5860 06:50:59.806861
5861 06:50:59.806958
5862 06:50:59.807048 TX Vref Scan disable
5863 06:50:59.810021 == TX Byte 0 ==
5864 06:50:59.813859 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5865 06:50:59.820309 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5866 06:50:59.820399 == TX Byte 1 ==
5867 06:50:59.823834 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5868 06:50:59.830163 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5869 06:50:59.830248
5870 06:50:59.830311 [DATLAT]
5871 06:50:59.830395 Freq=933, CH1 RK1
5872 06:50:59.830458
5873 06:50:59.833449 DATLAT Default: 0xb
5874 06:50:59.833548 0, 0xFFFF, sum = 0
5875 06:50:59.836898 1, 0xFFFF, sum = 0
5876 06:50:59.836998 2, 0xFFFF, sum = 0
5877 06:50:59.840410 3, 0xFFFF, sum = 0
5878 06:50:59.843133 4, 0xFFFF, sum = 0
5879 06:50:59.843214 5, 0xFFFF, sum = 0
5880 06:50:59.847032 6, 0xFFFF, sum = 0
5881 06:50:59.847149 7, 0xFFFF, sum = 0
5882 06:50:59.849850 8, 0xFFFF, sum = 0
5883 06:50:59.849965 9, 0xFFFF, sum = 0
5884 06:50:59.853301 10, 0x0, sum = 1
5885 06:50:59.853410 11, 0x0, sum = 2
5886 06:50:59.856755 12, 0x0, sum = 3
5887 06:50:59.856865 13, 0x0, sum = 4
5888 06:50:59.856970 best_step = 11
5889 06:50:59.857070
5890 06:50:59.860162 ==
5891 06:50:59.863478 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 06:50:59.866946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 06:50:59.867038 ==
5894 06:50:59.867116 RX Vref Scan: 0
5895 06:50:59.867183
5896 06:50:59.869904 RX Vref 0 -> 0, step: 1
5897 06:50:59.870014
5898 06:50:59.873489 RX Delay -45 -> 252, step: 4
5899 06:50:59.876278 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5900 06:50:59.883165 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5901 06:50:59.886517 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5902 06:50:59.889908 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5903 06:50:59.893371 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5904 06:50:59.896227 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5905 06:50:59.903359 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5906 06:50:59.906720 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5907 06:50:59.909599 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5908 06:50:59.912906 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5909 06:50:59.916222 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5910 06:50:59.919480 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5911 06:50:59.926257 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5912 06:50:59.929705 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5913 06:50:59.932850 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5914 06:50:59.936808 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5915 06:50:59.936922 ==
5916 06:50:59.939659 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 06:50:59.946623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 06:50:59.946719 ==
5919 06:50:59.946785 DQS Delay:
5920 06:50:59.946861 DQS0 = 0, DQS1 = 0
5921 06:50:59.950071 DQM Delay:
5922 06:50:59.950181 DQM0 = 104, DQM1 = 100
5923 06:50:59.952761 DQ Delay:
5924 06:50:59.956042 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5925 06:50:59.959858 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5926 06:50:59.962677 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =92
5927 06:50:59.966103 DQ12 =108, DQ13 =108, DQ14 =106, DQ15 =110
5928 06:50:59.966179
5929 06:50:59.966256
5930 06:50:59.972650 [DQSOSCAuto] RK1, (LSB)MR18= 0x3103, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5931 06:50:59.975766 CH1 RK1: MR19=505, MR18=3103
5932 06:50:59.982768 CH1_RK1: MR19=0x505, MR18=0x3103, DQSOSC=406, MR23=63, INC=65, DEC=43
5933 06:50:59.986169 [RxdqsGatingPostProcess] freq 933
5934 06:50:59.993093 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5935 06:50:59.996380 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 06:50:59.996497 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 06:50:59.999728 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 06:51:00.002633 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 06:51:00.006089 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 06:51:00.009635 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 06:51:00.012397 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 06:51:00.015866 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 06:51:00.019370 Pre-setting of DQS Precalculation
5944 06:51:00.026097 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5945 06:51:00.032963 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5946 06:51:00.039488 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5947 06:51:00.039569
5948 06:51:00.039645
5949 06:51:00.042713 [Calibration Summary] 1866 Mbps
5950 06:51:00.042814 CH 0, Rank 0
5951 06:51:00.045954 SW Impedance : PASS
5952 06:51:00.049432 DUTY Scan : NO K
5953 06:51:00.049510 ZQ Calibration : PASS
5954 06:51:00.052328 Jitter Meter : NO K
5955 06:51:00.056063 CBT Training : PASS
5956 06:51:00.056176 Write leveling : PASS
5957 06:51:00.059543 RX DQS gating : PASS
5958 06:51:00.059654 RX DQ/DQS(RDDQC) : PASS
5959 06:51:00.062929 TX DQ/DQS : PASS
5960 06:51:00.065598 RX DATLAT : PASS
5961 06:51:00.065669 RX DQ/DQS(Engine): PASS
5962 06:51:00.069580 TX OE : NO K
5963 06:51:00.069674 All Pass.
5964 06:51:00.069738
5965 06:51:00.072742 CH 0, Rank 1
5966 06:51:00.072849 SW Impedance : PASS
5967 06:51:00.076237 DUTY Scan : NO K
5968 06:51:00.079564 ZQ Calibration : PASS
5969 06:51:00.079676 Jitter Meter : NO K
5970 06:51:00.082868 CBT Training : PASS
5971 06:51:00.086262 Write leveling : PASS
5972 06:51:00.086375 RX DQS gating : PASS
5973 06:51:00.088954 RX DQ/DQS(RDDQC) : PASS
5974 06:51:00.092569 TX DQ/DQS : PASS
5975 06:51:00.092656 RX DATLAT : PASS
5976 06:51:00.096046 RX DQ/DQS(Engine): PASS
5977 06:51:00.099577 TX OE : NO K
5978 06:51:00.099655 All Pass.
5979 06:51:00.099730
5980 06:51:00.099823 CH 1, Rank 0
5981 06:51:00.102365 SW Impedance : PASS
5982 06:51:00.105730 DUTY Scan : NO K
5983 06:51:00.105829 ZQ Calibration : PASS
5984 06:51:00.109116 Jitter Meter : NO K
5985 06:51:00.109203 CBT Training : PASS
5986 06:51:00.112674 Write leveling : PASS
5987 06:51:00.116258 RX DQS gating : PASS
5988 06:51:00.116344 RX DQ/DQS(RDDQC) : PASS
5989 06:51:00.119169 TX DQ/DQS : PASS
5990 06:51:00.122707 RX DATLAT : PASS
5991 06:51:00.122791 RX DQ/DQS(Engine): PASS
5992 06:51:00.126193 TX OE : NO K
5993 06:51:00.126278 All Pass.
5994 06:51:00.126345
5995 06:51:00.129578 CH 1, Rank 1
5996 06:51:00.129662 SW Impedance : PASS
5997 06:51:00.132232 DUTY Scan : NO K
5998 06:51:00.135488 ZQ Calibration : PASS
5999 06:51:00.135572 Jitter Meter : NO K
6000 06:51:00.138729 CBT Training : PASS
6001 06:51:00.142293 Write leveling : PASS
6002 06:51:00.142377 RX DQS gating : PASS
6003 06:51:00.145734 RX DQ/DQS(RDDQC) : PASS
6004 06:51:00.148881 TX DQ/DQS : PASS
6005 06:51:00.148965 RX DATLAT : PASS
6006 06:51:00.152658 RX DQ/DQS(Engine): PASS
6007 06:51:00.152768 TX OE : NO K
6008 06:51:00.155888 All Pass.
6009 06:51:00.155975
6010 06:51:00.156042 DramC Write-DBI off
6011 06:51:00.158806 PER_BANK_REFRESH: Hybrid Mode
6012 06:51:00.162347 TX_TRACKING: ON
6013 06:51:00.168632 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6014 06:51:00.172277 [FAST_K] Save calibration result to emmc
6015 06:51:00.179060 dramc_set_vcore_voltage set vcore to 650000
6016 06:51:00.179150 Read voltage for 400, 6
6017 06:51:00.182212 Vio18 = 0
6018 06:51:00.182297 Vcore = 650000
6019 06:51:00.182364 Vdram = 0
6020 06:51:00.182428 Vddq = 0
6021 06:51:00.185512 Vmddr = 0
6022 06:51:00.188905 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6023 06:51:00.195624 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6024 06:51:00.198928 MEM_TYPE=3, freq_sel=20
6025 06:51:00.199013 sv_algorithm_assistance_LP4_800
6026 06:51:00.205203 ============ PULL DRAM RESETB DOWN ============
6027 06:51:00.208500 ========== PULL DRAM RESETB DOWN end =========
6028 06:51:00.211954 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6029 06:51:00.215297 ===================================
6030 06:51:00.218585 LPDDR4 DRAM CONFIGURATION
6031 06:51:00.221855 ===================================
6032 06:51:00.225327 EX_ROW_EN[0] = 0x0
6033 06:51:00.225412 EX_ROW_EN[1] = 0x0
6034 06:51:00.228847 LP4Y_EN = 0x0
6035 06:51:00.228932 WORK_FSP = 0x0
6036 06:51:00.232272 WL = 0x2
6037 06:51:00.232394 RL = 0x2
6038 06:51:00.235143 BL = 0x2
6039 06:51:00.235251 RPST = 0x0
6040 06:51:00.238534 RD_PRE = 0x0
6041 06:51:00.238646 WR_PRE = 0x1
6042 06:51:00.242086 WR_PST = 0x0
6043 06:51:00.242190 DBI_WR = 0x0
6044 06:51:00.245229 DBI_RD = 0x0
6045 06:51:00.245303 OTF = 0x1
6046 06:51:00.248332 ===================================
6047 06:51:00.251785 ===================================
6048 06:51:00.255285 ANA top config
6049 06:51:00.258747 ===================================
6050 06:51:00.261960 DLL_ASYNC_EN = 0
6051 06:51:00.262079 ALL_SLAVE_EN = 1
6052 06:51:00.265032 NEW_RANK_MODE = 1
6053 06:51:00.268868 DLL_IDLE_MODE = 1
6054 06:51:00.271737 LP45_APHY_COMB_EN = 1
6055 06:51:00.271847 TX_ODT_DIS = 1
6056 06:51:00.275387 NEW_8X_MODE = 1
6057 06:51:00.278886 ===================================
6058 06:51:00.281754 ===================================
6059 06:51:00.285284 data_rate = 800
6060 06:51:00.288825 CKR = 1
6061 06:51:00.292178 DQ_P2S_RATIO = 4
6062 06:51:00.295488 ===================================
6063 06:51:00.298787 CA_P2S_RATIO = 4
6064 06:51:00.298900 DQ_CA_OPEN = 0
6065 06:51:00.302093 DQ_SEMI_OPEN = 1
6066 06:51:00.305326 CA_SEMI_OPEN = 1
6067 06:51:00.308586 CA_FULL_RATE = 0
6068 06:51:00.311932 DQ_CKDIV4_EN = 0
6069 06:51:00.315353 CA_CKDIV4_EN = 1
6070 06:51:00.315466 CA_PREDIV_EN = 0
6071 06:51:00.318878 PH8_DLY = 0
6072 06:51:00.322264 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6073 06:51:00.325557 DQ_AAMCK_DIV = 0
6074 06:51:00.328863 CA_AAMCK_DIV = 0
6075 06:51:00.328948 CA_ADMCK_DIV = 4
6076 06:51:00.332370 DQ_TRACK_CA_EN = 0
6077 06:51:00.335270 CA_PICK = 800
6078 06:51:00.338740 CA_MCKIO = 400
6079 06:51:00.342293 MCKIO_SEMI = 400
6080 06:51:00.345185 PLL_FREQ = 3016
6081 06:51:00.348515 DQ_UI_PI_RATIO = 32
6082 06:51:00.351924 CA_UI_PI_RATIO = 32
6083 06:51:00.355210 ===================================
6084 06:51:00.355318 ===================================
6085 06:51:00.358951 memory_type:LPDDR4
6086 06:51:00.361826 GP_NUM : 10
6087 06:51:00.361909 SRAM_EN : 1
6088 06:51:00.365410 MD32_EN : 0
6089 06:51:00.368926 ===================================
6090 06:51:00.371891 [ANA_INIT] >>>>>>>>>>>>>>
6091 06:51:00.375167 <<<<<< [CONFIGURE PHASE]: ANA_TX
6092 06:51:00.378328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6093 06:51:00.382297 ===================================
6094 06:51:00.382374 data_rate = 800,PCW = 0X7400
6095 06:51:00.385164 ===================================
6096 06:51:00.388637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6097 06:51:00.395089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 06:51:00.408272 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 06:51:00.411609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6100 06:51:00.414977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6101 06:51:00.418245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6102 06:51:00.421532 [ANA_INIT] flow start
6103 06:51:00.421650 [ANA_INIT] PLL >>>>>>>>
6104 06:51:00.424902 [ANA_INIT] PLL <<<<<<<<
6105 06:51:00.428430 [ANA_INIT] MIDPI >>>>>>>>
6106 06:51:00.428526 [ANA_INIT] MIDPI <<<<<<<<
6107 06:51:00.431991 [ANA_INIT] DLL >>>>>>>>
6108 06:51:00.434721 [ANA_INIT] flow end
6109 06:51:00.438102 ============ LP4 DIFF to SE enter ============
6110 06:51:00.441684 ============ LP4 DIFF to SE exit ============
6111 06:51:00.445177 [ANA_INIT] <<<<<<<<<<<<<
6112 06:51:00.448178 [Flow] Enable top DCM control >>>>>
6113 06:51:00.451644 [Flow] Enable top DCM control <<<<<
6114 06:51:00.454578 Enable DLL master slave shuffle
6115 06:51:00.461362 ==============================================================
6116 06:51:00.461450 Gating Mode config
6117 06:51:00.468429 ==============================================================
6118 06:51:00.468516 Config description:
6119 06:51:00.478314 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6120 06:51:00.484552 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6121 06:51:00.491180 SELPH_MODE 0: By rank 1: By Phase
6122 06:51:00.494527 ==============================================================
6123 06:51:00.497819 GAT_TRACK_EN = 0
6124 06:51:00.501277 RX_GATING_MODE = 2
6125 06:51:00.504860 RX_GATING_TRACK_MODE = 2
6126 06:51:00.507700 SELPH_MODE = 1
6127 06:51:00.511256 PICG_EARLY_EN = 1
6128 06:51:00.514624 VALID_LAT_VALUE = 1
6129 06:51:00.517938 ==============================================================
6130 06:51:00.521271 Enter into Gating configuration >>>>
6131 06:51:00.524588 Exit from Gating configuration <<<<
6132 06:51:00.527927 Enter into DVFS_PRE_config >>>>>
6133 06:51:00.540941 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6134 06:51:00.544306 Exit from DVFS_PRE_config <<<<<
6135 06:51:00.547550 Enter into PICG configuration >>>>
6136 06:51:00.547715 Exit from PICG configuration <<<<
6137 06:51:00.551159 [RX_INPUT] configuration >>>>>
6138 06:51:00.554635 [RX_INPUT] configuration <<<<<
6139 06:51:00.560980 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6140 06:51:00.564418 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6141 06:51:00.571309 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 06:51:00.577729 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 06:51:00.584668 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 06:51:00.590977 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 06:51:00.594397 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6146 06:51:00.597651 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6147 06:51:00.600923 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6148 06:51:00.607613 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6149 06:51:00.611105 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6150 06:51:00.614612 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6151 06:51:00.617437 ===================================
6152 06:51:00.620883 LPDDR4 DRAM CONFIGURATION
6153 06:51:00.624445 ===================================
6154 06:51:00.627684 EX_ROW_EN[0] = 0x0
6155 06:51:00.627766 EX_ROW_EN[1] = 0x0
6156 06:51:00.630925 LP4Y_EN = 0x0
6157 06:51:00.631002 WORK_FSP = 0x0
6158 06:51:00.634271 WL = 0x2
6159 06:51:00.634383 RL = 0x2
6160 06:51:00.637496 BL = 0x2
6161 06:51:00.637603 RPST = 0x0
6162 06:51:00.641391 RD_PRE = 0x0
6163 06:51:00.641525 WR_PRE = 0x1
6164 06:51:00.644163 WR_PST = 0x0
6165 06:51:00.644265 DBI_WR = 0x0
6166 06:51:00.647652 DBI_RD = 0x0
6167 06:51:00.647767 OTF = 0x1
6168 06:51:00.650998 ===================================
6169 06:51:00.654257 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6170 06:51:00.661139 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6171 06:51:00.664600 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 06:51:00.667475 ===================================
6173 06:51:00.670929 LPDDR4 DRAM CONFIGURATION
6174 06:51:00.674496 ===================================
6175 06:51:00.674604 EX_ROW_EN[0] = 0x10
6176 06:51:00.678002 EX_ROW_EN[1] = 0x0
6177 06:51:00.680875 LP4Y_EN = 0x0
6178 06:51:00.680976 WORK_FSP = 0x0
6179 06:51:00.684198 WL = 0x2
6180 06:51:00.684336 RL = 0x2
6181 06:51:00.687356 BL = 0x2
6182 06:51:00.687453 RPST = 0x0
6183 06:51:00.690661 RD_PRE = 0x0
6184 06:51:00.690766 WR_PRE = 0x1
6185 06:51:00.694213 WR_PST = 0x0
6186 06:51:00.694301 DBI_WR = 0x0
6187 06:51:00.697783 DBI_RD = 0x0
6188 06:51:00.697855 OTF = 0x1
6189 06:51:00.701258 ===================================
6190 06:51:00.707541 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6191 06:51:00.711527 nWR fixed to 30
6192 06:51:00.714929 [ModeRegInit_LP4] CH0 RK0
6193 06:51:00.715029 [ModeRegInit_LP4] CH0 RK1
6194 06:51:00.718363 [ModeRegInit_LP4] CH1 RK0
6195 06:51:00.721898 [ModeRegInit_LP4] CH1 RK1
6196 06:51:00.721972 match AC timing 19
6197 06:51:00.728290 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6198 06:51:00.731212 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6199 06:51:00.734675 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6200 06:51:00.741484 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6201 06:51:00.744580 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6202 06:51:00.744660 ==
6203 06:51:00.747916 Dram Type= 6, Freq= 0, CH_0, rank 0
6204 06:51:00.751347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6205 06:51:00.751448 ==
6206 06:51:00.758302 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6207 06:51:00.764334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6208 06:51:00.768221 [CA 0] Center 36 (8~64) winsize 57
6209 06:51:00.771561 [CA 1] Center 36 (8~64) winsize 57
6210 06:51:00.774926 [CA 2] Center 36 (8~64) winsize 57
6211 06:51:00.777858 [CA 3] Center 36 (8~64) winsize 57
6212 06:51:00.777945 [CA 4] Center 36 (8~64) winsize 57
6213 06:51:00.781377 [CA 5] Center 36 (8~64) winsize 57
6214 06:51:00.781465
6215 06:51:00.787633 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6216 06:51:00.787720
6217 06:51:00.791106 [CATrainingPosCal] consider 1 rank data
6218 06:51:00.794448 u2DelayCellTimex100 = 270/100 ps
6219 06:51:00.797608 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 06:51:00.800963 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 06:51:00.804300 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 06:51:00.807656 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 06:51:00.811161 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 06:51:00.814616 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 06:51:00.814696
6226 06:51:00.817841 CA PerBit enable=1, Macro0, CA PI delay=36
6227 06:51:00.817920
6228 06:51:00.821372 [CBTSetCACLKResult] CA Dly = 36
6229 06:51:00.824619 CS Dly: 1 (0~32)
6230 06:51:00.824704 ==
6231 06:51:00.827426 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 06:51:00.830921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 06:51:00.831019 ==
6234 06:51:00.837911 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 06:51:00.840724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 06:51:00.844185 [CA 0] Center 36 (8~64) winsize 57
6237 06:51:00.847617 [CA 1] Center 36 (8~64) winsize 57
6238 06:51:00.850780 [CA 2] Center 36 (8~64) winsize 57
6239 06:51:00.854200 [CA 3] Center 36 (8~64) winsize 57
6240 06:51:00.857420 [CA 4] Center 36 (8~64) winsize 57
6241 06:51:00.860917 [CA 5] Center 36 (8~64) winsize 57
6242 06:51:00.861001
6243 06:51:00.864067 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 06:51:00.864166
6245 06:51:00.867498 [CATrainingPosCal] consider 2 rank data
6246 06:51:00.870980 u2DelayCellTimex100 = 270/100 ps
6247 06:51:00.874424 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 06:51:00.877157 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 06:51:00.884450 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 06:51:00.887218 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 06:51:00.890793 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 06:51:00.893824 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 06:51:00.893923
6254 06:51:00.897208 CA PerBit enable=1, Macro0, CA PI delay=36
6255 06:51:00.897307
6256 06:51:00.900748 [CBTSetCACLKResult] CA Dly = 36
6257 06:51:00.900831 CS Dly: 1 (0~32)
6258 06:51:00.900897
6259 06:51:00.904080 ----->DramcWriteLeveling(PI) begin...
6260 06:51:00.907101 ==
6261 06:51:00.910359 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 06:51:00.914280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 06:51:00.914379 ==
6264 06:51:00.917688 Write leveling (Byte 0): 40 => 8
6265 06:51:00.920505 Write leveling (Byte 1): 40 => 8
6266 06:51:00.920603 DramcWriteLeveling(PI) end<-----
6267 06:51:00.923944
6268 06:51:00.924073 ==
6269 06:51:00.927437 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 06:51:00.930820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 06:51:00.930921 ==
6272 06:51:00.934296 [Gating] SW mode calibration
6273 06:51:00.940654 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6274 06:51:00.944197 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6275 06:51:00.950441 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 06:51:00.954064 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 06:51:00.957529 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 06:51:00.964034 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 06:51:00.967298 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 06:51:00.970697 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 06:51:00.977557 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 06:51:00.980610 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 06:51:00.983791 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 06:51:00.987076 Total UI for P1: 0, mck2ui 16
6285 06:51:00.991045 best dqsien dly found for B0: ( 0, 14, 24)
6286 06:51:00.994172 Total UI for P1: 0, mck2ui 16
6287 06:51:00.997722 best dqsien dly found for B1: ( 0, 14, 24)
6288 06:51:01.000511 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6289 06:51:01.003981 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6290 06:51:01.004080
6291 06:51:01.010878 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 06:51:01.013618 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 06:51:01.013715 [Gating] SW calibration Done
6294 06:51:01.017132 ==
6295 06:51:01.020873 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 06:51:01.024208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 06:51:01.024336 ==
6298 06:51:01.024404 RX Vref Scan: 0
6299 06:51:01.024467
6300 06:51:01.027364 RX Vref 0 -> 0, step: 1
6301 06:51:01.027445
6302 06:51:01.030655 RX Delay -410 -> 252, step: 16
6303 06:51:01.033799 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6304 06:51:01.037313 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6305 06:51:01.044185 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6306 06:51:01.047067 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6307 06:51:01.050568 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6308 06:51:01.053932 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6309 06:51:01.060307 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6310 06:51:01.063754 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6311 06:51:01.067246 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6312 06:51:01.070170 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6313 06:51:01.077284 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6314 06:51:01.080195 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6315 06:51:01.083475 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6316 06:51:01.086920 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6317 06:51:01.093594 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6318 06:51:01.096747 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6319 06:51:01.096830 ==
6320 06:51:01.100699 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 06:51:01.103941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 06:51:01.104024 ==
6323 06:51:01.107176 DQS Delay:
6324 06:51:01.107260 DQS0 = 27, DQS1 = 35
6325 06:51:01.110623 DQM Delay:
6326 06:51:01.110707 DQM0 = 9, DQM1 = 12
6327 06:51:01.110773 DQ Delay:
6328 06:51:01.113381 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6329 06:51:01.116798 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6330 06:51:01.120166 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6331 06:51:01.123687 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6332 06:51:01.123800
6333 06:51:01.123865
6334 06:51:01.123924 ==
6335 06:51:01.127126 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 06:51:01.133249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 06:51:01.133347 ==
6338 06:51:01.133412
6339 06:51:01.133471
6340 06:51:01.133577 TX Vref Scan disable
6341 06:51:01.136797 == TX Byte 0 ==
6342 06:51:01.140239 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 06:51:01.143446 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 06:51:01.146650 == TX Byte 1 ==
6345 06:51:01.150061 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 06:51:01.153425 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 06:51:01.153546 ==
6348 06:51:01.156326 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 06:51:01.163230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 06:51:01.163316 ==
6351 06:51:01.163382
6352 06:51:01.163443
6353 06:51:01.163503 TX Vref Scan disable
6354 06:51:01.166766 == TX Byte 0 ==
6355 06:51:01.169663 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 06:51:01.173192 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 06:51:01.176537 == TX Byte 1 ==
6358 06:51:01.180111 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 06:51:01.183548 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 06:51:01.183646
6361 06:51:01.186462 [DATLAT]
6362 06:51:01.186544 Freq=400, CH0 RK0
6363 06:51:01.186625
6364 06:51:01.189636 DATLAT Default: 0xf
6365 06:51:01.189734 0, 0xFFFF, sum = 0
6366 06:51:01.193186 1, 0xFFFF, sum = 0
6367 06:51:01.193309 2, 0xFFFF, sum = 0
6368 06:51:01.196693 3, 0xFFFF, sum = 0
6369 06:51:01.196801 4, 0xFFFF, sum = 0
6370 06:51:01.199476 5, 0xFFFF, sum = 0
6371 06:51:01.199561 6, 0xFFFF, sum = 0
6372 06:51:01.202835 7, 0xFFFF, sum = 0
6373 06:51:01.202950 8, 0xFFFF, sum = 0
6374 06:51:01.206235 9, 0xFFFF, sum = 0
6375 06:51:01.209712 10, 0xFFFF, sum = 0
6376 06:51:01.209798 11, 0xFFFF, sum = 0
6377 06:51:01.212889 12, 0xFFFF, sum = 0
6378 06:51:01.213004 13, 0x0, sum = 1
6379 06:51:01.216303 14, 0x0, sum = 2
6380 06:51:01.216433 15, 0x0, sum = 3
6381 06:51:01.219519 16, 0x0, sum = 4
6382 06:51:01.219618 best_step = 14
6383 06:51:01.219697
6384 06:51:01.219758 ==
6385 06:51:01.222757 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 06:51:01.226273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 06:51:01.226372 ==
6388 06:51:01.229556 RX Vref Scan: 1
6389 06:51:01.229640
6390 06:51:01.233196 RX Vref 0 -> 0, step: 1
6391 06:51:01.233279
6392 06:51:01.233347 RX Delay -311 -> 252, step: 8
6393 06:51:01.233410
6394 06:51:01.235838 Set Vref, RX VrefLevel [Byte0]: 55
6395 06:51:01.239329 [Byte1]: 53
6396 06:51:01.244932
6397 06:51:01.245029 Final RX Vref Byte 0 = 55 to rank0
6398 06:51:01.247745 Final RX Vref Byte 1 = 53 to rank0
6399 06:51:01.251251 Final RX Vref Byte 0 = 55 to rank1
6400 06:51:01.254613 Final RX Vref Byte 1 = 53 to rank1==
6401 06:51:01.257866 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 06:51:01.264642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 06:51:01.264752 ==
6404 06:51:01.264823 DQS Delay:
6405 06:51:01.268121 DQS0 = 24, DQS1 = 36
6406 06:51:01.268206 DQM Delay:
6407 06:51:01.268273 DQM0 = 8, DQM1 = 13
6408 06:51:01.271444 DQ Delay:
6409 06:51:01.274922 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6410 06:51:01.275006 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6411 06:51:01.277818 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6412 06:51:01.281274 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6413 06:51:01.281387
6414 06:51:01.281490
6415 06:51:01.291256 [DQSOSCAuto] RK0, (LSB)MR18= 0xd2c0, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 383 ps
6416 06:51:01.294629 CH0 RK0: MR19=C0C, MR18=D2C0
6417 06:51:01.301421 CH0_RK0: MR19=0xC0C, MR18=0xD2C0, DQSOSC=383, MR23=63, INC=402, DEC=268
6418 06:51:01.301534 ==
6419 06:51:01.304280 Dram Type= 6, Freq= 0, CH_0, rank 1
6420 06:51:01.307709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 06:51:01.307819 ==
6422 06:51:01.311025 [Gating] SW mode calibration
6423 06:51:01.317828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6424 06:51:01.321267 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6425 06:51:01.327507 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 06:51:01.330784 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 06:51:01.334481 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 06:51:01.340890 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 06:51:01.344665 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 06:51:01.347381 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 06:51:01.354315 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 06:51:01.357779 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 06:51:01.361256 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 06:51:01.364582 Total UI for P1: 0, mck2ui 16
6435 06:51:01.367800 best dqsien dly found for B0: ( 0, 14, 24)
6436 06:51:01.371028 Total UI for P1: 0, mck2ui 16
6437 06:51:01.374280 best dqsien dly found for B1: ( 0, 14, 24)
6438 06:51:01.377566 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6439 06:51:01.380988 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6440 06:51:01.384003
6441 06:51:01.387432 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 06:51:01.390974 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 06:51:01.393720 [Gating] SW calibration Done
6444 06:51:01.393809 ==
6445 06:51:01.397069 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 06:51:01.400665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 06:51:01.400756 ==
6448 06:51:01.400853 RX Vref Scan: 0
6449 06:51:01.404143
6450 06:51:01.404250 RX Vref 0 -> 0, step: 1
6451 06:51:01.404362
6452 06:51:01.407089 RX Delay -410 -> 252, step: 16
6453 06:51:01.410539 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6454 06:51:01.417633 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6455 06:51:01.420337 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6456 06:51:01.423845 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6457 06:51:01.427386 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6458 06:51:01.433890 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6459 06:51:01.437351 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6460 06:51:01.440673 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6461 06:51:01.443958 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6462 06:51:01.450665 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6463 06:51:01.454063 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6464 06:51:01.457321 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6465 06:51:01.460582 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6466 06:51:01.467095 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6467 06:51:01.470591 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6468 06:51:01.473820 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6469 06:51:01.473915 ==
6470 06:51:01.477177 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 06:51:01.480532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 06:51:01.483858 ==
6473 06:51:01.483964 DQS Delay:
6474 06:51:01.484067 DQS0 = 27, DQS1 = 35
6475 06:51:01.487046 DQM Delay:
6476 06:51:01.487122 DQM0 = 12, DQM1 = 11
6477 06:51:01.490328 DQ Delay:
6478 06:51:01.490414 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6479 06:51:01.493867 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6480 06:51:01.496772 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6481 06:51:01.500142 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6482 06:51:01.500229
6483 06:51:01.500334
6484 06:51:01.503679 ==
6485 06:51:01.503766 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 06:51:01.510022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 06:51:01.510110 ==
6488 06:51:01.510198
6489 06:51:01.510281
6490 06:51:01.513526 TX Vref Scan disable
6491 06:51:01.513613 == TX Byte 0 ==
6492 06:51:01.516952 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6493 06:51:01.520580 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6494 06:51:01.523424 == TX Byte 1 ==
6495 06:51:01.526925 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6496 06:51:01.530180 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6497 06:51:01.533704 ==
6498 06:51:01.536598 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 06:51:01.540107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 06:51:01.540195 ==
6501 06:51:01.540310
6502 06:51:01.540395
6503 06:51:01.543560 TX Vref Scan disable
6504 06:51:01.543647 == TX Byte 0 ==
6505 06:51:01.546414 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6506 06:51:01.553134 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6507 06:51:01.553221 == TX Byte 1 ==
6508 06:51:01.556971 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6509 06:51:01.559848 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6510 06:51:01.563363
6511 06:51:01.563450 [DATLAT]
6512 06:51:01.563538 Freq=400, CH0 RK1
6513 06:51:01.563623
6514 06:51:01.566828 DATLAT Default: 0xe
6515 06:51:01.566948 0, 0xFFFF, sum = 0
6516 06:51:01.570259 1, 0xFFFF, sum = 0
6517 06:51:01.570381 2, 0xFFFF, sum = 0
6518 06:51:01.573042 3, 0xFFFF, sum = 0
6519 06:51:01.573140 4, 0xFFFF, sum = 0
6520 06:51:01.576271 5, 0xFFFF, sum = 0
6521 06:51:01.579699 6, 0xFFFF, sum = 0
6522 06:51:01.579808 7, 0xFFFF, sum = 0
6523 06:51:01.583061 8, 0xFFFF, sum = 0
6524 06:51:01.583175 9, 0xFFFF, sum = 0
6525 06:51:01.586892 10, 0xFFFF, sum = 0
6526 06:51:01.587000 11, 0xFFFF, sum = 0
6527 06:51:01.589761 12, 0xFFFF, sum = 0
6528 06:51:01.589841 13, 0x0, sum = 1
6529 06:51:01.593283 14, 0x0, sum = 2
6530 06:51:01.593368 15, 0x0, sum = 3
6531 06:51:01.596604 16, 0x0, sum = 4
6532 06:51:01.596685 best_step = 14
6533 06:51:01.596749
6534 06:51:01.596810 ==
6535 06:51:01.599965 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 06:51:01.603382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 06:51:01.603468 ==
6538 06:51:01.606713 RX Vref Scan: 0
6539 06:51:01.606797
6540 06:51:01.610151 RX Vref 0 -> 0, step: 1
6541 06:51:01.610235
6542 06:51:01.610303 RX Delay -311 -> 252, step: 8
6543 06:51:01.618528 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6544 06:51:01.621884 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6545 06:51:01.624808 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6546 06:51:01.628364 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6547 06:51:01.635388 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6548 06:51:01.638038 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6549 06:51:01.641620 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6550 06:51:01.645190 iDelay=217, Bit 7, Center -4 (-223 ~ 216) 440
6551 06:51:01.651529 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6552 06:51:01.655161 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6553 06:51:01.658342 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6554 06:51:01.661824 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6555 06:51:01.668099 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6556 06:51:01.671398 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6557 06:51:01.674865 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6558 06:51:01.681673 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6559 06:51:01.681760 ==
6560 06:51:01.685097 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 06:51:01.687880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 06:51:01.687963 ==
6563 06:51:01.688029 DQS Delay:
6564 06:51:01.691221 DQS0 = 24, DQS1 = 32
6565 06:51:01.691304 DQM Delay:
6566 06:51:01.694952 DQM0 = 9, DQM1 = 9
6567 06:51:01.695035 DQ Delay:
6568 06:51:01.698173 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6569 06:51:01.701496 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =20
6570 06:51:01.704865 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6571 06:51:01.708400 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6572 06:51:01.708483
6573 06:51:01.708548
6574 06:51:01.714896 [DQSOSCAuto] RK1, (LSB)MR18= 0xba5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6575 06:51:01.717889 CH0 RK1: MR19=C0C, MR18=BA5A
6576 06:51:01.724790 CH0_RK1: MR19=0xC0C, MR18=0xBA5A, DQSOSC=386, MR23=63, INC=396, DEC=264
6577 06:51:01.728231 [RxdqsGatingPostProcess] freq 400
6578 06:51:01.731057 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6579 06:51:01.734599 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 06:51:01.737930 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 06:51:01.741346 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 06:51:01.744950 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 06:51:01.747889 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 06:51:01.751422 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 06:51:01.754298 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 06:51:01.757847 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 06:51:01.761452 Pre-setting of DQS Precalculation
6588 06:51:01.764193 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6589 06:51:01.767766 ==
6590 06:51:01.771196 Dram Type= 6, Freq= 0, CH_1, rank 0
6591 06:51:01.774549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 06:51:01.774671 ==
6593 06:51:01.777811 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6594 06:51:01.784632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6595 06:51:01.787773 [CA 0] Center 36 (8~64) winsize 57
6596 06:51:01.790880 [CA 1] Center 36 (8~64) winsize 57
6597 06:51:01.794338 [CA 2] Center 36 (8~64) winsize 57
6598 06:51:01.798032 [CA 3] Center 36 (8~64) winsize 57
6599 06:51:01.801268 [CA 4] Center 36 (8~64) winsize 57
6600 06:51:01.804416 [CA 5] Center 36 (8~64) winsize 57
6601 06:51:01.804517
6602 06:51:01.807590 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6603 06:51:01.807689
6604 06:51:01.810922 [CATrainingPosCal] consider 1 rank data
6605 06:51:01.814220 u2DelayCellTimex100 = 270/100 ps
6606 06:51:01.817620 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 06:51:01.821051 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 06:51:01.824445 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 06:51:01.827711 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 06:51:01.834220 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 06:51:01.837586 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 06:51:01.837670
6613 06:51:01.841140 CA PerBit enable=1, Macro0, CA PI delay=36
6614 06:51:01.841224
6615 06:51:01.844556 [CBTSetCACLKResult] CA Dly = 36
6616 06:51:01.844640 CS Dly: 1 (0~32)
6617 06:51:01.844708 ==
6618 06:51:01.847226 Dram Type= 6, Freq= 0, CH_1, rank 1
6619 06:51:01.850631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 06:51:01.854095 ==
6621 06:51:01.857719 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 06:51:01.863942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6623 06:51:01.867448 [CA 0] Center 36 (8~64) winsize 57
6624 06:51:01.870996 [CA 1] Center 36 (8~64) winsize 57
6625 06:51:01.873831 [CA 2] Center 36 (8~64) winsize 57
6626 06:51:01.877266 [CA 3] Center 36 (8~64) winsize 57
6627 06:51:01.880859 [CA 4] Center 36 (8~64) winsize 57
6628 06:51:01.884208 [CA 5] Center 36 (8~64) winsize 57
6629 06:51:01.884301
6630 06:51:01.887725 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6631 06:51:01.887808
6632 06:51:01.890542 [CATrainingPosCal] consider 2 rank data
6633 06:51:01.893913 u2DelayCellTimex100 = 270/100 ps
6634 06:51:01.897342 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 06:51:01.900548 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 06:51:01.903802 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 06:51:01.907228 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 06:51:01.910601 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 06:51:01.913950 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 06:51:01.914035
6641 06:51:01.917294 CA PerBit enable=1, Macro0, CA PI delay=36
6642 06:51:01.920441
6643 06:51:01.920525 [CBTSetCACLKResult] CA Dly = 36
6644 06:51:01.924275 CS Dly: 1 (0~32)
6645 06:51:01.924368
6646 06:51:01.927445 ----->DramcWriteLeveling(PI) begin...
6647 06:51:01.927530 ==
6648 06:51:01.930776 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 06:51:01.933599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 06:51:01.933682 ==
6651 06:51:01.937568 Write leveling (Byte 0): 40 => 8
6652 06:51:01.940280 Write leveling (Byte 1): 40 => 8
6653 06:51:01.943648 DramcWriteLeveling(PI) end<-----
6654 06:51:01.943732
6655 06:51:01.943798 ==
6656 06:51:01.947111 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 06:51:01.950433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 06:51:01.950517 ==
6659 06:51:01.953670 [Gating] SW mode calibration
6660 06:51:01.960466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6661 06:51:01.966877 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6662 06:51:01.970536 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 06:51:01.977112 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 06:51:01.980605 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 06:51:01.983407 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 06:51:01.990309 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 06:51:01.993828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 06:51:01.996588 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 06:51:02.003573 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 06:51:02.006942 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 06:51:02.010348 Total UI for P1: 0, mck2ui 16
6672 06:51:02.013789 best dqsien dly found for B0: ( 0, 14, 24)
6673 06:51:02.016677 Total UI for P1: 0, mck2ui 16
6674 06:51:02.020218 best dqsien dly found for B1: ( 0, 14, 24)
6675 06:51:02.023745 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6676 06:51:02.027145 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6677 06:51:02.027228
6678 06:51:02.030368 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 06:51:02.033686 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 06:51:02.036884 [Gating] SW calibration Done
6681 06:51:02.036967 ==
6682 06:51:02.040067 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 06:51:02.043277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 06:51:02.043393 ==
6685 06:51:02.046996 RX Vref Scan: 0
6686 06:51:02.047111
6687 06:51:02.050130 RX Vref 0 -> 0, step: 1
6688 06:51:02.050212
6689 06:51:02.050277 RX Delay -410 -> 252, step: 16
6690 06:51:02.056933 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6691 06:51:02.060115 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6692 06:51:02.063463 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6693 06:51:02.066713 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6694 06:51:02.073483 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6695 06:51:02.076940 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6696 06:51:02.080525 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6697 06:51:02.083350 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6698 06:51:02.090479 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6699 06:51:02.093892 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6700 06:51:02.097308 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6701 06:51:02.100110 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6702 06:51:02.106924 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6703 06:51:02.110459 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6704 06:51:02.113786 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6705 06:51:02.120138 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6706 06:51:02.120222 ==
6707 06:51:02.123753 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 06:51:02.126587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 06:51:02.126671 ==
6710 06:51:02.126737 DQS Delay:
6711 06:51:02.130534 DQS0 = 35, DQS1 = 35
6712 06:51:02.130616 DQM Delay:
6713 06:51:02.133419 DQM0 = 18, DQM1 = 13
6714 06:51:02.133512 DQ Delay:
6715 06:51:02.136929 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6716 06:51:02.140339 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6717 06:51:02.143669 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6718 06:51:02.147083 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6719 06:51:02.147165
6720 06:51:02.147230
6721 06:51:02.147290 ==
6722 06:51:02.150463 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 06:51:02.153608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 06:51:02.153691 ==
6725 06:51:02.153782
6726 06:51:02.153844
6727 06:51:02.157231 TX Vref Scan disable
6728 06:51:02.157334 == TX Byte 0 ==
6729 06:51:02.163776 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 06:51:02.167097 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 06:51:02.167179 == TX Byte 1 ==
6732 06:51:02.173937 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 06:51:02.177166 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 06:51:02.177248 ==
6735 06:51:02.180505 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 06:51:02.183918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 06:51:02.184002 ==
6738 06:51:02.184068
6739 06:51:02.184129
6740 06:51:02.187368 TX Vref Scan disable
6741 06:51:02.187450 == TX Byte 0 ==
6742 06:51:02.193721 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 06:51:02.197342 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 06:51:02.197425 == TX Byte 1 ==
6745 06:51:02.203436 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 06:51:02.206843 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 06:51:02.206926
6748 06:51:02.206991 [DATLAT]
6749 06:51:02.210332 Freq=400, CH1 RK0
6750 06:51:02.210415
6751 06:51:02.210480 DATLAT Default: 0xf
6752 06:51:02.213751 0, 0xFFFF, sum = 0
6753 06:51:02.213899 1, 0xFFFF, sum = 0
6754 06:51:02.217188 2, 0xFFFF, sum = 0
6755 06:51:02.217296 3, 0xFFFF, sum = 0
6756 06:51:02.220633 4, 0xFFFF, sum = 0
6757 06:51:02.220717 5, 0xFFFF, sum = 0
6758 06:51:02.224087 6, 0xFFFF, sum = 0
6759 06:51:02.224185 7, 0xFFFF, sum = 0
6760 06:51:02.227457 8, 0xFFFF, sum = 0
6761 06:51:02.227541 9, 0xFFFF, sum = 0
6762 06:51:02.230203 10, 0xFFFF, sum = 0
6763 06:51:02.230287 11, 0xFFFF, sum = 0
6764 06:51:02.233934 12, 0xFFFF, sum = 0
6765 06:51:02.234034 13, 0x0, sum = 1
6766 06:51:02.237432 14, 0x0, sum = 2
6767 06:51:02.237516 15, 0x0, sum = 3
6768 06:51:02.240268 16, 0x0, sum = 4
6769 06:51:02.240376 best_step = 14
6770 06:51:02.240443
6771 06:51:02.240505 ==
6772 06:51:02.243676 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 06:51:02.250699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 06:51:02.250783 ==
6775 06:51:02.250849 RX Vref Scan: 1
6776 06:51:02.250912
6777 06:51:02.253587 RX Vref 0 -> 0, step: 1
6778 06:51:02.253669
6779 06:51:02.257074 RX Delay -311 -> 252, step: 8
6780 06:51:02.257157
6781 06:51:02.260478 Set Vref, RX VrefLevel [Byte0]: 52
6782 06:51:02.263708 [Byte1]: 53
6783 06:51:02.263791
6784 06:51:02.267106 Final RX Vref Byte 0 = 52 to rank0
6785 06:51:02.270199 Final RX Vref Byte 1 = 53 to rank0
6786 06:51:02.273357 Final RX Vref Byte 0 = 52 to rank1
6787 06:51:02.276740 Final RX Vref Byte 1 = 53 to rank1==
6788 06:51:02.280260 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 06:51:02.286787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 06:51:02.286870 ==
6791 06:51:02.286936 DQS Delay:
6792 06:51:02.290166 DQS0 = 32, DQS1 = 32
6793 06:51:02.290282 DQM Delay:
6794 06:51:02.290348 DQM0 = 13, DQM1 = 9
6795 06:51:02.293323 DQ Delay:
6796 06:51:02.296966 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6797 06:51:02.297049 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6798 06:51:02.299949 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6799 06:51:02.303444 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6800 06:51:02.303527
6801 06:51:02.303591
6802 06:51:02.313215 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6803 06:51:02.316598 CH1 RK0: MR19=C0C, MR18=8FC8
6804 06:51:02.323422 CH1_RK0: MR19=0xC0C, MR18=0x8FC8, DQSOSC=385, MR23=63, INC=398, DEC=265
6805 06:51:02.323506 ==
6806 06:51:02.326226 Dram Type= 6, Freq= 0, CH_1, rank 1
6807 06:51:02.329610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 06:51:02.329707 ==
6809 06:51:02.333152 [Gating] SW mode calibration
6810 06:51:02.340082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6811 06:51:02.346373 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6812 06:51:02.349794 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 06:51:02.353210 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 06:51:02.359467 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 06:51:02.362948 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 06:51:02.366394 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 06:51:02.369427 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 06:51:02.376750 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 06:51:02.379444 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 06:51:02.382828 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 06:51:02.386210 Total UI for P1: 0, mck2ui 16
6822 06:51:02.389679 best dqsien dly found for B0: ( 0, 14, 24)
6823 06:51:02.392862 Total UI for P1: 0, mck2ui 16
6824 06:51:02.396272 best dqsien dly found for B1: ( 0, 14, 24)
6825 06:51:02.399320 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6826 06:51:02.403243 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6827 06:51:02.406479
6828 06:51:02.409590 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 06:51:02.412823 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 06:51:02.415937 [Gating] SW calibration Done
6831 06:51:02.416038 ==
6832 06:51:02.419586 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 06:51:02.422577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 06:51:02.422689 ==
6835 06:51:02.422771 RX Vref Scan: 0
6836 06:51:02.425867
6837 06:51:02.425952 RX Vref 0 -> 0, step: 1
6838 06:51:02.426038
6839 06:51:02.429348 RX Delay -410 -> 252, step: 16
6840 06:51:02.432807 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6841 06:51:02.439616 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6842 06:51:02.442462 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6843 06:51:02.446008 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6844 06:51:02.449469 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6845 06:51:02.455800 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6846 06:51:02.459341 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6847 06:51:02.462854 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6848 06:51:02.465712 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6849 06:51:02.472782 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6850 06:51:02.476185 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6851 06:51:02.479542 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6852 06:51:02.482319 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6853 06:51:02.489137 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6854 06:51:02.492429 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6855 06:51:02.495957 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6856 06:51:02.496033 ==
6857 06:51:02.499400 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 06:51:02.502899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 06:51:02.505663 ==
6860 06:51:02.505780 DQS Delay:
6861 06:51:02.505888 DQS0 = 27, DQS1 = 35
6862 06:51:02.509052 DQM Delay:
6863 06:51:02.509173 DQM0 = 11, DQM1 = 14
6864 06:51:02.512380 DQ Delay:
6865 06:51:02.512489 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6866 06:51:02.515850 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6867 06:51:02.519310 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6868 06:51:02.522862 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6869 06:51:02.522974
6870 06:51:02.523075
6871 06:51:02.523168 ==
6872 06:51:02.525651 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 06:51:02.532309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 06:51:02.532427 ==
6875 06:51:02.532526
6876 06:51:02.532615
6877 06:51:02.532710 TX Vref Scan disable
6878 06:51:02.535874 == TX Byte 0 ==
6879 06:51:02.538908 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6880 06:51:02.542571 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6881 06:51:02.545636 == TX Byte 1 ==
6882 06:51:02.549064 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6883 06:51:02.552279 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6884 06:51:02.552406 ==
6885 06:51:02.555494 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 06:51:02.562291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 06:51:02.562422 ==
6888 06:51:02.562546
6889 06:51:02.562656
6890 06:51:02.565618 TX Vref Scan disable
6891 06:51:02.565709 == TX Byte 0 ==
6892 06:51:02.569147 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6893 06:51:02.572041 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6894 06:51:02.575562 == TX Byte 1 ==
6895 06:51:02.579141 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6896 06:51:02.582518 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6897 06:51:02.582636
6898 06:51:02.585519 [DATLAT]
6899 06:51:02.585610 Freq=400, CH1 RK1
6900 06:51:02.585704
6901 06:51:02.589065 DATLAT Default: 0xe
6902 06:51:02.589153 0, 0xFFFF, sum = 0
6903 06:51:02.592541 1, 0xFFFF, sum = 0
6904 06:51:02.592632 2, 0xFFFF, sum = 0
6905 06:51:02.595429 3, 0xFFFF, sum = 0
6906 06:51:02.595518 4, 0xFFFF, sum = 0
6907 06:51:02.598823 5, 0xFFFF, sum = 0
6908 06:51:02.598928 6, 0xFFFF, sum = 0
6909 06:51:02.602164 7, 0xFFFF, sum = 0
6910 06:51:02.602267 8, 0xFFFF, sum = 0
6911 06:51:02.605573 9, 0xFFFF, sum = 0
6912 06:51:02.609080 10, 0xFFFF, sum = 0
6913 06:51:02.609181 11, 0xFFFF, sum = 0
6914 06:51:02.612566 12, 0xFFFF, sum = 0
6915 06:51:02.612681 13, 0x0, sum = 1
6916 06:51:02.615813 14, 0x0, sum = 2
6917 06:51:02.615897 15, 0x0, sum = 3
6918 06:51:02.615985 16, 0x0, sum = 4
6919 06:51:02.619223 best_step = 14
6920 06:51:02.619306
6921 06:51:02.619372 ==
6922 06:51:02.622537 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 06:51:02.625267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 06:51:02.625364 ==
6925 06:51:02.628826 RX Vref Scan: 0
6926 06:51:02.628910
6927 06:51:02.629006 RX Vref 0 -> 0, step: 1
6928 06:51:02.632338
6929 06:51:02.632422 RX Delay -311 -> 252, step: 8
6930 06:51:02.640844 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6931 06:51:02.643710 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6932 06:51:02.647259 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6933 06:51:02.650675 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6934 06:51:02.657342 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6935 06:51:02.660586 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6936 06:51:02.663600 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6937 06:51:02.667080 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6938 06:51:02.673484 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6939 06:51:02.677110 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6940 06:51:02.680606 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6941 06:51:02.683910 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6942 06:51:02.690094 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6943 06:51:02.693699 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6944 06:51:02.697196 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6945 06:51:02.703689 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6946 06:51:02.703769 ==
6947 06:51:02.707189 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 06:51:02.710550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 06:51:02.710635 ==
6950 06:51:02.710701 DQS Delay:
6951 06:51:02.713885 DQS0 = 28, DQS1 = 32
6952 06:51:02.713962 DQM Delay:
6953 06:51:02.717407 DQM0 = 11, DQM1 = 11
6954 06:51:02.717516 DQ Delay:
6955 06:51:02.720454 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6956 06:51:02.723797 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6957 06:51:02.726983 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6958 06:51:02.730436 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6959 06:51:02.730513
6960 06:51:02.730589
6961 06:51:02.736536 [DQSOSCAuto] RK1, (LSB)MR18= 0xc052, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
6962 06:51:02.740078 CH1 RK1: MR19=C0C, MR18=C052
6963 06:51:02.747127 CH1_RK1: MR19=0xC0C, MR18=0xC052, DQSOSC=386, MR23=63, INC=396, DEC=264
6964 06:51:02.749820 [RxdqsGatingPostProcess] freq 400
6965 06:51:02.753244 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6966 06:51:02.756821 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 06:51:02.760398 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 06:51:02.763142 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 06:51:02.766812 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 06:51:02.770250 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 06:51:02.773624 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 06:51:02.776888 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 06:51:02.780145 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 06:51:02.783515 Pre-setting of DQS Precalculation
6975 06:51:02.786868 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6976 06:51:02.796596 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6977 06:51:02.803353 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6978 06:51:02.803444
6979 06:51:02.803510
6980 06:51:02.806415 [Calibration Summary] 800 Mbps
6981 06:51:02.806506 CH 0, Rank 0
6982 06:51:02.809720 SW Impedance : PASS
6983 06:51:02.809800 DUTY Scan : NO K
6984 06:51:02.813166 ZQ Calibration : PASS
6985 06:51:02.816703 Jitter Meter : NO K
6986 06:51:02.816782 CBT Training : PASS
6987 06:51:02.820162 Write leveling : PASS
6988 06:51:02.823452 RX DQS gating : PASS
6989 06:51:02.823526 RX DQ/DQS(RDDQC) : PASS
6990 06:51:02.826155 TX DQ/DQS : PASS
6991 06:51:02.829905 RX DATLAT : PASS
6992 06:51:02.829990 RX DQ/DQS(Engine): PASS
6993 06:51:02.833305 TX OE : NO K
6994 06:51:02.833390 All Pass.
6995 06:51:02.833457
6996 06:51:02.836574 CH 0, Rank 1
6997 06:51:02.836658 SW Impedance : PASS
6998 06:51:02.839901 DUTY Scan : NO K
6999 06:51:02.843501 ZQ Calibration : PASS
7000 06:51:02.843586 Jitter Meter : NO K
7001 06:51:02.846676 CBT Training : PASS
7002 06:51:02.846763 Write leveling : NO K
7003 06:51:02.849556 RX DQS gating : PASS
7004 06:51:02.853048 RX DQ/DQS(RDDQC) : PASS
7005 06:51:02.853136 TX DQ/DQS : PASS
7006 06:51:02.856431 RX DATLAT : PASS
7007 06:51:02.859978 RX DQ/DQS(Engine): PASS
7008 06:51:02.860065 TX OE : NO K
7009 06:51:02.862876 All Pass.
7010 06:51:02.862963
7011 06:51:02.863051 CH 1, Rank 0
7012 06:51:02.866346 SW Impedance : PASS
7013 06:51:02.866433 DUTY Scan : NO K
7014 06:51:02.869227 ZQ Calibration : PASS
7015 06:51:02.872834 Jitter Meter : NO K
7016 06:51:02.872921 CBT Training : PASS
7017 06:51:02.876450 Write leveling : PASS
7018 06:51:02.879173 RX DQS gating : PASS
7019 06:51:02.879260 RX DQ/DQS(RDDQC) : PASS
7020 06:51:02.882569 TX DQ/DQS : PASS
7021 06:51:02.886099 RX DATLAT : PASS
7022 06:51:02.886186 RX DQ/DQS(Engine): PASS
7023 06:51:02.889472 TX OE : NO K
7024 06:51:02.889560 All Pass.
7025 06:51:02.889649
7026 06:51:02.893101 CH 1, Rank 1
7027 06:51:02.893188 SW Impedance : PASS
7028 06:51:02.895802 DUTY Scan : NO K
7029 06:51:02.899343 ZQ Calibration : PASS
7030 06:51:02.899430 Jitter Meter : NO K
7031 06:51:02.902813 CBT Training : PASS
7032 06:51:02.902899 Write leveling : NO K
7033 06:51:02.906051 RX DQS gating : PASS
7034 06:51:02.909290 RX DQ/DQS(RDDQC) : PASS
7035 06:51:02.909376 TX DQ/DQS : PASS
7036 06:51:02.912550 RX DATLAT : PASS
7037 06:51:02.915933 RX DQ/DQS(Engine): PASS
7038 06:51:02.916020 TX OE : NO K
7039 06:51:02.919337 All Pass.
7040 06:51:02.919423
7041 06:51:02.919512 DramC Write-DBI off
7042 06:51:02.922540 PER_BANK_REFRESH: Hybrid Mode
7043 06:51:02.925678 TX_TRACKING: ON
7044 06:51:02.932587 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7045 06:51:02.935726 [FAST_K] Save calibration result to emmc
7046 06:51:02.942371 dramc_set_vcore_voltage set vcore to 725000
7047 06:51:02.942464 Read voltage for 1600, 0
7048 06:51:02.942569 Vio18 = 0
7049 06:51:02.945527 Vcore = 725000
7050 06:51:02.945607 Vdram = 0
7051 06:51:02.945691 Vddq = 0
7052 06:51:02.948884 Vmddr = 0
7053 06:51:02.952164 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7054 06:51:02.958828 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7055 06:51:02.962377 MEM_TYPE=3, freq_sel=13
7056 06:51:02.962492 sv_algorithm_assistance_LP4_3733
7057 06:51:02.968741 ============ PULL DRAM RESETB DOWN ============
7058 06:51:02.972339 ========== PULL DRAM RESETB DOWN end =========
7059 06:51:02.975086 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7060 06:51:02.978656 ===================================
7061 06:51:02.982202 LPDDR4 DRAM CONFIGURATION
7062 06:51:02.985136 ===================================
7063 06:51:02.988529 EX_ROW_EN[0] = 0x0
7064 06:51:02.988643 EX_ROW_EN[1] = 0x0
7065 06:51:02.991870 LP4Y_EN = 0x0
7066 06:51:02.991946 WORK_FSP = 0x1
7067 06:51:02.995354 WL = 0x5
7068 06:51:02.995427 RL = 0x5
7069 06:51:02.998893 BL = 0x2
7070 06:51:02.998972 RPST = 0x0
7071 06:51:03.002407 RD_PRE = 0x0
7072 06:51:03.002480 WR_PRE = 0x1
7073 06:51:03.005248 WR_PST = 0x1
7074 06:51:03.005327 DBI_WR = 0x0
7075 06:51:03.008546 DBI_RD = 0x0
7076 06:51:03.008616 OTF = 0x1
7077 06:51:03.012219 ===================================
7078 06:51:03.015256 ===================================
7079 06:51:03.019173 ANA top config
7080 06:51:03.021874 ===================================
7081 06:51:03.025175 DLL_ASYNC_EN = 0
7082 06:51:03.025262 ALL_SLAVE_EN = 0
7083 06:51:03.028737 NEW_RANK_MODE = 1
7084 06:51:03.032079 DLL_IDLE_MODE = 1
7085 06:51:03.035623 LP45_APHY_COMB_EN = 1
7086 06:51:03.035719 TX_ODT_DIS = 0
7087 06:51:03.038437 NEW_8X_MODE = 1
7088 06:51:03.042049 ===================================
7089 06:51:03.045160 ===================================
7090 06:51:03.048337 data_rate = 3200
7091 06:51:03.052223 CKR = 1
7092 06:51:03.055497 DQ_P2S_RATIO = 8
7093 06:51:03.058550 ===================================
7094 06:51:03.062322 CA_P2S_RATIO = 8
7095 06:51:03.062438 DQ_CA_OPEN = 0
7096 06:51:03.065691 DQ_SEMI_OPEN = 0
7097 06:51:03.068591 CA_SEMI_OPEN = 0
7098 06:51:03.072154 CA_FULL_RATE = 0
7099 06:51:03.075017 DQ_CKDIV4_EN = 0
7100 06:51:03.078438 CA_CKDIV4_EN = 0
7101 06:51:03.078544 CA_PREDIV_EN = 0
7102 06:51:03.081927 PH8_DLY = 12
7103 06:51:03.085313 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7104 06:51:03.088808 DQ_AAMCK_DIV = 4
7105 06:51:03.092072 CA_AAMCK_DIV = 4
7106 06:51:03.095528 CA_ADMCK_DIV = 4
7107 06:51:03.095641 DQ_TRACK_CA_EN = 0
7108 06:51:03.098310 CA_PICK = 1600
7109 06:51:03.101817 CA_MCKIO = 1600
7110 06:51:03.105438 MCKIO_SEMI = 0
7111 06:51:03.108298 PLL_FREQ = 3068
7112 06:51:03.111849 DQ_UI_PI_RATIO = 32
7113 06:51:03.115433 CA_UI_PI_RATIO = 0
7114 06:51:03.118176 ===================================
7115 06:51:03.121638 ===================================
7116 06:51:03.121721 memory_type:LPDDR4
7117 06:51:03.125083 GP_NUM : 10
7118 06:51:03.128450 SRAM_EN : 1
7119 06:51:03.128537 MD32_EN : 0
7120 06:51:03.131624 ===================================
7121 06:51:03.134878 [ANA_INIT] >>>>>>>>>>>>>>
7122 06:51:03.138129 <<<<<< [CONFIGURE PHASE]: ANA_TX
7123 06:51:03.141766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7124 06:51:03.145281 ===================================
7125 06:51:03.148186 data_rate = 3200,PCW = 0X7600
7126 06:51:03.151632 ===================================
7127 06:51:03.155119 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7128 06:51:03.158441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 06:51:03.164776 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 06:51:03.168148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7131 06:51:03.171506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7132 06:51:03.175049 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7133 06:51:03.178548 [ANA_INIT] flow start
7134 06:51:03.181817 [ANA_INIT] PLL >>>>>>>>
7135 06:51:03.181931 [ANA_INIT] PLL <<<<<<<<
7136 06:51:03.184551 [ANA_INIT] MIDPI >>>>>>>>
7137 06:51:03.188186 [ANA_INIT] MIDPI <<<<<<<<
7138 06:51:03.188261 [ANA_INIT] DLL >>>>>>>>
7139 06:51:03.191243 [ANA_INIT] DLL <<<<<<<<
7140 06:51:03.195021 [ANA_INIT] flow end
7141 06:51:03.198273 ============ LP4 DIFF to SE enter ============
7142 06:51:03.201420 ============ LP4 DIFF to SE exit ============
7143 06:51:03.205235 [ANA_INIT] <<<<<<<<<<<<<
7144 06:51:03.208180 [Flow] Enable top DCM control >>>>>
7145 06:51:03.211739 [Flow] Enable top DCM control <<<<<
7146 06:51:03.214569 Enable DLL master slave shuffle
7147 06:51:03.218043 ==============================================================
7148 06:51:03.221537 Gating Mode config
7149 06:51:03.227880 ==============================================================
7150 06:51:03.227960 Config description:
7151 06:51:03.238253 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7152 06:51:03.244907 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7153 06:51:03.251220 SELPH_MODE 0: By rank 1: By Phase
7154 06:51:03.254853 ==============================================================
7155 06:51:03.258421 GAT_TRACK_EN = 1
7156 06:51:03.261190 RX_GATING_MODE = 2
7157 06:51:03.264750 RX_GATING_TRACK_MODE = 2
7158 06:51:03.268066 SELPH_MODE = 1
7159 06:51:03.271536 PICG_EARLY_EN = 1
7160 06:51:03.274998 VALID_LAT_VALUE = 1
7161 06:51:03.278461 ==============================================================
7162 06:51:03.281347 Enter into Gating configuration >>>>
7163 06:51:03.284746 Exit from Gating configuration <<<<
7164 06:51:03.287768 Enter into DVFS_PRE_config >>>>>
7165 06:51:03.301499 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7166 06:51:03.301614 Exit from DVFS_PRE_config <<<<<
7167 06:51:03.304303 Enter into PICG configuration >>>>
7168 06:51:03.307915 Exit from PICG configuration <<<<
7169 06:51:03.311385 [RX_INPUT] configuration >>>>>
7170 06:51:03.314225 [RX_INPUT] configuration <<<<<
7171 06:51:03.321568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7172 06:51:03.324382 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7173 06:51:03.331523 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 06:51:03.337841 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 06:51:03.344215 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 06:51:03.351374 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 06:51:03.354065 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7178 06:51:03.357982 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7179 06:51:03.361445 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7180 06:51:03.367379 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7181 06:51:03.371134 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7182 06:51:03.374200 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7183 06:51:03.377324 ===================================
7184 06:51:03.381337 LPDDR4 DRAM CONFIGURATION
7185 06:51:03.384576 ===================================
7186 06:51:03.384687 EX_ROW_EN[0] = 0x0
7187 06:51:03.387753 EX_ROW_EN[1] = 0x0
7188 06:51:03.390602 LP4Y_EN = 0x0
7189 06:51:03.390690 WORK_FSP = 0x1
7190 06:51:03.394018 WL = 0x5
7191 06:51:03.394105 RL = 0x5
7192 06:51:03.397426 BL = 0x2
7193 06:51:03.397497 RPST = 0x0
7194 06:51:03.400923 RD_PRE = 0x0
7195 06:51:03.401013 WR_PRE = 0x1
7196 06:51:03.403755 WR_PST = 0x1
7197 06:51:03.403831 DBI_WR = 0x0
7198 06:51:03.407288 DBI_RD = 0x0
7199 06:51:03.407367 OTF = 0x1
7200 06:51:03.410731 ===================================
7201 06:51:03.414251 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7202 06:51:03.420520 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7203 06:51:03.423858 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 06:51:03.427312 ===================================
7205 06:51:03.430497 LPDDR4 DRAM CONFIGURATION
7206 06:51:03.433641 ===================================
7207 06:51:03.433726 EX_ROW_EN[0] = 0x10
7208 06:51:03.437221 EX_ROW_EN[1] = 0x0
7209 06:51:03.440682 LP4Y_EN = 0x0
7210 06:51:03.440787 WORK_FSP = 0x1
7211 06:51:03.443694 WL = 0x5
7212 06:51:03.443773 RL = 0x5
7213 06:51:03.446976 BL = 0x2
7214 06:51:03.447055 RPST = 0x0
7215 06:51:03.450297 RD_PRE = 0x0
7216 06:51:03.450381 WR_PRE = 0x1
7217 06:51:03.453753 WR_PST = 0x1
7218 06:51:03.453840 DBI_WR = 0x0
7219 06:51:03.457387 DBI_RD = 0x0
7220 06:51:03.457470 OTF = 0x1
7221 06:51:03.460220 ===================================
7222 06:51:03.467327 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7223 06:51:03.467410 ==
7224 06:51:03.470732 Dram Type= 6, Freq= 0, CH_0, rank 0
7225 06:51:03.474155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7226 06:51:03.474231 ==
7227 06:51:03.477565 [Duty_Offset_Calibration]
7228 06:51:03.480984 B0:2 B1:1 CA:1
7229 06:51:03.481070
7230 06:51:03.483641 [DutyScan_Calibration_Flow] k_type=0
7231 06:51:03.492263
7232 06:51:03.492355 ==CLK 0==
7233 06:51:03.495581 Final CLK duty delay cell = 0
7234 06:51:03.498930 [0] MAX Duty = 5156%(X100), DQS PI = 22
7235 06:51:03.502143 [0] MIN Duty = 4875%(X100), DQS PI = 46
7236 06:51:03.505920 [0] AVG Duty = 5015%(X100)
7237 06:51:03.505995
7238 06:51:03.509212 CH0 CLK Duty spec in!! Max-Min= 281%
7239 06:51:03.512651 [DutyScan_Calibration_Flow] ====Done====
7240 06:51:03.512737
7241 06:51:03.515444 [DutyScan_Calibration_Flow] k_type=1
7242 06:51:03.531585
7243 06:51:03.531666 ==DQS 0 ==
7244 06:51:03.535052 Final DQS duty delay cell = -4
7245 06:51:03.538483 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7246 06:51:03.541489 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7247 06:51:03.544911 [-4] AVG Duty = 4922%(X100)
7248 06:51:03.544988
7249 06:51:03.545061 ==DQS 1 ==
7250 06:51:03.548236 Final DQS duty delay cell = 0
7251 06:51:03.551591 [0] MAX Duty = 5187%(X100), DQS PI = 4
7252 06:51:03.555352 [0] MIN Duty = 5062%(X100), DQS PI = 32
7253 06:51:03.558191 [0] AVG Duty = 5124%(X100)
7254 06:51:03.558274
7255 06:51:03.561191 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7256 06:51:03.561276
7257 06:51:03.564561 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7258 06:51:03.568083 [DutyScan_Calibration_Flow] ====Done====
7259 06:51:03.568168
7260 06:51:03.571259 [DutyScan_Calibration_Flow] k_type=3
7261 06:51:03.588090
7262 06:51:03.588180 ==DQM 0 ==
7263 06:51:03.591605 Final DQM duty delay cell = 0
7264 06:51:03.594940 [0] MAX Duty = 5218%(X100), DQS PI = 34
7265 06:51:03.598373 [0] MIN Duty = 4907%(X100), DQS PI = 56
7266 06:51:03.601187 [0] AVG Duty = 5062%(X100)
7267 06:51:03.601272
7268 06:51:03.601339 ==DQM 1 ==
7269 06:51:03.604654 Final DQM duty delay cell = -4
7270 06:51:03.608168 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7271 06:51:03.611626 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7272 06:51:03.615698 [-4] AVG Duty = 4891%(X100)
7273 06:51:03.615775
7274 06:51:03.618267 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7275 06:51:03.618350
7276 06:51:03.621278 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7277 06:51:03.625274 [DutyScan_Calibration_Flow] ====Done====
7278 06:51:03.625368
7279 06:51:03.628037 [DutyScan_Calibration_Flow] k_type=2
7280 06:51:03.645804
7281 06:51:03.645884 ==DQ 0 ==
7282 06:51:03.649395 Final DQ duty delay cell = 0
7283 06:51:03.652282 [0] MAX Duty = 5062%(X100), DQS PI = 26
7284 06:51:03.655901 [0] MIN Duty = 4907%(X100), DQS PI = 0
7285 06:51:03.655982 [0] AVG Duty = 4984%(X100)
7286 06:51:03.656047
7287 06:51:03.659503 ==DQ 1 ==
7288 06:51:03.662253 Final DQ duty delay cell = 0
7289 06:51:03.665803 [0] MAX Duty = 5156%(X100), DQS PI = 22
7290 06:51:03.669120 [0] MIN Duty = 4938%(X100), DQS PI = 34
7291 06:51:03.669197 [0] AVG Duty = 5047%(X100)
7292 06:51:03.669270
7293 06:51:03.672228 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7294 06:51:03.672311
7295 06:51:03.676061 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7296 06:51:03.682537 [DutyScan_Calibration_Flow] ====Done====
7297 06:51:03.682647 ==
7298 06:51:03.685811 Dram Type= 6, Freq= 0, CH_1, rank 0
7299 06:51:03.688870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 06:51:03.688947 ==
7301 06:51:03.692559 [Duty_Offset_Calibration]
7302 06:51:03.692641 B0:1 B1:0 CA:0
7303 06:51:03.692706
7304 06:51:03.695621 [DutyScan_Calibration_Flow] k_type=0
7305 06:51:03.705114
7306 06:51:03.705206 ==CLK 0==
7307 06:51:03.708437 Final CLK duty delay cell = -4
7308 06:51:03.712068 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7309 06:51:03.714862 [-4] MIN Duty = 4875%(X100), DQS PI = 50
7310 06:51:03.718403 [-4] AVG Duty = 4922%(X100)
7311 06:51:03.718486
7312 06:51:03.721920 CH1 CLK Duty spec in!! Max-Min= 94%
7313 06:51:03.725356 [DutyScan_Calibration_Flow] ====Done====
7314 06:51:03.725439
7315 06:51:03.727993 [DutyScan_Calibration_Flow] k_type=1
7316 06:51:03.744507
7317 06:51:03.744615 ==DQS 0 ==
7318 06:51:03.747406 Final DQS duty delay cell = 0
7319 06:51:03.750945 [0] MAX Duty = 5094%(X100), DQS PI = 26
7320 06:51:03.754445 [0] MIN Duty = 4844%(X100), DQS PI = 44
7321 06:51:03.757935 [0] AVG Duty = 4969%(X100)
7322 06:51:03.758018
7323 06:51:03.758082 ==DQS 1 ==
7324 06:51:03.760733 Final DQS duty delay cell = -4
7325 06:51:03.764166 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7326 06:51:03.767675 [-4] MIN Duty = 4750%(X100), DQS PI = 8
7327 06:51:03.771209 [-4] AVG Duty = 4859%(X100)
7328 06:51:03.771292
7329 06:51:03.774018 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7330 06:51:03.774101
7331 06:51:03.777426 CH1 DQS 1 Duty spec in!! Max-Min= 219%
7332 06:51:03.780697 [DutyScan_Calibration_Flow] ====Done====
7333 06:51:03.780779
7334 06:51:03.783849 [DutyScan_Calibration_Flow] k_type=3
7335 06:51:03.801639
7336 06:51:03.801756 ==DQM 0 ==
7337 06:51:03.805025 Final DQM duty delay cell = 0
7338 06:51:03.808334 [0] MAX Duty = 5218%(X100), DQS PI = 18
7339 06:51:03.811685 [0] MIN Duty = 4969%(X100), DQS PI = 48
7340 06:51:03.814822 [0] AVG Duty = 5093%(X100)
7341 06:51:03.814904
7342 06:51:03.814969 ==DQM 1 ==
7343 06:51:03.817944 Final DQM duty delay cell = 0
7344 06:51:03.821656 [0] MAX Duty = 5093%(X100), DQS PI = 16
7345 06:51:03.824520 [0] MIN Duty = 4907%(X100), DQS PI = 50
7346 06:51:03.828291 [0] AVG Duty = 5000%(X100)
7347 06:51:03.828394
7348 06:51:03.831631 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7349 06:51:03.831717
7350 06:51:03.835072 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7351 06:51:03.837812 [DutyScan_Calibration_Flow] ====Done====
7352 06:51:03.837898
7353 06:51:03.841271 [DutyScan_Calibration_Flow] k_type=2
7354 06:51:03.857502
7355 06:51:03.857589 ==DQ 0 ==
7356 06:51:03.860957 Final DQ duty delay cell = -4
7357 06:51:03.864493 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7358 06:51:03.867966 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7359 06:51:03.870862 [-4] AVG Duty = 4968%(X100)
7360 06:51:03.870944
7361 06:51:03.871009 ==DQ 1 ==
7362 06:51:03.874338 Final DQ duty delay cell = 0
7363 06:51:03.877918 [0] MAX Duty = 5156%(X100), DQS PI = 18
7364 06:51:03.880754 [0] MIN Duty = 4938%(X100), DQS PI = 10
7365 06:51:03.884202 [0] AVG Duty = 5047%(X100)
7366 06:51:03.884296
7367 06:51:03.887599 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7368 06:51:03.887683
7369 06:51:03.890954 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7370 06:51:03.894370 [DutyScan_Calibration_Flow] ====Done====
7371 06:51:03.897753 nWR fixed to 30
7372 06:51:03.901261 [ModeRegInit_LP4] CH0 RK0
7373 06:51:03.901375 [ModeRegInit_LP4] CH0 RK1
7374 06:51:03.904012 [ModeRegInit_LP4] CH1 RK0
7375 06:51:03.907565 [ModeRegInit_LP4] CH1 RK1
7376 06:51:03.907649 match AC timing 5
7377 06:51:03.913844 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7378 06:51:03.917181 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7379 06:51:03.920562 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7380 06:51:03.927543 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7381 06:51:03.930926 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7382 06:51:03.931002 [MiockJmeterHQA]
7383 06:51:03.931065
7384 06:51:03.933684 [DramcMiockJmeter] u1RxGatingPI = 0
7385 06:51:03.937446 0 : 4254, 4027
7386 06:51:03.937531 4 : 4253, 4027
7387 06:51:03.940695 8 : 4257, 4030
7388 06:51:03.940770 12 : 4252, 4027
7389 06:51:03.943893 16 : 4255, 4030
7390 06:51:03.943977 20 : 4252, 4027
7391 06:51:03.944041 24 : 4252, 4026
7392 06:51:03.947108 28 : 4366, 4140
7393 06:51:03.947183 32 : 4252, 4027
7394 06:51:03.950221 36 : 4255, 4029
7395 06:51:03.950308 40 : 4252, 4027
7396 06:51:03.953849 44 : 4363, 4140
7397 06:51:03.953936 48 : 4253, 4026
7398 06:51:03.956783 52 : 4360, 4138
7399 06:51:03.956869 56 : 4250, 4026
7400 06:51:03.956932 60 : 4250, 4027
7401 06:51:03.960642 64 : 4252, 4030
7402 06:51:03.960734 68 : 4253, 4029
7403 06:51:03.964007 72 : 4250, 4027
7404 06:51:03.964116 76 : 4252, 4029
7405 06:51:03.967231 80 : 4363, 4140
7406 06:51:03.967310 84 : 4249, 4027
7407 06:51:03.967387 88 : 4253, 87
7408 06:51:03.970258 92 : 4250, 0
7409 06:51:03.970333 96 : 4363, 0
7410 06:51:03.973632 100 : 4250, 0
7411 06:51:03.973712 104 : 4250, 0
7412 06:51:03.973776 108 : 4250, 0
7413 06:51:03.977187 112 : 4250, 0
7414 06:51:03.977260 116 : 4253, 0
7415 06:51:03.977336 120 : 4250, 0
7416 06:51:03.979996 124 : 4361, 0
7417 06:51:03.980076 128 : 4360, 0
7418 06:51:03.983517 132 : 4250, 0
7419 06:51:03.983590 136 : 4360, 0
7420 06:51:03.983660 140 : 4250, 0
7421 06:51:03.986952 144 : 4250, 0
7422 06:51:03.987054 148 : 4250, 0
7423 06:51:03.990541 152 : 4250, 0
7424 06:51:03.990627 156 : 4253, 0
7425 06:51:03.990690 160 : 4361, 0
7426 06:51:03.993184 164 : 4250, 0
7427 06:51:03.993270 168 : 4250, 0
7428 06:51:03.996613 172 : 4250, 0
7429 06:51:03.996687 176 : 4360, 0
7430 06:51:03.996764 180 : 4360, 0
7431 06:51:03.999999 184 : 4250, 0
7432 06:51:04.000102 188 : 4249, 0
7433 06:51:04.003331 192 : 4250, 0
7434 06:51:04.003406 196 : 4252, 0
7435 06:51:04.003483 200 : 4249, 0
7436 06:51:04.006584 204 : 4250, 1165
7437 06:51:04.006661 208 : 4250, 4003
7438 06:51:04.010077 212 : 4361, 4137
7439 06:51:04.010160 216 : 4250, 4026
7440 06:51:04.012888 220 : 4250, 4027
7441 06:51:04.012965 224 : 4360, 4138
7442 06:51:04.016471 228 : 4360, 4137
7443 06:51:04.016546 232 : 4250, 4026
7444 06:51:04.019896 236 : 4363, 4139
7445 06:51:04.019997 240 : 4361, 4137
7446 06:51:04.023291 244 : 4250, 4027
7447 06:51:04.023378 248 : 4250, 4026
7448 06:51:04.023447 252 : 4253, 4029
7449 06:51:04.026505 256 : 4250, 4027
7450 06:51:04.026583 260 : 4250, 4027
7451 06:51:04.030140 264 : 4250, 4026
7452 06:51:04.030223 268 : 4253, 4029
7453 06:51:04.032894 272 : 4250, 4027
7454 06:51:04.032990 276 : 4360, 4138
7455 06:51:04.036476 280 : 4360, 4137
7456 06:51:04.036617 284 : 4250, 4026
7457 06:51:04.039944 288 : 4363, 4139
7458 06:51:04.040027 292 : 4361, 4137
7459 06:51:04.043342 296 : 4250, 4027
7460 06:51:04.043458 300 : 4250, 4026
7461 06:51:04.046636 304 : 4253, 4029
7462 06:51:04.046720 308 : 4250, 3947
7463 06:51:04.046787 312 : 4250, 2083
7464 06:51:04.046848
7465 06:51:04.049952 MIOCK jitter meter ch=0
7466 06:51:04.050035
7467 06:51:04.053476 1T = (312-88) = 224 dly cells
7468 06:51:04.059644 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7469 06:51:04.059742 ==
7470 06:51:04.063089 Dram Type= 6, Freq= 0, CH_0, rank 0
7471 06:51:04.066392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7472 06:51:04.066476 ==
7473 06:51:04.072812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7474 06:51:04.076187 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7475 06:51:04.079501 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7476 06:51:04.086280 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7477 06:51:04.095225 [CA 0] Center 42 (12~73) winsize 62
7478 06:51:04.098378 [CA 1] Center 42 (12~73) winsize 62
7479 06:51:04.101988 [CA 2] Center 37 (7~67) winsize 61
7480 06:51:04.105417 [CA 3] Center 37 (7~67) winsize 61
7481 06:51:04.108844 [CA 4] Center 36 (6~66) winsize 61
7482 06:51:04.112258 [CA 5] Center 35 (6~64) winsize 59
7483 06:51:04.112386
7484 06:51:04.114945 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7485 06:51:04.115064
7486 06:51:04.118540 [CATrainingPosCal] consider 1 rank data
7487 06:51:04.121444 u2DelayCellTimex100 = 290/100 ps
7488 06:51:04.128493 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7489 06:51:04.131919 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7490 06:51:04.135266 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7491 06:51:04.138718 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7492 06:51:04.141557 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7493 06:51:04.145084 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7494 06:51:04.145166
7495 06:51:04.148623 CA PerBit enable=1, Macro0, CA PI delay=35
7496 06:51:04.148705
7497 06:51:04.151988 [CBTSetCACLKResult] CA Dly = 35
7498 06:51:04.155316 CS Dly: 9 (0~40)
7499 06:51:04.158335 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7500 06:51:04.161704 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7501 06:51:04.161857 ==
7502 06:51:04.165112 Dram Type= 6, Freq= 0, CH_0, rank 1
7503 06:51:04.168425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 06:51:04.171305 ==
7505 06:51:04.174847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 06:51:04.178456 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 06:51:04.184700 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 06:51:04.188188 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 06:51:04.198751 [CA 0] Center 42 (12~73) winsize 62
7510 06:51:04.201730 [CA 1] Center 42 (12~73) winsize 62
7511 06:51:04.205173 [CA 2] Center 38 (8~68) winsize 61
7512 06:51:04.208674 [CA 3] Center 37 (8~67) winsize 60
7513 06:51:04.211786 [CA 4] Center 36 (6~66) winsize 61
7514 06:51:04.214801 [CA 5] Center 35 (5~65) winsize 61
7515 06:51:04.214908
7516 06:51:04.218332 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7517 06:51:04.218416
7518 06:51:04.221964 [CATrainingPosCal] consider 2 rank data
7519 06:51:04.225205 u2DelayCellTimex100 = 290/100 ps
7520 06:51:04.228172 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7521 06:51:04.235295 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7522 06:51:04.238057 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7523 06:51:04.241917 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7524 06:51:04.244741 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7525 06:51:04.248270 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7526 06:51:04.248407
7527 06:51:04.251799 CA PerBit enable=1, Macro0, CA PI delay=35
7528 06:51:04.251882
7529 06:51:04.255362 [CBTSetCACLKResult] CA Dly = 35
7530 06:51:04.258158 CS Dly: 10 (0~42)
7531 06:51:04.261536 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 06:51:04.264874 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 06:51:04.264973
7534 06:51:04.268465 ----->DramcWriteLeveling(PI) begin...
7535 06:51:04.268585 ==
7536 06:51:04.271820 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 06:51:04.275261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 06:51:04.278560 ==
7539 06:51:04.278633 Write leveling (Byte 0): 36 => 36
7540 06:51:04.281962 Write leveling (Byte 1): 29 => 29
7541 06:51:04.284814 DramcWriteLeveling(PI) end<-----
7542 06:51:04.284896
7543 06:51:04.284960 ==
7544 06:51:04.288425 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 06:51:04.294774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 06:51:04.294858 ==
7547 06:51:04.294924 [Gating] SW mode calibration
7548 06:51:04.304606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7549 06:51:04.308216 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7550 06:51:04.315036 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 06:51:04.318429 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 06:51:04.321767 1 4 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7553 06:51:04.324572 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7554 06:51:04.331622 1 4 16 | B1->B0 | 2424 3635 | 0 1 | (1 1) (1 1)
7555 06:51:04.334732 1 4 20 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
7556 06:51:04.338332 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7557 06:51:04.344508 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7558 06:51:04.348161 1 5 0 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
7559 06:51:04.351184 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7560 06:51:04.357830 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7561 06:51:04.361379 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7562 06:51:04.364839 1 5 16 | B1->B0 | 3434 2828 | 0 0 | (0 0) (0 0)
7563 06:51:04.371522 1 5 20 | B1->B0 | 2727 2424 | 0 0 | (1 0) (0 0)
7564 06:51:04.375040 1 5 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7565 06:51:04.378547 1 5 28 | B1->B0 | 2323 2222 | 0 1 | (0 0) (1 1)
7566 06:51:04.384711 1 6 0 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7567 06:51:04.388234 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7568 06:51:04.391694 1 6 8 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
7569 06:51:04.398085 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7570 06:51:04.401541 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7571 06:51:04.405055 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 06:51:04.411408 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7573 06:51:04.414737 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 06:51:04.418191 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 06:51:04.424943 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 06:51:04.427804 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 06:51:04.431333 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 06:51:04.438275 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7579 06:51:04.441359 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7580 06:51:04.444873 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 06:51:04.450953 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 06:51:04.454231 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 06:51:04.457588 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 06:51:04.461324 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 06:51:04.467839 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 06:51:04.470906 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 06:51:04.474451 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 06:51:04.481177 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 06:51:04.483902 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 06:51:04.487186 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 06:51:04.494158 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 06:51:04.497693 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 06:51:04.500550 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 06:51:04.507709 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7595 06:51:04.510542 Total UI for P1: 0, mck2ui 16
7596 06:51:04.514130 best dqsien dly found for B0: ( 1, 9, 12)
7597 06:51:04.517687 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 06:51:04.520481 Total UI for P1: 0, mck2ui 16
7599 06:51:04.524025 best dqsien dly found for B1: ( 1, 9, 16)
7600 06:51:04.527476 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7601 06:51:04.530833 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7602 06:51:04.530920
7603 06:51:04.534169 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7604 06:51:04.537135 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7605 06:51:04.540538 [Gating] SW calibration Done
7606 06:51:04.540617 ==
7607 06:51:04.543914 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 06:51:04.550318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 06:51:04.550431 ==
7610 06:51:04.550540 RX Vref Scan: 0
7611 06:51:04.550632
7612 06:51:04.553705 RX Vref 0 -> 0, step: 1
7613 06:51:04.553789
7614 06:51:04.556944 RX Delay 0 -> 252, step: 8
7615 06:51:04.560417 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7616 06:51:04.563931 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7617 06:51:04.566648 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7618 06:51:04.570234 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7619 06:51:04.576876 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7620 06:51:04.580592 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7621 06:51:04.583612 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7622 06:51:04.587235 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7623 06:51:04.590298 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7624 06:51:04.596768 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7625 06:51:04.600258 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7626 06:51:04.603490 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7627 06:51:04.606933 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7628 06:51:04.610276 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7629 06:51:04.616699 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7630 06:51:04.620124 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7631 06:51:04.620203 ==
7632 06:51:04.623588 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 06:51:04.627199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 06:51:04.627279 ==
7635 06:51:04.630700 DQS Delay:
7636 06:51:04.630806 DQS0 = 0, DQS1 = 0
7637 06:51:04.630898 DQM Delay:
7638 06:51:04.633404 DQM0 = 136, DQM1 = 130
7639 06:51:04.633509 DQ Delay:
7640 06:51:04.636755 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7641 06:51:04.640264 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7642 06:51:04.643622 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7643 06:51:04.650546 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7644 06:51:04.650629
7645 06:51:04.650693
7646 06:51:04.650753 ==
7647 06:51:04.653388 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 06:51:04.656860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 06:51:04.656937 ==
7650 06:51:04.657001
7651 06:51:04.657067
7652 06:51:04.660300 TX Vref Scan disable
7653 06:51:04.660384 == TX Byte 0 ==
7654 06:51:04.666638 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7655 06:51:04.670216 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7656 06:51:04.670301 == TX Byte 1 ==
7657 06:51:04.676657 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7658 06:51:04.680185 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7659 06:51:04.680259 ==
7660 06:51:04.683669 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 06:51:04.687099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 06:51:04.687201 ==
7663 06:51:04.701578
7664 06:51:04.704309 TX Vref early break, caculate TX vref
7665 06:51:04.707746 TX Vref=16, minBit 4, minWin=22, winSum=376
7666 06:51:04.711562 TX Vref=18, minBit 0, minWin=23, winSum=388
7667 06:51:04.714983 TX Vref=20, minBit 0, minWin=24, winSum=399
7668 06:51:04.718213 TX Vref=22, minBit 0, minWin=24, winSum=405
7669 06:51:04.721584 TX Vref=24, minBit 4, minWin=24, winSum=409
7670 06:51:04.724938 TX Vref=26, minBit 0, minWin=25, winSum=423
7671 06:51:04.731189 TX Vref=28, minBit 7, minWin=24, winSum=421
7672 06:51:04.734547 TX Vref=30, minBit 2, minWin=24, winSum=411
7673 06:51:04.738033 TX Vref=32, minBit 8, minWin=23, winSum=403
7674 06:51:04.741487 TX Vref=34, minBit 1, minWin=23, winSum=394
7675 06:51:04.747657 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
7676 06:51:04.747749
7677 06:51:04.750930 Final TX Range 0 Vref 26
7678 06:51:04.751007
7679 06:51:04.751077 ==
7680 06:51:04.754517 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 06:51:04.757425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 06:51:04.757498 ==
7683 06:51:04.757588
7684 06:51:04.757684
7685 06:51:04.760867 TX Vref Scan disable
7686 06:51:04.767861 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7687 06:51:04.767962 == TX Byte 0 ==
7688 06:51:04.771360 u2DelayCellOfst[0]=10 cells (3 PI)
7689 06:51:04.774234 u2DelayCellOfst[1]=13 cells (4 PI)
7690 06:51:04.777796 u2DelayCellOfst[2]=10 cells (3 PI)
7691 06:51:04.781246 u2DelayCellOfst[3]=6 cells (2 PI)
7692 06:51:04.784765 u2DelayCellOfst[4]=6 cells (2 PI)
7693 06:51:04.787723 u2DelayCellOfst[5]=0 cells (0 PI)
7694 06:51:04.787800 u2DelayCellOfst[6]=16 cells (5 PI)
7695 06:51:04.791337 u2DelayCellOfst[7]=16 cells (5 PI)
7696 06:51:04.797433 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7697 06:51:04.800867 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7698 06:51:04.800946 == TX Byte 1 ==
7699 06:51:04.804478 u2DelayCellOfst[8]=0 cells (0 PI)
7700 06:51:04.807877 u2DelayCellOfst[9]=0 cells (0 PI)
7701 06:51:04.810804 u2DelayCellOfst[10]=6 cells (2 PI)
7702 06:51:04.814393 u2DelayCellOfst[11]=6 cells (2 PI)
7703 06:51:04.817901 u2DelayCellOfst[12]=10 cells (3 PI)
7704 06:51:04.820632 u2DelayCellOfst[13]=10 cells (3 PI)
7705 06:51:04.824232 u2DelayCellOfst[14]=16 cells (5 PI)
7706 06:51:04.827723 u2DelayCellOfst[15]=10 cells (3 PI)
7707 06:51:04.830572 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7708 06:51:04.837129 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7709 06:51:04.837209 DramC Write-DBI on
7710 06:51:04.837273 ==
7711 06:51:04.840915 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 06:51:04.843869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 06:51:04.843945 ==
7714 06:51:04.847399
7715 06:51:04.847480
7716 06:51:04.847549 TX Vref Scan disable
7717 06:51:04.850811 == TX Byte 0 ==
7718 06:51:04.853783 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7719 06:51:04.857061 == TX Byte 1 ==
7720 06:51:04.860735 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7721 06:51:04.860823 DramC Write-DBI off
7722 06:51:04.863854
7723 06:51:04.863934 [DATLAT]
7724 06:51:04.864002 Freq=1600, CH0 RK0
7725 06:51:04.864103
7726 06:51:04.867517 DATLAT Default: 0xf
7727 06:51:04.867605 0, 0xFFFF, sum = 0
7728 06:51:04.870635 1, 0xFFFF, sum = 0
7729 06:51:04.870717 2, 0xFFFF, sum = 0
7730 06:51:04.874115 3, 0xFFFF, sum = 0
7731 06:51:04.877605 4, 0xFFFF, sum = 0
7732 06:51:04.877696 5, 0xFFFF, sum = 0
7733 06:51:04.880961 6, 0xFFFF, sum = 0
7734 06:51:04.881049 7, 0xFFFF, sum = 0
7735 06:51:04.883793 8, 0xFFFF, sum = 0
7736 06:51:04.883888 9, 0xFFFF, sum = 0
7737 06:51:04.887276 10, 0xFFFF, sum = 0
7738 06:51:04.887361 11, 0xFFFF, sum = 0
7739 06:51:04.890759 12, 0xFFFF, sum = 0
7740 06:51:04.890844 13, 0xFFFF, sum = 0
7741 06:51:04.894335 14, 0x0, sum = 1
7742 06:51:04.894420 15, 0x0, sum = 2
7743 06:51:04.897246 16, 0x0, sum = 3
7744 06:51:04.897331 17, 0x0, sum = 4
7745 06:51:04.900666 best_step = 15
7746 06:51:04.900749
7747 06:51:04.900815 ==
7748 06:51:04.903991 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 06:51:04.907274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 06:51:04.907371 ==
7751 06:51:04.907471 RX Vref Scan: 1
7752 06:51:04.907567
7753 06:51:04.910704 Set Vref Range= 24 -> 127
7754 06:51:04.910788
7755 06:51:04.914097 RX Vref 24 -> 127, step: 1
7756 06:51:04.914181
7757 06:51:04.917512 RX Delay 19 -> 252, step: 4
7758 06:51:04.917596
7759 06:51:04.920265 Set Vref, RX VrefLevel [Byte0]: 24
7760 06:51:04.923684 [Byte1]: 24
7761 06:51:04.923768
7762 06:51:04.927340 Set Vref, RX VrefLevel [Byte0]: 25
7763 06:51:04.930174 [Byte1]: 25
7764 06:51:04.930255
7765 06:51:04.933604 Set Vref, RX VrefLevel [Byte0]: 26
7766 06:51:04.937176 [Byte1]: 26
7767 06:51:04.940686
7768 06:51:04.940770 Set Vref, RX VrefLevel [Byte0]: 27
7769 06:51:04.944125 [Byte1]: 27
7770 06:51:04.948416
7771 06:51:04.948500 Set Vref, RX VrefLevel [Byte0]: 28
7772 06:51:04.951842 [Byte1]: 28
7773 06:51:04.955755
7774 06:51:04.955845 Set Vref, RX VrefLevel [Byte0]: 29
7775 06:51:04.958992 [Byte1]: 29
7776 06:51:04.963300
7777 06:51:04.963393 Set Vref, RX VrefLevel [Byte0]: 30
7778 06:51:04.967172 [Byte1]: 30
7779 06:51:04.971105
7780 06:51:04.971187 Set Vref, RX VrefLevel [Byte0]: 31
7781 06:51:04.974344 [Byte1]: 31
7782 06:51:04.978818
7783 06:51:04.978897 Set Vref, RX VrefLevel [Byte0]: 32
7784 06:51:04.981943 [Byte1]: 32
7785 06:51:04.986091
7786 06:51:04.986174 Set Vref, RX VrefLevel [Byte0]: 33
7787 06:51:04.989626 [Byte1]: 33
7788 06:51:04.993966
7789 06:51:04.994051 Set Vref, RX VrefLevel [Byte0]: 34
7790 06:51:04.997273 [Byte1]: 34
7791 06:51:05.001399
7792 06:51:05.001479 Set Vref, RX VrefLevel [Byte0]: 35
7793 06:51:05.005086 [Byte1]: 35
7794 06:51:05.009232
7795 06:51:05.009316 Set Vref, RX VrefLevel [Byte0]: 36
7796 06:51:05.012482 [Byte1]: 36
7797 06:51:05.016536
7798 06:51:05.016629 Set Vref, RX VrefLevel [Byte0]: 37
7799 06:51:05.019944 [Byte1]: 37
7800 06:51:05.024003
7801 06:51:05.024112 Set Vref, RX VrefLevel [Byte0]: 38
7802 06:51:05.027461 [Byte1]: 38
7803 06:51:05.031710
7804 06:51:05.031788 Set Vref, RX VrefLevel [Byte0]: 39
7805 06:51:05.035126 [Byte1]: 39
7806 06:51:05.039229
7807 06:51:05.039315 Set Vref, RX VrefLevel [Byte0]: 40
7808 06:51:05.042822 [Byte1]: 40
7809 06:51:05.046995
7810 06:51:05.047085 Set Vref, RX VrefLevel [Byte0]: 41
7811 06:51:05.049877 [Byte1]: 41
7812 06:51:05.054190
7813 06:51:05.054276 Set Vref, RX VrefLevel [Byte0]: 42
7814 06:51:05.057734 [Byte1]: 42
7815 06:51:05.061800
7816 06:51:05.061884 Set Vref, RX VrefLevel [Byte0]: 43
7817 06:51:05.065275 [Byte1]: 43
7818 06:51:05.069326
7819 06:51:05.069408 Set Vref, RX VrefLevel [Byte0]: 44
7820 06:51:05.072586 [Byte1]: 44
7821 06:51:05.077261
7822 06:51:05.077348 Set Vref, RX VrefLevel [Byte0]: 45
7823 06:51:05.080499 [Byte1]: 45
7824 06:51:05.084748
7825 06:51:05.084843 Set Vref, RX VrefLevel [Byte0]: 46
7826 06:51:05.088233 [Byte1]: 46
7827 06:51:05.092323
7828 06:51:05.092435 Set Vref, RX VrefLevel [Byte0]: 47
7829 06:51:05.095730 [Byte1]: 47
7830 06:51:05.099703
7831 06:51:05.099788 Set Vref, RX VrefLevel [Byte0]: 48
7832 06:51:05.103517 [Byte1]: 48
7833 06:51:05.107195
7834 06:51:05.107280 Set Vref, RX VrefLevel [Byte0]: 49
7835 06:51:05.110497 [Byte1]: 49
7836 06:51:05.114957
7837 06:51:05.115071 Set Vref, RX VrefLevel [Byte0]: 50
7838 06:51:05.118154 [Byte1]: 50
7839 06:51:05.122363
7840 06:51:05.122491 Set Vref, RX VrefLevel [Byte0]: 51
7841 06:51:05.125798 [Byte1]: 51
7842 06:51:05.130379
7843 06:51:05.130539 Set Vref, RX VrefLevel [Byte0]: 52
7844 06:51:05.133464 [Byte1]: 52
7845 06:51:05.137503
7846 06:51:05.137590 Set Vref, RX VrefLevel [Byte0]: 53
7847 06:51:05.141084 [Byte1]: 53
7848 06:51:05.145360
7849 06:51:05.145461 Set Vref, RX VrefLevel [Byte0]: 54
7850 06:51:05.148940 [Byte1]: 54
7851 06:51:05.153234
7852 06:51:05.153348 Set Vref, RX VrefLevel [Byte0]: 55
7853 06:51:05.156116 [Byte1]: 55
7854 06:51:05.160321
7855 06:51:05.160421 Set Vref, RX VrefLevel [Byte0]: 56
7856 06:51:05.163773 [Byte1]: 56
7857 06:51:05.168085
7858 06:51:05.168186 Set Vref, RX VrefLevel [Byte0]: 57
7859 06:51:05.171556 [Byte1]: 57
7860 06:51:05.175688
7861 06:51:05.175773 Set Vref, RX VrefLevel [Byte0]: 58
7862 06:51:05.178901 [Byte1]: 58
7863 06:51:05.182826
7864 06:51:05.182908 Set Vref, RX VrefLevel [Byte0]: 59
7865 06:51:05.186391 [Byte1]: 59
7866 06:51:05.190433
7867 06:51:05.190517 Set Vref, RX VrefLevel [Byte0]: 60
7868 06:51:05.193960 [Byte1]: 60
7869 06:51:05.198149
7870 06:51:05.198278 Set Vref, RX VrefLevel [Byte0]: 61
7871 06:51:05.201729 [Byte1]: 61
7872 06:51:05.206047
7873 06:51:05.206157 Set Vref, RX VrefLevel [Byte0]: 62
7874 06:51:05.208965 [Byte1]: 62
7875 06:51:05.213591
7876 06:51:05.213736 Set Vref, RX VrefLevel [Byte0]: 63
7877 06:51:05.217078 [Byte1]: 63
7878 06:51:05.220937
7879 06:51:05.221017 Set Vref, RX VrefLevel [Byte0]: 64
7880 06:51:05.224320 [Byte1]: 64
7881 06:51:05.229014
7882 06:51:05.229123 Set Vref, RX VrefLevel [Byte0]: 65
7883 06:51:05.231748 [Byte1]: 65
7884 06:51:05.236140
7885 06:51:05.236251 Set Vref, RX VrefLevel [Byte0]: 66
7886 06:51:05.239309 [Byte1]: 66
7887 06:51:05.243591
7888 06:51:05.243674 Set Vref, RX VrefLevel [Byte0]: 67
7889 06:51:05.247224 [Byte1]: 67
7890 06:51:05.251464
7891 06:51:05.251547 Set Vref, RX VrefLevel [Byte0]: 68
7892 06:51:05.254495 [Byte1]: 68
7893 06:51:05.259130
7894 06:51:05.259254 Set Vref, RX VrefLevel [Byte0]: 69
7895 06:51:05.261868 [Byte1]: 69
7896 06:51:05.266228
7897 06:51:05.266316 Set Vref, RX VrefLevel [Byte0]: 70
7898 06:51:05.269745 [Byte1]: 70
7899 06:51:05.274079
7900 06:51:05.274163 Set Vref, RX VrefLevel [Byte0]: 71
7901 06:51:05.277477 [Byte1]: 71
7902 06:51:05.281687
7903 06:51:05.281798 Set Vref, RX VrefLevel [Byte0]: 72
7904 06:51:05.285086 [Byte1]: 72
7905 06:51:05.289168
7906 06:51:05.289254 Set Vref, RX VrefLevel [Byte0]: 73
7907 06:51:05.292789 [Byte1]: 73
7908 06:51:05.296901
7909 06:51:05.296988 Set Vref, RX VrefLevel [Byte0]: 74
7910 06:51:05.300255 [Byte1]: 74
7911 06:51:05.304324
7912 06:51:05.304408 Set Vref, RX VrefLevel [Byte0]: 75
7913 06:51:05.307710 [Byte1]: 75
7914 06:51:05.312153
7915 06:51:05.312237 Set Vref, RX VrefLevel [Byte0]: 76
7916 06:51:05.315535 [Byte1]: 76
7917 06:51:05.319752
7918 06:51:05.319836 Final RX Vref Byte 0 = 57 to rank0
7919 06:51:05.323141 Final RX Vref Byte 1 = 60 to rank0
7920 06:51:05.325792 Final RX Vref Byte 0 = 57 to rank1
7921 06:51:05.329336 Final RX Vref Byte 1 = 60 to rank1==
7922 06:51:05.332825 Dram Type= 6, Freq= 0, CH_0, rank 0
7923 06:51:05.339746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7924 06:51:05.339830 ==
7925 06:51:05.339896 DQS Delay:
7926 06:51:05.339961 DQS0 = 0, DQS1 = 0
7927 06:51:05.342596 DQM Delay:
7928 06:51:05.342675 DQM0 = 133, DQM1 = 128
7929 06:51:05.346151 DQ Delay:
7930 06:51:05.349530 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =134
7931 06:51:05.353000 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7932 06:51:05.356240 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7933 06:51:05.359446 DQ12 =134, DQ13 =134, DQ14 =138, DQ15 =134
7934 06:51:05.359525
7935 06:51:05.359589
7936 06:51:05.359649
7937 06:51:05.362807 [DramC_TX_OE_Calibration] TA2
7938 06:51:05.366100 Original DQ_B0 (3 6) =30, OEN = 27
7939 06:51:05.369765 Original DQ_B1 (3 6) =30, OEN = 27
7940 06:51:05.372857 24, 0x0, End_B0=24 End_B1=24
7941 06:51:05.372938 25, 0x0, End_B0=25 End_B1=25
7942 06:51:05.376194 26, 0x0, End_B0=26 End_B1=26
7943 06:51:05.379824 27, 0x0, End_B0=27 End_B1=27
7944 06:51:05.382774 28, 0x0, End_B0=28 End_B1=28
7945 06:51:05.382879 29, 0x0, End_B0=29 End_B1=29
7946 06:51:05.386200 30, 0x0, End_B0=30 End_B1=30
7947 06:51:05.389554 31, 0x4141, End_B0=30 End_B1=30
7948 06:51:05.392837 Byte0 end_step=30 best_step=27
7949 06:51:05.396173 Byte1 end_step=30 best_step=27
7950 06:51:05.399882 Byte0 TX OE(2T, 0.5T) = (3, 3)
7951 06:51:05.399962 Byte1 TX OE(2T, 0.5T) = (3, 3)
7952 06:51:05.400027
7953 06:51:05.402522
7954 06:51:05.409347 [DQSOSCAuto] RK0, (LSB)MR18= 0x2621, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
7955 06:51:05.412953 CH0 RK0: MR19=303, MR18=2621
7956 06:51:05.419440 CH0_RK0: MR19=0x303, MR18=0x2621, DQSOSC=390, MR23=63, INC=24, DEC=16
7957 06:51:05.419549
7958 06:51:05.423116 ----->DramcWriteLeveling(PI) begin...
7959 06:51:05.423220 ==
7960 06:51:05.425821 Dram Type= 6, Freq= 0, CH_0, rank 1
7961 06:51:05.429352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 06:51:05.429455 ==
7963 06:51:05.432770 Write leveling (Byte 0): 35 => 35
7964 06:51:05.436361 Write leveling (Byte 1): 29 => 29
7965 06:51:05.439132 DramcWriteLeveling(PI) end<-----
7966 06:51:05.439231
7967 06:51:05.439324 ==
7968 06:51:05.442618 Dram Type= 6, Freq= 0, CH_0, rank 1
7969 06:51:05.446093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 06:51:05.446167 ==
7971 06:51:05.449691 [Gating] SW mode calibration
7972 06:51:05.456138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7973 06:51:05.462502 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7974 06:51:05.465811 1 4 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7975 06:51:05.469440 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7976 06:51:05.476164 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7977 06:51:05.478931 1 4 12 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
7978 06:51:05.482770 1 4 16 | B1->B0 | 3030 3635 | 0 1 | (0 0) (1 1)
7979 06:51:05.489156 1 4 20 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
7980 06:51:05.492682 1 4 24 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
7981 06:51:05.495972 1 4 28 | B1->B0 | 3434 3b3b | 1 0 | (1 1) (0 0)
7982 06:51:05.502594 1 5 0 | B1->B0 | 3434 3938 | 1 1 | (1 1) (1 1)
7983 06:51:05.506052 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7984 06:51:05.509392 1 5 8 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
7985 06:51:05.516089 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
7986 06:51:05.519389 1 5 16 | B1->B0 | 2c2c 2f2f | 0 1 | (1 0) (0 0)
7987 06:51:05.523013 1 5 20 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7988 06:51:05.525764 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7989 06:51:05.532751 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7990 06:51:05.536225 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
7991 06:51:05.539656 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7992 06:51:05.545888 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7993 06:51:05.549353 1 6 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7994 06:51:05.552893 1 6 16 | B1->B0 | 3939 4646 | 0 1 | (0 0) (0 0)
7995 06:51:05.559207 1 6 20 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
7996 06:51:05.562685 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7997 06:51:05.565439 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 06:51:05.572207 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 06:51:05.575690 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 06:51:05.579099 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 06:51:05.585453 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 06:51:05.588933 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8003 06:51:05.592515 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 06:51:05.598911 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 06:51:05.602135 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 06:51:05.605315 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 06:51:05.612156 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 06:51:05.615555 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 06:51:05.619017 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 06:51:05.625735 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 06:51:05.629131 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 06:51:05.631836 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 06:51:05.638811 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 06:51:05.642322 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 06:51:05.645155 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 06:51:05.652168 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 06:51:05.655587 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8018 06:51:05.658392 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8019 06:51:05.661870 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 06:51:05.665347 Total UI for P1: 0, mck2ui 16
8021 06:51:05.668786 best dqsien dly found for B0: ( 1, 9, 14)
8022 06:51:05.672263 Total UI for P1: 0, mck2ui 16
8023 06:51:05.675645 best dqsien dly found for B1: ( 1, 9, 14)
8024 06:51:05.678949 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8025 06:51:05.682399 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8026 06:51:05.685289
8027 06:51:05.688815 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8028 06:51:05.691730 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8029 06:51:05.695282 [Gating] SW calibration Done
8030 06:51:05.695384 ==
8031 06:51:05.698805 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 06:51:05.702244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 06:51:05.702351 ==
8034 06:51:05.702444 RX Vref Scan: 0
8035 06:51:05.705736
8036 06:51:05.705811 RX Vref 0 -> 0, step: 1
8037 06:51:05.705873
8038 06:51:05.708486 RX Delay 0 -> 252, step: 8
8039 06:51:05.711927 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8040 06:51:05.715317 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8041 06:51:05.722204 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8042 06:51:05.725356 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8043 06:51:05.728488 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8044 06:51:05.732365 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8045 06:51:05.735507 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8046 06:51:05.742266 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8047 06:51:05.745043 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8048 06:51:05.748516 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8049 06:51:05.751908 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8050 06:51:05.755419 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8051 06:51:05.761658 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8052 06:51:05.765121 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8053 06:51:05.768732 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8054 06:51:05.771539 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8055 06:51:05.771646 ==
8056 06:51:05.775047 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 06:51:05.782066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 06:51:05.782170 ==
8059 06:51:05.782287 DQS Delay:
8060 06:51:05.784850 DQS0 = 0, DQS1 = 0
8061 06:51:05.784922 DQM Delay:
8062 06:51:05.784982 DQM0 = 136, DQM1 = 128
8063 06:51:05.788397 DQ Delay:
8064 06:51:05.791600 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8065 06:51:05.795154 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8066 06:51:05.798696 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8067 06:51:05.801447 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8068 06:51:05.801530
8069 06:51:05.801604
8070 06:51:05.801661 ==
8071 06:51:05.804916 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 06:51:05.808379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 06:51:05.811352 ==
8074 06:51:05.811428
8075 06:51:05.811494
8076 06:51:05.811588 TX Vref Scan disable
8077 06:51:05.815295 == TX Byte 0 ==
8078 06:51:05.818151 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8079 06:51:05.821544 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8080 06:51:05.825024 == TX Byte 1 ==
8081 06:51:05.828427 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8082 06:51:05.831785 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8083 06:51:05.834898 ==
8084 06:51:05.834969 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 06:51:05.841360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 06:51:05.841442 ==
8087 06:51:05.854495
8088 06:51:05.857303 TX Vref early break, caculate TX vref
8089 06:51:05.861141 TX Vref=16, minBit 1, minWin=22, winSum=387
8090 06:51:05.864431 TX Vref=18, minBit 1, minWin=23, winSum=390
8091 06:51:05.867690 TX Vref=20, minBit 1, minWin=23, winSum=404
8092 06:51:05.871062 TX Vref=22, minBit 1, minWin=24, winSum=411
8093 06:51:05.873791 TX Vref=24, minBit 2, minWin=25, winSum=420
8094 06:51:05.880628 TX Vref=26, minBit 1, minWin=24, winSum=426
8095 06:51:05.884161 TX Vref=28, minBit 0, minWin=25, winSum=423
8096 06:51:05.887714 TX Vref=30, minBit 0, minWin=25, winSum=413
8097 06:51:05.890621 TX Vref=32, minBit 4, minWin=24, winSum=408
8098 06:51:05.894105 TX Vref=34, minBit 0, minWin=24, winSum=395
8099 06:51:05.900715 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8100 06:51:05.900797
8101 06:51:05.903813 Final TX Range 0 Vref 28
8102 06:51:05.903895
8103 06:51:05.903958 ==
8104 06:51:05.907274 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 06:51:05.910745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 06:51:05.910845 ==
8107 06:51:05.910941
8108 06:51:05.911030
8109 06:51:05.914349 TX Vref Scan disable
8110 06:51:05.920588 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8111 06:51:05.920663 == TX Byte 0 ==
8112 06:51:05.924162 u2DelayCellOfst[0]=13 cells (4 PI)
8113 06:51:05.927639 u2DelayCellOfst[1]=13 cells (4 PI)
8114 06:51:05.930496 u2DelayCellOfst[2]=10 cells (3 PI)
8115 06:51:05.934120 u2DelayCellOfst[3]=10 cells (3 PI)
8116 06:51:05.936883 u2DelayCellOfst[4]=10 cells (3 PI)
8117 06:51:05.940280 u2DelayCellOfst[5]=0 cells (0 PI)
8118 06:51:05.943512 u2DelayCellOfst[6]=16 cells (5 PI)
8119 06:51:05.947053 u2DelayCellOfst[7]=16 cells (5 PI)
8120 06:51:05.950555 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8121 06:51:05.953861 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8122 06:51:05.957200 == TX Byte 1 ==
8123 06:51:05.957288 u2DelayCellOfst[8]=0 cells (0 PI)
8124 06:51:05.960698 u2DelayCellOfst[9]=0 cells (0 PI)
8125 06:51:05.963925 u2DelayCellOfst[10]=6 cells (2 PI)
8126 06:51:05.967276 u2DelayCellOfst[11]=3 cells (1 PI)
8127 06:51:05.970738 u2DelayCellOfst[12]=10 cells (3 PI)
8128 06:51:05.973716 u2DelayCellOfst[13]=10 cells (3 PI)
8129 06:51:05.976946 u2DelayCellOfst[14]=13 cells (4 PI)
8130 06:51:05.980193 u2DelayCellOfst[15]=10 cells (3 PI)
8131 06:51:05.983397 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8132 06:51:05.990146 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8133 06:51:05.990234 DramC Write-DBI on
8134 06:51:05.990300 ==
8135 06:51:05.993733 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 06:51:05.997235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 06:51:06.000094 ==
8138 06:51:06.000177
8139 06:51:06.000242
8140 06:51:06.000315 TX Vref Scan disable
8141 06:51:06.003678 == TX Byte 0 ==
8142 06:51:06.007028 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8143 06:51:06.010288 == TX Byte 1 ==
8144 06:51:06.013590 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8145 06:51:06.013675 DramC Write-DBI off
8146 06:51:06.017560
8147 06:51:06.017644 [DATLAT]
8148 06:51:06.017728 Freq=1600, CH0 RK1
8149 06:51:06.017795
8150 06:51:06.020345 DATLAT Default: 0xf
8151 06:51:06.020430 0, 0xFFFF, sum = 0
8152 06:51:06.023785 1, 0xFFFF, sum = 0
8153 06:51:06.023889 2, 0xFFFF, sum = 0
8154 06:51:06.027247 3, 0xFFFF, sum = 0
8155 06:51:06.030668 4, 0xFFFF, sum = 0
8156 06:51:06.030768 5, 0xFFFF, sum = 0
8157 06:51:06.033528 6, 0xFFFF, sum = 0
8158 06:51:06.033627 7, 0xFFFF, sum = 0
8159 06:51:06.037056 8, 0xFFFF, sum = 0
8160 06:51:06.037129 9, 0xFFFF, sum = 0
8161 06:51:06.040545 10, 0xFFFF, sum = 0
8162 06:51:06.040619 11, 0xFFFF, sum = 0
8163 06:51:06.044005 12, 0xFFFF, sum = 0
8164 06:51:06.044077 13, 0xFFFF, sum = 0
8165 06:51:06.047252 14, 0x0, sum = 1
8166 06:51:06.047352 15, 0x0, sum = 2
8167 06:51:06.050529 16, 0x0, sum = 3
8168 06:51:06.050628 17, 0x0, sum = 4
8169 06:51:06.053413 best_step = 15
8170 06:51:06.053501
8171 06:51:06.053607 ==
8172 06:51:06.056802 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 06:51:06.060272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 06:51:06.060381 ==
8175 06:51:06.060444 RX Vref Scan: 0
8176 06:51:06.063724
8177 06:51:06.063843 RX Vref 0 -> 0, step: 1
8178 06:51:06.063931
8179 06:51:06.067196 RX Delay 19 -> 252, step: 4
8180 06:51:06.069907 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8181 06:51:06.076585 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8182 06:51:06.080104 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8183 06:51:06.083465 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8184 06:51:06.087241 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8185 06:51:06.090448 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8186 06:51:06.097093 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8187 06:51:06.100131 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8188 06:51:06.103579 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8189 06:51:06.106445 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8190 06:51:06.109908 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8191 06:51:06.116835 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8192 06:51:06.119641 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8193 06:51:06.123641 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8194 06:51:06.126317 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8195 06:51:06.129833 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8196 06:51:06.133339 ==
8197 06:51:06.136737 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 06:51:06.139562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 06:51:06.139637 ==
8200 06:51:06.139699 DQS Delay:
8201 06:51:06.143103 DQS0 = 0, DQS1 = 0
8202 06:51:06.143203 DQM Delay:
8203 06:51:06.146529 DQM0 = 134, DQM1 = 127
8204 06:51:06.146603 DQ Delay:
8205 06:51:06.149940 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8206 06:51:06.153206 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8207 06:51:06.156503 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8208 06:51:06.159913 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8209 06:51:06.160013
8210 06:51:06.160113
8211 06:51:06.160201
8212 06:51:06.162708 [DramC_TX_OE_Calibration] TA2
8213 06:51:06.166297 Original DQ_B0 (3 6) =30, OEN = 27
8214 06:51:06.169823 Original DQ_B1 (3 6) =30, OEN = 27
8215 06:51:06.173176 24, 0x0, End_B0=24 End_B1=24
8216 06:51:06.176546 25, 0x0, End_B0=25 End_B1=25
8217 06:51:06.176652 26, 0x0, End_B0=26 End_B1=26
8218 06:51:06.179286 27, 0x0, End_B0=27 End_B1=27
8219 06:51:06.182886 28, 0x0, End_B0=28 End_B1=28
8220 06:51:06.186280 29, 0x0, End_B0=29 End_B1=29
8221 06:51:06.189697 30, 0x0, End_B0=30 End_B1=30
8222 06:51:06.189804 31, 0x4141, End_B0=30 End_B1=30
8223 06:51:06.192927 Byte0 end_step=30 best_step=27
8224 06:51:06.195849 Byte1 end_step=30 best_step=27
8225 06:51:06.199370 Byte0 TX OE(2T, 0.5T) = (3, 3)
8226 06:51:06.203250 Byte1 TX OE(2T, 0.5T) = (3, 3)
8227 06:51:06.203321
8228 06:51:06.203383
8229 06:51:06.209603 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8230 06:51:06.212805 CH0 RK1: MR19=303, MR18=2109
8231 06:51:06.219089 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8232 06:51:06.222863 [RxdqsGatingPostProcess] freq 1600
8233 06:51:06.229220 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8234 06:51:06.229301 best DQS0 dly(2T, 0.5T) = (1, 1)
8235 06:51:06.232633 best DQS1 dly(2T, 0.5T) = (1, 1)
8236 06:51:06.235991 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8237 06:51:06.239378 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8238 06:51:06.242826 best DQS0 dly(2T, 0.5T) = (1, 1)
8239 06:51:06.245771 best DQS1 dly(2T, 0.5T) = (1, 1)
8240 06:51:06.249327 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8241 06:51:06.252883 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8242 06:51:06.255733 Pre-setting of DQS Precalculation
8243 06:51:06.258976 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8244 06:51:06.259055 ==
8245 06:51:06.262254 Dram Type= 6, Freq= 0, CH_1, rank 0
8246 06:51:06.269022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8247 06:51:06.269111 ==
8248 06:51:06.272564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8249 06:51:06.279353 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8250 06:51:06.282183 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8251 06:51:06.289024 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8252 06:51:06.296558 [CA 0] Center 42 (12~72) winsize 61
8253 06:51:06.299895 [CA 1] Center 42 (12~72) winsize 61
8254 06:51:06.303383 [CA 2] Center 38 (9~68) winsize 60
8255 06:51:06.306874 [CA 3] Center 38 (9~67) winsize 59
8256 06:51:06.309678 [CA 4] Center 38 (9~67) winsize 59
8257 06:51:06.313191 [CA 5] Center 37 (7~67) winsize 61
8258 06:51:06.313261
8259 06:51:06.316789 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8260 06:51:06.316861
8261 06:51:06.320197 [CATrainingPosCal] consider 1 rank data
8262 06:51:06.322974 u2DelayCellTimex100 = 290/100 ps
8263 06:51:06.326500 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8264 06:51:06.333132 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8265 06:51:06.336321 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8266 06:51:06.340024 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8267 06:51:06.343149 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8268 06:51:06.346669 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8269 06:51:06.346745
8270 06:51:06.350187 CA PerBit enable=1, Macro0, CA PI delay=37
8271 06:51:06.350264
8272 06:51:06.353424 [CBTSetCACLKResult] CA Dly = 37
8273 06:51:06.356883 CS Dly: 12 (0~43)
8274 06:51:06.359646 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8275 06:51:06.363167 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8276 06:51:06.363239 ==
8277 06:51:06.366634 Dram Type= 6, Freq= 0, CH_1, rank 1
8278 06:51:06.369927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 06:51:06.373165 ==
8280 06:51:06.376656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8281 06:51:06.379943 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8282 06:51:06.386152 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8283 06:51:06.389798 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8284 06:51:06.400281 [CA 0] Center 42 (13~72) winsize 60
8285 06:51:06.403133 [CA 1] Center 42 (13~72) winsize 60
8286 06:51:06.406489 [CA 2] Center 38 (9~68) winsize 60
8287 06:51:06.409891 [CA 3] Center 38 (8~68) winsize 61
8288 06:51:06.413395 [CA 4] Center 38 (8~68) winsize 61
8289 06:51:06.416256 [CA 5] Center 37 (8~67) winsize 60
8290 06:51:06.416379
8291 06:51:06.419861 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8292 06:51:06.419943
8293 06:51:06.423297 [CATrainingPosCal] consider 2 rank data
8294 06:51:06.426809 u2DelayCellTimex100 = 290/100 ps
8295 06:51:06.430221 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8296 06:51:06.436499 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8297 06:51:06.439910 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8298 06:51:06.443370 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8299 06:51:06.446890 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8300 06:51:06.450284 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8301 06:51:06.450355
8302 06:51:06.453159 CA PerBit enable=1, Macro0, CA PI delay=37
8303 06:51:06.453260
8304 06:51:06.456437 [CBTSetCACLKResult] CA Dly = 37
8305 06:51:06.456544 CS Dly: 13 (0~45)
8306 06:51:06.463411 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8307 06:51:06.466482 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8308 06:51:06.466591
8309 06:51:06.470200 ----->DramcWriteLeveling(PI) begin...
8310 06:51:06.470286 ==
8311 06:51:06.473639 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 06:51:06.476775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 06:51:06.476852 ==
8314 06:51:06.480230 Write leveling (Byte 0): 25 => 25
8315 06:51:06.483085 Write leveling (Byte 1): 28 => 28
8316 06:51:06.486543 DramcWriteLeveling(PI) end<-----
8317 06:51:06.486618
8318 06:51:06.486679 ==
8319 06:51:06.489921 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 06:51:06.496737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 06:51:06.496825 ==
8322 06:51:06.496923 [Gating] SW mode calibration
8323 06:51:06.506557 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8324 06:51:06.509936 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8325 06:51:06.513446 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 06:51:06.519712 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 06:51:06.523235 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8328 06:51:06.526137 1 4 12 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
8329 06:51:06.533154 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 06:51:06.536613 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 06:51:06.540063 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 06:51:06.546262 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 06:51:06.549727 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 06:51:06.553275 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 06:51:06.559605 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8336 06:51:06.563196 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
8337 06:51:06.566696 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 06:51:06.572789 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 06:51:06.576145 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 06:51:06.579456 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 06:51:06.586309 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 06:51:06.589714 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 06:51:06.592996 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8344 06:51:06.599489 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 06:51:06.602630 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 06:51:06.606006 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 06:51:06.612824 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 06:51:06.616115 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 06:51:06.619226 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 06:51:06.625930 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 06:51:06.629546 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8352 06:51:06.632318 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8353 06:51:06.639278 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 06:51:06.642745 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 06:51:06.645569 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 06:51:06.652369 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 06:51:06.655812 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 06:51:06.658714 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 06:51:06.665779 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 06:51:06.669251 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 06:51:06.671983 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 06:51:06.678789 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 06:51:06.682251 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 06:51:06.685738 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 06:51:06.689097 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 06:51:06.695839 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 06:51:06.698635 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8368 06:51:06.702185 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8369 06:51:06.709105 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 06:51:06.711923 Total UI for P1: 0, mck2ui 16
8371 06:51:06.715274 best dqsien dly found for B0: ( 1, 9, 10)
8372 06:51:06.718619 Total UI for P1: 0, mck2ui 16
8373 06:51:06.722123 best dqsien dly found for B1: ( 1, 9, 10)
8374 06:51:06.725430 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8375 06:51:06.728843 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8376 06:51:06.728928
8377 06:51:06.732132 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8378 06:51:06.735219 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8379 06:51:06.738826 [Gating] SW calibration Done
8380 06:51:06.738911 ==
8381 06:51:06.741773 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 06:51:06.745208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 06:51:06.745321 ==
8384 06:51:06.748411 RX Vref Scan: 0
8385 06:51:06.748542
8386 06:51:06.751929 RX Vref 0 -> 0, step: 1
8387 06:51:06.752042
8388 06:51:06.752144 RX Delay 0 -> 252, step: 8
8389 06:51:06.758593 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8390 06:51:06.761695 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8391 06:51:06.765438 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8392 06:51:06.768575 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8393 06:51:06.772079 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8394 06:51:06.775508 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8395 06:51:06.781808 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8396 06:51:06.785451 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8397 06:51:06.788734 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8398 06:51:06.791621 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8399 06:51:06.795227 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8400 06:51:06.801726 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8401 06:51:06.805179 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8402 06:51:06.808669 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8403 06:51:06.812121 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8404 06:51:06.815045 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8405 06:51:06.818452 ==
8406 06:51:06.821943 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 06:51:06.825504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 06:51:06.825603 ==
8409 06:51:06.825670 DQS Delay:
8410 06:51:06.828266 DQS0 = 0, DQS1 = 0
8411 06:51:06.828352 DQM Delay:
8412 06:51:06.831394 DQM0 = 136, DQM1 = 133
8413 06:51:06.831466 DQ Delay:
8414 06:51:06.834915 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8415 06:51:06.838487 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8416 06:51:06.841362 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8417 06:51:06.844850 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8418 06:51:06.844950
8419 06:51:06.845035
8420 06:51:06.848394 ==
8421 06:51:06.848480 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 06:51:06.855023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 06:51:06.855126 ==
8424 06:51:06.855227
8425 06:51:06.855316
8426 06:51:06.858245 TX Vref Scan disable
8427 06:51:06.858345 == TX Byte 0 ==
8428 06:51:06.861479 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8429 06:51:06.868388 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8430 06:51:06.868485 == TX Byte 1 ==
8431 06:51:06.871587 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8432 06:51:06.878070 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8433 06:51:06.878174 ==
8434 06:51:06.881276 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 06:51:06.884841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 06:51:06.884927 ==
8437 06:51:06.897760
8438 06:51:06.900692 TX Vref early break, caculate TX vref
8439 06:51:06.904208 TX Vref=16, minBit 9, minWin=22, winSum=370
8440 06:51:06.907540 TX Vref=18, minBit 0, minWin=23, winSum=379
8441 06:51:06.910852 TX Vref=20, minBit 0, minWin=24, winSum=391
8442 06:51:06.914311 TX Vref=22, minBit 3, minWin=24, winSum=401
8443 06:51:06.917863 TX Vref=24, minBit 0, minWin=25, winSum=412
8444 06:51:06.924169 TX Vref=26, minBit 1, minWin=25, winSum=421
8445 06:51:06.927659 TX Vref=28, minBit 0, minWin=25, winSum=425
8446 06:51:06.930525 TX Vref=30, minBit 0, minWin=25, winSum=421
8447 06:51:06.933824 TX Vref=32, minBit 0, minWin=25, winSum=410
8448 06:51:06.937660 TX Vref=34, minBit 6, minWin=23, winSum=399
8449 06:51:06.943969 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8450 06:51:06.944052
8451 06:51:06.947572 Final TX Range 0 Vref 28
8452 06:51:06.947666
8453 06:51:06.947765 ==
8454 06:51:06.951066 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 06:51:06.953872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 06:51:06.953975 ==
8457 06:51:06.954073
8458 06:51:06.954149
8459 06:51:06.957330 TX Vref Scan disable
8460 06:51:06.964157 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8461 06:51:06.964256 == TX Byte 0 ==
8462 06:51:06.967639 u2DelayCellOfst[0]=20 cells (6 PI)
8463 06:51:06.970347 u2DelayCellOfst[1]=13 cells (4 PI)
8464 06:51:06.973634 u2DelayCellOfst[2]=0 cells (0 PI)
8465 06:51:06.977536 u2DelayCellOfst[3]=10 cells (3 PI)
8466 06:51:06.980977 u2DelayCellOfst[4]=13 cells (4 PI)
8467 06:51:06.983759 u2DelayCellOfst[5]=20 cells (6 PI)
8468 06:51:06.987265 u2DelayCellOfst[6]=20 cells (6 PI)
8469 06:51:06.987365 u2DelayCellOfst[7]=6 cells (2 PI)
8470 06:51:06.994041 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8471 06:51:06.997372 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8472 06:51:06.997472 == TX Byte 1 ==
8473 06:51:07.000460 u2DelayCellOfst[8]=0 cells (0 PI)
8474 06:51:07.004253 u2DelayCellOfst[9]=3 cells (1 PI)
8475 06:51:07.007448 u2DelayCellOfst[10]=13 cells (4 PI)
8476 06:51:07.010869 u2DelayCellOfst[11]=6 cells (2 PI)
8477 06:51:07.014301 u2DelayCellOfst[12]=13 cells (4 PI)
8478 06:51:07.017537 u2DelayCellOfst[13]=16 cells (5 PI)
8479 06:51:07.020855 u2DelayCellOfst[14]=20 cells (6 PI)
8480 06:51:07.024147 u2DelayCellOfst[15]=20 cells (6 PI)
8481 06:51:07.027055 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8482 06:51:07.034109 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8483 06:51:07.034194 DramC Write-DBI on
8484 06:51:07.034280 ==
8485 06:51:07.037020 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 06:51:07.040480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 06:51:07.040565 ==
8488 06:51:07.040652
8489 06:51:07.043862
8490 06:51:07.043947 TX Vref Scan disable
8491 06:51:07.047154 == TX Byte 0 ==
8492 06:51:07.050772 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8493 06:51:07.054162 == TX Byte 1 ==
8494 06:51:07.057738 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8495 06:51:07.057824 DramC Write-DBI off
8496 06:51:07.057910
8497 06:51:07.060480 [DATLAT]
8498 06:51:07.060565 Freq=1600, CH1 RK0
8499 06:51:07.060651
8500 06:51:07.064039 DATLAT Default: 0xf
8501 06:51:07.064124 0, 0xFFFF, sum = 0
8502 06:51:07.067401 1, 0xFFFF, sum = 0
8503 06:51:07.067550 2, 0xFFFF, sum = 0
8504 06:51:07.070613 3, 0xFFFF, sum = 0
8505 06:51:07.070700 4, 0xFFFF, sum = 0
8506 06:51:07.074178 5, 0xFFFF, sum = 0
8507 06:51:07.074277 6, 0xFFFF, sum = 0
8508 06:51:07.077534 7, 0xFFFF, sum = 0
8509 06:51:07.077617 8, 0xFFFF, sum = 0
8510 06:51:07.080906 9, 0xFFFF, sum = 0
8511 06:51:07.084199 10, 0xFFFF, sum = 0
8512 06:51:07.084292 11, 0xFFFF, sum = 0
8513 06:51:07.087070 12, 0xFFFF, sum = 0
8514 06:51:07.087165 13, 0xFFFF, sum = 0
8515 06:51:07.090507 14, 0x0, sum = 1
8516 06:51:07.090593 15, 0x0, sum = 2
8517 06:51:07.093950 16, 0x0, sum = 3
8518 06:51:07.094036 17, 0x0, sum = 4
8519 06:51:07.094123 best_step = 15
8520 06:51:07.097421
8521 06:51:07.097506 ==
8522 06:51:07.100866 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 06:51:07.103713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 06:51:07.103799 ==
8525 06:51:07.103884 RX Vref Scan: 1
8526 06:51:07.103965
8527 06:51:07.107199 Set Vref Range= 24 -> 127
8528 06:51:07.107308
8529 06:51:07.110610 RX Vref 24 -> 127, step: 1
8530 06:51:07.110707
8531 06:51:07.113789 RX Delay 27 -> 252, step: 4
8532 06:51:07.113921
8533 06:51:07.116983 Set Vref, RX VrefLevel [Byte0]: 24
8534 06:51:07.120361 [Byte1]: 24
8535 06:51:07.120460
8536 06:51:07.123834 Set Vref, RX VrefLevel [Byte0]: 25
8537 06:51:07.127424 [Byte1]: 25
8538 06:51:07.127523
8539 06:51:07.130558 Set Vref, RX VrefLevel [Byte0]: 26
8540 06:51:07.133882 [Byte1]: 26
8541 06:51:07.137094
8542 06:51:07.137200 Set Vref, RX VrefLevel [Byte0]: 27
8543 06:51:07.140593 [Byte1]: 27
8544 06:51:07.144743
8545 06:51:07.144828 Set Vref, RX VrefLevel [Byte0]: 28
8546 06:51:07.148223 [Byte1]: 28
8547 06:51:07.152283
8548 06:51:07.152405 Set Vref, RX VrefLevel [Byte0]: 29
8549 06:51:07.155704 [Byte1]: 29
8550 06:51:07.159784
8551 06:51:07.159868 Set Vref, RX VrefLevel [Byte0]: 30
8552 06:51:07.162662 [Byte1]: 30
8553 06:51:07.167578
8554 06:51:07.167663 Set Vref, RX VrefLevel [Byte0]: 31
8555 06:51:07.170441 [Byte1]: 31
8556 06:51:07.174931
8557 06:51:07.175061 Set Vref, RX VrefLevel [Byte0]: 32
8558 06:51:07.178313 [Byte1]: 32
8559 06:51:07.182583
8560 06:51:07.182681 Set Vref, RX VrefLevel [Byte0]: 33
8561 06:51:07.185466 [Byte1]: 33
8562 06:51:07.190032
8563 06:51:07.190116 Set Vref, RX VrefLevel [Byte0]: 34
8564 06:51:07.193334 [Byte1]: 34
8565 06:51:07.197349
8566 06:51:07.197435 Set Vref, RX VrefLevel [Byte0]: 35
8567 06:51:07.200677 [Byte1]: 35
8568 06:51:07.204987
8569 06:51:07.205072 Set Vref, RX VrefLevel [Byte0]: 36
8570 06:51:07.208522 [Byte1]: 36
8571 06:51:07.212156
8572 06:51:07.212240 Set Vref, RX VrefLevel [Byte0]: 37
8573 06:51:07.215746 [Byte1]: 37
8574 06:51:07.219977
8575 06:51:07.220061 Set Vref, RX VrefLevel [Byte0]: 38
8576 06:51:07.223331 [Byte1]: 38
8577 06:51:07.227373
8578 06:51:07.227458 Set Vref, RX VrefLevel [Byte0]: 39
8579 06:51:07.230768 [Byte1]: 39
8580 06:51:07.234819
8581 06:51:07.234904 Set Vref, RX VrefLevel [Byte0]: 40
8582 06:51:07.238162 [Byte1]: 40
8583 06:51:07.242807
8584 06:51:07.242891 Set Vref, RX VrefLevel [Byte0]: 41
8585 06:51:07.246095 [Byte1]: 41
8586 06:51:07.249960
8587 06:51:07.250045 Set Vref, RX VrefLevel [Byte0]: 42
8588 06:51:07.253224 [Byte1]: 42
8589 06:51:07.257611
8590 06:51:07.257697 Set Vref, RX VrefLevel [Byte0]: 43
8591 06:51:07.260986 [Byte1]: 43
8592 06:51:07.265107
8593 06:51:07.265191 Set Vref, RX VrefLevel [Byte0]: 44
8594 06:51:07.268551 [Byte1]: 44
8595 06:51:07.272768
8596 06:51:07.272853 Set Vref, RX VrefLevel [Byte0]: 45
8597 06:51:07.275640 [Byte1]: 45
8598 06:51:07.280299
8599 06:51:07.280403 Set Vref, RX VrefLevel [Byte0]: 46
8600 06:51:07.283581 [Byte1]: 46
8601 06:51:07.287701
8602 06:51:07.287786 Set Vref, RX VrefLevel [Byte0]: 47
8603 06:51:07.291291 [Byte1]: 47
8604 06:51:07.295372
8605 06:51:07.295491 Set Vref, RX VrefLevel [Byte0]: 48
8606 06:51:07.298578 [Byte1]: 48
8607 06:51:07.302986
8608 06:51:07.303071 Set Vref, RX VrefLevel [Byte0]: 49
8609 06:51:07.306289 [Byte1]: 49
8610 06:51:07.310382
8611 06:51:07.310466 Set Vref, RX VrefLevel [Byte0]: 50
8612 06:51:07.313286 [Byte1]: 50
8613 06:51:07.317520
8614 06:51:07.317605 Set Vref, RX VrefLevel [Byte0]: 51
8615 06:51:07.321080 [Byte1]: 51
8616 06:51:07.325266
8617 06:51:07.325351 Set Vref, RX VrefLevel [Byte0]: 52
8618 06:51:07.328704 [Byte1]: 52
8619 06:51:07.332949
8620 06:51:07.333034 Set Vref, RX VrefLevel [Byte0]: 53
8621 06:51:07.336261 [Byte1]: 53
8622 06:51:07.340374
8623 06:51:07.340459 Set Vref, RX VrefLevel [Byte0]: 54
8624 06:51:07.343842 [Byte1]: 54
8625 06:51:07.347916
8626 06:51:07.347996 Set Vref, RX VrefLevel [Byte0]: 55
8627 06:51:07.351405 [Byte1]: 55
8628 06:51:07.355646
8629 06:51:07.355755 Set Vref, RX VrefLevel [Byte0]: 56
8630 06:51:07.359098 [Byte1]: 56
8631 06:51:07.363055
8632 06:51:07.363152 Set Vref, RX VrefLevel [Byte0]: 57
8633 06:51:07.366303 [Byte1]: 57
8634 06:51:07.370622
8635 06:51:07.370734 Set Vref, RX VrefLevel [Byte0]: 58
8636 06:51:07.373864 [Byte1]: 58
8637 06:51:07.378348
8638 06:51:07.378461 Set Vref, RX VrefLevel [Byte0]: 59
8639 06:51:07.381685 [Byte1]: 59
8640 06:51:07.385781
8641 06:51:07.385863 Set Vref, RX VrefLevel [Byte0]: 60
8642 06:51:07.389102 [Byte1]: 60
8643 06:51:07.393263
8644 06:51:07.393345 Set Vref, RX VrefLevel [Byte0]: 61
8645 06:51:07.396739 [Byte1]: 61
8646 06:51:07.400402
8647 06:51:07.400499 Set Vref, RX VrefLevel [Byte0]: 62
8648 06:51:07.403856 [Byte1]: 62
8649 06:51:07.408490
8650 06:51:07.408572 Set Vref, RX VrefLevel [Byte0]: 63
8651 06:51:07.411702 [Byte1]: 63
8652 06:51:07.415926
8653 06:51:07.416013 Set Vref, RX VrefLevel [Byte0]: 64
8654 06:51:07.418768 [Byte1]: 64
8655 06:51:07.423611
8656 06:51:07.423695 Set Vref, RX VrefLevel [Byte0]: 65
8657 06:51:07.426501 [Byte1]: 65
8658 06:51:07.430693
8659 06:51:07.430778 Set Vref, RX VrefLevel [Byte0]: 66
8660 06:51:07.434022 [Byte1]: 66
8661 06:51:07.438224
8662 06:51:07.438361 Set Vref, RX VrefLevel [Byte0]: 67
8663 06:51:07.441731 [Byte1]: 67
8664 06:51:07.445732
8665 06:51:07.445869 Set Vref, RX VrefLevel [Byte0]: 68
8666 06:51:07.449272 [Byte1]: 68
8667 06:51:07.453319
8668 06:51:07.453422 Set Vref, RX VrefLevel [Byte0]: 69
8669 06:51:07.456885 [Byte1]: 69
8670 06:51:07.461126
8671 06:51:07.461263 Set Vref, RX VrefLevel [Byte0]: 70
8672 06:51:07.464578 [Byte1]: 70
8673 06:51:07.468206
8674 06:51:07.468315 Set Vref, RX VrefLevel [Byte0]: 71
8675 06:51:07.471599 [Byte1]: 71
8676 06:51:07.476129
8677 06:51:07.476227 Set Vref, RX VrefLevel [Byte0]: 72
8678 06:51:07.479479 [Byte1]: 72
8679 06:51:07.483477
8680 06:51:07.483576 Set Vref, RX VrefLevel [Byte0]: 73
8681 06:51:07.486722 [Byte1]: 73
8682 06:51:07.491052
8683 06:51:07.491151 Set Vref, RX VrefLevel [Byte0]: 74
8684 06:51:07.494626 [Byte1]: 74
8685 06:51:07.498635
8686 06:51:07.498734 Set Vref, RX VrefLevel [Byte0]: 75
8687 06:51:07.501767 [Byte1]: 75
8688 06:51:07.505928
8689 06:51:07.506031 Set Vref, RX VrefLevel [Byte0]: 76
8690 06:51:07.509501 [Byte1]: 76
8691 06:51:07.513625
8692 06:51:07.513711 Set Vref, RX VrefLevel [Byte0]: 77
8693 06:51:07.517188 [Byte1]: 77
8694 06:51:07.521282
8695 06:51:07.521366 Set Vref, RX VrefLevel [Byte0]: 78
8696 06:51:07.524375 [Byte1]: 78
8697 06:51:07.528557
8698 06:51:07.528642 Set Vref, RX VrefLevel [Byte0]: 79
8699 06:51:07.531915 [Byte1]: 79
8700 06:51:07.536044
8701 06:51:07.536129 Final RX Vref Byte 0 = 58 to rank0
8702 06:51:07.539522 Final RX Vref Byte 1 = 58 to rank0
8703 06:51:07.543045 Final RX Vref Byte 0 = 58 to rank1
8704 06:51:07.546515 Final RX Vref Byte 1 = 58 to rank1==
8705 06:51:07.549361 Dram Type= 6, Freq= 0, CH_1, rank 0
8706 06:51:07.556264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8707 06:51:07.556394 ==
8708 06:51:07.556514 DQS Delay:
8709 06:51:07.556596 DQS0 = 0, DQS1 = 0
8710 06:51:07.559429 DQM Delay:
8711 06:51:07.559514 DQM0 = 134, DQM1 = 131
8712 06:51:07.562815 DQ Delay:
8713 06:51:07.566406 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8714 06:51:07.569342 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8715 06:51:07.572863 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122
8716 06:51:07.576416 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8717 06:51:07.576502
8718 06:51:07.576587
8719 06:51:07.576668
8720 06:51:07.579743 [DramC_TX_OE_Calibration] TA2
8721 06:51:07.583194 Original DQ_B0 (3 6) =30, OEN = 27
8722 06:51:07.585967 Original DQ_B1 (3 6) =30, OEN = 27
8723 06:51:07.589549 24, 0x0, End_B0=24 End_B1=24
8724 06:51:07.589650 25, 0x0, End_B0=25 End_B1=25
8725 06:51:07.593147 26, 0x0, End_B0=26 End_B1=26
8726 06:51:07.595934 27, 0x0, End_B0=27 End_B1=27
8727 06:51:07.599300 28, 0x0, End_B0=28 End_B1=28
8728 06:51:07.599387 29, 0x0, End_B0=29 End_B1=29
8729 06:51:07.602708 30, 0x0, End_B0=30 End_B1=30
8730 06:51:07.606097 31, 0x4141, End_B0=30 End_B1=30
8731 06:51:07.609299 Byte0 end_step=30 best_step=27
8732 06:51:07.612931 Byte1 end_step=30 best_step=27
8733 06:51:07.615915 Byte0 TX OE(2T, 0.5T) = (3, 3)
8734 06:51:07.615997 Byte1 TX OE(2T, 0.5T) = (3, 3)
8735 06:51:07.619574
8736 06:51:07.619656
8737 06:51:07.626389 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8738 06:51:07.629779 CH1 RK0: MR19=303, MR18=1826
8739 06:51:07.636397 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8740 06:51:07.636481
8741 06:51:07.639452 ----->DramcWriteLeveling(PI) begin...
8742 06:51:07.639536 ==
8743 06:51:07.642554 Dram Type= 6, Freq= 0, CH_1, rank 1
8744 06:51:07.646286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 06:51:07.646369 ==
8746 06:51:07.649761 Write leveling (Byte 0): 25 => 25
8747 06:51:07.652528 Write leveling (Byte 1): 30 => 30
8748 06:51:07.656016 DramcWriteLeveling(PI) end<-----
8749 06:51:07.656137
8750 06:51:07.656241 ==
8751 06:51:07.659527 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 06:51:07.663023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8753 06:51:07.663106 ==
8754 06:51:07.666410 [Gating] SW mode calibration
8755 06:51:07.672758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8756 06:51:07.679670 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8757 06:51:07.683090 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 06:51:07.685853 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 06:51:07.692867 1 4 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
8760 06:51:07.696447 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
8761 06:51:07.699205 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 06:51:07.706164 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 06:51:07.709666 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 06:51:07.712489 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 06:51:07.719342 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 06:51:07.723051 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 06:51:07.725742 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8768 06:51:07.732807 1 5 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 1)
8769 06:51:07.735749 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 06:51:07.739260 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 06:51:07.742980 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 06:51:07.749738 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 06:51:07.752789 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 06:51:07.756245 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 06:51:07.762791 1 6 8 | B1->B0 | 3e3d 2323 | 1 0 | (0 0) (0 0)
8776 06:51:07.765738 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 06:51:07.769556 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 06:51:07.776210 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 06:51:07.779455 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 06:51:07.782323 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 06:51:07.789367 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 06:51:07.792861 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8783 06:51:07.796184 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8784 06:51:07.802746 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8785 06:51:07.806108 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8786 06:51:07.809633 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 06:51:07.816190 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 06:51:07.818984 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 06:51:07.822502 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 06:51:07.829050 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 06:51:07.832631 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 06:51:07.836115 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 06:51:07.839657 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 06:51:07.846214 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 06:51:07.849630 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 06:51:07.852972 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 06:51:07.859855 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 06:51:07.862575 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 06:51:07.865915 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8800 06:51:07.872582 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8801 06:51:07.872674 Total UI for P1: 0, mck2ui 16
8802 06:51:07.879364 best dqsien dly found for B1: ( 1, 9, 8)
8803 06:51:07.882464 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8804 06:51:07.885970 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 06:51:07.889417 Total UI for P1: 0, mck2ui 16
8806 06:51:07.892499 best dqsien dly found for B0: ( 1, 9, 14)
8807 06:51:07.896337 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8808 06:51:07.899525 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8809 06:51:07.899607
8810 06:51:07.906166 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8811 06:51:07.909648 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8812 06:51:07.909731 [Gating] SW calibration Done
8813 06:51:07.912481 ==
8814 06:51:07.916052 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 06:51:07.919546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 06:51:07.919628 ==
8817 06:51:07.919707 RX Vref Scan: 0
8818 06:51:07.919783
8819 06:51:07.922373 RX Vref 0 -> 0, step: 1
8820 06:51:07.922471
8821 06:51:07.925888 RX Delay 0 -> 252, step: 8
8822 06:51:07.929443 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8823 06:51:07.933075 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8824 06:51:07.935884 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8825 06:51:07.942903 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8826 06:51:07.945732 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8827 06:51:07.949150 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8828 06:51:07.952470 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8829 06:51:07.955741 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8830 06:51:07.962368 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8831 06:51:07.965771 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8832 06:51:07.969250 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8833 06:51:07.972719 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8834 06:51:07.976167 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8835 06:51:07.982215 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8836 06:51:07.985695 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8837 06:51:07.989158 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8838 06:51:07.989241 ==
8839 06:51:07.991991 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 06:51:07.995487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 06:51:07.995570 ==
8842 06:51:07.998786 DQS Delay:
8843 06:51:07.998867 DQS0 = 0, DQS1 = 0
8844 06:51:08.002579 DQM Delay:
8845 06:51:08.002660 DQM0 = 136, DQM1 = 133
8846 06:51:08.005544 DQ Delay:
8847 06:51:08.009010 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8848 06:51:08.012170 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8849 06:51:08.015489 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8850 06:51:08.018891 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8851 06:51:08.018973
8852 06:51:08.019038
8853 06:51:08.019098 ==
8854 06:51:08.022027 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 06:51:08.025536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 06:51:08.025619 ==
8857 06:51:08.025718
8858 06:51:08.025821
8859 06:51:08.029038 TX Vref Scan disable
8860 06:51:08.032234 == TX Byte 0 ==
8861 06:51:08.035783 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8862 06:51:08.039255 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8863 06:51:08.042064 == TX Byte 1 ==
8864 06:51:08.045454 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8865 06:51:08.049044 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8866 06:51:08.049126 ==
8867 06:51:08.051867 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 06:51:08.058818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 06:51:08.058901 ==
8870 06:51:08.070039
8871 06:51:08.073425 TX Vref early break, caculate TX vref
8872 06:51:08.076753 TX Vref=16, minBit 0, minWin=23, winSum=381
8873 06:51:08.080242 TX Vref=18, minBit 0, minWin=23, winSum=393
8874 06:51:08.083800 TX Vref=20, minBit 0, minWin=23, winSum=395
8875 06:51:08.087186 TX Vref=22, minBit 0, minWin=25, winSum=409
8876 06:51:08.090004 TX Vref=24, minBit 0, minWin=25, winSum=413
8877 06:51:08.096900 TX Vref=26, minBit 0, minWin=25, winSum=424
8878 06:51:08.100362 TX Vref=28, minBit 0, minWin=26, winSum=424
8879 06:51:08.103261 TX Vref=30, minBit 1, minWin=25, winSum=419
8880 06:51:08.106843 TX Vref=32, minBit 0, minWin=25, winSum=414
8881 06:51:08.110300 TX Vref=34, minBit 0, minWin=24, winSum=400
8882 06:51:08.117231 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8883 06:51:08.117314
8884 06:51:08.120490 Final TX Range 0 Vref 28
8885 06:51:08.120573
8886 06:51:08.120637 ==
8887 06:51:08.123333 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 06:51:08.126796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 06:51:08.126879 ==
8890 06:51:08.126944
8891 06:51:08.127004
8892 06:51:08.130273 TX Vref Scan disable
8893 06:51:08.136934 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8894 06:51:08.137016 == TX Byte 0 ==
8895 06:51:08.140245 u2DelayCellOfst[0]=16 cells (5 PI)
8896 06:51:08.143679 u2DelayCellOfst[1]=10 cells (3 PI)
8897 06:51:08.146916 u2DelayCellOfst[2]=0 cells (0 PI)
8898 06:51:08.150443 u2DelayCellOfst[3]=6 cells (2 PI)
8899 06:51:08.153897 u2DelayCellOfst[4]=6 cells (2 PI)
8900 06:51:08.156657 u2DelayCellOfst[5]=20 cells (6 PI)
8901 06:51:08.156748 u2DelayCellOfst[6]=16 cells (5 PI)
8902 06:51:08.160144 u2DelayCellOfst[7]=6 cells (2 PI)
8903 06:51:08.167139 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8904 06:51:08.170367 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8905 06:51:08.170452 == TX Byte 1 ==
8906 06:51:08.173578 u2DelayCellOfst[8]=0 cells (0 PI)
8907 06:51:08.176799 u2DelayCellOfst[9]=3 cells (1 PI)
8908 06:51:08.180213 u2DelayCellOfst[10]=10 cells (3 PI)
8909 06:51:08.183651 u2DelayCellOfst[11]=6 cells (2 PI)
8910 06:51:08.187020 u2DelayCellOfst[12]=13 cells (4 PI)
8911 06:51:08.190380 u2DelayCellOfst[13]=16 cells (5 PI)
8912 06:51:08.193220 u2DelayCellOfst[14]=16 cells (5 PI)
8913 06:51:08.196513 u2DelayCellOfst[15]=16 cells (5 PI)
8914 06:51:08.199886 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8915 06:51:08.203503 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8916 06:51:08.207048 DramC Write-DBI on
8917 06:51:08.207130 ==
8918 06:51:08.209779 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 06:51:08.213260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 06:51:08.213343 ==
8921 06:51:08.213441
8922 06:51:08.216636
8923 06:51:08.216718 TX Vref Scan disable
8924 06:51:08.220215 == TX Byte 0 ==
8925 06:51:08.223060 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8926 06:51:08.226535 == TX Byte 1 ==
8927 06:51:08.229800 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8928 06:51:08.229882 DramC Write-DBI off
8929 06:51:08.229947
8930 06:51:08.233672 [DATLAT]
8931 06:51:08.233754 Freq=1600, CH1 RK1
8932 06:51:08.233819
8933 06:51:08.236951 DATLAT Default: 0xf
8934 06:51:08.237034 0, 0xFFFF, sum = 0
8935 06:51:08.239833 1, 0xFFFF, sum = 0
8936 06:51:08.239916 2, 0xFFFF, sum = 0
8937 06:51:08.243228 3, 0xFFFF, sum = 0
8938 06:51:08.243304 4, 0xFFFF, sum = 0
8939 06:51:08.246644 5, 0xFFFF, sum = 0
8940 06:51:08.246727 6, 0xFFFF, sum = 0
8941 06:51:08.250164 7, 0xFFFF, sum = 0
8942 06:51:08.253590 8, 0xFFFF, sum = 0
8943 06:51:08.253673 9, 0xFFFF, sum = 0
8944 06:51:08.256945 10, 0xFFFF, sum = 0
8945 06:51:08.257028 11, 0xFFFF, sum = 0
8946 06:51:08.260126 12, 0xFFFF, sum = 0
8947 06:51:08.260209 13, 0xFFFF, sum = 0
8948 06:51:08.263246 14, 0x0, sum = 1
8949 06:51:08.263366 15, 0x0, sum = 2
8950 06:51:08.266376 16, 0x0, sum = 3
8951 06:51:08.266459 17, 0x0, sum = 4
8952 06:51:08.266525 best_step = 15
8953 06:51:08.269754
8954 06:51:08.269838 ==
8955 06:51:08.273356 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 06:51:08.276853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 06:51:08.276936 ==
8958 06:51:08.277001 RX Vref Scan: 0
8959 06:51:08.277062
8960 06:51:08.280176 RX Vref 0 -> 0, step: 1
8961 06:51:08.280258
8962 06:51:08.283459 RX Delay 19 -> 252, step: 4
8963 06:51:08.286645 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8964 06:51:08.290152 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8965 06:51:08.296667 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8966 06:51:08.299993 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8967 06:51:08.303409 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8968 06:51:08.306740 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8969 06:51:08.310148 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8970 06:51:08.316480 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8971 06:51:08.319744 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8972 06:51:08.323304 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8973 06:51:08.326117 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8974 06:51:08.329624 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8975 06:51:08.336562 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8976 06:51:08.339920 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8977 06:51:08.343263 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8978 06:51:08.346396 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8979 06:51:08.346496 ==
8980 06:51:08.349820 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 06:51:08.356029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 06:51:08.356118 ==
8983 06:51:08.356183 DQS Delay:
8984 06:51:08.356250 DQS0 = 0, DQS1 = 0
8985 06:51:08.359544 DQM Delay:
8986 06:51:08.359618 DQM0 = 134, DQM1 = 130
8987 06:51:08.363141 DQ Delay:
8988 06:51:08.366522 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8989 06:51:08.369951 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8990 06:51:08.372706 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8991 06:51:08.376030 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8992 06:51:08.376105
8993 06:51:08.376167
8994 06:51:08.376231
8995 06:51:08.379360 [DramC_TX_OE_Calibration] TA2
8996 06:51:08.382893 Original DQ_B0 (3 6) =30, OEN = 27
8997 06:51:08.386347 Original DQ_B1 (3 6) =30, OEN = 27
8998 06:51:08.389723 24, 0x0, End_B0=24 End_B1=24
8999 06:51:08.389801 25, 0x0, End_B0=25 End_B1=25
9000 06:51:08.392482 26, 0x0, End_B0=26 End_B1=26
9001 06:51:08.396508 27, 0x0, End_B0=27 End_B1=27
9002 06:51:08.399769 28, 0x0, End_B0=28 End_B1=28
9003 06:51:08.402821 29, 0x0, End_B0=29 End_B1=29
9004 06:51:08.402906 30, 0x0, End_B0=30 End_B1=30
9005 06:51:08.406205 31, 0x4141, End_B0=30 End_B1=30
9006 06:51:08.409489 Byte0 end_step=30 best_step=27
9007 06:51:08.412976 Byte1 end_step=30 best_step=27
9008 06:51:08.416220 Byte0 TX OE(2T, 0.5T) = (3, 3)
9009 06:51:08.416327 Byte1 TX OE(2T, 0.5T) = (3, 3)
9010 06:51:08.419645
9011 06:51:08.419739
9012 06:51:08.426583 [DQSOSCAuto] RK1, (LSB)MR18= 0x2106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9013 06:51:08.429374 CH1 RK1: MR19=303, MR18=2106
9014 06:51:08.436265 CH1_RK1: MR19=0x303, MR18=0x2106, DQSOSC=393, MR23=63, INC=23, DEC=15
9015 06:51:08.439242 [RxdqsGatingPostProcess] freq 1600
9016 06:51:08.442770 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9017 06:51:08.446341 best DQS0 dly(2T, 0.5T) = (1, 1)
9018 06:51:08.449110 best DQS1 dly(2T, 0.5T) = (1, 1)
9019 06:51:08.452479 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9020 06:51:08.455787 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9021 06:51:08.459620 best DQS0 dly(2T, 0.5T) = (1, 1)
9022 06:51:08.462811 best DQS1 dly(2T, 0.5T) = (1, 1)
9023 06:51:08.466097 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9024 06:51:08.469450 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9025 06:51:08.472440 Pre-setting of DQS Precalculation
9026 06:51:08.475848 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9027 06:51:08.482293 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9028 06:51:08.489531 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9029 06:51:08.489607
9030 06:51:08.492494
9031 06:51:08.492564 [Calibration Summary] 3200 Mbps
9032 06:51:08.495616 CH 0, Rank 0
9033 06:51:08.495690 SW Impedance : PASS
9034 06:51:08.498913 DUTY Scan : NO K
9035 06:51:08.502681 ZQ Calibration : PASS
9036 06:51:08.502766 Jitter Meter : NO K
9037 06:51:08.505800 CBT Training : PASS
9038 06:51:08.509263 Write leveling : PASS
9039 06:51:08.509339 RX DQS gating : PASS
9040 06:51:08.512795 RX DQ/DQS(RDDQC) : PASS
9041 06:51:08.515883 TX DQ/DQS : PASS
9042 06:51:08.515956 RX DATLAT : PASS
9043 06:51:08.519074 RX DQ/DQS(Engine): PASS
9044 06:51:08.522576 TX OE : PASS
9045 06:51:08.522680 All Pass.
9046 06:51:08.522740
9047 06:51:08.522799 CH 0, Rank 1
9048 06:51:08.525732 SW Impedance : PASS
9049 06:51:08.525806 DUTY Scan : NO K
9050 06:51:08.528888 ZQ Calibration : PASS
9051 06:51:08.532540 Jitter Meter : NO K
9052 06:51:08.532613 CBT Training : PASS
9053 06:51:08.536208 Write leveling : PASS
9054 06:51:08.538987 RX DQS gating : PASS
9055 06:51:08.539060 RX DQ/DQS(RDDQC) : PASS
9056 06:51:08.542456 TX DQ/DQS : PASS
9057 06:51:08.545941 RX DATLAT : PASS
9058 06:51:08.546023 RX DQ/DQS(Engine): PASS
9059 06:51:08.548726 TX OE : PASS
9060 06:51:08.548799 All Pass.
9061 06:51:08.548860
9062 06:51:08.552237 CH 1, Rank 0
9063 06:51:08.552342 SW Impedance : PASS
9064 06:51:08.555740 DUTY Scan : NO K
9065 06:51:08.559261 ZQ Calibration : PASS
9066 06:51:08.559341 Jitter Meter : NO K
9067 06:51:08.562170 CBT Training : PASS
9068 06:51:08.565570 Write leveling : PASS
9069 06:51:08.565648 RX DQS gating : PASS
9070 06:51:08.568902 RX DQ/DQS(RDDQC) : PASS
9071 06:51:08.572345 TX DQ/DQS : PASS
9072 06:51:08.572425 RX DATLAT : PASS
9073 06:51:08.575730 RX DQ/DQS(Engine): PASS
9074 06:51:08.575804 TX OE : PASS
9075 06:51:08.578912 All Pass.
9076 06:51:08.578990
9077 06:51:08.579053 CH 1, Rank 1
9078 06:51:08.582448 SW Impedance : PASS
9079 06:51:08.582529 DUTY Scan : NO K
9080 06:51:08.585267 ZQ Calibration : PASS
9081 06:51:08.588777 Jitter Meter : NO K
9082 06:51:08.588850 CBT Training : PASS
9083 06:51:08.592297 Write leveling : PASS
9084 06:51:08.595665 RX DQS gating : PASS
9085 06:51:08.595747 RX DQ/DQS(RDDQC) : PASS
9086 06:51:08.599116 TX DQ/DQS : PASS
9087 06:51:08.602416 RX DATLAT : PASS
9088 06:51:08.602488 RX DQ/DQS(Engine): PASS
9089 06:51:08.605187 TX OE : PASS
9090 06:51:08.605270 All Pass.
9091 06:51:08.605339
9092 06:51:08.608615 DramC Write-DBI on
9093 06:51:08.611812 PER_BANK_REFRESH: Hybrid Mode
9094 06:51:08.611889 TX_TRACKING: ON
9095 06:51:08.622238 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9096 06:51:08.628354 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9097 06:51:08.635226 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 06:51:08.638667 [FAST_K] Save calibration result to emmc
9099 06:51:08.641934 sync common calibartion params.
9100 06:51:08.645243 sync cbt_mode0:1, 1:1
9101 06:51:08.648300 dram_init: ddr_geometry: 2
9102 06:51:08.648383 dram_init: ddr_geometry: 2
9103 06:51:08.652196 dram_init: ddr_geometry: 2
9104 06:51:08.654919 0:dram_rank_size:100000000
9105 06:51:08.658414 1:dram_rank_size:100000000
9106 06:51:08.662056 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9107 06:51:08.664934 DFS_SHUFFLE_HW_MODE: ON
9108 06:51:08.668503 dramc_set_vcore_voltage set vcore to 725000
9109 06:51:08.672047 Read voltage for 1600, 0
9110 06:51:08.672159 Vio18 = 0
9111 06:51:08.672260 Vcore = 725000
9112 06:51:08.675400 Vdram = 0
9113 06:51:08.675484 Vddq = 0
9114 06:51:08.675548 Vmddr = 0
9115 06:51:08.678864 switch to 3200 Mbps bootup
9116 06:51:08.678942 [DramcRunTimeConfig]
9117 06:51:08.681645 PHYPLL
9118 06:51:08.681723 DPM_CONTROL_AFTERK: ON
9119 06:51:08.685032 PER_BANK_REFRESH: ON
9120 06:51:08.688362 REFRESH_OVERHEAD_REDUCTION: ON
9121 06:51:08.688436 CMD_PICG_NEW_MODE: OFF
9122 06:51:08.692228 XRTWTW_NEW_MODE: ON
9123 06:51:08.692340 XRTRTR_NEW_MODE: ON
9124 06:51:08.694969 TX_TRACKING: ON
9125 06:51:08.695043 RDSEL_TRACKING: OFF
9126 06:51:08.698463 DQS Precalculation for DVFS: ON
9127 06:51:08.702017 RX_TRACKING: OFF
9128 06:51:08.702096 HW_GATING DBG: ON
9129 06:51:08.704814 ZQCS_ENABLE_LP4: ON
9130 06:51:08.704888 RX_PICG_NEW_MODE: ON
9131 06:51:08.708298 TX_PICG_NEW_MODE: ON
9132 06:51:08.711713 ENABLE_RX_DCM_DPHY: ON
9133 06:51:08.711791 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9134 06:51:08.715157 DUMMY_READ_FOR_TRACKING: OFF
9135 06:51:08.718651 !!! SPM_CONTROL_AFTERK: OFF
9136 06:51:08.722181 !!! SPM could not control APHY
9137 06:51:08.722259 IMPEDANCE_TRACKING: ON
9138 06:51:08.724786 TEMP_SENSOR: ON
9139 06:51:08.724878 HW_SAVE_FOR_SR: OFF
9140 06:51:08.728620 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9141 06:51:08.731600 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9142 06:51:08.735268 Read ODT Tracking: ON
9143 06:51:08.738102 Refresh Rate DeBounce: ON
9144 06:51:08.738223 DFS_NO_QUEUE_FLUSH: ON
9145 06:51:08.741558 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9146 06:51:08.745127 ENABLE_DFS_RUNTIME_MRW: OFF
9147 06:51:08.748472 DDR_RESERVE_NEW_MODE: ON
9148 06:51:08.748569 MR_CBT_SWITCH_FREQ: ON
9149 06:51:08.751778 =========================
9150 06:51:08.770968 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9151 06:51:08.774420 dram_init: ddr_geometry: 2
9152 06:51:08.792364 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9153 06:51:08.795856 dram_init: dram init end (result: 0)
9154 06:51:08.802450 DRAM-K: Full calibration passed in 24491 msecs
9155 06:51:08.805816 MRC: failed to locate region type 0.
9156 06:51:08.805922 DRAM rank0 size:0x100000000,
9157 06:51:08.808714 DRAM rank1 size=0x100000000
9158 06:51:08.819168 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9159 06:51:08.825548 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9160 06:51:08.831863 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9161 06:51:08.839198 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9162 06:51:08.841913 DRAM rank0 size:0x100000000,
9163 06:51:08.845271 DRAM rank1 size=0x100000000
9164 06:51:08.845371 CBMEM:
9165 06:51:08.848638 IMD: root @ 0xfffff000 254 entries.
9166 06:51:08.851909 IMD: root @ 0xffffec00 62 entries.
9167 06:51:08.855270 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9168 06:51:08.858962 WARNING: RO_VPD is uninitialized or empty.
9169 06:51:08.865358 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9170 06:51:08.872627 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9171 06:51:08.885576 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9172 06:51:08.896487 BS: romstage times (exec / console): total (unknown) / 24014 ms
9173 06:51:08.896599
9174 06:51:08.896683
9175 06:51:08.906247 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9176 06:51:08.909723 ARM64: Exception handlers installed.
9177 06:51:08.913101 ARM64: Testing exception
9178 06:51:08.916191 ARM64: Done test exception
9179 06:51:08.916298 Enumerating buses...
9180 06:51:08.919533 Show all devs... Before device enumeration.
9181 06:51:08.922921 Root Device: enabled 1
9182 06:51:08.926237 CPU_CLUSTER: 0: enabled 1
9183 06:51:08.926323 CPU: 00: enabled 1
9184 06:51:08.929911 Compare with tree...
9185 06:51:08.929998 Root Device: enabled 1
9186 06:51:08.933426 CPU_CLUSTER: 0: enabled 1
9187 06:51:08.936296 CPU: 00: enabled 1
9188 06:51:08.936383 Root Device scanning...
9189 06:51:08.939843 scan_static_bus for Root Device
9190 06:51:08.943342 CPU_CLUSTER: 0 enabled
9191 06:51:08.946138 scan_static_bus for Root Device done
9192 06:51:08.949567 scan_bus: bus Root Device finished in 8 msecs
9193 06:51:08.949653 done
9194 06:51:08.956466 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9195 06:51:08.960039 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9196 06:51:08.966413 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9197 06:51:08.969832 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9198 06:51:08.973293 Allocating resources...
9199 06:51:08.973379 Reading resources...
9200 06:51:08.979507 Root Device read_resources bus 0 link: 0
9201 06:51:08.979593 DRAM rank0 size:0x100000000,
9202 06:51:08.982770 DRAM rank1 size=0x100000000
9203 06:51:08.986633 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9204 06:51:08.989847 CPU: 00 missing read_resources
9205 06:51:08.993151 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9206 06:51:09.000017 Root Device read_resources bus 0 link: 0 done
9207 06:51:09.000105 Done reading resources.
9208 06:51:09.006121 Show resources in subtree (Root Device)...After reading.
9209 06:51:09.009870 Root Device child on link 0 CPU_CLUSTER: 0
9210 06:51:09.012964 CPU_CLUSTER: 0 child on link 0 CPU: 00
9211 06:51:09.022620 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9212 06:51:09.022710 CPU: 00
9213 06:51:09.026119 Root Device assign_resources, bus 0 link: 0
9214 06:51:09.029489 CPU_CLUSTER: 0 missing set_resources
9215 06:51:09.032794 Root Device assign_resources, bus 0 link: 0 done
9216 06:51:09.036166 Done setting resources.
9217 06:51:09.042482 Show resources in subtree (Root Device)...After assigning values.
9218 06:51:09.045888 Root Device child on link 0 CPU_CLUSTER: 0
9219 06:51:09.049505 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 06:51:09.059266 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 06:51:09.059389 CPU: 00
9222 06:51:09.062741 Done allocating resources.
9223 06:51:09.066254 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9224 06:51:09.069035 Enabling resources...
9225 06:51:09.069119 done.
9226 06:51:09.076053 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9227 06:51:09.076175 Initializing devices...
9228 06:51:09.079566 Root Device init
9229 06:51:09.079656 init hardware done!
9230 06:51:09.082384 0x00000018: ctrlr->caps
9231 06:51:09.086066 52.000 MHz: ctrlr->f_max
9232 06:51:09.086168 0.400 MHz: ctrlr->f_min
9233 06:51:09.089311 0x40ff8080: ctrlr->voltages
9234 06:51:09.089407 sclk: 390625
9235 06:51:09.092221 Bus Width = 1
9236 06:51:09.092365 sclk: 390625
9237 06:51:09.095632 Bus Width = 1
9238 06:51:09.095753 Early init status = 3
9239 06:51:09.102337 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9240 06:51:09.105831 in-header: 03 fc 00 00 01 00 00 00
9241 06:51:09.105941 in-data: 00
9242 06:51:09.112715 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9243 06:51:09.116617 in-header: 03 fd 00 00 00 00 00 00
9244 06:51:09.119847 in-data:
9245 06:51:09.122992 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9246 06:51:09.127432 in-header: 03 fc 00 00 01 00 00 00
9247 06:51:09.131239 in-data: 00
9248 06:51:09.134312 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9249 06:51:09.139997 in-header: 03 fd 00 00 00 00 00 00
9250 06:51:09.143316 in-data:
9251 06:51:09.146470 [SSUSB] Setting up USB HOST controller...
9252 06:51:09.149613 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9253 06:51:09.152976 [SSUSB] phy power-on done.
9254 06:51:09.156542 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9255 06:51:09.162797 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9256 06:51:09.166273 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9257 06:51:09.173280 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9258 06:51:09.180210 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9259 06:51:09.186272 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9260 06:51:09.193281 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9261 06:51:09.199578 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9262 06:51:09.199697 SPM: binary array size = 0x9dc
9263 06:51:09.206344 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9264 06:51:09.213212 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9265 06:51:09.219437 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9266 06:51:09.223117 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9267 06:51:09.226388 configure_display: Starting display init
9268 06:51:09.263094 anx7625_power_on_init: Init interface.
9269 06:51:09.266276 anx7625_disable_pd_protocol: Disabled PD feature.
9270 06:51:09.269770 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9271 06:51:09.297501 anx7625_start_dp_work: Secure OCM version=00
9272 06:51:09.300931 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9273 06:51:09.315368 sp_tx_get_edid_block: EDID Block = 1
9274 06:51:09.418142 Extracted contents:
9275 06:51:09.421529 header: 00 ff ff ff ff ff ff 00
9276 06:51:09.424917 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9277 06:51:09.428412 version: 01 04
9278 06:51:09.431205 basic params: 95 1f 11 78 0a
9279 06:51:09.434618 chroma info: 76 90 94 55 54 90 27 21 50 54
9280 06:51:09.437965 established: 00 00 00
9281 06:51:09.444808 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9282 06:51:09.448211 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9283 06:51:09.454629 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9284 06:51:09.461786 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9285 06:51:09.468196 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9286 06:51:09.471211 extensions: 00
9287 06:51:09.471314 checksum: fb
9288 06:51:09.471446
9289 06:51:09.474387 Manufacturer: IVO Model 57d Serial Number 0
9290 06:51:09.477842 Made week 0 of 2020
9291 06:51:09.477941 EDID version: 1.4
9292 06:51:09.481474 Digital display
9293 06:51:09.484268 6 bits per primary color channel
9294 06:51:09.484388 DisplayPort interface
9295 06:51:09.487666 Maximum image size: 31 cm x 17 cm
9296 06:51:09.491430 Gamma: 220%
9297 06:51:09.491535 Check DPMS levels
9298 06:51:09.494516 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9299 06:51:09.497641 First detailed timing is preferred timing
9300 06:51:09.501229 Established timings supported:
9301 06:51:09.504308 Standard timings supported:
9302 06:51:09.504480 Detailed timings
9303 06:51:09.511350 Hex of detail: 383680a07038204018303c0035ae10000019
9304 06:51:09.514679 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9305 06:51:09.521459 0780 0798 07c8 0820 hborder 0
9306 06:51:09.524152 0438 043b 0447 0458 vborder 0
9307 06:51:09.527701 -hsync -vsync
9308 06:51:09.527793 Did detailed timing
9309 06:51:09.531126 Hex of detail: 000000000000000000000000000000000000
9310 06:51:09.534644 Manufacturer-specified data, tag 0
9311 06:51:09.540800 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9312 06:51:09.540882 ASCII string: InfoVision
9313 06:51:09.547852 Hex of detail: 000000fe00523134304e574635205248200a
9314 06:51:09.550711 ASCII string: R140NWF5 RH
9315 06:51:09.550805 Checksum
9316 06:51:09.550871 Checksum: 0xfb (valid)
9317 06:51:09.558059 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9318 06:51:09.560897 DSI data_rate: 832800000 bps
9319 06:51:09.564425 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9320 06:51:09.568091 anx7625_parse_edid: pixelclock(138800).
9321 06:51:09.574364 hactive(1920), hsync(48), hfp(24), hbp(88)
9322 06:51:09.577857 vactive(1080), vsync(12), vfp(3), vbp(17)
9323 06:51:09.580665 anx7625_dsi_config: config dsi.
9324 06:51:09.587297 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9325 06:51:09.600259 anx7625_dsi_config: success to config DSI
9326 06:51:09.603522 anx7625_dp_start: MIPI phy setup OK.
9327 06:51:09.606839 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9328 06:51:09.609990 mtk_ddp_mode_set invalid vrefresh 60
9329 06:51:09.613318 main_disp_path_setup
9330 06:51:09.613399 ovl_layer_smi_id_en
9331 06:51:09.616951 ovl_layer_smi_id_en
9332 06:51:09.617033 ccorr_config
9333 06:51:09.617113 aal_config
9334 06:51:09.620309 gamma_config
9335 06:51:09.620389 postmask_config
9336 06:51:09.623506 dither_config
9337 06:51:09.626961 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9338 06:51:09.633718 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9339 06:51:09.636530 Root Device init finished in 554 msecs
9340 06:51:09.636612 CPU_CLUSTER: 0 init
9341 06:51:09.646865 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9342 06:51:09.650471 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9343 06:51:09.653926 APU_MBOX 0x190000b0 = 0x10001
9344 06:51:09.656492 APU_MBOX 0x190001b0 = 0x10001
9345 06:51:09.659988 APU_MBOX 0x190005b0 = 0x10001
9346 06:51:09.663530 APU_MBOX 0x190006b0 = 0x10001
9347 06:51:09.666994 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9348 06:51:09.678787 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9349 06:51:09.691818 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9350 06:51:09.697858 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9351 06:51:09.709835 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9352 06:51:09.718721 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9353 06:51:09.722124 CPU_CLUSTER: 0 init finished in 81 msecs
9354 06:51:09.725693 Devices initialized
9355 06:51:09.728833 Show all devs... After init.
9356 06:51:09.728917 Root Device: enabled 1
9357 06:51:09.732086 CPU_CLUSTER: 0: enabled 1
9358 06:51:09.735370 CPU: 00: enabled 1
9359 06:51:09.739189 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9360 06:51:09.742409 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9361 06:51:09.745763 ELOG: NV offset 0x57f000 size 0x1000
9362 06:51:09.751836 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9363 06:51:09.758319 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9364 06:51:09.761744 ELOG: Event(17) added with size 13 at 2024-02-03 06:48:30 UTC
9365 06:51:09.768761 out: cmd=0x121: 03 db 21 01 00 00 00 00
9366 06:51:09.771471 in-header: 03 bb 00 00 2c 00 00 00
9367 06:51:09.781963 in-data: a4 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9368 06:51:09.788417 ELOG: Event(A1) added with size 10 at 2024-02-03 06:48:30 UTC
9369 06:51:09.794948 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9370 06:51:09.801869 ELOG: Event(A0) added with size 9 at 2024-02-03 06:48:30 UTC
9371 06:51:09.804681 elog_add_boot_reason: Logged dev mode boot
9372 06:51:09.811541 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9373 06:51:09.811624 Finalize devices...
9374 06:51:09.814923 Devices finalized
9375 06:51:09.818147 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9376 06:51:09.821261 Writing coreboot table at 0xffe64000
9377 06:51:09.824751 0. 000000000010a000-0000000000113fff: RAMSTAGE
9378 06:51:09.828316 1. 0000000040000000-00000000400fffff: RAM
9379 06:51:09.834721 2. 0000000040100000-000000004032afff: RAMSTAGE
9380 06:51:09.838169 3. 000000004032b000-00000000545fffff: RAM
9381 06:51:09.841765 4. 0000000054600000-000000005465ffff: BL31
9382 06:51:09.844917 5. 0000000054660000-00000000ffe63fff: RAM
9383 06:51:09.851237 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9384 06:51:09.855040 7. 0000000100000000-000000023fffffff: RAM
9385 06:51:09.857831 Passing 5 GPIOs to payload:
9386 06:51:09.861555 NAME | PORT | POLARITY | VALUE
9387 06:51:09.864763 EC in RW | 0x000000aa | low | undefined
9388 06:51:09.871349 EC interrupt | 0x00000005 | low | undefined
9389 06:51:09.874881 TPM interrupt | 0x000000ab | high | undefined
9390 06:51:09.881254 SD card detect | 0x00000011 | high | undefined
9391 06:51:09.884752 speaker enable | 0x00000093 | high | undefined
9392 06:51:09.888346 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9393 06:51:09.891288 in-header: 03 f9 00 00 02 00 00 00
9394 06:51:09.894700 in-data: 02 00
9395 06:51:09.898249 ADC[4]: Raw value=904726 ID=7
9396 06:51:09.898349 ADC[3]: Raw value=213441 ID=1
9397 06:51:09.900998 RAM Code: 0x71
9398 06:51:09.904334 ADC[6]: Raw value=75332 ID=0
9399 06:51:09.904420 ADC[5]: Raw value=212703 ID=1
9400 06:51:09.907918 SKU Code: 0x1
9401 06:51:09.911580 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3253
9402 06:51:09.914398 coreboot table: 964 bytes.
9403 06:51:09.918080 IMD ROOT 0. 0xfffff000 0x00001000
9404 06:51:09.921518 IMD SMALL 1. 0xffffe000 0x00001000
9405 06:51:09.924302 RO MCACHE 2. 0xffffc000 0x00001104
9406 06:51:09.927793 CONSOLE 3. 0xfff7c000 0x00080000
9407 06:51:09.931193 FMAP 4. 0xfff7b000 0x00000452
9408 06:51:09.934720 TIME STAMP 5. 0xfff7a000 0x00000910
9409 06:51:09.938059 VBOOT WORK 6. 0xfff66000 0x00014000
9410 06:51:09.941219 RAMOOPS 7. 0xffe66000 0x00100000
9411 06:51:09.944271 COREBOOT 8. 0xffe64000 0x00002000
9412 06:51:09.947508 IMD small region:
9413 06:51:09.951267 IMD ROOT 0. 0xffffec00 0x00000400
9414 06:51:09.954191 VPD 1. 0xffffeb80 0x0000006c
9415 06:51:09.957934 MMC STATUS 2. 0xffffeb60 0x00000004
9416 06:51:09.961065 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9417 06:51:09.964563 Probing TPM: done!
9418 06:51:09.967667 Connected to device vid:did:rid of 1ae0:0028:00
9419 06:51:09.978291 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9420 06:51:09.981448 Initialized TPM device CR50 revision 0
9421 06:51:09.985214 Checking cr50 for pending updates
9422 06:51:09.989144 Reading cr50 TPM mode
9423 06:51:09.997357 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9424 06:51:10.004204 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9425 06:51:10.044117 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9426 06:51:10.047536 Checking segment from ROM address 0x40100000
9427 06:51:10.050913 Checking segment from ROM address 0x4010001c
9428 06:51:10.057717 Loading segment from ROM address 0x40100000
9429 06:51:10.057795 code (compression=0)
9430 06:51:10.067667 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9431 06:51:10.074444 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9432 06:51:10.074535 it's not compressed!
9433 06:51:10.080890 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9434 06:51:10.084097 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9435 06:51:10.104841 Loading segment from ROM address 0x4010001c
9436 06:51:10.104930 Entry Point 0x80000000
9437 06:51:10.107888 Loaded segments
9438 06:51:10.111155 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9439 06:51:10.118214 Jumping to boot code at 0x80000000(0xffe64000)
9440 06:51:10.124545 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9441 06:51:10.131445 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9442 06:51:10.139067 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9443 06:51:10.142394 Checking segment from ROM address 0x40100000
9444 06:51:10.145814 Checking segment from ROM address 0x4010001c
9445 06:51:10.149566 Loading segment from ROM address 0x40100000
9446 06:51:10.153049 code (compression=1)
9447 06:51:10.159191 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9448 06:51:10.169295 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9449 06:51:10.169404 using LZMA
9450 06:51:10.177560 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9451 06:51:10.184274 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9452 06:51:10.187405 Loading segment from ROM address 0x4010001c
9453 06:51:10.187487 Entry Point 0x54601000
9454 06:51:10.190839 Loaded segments
9455 06:51:10.194108 NOTICE: MT8192 bl31_setup
9456 06:51:10.201416 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9457 06:51:10.204294 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9458 06:51:10.207758 WARNING: region 0:
9459 06:51:10.211250 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 06:51:10.211335 WARNING: region 1:
9461 06:51:10.217873 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9462 06:51:10.221086 WARNING: region 2:
9463 06:51:10.224810 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9464 06:51:10.227745 WARNING: region 3:
9465 06:51:10.231028 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9466 06:51:10.234530 WARNING: region 4:
9467 06:51:10.240876 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9468 06:51:10.240960 WARNING: region 5:
9469 06:51:10.244294 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 06:51:10.247850 WARNING: region 6:
9471 06:51:10.251500 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 06:51:10.251583 WARNING: region 7:
9473 06:51:10.257806 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 06:51:10.264781 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9475 06:51:10.268166 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9476 06:51:10.271482 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9477 06:51:10.278241 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9478 06:51:10.280862 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9479 06:51:10.284319 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9480 06:51:10.290844 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9481 06:51:10.294791 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9482 06:51:10.300956 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9483 06:51:10.304426 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9484 06:51:10.307619 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9485 06:51:10.314392 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9486 06:51:10.317200 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9487 06:51:10.320795 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9488 06:51:10.327212 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9489 06:51:10.330659 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9490 06:51:10.337342 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9491 06:51:10.340584 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9492 06:51:10.344137 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9493 06:51:10.351187 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9494 06:51:10.354400 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9495 06:51:10.357293 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9496 06:51:10.364168 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9497 06:51:10.367606 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9498 06:51:10.374435 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9499 06:51:10.377922 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9500 06:51:10.380789 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9501 06:51:10.387647 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9502 06:51:10.390826 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9503 06:51:10.397852 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9504 06:51:10.401338 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9505 06:51:10.404119 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9506 06:51:10.411152 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9507 06:51:10.414321 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9508 06:51:10.417388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9509 06:51:10.420736 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9510 06:51:10.427566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9511 06:51:10.431140 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9512 06:51:10.434598 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9513 06:51:10.437495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9514 06:51:10.440987 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9515 06:51:10.448110 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9516 06:51:10.450890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9517 06:51:10.454223 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9518 06:51:10.460961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9519 06:51:10.464251 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9520 06:51:10.467848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9521 06:51:10.470955 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9522 06:51:10.477990 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9523 06:51:10.481253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9524 06:51:10.487881 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9525 06:51:10.491551 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9526 06:51:10.494406 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9527 06:51:10.500910 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9528 06:51:10.504536 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9529 06:51:10.511569 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9530 06:51:10.514860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9531 06:51:10.517666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9532 06:51:10.524747 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9533 06:51:10.528164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9534 06:51:10.534841 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9535 06:51:10.537779 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9536 06:51:10.544959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9537 06:51:10.548396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9538 06:51:10.554850 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9539 06:51:10.558302 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9540 06:51:10.561200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9541 06:51:10.568089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9542 06:51:10.571702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9543 06:51:10.577876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9544 06:51:10.581322 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9545 06:51:10.584796 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9546 06:51:10.591451 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9547 06:51:10.594964 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9548 06:51:10.601469 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9549 06:51:10.604431 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9550 06:51:10.611767 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9551 06:51:10.614844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9552 06:51:10.621301 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9553 06:51:10.625009 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9554 06:51:10.628500 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9555 06:51:10.635140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9556 06:51:10.638474 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9557 06:51:10.644633 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9558 06:51:10.648261 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9559 06:51:10.654722 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9560 06:51:10.658127 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9561 06:51:10.661605 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9562 06:51:10.668649 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9563 06:51:10.671573 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9564 06:51:10.678172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9565 06:51:10.682144 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9566 06:51:10.685391 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9567 06:51:10.691535 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9568 06:51:10.695203 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9569 06:51:10.702174 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9570 06:51:10.704873 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9571 06:51:10.708756 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9572 06:51:10.715413 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9573 06:51:10.718583 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9574 06:51:10.721657 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9575 06:51:10.725180 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9576 06:51:10.731970 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9577 06:51:10.734952 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9578 06:51:10.741832 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9579 06:51:10.745351 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9580 06:51:10.748626 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9581 06:51:10.755252 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9582 06:51:10.758636 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9583 06:51:10.764999 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9584 06:51:10.768244 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9585 06:51:10.771876 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9586 06:51:10.778781 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9587 06:51:10.781565 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9588 06:51:10.788498 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9589 06:51:10.792000 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9590 06:51:10.795459 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9591 06:51:10.801768 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9592 06:51:10.805380 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9593 06:51:10.808787 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9594 06:51:10.811670 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9595 06:51:10.815133 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9596 06:51:10.821547 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9597 06:51:10.825039 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9598 06:51:10.828352 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9599 06:51:10.835291 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9600 06:51:10.838636 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9601 06:51:10.845444 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9602 06:51:10.848928 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9603 06:51:10.852436 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9604 06:51:10.858759 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9605 06:51:10.862126 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9606 06:51:10.865346 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9607 06:51:10.872361 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9608 06:51:10.875353 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9609 06:51:10.882353 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9610 06:51:10.885371 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9611 06:51:10.888882 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9612 06:51:10.895461 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9613 06:51:10.899148 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9614 06:51:10.902472 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9615 06:51:10.908839 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9616 06:51:10.912253 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9617 06:51:10.919278 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9618 06:51:10.922051 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9619 06:51:10.925678 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9620 06:51:10.932061 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9621 06:51:10.935406 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9622 06:51:10.942333 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9623 06:51:10.945952 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9624 06:51:10.949444 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9625 06:51:10.956005 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9626 06:51:10.959460 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9627 06:51:10.962267 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9628 06:51:10.969256 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9629 06:51:10.972795 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9630 06:51:10.979049 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9631 06:51:10.982267 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9632 06:51:10.985854 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9633 06:51:10.992635 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9634 06:51:10.996014 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9635 06:51:11.002416 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9636 06:51:11.005455 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9637 06:51:11.009205 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9638 06:51:11.015680 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9639 06:51:11.018780 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9640 06:51:11.022491 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9641 06:51:11.029201 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9642 06:51:11.032613 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9643 06:51:11.038736 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9644 06:51:11.042175 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9645 06:51:11.045694 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9646 06:51:11.052596 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9647 06:51:11.055979 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9648 06:51:11.062081 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9649 06:51:11.065413 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9650 06:51:11.069081 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9651 06:51:11.075858 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9652 06:51:11.079443 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9653 06:51:11.082338 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9654 06:51:11.088994 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9655 06:51:11.092132 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9656 06:51:11.099067 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9657 06:51:11.102523 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9658 06:51:11.105331 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9659 06:51:11.112337 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9660 06:51:11.115877 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9661 06:51:11.122450 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9662 06:51:11.125674 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9663 06:51:11.128856 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9664 06:51:11.135460 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9665 06:51:11.138823 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9666 06:51:11.145280 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9667 06:51:11.148907 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9668 06:51:11.155619 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9669 06:51:11.158789 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9670 06:51:11.162374 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9671 06:51:11.168490 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9672 06:51:11.171877 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9673 06:51:11.178739 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9674 06:51:11.181594 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9675 06:51:11.185199 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9676 06:51:11.192092 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9677 06:51:11.195539 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9678 06:51:11.201578 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9679 06:51:11.205143 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9680 06:51:11.211369 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9681 06:51:11.214923 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9682 06:51:11.218376 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9683 06:51:11.224892 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9684 06:51:11.228318 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9685 06:51:11.235042 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9686 06:51:11.238329 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9687 06:51:11.241616 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9688 06:51:11.248130 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9689 06:51:11.251532 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9690 06:51:11.258285 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9691 06:51:11.261428 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9692 06:51:11.265123 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9693 06:51:11.271541 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9694 06:51:11.274936 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9695 06:51:11.281631 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9696 06:51:11.285110 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9697 06:51:11.291403 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9698 06:51:11.294948 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9699 06:51:11.298409 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9700 06:51:11.304744 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9701 06:51:11.308089 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9702 06:51:11.314824 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9703 06:51:11.318407 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9704 06:51:11.321958 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9705 06:51:11.324634 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9706 06:51:11.328925 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9707 06:51:11.334622 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9708 06:51:11.338066 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9709 06:51:11.341732 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9710 06:51:11.348263 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9711 06:51:11.351605 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9712 06:51:11.354805 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9713 06:51:11.361275 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9714 06:51:11.364644 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9715 06:51:11.371615 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9716 06:51:11.374897 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9717 06:51:11.378188 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9718 06:51:11.384863 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9719 06:51:11.388234 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9720 06:51:11.394445 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9721 06:51:11.398237 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9722 06:51:11.401779 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9723 06:51:11.408226 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9724 06:51:11.411744 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9725 06:51:11.414420 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9726 06:51:11.421031 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9727 06:51:11.424516 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9728 06:51:11.427996 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9729 06:51:11.434224 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9730 06:51:11.437717 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9731 06:51:11.444772 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9732 06:51:11.447544 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9733 06:51:11.451185 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9734 06:51:11.457874 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9735 06:51:11.461233 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9736 06:51:11.464630 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9737 06:51:11.471269 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9738 06:51:11.474474 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9739 06:51:11.477731 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9740 06:51:11.484698 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9741 06:51:11.487522 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9742 06:51:11.490920 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9743 06:51:11.497628 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9744 06:51:11.500865 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9745 06:51:11.504590 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9746 06:51:11.507764 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9747 06:51:11.510824 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9748 06:51:11.517817 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9749 06:51:11.521006 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9750 06:51:11.524465 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9751 06:51:11.530782 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9752 06:51:11.534289 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9753 06:51:11.537803 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9754 06:51:11.540628 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9755 06:51:11.547703 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9756 06:51:11.550515 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9757 06:51:11.557646 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9758 06:51:11.560374 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9759 06:51:11.563821 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9760 06:51:11.570746 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9761 06:51:11.574148 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9762 06:51:11.580403 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9763 06:51:11.583807 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9764 06:51:11.587046 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9765 06:51:11.593658 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9766 06:51:11.597169 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9767 06:51:11.604201 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9768 06:51:11.606877 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9769 06:51:11.610309 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9770 06:51:11.617357 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9771 06:51:11.620682 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9772 06:51:11.627331 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9773 06:51:11.630566 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9774 06:51:11.633723 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9775 06:51:11.640383 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9776 06:51:11.643891 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9777 06:51:11.650428 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9778 06:51:11.653745 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9779 06:51:11.657276 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9780 06:51:11.663732 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9781 06:51:11.667170 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9782 06:51:11.673522 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9783 06:51:11.676956 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9784 06:51:11.683300 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9785 06:51:11.686848 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9786 06:51:11.690513 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9787 06:51:11.697204 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9788 06:51:11.700403 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9789 06:51:11.707120 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9790 06:51:11.710542 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9791 06:51:11.713286 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9792 06:51:11.720143 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9793 06:51:11.723773 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9794 06:51:11.730112 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9795 06:51:11.733378 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9796 06:51:11.736569 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9797 06:51:11.743037 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9798 06:51:11.746561 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9799 06:51:11.753073 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9800 06:51:11.756434 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9801 06:51:11.763490 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9802 06:51:11.766504 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9803 06:51:11.770010 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9804 06:51:11.776122 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9805 06:51:11.779591 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9806 06:51:11.786578 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9807 06:51:11.789368 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9808 06:51:11.793009 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9809 06:51:11.799995 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9810 06:51:11.802736 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9811 06:51:11.806214 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9812 06:51:11.812842 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9813 06:51:11.816142 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9814 06:51:11.822824 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9815 06:51:11.826104 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9816 06:51:11.832937 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9817 06:51:11.836452 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9818 06:51:11.839329 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9819 06:51:11.845924 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9820 06:51:11.849411 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9821 06:51:11.856204 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9822 06:51:11.859593 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9823 06:51:11.863132 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9824 06:51:11.869379 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9825 06:51:11.872808 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9826 06:51:11.879560 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9827 06:51:11.882776 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9828 06:51:11.885940 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9829 06:51:11.892531 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9830 06:51:11.896435 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9831 06:51:11.902813 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9832 06:51:11.906339 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9833 06:51:11.912610 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9834 06:51:11.916066 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9835 06:51:11.919487 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9836 06:51:11.926456 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9837 06:51:11.929251 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9838 06:51:11.936189 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9839 06:51:11.939374 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9840 06:51:11.946223 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9841 06:51:11.949638 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9842 06:51:11.956382 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9843 06:51:11.959206 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9844 06:51:11.962660 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9845 06:51:11.969303 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9846 06:51:11.972725 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9847 06:51:11.979396 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9848 06:51:11.982904 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9849 06:51:11.989149 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9850 06:51:11.992739 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9851 06:51:11.995519 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9852 06:51:12.002685 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9853 06:51:12.005877 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9854 06:51:12.012606 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9855 06:51:12.015448 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9856 06:51:12.022408 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9857 06:51:12.025754 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9858 06:51:12.032573 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9859 06:51:12.035386 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9860 06:51:12.038915 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9861 06:51:12.045293 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9862 06:51:12.048892 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9863 06:51:12.055260 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9864 06:51:12.058989 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9865 06:51:12.065717 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9866 06:51:12.068524 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9867 06:51:12.071994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9868 06:51:12.078951 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9869 06:51:12.082331 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9870 06:51:12.088611 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9871 06:51:12.092157 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9872 06:51:12.098463 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9873 06:51:12.101904 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9874 06:51:12.105418 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9875 06:51:12.111788 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9876 06:51:12.115239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9877 06:51:12.118443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9878 06:51:12.125235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9879 06:51:12.128464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9880 06:51:12.135076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9881 06:51:12.138508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9882 06:51:12.145388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9883 06:51:12.148857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9884 06:51:12.155028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9885 06:51:12.158607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9886 06:51:12.165426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9887 06:51:12.168629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9888 06:51:12.175336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9889 06:51:12.178398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9890 06:51:12.184911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9891 06:51:12.188658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9892 06:51:12.195474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9893 06:51:12.198287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9894 06:51:12.205390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9895 06:51:12.208809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9896 06:51:12.214968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9897 06:51:12.218481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9898 06:51:12.225421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9899 06:51:12.228858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9900 06:51:12.235205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9901 06:51:12.238344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9902 06:51:12.245268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9903 06:51:12.248599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9904 06:51:12.254927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9905 06:51:12.258585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9906 06:51:12.264897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9907 06:51:12.268335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9908 06:51:12.271961 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9909 06:51:12.275494 INFO: [APUAPC] vio 0
9910 06:51:12.278876 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9911 06:51:12.284934 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9912 06:51:12.288251 INFO: [APUAPC] D0_APC_0: 0x400510
9913 06:51:12.291415 INFO: [APUAPC] D0_APC_1: 0x0
9914 06:51:12.295062 INFO: [APUAPC] D0_APC_2: 0x1540
9915 06:51:12.298133 INFO: [APUAPC] D0_APC_3: 0x0
9916 06:51:12.301924 INFO: [APUAPC] D1_APC_0: 0xffffffff
9917 06:51:12.305061 INFO: [APUAPC] D1_APC_1: 0xffffffff
9918 06:51:12.308207 INFO: [APUAPC] D1_APC_2: 0x3fffff
9919 06:51:12.308381 INFO: [APUAPC] D1_APC_3: 0x0
9920 06:51:12.311586 INFO: [APUAPC] D2_APC_0: 0xffffffff
9921 06:51:12.315036 INFO: [APUAPC] D2_APC_1: 0xffffffff
9922 06:51:12.318528 INFO: [APUAPC] D2_APC_2: 0x3fffff
9923 06:51:12.322138 INFO: [APUAPC] D2_APC_3: 0x0
9924 06:51:12.324963 INFO: [APUAPC] D3_APC_0: 0xffffffff
9925 06:51:12.328436 INFO: [APUAPC] D3_APC_1: 0xffffffff
9926 06:51:12.331352 INFO: [APUAPC] D3_APC_2: 0x3fffff
9927 06:51:12.334870 INFO: [APUAPC] D3_APC_3: 0x0
9928 06:51:12.338334 INFO: [APUAPC] D4_APC_0: 0xffffffff
9929 06:51:12.341670 INFO: [APUAPC] D4_APC_1: 0xffffffff
9930 06:51:12.344940 INFO: [APUAPC] D4_APC_2: 0x3fffff
9931 06:51:12.348129 INFO: [APUAPC] D4_APC_3: 0x0
9932 06:51:12.351513 INFO: [APUAPC] D5_APC_0: 0xffffffff
9933 06:51:12.355030 INFO: [APUAPC] D5_APC_1: 0xffffffff
9934 06:51:12.357793 INFO: [APUAPC] D5_APC_2: 0x3fffff
9935 06:51:12.361242 INFO: [APUAPC] D5_APC_3: 0x0
9936 06:51:12.364603 INFO: [APUAPC] D6_APC_0: 0xffffffff
9937 06:51:12.368001 INFO: [APUAPC] D6_APC_1: 0xffffffff
9938 06:51:12.371289 INFO: [APUAPC] D6_APC_2: 0x3fffff
9939 06:51:12.374701 INFO: [APUAPC] D6_APC_3: 0x0
9940 06:51:12.377530 INFO: [APUAPC] D7_APC_0: 0xffffffff
9941 06:51:12.381004 INFO: [APUAPC] D7_APC_1: 0xffffffff
9942 06:51:12.384588 INFO: [APUAPC] D7_APC_2: 0x3fffff
9943 06:51:12.388120 INFO: [APUAPC] D7_APC_3: 0x0
9944 06:51:12.390938 INFO: [APUAPC] D8_APC_0: 0xffffffff
9945 06:51:12.394496 INFO: [APUAPC] D8_APC_1: 0xffffffff
9946 06:51:12.397347 INFO: [APUAPC] D8_APC_2: 0x3fffff
9947 06:51:12.401294 INFO: [APUAPC] D8_APC_3: 0x0
9948 06:51:12.404684 INFO: [APUAPC] D9_APC_0: 0xffffffff
9949 06:51:12.408082 INFO: [APUAPC] D9_APC_1: 0xffffffff
9950 06:51:12.410725 INFO: [APUAPC] D9_APC_2: 0x3fffff
9951 06:51:12.414699 INFO: [APUAPC] D9_APC_3: 0x0
9952 06:51:12.417699 INFO: [APUAPC] D10_APC_0: 0xffffffff
9953 06:51:12.420967 INFO: [APUAPC] D10_APC_1: 0xffffffff
9954 06:51:12.424189 INFO: [APUAPC] D10_APC_2: 0x3fffff
9955 06:51:12.427377 INFO: [APUAPC] D10_APC_3: 0x0
9956 06:51:12.431159 INFO: [APUAPC] D11_APC_0: 0xffffffff
9957 06:51:12.434664 INFO: [APUAPC] D11_APC_1: 0xffffffff
9958 06:51:12.437457 INFO: [APUAPC] D11_APC_2: 0x3fffff
9959 06:51:12.441096 INFO: [APUAPC] D11_APC_3: 0x0
9960 06:51:12.444527 INFO: [APUAPC] D12_APC_0: 0xffffffff
9961 06:51:12.447339 INFO: [APUAPC] D12_APC_1: 0xffffffff
9962 06:51:12.450702 INFO: [APUAPC] D12_APC_2: 0x3fffff
9963 06:51:12.453938 INFO: [APUAPC] D12_APC_3: 0x0
9964 06:51:12.457643 INFO: [APUAPC] D13_APC_0: 0xffffffff
9965 06:51:12.460935 INFO: [APUAPC] D13_APC_1: 0xffffffff
9966 06:51:12.464426 INFO: [APUAPC] D13_APC_2: 0x3fffff
9967 06:51:12.467236 INFO: [APUAPC] D13_APC_3: 0x0
9968 06:51:12.470692 INFO: [APUAPC] D14_APC_0: 0xffffffff
9969 06:51:12.474282 INFO: [APUAPC] D14_APC_1: 0xffffffff
9970 06:51:12.477875 INFO: [APUAPC] D14_APC_2: 0x3fffff
9971 06:51:12.481134 INFO: [APUAPC] D14_APC_3: 0x0
9972 06:51:12.484354 INFO: [APUAPC] D15_APC_0: 0xffffffff
9973 06:51:12.487305 INFO: [APUAPC] D15_APC_1: 0xffffffff
9974 06:51:12.490684 INFO: [APUAPC] D15_APC_2: 0x3fffff
9975 06:51:12.494295 INFO: [APUAPC] D15_APC_3: 0x0
9976 06:51:12.497160 INFO: [APUAPC] APC_CON: 0x4
9977 06:51:12.500809 INFO: [NOCDAPC] D0_APC_0: 0x0
9978 06:51:12.504260 INFO: [NOCDAPC] D0_APC_1: 0x0
9979 06:51:12.504385 INFO: [NOCDAPC] D1_APC_0: 0x0
9980 06:51:12.507622 INFO: [NOCDAPC] D1_APC_1: 0xfff
9981 06:51:12.510975 INFO: [NOCDAPC] D2_APC_0: 0x0
9982 06:51:12.513813 INFO: [NOCDAPC] D2_APC_1: 0xfff
9983 06:51:12.517216 INFO: [NOCDAPC] D3_APC_0: 0x0
9984 06:51:12.520733 INFO: [NOCDAPC] D3_APC_1: 0xfff
9985 06:51:12.523631 INFO: [NOCDAPC] D4_APC_0: 0x0
9986 06:51:12.526888 INFO: [NOCDAPC] D4_APC_1: 0xfff
9987 06:51:12.530381 INFO: [NOCDAPC] D5_APC_0: 0x0
9988 06:51:12.533935 INFO: [NOCDAPC] D5_APC_1: 0xfff
9989 06:51:12.537264 INFO: [NOCDAPC] D6_APC_0: 0x0
9990 06:51:12.537354 INFO: [NOCDAPC] D6_APC_1: 0xfff
9991 06:51:12.540482 INFO: [NOCDAPC] D7_APC_0: 0x0
9992 06:51:12.544074 INFO: [NOCDAPC] D7_APC_1: 0xfff
9993 06:51:12.547385 INFO: [NOCDAPC] D8_APC_0: 0x0
9994 06:51:12.550285 INFO: [NOCDAPC] D8_APC_1: 0xfff
9995 06:51:12.553867 INFO: [NOCDAPC] D9_APC_0: 0x0
9996 06:51:12.556746 INFO: [NOCDAPC] D9_APC_1: 0xfff
9997 06:51:12.560212 INFO: [NOCDAPC] D10_APC_0: 0x0
9998 06:51:12.563819 INFO: [NOCDAPC] D10_APC_1: 0xfff
9999 06:51:12.566953 INFO: [NOCDAPC] D11_APC_0: 0x0
10000 06:51:12.570176 INFO: [NOCDAPC] D11_APC_1: 0xfff
10001 06:51:12.573443 INFO: [NOCDAPC] D12_APC_0: 0x0
10002 06:51:12.577222 INFO: [NOCDAPC] D12_APC_1: 0xfff
10003 06:51:12.577331 INFO: [NOCDAPC] D13_APC_0: 0x0
10004 06:51:12.580008 INFO: [NOCDAPC] D13_APC_1: 0xfff
10005 06:51:12.583473 INFO: [NOCDAPC] D14_APC_0: 0x0
10006 06:51:12.586999 INFO: [NOCDAPC] D14_APC_1: 0xfff
10007 06:51:12.590305 INFO: [NOCDAPC] D15_APC_0: 0x0
10008 06:51:12.593711 INFO: [NOCDAPC] D15_APC_1: 0xfff
10009 06:51:12.597237 INFO: [NOCDAPC] APC_CON: 0x4
10010 06:51:12.600073 INFO: [APUAPC] set_apusys_apc done
10011 06:51:12.603663 INFO: [DEVAPC] devapc_init done
10012 06:51:12.606459 INFO: GICv3 without legacy support detected.
10013 06:51:12.610044 INFO: ARM GICv3 driver initialized in EL3
10014 06:51:12.616553 INFO: Maximum SPI INTID supported: 639
10015 06:51:12.620128 INFO: BL31: Initializing runtime services
10016 06:51:12.626861 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10017 06:51:12.626940 INFO: SPM: enable CPC mode
10018 06:51:12.633135 INFO: mcdi ready for mcusys-off-idle and system suspend
10019 06:51:12.636461 INFO: BL31: Preparing for EL3 exit to normal world
10020 06:51:12.639908 INFO: Entry point address = 0x80000000
10021 06:51:12.642815 INFO: SPSR = 0x8
10022 06:51:12.649051
10023 06:51:12.649138
10024 06:51:12.649204
10025 06:51:12.652417 Starting depthcharge on Spherion...
10026 06:51:12.652493
10027 06:51:12.652565 Wipe memory regions:
10028 06:51:12.652627
10029 06:51:12.653321 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10030 06:51:12.653425 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10031 06:51:12.653508 Setting prompt string to ['asurada:']
10032 06:51:12.653598 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10033 06:51:12.655165 [0x00000040000000, 0x00000054600000)
10034 06:51:12.777714
10035 06:51:12.777872 [0x00000054660000, 0x00000080000000)
10036 06:51:13.038649
10037 06:51:13.038793 [0x000000821a7280, 0x000000ffe64000)
10038 06:51:13.783340
10039 06:51:13.783540 [0x00000100000000, 0x00000240000000)
10040 06:51:15.672864
10041 06:51:15.676107 Initializing XHCI USB controller at 0x11200000.
10042 06:51:16.715333
10043 06:51:16.718623 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10044 06:51:16.718706
10045 06:51:16.718775
10046 06:51:16.718834
10047 06:51:16.719176 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10049 06:51:16.819497 asurada: tftpboot 192.168.201.1 12694793/tftp-deploy-3scfsdto/kernel/image.itb 12694793/tftp-deploy-3scfsdto/kernel/cmdline
10050 06:51:16.819628 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10051 06:51:16.819739 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10052 06:51:16.823679 tftpboot 192.168.201.1 12694793/tftp-deploy-3scfsdto/kernel/image.ittp-deploy-3scfsdto/kernel/cmdline
10053 06:51:16.823764
10054 06:51:16.823828 Waiting for link
10055 06:51:16.984125
10056 06:51:16.984273 R8152: Initializing
10057 06:51:16.984388
10058 06:51:16.987800 Version 9 (ocp_data = 6010)
10059 06:51:16.987873
10060 06:51:16.990989 R8152: Done initializing
10061 06:51:16.991063
10062 06:51:16.991129 Adding net device
10063 06:51:18.937164
10064 06:51:18.937319 done.
10065 06:51:18.937388
10066 06:51:18.937453 MAC: 00:e0:4c:78:7a:aa
10067 06:51:18.937513
10068 06:51:18.939873 Sending DHCP discover... done.
10069 06:51:18.939974
10070 06:51:22.016781 Waiting for reply... done.
10071 06:51:22.016919
10072 06:51:22.017020 Sending DHCP request... done.
10073 06:51:22.017117
10074 06:51:22.023749 Waiting for reply... done.
10075 06:51:22.023855
10076 06:51:22.023947 My ip is 192.168.201.12
10077 06:51:22.024035
10078 06:51:22.026955 The DHCP server ip is 192.168.201.1
10079 06:51:22.027049
10080 06:51:22.030321 TFTP server IP predefined by user: 192.168.201.1
10081 06:51:22.033792
10082 06:51:22.036895 Bootfile predefined by user: 12694793/tftp-deploy-3scfsdto/kernel/image.itb
10083 06:51:22.039764
10084 06:51:22.039839 Sending tftp read request... done.
10085 06:51:22.039901
10086 06:51:22.046512 Waiting for the transfer...
10087 06:51:22.046588
10088 06:51:22.315184 00000000 ################################################################
10089 06:51:22.315350
10090 06:51:22.577949 00080000 ################################################################
10091 06:51:22.578085
10092 06:51:22.842611 00100000 ################################################################
10093 06:51:22.842747
10094 06:51:23.100710 00180000 ################################################################
10095 06:51:23.100837
10096 06:51:23.365293 00200000 ################################################################
10097 06:51:23.365427
10098 06:51:23.635781 00280000 ################################################################
10099 06:51:23.635917
10100 06:51:23.906243 00300000 ################################################################
10101 06:51:23.906379
10102 06:51:24.169343 00380000 ################################################################
10103 06:51:24.169483
10104 06:51:24.427254 00400000 ################################################################
10105 06:51:24.427400
10106 06:51:24.686481 00480000 ################################################################
10107 06:51:24.686618
10108 06:51:24.956293 00500000 ################################################################
10109 06:51:24.956430
10110 06:51:25.228241 00580000 ################################################################
10111 06:51:25.228435
10112 06:51:25.490619 00600000 ################################################################
10113 06:51:25.490763
10114 06:51:25.751101 00680000 ################################################################
10115 06:51:25.751244
10116 06:51:26.008208 00700000 ################################################################
10117 06:51:26.008370
10118 06:51:26.266176 00780000 ################################################################
10119 06:51:26.266320
10120 06:51:26.537508 00800000 ################################################################
10121 06:51:26.537648
10122 06:51:26.800018 00880000 ################################################################
10123 06:51:26.800161
10124 06:51:27.067317 00900000 ################################################################
10125 06:51:27.067451
10126 06:51:27.334439 00980000 ################################################################
10127 06:51:27.334572
10128 06:51:27.601530 00a00000 ################################################################
10129 06:51:27.601669
10130 06:51:27.874407 00a80000 ################################################################
10131 06:51:27.874550
10132 06:51:28.146322 00b00000 ################################################################
10133 06:51:28.146455
10134 06:51:28.413315 00b80000 ################################################################
10135 06:51:28.413453
10136 06:51:28.692299 00c00000 ################################################################
10137 06:51:28.692480
10138 06:51:28.958568 00c80000 ################################################################
10139 06:51:28.958731
10140 06:51:29.219672 00d00000 ################################################################
10141 06:51:29.219837
10142 06:51:29.477172 00d80000 ################################################################
10143 06:51:29.477308
10144 06:51:29.738914 00e00000 ################################################################
10145 06:51:29.739052
10146 06:51:29.996808 00e80000 ################################################################
10147 06:51:29.997000
10148 06:51:30.260726 00f00000 ################################################################
10149 06:51:30.260861
10150 06:51:30.523300 00f80000 ################################################################
10151 06:51:30.523437
10152 06:51:30.784154 01000000 ################################################################
10153 06:51:30.784324
10154 06:51:31.052443 01080000 ################################################################
10155 06:51:31.052580
10156 06:51:31.323795 01100000 ################################################################
10157 06:51:31.323930
10158 06:51:31.584175 01180000 ################################################################
10159 06:51:31.584348
10160 06:51:31.845590 01200000 ################################################################
10161 06:51:31.845753
10162 06:51:32.109558 01280000 ################################################################
10163 06:51:32.109704
10164 06:51:32.376033 01300000 ################################################################
10165 06:51:32.376195
10166 06:51:32.639687 01380000 ################################################################
10167 06:51:32.639868
10168 06:51:32.909591 01400000 ################################################################
10169 06:51:32.909729
10170 06:51:33.174756 01480000 ################################################################
10171 06:51:33.174903
10172 06:51:33.445056 01500000 ################################################################
10173 06:51:33.445203
10174 06:51:33.709374 01580000 ################################################################
10175 06:51:33.709521
10176 06:51:33.979834 01600000 ################################################################
10177 06:51:33.980009
10178 06:51:34.254072 01680000 ################################################################
10179 06:51:34.254217
10180 06:51:34.520470 01700000 ################################################################
10181 06:51:34.520609
10182 06:51:34.779517 01780000 ################################################################
10183 06:51:34.779727
10184 06:51:35.037990 01800000 ################################################################
10185 06:51:35.038134
10186 06:51:35.313191 01880000 ################################################################
10187 06:51:35.313353
10188 06:51:35.579613 01900000 ################################################################
10189 06:51:35.579782
10190 06:51:35.841401 01980000 ################################################################
10191 06:51:35.841541
10192 06:51:36.104930 01a00000 ################################################################
10193 06:51:36.105119
10194 06:51:36.369640 01a80000 ################################################################
10195 06:51:36.369806
10196 06:51:36.636368 01b00000 ################################################################
10197 06:51:36.636501
10198 06:51:36.900898 01b80000 ################################################################
10199 06:51:36.901035
10200 06:51:37.169688 01c00000 ################################################################
10201 06:51:37.169845
10202 06:51:37.443281 01c80000 ################################################################
10203 06:51:37.443450
10204 06:51:37.710948 01d00000 ################################################################
10205 06:51:37.711115
10206 06:51:37.986831 01d80000 ################################################################
10207 06:51:37.986977
10208 06:51:38.261716 01e00000 ################################################################
10209 06:51:38.261852
10210 06:51:38.535307 01e80000 ################################################################
10211 06:51:38.535531
10212 06:51:38.801396 01f00000 ################################################################
10213 06:51:38.801528
10214 06:51:39.063980 01f80000 ################################################################
10215 06:51:39.064163
10216 06:51:39.323053 02000000 ################################################################
10217 06:51:39.323207
10218 06:51:39.583902 02080000 ################################################################
10219 06:51:39.584041
10220 06:51:39.852397 02100000 ################################################################
10221 06:51:39.852536
10222 06:51:40.120547 02180000 ################################################################
10223 06:51:40.120688
10224 06:51:40.397687 02200000 ################################################################
10225 06:51:40.397824
10226 06:51:40.667067 02280000 ################################################################
10227 06:51:40.667206
10228 06:51:40.939580 02300000 ################################################################
10229 06:51:40.939718
10230 06:51:41.196410 02380000 ################################################################
10231 06:51:41.196545
10232 06:51:41.454575 02400000 ################################################################
10233 06:51:41.454741
10234 06:51:41.718589 02480000 ################################################################
10235 06:51:41.718853
10236 06:51:41.978538 02500000 ################################################################
10237 06:51:41.978679
10238 06:51:42.237805 02580000 ################################################################
10239 06:51:42.237941
10240 06:51:42.520877 02600000 ################################################################
10241 06:51:42.521016
10242 06:51:42.829490 02680000 ################################################################
10243 06:51:42.829661
10244 06:51:43.087341 02700000 ################################################################
10245 06:51:43.087491
10246 06:51:43.346698 02780000 ################################################################
10247 06:51:43.346845
10248 06:51:43.608580 02800000 ################################################################
10249 06:51:43.608723
10250 06:51:43.867046 02880000 ################################################################
10251 06:51:43.867189
10252 06:51:44.129215 02900000 ################################################################
10253 06:51:44.129361
10254 06:51:44.385357 02980000 ################################################################
10255 06:51:44.385501
10256 06:51:44.641728 02a00000 ################################################################
10257 06:51:44.641885
10258 06:51:44.898692 02a80000 ################################################################
10259 06:51:44.898831
10260 06:51:45.171484 02b00000 ################################################################
10261 06:51:45.171632
10262 06:51:45.435067 02b80000 ################################################################
10263 06:51:45.435235
10264 06:51:45.694357 02c00000 ################################################################
10265 06:51:45.694501
10266 06:51:45.966378 02c80000 ################################################################
10267 06:51:45.966525
10268 06:51:46.233690 02d00000 ################################################################
10269 06:51:46.233863
10270 06:51:46.491123 02d80000 ################################################################
10271 06:51:46.491272
10272 06:51:46.751704 02e00000 ################################################################
10273 06:51:46.751895
10274 06:51:47.016135 02e80000 ################################################################
10275 06:51:47.016309
10276 06:51:47.273590 02f00000 ################################################################
10277 06:51:47.273734
10278 06:51:47.539553 02f80000 ################################################################
10279 06:51:47.539690
10280 06:51:47.797600 03000000 ################################################################
10281 06:51:47.797736
10282 06:51:48.054108 03080000 ################################################################
10283 06:51:48.054241
10284 06:51:48.095639 03100000 ########## done.
10285 06:51:48.095760
10286 06:51:48.098833 The bootfile was 51459754 bytes long.
10287 06:51:48.098919
10288 06:51:48.098985 Sending tftp read request... done.
10289 06:51:48.099047
10290 06:51:48.102033 Waiting for the transfer...
10291 06:51:48.102118
10292 06:51:48.105213 00000000 # done.
10293 06:51:48.105313
10294 06:51:48.111850 Command line loaded dynamically from TFTP file: 12694793/tftp-deploy-3scfsdto/kernel/cmdline
10295 06:51:48.111936
10296 06:51:48.125495 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10297 06:51:48.125582
10298 06:51:48.128603 Loading FIT.
10299 06:51:48.128723
10300 06:51:48.131726 Image ramdisk-1 has 39359858 bytes.
10301 06:51:48.131834
10302 06:51:48.131928 Image fdt-1 has 47278 bytes.
10303 06:51:48.132018
10304 06:51:48.135091 Image kernel-1 has 12050581 bytes.
10305 06:51:48.135173
10306 06:51:48.145248 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10307 06:51:48.145332
10308 06:51:48.161887 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10309 06:51:48.161976
10310 06:51:48.168472 Choosing best match conf-1 for compat google,spherion-rev2.
10311 06:51:48.172275
10312 06:51:48.176972 Connected to device vid:did:rid of 1ae0:0028:00
10313 06:51:48.184765
10314 06:51:48.188097 tpm_get_response: command 0x17b, return code 0x0
10315 06:51:48.188182
10316 06:51:48.191549 ec_init: CrosEC protocol v3 supported (256, 248)
10317 06:51:48.195501
10318 06:51:48.198815 tpm_cleanup: add release locality here.
10319 06:51:48.198899
10320 06:51:48.198983 Shutting down all USB controllers.
10321 06:51:48.202141
10322 06:51:48.202224 Removing current net device
10323 06:51:48.202309
10324 06:51:48.208699 Exiting depthcharge with code 4 at timestamp: 64871257
10325 06:51:48.208782
10326 06:51:48.212116 LZMA decompressing kernel-1 to 0x821a6718
10327 06:51:48.212200
10328 06:51:48.215220 LZMA decompressing kernel-1 to 0x40000000
10329 06:51:49.714409
10330 06:51:49.714544 jumping to kernel
10331 06:51:49.715194 end: 2.2.4 bootloader-commands (duration 00:00:37) [common]
10332 06:51:49.715331 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10333 06:51:49.715442 Setting prompt string to ['Linux version [0-9]']
10334 06:51:49.715527 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10335 06:51:49.715610 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10336 06:51:49.796505
10337 06:51:49.799606 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10338 06:51:49.802885 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10339 06:51:49.803046 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10340 06:51:49.803119 Setting prompt string to []
10341 06:51:49.803201 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10342 06:51:49.803276 Using line separator: #'\n'#
10343 06:51:49.803337 No login prompt set.
10344 06:51:49.803400 Parsing kernel messages
10345 06:51:49.803455 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10346 06:51:49.803554 [login-action] Waiting for messages, (timeout 00:03:48)
10347 06:51:49.822759 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10348 06:51:49.825924 [ 0.000000] random: crng init done
10349 06:51:49.833016 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10350 06:51:49.836218 [ 0.000000] efi: UEFI not found.
10351 06:51:49.842907 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10352 06:51:49.849187 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10353 06:51:49.859539 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10354 06:51:49.869206 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10355 06:51:49.876081 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10356 06:51:49.882254 [ 0.000000] printk: bootconsole [mtk8250] enabled
10357 06:51:49.889193 [ 0.000000] NUMA: No NUMA configuration found
10358 06:51:49.895586 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10359 06:51:49.899006 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10360 06:51:49.902395 [ 0.000000] Zone ranges:
10361 06:51:49.909100 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10362 06:51:49.912446 [ 0.000000] DMA32 empty
10363 06:51:49.918707 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10364 06:51:49.921828 [ 0.000000] Movable zone start for each node
10365 06:51:49.925069 [ 0.000000] Early memory node ranges
10366 06:51:49.931930 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10367 06:51:49.938632 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10368 06:51:49.945076 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10369 06:51:49.951706 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10370 06:51:49.955382 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10371 06:51:49.965080 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10372 06:51:50.020977 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10373 06:51:50.027268 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10374 06:51:50.033538 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10375 06:51:50.036864 [ 0.000000] psci: probing for conduit method from DT.
10376 06:51:50.043551 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10377 06:51:50.046810 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10378 06:51:50.053585 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10379 06:51:50.056882 [ 0.000000] psci: SMC Calling Convention v1.2
10380 06:51:50.063507 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10381 06:51:50.066896 [ 0.000000] Detected VIPT I-cache on CPU0
10382 06:51:50.073599 [ 0.000000] CPU features: detected: GIC system register CPU interface
10383 06:51:50.080253 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10384 06:51:50.086644 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10385 06:51:50.093407 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10386 06:51:50.103544 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10387 06:51:50.109854 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10388 06:51:50.113331 [ 0.000000] alternatives: applying boot alternatives
10389 06:51:50.120075 [ 0.000000] Fallback order for Node 0: 0
10390 06:51:50.126533 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10391 06:51:50.129925 [ 0.000000] Policy zone: Normal
10392 06:51:50.142819 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10393 06:51:50.152503 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10394 06:51:50.164769 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10395 06:51:50.174900 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10396 06:51:50.181651 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10397 06:51:50.185187 <6>[ 0.000000] software IO TLB: area num 8.
10398 06:51:50.241228 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10399 06:51:50.390438 <6>[ 0.000000] Memory: 7928816K/8385536K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 423952K reserved, 32768K cma-reserved)
10400 06:51:50.397156 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10401 06:51:50.403902 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10402 06:51:50.407561 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10403 06:51:50.413834 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10404 06:51:50.420646 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10405 06:51:50.423457 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10406 06:51:50.433989 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10407 06:51:50.440246 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10408 06:51:50.443526 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10409 06:51:50.451437 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10410 06:51:50.454861 <6>[ 0.000000] GICv3: 608 SPIs implemented
10411 06:51:50.461692 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10412 06:51:50.464953 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10413 06:51:50.468231 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10414 06:51:50.478391 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10415 06:51:50.487845 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10416 06:51:50.501509 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10417 06:51:50.507490 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10418 06:51:50.516835 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10419 06:51:50.530111 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10420 06:51:50.536501 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10421 06:51:50.543594 <6>[ 0.009181] Console: colour dummy device 80x25
10422 06:51:50.553732 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10423 06:51:50.560258 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10424 06:51:50.563712 <6>[ 0.029286] LSM: Security Framework initializing
10425 06:51:50.570391 <6>[ 0.034225] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10426 06:51:50.579984 <6>[ 0.042039] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10427 06:51:50.586423 <6>[ 0.051479] cblist_init_generic: Setting adjustable number of callback queues.
10428 06:51:50.593042 <6>[ 0.058924] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 06:51:50.603274 <6>[ 0.065264] cblist_init_generic: Setting adjustable number of callback queues.
10430 06:51:50.609949 <6>[ 0.072737] cblist_init_generic: Setting shift to 3 and lim to 1.
10431 06:51:50.613292 <6>[ 0.079138] rcu: Hierarchical SRCU implementation.
10432 06:51:50.619978 <6>[ 0.084160] rcu: Max phase no-delay instances is 1000.
10433 06:51:50.626137 <6>[ 0.091191] EFI services will not be available.
10434 06:51:50.629629 <6>[ 0.096147] smp: Bringing up secondary CPUs ...
10435 06:51:50.637724 <6>[ 0.101202] Detected VIPT I-cache on CPU1
10436 06:51:50.644442 <6>[ 0.101270] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10437 06:51:50.651050 <6>[ 0.101302] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10438 06:51:50.654178 <6>[ 0.101639] Detected VIPT I-cache on CPU2
10439 06:51:50.661082 <6>[ 0.101685] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10440 06:51:50.667638 <6>[ 0.101701] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10441 06:51:50.674213 <6>[ 0.101958] Detected VIPT I-cache on CPU3
10442 06:51:50.680630 <6>[ 0.102004] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10443 06:51:50.687480 <6>[ 0.102018] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10444 06:51:50.691003 <6>[ 0.102324] CPU features: detected: Spectre-v4
10445 06:51:50.697286 <6>[ 0.102331] CPU features: detected: Spectre-BHB
10446 06:51:50.700631 <6>[ 0.102336] Detected PIPT I-cache on CPU4
10447 06:51:50.707352 <6>[ 0.102385] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10448 06:51:50.713575 <6>[ 0.102400] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10449 06:51:50.720271 <6>[ 0.102678] Detected PIPT I-cache on CPU5
10450 06:51:50.727232 <6>[ 0.102733] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10451 06:51:50.733885 <6>[ 0.102749] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10452 06:51:50.737346 <6>[ 0.103026] Detected PIPT I-cache on CPU6
10453 06:51:50.743638 <6>[ 0.103090] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10454 06:51:50.750424 <6>[ 0.103106] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10455 06:51:50.756820 <6>[ 0.103405] Detected PIPT I-cache on CPU7
10456 06:51:50.763645 <6>[ 0.103469] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10457 06:51:50.770045 <6>[ 0.103486] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10458 06:51:50.773650 <6>[ 0.103532] smp: Brought up 1 node, 8 CPUs
10459 06:51:50.779837 <6>[ 0.244885] SMP: Total of 8 processors activated.
10460 06:51:50.783562 <6>[ 0.249806] CPU features: detected: 32-bit EL0 Support
10461 06:51:50.793490 <6>[ 0.255201] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10462 06:51:50.800118 <6>[ 0.264002] CPU features: detected: Common not Private translations
10463 06:51:50.806367 <6>[ 0.270517] CPU features: detected: CRC32 instructions
10464 06:51:50.809933 <6>[ 0.275868] CPU features: detected: RCpc load-acquire (LDAPR)
10465 06:51:50.816157 <6>[ 0.281829] CPU features: detected: LSE atomic instructions
10466 06:51:50.822813 <6>[ 0.287646] CPU features: detected: Privileged Access Never
10467 06:51:50.829660 <6>[ 0.293425] CPU features: detected: RAS Extension Support
10468 06:51:50.836497 <6>[ 0.299035] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10469 06:51:50.839245 <6>[ 0.306253] CPU: All CPU(s) started at EL2
10470 06:51:50.846105 <6>[ 0.310570] alternatives: applying system-wide alternatives
10471 06:51:50.855164 <6>[ 0.321284] devtmpfs: initialized
10472 06:51:50.871232 <6>[ 0.330233] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10473 06:51:50.877345 <6>[ 0.340192] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10474 06:51:50.884532 <6>[ 0.348440] pinctrl core: initialized pinctrl subsystem
10475 06:51:50.887726 <6>[ 0.355089] DMI not present or invalid.
10476 06:51:50.894102 <6>[ 0.359497] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10477 06:51:50.903753 <6>[ 0.366366] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10478 06:51:50.911076 <6>[ 0.373949] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10479 06:51:50.920774 <6>[ 0.382177] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10480 06:51:50.924097 <6>[ 0.390416] audit: initializing netlink subsys (disabled)
10481 06:51:50.933548 <5>[ 0.396108] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10482 06:51:50.940222 <6>[ 0.396807] thermal_sys: Registered thermal governor 'step_wise'
10483 06:51:50.947181 <6>[ 0.404076] thermal_sys: Registered thermal governor 'power_allocator'
10484 06:51:50.950664 <6>[ 0.410329] cpuidle: using governor menu
10485 06:51:50.956859 <6>[ 0.421293] NET: Registered PF_QIPCRTR protocol family
10486 06:51:50.963528 <6>[ 0.426766] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10487 06:51:50.970457 <6>[ 0.433868] ASID allocator initialised with 32768 entries
10488 06:51:50.973581 <6>[ 0.440427] Serial: AMBA PL011 UART driver
10489 06:51:50.983683 <4>[ 0.449215] Trying to register duplicate clock ID: 134
10490 06:51:51.037210 <6>[ 0.506293] KASLR enabled
10491 06:51:51.051464 <6>[ 0.513920] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10492 06:51:51.058540 <6>[ 0.520932] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10493 06:51:51.064679 <6>[ 0.527420] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10494 06:51:51.071220 <6>[ 0.534427] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10495 06:51:51.077980 <6>[ 0.540911] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10496 06:51:51.084501 <6>[ 0.547918] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10497 06:51:51.091505 <6>[ 0.554401] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10498 06:51:51.097916 <6>[ 0.561407] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10499 06:51:51.101147 <6>[ 0.568857] ACPI: Interpreter disabled.
10500 06:51:51.109744 <6>[ 0.575299] iommu: Default domain type: Translated
10501 06:51:51.115760 <6>[ 0.580409] iommu: DMA domain TLB invalidation policy: strict mode
10502 06:51:51.119537 <5>[ 0.587069] SCSI subsystem initialized
10503 06:51:51.125694 <6>[ 0.591314] usbcore: registered new interface driver usbfs
10504 06:51:51.132597 <6>[ 0.597044] usbcore: registered new interface driver hub
10505 06:51:51.135785 <6>[ 0.602597] usbcore: registered new device driver usb
10506 06:51:51.143285 <6>[ 0.608716] pps_core: LinuxPPS API ver. 1 registered
10507 06:51:51.152652 <6>[ 0.613907] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10508 06:51:51.156163 <6>[ 0.623247] PTP clock support registered
10509 06:51:51.159331 <6>[ 0.627488] EDAC MC: Ver: 3.0.0
10510 06:51:51.166871 <6>[ 0.632673] FPGA manager framework
10511 06:51:51.173476 <6>[ 0.636347] Advanced Linux Sound Architecture Driver Initialized.
10512 06:51:51.177082 <6>[ 0.643118] vgaarb: loaded
10513 06:51:51.183254 <6>[ 0.646250] clocksource: Switched to clocksource arch_sys_counter
10514 06:51:51.186589 <5>[ 0.652699] VFS: Disk quotas dquot_6.6.0
10515 06:51:51.193148 <6>[ 0.656886] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10516 06:51:51.196686 <6>[ 0.664077] pnp: PnP ACPI: disabled
10517 06:51:51.204841 <6>[ 0.670749] NET: Registered PF_INET protocol family
10518 06:51:51.215143 <6>[ 0.676339] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10519 06:51:51.226646 <6>[ 0.688671] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10520 06:51:51.236652 <6>[ 0.697487] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10521 06:51:51.243032 <6>[ 0.705454] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10522 06:51:51.249341 <6>[ 0.714154] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10523 06:51:51.261498 <6>[ 0.723871] TCP: Hash tables configured (established 65536 bind 65536)
10524 06:51:51.267812 <6>[ 0.730744] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10525 06:51:51.274708 <6>[ 0.737939] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10526 06:51:51.280907 <6>[ 0.745641] NET: Registered PF_UNIX/PF_LOCAL protocol family
10527 06:51:51.287742 <6>[ 0.751788] RPC: Registered named UNIX socket transport module.
10528 06:51:51.291218 <6>[ 0.757943] RPC: Registered udp transport module.
10529 06:51:51.297830 <6>[ 0.762876] RPC: Registered tcp transport module.
10530 06:51:51.304600 <6>[ 0.767808] RPC: Registered tcp NFSv4.1 backchannel transport module.
10531 06:51:51.307958 <6>[ 0.774471] PCI: CLS 0 bytes, default 64
10532 06:51:51.311277 <6>[ 0.778822] Unpacking initramfs...
10533 06:51:51.335947 <6>[ 0.798367] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10534 06:51:51.345892 <6>[ 0.807009] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10535 06:51:51.349136 <6>[ 0.815854] kvm [1]: IPA Size Limit: 40 bits
10536 06:51:51.355649 <6>[ 0.820382] kvm [1]: GICv3: no GICV resource entry
10537 06:51:51.358897 <6>[ 0.825402] kvm [1]: disabling GICv2 emulation
10538 06:51:51.365649 <6>[ 0.830084] kvm [1]: GIC system register CPU interface enabled
10539 06:51:51.369005 <6>[ 0.836242] kvm [1]: vgic interrupt IRQ18
10540 06:51:51.375663 <6>[ 0.840594] kvm [1]: VHE mode initialized successfully
10541 06:51:51.382074 <5>[ 0.847071] Initialise system trusted keyrings
10542 06:51:51.388846 <6>[ 0.851906] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10543 06:51:51.395907 <6>[ 0.861864] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10544 06:51:51.403206 <5>[ 0.868249] NFS: Registering the id_resolver key type
10545 06:51:51.405888 <5>[ 0.873544] Key type id_resolver registered
10546 06:51:51.412590 <5>[ 0.877961] Key type id_legacy registered
10547 06:51:51.419434 <6>[ 0.882254] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10548 06:51:51.426229 <6>[ 0.889175] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10549 06:51:51.432088 <6>[ 0.896894] 9p: Installing v9fs 9p2000 file system support
10550 06:51:51.468514 <5>[ 0.934106] Key type asymmetric registered
10551 06:51:51.472013 <5>[ 0.938437] Asymmetric key parser 'x509' registered
10552 06:51:51.481587 <6>[ 0.943574] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10553 06:51:51.484712 <6>[ 0.951189] io scheduler mq-deadline registered
10554 06:51:51.488269 <6>[ 0.955949] io scheduler kyber registered
10555 06:51:51.506883 <6>[ 0.972944] EINJ: ACPI disabled.
10556 06:51:51.539284 <4>[ 0.998217] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 06:51:51.548748 <4>[ 1.008868] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10558 06:51:51.564181 <6>[ 1.029650] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10559 06:51:51.571708 <6>[ 1.037635] printk: console [ttyS0] disabled
10560 06:51:51.599869 <6>[ 1.062268] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10561 06:51:51.606736 <6>[ 1.071741] printk: console [ttyS0] enabled
10562 06:51:51.609982 <6>[ 1.071741] printk: console [ttyS0] enabled
10563 06:51:51.616749 <6>[ 1.080649] printk: bootconsole [mtk8250] disabled
10564 06:51:51.619908 <6>[ 1.080649] printk: bootconsole [mtk8250] disabled
10565 06:51:51.626269 <6>[ 1.091812] SuperH (H)SCI(F) driver initialized
10566 06:51:51.629298 <6>[ 1.097096] msm_serial: driver initialized
10567 06:51:51.643343 <6>[ 1.106046] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10568 06:51:51.653568 <6>[ 1.114596] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10569 06:51:51.660267 <6>[ 1.123139] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10570 06:51:51.670320 <6>[ 1.131768] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10571 06:51:51.679947 <6>[ 1.140474] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10572 06:51:51.686651 <6>[ 1.149195] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10573 06:51:51.696641 <6>[ 1.157737] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10574 06:51:51.703737 <6>[ 1.166544] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10575 06:51:51.713165 <6>[ 1.175094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10576 06:51:51.725071 <6>[ 1.190810] loop: module loaded
10577 06:51:51.731403 <6>[ 1.196741] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10578 06:51:51.754216 <4>[ 1.220214] mtk-pmic-keys: Failed to locate of_node [id: -1]
10579 06:51:51.761160 <6>[ 1.227077] megasas: 07.719.03.00-rc1
10580 06:51:51.770834 <6>[ 1.236675] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10581 06:51:51.783834 <6>[ 1.249644] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10582 06:51:51.800872 <6>[ 1.266467] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10583 06:51:51.857681 <6>[ 1.316822] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10584 06:51:52.904762 <6>[ 2.370499] Freeing initrd memory: 38436K
10585 06:51:52.915313 <6>[ 2.381091] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10586 06:51:52.926729 <6>[ 2.392001] tun: Universal TUN/TAP device driver, 1.6
10587 06:51:52.930166 <6>[ 2.398060] thunder_xcv, ver 1.0
10588 06:51:52.932721 <6>[ 2.401564] thunder_bgx, ver 1.0
10589 06:51:52.936259 <6>[ 2.405059] nicpf, ver 1.0
10590 06:51:52.946455 <6>[ 2.409062] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10591 06:51:52.950604 <6>[ 2.416537] hns3: Copyright (c) 2017 Huawei Corporation.
10592 06:51:52.956719 <6>[ 2.422124] hclge is initializing
10593 06:51:52.960204 <6>[ 2.425704] e1000: Intel(R) PRO/1000 Network Driver
10594 06:51:52.967391 <6>[ 2.430833] e1000: Copyright (c) 1999-2006 Intel Corporation.
10595 06:51:52.970794 <6>[ 2.436845] e1000e: Intel(R) PRO/1000 Network Driver
10596 06:51:52.977000 <6>[ 2.442060] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10597 06:51:52.983043 <6>[ 2.448248] igb: Intel(R) Gigabit Ethernet Network Driver
10598 06:51:52.989455 <6>[ 2.453898] igb: Copyright (c) 2007-2014 Intel Corporation.
10599 06:51:52.996194 <6>[ 2.459734] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10600 06:51:53.003012 <6>[ 2.466252] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10601 06:51:53.006404 <6>[ 2.472714] sky2: driver version 1.30
10602 06:51:53.012863 <6>[ 2.477702] VFIO - User Level meta-driver version: 0.3
10603 06:51:53.019917 <6>[ 2.485936] usbcore: registered new interface driver usb-storage
10604 06:51:53.027156 <6>[ 2.492384] usbcore: registered new device driver onboard-usb-hub
10605 06:51:53.036114 <6>[ 2.501493] mt6397-rtc mt6359-rtc: registered as rtc0
10606 06:51:53.046404 <6>[ 2.506955] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:49:13 UTC (1706942953)
10607 06:51:53.049083 <6>[ 2.516511] i2c_dev: i2c /dev entries driver
10608 06:51:53.066218 <6>[ 2.528144] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10609 06:51:53.085892 <6>[ 2.551141] cpu cpu0: EM: created perf domain
10610 06:51:53.088960 <6>[ 2.556064] cpu cpu4: EM: created perf domain
10611 06:51:53.096842 <6>[ 2.561638] sdhci: Secure Digital Host Controller Interface driver
10612 06:51:53.102533 <6>[ 2.568071] sdhci: Copyright(c) Pierre Ossman
10613 06:51:53.109226 <6>[ 2.573026] Synopsys Designware Multimedia Card Interface Driver
10614 06:51:53.115848 <6>[ 2.579655] sdhci-pltfm: SDHCI platform and OF driver helper
10615 06:51:53.120002 <6>[ 2.579784] mmc0: CQHCI version 5.10
10616 06:51:53.125831 <6>[ 2.589732] ledtrig-cpu: registered to indicate activity on CPUs
10617 06:51:53.132835 <6>[ 2.596779] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10618 06:51:53.139423 <6>[ 2.603833] usbcore: registered new interface driver usbhid
10619 06:51:53.142885 <6>[ 2.609654] usbhid: USB HID core driver
10620 06:51:53.149801 <6>[ 2.613864] spi_master spi0: will run message pump with realtime priority
10621 06:51:53.193147 <6>[ 2.652049] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10622 06:51:53.208607 <6>[ 2.667216] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10623 06:51:53.216680 <6>[ 2.681705] mmc0: Command Queue Engine enabled
10624 06:51:53.223147 <6>[ 2.686450] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10625 06:51:53.229960 <6>[ 2.693171] cros-ec-spi spi0.0: Chrome EC device registered
10626 06:51:53.233597 <6>[ 2.693748] mmcblk0: mmc0:0001 DA4128 116 GiB
10627 06:51:53.244853 <6>[ 2.710033] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10628 06:51:53.251582 <6>[ 2.716905] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10629 06:51:53.258350 <6>[ 2.723103] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10630 06:51:53.264972 <6>[ 2.729344] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10631 06:51:53.274997 <6>[ 2.729453] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10632 06:51:53.281663 <6>[ 2.746518] NET: Registered PF_PACKET protocol family
10633 06:51:53.284964 <6>[ 2.751918] 9pnet: Installing 9P2000 support
10634 06:51:53.291678 <5>[ 2.756484] Key type dns_resolver registered
10635 06:51:53.294898 <6>[ 2.761459] registered taskstats version 1
10636 06:51:53.301060 <5>[ 2.765850] Loading compiled-in X.509 certificates
10637 06:51:53.331623 <4>[ 2.790343] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10638 06:51:53.341670 <4>[ 2.801308] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10639 06:51:53.348435 <3>[ 2.811860] debugfs: File 'uA_load' in directory '/' already present!
10640 06:51:53.355406 <3>[ 2.818580] debugfs: File 'min_uV' in directory '/' already present!
10641 06:51:53.361864 <3>[ 2.825211] debugfs: File 'max_uV' in directory '/' already present!
10642 06:51:53.368258 <3>[ 2.831824] debugfs: File 'constraint_flags' in directory '/' already present!
10643 06:51:53.379293 <3>[ 2.841506] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10644 06:51:53.388328 <6>[ 2.853971] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10645 06:51:53.396033 <6>[ 2.860741] xhci-mtk 11200000.usb: xHCI Host Controller
10646 06:51:53.402378 <6>[ 2.866249] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10647 06:51:53.412086 <6>[ 2.874074] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10648 06:51:53.418300 <6>[ 2.883493] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10649 06:51:53.425396 <6>[ 2.889543] xhci-mtk 11200000.usb: xHCI Host Controller
10650 06:51:53.432376 <6>[ 2.895018] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10651 06:51:53.438102 <6>[ 2.902664] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10652 06:51:53.444783 <6>[ 2.910314] hub 1-0:1.0: USB hub found
10653 06:51:53.448033 <6>[ 2.914324] hub 1-0:1.0: 1 port detected
10654 06:51:53.454911 <6>[ 2.918588] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10655 06:51:53.461322 <6>[ 2.927121] hub 2-0:1.0: USB hub found
10656 06:51:53.464666 <6>[ 2.931125] hub 2-0:1.0: 1 port detected
10657 06:51:53.473562 <6>[ 2.938834] mtk-msdc 11f70000.mmc: Got CD GPIO
10658 06:51:53.484384 <6>[ 2.946227] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10659 06:51:53.491502 <6>[ 2.954306] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10660 06:51:53.500653 <4>[ 2.962229] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10661 06:51:53.510677 <6>[ 2.971758] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10662 06:51:53.517614 <6>[ 2.979834] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10663 06:51:53.524201 <6>[ 2.987972] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10664 06:51:53.533916 <6>[ 2.995915] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10665 06:51:53.540235 <6>[ 3.003739] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10666 06:51:53.550748 <6>[ 3.011556] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10667 06:51:53.560584 <6>[ 3.022027] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10668 06:51:53.567010 <6>[ 3.030410] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10669 06:51:53.576500 <6>[ 3.038749] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10670 06:51:53.583630 <6>[ 3.047089] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10671 06:51:53.593725 <6>[ 3.055427] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10672 06:51:53.600201 <6>[ 3.063766] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10673 06:51:53.609901 <6>[ 3.072105] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10674 06:51:53.619717 <6>[ 3.080459] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10675 06:51:53.626680 <6>[ 3.088799] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10676 06:51:53.636707 <6>[ 3.097138] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10677 06:51:53.643502 <6>[ 3.105476] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10678 06:51:53.653557 <6>[ 3.113814] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10679 06:51:53.659653 <6>[ 3.122153] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10680 06:51:53.669814 <6>[ 3.130493] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10681 06:51:53.676107 <6>[ 3.138833] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10682 06:51:53.683440 <6>[ 3.147572] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10683 06:51:53.689674 <6>[ 3.154734] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10684 06:51:53.696407 <6>[ 3.161482] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10685 06:51:53.706078 <6>[ 3.168239] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10686 06:51:53.712752 <6>[ 3.175169] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10687 06:51:53.719658 <6>[ 3.182018] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10688 06:51:53.729572 <6>[ 3.191146] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10689 06:51:53.738971 <6>[ 3.200264] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10690 06:51:53.748939 <6>[ 3.209558] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10691 06:51:53.758810 <6>[ 3.219025] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10692 06:51:53.765547 <6>[ 3.228492] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10693 06:51:53.775945 <6>[ 3.237611] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10694 06:51:53.786105 <6>[ 3.247079] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10695 06:51:53.796033 <6>[ 3.256197] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10696 06:51:53.805439 <6>[ 3.265490] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10697 06:51:53.815561 <6>[ 3.275651] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10698 06:51:53.825415 <6>[ 3.287213] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10699 06:51:53.876241 <6>[ 3.338527] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10700 06:51:54.031369 <6>[ 3.496649] hub 1-1:1.0: USB hub found
10701 06:51:54.034166 <6>[ 3.501162] hub 1-1:1.0: 4 ports detected
10702 06:51:54.043959 <6>[ 3.509717] hub 1-1:1.0: USB hub found
10703 06:51:54.047169 <6>[ 3.514041] hub 1-1:1.0: 4 ports detected
10704 06:51:54.156472 <6>[ 3.618866] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10705 06:51:54.183203 <6>[ 3.648371] hub 2-1:1.0: USB hub found
10706 06:51:54.186349 <6>[ 3.652868] hub 2-1:1.0: 3 ports detected
10707 06:51:54.195871 <6>[ 3.660967] hub 2-1:1.0: USB hub found
10708 06:51:54.199313 <6>[ 3.665414] hub 2-1:1.0: 3 ports detected
10709 06:51:54.372471 <6>[ 3.834551] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10710 06:51:54.503976 <6>[ 3.969370] hub 1-1.4:1.0: USB hub found
10711 06:51:54.507367 <6>[ 3.973894] hub 1-1.4:1.0: 2 ports detected
10712 06:51:54.515735 <6>[ 3.981133] hub 1-1.4:1.0: USB hub found
10713 06:51:54.519112 <6>[ 3.985650] hub 1-1.4:1.0: 2 ports detected
10714 06:51:54.588178 <6>[ 4.050703] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10715 06:51:54.816487 <6>[ 4.278568] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10716 06:51:55.008014 <6>[ 4.470552] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10717 06:52:06.097329 <6>[ 15.567554] ALSA device list:
10718 06:52:06.104199 <6>[ 15.570846] No soundcards found.
10719 06:52:06.112365 <6>[ 15.578857] Freeing unused kernel memory: 8448K
10720 06:52:06.114946 <6>[ 15.583855] Run /init as init process
10721 06:52:06.164796 <6>[ 15.631245] NET: Registered PF_INET6 protocol family
10722 06:52:06.170866 <6>[ 15.637963] Segment Routing with IPv6
10723 06:52:06.174959 <6>[ 15.641920] In-situ OAM (IOAM) with IPv6
10724 06:52:06.212426 <30>[ 15.659378] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10725 06:52:06.215808 <30>[ 15.683398] systemd[1]: Detected architecture arm64.
10726 06:52:06.219033
10727 06:52:06.222301 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10728 06:52:06.222826
10729 06:52:06.235839 <30>[ 15.702568] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10730 06:52:06.416022 <30>[ 15.879454] systemd[1]: Queued start job for default target Graphical Interface.
10731 06:52:06.456788 <30>[ 15.923449] systemd[1]: Created slice system-getty.slice.
10732 06:52:06.463348 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10733 06:52:06.480975 <30>[ 15.947251] systemd[1]: Created slice system-modprobe.slice.
10734 06:52:06.486727 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10735 06:52:06.504377 <30>[ 15.970858] systemd[1]: Created slice system-serial\x2dgetty.slice.
10736 06:52:06.513870 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10737 06:52:06.528572 <30>[ 15.995567] systemd[1]: Created slice User and Session Slice.
10738 06:52:06.535472 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10739 06:52:06.555479 <30>[ 16.019092] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10740 06:52:06.565490 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10741 06:52:06.583963 <30>[ 16.047138] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10742 06:52:06.590728 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10743 06:52:06.615266 <30>[ 16.074976] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10744 06:52:06.621148 <30>[ 16.087210] systemd[1]: Reached target Local Encrypted Volumes.
10745 06:52:06.627970 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10746 06:52:06.644203 <30>[ 16.111057] systemd[1]: Reached target Paths.
10747 06:52:06.647465 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10748 06:52:06.663672 <30>[ 16.130501] systemd[1]: Reached target Remote File Systems.
10749 06:52:06.670451 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10750 06:52:06.683688 <30>[ 16.150479] systemd[1]: Reached target Slices.
10751 06:52:06.687056 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10752 06:52:06.704355 <30>[ 16.170921] systemd[1]: Reached target Swap.
10753 06:52:06.707500 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10754 06:52:06.727187 <30>[ 16.190953] systemd[1]: Listening on initctl Compatibility Named Pipe.
10755 06:52:06.733962 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10756 06:52:06.749012 <30>[ 16.215916] systemd[1]: Listening on Journal Audit Socket.
10757 06:52:06.755581 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10758 06:52:06.773153 <30>[ 16.239612] systemd[1]: Listening on Journal Socket (/dev/log).
10759 06:52:06.779174 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10760 06:52:06.796240 <30>[ 16.262988] systemd[1]: Listening on Journal Socket.
10761 06:52:06.802837 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10762 06:52:06.819599 <30>[ 16.283158] systemd[1]: Listening on Network Service Netlink Socket.
10763 06:52:06.826031 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10764 06:52:06.840477 <30>[ 16.307693] systemd[1]: Listening on udev Control Socket.
10765 06:52:06.847307 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10766 06:52:06.864460 <30>[ 16.331518] systemd[1]: Listening on udev Kernel Socket.
10767 06:52:06.870997 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10768 06:52:06.911836 <30>[ 16.378601] systemd[1]: Mounting Huge Pages File System...
10769 06:52:06.918553 Mounting [0;1;39mHuge Pages File System[0m...
10770 06:52:06.933277 <30>[ 16.400028] systemd[1]: Mounting POSIX Message Queue File System...
10771 06:52:06.939749 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10772 06:52:06.957327 <30>[ 16.424293] systemd[1]: Mounting Kernel Debug File System...
10773 06:52:06.964094 Mounting [0;1;39mKernel Debug File System[0m...
10774 06:52:06.983043 <30>[ 16.446757] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10775 06:52:06.994715 <30>[ 16.458327] systemd[1]: Starting Create list of static device nodes for the current kernel...
10776 06:52:07.001337 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10777 06:52:07.023875 <30>[ 16.490842] systemd[1]: Starting Load Kernel Module configfs...
10778 06:52:07.030100 Starting [0;1;39mLoad Kernel Module configfs[0m...
10779 06:52:07.047930 <30>[ 16.514948] systemd[1]: Starting Load Kernel Module drm...
10780 06:52:07.054761 Starting [0;1;39mLoad Kernel Module drm[0m...
10781 06:52:07.071563 <30>[ 16.534923] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10782 06:52:07.108968 <30>[ 16.575292] systemd[1]: Starting Journal Service...
10783 06:52:07.114775 Starting [0;1;39mJournal Service[0m...
10784 06:52:07.132776 <30>[ 16.599292] systemd[1]: Starting Load Kernel Modules...
10785 06:52:07.139078 Starting [0;1;39mLoad Kernel Modules[0m...
10786 06:52:07.159655 <30>[ 16.623500] systemd[1]: Starting Remount Root and Kernel File Systems...
10787 06:52:07.166327 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10788 06:52:07.204786 <30>[ 16.671681] systemd[1]: Starting Coldplug All udev Devices...
10789 06:52:07.211036 Starting [0;1;39mColdplug All udev Devices[0m...
10790 06:52:07.230172 <30>[ 16.697349] systemd[1]: Started Journal Service.
10791 06:52:07.236992 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10792 06:52:07.252865 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10793 06:52:07.268046 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10794 06:52:07.284180 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10795 06:52:07.303889 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10796 06:52:07.326611 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10797 06:52:07.346839 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10798 06:52:07.365719 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10799 06:52:07.386168 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10800 06:52:07.400152 See 'systemctl status systemd-remount-fs.service' for details.
10801 06:52:07.440027 Mounting [0;1;39mKernel Configuration File System[0m...
10802 06:52:07.463975 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10803 06:52:07.486402 <46>[ 16.949922] systemd-journald[175]: Received client request to flush runtime journal.
10804 06:52:07.493102 Starting [0;1;39mLoad/Save Random Seed[0m...
10805 06:52:07.517033 Starting [0;1;39mApply Kernel Variables[0m...
10806 06:52:07.540654 Starting [0;1;39mCreate System Users[0m...
10807 06:52:07.565645 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10808 06:52:07.580510 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10809 06:52:07.601061 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10810 06:52:07.617449 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10811 06:52:07.633562 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10812 06:52:07.641869 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10813 06:52:07.679852 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10814 06:52:07.704687 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10815 06:52:07.720008 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10816 06:52:07.739298 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10817 06:52:07.794075 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10818 06:52:07.823760 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10819 06:52:07.846015 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10820 06:52:07.864469 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10821 06:52:07.922079 Starting [0;1;39mNetwork Service[0m...
10822 06:52:07.943642 Starting [0;1;39mNetwork Time Synchronization[0m...
10823 06:52:07.970730 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10824 06:52:07.992134 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10825 06:52:08.016696 <6>[ 17.480152] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10826 06:52:08.026656 [[0;32m OK [0m] Started [0;<6>[ 17.490640] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10827 06:52:08.036995 1;39mNetwork Tim<6>[ 17.499998] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10828 06:52:08.040109 e Synchronization[0m.
10829 06:52:08.054077 <6>[ 17.517798] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10830 06:52:08.065550 <6>[ 17.532932] usbcore: registered new device driver r8152-cfgselector
10831 06:52:08.075346 <6>[ 17.542177] remoteproc remoteproc0: scp is available
10832 06:52:08.082005 <6>[ 17.547524] remoteproc remoteproc0: powering up scp
10833 06:52:08.088752 <6>[ 17.552678] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10834 06:52:08.098075 [[0;32m OK [<4>[ 17.556629] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10835 06:52:08.105246 0m] Found device<6>[ 17.558353] mc: Linux media interface: v0.10
10836 06:52:08.108688 <6>[ 17.561126] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10837 06:52:08.112106 [0;1;39m/dev/ttyS0[0m.
10838 06:52:08.118726 <4>[ 17.583239] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10839 06:52:08.128626 <3>[ 17.586731] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 06:52:08.134808 <3>[ 17.599176] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10841 06:52:08.144883 <3>[ 17.607340] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10842 06:52:08.154824 [[0;32m OK [<3>[ 17.618010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 06:52:08.161687 <6>[ 17.619402] videodev: Linux video capture interface: v2.00
10844 06:52:08.168153 <3>[ 17.627489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10845 06:52:08.178226 0m] Created slic<3>[ 17.641232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10846 06:52:08.188169 e [0;1;39msyste<3>[ 17.650713] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10847 06:52:08.198140 <6>[ 17.659347] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10848 06:52:08.204888 <3>[ 17.660182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10849 06:52:08.215111 m-systemd\x2dbac<6>[ 17.661291] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10850 06:52:08.221278 klight.slice[0m<6>[ 17.661301] pci_bus 0000:00: root bus resource [bus 00-ff]
10851 06:52:08.228022 <6>[ 17.661309] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10852 06:52:08.228601 .
10853 06:52:08.237684 <6>[ 17.661316] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10854 06:52:08.244584 <6>[ 17.661360] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10855 06:52:08.254393 <6>[ 17.661381] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10856 06:52:08.257160 <6>[ 17.661463] pci 0000:00:00.0: supports D1 D2
10857 06:52:08.264233 <6>[ 17.661467] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10858 06:52:08.273776 <6>[ 17.679411] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10859 06:52:08.280911 <6>[ 17.686391] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10860 06:52:08.287745 <6>[ 17.686397] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10861 06:52:08.294065 <6>[ 17.686404] remoteproc remoteproc0: remote processor scp is now up
10862 06:52:08.304324 <6>[ 17.690759] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10863 06:52:08.310468 <3>[ 17.694064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10864 06:52:08.320475 <6>[ 17.700394] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10865 06:52:08.327512 <6>[ 17.701507] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10866 06:52:08.334505 <6>[ 17.727544] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10867 06:52:08.344450 <3>[ 17.728451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10868 06:52:08.350881 <3>[ 17.728468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 06:52:08.357931 <3>[ 17.728472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10870 06:52:08.368101 <6>[ 17.729546] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10871 06:52:08.374898 <6>[ 17.752047] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10872 06:52:08.384006 <3>[ 17.752154] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 06:52:08.391445 <3>[ 17.752181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 06:52:08.401044 <3>[ 17.752186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 06:52:08.407530 <3>[ 17.752192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 06:52:08.413961 <3>[ 17.752197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 06:52:08.424925 <6>[ 17.752590] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10878 06:52:08.431503 <3>[ 17.767289] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10879 06:52:08.438490 <6>[ 17.767680] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10880 06:52:08.448447 <4>[ 17.776358] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10881 06:52:08.451840 <4>[ 17.776358] Fallback method does not support PEC.
10882 06:52:08.458647 <6>[ 17.783996] pci 0000:01:00.0: supports D1 D2
10883 06:52:08.461969 <6>[ 17.785425] Bluetooth: Core ver 2.22
10884 06:52:08.465191 <6>[ 17.786050] NET: Registered PF_BLUETOOTH protocol family
10885 06:52:08.472574 <6>[ 17.786055] Bluetooth: HCI device and connection manager initialized
10886 06:52:08.478664 <6>[ 17.786087] Bluetooth: HCI socket layer initialized
10887 06:52:08.482134 <6>[ 17.786093] Bluetooth: L2CAP socket layer initialized
10888 06:52:08.489512 <6>[ 17.786110] Bluetooth: SCO socket layer initialized
10889 06:52:08.499778 <4>[ 17.804730] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10890 06:52:08.505745 <6>[ 17.807086] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10891 06:52:08.513242 <3>[ 17.817398] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 06:52:08.519857 <4>[ 17.823363] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10893 06:52:08.529960 <6>[ 17.824355] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10894 06:52:08.536880 <6>[ 17.835598] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10895 06:52:08.543412 <6>[ 17.839050] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10896 06:52:08.557249 <6>[ 17.859921] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10897 06:52:08.564232 <6>[ 17.863480] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10898 06:52:08.570997 <6>[ 17.863501] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10899 06:52:08.577911 <6>[ 17.883841] usbcore: registered new interface driver uvcvideo
10900 06:52:08.587948 <6>[ 17.888109] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10901 06:52:08.598597 <4>[ 17.890675] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10902 06:52:08.601843 <3>[ 17.890683] Bluetooth: hci0: Failed to load firmware file (-2)
10903 06:52:08.608044 <3>[ 17.890686] Bluetooth: hci0: Failed to set up firmware (-2)
10904 06:52:08.618266 <4>[ 17.890689] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10905 06:52:08.624863 <6>[ 17.895833] r8152 2-1.3:1.0 eth0: v1.12.13
10906 06:52:08.628402 <6>[ 17.901358] usbcore: registered new interface driver btusb
10907 06:52:08.638222 <6>[ 17.903377] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10908 06:52:08.641400 <6>[ 17.903407] pci 0000:00:00.0: PCI bridge to [bus 01]
10909 06:52:08.651787 <6>[ 17.903419] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10910 06:52:08.654976 <6>[ 17.908232] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10911 06:52:08.664925 <3>[ 17.912095] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 06:52:08.676096 <3>[ 17.912734] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10913 06:52:08.679587 <6>[ 17.917028] usbcore: registered new interface driver r8152
10914 06:52:08.686354 <6>[ 17.932171] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10915 06:52:08.692845 <6>[ 17.941714] usbcore: registered new interface driver cdc_ether
10916 06:52:08.700712 <3>[ 17.942573] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 06:52:08.707371 <6>[ 17.944735] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10918 06:52:08.713185 <6>[ 17.945193] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10919 06:52:08.720680 <3>[ 17.946147] power_supply sbs-5-000b: driver failed to report `status' property: -6
10920 06:52:08.731094 <6>[ 17.947995] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10921 06:52:08.733800 <6>[ 17.956257] usbcore: registered new interface driver r8153_ecm
10922 06:52:08.744272 <6>[ 17.957073] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10923 06:52:08.750876 <5>[ 17.962846] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10924 06:52:08.760589 <3>[ 17.965907] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 06:52:08.770542 <3>[ 17.987286] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 06:52:08.776987 <6>[ 17.992362] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10927 06:52:08.784003 <5>[ 18.005442] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10928 06:52:08.790734 <3>[ 18.028749] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 06:52:08.799908 <5>[ 18.036558] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10930 06:52:08.806947 <3>[ 18.064904] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 06:52:08.816693 <4>[ 18.069659] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10932 06:52:08.826893 <3>[ 18.098148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 06:52:08.830186 <6>[ 18.101244] cfg80211: failed to load regulatory.db
10934 06:52:08.836956 <6>[ 18.192050] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10935 06:52:08.843513 <6>[ 18.310573] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10936 06:52:08.850249 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10937 06:52:08.871351 [[0;32m OK [0m] Reached targ<6>[ 18.337363] mt7921e 0000:01:00.0: ASIC revision: 79610010
10938 06:52:08.874537 et [0;1;39mSystem Time Synchronized[0m.
10939 06:52:08.922988 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10940 06:52:08.940009 Starting [0;1;39mNetwork Name Resolution[0m...
10941 06:52:08.964263 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10942 06:52:08.974587 <6>[ 18.438851] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10943 06:52:08.978647 <6>[ 18.438851]
10944 06:52:08.988690 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10945 06:52:09.025585 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10946 06:52:09.180209 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10947 06:52:09.195563 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10948 06:52:09.214926 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10949 06:52:09.231909 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10950 06:52:09.245348 <6>[ 18.708954] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10951 06:52:09.251847 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10952 06:52:09.274652 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10953 06:52:09.291818 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10954 06:52:09.311837 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10955 06:52:09.327672 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10956 06:52:09.343799 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10957 06:52:09.363113 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10958 06:52:09.392912 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10959 06:52:09.425484 Starting [0;1;39mUser Login Management[0m...
10960 06:52:09.443504 Starting [0;1;39mPermit User Sessions[0m...
10961 06:52:09.465595 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10962 06:52:09.481365 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10963 06:52:09.496589 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10964 06:52:09.513081 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10965 06:52:09.580934 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10966 06:52:09.601454 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10967 06:52:09.621063 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10968 06:52:09.636352 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10969 06:52:09.652182 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10970 06:52:09.708759 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10971 06:52:09.743275 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10972 06:52:09.783465
10973 06:52:09.784016
10974 06:52:09.787131 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10975 06:52:09.787597
10976 06:52:09.790731 debian-bullseye-arm64 login: root (automatic login)
10977 06:52:09.791286
10978 06:52:09.791652
10979 06:52:09.806075 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
10980 06:52:09.806636
10981 06:52:09.812673 The programs included with the Debian GNU/Linux system are free software;
10982 06:52:09.819615 the exact distribution terms for each program are described in the
10983 06:52:09.822708 individual files in /usr/share/doc/*/copyright.
10984 06:52:09.823127
10985 06:52:09.829040 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10986 06:52:09.832038 permitted by applicable law.
10987 06:52:09.833331 Matched prompt #10: / #
10989 06:52:09.834310 Setting prompt string to ['/ #']
10990 06:52:09.834731 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10992 06:52:09.835690 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10993 06:52:09.836138 start: 2.2.6 expect-shell-connection (timeout 00:03:28) [common]
10994 06:52:09.836540 Setting prompt string to ['/ #']
10995 06:52:09.836856 Forcing a shell prompt, looking for ['/ #']
10997 06:52:09.887768 / #
10998 06:52:09.888451 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10999 06:52:09.888916 Waiting using forced prompt support (timeout 00:02:30)
11000 06:52:09.893978
11001 06:52:09.894909 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11002 06:52:09.895446 start: 2.2.7 export-device-env (timeout 00:03:28) [common]
11003 06:52:09.895959 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11004 06:52:09.896462 end: 2.2 depthcharge-retry (duration 00:01:32) [common]
11005 06:52:09.896928 end: 2 depthcharge-action (duration 00:01:32) [common]
11006 06:52:09.897425 start: 3 lava-test-retry (timeout 00:08:03) [common]
11007 06:52:09.897902 start: 3.1 lava-test-shell (timeout 00:08:03) [common]
11008 06:52:09.898311 Using namespace: common
11010 06:52:09.999503 / # #
11011 06:52:10.000198 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11012 06:52:10.000852 #<6>[ 19.444685] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11013 06:52:10.001236 <6>[ 19.450312] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11014 06:52:10.006153
11015 06:52:10.007096 Using /lava-12694793
11017 06:52:10.108256 / # export SHELL=/bin/sh
11018 06:52:10.109087 export SHELL=/bin/sh<6>[ 19.563248] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11019 06:52:10.115417
11021 06:52:10.217240 / # . /lava-12694793/environment
11022 06:52:10.223978 . /lava-12694793/environment
11024 06:52:10.325842 / # /lava-12694793/bin/lava-test-runner /lava-12694793/0
11025 06:52:10.326527 Test shell timeout: 10s (minimum of the action and connection timeout)
11026 06:52:10.333125 /lava-12694793/bin/lava-test-runner /lava-12694793/0
11027 06:52:10.355792 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11028 06:52:10.361926 + cd /lava-12694793/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11029 06:52:10.362492 + cat uuid
11030 06:52:10.365237 + UUID=12694793_1.5.2.3.1
11031 06:52:10.365706 + set +x
11032 06:52:10.372207 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12694793_1.5.2.3.1>
11033 06:52:10.373184 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12694793_1.5.2.3.1
11034 06:52:10.373763 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12694793_1.5.2.3.1)
11035 06:52:10.374244 Skipping test definition patterns.
11036 06:52:10.374940 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11037 06:52:10.381743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11038 06:52:10.382469 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11040 06:52:10.391296 device: /dev/video2<4>[ 19.853501] use of bytesused == 0 is deprecated and will be removed in the future,
11041 06:52:10.394822 <4>[ 19.862452] use the actual size instead.
11042 06:52:10.395381
11043 06:52:10.408754 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11044 06:52:10.420886 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11045 06:52:10.426889
11046 06:52:10.441427 Compliance test for mtk-vcodec-enc device /dev/video2:
11047 06:52:10.447977
11048 06:52:10.459048 Driver Info:
11049 06:52:10.473569 Driver name : mtk-vcodec-enc
11050 06:52:10.487827 Card type : MT8192 video encoder
11051 06:52:10.497422 Bus info : platform:17020000.vcodec
11052 06:52:10.504910 Driver version : 6.1.75
11053 06:52:10.516368 Capabilities : 0x84204000
11054 06:52:10.531706 Video Memory-to-Memory Multiplanar
11055 06:52:10.538167 Streaming
11056 06:52:10.550424 Extended Pix Format
11057 06:52:10.566186 Device Capabilities
11058 06:52:10.575657 Device Caps : 0x04204000
11059 06:52:10.591238 Video Memory-to-Memory Multiplanar
11060 06:52:10.602576 Streaming
11061 06:52:10.617784 Extended Pix Format
11062 06:52:10.630863 Detected Stateful Encoder
11063 06:52:10.640536
11064 06:52:10.651299 Required ioctls:
11065 06:52:10.670661 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11066 06:52:10.671225 test VIDIOC_QUERYCAP: OK
11067 06:52:10.671887 Received signal: <TESTSET> START Required-ioctls
11068 06:52:10.672275 Starting test_set Required-ioctls
11069 06:52:10.695554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11070 06:52:10.696423 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11072 06:52:10.697949 test invalid ioctls: OK
11073 06:52:10.719436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11074 06:52:10.720000
11075 06:52:10.720715 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11077 06:52:10.730349 Allow for multiple opens:
11078 06:52:10.736977 <LAVA_SIGNAL_TESTSET STOP>
11079 06:52:10.737801 Received signal: <TESTSET> STOP
11080 06:52:10.738183 Closing test_set Required-ioctls
11081 06:52:10.747037 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11082 06:52:10.747707 Received signal: <TESTSET> START Allow-for-multiple-opens
11083 06:52:10.748057 Starting test_set Allow-for-multiple-opens
11084 06:52:10.749771 test second /dev/video2 open: OK
11085 06:52:10.770226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11086 06:52:10.770988 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11088 06:52:10.773789 test VIDIOC_QUERYCAP: OK
11089 06:52:10.795207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11090 06:52:10.795997 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11092 06:52:10.797877 test VIDIOC_G/S_PRIORITY: OK
11093 06:52:10.817642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11094 06:52:10.818483 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11096 06:52:10.820877 test for unlimited opens: OK
11097 06:52:10.842617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11098 06:52:10.843181
11099 06:52:10.843821 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11101 06:52:10.854552 Debug ioctls:
11102 06:52:10.860567 <LAVA_SIGNAL_TESTSET STOP>
11103 06:52:10.861401 Received signal: <TESTSET> STOP
11104 06:52:10.861782 Closing test_set Allow-for-multiple-opens
11105 06:52:10.870946 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11106 06:52:10.871786 Received signal: <TESTSET> START Debug-ioctls
11107 06:52:10.872176 Starting test_set Debug-ioctls
11108 06:52:10.873354 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11109 06:52:10.897570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11110 06:52:10.898409 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11112 06:52:10.904574 test VIDIOC_LOG_STATUS: OK (Not Supported)
11113 06:52:10.921965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11114 06:52:10.922531
11115 06:52:10.923172 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11117 06:52:10.934023 Input ioctls:
11118 06:52:10.941947 <LAVA_SIGNAL_TESTSET STOP>
11119 06:52:10.942673 Received signal: <TESTSET> STOP
11120 06:52:10.943069 Closing test_set Debug-ioctls
11121 06:52:10.951975 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11122 06:52:10.952763 Received signal: <TESTSET> START Input-ioctls
11123 06:52:10.953341 Starting test_set Input-ioctls
11124 06:52:10.954935 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11125 06:52:10.983920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11126 06:52:10.984729 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11128 06:52:10.986302 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11129 06:52:11.009383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11130 06:52:11.010233 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11132 06:52:11.016281 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11133 06:52:11.037274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11134 06:52:11.038152 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11136 06:52:11.044071 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11137 06:52:11.062112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11138 06:52:11.062929 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11140 06:52:11.066098 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11141 06:52:11.093666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11142 06:52:11.094499 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11144 06:52:11.096794 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11145 06:52:11.118072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11146 06:52:11.118909 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11148 06:52:11.121214 Inputs: 0 Audio Inputs: 0 Tuners: 0
11149 06:52:11.137102
11150 06:52:11.154777 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11151 06:52:11.176830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11152 06:52:11.177621 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11154 06:52:11.183074 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11155 06:52:11.202218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11156 06:52:11.203054 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11158 06:52:11.208037 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11159 06:52:11.226491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11160 06:52:11.227307 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11162 06:52:11.233124 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11163 06:52:11.252278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11164 06:52:11.253147 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11166 06:52:11.258218 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11167 06:52:11.275793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11168 06:52:11.276371
11169 06:52:11.277006 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11171 06:52:11.298308 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11172 06:52:11.325207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11173 06:52:11.326067 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11175 06:52:11.331825 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11176 06:52:11.357422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11177 06:52:11.358261 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11179 06:52:11.360703 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11180 06:52:11.378714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11181 06:52:11.379562 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11183 06:52:11.382112 test VIDIOC_G/S_EDID: OK (Not Supported)
11184 06:52:11.404785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11185 06:52:11.405346
11186 06:52:11.405989 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11188 06:52:11.416380 Control ioctls:
11189 06:52:11.423117 <LAVA_SIGNAL_TESTSET STOP>
11190 06:52:11.423976 Received signal: <TESTSET> STOP
11191 06:52:11.424425 Closing test_set Input-ioctls
11192 06:52:11.432179 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11193 06:52:11.433165 Received signal: <TESTSET> START Control-ioctls
11194 06:52:11.433561 Starting test_set Control-ioctls
11195 06:52:11.435494 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11196 06:52:11.467568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11197 06:52:11.468135 test VIDIOC_QUERYCTRL: OK
11198 06:52:11.468842 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11200 06:52:11.489280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11201 06:52:11.490111 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11203 06:52:11.492405 test VIDIOC_G/S_CTRL: OK
11204 06:52:11.519192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11205 06:52:11.520068 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11207 06:52:11.522246 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11208 06:52:11.545095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11209 06:52:11.545794 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11211 06:52:11.555257 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11212 06:52:11.558335 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11213 06:52:11.583304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11214 06:52:11.584202 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11216 06:52:11.586359 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11217 06:52:11.608557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11218 06:52:11.609389 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11220 06:52:11.612144 Standard Controls: 16 Private Controls: 0
11221 06:52:11.618568
11222 06:52:11.629578 Format ioctls:
11223 06:52:11.637934 <LAVA_SIGNAL_TESTSET STOP>
11224 06:52:11.638831 Received signal: <TESTSET> STOP
11225 06:52:11.639325 Closing test_set Control-ioctls
11226 06:52:11.649391 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11227 06:52:11.650287 Received signal: <TESTSET> START Format-ioctls
11228 06:52:11.650777 Starting test_set Format-ioctls
11229 06:52:11.652343 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11230 06:52:11.678053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11231 06:52:11.678915 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11233 06:52:11.680543 test VIDIOC_G/S_PARM: OK
11234 06:52:11.699020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11235 06:52:11.699864 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11237 06:52:11.702183 test VIDIOC_G_FBUF: OK (Not Supported)
11238 06:52:11.724860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11239 06:52:11.725710 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11241 06:52:11.728409 test VIDIOC_G_FMT: OK
11242 06:52:11.750306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11243 06:52:11.751155 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11245 06:52:11.753521 test VIDIOC_TRY_FMT: OK
11246 06:52:11.776028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11247 06:52:11.776956 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11249 06:52:11.785804 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11250 06:52:11.786361 test VIDIOC_S_FMT: FAIL
11251 06:52:11.814047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11252 06:52:11.814899 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11254 06:52:11.816801 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11255 06:52:11.839437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11256 06:52:11.840327 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11258 06:52:11.842454 test Cropping: OK
11259 06:52:11.866899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11260 06:52:11.867733 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11262 06:52:11.870193 test Composing: OK (Not Supported)
11263 06:52:11.894522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11264 06:52:11.895419 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11266 06:52:11.897952 test Scaling: OK (Not Supported)
11267 06:52:11.920594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11268 06:52:11.921150
11269 06:52:11.921780 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11271 06:52:11.930072 Codec ioctls:
11272 06:52:11.938144 <LAVA_SIGNAL_TESTSET STOP>
11273 06:52:11.938974 Received signal: <TESTSET> STOP
11274 06:52:11.939354 Closing test_set Format-ioctls
11275 06:52:11.947078 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11276 06:52:11.947907 Received signal: <TESTSET> START Codec-ioctls
11277 06:52:11.948338 Starting test_set Codec-ioctls
11278 06:52:11.950042 test VIDIOC_(TRY_)ENCODER_CMD: OK
11279 06:52:11.973692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11280 06:52:11.974529 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11282 06:52:11.980446 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11283 06:52:11.998454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11284 06:52:11.999523 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11286 06:52:12.004499 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11287 06:52:12.023413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11288 06:52:12.023961
11289 06:52:12.024641 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11291 06:52:12.033581 Buffer ioctls:
11292 06:52:12.040792 <LAVA_SIGNAL_TESTSET STOP>
11293 06:52:12.041626 Received signal: <TESTSET> STOP
11294 06:52:12.042036 Closing test_set Codec-ioctls
11295 06:52:12.051411 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11296 06:52:12.052246 Received signal: <TESTSET> START Buffer-ioctls
11297 06:52:12.052702 Starting test_set Buffer-ioctls
11298 06:52:12.054669 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11299 06:52:12.080691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11300 06:52:12.081261 test VIDIOC_EXPBUF: OK
11301 06:52:12.081908 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11303 06:52:12.100831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11304 06:52:12.101660 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11306 06:52:12.104836 test Requests: OK (Not Supported)
11307 06:52:12.128546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11308 06:52:12.129094
11309 06:52:12.129719 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11311 06:52:12.140452 Test input 0:
11312 06:52:12.151648
11313 06:52:12.161874 Streaming ioctls:
11314 06:52:12.169057 <LAVA_SIGNAL_TESTSET STOP>
11315 06:52:12.169894 Received signal: <TESTSET> STOP
11316 06:52:12.170274 Closing test_set Buffer-ioctls
11317 06:52:12.179188 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11318 06:52:12.180030 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11319 06:52:12.180514 Starting test_set Streaming-ioctls_Test-input-0
11320 06:52:12.182612 test read/write: OK (Not Supported)
11321 06:52:12.207148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11322 06:52:12.208020 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11324 06:52:12.213836 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11325 06:52:12.228506 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11326 06:52:12.232767 test blocking wait: FAIL
11327 06:52:12.263501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11328 06:52:12.264385 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11330 06:52:12.270269 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11331 06:52:12.275065 test MMAP (select): FAIL
11332 06:52:12.305197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11333 06:52:12.306040 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11335 06:52:12.311749 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11336 06:52:12.316950 test MMAP (epoll): FAIL
11337 06:52:12.343913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11338 06:52:12.344892 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11340 06:52:12.350235 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11341 06:52:12.360379 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11342 06:52:12.365885 test USERPTR (select): FAIL
11343 06:52:12.392738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11344 06:52:12.393630 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11346 06:52:12.398908 test DMABUF: Cannot test, specify --expbuf-device
11347 06:52:12.402523
11348 06:52:12.422181 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11349 06:52:12.426252 <LAVA_TEST_RUNNER EXIT>
11350 06:52:12.427116 ok: lava_test_shell seems to have completed
11351 06:52:12.427543 Marking unfinished test run as failed
11353 06:52:12.432788 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11354 06:52:12.433441 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11355 06:52:12.433927 end: 3 lava-test-retry (duration 00:00:03) [common]
11356 06:52:12.434405 start: 4 finalize (timeout 00:08:00) [common]
11357 06:52:12.434891 start: 4.1 power-off (timeout 00:00:30) [common]
11358 06:52:12.435697 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11359 06:52:12.557660 >> Command sent successfully.
11360 06:52:12.568597 Returned 0 in 0 seconds
11361 06:52:12.670019 end: 4.1 power-off (duration 00:00:00) [common]
11363 06:52:12.671520 start: 4.2 read-feedback (timeout 00:08:00) [common]
11364 06:52:12.672799 Listened to connection for namespace 'common' for up to 1s
11365 06:52:13.672588 Finalising connection for namespace 'common'
11366 06:52:13.673230 Disconnecting from shell: Finalise
11367 06:52:13.673621 / #
11368 06:52:13.774644 end: 4.2 read-feedback (duration 00:00:01) [common]
11369 06:52:13.775380 end: 4 finalize (duration 00:00:01) [common]
11370 06:52:13.776181 Cleaning after the job
11371 06:52:13.776800 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/ramdisk
11372 06:52:13.802127 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/kernel
11373 06:52:13.821914 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/dtb
11374 06:52:13.822206 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694793/tftp-deploy-3scfsdto/modules
11375 06:52:13.832247 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694793
11376 06:52:13.900648 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694793
11377 06:52:13.900829 Job finished correctly