Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 17
- Kernel Errors: 35
1 06:47:15.614086 lava-dispatcher, installed at version: 2023.10
2 06:47:15.614300 start: 0 validate
3 06:47:15.614432 Start time: 2024-02-03 06:47:15.614424+00:00 (UTC)
4 06:47:15.614549 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:47:15.614686 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 06:47:15.883665 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:47:15.884398 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:47:49.668090 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:47:49.668848 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:47:49.931053 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:47:49.931778 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:47:50.455324 Using caching service: 'http://localhost/cache/?uri=%s'
13 06:47:50.456304 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 06:48:02.236369 validate duration: 46.62
16 06:48:02.236618 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:48:02.236744 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:48:02.236861 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:48:02.237034 Not decompressing ramdisk as can be used compressed.
20 06:48:02.237130 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 06:48:02.237191 saving as /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/ramdisk/initrd.cpio.gz
22 06:48:02.237254 total size: 4665412 (4 MB)
23 06:48:02.494074 progress 0 % (0 MB)
24 06:48:02.495552 progress 5 % (0 MB)
25 06:48:02.496978 progress 10 % (0 MB)
26 06:48:02.498204 progress 15 % (0 MB)
27 06:48:02.499424 progress 20 % (0 MB)
28 06:48:02.500734 progress 25 % (1 MB)
29 06:48:02.501995 progress 30 % (1 MB)
30 06:48:02.503202 progress 35 % (1 MB)
31 06:48:02.504400 progress 40 % (1 MB)
32 06:48:02.505802 progress 45 % (2 MB)
33 06:48:02.507002 progress 50 % (2 MB)
34 06:48:02.508205 progress 55 % (2 MB)
35 06:48:02.509459 progress 60 % (2 MB)
36 06:48:02.510657 progress 65 % (2 MB)
37 06:48:02.511854 progress 70 % (3 MB)
38 06:48:02.513110 progress 75 % (3 MB)
39 06:48:02.514297 progress 80 % (3 MB)
40 06:48:02.515693 progress 85 % (3 MB)
41 06:48:02.516938 progress 90 % (4 MB)
42 06:48:02.518164 progress 95 % (4 MB)
43 06:48:02.519406 progress 100 % (4 MB)
44 06:48:02.519632 4 MB downloaded in 0.28 s (15.76 MB/s)
45 06:48:02.519866 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:48:02.520156 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:48:02.520240 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:48:02.520323 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:48:02.520487 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 06:48:02.520555 saving as /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/kernel/Image
52 06:48:02.520615 total size: 51532288 (49 MB)
53 06:48:02.520675 No compression specified
54 06:48:02.521818 progress 0 % (0 MB)
55 06:48:02.534917 progress 5 % (2 MB)
56 06:48:02.549402 progress 10 % (4 MB)
57 06:48:02.563425 progress 15 % (7 MB)
58 06:48:02.576957 progress 20 % (9 MB)
59 06:48:02.590803 progress 25 % (12 MB)
60 06:48:02.605291 progress 30 % (14 MB)
61 06:48:02.618772 progress 35 % (17 MB)
62 06:48:02.632173 progress 40 % (19 MB)
63 06:48:02.645449 progress 45 % (22 MB)
64 06:48:02.658905 progress 50 % (24 MB)
65 06:48:02.672218 progress 55 % (27 MB)
66 06:48:02.685545 progress 60 % (29 MB)
67 06:48:02.698745 progress 65 % (31 MB)
68 06:48:02.711791 progress 70 % (34 MB)
69 06:48:02.725202 progress 75 % (36 MB)
70 06:48:02.738506 progress 80 % (39 MB)
71 06:48:02.751580 progress 85 % (41 MB)
72 06:48:02.764755 progress 90 % (44 MB)
73 06:48:02.777820 progress 95 % (46 MB)
74 06:48:02.790611 progress 100 % (49 MB)
75 06:48:02.790812 49 MB downloaded in 0.27 s (181.89 MB/s)
76 06:48:02.790959 end: 1.2.1 http-download (duration 00:00:00) [common]
78 06:48:02.791185 end: 1.2 download-retry (duration 00:00:00) [common]
79 06:48:02.791270 start: 1.3 download-retry (timeout 00:09:59) [common]
80 06:48:02.791356 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 06:48:02.791493 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 06:48:02.791565 saving as /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/dtb/mt8192-asurada-spherion-r0.dtb
83 06:48:02.791625 total size: 47278 (0 MB)
84 06:48:02.791684 No compression specified
85 06:48:03.057496 progress 69 % (0 MB)
86 06:48:03.057824 progress 100 % (0 MB)
87 06:48:03.057989 0 MB downloaded in 0.27 s (0.17 MB/s)
88 06:48:03.058132 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:48:03.058360 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:48:03.058445 start: 1.4 download-retry (timeout 00:09:59) [common]
92 06:48:03.058556 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 06:48:03.058688 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 06:48:03.058754 saving as /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/nfsrootfs/full.rootfs.tar
95 06:48:03.058813 total size: 125290964 (119 MB)
96 06:48:03.058873 Using unxz to decompress xz
97 06:48:03.327078 progress 0 % (0 MB)
98 06:48:03.654992 progress 5 % (6 MB)
99 06:48:03.983166 progress 10 % (11 MB)
100 06:48:04.311870 progress 15 % (17 MB)
101 06:48:04.500452 progress 20 % (23 MB)
102 06:48:04.682127 progress 25 % (29 MB)
103 06:48:05.043230 progress 30 % (35 MB)
104 06:48:05.400943 progress 35 % (41 MB)
105 06:48:05.784858 progress 40 % (47 MB)
106 06:48:06.160049 progress 45 % (53 MB)
107 06:48:06.552574 progress 50 % (59 MB)
108 06:48:06.914999 progress 55 % (65 MB)
109 06:48:07.284086 progress 60 % (71 MB)
110 06:48:07.627074 progress 65 % (77 MB)
111 06:48:07.995868 progress 70 % (83 MB)
112 06:48:08.383247 progress 75 % (89 MB)
113 06:48:08.797474 progress 80 % (95 MB)
114 06:48:09.207959 progress 85 % (101 MB)
115 06:48:09.449553 progress 90 % (107 MB)
116 06:48:09.780583 progress 95 % (113 MB)
117 06:48:10.145844 progress 100 % (119 MB)
118 06:48:10.151436 119 MB downloaded in 7.09 s (16.85 MB/s)
119 06:48:10.151691 end: 1.4.1 http-download (duration 00:00:07) [common]
121 06:48:10.152052 end: 1.4 download-retry (duration 00:00:07) [common]
122 06:48:10.152139 start: 1.5 download-retry (timeout 00:09:52) [common]
123 06:48:10.152227 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 06:48:10.152462 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 06:48:10.152596 saving as /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/modules/modules.tar
126 06:48:10.152696 total size: 8624064 (8 MB)
127 06:48:10.152809 Using unxz to decompress xz
128 06:48:10.157696 progress 0 % (0 MB)
129 06:48:10.178638 progress 5 % (0 MB)
130 06:48:10.201918 progress 10 % (0 MB)
131 06:48:10.225129 progress 15 % (1 MB)
132 06:48:10.248463 progress 20 % (1 MB)
133 06:48:10.272361 progress 25 % (2 MB)
134 06:48:10.297728 progress 30 % (2 MB)
135 06:48:10.323446 progress 35 % (2 MB)
136 06:48:10.346670 progress 40 % (3 MB)
137 06:48:10.370792 progress 45 % (3 MB)
138 06:48:10.395817 progress 50 % (4 MB)
139 06:48:10.419649 progress 55 % (4 MB)
140 06:48:10.444233 progress 60 % (4 MB)
141 06:48:10.471624 progress 65 % (5 MB)
142 06:48:10.496173 progress 70 % (5 MB)
143 06:48:10.519465 progress 75 % (6 MB)
144 06:48:10.546247 progress 80 % (6 MB)
145 06:48:10.571679 progress 85 % (7 MB)
146 06:48:10.596414 progress 90 % (7 MB)
147 06:48:10.627563 progress 95 % (7 MB)
148 06:48:10.655648 progress 100 % (8 MB)
149 06:48:10.660557 8 MB downloaded in 0.51 s (16.19 MB/s)
150 06:48:10.660853 end: 1.5.1 http-download (duration 00:00:01) [common]
152 06:48:10.661120 end: 1.5 download-retry (duration 00:00:01) [common]
153 06:48:10.661214 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 06:48:10.661315 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 06:48:12.791802 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12694863/extract-nfsrootfs-kuz9jy9o
156 06:48:12.792012 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 06:48:12.792110 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 06:48:12.792281 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj
159 06:48:12.792414 makedir: /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin
160 06:48:12.792515 makedir: /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/tests
161 06:48:12.792612 makedir: /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/results
162 06:48:12.792722 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-add-keys
163 06:48:12.792870 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-add-sources
164 06:48:12.793000 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-background-process-start
165 06:48:12.793129 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-background-process-stop
166 06:48:12.793256 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-common-functions
167 06:48:12.793381 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-echo-ipv4
168 06:48:12.793508 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-install-packages
169 06:48:12.793633 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-installed-packages
170 06:48:12.793757 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-os-build
171 06:48:12.793881 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-probe-channel
172 06:48:12.794008 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-probe-ip
173 06:48:12.794133 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-target-ip
174 06:48:12.794257 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-target-mac
175 06:48:12.794382 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-target-storage
176 06:48:12.794510 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-test-case
177 06:48:12.794637 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-test-event
178 06:48:12.794761 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-test-feedback
179 06:48:12.794910 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-test-raise
180 06:48:12.795067 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-test-reference
181 06:48:12.795196 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-test-runner
182 06:48:12.795321 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-test-set
183 06:48:12.795446 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-test-shell
184 06:48:12.795571 Updating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-install-packages (oe)
185 06:48:12.795722 Updating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/bin/lava-installed-packages (oe)
186 06:48:12.795863 Creating /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/environment
187 06:48:12.795959 LAVA metadata
188 06:48:12.796029 - LAVA_JOB_ID=12694863
189 06:48:12.796091 - LAVA_DISPATCHER_IP=192.168.201.1
190 06:48:12.796194 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 06:48:12.796261 skipped lava-vland-overlay
192 06:48:12.796334 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 06:48:12.796413 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 06:48:12.796473 skipped lava-multinode-overlay
195 06:48:12.796545 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 06:48:12.796621 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 06:48:12.796694 Loading test definitions
198 06:48:12.796791 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 06:48:12.796862 Using /lava-12694863 at stage 0
200 06:48:12.797173 uuid=12694863_1.6.2.3.1 testdef=None
201 06:48:12.797261 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 06:48:12.797345 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 06:48:12.797855 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 06:48:12.798072 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 06:48:12.798700 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 06:48:12.798926 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 06:48:12.799810 runner path: /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/0/tests/0_dmesg test_uuid 12694863_1.6.2.3.1
210 06:48:12.799965 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 06:48:12.800186 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 06:48:12.800258 Using /lava-12694863 at stage 1
214 06:48:12.800560 uuid=12694863_1.6.2.3.5 testdef=None
215 06:48:12.800647 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 06:48:12.800946 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 06:48:12.801426 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 06:48:12.801640 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 06:48:12.802277 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 06:48:12.802501 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 06:48:12.803123 runner path: /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/1/tests/1_bootrr test_uuid 12694863_1.6.2.3.5
224 06:48:12.803276 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 06:48:12.803476 Creating lava-test-runner.conf files
227 06:48:12.803538 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/0 for stage 0
228 06:48:12.803629 - 0_dmesg
229 06:48:12.803709 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694863/lava-overlay-3r57gpnj/lava-12694863/1 for stage 1
230 06:48:12.803800 - 1_bootrr
231 06:48:12.803892 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 06:48:12.803976 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 06:48:12.811214 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 06:48:12.811331 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 06:48:12.811415 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 06:48:12.811501 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 06:48:12.811584 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 06:48:12.932172 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 06:48:12.932683 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 06:48:12.932817 extracting modules file /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694863/extract-nfsrootfs-kuz9jy9o
241 06:48:13.152813 extracting modules file /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694863/extract-overlay-ramdisk-xifuyj2n/ramdisk
242 06:48:13.380985 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 06:48:13.381155 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 06:48:13.381252 [common] Applying overlay to NFS
245 06:48:13.381323 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694863/compress-overlay-6sgah7i0/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694863/extract-nfsrootfs-kuz9jy9o
246 06:48:13.389363 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 06:48:13.389495 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 06:48:13.389590 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 06:48:13.389683 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 06:48:13.389762 Building ramdisk /var/lib/lava/dispatcher/tmp/12694863/extract-overlay-ramdisk-xifuyj2n/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694863/extract-overlay-ramdisk-xifuyj2n/ramdisk
251 06:48:13.722203 >> 119430 blocks
252 06:48:15.631277 rename /var/lib/lava/dispatcher/tmp/12694863/extract-overlay-ramdisk-xifuyj2n/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/ramdisk/ramdisk.cpio.gz
253 06:48:15.631736 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 06:48:15.631866 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 06:48:15.631969 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 06:48:15.632077 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/kernel/Image'
257 06:48:28.434921 Returned 0 in 12 seconds
258 06:48:28.536041 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/kernel/image.itb
259 06:48:28.920331 output: FIT description: Kernel Image image with one or more FDT blobs
260 06:48:28.920767 output: Created: Sat Feb 3 06:48:28 2024
261 06:48:28.920842 output: Image 0 (kernel-1)
262 06:48:28.920905 output: Description:
263 06:48:28.920968 output: Created: Sat Feb 3 06:48:28 2024
264 06:48:28.921032 output: Type: Kernel Image
265 06:48:28.921092 output: Compression: lzma compressed
266 06:48:28.921149 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
267 06:48:28.921212 output: Architecture: AArch64
268 06:48:28.921272 output: OS: Linux
269 06:48:28.921328 output: Load Address: 0x00000000
270 06:48:28.921385 output: Entry Point: 0x00000000
271 06:48:28.921440 output: Hash algo: crc32
272 06:48:28.921495 output: Hash value: 380e7c3c
273 06:48:28.921550 output: Image 1 (fdt-1)
274 06:48:28.921601 output: Description: mt8192-asurada-spherion-r0
275 06:48:28.921654 output: Created: Sat Feb 3 06:48:28 2024
276 06:48:28.921706 output: Type: Flat Device Tree
277 06:48:28.921758 output: Compression: uncompressed
278 06:48:28.921809 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 06:48:28.921860 output: Architecture: AArch64
280 06:48:28.921912 output: Hash algo: crc32
281 06:48:28.921963 output: Hash value: cc4352de
282 06:48:28.922015 output: Image 2 (ramdisk-1)
283 06:48:28.922066 output: Description: unavailable
284 06:48:28.922117 output: Created: Sat Feb 3 06:48:28 2024
285 06:48:28.922169 output: Type: RAMDisk Image
286 06:48:28.922220 output: Compression: Unknown Compression
287 06:48:28.922271 output: Data Size: 17799847 Bytes = 17382.66 KiB = 16.98 MiB
288 06:48:28.922322 output: Architecture: AArch64
289 06:48:28.922374 output: OS: Linux
290 06:48:28.922425 output: Load Address: unavailable
291 06:48:28.922477 output: Entry Point: unavailable
292 06:48:28.922528 output: Hash algo: crc32
293 06:48:28.922578 output: Hash value: f13b32ea
294 06:48:28.922630 output: Default Configuration: 'conf-1'
295 06:48:28.922682 output: Configuration 0 (conf-1)
296 06:48:28.922733 output: Description: mt8192-asurada-spherion-r0
297 06:48:28.922784 output: Kernel: kernel-1
298 06:48:28.922835 output: Init Ramdisk: ramdisk-1
299 06:48:28.922886 output: FDT: fdt-1
300 06:48:28.922937 output: Loadables: kernel-1
301 06:48:28.922989 output:
302 06:48:28.923195 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 06:48:28.923293 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 06:48:28.923393 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 06:48:28.923488 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
306 06:48:28.923568 No LXC device requested
307 06:48:28.923644 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 06:48:28.923729 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
309 06:48:28.923805 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 06:48:28.923871 Checking files for TFTP limit of 4294967296 bytes.
311 06:48:28.924360 end: 1 tftp-deploy (duration 00:00:27) [common]
312 06:48:28.924468 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 06:48:28.924558 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 06:48:28.924715 substitutions:
315 06:48:28.924850 - {DTB}: 12694863/tftp-deploy-urr229ql/dtb/mt8192-asurada-spherion-r0.dtb
316 06:48:28.924920 - {INITRD}: 12694863/tftp-deploy-urr229ql/ramdisk/ramdisk.cpio.gz
317 06:48:28.924981 - {KERNEL}: 12694863/tftp-deploy-urr229ql/kernel/Image
318 06:48:28.925039 - {LAVA_MAC}: None
319 06:48:28.925095 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12694863/extract-nfsrootfs-kuz9jy9o
320 06:48:28.925151 - {NFS_SERVER_IP}: 192.168.201.1
321 06:48:28.925205 - {PRESEED_CONFIG}: None
322 06:48:28.925258 - {PRESEED_LOCAL}: None
323 06:48:28.925311 - {RAMDISK}: 12694863/tftp-deploy-urr229ql/ramdisk/ramdisk.cpio.gz
324 06:48:28.925365 - {ROOT_PART}: None
325 06:48:28.925418 - {ROOT}: None
326 06:48:28.925471 - {SERVER_IP}: 192.168.201.1
327 06:48:28.925523 - {TEE}: None
328 06:48:28.925576 Parsed boot commands:
329 06:48:28.925627 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 06:48:28.925814 Parsed boot commands: tftpboot 192.168.201.1 12694863/tftp-deploy-urr229ql/kernel/image.itb 12694863/tftp-deploy-urr229ql/kernel/cmdline
331 06:48:28.925901 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 06:48:28.925985 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 06:48:28.926076 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 06:48:28.926160 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 06:48:28.926229 Not connected, no need to disconnect.
336 06:48:28.926304 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 06:48:28.926388 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 06:48:28.926454 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
339 06:48:28.930571 Setting prompt string to ['lava-test: # ']
340 06:48:28.930924 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 06:48:28.931026 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 06:48:28.931120 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 06:48:28.931253 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 06:48:28.931485 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
345 06:48:34.073427 >> Command sent successfully.
346 06:48:34.085239 Returned 0 in 5 seconds
347 06:48:34.186623 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 06:48:34.188493 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 06:48:34.189099 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 06:48:34.189613 Setting prompt string to 'Starting depthcharge on Spherion...'
352 06:48:34.189986 Changing prompt to 'Starting depthcharge on Spherion...'
353 06:48:34.190367 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 06:48:34.191766 [Enter `^Ec?' for help]
355 06:48:34.358982
356 06:48:34.359520
357 06:48:34.359906 F0: 102B 0000
358 06:48:34.360285
359 06:48:34.362425 F3: 1001 0000 [0200]
360 06:48:34.362819
361 06:48:34.363281 F3: 1001 0000
362 06:48:34.363914
363 06:48:34.364486 F7: 102D 0000
364 06:48:34.365011
365 06:48:34.367111 F1: 0000 0000
366 06:48:34.367591
367 06:48:34.368079 V0: 0000 0000 [0001]
368 06:48:34.368620
369 06:48:34.369121 00: 0007 8000
370 06:48:34.369937
371 06:48:34.370339 01: 0000 0000
372 06:48:34.370798
373 06:48:34.371234 BP: 0C00 0209 [0000]
374 06:48:34.371666
375 06:48:34.373721 G0: 1182 0000
376 06:48:34.374203
377 06:48:34.374692 EC: 0000 0021 [4000]
378 06:48:34.375152
379 06:48:34.378084 S7: 0000 0000 [0000]
380 06:48:34.378658
381 06:48:34.379148 CC: 0000 0000 [0001]
382 06:48:34.379611
383 06:48:34.381280 T0: 0000 0040 [010F]
384 06:48:34.381766
385 06:48:34.382258 Jump to BL
386 06:48:34.382721
387 06:48:34.406476
388 06:48:34.407045
389 06:48:34.407535
390 06:48:34.413296 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 06:48:34.417066 ARM64: Exception handlers installed.
392 06:48:34.420044 ARM64: Testing exception
393 06:48:34.423606 ARM64: Done test exception
394 06:48:34.430352 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 06:48:34.440535 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 06:48:34.447676 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 06:48:34.457590 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 06:48:34.464320 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 06:48:34.471381 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 06:48:34.482857 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 06:48:34.490018 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 06:48:34.509246 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 06:48:34.512686 WDT: Last reset was cold boot
404 06:48:34.516259 SPI1(PAD0) initialized at 2873684 Hz
405 06:48:34.519170 SPI5(PAD0) initialized at 992727 Hz
406 06:48:34.523048 VBOOT: Loading verstage.
407 06:48:34.528648 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 06:48:34.533025 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 06:48:34.535776 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 06:48:34.539276 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 06:48:34.546322 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 06:48:34.553621 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 06:48:34.564461 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 06:48:34.565091
415 06:48:34.565588
416 06:48:34.574066 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 06:48:34.577253 ARM64: Exception handlers installed.
418 06:48:34.580604 ARM64: Testing exception
419 06:48:34.581207 ARM64: Done test exception
420 06:48:34.588175 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 06:48:34.591408 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 06:48:34.605337 Probing TPM: . done!
423 06:48:34.605910 TPM ready after 0 ms
424 06:48:34.612535 Connected to device vid:did:rid of 1ae0:0028:00
425 06:48:34.619036 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
426 06:48:34.622538 Initialized TPM device CR50 revision 0
427 06:48:34.673364 tlcl_send_startup: Startup return code is 0
428 06:48:34.673932 TPM: setup succeeded
429 06:48:34.684129 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 06:48:34.693297 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 06:48:34.703435 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 06:48:34.712115 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 06:48:34.715606 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 06:48:34.718931 in-header: 03 07 00 00 08 00 00 00
435 06:48:34.721594 in-data: aa e4 47 04 13 02 00 00
436 06:48:34.725366 Chrome EC: UHEPI supported
437 06:48:34.732541 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 06:48:34.735336 in-header: 03 9d 00 00 08 00 00 00
439 06:48:34.739141 in-data: 10 20 20 08 00 00 00 00
440 06:48:34.739711 Phase 1
441 06:48:34.742081 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 06:48:34.748403 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 06:48:34.756047 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 06:48:34.758528 Recovery requested (1009000e)
445 06:48:34.763230 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 06:48:34.770871 tlcl_extend: response is 0
447 06:48:34.779357 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 06:48:34.784574 tlcl_extend: response is 0
449 06:48:34.791277 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 06:48:34.811779 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 06:48:34.818544 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 06:48:34.819115
453 06:48:34.819522
454 06:48:34.827858 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 06:48:34.831122 ARM64: Exception handlers installed.
456 06:48:34.834867 ARM64: Testing exception
457 06:48:34.835332 ARM64: Done test exception
458 06:48:34.857532 pmic_efuse_setting: Set efuses in 11 msecs
459 06:48:34.861767 pmwrap_interface_init: Select PMIF_VLD_RDY
460 06:48:34.867714 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 06:48:34.871283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 06:48:34.874818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 06:48:34.882155 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 06:48:34.885354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 06:48:34.889046 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 06:48:34.895831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 06:48:34.900049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 06:48:34.905985 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 06:48:34.909373 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 06:48:34.912883 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 06:48:34.920024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 06:48:34.922649 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 06:48:34.929079 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 06:48:34.936495 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 06:48:34.939009 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 06:48:34.946392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 06:48:34.953615 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 06:48:34.956189 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 06:48:34.963025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 06:48:34.969715 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 06:48:34.973516 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 06:48:34.980268 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 06:48:34.987137 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 06:48:34.990856 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 06:48:34.997196 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 06:48:35.000007 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 06:48:35.007053 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 06:48:35.009889 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 06:48:35.017031 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 06:48:35.019547 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 06:48:35.026256 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 06:48:35.029905 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 06:48:35.037308 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 06:48:35.039832 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 06:48:35.046895 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 06:48:35.050868 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 06:48:35.056427 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 06:48:35.060004 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 06:48:35.063153 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 06:48:35.069689 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 06:48:35.073216 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 06:48:35.076790 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 06:48:35.083381 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 06:48:35.086305 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 06:48:35.090051 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 06:48:35.096880 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 06:48:35.100224 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 06:48:35.103707 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 06:48:35.107215 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 06:48:35.113290 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 06:48:35.120571 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 06:48:35.130826 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 06:48:35.133451 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 06:48:35.140066 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 06:48:35.149816 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 06:48:35.154511 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 06:48:35.159880 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 06:48:35.163344 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 06:48:35.169901 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
520 06:48:35.177096 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 06:48:35.179846 [RTC]rtc_osc_init,62: osc32con val = 0xde70
522 06:48:35.183650 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 06:48:35.194628 [RTC]rtc_get_frequency_meter,154: input=15, output=764
524 06:48:35.203467 [RTC]rtc_get_frequency_meter,154: input=23, output=949
525 06:48:35.213423 [RTC]rtc_get_frequency_meter,154: input=19, output=857
526 06:48:35.222669 [RTC]rtc_get_frequency_meter,154: input=17, output=810
527 06:48:35.232128 [RTC]rtc_get_frequency_meter,154: input=16, output=787
528 06:48:35.242044 [RTC]rtc_get_frequency_meter,154: input=16, output=786
529 06:48:35.251471 [RTC]rtc_get_frequency_meter,154: input=17, output=810
530 06:48:35.255146 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
531 06:48:35.262209 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
532 06:48:35.264944 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 06:48:35.268331 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
534 06:48:35.276266 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 06:48:35.279806 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
536 06:48:35.281945 ADC[4]: Raw value=671168 ID=5
537 06:48:35.282520 ADC[3]: Raw value=212917 ID=1
538 06:48:35.285652 RAM Code: 0x51
539 06:48:35.288791 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 06:48:35.296142 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 06:48:35.302488 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
542 06:48:35.308424 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
543 06:48:35.311893 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 06:48:35.316083 in-header: 03 07 00 00 08 00 00 00
545 06:48:35.319218 in-data: aa e4 47 04 13 02 00 00
546 06:48:35.321260 Chrome EC: UHEPI supported
547 06:48:35.328499 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 06:48:35.331630 in-header: 03 d5 00 00 08 00 00 00
549 06:48:35.335046 in-data: 98 20 60 08 00 00 00 00
550 06:48:35.338362 MRC: failed to locate region type 0.
551 06:48:35.346752 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 06:48:35.347325 DRAM-K: Running full calibration
553 06:48:35.351883 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
554 06:48:35.356885 header.status = 0x0
555 06:48:35.357952 header.version = 0x6 (expected: 0x6)
556 06:48:35.362080 header.size = 0xd00 (expected: 0xd00)
557 06:48:35.362655 header.flags = 0x0
558 06:48:35.367775 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 06:48:35.386332 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
560 06:48:35.393099 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 06:48:35.396431 dram_init: ddr_geometry: 0
562 06:48:35.399510 [EMI] MDL number = 0
563 06:48:35.399982 [EMI] Get MDL freq = 0
564 06:48:35.403342 dram_init: ddr_type: 0
565 06:48:35.403816 is_discrete_lpddr4: 1
566 06:48:35.406950 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 06:48:35.407532
568 06:48:35.407911
569 06:48:35.410078 [Bian_co] ETT version 0.0.0.1
570 06:48:35.413309 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
571 06:48:35.413786
572 06:48:35.420788 dramc_set_vcore_voltage set vcore to 650000
573 06:48:35.421370 Read voltage for 800, 4
574 06:48:35.423853 Vio18 = 0
575 06:48:35.424430 Vcore = 650000
576 06:48:35.424854 Vdram = 0
577 06:48:35.427367 Vddq = 0
578 06:48:35.427950 Vmddr = 0
579 06:48:35.428329 dram_init: config_dvfs: 1
580 06:48:35.433689 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 06:48:35.441002 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 06:48:35.443820 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
583 06:48:35.446917 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
584 06:48:35.450577 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
585 06:48:35.453950 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
586 06:48:35.456554 MEM_TYPE=3, freq_sel=18
587 06:48:35.459983 sv_algorithm_assistance_LP4_1600
588 06:48:35.463374 ============ PULL DRAM RESETB DOWN ============
589 06:48:35.466956 ========== PULL DRAM RESETB DOWN end =========
590 06:48:35.474101 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 06:48:35.477180 ===================================
592 06:48:35.477755 LPDDR4 DRAM CONFIGURATION
593 06:48:35.479988 ===================================
594 06:48:35.483589 EX_ROW_EN[0] = 0x0
595 06:48:35.487089 EX_ROW_EN[1] = 0x0
596 06:48:35.487761 LP4Y_EN = 0x0
597 06:48:35.490159 WORK_FSP = 0x0
598 06:48:35.490731 WL = 0x2
599 06:48:35.493446 RL = 0x2
600 06:48:35.493984 BL = 0x2
601 06:48:35.496891 RPST = 0x0
602 06:48:35.497458 RD_PRE = 0x0
603 06:48:35.501010 WR_PRE = 0x1
604 06:48:35.501737 WR_PST = 0x0
605 06:48:35.503212 DBI_WR = 0x0
606 06:48:35.503678 DBI_RD = 0x0
607 06:48:35.507622 OTF = 0x1
608 06:48:35.510361 ===================================
609 06:48:35.513175 ===================================
610 06:48:35.513648 ANA top config
611 06:48:35.516636 ===================================
612 06:48:35.520072 DLL_ASYNC_EN = 0
613 06:48:35.523299 ALL_SLAVE_EN = 1
614 06:48:35.523862 NEW_RANK_MODE = 1
615 06:48:35.526629 DLL_IDLE_MODE = 1
616 06:48:35.530266 LP45_APHY_COMB_EN = 1
617 06:48:35.533411 TX_ODT_DIS = 1
618 06:48:35.537030 NEW_8X_MODE = 1
619 06:48:35.540223 ===================================
620 06:48:35.544008 ===================================
621 06:48:35.544586 data_rate = 1600
622 06:48:35.546782 CKR = 1
623 06:48:35.550185 DQ_P2S_RATIO = 8
624 06:48:35.553167 ===================================
625 06:48:35.557058 CA_P2S_RATIO = 8
626 06:48:35.560377 DQ_CA_OPEN = 0
627 06:48:35.563169 DQ_SEMI_OPEN = 0
628 06:48:35.563642 CA_SEMI_OPEN = 0
629 06:48:35.567033 CA_FULL_RATE = 0
630 06:48:35.569978 DQ_CKDIV4_EN = 1
631 06:48:35.573797 CA_CKDIV4_EN = 1
632 06:48:35.577219 CA_PREDIV_EN = 0
633 06:48:35.577796 PH8_DLY = 0
634 06:48:35.580082 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 06:48:35.583431 DQ_AAMCK_DIV = 4
636 06:48:35.586877 CA_AAMCK_DIV = 4
637 06:48:35.590203 CA_ADMCK_DIV = 4
638 06:48:35.593603 DQ_TRACK_CA_EN = 0
639 06:48:35.594183 CA_PICK = 800
640 06:48:35.596814 CA_MCKIO = 800
641 06:48:35.600234 MCKIO_SEMI = 0
642 06:48:35.603368 PLL_FREQ = 3068
643 06:48:35.606890 DQ_UI_PI_RATIO = 32
644 06:48:35.610338 CA_UI_PI_RATIO = 0
645 06:48:35.613179 ===================================
646 06:48:35.616658 ===================================
647 06:48:35.619977 memory_type:LPDDR4
648 06:48:35.620442 GP_NUM : 10
649 06:48:35.623395 SRAM_EN : 1
650 06:48:35.623960 MD32_EN : 0
651 06:48:35.627198 ===================================
652 06:48:35.630106 [ANA_INIT] >>>>>>>>>>>>>>
653 06:48:35.633052 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 06:48:35.636518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 06:48:35.640948 ===================================
656 06:48:35.643981 data_rate = 1600,PCW = 0X7600
657 06:48:35.646306 ===================================
658 06:48:35.649594 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 06:48:35.653264 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 06:48:35.659669 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 06:48:35.663338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 06:48:35.666853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 06:48:35.670179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 06:48:35.673128 [ANA_INIT] flow start
665 06:48:35.677233 [ANA_INIT] PLL >>>>>>>>
666 06:48:35.677654 [ANA_INIT] PLL <<<<<<<<
667 06:48:35.679868 [ANA_INIT] MIDPI >>>>>>>>
668 06:48:35.683327 [ANA_INIT] MIDPI <<<<<<<<
669 06:48:35.687307 [ANA_INIT] DLL >>>>>>>>
670 06:48:35.687729 [ANA_INIT] flow end
671 06:48:35.690062 ============ LP4 DIFF to SE enter ============
672 06:48:35.696387 ============ LP4 DIFF to SE exit ============
673 06:48:35.696850 [ANA_INIT] <<<<<<<<<<<<<
674 06:48:35.700401 [Flow] Enable top DCM control >>>>>
675 06:48:35.703959 [Flow] Enable top DCM control <<<<<
676 06:48:35.706794 Enable DLL master slave shuffle
677 06:48:35.713224 ==============================================================
678 06:48:35.713306 Gating Mode config
679 06:48:35.719215 ==============================================================
680 06:48:35.723050 Config description:
681 06:48:35.729214 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 06:48:35.735831 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 06:48:35.742778 SELPH_MODE 0: By rank 1: By Phase
684 06:48:35.749454 ==============================================================
685 06:48:35.749537 GAT_TRACK_EN = 1
686 06:48:35.753022 RX_GATING_MODE = 2
687 06:48:35.757071 RX_GATING_TRACK_MODE = 2
688 06:48:35.759966 SELPH_MODE = 1
689 06:48:35.763475 PICG_EARLY_EN = 1
690 06:48:35.766969 VALID_LAT_VALUE = 1
691 06:48:35.773186 ==============================================================
692 06:48:35.777291 Enter into Gating configuration >>>>
693 06:48:35.780138 Exit from Gating configuration <<<<
694 06:48:35.782841 Enter into DVFS_PRE_config >>>>>
695 06:48:35.792832 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 06:48:35.796342 Exit from DVFS_PRE_config <<<<<
697 06:48:35.799727 Enter into PICG configuration >>>>
698 06:48:35.804505 Exit from PICG configuration <<<<
699 06:48:35.804586 [RX_INPUT] configuration >>>>>
700 06:48:35.806418 [RX_INPUT] configuration <<<<<
701 06:48:35.812843 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 06:48:35.819858 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 06:48:35.822547 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 06:48:35.829664 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 06:48:35.836155 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 06:48:35.842808 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 06:48:35.846033 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 06:48:35.849419 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 06:48:35.856258 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 06:48:35.859694 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 06:48:35.863010 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 06:48:35.866751 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 06:48:35.869430 ===================================
714 06:48:35.873065 LPDDR4 DRAM CONFIGURATION
715 06:48:35.876009 ===================================
716 06:48:35.879650 EX_ROW_EN[0] = 0x0
717 06:48:35.879732 EX_ROW_EN[1] = 0x0
718 06:48:35.882972 LP4Y_EN = 0x0
719 06:48:35.883054 WORK_FSP = 0x0
720 06:48:35.886267 WL = 0x2
721 06:48:35.886349 RL = 0x2
722 06:48:35.889319 BL = 0x2
723 06:48:35.889401 RPST = 0x0
724 06:48:35.892729 RD_PRE = 0x0
725 06:48:35.892826 WR_PRE = 0x1
726 06:48:35.896350 WR_PST = 0x0
727 06:48:35.896432 DBI_WR = 0x0
728 06:48:35.899498 DBI_RD = 0x0
729 06:48:35.902804 OTF = 0x1
730 06:48:35.906794 ===================================
731 06:48:35.909629 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 06:48:35.912902 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 06:48:35.916751 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 06:48:35.919365 ===================================
735 06:48:35.922473 LPDDR4 DRAM CONFIGURATION
736 06:48:35.926062 ===================================
737 06:48:35.929419 EX_ROW_EN[0] = 0x10
738 06:48:35.929502 EX_ROW_EN[1] = 0x0
739 06:48:35.932303 LP4Y_EN = 0x0
740 06:48:35.932385 WORK_FSP = 0x0
741 06:48:35.935899 WL = 0x2
742 06:48:35.936016 RL = 0x2
743 06:48:35.939937 BL = 0x2
744 06:48:35.940019 RPST = 0x0
745 06:48:35.942759 RD_PRE = 0x0
746 06:48:35.942841 WR_PRE = 0x1
747 06:48:35.946059 WR_PST = 0x0
748 06:48:35.946141 DBI_WR = 0x0
749 06:48:35.949990 DBI_RD = 0x0
750 06:48:35.950072 OTF = 0x1
751 06:48:35.952720 ===================================
752 06:48:35.959389 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 06:48:35.964143 nWR fixed to 40
754 06:48:35.967547 [ModeRegInit_LP4] CH0 RK0
755 06:48:35.967630 [ModeRegInit_LP4] CH0 RK1
756 06:48:35.970474 [ModeRegInit_LP4] CH1 RK0
757 06:48:35.973765 [ModeRegInit_LP4] CH1 RK1
758 06:48:35.973847 match AC timing 12
759 06:48:35.980351 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
760 06:48:35.983735 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 06:48:35.987181 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 06:48:35.993724 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 06:48:35.997927 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 06:48:35.998010 [EMI DOE] emi_dcm 0
765 06:48:36.003774 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 06:48:36.003857 ==
767 06:48:36.007207 Dram Type= 6, Freq= 0, CH_0, rank 0
768 06:48:36.011668 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
769 06:48:36.011751 ==
770 06:48:36.017544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 06:48:36.020945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 06:48:36.032089 [CA 0] Center 37 (7~68) winsize 62
773 06:48:36.034705 [CA 1] Center 37 (7~68) winsize 62
774 06:48:36.037898 [CA 2] Center 35 (5~66) winsize 62
775 06:48:36.041364 [CA 3] Center 35 (4~66) winsize 63
776 06:48:36.045082 [CA 4] Center 34 (4~65) winsize 62
777 06:48:36.047727 [CA 5] Center 33 (3~64) winsize 62
778 06:48:36.047809
779 06:48:36.052081 [CmdBusTrainingLP45] Vref(ca) range 1: 32
780 06:48:36.052163
781 06:48:36.054797 [CATrainingPosCal] consider 1 rank data
782 06:48:36.058175 u2DelayCellTimex100 = 270/100 ps
783 06:48:36.061295 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 06:48:36.065061 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
785 06:48:36.071241 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
786 06:48:36.075084 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
787 06:48:36.078560 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
788 06:48:36.081240 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 06:48:36.081322
790 06:48:36.084507 CA PerBit enable=1, Macro0, CA PI delay=33
791 06:48:36.084589
792 06:48:36.088491 [CBTSetCACLKResult] CA Dly = 33
793 06:48:36.088574 CS Dly: 5 (0~36)
794 06:48:36.091688 ==
795 06:48:36.091770 Dram Type= 6, Freq= 0, CH_0, rank 1
796 06:48:36.098006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
797 06:48:36.098089 ==
798 06:48:36.101206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 06:48:36.107932 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 06:48:36.117470 [CA 0] Center 37 (7~68) winsize 62
801 06:48:36.121438 [CA 1] Center 37 (7~68) winsize 62
802 06:48:36.123980 [CA 2] Center 35 (5~66) winsize 62
803 06:48:36.127152 [CA 3] Center 35 (4~66) winsize 63
804 06:48:36.130641 [CA 4] Center 33 (3~64) winsize 62
805 06:48:36.134044 [CA 5] Center 34 (3~65) winsize 63
806 06:48:36.134127
807 06:48:36.137676 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 06:48:36.137758
809 06:48:36.140604 [CATrainingPosCal] consider 2 rank data
810 06:48:36.144585 u2DelayCellTimex100 = 270/100 ps
811 06:48:36.147355 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 06:48:36.150934 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 06:48:36.157793 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
814 06:48:36.161039 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
815 06:48:36.164132 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
816 06:48:36.167764 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 06:48:36.167848
818 06:48:36.170670 CA PerBit enable=1, Macro0, CA PI delay=33
819 06:48:36.170778
820 06:48:36.173830 [CBTSetCACLKResult] CA Dly = 33
821 06:48:36.173903 CS Dly: 5 (0~37)
822 06:48:36.173965
823 06:48:36.177910 ----->DramcWriteLeveling(PI) begin...
824 06:48:36.180482 ==
825 06:48:36.184111 Dram Type= 6, Freq= 0, CH_0, rank 0
826 06:48:36.187954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
827 06:48:36.188036 ==
828 06:48:36.190976 Write leveling (Byte 0): 27 => 27
829 06:48:36.193907 Write leveling (Byte 1): 30 => 30
830 06:48:36.197618 DramcWriteLeveling(PI) end<-----
831 06:48:36.197699
832 06:48:36.197763 ==
833 06:48:36.200355 Dram Type= 6, Freq= 0, CH_0, rank 0
834 06:48:36.204507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
835 06:48:36.204589 ==
836 06:48:36.208822 [Gating] SW mode calibration
837 06:48:36.213888 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 06:48:36.220680 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 06:48:36.224159 0 6 0 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 1)
840 06:48:36.227723 0 6 4 | B1->B0 | 2d2d 2626 | 1 0 | (1 0) (1 0)
841 06:48:36.230692 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 06:48:36.237426 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 06:48:36.241063 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 06:48:36.243776 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 06:48:36.250705 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 06:48:36.253953 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 06:48:36.257207 0 7 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
848 06:48:36.263974 0 7 4 | B1->B0 | 3a3a 3f3f | 0 0 | (1 1) (0 0)
849 06:48:36.267368 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 06:48:36.270676 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 06:48:36.276978 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 06:48:36.280755 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 06:48:36.284142 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 06:48:36.290416 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 06:48:36.294002 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
856 06:48:36.297453 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 06:48:36.303675 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 06:48:36.307185 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 06:48:36.310511 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 06:48:36.314422 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 06:48:36.320627 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 06:48:36.324282 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 06:48:36.327841 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 06:48:36.334497 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 06:48:36.338031 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 06:48:36.340559 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 06:48:36.347204 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 06:48:36.350589 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 06:48:36.354267 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 06:48:36.361216 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 06:48:36.364583 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
872 06:48:36.367819 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
873 06:48:36.370586 Total UI for P1: 0, mck2ui 16
874 06:48:36.374161 best dqsien dly found for B1: ( 0, 10, 0)
875 06:48:36.377926 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
876 06:48:36.380526 Total UI for P1: 0, mck2ui 16
877 06:48:36.384202 best dqsien dly found for B0: ( 0, 10, 2)
878 06:48:36.390664 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
879 06:48:36.394684 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
880 06:48:36.394765
881 06:48:36.397320 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
882 06:48:36.401218 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
883 06:48:36.404526 [Gating] SW calibration Done
884 06:48:36.404607 ==
885 06:48:36.408373 Dram Type= 6, Freq= 0, CH_0, rank 0
886 06:48:36.411462 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
887 06:48:36.411544 ==
888 06:48:36.411608 RX Vref Scan: 0
889 06:48:36.411668
890 06:48:36.414829 RX Vref 0 -> 0, step: 1
891 06:48:36.414910
892 06:48:36.418185 RX Delay -130 -> 252, step: 16
893 06:48:36.421819 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
894 06:48:36.424911 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
895 06:48:36.428573 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
896 06:48:36.434947 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
897 06:48:36.438066 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
898 06:48:36.442472 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
899 06:48:36.444783 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
900 06:48:36.448415 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
901 06:48:36.454828 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
902 06:48:36.458143 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
903 06:48:36.461708 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
904 06:48:36.464649 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
905 06:48:36.468410 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
906 06:48:36.474867 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
907 06:48:36.478216 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
908 06:48:36.481533 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
909 06:48:36.481615 ==
910 06:48:36.484927 Dram Type= 6, Freq= 0, CH_0, rank 0
911 06:48:36.488897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
912 06:48:36.488980 ==
913 06:48:36.491884 DQS Delay:
914 06:48:36.491964 DQS0 = 0, DQS1 = 0
915 06:48:36.494651 DQM Delay:
916 06:48:36.494731 DQM0 = 84, DQM1 = 74
917 06:48:36.494796 DQ Delay:
918 06:48:36.498138 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
919 06:48:36.501342 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
920 06:48:36.504788 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
921 06:48:36.508310 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
922 06:48:36.508392
923 06:48:36.508456
924 06:48:36.511559 ==
925 06:48:36.514662 Dram Type= 6, Freq= 0, CH_0, rank 0
926 06:48:36.517995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
927 06:48:36.518077 ==
928 06:48:36.518142
929 06:48:36.518202
930 06:48:36.521287 TX Vref Scan disable
931 06:48:36.521368 == TX Byte 0 ==
932 06:48:36.524614 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
933 06:48:36.531793 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
934 06:48:36.531901 == TX Byte 1 ==
935 06:48:36.534687 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
936 06:48:36.541358 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
937 06:48:36.541439 ==
938 06:48:36.544974 Dram Type= 6, Freq= 0, CH_0, rank 0
939 06:48:36.547868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 06:48:36.547949 ==
941 06:48:36.561217 TX Vref=22, minBit 0, minWin=27, winSum=442
942 06:48:36.565035 TX Vref=24, minBit 3, minWin=27, winSum=446
943 06:48:36.567950 TX Vref=26, minBit 0, minWin=27, winSum=449
944 06:48:36.571619 TX Vref=28, minBit 1, minWin=28, winSum=452
945 06:48:36.574609 TX Vref=30, minBit 0, minWin=28, winSum=451
946 06:48:36.578012 TX Vref=32, minBit 0, minWin=28, winSum=454
947 06:48:36.584601 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
948 06:48:36.584683
949 06:48:36.587868 Final TX Range 1 Vref 32
950 06:48:36.587950
951 06:48:36.588014 ==
952 06:48:36.591262 Dram Type= 6, Freq= 0, CH_0, rank 0
953 06:48:36.594741 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
954 06:48:36.594823 ==
955 06:48:36.594888
956 06:48:36.598176
957 06:48:36.598257 TX Vref Scan disable
958 06:48:36.601466 == TX Byte 0 ==
959 06:48:36.604353 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
960 06:48:36.607827 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
961 06:48:36.611837 == TX Byte 1 ==
962 06:48:36.614907 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
963 06:48:36.618060 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
964 06:48:36.621724
965 06:48:36.621806 [DATLAT]
966 06:48:36.621870 Freq=800, CH0 RK0
967 06:48:36.621930
968 06:48:36.626274 DATLAT Default: 0xa
969 06:48:36.626355 0, 0xFFFF, sum = 0
970 06:48:36.628448 1, 0xFFFF, sum = 0
971 06:48:36.628571 2, 0xFFFF, sum = 0
972 06:48:36.631234 3, 0xFFFF, sum = 0
973 06:48:36.631316 4, 0xFFFF, sum = 0
974 06:48:36.635305 5, 0xFFFF, sum = 0
975 06:48:36.635388 6, 0xFFFF, sum = 0
976 06:48:36.638246 7, 0xFFFF, sum = 0
977 06:48:36.638328 8, 0x0, sum = 1
978 06:48:36.640973 9, 0x0, sum = 2
979 06:48:36.641055 10, 0x0, sum = 3
980 06:48:36.644596 11, 0x0, sum = 4
981 06:48:36.644678 best_step = 9
982 06:48:36.644783
983 06:48:36.644843 ==
984 06:48:36.648084 Dram Type= 6, Freq= 0, CH_0, rank 0
985 06:48:36.654584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
986 06:48:36.654669 ==
987 06:48:36.654734 RX Vref Scan: 1
988 06:48:36.654794
989 06:48:36.658121 Set Vref Range= 32 -> 127
990 06:48:36.658206
991 06:48:36.661612 RX Vref 32 -> 127, step: 1
992 06:48:36.661696
993 06:48:36.661782 RX Delay -111 -> 252, step: 8
994 06:48:36.664340
995 06:48:36.664424 Set Vref, RX VrefLevel [Byte0]: 32
996 06:48:36.668320 [Byte1]: 32
997 06:48:36.672226
998 06:48:36.672310 Set Vref, RX VrefLevel [Byte0]: 33
999 06:48:36.678811 [Byte1]: 33
1000 06:48:36.678895
1001 06:48:36.681750 Set Vref, RX VrefLevel [Byte0]: 34
1002 06:48:36.685459 [Byte1]: 34
1003 06:48:36.685543
1004 06:48:36.688234 Set Vref, RX VrefLevel [Byte0]: 35
1005 06:48:36.691960 [Byte1]: 35
1006 06:48:36.694944
1007 06:48:36.695028 Set Vref, RX VrefLevel [Byte0]: 36
1008 06:48:36.698511 [Byte1]: 36
1009 06:48:36.702680
1010 06:48:36.702765 Set Vref, RX VrefLevel [Byte0]: 37
1011 06:48:36.706506 [Byte1]: 37
1012 06:48:36.710247
1013 06:48:36.710330 Set Vref, RX VrefLevel [Byte0]: 38
1014 06:48:36.714000 [Byte1]: 38
1015 06:48:36.718642
1016 06:48:36.718726 Set Vref, RX VrefLevel [Byte0]: 39
1017 06:48:36.721386 [Byte1]: 39
1018 06:48:36.726759
1019 06:48:36.726843 Set Vref, RX VrefLevel [Byte0]: 40
1020 06:48:36.729414 [Byte1]: 40
1021 06:48:36.733547
1022 06:48:36.733631 Set Vref, RX VrefLevel [Byte0]: 41
1023 06:48:36.736842 [Byte1]: 41
1024 06:48:36.741211
1025 06:48:36.741299 Set Vref, RX VrefLevel [Byte0]: 42
1026 06:48:36.744307 [Byte1]: 42
1027 06:48:36.748781
1028 06:48:36.748865 Set Vref, RX VrefLevel [Byte0]: 43
1029 06:48:36.752108 [Byte1]: 43
1030 06:48:36.756583
1031 06:48:36.756667 Set Vref, RX VrefLevel [Byte0]: 44
1032 06:48:36.760727 [Byte1]: 44
1033 06:48:36.764060
1034 06:48:36.764168 Set Vref, RX VrefLevel [Byte0]: 45
1035 06:48:36.767407 [Byte1]: 45
1036 06:48:36.772468
1037 06:48:36.772571 Set Vref, RX VrefLevel [Byte0]: 46
1038 06:48:36.775166 [Byte1]: 46
1039 06:48:36.779114
1040 06:48:36.779211 Set Vref, RX VrefLevel [Byte0]: 47
1041 06:48:36.782491 [Byte1]: 47
1042 06:48:36.787292
1043 06:48:36.787372 Set Vref, RX VrefLevel [Byte0]: 48
1044 06:48:36.790350 [Byte1]: 48
1045 06:48:36.795047
1046 06:48:36.795126 Set Vref, RX VrefLevel [Byte0]: 49
1047 06:48:36.798482 [Byte1]: 49
1048 06:48:36.802261
1049 06:48:36.802341 Set Vref, RX VrefLevel [Byte0]: 50
1050 06:48:36.805485 [Byte1]: 50
1051 06:48:36.809615
1052 06:48:36.809695 Set Vref, RX VrefLevel [Byte0]: 51
1053 06:48:36.813483 [Byte1]: 51
1054 06:48:36.817460
1055 06:48:36.817540 Set Vref, RX VrefLevel [Byte0]: 52
1056 06:48:36.820802 [Byte1]: 52
1057 06:48:36.825301
1058 06:48:36.825381 Set Vref, RX VrefLevel [Byte0]: 53
1059 06:48:36.828751 [Byte1]: 53
1060 06:48:36.833001
1061 06:48:36.833083 Set Vref, RX VrefLevel [Byte0]: 54
1062 06:48:36.836049 [Byte1]: 54
1063 06:48:36.840460
1064 06:48:36.844167 Set Vref, RX VrefLevel [Byte0]: 55
1065 06:48:36.844249 [Byte1]: 55
1066 06:48:36.848311
1067 06:48:36.848392 Set Vref, RX VrefLevel [Byte0]: 56
1068 06:48:36.851923 [Byte1]: 56
1069 06:48:36.856459
1070 06:48:36.856543 Set Vref, RX VrefLevel [Byte0]: 57
1071 06:48:36.859285 [Byte1]: 57
1072 06:48:36.863879
1073 06:48:36.863960 Set Vref, RX VrefLevel [Byte0]: 58
1074 06:48:36.866820 [Byte1]: 58
1075 06:48:36.871973
1076 06:48:36.872079 Set Vref, RX VrefLevel [Byte0]: 59
1077 06:48:36.874348 [Byte1]: 59
1078 06:48:36.878800
1079 06:48:36.878879 Set Vref, RX VrefLevel [Byte0]: 60
1080 06:48:36.882134 [Byte1]: 60
1081 06:48:36.887025
1082 06:48:36.887105 Set Vref, RX VrefLevel [Byte0]: 61
1083 06:48:36.889917 [Byte1]: 61
1084 06:48:36.895179
1085 06:48:36.895262 Set Vref, RX VrefLevel [Byte0]: 62
1086 06:48:36.897330 [Byte1]: 62
1087 06:48:36.902050
1088 06:48:36.902130 Set Vref, RX VrefLevel [Byte0]: 63
1089 06:48:36.904964 [Byte1]: 63
1090 06:48:36.909532
1091 06:48:36.909612 Set Vref, RX VrefLevel [Byte0]: 64
1092 06:48:36.912871 [Byte1]: 64
1093 06:48:36.916810
1094 06:48:36.916890 Set Vref, RX VrefLevel [Byte0]: 65
1095 06:48:36.920533 [Byte1]: 65
1096 06:48:36.924450
1097 06:48:36.924529 Set Vref, RX VrefLevel [Byte0]: 66
1098 06:48:36.927778 [Byte1]: 66
1099 06:48:36.932212
1100 06:48:36.932292 Set Vref, RX VrefLevel [Byte0]: 67
1101 06:48:36.935670 [Byte1]: 67
1102 06:48:36.939998
1103 06:48:36.940078 Set Vref, RX VrefLevel [Byte0]: 68
1104 06:48:36.943306 [Byte1]: 68
1105 06:48:36.947554
1106 06:48:36.947634 Set Vref, RX VrefLevel [Byte0]: 69
1107 06:48:36.951009 [Byte1]: 69
1108 06:48:36.954933
1109 06:48:36.955013 Set Vref, RX VrefLevel [Byte0]: 70
1110 06:48:36.958652 [Byte1]: 70
1111 06:48:36.962805
1112 06:48:36.962885 Set Vref, RX VrefLevel [Byte0]: 71
1113 06:48:36.966181 [Byte1]: 71
1114 06:48:36.970543
1115 06:48:36.970623 Set Vref, RX VrefLevel [Byte0]: 72
1116 06:48:36.974123 [Byte1]: 72
1117 06:48:36.977906
1118 06:48:36.977986 Final RX Vref Byte 0 = 53 to rank0
1119 06:48:36.982023 Final RX Vref Byte 1 = 56 to rank0
1120 06:48:36.985907 Final RX Vref Byte 0 = 53 to rank1
1121 06:48:36.989371 Final RX Vref Byte 1 = 56 to rank1==
1122 06:48:36.991306 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 06:48:36.998918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1124 06:48:36.998999 ==
1125 06:48:36.999063 DQS Delay:
1126 06:48:36.999122 DQS0 = 0, DQS1 = 0
1127 06:48:37.001354 DQM Delay:
1128 06:48:37.001434 DQM0 = 83, DQM1 = 73
1129 06:48:37.004902 DQ Delay:
1130 06:48:37.008219 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1131 06:48:37.008299 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1132 06:48:37.011691 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1133 06:48:37.015115 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1134 06:48:37.018154
1135 06:48:37.018233
1136 06:48:37.024716 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1137 06:48:37.027864 CH0 RK0: MR19=606, MR18=3838
1138 06:48:37.034745 CH0_RK0: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1139 06:48:37.034827
1140 06:48:37.038862 ----->DramcWriteLeveling(PI) begin...
1141 06:48:37.038943 ==
1142 06:48:37.041521 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 06:48:37.044917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1144 06:48:37.044998 ==
1145 06:48:37.048013 Write leveling (Byte 0): 30 => 30
1146 06:48:37.051594 Write leveling (Byte 1): 27 => 27
1147 06:48:37.055413 DramcWriteLeveling(PI) end<-----
1148 06:48:37.055498
1149 06:48:37.055562 ==
1150 06:48:37.059181 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 06:48:37.062006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1152 06:48:37.062086 ==
1153 06:48:37.065081 [Gating] SW mode calibration
1154 06:48:37.071892 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 06:48:37.078195 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 06:48:37.081434 0 6 0 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 1)
1157 06:48:37.086038 0 6 4 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
1158 06:48:37.091901 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 06:48:37.095319 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 06:48:37.098840 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 06:48:37.105193 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 06:48:37.108255 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 06:48:37.111584 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 06:48:37.115324 0 7 0 | B1->B0 | 2b2b 2d2d | 0 0 | (0 0) (0 0)
1165 06:48:37.121505 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1166 06:48:37.125115 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1167 06:48:37.128301 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1168 06:48:37.135114 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1169 06:48:37.138412 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1170 06:48:37.142056 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1171 06:48:37.148824 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1172 06:48:37.151602 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1173 06:48:37.155173 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1174 06:48:37.161328 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1175 06:48:37.165094 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1176 06:48:37.167930 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1177 06:48:37.174654 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1178 06:48:37.178782 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1179 06:48:37.181661 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1180 06:48:37.188198 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1181 06:48:37.191065 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1182 06:48:37.194523 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1183 06:48:37.201158 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1184 06:48:37.204680 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1185 06:48:37.208255 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1186 06:48:37.214510 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1187 06:48:37.217987 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1188 06:48:37.221004 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1189 06:48:37.228749 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1190 06:48:37.231431 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 06:48:37.234738 Total UI for P1: 0, mck2ui 16
1192 06:48:37.237784 best dqsien dly found for B0: ( 0, 10, 4)
1193 06:48:37.241650 Total UI for P1: 0, mck2ui 16
1194 06:48:37.244565 best dqsien dly found for B1: ( 0, 10, 4)
1195 06:48:37.248097 best DQS0 dly(MCK, UI, PI) = (0, 10, 4)
1196 06:48:37.251151 best DQS1 dly(MCK, UI, PI) = (0, 10, 4)
1197 06:48:37.251232
1198 06:48:37.254951 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 4)
1199 06:48:37.257865 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 4)
1200 06:48:37.261668 [Gating] SW calibration Done
1201 06:48:37.261750 ==
1202 06:48:37.265076 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 06:48:37.268242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1204 06:48:37.268349 ==
1205 06:48:37.271738 RX Vref Scan: 0
1206 06:48:37.271820
1207 06:48:37.271885 RX Vref 0 -> 0, step: 1
1208 06:48:37.271945
1209 06:48:37.274559 RX Delay -130 -> 252, step: 16
1210 06:48:37.281679 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1211 06:48:37.285050 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1212 06:48:37.328842 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1213 06:48:37.328926 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1214 06:48:37.329176 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1215 06:48:37.329653 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1216 06:48:37.330251 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1217 06:48:37.330336 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1218 06:48:37.330585 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1219 06:48:37.331427 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1220 06:48:37.331990 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1221 06:48:37.332072 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1222 06:48:37.332472 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1223 06:48:37.334647 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1224 06:48:37.334729 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1225 06:48:37.341546 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1226 06:48:37.341627 ==
1227 06:48:37.345582 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 06:48:37.347567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1229 06:48:37.347649 ==
1230 06:48:37.347714 DQS Delay:
1231 06:48:37.351488 DQS0 = 0, DQS1 = 0
1232 06:48:37.351570 DQM Delay:
1233 06:48:37.354748 DQM0 = 82, DQM1 = 74
1234 06:48:37.354829 DQ Delay:
1235 06:48:37.357513 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1236 06:48:37.361091 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1237 06:48:37.364116 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1238 06:48:37.368357 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1239 06:48:37.368465
1240 06:48:37.368557
1241 06:48:37.368654 ==
1242 06:48:37.371117 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 06:48:37.374448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1244 06:48:37.374531 ==
1245 06:48:37.374596
1246 06:48:37.377666
1247 06:48:37.377747 TX Vref Scan disable
1248 06:48:37.380995 == TX Byte 0 ==
1249 06:48:37.384150 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1250 06:48:37.387826 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1251 06:48:37.390805 == TX Byte 1 ==
1252 06:48:37.394193 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1253 06:48:37.398252 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1254 06:48:37.398347 ==
1255 06:48:37.401017 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 06:48:37.408105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1257 06:48:37.408187 ==
1258 06:48:37.419369 TX Vref=22, minBit 9, minWin=26, winSum=443
1259 06:48:37.423290 TX Vref=24, minBit 9, minWin=27, winSum=449
1260 06:48:37.426242 TX Vref=26, minBit 14, minWin=27, winSum=452
1261 06:48:37.429753 TX Vref=28, minBit 2, minWin=28, winSum=455
1262 06:48:37.432671 TX Vref=30, minBit 2, minWin=28, winSum=458
1263 06:48:37.439290 TX Vref=32, minBit 2, minWin=28, winSum=456
1264 06:48:37.442720 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 30
1265 06:48:37.442802
1266 06:48:37.445856 Final TX Range 1 Vref 30
1267 06:48:37.445938
1268 06:48:37.446003 ==
1269 06:48:37.449483 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 06:48:37.452769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1271 06:48:37.452852 ==
1272 06:48:37.456321
1273 06:48:37.456402
1274 06:48:37.456466 TX Vref Scan disable
1275 06:48:37.459928 == TX Byte 0 ==
1276 06:48:37.463179 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1277 06:48:37.466272 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1278 06:48:37.470485 == TX Byte 1 ==
1279 06:48:37.473528 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1280 06:48:37.479456 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1281 06:48:37.479538
1282 06:48:37.479603 [DATLAT]
1283 06:48:37.479663 Freq=800, CH0 RK1
1284 06:48:37.479722
1285 06:48:37.483098 DATLAT Default: 0x9
1286 06:48:37.483180 0, 0xFFFF, sum = 0
1287 06:48:37.487162 1, 0xFFFF, sum = 0
1288 06:48:37.487245 2, 0xFFFF, sum = 0
1289 06:48:37.489610 3, 0xFFFF, sum = 0
1290 06:48:37.493146 4, 0xFFFF, sum = 0
1291 06:48:37.493229 5, 0xFFFF, sum = 0
1292 06:48:37.496540 6, 0xFFFF, sum = 0
1293 06:48:37.496622 7, 0xFFFF, sum = 0
1294 06:48:37.499435 8, 0x0, sum = 1
1295 06:48:37.499519 9, 0x0, sum = 2
1296 06:48:37.499585 10, 0x0, sum = 3
1297 06:48:37.502743 11, 0x0, sum = 4
1298 06:48:37.502827 best_step = 9
1299 06:48:37.502891
1300 06:48:37.502950 ==
1301 06:48:37.506940 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 06:48:37.512814 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1303 06:48:37.512896 ==
1304 06:48:37.512961 RX Vref Scan: 0
1305 06:48:37.513021
1306 06:48:37.516431 RX Vref 0 -> 0, step: 1
1307 06:48:37.516549
1308 06:48:37.519641 RX Delay -95 -> 252, step: 8
1309 06:48:37.522636 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1310 06:48:37.526267 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1311 06:48:37.532536 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1312 06:48:37.535884 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1313 06:48:37.539653 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1314 06:48:37.542447 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1315 06:48:37.547397 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1316 06:48:37.553268 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1317 06:48:37.556937 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1318 06:48:37.559239 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1319 06:48:37.562482 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1320 06:48:37.566390 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1321 06:48:37.572569 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1322 06:48:37.576430 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1323 06:48:37.579787 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1324 06:48:37.582857 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1325 06:48:37.582938 ==
1326 06:48:37.586016 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 06:48:37.589888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1328 06:48:37.593168 ==
1329 06:48:37.593250 DQS Delay:
1330 06:48:37.593315 DQS0 = 0, DQS1 = 0
1331 06:48:37.596894 DQM Delay:
1332 06:48:37.596975 DQM0 = 86, DQM1 = 74
1333 06:48:37.599845 DQ Delay:
1334 06:48:37.599926 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =80
1335 06:48:37.602825 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1336 06:48:37.606418 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1337 06:48:37.609724 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1338 06:48:37.609806
1339 06:48:37.612527
1340 06:48:37.620483 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1341 06:48:37.622953 CH0 RK1: MR19=606, MR18=4C4C
1342 06:48:37.630147 CH0_RK1: MR19=0x606, MR18=0x4C4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1343 06:48:37.630265 [RxdqsGatingPostProcess] freq 800
1344 06:48:37.636752 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1345 06:48:37.639688 Pre-setting of DQS Precalculation
1346 06:48:37.642734 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1347 06:48:37.646034 ==
1348 06:48:37.646114 Dram Type= 6, Freq= 0, CH_1, rank 0
1349 06:48:37.652913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1350 06:48:37.652995 ==
1351 06:48:37.656585 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1352 06:48:37.663077 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1353 06:48:37.672308 [CA 0] Center 37 (6~68) winsize 63
1354 06:48:37.675679 [CA 1] Center 37 (6~68) winsize 63
1355 06:48:37.679054 [CA 2] Center 34 (4~65) winsize 62
1356 06:48:37.683237 [CA 3] Center 34 (4~65) winsize 62
1357 06:48:37.685623 [CA 4] Center 33 (3~64) winsize 62
1358 06:48:37.689205 [CA 5] Center 33 (3~64) winsize 62
1359 06:48:37.689286
1360 06:48:37.692117 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1361 06:48:37.692197
1362 06:48:37.696184 [CATrainingPosCal] consider 1 rank data
1363 06:48:37.698968 u2DelayCellTimex100 = 270/100 ps
1364 06:48:37.702401 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1365 06:48:37.705394 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1366 06:48:37.712534 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1367 06:48:37.715512 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1368 06:48:37.718949 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1369 06:48:37.722017 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1370 06:48:37.722097
1371 06:48:37.725918 CA PerBit enable=1, Macro0, CA PI delay=33
1372 06:48:37.725999
1373 06:48:37.728728 [CBTSetCACLKResult] CA Dly = 33
1374 06:48:37.728824 CS Dly: 5 (0~36)
1375 06:48:37.728888 ==
1376 06:48:37.732222 Dram Type= 6, Freq= 0, CH_1, rank 1
1377 06:48:37.739179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1378 06:48:37.739260 ==
1379 06:48:37.742588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 06:48:37.749115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 06:48:37.758232 [CA 0] Center 37 (6~68) winsize 63
1382 06:48:37.761371 [CA 1] Center 37 (6~68) winsize 63
1383 06:48:37.765114 [CA 2] Center 34 (4~65) winsize 62
1384 06:48:37.768239 [CA 3] Center 34 (4~65) winsize 62
1385 06:48:37.771615 [CA 4] Center 33 (3~64) winsize 62
1386 06:48:37.774856 [CA 5] Center 33 (3~64) winsize 62
1387 06:48:37.774937
1388 06:48:37.778341 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1389 06:48:37.778422
1390 06:48:37.781584 [CATrainingPosCal] consider 2 rank data
1391 06:48:37.784714 u2DelayCellTimex100 = 270/100 ps
1392 06:48:37.788386 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1393 06:48:37.791970 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1394 06:48:37.798437 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 06:48:37.801395 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 06:48:37.804941 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 06:48:37.808286 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 06:48:37.808367
1399 06:48:37.812185 CA PerBit enable=1, Macro0, CA PI delay=33
1400 06:48:37.812267
1401 06:48:37.814966 [CBTSetCACLKResult] CA Dly = 33
1402 06:48:37.815046 CS Dly: 5 (0~36)
1403 06:48:37.815111
1404 06:48:37.818010 ----->DramcWriteLeveling(PI) begin...
1405 06:48:37.821889 ==
1406 06:48:37.821970 Dram Type= 6, Freq= 0, CH_1, rank 0
1407 06:48:37.828893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1408 06:48:37.828974 ==
1409 06:48:37.831512 Write leveling (Byte 0): 25 => 25
1410 06:48:37.834615 Write leveling (Byte 1): 23 => 23
1411 06:48:37.837944 DramcWriteLeveling(PI) end<-----
1412 06:48:37.838025
1413 06:48:37.838088 ==
1414 06:48:37.841585 Dram Type= 6, Freq= 0, CH_1, rank 0
1415 06:48:37.844700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1416 06:48:37.844819 ==
1417 06:48:37.847817 [Gating] SW mode calibration
1418 06:48:37.855150 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1419 06:48:37.858077 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1420 06:48:37.864528 0 6 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1421 06:48:37.868040 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1422 06:48:37.870932 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1423 06:48:37.877667 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1424 06:48:37.881388 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1425 06:48:37.884251 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1426 06:48:37.890807 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1427 06:48:37.894182 0 6 28 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
1428 06:48:37.897452 0 7 0 | B1->B0 | 2b2b 3d3d | 0 1 | (0 0) (1 1)
1429 06:48:37.904632 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1430 06:48:37.907752 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1431 06:48:37.911640 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1432 06:48:37.917442 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1433 06:48:37.921439 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1434 06:48:37.923998 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1435 06:48:37.930718 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1436 06:48:37.934492 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1437 06:48:37.937335 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1438 06:48:37.943840 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1439 06:48:37.948147 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1440 06:48:37.950841 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1441 06:48:37.957541 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1442 06:48:37.960725 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1443 06:48:37.964496 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1444 06:48:37.970760 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1445 06:48:37.974520 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1446 06:48:37.977344 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1447 06:48:37.980914 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1448 06:48:37.988352 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1449 06:48:37.991159 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1450 06:48:37.994122 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1451 06:48:38.001751 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1452 06:48:38.004633 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1453 06:48:38.007514 Total UI for P1: 0, mck2ui 16
1454 06:48:38.010726 best dqsien dly found for B0: ( 0, 9, 30)
1455 06:48:38.014197 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1456 06:48:38.017701 Total UI for P1: 0, mck2ui 16
1457 06:48:38.021088 best dqsien dly found for B1: ( 0, 10, 0)
1458 06:48:38.024261 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1459 06:48:38.027793 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1460 06:48:38.027875
1461 06:48:38.034383 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1462 06:48:38.037509 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1463 06:48:38.041045 [Gating] SW calibration Done
1464 06:48:38.041127 ==
1465 06:48:38.044004 Dram Type= 6, Freq= 0, CH_1, rank 0
1466 06:48:38.047751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1467 06:48:38.047833 ==
1468 06:48:38.047898 RX Vref Scan: 0
1469 06:48:38.047958
1470 06:48:38.051413 RX Vref 0 -> 0, step: 1
1471 06:48:38.051494
1472 06:48:38.054369 RX Delay -130 -> 252, step: 16
1473 06:48:38.057671 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1474 06:48:38.061079 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1475 06:48:38.067491 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1476 06:48:38.071086 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1477 06:48:38.075026 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1478 06:48:38.077939 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1479 06:48:38.081119 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1480 06:48:38.084045 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1481 06:48:38.091184 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1482 06:48:38.094553 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1483 06:48:38.097658 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1484 06:48:38.101740 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1485 06:48:38.107340 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1486 06:48:38.110859 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1487 06:48:38.114162 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1488 06:48:38.117448 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1489 06:48:38.117556 ==
1490 06:48:38.121095 Dram Type= 6, Freq= 0, CH_1, rank 0
1491 06:48:38.124436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1492 06:48:38.127536 ==
1493 06:48:38.127618 DQS Delay:
1494 06:48:38.127683 DQS0 = 0, DQS1 = 0
1495 06:48:38.131063 DQM Delay:
1496 06:48:38.131201 DQM0 = 81, DQM1 = 73
1497 06:48:38.133979 DQ Delay:
1498 06:48:38.134087 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1499 06:48:38.138334 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1500 06:48:38.141370 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1501 06:48:38.144634 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1502 06:48:38.144741
1503 06:48:38.147665
1504 06:48:38.147747 ==
1505 06:48:38.150986 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 06:48:38.154450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1507 06:48:38.154532 ==
1508 06:48:38.154597
1509 06:48:38.154657
1510 06:48:38.157218 TX Vref Scan disable
1511 06:48:38.157299 == TX Byte 0 ==
1512 06:48:38.164264 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1513 06:48:38.167569 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1514 06:48:38.167651 == TX Byte 1 ==
1515 06:48:38.174516 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1516 06:48:38.177412 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1517 06:48:38.177494 ==
1518 06:48:38.180998 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 06:48:38.184195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1520 06:48:38.184277 ==
1521 06:48:38.198038 TX Vref=22, minBit 3, minWin=27, winSum=448
1522 06:48:38.201622 TX Vref=24, minBit 3, minWin=27, winSum=448
1523 06:48:38.204004 TX Vref=26, minBit 0, minWin=28, winSum=454
1524 06:48:38.207934 TX Vref=28, minBit 0, minWin=28, winSum=459
1525 06:48:38.211068 TX Vref=30, minBit 0, minWin=28, winSum=456
1526 06:48:38.214040 TX Vref=32, minBit 0, minWin=28, winSum=455
1527 06:48:38.220759 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
1528 06:48:38.220841
1529 06:48:38.224687 Final TX Range 1 Vref 28
1530 06:48:38.224804
1531 06:48:38.224868 ==
1532 06:48:38.227955 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 06:48:38.230718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1534 06:48:38.230800 ==
1535 06:48:38.230865
1536 06:48:38.230925
1537 06:48:38.234263 TX Vref Scan disable
1538 06:48:38.238067 == TX Byte 0 ==
1539 06:48:38.241024 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1540 06:48:38.245187 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1541 06:48:38.247648 == TX Byte 1 ==
1542 06:48:38.251075 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1543 06:48:38.254547 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1544 06:48:38.254629
1545 06:48:38.257876 [DATLAT]
1546 06:48:38.257958 Freq=800, CH1 RK0
1547 06:48:38.258023
1548 06:48:38.261474 DATLAT Default: 0xa
1549 06:48:38.261555 0, 0xFFFF, sum = 0
1550 06:48:38.264486 1, 0xFFFF, sum = 0
1551 06:48:38.264569 2, 0xFFFF, sum = 0
1552 06:48:38.267727 3, 0xFFFF, sum = 0
1553 06:48:38.267810 4, 0xFFFF, sum = 0
1554 06:48:38.271433 5, 0xFFFF, sum = 0
1555 06:48:38.271516 6, 0xFFFF, sum = 0
1556 06:48:38.274318 7, 0xFFFF, sum = 0
1557 06:48:38.274400 8, 0x0, sum = 1
1558 06:48:38.277720 9, 0x0, sum = 2
1559 06:48:38.277803 10, 0x0, sum = 3
1560 06:48:38.280807 11, 0x0, sum = 4
1561 06:48:38.280890 best_step = 9
1562 06:48:38.280954
1563 06:48:38.281015 ==
1564 06:48:38.284234 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 06:48:38.291826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1566 06:48:38.291909 ==
1567 06:48:38.291973 RX Vref Scan: 1
1568 06:48:38.292037
1569 06:48:38.294661 Set Vref Range= 32 -> 127
1570 06:48:38.294743
1571 06:48:38.297621 RX Vref 32 -> 127, step: 1
1572 06:48:38.297702
1573 06:48:38.297766 RX Delay -111 -> 252, step: 8
1574 06:48:38.301602
1575 06:48:38.301683 Set Vref, RX VrefLevel [Byte0]: 32
1576 06:48:38.303951 [Byte1]: 32
1577 06:48:38.308474
1578 06:48:38.308556 Set Vref, RX VrefLevel [Byte0]: 33
1579 06:48:38.312209 [Byte1]: 33
1580 06:48:38.316654
1581 06:48:38.316756 Set Vref, RX VrefLevel [Byte0]: 34
1582 06:48:38.320019 [Byte1]: 34
1583 06:48:38.324233
1584 06:48:38.324315 Set Vref, RX VrefLevel [Byte0]: 35
1585 06:48:38.326787 [Byte1]: 35
1586 06:48:38.331116
1587 06:48:38.331197 Set Vref, RX VrefLevel [Byte0]: 36
1588 06:48:38.335006 [Byte1]: 36
1589 06:48:38.338913
1590 06:48:38.338994 Set Vref, RX VrefLevel [Byte0]: 37
1591 06:48:38.343148 [Byte1]: 37
1592 06:48:38.346963
1593 06:48:38.347044 Set Vref, RX VrefLevel [Byte0]: 38
1594 06:48:38.350206 [Byte1]: 38
1595 06:48:38.354803
1596 06:48:38.354885 Set Vref, RX VrefLevel [Byte0]: 39
1597 06:48:38.357283 [Byte1]: 39
1598 06:48:38.362085
1599 06:48:38.362167 Set Vref, RX VrefLevel [Byte0]: 40
1600 06:48:38.365606 [Byte1]: 40
1601 06:48:38.371122
1602 06:48:38.371205 Set Vref, RX VrefLevel [Byte0]: 41
1603 06:48:38.373388 [Byte1]: 41
1604 06:48:38.377098
1605 06:48:38.377175 Set Vref, RX VrefLevel [Byte0]: 42
1606 06:48:38.381745 [Byte1]: 42
1607 06:48:38.384860
1608 06:48:38.384933 Set Vref, RX VrefLevel [Byte0]: 43
1609 06:48:38.388026 [Byte1]: 43
1610 06:48:38.392474
1611 06:48:38.392549 Set Vref, RX VrefLevel [Byte0]: 44
1612 06:48:38.396142 [Byte1]: 44
1613 06:48:38.400107
1614 06:48:38.400182 Set Vref, RX VrefLevel [Byte0]: 45
1615 06:48:38.403713 [Byte1]: 45
1616 06:48:38.408005
1617 06:48:38.408077 Set Vref, RX VrefLevel [Byte0]: 46
1618 06:48:38.411948 [Byte1]: 46
1619 06:48:38.415729
1620 06:48:38.415801 Set Vref, RX VrefLevel [Byte0]: 47
1621 06:48:38.419380 [Byte1]: 47
1622 06:48:38.423213
1623 06:48:38.423291 Set Vref, RX VrefLevel [Byte0]: 48
1624 06:48:38.426155 [Byte1]: 48
1625 06:48:38.431308
1626 06:48:38.431391 Set Vref, RX VrefLevel [Byte0]: 49
1627 06:48:38.434159 [Byte1]: 49
1628 06:48:38.438444
1629 06:48:38.438519 Set Vref, RX VrefLevel [Byte0]: 50
1630 06:48:38.441718 [Byte1]: 50
1631 06:48:38.446117
1632 06:48:38.446192 Set Vref, RX VrefLevel [Byte0]: 51
1633 06:48:38.449758 [Byte1]: 51
1634 06:48:38.453735
1635 06:48:38.453810 Set Vref, RX VrefLevel [Byte0]: 52
1636 06:48:38.457476 [Byte1]: 52
1637 06:48:38.461522
1638 06:48:38.461598 Set Vref, RX VrefLevel [Byte0]: 53
1639 06:48:38.466067 [Byte1]: 53
1640 06:48:38.469742
1641 06:48:38.469818 Set Vref, RX VrefLevel [Byte0]: 54
1642 06:48:38.472555 [Byte1]: 54
1643 06:48:38.476429
1644 06:48:38.476507 Set Vref, RX VrefLevel [Byte0]: 55
1645 06:48:38.480904 [Byte1]: 55
1646 06:48:38.484649
1647 06:48:38.484729 Set Vref, RX VrefLevel [Byte0]: 56
1648 06:48:38.487508 [Byte1]: 56
1649 06:48:38.491831
1650 06:48:38.491907 Set Vref, RX VrefLevel [Byte0]: 57
1651 06:48:38.495301 [Byte1]: 57
1652 06:48:38.499513
1653 06:48:38.499594 Set Vref, RX VrefLevel [Byte0]: 58
1654 06:48:38.502804 [Byte1]: 58
1655 06:48:38.507148
1656 06:48:38.507229 Set Vref, RX VrefLevel [Byte0]: 59
1657 06:48:38.510564 [Byte1]: 59
1658 06:48:38.516378
1659 06:48:38.516454 Set Vref, RX VrefLevel [Byte0]: 60
1660 06:48:38.518244 [Byte1]: 60
1661 06:48:38.522403
1662 06:48:38.522481 Set Vref, RX VrefLevel [Byte0]: 61
1663 06:48:38.526497 [Byte1]: 61
1664 06:48:38.530558
1665 06:48:38.530632 Set Vref, RX VrefLevel [Byte0]: 62
1666 06:48:38.533851 [Byte1]: 62
1667 06:48:38.537664
1668 06:48:38.537745 Set Vref, RX VrefLevel [Byte0]: 63
1669 06:48:38.541318 [Byte1]: 63
1670 06:48:38.545756
1671 06:48:38.545837 Set Vref, RX VrefLevel [Byte0]: 64
1672 06:48:38.548955 [Byte1]: 64
1673 06:48:38.552988
1674 06:48:38.553070 Set Vref, RX VrefLevel [Byte0]: 65
1675 06:48:38.556740 [Byte1]: 65
1676 06:48:38.560637
1677 06:48:38.560741 Set Vref, RX VrefLevel [Byte0]: 66
1678 06:48:38.563817 [Byte1]: 66
1679 06:48:38.568854
1680 06:48:38.568975 Set Vref, RX VrefLevel [Byte0]: 67
1681 06:48:38.571989 [Byte1]: 67
1682 06:48:38.576009
1683 06:48:38.576091 Set Vref, RX VrefLevel [Byte0]: 68
1684 06:48:38.579180 [Byte1]: 68
1685 06:48:38.584205
1686 06:48:38.584283 Set Vref, RX VrefLevel [Byte0]: 69
1687 06:48:38.588132 [Byte1]: 69
1688 06:48:38.591279
1689 06:48:38.591356 Set Vref, RX VrefLevel [Byte0]: 70
1690 06:48:38.595407 [Byte1]: 70
1691 06:48:38.600311
1692 06:48:38.600387 Set Vref, RX VrefLevel [Byte0]: 71
1693 06:48:38.602228 [Byte1]: 71
1694 06:48:38.606637
1695 06:48:38.606711 Set Vref, RX VrefLevel [Byte0]: 72
1696 06:48:38.610052 [Byte1]: 72
1697 06:48:38.614996
1698 06:48:38.615072 Set Vref, RX VrefLevel [Byte0]: 73
1699 06:48:38.617556 [Byte1]: 73
1700 06:48:38.622351
1701 06:48:38.622432 Set Vref, RX VrefLevel [Byte0]: 74
1702 06:48:38.625179 [Byte1]: 74
1703 06:48:38.629914
1704 06:48:38.630001 Set Vref, RX VrefLevel [Byte0]: 75
1705 06:48:38.633206 [Byte1]: 75
1706 06:48:38.637988
1707 06:48:38.638068 Final RX Vref Byte 0 = 59 to rank0
1708 06:48:38.640620 Final RX Vref Byte 1 = 60 to rank0
1709 06:48:38.644311 Final RX Vref Byte 0 = 59 to rank1
1710 06:48:38.647471 Final RX Vref Byte 1 = 60 to rank1==
1711 06:48:38.650465 Dram Type= 6, Freq= 0, CH_1, rank 0
1712 06:48:38.657285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1713 06:48:38.657366 ==
1714 06:48:38.657433 DQS Delay:
1715 06:48:38.660351 DQS0 = 0, DQS1 = 0
1716 06:48:38.660431 DQM Delay:
1717 06:48:38.660494 DQM0 = 81, DQM1 = 74
1718 06:48:38.664342 DQ Delay:
1719 06:48:38.666790 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1720 06:48:38.670355 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1721 06:48:38.674418 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1722 06:48:38.676932 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1723 06:48:38.677012
1724 06:48:38.677076
1725 06:48:38.683508 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e4e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1726 06:48:38.687556 CH1 RK0: MR19=606, MR18=4E4E
1727 06:48:38.693524 CH1_RK0: MR19=0x606, MR18=0x4E4E, DQSOSC=390, MR23=63, INC=97, DEC=64
1728 06:48:38.693645
1729 06:48:38.697496 ----->DramcWriteLeveling(PI) begin...
1730 06:48:38.697577 ==
1731 06:48:38.700953 Dram Type= 6, Freq= 0, CH_1, rank 1
1732 06:48:38.703818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1733 06:48:38.703898 ==
1734 06:48:38.707267 Write leveling (Byte 0): 24 => 24
1735 06:48:38.710045 Write leveling (Byte 1): 26 => 26
1736 06:48:38.713914 DramcWriteLeveling(PI) end<-----
1737 06:48:38.713994
1738 06:48:38.714056 ==
1739 06:48:38.717247 Dram Type= 6, Freq= 0, CH_1, rank 1
1740 06:48:38.720585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1741 06:48:38.720690 ==
1742 06:48:38.723269 [Gating] SW mode calibration
1743 06:48:38.730565 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1744 06:48:38.736824 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1745 06:48:38.740135 0 6 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1746 06:48:38.743935 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1747 06:48:38.750443 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1748 06:48:38.753921 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1749 06:48:38.757054 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1750 06:48:38.764353 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1751 06:48:38.766678 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1752 06:48:38.770304 0 6 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1753 06:48:38.776808 0 7 0 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
1754 06:48:38.780150 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1755 06:48:38.783517 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1756 06:48:38.790486 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1757 06:48:38.793552 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1758 06:48:38.798144 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1759 06:48:38.803962 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1760 06:48:38.807723 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1761 06:48:38.810338 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1762 06:48:38.816632 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1763 06:48:38.820081 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1764 06:48:38.823354 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1765 06:48:38.829885 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1766 06:48:38.834092 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1767 06:48:38.837185 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1768 06:48:38.840106 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1769 06:48:38.846427 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1770 06:48:38.850083 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1771 06:48:38.853843 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1772 06:48:38.859646 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1773 06:48:38.863693 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1774 06:48:38.866913 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1775 06:48:38.873661 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1776 06:48:38.876329 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1777 06:48:38.879941 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1778 06:48:38.883157 Total UI for P1: 0, mck2ui 16
1779 06:48:38.887121 best dqsien dly found for B0: ( 0, 9, 26)
1780 06:48:38.893540 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1781 06:48:38.893621 Total UI for P1: 0, mck2ui 16
1782 06:48:38.899923 best dqsien dly found for B1: ( 0, 10, 0)
1783 06:48:38.903529 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1784 06:48:38.907016 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1785 06:48:38.907096
1786 06:48:38.910577 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1787 06:48:38.913107 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1788 06:48:38.917157 [Gating] SW calibration Done
1789 06:48:38.917237 ==
1790 06:48:38.919976 Dram Type= 6, Freq= 0, CH_1, rank 1
1791 06:48:38.923753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1792 06:48:38.923833 ==
1793 06:48:38.926483 RX Vref Scan: 0
1794 06:48:38.926563
1795 06:48:38.926626 RX Vref 0 -> 0, step: 1
1796 06:48:38.926685
1797 06:48:38.930039 RX Delay -130 -> 252, step: 16
1798 06:48:38.933204 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1799 06:48:38.940268 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1800 06:48:38.943952 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1801 06:48:38.946531 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1802 06:48:38.950395 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1803 06:48:38.953143 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1804 06:48:38.959989 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1805 06:48:38.963530 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1806 06:48:38.966786 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1807 06:48:38.970096 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1808 06:48:38.973479 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1809 06:48:38.980678 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1810 06:48:38.984316 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1811 06:48:38.987505 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1812 06:48:38.989833 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1813 06:48:38.994109 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1814 06:48:38.997209 ==
1815 06:48:39.000212 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 06:48:39.003899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1817 06:48:39.003979 ==
1818 06:48:39.004043 DQS Delay:
1819 06:48:39.007126 DQS0 = 0, DQS1 = 0
1820 06:48:39.007206 DQM Delay:
1821 06:48:39.009996 DQM0 = 85, DQM1 = 73
1822 06:48:39.010076 DQ Delay:
1823 06:48:39.013987 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1824 06:48:39.017153 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1825 06:48:39.020067 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1826 06:48:39.023336 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1827 06:48:39.023415
1828 06:48:39.023479
1829 06:48:39.023538 ==
1830 06:48:39.026973 Dram Type= 6, Freq= 0, CH_1, rank 1
1831 06:48:39.030553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1832 06:48:39.030634 ==
1833 06:48:39.030697
1834 06:48:39.030756
1835 06:48:39.033911 TX Vref Scan disable
1836 06:48:39.036953 == TX Byte 0 ==
1837 06:48:39.040559 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1838 06:48:39.043554 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1839 06:48:39.047728 == TX Byte 1 ==
1840 06:48:39.049921 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1841 06:48:39.053264 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1842 06:48:39.053344 ==
1843 06:48:39.056692 Dram Type= 6, Freq= 0, CH_1, rank 1
1844 06:48:39.059788 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1845 06:48:39.063030 ==
1846 06:48:39.075908 TX Vref=22, minBit 3, minWin=27, winSum=448
1847 06:48:39.078105 TX Vref=24, minBit 0, minWin=27, winSum=448
1848 06:48:39.081405 TX Vref=26, minBit 8, minWin=27, winSum=455
1849 06:48:39.085081 TX Vref=28, minBit 9, minWin=27, winSum=457
1850 06:48:39.088031 TX Vref=30, minBit 5, minWin=28, winSum=459
1851 06:48:39.091546 TX Vref=32, minBit 9, minWin=27, winSum=454
1852 06:48:39.098179 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
1853 06:48:39.098260
1854 06:48:39.101535 Final TX Range 1 Vref 30
1855 06:48:39.101615
1856 06:48:39.101679 ==
1857 06:48:39.104725 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 06:48:39.108366 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1859 06:48:39.108446 ==
1860 06:48:39.108510
1861 06:48:39.108568
1862 06:48:39.111874 TX Vref Scan disable
1863 06:48:39.114964 == TX Byte 0 ==
1864 06:48:39.118683 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1865 06:48:39.122073 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1866 06:48:39.125168 == TX Byte 1 ==
1867 06:48:39.128101 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1868 06:48:39.132115 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1869 06:48:39.132195
1870 06:48:39.134692 [DATLAT]
1871 06:48:39.134791 Freq=800, CH1 RK1
1872 06:48:39.134856
1873 06:48:39.139180 DATLAT Default: 0x9
1874 06:48:39.139260 0, 0xFFFF, sum = 0
1875 06:48:39.141970 1, 0xFFFF, sum = 0
1876 06:48:39.142052 2, 0xFFFF, sum = 0
1877 06:48:39.144928 3, 0xFFFF, sum = 0
1878 06:48:39.145009 4, 0xFFFF, sum = 0
1879 06:48:39.149155 5, 0xFFFF, sum = 0
1880 06:48:39.149237 6, 0xFFFF, sum = 0
1881 06:48:39.151904 7, 0xFFFF, sum = 0
1882 06:48:39.151985 8, 0x0, sum = 1
1883 06:48:39.154914 9, 0x0, sum = 2
1884 06:48:39.154996 10, 0x0, sum = 3
1885 06:48:39.158009 11, 0x0, sum = 4
1886 06:48:39.158091 best_step = 9
1887 06:48:39.158156
1888 06:48:39.158216 ==
1889 06:48:39.161454 Dram Type= 6, Freq= 0, CH_1, rank 1
1890 06:48:39.164635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1891 06:48:39.168623 ==
1892 06:48:39.168702 RX Vref Scan: 0
1893 06:48:39.168807
1894 06:48:39.171585 RX Vref 0 -> 0, step: 1
1895 06:48:39.171676
1896 06:48:39.174602 RX Delay -111 -> 252, step: 8
1897 06:48:39.177990 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1898 06:48:39.181420 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1899 06:48:39.184677 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1900 06:48:39.191239 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1901 06:48:39.194842 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1902 06:48:39.197945 iDelay=217, Bit 5, Center 100 (-15 ~ 216) 232
1903 06:48:39.201998 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1904 06:48:39.204496 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1905 06:48:39.211602 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1906 06:48:39.214476 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1907 06:48:39.218299 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1908 06:48:39.221183 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1909 06:48:39.224847 iDelay=217, Bit 12, Center 88 (-31 ~ 208) 240
1910 06:48:39.232015 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1911 06:48:39.234415 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1912 06:48:39.237990 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1913 06:48:39.238071 ==
1914 06:48:39.240910 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 06:48:39.244875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1916 06:48:39.248336 ==
1917 06:48:39.248441 DQS Delay:
1918 06:48:39.248532 DQS0 = 0, DQS1 = 0
1919 06:48:39.251532 DQM Delay:
1920 06:48:39.251612 DQM0 = 84, DQM1 = 74
1921 06:48:39.254941 DQ Delay:
1922 06:48:39.255021 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =80
1923 06:48:39.257999 DQ4 =84, DQ5 =100, DQ6 =92, DQ7 =80
1924 06:48:39.261263 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1925 06:48:39.265028 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1926 06:48:39.265108
1927 06:48:39.268441
1928 06:48:39.274736 [DQSOSCAuto] RK1, (LSB)MR18= 0x4040, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1929 06:48:39.278164 CH1 RK1: MR19=606, MR18=4040
1930 06:48:39.284356 CH1_RK1: MR19=0x606, MR18=0x4040, DQSOSC=393, MR23=63, INC=95, DEC=63
1931 06:48:39.288636 [RxdqsGatingPostProcess] freq 800
1932 06:48:39.291582 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1933 06:48:39.295122 Pre-setting of DQS Precalculation
1934 06:48:39.298588 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1935 06:48:39.308337 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1936 06:48:39.315058 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1937 06:48:39.315138
1938 06:48:39.315202
1939 06:48:39.317518 [Calibration Summary] 1600 Mbps
1940 06:48:39.317598 CH 0, Rank 0
1941 06:48:39.321036 SW Impedance : PASS
1942 06:48:39.321125 DUTY Scan : NO K
1943 06:48:39.324632 ZQ Calibration : PASS
1944 06:48:39.327381 Jitter Meter : NO K
1945 06:48:39.327460 CBT Training : PASS
1946 06:48:39.331160 Write leveling : PASS
1947 06:48:39.334419 RX DQS gating : PASS
1948 06:48:39.334500 RX DQ/DQS(RDDQC) : PASS
1949 06:48:39.338026 TX DQ/DQS : PASS
1950 06:48:39.341453 RX DATLAT : PASS
1951 06:48:39.341532 RX DQ/DQS(Engine): PASS
1952 06:48:39.344413 TX OE : NO K
1953 06:48:39.344518 All Pass.
1954 06:48:39.344610
1955 06:48:39.348048 CH 0, Rank 1
1956 06:48:39.348129 SW Impedance : PASS
1957 06:48:39.351259 DUTY Scan : NO K
1958 06:48:39.354220 ZQ Calibration : PASS
1959 06:48:39.354332 Jitter Meter : NO K
1960 06:48:39.357488 CBT Training : PASS
1961 06:48:39.361583 Write leveling : PASS
1962 06:48:39.361663 RX DQS gating : PASS
1963 06:48:39.364282 RX DQ/DQS(RDDQC) : PASS
1964 06:48:39.367521 TX DQ/DQS : PASS
1965 06:48:39.367627 RX DATLAT : PASS
1966 06:48:39.370929 RX DQ/DQS(Engine): PASS
1967 06:48:39.371009 TX OE : NO K
1968 06:48:39.373979 All Pass.
1969 06:48:39.374083
1970 06:48:39.374174 CH 1, Rank 0
1971 06:48:39.377330 SW Impedance : PASS
1972 06:48:39.377410 DUTY Scan : NO K
1973 06:48:39.380991 ZQ Calibration : PASS
1974 06:48:39.385078 Jitter Meter : NO K
1975 06:48:39.385158 CBT Training : PASS
1976 06:48:39.387538 Write leveling : PASS
1977 06:48:39.390549 RX DQS gating : PASS
1978 06:48:39.390630 RX DQ/DQS(RDDQC) : PASS
1979 06:48:39.394136 TX DQ/DQS : PASS
1980 06:48:39.397408 RX DATLAT : PASS
1981 06:48:39.397488 RX DQ/DQS(Engine): PASS
1982 06:48:39.401148 TX OE : NO K
1983 06:48:39.401229 All Pass.
1984 06:48:39.401293
1985 06:48:39.404782 CH 1, Rank 1
1986 06:48:39.404862 SW Impedance : PASS
1987 06:48:39.407282 DUTY Scan : NO K
1988 06:48:39.411014 ZQ Calibration : PASS
1989 06:48:39.411094 Jitter Meter : NO K
1990 06:48:39.414284 CBT Training : PASS
1991 06:48:39.414373 Write leveling : PASS
1992 06:48:39.417761 RX DQS gating : PASS
1993 06:48:39.421094 RX DQ/DQS(RDDQC) : PASS
1994 06:48:39.421174 TX DQ/DQS : PASS
1995 06:48:39.424341 RX DATLAT : PASS
1996 06:48:39.427494 RX DQ/DQS(Engine): PASS
1997 06:48:39.427574 TX OE : NO K
1998 06:48:39.431461 All Pass.
1999 06:48:39.431541
2000 06:48:39.431604 DramC Write-DBI off
2001 06:48:39.434479 PER_BANK_REFRESH: Hybrid Mode
2002 06:48:39.434559 TX_TRACKING: ON
2003 06:48:39.437616 [GetDramInforAfterCalByMRR] Vendor 6.
2004 06:48:39.444596 [GetDramInforAfterCalByMRR] Revision 606.
2005 06:48:39.448164 [GetDramInforAfterCalByMRR] Revision 2 0.
2006 06:48:39.448245 MR0 0x3939
2007 06:48:39.448308 MR8 0x1111
2008 06:48:39.451028 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2009 06:48:39.451107
2010 06:48:39.454701 MR0 0x3939
2011 06:48:39.454781 MR8 0x1111
2012 06:48:39.457737 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2013 06:48:39.457817
2014 06:48:39.467824 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2015 06:48:39.470774 [FAST_K] Save calibration result to emmc
2016 06:48:39.474493 [FAST_K] Save calibration result to emmc
2017 06:48:39.477647 dram_init: config_dvfs: 1
2018 06:48:39.481382 dramc_set_vcore_voltage set vcore to 662500
2019 06:48:39.485105 Read voltage for 1200, 2
2020 06:48:39.485184 Vio18 = 0
2021 06:48:39.485247 Vcore = 662500
2022 06:48:39.487133 Vdram = 0
2023 06:48:39.487213 Vddq = 0
2024 06:48:39.487277 Vmddr = 0
2025 06:48:39.494014 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2026 06:48:39.498360 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2027 06:48:39.501259 MEM_TYPE=3, freq_sel=15
2028 06:48:39.504203 sv_algorithm_assistance_LP4_1600
2029 06:48:39.507375 ============ PULL DRAM RESETB DOWN ============
2030 06:48:39.511325 ========== PULL DRAM RESETB DOWN end =========
2031 06:48:39.517646 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2032 06:48:39.520973 ===================================
2033 06:48:39.521053 LPDDR4 DRAM CONFIGURATION
2034 06:48:39.524118 ===================================
2035 06:48:39.527573 EX_ROW_EN[0] = 0x0
2036 06:48:39.530698 EX_ROW_EN[1] = 0x0
2037 06:48:39.530778 LP4Y_EN = 0x0
2038 06:48:39.534056 WORK_FSP = 0x0
2039 06:48:39.534136 WL = 0x4
2040 06:48:39.537811 RL = 0x4
2041 06:48:39.537891 BL = 0x2
2042 06:48:39.541127 RPST = 0x0
2043 06:48:39.541207 RD_PRE = 0x0
2044 06:48:39.544200 WR_PRE = 0x1
2045 06:48:39.544280 WR_PST = 0x0
2046 06:48:39.547325 DBI_WR = 0x0
2047 06:48:39.547405 DBI_RD = 0x0
2048 06:48:39.550785 OTF = 0x1
2049 06:48:39.553927 ===================================
2050 06:48:39.557802 ===================================
2051 06:48:39.557881 ANA top config
2052 06:48:39.561192 ===================================
2053 06:48:39.564627 DLL_ASYNC_EN = 0
2054 06:48:39.567411 ALL_SLAVE_EN = 0
2055 06:48:39.567491 NEW_RANK_MODE = 1
2056 06:48:39.570930 DLL_IDLE_MODE = 1
2057 06:48:39.574275 LP45_APHY_COMB_EN = 1
2058 06:48:39.578066 TX_ODT_DIS = 1
2059 06:48:39.580641 NEW_8X_MODE = 1
2060 06:48:39.583761 ===================================
2061 06:48:39.587665 ===================================
2062 06:48:39.587746 data_rate = 2400
2063 06:48:39.590832 CKR = 1
2064 06:48:39.594556 DQ_P2S_RATIO = 8
2065 06:48:39.597166 ===================================
2066 06:48:39.601144 CA_P2S_RATIO = 8
2067 06:48:39.603759 DQ_CA_OPEN = 0
2068 06:48:39.607287 DQ_SEMI_OPEN = 0
2069 06:48:39.607368 CA_SEMI_OPEN = 0
2070 06:48:39.610716 CA_FULL_RATE = 0
2071 06:48:39.614407 DQ_CKDIV4_EN = 0
2072 06:48:39.617259 CA_CKDIV4_EN = 0
2073 06:48:39.620634 CA_PREDIV_EN = 0
2074 06:48:39.624336 PH8_DLY = 17
2075 06:48:39.624416 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2076 06:48:39.627494 DQ_AAMCK_DIV = 4
2077 06:48:39.630978 CA_AAMCK_DIV = 4
2078 06:48:39.633954 CA_ADMCK_DIV = 4
2079 06:48:39.637661 DQ_TRACK_CA_EN = 0
2080 06:48:39.640950 CA_PICK = 1200
2081 06:48:39.643859 CA_MCKIO = 1200
2082 06:48:39.643939 MCKIO_SEMI = 0
2083 06:48:39.647393 PLL_FREQ = 2366
2084 06:48:39.651221 DQ_UI_PI_RATIO = 32
2085 06:48:39.654119 CA_UI_PI_RATIO = 0
2086 06:48:39.657150 ===================================
2087 06:48:39.660479 ===================================
2088 06:48:39.664003 memory_type:LPDDR4
2089 06:48:39.664083 GP_NUM : 10
2090 06:48:39.667911 SRAM_EN : 1
2091 06:48:39.668015 MD32_EN : 0
2092 06:48:39.670878 ===================================
2093 06:48:39.673919 [ANA_INIT] >>>>>>>>>>>>>>
2094 06:48:39.677893 <<<<<< [CONFIGURE PHASE]: ANA_TX
2095 06:48:39.680438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2096 06:48:39.684636 ===================================
2097 06:48:39.687875 data_rate = 2400,PCW = 0X5b00
2098 06:48:39.690319 ===================================
2099 06:48:39.694154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2100 06:48:39.701253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2101 06:48:39.703662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2102 06:48:39.710448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2103 06:48:39.713655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2104 06:48:39.716930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2105 06:48:39.717010 [ANA_INIT] flow start
2106 06:48:39.720703 [ANA_INIT] PLL >>>>>>>>
2107 06:48:39.723961 [ANA_INIT] PLL <<<<<<<<
2108 06:48:39.724041 [ANA_INIT] MIDPI >>>>>>>>
2109 06:48:39.727647 [ANA_INIT] MIDPI <<<<<<<<
2110 06:48:39.731645 [ANA_INIT] DLL >>>>>>>>
2111 06:48:39.731724 [ANA_INIT] DLL <<<<<<<<
2112 06:48:39.733618 [ANA_INIT] flow end
2113 06:48:39.737221 ============ LP4 DIFF to SE enter ============
2114 06:48:39.740455 ============ LP4 DIFF to SE exit ============
2115 06:48:39.744255 [ANA_INIT] <<<<<<<<<<<<<
2116 06:48:39.747128 [Flow] Enable top DCM control >>>>>
2117 06:48:39.750443 [Flow] Enable top DCM control <<<<<
2118 06:48:39.754388 Enable DLL master slave shuffle
2119 06:48:39.760628 ==============================================================
2120 06:48:39.760731 Gating Mode config
2121 06:48:39.767284 ==============================================================
2122 06:48:39.767364 Config description:
2123 06:48:39.777036 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2124 06:48:39.784122 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2125 06:48:39.790974 SELPH_MODE 0: By rank 1: By Phase
2126 06:48:39.794750 ==============================================================
2127 06:48:39.797043 GAT_TRACK_EN = 1
2128 06:48:39.800218 RX_GATING_MODE = 2
2129 06:48:39.803762 RX_GATING_TRACK_MODE = 2
2130 06:48:39.807445 SELPH_MODE = 1
2131 06:48:39.810297 PICG_EARLY_EN = 1
2132 06:48:39.813780 VALID_LAT_VALUE = 1
2133 06:48:39.820291 ==============================================================
2134 06:48:39.823570 Enter into Gating configuration >>>>
2135 06:48:39.826744 Exit from Gating configuration <<<<
2136 06:48:39.830942 Enter into DVFS_PRE_config >>>>>
2137 06:48:39.840967 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2138 06:48:39.843874 Exit from DVFS_PRE_config <<<<<
2139 06:48:39.846720 Enter into PICG configuration >>>>
2140 06:48:39.850210 Exit from PICG configuration <<<<
2141 06:48:39.850294 [RX_INPUT] configuration >>>>>
2142 06:48:39.853596 [RX_INPUT] configuration <<<<<
2143 06:48:39.860519 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2144 06:48:39.863819 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2145 06:48:39.870842 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2146 06:48:39.877297 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2147 06:48:39.883774 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2148 06:48:39.891067 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2149 06:48:39.893827 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2150 06:48:39.896836 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2151 06:48:39.903719 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2152 06:48:39.907091 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2153 06:48:39.910147 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2154 06:48:39.913592 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2155 06:48:39.916638 ===================================
2156 06:48:39.920373 LPDDR4 DRAM CONFIGURATION
2157 06:48:39.923881 ===================================
2158 06:48:39.926634 EX_ROW_EN[0] = 0x0
2159 06:48:39.926719 EX_ROW_EN[1] = 0x0
2160 06:48:39.930293 LP4Y_EN = 0x0
2161 06:48:39.930376 WORK_FSP = 0x0
2162 06:48:39.933134 WL = 0x4
2163 06:48:39.933218 RL = 0x4
2164 06:48:39.937702 BL = 0x2
2165 06:48:39.937785 RPST = 0x0
2166 06:48:39.940169 RD_PRE = 0x0
2167 06:48:39.940252 WR_PRE = 0x1
2168 06:48:39.943468 WR_PST = 0x0
2169 06:48:39.943552 DBI_WR = 0x0
2170 06:48:39.947312 DBI_RD = 0x0
2171 06:48:39.947396 OTF = 0x1
2172 06:48:39.950251 ===================================
2173 06:48:39.957326 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2174 06:48:39.960105 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2175 06:48:39.963812 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2176 06:48:39.966864 ===================================
2177 06:48:39.970321 LPDDR4 DRAM CONFIGURATION
2178 06:48:39.973520 ===================================
2179 06:48:39.976741 EX_ROW_EN[0] = 0x10
2180 06:48:39.976818 EX_ROW_EN[1] = 0x0
2181 06:48:39.981068 LP4Y_EN = 0x0
2182 06:48:39.981173 WORK_FSP = 0x0
2183 06:48:39.983431 WL = 0x4
2184 06:48:39.983535 RL = 0x4
2185 06:48:39.989159 BL = 0x2
2186 06:48:39.989262 RPST = 0x0
2187 06:48:39.990060 RD_PRE = 0x0
2188 06:48:39.990156 WR_PRE = 0x1
2189 06:48:39.993220 WR_PST = 0x0
2190 06:48:39.993317 DBI_WR = 0x0
2191 06:48:39.997255 DBI_RD = 0x0
2192 06:48:39.997352 OTF = 0x1
2193 06:48:40.000538 ===================================
2194 06:48:40.006765 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2195 06:48:40.006870 ==
2196 06:48:40.011110 Dram Type= 6, Freq= 0, CH_0, rank 0
2197 06:48:40.013247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2198 06:48:40.016581 ==
2199 06:48:40.016685 [Duty_Offset_Calibration]
2200 06:48:40.019757 B0:0 B1:2 CA:1
2201 06:48:40.019855
2202 06:48:40.023541 [DutyScan_Calibration_Flow] k_type=0
2203 06:48:40.031897
2204 06:48:40.031999 ==CLK 0==
2205 06:48:40.034932 Final CLK duty delay cell = 0
2206 06:48:40.038417 [0] MAX Duty = 5093%(X100), DQS PI = 12
2207 06:48:40.041905 [0] MIN Duty = 4938%(X100), DQS PI = 54
2208 06:48:40.042009 [0] AVG Duty = 5015%(X100)
2209 06:48:40.045308
2210 06:48:40.048288 CH0 CLK Duty spec in!! Max-Min= 155%
2211 06:48:40.051830 [DutyScan_Calibration_Flow] ====Done====
2212 06:48:40.051935
2213 06:48:40.055034 [DutyScan_Calibration_Flow] k_type=1
2214 06:48:40.071240
2215 06:48:40.071344 ==DQS 0 ==
2216 06:48:40.074541 Final DQS duty delay cell = 0
2217 06:48:40.077721 [0] MAX Duty = 5125%(X100), DQS PI = 30
2218 06:48:40.081427 [0] MIN Duty = 5031%(X100), DQS PI = 6
2219 06:48:40.084541 [0] AVG Duty = 5078%(X100)
2220 06:48:40.084642
2221 06:48:40.084742 ==DQS 1 ==
2222 06:48:40.087652 Final DQS duty delay cell = 0
2223 06:48:40.090836 [0] MAX Duty = 5062%(X100), DQS PI = 56
2224 06:48:40.094693 [0] MIN Duty = 4906%(X100), DQS PI = 16
2225 06:48:40.097512 [0] AVG Duty = 4984%(X100)
2226 06:48:40.097612
2227 06:48:40.101207 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2228 06:48:40.101283
2229 06:48:40.104284 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2230 06:48:40.107765 [DutyScan_Calibration_Flow] ====Done====
2231 06:48:40.107864
2232 06:48:40.111049 [DutyScan_Calibration_Flow] k_type=3
2233 06:48:40.127940
2234 06:48:40.128045 ==DQM 0 ==
2235 06:48:40.130781 Final DQM duty delay cell = 0
2236 06:48:40.134840 [0] MAX Duty = 5156%(X100), DQS PI = 22
2237 06:48:40.137321 [0] MIN Duty = 4969%(X100), DQS PI = 54
2238 06:48:40.141466 [0] AVG Duty = 5062%(X100)
2239 06:48:40.141568
2240 06:48:40.141660 ==DQM 1 ==
2241 06:48:40.144778 Final DQM duty delay cell = 0
2242 06:48:40.148039 [0] MAX Duty = 5000%(X100), DQS PI = 54
2243 06:48:40.151124 [0] MIN Duty = 4844%(X100), DQS PI = 20
2244 06:48:40.151226 [0] AVG Duty = 4922%(X100)
2245 06:48:40.154361
2246 06:48:40.157933 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2247 06:48:40.158026
2248 06:48:40.161625 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2249 06:48:40.164807 [DutyScan_Calibration_Flow] ====Done====
2250 06:48:40.164884
2251 06:48:40.167993 [DutyScan_Calibration_Flow] k_type=2
2252 06:48:40.182824
2253 06:48:40.182933 ==DQ 0 ==
2254 06:48:40.185728 Final DQ duty delay cell = -4
2255 06:48:40.189316 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2256 06:48:40.192634 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2257 06:48:40.195776 [-4] AVG Duty = 4937%(X100)
2258 06:48:40.195874
2259 06:48:40.195964 ==DQ 1 ==
2260 06:48:40.199806 Final DQ duty delay cell = -4
2261 06:48:40.202810 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2262 06:48:40.206386 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2263 06:48:40.209113 [-4] AVG Duty = 4969%(X100)
2264 06:48:40.209216
2265 06:48:40.212406 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2266 06:48:40.212506
2267 06:48:40.216174 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2268 06:48:40.219596 [DutyScan_Calibration_Flow] ====Done====
2269 06:48:40.219698 ==
2270 06:48:40.222409 Dram Type= 6, Freq= 0, CH_1, rank 0
2271 06:48:40.225510 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2272 06:48:40.225612 ==
2273 06:48:40.228959 [Duty_Offset_Calibration]
2274 06:48:40.229057 B0:0 B1:5 CA:-5
2275 06:48:40.229148
2276 06:48:40.232274 [DutyScan_Calibration_Flow] k_type=0
2277 06:48:40.243087
2278 06:48:40.243197 ==CLK 0==
2279 06:48:40.246338 Final CLK duty delay cell = 0
2280 06:48:40.249700 [0] MAX Duty = 5094%(X100), DQS PI = 24
2281 06:48:40.252868 [0] MIN Duty = 4907%(X100), DQS PI = 44
2282 06:48:40.252948 [0] AVG Duty = 5000%(X100)
2283 06:48:40.256187
2284 06:48:40.259885 CH1 CLK Duty spec in!! Max-Min= 187%
2285 06:48:40.263950 [DutyScan_Calibration_Flow] ====Done====
2286 06:48:40.264031
2287 06:48:40.266089 [DutyScan_Calibration_Flow] k_type=1
2288 06:48:40.281832
2289 06:48:40.281915 ==DQS 0 ==
2290 06:48:40.285266 Final DQS duty delay cell = 0
2291 06:48:40.288564 [0] MAX Duty = 5125%(X100), DQS PI = 16
2292 06:48:40.291396 [0] MIN Duty = 4875%(X100), DQS PI = 40
2293 06:48:40.295634 [0] AVG Duty = 5000%(X100)
2294 06:48:40.295750
2295 06:48:40.295818 ==DQS 1 ==
2296 06:48:40.298417 Final DQS duty delay cell = -4
2297 06:48:40.301747 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2298 06:48:40.305220 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2299 06:48:40.308823 [-4] AVG Duty = 4953%(X100)
2300 06:48:40.308903
2301 06:48:40.311432 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2302 06:48:40.311530
2303 06:48:40.315082 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2304 06:48:40.318041 [DutyScan_Calibration_Flow] ====Done====
2305 06:48:40.318146
2306 06:48:40.322067 [DutyScan_Calibration_Flow] k_type=3
2307 06:48:40.337228
2308 06:48:40.337335 ==DQM 0 ==
2309 06:48:40.340911 Final DQM duty delay cell = -4
2310 06:48:40.343978 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2311 06:48:40.347906 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2312 06:48:40.350659 [-4] AVG Duty = 4953%(X100)
2313 06:48:40.350759
2314 06:48:40.350855 ==DQM 1 ==
2315 06:48:40.353839 Final DQM duty delay cell = -4
2316 06:48:40.356823 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2317 06:48:40.361069 [-4] MIN Duty = 4906%(X100), DQS PI = 56
2318 06:48:40.363589 [-4] AVG Duty = 5000%(X100)
2319 06:48:40.363687
2320 06:48:40.366879 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2321 06:48:40.366977
2322 06:48:40.369839 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2323 06:48:40.373265 [DutyScan_Calibration_Flow] ====Done====
2324 06:48:40.373368
2325 06:48:40.376518 [DutyScan_Calibration_Flow] k_type=2
2326 06:48:40.394876
2327 06:48:40.394980 ==DQ 0 ==
2328 06:48:40.397164 Final DQ duty delay cell = 0
2329 06:48:40.400393 [0] MAX Duty = 5093%(X100), DQS PI = 0
2330 06:48:40.403944 [0] MIN Duty = 4969%(X100), DQS PI = 42
2331 06:48:40.404027 [0] AVG Duty = 5031%(X100)
2332 06:48:40.406902
2333 06:48:40.406985 ==DQ 1 ==
2334 06:48:40.411057 Final DQ duty delay cell = 0
2335 06:48:40.414302 [0] MAX Duty = 5000%(X100), DQS PI = 6
2336 06:48:40.417032 [0] MIN Duty = 4907%(X100), DQS PI = 0
2337 06:48:40.417115 [0] AVG Duty = 4953%(X100)
2338 06:48:40.417201
2339 06:48:40.420339 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2340 06:48:40.420423
2341 06:48:40.423941 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2342 06:48:40.430163 [DutyScan_Calibration_Flow] ====Done====
2343 06:48:40.433876 nWR fixed to 30
2344 06:48:40.433961 [ModeRegInit_LP4] CH0 RK0
2345 06:48:40.437431 [ModeRegInit_LP4] CH0 RK1
2346 06:48:40.440300 [ModeRegInit_LP4] CH1 RK0
2347 06:48:40.440380 [ModeRegInit_LP4] CH1 RK1
2348 06:48:40.443720 match AC timing 6
2349 06:48:40.446913 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2350 06:48:40.450609 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2351 06:48:40.457243 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2352 06:48:40.460692 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2353 06:48:40.467199 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2354 06:48:40.467280 ==
2355 06:48:40.470713 Dram Type= 6, Freq= 0, CH_0, rank 0
2356 06:48:40.474179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2357 06:48:40.474259 ==
2358 06:48:40.480451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2359 06:48:40.483717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2360 06:48:40.493670 [CA 0] Center 39 (9~70) winsize 62
2361 06:48:40.496746 [CA 1] Center 39 (9~70) winsize 62
2362 06:48:40.500789 [CA 2] Center 36 (5~67) winsize 63
2363 06:48:40.503675 [CA 3] Center 35 (5~66) winsize 62
2364 06:48:40.507196 [CA 4] Center 34 (3~65) winsize 63
2365 06:48:40.510261 [CA 5] Center 33 (3~64) winsize 62
2366 06:48:40.510341
2367 06:48:40.513751 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2368 06:48:40.513832
2369 06:48:40.517388 [CATrainingPosCal] consider 1 rank data
2370 06:48:40.520307 u2DelayCellTimex100 = 270/100 ps
2371 06:48:40.523585 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2372 06:48:40.527037 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2373 06:48:40.533125 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2374 06:48:40.537011 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2375 06:48:40.540210 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2376 06:48:40.543660 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2377 06:48:40.543741
2378 06:48:40.546816 CA PerBit enable=1, Macro0, CA PI delay=33
2379 06:48:40.546896
2380 06:48:40.550215 [CBTSetCACLKResult] CA Dly = 33
2381 06:48:40.550295 CS Dly: 7 (0~38)
2382 06:48:40.553391 ==
2383 06:48:40.553471 Dram Type= 6, Freq= 0, CH_0, rank 1
2384 06:48:40.560498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2385 06:48:40.560586 ==
2386 06:48:40.563078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2387 06:48:40.570031 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2388 06:48:40.579152 [CA 0] Center 39 (8~70) winsize 63
2389 06:48:40.582600 [CA 1] Center 38 (8~69) winsize 62
2390 06:48:40.585438 [CA 2] Center 36 (5~67) winsize 63
2391 06:48:40.589343 [CA 3] Center 35 (4~66) winsize 63
2392 06:48:40.592386 [CA 4] Center 33 (3~64) winsize 62
2393 06:48:40.595731 [CA 5] Center 34 (3~65) winsize 63
2394 06:48:40.595812
2395 06:48:40.599834 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2396 06:48:40.599915
2397 06:48:40.602293 [CATrainingPosCal] consider 2 rank data
2398 06:48:40.605530 u2DelayCellTimex100 = 270/100 ps
2399 06:48:40.609440 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2400 06:48:40.612665 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2401 06:48:40.619931 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2402 06:48:40.622468 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2403 06:48:40.625569 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2404 06:48:40.629353 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2405 06:48:40.629433
2406 06:48:40.632496 CA PerBit enable=1, Macro0, CA PI delay=33
2407 06:48:40.632576
2408 06:48:40.635858 [CBTSetCACLKResult] CA Dly = 33
2409 06:48:40.635939 CS Dly: 7 (0~39)
2410 06:48:40.636003
2411 06:48:40.639183 ----->DramcWriteLeveling(PI) begin...
2412 06:48:40.642291 ==
2413 06:48:40.645820 Dram Type= 6, Freq= 0, CH_0, rank 0
2414 06:48:40.650125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2415 06:48:40.650206 ==
2416 06:48:40.652665 Write leveling (Byte 0): 27 => 27
2417 06:48:40.656583 Write leveling (Byte 1): 25 => 25
2418 06:48:40.659220 DramcWriteLeveling(PI) end<-----
2419 06:48:40.659299
2420 06:48:40.659363 ==
2421 06:48:40.662338 Dram Type= 6, Freq= 0, CH_0, rank 0
2422 06:48:40.666111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2423 06:48:40.666191 ==
2424 06:48:40.668925 [Gating] SW mode calibration
2425 06:48:40.675550 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2426 06:48:40.679374 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2427 06:48:40.686094 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2428 06:48:40.689145 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2429 06:48:40.692177 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2430 06:48:40.699099 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2431 06:48:40.702249 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2432 06:48:40.705749 0 11 20 | B1->B0 | 2c2c 2626 | 0 0 | (1 0) (1 0)
2433 06:48:40.712096 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2434 06:48:40.716584 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2435 06:48:40.718774 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2436 06:48:40.725783 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2437 06:48:40.729809 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2438 06:48:40.732041 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2439 06:48:40.739638 0 12 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2440 06:48:40.742462 0 12 20 | B1->B0 | 3d3c 4646 | 1 0 | (0 0) (0 0)
2441 06:48:40.745490 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2442 06:48:40.752553 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2443 06:48:40.755629 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2444 06:48:40.759021 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2445 06:48:40.765906 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2446 06:48:40.768927 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2447 06:48:40.772669 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2448 06:48:40.779655 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2449 06:48:40.782737 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2450 06:48:40.785709 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2451 06:48:40.789296 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2452 06:48:40.795867 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2453 06:48:40.799232 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2454 06:48:40.802739 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2455 06:48:40.809297 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2456 06:48:40.812878 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2457 06:48:40.815890 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2458 06:48:40.822420 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2459 06:48:40.825856 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2460 06:48:40.829115 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2461 06:48:40.836430 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2462 06:48:40.838905 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2463 06:48:40.842125 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2464 06:48:40.848703 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2465 06:48:40.852581 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2466 06:48:40.856087 Total UI for P1: 0, mck2ui 16
2467 06:48:40.858791 best dqsien dly found for B0: ( 0, 15, 18)
2468 06:48:40.862373 Total UI for P1: 0, mck2ui 16
2469 06:48:40.865373 best dqsien dly found for B1: ( 0, 15, 18)
2470 06:48:40.868700 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2471 06:48:40.871959 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2472 06:48:40.872060
2473 06:48:40.875804 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2474 06:48:40.879050 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2475 06:48:40.882182 [Gating] SW calibration Done
2476 06:48:40.882266 ==
2477 06:48:40.886038 Dram Type= 6, Freq= 0, CH_0, rank 0
2478 06:48:40.888598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2479 06:48:40.888695 ==
2480 06:48:40.892499 RX Vref Scan: 0
2481 06:48:40.892593
2482 06:48:40.896269 RX Vref 0 -> 0, step: 1
2483 06:48:40.896355
2484 06:48:40.896445 RX Delay -40 -> 252, step: 8
2485 06:48:40.903044 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2486 06:48:40.905604 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2487 06:48:40.909085 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2488 06:48:40.912810 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2489 06:48:40.915254 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2490 06:48:40.921870 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2491 06:48:40.925401 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2492 06:48:40.928802 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2493 06:48:40.932034 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2494 06:48:40.935305 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2495 06:48:40.941986 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2496 06:48:40.945414 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2497 06:48:40.948926 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2498 06:48:40.953031 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2499 06:48:40.955395 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2500 06:48:40.962044 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2501 06:48:40.962117 ==
2502 06:48:40.966634 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 06:48:40.968739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2504 06:48:40.968850 ==
2505 06:48:40.968950 DQS Delay:
2506 06:48:40.972412 DQS0 = 0, DQS1 = 0
2507 06:48:40.972509 DQM Delay:
2508 06:48:40.975624 DQM0 = 115, DQM1 = 107
2509 06:48:40.975722 DQ Delay:
2510 06:48:40.979332 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2511 06:48:40.981859 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2512 06:48:40.985599 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =107
2513 06:48:40.989629 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2514 06:48:40.989700
2515 06:48:40.989779
2516 06:48:40.991983 ==
2517 06:48:40.995098 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 06:48:40.998443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2519 06:48:40.998513 ==
2520 06:48:40.998580
2521 06:48:40.998639
2522 06:48:41.001904 TX Vref Scan disable
2523 06:48:41.001977 == TX Byte 0 ==
2524 06:48:41.004995 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2525 06:48:41.011889 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2526 06:48:41.011991 == TX Byte 1 ==
2527 06:48:41.015358 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2528 06:48:41.022577 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2529 06:48:41.022678 ==
2530 06:48:41.025022 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 06:48:41.028421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2532 06:48:41.028518 ==
2533 06:48:41.041277 TX Vref=22, minBit 8, minWin=25, winSum=415
2534 06:48:41.043709 TX Vref=24, minBit 9, minWin=25, winSum=421
2535 06:48:41.047371 TX Vref=26, minBit 12, minWin=25, winSum=428
2536 06:48:41.050638 TX Vref=28, minBit 8, minWin=26, winSum=435
2537 06:48:41.053748 TX Vref=30, minBit 8, minWin=26, winSum=432
2538 06:48:41.060690 TX Vref=32, minBit 8, minWin=26, winSum=431
2539 06:48:41.064530 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 28
2540 06:48:41.064631
2541 06:48:41.067050 Final TX Range 1 Vref 28
2542 06:48:41.067150
2543 06:48:41.067244 ==
2544 06:48:41.070344 Dram Type= 6, Freq= 0, CH_0, rank 0
2545 06:48:41.073839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2546 06:48:41.073925 ==
2547 06:48:41.077221
2548 06:48:41.077320
2549 06:48:41.077417 TX Vref Scan disable
2550 06:48:41.080810 == TX Byte 0 ==
2551 06:48:41.083614 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2552 06:48:41.087243 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2553 06:48:41.090479 == TX Byte 1 ==
2554 06:48:41.093903 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2555 06:48:41.097613 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2556 06:48:41.097719
2557 06:48:41.100688 [DATLAT]
2558 06:48:41.100815 Freq=1200, CH0 RK0
2559 06:48:41.100878
2560 06:48:41.104193 DATLAT Default: 0xd
2561 06:48:41.104292 0, 0xFFFF, sum = 0
2562 06:48:41.107772 1, 0xFFFF, sum = 0
2563 06:48:41.107874 2, 0xFFFF, sum = 0
2564 06:48:41.110989 3, 0xFFFF, sum = 0
2565 06:48:41.111062 4, 0xFFFF, sum = 0
2566 06:48:41.114128 5, 0xFFFF, sum = 0
2567 06:48:41.114232 6, 0xFFFF, sum = 0
2568 06:48:41.117703 7, 0xFFFF, sum = 0
2569 06:48:41.117775 8, 0xFFFF, sum = 0
2570 06:48:41.120832 9, 0xFFFF, sum = 0
2571 06:48:41.124020 10, 0xFFFF, sum = 0
2572 06:48:41.124089 11, 0x0, sum = 1
2573 06:48:41.124173 12, 0x0, sum = 2
2574 06:48:41.127604 13, 0x0, sum = 3
2575 06:48:41.127713 14, 0x0, sum = 4
2576 06:48:41.130966 best_step = 12
2577 06:48:41.131060
2578 06:48:41.131152 ==
2579 06:48:41.134008 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 06:48:41.137413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2581 06:48:41.137495 ==
2582 06:48:41.140968 RX Vref Scan: 1
2583 06:48:41.141037
2584 06:48:41.141102 Set Vref Range= 32 -> 127
2585 06:48:41.144491
2586 06:48:41.144584 RX Vref 32 -> 127, step: 1
2587 06:48:41.144675
2588 06:48:41.147472 RX Delay -21 -> 252, step: 4
2589 06:48:41.147567
2590 06:48:41.150367 Set Vref, RX VrefLevel [Byte0]: 32
2591 06:48:41.154462 [Byte1]: 32
2592 06:48:41.154557
2593 06:48:41.157197 Set Vref, RX VrefLevel [Byte0]: 33
2594 06:48:41.160618 [Byte1]: 33
2595 06:48:41.165354
2596 06:48:41.165445 Set Vref, RX VrefLevel [Byte0]: 34
2597 06:48:41.168453 [Byte1]: 34
2598 06:48:41.172993
2599 06:48:41.173073 Set Vref, RX VrefLevel [Byte0]: 35
2600 06:48:41.176258 [Byte1]: 35
2601 06:48:41.180745
2602 06:48:41.180820 Set Vref, RX VrefLevel [Byte0]: 36
2603 06:48:41.183943 [Byte1]: 36
2604 06:48:41.189123
2605 06:48:41.189198 Set Vref, RX VrefLevel [Byte0]: 37
2606 06:48:41.193002 [Byte1]: 37
2607 06:48:41.196681
2608 06:48:41.200432 Set Vref, RX VrefLevel [Byte0]: 38
2609 06:48:41.200539 [Byte1]: 38
2610 06:48:41.204895
2611 06:48:41.205000 Set Vref, RX VrefLevel [Byte0]: 39
2612 06:48:41.208063 [Byte1]: 39
2613 06:48:41.213173
2614 06:48:41.213247 Set Vref, RX VrefLevel [Byte0]: 40
2615 06:48:41.216234 [Byte1]: 40
2616 06:48:41.220978
2617 06:48:41.221052 Set Vref, RX VrefLevel [Byte0]: 41
2618 06:48:41.223972 [Byte1]: 41
2619 06:48:41.228900
2620 06:48:41.228971 Set Vref, RX VrefLevel [Byte0]: 42
2621 06:48:41.231971 [Byte1]: 42
2622 06:48:41.236476
2623 06:48:41.236584 Set Vref, RX VrefLevel [Byte0]: 43
2624 06:48:41.239840 [Byte1]: 43
2625 06:48:41.244192
2626 06:48:41.244289 Set Vref, RX VrefLevel [Byte0]: 44
2627 06:48:41.247443 [Byte1]: 44
2628 06:48:41.252670
2629 06:48:41.252772 Set Vref, RX VrefLevel [Byte0]: 45
2630 06:48:41.255735 [Byte1]: 45
2631 06:48:41.260540
2632 06:48:41.260635 Set Vref, RX VrefLevel [Byte0]: 46
2633 06:48:41.264470 [Byte1]: 46
2634 06:48:41.268081
2635 06:48:41.268177 Set Vref, RX VrefLevel [Byte0]: 47
2636 06:48:41.271486 [Byte1]: 47
2637 06:48:41.276382
2638 06:48:41.276482 Set Vref, RX VrefLevel [Byte0]: 48
2639 06:48:41.279391 [Byte1]: 48
2640 06:48:41.284160
2641 06:48:41.284259 Set Vref, RX VrefLevel [Byte0]: 49
2642 06:48:41.287286 [Byte1]: 49
2643 06:48:41.291939
2644 06:48:41.292014 Set Vref, RX VrefLevel [Byte0]: 50
2645 06:48:41.295155 [Byte1]: 50
2646 06:48:41.299381
2647 06:48:41.299492 Set Vref, RX VrefLevel [Byte0]: 51
2648 06:48:41.303435 [Byte1]: 51
2649 06:48:41.307693
2650 06:48:41.307794 Set Vref, RX VrefLevel [Byte0]: 52
2651 06:48:41.311263 [Byte1]: 52
2652 06:48:41.315758
2653 06:48:41.315831 Set Vref, RX VrefLevel [Byte0]: 53
2654 06:48:41.318850 [Byte1]: 53
2655 06:48:41.324220
2656 06:48:41.324320 Set Vref, RX VrefLevel [Byte0]: 54
2657 06:48:41.327105 [Byte1]: 54
2658 06:48:41.331390
2659 06:48:41.331492 Set Vref, RX VrefLevel [Byte0]: 55
2660 06:48:41.334457 [Byte1]: 55
2661 06:48:41.339240
2662 06:48:41.339343 Set Vref, RX VrefLevel [Byte0]: 56
2663 06:48:41.343063 [Byte1]: 56
2664 06:48:41.347228
2665 06:48:41.347324 Set Vref, RX VrefLevel [Byte0]: 57
2666 06:48:41.351235 [Byte1]: 57
2667 06:48:41.355158
2668 06:48:41.355252 Set Vref, RX VrefLevel [Byte0]: 58
2669 06:48:41.358407 [Byte1]: 58
2670 06:48:41.362967
2671 06:48:41.363063 Set Vref, RX VrefLevel [Byte0]: 59
2672 06:48:41.366455 [Byte1]: 59
2673 06:48:41.370711
2674 06:48:41.370806 Set Vref, RX VrefLevel [Byte0]: 60
2675 06:48:41.374800 [Byte1]: 60
2676 06:48:41.378734
2677 06:48:41.378831 Set Vref, RX VrefLevel [Byte0]: 61
2678 06:48:41.382146 [Byte1]: 61
2679 06:48:41.386669
2680 06:48:41.386763 Set Vref, RX VrefLevel [Byte0]: 62
2681 06:48:41.390000 [Byte1]: 62
2682 06:48:41.394450
2683 06:48:41.398320 Set Vref, RX VrefLevel [Byte0]: 63
2684 06:48:41.401426 [Byte1]: 63
2685 06:48:41.401525
2686 06:48:41.404922 Set Vref, RX VrefLevel [Byte0]: 64
2687 06:48:41.407742 [Byte1]: 64
2688 06:48:41.407828
2689 06:48:41.411555 Set Vref, RX VrefLevel [Byte0]: 65
2690 06:48:41.414935 [Byte1]: 65
2691 06:48:41.419005
2692 06:48:41.419104 Final RX Vref Byte 0 = 52 to rank0
2693 06:48:41.421905 Final RX Vref Byte 1 = 48 to rank0
2694 06:48:41.425568 Final RX Vref Byte 0 = 52 to rank1
2695 06:48:41.428491 Final RX Vref Byte 1 = 48 to rank1==
2696 06:48:41.432061 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 06:48:41.438363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2698 06:48:41.438470 ==
2699 06:48:41.438563 DQS Delay:
2700 06:48:41.438653 DQS0 = 0, DQS1 = 0
2701 06:48:41.441863 DQM Delay:
2702 06:48:41.441963 DQM0 = 114, DQM1 = 105
2703 06:48:41.445656 DQ Delay:
2704 06:48:41.449255 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2705 06:48:41.452426 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2706 06:48:41.455816 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2707 06:48:41.458798 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2708 06:48:41.458897
2709 06:48:41.458990
2710 06:48:41.465791 [DQSOSCAuto] RK0, (LSB)MR18= 0x505, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2711 06:48:41.468880 CH0 RK0: MR19=404, MR18=505
2712 06:48:41.475311 CH0_RK0: MR19=0x404, MR18=0x505, DQSOSC=408, MR23=63, INC=39, DEC=26
2713 06:48:41.475413
2714 06:48:41.478663 ----->DramcWriteLeveling(PI) begin...
2715 06:48:41.478765 ==
2716 06:48:41.481802 Dram Type= 6, Freq= 0, CH_0, rank 1
2717 06:48:41.485566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2718 06:48:41.485665 ==
2719 06:48:41.488404 Write leveling (Byte 0): 28 => 28
2720 06:48:41.492134 Write leveling (Byte 1): 24 => 24
2721 06:48:41.495580 DramcWriteLeveling(PI) end<-----
2722 06:48:41.495682
2723 06:48:41.495774 ==
2724 06:48:41.498539 Dram Type= 6, Freq= 0, CH_0, rank 1
2725 06:48:41.501759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2726 06:48:41.504913 ==
2727 06:48:41.504991 [Gating] SW mode calibration
2728 06:48:41.512140 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2729 06:48:41.518758 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2730 06:48:41.521646 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2731 06:48:41.528633 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2732 06:48:41.533100 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2733 06:48:41.535330 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2734 06:48:41.542030 0 11 16 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
2735 06:48:41.545098 0 11 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
2736 06:48:41.548772 0 11 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2737 06:48:41.555867 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2738 06:48:41.558817 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2739 06:48:41.562017 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2740 06:48:41.569580 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2741 06:48:41.572555 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2742 06:48:41.575055 0 12 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
2743 06:48:41.578581 0 12 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2744 06:48:41.585519 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2745 06:48:41.588436 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2746 06:48:41.591745 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2747 06:48:41.598693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2748 06:48:41.602264 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2749 06:48:41.605487 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2750 06:48:41.611914 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2751 06:48:41.615435 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2752 06:48:41.618282 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2753 06:48:41.625074 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2754 06:48:41.629264 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2755 06:48:41.631709 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2756 06:48:41.638557 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2757 06:48:41.642036 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2758 06:48:41.645346 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2759 06:48:41.651682 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2760 06:48:41.654867 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2761 06:48:41.658531 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2762 06:48:41.665245 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2763 06:48:41.668801 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2764 06:48:41.671816 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2765 06:48:41.678330 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2766 06:48:41.681714 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2767 06:48:41.685247 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2768 06:48:41.688259 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2769 06:48:41.692409 Total UI for P1: 0, mck2ui 16
2770 06:48:41.695338 best dqsien dly found for B0: ( 0, 15, 18)
2771 06:48:41.698683 Total UI for P1: 0, mck2ui 16
2772 06:48:41.701964 best dqsien dly found for B1: ( 0, 15, 18)
2773 06:48:41.705357 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2774 06:48:41.712270 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2775 06:48:41.712372
2776 06:48:41.715738 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2777 06:48:41.718455 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2778 06:48:41.721969 [Gating] SW calibration Done
2779 06:48:41.722072 ==
2780 06:48:41.725702 Dram Type= 6, Freq= 0, CH_0, rank 1
2781 06:48:41.728328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2782 06:48:41.728424 ==
2783 06:48:41.728514 RX Vref Scan: 0
2784 06:48:41.733318
2785 06:48:41.733415 RX Vref 0 -> 0, step: 1
2786 06:48:41.733503
2787 06:48:41.736519 RX Delay -40 -> 252, step: 8
2788 06:48:41.738700 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2789 06:48:41.742636 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2790 06:48:41.748210 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2791 06:48:41.751765 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2792 06:48:41.755640 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2793 06:48:41.758343 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2794 06:48:41.762254 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2795 06:48:41.768152 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2796 06:48:41.771556 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2797 06:48:41.775034 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2798 06:48:41.780441 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2799 06:48:41.781808 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2800 06:48:41.788655 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2801 06:48:41.791857 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2802 06:48:41.794995 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2803 06:48:41.798047 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2804 06:48:41.798133 ==
2805 06:48:41.802166 Dram Type= 6, Freq= 0, CH_0, rank 1
2806 06:48:41.805264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2807 06:48:41.808344 ==
2808 06:48:41.808439 DQS Delay:
2809 06:48:41.808527 DQS0 = 0, DQS1 = 0
2810 06:48:41.812023 DQM Delay:
2811 06:48:41.812120 DQM0 = 115, DQM1 = 106
2812 06:48:41.815125 DQ Delay:
2813 06:48:41.818332 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =107
2814 06:48:41.821739 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2815 06:48:41.825095 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2816 06:48:41.828582 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2817 06:48:41.828677
2818 06:48:41.828757
2819 06:48:41.828839 ==
2820 06:48:41.831806 Dram Type= 6, Freq= 0, CH_0, rank 1
2821 06:48:41.835585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2822 06:48:41.835686 ==
2823 06:48:41.835781
2824 06:48:41.835867
2825 06:48:41.838915 TX Vref Scan disable
2826 06:48:41.841988 == TX Byte 0 ==
2827 06:48:41.845586 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2828 06:48:41.848231 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2829 06:48:41.851717 == TX Byte 1 ==
2830 06:48:41.855083 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2831 06:48:41.858642 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2832 06:48:41.858738 ==
2833 06:48:41.861901 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 06:48:41.868045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2835 06:48:41.868153 ==
2836 06:48:41.878765 TX Vref=22, minBit 8, minWin=25, winSum=423
2837 06:48:41.882199 TX Vref=24, minBit 8, minWin=25, winSum=423
2838 06:48:41.887429 TX Vref=26, minBit 9, minWin=25, winSum=426
2839 06:48:41.889709 TX Vref=28, minBit 9, minWin=26, winSum=433
2840 06:48:41.891894 TX Vref=30, minBit 9, minWin=26, winSum=433
2841 06:48:41.896210 TX Vref=32, minBit 8, minWin=25, winSum=434
2842 06:48:41.901827 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
2843 06:48:41.901984
2844 06:48:41.905553 Final TX Range 1 Vref 28
2845 06:48:41.905661
2846 06:48:41.905756 ==
2847 06:48:41.908711 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 06:48:41.912269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2849 06:48:41.912384 ==
2850 06:48:41.912477
2851 06:48:41.915375
2852 06:48:41.915473 TX Vref Scan disable
2853 06:48:41.918938 == TX Byte 0 ==
2854 06:48:41.922902 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2855 06:48:41.926314 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2856 06:48:41.928450 == TX Byte 1 ==
2857 06:48:41.932217 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2858 06:48:41.935242 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2859 06:48:41.935340
2860 06:48:41.938729 [DATLAT]
2861 06:48:41.938840 Freq=1200, CH0 RK1
2862 06:48:41.938935
2863 06:48:41.941983 DATLAT Default: 0xc
2864 06:48:41.942089 0, 0xFFFF, sum = 0
2865 06:48:41.945657 1, 0xFFFF, sum = 0
2866 06:48:41.945759 2, 0xFFFF, sum = 0
2867 06:48:41.949480 3, 0xFFFF, sum = 0
2868 06:48:41.949580 4, 0xFFFF, sum = 0
2869 06:48:41.951865 5, 0xFFFF, sum = 0
2870 06:48:41.951973 6, 0xFFFF, sum = 0
2871 06:48:41.955338 7, 0xFFFF, sum = 0
2872 06:48:41.959656 8, 0xFFFF, sum = 0
2873 06:48:41.959760 9, 0xFFFF, sum = 0
2874 06:48:41.962172 10, 0xFFFF, sum = 0
2875 06:48:41.962272 11, 0x0, sum = 1
2876 06:48:41.965608 12, 0x0, sum = 2
2877 06:48:41.965717 13, 0x0, sum = 3
2878 06:48:41.965809 14, 0x0, sum = 4
2879 06:48:41.969013 best_step = 12
2880 06:48:41.969108
2881 06:48:41.969207 ==
2882 06:48:41.972173 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 06:48:41.975279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2884 06:48:41.975383 ==
2885 06:48:41.978583 RX Vref Scan: 0
2886 06:48:41.978677
2887 06:48:41.978770 RX Vref 0 -> 0, step: 1
2888 06:48:41.978858
2889 06:48:41.982209 RX Delay -21 -> 252, step: 4
2890 06:48:41.989105 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2891 06:48:41.992479 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2892 06:48:41.996506 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2893 06:48:42.000342 iDelay=199, Bit 3, Center 110 (39 ~ 182) 144
2894 06:48:42.002381 iDelay=199, Bit 4, Center 118 (43 ~ 194) 152
2895 06:48:42.008742 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2896 06:48:42.012130 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2897 06:48:42.015490 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2898 06:48:42.019068 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2899 06:48:42.022710 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2900 06:48:42.029126 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2901 06:48:42.032124 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2902 06:48:42.035400 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2903 06:48:42.039425 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2904 06:48:42.042092 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2905 06:48:42.048664 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2906 06:48:42.048817 ==
2907 06:48:42.052045 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 06:48:42.055627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2909 06:48:42.055728 ==
2910 06:48:42.055826 DQS Delay:
2911 06:48:42.058830 DQS0 = 0, DQS1 = 0
2912 06:48:42.058930 DQM Delay:
2913 06:48:42.062599 DQM0 = 115, DQM1 = 105
2914 06:48:42.062697 DQ Delay:
2915 06:48:42.066482 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =110
2916 06:48:42.068547 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =124
2917 06:48:42.071983 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2918 06:48:42.075581 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2919 06:48:42.075682
2920 06:48:42.075772
2921 06:48:42.086107 [DQSOSCAuto] RK1, (LSB)MR18= 0x1212, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2922 06:48:42.089000 CH0 RK1: MR19=404, MR18=1212
2923 06:48:42.091946 CH0_RK1: MR19=0x404, MR18=0x1212, DQSOSC=403, MR23=63, INC=40, DEC=26
2924 06:48:42.096206 [RxdqsGatingPostProcess] freq 1200
2925 06:48:42.102582 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2926 06:48:42.105623 Pre-setting of DQS Precalculation
2927 06:48:42.109338 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2928 06:48:42.109416 ==
2929 06:48:42.111960 Dram Type= 6, Freq= 0, CH_1, rank 0
2930 06:48:42.118884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2931 06:48:42.118990 ==
2932 06:48:42.122989 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2933 06:48:42.129216 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2934 06:48:42.137323 [CA 0] Center 37 (7~68) winsize 62
2935 06:48:42.140802 [CA 1] Center 37 (7~68) winsize 62
2936 06:48:42.144526 [CA 2] Center 34 (4~65) winsize 62
2937 06:48:42.147301 [CA 3] Center 33 (3~64) winsize 62
2938 06:48:42.151061 [CA 4] Center 32 (1~63) winsize 63
2939 06:48:42.154436 [CA 5] Center 32 (2~63) winsize 62
2940 06:48:42.154534
2941 06:48:42.157993 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2942 06:48:42.158089
2943 06:48:42.161434 [CATrainingPosCal] consider 1 rank data
2944 06:48:42.164639 u2DelayCellTimex100 = 270/100 ps
2945 06:48:42.167843 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2946 06:48:42.170961 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2947 06:48:42.177730 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2948 06:48:42.180639 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2949 06:48:42.184111 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2950 06:48:42.187462 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2951 06:48:42.187571
2952 06:48:42.190566 CA PerBit enable=1, Macro0, CA PI delay=32
2953 06:48:42.190664
2954 06:48:42.193888 [CBTSetCACLKResult] CA Dly = 32
2955 06:48:42.193983 CS Dly: 6 (0~37)
2956 06:48:42.198360 ==
2957 06:48:42.198466 Dram Type= 6, Freq= 0, CH_1, rank 1
2958 06:48:42.204071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2959 06:48:42.204174 ==
2960 06:48:42.207412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2961 06:48:42.213897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2962 06:48:42.223315 [CA 0] Center 37 (7~68) winsize 62
2963 06:48:42.225930 [CA 1] Center 37 (7~68) winsize 62
2964 06:48:42.229567 [CA 2] Center 34 (3~65) winsize 63
2965 06:48:42.233238 [CA 3] Center 33 (3~64) winsize 62
2966 06:48:42.236345 [CA 4] Center 32 (2~63) winsize 62
2967 06:48:42.239392 [CA 5] Center 32 (2~63) winsize 62
2968 06:48:42.239504
2969 06:48:42.243435 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2970 06:48:42.243539
2971 06:48:42.247084 [CATrainingPosCal] consider 2 rank data
2972 06:48:42.249495 u2DelayCellTimex100 = 270/100 ps
2973 06:48:42.252616 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2974 06:48:42.256814 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2975 06:48:42.263354 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2976 06:48:42.266417 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2977 06:48:42.269447 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2978 06:48:42.273200 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2979 06:48:42.273300
2980 06:48:42.275910 CA PerBit enable=1, Macro0, CA PI delay=32
2981 06:48:42.276008
2982 06:48:42.279789 [CBTSetCACLKResult] CA Dly = 32
2983 06:48:42.279890 CS Dly: 6 (0~38)
2984 06:48:42.279981
2985 06:48:42.284420 ----->DramcWriteLeveling(PI) begin...
2986 06:48:42.286739 ==
2987 06:48:42.286829 Dram Type= 6, Freq= 0, CH_1, rank 0
2988 06:48:42.293693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2989 06:48:42.293796 ==
2990 06:48:42.296323 Write leveling (Byte 0): 24 => 24
2991 06:48:42.299493 Write leveling (Byte 1): 24 => 24
2992 06:48:42.299601 DramcWriteLeveling(PI) end<-----
2993 06:48:42.302936
2994 06:48:42.303010 ==
2995 06:48:42.306589 Dram Type= 6, Freq= 0, CH_1, rank 0
2996 06:48:42.309563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2997 06:48:42.309662 ==
2998 06:48:42.313136 [Gating] SW mode calibration
2999 06:48:42.319463 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3000 06:48:42.323000 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3001 06:48:42.330163 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3002 06:48:42.333144 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3003 06:48:42.336494 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3004 06:48:42.342660 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3005 06:48:42.345868 0 11 16 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 0)
3006 06:48:42.349161 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3007 06:48:42.356001 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3008 06:48:42.359236 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3009 06:48:42.362766 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3010 06:48:42.369640 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3011 06:48:42.373042 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3012 06:48:42.376244 0 12 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
3013 06:48:42.382747 0 12 16 | B1->B0 | 3939 4646 | 1 0 | (1 1) (0 0)
3014 06:48:42.385773 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3015 06:48:42.389299 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3016 06:48:42.396153 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3017 06:48:42.399032 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3018 06:48:42.402489 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3019 06:48:42.409026 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3020 06:48:42.413254 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3021 06:48:42.416389 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3022 06:48:42.422445 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3023 06:48:42.425651 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3024 06:48:42.429059 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3025 06:48:42.435575 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3026 06:48:42.439452 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3027 06:48:42.442414 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3028 06:48:42.448880 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3029 06:48:42.452789 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3030 06:48:42.455683 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3031 06:48:42.461842 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3032 06:48:42.465426 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3033 06:48:42.469336 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3034 06:48:42.471739 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3035 06:48:42.478831 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3036 06:48:42.482065 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3037 06:48:42.485443 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3038 06:48:42.492145 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3039 06:48:42.495495 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3040 06:48:42.498939 Total UI for P1: 0, mck2ui 16
3041 06:48:42.502539 best dqsien dly found for B0: ( 0, 15, 18)
3042 06:48:42.505770 Total UI for P1: 0, mck2ui 16
3043 06:48:42.508768 best dqsien dly found for B1: ( 0, 15, 18)
3044 06:48:42.512678 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
3045 06:48:42.515459 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3046 06:48:42.515541
3047 06:48:42.519372 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
3048 06:48:42.522520 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3049 06:48:42.525875 [Gating] SW calibration Done
3050 06:48:42.525957 ==
3051 06:48:42.529417 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 06:48:42.535085 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3053 06:48:42.535167 ==
3054 06:48:42.535232 RX Vref Scan: 0
3055 06:48:42.535293
3056 06:48:42.538456 RX Vref 0 -> 0, step: 1
3057 06:48:42.538537
3058 06:48:42.541912 RX Delay -40 -> 252, step: 8
3059 06:48:42.545376 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3060 06:48:42.548558 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3061 06:48:42.552507 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3062 06:48:42.556521 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3063 06:48:42.562675 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3064 06:48:42.565114 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3065 06:48:42.569298 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3066 06:48:42.572408 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3067 06:48:42.575237 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3068 06:48:42.582201 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3069 06:48:42.585489 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3070 06:48:42.588304 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3071 06:48:42.591818 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3072 06:48:42.595586 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3073 06:48:42.601944 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3074 06:48:42.605254 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3075 06:48:42.605336 ==
3076 06:48:42.608601 Dram Type= 6, Freq= 0, CH_1, rank 0
3077 06:48:42.611494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3078 06:48:42.611576 ==
3079 06:48:42.615004 DQS Delay:
3080 06:48:42.615085 DQS0 = 0, DQS1 = 0
3081 06:48:42.615149 DQM Delay:
3082 06:48:42.618281 DQM0 = 115, DQM1 = 109
3083 06:48:42.618362 DQ Delay:
3084 06:48:42.622447 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3085 06:48:42.625267 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3086 06:48:42.628962 DQ8 =87, DQ9 =99, DQ10 =111, DQ11 =103
3087 06:48:42.634922 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3088 06:48:42.635004
3089 06:48:42.635068
3090 06:48:42.635128 ==
3091 06:48:42.639137 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 06:48:42.641948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3093 06:48:42.642030 ==
3094 06:48:42.642095
3095 06:48:42.642154
3096 06:48:42.644979 TX Vref Scan disable
3097 06:48:42.645060 == TX Byte 0 ==
3098 06:48:42.651804 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3099 06:48:42.655672 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3100 06:48:42.655754 == TX Byte 1 ==
3101 06:48:42.661843 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3102 06:48:42.665246 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3103 06:48:42.665327 ==
3104 06:48:42.668399 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 06:48:42.671514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3106 06:48:42.671596 ==
3107 06:48:42.684274 TX Vref=22, minBit 0, minWin=25, winSum=414
3108 06:48:42.687388 TX Vref=24, minBit 11, minWin=25, winSum=423
3109 06:48:42.690641 TX Vref=26, minBit 15, minWin=25, winSum=425
3110 06:48:42.693862 TX Vref=28, minBit 8, minWin=26, winSum=434
3111 06:48:42.697436 TX Vref=30, minBit 9, minWin=26, winSum=433
3112 06:48:42.703700 TX Vref=32, minBit 8, minWin=26, winSum=430
3113 06:48:42.707039 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
3114 06:48:42.707121
3115 06:48:42.710561 Final TX Range 1 Vref 28
3116 06:48:42.710643
3117 06:48:42.710708 ==
3118 06:48:42.714322 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 06:48:42.717264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3120 06:48:42.717345 ==
3121 06:48:42.721152
3122 06:48:42.721232
3123 06:48:42.721297 TX Vref Scan disable
3124 06:48:42.723891 == TX Byte 0 ==
3125 06:48:42.727717 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3126 06:48:42.730987 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3127 06:48:42.734390 == TX Byte 1 ==
3128 06:48:42.737297 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3129 06:48:42.740743 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3130 06:48:42.740840
3131 06:48:42.744015 [DATLAT]
3132 06:48:42.744096 Freq=1200, CH1 RK0
3133 06:48:42.744160
3134 06:48:42.747334 DATLAT Default: 0xd
3135 06:48:42.747414 0, 0xFFFF, sum = 0
3136 06:48:42.750968 1, 0xFFFF, sum = 0
3137 06:48:42.751050 2, 0xFFFF, sum = 0
3138 06:48:42.753982 3, 0xFFFF, sum = 0
3139 06:48:42.754065 4, 0xFFFF, sum = 0
3140 06:48:42.757376 5, 0xFFFF, sum = 0
3141 06:48:42.757458 6, 0xFFFF, sum = 0
3142 06:48:42.760740 7, 0xFFFF, sum = 0
3143 06:48:42.760835 8, 0xFFFF, sum = 0
3144 06:48:42.763997 9, 0xFFFF, sum = 0
3145 06:48:42.767532 10, 0xFFFF, sum = 0
3146 06:48:42.767614 11, 0x0, sum = 1
3147 06:48:42.767680 12, 0x0, sum = 2
3148 06:48:42.771487 13, 0x0, sum = 3
3149 06:48:42.771570 14, 0x0, sum = 4
3150 06:48:42.774908 best_step = 12
3151 06:48:42.774988
3152 06:48:42.775052 ==
3153 06:48:42.777844 Dram Type= 6, Freq= 0, CH_1, rank 0
3154 06:48:42.781237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3155 06:48:42.781318 ==
3156 06:48:42.784045 RX Vref Scan: 1
3157 06:48:42.784125
3158 06:48:42.784189 Set Vref Range= 32 -> 127
3159 06:48:42.784249
3160 06:48:42.787767 RX Vref 32 -> 127, step: 1
3161 06:48:42.787847
3162 06:48:42.791117 RX Delay -29 -> 252, step: 4
3163 06:48:42.791197
3164 06:48:42.793827 Set Vref, RX VrefLevel [Byte0]: 32
3165 06:48:42.797492 [Byte1]: 32
3166 06:48:42.800593
3167 06:48:42.800674 Set Vref, RX VrefLevel [Byte0]: 33
3168 06:48:42.803979 [Byte1]: 33
3169 06:48:42.808462
3170 06:48:42.808543 Set Vref, RX VrefLevel [Byte0]: 34
3171 06:48:42.812111 [Byte1]: 34
3172 06:48:42.817038
3173 06:48:42.817119 Set Vref, RX VrefLevel [Byte0]: 35
3174 06:48:42.819751 [Byte1]: 35
3175 06:48:42.824920
3176 06:48:42.825001 Set Vref, RX VrefLevel [Byte0]: 36
3177 06:48:42.828502 [Byte1]: 36
3178 06:48:42.832630
3179 06:48:42.832717 Set Vref, RX VrefLevel [Byte0]: 37
3180 06:48:42.835591 [Byte1]: 37
3181 06:48:42.840595
3182 06:48:42.840693 Set Vref, RX VrefLevel [Byte0]: 38
3183 06:48:42.843527 [Byte1]: 38
3184 06:48:42.848930
3185 06:48:42.849011 Set Vref, RX VrefLevel [Byte0]: 39
3186 06:48:42.851769 [Byte1]: 39
3187 06:48:42.856248
3188 06:48:42.856328 Set Vref, RX VrefLevel [Byte0]: 40
3189 06:48:42.860284 [Byte1]: 40
3190 06:48:42.864629
3191 06:48:42.864735 Set Vref, RX VrefLevel [Byte0]: 41
3192 06:48:42.867769 [Byte1]: 41
3193 06:48:42.872852
3194 06:48:42.872933 Set Vref, RX VrefLevel [Byte0]: 42
3195 06:48:42.875378 [Byte1]: 42
3196 06:48:42.880984
3197 06:48:42.881091 Set Vref, RX VrefLevel [Byte0]: 43
3198 06:48:42.883722 [Byte1]: 43
3199 06:48:42.888680
3200 06:48:42.888770 Set Vref, RX VrefLevel [Byte0]: 44
3201 06:48:42.891444 [Byte1]: 44
3202 06:48:42.896600
3203 06:48:42.896681 Set Vref, RX VrefLevel [Byte0]: 45
3204 06:48:42.899421 [Byte1]: 45
3205 06:48:42.904402
3206 06:48:42.904482 Set Vref, RX VrefLevel [Byte0]: 46
3207 06:48:42.908466 [Byte1]: 46
3208 06:48:42.912266
3209 06:48:42.912347 Set Vref, RX VrefLevel [Byte0]: 47
3210 06:48:42.915687 [Byte1]: 47
3211 06:48:42.919913
3212 06:48:42.919993 Set Vref, RX VrefLevel [Byte0]: 48
3213 06:48:42.922923 [Byte1]: 48
3214 06:48:42.928586
3215 06:48:42.928667 Set Vref, RX VrefLevel [Byte0]: 49
3216 06:48:42.931417 [Byte1]: 49
3217 06:48:42.935714
3218 06:48:42.935795 Set Vref, RX VrefLevel [Byte0]: 50
3219 06:48:42.939105 [Byte1]: 50
3220 06:48:42.943916
3221 06:48:42.943998 Set Vref, RX VrefLevel [Byte0]: 51
3222 06:48:42.947221 [Byte1]: 51
3223 06:48:42.951644
3224 06:48:42.951725 Set Vref, RX VrefLevel [Byte0]: 52
3225 06:48:42.954759 [Byte1]: 52
3226 06:48:42.960323
3227 06:48:42.960403 Set Vref, RX VrefLevel [Byte0]: 53
3228 06:48:42.962835 [Byte1]: 53
3229 06:48:42.967906
3230 06:48:42.967987 Set Vref, RX VrefLevel [Byte0]: 54
3231 06:48:42.971021 [Byte1]: 54
3232 06:48:42.976339
3233 06:48:42.976420 Set Vref, RX VrefLevel [Byte0]: 55
3234 06:48:42.979686 [Byte1]: 55
3235 06:48:42.983783
3236 06:48:42.983867 Set Vref, RX VrefLevel [Byte0]: 56
3237 06:48:42.987473 [Byte1]: 56
3238 06:48:42.992122
3239 06:48:42.992206 Set Vref, RX VrefLevel [Byte0]: 57
3240 06:48:42.995129 [Byte1]: 57
3241 06:48:42.999150
3242 06:48:42.999233 Set Vref, RX VrefLevel [Byte0]: 58
3243 06:48:43.003013 [Byte1]: 58
3244 06:48:43.007373
3245 06:48:43.007457 Set Vref, RX VrefLevel [Byte0]: 59
3246 06:48:43.010525 [Byte1]: 59
3247 06:48:43.015192
3248 06:48:43.015276 Set Vref, RX VrefLevel [Byte0]: 60
3249 06:48:43.018575 [Byte1]: 60
3250 06:48:43.023621
3251 06:48:43.023704 Set Vref, RX VrefLevel [Byte0]: 61
3252 06:48:43.027006 [Byte1]: 61
3253 06:48:43.031370
3254 06:48:43.031457 Set Vref, RX VrefLevel [Byte0]: 62
3255 06:48:43.034838 [Byte1]: 62
3256 06:48:43.039387
3257 06:48:43.039495 Set Vref, RX VrefLevel [Byte0]: 63
3258 06:48:43.042691 [Byte1]: 63
3259 06:48:43.047140
3260 06:48:43.047230 Set Vref, RX VrefLevel [Byte0]: 64
3261 06:48:43.050750 [Byte1]: 64
3262 06:48:43.055150
3263 06:48:43.055234 Set Vref, RX VrefLevel [Byte0]: 65
3264 06:48:43.058387 [Byte1]: 65
3265 06:48:43.063594
3266 06:48:43.063678 Final RX Vref Byte 0 = 57 to rank0
3267 06:48:43.066339 Final RX Vref Byte 1 = 48 to rank0
3268 06:48:43.069546 Final RX Vref Byte 0 = 57 to rank1
3269 06:48:43.072949 Final RX Vref Byte 1 = 48 to rank1==
3270 06:48:43.076734 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 06:48:43.084212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3272 06:48:43.084297 ==
3273 06:48:43.084400 DQS Delay:
3274 06:48:43.084500 DQS0 = 0, DQS1 = 0
3275 06:48:43.086182 DQM Delay:
3276 06:48:43.086281 DQM0 = 115, DQM1 = 105
3277 06:48:43.090091 DQ Delay:
3278 06:48:43.093529 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3279 06:48:43.096560 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3280 06:48:43.099515 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =98
3281 06:48:43.104884 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =116
3282 06:48:43.104968
3283 06:48:43.105054
3284 06:48:43.110225 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3285 06:48:43.113296 CH1 RK0: MR19=404, MR18=1B1B
3286 06:48:43.119680 CH1_RK0: MR19=0x404, MR18=0x1B1B, DQSOSC=399, MR23=63, INC=41, DEC=27
3287 06:48:43.119764
3288 06:48:43.123132 ----->DramcWriteLeveling(PI) begin...
3289 06:48:43.123217 ==
3290 06:48:43.126447 Dram Type= 6, Freq= 0, CH_1, rank 1
3291 06:48:43.129500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3292 06:48:43.133231 ==
3293 06:48:43.133315 Write leveling (Byte 0): 20 => 20
3294 06:48:43.136479 Write leveling (Byte 1): 21 => 21
3295 06:48:43.139480 DramcWriteLeveling(PI) end<-----
3296 06:48:43.139565
3297 06:48:43.139666 ==
3298 06:48:43.143281 Dram Type= 6, Freq= 0, CH_1, rank 1
3299 06:48:43.149596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3300 06:48:43.149679 ==
3301 06:48:43.149763 [Gating] SW mode calibration
3302 06:48:43.159980 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3303 06:48:43.163347 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3304 06:48:43.166350 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3305 06:48:43.172947 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3306 06:48:43.176627 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3307 06:48:43.179710 0 11 12 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
3308 06:48:43.186607 0 11 16 | B1->B0 | 3232 2323 | 1 0 | (0 1) (1 0)
3309 06:48:43.189382 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3310 06:48:43.193040 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3311 06:48:43.199398 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3312 06:48:43.202486 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3313 06:48:43.206269 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3314 06:48:43.213755 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3315 06:48:43.216034 0 12 12 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
3316 06:48:43.220454 0 12 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3317 06:48:43.226444 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3318 06:48:43.229909 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3319 06:48:43.233288 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3320 06:48:43.239556 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3321 06:48:43.243158 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3322 06:48:43.246394 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3323 06:48:43.253174 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3324 06:48:43.255892 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3325 06:48:43.259332 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3326 06:48:43.266325 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3327 06:48:43.269351 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3328 06:48:43.272860 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3329 06:48:43.275878 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3330 06:48:43.283031 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3331 06:48:43.286135 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3332 06:48:43.289323 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3333 06:48:43.295923 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3334 06:48:43.299626 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3335 06:48:43.302420 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3336 06:48:43.309886 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3337 06:48:43.313006 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3338 06:48:43.316261 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3339 06:48:43.323122 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3340 06:48:43.325990 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3341 06:48:43.330088 Total UI for P1: 0, mck2ui 16
3342 06:48:43.332428 best dqsien dly found for B0: ( 0, 15, 12)
3343 06:48:43.335644 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3344 06:48:43.339219 Total UI for P1: 0, mck2ui 16
3345 06:48:43.342994 best dqsien dly found for B1: ( 0, 15, 14)
3346 06:48:43.345628 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3347 06:48:43.348929 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3348 06:48:43.349004
3349 06:48:43.355747 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3350 06:48:43.359353 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3351 06:48:43.362354 [Gating] SW calibration Done
3352 06:48:43.362428 ==
3353 06:48:43.366295 Dram Type= 6, Freq= 0, CH_1, rank 1
3354 06:48:43.369224 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3355 06:48:43.369301 ==
3356 06:48:43.369365 RX Vref Scan: 0
3357 06:48:43.369425
3358 06:48:43.372794 RX Vref 0 -> 0, step: 1
3359 06:48:43.372891
3360 06:48:43.375931 RX Delay -40 -> 252, step: 8
3361 06:48:43.379440 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3362 06:48:43.382241 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3363 06:48:43.389590 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3364 06:48:43.392315 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3365 06:48:43.395714 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3366 06:48:43.398878 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3367 06:48:43.402255 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3368 06:48:43.407058 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3369 06:48:43.413063 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3370 06:48:43.415545 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3371 06:48:43.419209 iDelay=208, Bit 10, Center 103 (32 ~ 175) 144
3372 06:48:43.422347 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3373 06:48:43.425657 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3374 06:48:43.432416 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3375 06:48:43.436405 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3376 06:48:43.439272 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3377 06:48:43.439375 ==
3378 06:48:43.442845 Dram Type= 6, Freq= 0, CH_1, rank 1
3379 06:48:43.445724 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3380 06:48:43.445824 ==
3381 06:48:43.449253 DQS Delay:
3382 06:48:43.449351 DQS0 = 0, DQS1 = 0
3383 06:48:43.452831 DQM Delay:
3384 06:48:43.452906 DQM0 = 117, DQM1 = 105
3385 06:48:43.452974 DQ Delay:
3386 06:48:43.459728 DQ0 =119, DQ1 =115, DQ2 =111, DQ3 =115
3387 06:48:43.463079 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3388 06:48:43.465861 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3389 06:48:43.468907 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3390 06:48:43.469018
3391 06:48:43.469112
3392 06:48:43.469202 ==
3393 06:48:43.472507 Dram Type= 6, Freq= 0, CH_1, rank 1
3394 06:48:43.476625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3395 06:48:43.476769 ==
3396 06:48:43.476856
3397 06:48:43.476945
3398 06:48:43.479018 TX Vref Scan disable
3399 06:48:43.482262 == TX Byte 0 ==
3400 06:48:43.485513 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3401 06:48:43.489153 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3402 06:48:43.492000 == TX Byte 1 ==
3403 06:48:43.495543 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3404 06:48:43.498937 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3405 06:48:43.499036 ==
3406 06:48:43.502500 Dram Type= 6, Freq= 0, CH_1, rank 1
3407 06:48:43.505336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3408 06:48:43.509080 ==
3409 06:48:43.519369 TX Vref=22, minBit 9, minWin=25, winSum=422
3410 06:48:43.522132 TX Vref=24, minBit 9, minWin=25, winSum=427
3411 06:48:43.525111 TX Vref=26, minBit 8, minWin=26, winSum=429
3412 06:48:43.529236 TX Vref=28, minBit 8, minWin=26, winSum=436
3413 06:48:43.531603 TX Vref=30, minBit 9, minWin=26, winSum=433
3414 06:48:43.535500 TX Vref=32, minBit 9, minWin=26, winSum=434
3415 06:48:43.542299 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 28
3416 06:48:43.542405
3417 06:48:43.545610 Final TX Range 1 Vref 28
3418 06:48:43.545713
3419 06:48:43.545807 ==
3420 06:48:43.549295 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 06:48:43.552516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3422 06:48:43.552615 ==
3423 06:48:43.552716
3424 06:48:43.555999
3425 06:48:43.556097 TX Vref Scan disable
3426 06:48:43.558949 == TX Byte 0 ==
3427 06:48:43.562460 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3428 06:48:43.565065 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3429 06:48:43.568671 == TX Byte 1 ==
3430 06:48:43.572074 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3431 06:48:43.574942 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3432 06:48:43.575054
3433 06:48:43.578857 [DATLAT]
3434 06:48:43.578957 Freq=1200, CH1 RK1
3435 06:48:43.579050
3436 06:48:43.581575 DATLAT Default: 0xc
3437 06:48:43.581674 0, 0xFFFF, sum = 0
3438 06:48:43.585644 1, 0xFFFF, sum = 0
3439 06:48:43.585736 2, 0xFFFF, sum = 0
3440 06:48:43.588242 3, 0xFFFF, sum = 0
3441 06:48:43.588341 4, 0xFFFF, sum = 0
3442 06:48:43.591587 5, 0xFFFF, sum = 0
3443 06:48:43.591687 6, 0xFFFF, sum = 0
3444 06:48:43.596166 7, 0xFFFF, sum = 0
3445 06:48:43.598246 8, 0xFFFF, sum = 0
3446 06:48:43.598347 9, 0xFFFF, sum = 0
3447 06:48:43.601892 10, 0xFFFF, sum = 0
3448 06:48:43.601992 11, 0x0, sum = 1
3449 06:48:43.605105 12, 0x0, sum = 2
3450 06:48:43.605185 13, 0x0, sum = 3
3451 06:48:43.605263 14, 0x0, sum = 4
3452 06:48:43.608781 best_step = 12
3453 06:48:43.608882
3454 06:48:43.608976 ==
3455 06:48:43.611844 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 06:48:43.615187 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3457 06:48:43.615288 ==
3458 06:48:43.618613 RX Vref Scan: 0
3459 06:48:43.618714
3460 06:48:43.618789 RX Vref 0 -> 0, step: 1
3461 06:48:43.621900
3462 06:48:43.621996 RX Delay -29 -> 252, step: 4
3463 06:48:43.628792 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3464 06:48:43.632517 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3465 06:48:43.635295 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3466 06:48:43.639101 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3467 06:48:43.642515 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3468 06:48:43.649113 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3469 06:48:43.652379 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3470 06:48:43.655798 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3471 06:48:43.659585 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3472 06:48:43.663283 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3473 06:48:43.668975 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3474 06:48:43.672248 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3475 06:48:43.675794 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3476 06:48:43.678948 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3477 06:48:43.682096 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3478 06:48:43.689705 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3479 06:48:43.689787 ==
3480 06:48:43.691956 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 06:48:43.695726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3482 06:48:43.695808 ==
3483 06:48:43.695873 DQS Delay:
3484 06:48:43.698668 DQS0 = 0, DQS1 = 0
3485 06:48:43.698749 DQM Delay:
3486 06:48:43.702614 DQM0 = 114, DQM1 = 103
3487 06:48:43.702720 DQ Delay:
3488 06:48:43.706863 DQ0 =114, DQ1 =112, DQ2 =106, DQ3 =112
3489 06:48:43.709272 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3490 06:48:43.712080 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3491 06:48:43.715435 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3492 06:48:43.715534
3493 06:48:43.715637
3494 06:48:43.725692 [DQSOSCAuto] RK1, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3495 06:48:43.725799 CH1 RK1: MR19=404, MR18=808
3496 06:48:43.732485 CH1_RK1: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
3497 06:48:43.735352 [RxdqsGatingPostProcess] freq 1200
3498 06:48:43.742573 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3499 06:48:43.746233 Pre-setting of DQS Precalculation
3500 06:48:43.748745 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3501 06:48:43.755882 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3502 06:48:43.765563 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3503 06:48:43.765667
3504 06:48:43.765761
3505 06:48:43.768924 [Calibration Summary] 2400 Mbps
3506 06:48:43.768998 CH 0, Rank 0
3507 06:48:43.772978 SW Impedance : PASS
3508 06:48:43.773079 DUTY Scan : NO K
3509 06:48:43.775397 ZQ Calibration : PASS
3510 06:48:43.778774 Jitter Meter : NO K
3511 06:48:43.778878 CBT Training : PASS
3512 06:48:43.781973 Write leveling : PASS
3513 06:48:43.785976 RX DQS gating : PASS
3514 06:48:43.786052 RX DQ/DQS(RDDQC) : PASS
3515 06:48:43.789202 TX DQ/DQS : PASS
3516 06:48:43.789312 RX DATLAT : PASS
3517 06:48:43.792108 RX DQ/DQS(Engine): PASS
3518 06:48:43.795481 TX OE : NO K
3519 06:48:43.795580 All Pass.
3520 06:48:43.795669
3521 06:48:43.795759 CH 0, Rank 1
3522 06:48:43.798919 SW Impedance : PASS
3523 06:48:43.802714 DUTY Scan : NO K
3524 06:48:43.802813 ZQ Calibration : PASS
3525 06:48:43.805810 Jitter Meter : NO K
3526 06:48:43.809519 CBT Training : PASS
3527 06:48:43.809620 Write leveling : PASS
3528 06:48:43.812438 RX DQS gating : PASS
3529 06:48:43.815706 RX DQ/DQS(RDDQC) : PASS
3530 06:48:43.815803 TX DQ/DQS : PASS
3531 06:48:43.819093 RX DATLAT : PASS
3532 06:48:43.822790 RX DQ/DQS(Engine): PASS
3533 06:48:43.822887 TX OE : NO K
3534 06:48:43.822985 All Pass.
3535 06:48:43.825719
3536 06:48:43.825815 CH 1, Rank 0
3537 06:48:43.828968 SW Impedance : PASS
3538 06:48:43.829064 DUTY Scan : NO K
3539 06:48:43.832652 ZQ Calibration : PASS
3540 06:48:43.832756 Jitter Meter : NO K
3541 06:48:43.835387 CBT Training : PASS
3542 06:48:43.839098 Write leveling : PASS
3543 06:48:43.839193 RX DQS gating : PASS
3544 06:48:43.842195 RX DQ/DQS(RDDQC) : PASS
3545 06:48:43.845319 TX DQ/DQS : PASS
3546 06:48:43.845417 RX DATLAT : PASS
3547 06:48:43.848896 RX DQ/DQS(Engine): PASS
3548 06:48:43.852377 TX OE : NO K
3549 06:48:43.852483 All Pass.
3550 06:48:43.852576
3551 06:48:43.852662 CH 1, Rank 1
3552 06:48:43.855312 SW Impedance : PASS
3553 06:48:43.858771 DUTY Scan : NO K
3554 06:48:43.858870 ZQ Calibration : PASS
3555 06:48:43.861849 Jitter Meter : NO K
3556 06:48:43.865668 CBT Training : PASS
3557 06:48:43.865764 Write leveling : PASS
3558 06:48:43.868993 RX DQS gating : PASS
3559 06:48:43.871573 RX DQ/DQS(RDDQC) : PASS
3560 06:48:43.871678 TX DQ/DQS : PASS
3561 06:48:43.874957 RX DATLAT : PASS
3562 06:48:43.878517 RX DQ/DQS(Engine): PASS
3563 06:48:43.878624 TX OE : NO K
3564 06:48:43.878715 All Pass.
3565 06:48:43.881996
3566 06:48:43.882096 DramC Write-DBI off
3567 06:48:43.885086 PER_BANK_REFRESH: Hybrid Mode
3568 06:48:43.885181 TX_TRACKING: ON
3569 06:48:43.895040 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3570 06:48:43.898670 [FAST_K] Save calibration result to emmc
3571 06:48:43.902046 dramc_set_vcore_voltage set vcore to 650000
3572 06:48:43.905156 Read voltage for 600, 5
3573 06:48:43.905254 Vio18 = 0
3574 06:48:43.908580 Vcore = 650000
3575 06:48:43.908678 Vdram = 0
3576 06:48:43.908758 Vddq = 0
3577 06:48:43.908827 Vmddr = 0
3578 06:48:43.914856 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3579 06:48:43.922281 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3580 06:48:43.922384 MEM_TYPE=3, freq_sel=19
3581 06:48:43.925190 sv_algorithm_assistance_LP4_1600
3582 06:48:43.928642 ============ PULL DRAM RESETB DOWN ============
3583 06:48:43.935026 ========== PULL DRAM RESETB DOWN end =========
3584 06:48:43.939174 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3585 06:48:43.941702 ===================================
3586 06:48:43.945228 LPDDR4 DRAM CONFIGURATION
3587 06:48:43.948964 ===================================
3588 06:48:43.949040 EX_ROW_EN[0] = 0x0
3589 06:48:43.951621 EX_ROW_EN[1] = 0x0
3590 06:48:43.951726 LP4Y_EN = 0x0
3591 06:48:43.954938 WORK_FSP = 0x0
3592 06:48:43.955034 WL = 0x2
3593 06:48:43.958131 RL = 0x2
3594 06:48:43.958202 BL = 0x2
3595 06:48:43.961655 RPST = 0x0
3596 06:48:43.965018 RD_PRE = 0x0
3597 06:48:43.965099 WR_PRE = 0x1
3598 06:48:43.968132 WR_PST = 0x0
3599 06:48:43.968227 DBI_WR = 0x0
3600 06:48:43.971908 DBI_RD = 0x0
3601 06:48:43.972014 OTF = 0x1
3602 06:48:43.974880 ===================================
3603 06:48:43.978413 ===================================
3604 06:48:43.981881 ANA top config
3605 06:48:43.981982 ===================================
3606 06:48:43.985078 DLL_ASYNC_EN = 0
3607 06:48:43.988070 ALL_SLAVE_EN = 1
3608 06:48:43.991747 NEW_RANK_MODE = 1
3609 06:48:43.994502 DLL_IDLE_MODE = 1
3610 06:48:43.994603 LP45_APHY_COMB_EN = 1
3611 06:48:43.998106 TX_ODT_DIS = 1
3612 06:48:44.001759 NEW_8X_MODE = 1
3613 06:48:44.005183 ===================================
3614 06:48:44.008255 ===================================
3615 06:48:44.011549 data_rate = 1200
3616 06:48:44.014486 CKR = 1
3617 06:48:44.018058 DQ_P2S_RATIO = 8
3618 06:48:44.021032 ===================================
3619 06:48:44.021136 CA_P2S_RATIO = 8
3620 06:48:44.024971 DQ_CA_OPEN = 0
3621 06:48:44.028246 DQ_SEMI_OPEN = 0
3622 06:48:44.031005 CA_SEMI_OPEN = 0
3623 06:48:44.034698 CA_FULL_RATE = 0
3624 06:48:44.034798 DQ_CKDIV4_EN = 1
3625 06:48:44.037787 CA_CKDIV4_EN = 1
3626 06:48:44.041904 CA_PREDIV_EN = 0
3627 06:48:44.044988 PH8_DLY = 0
3628 06:48:44.047768 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3629 06:48:44.050993 DQ_AAMCK_DIV = 4
3630 06:48:44.051092 CA_AAMCK_DIV = 4
3631 06:48:44.054464 CA_ADMCK_DIV = 4
3632 06:48:44.058091 DQ_TRACK_CA_EN = 0
3633 06:48:44.061230 CA_PICK = 600
3634 06:48:44.064323 CA_MCKIO = 600
3635 06:48:44.068197 MCKIO_SEMI = 0
3636 06:48:44.070807 PLL_FREQ = 2288
3637 06:48:44.074651 DQ_UI_PI_RATIO = 32
3638 06:48:44.074749 CA_UI_PI_RATIO = 0
3639 06:48:44.077399 ===================================
3640 06:48:44.081253 ===================================
3641 06:48:44.084902 memory_type:LPDDR4
3642 06:48:44.087469 GP_NUM : 10
3643 06:48:44.087565 SRAM_EN : 1
3644 06:48:44.091061 MD32_EN : 0
3645 06:48:44.094988 ===================================
3646 06:48:44.097353 [ANA_INIT] >>>>>>>>>>>>>>
3647 06:48:44.097450 <<<<<< [CONFIGURE PHASE]: ANA_TX
3648 06:48:44.104329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3649 06:48:44.107831 ===================================
3650 06:48:44.107944 data_rate = 1200,PCW = 0X5800
3651 06:48:44.110594 ===================================
3652 06:48:44.114247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3653 06:48:44.120580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3654 06:48:44.127472 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3655 06:48:44.130410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3656 06:48:44.133712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3657 06:48:44.137992 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3658 06:48:44.140611 [ANA_INIT] flow start
3659 06:48:44.140756 [ANA_INIT] PLL >>>>>>>>
3660 06:48:44.143664 [ANA_INIT] PLL <<<<<<<<
3661 06:48:44.147201 [ANA_INIT] MIDPI >>>>>>>>
3662 06:48:44.150509 [ANA_INIT] MIDPI <<<<<<<<
3663 06:48:44.150609 [ANA_INIT] DLL >>>>>>>>
3664 06:48:44.153809 [ANA_INIT] flow end
3665 06:48:44.157089 ============ LP4 DIFF to SE enter ============
3666 06:48:44.160606 ============ LP4 DIFF to SE exit ============
3667 06:48:44.164353 [ANA_INIT] <<<<<<<<<<<<<
3668 06:48:44.167418 [Flow] Enable top DCM control >>>>>
3669 06:48:44.170625 [Flow] Enable top DCM control <<<<<
3670 06:48:44.173502 Enable DLL master slave shuffle
3671 06:48:44.181048 ==============================================================
3672 06:48:44.181129 Gating Mode config
3673 06:48:44.186675 ==============================================================
3674 06:48:44.186779 Config description:
3675 06:48:44.197644 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3676 06:48:44.203539 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3677 06:48:44.210224 SELPH_MODE 0: By rank 1: By Phase
3678 06:48:44.213267 ==============================================================
3679 06:48:44.217643 GAT_TRACK_EN = 1
3680 06:48:44.220002 RX_GATING_MODE = 2
3681 06:48:44.223670 RX_GATING_TRACK_MODE = 2
3682 06:48:44.226612 SELPH_MODE = 1
3683 06:48:44.230835 PICG_EARLY_EN = 1
3684 06:48:44.233217 VALID_LAT_VALUE = 1
3685 06:48:44.239823 ==============================================================
3686 06:48:44.242930 Enter into Gating configuration >>>>
3687 06:48:44.246490 Exit from Gating configuration <<<<
3688 06:48:44.246571 Enter into DVFS_PRE_config >>>>>
3689 06:48:44.259956 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3690 06:48:44.263753 Exit from DVFS_PRE_config <<<<<
3691 06:48:44.266932 Enter into PICG configuration >>>>
3692 06:48:44.270055 Exit from PICG configuration <<<<
3693 06:48:44.270137 [RX_INPUT] configuration >>>>>
3694 06:48:44.273059 [RX_INPUT] configuration <<<<<
3695 06:48:44.279471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3696 06:48:44.286588 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3697 06:48:44.289644 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3698 06:48:44.295932 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3699 06:48:44.302731 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3700 06:48:44.309799 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3701 06:48:44.312610 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3702 06:48:44.316199 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3703 06:48:44.323640 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3704 06:48:44.325973 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3705 06:48:44.329330 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3706 06:48:44.335872 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3707 06:48:44.339500 ===================================
3708 06:48:44.339581 LPDDR4 DRAM CONFIGURATION
3709 06:48:44.342666 ===================================
3710 06:48:44.345810 EX_ROW_EN[0] = 0x0
3711 06:48:44.345891 EX_ROW_EN[1] = 0x0
3712 06:48:44.349278 LP4Y_EN = 0x0
3713 06:48:44.349359 WORK_FSP = 0x0
3714 06:48:44.352728 WL = 0x2
3715 06:48:44.355548 RL = 0x2
3716 06:48:44.355629 BL = 0x2
3717 06:48:44.358808 RPST = 0x0
3718 06:48:44.358889 RD_PRE = 0x0
3719 06:48:44.362817 WR_PRE = 0x1
3720 06:48:44.362898 WR_PST = 0x0
3721 06:48:44.365931 DBI_WR = 0x0
3722 06:48:44.366012 DBI_RD = 0x0
3723 06:48:44.369085 OTF = 0x1
3724 06:48:44.372687 ===================================
3725 06:48:44.375854 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3726 06:48:44.379046 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3727 06:48:44.382918 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3728 06:48:44.386130 ===================================
3729 06:48:44.388924 LPDDR4 DRAM CONFIGURATION
3730 06:48:44.392674 ===================================
3731 06:48:44.395429 EX_ROW_EN[0] = 0x10
3732 06:48:44.395509 EX_ROW_EN[1] = 0x0
3733 06:48:44.398815 LP4Y_EN = 0x0
3734 06:48:44.398896 WORK_FSP = 0x0
3735 06:48:44.402051 WL = 0x2
3736 06:48:44.402131 RL = 0x2
3737 06:48:44.405350 BL = 0x2
3738 06:48:44.408676 RPST = 0x0
3739 06:48:44.408794 RD_PRE = 0x0
3740 06:48:44.411908 WR_PRE = 0x1
3741 06:48:44.411989 WR_PST = 0x0
3742 06:48:44.415418 DBI_WR = 0x0
3743 06:48:44.415499 DBI_RD = 0x0
3744 06:48:44.418681 OTF = 0x1
3745 06:48:44.422207 ===================================
3746 06:48:44.427096 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3747 06:48:44.431166 nWR fixed to 30
3748 06:48:44.434102 [ModeRegInit_LP4] CH0 RK0
3749 06:48:44.434184 [ModeRegInit_LP4] CH0 RK1
3750 06:48:44.437453 [ModeRegInit_LP4] CH1 RK0
3751 06:48:44.440697 [ModeRegInit_LP4] CH1 RK1
3752 06:48:44.440799 match AC timing 16
3753 06:48:44.447531 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3754 06:48:44.451214 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3755 06:48:44.453613 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3756 06:48:44.460767 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3757 06:48:44.464485 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3758 06:48:44.464566 ==
3759 06:48:44.467923 Dram Type= 6, Freq= 0, CH_0, rank 0
3760 06:48:44.470279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3761 06:48:44.470361 ==
3762 06:48:44.477151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3763 06:48:44.484776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3764 06:48:44.487679 [CA 0] Center 35 (5~66) winsize 62
3765 06:48:44.490398 [CA 1] Center 35 (5~66) winsize 62
3766 06:48:44.494710 [CA 2] Center 34 (4~65) winsize 62
3767 06:48:44.497614 [CA 3] Center 34 (4~65) winsize 62
3768 06:48:44.500556 [CA 4] Center 33 (3~64) winsize 62
3769 06:48:44.504471 [CA 5] Center 33 (3~64) winsize 62
3770 06:48:44.504552
3771 06:48:44.507126 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3772 06:48:44.507206
3773 06:48:44.510446 [CATrainingPosCal] consider 1 rank data
3774 06:48:44.513995 u2DelayCellTimex100 = 270/100 ps
3775 06:48:44.516802 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3776 06:48:44.520100 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3777 06:48:44.523518 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3778 06:48:44.526656 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3779 06:48:44.530092 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3780 06:48:44.537844 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3781 06:48:44.537925
3782 06:48:44.539665 CA PerBit enable=1, Macro0, CA PI delay=33
3783 06:48:44.539746
3784 06:48:44.543301 [CBTSetCACLKResult] CA Dly = 33
3785 06:48:44.543383 CS Dly: 4 (0~35)
3786 06:48:44.543448 ==
3787 06:48:44.546899 Dram Type= 6, Freq= 0, CH_0, rank 1
3788 06:48:44.550186 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3789 06:48:44.552960 ==
3790 06:48:44.557377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3791 06:48:44.563169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3792 06:48:44.566361 [CA 0] Center 35 (5~66) winsize 62
3793 06:48:44.569633 [CA 1] Center 35 (5~66) winsize 62
3794 06:48:44.573500 [CA 2] Center 34 (4~65) winsize 62
3795 06:48:44.576328 [CA 3] Center 34 (4~65) winsize 62
3796 06:48:44.579598 [CA 4] Center 33 (3~64) winsize 62
3797 06:48:44.582856 [CA 5] Center 33 (3~64) winsize 62
3798 06:48:44.582937
3799 06:48:44.586395 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3800 06:48:44.586476
3801 06:48:44.590012 [CATrainingPosCal] consider 2 rank data
3802 06:48:44.593422 u2DelayCellTimex100 = 270/100 ps
3803 06:48:44.596965 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3804 06:48:44.600213 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3805 06:48:44.603133 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3806 06:48:44.609354 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3807 06:48:44.613057 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3808 06:48:44.616121 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3809 06:48:44.616202
3810 06:48:44.619177 CA PerBit enable=1, Macro0, CA PI delay=33
3811 06:48:44.619258
3812 06:48:44.622716 [CBTSetCACLKResult] CA Dly = 33
3813 06:48:44.622797 CS Dly: 4 (0~36)
3814 06:48:44.622861
3815 06:48:44.625957 ----->DramcWriteLeveling(PI) begin...
3816 06:48:44.626040 ==
3817 06:48:44.629119 Dram Type= 6, Freq= 0, CH_0, rank 0
3818 06:48:44.635794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3819 06:48:44.635876 ==
3820 06:48:44.638998 Write leveling (Byte 0): 31 => 31
3821 06:48:44.642446 Write leveling (Byte 1): 31 => 31
3822 06:48:44.646214 DramcWriteLeveling(PI) end<-----
3823 06:48:44.646295
3824 06:48:44.646395 ==
3825 06:48:44.649369 Dram Type= 6, Freq= 0, CH_0, rank 0
3826 06:48:44.652212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3827 06:48:44.652293 ==
3828 06:48:44.655967 [Gating] SW mode calibration
3829 06:48:44.663898 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3830 06:48:44.666024 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3831 06:48:44.672544 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3832 06:48:44.675507 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3833 06:48:44.679046 0 5 8 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (1 0)
3834 06:48:44.685570 0 5 12 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
3835 06:48:44.689250 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3836 06:48:44.692128 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3837 06:48:44.698528 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3838 06:48:44.703023 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3839 06:48:44.705252 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3840 06:48:44.711817 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3841 06:48:44.715485 0 6 8 | B1->B0 | 2626 3232 | 0 0 | (0 0) (1 1)
3842 06:48:44.719056 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3843 06:48:44.725910 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3844 06:48:44.728315 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3845 06:48:44.732127 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3846 06:48:44.738683 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3847 06:48:44.741561 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3848 06:48:44.745367 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3849 06:48:44.751467 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3850 06:48:44.754959 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3851 06:48:44.758283 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3852 06:48:44.764745 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3853 06:48:44.768418 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3854 06:48:44.772349 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3855 06:48:44.778516 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3856 06:48:44.781321 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3857 06:48:44.784619 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3858 06:48:44.791319 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3859 06:48:44.794371 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3860 06:48:44.798615 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3861 06:48:44.804591 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3862 06:48:44.807556 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3863 06:48:44.811140 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3864 06:48:44.817960 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3865 06:48:44.821580 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3866 06:48:44.824261 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3867 06:48:44.828111 Total UI for P1: 0, mck2ui 16
3868 06:48:44.831234 best dqsien dly found for B0: ( 0, 9, 10)
3869 06:48:44.834216 Total UI for P1: 0, mck2ui 16
3870 06:48:44.837708 best dqsien dly found for B1: ( 0, 9, 10)
3871 06:48:44.841694 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3872 06:48:44.844604 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3873 06:48:44.844700
3874 06:48:44.850991 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3875 06:48:44.854117 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3876 06:48:44.857892 [Gating] SW calibration Done
3877 06:48:44.857990 ==
3878 06:48:44.861200 Dram Type= 6, Freq= 0, CH_0, rank 0
3879 06:48:44.864285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3880 06:48:44.864383 ==
3881 06:48:44.864473 RX Vref Scan: 0
3882 06:48:44.864571
3883 06:48:44.867386 RX Vref 0 -> 0, step: 1
3884 06:48:44.867492
3885 06:48:44.870725 RX Delay -230 -> 252, step: 16
3886 06:48:44.874407 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3887 06:48:44.877508 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3888 06:48:44.884053 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3889 06:48:44.887538 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3890 06:48:44.890784 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3891 06:48:44.894789 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3892 06:48:44.901266 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3893 06:48:44.904175 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3894 06:48:44.908447 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3895 06:48:44.910594 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3896 06:48:44.914434 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3897 06:48:44.921762 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3898 06:48:44.924023 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3899 06:48:44.927129 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3900 06:48:44.930864 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3901 06:48:44.937524 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3902 06:48:44.937619 ==
3903 06:48:44.940623 Dram Type= 6, Freq= 0, CH_0, rank 0
3904 06:48:44.944239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3905 06:48:44.944350 ==
3906 06:48:44.944442 DQS Delay:
3907 06:48:44.946971 DQS0 = 0, DQS1 = 0
3908 06:48:44.947076 DQM Delay:
3909 06:48:44.951002 DQM0 = 38, DQM1 = 33
3910 06:48:44.951102 DQ Delay:
3911 06:48:44.954124 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3912 06:48:44.957480 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3913 06:48:44.960227 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3914 06:48:44.964309 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3915 06:48:44.964404
3916 06:48:44.964501
3917 06:48:44.964591 ==
3918 06:48:44.967034 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 06:48:44.971213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3920 06:48:44.973701 ==
3921 06:48:44.973798
3922 06:48:44.973886
3923 06:48:44.973985 TX Vref Scan disable
3924 06:48:44.976979 == TX Byte 0 ==
3925 06:48:44.980667 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3926 06:48:44.983471 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3927 06:48:44.986911 == TX Byte 1 ==
3928 06:48:44.990010 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3929 06:48:44.996872 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3930 06:48:44.996951 ==
3931 06:48:45.000977 Dram Type= 6, Freq= 0, CH_0, rank 0
3932 06:48:45.003967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3933 06:48:45.004071 ==
3934 06:48:45.004162
3935 06:48:45.004261
3936 06:48:45.006405 TX Vref Scan disable
3937 06:48:45.006516 == TX Byte 0 ==
3938 06:48:45.013393 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3939 06:48:45.016332 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3940 06:48:45.020036 == TX Byte 1 ==
3941 06:48:45.023385 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3942 06:48:45.026640 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3943 06:48:45.026712
3944 06:48:45.026776 [DATLAT]
3945 06:48:45.030421 Freq=600, CH0 RK0
3946 06:48:45.030496
3947 06:48:45.030558 DATLAT Default: 0x9
3948 06:48:45.032887 0, 0xFFFF, sum = 0
3949 06:48:45.036947 1, 0xFFFF, sum = 0
3950 06:48:45.037026 2, 0xFFFF, sum = 0
3951 06:48:45.040139 3, 0xFFFF, sum = 0
3952 06:48:45.040241 4, 0xFFFF, sum = 0
3953 06:48:45.043122 5, 0xFFFF, sum = 0
3954 06:48:45.043213 6, 0xFFFF, sum = 0
3955 06:48:45.047401 7, 0x0, sum = 1
3956 06:48:45.047486 8, 0x0, sum = 2
3957 06:48:45.047552 9, 0x0, sum = 3
3958 06:48:45.049659 10, 0x0, sum = 4
3959 06:48:45.049742 best_step = 8
3960 06:48:45.049806
3961 06:48:45.049865 ==
3962 06:48:45.052783 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 06:48:45.059637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3964 06:48:45.059719 ==
3965 06:48:45.059783 RX Vref Scan: 1
3966 06:48:45.059844
3967 06:48:45.063406 RX Vref 0 -> 0, step: 1
3968 06:48:45.063487
3969 06:48:45.066956 RX Delay -195 -> 252, step: 8
3970 06:48:45.067037
3971 06:48:45.069865 Set Vref, RX VrefLevel [Byte0]: 52
3972 06:48:45.072942 [Byte1]: 48
3973 06:48:45.073023
3974 06:48:45.076352 Final RX Vref Byte 0 = 52 to rank0
3975 06:48:45.079771 Final RX Vref Byte 1 = 48 to rank0
3976 06:48:45.083821 Final RX Vref Byte 0 = 52 to rank1
3977 06:48:45.086622 Final RX Vref Byte 1 = 48 to rank1==
3978 06:48:45.089522 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 06:48:45.092726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3980 06:48:45.092807 ==
3981 06:48:45.096432 DQS Delay:
3982 06:48:45.096512 DQS0 = 0, DQS1 = 0
3983 06:48:45.099697 DQM Delay:
3984 06:48:45.099778 DQM0 = 39, DQM1 = 29
3985 06:48:45.099842 DQ Delay:
3986 06:48:45.102987 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3987 06:48:45.105945 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
3988 06:48:45.109219 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3989 06:48:45.112725 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
3990 06:48:45.112837
3991 06:48:45.112929
3992 06:48:45.122920 [DQSOSCAuto] RK0, (LSB)MR18= 0x5656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3993 06:48:45.126628 CH0 RK0: MR19=808, MR18=5656
3994 06:48:45.132366 CH0_RK0: MR19=0x808, MR18=0x5656, DQSOSC=393, MR23=63, INC=169, DEC=113
3995 06:48:45.132447
3996 06:48:45.136136 ----->DramcWriteLeveling(PI) begin...
3997 06:48:45.136219 ==
3998 06:48:45.139186 Dram Type= 6, Freq= 0, CH_0, rank 1
3999 06:48:45.142258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4000 06:48:45.142344 ==
4001 06:48:45.145491 Write leveling (Byte 0): 30 => 30
4002 06:48:45.149215 Write leveling (Byte 1): 28 => 28
4003 06:48:45.152516 DramcWriteLeveling(PI) end<-----
4004 06:48:45.152600
4005 06:48:45.152702 ==
4006 06:48:45.156412 Dram Type= 6, Freq= 0, CH_0, rank 1
4007 06:48:45.158975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4008 06:48:45.159063 ==
4009 06:48:45.163397 [Gating] SW mode calibration
4010 06:48:45.169082 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4011 06:48:45.175637 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4012 06:48:45.179176 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 06:48:45.182644 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 06:48:45.189967 0 5 8 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 0)
4015 06:48:45.191810 0 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4016 06:48:45.195367 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 06:48:45.202835 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 06:48:45.205254 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 06:48:45.208652 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 06:48:45.215397 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 06:48:45.218517 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 06:48:45.222045 0 6 8 | B1->B0 | 2d2d 3535 | 0 0 | (0 0) (0 0)
4023 06:48:45.229869 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
4024 06:48:45.232514 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 06:48:45.235223 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 06:48:45.242186 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 06:48:45.245163 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 06:48:45.248667 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 06:48:45.255193 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 06:48:45.258738 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4031 06:48:45.262036 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4032 06:48:45.268431 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 06:48:45.272863 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 06:48:45.274865 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 06:48:45.281585 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 06:48:45.285291 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 06:48:45.288013 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 06:48:45.294689 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 06:48:45.298478 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 06:48:45.301430 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 06:48:45.304632 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 06:48:45.311563 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 06:48:45.314524 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 06:48:45.318315 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 06:48:45.324777 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4046 06:48:45.327949 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4047 06:48:45.331130 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 06:48:45.334929 Total UI for P1: 0, mck2ui 16
4049 06:48:45.338906 best dqsien dly found for B0: ( 0, 9, 6)
4050 06:48:45.341356 Total UI for P1: 0, mck2ui 16
4051 06:48:45.344148 best dqsien dly found for B1: ( 0, 9, 6)
4052 06:48:45.348311 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4053 06:48:45.351431 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4054 06:48:45.351515
4055 06:48:45.358068 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4056 06:48:45.361660 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4057 06:48:45.364524 [Gating] SW calibration Done
4058 06:48:45.364608 ==
4059 06:48:45.367954 Dram Type= 6, Freq= 0, CH_0, rank 1
4060 06:48:45.370923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4061 06:48:45.371007 ==
4062 06:48:45.371109 RX Vref Scan: 0
4063 06:48:45.371208
4064 06:48:45.374343 RX Vref 0 -> 0, step: 1
4065 06:48:45.374427
4066 06:48:45.378032 RX Delay -230 -> 252, step: 16
4067 06:48:45.381558 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4068 06:48:45.384368 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4069 06:48:45.391213 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4070 06:48:45.394496 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4071 06:48:45.398049 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4072 06:48:45.400982 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4073 06:48:45.407995 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4074 06:48:45.411121 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4075 06:48:45.414446 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4076 06:48:45.417166 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4077 06:48:45.420791 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4078 06:48:45.426998 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4079 06:48:45.430714 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4080 06:48:45.433850 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4081 06:48:45.440847 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4082 06:48:45.443690 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4083 06:48:45.443774 ==
4084 06:48:45.447052 Dram Type= 6, Freq= 0, CH_0, rank 1
4085 06:48:45.450758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4086 06:48:45.450843 ==
4087 06:48:45.450929 DQS Delay:
4088 06:48:45.454268 DQS0 = 0, DQS1 = 0
4089 06:48:45.454352 DQM Delay:
4090 06:48:45.457300 DQM0 = 44, DQM1 = 33
4091 06:48:45.457384 DQ Delay:
4092 06:48:45.460758 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4093 06:48:45.463569 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =57
4094 06:48:45.467097 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4095 06:48:45.470640 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4096 06:48:45.470724
4097 06:48:45.470808
4098 06:48:45.470888 ==
4099 06:48:45.473708 Dram Type= 6, Freq= 0, CH_0, rank 1
4100 06:48:45.477320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4101 06:48:45.480323 ==
4102 06:48:45.480406
4103 06:48:45.480507
4104 06:48:45.480605 TX Vref Scan disable
4105 06:48:45.483724 == TX Byte 0 ==
4106 06:48:45.487011 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4107 06:48:45.490377 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4108 06:48:45.493854 == TX Byte 1 ==
4109 06:48:45.496998 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4110 06:48:45.503640 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4111 06:48:45.503724 ==
4112 06:48:45.507367 Dram Type= 6, Freq= 0, CH_0, rank 1
4113 06:48:45.510640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4114 06:48:45.510725 ==
4115 06:48:45.510810
4116 06:48:45.510890
4117 06:48:45.514202 TX Vref Scan disable
4118 06:48:45.517298 == TX Byte 0 ==
4119 06:48:45.520074 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4120 06:48:45.523322 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4121 06:48:45.526851 == TX Byte 1 ==
4122 06:48:45.530139 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4123 06:48:45.533518 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4124 06:48:45.533603
4125 06:48:45.533688 [DATLAT]
4126 06:48:45.536753 Freq=600, CH0 RK1
4127 06:48:45.536836
4128 06:48:45.539622 DATLAT Default: 0x8
4129 06:48:45.539706 0, 0xFFFF, sum = 0
4130 06:48:45.543760 1, 0xFFFF, sum = 0
4131 06:48:45.543846 2, 0xFFFF, sum = 0
4132 06:48:45.546442 3, 0xFFFF, sum = 0
4133 06:48:45.546527 4, 0xFFFF, sum = 0
4134 06:48:45.549828 5, 0xFFFF, sum = 0
4135 06:48:45.549913 6, 0xFFFF, sum = 0
4136 06:48:45.553101 7, 0x0, sum = 1
4137 06:48:45.553186 8, 0x0, sum = 2
4138 06:48:45.553272 9, 0x0, sum = 3
4139 06:48:45.556472 10, 0x0, sum = 4
4140 06:48:45.556557 best_step = 8
4141 06:48:45.556658
4142 06:48:45.556789 ==
4143 06:48:45.559652 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 06:48:45.566311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4145 06:48:45.566396 ==
4146 06:48:45.566482 RX Vref Scan: 0
4147 06:48:45.566562
4148 06:48:45.569945 RX Vref 0 -> 0, step: 1
4149 06:48:45.570029
4150 06:48:45.573355 RX Delay -195 -> 252, step: 8
4151 06:48:45.576460 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4152 06:48:45.582975 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4153 06:48:45.586262 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4154 06:48:45.589776 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4155 06:48:45.593089 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4156 06:48:45.599500 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4157 06:48:45.602672 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4158 06:48:45.605942 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4159 06:48:45.609254 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4160 06:48:45.615911 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4161 06:48:45.619221 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4162 06:48:45.622873 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4163 06:48:45.625629 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4164 06:48:45.632657 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4165 06:48:45.635652 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4166 06:48:45.640113 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4167 06:48:45.640196 ==
4168 06:48:45.642557 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 06:48:45.645892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4170 06:48:45.645977 ==
4171 06:48:45.648664 DQS Delay:
4172 06:48:45.648787 DQS0 = 0, DQS1 = 0
4173 06:48:45.652114 DQM Delay:
4174 06:48:45.652198 DQM0 = 42, DQM1 = 33
4175 06:48:45.652283 DQ Delay:
4176 06:48:45.655685 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4177 06:48:45.658878 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =48
4178 06:48:45.662518 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4179 06:48:45.665540 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4180 06:48:45.665624
4181 06:48:45.665709
4182 06:48:45.675950 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d6d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4183 06:48:45.679231 CH0 RK1: MR19=808, MR18=6D6D
4184 06:48:45.685301 CH0_RK1: MR19=0x808, MR18=0x6D6D, DQSOSC=389, MR23=63, INC=173, DEC=115
4185 06:48:45.689003 [RxdqsGatingPostProcess] freq 600
4186 06:48:45.692485 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4187 06:48:45.696097 Pre-setting of DQS Precalculation
4188 06:48:45.702116 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4189 06:48:45.702200 ==
4190 06:48:45.705070 Dram Type= 6, Freq= 0, CH_1, rank 0
4191 06:48:45.709654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4192 06:48:45.709742 ==
4193 06:48:45.715316 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4194 06:48:45.718479 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4195 06:48:45.722414 [CA 0] Center 35 (5~66) winsize 62
4196 06:48:45.726005 [CA 1] Center 35 (5~66) winsize 62
4197 06:48:45.729292 [CA 2] Center 33 (3~64) winsize 62
4198 06:48:45.732677 [CA 3] Center 33 (3~64) winsize 62
4199 06:48:45.735878 [CA 4] Center 33 (2~64) winsize 63
4200 06:48:45.739747 [CA 5] Center 33 (2~64) winsize 63
4201 06:48:45.739831
4202 06:48:45.742494 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4203 06:48:45.742577
4204 06:48:45.745577 [CATrainingPosCal] consider 1 rank data
4205 06:48:45.748700 u2DelayCellTimex100 = 270/100 ps
4206 06:48:45.752475 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4207 06:48:45.759236 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4208 06:48:45.762203 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4209 06:48:45.765650 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4210 06:48:45.768990 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4211 06:48:45.772650 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4212 06:48:45.772758
4213 06:48:45.776046 CA PerBit enable=1, Macro0, CA PI delay=33
4214 06:48:45.776130
4215 06:48:45.778830 [CBTSetCACLKResult] CA Dly = 33
4216 06:48:45.778914 CS Dly: 4 (0~35)
4217 06:48:45.782853 ==
4218 06:48:45.782937 Dram Type= 6, Freq= 0, CH_1, rank 1
4219 06:48:45.788984 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4220 06:48:45.789068 ==
4221 06:48:45.792205 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4222 06:48:45.799105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4223 06:48:45.803125 [CA 0] Center 35 (5~66) winsize 62
4224 06:48:45.806070 [CA 1] Center 34 (4~65) winsize 62
4225 06:48:45.808942 [CA 2] Center 33 (3~64) winsize 62
4226 06:48:45.812740 [CA 3] Center 33 (3~64) winsize 62
4227 06:48:45.816260 [CA 4] Center 32 (2~63) winsize 62
4228 06:48:45.818884 [CA 5] Center 32 (2~63) winsize 62
4229 06:48:45.818968
4230 06:48:45.822284 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4231 06:48:45.822368
4232 06:48:45.825828 [CATrainingPosCal] consider 2 rank data
4233 06:48:45.829409 u2DelayCellTimex100 = 270/100 ps
4234 06:48:45.832664 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4235 06:48:45.839017 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4236 06:48:45.842787 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4237 06:48:45.845570 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4238 06:48:45.848908 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4239 06:48:45.852316 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4240 06:48:45.852400
4241 06:48:45.856586 CA PerBit enable=1, Macro0, CA PI delay=32
4242 06:48:45.856670
4243 06:48:45.859063 [CBTSetCACLKResult] CA Dly = 32
4244 06:48:45.859147 CS Dly: 4 (0~36)
4245 06:48:45.862320
4246 06:48:45.865180 ----->DramcWriteLeveling(PI) begin...
4247 06:48:45.865266 ==
4248 06:48:45.869599 Dram Type= 6, Freq= 0, CH_1, rank 0
4249 06:48:45.872270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4250 06:48:45.872355 ==
4251 06:48:45.875491 Write leveling (Byte 0): 27 => 27
4252 06:48:45.879556 Write leveling (Byte 1): 26 => 26
4253 06:48:45.881923 DramcWriteLeveling(PI) end<-----
4254 06:48:45.882007
4255 06:48:45.882095 ==
4256 06:48:45.886296 Dram Type= 6, Freq= 0, CH_1, rank 0
4257 06:48:45.888546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4258 06:48:45.888631 ==
4259 06:48:45.892220 [Gating] SW mode calibration
4260 06:48:45.898607 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4261 06:48:45.904878 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4262 06:48:45.908667 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4263 06:48:45.911676 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4264 06:48:45.918670 0 5 8 | B1->B0 | 3030 2b2b | 0 0 | (1 1) (0 0)
4265 06:48:45.922126 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 06:48:45.925101 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 06:48:45.931308 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 06:48:45.934862 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 06:48:45.938404 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 06:48:45.944468 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 06:48:45.947912 0 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4272 06:48:45.951606 0 6 8 | B1->B0 | 3535 3f3f | 0 1 | (0 0) (0 0)
4273 06:48:45.957946 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 06:48:45.962823 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 06:48:45.964627 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 06:48:45.971178 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 06:48:45.974599 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 06:48:45.978033 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 06:48:45.984236 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 06:48:45.987919 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4281 06:48:45.991633 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 06:48:45.998395 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 06:48:46.001073 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 06:48:46.004221 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 06:48:46.010958 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 06:48:46.015351 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 06:48:46.017365 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 06:48:46.024051 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 06:48:46.027480 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 06:48:46.031340 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 06:48:46.037865 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 06:48:46.040411 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 06:48:46.043708 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 06:48:46.051208 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 06:48:46.054097 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4296 06:48:46.057429 Total UI for P1: 0, mck2ui 16
4297 06:48:46.060357 best dqsien dly found for B0: ( 0, 9, 2)
4298 06:48:46.063812 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4299 06:48:46.067865 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 06:48:46.070544 Total UI for P1: 0, mck2ui 16
4301 06:48:46.073830 best dqsien dly found for B1: ( 0, 9, 10)
4302 06:48:46.077000 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4303 06:48:46.083720 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4304 06:48:46.083819
4305 06:48:46.087165 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4306 06:48:46.091329 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4307 06:48:46.093804 [Gating] SW calibration Done
4308 06:48:46.093884 ==
4309 06:48:46.096670 Dram Type= 6, Freq= 0, CH_1, rank 0
4310 06:48:46.100100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4311 06:48:46.100196 ==
4312 06:48:46.104415 RX Vref Scan: 0
4313 06:48:46.104494
4314 06:48:46.104558 RX Vref 0 -> 0, step: 1
4315 06:48:46.104617
4316 06:48:46.106610 RX Delay -230 -> 252, step: 16
4317 06:48:46.110762 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4318 06:48:46.116751 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4319 06:48:46.120159 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4320 06:48:46.123377 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4321 06:48:46.126535 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4322 06:48:46.130113 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4323 06:48:46.136874 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4324 06:48:46.139798 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4325 06:48:46.143705 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4326 06:48:46.146571 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4327 06:48:46.153187 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4328 06:48:46.157434 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4329 06:48:46.159630 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4330 06:48:46.163550 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4331 06:48:46.169859 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4332 06:48:46.173272 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4333 06:48:46.173353 ==
4334 06:48:46.176835 Dram Type= 6, Freq= 0, CH_1, rank 0
4335 06:48:46.180212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4336 06:48:46.180294 ==
4337 06:48:46.183168 DQS Delay:
4338 06:48:46.183267 DQS0 = 0, DQS1 = 0
4339 06:48:46.183357 DQM Delay:
4340 06:48:46.186283 DQM0 = 38, DQM1 = 30
4341 06:48:46.186364 DQ Delay:
4342 06:48:46.189635 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4343 06:48:46.192716 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4344 06:48:46.196944 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4345 06:48:46.199358 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4346 06:48:46.199439
4347 06:48:46.199502
4348 06:48:46.199561 ==
4349 06:48:46.203163 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 06:48:46.209223 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4351 06:48:46.209305 ==
4352 06:48:46.209369
4353 06:48:46.209428
4354 06:48:46.209485 TX Vref Scan disable
4355 06:48:46.213202 == TX Byte 0 ==
4356 06:48:46.216942 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4357 06:48:46.220236 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4358 06:48:46.223736 == TX Byte 1 ==
4359 06:48:46.226753 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4360 06:48:46.230200 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4361 06:48:46.233254 ==
4362 06:48:46.236443 Dram Type= 6, Freq= 0, CH_1, rank 0
4363 06:48:46.239826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4364 06:48:46.239941 ==
4365 06:48:46.240037
4366 06:48:46.240125
4367 06:48:46.243073 TX Vref Scan disable
4368 06:48:46.243182 == TX Byte 0 ==
4369 06:48:46.250181 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4370 06:48:46.252976 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4371 06:48:46.253071 == TX Byte 1 ==
4372 06:48:46.259813 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4373 06:48:46.263507 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4374 06:48:46.263605
4375 06:48:46.263695 [DATLAT]
4376 06:48:46.266549 Freq=600, CH1 RK0
4377 06:48:46.266644
4378 06:48:46.266732 DATLAT Default: 0x9
4379 06:48:46.269961 0, 0xFFFF, sum = 0
4380 06:48:46.270052 1, 0xFFFF, sum = 0
4381 06:48:46.272813 2, 0xFFFF, sum = 0
4382 06:48:46.276809 3, 0xFFFF, sum = 0
4383 06:48:46.276916 4, 0xFFFF, sum = 0
4384 06:48:46.279828 5, 0xFFFF, sum = 0
4385 06:48:46.279930 6, 0xFFFF, sum = 0
4386 06:48:46.282781 7, 0x0, sum = 1
4387 06:48:46.282884 8, 0x0, sum = 2
4388 06:48:46.282977 9, 0x0, sum = 3
4389 06:48:46.286184 10, 0x0, sum = 4
4390 06:48:46.286296 best_step = 8
4391 06:48:46.286385
4392 06:48:46.286470 ==
4393 06:48:46.289373 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 06:48:46.296253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4395 06:48:46.296353 ==
4396 06:48:46.296452 RX Vref Scan: 1
4397 06:48:46.296544
4398 06:48:46.300009 RX Vref 0 -> 0, step: 1
4399 06:48:46.300104
4400 06:48:46.302476 RX Delay -195 -> 252, step: 8
4401 06:48:46.302570
4402 06:48:46.306207 Set Vref, RX VrefLevel [Byte0]: 57
4403 06:48:46.309555 [Byte1]: 48
4404 06:48:46.309625
4405 06:48:46.312269 Final RX Vref Byte 0 = 57 to rank0
4406 06:48:46.315943 Final RX Vref Byte 1 = 48 to rank0
4407 06:48:46.319180 Final RX Vref Byte 0 = 57 to rank1
4408 06:48:46.322182 Final RX Vref Byte 1 = 48 to rank1==
4409 06:48:46.326148 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 06:48:46.329134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4411 06:48:46.329204 ==
4412 06:48:46.332174 DQS Delay:
4413 06:48:46.332269 DQS0 = 0, DQS1 = 0
4414 06:48:46.336221 DQM Delay:
4415 06:48:46.336316 DQM0 = 37, DQM1 = 31
4416 06:48:46.336406 DQ Delay:
4417 06:48:46.339337 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4418 06:48:46.342286 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4419 06:48:46.345772 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4420 06:48:46.348903 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4421 06:48:46.348999
4422 06:48:46.352254
4423 06:48:46.358856 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e7e, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4424 06:48:46.362183 CH1 RK0: MR19=808, MR18=7E7E
4425 06:48:46.369149 CH1_RK0: MR19=0x808, MR18=0x7E7E, DQSOSC=386, MR23=63, INC=176, DEC=117
4426 06:48:46.369236
4427 06:48:46.372484 ----->DramcWriteLeveling(PI) begin...
4428 06:48:46.372582 ==
4429 06:48:46.375061 Dram Type= 6, Freq= 0, CH_1, rank 1
4430 06:48:46.379444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4431 06:48:46.379544 ==
4432 06:48:46.382205 Write leveling (Byte 0): 27 => 27
4433 06:48:46.384934 Write leveling (Byte 1): 27 => 27
4434 06:48:46.388391 DramcWriteLeveling(PI) end<-----
4435 06:48:46.388489
4436 06:48:46.388576 ==
4437 06:48:46.391916 Dram Type= 6, Freq= 0, CH_1, rank 1
4438 06:48:46.395294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4439 06:48:46.395390 ==
4440 06:48:46.398075 [Gating] SW mode calibration
4441 06:48:46.405078 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4442 06:48:46.411941 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4443 06:48:46.415345 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4444 06:48:46.418095 0 5 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4445 06:48:46.425137 0 5 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
4446 06:48:46.428668 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 06:48:46.432096 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 06:48:46.438304 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 06:48:46.441660 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 06:48:46.444809 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 06:48:46.451776 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 06:48:46.454655 0 6 4 | B1->B0 | 2727 3333 | 0 1 | (0 0) (1 1)
4453 06:48:46.457863 0 6 8 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
4454 06:48:46.464279 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 06:48:46.467833 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 06:48:46.471477 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 06:48:46.477776 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 06:48:46.480903 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 06:48:46.484866 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 06:48:46.491458 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 06:48:46.494381 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4462 06:48:46.497640 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 06:48:46.504024 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 06:48:46.507530 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 06:48:46.511044 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 06:48:46.517401 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 06:48:46.520797 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 06:48:46.524441 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 06:48:46.530549 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 06:48:46.534460 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 06:48:46.537182 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 06:48:46.543570 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 06:48:46.546767 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 06:48:46.550614 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 06:48:46.557266 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 06:48:46.560592 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4477 06:48:46.563692 Total UI for P1: 0, mck2ui 16
4478 06:48:46.567078 best dqsien dly found for B0: ( 0, 9, 2)
4479 06:48:46.570354 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 06:48:46.573228 Total UI for P1: 0, mck2ui 16
4481 06:48:46.576802 best dqsien dly found for B1: ( 0, 9, 4)
4482 06:48:46.580135 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4483 06:48:46.583296 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4484 06:48:46.583400
4485 06:48:46.590195 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4486 06:48:46.593387 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4487 06:48:46.593478 [Gating] SW calibration Done
4488 06:48:46.596596 ==
4489 06:48:46.600147 Dram Type= 6, Freq= 0, CH_1, rank 1
4490 06:48:46.603082 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4491 06:48:46.603183 ==
4492 06:48:46.603282 RX Vref Scan: 0
4493 06:48:46.603374
4494 06:48:46.606920 RX Vref 0 -> 0, step: 1
4495 06:48:46.607020
4496 06:48:46.610047 RX Delay -230 -> 252, step: 16
4497 06:48:46.613073 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4498 06:48:46.616298 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4499 06:48:46.623295 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4500 06:48:46.626569 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4501 06:48:46.629547 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4502 06:48:46.633145 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4503 06:48:46.640286 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4504 06:48:46.643845 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4505 06:48:46.646486 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4506 06:48:46.649453 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4507 06:48:46.653177 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4508 06:48:46.659604 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4509 06:48:46.663014 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4510 06:48:46.666754 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4511 06:48:46.669476 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4512 06:48:46.676123 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4513 06:48:46.676232 ==
4514 06:48:46.679803 Dram Type= 6, Freq= 0, CH_1, rank 1
4515 06:48:46.682534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4516 06:48:46.682639 ==
4517 06:48:46.682732 DQS Delay:
4518 06:48:46.685769 DQS0 = 0, DQS1 = 0
4519 06:48:46.685871 DQM Delay:
4520 06:48:46.689393 DQM0 = 40, DQM1 = 34
4521 06:48:46.689496 DQ Delay:
4522 06:48:46.693396 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4523 06:48:46.695961 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4524 06:48:46.699740 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4525 06:48:46.702355 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4526 06:48:46.702454
4527 06:48:46.702543
4528 06:48:46.702632 ==
4529 06:48:46.706074 Dram Type= 6, Freq= 0, CH_1, rank 1
4530 06:48:46.709224 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4531 06:48:46.712201 ==
4532 06:48:46.712298
4533 06:48:46.712389
4534 06:48:46.712479 TX Vref Scan disable
4535 06:48:46.715713 == TX Byte 0 ==
4536 06:48:46.719065 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4537 06:48:46.725329 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4538 06:48:46.725433 == TX Byte 1 ==
4539 06:48:46.728896 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4540 06:48:46.735981 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4541 06:48:46.736088 ==
4542 06:48:46.739189 Dram Type= 6, Freq= 0, CH_1, rank 1
4543 06:48:46.742032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4544 06:48:46.742129 ==
4545 06:48:46.742227
4546 06:48:46.742317
4547 06:48:46.745183 TX Vref Scan disable
4548 06:48:46.748642 == TX Byte 0 ==
4549 06:48:46.752391 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4550 06:48:46.755322 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4551 06:48:46.759028 == TX Byte 1 ==
4552 06:48:46.762212 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4553 06:48:46.765862 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4554 06:48:46.765962
4555 06:48:46.766063 [DATLAT]
4556 06:48:46.769075 Freq=600, CH1 RK1
4557 06:48:46.769146
4558 06:48:46.769207 DATLAT Default: 0x8
4559 06:48:46.771794 0, 0xFFFF, sum = 0
4560 06:48:46.775367 1, 0xFFFF, sum = 0
4561 06:48:46.775464 2, 0xFFFF, sum = 0
4562 06:48:46.778529 3, 0xFFFF, sum = 0
4563 06:48:46.778625 4, 0xFFFF, sum = 0
4564 06:48:46.781940 5, 0xFFFF, sum = 0
4565 06:48:46.782051 6, 0xFFFF, sum = 0
4566 06:48:46.786032 7, 0x0, sum = 1
4567 06:48:46.786136 8, 0x0, sum = 2
4568 06:48:46.786228 9, 0x0, sum = 3
4569 06:48:46.788359 10, 0x0, sum = 4
4570 06:48:46.788460 best_step = 8
4571 06:48:46.788561
4572 06:48:46.788650 ==
4573 06:48:46.791633 Dram Type= 6, Freq= 0, CH_1, rank 1
4574 06:48:46.798841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4575 06:48:46.798949 ==
4576 06:48:46.799041 RX Vref Scan: 0
4577 06:48:46.799145
4578 06:48:46.801981 RX Vref 0 -> 0, step: 1
4579 06:48:46.802077
4580 06:48:46.805525 RX Delay -195 -> 252, step: 8
4581 06:48:46.808628 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4582 06:48:46.814817 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4583 06:48:46.818197 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4584 06:48:46.821185 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4585 06:48:46.825448 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4586 06:48:46.831610 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4587 06:48:46.834942 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4588 06:48:46.838499 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4589 06:48:46.841862 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4590 06:48:46.848831 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4591 06:48:46.851479 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4592 06:48:46.854842 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4593 06:48:46.857782 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4594 06:48:46.864306 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4595 06:48:46.867847 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4596 06:48:46.871345 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4597 06:48:46.871441 ==
4598 06:48:46.874597 Dram Type= 6, Freq= 0, CH_1, rank 1
4599 06:48:46.877696 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4600 06:48:46.880983 ==
4601 06:48:46.881068 DQS Delay:
4602 06:48:46.881135 DQS0 = 0, DQS1 = 0
4603 06:48:46.883977 DQM Delay:
4604 06:48:46.884087 DQM0 = 36, DQM1 = 29
4605 06:48:46.887383 DQ Delay:
4606 06:48:46.887489 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4607 06:48:46.891451 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4608 06:48:46.893916 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4609 06:48:46.897679 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4610 06:48:46.897776
4611 06:48:46.901357
4612 06:48:46.907389 [DQSOSCAuto] RK1, (LSB)MR18= 0x5252, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4613 06:48:46.910359 CH1 RK1: MR19=808, MR18=5252
4614 06:48:46.917155 CH1_RK1: MR19=0x808, MR18=0x5252, DQSOSC=394, MR23=63, INC=168, DEC=112
4615 06:48:46.920585 [RxdqsGatingPostProcess] freq 600
4616 06:48:46.923976 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4617 06:48:46.926963 Pre-setting of DQS Precalculation
4618 06:48:46.933986 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4619 06:48:46.940126 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4620 06:48:46.946549 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4621 06:48:46.946662
4622 06:48:46.946754
4623 06:48:46.950660 [Calibration Summary] 1200 Mbps
4624 06:48:46.950757 CH 0, Rank 0
4625 06:48:46.954226 SW Impedance : PASS
4626 06:48:46.957989 DUTY Scan : NO K
4627 06:48:46.958099 ZQ Calibration : PASS
4628 06:48:46.960289 Jitter Meter : NO K
4629 06:48:46.963090 CBT Training : PASS
4630 06:48:46.963186 Write leveling : PASS
4631 06:48:46.967016 RX DQS gating : PASS
4632 06:48:46.970608 RX DQ/DQS(RDDQC) : PASS
4633 06:48:46.970704 TX DQ/DQS : PASS
4634 06:48:46.973057 RX DATLAT : PASS
4635 06:48:46.973130 RX DQ/DQS(Engine): PASS
4636 06:48:46.976611 TX OE : NO K
4637 06:48:46.976712 All Pass.
4638 06:48:46.976815
4639 06:48:46.979604 CH 0, Rank 1
4640 06:48:46.979692 SW Impedance : PASS
4641 06:48:46.982949 DUTY Scan : NO K
4642 06:48:46.986840 ZQ Calibration : PASS
4643 06:48:46.986939 Jitter Meter : NO K
4644 06:48:46.989957 CBT Training : PASS
4645 06:48:46.993261 Write leveling : PASS
4646 06:48:46.993360 RX DQS gating : PASS
4647 06:48:46.996196 RX DQ/DQS(RDDQC) : PASS
4648 06:48:46.999658 TX DQ/DQS : PASS
4649 06:48:46.999756 RX DATLAT : PASS
4650 06:48:47.002534 RX DQ/DQS(Engine): PASS
4651 06:48:47.007120 TX OE : NO K
4652 06:48:47.007230 All Pass.
4653 06:48:47.007353
4654 06:48:47.007442 CH 1, Rank 0
4655 06:48:47.010955 SW Impedance : PASS
4656 06:48:47.013025 DUTY Scan : NO K
4657 06:48:47.013099 ZQ Calibration : PASS
4658 06:48:47.016261 Jitter Meter : NO K
4659 06:48:47.020133 CBT Training : PASS
4660 06:48:47.020234 Write leveling : PASS
4661 06:48:47.023107 RX DQS gating : PASS
4662 06:48:47.026207 RX DQ/DQS(RDDQC) : PASS
4663 06:48:47.026277 TX DQ/DQS : PASS
4664 06:48:47.029526 RX DATLAT : PASS
4665 06:48:47.032942 RX DQ/DQS(Engine): PASS
4666 06:48:47.033033 TX OE : NO K
4667 06:48:47.033127 All Pass.
4668 06:48:47.033188
4669 06:48:47.035921 CH 1, Rank 1
4670 06:48:47.039394 SW Impedance : PASS
4671 06:48:47.039499 DUTY Scan : NO K
4672 06:48:47.042534 ZQ Calibration : PASS
4673 06:48:47.042630 Jitter Meter : NO K
4674 06:48:47.046206 CBT Training : PASS
4675 06:48:47.049624 Write leveling : PASS
4676 06:48:47.049702 RX DQS gating : PASS
4677 06:48:47.052643 RX DQ/DQS(RDDQC) : PASS
4678 06:48:47.056017 TX DQ/DQS : PASS
4679 06:48:47.056123 RX DATLAT : PASS
4680 06:48:47.059143 RX DQ/DQS(Engine): PASS
4681 06:48:47.062783 TX OE : NO K
4682 06:48:47.062881 All Pass.
4683 06:48:47.062982
4684 06:48:47.065650 DramC Write-DBI off
4685 06:48:47.065739 PER_BANK_REFRESH: Hybrid Mode
4686 06:48:47.068980 TX_TRACKING: ON
4687 06:48:47.076003 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4688 06:48:47.082338 [FAST_K] Save calibration result to emmc
4689 06:48:47.085484 dramc_set_vcore_voltage set vcore to 662500
4690 06:48:47.085572 Read voltage for 933, 3
4691 06:48:47.089594 Vio18 = 0
4692 06:48:47.089701 Vcore = 662500
4693 06:48:47.089792 Vdram = 0
4694 06:48:47.092322 Vddq = 0
4695 06:48:47.092424 Vmddr = 0
4696 06:48:47.096408 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4697 06:48:47.102636 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4698 06:48:47.105882 MEM_TYPE=3, freq_sel=17
4699 06:48:47.108680 sv_algorithm_assistance_LP4_1600
4700 06:48:47.111862 ============ PULL DRAM RESETB DOWN ============
4701 06:48:47.116074 ========== PULL DRAM RESETB DOWN end =========
4702 06:48:47.121836 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4703 06:48:47.125724 ===================================
4704 06:48:47.125827 LPDDR4 DRAM CONFIGURATION
4705 06:48:47.128344 ===================================
4706 06:48:47.132167 EX_ROW_EN[0] = 0x0
4707 06:48:47.135643 EX_ROW_EN[1] = 0x0
4708 06:48:47.135742 LP4Y_EN = 0x0
4709 06:48:47.138453 WORK_FSP = 0x0
4710 06:48:47.138558 WL = 0x3
4711 06:48:47.141918 RL = 0x3
4712 06:48:47.142021 BL = 0x2
4713 06:48:47.146093 RPST = 0x0
4714 06:48:47.146174 RD_PRE = 0x0
4715 06:48:47.148693 WR_PRE = 0x1
4716 06:48:47.148820 WR_PST = 0x0
4717 06:48:47.151697 DBI_WR = 0x0
4718 06:48:47.151772 DBI_RD = 0x0
4719 06:48:47.155186 OTF = 0x1
4720 06:48:47.158606 ===================================
4721 06:48:47.161617 ===================================
4722 06:48:47.161707 ANA top config
4723 06:48:47.165296 ===================================
4724 06:48:47.168563 DLL_ASYNC_EN = 0
4725 06:48:47.171543 ALL_SLAVE_EN = 1
4726 06:48:47.171622 NEW_RANK_MODE = 1
4727 06:48:47.174731 DLL_IDLE_MODE = 1
4728 06:48:47.178425 LP45_APHY_COMB_EN = 1
4729 06:48:47.181439 TX_ODT_DIS = 1
4730 06:48:47.184689 NEW_8X_MODE = 1
4731 06:48:47.188558 ===================================
4732 06:48:47.191760 ===================================
4733 06:48:47.195180 data_rate = 1866
4734 06:48:47.195344 CKR = 1
4735 06:48:47.199095 DQ_P2S_RATIO = 8
4736 06:48:47.201677 ===================================
4737 06:48:47.205477 CA_P2S_RATIO = 8
4738 06:48:47.208626 DQ_CA_OPEN = 0
4739 06:48:47.211250 DQ_SEMI_OPEN = 0
4740 06:48:47.211467 CA_SEMI_OPEN = 0
4741 06:48:47.215021 CA_FULL_RATE = 0
4742 06:48:47.218892 DQ_CKDIV4_EN = 1
4743 06:48:47.221416 CA_CKDIV4_EN = 1
4744 06:48:47.225182 CA_PREDIV_EN = 0
4745 06:48:47.228002 PH8_DLY = 0
4746 06:48:47.228367 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4747 06:48:47.231287 DQ_AAMCK_DIV = 4
4748 06:48:47.235079 CA_AAMCK_DIV = 4
4749 06:48:47.238692 CA_ADMCK_DIV = 4
4750 06:48:47.241105 DQ_TRACK_CA_EN = 0
4751 06:48:47.245276 CA_PICK = 933
4752 06:48:47.248210 CA_MCKIO = 933
4753 06:48:47.248824 MCKIO_SEMI = 0
4754 06:48:47.252031 PLL_FREQ = 3732
4755 06:48:47.254955 DQ_UI_PI_RATIO = 32
4756 06:48:47.258550 CA_UI_PI_RATIO = 0
4757 06:48:47.261706 ===================================
4758 06:48:47.264806 ===================================
4759 06:48:47.268240 memory_type:LPDDR4
4760 06:48:47.268690 GP_NUM : 10
4761 06:48:47.271205 SRAM_EN : 1
4762 06:48:47.274396 MD32_EN : 0
4763 06:48:47.277645 ===================================
4764 06:48:47.278107 [ANA_INIT] >>>>>>>>>>>>>>
4765 06:48:47.281378 <<<<<< [CONFIGURE PHASE]: ANA_TX
4766 06:48:47.284838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4767 06:48:47.289616 ===================================
4768 06:48:47.291425 data_rate = 1866,PCW = 0X8f00
4769 06:48:47.294322 ===================================
4770 06:48:47.297505 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4771 06:48:47.304107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4772 06:48:47.307101 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4773 06:48:47.314179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4774 06:48:47.317939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4775 06:48:47.320593 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4776 06:48:47.320664 [ANA_INIT] flow start
4777 06:48:47.324402 [ANA_INIT] PLL >>>>>>>>
4778 06:48:47.327464 [ANA_INIT] PLL <<<<<<<<
4779 06:48:47.330410 [ANA_INIT] MIDPI >>>>>>>>
4780 06:48:47.330478 [ANA_INIT] MIDPI <<<<<<<<
4781 06:48:47.333976 [ANA_INIT] DLL >>>>>>>>
4782 06:48:47.337113 [ANA_INIT] flow end
4783 06:48:47.340292 ============ LP4 DIFF to SE enter ============
4784 06:48:47.344002 ============ LP4 DIFF to SE exit ============
4785 06:48:47.347031 [ANA_INIT] <<<<<<<<<<<<<
4786 06:48:47.351486 [Flow] Enable top DCM control >>>>>
4787 06:48:47.354322 [Flow] Enable top DCM control <<<<<
4788 06:48:47.356940 Enable DLL master slave shuffle
4789 06:48:47.360342 ==============================================================
4790 06:48:47.363677 Gating Mode config
4791 06:48:47.367240 ==============================================================
4792 06:48:47.370203 Config description:
4793 06:48:47.380464 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4794 06:48:47.387303 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4795 06:48:47.390223 SELPH_MODE 0: By rank 1: By Phase
4796 06:48:47.397078 ==============================================================
4797 06:48:47.400225 GAT_TRACK_EN = 1
4798 06:48:47.403342 RX_GATING_MODE = 2
4799 06:48:47.406622 RX_GATING_TRACK_MODE = 2
4800 06:48:47.410910 SELPH_MODE = 1
4801 06:48:47.413511 PICG_EARLY_EN = 1
4802 06:48:47.416421 VALID_LAT_VALUE = 1
4803 06:48:47.420268 ==============================================================
4804 06:48:47.423412 Enter into Gating configuration >>>>
4805 06:48:47.426641 Exit from Gating configuration <<<<
4806 06:48:47.430032 Enter into DVFS_PRE_config >>>>>
4807 06:48:47.440152 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4808 06:48:47.444484 Exit from DVFS_PRE_config <<<<<
4809 06:48:47.446416 Enter into PICG configuration >>>>
4810 06:48:47.449772 Exit from PICG configuration <<<<
4811 06:48:47.453188 [RX_INPUT] configuration >>>>>
4812 06:48:47.457062 [RX_INPUT] configuration <<<<<
4813 06:48:47.463049 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4814 06:48:47.466054 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4815 06:48:47.473103 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4816 06:48:47.479252 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4817 06:48:47.485913 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4818 06:48:47.493074 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4819 06:48:47.496211 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4820 06:48:47.499304 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4821 06:48:47.502957 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4822 06:48:47.509523 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4823 06:48:47.513781 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4824 06:48:47.516074 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4825 06:48:47.519821 ===================================
4826 06:48:47.522572 LPDDR4 DRAM CONFIGURATION
4827 06:48:47.525855 ===================================
4828 06:48:47.525936 EX_ROW_EN[0] = 0x0
4829 06:48:47.529328 EX_ROW_EN[1] = 0x0
4830 06:48:47.533100 LP4Y_EN = 0x0
4831 06:48:47.533181 WORK_FSP = 0x0
4832 06:48:47.536442 WL = 0x3
4833 06:48:47.536523 RL = 0x3
4834 06:48:47.540215 BL = 0x2
4835 06:48:47.540295 RPST = 0x0
4836 06:48:47.542376 RD_PRE = 0x0
4837 06:48:47.542457 WR_PRE = 0x1
4838 06:48:47.545882 WR_PST = 0x0
4839 06:48:47.545964 DBI_WR = 0x0
4840 06:48:47.549218 DBI_RD = 0x0
4841 06:48:47.549298 OTF = 0x1
4842 06:48:47.552602 ===================================
4843 06:48:47.555720 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4844 06:48:47.562815 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4845 06:48:47.566371 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4846 06:48:47.568744 ===================================
4847 06:48:47.572814 LPDDR4 DRAM CONFIGURATION
4848 06:48:47.575623 ===================================
4849 06:48:47.575704 EX_ROW_EN[0] = 0x10
4850 06:48:47.578831 EX_ROW_EN[1] = 0x0
4851 06:48:47.583008 LP4Y_EN = 0x0
4852 06:48:47.583088 WORK_FSP = 0x0
4853 06:48:47.585602 WL = 0x3
4854 06:48:47.585684 RL = 0x3
4855 06:48:47.589108 BL = 0x2
4856 06:48:47.589190 RPST = 0x0
4857 06:48:47.593002 RD_PRE = 0x0
4858 06:48:47.593083 WR_PRE = 0x1
4859 06:48:47.595367 WR_PST = 0x0
4860 06:48:47.595448 DBI_WR = 0x0
4861 06:48:47.598742 DBI_RD = 0x0
4862 06:48:47.598822 OTF = 0x1
4863 06:48:47.602529 ===================================
4864 06:48:47.608598 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4865 06:48:47.612641 nWR fixed to 30
4866 06:48:47.616313 [ModeRegInit_LP4] CH0 RK0
4867 06:48:47.616394 [ModeRegInit_LP4] CH0 RK1
4868 06:48:47.619967 [ModeRegInit_LP4] CH1 RK0
4869 06:48:47.623966 [ModeRegInit_LP4] CH1 RK1
4870 06:48:47.624047 match AC timing 8
4871 06:48:47.629592 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4872 06:48:47.632815 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4873 06:48:47.636227 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4874 06:48:47.642767 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4875 06:48:47.647217 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4876 06:48:47.647300 ==
4877 06:48:47.650069 Dram Type= 6, Freq= 0, CH_0, rank 0
4878 06:48:47.652561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4879 06:48:47.652642 ==
4880 06:48:47.660183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4881 06:48:47.666716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4882 06:48:47.669484 [CA 0] Center 38 (8~69) winsize 62
4883 06:48:47.672598 [CA 1] Center 38 (8~69) winsize 62
4884 06:48:47.675745 [CA 2] Center 36 (6~67) winsize 62
4885 06:48:47.680136 [CA 3] Center 35 (5~66) winsize 62
4886 06:48:47.682925 [CA 4] Center 34 (4~65) winsize 62
4887 06:48:47.685775 [CA 5] Center 34 (4~64) winsize 61
4888 06:48:47.685857
4889 06:48:47.689835 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4890 06:48:47.689916
4891 06:48:47.692908 [CATrainingPosCal] consider 1 rank data
4892 06:48:47.696728 u2DelayCellTimex100 = 270/100 ps
4893 06:48:47.699895 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4894 06:48:47.702955 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4895 06:48:47.705784 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4896 06:48:47.708853 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4897 06:48:47.712880 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4898 06:48:47.715745 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4899 06:48:47.718744
4900 06:48:47.722133 CA PerBit enable=1, Macro0, CA PI delay=34
4901 06:48:47.722214
4902 06:48:47.725987 [CBTSetCACLKResult] CA Dly = 34
4903 06:48:47.726069 CS Dly: 7 (0~38)
4904 06:48:47.726134 ==
4905 06:48:47.729294 Dram Type= 6, Freq= 0, CH_0, rank 1
4906 06:48:47.733458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4907 06:48:47.733540 ==
4908 06:48:47.738966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4909 06:48:47.745523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4910 06:48:47.748609 [CA 0] Center 38 (8~69) winsize 62
4911 06:48:47.752348 [CA 1] Center 38 (7~69) winsize 63
4912 06:48:47.755884 [CA 2] Center 36 (6~67) winsize 62
4913 06:48:47.759138 [CA 3] Center 35 (5~66) winsize 62
4914 06:48:47.762193 [CA 4] Center 34 (4~65) winsize 62
4915 06:48:47.765388 [CA 5] Center 34 (4~65) winsize 62
4916 06:48:47.765469
4917 06:48:47.768937 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4918 06:48:47.769018
4919 06:48:47.771889 [CATrainingPosCal] consider 2 rank data
4920 06:48:47.775768 u2DelayCellTimex100 = 270/100 ps
4921 06:48:47.779070 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4922 06:48:47.782413 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4923 06:48:47.785745 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4924 06:48:47.788591 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4925 06:48:47.792736 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4926 06:48:47.798969 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4927 06:48:47.799050
4928 06:48:47.803481 CA PerBit enable=1, Macro0, CA PI delay=34
4929 06:48:47.803587
4930 06:48:47.805701 [CBTSetCACLKResult] CA Dly = 34
4931 06:48:47.805790 CS Dly: 7 (0~39)
4932 06:48:47.805854
4933 06:48:47.809016 ----->DramcWriteLeveling(PI) begin...
4934 06:48:47.809123 ==
4935 06:48:47.812468 Dram Type= 6, Freq= 0, CH_0, rank 0
4936 06:48:47.818764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4937 06:48:47.818839 ==
4938 06:48:47.822077 Write leveling (Byte 0): 29 => 29
4939 06:48:47.822158 Write leveling (Byte 1): 27 => 27
4940 06:48:47.825249 DramcWriteLeveling(PI) end<-----
4941 06:48:47.825329
4942 06:48:47.828391 ==
4943 06:48:47.828471 Dram Type= 6, Freq= 0, CH_0, rank 0
4944 06:48:47.835385 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4945 06:48:47.835466 ==
4946 06:48:47.838888 [Gating] SW mode calibration
4947 06:48:47.845471 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4948 06:48:47.848858 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4949 06:48:47.855239 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4950 06:48:47.858646 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4951 06:48:47.862186 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4952 06:48:47.868223 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4953 06:48:47.871621 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4954 06:48:47.875503 0 10 20 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 1)
4955 06:48:47.881569 0 10 24 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
4956 06:48:47.885018 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4957 06:48:47.888102 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4958 06:48:47.895246 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4959 06:48:47.898714 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4960 06:48:47.901673 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4961 06:48:47.908242 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4962 06:48:47.912268 0 11 20 | B1->B0 | 2b2b 3333 | 0 1 | (0 0) (0 0)
4963 06:48:47.914651 0 11 24 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
4964 06:48:47.921422 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4965 06:48:47.924886 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4966 06:48:47.928452 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4967 06:48:47.934216 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4968 06:48:47.937574 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4969 06:48:47.941233 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4970 06:48:47.947547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4971 06:48:47.950937 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4972 06:48:47.955396 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4973 06:48:47.961248 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4974 06:48:47.964692 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4975 06:48:47.967768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4976 06:48:47.973969 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4977 06:48:47.977197 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4978 06:48:47.981270 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4979 06:48:47.987165 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4980 06:48:47.991183 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4981 06:48:47.993878 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4982 06:48:47.997657 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4983 06:48:48.004358 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4984 06:48:48.007867 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4985 06:48:48.010575 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4986 06:48:48.016966 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4987 06:48:48.020246 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4988 06:48:48.023873 Total UI for P1: 0, mck2ui 16
4989 06:48:48.026781 best dqsien dly found for B0: ( 0, 14, 20)
4990 06:48:48.030748 Total UI for P1: 0, mck2ui 16
4991 06:48:48.033622 best dqsien dly found for B1: ( 0, 14, 22)
4992 06:48:48.036846 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4993 06:48:48.040389 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4994 06:48:48.040469
4995 06:48:48.043254 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4996 06:48:48.050496 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4997 06:48:48.050581 [Gating] SW calibration Done
4998 06:48:48.050650 ==
4999 06:48:48.053939 Dram Type= 6, Freq= 0, CH_0, rank 0
5000 06:48:48.061061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5001 06:48:48.061171 ==
5002 06:48:48.061267 RX Vref Scan: 0
5003 06:48:48.061370
5004 06:48:48.064180 RX Vref 0 -> 0, step: 1
5005 06:48:48.064256
5006 06:48:48.066442 RX Delay -80 -> 252, step: 8
5007 06:48:48.070278 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5008 06:48:48.073505 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5009 06:48:48.076917 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5010 06:48:48.080051 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5011 06:48:48.087423 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5012 06:48:48.090714 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5013 06:48:48.093248 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5014 06:48:48.096473 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5015 06:48:48.099732 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5016 06:48:48.103067 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5017 06:48:48.109856 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5018 06:48:48.113405 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5019 06:48:48.116657 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5020 06:48:48.119802 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5021 06:48:48.122891 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5022 06:48:48.130033 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5023 06:48:48.130112 ==
5024 06:48:48.133182 Dram Type= 6, Freq= 0, CH_0, rank 0
5025 06:48:48.136145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5026 06:48:48.136218 ==
5027 06:48:48.136280 DQS Delay:
5028 06:48:48.140641 DQS0 = 0, DQS1 = 0
5029 06:48:48.140726 DQM Delay:
5030 06:48:48.142802 DQM0 = 97, DQM1 = 85
5031 06:48:48.142875 DQ Delay:
5032 06:48:48.146615 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5033 06:48:48.149764 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =107
5034 06:48:48.152811 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5035 06:48:48.156196 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5036 06:48:48.156268
5037 06:48:48.156335
5038 06:48:48.156395 ==
5039 06:48:48.159588 Dram Type= 6, Freq= 0, CH_0, rank 0
5040 06:48:48.162905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5041 06:48:48.166407 ==
5042 06:48:48.166479
5043 06:48:48.166541
5044 06:48:48.166606 TX Vref Scan disable
5045 06:48:48.169195 == TX Byte 0 ==
5046 06:48:48.172931 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5047 06:48:48.175983 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5048 06:48:48.179722 == TX Byte 1 ==
5049 06:48:48.183301 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5050 06:48:48.189174 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5051 06:48:48.189249 ==
5052 06:48:48.192903 Dram Type= 6, Freq= 0, CH_0, rank 0
5053 06:48:48.196118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5054 06:48:48.196190 ==
5055 06:48:48.196252
5056 06:48:48.196310
5057 06:48:48.198931 TX Vref Scan disable
5058 06:48:48.199007 == TX Byte 0 ==
5059 06:48:48.205982 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5060 06:48:48.209281 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5061 06:48:48.209361 == TX Byte 1 ==
5062 06:48:48.215443 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5063 06:48:48.218917 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5064 06:48:48.218995
5065 06:48:48.219058 [DATLAT]
5066 06:48:48.221974 Freq=933, CH0 RK0
5067 06:48:48.222046
5068 06:48:48.222106 DATLAT Default: 0xd
5069 06:48:48.225604 0, 0xFFFF, sum = 0
5070 06:48:48.225682 1, 0xFFFF, sum = 0
5071 06:48:48.229165 2, 0xFFFF, sum = 0
5072 06:48:48.229241 3, 0xFFFF, sum = 0
5073 06:48:48.232495 4, 0xFFFF, sum = 0
5074 06:48:48.235590 5, 0xFFFF, sum = 0
5075 06:48:48.235665 6, 0xFFFF, sum = 0
5076 06:48:48.238975 7, 0xFFFF, sum = 0
5077 06:48:48.239048 8, 0xFFFF, sum = 0
5078 06:48:48.241961 9, 0xFFFF, sum = 0
5079 06:48:48.242035 10, 0x0, sum = 1
5080 06:48:48.245305 11, 0x0, sum = 2
5081 06:48:48.245410 12, 0x0, sum = 3
5082 06:48:48.245494 13, 0x0, sum = 4
5083 06:48:48.248500 best_step = 11
5084 06:48:48.248578
5085 06:48:48.248678 ==
5086 06:48:48.252138 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 06:48:48.255565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5088 06:48:48.255648 ==
5089 06:48:48.258593 RX Vref Scan: 1
5090 06:48:48.258676
5091 06:48:48.262383 RX Vref 0 -> 0, step: 1
5092 06:48:48.262467
5093 06:48:48.262551 RX Delay -77 -> 252, step: 4
5094 06:48:48.262632
5095 06:48:48.265332 Set Vref, RX VrefLevel [Byte0]: 52
5096 06:48:48.268689 [Byte1]: 48
5097 06:48:48.273170
5098 06:48:48.273256 Final RX Vref Byte 0 = 52 to rank0
5099 06:48:48.276666 Final RX Vref Byte 1 = 48 to rank0
5100 06:48:48.279522 Final RX Vref Byte 0 = 52 to rank1
5101 06:48:48.282946 Final RX Vref Byte 1 = 48 to rank1==
5102 06:48:48.286410 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 06:48:48.292985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5104 06:48:48.293069 ==
5105 06:48:48.293161 DQS Delay:
5106 06:48:48.293242 DQS0 = 0, DQS1 = 0
5107 06:48:48.296626 DQM Delay:
5108 06:48:48.296740 DQM0 = 96, DQM1 = 86
5109 06:48:48.299639 DQ Delay:
5110 06:48:48.303652 DQ0 =92, DQ1 =96, DQ2 =96, DQ3 =92
5111 06:48:48.306433 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5112 06:48:48.309801 DQ8 =78, DQ9 =70, DQ10 =88, DQ11 =78
5113 06:48:48.313205 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =96
5114 06:48:48.313288
5115 06:48:48.313373
5116 06:48:48.319940 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5117 06:48:48.323645 CH0 RK0: MR19=505, MR18=2525
5118 06:48:48.329658 CH0_RK0: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5119 06:48:48.329742
5120 06:48:48.332861 ----->DramcWriteLeveling(PI) begin...
5121 06:48:48.332945 ==
5122 06:48:48.336162 Dram Type= 6, Freq= 0, CH_0, rank 1
5123 06:48:48.340973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5124 06:48:48.341057 ==
5125 06:48:48.343029 Write leveling (Byte 0): 28 => 28
5126 06:48:48.345977 Write leveling (Byte 1): 25 => 25
5127 06:48:48.349433 DramcWriteLeveling(PI) end<-----
5128 06:48:48.349517
5129 06:48:48.349601 ==
5130 06:48:48.352391 Dram Type= 6, Freq= 0, CH_0, rank 1
5131 06:48:48.356228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5132 06:48:48.359091 ==
5133 06:48:48.359175 [Gating] SW mode calibration
5134 06:48:48.365869 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5135 06:48:48.372445 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5136 06:48:48.375614 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 06:48:48.382485 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 06:48:48.385875 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 06:48:48.389410 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 06:48:48.395673 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5141 06:48:48.399048 0 10 20 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
5142 06:48:48.402542 0 10 24 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
5143 06:48:48.408758 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 06:48:48.411973 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 06:48:48.415307 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 06:48:48.422127 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 06:48:48.425163 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 06:48:48.429061 0 11 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5149 06:48:48.435021 0 11 20 | B1->B0 | 2c2c 3737 | 0 1 | (1 1) (1 1)
5150 06:48:48.438905 0 11 24 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5151 06:48:48.441631 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 06:48:48.448813 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 06:48:48.451713 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 06:48:48.455394 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 06:48:48.461621 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 06:48:48.466040 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5157 06:48:48.468173 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5158 06:48:48.474668 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5159 06:48:48.478407 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 06:48:48.481401 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 06:48:48.488463 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 06:48:48.491557 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 06:48:48.494791 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 06:48:48.501421 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 06:48:48.504674 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 06:48:48.508179 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 06:48:48.514816 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 06:48:48.518458 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 06:48:48.521800 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 06:48:48.528902 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 06:48:48.531338 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 06:48:48.534633 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 06:48:48.538381 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5174 06:48:48.544831 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5175 06:48:48.548413 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 06:48:48.551480 Total UI for P1: 0, mck2ui 16
5177 06:48:48.554876 best dqsien dly found for B0: ( 0, 14, 22)
5178 06:48:48.557925 Total UI for P1: 0, mck2ui 16
5179 06:48:48.561372 best dqsien dly found for B1: ( 0, 14, 24)
5180 06:48:48.564885 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5181 06:48:48.567812 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
5182 06:48:48.567894
5183 06:48:48.571945 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5184 06:48:48.577425 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
5185 06:48:48.577508 [Gating] SW calibration Done
5186 06:48:48.577592 ==
5187 06:48:48.580814 Dram Type= 6, Freq= 0, CH_0, rank 1
5188 06:48:48.587564 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5189 06:48:48.587671 ==
5190 06:48:48.587756 RX Vref Scan: 0
5191 06:48:48.587837
5192 06:48:48.590806 RX Vref 0 -> 0, step: 1
5193 06:48:48.590889
5194 06:48:48.594008 RX Delay -80 -> 252, step: 8
5195 06:48:48.597407 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5196 06:48:48.600995 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5197 06:48:48.603816 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5198 06:48:48.610582 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5199 06:48:48.613971 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5200 06:48:48.617084 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5201 06:48:48.620460 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5202 06:48:48.624090 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5203 06:48:48.628083 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5204 06:48:48.634620 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5205 06:48:48.637280 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5206 06:48:48.641159 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5207 06:48:48.643795 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5208 06:48:48.647540 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5209 06:48:48.653781 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5210 06:48:48.657582 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5211 06:48:48.657662 ==
5212 06:48:48.660979 Dram Type= 6, Freq= 0, CH_0, rank 1
5213 06:48:48.663845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5214 06:48:48.663926 ==
5215 06:48:48.663990 DQS Delay:
5216 06:48:48.668133 DQS0 = 0, DQS1 = 0
5217 06:48:48.668238 DQM Delay:
5218 06:48:48.670160 DQM0 = 95, DQM1 = 85
5219 06:48:48.670241 DQ Delay:
5220 06:48:48.673836 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =87
5221 06:48:48.677080 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5222 06:48:48.680677 DQ8 =71, DQ9 =71, DQ10 =87, DQ11 =79
5223 06:48:48.684026 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5224 06:48:48.684107
5225 06:48:48.684171
5226 06:48:48.684230 ==
5227 06:48:48.687235 Dram Type= 6, Freq= 0, CH_0, rank 1
5228 06:48:48.693726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5229 06:48:48.693807 ==
5230 06:48:48.693871
5231 06:48:48.693931
5232 06:48:48.693987 TX Vref Scan disable
5233 06:48:48.697084 == TX Byte 0 ==
5234 06:48:48.700091 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5235 06:48:48.703159 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5236 06:48:48.707151 == TX Byte 1 ==
5237 06:48:48.709906 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5238 06:48:48.716633 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5239 06:48:48.716744 ==
5240 06:48:48.720262 Dram Type= 6, Freq= 0, CH_0, rank 1
5241 06:48:48.723054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5242 06:48:48.723135 ==
5243 06:48:48.723199
5244 06:48:48.723258
5245 06:48:48.726356 TX Vref Scan disable
5246 06:48:48.726436 == TX Byte 0 ==
5247 06:48:48.733009 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5248 06:48:48.736275 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5249 06:48:48.736349 == TX Byte 1 ==
5250 06:48:48.742961 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5251 06:48:48.746687 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5252 06:48:48.746764
5253 06:48:48.746835 [DATLAT]
5254 06:48:48.750400 Freq=933, CH0 RK1
5255 06:48:48.750476
5256 06:48:48.750545 DATLAT Default: 0xb
5257 06:48:48.752690 0, 0xFFFF, sum = 0
5258 06:48:48.752814 1, 0xFFFF, sum = 0
5259 06:48:48.756278 2, 0xFFFF, sum = 0
5260 06:48:48.756359 3, 0xFFFF, sum = 0
5261 06:48:48.759707 4, 0xFFFF, sum = 0
5262 06:48:48.762919 5, 0xFFFF, sum = 0
5263 06:48:48.763028 6, 0xFFFF, sum = 0
5264 06:48:48.766360 7, 0xFFFF, sum = 0
5265 06:48:48.766430 8, 0xFFFF, sum = 0
5266 06:48:48.769797 9, 0xFFFF, sum = 0
5267 06:48:48.769873 10, 0x0, sum = 1
5268 06:48:48.772834 11, 0x0, sum = 2
5269 06:48:48.772907 12, 0x0, sum = 3
5270 06:48:48.772968 13, 0x0, sum = 4
5271 06:48:48.777064 best_step = 11
5272 06:48:48.777140
5273 06:48:48.777201 ==
5274 06:48:48.779918 Dram Type= 6, Freq= 0, CH_0, rank 1
5275 06:48:48.783178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5276 06:48:48.783277 ==
5277 06:48:48.786362 RX Vref Scan: 0
5278 06:48:48.786445
5279 06:48:48.789779 RX Vref 0 -> 0, step: 1
5280 06:48:48.789850
5281 06:48:48.789916 RX Delay -69 -> 252, step: 4
5282 06:48:48.797516 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5283 06:48:48.800607 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5284 06:48:48.804389 iDelay=203, Bit 2, Center 94 (-1 ~ 190) 192
5285 06:48:48.807033 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184
5286 06:48:48.810313 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5287 06:48:48.817243 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5288 06:48:48.820273 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5289 06:48:48.823757 iDelay=203, Bit 7, Center 106 (11 ~ 202) 192
5290 06:48:48.827522 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5291 06:48:48.830221 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5292 06:48:48.836944 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5293 06:48:48.840435 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5294 06:48:48.843293 iDelay=203, Bit 12, Center 92 (3 ~ 182) 180
5295 06:48:48.846757 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5296 06:48:48.850055 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5297 06:48:48.853126 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5298 06:48:48.857444 ==
5299 06:48:48.857532 Dram Type= 6, Freq= 0, CH_0, rank 1
5300 06:48:48.863095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5301 06:48:48.863176 ==
5302 06:48:48.863240 DQS Delay:
5303 06:48:48.866611 DQS0 = 0, DQS1 = 0
5304 06:48:48.866692 DQM Delay:
5305 06:48:48.870035 DQM0 = 97, DQM1 = 86
5306 06:48:48.870116 DQ Delay:
5307 06:48:48.873181 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =90
5308 06:48:48.876455 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =106
5309 06:48:48.880215 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5310 06:48:48.883623 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =96
5311 06:48:48.883706
5312 06:48:48.883769
5313 06:48:48.890441 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5314 06:48:48.893186 CH0 RK1: MR19=505, MR18=2F2F
5315 06:48:48.900421 CH0_RK1: MR19=0x505, MR18=0x2F2F, DQSOSC=407, MR23=63, INC=65, DEC=43
5316 06:48:48.903383 [RxdqsGatingPostProcess] freq 933
5317 06:48:48.909712 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5318 06:48:48.909805 Pre-setting of DQS Precalculation
5319 06:48:48.917153 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5320 06:48:48.917234 ==
5321 06:48:48.919679 Dram Type= 6, Freq= 0, CH_1, rank 0
5322 06:48:48.924104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5323 06:48:48.924185 ==
5324 06:48:48.929486 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5325 06:48:48.936042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5326 06:48:48.939744 [CA 0] Center 37 (6~68) winsize 63
5327 06:48:48.943343 [CA 1] Center 37 (6~68) winsize 63
5328 06:48:48.946582 [CA 2] Center 35 (5~65) winsize 61
5329 06:48:48.950038 [CA 3] Center 34 (3~65) winsize 63
5330 06:48:48.952664 [CA 4] Center 32 (2~63) winsize 62
5331 06:48:48.956549 [CA 5] Center 33 (2~64) winsize 63
5332 06:48:48.956654
5333 06:48:48.959737 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5334 06:48:48.959818
5335 06:48:48.963267 [CATrainingPosCal] consider 1 rank data
5336 06:48:48.966173 u2DelayCellTimex100 = 270/100 ps
5337 06:48:48.969924 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5338 06:48:48.972568 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5339 06:48:48.976265 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5340 06:48:48.980194 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5341 06:48:48.983424 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5342 06:48:48.989727 CA5 delay=33 (2~64),Diff = 1 PI (6 cell)
5343 06:48:48.989808
5344 06:48:48.992483 CA PerBit enable=1, Macro0, CA PI delay=32
5345 06:48:48.992582
5346 06:48:48.995915 [CBTSetCACLKResult] CA Dly = 32
5347 06:48:48.995995 CS Dly: 5 (0~36)
5348 06:48:48.996059 ==
5349 06:48:48.999071 Dram Type= 6, Freq= 0, CH_1, rank 1
5350 06:48:49.002770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5351 06:48:49.006280 ==
5352 06:48:49.009138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5353 06:48:49.015593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5354 06:48:49.019296 [CA 0] Center 37 (6~68) winsize 63
5355 06:48:49.022464 [CA 1] Center 37 (6~68) winsize 63
5356 06:48:49.025835 [CA 2] Center 34 (4~65) winsize 62
5357 06:48:49.029243 [CA 3] Center 34 (4~65) winsize 62
5358 06:48:49.033104 [CA 4] Center 33 (2~64) winsize 63
5359 06:48:49.035737 [CA 5] Center 33 (2~64) winsize 63
5360 06:48:49.035816
5361 06:48:49.038850 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5362 06:48:49.038929
5363 06:48:49.042679 [CATrainingPosCal] consider 2 rank data
5364 06:48:49.045548 u2DelayCellTimex100 = 270/100 ps
5365 06:48:49.049471 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5366 06:48:49.052144 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5367 06:48:49.055797 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5368 06:48:49.062207 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5369 06:48:49.065806 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5370 06:48:49.068799 CA5 delay=33 (2~64),Diff = 1 PI (6 cell)
5371 06:48:49.068904
5372 06:48:49.072474 CA PerBit enable=1, Macro0, CA PI delay=32
5373 06:48:49.072579
5374 06:48:49.075471 [CBTSetCACLKResult] CA Dly = 32
5375 06:48:49.075576 CS Dly: 5 (0~37)
5376 06:48:49.075667
5377 06:48:49.078498 ----->DramcWriteLeveling(PI) begin...
5378 06:48:49.078579 ==
5379 06:48:49.082237 Dram Type= 6, Freq= 0, CH_1, rank 0
5380 06:48:49.088533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5381 06:48:49.088639 ==
5382 06:48:49.092663 Write leveling (Byte 0): 27 => 27
5383 06:48:49.095569 Write leveling (Byte 1): 23 => 23
5384 06:48:49.095650 DramcWriteLeveling(PI) end<-----
5385 06:48:49.098576
5386 06:48:49.098655 ==
5387 06:48:49.102093 Dram Type= 6, Freq= 0, CH_1, rank 0
5388 06:48:49.105545 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5389 06:48:49.105625 ==
5390 06:48:49.108558 [Gating] SW mode calibration
5391 06:48:49.114944 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5392 06:48:49.118297 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5393 06:48:49.125180 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5394 06:48:49.128443 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5395 06:48:49.134209 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5396 06:48:49.138761 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5397 06:48:49.141827 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5398 06:48:49.145170 0 10 20 | B1->B0 | 3333 2525 | 0 0 | (0 1) (1 0)
5399 06:48:49.151760 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
5400 06:48:49.154974 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 06:48:49.158108 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 06:48:49.165935 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 06:48:49.168471 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 06:48:49.171955 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5405 06:48:49.178086 0 11 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
5406 06:48:49.181804 0 11 20 | B1->B0 | 2525 4040 | 0 0 | (0 0) (0 0)
5407 06:48:49.184921 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5408 06:48:49.191525 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 06:48:49.194929 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 06:48:49.197860 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 06:48:49.204653 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 06:48:49.207589 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 06:48:49.211238 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 06:48:49.217609 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 06:48:49.221502 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 06:48:49.224872 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 06:48:49.230993 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 06:48:49.234247 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 06:48:49.238885 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 06:48:49.244148 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 06:48:49.247402 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 06:48:49.250894 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 06:48:49.257765 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 06:48:49.261056 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 06:48:49.264050 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 06:48:49.270774 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 06:48:49.273890 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 06:48:49.277889 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 06:48:49.284277 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5430 06:48:49.287687 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5431 06:48:49.291163 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 06:48:49.294654 Total UI for P1: 0, mck2ui 16
5433 06:48:49.298005 best dqsien dly found for B0: ( 0, 14, 18)
5434 06:48:49.301785 Total UI for P1: 0, mck2ui 16
5435 06:48:49.304232 best dqsien dly found for B1: ( 0, 14, 22)
5436 06:48:49.307438 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5437 06:48:49.310591 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5438 06:48:49.310672
5439 06:48:49.313798 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5440 06:48:49.320553 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5441 06:48:49.320659 [Gating] SW calibration Done
5442 06:48:49.320748 ==
5443 06:48:49.324229 Dram Type= 6, Freq= 0, CH_1, rank 0
5444 06:48:49.330076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5445 06:48:49.330156 ==
5446 06:48:49.330221 RX Vref Scan: 0
5447 06:48:49.330295
5448 06:48:49.333831 RX Vref 0 -> 0, step: 1
5449 06:48:49.333912
5450 06:48:49.338503 RX Delay -80 -> 252, step: 8
5451 06:48:49.340597 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5452 06:48:49.343397 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5453 06:48:49.346702 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5454 06:48:49.353464 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5455 06:48:49.356955 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5456 06:48:49.360156 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5457 06:48:49.363865 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5458 06:48:49.367111 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5459 06:48:49.370500 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5460 06:48:49.376589 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5461 06:48:49.380015 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5462 06:48:49.383668 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5463 06:48:49.386807 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5464 06:48:49.389793 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5465 06:48:49.396598 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5466 06:48:49.400677 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5467 06:48:49.400770 ==
5468 06:48:49.403759 Dram Type= 6, Freq= 0, CH_1, rank 0
5469 06:48:49.406764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5470 06:48:49.406836 ==
5471 06:48:49.406897 DQS Delay:
5472 06:48:49.409954 DQS0 = 0, DQS1 = 0
5473 06:48:49.410022 DQM Delay:
5474 06:48:49.413340 DQM0 = 95, DQM1 = 88
5475 06:48:49.413420 DQ Delay:
5476 06:48:49.416617 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5477 06:48:49.420264 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =95
5478 06:48:49.423185 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5479 06:48:49.426537 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5480 06:48:49.426618
5481 06:48:49.426682
5482 06:48:49.426740 ==
5483 06:48:49.430742 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 06:48:49.436469 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5485 06:48:49.436550 ==
5486 06:48:49.436633
5487 06:48:49.436694
5488 06:48:49.436775 TX Vref Scan disable
5489 06:48:49.439514 == TX Byte 0 ==
5490 06:48:49.443218 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5491 06:48:49.446480 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5492 06:48:49.450502 == TX Byte 1 ==
5493 06:48:49.453002 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5494 06:48:49.459913 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5495 06:48:49.460019 ==
5496 06:48:49.462832 Dram Type= 6, Freq= 0, CH_1, rank 0
5497 06:48:49.466039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5498 06:48:49.466147 ==
5499 06:48:49.466244
5500 06:48:49.466331
5501 06:48:49.469672 TX Vref Scan disable
5502 06:48:49.469752 == TX Byte 0 ==
5503 06:48:49.476371 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5504 06:48:49.480496 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5505 06:48:49.480603 == TX Byte 1 ==
5506 06:48:49.486087 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5507 06:48:49.489197 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5508 06:48:49.489278
5509 06:48:49.489343 [DATLAT]
5510 06:48:49.492314 Freq=933, CH1 RK0
5511 06:48:49.492394
5512 06:48:49.492457 DATLAT Default: 0xd
5513 06:48:49.496176 0, 0xFFFF, sum = 0
5514 06:48:49.496258 1, 0xFFFF, sum = 0
5515 06:48:49.499845 2, 0xFFFF, sum = 0
5516 06:48:49.499928 3, 0xFFFF, sum = 0
5517 06:48:49.502767 4, 0xFFFF, sum = 0
5518 06:48:49.506109 5, 0xFFFF, sum = 0
5519 06:48:49.506191 6, 0xFFFF, sum = 0
5520 06:48:49.509143 7, 0xFFFF, sum = 0
5521 06:48:49.509224 8, 0xFFFF, sum = 0
5522 06:48:49.512126 9, 0xFFFF, sum = 0
5523 06:48:49.512207 10, 0x0, sum = 1
5524 06:48:49.516335 11, 0x0, sum = 2
5525 06:48:49.516417 12, 0x0, sum = 3
5526 06:48:49.516482 13, 0x0, sum = 4
5527 06:48:49.519212 best_step = 11
5528 06:48:49.519293
5529 06:48:49.519357 ==
5530 06:48:49.523003 Dram Type= 6, Freq= 0, CH_1, rank 0
5531 06:48:49.525449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5532 06:48:49.525530 ==
5533 06:48:49.529021 RX Vref Scan: 1
5534 06:48:49.529101
5535 06:48:49.532162 RX Vref 0 -> 0, step: 1
5536 06:48:49.532242
5537 06:48:49.532305 RX Delay -69 -> 252, step: 4
5538 06:48:49.532366
5539 06:48:49.535963 Set Vref, RX VrefLevel [Byte0]: 57
5540 06:48:49.538704 [Byte1]: 48
5541 06:48:49.543937
5542 06:48:49.544017 Final RX Vref Byte 0 = 57 to rank0
5543 06:48:49.546909 Final RX Vref Byte 1 = 48 to rank0
5544 06:48:49.550514 Final RX Vref Byte 0 = 57 to rank1
5545 06:48:49.554356 Final RX Vref Byte 1 = 48 to rank1==
5546 06:48:49.556847 Dram Type= 6, Freq= 0, CH_1, rank 0
5547 06:48:49.563490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5548 06:48:49.563571 ==
5549 06:48:49.563636 DQS Delay:
5550 06:48:49.567648 DQS0 = 0, DQS1 = 0
5551 06:48:49.567728 DQM Delay:
5552 06:48:49.567792 DQM0 = 94, DQM1 = 88
5553 06:48:49.571555 DQ Delay:
5554 06:48:49.573425 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5555 06:48:49.576910 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =92
5556 06:48:49.580239 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =82
5557 06:48:49.583430 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5558 06:48:49.583510
5559 06:48:49.583578
5560 06:48:49.589712 [DQSOSCAuto] RK0, (LSB)MR18= 0x3535, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5561 06:48:49.593035 CH1 RK0: MR19=505, MR18=3535
5562 06:48:49.599599 CH1_RK0: MR19=0x505, MR18=0x3535, DQSOSC=405, MR23=63, INC=66, DEC=44
5563 06:48:49.599680
5564 06:48:49.603462 ----->DramcWriteLeveling(PI) begin...
5565 06:48:49.603544 ==
5566 06:48:49.606748 Dram Type= 6, Freq= 0, CH_1, rank 1
5567 06:48:49.610133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5568 06:48:49.610215 ==
5569 06:48:49.613567 Write leveling (Byte 0): 26 => 26
5570 06:48:49.616856 Write leveling (Byte 1): 26 => 26
5571 06:48:49.619990 DramcWriteLeveling(PI) end<-----
5572 06:48:49.620070
5573 06:48:49.620134 ==
5574 06:48:49.623022 Dram Type= 6, Freq= 0, CH_1, rank 1
5575 06:48:49.626347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5576 06:48:49.629487 ==
5577 06:48:49.629566 [Gating] SW mode calibration
5578 06:48:49.639653 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5579 06:48:49.644017 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5580 06:48:49.646123 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 06:48:49.652943 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 06:48:49.655959 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 06:48:49.659722 0 10 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5584 06:48:49.665907 0 10 16 | B1->B0 | 3434 2626 | 0 1 | (0 0) (1 1)
5585 06:48:49.669101 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5586 06:48:49.672606 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 06:48:49.679288 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 06:48:49.682483 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 06:48:49.685535 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 06:48:49.692456 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 06:48:49.695774 0 11 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5592 06:48:49.699046 0 11 16 | B1->B0 | 2424 4040 | 0 0 | (0 0) (0 0)
5593 06:48:49.705907 0 11 20 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5594 06:48:49.709097 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 06:48:49.713147 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 06:48:49.719164 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 06:48:49.722466 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 06:48:49.725578 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 06:48:49.732655 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 06:48:49.735234 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5601 06:48:49.739206 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5602 06:48:49.745541 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 06:48:49.749500 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 06:48:49.752303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 06:48:49.758748 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 06:48:49.761960 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 06:48:49.765354 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 06:48:49.771642 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 06:48:49.774758 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 06:48:49.778159 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 06:48:49.784811 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 06:48:49.788620 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 06:48:49.791931 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 06:48:49.798272 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 06:48:49.801325 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 06:48:49.804441 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5617 06:48:49.807951 Total UI for P1: 0, mck2ui 16
5618 06:48:49.811162 best dqsien dly found for B0: ( 0, 14, 14)
5619 06:48:49.814700 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5620 06:48:49.821134 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 06:48:49.824796 Total UI for P1: 0, mck2ui 16
5622 06:48:49.828086 best dqsien dly found for B1: ( 0, 14, 18)
5623 06:48:49.831482 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5624 06:48:49.834474 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5625 06:48:49.834555
5626 06:48:49.837684 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5627 06:48:49.841156 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5628 06:48:49.844206 [Gating] SW calibration Done
5629 06:48:49.844286 ==
5630 06:48:49.847761 Dram Type= 6, Freq= 0, CH_1, rank 1
5631 06:48:49.851109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5632 06:48:49.854623 ==
5633 06:48:49.854702 RX Vref Scan: 0
5634 06:48:49.854767
5635 06:48:49.858098 RX Vref 0 -> 0, step: 1
5636 06:48:49.858179
5637 06:48:49.858243 RX Delay -80 -> 252, step: 8
5638 06:48:49.864908 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5639 06:48:49.867655 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5640 06:48:49.871004 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5641 06:48:49.874817 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5642 06:48:49.877689 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5643 06:48:49.881456 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5644 06:48:49.888371 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5645 06:48:49.892001 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5646 06:48:49.895378 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5647 06:48:49.897780 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5648 06:48:49.901835 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5649 06:48:49.907382 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5650 06:48:49.911239 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5651 06:48:49.914611 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5652 06:48:49.917969 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5653 06:48:49.920997 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5654 06:48:49.921078 ==
5655 06:48:49.924684 Dram Type= 6, Freq= 0, CH_1, rank 1
5656 06:48:49.930798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5657 06:48:49.930883 ==
5658 06:48:49.931007 DQS Delay:
5659 06:48:49.931070 DQS0 = 0, DQS1 = 0
5660 06:48:49.935320 DQM Delay:
5661 06:48:49.935399 DQM0 = 95, DQM1 = 87
5662 06:48:49.937361 DQ Delay:
5663 06:48:49.940900 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =95
5664 06:48:49.944017 DQ4 =95, DQ5 =107, DQ6 =99, DQ7 =91
5665 06:48:49.947149 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5666 06:48:49.950844 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5667 06:48:49.950925
5668 06:48:49.950989
5669 06:48:49.951048 ==
5670 06:48:49.954668 Dram Type= 6, Freq= 0, CH_1, rank 1
5671 06:48:49.957247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5672 06:48:49.957327 ==
5673 06:48:49.957391
5674 06:48:49.957450
5675 06:48:49.960660 TX Vref Scan disable
5676 06:48:49.960791 == TX Byte 0 ==
5677 06:48:49.967248 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5678 06:48:49.970532 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5679 06:48:49.970613 == TX Byte 1 ==
5680 06:48:49.977535 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5681 06:48:49.980760 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5682 06:48:49.980840 ==
5683 06:48:49.984119 Dram Type= 6, Freq= 0, CH_1, rank 1
5684 06:48:49.987265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5685 06:48:49.987346 ==
5686 06:48:49.987411
5687 06:48:49.990605
5688 06:48:49.990685 TX Vref Scan disable
5689 06:48:49.993939 == TX Byte 0 ==
5690 06:48:49.997038 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5691 06:48:50.000204 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5692 06:48:50.003509 == TX Byte 1 ==
5693 06:48:50.007235 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5694 06:48:50.013381 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5695 06:48:50.013462
5696 06:48:50.013525 [DATLAT]
5697 06:48:50.013584 Freq=933, CH1 RK1
5698 06:48:50.013642
5699 06:48:50.017091 DATLAT Default: 0xb
5700 06:48:50.017171 0, 0xFFFF, sum = 0
5701 06:48:50.020415 1, 0xFFFF, sum = 0
5702 06:48:50.020497 2, 0xFFFF, sum = 0
5703 06:48:50.023457 3, 0xFFFF, sum = 0
5704 06:48:50.023538 4, 0xFFFF, sum = 0
5705 06:48:50.026681 5, 0xFFFF, sum = 0
5706 06:48:50.030598 6, 0xFFFF, sum = 0
5707 06:48:50.030679 7, 0xFFFF, sum = 0
5708 06:48:50.033215 8, 0xFFFF, sum = 0
5709 06:48:50.033296 9, 0xFFFF, sum = 0
5710 06:48:50.036709 10, 0x0, sum = 1
5711 06:48:50.036792 11, 0x0, sum = 2
5712 06:48:50.036857 12, 0x0, sum = 3
5713 06:48:50.040120 13, 0x0, sum = 4
5714 06:48:50.040201 best_step = 11
5715 06:48:50.040265
5716 06:48:50.043039 ==
5717 06:48:50.043119 Dram Type= 6, Freq= 0, CH_1, rank 1
5718 06:48:50.049737 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5719 06:48:50.049845 ==
5720 06:48:50.049956 RX Vref Scan: 0
5721 06:48:50.050027
5722 06:48:50.053153 RX Vref 0 -> 0, step: 1
5723 06:48:50.053233
5724 06:48:50.056373 RX Delay -69 -> 252, step: 4
5725 06:48:50.060137 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5726 06:48:50.068304 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5727 06:48:50.069771 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5728 06:48:50.073066 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5729 06:48:50.076434 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5730 06:48:50.080204 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5731 06:48:50.086393 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5732 06:48:50.089583 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5733 06:48:50.093101 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5734 06:48:50.096300 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5735 06:48:50.099724 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5736 06:48:50.103056 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5737 06:48:50.110464 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5738 06:48:50.113321 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5739 06:48:50.116449 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5740 06:48:50.119201 iDelay=203, Bit 15, Center 98 (11 ~ 186) 176
5741 06:48:50.119329 ==
5742 06:48:50.122860 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 06:48:50.129722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5744 06:48:50.129865 ==
5745 06:48:50.129993 DQS Delay:
5746 06:48:50.130112 DQS0 = 0, DQS1 = 0
5747 06:48:50.132479 DQM Delay:
5748 06:48:50.132614 DQM0 = 95, DQM1 = 88
5749 06:48:50.136674 DQ Delay:
5750 06:48:50.139117 DQ0 =96, DQ1 =92, DQ2 =88, DQ3 =92
5751 06:48:50.142414 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =94
5752 06:48:50.145853 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =82
5753 06:48:50.150286 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =98
5754 06:48:50.150387
5755 06:48:50.150478
5756 06:48:50.155759 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5757 06:48:50.158915 CH1 RK1: MR19=505, MR18=2121
5758 06:48:50.165680 CH1_RK1: MR19=0x505, MR18=0x2121, DQSOSC=411, MR23=63, INC=64, DEC=42
5759 06:48:50.169252 [RxdqsGatingPostProcess] freq 933
5760 06:48:50.172455 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5761 06:48:50.175666 Pre-setting of DQS Precalculation
5762 06:48:50.182162 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5763 06:48:50.189029 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5764 06:48:50.196436 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5765 06:48:50.196517
5766 06:48:50.196581
5767 06:48:50.199065 [Calibration Summary] 1866 Mbps
5768 06:48:50.199171 CH 0, Rank 0
5769 06:48:50.202115 SW Impedance : PASS
5770 06:48:50.205884 DUTY Scan : NO K
5771 06:48:50.205965 ZQ Calibration : PASS
5772 06:48:50.208898 Jitter Meter : NO K
5773 06:48:50.212193 CBT Training : PASS
5774 06:48:50.212274 Write leveling : PASS
5775 06:48:50.215769 RX DQS gating : PASS
5776 06:48:50.219553 RX DQ/DQS(RDDQC) : PASS
5777 06:48:50.219633 TX DQ/DQS : PASS
5778 06:48:50.221878 RX DATLAT : PASS
5779 06:48:50.225720 RX DQ/DQS(Engine): PASS
5780 06:48:50.225800 TX OE : NO K
5781 06:48:50.229016 All Pass.
5782 06:48:50.229096
5783 06:48:50.229160 CH 0, Rank 1
5784 06:48:50.231822 SW Impedance : PASS
5785 06:48:50.231903 DUTY Scan : NO K
5786 06:48:50.235959 ZQ Calibration : PASS
5787 06:48:50.238842 Jitter Meter : NO K
5788 06:48:50.238922 CBT Training : PASS
5789 06:48:50.242405 Write leveling : PASS
5790 06:48:50.242485 RX DQS gating : PASS
5791 06:48:50.246037 RX DQ/DQS(RDDQC) : PASS
5792 06:48:50.249057 TX DQ/DQS : PASS
5793 06:48:50.249137 RX DATLAT : PASS
5794 06:48:50.251738 RX DQ/DQS(Engine): PASS
5795 06:48:50.255129 TX OE : NO K
5796 06:48:50.255211 All Pass.
5797 06:48:50.255275
5798 06:48:50.255334 CH 1, Rank 0
5799 06:48:50.258484 SW Impedance : PASS
5800 06:48:50.261862 DUTY Scan : NO K
5801 06:48:50.261941 ZQ Calibration : PASS
5802 06:48:50.265452 Jitter Meter : NO K
5803 06:48:50.268585 CBT Training : PASS
5804 06:48:50.268666 Write leveling : PASS
5805 06:48:50.272092 RX DQS gating : PASS
5806 06:48:50.275217 RX DQ/DQS(RDDQC) : PASS
5807 06:48:50.275339 TX DQ/DQS : PASS
5808 06:48:50.278159 RX DATLAT : PASS
5809 06:48:50.282160 RX DQ/DQS(Engine): PASS
5810 06:48:50.282260 TX OE : NO K
5811 06:48:50.284881 All Pass.
5812 06:48:50.284962
5813 06:48:50.285026 CH 1, Rank 1
5814 06:48:50.288692 SW Impedance : PASS
5815 06:48:50.288804 DUTY Scan : NO K
5816 06:48:50.291994 ZQ Calibration : PASS
5817 06:48:50.295176 Jitter Meter : NO K
5818 06:48:50.295282 CBT Training : PASS
5819 06:48:50.298450 Write leveling : PASS
5820 06:48:50.301478 RX DQS gating : PASS
5821 06:48:50.301558 RX DQ/DQS(RDDQC) : PASS
5822 06:48:50.305241 TX DQ/DQS : PASS
5823 06:48:50.305321 RX DATLAT : PASS
5824 06:48:50.307929 RX DQ/DQS(Engine): PASS
5825 06:48:50.312348 TX OE : NO K
5826 06:48:50.312454 All Pass.
5827 06:48:50.312545
5828 06:48:50.315471 DramC Write-DBI off
5829 06:48:50.315577 PER_BANK_REFRESH: Hybrid Mode
5830 06:48:50.318558 TX_TRACKING: ON
5831 06:48:50.328265 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5832 06:48:50.331878 [FAST_K] Save calibration result to emmc
5833 06:48:50.334879 dramc_set_vcore_voltage set vcore to 650000
5834 06:48:50.334982 Read voltage for 400, 6
5835 06:48:50.337999 Vio18 = 0
5836 06:48:50.338098 Vcore = 650000
5837 06:48:50.338187 Vdram = 0
5838 06:48:50.341776 Vddq = 0
5839 06:48:50.341856 Vmddr = 0
5840 06:48:50.348287 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5841 06:48:50.350831 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5842 06:48:50.355369 MEM_TYPE=3, freq_sel=20
5843 06:48:50.358011 sv_algorithm_assistance_LP4_800
5844 06:48:50.361944 ============ PULL DRAM RESETB DOWN ============
5845 06:48:50.364625 ========== PULL DRAM RESETB DOWN end =========
5846 06:48:50.371066 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5847 06:48:50.374412 ===================================
5848 06:48:50.374521 LPDDR4 DRAM CONFIGURATION
5849 06:48:50.378392 ===================================
5850 06:48:50.380953 EX_ROW_EN[0] = 0x0
5851 06:48:50.384211 EX_ROW_EN[1] = 0x0
5852 06:48:50.384310 LP4Y_EN = 0x0
5853 06:48:50.388082 WORK_FSP = 0x0
5854 06:48:50.388163 WL = 0x2
5855 06:48:50.390617 RL = 0x2
5856 06:48:50.390722 BL = 0x2
5857 06:48:50.394022 RPST = 0x0
5858 06:48:50.394102 RD_PRE = 0x0
5859 06:48:50.397644 WR_PRE = 0x1
5860 06:48:50.397724 WR_PST = 0x0
5861 06:48:50.401105 DBI_WR = 0x0
5862 06:48:50.401185 DBI_RD = 0x0
5863 06:48:50.403968 OTF = 0x1
5864 06:48:50.407643 ===================================
5865 06:48:50.411496 ===================================
5866 06:48:50.411573 ANA top config
5867 06:48:50.413710 ===================================
5868 06:48:50.417517 DLL_ASYNC_EN = 0
5869 06:48:50.420135 ALL_SLAVE_EN = 1
5870 06:48:50.423932 NEW_RANK_MODE = 1
5871 06:48:50.424014 DLL_IDLE_MODE = 1
5872 06:48:50.427641 LP45_APHY_COMB_EN = 1
5873 06:48:50.430240 TX_ODT_DIS = 1
5874 06:48:50.434039 NEW_8X_MODE = 1
5875 06:48:50.437992 ===================================
5876 06:48:50.440426 ===================================
5877 06:48:50.443906 data_rate = 800
5878 06:48:50.443987 CKR = 1
5879 06:48:50.447125 DQ_P2S_RATIO = 4
5880 06:48:50.450518 ===================================
5881 06:48:50.454317 CA_P2S_RATIO = 4
5882 06:48:50.456733 DQ_CA_OPEN = 0
5883 06:48:50.461039 DQ_SEMI_OPEN = 1
5884 06:48:50.463855 CA_SEMI_OPEN = 1
5885 06:48:50.463961 CA_FULL_RATE = 0
5886 06:48:50.467218 DQ_CKDIV4_EN = 0
5887 06:48:50.470171 CA_CKDIV4_EN = 1
5888 06:48:50.473367 CA_PREDIV_EN = 0
5889 06:48:50.476808 PH8_DLY = 0
5890 06:48:50.480393 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5891 06:48:50.480490 DQ_AAMCK_DIV = 0
5892 06:48:50.483640 CA_AAMCK_DIV = 0
5893 06:48:50.487691 CA_ADMCK_DIV = 4
5894 06:48:50.491019 DQ_TRACK_CA_EN = 0
5895 06:48:50.493221 CA_PICK = 800
5896 06:48:50.496900 CA_MCKIO = 400
5897 06:48:50.496981 MCKIO_SEMI = 400
5898 06:48:50.500743 PLL_FREQ = 3016
5899 06:48:50.503427 DQ_UI_PI_RATIO = 32
5900 06:48:50.507106 CA_UI_PI_RATIO = 32
5901 06:48:50.509891 ===================================
5902 06:48:50.513506 ===================================
5903 06:48:50.516607 memory_type:LPDDR4
5904 06:48:50.516688 GP_NUM : 10
5905 06:48:50.519989 SRAM_EN : 1
5906 06:48:50.523976 MD32_EN : 0
5907 06:48:50.526641 ===================================
5908 06:48:50.526722 [ANA_INIT] >>>>>>>>>>>>>>
5909 06:48:50.529900 <<<<<< [CONFIGURE PHASE]: ANA_TX
5910 06:48:50.533478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5911 06:48:50.536760 ===================================
5912 06:48:50.539879 data_rate = 800,PCW = 0X7400
5913 06:48:50.543458 ===================================
5914 06:48:50.546666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5915 06:48:50.553096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5916 06:48:50.564089 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5917 06:48:50.569619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5918 06:48:50.573938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5919 06:48:50.576193 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5920 06:48:50.576274 [ANA_INIT] flow start
5921 06:48:50.579993 [ANA_INIT] PLL >>>>>>>>
5922 06:48:50.583047 [ANA_INIT] PLL <<<<<<<<
5923 06:48:50.583129 [ANA_INIT] MIDPI >>>>>>>>
5924 06:48:50.586811 [ANA_INIT] MIDPI <<<<<<<<
5925 06:48:50.589531 [ANA_INIT] DLL >>>>>>>>
5926 06:48:50.589612 [ANA_INIT] flow end
5927 06:48:50.596433 ============ LP4 DIFF to SE enter ============
5928 06:48:50.599474 ============ LP4 DIFF to SE exit ============
5929 06:48:50.602985 [ANA_INIT] <<<<<<<<<<<<<
5930 06:48:50.606598 [Flow] Enable top DCM control >>>>>
5931 06:48:53.204367 [Flow] Enable top DCM control <<<<<
5932 06:48:53.204626 Enable DLL master slave shuffle
5933 06:48:53.204914 ==============================================================
5934 06:48:53.204987 Gating Mode config
5935 06:48:53.205049 ==============================================================
5936 06:48:53.205108 Config description:
5937 06:48:53.205165 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5938 06:48:53.205222 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5939 06:48:53.205279 SELPH_MODE 0: By rank 1: By Phase
5940 06:48:53.205335 ==============================================================
5941 06:48:53.205389 GAT_TRACK_EN = 0
5942 06:48:53.205443 RX_GATING_MODE = 2
5943 06:48:53.205515 RX_GATING_TRACK_MODE = 2
5944 06:48:53.205600 SELPH_MODE = 1
5945 06:48:53.205709 PICG_EARLY_EN = 1
5946 06:48:53.205806 VALID_LAT_VALUE = 1
5947 06:48:53.205871 ==============================================================
5948 06:48:53.205923 Enter into Gating configuration >>>>
5949 06:48:53.205976 Exit from Gating configuration <<<<
5950 06:48:53.206028 Enter into DVFS_PRE_config >>>>>
5951 06:48:53.206102 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5952 06:48:53.206211 Exit from DVFS_PRE_config <<<<<
5953 06:48:53.206316 Enter into PICG configuration >>>>
5954 06:48:53.206421 Exit from PICG configuration <<<<
5955 06:48:53.206525 [RX_INPUT] configuration >>>>>
5956 06:48:53.206630 [RX_INPUT] configuration <<<<<
5957 06:48:53.206734 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5958 06:48:53.206839 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5959 06:48:53.206945 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5960 06:48:53.207050 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5961 06:48:53.207129 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5962 06:48:53.207185 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5963 06:48:53.207239 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5964 06:48:53.207293 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5965 06:48:53.207353 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5966 06:48:53.207407 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5967 06:48:53.207460 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5968 06:48:53.207513 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5969 06:48:53.207566 ===================================
5970 06:48:53.207620 LPDDR4 DRAM CONFIGURATION
5971 06:48:53.207677 ===================================
5972 06:48:53.207768 EX_ROW_EN[0] = 0x0
5973 06:48:53.207822 EX_ROW_EN[1] = 0x0
5974 06:48:53.207875 LP4Y_EN = 0x0
5975 06:48:53.207928 WORK_FSP = 0x0
5976 06:48:53.207982 WL = 0x2
5977 06:48:53.208034 RL = 0x2
5978 06:48:53.208086 BL = 0x2
5979 06:48:53.208139 RPST = 0x0
5980 06:48:53.208191 RD_PRE = 0x0
5981 06:48:53.208244 WR_PRE = 0x1
5982 06:48:53.208296 WR_PST = 0x0
5983 06:48:53.208348 DBI_WR = 0x0
5984 06:48:53.208401 DBI_RD = 0x0
5985 06:48:53.208454 OTF = 0x1
5986 06:48:53.208507 ===================================
5987 06:48:53.208572 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5988 06:48:53.208625 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5989 06:48:53.208676 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5990 06:48:53.208767 ===================================
5991 06:48:53.208832 LPDDR4 DRAM CONFIGURATION
5992 06:48:53.208884 ===================================
5993 06:48:53.208937 EX_ROW_EN[0] = 0x10
5994 06:48:53.208989 EX_ROW_EN[1] = 0x0
5995 06:48:53.209070 LP4Y_EN = 0x0
5996 06:48:53.209121 WORK_FSP = 0x0
5997 06:48:53.209173 WL = 0x2
5998 06:48:53.209225 RL = 0x2
5999 06:48:53.209290 BL = 0x2
6000 06:48:53.209355 RPST = 0x0
6001 06:48:53.209406 RD_PRE = 0x0
6002 06:48:53.209458 WR_PRE = 0x1
6003 06:48:53.209523 WR_PST = 0x0
6004 06:48:53.209588 DBI_WR = 0x0
6005 06:48:53.209639 DBI_RD = 0x0
6006 06:48:53.209690 OTF = 0x1
6007 06:48:53.209742 ===================================
6008 06:48:53.209822 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6009 06:48:53.209874 nWR fixed to 30
6010 06:48:53.209926 [ModeRegInit_LP4] CH0 RK0
6011 06:48:53.209978 [ModeRegInit_LP4] CH0 RK1
6012 06:48:53.210056 [ModeRegInit_LP4] CH1 RK0
6013 06:48:53.210107 [ModeRegInit_LP4] CH1 RK1
6014 06:48:53.210159 match AC timing 18
6015 06:48:53.210210 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6016 06:48:53.210276 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6017 06:48:53.210341 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6018 06:48:53.210393 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6019 06:48:53.210445 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6020 06:48:53.210510 ==
6021 06:48:53.210595 Dram Type= 6, Freq= 0, CH_0, rank 0
6022 06:48:53.210663 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6023 06:48:53.210716 ==
6024 06:48:53.210782 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6025 06:48:53.210848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6026 06:48:53.210901 [CA 0] Center 36 (8~64) winsize 57
6027 06:48:53.210953 [CA 1] Center 36 (8~64) winsize 57
6028 06:48:53.211019 [CA 2] Center 36 (8~64) winsize 57
6029 06:48:53.211084 [CA 3] Center 36 (8~64) winsize 57
6030 06:48:53.211136 [CA 4] Center 36 (8~64) winsize 57
6031 06:48:53.211187 [CA 5] Center 36 (8~64) winsize 57
6032 06:48:53.211239
6033 06:48:53.211317 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6034 06:48:53.211369
6035 06:48:53.211422 [CATrainingPosCal] consider 1 rank data
6036 06:48:53.211474 u2DelayCellTimex100 = 270/100 ps
6037 06:48:53.211552 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6038 06:48:53.211605 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6039 06:48:53.211657 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6040 06:48:53.211709 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6041 06:48:53.211999 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6042 06:48:53.212084 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6043 06:48:53.212140
6044 06:48:53.212193 CA PerBit enable=1, Macro0, CA PI delay=36
6045 06:48:53.212247
6046 06:48:53.212299 [CBTSetCACLKResult] CA Dly = 36
6047 06:48:53.212351 CS Dly: 1 (0~32)
6048 06:48:53.212404 ==
6049 06:48:53.212457 Dram Type= 6, Freq= 0, CH_0, rank 1
6050 06:48:53.212509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6051 06:48:53.212579 ==
6052 06:48:53.212685 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6053 06:48:53.212843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6054 06:48:53.212949 [CA 0] Center 36 (8~64) winsize 57
6055 06:48:53.213052 [CA 1] Center 36 (8~64) winsize 57
6056 06:48:53.213169 [CA 2] Center 36 (8~64) winsize 57
6057 06:48:53.213286 [CA 3] Center 36 (8~64) winsize 57
6058 06:48:53.213403 [CA 4] Center 36 (8~64) winsize 57
6059 06:48:53.213520 [CA 5] Center 36 (8~64) winsize 57
6060 06:48:53.213576
6061 06:48:53.213642 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6062 06:48:53.213708
6063 06:48:53.213760 [CATrainingPosCal] consider 2 rank data
6064 06:48:53.213813 u2DelayCellTimex100 = 270/100 ps
6065 06:48:53.213878 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6066 06:48:53.213950 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6067 06:48:53.214002 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6068 06:48:53.214054 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6069 06:48:53.214106 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6070 06:48:53.214185 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6071 06:48:53.214236
6072 06:48:53.214289 CA PerBit enable=1, Macro0, CA PI delay=36
6073 06:48:53.214340
6074 06:48:53.214406 [CBTSetCACLKResult] CA Dly = 36
6075 06:48:53.214471 CS Dly: 1 (0~32)
6076 06:48:53.214522
6077 06:48:53.214573 ----->DramcWriteLeveling(PI) begin...
6078 06:48:53.214640 ==
6079 06:48:53.214706 Dram Type= 6, Freq= 0, CH_0, rank 0
6080 06:48:53.214758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6081 06:48:53.214811 ==
6082 06:48:53.214876 Write leveling (Byte 0): 32 => 0
6083 06:48:53.214942 Write leveling (Byte 1): 32 => 0
6084 06:48:53.214993 DramcWriteLeveling(PI) end<-----
6085 06:48:53.215045
6086 06:48:53.215096 ==
6087 06:48:53.215175 Dram Type= 6, Freq= 0, CH_0, rank 0
6088 06:48:53.215227 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6089 06:48:53.215280 ==
6090 06:48:53.215332 [Gating] SW mode calibration
6091 06:48:53.215398 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6092 06:48:53.215464 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6093 06:48:53.215517 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6094 06:48:53.215569 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6095 06:48:53.215635 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6096 06:48:53.215701 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6097 06:48:53.215785 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6098 06:48:53.215844 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6099 06:48:53.215911 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6100 06:48:53.215976 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6101 06:48:53.216028 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6102 06:48:53.216079 Total UI for P1: 0, mck2ui 16
6103 06:48:53.216145 best dqsien dly found for B0: ( 0, 10, 16)
6104 06:48:53.216212 Total UI for P1: 0, mck2ui 16
6105 06:48:53.216264 best dqsien dly found for B1: ( 0, 10, 16)
6106 06:48:53.216316 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6107 06:48:53.216382 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6108 06:48:53.216448
6109 06:48:53.216500 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6110 06:48:53.216553 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6111 06:48:53.216605 [Gating] SW calibration Done
6112 06:48:53.216671 ==
6113 06:48:53.216732 Dram Type= 6, Freq= 0, CH_0, rank 0
6114 06:48:53.216799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6115 06:48:53.216851 ==
6116 06:48:53.216931 RX Vref Scan: 0
6117 06:48:53.216983
6118 06:48:53.217035 RX Vref 0 -> 0, step: 1
6119 06:48:53.217087
6120 06:48:53.217153 RX Delay -410 -> 252, step: 16
6121 06:48:53.217219 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6122 06:48:53.217272 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6123 06:48:53.217323 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6124 06:48:53.217389 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6125 06:48:53.217455 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6126 06:48:53.217507 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6127 06:48:53.217559 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6128 06:48:53.217611 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6129 06:48:53.217677 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6130 06:48:53.217730 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6131 06:48:53.217787 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6132 06:48:53.217841 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6133 06:48:53.217894 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6134 06:48:53.217947 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6135 06:48:53.218001 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6136 06:48:53.218053 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6137 06:48:53.218106 ==
6138 06:48:53.218159 Dram Type= 6, Freq= 0, CH_0, rank 0
6139 06:48:53.218212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6140 06:48:53.218264 ==
6141 06:48:53.218317 DQS Delay:
6142 06:48:53.218394 DQS0 = 51, DQS1 = 59
6143 06:48:53.218499 DQM Delay:
6144 06:48:53.218629 DQM0 = 12, DQM1 = 13
6145 06:48:53.218732 DQ Delay:
6146 06:48:53.218862 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6147 06:48:53.218966 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6148 06:48:53.219084 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6149 06:48:53.219190 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6150 06:48:53.219396
6151 06:48:53.219453
6152 06:48:53.219507 ==
6153 06:48:53.219561 Dram Type= 6, Freq= 0, CH_0, rank 0
6154 06:48:53.219615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6155 06:48:53.219669 ==
6156 06:48:53.219722
6157 06:48:53.219775
6158 06:48:53.219827 TX Vref Scan disable
6159 06:48:53.219881 == TX Byte 0 ==
6160 06:48:53.219934 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6161 06:48:53.219988 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6162 06:48:53.220041 == TX Byte 1 ==
6163 06:48:53.220094 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6164 06:48:53.220147 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6165 06:48:53.220200 ==
6166 06:48:53.220254 Dram Type= 6, Freq= 0, CH_0, rank 0
6167 06:48:53.220548 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6168 06:48:53.220659 ==
6169 06:48:53.220785
6170 06:48:53.220881
6171 06:48:53.220962 TX Vref Scan disable
6172 06:48:53.221059 == TX Byte 0 ==
6173 06:48:53.221153 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6174 06:48:53.221248 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6175 06:48:53.221356 == TX Byte 1 ==
6176 06:48:53.221439 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6177 06:48:53.221533 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6178 06:48:53.221642
6179 06:48:53.221722 [DATLAT]
6180 06:48:53.221848 Freq=400, CH0 RK0
6181 06:48:53.221925
6182 06:48:53.221978 DATLAT Default: 0xf
6183 06:48:53.222030 0, 0xFFFF, sum = 0
6184 06:48:53.222085 1, 0xFFFF, sum = 0
6185 06:48:53.222167 2, 0xFFFF, sum = 0
6186 06:48:53.222220 3, 0xFFFF, sum = 0
6187 06:48:53.222273 4, 0xFFFF, sum = 0
6188 06:48:53.222325 5, 0xFFFF, sum = 0
6189 06:48:53.222394 6, 0xFFFF, sum = 0
6190 06:48:53.222460 7, 0xFFFF, sum = 0
6191 06:48:53.222513 8, 0xFFFF, sum = 0
6192 06:48:53.222566 9, 0xFFFF, sum = 0
6193 06:48:53.222619 10, 0xFFFF, sum = 0
6194 06:48:53.222701 11, 0xFFFF, sum = 0
6195 06:48:53.222754 12, 0x0, sum = 1
6196 06:48:53.222807 13, 0x0, sum = 2
6197 06:48:53.222860 14, 0x0, sum = 3
6198 06:48:53.222928 15, 0x0, sum = 4
6199 06:48:53.222994 best_step = 13
6200 06:48:53.223046
6201 06:48:53.223097 ==
6202 06:48:53.223149 Dram Type= 6, Freq= 0, CH_0, rank 0
6203 06:48:53.223228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6204 06:48:53.223280 ==
6205 06:48:53.223332 RX Vref Scan: 1
6206 06:48:53.223384
6207 06:48:53.223449 RX Vref 0 -> 0, step: 1
6208 06:48:53.223514
6209 06:48:53.223583 RX Delay -359 -> 252, step: 8
6210 06:48:53.223679
6211 06:48:53.223786 Set Vref, RX VrefLevel [Byte0]: 52
6212 06:48:53.223894 [Byte1]: 48
6213 06:48:53.223952
6214 06:48:53.224020 Final RX Vref Byte 0 = 52 to rank0
6215 06:48:53.224074 Final RX Vref Byte 1 = 48 to rank0
6216 06:48:53.224127 Final RX Vref Byte 0 = 52 to rank1
6217 06:48:53.224180 Final RX Vref Byte 1 = 48 to rank1==
6218 06:48:53.224248 Dram Type= 6, Freq= 0, CH_0, rank 0
6219 06:48:53.224302 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6220 06:48:53.224356 ==
6221 06:48:53.224409 DQS Delay:
6222 06:48:53.224462 DQS0 = 52, DQS1 = 68
6223 06:48:53.224515 DQM Delay:
6224 06:48:53.224568 DQM0 = 9, DQM1 = 16
6225 06:48:53.224621 DQ Delay:
6226 06:48:53.224674 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6227 06:48:53.224755 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6228 06:48:53.224823 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6229 06:48:53.224876 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6230 06:48:53.224930
6231 06:48:53.224982
6232 06:48:53.225048 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaaa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6233 06:48:53.225101 CH0 RK0: MR19=C0C, MR18=AAAA
6234 06:48:53.225154 CH0_RK0: MR19=0xC0C, MR18=0xAAAA, DQSOSC=388, MR23=63, INC=392, DEC=261
6235 06:48:53.225206 ==
6236 06:48:53.225272 Dram Type= 6, Freq= 0, CH_0, rank 1
6237 06:48:53.225338 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6238 06:48:53.225391 ==
6239 06:48:53.225443 [Gating] SW mode calibration
6240 06:48:53.225509 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6241 06:48:53.225575 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6242 06:48:53.225628 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6243 06:48:53.225680 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6244 06:48:53.225732 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6245 06:48:53.225812 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6246 06:48:53.225864 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6247 06:48:53.225929 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6248 06:48:53.225982 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6249 06:48:53.226074 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6250 06:48:53.226126 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6251 06:48:53.226179 Total UI for P1: 0, mck2ui 16
6252 06:48:53.226231 best dqsien dly found for B0: ( 0, 10, 16)
6253 06:48:53.226296 Total UI for P1: 0, mck2ui 16
6254 06:48:53.226350 best dqsien dly found for B1: ( 0, 10, 16)
6255 06:48:53.226419 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6256 06:48:53.226487 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6257 06:48:53.226556
6258 06:48:53.226622 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6259 06:48:53.226675 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6260 06:48:53.226727 [Gating] SW calibration Done
6261 06:48:53.226780 ==
6262 06:48:53.226833 Dram Type= 6, Freq= 0, CH_0, rank 1
6263 06:48:53.226886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6264 06:48:53.226940 ==
6265 06:48:53.226992 RX Vref Scan: 0
6266 06:48:53.227045
6267 06:48:53.227097 RX Vref 0 -> 0, step: 1
6268 06:48:53.227150
6269 06:48:53.227202 RX Delay -410 -> 252, step: 16
6270 06:48:53.227256 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6271 06:48:53.227309 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6272 06:48:53.227362 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6273 06:48:53.227415 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6274 06:48:53.227468 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6275 06:48:53.227521 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6276 06:48:53.227573 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6277 06:48:53.227625 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6278 06:48:53.227678 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6279 06:48:53.227731 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6280 06:48:53.227783 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6281 06:48:53.227836 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6282 06:48:53.227888 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6283 06:48:53.227941 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6284 06:48:53.227993 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6285 06:48:53.228046 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6286 06:48:53.228098 ==
6287 06:48:53.228151 Dram Type= 6, Freq= 0, CH_0, rank 1
6288 06:48:53.228203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6289 06:48:53.228256 ==
6290 06:48:53.228309 DQS Delay:
6291 06:48:53.228361 DQS0 = 43, DQS1 = 59
6292 06:48:53.228414 DQM Delay:
6293 06:48:53.228467 DQM0 = 6, DQM1 = 15
6294 06:48:53.228520 DQ Delay:
6295 06:48:53.228572 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6296 06:48:53.228625 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6297 06:48:53.228678 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6298 06:48:53.228789 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6299 06:48:53.228842
6300 06:48:53.228937
6301 06:48:53.229018 ==
6302 06:48:53.229083 Dram Type= 6, Freq= 0, CH_0, rank 1
6303 06:48:53.229163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6304 06:48:53.229215 ==
6305 06:48:53.229267
6306 06:48:53.229319
6307 06:48:53.229384 TX Vref Scan disable
6308 06:48:53.229436 == TX Byte 0 ==
6309 06:48:53.229533 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6310 06:48:53.229805 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6311 06:48:53.229896 == TX Byte 1 ==
6312 06:48:53.229951 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6313 06:48:53.230006 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6314 06:48:53.230060 ==
6315 06:48:53.230114 Dram Type= 6, Freq= 0, CH_0, rank 1
6316 06:48:53.230168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6317 06:48:53.230222 ==
6318 06:48:53.230276
6319 06:48:53.230329
6320 06:48:53.230381 TX Vref Scan disable
6321 06:48:53.230434 == TX Byte 0 ==
6322 06:48:53.230488 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6323 06:48:53.230541 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6324 06:48:53.230594 == TX Byte 1 ==
6325 06:48:53.230647 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6326 06:48:53.230713 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6327 06:48:53.230765
6328 06:48:53.230816 [DATLAT]
6329 06:48:53.230868 Freq=400, CH0 RK1
6330 06:48:53.230920
6331 06:48:53.230971 DATLAT Default: 0xd
6332 06:48:53.231022 0, 0xFFFF, sum = 0
6333 06:48:53.231075 1, 0xFFFF, sum = 0
6334 06:48:53.231127 2, 0xFFFF, sum = 0
6335 06:48:53.231180 3, 0xFFFF, sum = 0
6336 06:48:53.231233 4, 0xFFFF, sum = 0
6337 06:48:53.231285 5, 0xFFFF, sum = 0
6338 06:48:53.231353 6, 0xFFFF, sum = 0
6339 06:48:53.231407 7, 0xFFFF, sum = 0
6340 06:48:53.231460 8, 0xFFFF, sum = 0
6341 06:48:53.231513 9, 0xFFFF, sum = 0
6342 06:48:53.231566 10, 0xFFFF, sum = 0
6343 06:48:53.231620 11, 0xFFFF, sum = 0
6344 06:48:53.231674 12, 0x0, sum = 1
6345 06:48:53.231728 13, 0x0, sum = 2
6346 06:48:53.231781 14, 0x0, sum = 3
6347 06:48:53.231835 15, 0x0, sum = 4
6348 06:48:53.231916 best_step = 13
6349 06:48:53.231982
6350 06:48:53.232033 ==
6351 06:48:53.232084 Dram Type= 6, Freq= 0, CH_0, rank 1
6352 06:48:53.232136 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6353 06:48:53.232188 ==
6354 06:48:53.232240 RX Vref Scan: 0
6355 06:48:53.232291
6356 06:48:53.232342 RX Vref 0 -> 0, step: 1
6357 06:48:53.232393
6358 06:48:53.232443 RX Delay -359 -> 252, step: 8
6359 06:48:53.232511 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6360 06:48:53.232563 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6361 06:48:53.232616 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6362 06:48:53.232668 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6363 06:48:53.232760 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6364 06:48:53.232815 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6365 06:48:53.232867 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6366 06:48:53.232920 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6367 06:48:53.232972 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6368 06:48:53.233024 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6369 06:48:53.233077 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6370 06:48:53.233129 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6371 06:48:53.233181 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6372 06:48:53.233246 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6373 06:48:53.233311 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6374 06:48:53.233364 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6375 06:48:53.233416 ==
6376 06:48:53.233468 Dram Type= 6, Freq= 0, CH_0, rank 1
6377 06:48:53.233521 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6378 06:48:53.233573 ==
6379 06:48:53.233626 DQS Delay:
6380 06:48:53.233678 DQS0 = 52, DQS1 = 64
6381 06:48:53.233730 DQM Delay:
6382 06:48:53.233811 DQM0 = 10, DQM1 = 13
6383 06:48:53.233863 DQ Delay:
6384 06:48:53.233915 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6385 06:48:53.233968 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6386 06:48:53.234022 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6387 06:48:53.234075 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6388 06:48:53.234127
6389 06:48:53.234179
6390 06:48:53.234230 [DQSOSCAuto] RK1, (LSB)MR18= 0xc8c8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6391 06:48:53.234284 CH0 RK1: MR19=C0C, MR18=C8C8
6392 06:48:53.234336 CH0_RK1: MR19=0xC0C, MR18=0xC8C8, DQSOSC=385, MR23=63, INC=398, DEC=265
6393 06:48:53.234389 [RxdqsGatingPostProcess] freq 400
6394 06:48:53.234441 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6395 06:48:53.234506 Pre-setting of DQS Precalculation
6396 06:48:53.234558 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6397 06:48:53.234609 ==
6398 06:48:53.234678 Dram Type= 6, Freq= 0, CH_1, rank 0
6399 06:48:53.234742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6400 06:48:53.234794 ==
6401 06:48:53.234845 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6402 06:48:53.234896 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6403 06:48:53.234947 [CA 0] Center 36 (8~64) winsize 57
6404 06:48:53.234999 [CA 1] Center 36 (8~64) winsize 57
6405 06:48:53.235050 [CA 2] Center 36 (8~64) winsize 57
6406 06:48:53.235117 [CA 3] Center 36 (8~64) winsize 57
6407 06:48:53.235197 [CA 4] Center 36 (8~64) winsize 57
6408 06:48:53.235277 [CA 5] Center 36 (8~64) winsize 57
6409 06:48:53.235329
6410 06:48:53.235381 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6411 06:48:53.235433
6412 06:48:53.235484 [CATrainingPosCal] consider 1 rank data
6413 06:48:53.235536 u2DelayCellTimex100 = 270/100 ps
6414 06:48:53.235589 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6415 06:48:53.235642 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6416 06:48:53.235694 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6417 06:48:53.235747 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6418 06:48:53.235799 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6419 06:48:53.235852 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6420 06:48:53.235903
6421 06:48:53.235955 CA PerBit enable=1, Macro0, CA PI delay=36
6422 06:48:53.236022
6423 06:48:53.236078 [CBTSetCACLKResult] CA Dly = 36
6424 06:48:53.236132 CS Dly: 1 (0~32)
6425 06:48:53.236185 ==
6426 06:48:53.236238 Dram Type= 6, Freq= 0, CH_1, rank 1
6427 06:48:53.236290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6428 06:48:53.236343 ==
6429 06:48:53.236396 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6430 06:48:53.236449 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6431 06:48:53.236501 [CA 0] Center 36 (8~64) winsize 57
6432 06:48:53.236554 [CA 1] Center 36 (8~64) winsize 57
6433 06:48:53.236605 [CA 2] Center 36 (8~64) winsize 57
6434 06:48:53.236658 [CA 3] Center 36 (8~64) winsize 57
6435 06:48:53.236731 [CA 4] Center 36 (8~64) winsize 57
6436 06:48:53.236838 [CA 5] Center 36 (8~64) winsize 57
6437 06:48:53.236890
6438 06:48:53.236943 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6439 06:48:53.236995
6440 06:48:53.237047 [CATrainingPosCal] consider 2 rank data
6441 06:48:53.237099 u2DelayCellTimex100 = 270/100 ps
6442 06:48:53.237151 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6443 06:48:53.237443 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6444 06:48:53.237508 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6445 06:48:53.237563 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6446 06:48:53.237616 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6447 06:48:53.237670 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6448 06:48:53.237722
6449 06:48:53.237775 CA PerBit enable=1, Macro0, CA PI delay=36
6450 06:48:53.237828
6451 06:48:53.237881 [CBTSetCACLKResult] CA Dly = 36
6452 06:48:53.237933 CS Dly: 1 (0~32)
6453 06:48:53.237985
6454 06:48:53.238038 ----->DramcWriteLeveling(PI) begin...
6455 06:48:53.238092 ==
6456 06:48:53.238145 Dram Type= 6, Freq= 0, CH_1, rank 0
6457 06:48:53.238197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6458 06:48:53.238250 ==
6459 06:48:53.238303 Write leveling (Byte 0): 32 => 0
6460 06:48:53.238355 Write leveling (Byte 1): 32 => 0
6461 06:48:53.238407 DramcWriteLeveling(PI) end<-----
6462 06:48:53.238459
6463 06:48:53.238546 ==
6464 06:48:53.238598 Dram Type= 6, Freq= 0, CH_1, rank 0
6465 06:48:53.238652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6466 06:48:53.238706 ==
6467 06:48:53.238758 [Gating] SW mode calibration
6468 06:48:53.238811 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6469 06:48:53.238865 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6470 06:48:53.238917 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6471 06:48:53.238970 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 06:48:53.239023 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 06:48:53.239076 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6474 06:48:53.239128 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 06:48:53.239181 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 06:48:53.239233 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 06:48:53.239286 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6478 06:48:53.239338 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 06:48:53.239390 Total UI for P1: 0, mck2ui 16
6480 06:48:53.239443 best dqsien dly found for B0: ( 0, 10, 16)
6481 06:48:53.239496 Total UI for P1: 0, mck2ui 16
6482 06:48:53.239548 best dqsien dly found for B1: ( 0, 10, 16)
6483 06:48:53.239600 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6484 06:48:53.239653 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6485 06:48:53.239705
6486 06:48:53.239757 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6487 06:48:53.239809 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6488 06:48:53.239862 [Gating] SW calibration Done
6489 06:48:53.239914 ==
6490 06:48:53.239966 Dram Type= 6, Freq= 0, CH_1, rank 0
6491 06:48:53.240018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6492 06:48:53.240071 ==
6493 06:48:53.240123 RX Vref Scan: 0
6494 06:48:53.240175
6495 06:48:53.240227 RX Vref 0 -> 0, step: 1
6496 06:48:53.240279
6497 06:48:53.240331 RX Delay -410 -> 252, step: 16
6498 06:48:53.240383 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6499 06:48:53.240436 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6500 06:48:53.240488 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6501 06:48:53.240564 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6502 06:48:53.240618 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6503 06:48:53.240671 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6504 06:48:53.240746 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6505 06:48:53.240799 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6506 06:48:53.240851 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6507 06:48:53.240904 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6508 06:48:53.240955 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6509 06:48:53.241008 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6510 06:48:53.241059 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6511 06:48:53.241111 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6512 06:48:53.241163 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6513 06:48:53.241215 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6514 06:48:53.241266 ==
6515 06:48:53.241318 Dram Type= 6, Freq= 0, CH_1, rank 0
6516 06:48:53.241371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6517 06:48:53.241423 ==
6518 06:48:53.241475 DQS Delay:
6519 06:48:53.241527 DQS0 = 43, DQS1 = 59
6520 06:48:53.241579 DQM Delay:
6521 06:48:53.241630 DQM0 = 6, DQM1 = 15
6522 06:48:53.241682 DQ Delay:
6523 06:48:53.241734 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6524 06:48:53.241786 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6525 06:48:53.241839 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6526 06:48:53.241891 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6527 06:48:53.241943
6528 06:48:53.241995
6529 06:48:53.242047 ==
6530 06:48:53.242098 Dram Type= 6, Freq= 0, CH_1, rank 0
6531 06:48:53.242151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6532 06:48:53.242203 ==
6533 06:48:53.242255
6534 06:48:53.242306
6535 06:48:53.242358 TX Vref Scan disable
6536 06:48:53.242410 == TX Byte 0 ==
6537 06:48:53.242462 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6538 06:48:53.242515 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6539 06:48:53.242567 == TX Byte 1 ==
6540 06:48:53.242619 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6541 06:48:53.242671 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6542 06:48:53.242724 ==
6543 06:48:53.242776 Dram Type= 6, Freq= 0, CH_1, rank 0
6544 06:48:53.242829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6545 06:48:53.242881 ==
6546 06:48:53.242933
6547 06:48:53.242984
6548 06:48:53.243035 TX Vref Scan disable
6549 06:48:53.243087 == TX Byte 0 ==
6550 06:48:53.243139 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6551 06:48:53.243192 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6552 06:48:53.243261 == TX Byte 1 ==
6553 06:48:53.243328 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6554 06:48:53.243380 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6555 06:48:53.243432
6556 06:48:53.243484 [DATLAT]
6557 06:48:53.243553 Freq=400, CH1 RK0
6558 06:48:53.243637
6559 06:48:53.243710 DATLAT Default: 0xf
6560 06:48:53.243793 0, 0xFFFF, sum = 0
6561 06:48:53.243878 1, 0xFFFF, sum = 0
6562 06:48:53.243962 2, 0xFFFF, sum = 0
6563 06:48:53.244047 3, 0xFFFF, sum = 0
6564 06:48:53.244130 4, 0xFFFF, sum = 0
6565 06:48:53.244214 5, 0xFFFF, sum = 0
6566 06:48:53.244298 6, 0xFFFF, sum = 0
6567 06:48:53.244380 7, 0xFFFF, sum = 0
6568 06:48:53.244462 8, 0xFFFF, sum = 0
6569 06:48:53.244545 9, 0xFFFF, sum = 0
6570 06:48:53.244628 10, 0xFFFF, sum = 0
6571 06:48:53.244715 11, 0xFFFF, sum = 0
6572 06:48:53.244797 12, 0x0, sum = 1
6573 06:48:53.244875 13, 0x0, sum = 2
6574 06:48:53.244953 14, 0x0, sum = 3
6575 06:48:53.245030 15, 0x0, sum = 4
6576 06:48:53.245107 best_step = 13
6577 06:48:53.245181
6578 06:48:53.245255 ==
6579 06:48:53.245340 Dram Type= 6, Freq= 0, CH_1, rank 0
6580 06:48:53.245462 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6581 06:48:53.245520 ==
6582 06:48:53.245576 RX Vref Scan: 1
6583 06:48:53.245632
6584 06:48:53.245687 RX Vref 0 -> 0, step: 1
6585 06:48:53.245742
6586 06:48:53.246033 RX Delay -359 -> 252, step: 8
6587 06:48:53.246110
6588 06:48:53.246224 Set Vref, RX VrefLevel [Byte0]: 57
6589 06:48:53.246279 [Byte1]: 48
6590 06:48:53.246332
6591 06:48:53.246385 Final RX Vref Byte 0 = 57 to rank0
6592 06:48:53.246439 Final RX Vref Byte 1 = 48 to rank0
6593 06:48:53.246492 Final RX Vref Byte 0 = 57 to rank1
6594 06:48:53.246562 Final RX Vref Byte 1 = 48 to rank1==
6595 06:48:53.246678 Dram Type= 6, Freq= 0, CH_1, rank 0
6596 06:48:53.246762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6597 06:48:53.246829 ==
6598 06:48:53.246882 DQS Delay:
6599 06:48:53.246934 DQS0 = 48, DQS1 = 68
6600 06:48:53.246987 DQM Delay:
6601 06:48:53.247039 DQM0 = 7, DQM1 = 20
6602 06:48:53.247091 DQ Delay:
6603 06:48:53.247143 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6604 06:48:53.247195 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6605 06:48:53.247265 DQ8 =0, DQ9 =12, DQ10 =20, DQ11 =12
6606 06:48:53.247333 DQ12 =28, DQ13 =32, DQ14 =28, DQ15 =28
6607 06:48:53.247386
6608 06:48:53.247438
6609 06:48:53.247508 [DQSOSCAuto] RK0, (LSB)MR18= 0xd3d3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6610 06:48:53.247593 CH1 RK0: MR19=C0C, MR18=D3D3
6611 06:48:53.247660 CH1_RK0: MR19=0xC0C, MR18=0xD3D3, DQSOSC=383, MR23=63, INC=402, DEC=268
6612 06:48:53.247713 ==
6613 06:48:53.247766 Dram Type= 6, Freq= 0, CH_1, rank 1
6614 06:48:53.247835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6615 06:48:53.247902 ==
6616 06:48:53.247954 [Gating] SW mode calibration
6617 06:48:53.248007 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6618 06:48:53.248060 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6619 06:48:53.248113 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6620 06:48:53.248166 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6621 06:48:53.248235 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6622 06:48:53.248300 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6623 06:48:53.248353 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6624 06:48:53.248406 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6625 06:48:53.248458 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6626 06:48:53.248512 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6627 06:48:53.248565 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6628 06:48:53.248617 Total UI for P1: 0, mck2ui 16
6629 06:48:53.248670 best dqsien dly found for B0: ( 0, 10, 16)
6630 06:48:53.248765 Total UI for P1: 0, mck2ui 16
6631 06:48:53.248857 best dqsien dly found for B1: ( 0, 10, 16)
6632 06:48:53.248910 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6633 06:48:53.248962 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6634 06:48:53.249015
6635 06:48:53.249067 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6636 06:48:53.249120 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6637 06:48:53.249172 [Gating] SW calibration Done
6638 06:48:53.249224 ==
6639 06:48:53.249276 Dram Type= 6, Freq= 0, CH_1, rank 1
6640 06:48:53.249328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6641 06:48:53.249380 ==
6642 06:48:53.249432 RX Vref Scan: 0
6643 06:48:53.249484
6644 06:48:53.249536 RX Vref 0 -> 0, step: 1
6645 06:48:53.249589
6646 06:48:53.249641 RX Delay -410 -> 252, step: 16
6647 06:48:53.249693 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6648 06:48:53.249746 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6649 06:48:53.249798 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6650 06:48:53.249851 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6651 06:48:53.249903 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6652 06:48:53.249955 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6653 06:48:53.250007 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6654 06:48:53.250089 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6655 06:48:53.250141 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6656 06:48:53.250193 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6657 06:48:53.250245 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6658 06:48:53.250297 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6659 06:48:53.250349 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6660 06:48:53.250401 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6661 06:48:53.250453 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6662 06:48:53.250506 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6663 06:48:53.250559 ==
6664 06:48:53.250611 Dram Type= 6, Freq= 0, CH_1, rank 1
6665 06:48:53.250664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6666 06:48:53.250717 ==
6667 06:48:53.250768 DQS Delay:
6668 06:48:53.250820 DQS0 = 43, DQS1 = 59
6669 06:48:53.250872 DQM Delay:
6670 06:48:53.250923 DQM0 = 10, DQM1 = 17
6671 06:48:53.250975 DQ Delay:
6672 06:48:53.251026 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6673 06:48:53.251078 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6674 06:48:53.251130 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6675 06:48:53.251182 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6676 06:48:53.251234
6677 06:48:53.251286
6678 06:48:53.251337 ==
6679 06:48:53.251388 Dram Type= 6, Freq= 0, CH_1, rank 1
6680 06:48:53.251440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6681 06:48:53.251492 ==
6682 06:48:53.251544
6683 06:48:53.251595
6684 06:48:53.251647 TX Vref Scan disable
6685 06:48:53.251699 == TX Byte 0 ==
6686 06:48:53.251751 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6687 06:48:53.251803 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6688 06:48:53.251855 == TX Byte 1 ==
6689 06:48:53.251907 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6690 06:48:53.251959 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6691 06:48:53.252011 ==
6692 06:48:53.252064 Dram Type= 6, Freq= 0, CH_1, rank 1
6693 06:48:53.252116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6694 06:48:53.252168 ==
6695 06:48:53.252220
6696 06:48:53.252272
6697 06:48:53.252323 TX Vref Scan disable
6698 06:48:53.252375 == TX Byte 0 ==
6699 06:48:53.252427 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6700 06:48:53.252479 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6701 06:48:53.252531 == TX Byte 1 ==
6702 06:48:53.252583 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6703 06:48:53.252634 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6704 06:48:53.252686
6705 06:48:53.252774 [DATLAT]
6706 06:48:53.252827 Freq=400, CH1 RK1
6707 06:48:53.252880
6708 06:48:53.252931 DATLAT Default: 0xd
6709 06:48:53.252983 0, 0xFFFF, sum = 0
6710 06:48:53.253036 1, 0xFFFF, sum = 0
6711 06:48:53.253090 2, 0xFFFF, sum = 0
6712 06:48:53.253143 3, 0xFFFF, sum = 0
6713 06:48:53.253196 4, 0xFFFF, sum = 0
6714 06:48:53.253249 5, 0xFFFF, sum = 0
6715 06:48:53.253302 6, 0xFFFF, sum = 0
6716 06:48:53.253372 7, 0xFFFF, sum = 0
6717 06:48:53.253440 8, 0xFFFF, sum = 0
6718 06:48:53.253493 9, 0xFFFF, sum = 0
6719 06:48:53.253545 10, 0xFFFF, sum = 0
6720 06:48:53.253598 11, 0xFFFF, sum = 0
6721 06:48:53.253856 12, 0x0, sum = 1
6722 06:48:53.253920 13, 0x0, sum = 2
6723 06:48:53.253975 14, 0x0, sum = 3
6724 06:48:53.254029 15, 0x0, sum = 4
6725 06:48:53.254099 best_step = 13
6726 06:48:53.254153
6727 06:48:53.254221 ==
6728 06:48:53.254273 Dram Type= 6, Freq= 0, CH_1, rank 1
6729 06:48:53.254326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6730 06:48:53.254378 ==
6731 06:48:53.254431 RX Vref Scan: 0
6732 06:48:53.254483
6733 06:48:53.254535 RX Vref 0 -> 0, step: 1
6734 06:48:53.254605
6735 06:48:53.254658 RX Delay -359 -> 252, step: 8
6736 06:48:53.254712 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6737 06:48:53.254777 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6738 06:48:53.254830 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6739 06:48:53.254882 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6740 06:48:53.254934 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6741 06:48:53.254986 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6742 06:48:53.255038 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6743 06:48:53.255089 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6744 06:48:53.255142 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6745 06:48:53.255247 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6746 06:48:53.255315 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6747 06:48:53.255366 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6748 06:48:53.255420 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6749 06:48:53.255473 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6750 06:48:53.255526 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6751 06:48:53.255577 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6752 06:48:53.255629 ==
6753 06:48:53.255682 Dram Type= 6, Freq= 0, CH_1, rank 1
6754 06:48:53.255734 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6755 06:48:53.255786 ==
6756 06:48:53.255838 DQS Delay:
6757 06:48:53.255890 DQS0 = 48, DQS1 = 64
6758 06:48:53.255942 DQM Delay:
6759 06:48:53.255994 DQM0 = 9, DQM1 = 15
6760 06:48:53.256045 DQ Delay:
6761 06:48:53.256096 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6762 06:48:53.256149 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6763 06:48:53.256200 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6764 06:48:53.256252 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6765 06:48:53.256304
6766 06:48:53.256356
6767 06:48:53.256408 [DQSOSCAuto] RK1, (LSB)MR18= 0xb3b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6768 06:48:53.256461 CH1 RK1: MR19=C0C, MR18=B3B3
6769 06:48:53.256514 CH1_RK1: MR19=0xC0C, MR18=0xB3B3, DQSOSC=387, MR23=63, INC=394, DEC=262
6770 06:48:53.256567 [RxdqsGatingPostProcess] freq 400
6771 06:48:53.256619 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6772 06:48:53.256671 Pre-setting of DQS Precalculation
6773 06:48:53.256756 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6774 06:48:53.256823 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6775 06:48:53.256876 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6776 06:48:53.256929
6777 06:48:53.257013
6778 06:48:53.257065 [Calibration Summary] 800 Mbps
6779 06:48:53.257117 CH 0, Rank 0
6780 06:48:53.257170 SW Impedance : PASS
6781 06:48:53.257222 DUTY Scan : NO K
6782 06:48:53.257274 ZQ Calibration : PASS
6783 06:48:53.257326 Jitter Meter : NO K
6784 06:48:53.257378 CBT Training : PASS
6785 06:48:53.257430 Write leveling : PASS
6786 06:48:53.257482 RX DQS gating : PASS
6787 06:48:53.257535 RX DQ/DQS(RDDQC) : PASS
6788 06:48:53.257587 TX DQ/DQS : PASS
6789 06:48:53.257640 RX DATLAT : PASS
6790 06:48:53.257691 RX DQ/DQS(Engine): PASS
6791 06:48:53.257744 TX OE : NO K
6792 06:48:53.257796 All Pass.
6793 06:48:53.257848
6794 06:48:53.257900 CH 0, Rank 1
6795 06:48:53.257952 SW Impedance : PASS
6796 06:48:53.258004 DUTY Scan : NO K
6797 06:48:53.258056 ZQ Calibration : PASS
6798 06:48:53.258108 Jitter Meter : NO K
6799 06:48:53.258161 CBT Training : PASS
6800 06:48:53.258213 Write leveling : NO K
6801 06:48:53.258265 RX DQS gating : PASS
6802 06:48:53.258317 RX DQ/DQS(RDDQC) : PASS
6803 06:48:53.258369 TX DQ/DQS : PASS
6804 06:48:53.258421 RX DATLAT : PASS
6805 06:48:53.258473 RX DQ/DQS(Engine): PASS
6806 06:48:53.258524 TX OE : NO K
6807 06:48:53.258576 All Pass.
6808 06:48:53.258628
6809 06:48:53.258680 CH 1, Rank 0
6810 06:48:53.258733 SW Impedance : PASS
6811 06:48:53.258784 DUTY Scan : NO K
6812 06:48:53.258836 ZQ Calibration : PASS
6813 06:48:53.258888 Jitter Meter : NO K
6814 06:48:53.258940 CBT Training : PASS
6815 06:48:53.258992 Write leveling : PASS
6816 06:48:53.259044 RX DQS gating : PASS
6817 06:48:53.259097 RX DQ/DQS(RDDQC) : PASS
6818 06:48:53.259148 TX DQ/DQS : PASS
6819 06:48:53.259200 RX DATLAT : PASS
6820 06:48:53.259251 RX DQ/DQS(Engine): PASS
6821 06:48:53.259303 TX OE : NO K
6822 06:48:53.259355 All Pass.
6823 06:48:53.259407
6824 06:48:53.259458 CH 1, Rank 1
6825 06:48:53.259510 SW Impedance : PASS
6826 06:48:53.259562 DUTY Scan : NO K
6827 06:48:53.259613 ZQ Calibration : PASS
6828 06:48:53.259665 Jitter Meter : NO K
6829 06:48:53.259717 CBT Training : PASS
6830 06:48:53.259768 Write leveling : NO K
6831 06:48:53.259821 RX DQS gating : PASS
6832 06:48:53.259873 RX DQ/DQS(RDDQC) : PASS
6833 06:48:53.259925 TX DQ/DQS : PASS
6834 06:48:53.259978 RX DATLAT : PASS
6835 06:48:53.260030 RX DQ/DQS(Engine): PASS
6836 06:48:53.260082 TX OE : NO K
6837 06:48:53.260134 All Pass.
6838 06:48:53.260186
6839 06:48:53.260238 DramC Write-DBI off
6840 06:48:53.260290 PER_BANK_REFRESH: Hybrid Mode
6841 06:48:53.260342 TX_TRACKING: ON
6842 06:48:53.260394 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6843 06:48:53.260447 [FAST_K] Save calibration result to emmc
6844 06:48:53.260499 dramc_set_vcore_voltage set vcore to 725000
6845 06:48:53.260552 Read voltage for 1600, 0
6846 06:48:53.260604 Vio18 = 0
6847 06:48:53.260656 Vcore = 725000
6848 06:48:53.260727 Vdram = 0
6849 06:48:53.260794 Vddq = 0
6850 06:48:53.260846 Vmddr = 0
6851 06:48:53.260897 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6852 06:48:53.260982 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6853 06:48:53.261034 MEM_TYPE=3, freq_sel=13
6854 06:48:53.261087 sv_algorithm_assistance_LP4_3733
6855 06:48:53.261139 ============ PULL DRAM RESETB DOWN ============
6856 06:48:53.261267 ========== PULL DRAM RESETB DOWN end =========
6857 06:48:53.261394 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6858 06:48:53.261450 ===================================
6859 06:48:53.261503 LPDDR4 DRAM CONFIGURATION
6860 06:48:53.261555 ===================================
6861 06:48:53.261608 EX_ROW_EN[0] = 0x0
6862 06:48:53.261660 EX_ROW_EN[1] = 0x0
6863 06:48:53.261908 LP4Y_EN = 0x0
6864 06:48:53.261968 WORK_FSP = 0x1
6865 06:48:53.262022 WL = 0x5
6866 06:48:53.262075 RL = 0x5
6867 06:48:53.262128 BL = 0x2
6868 06:48:53.262180 RPST = 0x0
6869 06:48:53.262232 RD_PRE = 0x0
6870 06:48:53.262284 WR_PRE = 0x1
6871 06:48:53.262336 WR_PST = 0x1
6872 06:48:53.262389 DBI_WR = 0x0
6873 06:48:53.262441 DBI_RD = 0x0
6874 06:48:53.262494 OTF = 0x1
6875 06:48:53.262546 ===================================
6876 06:48:53.262599 ===================================
6877 06:48:53.262652 ANA top config
6878 06:48:53.262703 ===================================
6879 06:48:53.262755 DLL_ASYNC_EN = 0
6880 06:48:53.262807 ALL_SLAVE_EN = 0
6881 06:48:53.262859 NEW_RANK_MODE = 1
6882 06:48:53.262911 DLL_IDLE_MODE = 1
6883 06:48:53.262963 LP45_APHY_COMB_EN = 1
6884 06:48:53.263016 TX_ODT_DIS = 0
6885 06:48:53.263068 NEW_8X_MODE = 1
6886 06:48:53.263121 ===================================
6887 06:48:53.263173 ===================================
6888 06:48:53.263225 data_rate = 3200
6889 06:48:53.263278 CKR = 1
6890 06:48:53.263330 DQ_P2S_RATIO = 8
6891 06:48:53.263382 ===================================
6892 06:48:53.263434 CA_P2S_RATIO = 8
6893 06:48:53.263485 DQ_CA_OPEN = 0
6894 06:48:53.263537 DQ_SEMI_OPEN = 0
6895 06:48:53.263588 CA_SEMI_OPEN = 0
6896 06:48:53.263640 CA_FULL_RATE = 0
6897 06:48:53.263692 DQ_CKDIV4_EN = 0
6898 06:48:53.263744 CA_CKDIV4_EN = 0
6899 06:48:53.263795 CA_PREDIV_EN = 0
6900 06:48:53.263847 PH8_DLY = 12
6901 06:48:53.263899 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6902 06:48:53.263951 DQ_AAMCK_DIV = 4
6903 06:48:53.264002 CA_AAMCK_DIV = 4
6904 06:48:53.264054 CA_ADMCK_DIV = 4
6905 06:48:53.264106 DQ_TRACK_CA_EN = 0
6906 06:48:53.264158 CA_PICK = 1600
6907 06:48:53.264210 CA_MCKIO = 1600
6908 06:48:53.264261 MCKIO_SEMI = 0
6909 06:48:53.264313 PLL_FREQ = 3068
6910 06:48:53.264365 DQ_UI_PI_RATIO = 32
6911 06:48:53.264418 CA_UI_PI_RATIO = 0
6912 06:48:53.264470 ===================================
6913 06:48:53.264522 ===================================
6914 06:48:53.264574 memory_type:LPDDR4
6915 06:48:53.264627 GP_NUM : 10
6916 06:48:53.264678 SRAM_EN : 1
6917 06:48:53.264773 MD32_EN : 0
6918 06:48:53.264826 ===================================
6919 06:48:53.264879 [ANA_INIT] >>>>>>>>>>>>>>
6920 06:48:53.264931 <<<<<< [CONFIGURE PHASE]: ANA_TX
6921 06:48:53.264983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6922 06:48:53.265036 ===================================
6923 06:48:53.265088 data_rate = 3200,PCW = 0X7600
6924 06:48:53.265141 ===================================
6925 06:48:53.265193 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6926 06:48:53.265246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6927 06:48:53.266720 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6928 06:48:53.270288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6929 06:48:53.274205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6930 06:48:53.276443 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6931 06:48:53.280039 [ANA_INIT] flow start
6932 06:48:53.283299 [ANA_INIT] PLL >>>>>>>>
6933 06:48:53.283380 [ANA_INIT] PLL <<<<<<<<
6934 06:48:53.286675 [ANA_INIT] MIDPI >>>>>>>>
6935 06:48:53.290003 [ANA_INIT] MIDPI <<<<<<<<
6936 06:48:53.290083 [ANA_INIT] DLL >>>>>>>>
6937 06:48:53.293018 [ANA_INIT] DLL <<<<<<<<
6938 06:48:53.296266 [ANA_INIT] flow end
6939 06:48:53.299868 ============ LP4 DIFF to SE enter ============
6940 06:48:53.303201 ============ LP4 DIFF to SE exit ============
6941 06:48:53.306436 [ANA_INIT] <<<<<<<<<<<<<
6942 06:48:53.309474 [Flow] Enable top DCM control >>>>>
6943 06:48:53.313069 [Flow] Enable top DCM control <<<<<
6944 06:48:53.317170 Enable DLL master slave shuffle
6945 06:48:53.319551 ==============================================================
6946 06:48:53.322906 Gating Mode config
6947 06:48:53.330024 ==============================================================
6948 06:48:53.330109 Config description:
6949 06:48:53.339925 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6950 06:48:53.346275 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6951 06:48:53.352899 SELPH_MODE 0: By rank 1: By Phase
6952 06:48:53.356531 ==============================================================
6953 06:48:53.359056 GAT_TRACK_EN = 1
6954 06:48:53.362572 RX_GATING_MODE = 2
6955 06:48:53.366270 RX_GATING_TRACK_MODE = 2
6956 06:48:53.369004 SELPH_MODE = 1
6957 06:48:53.372852 PICG_EARLY_EN = 1
6958 06:48:53.375685 VALID_LAT_VALUE = 1
6959 06:48:53.379435 ==============================================================
6960 06:48:53.382341 Enter into Gating configuration >>>>
6961 06:48:53.385727 Exit from Gating configuration <<<<
6962 06:48:53.388751 Enter into DVFS_PRE_config >>>>>
6963 06:48:53.402102 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6964 06:48:53.405502 Exit from DVFS_PRE_config <<<<<
6965 06:48:53.408800 Enter into PICG configuration >>>>
6966 06:48:53.411973 Exit from PICG configuration <<<<
6967 06:48:53.412053 [RX_INPUT] configuration >>>>>
6968 06:48:53.415519 [RX_INPUT] configuration <<<<<
6969 06:48:53.422451 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6970 06:48:53.425527 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6971 06:48:53.432292 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6972 06:48:53.438604 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6973 06:48:53.445504 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6974 06:48:53.451574 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6975 06:48:53.455065 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6976 06:48:53.458835 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6977 06:48:53.466084 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6978 06:48:53.468305 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6979 06:48:53.472114 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6980 06:48:53.474998 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6981 06:48:53.478061 ===================================
6982 06:48:53.481931 LPDDR4 DRAM CONFIGURATION
6983 06:48:53.527575 ===================================
6984 06:48:53.527662 EX_ROW_EN[0] = 0x0
6985 06:48:53.527727 EX_ROW_EN[1] = 0x0
6986 06:48:53.527787 LP4Y_EN = 0x0
6987 06:48:53.527844 WORK_FSP = 0x1
6988 06:48:53.527901 WL = 0x5
6989 06:48:53.527957 RL = 0x5
6990 06:48:53.528011 BL = 0x2
6991 06:48:53.528065 RPST = 0x0
6992 06:48:53.528119 RD_PRE = 0x0
6993 06:48:53.528172 WR_PRE = 0x1
6994 06:48:53.528225 WR_PST = 0x1
6995 06:48:53.528277 DBI_WR = 0x0
6996 06:48:53.528330 DBI_RD = 0x0
6997 06:48:53.528383 OTF = 0x1
6998 06:48:53.528436 ===================================
6999 06:48:53.528489 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7000 06:48:53.528542 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7001 06:48:53.528595 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7002 06:48:53.528648 ===================================
7003 06:48:53.531365 LPDDR4 DRAM CONFIGURATION
7004 06:48:53.535068 ===================================
7005 06:48:53.537985 EX_ROW_EN[0] = 0x10
7006 06:48:53.538066 EX_ROW_EN[1] = 0x0
7007 06:48:53.540855 LP4Y_EN = 0x0
7008 06:48:53.540936 WORK_FSP = 0x1
7009 06:48:53.544048 WL = 0x5
7010 06:48:53.544129 RL = 0x5
7011 06:48:53.547745 BL = 0x2
7012 06:48:53.547825 RPST = 0x0
7013 06:48:53.550976 RD_PRE = 0x0
7014 06:48:53.554457 WR_PRE = 0x1
7015 06:48:53.554538 WR_PST = 0x1
7016 06:48:53.558472 DBI_WR = 0x0
7017 06:48:53.558553 DBI_RD = 0x0
7018 06:48:53.561096 OTF = 0x1
7019 06:48:53.563929 ===================================
7020 06:48:53.567262 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7021 06:48:53.570553 ==
7022 06:48:53.574334 Dram Type= 6, Freq= 0, CH_0, rank 0
7023 06:48:53.577724 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7024 06:48:53.577806 ==
7025 06:48:53.580633 [Duty_Offset_Calibration]
7026 06:48:53.580784 B0:0 B1:2 CA:1
7027 06:48:53.580853
7028 06:48:53.584223 [DutyScan_Calibration_Flow] k_type=0
7029 06:48:53.593680
7030 06:48:53.593776 ==CLK 0==
7031 06:48:53.597374 Final CLK duty delay cell = 0
7032 06:48:53.600537 [0] MAX Duty = 5187%(X100), DQS PI = 24
7033 06:48:53.603976 [0] MIN Duty = 4969%(X100), DQS PI = 36
7034 06:48:53.607313 [0] AVG Duty = 5078%(X100)
7035 06:48:53.607386
7036 06:48:53.610680 CH0 CLK Duty spec in!! Max-Min= 218%
7037 06:48:53.613814 [DutyScan_Calibration_Flow] ====Done====
7038 06:48:53.613894
7039 06:48:53.616975 [DutyScan_Calibration_Flow] k_type=1
7040 06:48:53.634349
7041 06:48:53.634429 ==DQS 0 ==
7042 06:48:53.637248 Final DQS duty delay cell = 0
7043 06:48:53.641684 [0] MAX Duty = 5156%(X100), DQS PI = 34
7044 06:48:53.644412 [0] MIN Duty = 5031%(X100), DQS PI = 8
7045 06:48:53.644492 [0] AVG Duty = 5093%(X100)
7046 06:48:53.647094
7047 06:48:53.647182 ==DQS 1 ==
7048 06:48:53.650576 Final DQS duty delay cell = 0
7049 06:48:53.653663 [0] MAX Duty = 5031%(X100), DQS PI = 6
7050 06:48:53.657272 [0] MIN Duty = 4876%(X100), DQS PI = 18
7051 06:48:53.660593 [0] AVG Duty = 4953%(X100)
7052 06:48:53.660695
7053 06:48:53.663644 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7054 06:48:53.663747
7055 06:48:53.666857 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7056 06:48:53.670191 [DutyScan_Calibration_Flow] ====Done====
7057 06:48:53.670264
7058 06:48:53.673750 [DutyScan_Calibration_Flow] k_type=3
7059 06:48:53.691016
7060 06:48:53.691117 ==DQM 0 ==
7061 06:48:53.694129 Final DQM duty delay cell = 0
7062 06:48:53.697629 [0] MAX Duty = 5187%(X100), DQS PI = 22
7063 06:48:53.701400 [0] MIN Duty = 4907%(X100), DQS PI = 56
7064 06:48:53.704413 [0] AVG Duty = 5047%(X100)
7065 06:48:53.704515
7066 06:48:53.704604 ==DQM 1 ==
7067 06:48:53.708100 Final DQM duty delay cell = 0
7068 06:48:53.710850 [0] MAX Duty = 5031%(X100), DQS PI = 52
7069 06:48:53.714411 [0] MIN Duty = 4782%(X100), DQS PI = 14
7070 06:48:53.718151 [0] AVG Duty = 4906%(X100)
7071 06:48:53.718232
7072 06:48:53.721010 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7073 06:48:53.721092
7074 06:48:53.724322 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7075 06:48:53.728435 [DutyScan_Calibration_Flow] ====Done====
7076 06:48:53.728516
7077 06:48:53.730554 [DutyScan_Calibration_Flow] k_type=2
7078 06:48:53.747493
7079 06:48:53.747574 ==DQ 0 ==
7080 06:48:53.750976 Final DQ duty delay cell = 0
7081 06:48:53.754232 [0] MAX Duty = 5218%(X100), DQS PI = 18
7082 06:48:53.757522 [0] MIN Duty = 4969%(X100), DQS PI = 54
7083 06:48:53.757604 [0] AVG Duty = 5093%(X100)
7084 06:48:53.760547
7085 06:48:53.760628 ==DQ 1 ==
7086 06:48:53.764126 Final DQ duty delay cell = -4
7087 06:48:53.767173 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7088 06:48:53.771005 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7089 06:48:53.773740 [-4] AVG Duty = 4953%(X100)
7090 06:48:53.773820
7091 06:48:53.777217 CH0 DQ 0 Duty spec in!! Max-Min= 249%
7092 06:48:53.777298
7093 06:48:53.780309 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7094 06:48:53.784025 [DutyScan_Calibration_Flow] ====Done====
7095 06:48:53.784107 ==
7096 06:48:53.788415 Dram Type= 6, Freq= 0, CH_1, rank 0
7097 06:48:53.790749 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7098 06:48:53.790830 ==
7099 06:48:53.794350 [Duty_Offset_Calibration]
7100 06:48:53.794431 B0:0 B1:5 CA:-5
7101 06:48:53.794495
7102 06:48:53.797031 [DutyScan_Calibration_Flow] k_type=0
7103 06:48:53.808403
7104 06:48:53.808484 ==CLK 0==
7105 06:48:53.811351 Final CLK duty delay cell = 0
7106 06:48:53.814359 [0] MAX Duty = 5156%(X100), DQS PI = 22
7107 06:48:53.817772 [0] MIN Duty = 4875%(X100), DQS PI = 50
7108 06:48:53.817853 [0] AVG Duty = 5015%(X100)
7109 06:48:53.821334
7110 06:48:53.825102 CH1 CLK Duty spec in!! Max-Min= 281%
7111 06:48:53.828429 [DutyScan_Calibration_Flow] ====Done====
7112 06:48:53.828510
7113 06:48:53.831187 [DutyScan_Calibration_Flow] k_type=1
7114 06:48:53.847042
7115 06:48:53.847123 ==DQS 0 ==
7116 06:48:53.850621 Final DQS duty delay cell = 0
7117 06:48:53.853613 [0] MAX Duty = 5156%(X100), DQS PI = 18
7118 06:48:53.856672 [0] MIN Duty = 4876%(X100), DQS PI = 42
7119 06:48:53.860897 [0] AVG Duty = 5016%(X100)
7120 06:48:53.860978
7121 06:48:53.861043 ==DQS 1 ==
7122 06:48:53.863217 Final DQS duty delay cell = -4
7123 06:48:53.866474 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7124 06:48:53.870364 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7125 06:48:53.873191 [-4] AVG Duty = 4922%(X100)
7126 06:48:53.873273
7127 06:48:53.876390 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7128 06:48:53.876472
7129 06:48:53.880472 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7130 06:48:53.883650 [DutyScan_Calibration_Flow] ====Done====
7131 06:48:53.883731
7132 06:48:53.886389 [DutyScan_Calibration_Flow] k_type=3
7133 06:48:53.902487
7134 06:48:53.902568 ==DQM 0 ==
7135 06:48:53.905807 Final DQM duty delay cell = -4
7136 06:48:53.908905 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7137 06:48:53.912413 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7138 06:48:53.915631 [-4] AVG Duty = 4937%(X100)
7139 06:48:53.915712
7140 06:48:53.915775 ==DQM 1 ==
7141 06:48:53.919070 Final DQM duty delay cell = -4
7142 06:48:53.922237 [-4] MAX Duty = 5062%(X100), DQS PI = 0
7143 06:48:53.925647 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7144 06:48:53.928910 [-4] AVG Duty = 4984%(X100)
7145 06:48:53.928992
7146 06:48:53.932346 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7147 06:48:53.932427
7148 06:48:53.935484 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7149 06:48:53.938985 [DutyScan_Calibration_Flow] ====Done====
7150 06:48:53.939066
7151 06:48:53.942497 [DutyScan_Calibration_Flow] k_type=2
7152 06:48:53.959863
7153 06:48:53.959943 ==DQ 0 ==
7154 06:48:53.963372 Final DQ duty delay cell = 0
7155 06:48:53.967129 [0] MAX Duty = 5093%(X100), DQS PI = 4
7156 06:48:53.970151 [0] MIN Duty = 4938%(X100), DQS PI = 46
7157 06:48:53.970228 [0] AVG Duty = 5015%(X100)
7158 06:48:53.973263
7159 06:48:53.973340 ==DQ 1 ==
7160 06:48:53.976841 Final DQ duty delay cell = 0
7161 06:48:53.980381 [0] MAX Duty = 5062%(X100), DQS PI = 6
7162 06:48:53.983145 [0] MIN Duty = 4875%(X100), DQS PI = 30
7163 06:48:53.983222 [0] AVG Duty = 4968%(X100)
7164 06:48:53.983286
7165 06:48:53.986595 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7166 06:48:53.986680
7167 06:48:53.993356 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7168 06:48:53.996740 [DutyScan_Calibration_Flow] ====Done====
7169 06:48:53.999912 nWR fixed to 30
7170 06:48:53.999998 [ModeRegInit_LP4] CH0 RK0
7171 06:48:54.003664 [ModeRegInit_LP4] CH0 RK1
7172 06:48:54.007187 [ModeRegInit_LP4] CH1 RK0
7173 06:48:54.010611 [ModeRegInit_LP4] CH1 RK1
7174 06:48:54.010692 match AC timing 4
7175 06:48:54.013499 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7176 06:48:54.019782 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7177 06:48:54.024344 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7178 06:48:54.026823 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7179 06:48:54.033055 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7180 06:48:54.033135 [MiockJmeterHQA]
7181 06:48:54.033199
7182 06:48:54.036134 [DramcMiockJmeter] u1RxGatingPI = 0
7183 06:48:54.039476 0 : 4252, 4027
7184 06:48:54.039558 4 : 4253, 4027
7185 06:48:54.039623 8 : 4252, 4027
7186 06:48:54.043214 12 : 4255, 4030
7187 06:48:54.043296 16 : 4253, 4026
7188 06:48:54.046195 20 : 4363, 4138
7189 06:48:54.046277 24 : 4362, 4137
7190 06:48:54.049431 28 : 4252, 4027
7191 06:48:54.049513 32 : 4252, 4027
7192 06:48:54.053209 36 : 4253, 4026
7193 06:48:54.053291 40 : 4252, 4027
7194 06:48:54.053356 44 : 4254, 4029
7195 06:48:54.056185 48 : 4363, 4137
7196 06:48:54.056277 52 : 4252, 4026
7197 06:48:54.059361 56 : 4253, 4026
7198 06:48:54.059443 60 : 4253, 4027
7199 06:48:54.062953 64 : 4255, 4029
7200 06:48:54.063035 68 : 4250, 4027
7201 06:48:54.065813 72 : 4363, 4140
7202 06:48:54.065894 76 : 4360, 4138
7203 06:48:54.065959 80 : 4250, 4027
7204 06:48:54.069673 84 : 4249, 4027
7205 06:48:54.069755 88 : 4250, 4026
7206 06:48:54.072742 92 : 4250, 4027
7207 06:48:54.072838 96 : 4252, 4029
7208 06:48:54.076290 100 : 4361, 2222
7209 06:48:54.076382 104 : 4250, 0
7210 06:48:54.079012 108 : 4250, 0
7211 06:48:54.079094 112 : 4252, 0
7212 06:48:54.079158 116 : 4252, 0
7213 06:48:54.082364 120 : 4361, 0
7214 06:48:54.082446 124 : 4360, 0
7215 06:48:54.082512 128 : 4249, 0
7216 06:48:54.085932 132 : 4250, 0
7217 06:48:54.086014 136 : 4250, 0
7218 06:48:54.089225 140 : 4249, 0
7219 06:48:54.089307 144 : 4250, 0
7220 06:48:54.089372 148 : 4250, 0
7221 06:48:54.092675 152 : 4252, 0
7222 06:48:54.092821 156 : 4250, 0
7223 06:48:54.096147 160 : 4250, 0
7224 06:48:54.096232 164 : 4252, 0
7225 06:48:54.096329 168 : 4360, 0
7226 06:48:54.099158 172 : 4361, 0
7227 06:48:54.099239 176 : 4363, 0
7228 06:48:54.102692 180 : 4249, 0
7229 06:48:54.102774 184 : 4250, 0
7230 06:48:54.102838 188 : 4250, 0
7231 06:48:54.106130 192 : 4249, 0
7232 06:48:54.106216 196 : 4250, 0
7233 06:48:54.106293 200 : 4250, 0
7234 06:48:54.108835 204 : 4252, 0
7235 06:48:54.108917 208 : 4250, 0
7236 06:48:54.112337 212 : 4250, 0
7237 06:48:54.112450 216 : 4253, 0
7238 06:48:54.115793 220 : 4249, 681
7239 06:48:54.115875 224 : 4360, 4071
7240 06:48:54.115940 228 : 4250, 4026
7241 06:48:54.118789 232 : 4250, 4027
7242 06:48:54.118870 236 : 4249, 4027
7243 06:48:54.122873 240 : 4252, 4029
7244 06:48:54.122956 244 : 4250, 4026
7245 06:48:54.125593 248 : 4250, 4027
7246 06:48:54.125675 252 : 4360, 4138
7247 06:48:54.128753 256 : 4250, 4027
7248 06:48:54.128836 260 : 4250, 4026
7249 06:48:54.132091 264 : 4360, 4138
7250 06:48:54.132172 268 : 4250, 4027
7251 06:48:54.135731 272 : 4250, 4027
7252 06:48:54.135812 276 : 4363, 4140
7253 06:48:54.138722 280 : 4250, 4026
7254 06:48:54.138804 284 : 4250, 4027
7255 06:48:54.142115 288 : 4249, 4027
7256 06:48:54.142197 292 : 4252, 4029
7257 06:48:54.142261 296 : 4250, 4026
7258 06:48:54.145455 300 : 4250, 4027
7259 06:48:54.145537 304 : 4360, 4138
7260 06:48:54.148317 308 : 4250, 4027
7261 06:48:54.148399 312 : 4250, 4026
7262 06:48:54.151754 316 : 4361, 4137
7263 06:48:54.151835 320 : 4250, 4027
7264 06:48:54.155113 324 : 4249, 4027
7265 06:48:54.155194 328 : 4363, 4140
7266 06:48:54.158420 332 : 4250, 4026
7267 06:48:54.158502 336 : 4250, 3894
7268 06:48:54.161929 340 : 4249, 2092
7269 06:48:54.162012
7270 06:48:54.162075 MIOCK jitter meter ch=0
7271 06:48:54.162134
7272 06:48:54.165889 1T = (340-104) = 236 dly cells
7273 06:48:54.171711 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7274 06:48:54.171790 ==
7275 06:48:54.175031 Dram Type= 6, Freq= 0, CH_0, rank 0
7276 06:48:54.178480 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7277 06:48:54.178563 ==
7278 06:48:54.185266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7279 06:48:54.189059 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7280 06:48:54.191354 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7281 06:48:54.198268 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7282 06:48:54.207149 [CA 0] Center 41 (11~72) winsize 62
7283 06:48:54.210614 [CA 1] Center 41 (11~72) winsize 62
7284 06:48:54.214325 [CA 2] Center 37 (7~68) winsize 62
7285 06:48:54.217501 [CA 3] Center 37 (7~67) winsize 61
7286 06:48:54.220775 [CA 4] Center 35 (5~66) winsize 62
7287 06:48:54.223873 [CA 5] Center 35 (5~65) winsize 61
7288 06:48:54.223952
7289 06:48:54.227404 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7290 06:48:54.227477
7291 06:48:54.230173 [CATrainingPosCal] consider 1 rank data
7292 06:48:54.233978 u2DelayCellTimex100 = 275/100 ps
7293 06:48:54.236861 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7294 06:48:54.243523 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7295 06:48:54.247286 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7296 06:48:54.250213 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7297 06:48:54.254090 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7298 06:48:54.257111 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7299 06:48:54.257193
7300 06:48:54.259942 CA PerBit enable=1, Macro0, CA PI delay=35
7301 06:48:54.260022
7302 06:48:54.263376 [CBTSetCACLKResult] CA Dly = 35
7303 06:48:54.266763 CS Dly: 11 (0~42)
7304 06:48:54.270138 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7305 06:48:54.274506 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7306 06:48:54.274593 ==
7307 06:48:54.277035 Dram Type= 6, Freq= 0, CH_0, rank 1
7308 06:48:54.280277 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7309 06:48:54.283594 ==
7310 06:48:54.286728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7311 06:48:54.289872 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7312 06:48:54.296990 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7313 06:48:54.303022 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7314 06:48:54.310732 [CA 0] Center 42 (12~73) winsize 62
7315 06:48:54.312904 [CA 1] Center 41 (11~72) winsize 62
7316 06:48:54.316404 [CA 2] Center 38 (9~68) winsize 60
7317 06:48:54.320062 [CA 3] Center 37 (7~67) winsize 61
7318 06:48:54.322935 [CA 4] Center 35 (5~65) winsize 61
7319 06:48:54.326410 [CA 5] Center 35 (5~65) winsize 61
7320 06:48:54.326497
7321 06:48:54.329638 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7322 06:48:54.329719
7323 06:48:54.332806 [CATrainingPosCal] consider 2 rank data
7324 06:48:54.336161 u2DelayCellTimex100 = 275/100 ps
7325 06:48:54.340133 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7326 06:48:54.346319 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7327 06:48:54.349769 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7328 06:48:54.353075 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7329 06:48:54.355974 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7330 06:48:54.359740 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7331 06:48:54.359820
7332 06:48:54.362693 CA PerBit enable=1, Macro0, CA PI delay=35
7333 06:48:54.362774
7334 06:48:54.365956 [CBTSetCACLKResult] CA Dly = 35
7335 06:48:54.369271 CS Dly: 11 (0~43)
7336 06:48:54.372919 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7337 06:48:54.375947 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7338 06:48:54.376028
7339 06:48:54.379710 ----->DramcWriteLeveling(PI) begin...
7340 06:48:54.379791 ==
7341 06:48:54.382583 Dram Type= 6, Freq= 0, CH_0, rank 0
7342 06:48:54.389259 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7343 06:48:54.389340 ==
7344 06:48:54.392532 Write leveling (Byte 0): 29 => 29
7345 06:48:54.395915 Write leveling (Byte 1): 25 => 25
7346 06:48:54.395996 DramcWriteLeveling(PI) end<-----
7347 06:48:54.396060
7348 06:48:54.399162 ==
7349 06:48:54.403073 Dram Type= 6, Freq= 0, CH_0, rank 0
7350 06:48:54.406358 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7351 06:48:54.406454 ==
7352 06:48:54.409730 [Gating] SW mode calibration
7353 06:48:54.416078 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7354 06:48:54.419082 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7355 06:48:54.425637 0 12 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7356 06:48:54.429027 0 12 4 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
7357 06:48:54.433066 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7358 06:48:54.438642 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7359 06:48:54.442098 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7360 06:48:54.447492 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7361 06:48:54.452727 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7362 06:48:54.455219 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7363 06:48:54.458692 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
7364 06:48:54.467227 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
7365 06:48:54.468472 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7366 06:48:54.471931 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7367 06:48:54.478427 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7368 06:48:54.481742 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7369 06:48:54.485082 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7370 06:48:54.491685 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7371 06:48:54.494740 0 14 0 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7372 06:48:54.498226 0 14 4 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7373 06:48:54.504918 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7374 06:48:54.508664 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7375 06:48:54.511604 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7376 06:48:54.518051 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7377 06:48:54.521146 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7378 06:48:54.524501 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7379 06:48:54.531009 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7380 06:48:54.534962 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7381 06:48:54.538243 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7382 06:48:54.545284 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7383 06:48:54.547626 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7384 06:48:54.551615 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7385 06:48:54.557534 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7386 06:48:54.560876 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7387 06:48:54.564244 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7388 06:48:54.571135 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7389 06:48:54.573835 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7390 06:48:54.577467 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7391 06:48:54.584825 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7392 06:48:54.587101 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7393 06:48:54.590732 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7394 06:48:54.597767 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7395 06:48:54.600949 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7396 06:48:54.604011 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7397 06:48:54.611288 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7398 06:48:54.611359 Total UI for P1: 0, mck2ui 16
7399 06:48:54.616985 best dqsien dly found for B0: ( 1, 1, 2)
7400 06:48:54.617061 Total UI for P1: 0, mck2ui 16
7401 06:48:54.623417 best dqsien dly found for B1: ( 1, 1, 4)
7402 06:48:54.627508 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7403 06:48:54.630557 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7404 06:48:54.630627
7405 06:48:54.633820 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7406 06:48:54.636699 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7407 06:48:54.641157 [Gating] SW calibration Done
7408 06:48:54.641240 ==
7409 06:48:54.643733 Dram Type= 6, Freq= 0, CH_0, rank 0
7410 06:48:54.646711 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7411 06:48:54.646792 ==
7412 06:48:54.650292 RX Vref Scan: 0
7413 06:48:54.650373
7414 06:48:54.650438 RX Vref 0 -> 0, step: 1
7415 06:48:54.650498
7416 06:48:54.654013 RX Delay 0 -> 252, step: 8
7417 06:48:54.656698 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7418 06:48:54.660150 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7419 06:48:54.667250 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7420 06:48:54.670189 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7421 06:48:54.673373 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7422 06:48:54.676230 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7423 06:48:54.680267 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7424 06:48:54.686410 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7425 06:48:54.689724 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7426 06:48:54.693025 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7427 06:48:54.696212 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7428 06:48:54.700100 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7429 06:48:54.706349 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7430 06:48:54.711292 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7431 06:48:54.712677 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7432 06:48:54.716149 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7433 06:48:54.719875 ==
7434 06:48:54.719956 Dram Type= 6, Freq= 0, CH_0, rank 0
7435 06:48:54.726954 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7436 06:48:54.727036 ==
7437 06:48:54.727101 DQS Delay:
7438 06:48:54.729341 DQS0 = 0, DQS1 = 0
7439 06:48:54.729422 DQM Delay:
7440 06:48:54.732912 DQM0 = 130, DQM1 = 124
7441 06:48:54.732994 DQ Delay:
7442 06:48:54.736728 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7443 06:48:54.739377 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7444 06:48:54.742865 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7445 06:48:54.746239 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7446 06:48:54.746321
7447 06:48:54.746385
7448 06:48:54.746445 ==
7449 06:48:54.749291 Dram Type= 6, Freq= 0, CH_0, rank 0
7450 06:48:54.755678 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7451 06:48:54.755760 ==
7452 06:48:54.755825
7453 06:48:54.755885
7454 06:48:54.755943 TX Vref Scan disable
7455 06:48:54.759622 == TX Byte 0 ==
7456 06:48:54.762480 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7457 06:48:54.769398 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7458 06:48:54.769480 == TX Byte 1 ==
7459 06:48:54.772625 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7460 06:48:54.779095 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7461 06:48:54.779177 ==
7462 06:48:54.782554 Dram Type= 6, Freq= 0, CH_0, rank 0
7463 06:48:54.786027 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7464 06:48:54.786108 ==
7465 06:48:54.798953
7466 06:48:54.802204 TX Vref early break, caculate TX vref
7467 06:48:54.805183 TX Vref=16, minBit 10, minWin=21, winSum=372
7468 06:48:54.808592 TX Vref=18, minBit 10, minWin=21, winSum=380
7469 06:48:54.812294 TX Vref=20, minBit 8, minWin=23, winSum=389
7470 06:48:54.816053 TX Vref=22, minBit 10, minWin=23, winSum=396
7471 06:48:54.818435 TX Vref=24, minBit 8, minWin=23, winSum=406
7472 06:48:54.825314 TX Vref=26, minBit 9, minWin=24, winSum=414
7473 06:48:54.829192 TX Vref=28, minBit 6, minWin=25, winSum=415
7474 06:48:54.832024 TX Vref=30, minBit 0, minWin=25, winSum=411
7475 06:48:54.836363 TX Vref=32, minBit 6, minWin=24, winSum=397
7476 06:48:54.838788 TX Vref=34, minBit 1, minWin=24, winSum=392
7477 06:48:54.844990 [TxChooseVref] Worse bit 6, Min win 25, Win sum 415, Final Vref 28
7478 06:48:54.845077
7479 06:48:54.848308 Final TX Range 0 Vref 28
7480 06:48:54.848389
7481 06:48:54.848453 ==
7482 06:48:54.852055 Dram Type= 6, Freq= 0, CH_0, rank 0
7483 06:48:54.854931 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7484 06:48:54.855013 ==
7485 06:48:54.855078
7486 06:48:54.855137
7487 06:48:54.858661 TX Vref Scan disable
7488 06:48:54.865349 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7489 06:48:54.865432 == TX Byte 0 ==
7490 06:48:54.868486 u2DelayCellOfst[0]=10 cells (3 PI)
7491 06:48:54.871796 u2DelayCellOfst[1]=17 cells (5 PI)
7492 06:48:54.875300 u2DelayCellOfst[2]=14 cells (4 PI)
7493 06:48:54.878061 u2DelayCellOfst[3]=10 cells (3 PI)
7494 06:48:54.881663 u2DelayCellOfst[4]=7 cells (2 PI)
7495 06:48:54.885426 u2DelayCellOfst[5]=0 cells (0 PI)
7496 06:48:54.888051 u2DelayCellOfst[6]=17 cells (5 PI)
7497 06:48:54.891332 u2DelayCellOfst[7]=17 cells (5 PI)
7498 06:48:54.895024 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7499 06:48:54.898765 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7500 06:48:54.901834 == TX Byte 1 ==
7501 06:48:54.901915 u2DelayCellOfst[8]=0 cells (0 PI)
7502 06:48:54.904587 u2DelayCellOfst[9]=3 cells (1 PI)
7503 06:48:54.909058 u2DelayCellOfst[10]=10 cells (3 PI)
7504 06:48:54.911407 u2DelayCellOfst[11]=3 cells (1 PI)
7505 06:48:54.914662 u2DelayCellOfst[12]=14 cells (4 PI)
7506 06:48:54.918029 u2DelayCellOfst[13]=14 cells (4 PI)
7507 06:48:54.921175 u2DelayCellOfst[14]=17 cells (5 PI)
7508 06:48:54.927178 u2DelayCellOfst[15]=14 cells (4 PI)
7509 06:48:54.927926 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7510 06:48:54.935109 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7511 06:48:54.935189 DramC Write-DBI on
7512 06:48:54.935252 ==
7513 06:48:54.937827 Dram Type= 6, Freq= 0, CH_0, rank 0
7514 06:48:54.944684 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7515 06:48:54.944771 ==
7516 06:48:54.944835
7517 06:48:54.944894
7518 06:48:54.944951 TX Vref Scan disable
7519 06:48:54.948132 == TX Byte 0 ==
7520 06:48:54.951682 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7521 06:48:54.954849 == TX Byte 1 ==
7522 06:48:54.959020 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7523 06:48:54.961632 DramC Write-DBI off
7524 06:48:54.961712
7525 06:48:54.961776 [DATLAT]
7526 06:48:54.961835 Freq=1600, CH0 RK0
7527 06:48:54.961892
7528 06:48:54.964896 DATLAT Default: 0xf
7529 06:48:54.964977 0, 0xFFFF, sum = 0
7530 06:48:54.968389 1, 0xFFFF, sum = 0
7531 06:48:54.971371 2, 0xFFFF, sum = 0
7532 06:48:54.971453 3, 0xFFFF, sum = 0
7533 06:48:54.974713 4, 0xFFFF, sum = 0
7534 06:48:54.974795 5, 0xFFFF, sum = 0
7535 06:48:54.977925 6, 0xFFFF, sum = 0
7536 06:48:54.978007 7, 0xFFFF, sum = 0
7537 06:48:54.981416 8, 0xFFFF, sum = 0
7538 06:48:54.981497 9, 0xFFFF, sum = 0
7539 06:48:54.985472 10, 0xFFFF, sum = 0
7540 06:48:54.985553 11, 0xFFFF, sum = 0
7541 06:48:54.987929 12, 0xBFF, sum = 0
7542 06:48:54.988010 13, 0x0, sum = 1
7543 06:48:54.991664 14, 0x0, sum = 2
7544 06:48:54.991754 15, 0x0, sum = 3
7545 06:48:54.996247 16, 0x0, sum = 4
7546 06:48:54.996329 best_step = 14
7547 06:48:54.996392
7548 06:48:54.996451 ==
7549 06:48:54.998815 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 06:48:55.001949 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7551 06:48:55.004643 ==
7552 06:48:55.004744 RX Vref Scan: 1
7553 06:48:55.004821
7554 06:48:55.007838 Set Vref Range= 24 -> 127
7555 06:48:55.007918
7556 06:48:55.011406 RX Vref 24 -> 127, step: 1
7557 06:48:55.011486
7558 06:48:55.011549 RX Delay 11 -> 252, step: 4
7559 06:48:55.011609
7560 06:48:55.014881 Set Vref, RX VrefLevel [Byte0]: 24
7561 06:48:55.017652 [Byte1]: 24
7562 06:48:55.021183
7563 06:48:55.021264 Set Vref, RX VrefLevel [Byte0]: 25
7564 06:48:55.025292 [Byte1]: 25
7565 06:48:55.029009
7566 06:48:55.029089 Set Vref, RX VrefLevel [Byte0]: 26
7567 06:48:55.033151 [Byte1]: 26
7568 06:48:55.036599
7569 06:48:55.036682 Set Vref, RX VrefLevel [Byte0]: 27
7570 06:48:55.039951 [Byte1]: 27
7571 06:48:55.044323
7572 06:48:55.044402 Set Vref, RX VrefLevel [Byte0]: 28
7573 06:48:55.047965 [Byte1]: 28
7574 06:48:55.051972
7575 06:48:55.052052 Set Vref, RX VrefLevel [Byte0]: 29
7576 06:48:55.055789 [Byte1]: 29
7577 06:48:55.059955
7578 06:48:55.060035 Set Vref, RX VrefLevel [Byte0]: 30
7579 06:48:55.063293 [Byte1]: 30
7580 06:48:55.067594
7581 06:48:55.067674 Set Vref, RX VrefLevel [Byte0]: 31
7582 06:48:55.070379 [Byte1]: 31
7583 06:48:55.074729
7584 06:48:55.074808 Set Vref, RX VrefLevel [Byte0]: 32
7585 06:48:55.078172 [Byte1]: 32
7586 06:48:55.082351
7587 06:48:55.082431 Set Vref, RX VrefLevel [Byte0]: 33
7588 06:48:55.085937 [Byte1]: 33
7589 06:48:55.089734
7590 06:48:55.089815 Set Vref, RX VrefLevel [Byte0]: 34
7591 06:48:55.093112 [Byte1]: 34
7592 06:48:55.097863
7593 06:48:55.097944 Set Vref, RX VrefLevel [Byte0]: 35
7594 06:48:55.100986 [Byte1]: 35
7595 06:48:55.105402
7596 06:48:55.105483 Set Vref, RX VrefLevel [Byte0]: 36
7597 06:48:55.108357 [Byte1]: 36
7598 06:48:55.113093
7599 06:48:55.113174 Set Vref, RX VrefLevel [Byte0]: 37
7600 06:48:55.116254 [Byte1]: 37
7601 06:48:55.120500
7602 06:48:55.120581 Set Vref, RX VrefLevel [Byte0]: 38
7603 06:48:55.124970 [Byte1]: 38
7604 06:48:55.128037
7605 06:48:55.128117 Set Vref, RX VrefLevel [Byte0]: 39
7606 06:48:55.131911 [Byte1]: 39
7607 06:48:55.136097
7608 06:48:55.136177 Set Vref, RX VrefLevel [Byte0]: 40
7609 06:48:55.141343 [Byte1]: 40
7610 06:48:55.143845
7611 06:48:55.143925 Set Vref, RX VrefLevel [Byte0]: 41
7612 06:48:55.146733 [Byte1]: 41
7613 06:48:55.150864
7614 06:48:55.150944 Set Vref, RX VrefLevel [Byte0]: 42
7615 06:48:55.154841 [Byte1]: 42
7616 06:48:55.158832
7617 06:48:55.158912 Set Vref, RX VrefLevel [Byte0]: 43
7618 06:48:55.161684 [Byte1]: 43
7619 06:48:55.166369
7620 06:48:55.166449 Set Vref, RX VrefLevel [Byte0]: 44
7621 06:48:55.169957 [Byte1]: 44
7622 06:48:55.174979
7623 06:48:55.175060 Set Vref, RX VrefLevel [Byte0]: 45
7624 06:48:55.177192 [Byte1]: 45
7625 06:48:55.181439
7626 06:48:55.181519 Set Vref, RX VrefLevel [Byte0]: 46
7627 06:48:55.184948 [Byte1]: 46
7628 06:48:55.189561
7629 06:48:55.189641 Set Vref, RX VrefLevel [Byte0]: 47
7630 06:48:55.192047 [Byte1]: 47
7631 06:48:55.196579
7632 06:48:55.196689 Set Vref, RX VrefLevel [Byte0]: 48
7633 06:48:55.201164 [Byte1]: 48
7634 06:48:55.204360
7635 06:48:55.204441 Set Vref, RX VrefLevel [Byte0]: 49
7636 06:48:55.207581 [Byte1]: 49
7637 06:48:55.211784
7638 06:48:55.211864 Set Vref, RX VrefLevel [Byte0]: 50
7639 06:48:55.214978 [Byte1]: 50
7640 06:48:55.219437
7641 06:48:55.219518 Set Vref, RX VrefLevel [Byte0]: 51
7642 06:48:55.222735 [Byte1]: 51
7643 06:48:55.227074
7644 06:48:55.227154 Set Vref, RX VrefLevel [Byte0]: 52
7645 06:48:55.230553 [Byte1]: 52
7646 06:48:55.234790
7647 06:48:55.234871 Set Vref, RX VrefLevel [Byte0]: 53
7648 06:48:55.237911 [Byte1]: 53
7649 06:48:55.243437
7650 06:48:55.243518 Set Vref, RX VrefLevel [Byte0]: 54
7651 06:48:55.247292 [Byte1]: 54
7652 06:48:55.249877
7653 06:48:55.249958 Set Vref, RX VrefLevel [Byte0]: 55
7654 06:48:55.253201 [Byte1]: 55
7655 06:48:55.258008
7656 06:48:55.258090 Set Vref, RX VrefLevel [Byte0]: 56
7657 06:48:55.261057 [Byte1]: 56
7658 06:48:55.265325
7659 06:48:55.265407 Set Vref, RX VrefLevel [Byte0]: 57
7660 06:48:55.268519 [Byte1]: 57
7661 06:48:55.272862
7662 06:48:55.272942 Set Vref, RX VrefLevel [Byte0]: 58
7663 06:48:55.276012 [Byte1]: 58
7664 06:48:55.280847
7665 06:48:55.280929 Set Vref, RX VrefLevel [Byte0]: 59
7666 06:48:55.283607 [Byte1]: 59
7667 06:48:55.287668
7668 06:48:55.287749 Set Vref, RX VrefLevel [Byte0]: 60
7669 06:48:55.291112 [Byte1]: 60
7670 06:48:55.295425
7671 06:48:55.295506 Set Vref, RX VrefLevel [Byte0]: 61
7672 06:48:55.298986 [Byte1]: 61
7673 06:48:55.303490
7674 06:48:55.303571 Set Vref, RX VrefLevel [Byte0]: 62
7675 06:48:55.306955 [Byte1]: 62
7676 06:48:55.310964
7677 06:48:55.311046 Set Vref, RX VrefLevel [Byte0]: 63
7678 06:48:55.314379 [Byte1]: 63
7679 06:48:55.318487
7680 06:48:55.318569 Set Vref, RX VrefLevel [Byte0]: 64
7681 06:48:55.322377 [Byte1]: 64
7682 06:48:55.325766
7683 06:48:55.325847 Set Vref, RX VrefLevel [Byte0]: 65
7684 06:48:55.329538 [Byte1]: 65
7685 06:48:55.333732
7686 06:48:55.333814 Set Vref, RX VrefLevel [Byte0]: 66
7687 06:48:55.337288 [Byte1]: 66
7688 06:48:55.340978
7689 06:48:55.341059 Set Vref, RX VrefLevel [Byte0]: 67
7690 06:48:55.344761 [Byte1]: 67
7691 06:48:55.349133
7692 06:48:55.349215 Set Vref, RX VrefLevel [Byte0]: 68
7693 06:48:55.352582 [Byte1]: 68
7694 06:48:55.356424
7695 06:48:55.356508 Set Vref, RX VrefLevel [Byte0]: 69
7696 06:48:55.359689 [Byte1]: 69
7697 06:48:55.364586
7698 06:48:55.364667 Set Vref, RX VrefLevel [Byte0]: 70
7699 06:48:55.367512 [Byte1]: 70
7700 06:48:55.371608
7701 06:48:55.371687 Final RX Vref Byte 0 = 54 to rank0
7702 06:48:55.375402 Final RX Vref Byte 1 = 54 to rank0
7703 06:48:55.378477 Final RX Vref Byte 0 = 54 to rank1
7704 06:48:55.381612 Final RX Vref Byte 1 = 54 to rank1==
7705 06:48:55.385011 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 06:48:55.391957 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7707 06:48:55.392038 ==
7708 06:48:55.392103 DQS Delay:
7709 06:48:55.392163 DQS0 = 0, DQS1 = 0
7710 06:48:55.395181 DQM Delay:
7711 06:48:55.395261 DQM0 = 126, DQM1 = 120
7712 06:48:55.398653 DQ Delay:
7713 06:48:55.402028 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7714 06:48:55.405722 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7715 06:48:55.408024 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7716 06:48:55.411542 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7717 06:48:55.411622
7718 06:48:55.411686
7719 06:48:55.411745
7720 06:48:55.415102 [DramC_TX_OE_Calibration] TA2
7721 06:48:55.418276 Original DQ_B0 (3 6) =30, OEN = 27
7722 06:48:55.421650 Original DQ_B1 (3 6) =30, OEN = 27
7723 06:48:55.425093 24, 0x0, End_B0=24 End_B1=24
7724 06:48:55.425175 25, 0x0, End_B0=25 End_B1=25
7725 06:48:55.428431 26, 0x0, End_B0=26 End_B1=26
7726 06:48:55.431295 27, 0x0, End_B0=27 End_B1=27
7727 06:48:55.434580 28, 0x0, End_B0=28 End_B1=28
7728 06:48:55.438285 29, 0x0, End_B0=29 End_B1=29
7729 06:48:55.438395 30, 0x0, End_B0=30 End_B1=30
7730 06:48:55.441272 31, 0x4141, End_B0=30 End_B1=30
7731 06:48:55.444725 Byte0 end_step=30 best_step=27
7732 06:48:55.449452 Byte1 end_step=30 best_step=27
7733 06:48:55.451266 Byte0 TX OE(2T, 0.5T) = (3, 3)
7734 06:48:55.455147 Byte1 TX OE(2T, 0.5T) = (3, 3)
7735 06:48:55.455228
7736 06:48:55.455292
7737 06:48:55.461270 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7738 06:48:55.464918 CH0 RK0: MR19=303, MR18=1C1C
7739 06:48:55.471724 CH0_RK0: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
7740 06:48:55.471805
7741 06:48:55.474510 ----->DramcWriteLeveling(PI) begin...
7742 06:48:55.474593 ==
7743 06:48:55.477524 Dram Type= 6, Freq= 0, CH_0, rank 1
7744 06:48:55.481188 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7745 06:48:55.481270 ==
7746 06:48:55.484744 Write leveling (Byte 0): 29 => 29
7747 06:48:55.487545 Write leveling (Byte 1): 25 => 25
7748 06:48:55.491974 DramcWriteLeveling(PI) end<-----
7749 06:48:55.492056
7750 06:48:55.492119 ==
7751 06:48:55.494067 Dram Type= 6, Freq= 0, CH_0, rank 1
7752 06:48:55.497591 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7753 06:48:55.497676 ==
7754 06:48:55.501341 [Gating] SW mode calibration
7755 06:48:55.508038 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7756 06:48:55.514560 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7757 06:48:55.517437 0 12 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7758 06:48:55.524756 0 12 4 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
7759 06:48:55.527437 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7760 06:48:55.530581 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7761 06:48:55.537299 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7762 06:48:55.540868 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7763 06:48:55.543793 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7764 06:48:55.547273 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7765 06:48:55.553864 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 1)
7766 06:48:55.557616 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
7767 06:48:55.561477 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7768 06:48:55.567887 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7769 06:48:55.570329 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7770 06:48:55.573520 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7771 06:48:55.580478 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7772 06:48:55.583891 0 13 28 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7773 06:48:55.587034 0 14 0 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (1 1)
7774 06:48:55.593936 0 14 4 | B1->B0 | 3d3c 4646 | 1 0 | (0 0) (0 0)
7775 06:48:55.597092 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7776 06:48:55.600402 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7777 06:48:55.607413 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7778 06:48:55.609846 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7779 06:48:55.613683 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7780 06:48:55.620854 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7781 06:48:55.623390 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7782 06:48:55.627256 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7783 06:48:55.633442 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7784 06:48:55.637463 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7785 06:48:55.640075 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7786 06:48:55.646545 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7787 06:48:55.650168 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7788 06:48:55.652976 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7789 06:48:55.659777 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7790 06:48:55.663989 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7791 06:48:55.667765 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7792 06:48:55.672678 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7793 06:48:55.676362 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7794 06:48:55.680576 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7795 06:48:55.686071 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7796 06:48:55.689880 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7797 06:48:55.693122 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7798 06:48:55.699520 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7799 06:48:55.699603 Total UI for P1: 0, mck2ui 16
7800 06:48:55.706218 best dqsien dly found for B0: ( 1, 0, 30)
7801 06:48:55.709315 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7802 06:48:55.712921 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7803 06:48:55.716114 Total UI for P1: 0, mck2ui 16
7804 06:48:55.719133 best dqsien dly found for B1: ( 1, 1, 4)
7805 06:48:55.723066 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7806 06:48:55.726272 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7807 06:48:55.726353
7808 06:48:55.732475 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7809 06:48:55.735538 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7810 06:48:55.735620 [Gating] SW calibration Done
7811 06:48:55.739287 ==
7812 06:48:55.739368 Dram Type= 6, Freq= 0, CH_0, rank 1
7813 06:48:55.745963 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7814 06:48:55.746045 ==
7815 06:48:55.746110 RX Vref Scan: 0
7816 06:48:55.746171
7817 06:48:55.749113 RX Vref 0 -> 0, step: 1
7818 06:48:55.749194
7819 06:48:55.753098 RX Delay 0 -> 252, step: 8
7820 06:48:55.756066 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7821 06:48:55.758794 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7822 06:48:55.762756 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7823 06:48:55.769237 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7824 06:48:55.772174 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7825 06:48:55.775455 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7826 06:48:55.778814 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7827 06:48:55.782102 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7828 06:48:55.789259 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7829 06:48:55.792025 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7830 06:48:55.795421 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7831 06:48:55.798794 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7832 06:48:55.801935 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7833 06:48:55.809253 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7834 06:48:55.811757 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7835 06:48:55.815660 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7836 06:48:55.815741 ==
7837 06:48:55.818895 Dram Type= 6, Freq= 0, CH_0, rank 1
7838 06:48:55.822294 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7839 06:48:55.825351 ==
7840 06:48:55.825431 DQS Delay:
7841 06:48:55.825497 DQS0 = 0, DQS1 = 0
7842 06:48:55.828147 DQM Delay:
7843 06:48:55.828227 DQM0 = 130, DQM1 = 123
7844 06:48:55.832685 DQ Delay:
7845 06:48:55.836108 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7846 06:48:55.838776 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7847 06:48:55.842183 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7848 06:48:55.844964 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7849 06:48:55.845045
7850 06:48:55.845108
7851 06:48:55.845168 ==
7852 06:48:55.848356 Dram Type= 6, Freq= 0, CH_0, rank 1
7853 06:48:55.852177 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7854 06:48:55.854911 ==
7855 06:48:55.854992
7856 06:48:55.855056
7857 06:48:55.855115 TX Vref Scan disable
7858 06:48:55.859543 == TX Byte 0 ==
7859 06:48:55.861501 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7860 06:48:55.865099 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7861 06:48:55.867714 == TX Byte 1 ==
7862 06:48:55.871526 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7863 06:48:55.874566 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7864 06:48:55.877900 ==
7865 06:48:55.877981 Dram Type= 6, Freq= 0, CH_0, rank 1
7866 06:48:55.884566 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7867 06:48:55.884679 ==
7868 06:48:55.897354
7869 06:48:55.899740 TX Vref early break, caculate TX vref
7870 06:48:55.903469 TX Vref=16, minBit 8, minWin=21, winSum=368
7871 06:48:55.906900 TX Vref=18, minBit 1, minWin=23, winSum=383
7872 06:48:55.909927 TX Vref=20, minBit 9, minWin=23, winSum=390
7873 06:48:55.913824 TX Vref=22, minBit 8, minWin=23, winSum=395
7874 06:48:55.916856 TX Vref=24, minBit 1, minWin=24, winSum=403
7875 06:48:55.922878 TX Vref=26, minBit 7, minWin=25, winSum=414
7876 06:48:55.926874 TX Vref=28, minBit 1, minWin=25, winSum=413
7877 06:48:55.929633 TX Vref=30, minBit 0, minWin=25, winSum=409
7878 06:48:55.933379 TX Vref=32, minBit 8, minWin=24, winSum=400
7879 06:48:55.936655 TX Vref=34, minBit 8, minWin=23, winSum=390
7880 06:48:55.942900 [TxChooseVref] Worse bit 7, Min win 25, Win sum 414, Final Vref 26
7881 06:48:55.943003
7882 06:48:55.946649 Final TX Range 0 Vref 26
7883 06:48:55.946748
7884 06:48:55.946829 ==
7885 06:48:55.949480 Dram Type= 6, Freq= 0, CH_0, rank 1
7886 06:48:55.953664 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7887 06:48:55.953764 ==
7888 06:48:55.953856
7889 06:48:55.953946
7890 06:48:55.956441 TX Vref Scan disable
7891 06:48:55.962984 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7892 06:48:55.963097 == TX Byte 0 ==
7893 06:48:55.966633 u2DelayCellOfst[0]=14 cells (4 PI)
7894 06:48:55.969566 u2DelayCellOfst[1]=17 cells (5 PI)
7895 06:48:55.973073 u2DelayCellOfst[2]=14 cells (4 PI)
7896 06:48:55.977835 u2DelayCellOfst[3]=14 cells (4 PI)
7897 06:48:55.979979 u2DelayCellOfst[4]=10 cells (3 PI)
7898 06:48:55.983922 u2DelayCellOfst[5]=0 cells (0 PI)
7899 06:48:55.986076 u2DelayCellOfst[6]=17 cells (5 PI)
7900 06:48:55.989616 u2DelayCellOfst[7]=17 cells (5 PI)
7901 06:48:55.993641 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7902 06:48:55.996124 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7903 06:48:55.999548 == TX Byte 1 ==
7904 06:48:56.003072 u2DelayCellOfst[8]=3 cells (1 PI)
7905 06:48:56.003178 u2DelayCellOfst[9]=0 cells (0 PI)
7906 06:48:56.006311 u2DelayCellOfst[10]=14 cells (4 PI)
7907 06:48:56.009321 u2DelayCellOfst[11]=7 cells (2 PI)
7908 06:48:56.013075 u2DelayCellOfst[12]=17 cells (5 PI)
7909 06:48:56.016108 u2DelayCellOfst[13]=17 cells (5 PI)
7910 06:48:56.019529 u2DelayCellOfst[14]=21 cells (6 PI)
7911 06:48:56.022857 u2DelayCellOfst[15]=17 cells (5 PI)
7912 06:48:56.026071 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7913 06:48:56.032767 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7914 06:48:56.032847 DramC Write-DBI on
7915 06:48:56.032911 ==
7916 06:48:56.036115 Dram Type= 6, Freq= 0, CH_0, rank 1
7917 06:48:56.039861 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7918 06:48:56.043035 ==
7919 06:48:56.043115
7920 06:48:56.043179
7921 06:48:56.043237 TX Vref Scan disable
7922 06:48:56.046544 == TX Byte 0 ==
7923 06:48:56.050716 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7924 06:48:56.052874 == TX Byte 1 ==
7925 06:48:56.055987 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7926 06:48:56.060251 DramC Write-DBI off
7927 06:48:56.060331
7928 06:48:56.060394 [DATLAT]
7929 06:48:56.060454 Freq=1600, CH0 RK1
7930 06:48:56.060512
7931 06:48:56.062869 DATLAT Default: 0xe
7932 06:48:56.066178 0, 0xFFFF, sum = 0
7933 06:48:56.066261 1, 0xFFFF, sum = 0
7934 06:48:56.069542 2, 0xFFFF, sum = 0
7935 06:48:56.069623 3, 0xFFFF, sum = 0
7936 06:48:56.072351 4, 0xFFFF, sum = 0
7937 06:48:56.072433 5, 0xFFFF, sum = 0
7938 06:48:56.075920 6, 0xFFFF, sum = 0
7939 06:48:56.076001 7, 0xFFFF, sum = 0
7940 06:48:56.079596 8, 0xFFFF, sum = 0
7941 06:48:56.079677 9, 0xFFFF, sum = 0
7942 06:48:56.083579 10, 0xFFFF, sum = 0
7943 06:48:56.083687 11, 0xFFFF, sum = 0
7944 06:48:56.086258 12, 0x8FFF, sum = 0
7945 06:48:56.086339 13, 0x0, sum = 1
7946 06:48:56.089889 14, 0x0, sum = 2
7947 06:48:56.090000 15, 0x0, sum = 3
7948 06:48:56.092680 16, 0x0, sum = 4
7949 06:48:56.092805 best_step = 14
7950 06:48:56.092871
7951 06:48:56.092931 ==
7952 06:48:56.096016 Dram Type= 6, Freq= 0, CH_0, rank 1
7953 06:48:56.102226 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7954 06:48:56.102309 ==
7955 06:48:56.102375 RX Vref Scan: 0
7956 06:48:56.102436
7957 06:48:56.105513 RX Vref 0 -> 0, step: 1
7958 06:48:56.105595
7959 06:48:56.109506 RX Delay 11 -> 252, step: 4
7960 06:48:56.112087 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7961 06:48:56.115857 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7962 06:48:56.118696 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7963 06:48:56.125416 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7964 06:48:56.128612 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7965 06:48:56.132819 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7966 06:48:56.135727 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7967 06:48:56.139101 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7968 06:48:56.145346 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7969 06:48:56.148632 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7970 06:48:56.152159 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7971 06:48:56.154971 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7972 06:48:56.162326 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7973 06:48:56.165035 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7974 06:48:56.168415 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7975 06:48:56.172094 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7976 06:48:56.172176 ==
7977 06:48:56.175116 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 06:48:56.181405 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7979 06:48:56.181488 ==
7980 06:48:56.181552 DQS Delay:
7981 06:48:56.181612 DQS0 = 0, DQS1 = 0
7982 06:48:56.185841 DQM Delay:
7983 06:48:56.185923 DQM0 = 127, DQM1 = 120
7984 06:48:56.188581 DQ Delay:
7985 06:48:56.191260 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =122
7986 06:48:56.194614 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
7987 06:48:56.198884 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7988 06:48:56.201019 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7989 06:48:56.201100
7990 06:48:56.201164
7991 06:48:56.201223
7992 06:48:56.204456 [DramC_TX_OE_Calibration] TA2
7993 06:48:56.208095 Original DQ_B0 (3 6) =30, OEN = 27
7994 06:48:56.211789 Original DQ_B1 (3 6) =30, OEN = 27
7995 06:48:56.215358 24, 0x0, End_B0=24 End_B1=24
7996 06:48:56.215442 25, 0x0, End_B0=25 End_B1=25
7997 06:48:56.217949 26, 0x0, End_B0=26 End_B1=26
7998 06:48:56.221115 27, 0x0, End_B0=27 End_B1=27
7999 06:48:56.225234 28, 0x0, End_B0=28 End_B1=28
8000 06:48:56.228302 29, 0x0, End_B0=29 End_B1=29
8001 06:48:56.228383 30, 0x0, End_B0=30 End_B1=30
8002 06:48:56.231116 31, 0x4141, End_B0=30 End_B1=30
8003 06:48:56.234569 Byte0 end_step=30 best_step=27
8004 06:48:56.238027 Byte1 end_step=30 best_step=27
8005 06:48:56.241428 Byte0 TX OE(2T, 0.5T) = (3, 3)
8006 06:48:56.244484 Byte1 TX OE(2T, 0.5T) = (3, 3)
8007 06:48:56.244565
8008 06:48:56.244628
8009 06:48:56.251005 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8010 06:48:56.254579 CH0 RK1: MR19=303, MR18=2323
8011 06:48:56.260966 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
8012 06:48:56.264083 [RxdqsGatingPostProcess] freq 1600
8013 06:48:56.268034 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8014 06:48:56.270841 Pre-setting of DQS Precalculation
8015 06:48:56.277400 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8016 06:48:56.277481 ==
8017 06:48:56.281686 Dram Type= 6, Freq= 0, CH_1, rank 0
8018 06:48:56.283832 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8019 06:48:56.283914 ==
8020 06:48:56.290266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8021 06:48:56.293789 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8022 06:48:56.297280 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8023 06:48:56.304007 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8024 06:48:56.312368 [CA 0] Center 41 (11~71) winsize 61
8025 06:48:56.315522 [CA 1] Center 40 (10~71) winsize 62
8026 06:48:56.318917 [CA 2] Center 36 (7~66) winsize 60
8027 06:48:56.322254 [CA 3] Center 35 (6~65) winsize 60
8028 06:48:56.325564 [CA 4] Center 33 (4~63) winsize 60
8029 06:48:56.329563 [CA 5] Center 33 (4~63) winsize 60
8030 06:48:56.329644
8031 06:48:56.332616 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8032 06:48:56.332727
8033 06:48:56.335969 [CATrainingPosCal] consider 1 rank data
8034 06:48:56.339848 u2DelayCellTimex100 = 275/100 ps
8035 06:48:56.342336 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8036 06:48:56.348591 CA1 delay=40 (10~71),Diff = 7 PI (24 cell)
8037 06:48:56.352020 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8038 06:48:56.355461 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8039 06:48:56.358722 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8040 06:48:56.362121 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8041 06:48:56.362204
8042 06:48:56.365267 CA PerBit enable=1, Macro0, CA PI delay=33
8043 06:48:56.365348
8044 06:48:56.368815 [CBTSetCACLKResult] CA Dly = 33
8045 06:48:56.371870 CS Dly: 8 (0~39)
8046 06:48:56.375304 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8047 06:48:56.378909 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8048 06:48:56.378989 ==
8049 06:48:56.382076 Dram Type= 6, Freq= 0, CH_1, rank 1
8050 06:48:56.385513 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8051 06:48:56.388619 ==
8052 06:48:56.391589 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8053 06:48:56.395158 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8054 06:48:56.402407 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8055 06:48:56.408145 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8056 06:48:56.414991 [CA 0] Center 41 (11~71) winsize 61
8057 06:48:56.418896 [CA 1] Center 41 (11~71) winsize 61
8058 06:48:56.421505 [CA 2] Center 36 (7~66) winsize 60
8059 06:48:56.425408 [CA 3] Center 35 (6~65) winsize 60
8060 06:48:56.428434 [CA 4] Center 34 (5~64) winsize 60
8061 06:48:56.431189 [CA 5] Center 34 (5~64) winsize 60
8062 06:48:56.431269
8063 06:48:56.434642 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8064 06:48:56.434747
8065 06:48:56.438564 [CATrainingPosCal] consider 2 rank data
8066 06:48:56.441090 u2DelayCellTimex100 = 275/100 ps
8067 06:48:56.449092 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8068 06:48:56.451228 CA1 delay=41 (11~71),Diff = 7 PI (24 cell)
8069 06:48:56.454414 CA2 delay=36 (7~66),Diff = 2 PI (7 cell)
8070 06:48:56.457722 CA3 delay=35 (6~65),Diff = 1 PI (3 cell)
8071 06:48:56.461093 CA4 delay=34 (5~63),Diff = 0 PI (0 cell)
8072 06:48:56.464264 CA5 delay=34 (5~63),Diff = 0 PI (0 cell)
8073 06:48:56.464345
8074 06:48:56.467865 CA PerBit enable=1, Macro0, CA PI delay=34
8075 06:48:56.467945
8076 06:48:56.470916 [CBTSetCACLKResult] CA Dly = 34
8077 06:48:56.474083 CS Dly: 9 (0~42)
8078 06:48:56.477526 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8079 06:48:56.481327 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8080 06:48:56.481407
8081 06:48:56.484433 ----->DramcWriteLeveling(PI) begin...
8082 06:48:56.484515 ==
8083 06:48:56.487763 Dram Type= 6, Freq= 0, CH_1, rank 0
8084 06:48:56.494069 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8085 06:48:56.494150 ==
8086 06:48:56.497635 Write leveling (Byte 0): 23 => 23
8087 06:48:56.500581 Write leveling (Byte 1): 22 => 22
8088 06:48:56.500665 DramcWriteLeveling(PI) end<-----
8089 06:48:56.500737
8090 06:48:56.504133 ==
8091 06:48:56.507226 Dram Type= 6, Freq= 0, CH_1, rank 0
8092 06:48:56.510659 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8093 06:48:56.510740 ==
8094 06:48:56.514511 [Gating] SW mode calibration
8095 06:48:56.520536 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8096 06:48:56.523801 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8097 06:48:56.530161 0 12 0 | B1->B0 | 2525 3434 | 0 0 | (1 1) (0 0)
8098 06:48:56.534100 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8099 06:48:56.536639 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8100 06:48:56.543728 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8101 06:48:56.547168 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8102 06:48:56.550382 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8103 06:48:56.556666 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8104 06:48:56.559971 0 12 28 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 1)
8105 06:48:56.563849 0 13 0 | B1->B0 | 3131 2323 | 1 0 | (1 1) (1 0)
8106 06:48:56.570274 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8107 06:48:56.573348 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 06:48:56.577080 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 06:48:56.583476 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8110 06:48:56.586724 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 06:48:56.590181 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 06:48:56.596661 0 13 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8113 06:48:56.600225 0 14 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8114 06:48:56.604179 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 06:48:56.610173 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 06:48:56.613312 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8117 06:48:56.616667 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8118 06:48:56.623432 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 06:48:56.626460 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8120 06:48:56.630495 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8121 06:48:56.636932 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8122 06:48:56.640174 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8123 06:48:56.642909 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 06:48:56.649792 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 06:48:56.653260 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 06:48:56.656253 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 06:48:56.660577 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 06:48:56.666476 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 06:48:56.669737 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 06:48:56.672466 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 06:48:56.680171 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 06:48:56.683082 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 06:48:56.686251 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 06:48:56.693195 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 06:48:56.696656 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8136 06:48:56.699821 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8137 06:48:56.702713 Total UI for P1: 0, mck2ui 16
8138 06:48:56.705979 best dqsien dly found for B0: ( 1, 0, 24)
8139 06:48:56.713024 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8140 06:48:56.715823 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8141 06:48:56.719497 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8142 06:48:56.722966 Total UI for P1: 0, mck2ui 16
8143 06:48:56.726456 best dqsien dly found for B1: ( 1, 1, 0)
8144 06:48:56.729668 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8145 06:48:56.732611 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8146 06:48:56.732724
8147 06:48:56.739152 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8148 06:48:56.742515 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8149 06:48:56.745925 [Gating] SW calibration Done
8150 06:48:56.746006 ==
8151 06:48:56.748677 Dram Type= 6, Freq= 0, CH_1, rank 0
8152 06:48:56.752217 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8153 06:48:56.752299 ==
8154 06:48:56.752365 RX Vref Scan: 0
8155 06:48:56.752426
8156 06:48:56.755345 RX Vref 0 -> 0, step: 1
8157 06:48:56.755427
8158 06:48:56.759206 RX Delay 0 -> 252, step: 8
8159 06:48:56.762217 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8160 06:48:56.765628 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8161 06:48:56.772483 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8162 06:48:56.775892 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8163 06:48:56.778699 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8164 06:48:56.782099 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8165 06:48:56.785402 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8166 06:48:56.792084 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8167 06:48:56.795068 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8168 06:48:56.799287 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8169 06:48:56.801907 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8170 06:48:56.805544 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8171 06:48:56.812230 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8172 06:48:56.814915 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8173 06:48:56.819139 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8174 06:48:56.821530 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8175 06:48:56.821613 ==
8176 06:48:56.825395 Dram Type= 6, Freq= 0, CH_1, rank 0
8177 06:48:56.831522 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8178 06:48:56.831604 ==
8179 06:48:56.831669 DQS Delay:
8180 06:48:56.834658 DQS0 = 0, DQS1 = 0
8181 06:48:56.834738 DQM Delay:
8182 06:48:56.834801 DQM0 = 129, DQM1 = 126
8183 06:48:56.839380 DQ Delay:
8184 06:48:56.841429 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8185 06:48:56.844682 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8186 06:48:56.848403 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =115
8187 06:48:56.851734 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8188 06:48:56.851815
8189 06:48:56.851880
8190 06:48:56.851940 ==
8191 06:48:56.855068 Dram Type= 6, Freq= 0, CH_1, rank 0
8192 06:48:56.861575 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8193 06:48:56.861661 ==
8194 06:48:56.861727
8195 06:48:56.861788
8196 06:48:56.861846 TX Vref Scan disable
8197 06:48:56.865062 == TX Byte 0 ==
8198 06:48:56.868304 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8199 06:48:56.874774 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8200 06:48:56.874856 == TX Byte 1 ==
8201 06:48:56.877918 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8202 06:48:56.884489 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8203 06:48:56.884572 ==
8204 06:48:56.887814 Dram Type= 6, Freq= 0, CH_1, rank 0
8205 06:48:56.891287 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8206 06:48:56.891396 ==
8207 06:48:56.903139
8208 06:48:56.906342 TX Vref early break, caculate TX vref
8209 06:48:56.909534 TX Vref=16, minBit 0, minWin=21, winSum=362
8210 06:48:56.912514 TX Vref=18, minBit 3, minWin=22, winSum=376
8211 06:48:56.916093 TX Vref=20, minBit 3, minWin=22, winSum=384
8212 06:48:56.919600 TX Vref=22, minBit 4, minWin=23, winSum=394
8213 06:48:56.922959 TX Vref=24, minBit 1, minWin=24, winSum=404
8214 06:48:56.929028 TX Vref=26, minBit 0, minWin=24, winSum=412
8215 06:48:56.932446 TX Vref=28, minBit 3, minWin=24, winSum=412
8216 06:48:56.936355 TX Vref=30, minBit 0, minWin=24, winSum=404
8217 06:48:56.939513 TX Vref=32, minBit 1, minWin=23, winSum=395
8218 06:48:56.942915 TX Vref=34, minBit 0, minWin=23, winSum=385
8219 06:48:56.949129 [TxChooseVref] Worse bit 0, Min win 24, Win sum 412, Final Vref 26
8220 06:48:56.949210
8221 06:48:56.952881 Final TX Range 0 Vref 26
8222 06:48:56.952961
8223 06:48:56.953025 ==
8224 06:48:56.955936 Dram Type= 6, Freq= 0, CH_1, rank 0
8225 06:48:56.959561 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8226 06:48:56.959642 ==
8227 06:48:56.959706
8228 06:48:56.959765
8229 06:48:56.962600 TX Vref Scan disable
8230 06:48:56.968922 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8231 06:48:56.969003 == TX Byte 0 ==
8232 06:48:56.972909 u2DelayCellOfst[0]=14 cells (4 PI)
8233 06:48:56.975513 u2DelayCellOfst[1]=10 cells (3 PI)
8234 06:48:56.979050 u2DelayCellOfst[2]=0 cells (0 PI)
8235 06:48:56.982250 u2DelayCellOfst[3]=3 cells (1 PI)
8236 06:48:56.985866 u2DelayCellOfst[4]=7 cells (2 PI)
8237 06:48:56.989066 u2DelayCellOfst[5]=17 cells (5 PI)
8238 06:48:56.992135 u2DelayCellOfst[6]=14 cells (4 PI)
8239 06:48:56.995320 u2DelayCellOfst[7]=7 cells (2 PI)
8240 06:48:56.998703 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8241 06:48:57.002091 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8242 06:48:57.005325 == TX Byte 1 ==
8243 06:48:57.005405 u2DelayCellOfst[8]=0 cells (0 PI)
8244 06:48:57.009039 u2DelayCellOfst[9]=7 cells (2 PI)
8245 06:48:57.012978 u2DelayCellOfst[10]=10 cells (3 PI)
8246 06:48:57.015190 u2DelayCellOfst[11]=3 cells (1 PI)
8247 06:48:57.018978 u2DelayCellOfst[12]=14 cells (4 PI)
8248 06:48:57.022183 u2DelayCellOfst[13]=21 cells (6 PI)
8249 06:48:57.025002 u2DelayCellOfst[14]=21 cells (6 PI)
8250 06:48:57.028596 u2DelayCellOfst[15]=17 cells (5 PI)
8251 06:48:57.032163 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8252 06:48:57.039305 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8253 06:48:57.039386 DramC Write-DBI on
8254 06:48:57.039450 ==
8255 06:48:57.042733 Dram Type= 6, Freq= 0, CH_1, rank 0
8256 06:48:57.048395 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8257 06:48:57.048476 ==
8258 06:48:57.048539
8259 06:48:57.048599
8260 06:48:57.048655 TX Vref Scan disable
8261 06:48:57.052394 == TX Byte 0 ==
8262 06:48:57.055276 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8263 06:48:57.058791 == TX Byte 1 ==
8264 06:48:57.062483 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8265 06:48:57.065359 DramC Write-DBI off
8266 06:48:57.065439
8267 06:48:57.065502 [DATLAT]
8268 06:48:57.065561 Freq=1600, CH1 RK0
8269 06:48:57.065620
8270 06:48:57.068395 DATLAT Default: 0xf
8271 06:48:57.068475 0, 0xFFFF, sum = 0
8272 06:48:57.071862 1, 0xFFFF, sum = 0
8273 06:48:57.075338 2, 0xFFFF, sum = 0
8274 06:48:57.075443 3, 0xFFFF, sum = 0
8275 06:48:57.078185 4, 0xFFFF, sum = 0
8276 06:48:57.078267 5, 0xFFFF, sum = 0
8277 06:48:57.081922 6, 0xFFFF, sum = 0
8278 06:48:57.082004 7, 0xFFFF, sum = 0
8279 06:48:57.085345 8, 0xFFFF, sum = 0
8280 06:48:57.085426 9, 0xFFFF, sum = 0
8281 06:48:57.088682 10, 0xFFFF, sum = 0
8282 06:48:57.088809 11, 0xFFFF, sum = 0
8283 06:48:57.092125 12, 0xF7F, sum = 0
8284 06:48:57.092209 13, 0x0, sum = 1
8285 06:48:57.094900 14, 0x0, sum = 2
8286 06:48:57.094981 15, 0x0, sum = 3
8287 06:48:57.098105 16, 0x0, sum = 4
8288 06:48:57.098186 best_step = 14
8289 06:48:57.098250
8290 06:48:57.098310 ==
8291 06:48:57.101561 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 06:48:57.105190 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8293 06:48:57.108173 ==
8294 06:48:57.108253 RX Vref Scan: 1
8295 06:48:57.108318
8296 06:48:57.111567 Set Vref Range= 24 -> 127
8297 06:48:57.111648
8298 06:48:57.111711 RX Vref 24 -> 127, step: 1
8299 06:48:57.115097
8300 06:48:57.115176 RX Delay 11 -> 252, step: 4
8301 06:48:57.115240
8302 06:48:57.118284 Set Vref, RX VrefLevel [Byte0]: 24
8303 06:48:57.121418 [Byte1]: 24
8304 06:48:57.125120
8305 06:48:57.125200 Set Vref, RX VrefLevel [Byte0]: 25
8306 06:48:57.129211 [Byte1]: 25
8307 06:48:57.133257
8308 06:48:57.133337 Set Vref, RX VrefLevel [Byte0]: 26
8309 06:48:57.136232 [Byte1]: 26
8310 06:48:57.140768
8311 06:48:57.140848 Set Vref, RX VrefLevel [Byte0]: 27
8312 06:48:57.143708 [Byte1]: 27
8313 06:48:57.148211
8314 06:48:57.148291 Set Vref, RX VrefLevel [Byte0]: 28
8315 06:48:57.151209 [Byte1]: 28
8316 06:48:57.155689
8317 06:48:57.155769 Set Vref, RX VrefLevel [Byte0]: 29
8318 06:48:57.159319 [Byte1]: 29
8319 06:48:57.163698
8320 06:48:57.163778 Set Vref, RX VrefLevel [Byte0]: 30
8321 06:48:57.166641 [Byte1]: 30
8322 06:48:57.171649
8323 06:48:57.171729 Set Vref, RX VrefLevel [Byte0]: 31
8324 06:48:57.174529 [Byte1]: 31
8325 06:48:57.178388
8326 06:48:57.178494 Set Vref, RX VrefLevel [Byte0]: 32
8327 06:48:57.181646 [Byte1]: 32
8328 06:48:57.186225
8329 06:48:57.186306 Set Vref, RX VrefLevel [Byte0]: 33
8330 06:48:57.190099 [Byte1]: 33
8331 06:48:57.194696
8332 06:48:57.194776 Set Vref, RX VrefLevel [Byte0]: 34
8333 06:48:57.197241 [Byte1]: 34
8334 06:48:57.201118
8335 06:48:57.201199 Set Vref, RX VrefLevel [Byte0]: 35
8336 06:48:57.204542 [Byte1]: 35
8337 06:48:57.208896
8338 06:48:57.208975 Set Vref, RX VrefLevel [Byte0]: 36
8339 06:48:57.213097 [Byte1]: 36
8340 06:48:57.217054
8341 06:48:57.217134 Set Vref, RX VrefLevel [Byte0]: 37
8342 06:48:57.220602 [Byte1]: 37
8343 06:48:57.224318
8344 06:48:57.224398 Set Vref, RX VrefLevel [Byte0]: 38
8345 06:48:57.227188 [Byte1]: 38
8346 06:48:57.231872
8347 06:48:57.231952 Set Vref, RX VrefLevel [Byte0]: 39
8348 06:48:57.235369 [Byte1]: 39
8349 06:48:57.239791
8350 06:48:57.239870 Set Vref, RX VrefLevel [Byte0]: 40
8351 06:48:57.242602 [Byte1]: 40
8352 06:48:57.247437
8353 06:48:57.247546 Set Vref, RX VrefLevel [Byte0]: 41
8354 06:48:57.250243 [Byte1]: 41
8355 06:48:57.254507
8356 06:48:57.254586 Set Vref, RX VrefLevel [Byte0]: 42
8357 06:48:57.257622 [Byte1]: 42
8358 06:48:57.262604
8359 06:48:57.262685 Set Vref, RX VrefLevel [Byte0]: 43
8360 06:48:57.266112 [Byte1]: 43
8361 06:48:57.269916
8362 06:48:57.269994 Set Vref, RX VrefLevel [Byte0]: 44
8363 06:48:57.273181 [Byte1]: 44
8364 06:48:57.277477
8365 06:48:57.277557 Set Vref, RX VrefLevel [Byte0]: 45
8366 06:48:57.280628 [Byte1]: 45
8367 06:48:57.285017
8368 06:48:57.285096 Set Vref, RX VrefLevel [Byte0]: 46
8369 06:48:57.288868 [Byte1]: 46
8370 06:48:57.292584
8371 06:48:57.292688 Set Vref, RX VrefLevel [Byte0]: 47
8372 06:48:57.295945 [Byte1]: 47
8373 06:48:57.300990
8374 06:48:57.301070 Set Vref, RX VrefLevel [Byte0]: 48
8375 06:48:57.303901 [Byte1]: 48
8376 06:48:57.308308
8377 06:48:57.308387 Set Vref, RX VrefLevel [Byte0]: 49
8378 06:48:57.311510 [Byte1]: 49
8379 06:48:57.316331
8380 06:48:57.316410 Set Vref, RX VrefLevel [Byte0]: 50
8381 06:48:57.319838 [Byte1]: 50
8382 06:48:57.324263
8383 06:48:57.324357 Set Vref, RX VrefLevel [Byte0]: 51
8384 06:48:57.327401 [Byte1]: 51
8385 06:48:57.330709
8386 06:48:57.330788 Set Vref, RX VrefLevel [Byte0]: 52
8387 06:48:57.334278 [Byte1]: 52
8388 06:48:57.338349
8389 06:48:57.338429 Set Vref, RX VrefLevel [Byte0]: 53
8390 06:48:57.341522 [Byte1]: 53
8391 06:48:57.346590
8392 06:48:57.346668 Set Vref, RX VrefLevel [Byte0]: 54
8393 06:48:57.349802 [Byte1]: 54
8394 06:48:57.353480
8395 06:48:57.353559 Set Vref, RX VrefLevel [Byte0]: 55
8396 06:48:57.358754 [Byte1]: 55
8397 06:48:57.361472
8398 06:48:57.361554 Set Vref, RX VrefLevel [Byte0]: 56
8399 06:48:57.364610 [Byte1]: 56
8400 06:48:57.368674
8401 06:48:57.368784 Set Vref, RX VrefLevel [Byte0]: 57
8402 06:48:57.372025 [Byte1]: 57
8403 06:48:57.376347
8404 06:48:57.376429 Set Vref, RX VrefLevel [Byte0]: 58
8405 06:48:57.379721 [Byte1]: 58
8406 06:48:57.384929
8407 06:48:57.385010 Set Vref, RX VrefLevel [Byte0]: 59
8408 06:48:57.387249 [Byte1]: 59
8409 06:48:57.391735
8410 06:48:57.391817 Set Vref, RX VrefLevel [Byte0]: 60
8411 06:48:57.395032 [Byte1]: 60
8412 06:48:57.399450
8413 06:48:57.399532 Set Vref, RX VrefLevel [Byte0]: 61
8414 06:48:57.402880 [Byte1]: 61
8415 06:48:57.406730
8416 06:48:57.406812 Set Vref, RX VrefLevel [Byte0]: 62
8417 06:48:57.410128 [Byte1]: 62
8418 06:48:57.414508
8419 06:48:57.414590 Set Vref, RX VrefLevel [Byte0]: 63
8420 06:48:57.417780 [Byte1]: 63
8421 06:48:57.424146
8422 06:48:57.424227 Set Vref, RX VrefLevel [Byte0]: 64
8423 06:48:57.425855 [Byte1]: 64
8424 06:48:57.430009
8425 06:48:57.430090 Set Vref, RX VrefLevel [Byte0]: 65
8426 06:48:57.433409 [Byte1]: 65
8427 06:48:57.437321
8428 06:48:57.437402 Set Vref, RX VrefLevel [Byte0]: 66
8429 06:48:57.440617 [Byte1]: 66
8430 06:48:57.446521
8431 06:48:57.446603 Set Vref, RX VrefLevel [Byte0]: 67
8432 06:48:57.448779 [Byte1]: 67
8433 06:48:57.452911
8434 06:48:57.452993 Set Vref, RX VrefLevel [Byte0]: 68
8435 06:48:57.457835 [Byte1]: 68
8436 06:48:57.460081
8437 06:48:57.460162 Set Vref, RX VrefLevel [Byte0]: 69
8438 06:48:57.463396 [Byte1]: 69
8439 06:48:57.469193
8440 06:48:57.469279 Set Vref, RX VrefLevel [Byte0]: 70
8441 06:48:57.471097 [Byte1]: 70
8442 06:48:57.475355
8443 06:48:57.475467 Set Vref, RX VrefLevel [Byte0]: 71
8444 06:48:57.479259 [Byte1]: 71
8445 06:48:57.483417
8446 06:48:57.483501 Set Vref, RX VrefLevel [Byte0]: 72
8447 06:48:57.486144 [Byte1]: 72
8448 06:48:57.490818
8449 06:48:57.490901 Set Vref, RX VrefLevel [Byte0]: 73
8450 06:48:57.494149 [Byte1]: 73
8451 06:48:57.498553
8452 06:48:57.498635 Set Vref, RX VrefLevel [Byte0]: 74
8453 06:48:57.502162 [Byte1]: 74
8454 06:48:57.506955
8455 06:48:57.507037 Set Vref, RX VrefLevel [Byte0]: 75
8456 06:48:57.509003 [Byte1]: 75
8457 06:48:57.513376
8458 06:48:57.513458 Set Vref, RX VrefLevel [Byte0]: 76
8459 06:48:57.516669 [Byte1]: 76
8460 06:48:57.521052
8461 06:48:57.521133 Final RX Vref Byte 0 = 63 to rank0
8462 06:48:57.524386 Final RX Vref Byte 1 = 54 to rank0
8463 06:48:57.528084 Final RX Vref Byte 0 = 63 to rank1
8464 06:48:57.531285 Final RX Vref Byte 1 = 54 to rank1==
8465 06:48:57.534524 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 06:48:57.541687 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8467 06:48:57.541770 ==
8468 06:48:57.541835 DQS Delay:
8469 06:48:57.543978 DQS0 = 0, DQS1 = 0
8470 06:48:57.544060 DQM Delay:
8471 06:48:57.544124 DQM0 = 128, DQM1 = 124
8472 06:48:57.547648 DQ Delay:
8473 06:48:57.550827 DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =126
8474 06:48:57.554059 DQ4 =130, DQ5 =138, DQ6 =134, DQ7 =126
8475 06:48:57.557743 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8476 06:48:57.560809 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8477 06:48:57.560917
8478 06:48:57.561009
8479 06:48:57.561122
8480 06:48:57.564595 [DramC_TX_OE_Calibration] TA2
8481 06:48:57.567245 Original DQ_B0 (3 6) =30, OEN = 27
8482 06:48:57.570768 Original DQ_B1 (3 6) =30, OEN = 27
8483 06:48:57.574312 24, 0x0, End_B0=24 End_B1=24
8484 06:48:57.574399 25, 0x0, End_B0=25 End_B1=25
8485 06:48:57.577011 26, 0x0, End_B0=26 End_B1=26
8486 06:48:57.580636 27, 0x0, End_B0=27 End_B1=27
8487 06:48:57.584241 28, 0x0, End_B0=28 End_B1=28
8488 06:48:57.586998 29, 0x0, End_B0=29 End_B1=29
8489 06:48:57.587081 30, 0x0, End_B0=30 End_B1=30
8490 06:48:57.590676 31, 0x5151, End_B0=30 End_B1=30
8491 06:48:57.593669 Byte0 end_step=30 best_step=27
8492 06:48:57.597415 Byte1 end_step=30 best_step=27
8493 06:48:57.600626 Byte0 TX OE(2T, 0.5T) = (3, 3)
8494 06:48:57.603656 Byte1 TX OE(2T, 0.5T) = (3, 3)
8495 06:48:57.603738
8496 06:48:57.603803
8497 06:48:57.610582 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8498 06:48:57.614179 CH1 RK0: MR19=303, MR18=2525
8499 06:48:57.620309 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8500 06:48:57.620391
8501 06:48:57.623348 ----->DramcWriteLeveling(PI) begin...
8502 06:48:57.623431 ==
8503 06:48:57.626859 Dram Type= 6, Freq= 0, CH_1, rank 1
8504 06:48:57.629922 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8505 06:48:57.630004 ==
8506 06:48:57.633880 Write leveling (Byte 0): 23 => 23
8507 06:48:57.637003 Write leveling (Byte 1): 20 => 20
8508 06:48:57.639991 DramcWriteLeveling(PI) end<-----
8509 06:48:57.640072
8510 06:48:57.640137 ==
8511 06:48:57.643245 Dram Type= 6, Freq= 0, CH_1, rank 1
8512 06:48:57.646617 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8513 06:48:57.646700 ==
8514 06:48:57.650180 [Gating] SW mode calibration
8515 06:48:57.656631 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8516 06:48:57.663515 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8517 06:48:57.666464 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
8518 06:48:57.673112 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8519 06:48:57.676513 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8520 06:48:57.680372 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8521 06:48:57.686348 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8522 06:48:57.689679 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8523 06:48:57.692996 0 12 24 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
8524 06:48:57.699576 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8525 06:48:57.702840 0 13 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8526 06:48:57.706140 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8527 06:48:57.712954 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8528 06:48:57.716817 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8529 06:48:57.719085 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8530 06:48:57.726047 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8531 06:48:57.730093 0 13 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
8532 06:48:57.732471 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8533 06:48:57.739710 0 14 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8534 06:48:57.742690 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8535 06:48:57.746331 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8536 06:48:57.752230 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8537 06:48:57.755670 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8538 06:48:57.758885 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8539 06:48:57.765472 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8540 06:48:57.769156 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8541 06:48:57.771876 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8542 06:48:57.778865 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8543 06:48:57.782141 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8544 06:48:57.785479 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8545 06:48:57.791764 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8546 06:48:57.795679 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8547 06:48:57.798468 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8548 06:48:57.805284 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8549 06:48:57.808313 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8550 06:48:57.812830 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8551 06:48:57.818442 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8552 06:48:57.821710 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8553 06:48:57.825321 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8554 06:48:57.831861 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8555 06:48:57.835092 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8556 06:48:57.837967 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8557 06:48:57.842200 Total UI for P1: 0, mck2ui 16
8558 06:48:57.845220 best dqsien dly found for B0: ( 1, 0, 24)
8559 06:48:57.851430 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8560 06:48:57.855351 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8561 06:48:57.857891 Total UI for P1: 0, mck2ui 16
8562 06:48:57.861284 best dqsien dly found for B1: ( 1, 0, 30)
8563 06:48:57.864613 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8564 06:48:57.867822 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8565 06:48:57.867921
8566 06:48:57.871236 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8567 06:48:57.874765 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8568 06:48:57.877540 [Gating] SW calibration Done
8569 06:48:57.877622 ==
8570 06:48:57.880880 Dram Type= 6, Freq= 0, CH_1, rank 1
8571 06:48:57.884311 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8572 06:48:57.888533 ==
8573 06:48:57.888641 RX Vref Scan: 0
8574 06:48:57.888771
8575 06:48:57.890809 RX Vref 0 -> 0, step: 1
8576 06:48:57.890891
8577 06:48:57.890955 RX Delay 0 -> 252, step: 8
8578 06:48:57.897873 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8579 06:48:57.900698 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8580 06:48:57.903825 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8581 06:48:57.907826 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8582 06:48:57.914168 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8583 06:48:57.917484 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8584 06:48:57.920379 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8585 06:48:57.923683 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8586 06:48:57.927131 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8587 06:48:57.933735 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8588 06:48:57.937335 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8589 06:48:57.940908 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8590 06:48:57.943846 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8591 06:48:57.947546 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8592 06:48:57.953323 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8593 06:48:57.957175 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8594 06:48:57.957258 ==
8595 06:48:57.960009 Dram Type= 6, Freq= 0, CH_1, rank 1
8596 06:48:57.963632 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8597 06:48:57.963715 ==
8598 06:48:57.967004 DQS Delay:
8599 06:48:57.967086 DQS0 = 0, DQS1 = 0
8600 06:48:57.967151 DQM Delay:
8601 06:48:57.969808 DQM0 = 130, DQM1 = 124
8602 06:48:57.969890 DQ Delay:
8603 06:48:57.973378 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =127
8604 06:48:57.976837 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =127
8605 06:48:57.983457 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
8606 06:48:57.987624 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8607 06:48:57.987705
8608 06:48:57.987770
8609 06:48:57.987831 ==
8610 06:48:57.990058 Dram Type= 6, Freq= 0, CH_1, rank 1
8611 06:48:57.993394 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8612 06:48:57.993502 ==
8613 06:48:57.993596
8614 06:48:57.993686
8615 06:48:57.996701 TX Vref Scan disable
8616 06:48:58.000286 == TX Byte 0 ==
8617 06:48:58.003345 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8618 06:48:58.006553 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8619 06:48:58.010648 == TX Byte 1 ==
8620 06:48:58.013810 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8621 06:48:58.016826 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8622 06:48:58.016908 ==
8623 06:48:58.019723 Dram Type= 6, Freq= 0, CH_1, rank 1
8624 06:48:58.022985 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8625 06:48:58.026112 ==
8626 06:48:58.038312
8627 06:48:58.041343 TX Vref early break, caculate TX vref
8628 06:48:58.044671 TX Vref=16, minBit 5, minWin=21, winSum=379
8629 06:48:58.048218 TX Vref=18, minBit 0, minWin=22, winSum=382
8630 06:48:58.051215 TX Vref=20, minBit 4, minWin=23, winSum=394
8631 06:48:58.054815 TX Vref=22, minBit 5, minWin=23, winSum=403
8632 06:48:58.057904 TX Vref=24, minBit 5, minWin=23, winSum=410
8633 06:48:58.064427 TX Vref=26, minBit 0, minWin=23, winSum=415
8634 06:48:58.067823 TX Vref=28, minBit 0, minWin=24, winSum=415
8635 06:48:58.071209 TX Vref=30, minBit 5, minWin=23, winSum=412
8636 06:48:58.074538 TX Vref=32, minBit 0, minWin=22, winSum=406
8637 06:48:58.078222 TX Vref=34, minBit 0, minWin=23, winSum=397
8638 06:48:58.081031 TX Vref=36, minBit 0, minWin=21, winSum=390
8639 06:48:58.087530 [TxChooseVref] Worse bit 0, Min win 24, Win sum 415, Final Vref 28
8640 06:48:58.087613
8641 06:48:58.091829 Final TX Range 0 Vref 28
8642 06:48:58.091923
8643 06:48:58.091989 ==
8644 06:48:58.094503 Dram Type= 6, Freq= 0, CH_1, rank 1
8645 06:48:58.098161 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8646 06:48:58.098244 ==
8647 06:48:58.101037
8648 06:48:58.101119
8649 06:48:58.101193 TX Vref Scan disable
8650 06:48:58.107515 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8651 06:48:58.107597 == TX Byte 0 ==
8652 06:48:58.111555 u2DelayCellOfst[0]=14 cells (4 PI)
8653 06:48:58.114453 u2DelayCellOfst[1]=7 cells (2 PI)
8654 06:48:58.117363 u2DelayCellOfst[2]=0 cells (0 PI)
8655 06:48:58.120689 u2DelayCellOfst[3]=7 cells (2 PI)
8656 06:48:58.124461 u2DelayCellOfst[4]=7 cells (2 PI)
8657 06:48:58.127869 u2DelayCellOfst[5]=14 cells (4 PI)
8658 06:48:58.131215 u2DelayCellOfst[6]=14 cells (4 PI)
8659 06:48:58.133846 u2DelayCellOfst[7]=3 cells (1 PI)
8660 06:48:58.137147 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8661 06:48:58.140771 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8662 06:48:58.143775 == TX Byte 1 ==
8663 06:48:58.147540 u2DelayCellOfst[8]=0 cells (0 PI)
8664 06:48:58.150527 u2DelayCellOfst[9]=3 cells (1 PI)
8665 06:48:58.150609 u2DelayCellOfst[10]=7 cells (2 PI)
8666 06:48:58.154281 u2DelayCellOfst[11]=3 cells (1 PI)
8667 06:48:58.157735 u2DelayCellOfst[12]=14 cells (4 PI)
8668 06:48:58.160918 u2DelayCellOfst[13]=17 cells (5 PI)
8669 06:48:58.164113 u2DelayCellOfst[14]=17 cells (5 PI)
8670 06:48:58.167602 u2DelayCellOfst[15]=14 cells (4 PI)
8671 06:48:58.173537 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8672 06:48:58.177173 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8673 06:48:58.177256 DramC Write-DBI on
8674 06:48:58.177321 ==
8675 06:48:58.180942 Dram Type= 6, Freq= 0, CH_1, rank 1
8676 06:48:58.187519 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8677 06:48:58.187601 ==
8678 06:48:58.187666
8679 06:48:58.187727
8680 06:48:58.189958 TX Vref Scan disable
8681 06:48:58.190039 == TX Byte 0 ==
8682 06:48:58.197758 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8683 06:48:58.197840 == TX Byte 1 ==
8684 06:48:58.200077 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8685 06:48:58.203514 DramC Write-DBI off
8686 06:48:58.203646
8687 06:48:58.203762 [DATLAT]
8688 06:48:58.206530 Freq=1600, CH1 RK1
8689 06:48:58.206638
8690 06:48:58.206738 DATLAT Default: 0xe
8691 06:48:58.210730 0, 0xFFFF, sum = 0
8692 06:48:58.210840 1, 0xFFFF, sum = 0
8693 06:48:58.213457 2, 0xFFFF, sum = 0
8694 06:48:58.213540 3, 0xFFFF, sum = 0
8695 06:48:58.216861 4, 0xFFFF, sum = 0
8696 06:48:58.216944 5, 0xFFFF, sum = 0
8697 06:48:58.220121 6, 0xFFFF, sum = 0
8698 06:48:58.220203 7, 0xFFFF, sum = 0
8699 06:48:58.223437 8, 0xFFFF, sum = 0
8700 06:48:58.223520 9, 0xFFFF, sum = 0
8701 06:48:58.227373 10, 0xFFFF, sum = 0
8702 06:48:58.231424 11, 0xFFFF, sum = 0
8703 06:48:58.231507 12, 0xF7F, sum = 0
8704 06:48:58.233818 13, 0x0, sum = 1
8705 06:48:58.233901 14, 0x0, sum = 2
8706 06:48:58.236721 15, 0x0, sum = 3
8707 06:48:58.236818 16, 0x0, sum = 4
8708 06:48:58.236887 best_step = 14
8709 06:48:58.236948
8710 06:48:58.240658 ==
8711 06:48:58.243255 Dram Type= 6, Freq= 0, CH_1, rank 1
8712 06:48:58.246927 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8713 06:48:58.247010 ==
8714 06:48:58.247076 RX Vref Scan: 0
8715 06:48:58.247137
8716 06:48:58.249737 RX Vref 0 -> 0, step: 1
8717 06:48:58.249820
8718 06:48:58.253643 RX Delay 3 -> 252, step: 4
8719 06:48:58.256561 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8720 06:48:58.259427 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8721 06:48:58.266972 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8722 06:48:58.270170 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8723 06:48:58.272611 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8724 06:48:58.275899 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8725 06:48:58.279374 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8726 06:48:58.285759 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8727 06:48:58.290060 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8728 06:48:58.292982 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8729 06:48:58.295931 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8730 06:48:58.303192 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8731 06:48:58.305821 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8732 06:48:58.308938 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8733 06:48:58.313097 iDelay=195, Bit 14, Center 136 (79 ~ 194) 116
8734 06:48:58.315838 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8735 06:48:58.315919 ==
8736 06:48:58.319379 Dram Type= 6, Freq= 0, CH_1, rank 1
8737 06:48:58.325887 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8738 06:48:58.325969 ==
8739 06:48:58.326035 DQS Delay:
8740 06:48:58.329116 DQS0 = 0, DQS1 = 0
8741 06:48:58.329198 DQM Delay:
8742 06:48:58.332716 DQM0 = 127, DQM1 = 122
8743 06:48:58.332811 DQ Delay:
8744 06:48:58.335737 DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =124
8745 06:48:58.339280 DQ4 =126, DQ5 =140, DQ6 =136, DQ7 =126
8746 06:48:58.342560 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8747 06:48:58.345516 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8748 06:48:58.345598
8749 06:48:58.345663
8750 06:48:58.345723
8751 06:48:58.349293 [DramC_TX_OE_Calibration] TA2
8752 06:48:58.352341 Original DQ_B0 (3 6) =30, OEN = 27
8753 06:48:58.355612 Original DQ_B1 (3 6) =30, OEN = 27
8754 06:48:58.358880 24, 0x0, End_B0=24 End_B1=24
8755 06:48:58.362045 25, 0x0, End_B0=25 End_B1=25
8756 06:48:58.362129 26, 0x0, End_B0=26 End_B1=26
8757 06:48:58.365464 27, 0x0, End_B0=27 End_B1=27
8758 06:48:58.368958 28, 0x0, End_B0=28 End_B1=28
8759 06:48:58.372749 29, 0x0, End_B0=29 End_B1=29
8760 06:48:58.372832 30, 0x0, End_B0=30 End_B1=30
8761 06:48:58.375568 31, 0x4141, End_B0=30 End_B1=30
8762 06:48:58.378960 Byte0 end_step=30 best_step=27
8763 06:48:58.382076 Byte1 end_step=30 best_step=27
8764 06:48:58.385398 Byte0 TX OE(2T, 0.5T) = (3, 3)
8765 06:48:58.388773 Byte1 TX OE(2T, 0.5T) = (3, 3)
8766 06:48:58.388855
8767 06:48:58.388920
8768 06:48:58.395781 [DQSOSCAuto] RK1, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
8769 06:48:58.399637 CH1 RK1: MR19=303, MR18=1919
8770 06:48:58.405258 CH1_RK1: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
8771 06:48:58.408969 [RxdqsGatingPostProcess] freq 1600
8772 06:48:58.411961 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8773 06:48:58.415705 Pre-setting of DQS Precalculation
8774 06:48:58.422167 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8775 06:48:58.428161 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8776 06:48:58.435262 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8777 06:48:58.435345
8778 06:48:58.435410
8779 06:48:58.438905 [Calibration Summary] 3200 Mbps
8780 06:48:58.442029 CH 0, Rank 0
8781 06:48:58.442111 SW Impedance : PASS
8782 06:48:58.445094 DUTY Scan : NO K
8783 06:48:58.448631 ZQ Calibration : PASS
8784 06:48:58.448718 Jitter Meter : NO K
8785 06:48:58.452083 CBT Training : PASS
8786 06:48:58.452165 Write leveling : PASS
8787 06:48:58.455148 RX DQS gating : PASS
8788 06:48:58.458455 RX DQ/DQS(RDDQC) : PASS
8789 06:48:58.458537 TX DQ/DQS : PASS
8790 06:48:58.461631 RX DATLAT : PASS
8791 06:48:58.465436 RX DQ/DQS(Engine): PASS
8792 06:48:58.465517 TX OE : PASS
8793 06:48:58.468372 All Pass.
8794 06:48:58.468453
8795 06:48:58.468518 CH 0, Rank 1
8796 06:48:58.471908 SW Impedance : PASS
8797 06:48:58.471990 DUTY Scan : NO K
8798 06:48:58.475498 ZQ Calibration : PASS
8799 06:48:58.478646 Jitter Meter : NO K
8800 06:48:58.478728 CBT Training : PASS
8801 06:48:58.481623 Write leveling : PASS
8802 06:48:58.484699 RX DQS gating : PASS
8803 06:48:58.484803 RX DQ/DQS(RDDQC) : PASS
8804 06:48:58.488521 TX DQ/DQS : PASS
8805 06:48:58.491816 RX DATLAT : PASS
8806 06:48:58.491897 RX DQ/DQS(Engine): PASS
8807 06:48:58.494934 TX OE : PASS
8808 06:48:58.495016 All Pass.
8809 06:48:58.495082
8810 06:48:58.498028 CH 1, Rank 0
8811 06:48:58.498109 SW Impedance : PASS
8812 06:48:58.501855 DUTY Scan : NO K
8813 06:48:58.505559 ZQ Calibration : PASS
8814 06:48:58.505641 Jitter Meter : NO K
8815 06:48:58.508424 CBT Training : PASS
8816 06:48:58.508506 Write leveling : PASS
8817 06:48:58.511792 RX DQS gating : PASS
8818 06:48:58.515341 RX DQ/DQS(RDDQC) : PASS
8819 06:48:58.515423 TX DQ/DQS : PASS
8820 06:48:58.518075 RX DATLAT : PASS
8821 06:48:58.521789 RX DQ/DQS(Engine): PASS
8822 06:48:58.521871 TX OE : PASS
8823 06:48:58.525292 All Pass.
8824 06:48:58.525374
8825 06:48:58.525439 CH 1, Rank 1
8826 06:48:58.527964 SW Impedance : PASS
8827 06:48:58.528045 DUTY Scan : NO K
8828 06:48:58.531463 ZQ Calibration : PASS
8829 06:48:58.534690 Jitter Meter : NO K
8830 06:48:58.534772 CBT Training : PASS
8831 06:48:58.538063 Write leveling : PASS
8832 06:48:58.541439 RX DQS gating : PASS
8833 06:48:58.541521 RX DQ/DQS(RDDQC) : PASS
8834 06:48:58.544483 TX DQ/DQS : PASS
8835 06:48:58.547515 RX DATLAT : PASS
8836 06:48:58.547598 RX DQ/DQS(Engine): PASS
8837 06:48:58.551459 TX OE : PASS
8838 06:48:58.551542 All Pass.
8839 06:48:58.551607
8840 06:48:58.554638 DramC Write-DBI on
8841 06:48:58.557806 PER_BANK_REFRESH: Hybrid Mode
8842 06:48:58.558005 TX_TRACKING: ON
8843 06:48:58.568286 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8844 06:48:58.574271 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8845 06:48:58.581030 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8846 06:48:58.584033 [FAST_K] Save calibration result to emmc
8847 06:48:58.587318 sync common calibartion params.
8848 06:48:58.590612 sync cbt_mode0:0, 1:0
8849 06:48:58.594390 dram_init: ddr_geometry: 0
8850 06:48:58.594478 dram_init: ddr_geometry: 0
8851 06:48:58.597331 dram_init: ddr_geometry: 0
8852 06:48:58.600510 0:dram_rank_size:80000000
8853 06:48:58.600594 1:dram_rank_size:80000000
8854 06:48:58.607167 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8855 06:48:58.611105 DFS_SHUFFLE_HW_MODE: ON
8856 06:48:58.613814 dramc_set_vcore_voltage set vcore to 725000
8857 06:48:58.617002 Read voltage for 1600, 0
8858 06:48:58.617084 Vio18 = 0
8859 06:48:58.617149 Vcore = 725000
8860 06:48:58.620562 Vdram = 0
8861 06:48:58.620643 Vddq = 0
8862 06:48:58.620713 Vmddr = 0
8863 06:48:58.623597 switch to 3200 Mbps bootup
8864 06:48:58.623679 [DramcRunTimeConfig]
8865 06:48:58.628631 PHYPLL
8866 06:48:58.628718 DPM_CONTROL_AFTERK: ON
8867 06:48:58.630377 PER_BANK_REFRESH: ON
8868 06:48:58.633417 REFRESH_OVERHEAD_REDUCTION: ON
8869 06:48:58.633499 CMD_PICG_NEW_MODE: OFF
8870 06:48:58.637621 XRTWTW_NEW_MODE: ON
8871 06:48:58.637742 XRTRTR_NEW_MODE: ON
8872 06:48:58.640799 TX_TRACKING: ON
8873 06:48:58.640882 RDSEL_TRACKING: OFF
8874 06:48:58.643790 DQS Precalculation for DVFS: ON
8875 06:48:58.647384 RX_TRACKING: OFF
8876 06:48:58.647466 HW_GATING DBG: ON
8877 06:48:58.650006 ZQCS_ENABLE_LP4: ON
8878 06:48:58.650088 RX_PICG_NEW_MODE: ON
8879 06:48:58.653495 TX_PICG_NEW_MODE: ON
8880 06:48:58.657041 ENABLE_RX_DCM_DPHY: ON
8881 06:48:58.657123 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8882 06:48:58.660889 DUMMY_READ_FOR_TRACKING: OFF
8883 06:48:58.663054 !!! SPM_CONTROL_AFTERK: OFF
8884 06:48:58.666804 !!! SPM could not control APHY
8885 06:48:58.669936 IMPEDANCE_TRACKING: ON
8886 06:48:58.670017 TEMP_SENSOR: ON
8887 06:48:58.673675 HW_SAVE_FOR_SR: OFF
8888 06:48:58.673757 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8889 06:48:58.680432 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8890 06:48:58.680514 Read ODT Tracking: ON
8891 06:48:58.683318 Refresh Rate DeBounce: ON
8892 06:48:58.683400 DFS_NO_QUEUE_FLUSH: ON
8893 06:48:58.686516 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8894 06:48:58.689676 ENABLE_DFS_RUNTIME_MRW: OFF
8895 06:48:58.693389 DDR_RESERVE_NEW_MODE: ON
8896 06:48:58.693480 MR_CBT_SWITCH_FREQ: ON
8897 06:48:58.696364 =========================
8898 06:48:58.716636 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8899 06:48:58.719443 dram_init: ddr_geometry: 0
8900 06:48:58.737038 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8901 06:48:58.740662 dram_init: dram init end (result: 0)
8902 06:48:58.747073 DRAM-K: Full calibration passed in 23389 msecs
8903 06:48:58.750599 MRC: failed to locate region type 0.
8904 06:48:58.750682 DRAM rank0 size:0x80000000,
8905 06:48:58.754018 DRAM rank1 size=0x80000000
8906 06:48:58.763538 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8907 06:48:58.770008 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8908 06:48:58.777381 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8909 06:48:58.783404 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8910 06:48:58.787313 DRAM rank0 size:0x80000000,
8911 06:48:58.790160 DRAM rank1 size=0x80000000
8912 06:48:58.790242 CBMEM:
8913 06:48:58.793533 IMD: root @ 0xfffff000 254 entries.
8914 06:48:58.796566 IMD: root @ 0xffffec00 62 entries.
8915 06:48:58.800602 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8916 06:48:58.802963 WARNING: RO_VPD is uninitialized or empty.
8917 06:48:58.810096 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8918 06:48:58.817043 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8919 06:48:58.829412 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8920 06:48:58.840661 BS: romstage times (exec / console): total (unknown) / 22936 ms
8921 06:48:58.840784
8922 06:48:58.840850
8923 06:48:58.852110 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8924 06:48:58.854624 ARM64: Exception handlers installed.
8925 06:48:58.857395 ARM64: Testing exception
8926 06:48:58.860242 ARM64: Done test exception
8927 06:48:58.860324 Enumerating buses...
8928 06:48:58.863796 Show all devs... Before device enumeration.
8929 06:48:58.867292 Root Device: enabled 1
8930 06:48:58.870763 CPU_CLUSTER: 0: enabled 1
8931 06:48:58.870845 CPU: 00: enabled 1
8932 06:48:58.873706 Compare with tree...
8933 06:48:58.873788 Root Device: enabled 1
8934 06:48:58.877143 CPU_CLUSTER: 0: enabled 1
8935 06:48:58.880550 CPU: 00: enabled 1
8936 06:48:58.880632 Root Device scanning...
8937 06:48:58.883469 scan_static_bus for Root Device
8938 06:48:58.887189 CPU_CLUSTER: 0 enabled
8939 06:48:58.890331 scan_static_bus for Root Device done
8940 06:48:58.893995 scan_bus: bus Root Device finished in 8 msecs
8941 06:48:58.894077 done
8942 06:48:58.900646 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8943 06:48:58.903694 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8944 06:48:58.910131 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8945 06:48:58.913508 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8946 06:48:58.916916 Allocating resources...
8947 06:48:58.920331 Reading resources...
8948 06:48:58.923794 Root Device read_resources bus 0 link: 0
8949 06:48:58.923876 DRAM rank0 size:0x80000000,
8950 06:48:58.927460 DRAM rank1 size=0x80000000
8951 06:48:58.930172 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8952 06:48:58.933283 CPU: 00 missing read_resources
8953 06:48:58.936943 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8954 06:48:58.943424 Root Device read_resources bus 0 link: 0 done
8955 06:48:58.943506 Done reading resources.
8956 06:48:58.950484 Show resources in subtree (Root Device)...After reading.
8957 06:48:58.953684 Root Device child on link 0 CPU_CLUSTER: 0
8958 06:48:58.956611 CPU_CLUSTER: 0 child on link 0 CPU: 00
8959 06:48:58.966903 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8960 06:48:58.966987 CPU: 00
8961 06:48:58.970691 Root Device assign_resources, bus 0 link: 0
8962 06:48:58.973257 CPU_CLUSTER: 0 missing set_resources
8963 06:48:58.980145 Root Device assign_resources, bus 0 link: 0 done
8964 06:48:58.980226 Done setting resources.
8965 06:48:58.987163 Show resources in subtree (Root Device)...After assigning values.
8966 06:48:58.989704 Root Device child on link 0 CPU_CLUSTER: 0
8967 06:48:58.993329 CPU_CLUSTER: 0 child on link 0 CPU: 00
8968 06:48:59.002991 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8969 06:48:59.003075 CPU: 00
8970 06:48:59.006388 Done allocating resources.
8971 06:48:59.009881 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8972 06:48:59.013323 Enabling resources...
8973 06:48:59.013405 done.
8974 06:48:59.020144 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8975 06:48:59.020226 Initializing devices...
8976 06:48:59.023134 Root Device init
8977 06:48:59.023216 init hardware done!
8978 06:48:59.026167 0x00000018: ctrlr->caps
8979 06:48:59.029272 52.000 MHz: ctrlr->f_max
8980 06:48:59.029355 0.400 MHz: ctrlr->f_min
8981 06:48:59.033533 0x40ff8080: ctrlr->voltages
8982 06:48:59.036762 sclk: 390625
8983 06:48:59.036844 Bus Width = 1
8984 06:48:59.036910 sclk: 390625
8985 06:48:59.039514 Bus Width = 1
8986 06:48:59.039595 Early init status = 3
8987 06:48:59.046735 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8988 06:48:59.049370 in-header: 03 fb 00 00 01 00 00 00
8989 06:48:59.049452 in-data: 01
8990 06:48:59.056358 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8991 06:48:59.058828 in-header: 03 fb 00 00 01 00 00 00
8992 06:48:59.062269 in-data: 01
8993 06:48:59.065678 [SSUSB] Setting up USB HOST controller...
8994 06:48:59.068949 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8995 06:48:59.073055 [SSUSB] phy power-on done.
8996 06:48:59.075736 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8997 06:48:59.082662 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8998 06:48:59.086554 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8999 06:48:59.092443 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9000 06:48:59.098616 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9001 06:48:59.105259 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9002 06:48:59.112226 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9003 06:48:59.118570 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9004 06:48:59.121727 SPM: binary array size = 0x9dc
9005 06:48:59.125692 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9006 06:48:59.131568 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9007 06:48:59.138530 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9008 06:48:59.141872 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9009 06:48:59.148424 configure_display: Starting display init
9010 06:48:59.182405 anx7625_power_on_init: Init interface.
9011 06:48:59.185392 anx7625_disable_pd_protocol: Disabled PD feature.
9012 06:48:59.188530 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9013 06:48:59.217817 anx7625_start_dp_work: Secure OCM version=00
9014 06:48:59.219639 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9015 06:48:59.234900 sp_tx_get_edid_block: EDID Block = 1
9016 06:48:59.337201 Extracted contents:
9017 06:48:59.340344 header: 00 ff ff ff ff ff ff 00
9018 06:48:59.343578 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9019 06:48:59.347394 version: 01 04
9020 06:48:59.350985 basic params: 95 1f 11 78 0a
9021 06:48:59.353320 chroma info: 76 90 94 55 54 90 27 21 50 54
9022 06:48:59.356801 established: 00 00 00
9023 06:48:59.364192 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9024 06:48:59.366737 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9025 06:48:59.373688 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9026 06:48:59.380696 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9027 06:48:59.386341 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9028 06:48:59.390873 extensions: 00
9029 06:48:59.390954 checksum: fb
9030 06:48:59.391054
9031 06:48:59.396366 Manufacturer: IVO Model 57d Serial Number 0
9032 06:48:59.396447 Made week 0 of 2020
9033 06:48:59.399628 EDID version: 1.4
9034 06:48:59.399766 Digital display
9035 06:48:59.403266 6 bits per primary color channel
9036 06:48:59.403348 DisplayPort interface
9037 06:48:59.406617 Maximum image size: 31 cm x 17 cm
9038 06:48:59.410157 Gamma: 220%
9039 06:48:59.410237 Check DPMS levels
9040 06:48:59.416539 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9041 06:48:59.419806 First detailed timing is preferred timing
9042 06:48:59.419903 Established timings supported:
9043 06:48:59.422791 Standard timings supported:
9044 06:48:59.425943 Detailed timings
9045 06:48:59.429614 Hex of detail: 383680a07038204018303c0035ae10000019
9046 06:48:59.436671 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9047 06:48:59.439114 0780 0798 07c8 0820 hborder 0
9048 06:48:59.442674 0438 043b 0447 0458 vborder 0
9049 06:48:59.446479 -hsync -vsync
9050 06:48:59.446560 Did detailed timing
9051 06:48:59.452575 Hex of detail: 000000000000000000000000000000000000
9052 06:48:59.455746 Manufacturer-specified data, tag 0
9053 06:48:59.459236 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9054 06:48:59.462720 ASCII string: InfoVision
9055 06:48:59.466381 Hex of detail: 000000fe00523134304e574635205248200a
9056 06:48:59.469599 ASCII string: R140NWF5 RH
9057 06:48:59.469680 Checksum
9058 06:48:59.472440 Checksum: 0xfb (valid)
9059 06:48:59.475685 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9060 06:48:59.479277 DSI data_rate: 832800000 bps
9061 06:48:59.486217 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9062 06:48:59.488989 anx7625_parse_edid: pixelclock(138800).
9063 06:48:59.492411 hactive(1920), hsync(48), hfp(24), hbp(88)
9064 06:48:59.495778 vactive(1080), vsync(12), vfp(3), vbp(17)
9065 06:48:59.499170 anx7625_dsi_config: config dsi.
9066 06:48:59.505747 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9067 06:48:59.519036 anx7625_dsi_config: success to config DSI
9068 06:48:59.522513 anx7625_dp_start: MIPI phy setup OK.
9069 06:48:59.526158 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9070 06:48:59.529648 mtk_ddp_mode_set invalid vrefresh 60
9071 06:48:59.533483 main_disp_path_setup
9072 06:48:59.533564 ovl_layer_smi_id_en
9073 06:48:59.535815 ovl_layer_smi_id_en
9074 06:48:59.535897 ccorr_config
9075 06:48:59.535963 aal_config
9076 06:48:59.539657 gamma_config
9077 06:48:59.539738 postmask_config
9078 06:48:59.542386 dither_config
9079 06:48:59.546253 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9080 06:48:59.552648 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9081 06:48:59.555623 Root Device init finished in 529 msecs
9082 06:48:59.559179 CPU_CLUSTER: 0 init
9083 06:48:59.565365 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9084 06:48:59.569042 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9085 06:48:59.573802 APU_MBOX 0x190000b0 = 0x10001
9086 06:48:59.575499 APU_MBOX 0x190001b0 = 0x10001
9087 06:48:59.578855 APU_MBOX 0x190005b0 = 0x10001
9088 06:48:59.582665 APU_MBOX 0x190006b0 = 0x10001
9089 06:48:59.586153 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9090 06:48:59.598373 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9091 06:48:59.610235 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9092 06:48:59.617118 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9093 06:48:59.628685 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9094 06:48:59.637933 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9095 06:48:59.640979 CPU_CLUSTER: 0 init finished in 81 msecs
9096 06:48:59.644516 Devices initialized
9097 06:48:59.647788 Show all devs... After init.
9098 06:48:59.647870 Root Device: enabled 1
9099 06:48:59.651665 CPU_CLUSTER: 0: enabled 1
9100 06:48:59.654167 CPU: 00: enabled 1
9101 06:48:59.657951 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9102 06:48:59.660933 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9103 06:48:59.664031 ELOG: NV offset 0x57f000 size 0x1000
9104 06:48:59.670999 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9105 06:48:59.678016 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9106 06:48:59.681237 ELOG: Event(17) added with size 13 at 2024-02-03 06:49:03 UTC
9107 06:48:59.685035 out: cmd=0x121: 03 db 21 01 00 00 00 00
9108 06:48:59.687844 in-header: 03 39 00 00 2c 00 00 00
9109 06:48:59.701432 in-data: 2a 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9110 06:48:59.709136 ELOG: Event(A1) added with size 10 at 2024-02-03 06:49:03 UTC
9111 06:48:59.715906 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9112 06:48:59.720964 ELOG: Event(A0) added with size 9 at 2024-02-03 06:49:03 UTC
9113 06:48:59.724287 elog_add_boot_reason: Logged dev mode boot
9114 06:48:59.728292 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9115 06:48:59.731396 Finalize devices...
9116 06:48:59.731479 Devices finalized
9117 06:48:59.737689 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9118 06:48:59.741469 Writing coreboot table at 0xffe64000
9119 06:48:59.744079 0. 000000000010a000-0000000000113fff: RAMSTAGE
9120 06:48:59.747412 1. 0000000040000000-00000000400fffff: RAM
9121 06:48:59.754393 2. 0000000040100000-000000004032afff: RAMSTAGE
9122 06:48:59.757632 3. 000000004032b000-00000000545fffff: RAM
9123 06:48:59.762090 4. 0000000054600000-000000005465ffff: BL31
9124 06:48:59.764458 5. 0000000054660000-00000000ffe63fff: RAM
9125 06:48:59.770454 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9126 06:48:59.774567 7. 0000000100000000-000000013fffffff: RAM
9127 06:48:59.777286 Passing 5 GPIOs to payload:
9128 06:48:59.781541 NAME | PORT | POLARITY | VALUE
9129 06:48:59.783738 EC in RW | 0x000000aa | low | undefined
9130 06:48:59.790561 EC interrupt | 0x00000005 | low | undefined
9131 06:48:59.794076 TPM interrupt | 0x000000ab | high | undefined
9132 06:48:59.800664 SD card detect | 0x00000011 | high | undefined
9133 06:48:59.804039 speaker enable | 0x00000093 | high | undefined
9134 06:48:59.807427 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9135 06:48:59.810772 in-header: 03 ef 00 00 02 00 00 00
9136 06:48:59.814220 in-data: 0c 00
9137 06:48:59.814301 ADC[4]: Raw value=669327 ID=5
9138 06:48:59.817263 ADC[3]: Raw value=212549 ID=1
9139 06:48:59.821284 RAM Code: 0x51
9140 06:48:59.821365 ADC[6]: Raw value=74410 ID=0
9141 06:48:59.823921 ADC[5]: Raw value=211812 ID=1
9142 06:48:59.827797 SKU Code: 0x1
9143 06:48:59.830454 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 128c
9144 06:48:59.833626 coreboot table: 964 bytes.
9145 06:48:59.837013 IMD ROOT 0. 0xfffff000 0x00001000
9146 06:48:59.840840 IMD SMALL 1. 0xffffe000 0x00001000
9147 06:48:59.844534 RO MCACHE 2. 0xffffc000 0x00001104
9148 06:48:59.847133 CONSOLE 3. 0xfff7c000 0x00080000
9149 06:48:59.850463 FMAP 4. 0xfff7b000 0x00000452
9150 06:48:59.853471 TIME STAMP 5. 0xfff7a000 0x00000910
9151 06:48:59.856891 VBOOT WORK 6. 0xfff66000 0x00014000
9152 06:48:59.860491 RAMOOPS 7. 0xffe66000 0x00100000
9153 06:48:59.863510 COREBOOT 8. 0xffe64000 0x00002000
9154 06:48:59.867453 IMD small region:
9155 06:48:59.870100 IMD ROOT 0. 0xffffec00 0x00000400
9156 06:48:59.873685 VPD 1. 0xffffeb80 0x0000006c
9157 06:48:59.877224 MMC STATUS 2. 0xffffeb60 0x00000004
9158 06:48:59.880218 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9159 06:48:59.884049 Probing TPM: done!
9160 06:48:59.886973 Connected to device vid:did:rid of 1ae0:0028:00
9161 06:48:59.897352 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9162 06:48:59.900532 Initialized TPM device CR50 revision 0
9163 06:48:59.904056 Checking cr50 for pending updates
9164 06:48:59.907532 Reading cr50 TPM mode
9165 06:48:59.917621 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9166 06:48:59.923205 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9167 06:48:59.963244 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9168 06:48:59.966265 Checking segment from ROM address 0x40100000
9169 06:48:59.970048 Checking segment from ROM address 0x4010001c
9170 06:48:59.976281 Loading segment from ROM address 0x40100000
9171 06:48:59.976364 code (compression=0)
9172 06:48:59.983467 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9173 06:48:59.993475 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9174 06:48:59.993558 it's not compressed!
9175 06:48:59.999599 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9176 06:49:00.003893 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9177 06:49:00.024105 Loading segment from ROM address 0x4010001c
9178 06:49:00.024188 Entry Point 0x80000000
9179 06:49:00.026764 Loaded segments
9180 06:49:00.030413 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9181 06:49:00.037054 Jumping to boot code at 0x80000000(0xffe64000)
9182 06:49:00.043376 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9183 06:49:00.049884 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9184 06:49:00.058689 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9185 06:49:00.062131 Checking segment from ROM address 0x40100000
9186 06:49:00.064620 Checking segment from ROM address 0x4010001c
9187 06:49:00.071479 Loading segment from ROM address 0x40100000
9188 06:49:00.071563 code (compression=1)
9189 06:49:00.077895 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9190 06:49:00.088057 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9191 06:49:00.088143 using LZMA
9192 06:49:00.096471 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9193 06:49:00.103338 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9194 06:49:00.106389 Loading segment from ROM address 0x4010001c
9195 06:49:00.106472 Entry Point 0x54601000
9196 06:49:00.110157 Loaded segments
9197 06:49:00.112809 NOTICE: MT8192 bl31_setup
9198 06:49:00.120493 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9199 06:49:00.123004 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9200 06:49:00.126935 WARNING: region 0:
9201 06:49:00.130394 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9202 06:49:00.130501 WARNING: region 1:
9203 06:49:00.136398 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9204 06:49:00.139930 WARNING: region 2:
9205 06:49:00.143190 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9206 06:49:00.147116 WARNING: region 3:
9207 06:49:00.149991 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9208 06:49:00.153345 WARNING: region 4:
9209 06:49:00.159741 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9210 06:49:00.159822 WARNING: region 5:
9211 06:49:00.163367 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9212 06:49:00.167017 WARNING: region 6:
9213 06:49:00.170171 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9214 06:49:00.173247 WARNING: region 7:
9215 06:49:00.176815 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9216 06:49:00.183446 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9217 06:49:00.186626 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9218 06:49:00.189978 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9219 06:49:00.196361 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9220 06:49:00.200654 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9221 06:49:00.203381 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9222 06:49:00.210350 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9223 06:49:00.213587 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9224 06:49:00.220172 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9225 06:49:00.224118 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9226 06:49:00.226485 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9227 06:49:00.233819 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9228 06:49:00.236553 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9229 06:49:00.241201 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9230 06:49:00.246718 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9231 06:49:00.249949 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9232 06:49:00.256318 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9233 06:49:00.260330 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9234 06:49:00.263397 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9235 06:49:00.270202 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9236 06:49:00.273474 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9237 06:49:00.277061 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9238 06:49:00.283327 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9239 06:49:00.286616 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9240 06:49:00.293487 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9241 06:49:00.296656 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9242 06:49:00.299993 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9243 06:49:00.306411 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9244 06:49:00.309940 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9245 06:49:00.317421 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9246 06:49:00.320642 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9247 06:49:00.323421 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9248 06:49:00.329813 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9249 06:49:00.332943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9250 06:49:00.336322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9251 06:49:00.339591 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9252 06:49:00.346324 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9253 06:49:00.349870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9254 06:49:00.352883 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9255 06:49:00.356087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9256 06:49:00.362659 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9257 06:49:00.366391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9258 06:49:00.369475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9259 06:49:00.372616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9260 06:49:00.379785 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9261 06:49:00.382854 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9262 06:49:00.386342 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9263 06:49:00.389839 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9264 06:49:00.396434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9265 06:49:00.400030 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9266 06:49:00.406180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9267 06:49:00.409430 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9268 06:49:00.416413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9269 06:49:00.420284 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9270 06:49:00.423109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9271 06:49:00.429257 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9272 06:49:00.432890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9273 06:49:00.439811 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9274 06:49:00.443546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9275 06:49:00.449824 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9276 06:49:00.453160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9277 06:49:00.456377 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9278 06:49:00.463038 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9279 06:49:00.466260 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9280 06:49:00.473116 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9281 06:49:00.476307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9282 06:49:00.483106 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9283 06:49:00.486262 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9284 06:49:00.489692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9285 06:49:00.496474 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9286 06:49:00.499816 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9287 06:49:00.506445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9288 06:49:00.509921 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9289 06:49:00.516784 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9290 06:49:00.519490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9291 06:49:00.522774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9292 06:49:00.530247 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9293 06:49:00.533363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9294 06:49:00.540607 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9295 06:49:00.542965 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9296 06:49:00.549162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9297 06:49:00.553133 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9298 06:49:00.559102 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9299 06:49:00.562511 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9300 06:49:00.566053 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9301 06:49:00.572832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9302 06:49:00.575848 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9303 06:49:00.583958 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9304 06:49:00.585844 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9305 06:49:00.592550 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9306 06:49:00.596236 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9307 06:49:00.599384 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9308 06:49:00.606624 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9309 06:49:00.609017 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9310 06:49:00.615751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9311 06:49:00.619559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9312 06:49:00.625607 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9313 06:49:00.628977 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9314 06:49:00.632282 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9315 06:49:00.636451 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9316 06:49:00.642334 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9317 06:49:00.646334 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9318 06:49:00.648994 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9319 06:49:00.655850 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9320 06:49:00.659197 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9321 06:49:00.666098 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9322 06:49:00.669521 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9323 06:49:00.672041 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9324 06:49:00.679002 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9325 06:49:00.682303 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9326 06:49:00.689221 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9327 06:49:00.691916 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9328 06:49:00.696225 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9329 06:49:00.702115 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9330 06:49:00.705229 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9331 06:49:00.712418 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9332 06:49:00.715777 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9333 06:49:00.718906 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9334 06:49:00.721935 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9335 06:49:00.728932 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9336 06:49:00.732244 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9337 06:49:00.735597 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9338 06:49:00.738438 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9339 06:49:00.745455 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9340 06:49:00.748903 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9341 06:49:00.751908 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9342 06:49:00.758759 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9343 06:49:00.761903 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9344 06:49:00.769295 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9345 06:49:00.771765 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9346 06:49:00.775715 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9347 06:49:00.782540 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9348 06:49:00.785207 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9349 06:49:00.791559 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9350 06:49:00.794850 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9351 06:49:00.798508 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9352 06:49:00.805049 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9353 06:49:00.808113 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9354 06:49:00.814813 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9355 06:49:00.818123 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9356 06:49:00.822730 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9357 06:49:00.828256 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9358 06:49:00.831593 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9359 06:49:00.838028 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9360 06:49:00.841592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9361 06:49:00.845743 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9362 06:49:00.851572 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9363 06:49:00.854570 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9364 06:49:00.858104 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9365 06:49:00.865530 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9366 06:49:00.868074 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9367 06:49:00.874927 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9368 06:49:00.878370 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9369 06:49:00.881801 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9370 06:49:00.888277 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9371 06:49:00.891476 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9372 06:49:00.894741 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9373 06:49:00.901985 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9374 06:49:00.906008 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9375 06:49:00.911357 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9376 06:49:00.915176 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9377 06:49:00.918143 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9378 06:49:00.925031 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9379 06:49:00.927980 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9380 06:49:00.934783 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9381 06:49:00.938198 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9382 06:49:00.942025 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9383 06:49:00.948592 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9384 06:49:00.951875 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9385 06:49:00.957867 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9386 06:49:00.961213 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9387 06:49:00.964923 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9388 06:49:00.971538 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9389 06:49:00.974658 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9390 06:49:00.981430 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9391 06:49:00.985342 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9392 06:49:00.988872 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9393 06:49:00.994385 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9394 06:49:00.998222 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9395 06:49:01.000831 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9396 06:49:01.008364 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9397 06:49:01.011123 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9398 06:49:01.018354 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9399 06:49:01.021141 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9400 06:49:01.027857 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9401 06:49:01.030702 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9402 06:49:01.035041 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9403 06:49:01.041740 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9404 06:49:01.044027 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9405 06:49:01.050610 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9406 06:49:01.054571 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9407 06:49:01.057424 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9408 06:49:01.064287 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9409 06:49:01.067019 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9410 06:49:01.074149 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9411 06:49:01.077477 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9412 06:49:01.080194 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9413 06:49:01.086979 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9414 06:49:01.090469 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9415 06:49:01.096891 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9416 06:49:01.100207 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9417 06:49:01.107571 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9418 06:49:01.111372 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9419 06:49:01.113667 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9420 06:49:01.120170 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9421 06:49:01.123701 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9422 06:49:01.130460 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9423 06:49:01.133678 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9424 06:49:01.136810 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9425 06:49:01.143373 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9426 06:49:01.146686 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9427 06:49:01.153372 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9428 06:49:01.156606 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9429 06:49:01.163586 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9430 06:49:01.167784 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9431 06:49:01.171050 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9432 06:49:01.177188 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9433 06:49:01.179638 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9434 06:49:01.187382 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9435 06:49:01.189701 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9436 06:49:01.196849 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9437 06:49:01.199895 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9438 06:49:01.203000 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9439 06:49:01.209678 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9440 06:49:01.213252 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9441 06:49:01.219576 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9442 06:49:01.223090 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9443 06:49:01.226709 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9444 06:49:01.234325 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9445 06:49:01.236492 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9446 06:49:01.239788 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9447 06:49:01.243334 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9448 06:49:01.249520 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9449 06:49:01.253022 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9450 06:49:01.255958 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9451 06:49:01.262707 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9452 06:49:01.266048 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9453 06:49:01.273049 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9454 06:49:01.277571 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9455 06:49:01.280020 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9456 06:49:01.286021 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9457 06:49:01.289267 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9458 06:49:01.292834 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9459 06:49:01.298926 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9460 06:49:01.302969 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9461 06:49:01.305613 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9462 06:49:01.313239 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9463 06:49:01.315652 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9464 06:49:01.319523 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9465 06:49:01.325578 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9466 06:49:01.329185 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9467 06:49:01.335912 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9468 06:49:01.339608 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9469 06:49:01.342348 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9470 06:49:01.349105 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9471 06:49:01.352105 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9472 06:49:01.359318 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9473 06:49:01.362338 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9474 06:49:01.365168 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9475 06:49:01.372230 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9476 06:49:01.375284 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9477 06:49:01.379320 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9478 06:49:01.385863 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9479 06:49:01.388746 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9480 06:49:01.392487 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9481 06:49:01.398419 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9482 06:49:01.401959 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9483 06:49:01.408848 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9484 06:49:01.412870 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9485 06:49:01.415933 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9486 06:49:01.418850 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9487 06:49:01.426010 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9488 06:49:01.428246 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9489 06:49:01.431437 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9490 06:49:01.435080 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9491 06:49:01.438016 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9492 06:49:01.444611 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9493 06:49:01.448721 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9494 06:49:01.451673 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9495 06:49:01.459262 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9496 06:49:01.461552 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9497 06:49:01.465194 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9498 06:49:01.471181 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9499 06:49:01.474667 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9500 06:49:01.478894 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9501 06:49:01.485205 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9502 06:49:01.488331 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9503 06:49:01.494527 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9504 06:49:01.497742 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9505 06:49:01.500900 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9506 06:49:01.507671 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9507 06:49:01.510787 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9508 06:49:01.518191 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9509 06:49:01.521296 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9510 06:49:01.528764 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9511 06:49:01.530788 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9512 06:49:01.534570 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9513 06:49:01.541536 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9514 06:49:01.545096 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9515 06:49:01.551107 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9516 06:49:01.554440 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9517 06:49:01.557297 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9518 06:49:01.564413 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9519 06:49:01.567269 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9520 06:49:01.574187 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9521 06:49:01.577272 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9522 06:49:01.581000 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9523 06:49:01.587351 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9524 06:49:01.590854 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9525 06:49:01.597225 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9526 06:49:01.601546 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9527 06:49:01.606955 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9528 06:49:01.610534 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9529 06:49:01.614036 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9530 06:49:01.620291 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9531 06:49:01.623666 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9532 06:49:01.630516 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9533 06:49:01.633733 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9534 06:49:01.636692 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9535 06:49:01.643748 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9536 06:49:01.647821 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9537 06:49:01.654199 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9538 06:49:01.657197 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9539 06:49:01.660007 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9540 06:49:01.666818 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9541 06:49:01.670869 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9542 06:49:01.676538 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9543 06:49:01.680942 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9544 06:49:01.686888 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9545 06:49:01.689734 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9546 06:49:01.693289 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9547 06:49:01.700141 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9548 06:49:01.703479 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9549 06:49:01.710201 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9550 06:49:01.713155 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9551 06:49:01.716660 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9552 06:49:01.723202 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9553 06:49:01.726553 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9554 06:49:01.733138 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9555 06:49:01.736315 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9556 06:49:01.739500 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9557 06:49:01.746657 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9558 06:49:01.749751 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9559 06:49:01.756915 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9560 06:49:01.759642 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9561 06:49:01.763454 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9562 06:49:01.769166 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9563 06:49:01.772610 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9564 06:49:01.779038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9565 06:49:01.783200 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9566 06:49:01.789011 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9567 06:49:01.792185 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9568 06:49:01.799368 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9569 06:49:01.802779 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9570 06:49:01.805391 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9571 06:49:01.812158 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9572 06:49:01.815651 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9573 06:49:01.822208 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9574 06:49:01.825588 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9575 06:49:01.831997 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9576 06:49:01.836150 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9577 06:49:01.838737 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9578 06:49:01.845037 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9579 06:49:01.848284 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9580 06:49:01.855082 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9581 06:49:01.858301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9582 06:49:01.864998 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9583 06:49:01.868423 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9584 06:49:01.874453 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9585 06:49:01.878286 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9586 06:49:01.881680 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9587 06:49:01.888113 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9588 06:49:01.891840 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9589 06:49:01.897817 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9590 06:49:01.901174 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9591 06:49:01.907752 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9592 06:49:01.910876 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9593 06:49:01.914782 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9594 06:49:01.920795 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9595 06:49:01.924592 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9596 06:49:01.930660 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9597 06:49:01.933810 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9598 06:49:01.940667 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9599 06:49:01.944830 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9600 06:49:01.951077 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9601 06:49:01.954312 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9602 06:49:01.957991 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9603 06:49:01.964095 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9604 06:49:01.967345 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9605 06:49:01.973779 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9606 06:49:01.977243 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9607 06:49:01.983690 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9608 06:49:01.987337 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9609 06:49:01.990759 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9610 06:49:01.996893 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9611 06:49:02.000831 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9612 06:49:02.007479 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9613 06:49:02.010037 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9614 06:49:02.017233 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9615 06:49:02.020136 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9616 06:49:02.026971 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9617 06:49:02.029946 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9618 06:49:02.033596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9619 06:49:02.039746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9620 06:49:02.043072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9621 06:49:02.050360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9622 06:49:02.052967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9623 06:49:02.059999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9624 06:49:02.064175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9625 06:49:02.069990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9626 06:49:02.073485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9627 06:49:02.079600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9628 06:49:02.082856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9629 06:49:02.089506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9630 06:49:02.092895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9631 06:49:02.099256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9632 06:49:02.102759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9633 06:49:02.109980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9634 06:49:02.113136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9635 06:49:02.119126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9636 06:49:02.123159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9637 06:49:02.126299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9638 06:49:02.134136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9639 06:49:02.139211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9640 06:49:02.142818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9641 06:49:02.146262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9642 06:49:02.152920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9643 06:49:02.155957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9644 06:49:02.162246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9645 06:49:02.169333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9646 06:49:02.172116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9647 06:49:02.179412 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9648 06:49:02.182348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9649 06:49:02.189686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9650 06:49:02.191979 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9651 06:49:02.192061 INFO: [APUAPC] vio 0
9652 06:49:02.200655 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9653 06:49:02.202945 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9654 06:49:02.206566 INFO: [APUAPC] D0_APC_0: 0x400510
9655 06:49:02.210323 INFO: [APUAPC] D0_APC_1: 0x0
9656 06:49:02.212912 INFO: [APUAPC] D0_APC_2: 0x1540
9657 06:49:02.216257 INFO: [APUAPC] D0_APC_3: 0x0
9658 06:49:02.219401 INFO: [APUAPC] D1_APC_0: 0xffffffff
9659 06:49:02.222946 INFO: [APUAPC] D1_APC_1: 0xffffffff
9660 06:49:02.226399 INFO: [APUAPC] D1_APC_2: 0x3fffff
9661 06:49:02.229550 INFO: [APUAPC] D1_APC_3: 0x0
9662 06:49:02.233280 INFO: [APUAPC] D2_APC_0: 0xffffffff
9663 06:49:02.236318 INFO: [APUAPC] D2_APC_1: 0xffffffff
9664 06:49:02.239182 INFO: [APUAPC] D2_APC_2: 0x3fffff
9665 06:49:02.243114 INFO: [APUAPC] D2_APC_3: 0x0
9666 06:49:02.247240 INFO: [APUAPC] D3_APC_0: 0xffffffff
9667 06:49:02.249684 INFO: [APUAPC] D3_APC_1: 0xffffffff
9668 06:49:02.253655 INFO: [APUAPC] D3_APC_2: 0x3fffff
9669 06:49:02.256017 INFO: [APUAPC] D3_APC_3: 0x0
9670 06:49:02.259162 INFO: [APUAPC] D4_APC_0: 0xffffffff
9671 06:49:02.262754 INFO: [APUAPC] D4_APC_1: 0xffffffff
9672 06:49:02.265884 INFO: [APUAPC] D4_APC_2: 0x3fffff
9673 06:49:02.269446 INFO: [APUAPC] D4_APC_3: 0x0
9674 06:49:02.272684 INFO: [APUAPC] D5_APC_0: 0xffffffff
9675 06:49:02.275860 INFO: [APUAPC] D5_APC_1: 0xffffffff
9676 06:49:02.278807 INFO: [APUAPC] D5_APC_2: 0x3fffff
9677 06:49:02.278889 INFO: [APUAPC] D5_APC_3: 0x0
9678 06:49:02.285586 INFO: [APUAPC] D6_APC_0: 0xffffffff
9679 06:49:02.288657 INFO: [APUAPC] D6_APC_1: 0xffffffff
9680 06:49:02.293366 INFO: [APUAPC] D6_APC_2: 0x3fffff
9681 06:49:02.293448 INFO: [APUAPC] D6_APC_3: 0x0
9682 06:49:02.296506 INFO: [APUAPC] D7_APC_0: 0xffffffff
9683 06:49:02.299972 INFO: [APUAPC] D7_APC_1: 0xffffffff
9684 06:49:02.302400 INFO: [APUAPC] D7_APC_2: 0x3fffff
9685 06:49:02.306023 INFO: [APUAPC] D7_APC_3: 0x0
9686 06:49:02.308578 INFO: [APUAPC] D8_APC_0: 0xffffffff
9687 06:49:02.312034 INFO: [APUAPC] D8_APC_1: 0xffffffff
9688 06:49:02.315511 INFO: [APUAPC] D8_APC_2: 0x3fffff
9689 06:49:02.319529 INFO: [APUAPC] D8_APC_3: 0x0
9690 06:49:02.322209 INFO: [APUAPC] D9_APC_0: 0xffffffff
9691 06:49:02.325217 INFO: [APUAPC] D9_APC_1: 0xffffffff
9692 06:49:02.329177 INFO: [APUAPC] D9_APC_2: 0x3fffff
9693 06:49:02.332520 INFO: [APUAPC] D9_APC_3: 0x0
9694 06:49:02.335274 INFO: [APUAPC] D10_APC_0: 0xffffffff
9695 06:49:02.339150 INFO: [APUAPC] D10_APC_1: 0xffffffff
9696 06:49:02.342314 INFO: [APUAPC] D10_APC_2: 0x3fffff
9697 06:49:02.345370 INFO: [APUAPC] D10_APC_3: 0x0
9698 06:49:02.348745 INFO: [APUAPC] D11_APC_0: 0xffffffff
9699 06:49:02.352150 INFO: [APUAPC] D11_APC_1: 0xffffffff
9700 06:49:02.355079 INFO: [APUAPC] D11_APC_2: 0x3fffff
9701 06:49:02.359102 INFO: [APUAPC] D11_APC_3: 0x0
9702 06:49:02.361656 INFO: [APUAPC] D12_APC_0: 0xffffffff
9703 06:49:02.366258 INFO: [APUAPC] D12_APC_1: 0xffffffff
9704 06:49:02.369335 INFO: [APUAPC] D12_APC_2: 0x3fffff
9705 06:49:02.372017 INFO: [APUAPC] D12_APC_3: 0x0
9706 06:49:02.376635 INFO: [APUAPC] D13_APC_0: 0xffffffff
9707 06:49:02.378342 INFO: [APUAPC] D13_APC_1: 0xffffffff
9708 06:49:02.382168 INFO: [APUAPC] D13_APC_2: 0x3fffff
9709 06:49:02.385097 INFO: [APUAPC] D13_APC_3: 0x0
9710 06:49:02.388482 INFO: [APUAPC] D14_APC_0: 0xffffffff
9711 06:49:02.392351 INFO: [APUAPC] D14_APC_1: 0xffffffff
9712 06:49:02.398098 INFO: [APUAPC] D14_APC_2: 0x3fffff
9713 06:49:02.398180 INFO: [APUAPC] D14_APC_3: 0x0
9714 06:49:02.401576 INFO: [APUAPC] D15_APC_0: 0xffffffff
9715 06:49:02.408140 INFO: [APUAPC] D15_APC_1: 0xffffffff
9716 06:49:02.411510 INFO: [APUAPC] D15_APC_2: 0x3fffff
9717 06:49:02.411592 INFO: [APUAPC] D15_APC_3: 0x0
9718 06:49:02.414687 INFO: [APUAPC] APC_CON: 0x4
9719 06:49:02.418192 INFO: [NOCDAPC] D0_APC_0: 0x0
9720 06:49:02.420988 INFO: [NOCDAPC] D0_APC_1: 0x0
9721 06:49:02.425227 INFO: [NOCDAPC] D1_APC_0: 0x0
9722 06:49:02.428234 INFO: [NOCDAPC] D1_APC_1: 0xfff
9723 06:49:02.431186 INFO: [NOCDAPC] D2_APC_0: 0x0
9724 06:49:02.434327 INFO: [NOCDAPC] D2_APC_1: 0xfff
9725 06:49:02.437854 INFO: [NOCDAPC] D3_APC_0: 0x0
9726 06:49:02.441083 INFO: [NOCDAPC] D3_APC_1: 0xfff
9727 06:49:02.441165 INFO: [NOCDAPC] D4_APC_0: 0x0
9728 06:49:02.444480 INFO: [NOCDAPC] D4_APC_1: 0xfff
9729 06:49:02.447364 INFO: [NOCDAPC] D5_APC_0: 0x0
9730 06:49:02.451095 INFO: [NOCDAPC] D5_APC_1: 0xfff
9731 06:49:02.454527 INFO: [NOCDAPC] D6_APC_0: 0x0
9732 06:49:02.458018 INFO: [NOCDAPC] D6_APC_1: 0xfff
9733 06:49:02.461196 INFO: [NOCDAPC] D7_APC_0: 0x0
9734 06:49:02.464596 INFO: [NOCDAPC] D7_APC_1: 0xfff
9735 06:49:02.467509 INFO: [NOCDAPC] D8_APC_0: 0x0
9736 06:49:02.471274 INFO: [NOCDAPC] D8_APC_1: 0xfff
9737 06:49:02.473926 INFO: [NOCDAPC] D9_APC_0: 0x0
9738 06:49:02.474008 INFO: [NOCDAPC] D9_APC_1: 0xfff
9739 06:49:02.477673 INFO: [NOCDAPC] D10_APC_0: 0x0
9740 06:49:02.480682 INFO: [NOCDAPC] D10_APC_1: 0xfff
9741 06:49:02.484172 INFO: [NOCDAPC] D11_APC_0: 0x0
9742 06:49:02.487053 INFO: [NOCDAPC] D11_APC_1: 0xfff
9743 06:49:02.490782 INFO: [NOCDAPC] D12_APC_0: 0x0
9744 06:49:02.493975 INFO: [NOCDAPC] D12_APC_1: 0xfff
9745 06:49:02.497324 INFO: [NOCDAPC] D13_APC_0: 0x0
9746 06:49:02.500572 INFO: [NOCDAPC] D13_APC_1: 0xfff
9747 06:49:02.503852 INFO: [NOCDAPC] D14_APC_0: 0x0
9748 06:49:02.507314 INFO: [NOCDAPC] D14_APC_1: 0xfff
9749 06:49:02.511054 INFO: [NOCDAPC] D15_APC_0: 0x0
9750 06:49:02.513690 INFO: [NOCDAPC] D15_APC_1: 0xfff
9751 06:49:02.517471 INFO: [NOCDAPC] APC_CON: 0x4
9752 06:49:02.520567 INFO: [APUAPC] set_apusys_apc done
9753 06:49:02.523663 INFO: [DEVAPC] devapc_init done
9754 06:49:02.527303 INFO: GICv3 without legacy support detected.
9755 06:49:02.529866 INFO: ARM GICv3 driver initialized in EL3
9756 06:49:02.533506 INFO: Maximum SPI INTID supported: 639
9757 06:49:02.536578 INFO: BL31: Initializing runtime services
9758 06:49:02.543197 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9759 06:49:02.546428 INFO: SPM: enable CPC mode
9760 06:49:02.553367 INFO: mcdi ready for mcusys-off-idle and system suspend
9761 06:49:02.556610 INFO: BL31: Preparing for EL3 exit to normal world
9762 06:49:02.560630 INFO: Entry point address = 0x80000000
9763 06:49:02.563680 INFO: SPSR = 0x8
9764 06:49:02.567965
9765 06:49:02.568046
9766 06:49:02.568111
9767 06:49:02.568793 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9768 06:49:02.568894 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9769 06:49:02.569243 Setting prompt string to ['asurada:']
9770 06:49:02.569329 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9771 06:49:02.571308 Starting depthcharge on Spherion...
9772 06:49:02.571391
9773 06:49:02.571455 Wipe memory regions:
9774 06:49:02.571515
9775 06:49:02.574957 [0x00000040000000, 0x00000054600000)
9776 06:49:02.696592
9777 06:49:02.696713 [0x00000054660000, 0x00000080000000)
9778 06:49:02.957962
9779 06:49:02.958092 [0x000000821a7280, 0x000000ffe64000)
9780 06:49:03.702031
9781 06:49:03.702206 [0x00000100000000, 0x00000140000000)
9782 06:49:04.083293
9783 06:49:04.086598 Initializing XHCI USB controller at 0x11200000.
9784 06:49:05.124257
9785 06:49:05.127326 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9786 06:49:05.127420
9787 06:49:05.127485
9788 06:49:05.127546
9789 06:49:05.127833 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9791 06:49:05.228165 asurada: tftpboot 192.168.201.1 12694863/tftp-deploy-urr229ql/kernel/image.itb 12694863/tftp-deploy-urr229ql/kernel/cmdline
9792 06:49:05.228285 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9793 06:49:05.228367 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9794 06:49:05.233172 tftpboot 192.168.201.1 12694863/tftp-deploy-urr229ql/kernel/image.itp-deploy-urr229ql/kernel/cmdline
9795 06:49:05.233257
9796 06:49:05.233322 Waiting for link
9797 06:49:05.392894
9798 06:49:05.393019 R8152: Initializing
9799 06:49:05.393086
9800 06:49:05.396486 Version 9 (ocp_data = 6010)
9801 06:49:05.396568
9802 06:49:05.399630 R8152: Done initializing
9803 06:49:05.399717
9804 06:49:05.399783 Adding net device
9805 06:49:07.286041
9806 06:49:07.286186 done.
9807 06:49:07.286253
9808 06:49:07.286313 MAC: 00:e0:4c:68:03:bd
9809 06:49:07.286373
9810 06:49:07.289759 Sending DHCP discover... done.
9811 06:49:07.289844
9812 06:49:07.292521 Waiting for reply... done.
9813 06:49:07.292629
9814 06:49:07.296570 Sending DHCP request... done.
9815 06:49:07.296651
9816 06:49:07.301260 Waiting for reply... done.
9817 06:49:07.301342
9818 06:49:07.301406 My ip is 192.168.201.16
9819 06:49:07.301467
9820 06:49:07.304677 The DHCP server ip is 192.168.201.1
9821 06:49:07.304796
9822 06:49:07.311100 TFTP server IP predefined by user: 192.168.201.1
9823 06:49:07.311210
9824 06:49:07.318169 Bootfile predefined by user: 12694863/tftp-deploy-urr229ql/kernel/image.itb
9825 06:49:07.318251
9826 06:49:07.318315 Sending tftp read request... done.
9827 06:49:07.321398
9828 06:49:07.324732 Waiting for the transfer...
9829 06:49:07.324816
9830 06:49:07.585709 00000000 ################################################################
9831 06:49:07.585848
9832 06:49:07.840046 00080000 ################################################################
9833 06:49:07.840205
9834 06:49:08.117918 00100000 ################################################################
9835 06:49:08.118055
9836 06:49:08.379192 00180000 ################################################################
9837 06:49:08.379333
9838 06:49:08.630416 00200000 ################################################################
9839 06:49:08.630557
9840 06:49:08.887861 00280000 ################################################################
9841 06:49:08.888008
9842 06:49:09.138978 00300000 ################################################################
9843 06:49:09.139120
9844 06:49:09.390774 00380000 ################################################################
9845 06:49:09.390922
9846 06:49:09.650068 00400000 ################################################################
9847 06:49:09.650210
9848 06:49:09.906777 00480000 ################################################################
9849 06:49:09.906914
9850 06:49:10.170051 00500000 ################################################################
9851 06:49:10.170190
9852 06:49:10.422898 00580000 ################################################################
9853 06:49:10.423036
9854 06:49:10.676031 00600000 ################################################################
9855 06:49:10.676166
9856 06:49:10.926735 00680000 ################################################################
9857 06:49:10.926869
9858 06:49:11.188987 00700000 ################################################################
9859 06:49:11.189131
9860 06:49:11.487165 00780000 ################################################################
9861 06:49:11.487300
9862 06:49:11.781794 00800000 ################################################################
9863 06:49:11.781934
9864 06:49:12.084214 00880000 ################################################################
9865 06:49:12.084355
9866 06:49:12.385741 00900000 ################################################################
9867 06:49:12.385883
9868 06:49:12.761483 00980000 ################################################################
9869 06:49:12.762061
9870 06:49:13.073831 00a00000 ################################################################
9871 06:49:13.073962
9872 06:49:13.353417 00a80000 ################################################################
9873 06:49:13.353555
9874 06:49:13.636829 00b00000 ################################################################
9875 06:49:13.636960
9876 06:49:13.931687 00b80000 ################################################################
9877 06:49:13.931817
9878 06:49:14.222401 00c00000 ################################################################
9879 06:49:14.222529
9880 06:49:14.509660 00c80000 ################################################################
9881 06:49:14.509818
9882 06:49:14.801024 00d00000 ################################################################
9883 06:49:14.801151
9884 06:49:15.139248 00d80000 ################################################################
9885 06:49:15.139776
9886 06:49:15.519954 00e00000 ################################################################
9887 06:49:15.520479
9888 06:49:15.898041 00e80000 ################################################################
9889 06:49:15.898646
9890 06:49:16.293920 00f00000 ################################################################
9891 06:49:16.294433
9892 06:49:16.610420 00f80000 ################################################################
9893 06:49:16.610551
9894 06:49:16.897580 01000000 ################################################################
9895 06:49:16.897739
9896 06:49:17.195127 01080000 ################################################################
9897 06:49:17.195260
9898 06:49:17.455908 01100000 ################################################################
9899 06:49:17.456039
9900 06:49:17.782685 01180000 ################################################################
9901 06:49:17.783185
9902 06:49:18.162508 01200000 ################################################################
9903 06:49:18.163001
9904 06:49:18.538679 01280000 ################################################################
9905 06:49:18.539215
9906 06:49:18.931201 01300000 ################################################################
9907 06:49:18.931814
9908 06:49:19.325283 01380000 ################################################################
9909 06:49:19.325979
9910 06:49:19.708793 01400000 ################################################################
9911 06:49:19.709363
9912 06:49:20.092963 01480000 ################################################################
9913 06:49:20.093687
9914 06:49:20.483692 01500000 ################################################################
9915 06:49:20.484257
9916 06:49:20.879745 01580000 ################################################################
9917 06:49:20.880291
9918 06:49:21.272627 01600000 ################################################################
9919 06:49:21.273227
9920 06:49:21.661254 01680000 ################################################################
9921 06:49:21.661798
9922 06:49:22.041474 01700000 ################################################################
9923 06:49:22.042022
9924 06:49:22.424854 01780000 ################################################################
9925 06:49:22.425381
9926 06:49:22.830679 01800000 ################################################################
9927 06:49:22.831300
9928 06:49:23.256589 01880000 ################################################################
9929 06:49:23.257189
9930 06:49:23.658830 01900000 ################################################################
9931 06:49:23.659373
9932 06:49:23.976285 01980000 ################################################################
9933 06:49:23.976425
9934 06:49:24.268474 01a00000 ################################################################
9935 06:49:24.268611
9936 06:49:24.562806 01a80000 ################################################################
9937 06:49:24.562943
9938 06:49:24.863564 01b00000 ################################################################
9939 06:49:24.863708
9940 06:49:25.168825 01b80000 ################################################################
9941 06:49:25.168965
9942 06:49:25.472807 01c00000 ################################################################
9943 06:49:25.472945
9944 06:49:25.482268 01c80000 ## done.
9945 06:49:25.482350
9946 06:49:25.485222 The bootfile was 29899742 bytes long.
9947 06:49:25.485309
9948 06:49:25.488831 Sending tftp read request... done.
9949 06:49:25.488933
9950 06:49:25.489007 Waiting for the transfer...
9951 06:49:25.489074
9952 06:49:25.492062 00000000 # done.
9953 06:49:25.492156
9954 06:49:25.499780 Command line loaded dynamically from TFTP file: 12694863/tftp-deploy-urr229ql/kernel/cmdline
9955 06:49:25.499968
9956 06:49:25.521862 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694863/extract-nfsrootfs-kuz9jy9o,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9957 06:49:25.522128
9958 06:49:25.522279 Loading FIT.
9959 06:49:25.522416
9960 06:49:25.525097 Image ramdisk-1 has 17799847 bytes.
9961 06:49:25.525295
9962 06:49:25.528422 Image fdt-1 has 47278 bytes.
9963 06:49:25.528619
9964 06:49:25.531560 Image kernel-1 has 12050581 bytes.
9965 06:49:25.531793
9966 06:49:25.541924 Compat preference: google,spherion-rev12-sku1 google,spherion-rev12 google,spherion-sku1 google,spherion
9967 06:49:25.542307
9968 06:49:25.558806 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
9969 06:49:25.559390
9970 06:49:25.565502 Choosing best match conf-1 for compat google,spherion.
9971 06:49:25.566055
9972 06:49:25.572271 Connected to device vid:did:rid of 1ae0:0028:00
9973 06:49:25.579383
9974 06:49:25.582974 tpm_get_response: command 0x17b, return code 0x0
9975 06:49:25.583536
9976 06:49:25.586567 ec_init: CrosEC protocol v3 supported (256, 248)
9977 06:49:25.590928
9978 06:49:25.593183 tpm_cleanup: add release locality here.
9979 06:49:25.593645
9980 06:49:25.594009 Shutting down all USB controllers.
9981 06:49:25.596623
9982 06:49:25.597229 Removing current net device
9983 06:49:25.597604
9984 06:49:25.603533 Exiting depthcharge with code 4 at timestamp: 51193714
9985 06:49:25.604095
9986 06:49:25.607040 LZMA decompressing kernel-1 to 0x821a6718
9987 06:49:25.607600
9988 06:49:25.610139 LZMA decompressing kernel-1 to 0x40000000
9989 06:49:27.108310
9990 06:49:27.108919 jumping to kernel
9991 06:49:27.110630 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
9992 06:49:27.111159 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
9993 06:49:27.111567 Setting prompt string to ['Linux version [0-9]']
9994 06:49:27.111939 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9995 06:49:27.112311 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
9996 06:49:27.158346
9997 06:49:27.161670 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
9998 06:49:27.165479 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
9999 06:49:27.166054 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10000 06:49:27.166447 Setting prompt string to []
10001 06:49:27.166863 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10002 06:49:27.167244 Using line separator: #'\n'#
10003 06:49:27.167574 No login prompt set.
10004 06:49:27.167902 Parsing kernel messages
10005 06:49:27.168207 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10006 06:49:27.168790 [login-action] Waiting for messages, (timeout 00:04:02)
10007 06:49:27.184261 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10008 06:49:27.188194 [ 0.000000] random: crng init done
10009 06:49:27.194523 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10010 06:49:27.197653 [ 0.000000] efi: UEFI not found.
10011 06:49:27.204700 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10012 06:49:27.211527 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10013 06:49:27.220679 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10014 06:49:27.231146 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10015 06:49:27.237305 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10016 06:49:27.244667 [ 0.000000] printk: bootconsole [mtk8250] enabled
10017 06:49:27.250560 [ 0.000000] NUMA: No NUMA configuration found
10018 06:49:27.257467 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10019 06:49:27.260587 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10020 06:49:27.263982 [ 0.000000] Zone ranges:
10021 06:49:27.270254 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10022 06:49:27.273804 [ 0.000000] DMA32 empty
10023 06:49:27.280570 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10024 06:49:27.283834 [ 0.000000] Movable zone start for each node
10025 06:49:27.286884 [ 0.000000] Early memory node ranges
10026 06:49:27.293628 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10027 06:49:27.301151 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10028 06:49:27.306830 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10029 06:49:27.314425 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10030 06:49:27.319988 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10031 06:49:27.326475 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10032 06:49:27.356190 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10033 06:49:27.362674 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10034 06:49:27.369406 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10035 06:49:27.372937 [ 0.000000] psci: probing for conduit method from DT.
10036 06:49:27.380396 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10037 06:49:27.382650 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10038 06:49:27.390130 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10039 06:49:27.393213 [ 0.000000] psci: SMC Calling Convention v1.2
10040 06:49:27.399878 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10041 06:49:27.402727 [ 0.000000] Detected VIPT I-cache on CPU0
10042 06:49:27.409639 [ 0.000000] CPU features: detected: GIC system register CPU interface
10043 06:49:27.415964 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10044 06:49:27.422443 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10045 06:49:27.430086 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10046 06:49:27.436072 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10047 06:49:27.445434 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10048 06:49:27.449222 [ 0.000000] alternatives: applying boot alternatives
10049 06:49:27.455539 [ 0.000000] Fallback order for Node 0: 0
10050 06:49:27.462208 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10051 06:49:27.465407 [ 0.000000] Policy zone: Normal
10052 06:49:27.488856 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694863/extract-nfsrootfs-kuz9jy9o,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10053 06:49:27.498728 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10054 06:49:27.508485 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10055 06:49:27.515003 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10056 06:49:27.521482 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10057 06:49:27.529073 <6>[ 0.000000] software IO TLB: area num 8.
10058 06:49:27.583047 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10059 06:49:27.663715 <6>[ 0.000000] Memory: 3835460K/4191232K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 323004K reserved, 32768K cma-reserved)
10060 06:49:27.670197 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10061 06:49:27.676922 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10062 06:49:27.680116 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10063 06:49:27.686898 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10064 06:49:27.693833 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10065 06:49:27.696435 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10066 06:49:27.706900 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10067 06:49:27.713289 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10068 06:49:27.719577 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10069 06:49:27.726680 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10070 06:49:27.730533 <6>[ 0.000000] GICv3: 608 SPIs implemented
10071 06:49:27.732856 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10072 06:49:27.739226 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10073 06:49:27.743552 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10074 06:49:27.749239 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10075 06:49:27.763447 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10076 06:49:27.775900 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10077 06:49:27.782567 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10078 06:49:27.790031 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10079 06:49:27.803367 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10080 06:49:27.809967 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10081 06:49:27.816212 <6>[ 0.009179] Console: colour dummy device 80x25
10082 06:49:27.826421 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10083 06:49:27.830067 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10084 06:49:27.836901 <6>[ 0.029222] LSM: Security Framework initializing
10085 06:49:27.843030 <6>[ 0.034137] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10086 06:49:27.853350 <6>[ 0.041744] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10087 06:49:27.860571 <6>[ 0.050975] cblist_init_generic: Setting adjustable number of callback queues.
10088 06:49:27.866000 <6>[ 0.058463] cblist_init_generic: Setting shift to 3 and lim to 1.
10089 06:49:27.876437 <6>[ 0.064802] cblist_init_generic: Setting adjustable number of callback queues.
10090 06:49:27.879188 <6>[ 0.072275] cblist_init_generic: Setting shift to 3 and lim to 1.
10091 06:49:27.885877 <6>[ 0.078674] rcu: Hierarchical SRCU implementation.
10092 06:49:27.892702 <6>[ 0.083688] rcu: Max phase no-delay instances is 1000.
10093 06:49:27.898906 <6>[ 0.090710] EFI services will not be available.
10094 06:49:27.902520 <6>[ 0.095693] smp: Bringing up secondary CPUs ...
10095 06:49:27.910418 <6>[ 0.100771] Detected VIPT I-cache on CPU1
10096 06:49:27.916799 <6>[ 0.100838] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10097 06:49:27.923682 <6>[ 0.100869] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10098 06:49:27.926740 <6>[ 0.101198] Detected VIPT I-cache on CPU2
10099 06:49:27.933626 <6>[ 0.101245] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10100 06:49:27.943039 <6>[ 0.101260] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10101 06:49:27.946861 <6>[ 0.101517] Detected VIPT I-cache on CPU3
10102 06:49:27.953119 <6>[ 0.101563] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10103 06:49:27.959349 <6>[ 0.101577] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10104 06:49:27.963670 <6>[ 0.101878] CPU features: detected: Spectre-v4
10105 06:49:27.970177 <6>[ 0.101884] CPU features: detected: Spectre-BHB
10106 06:49:27.973178 <6>[ 0.101889] Detected PIPT I-cache on CPU4
10107 06:49:27.979586 <6>[ 0.101946] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10108 06:49:27.986981 <6>[ 0.101963] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10109 06:49:27.993425 <6>[ 0.102256] Detected PIPT I-cache on CPU5
10110 06:49:27.999656 <6>[ 0.102318] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10111 06:49:28.006547 <6>[ 0.102334] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10112 06:49:28.009311 <6>[ 0.102613] Detected PIPT I-cache on CPU6
10113 06:49:28.015995 <6>[ 0.102673] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10114 06:49:28.025740 <6>[ 0.102690] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10115 06:49:28.029222 <6>[ 0.102992] Detected PIPT I-cache on CPU7
10116 06:49:28.035766 <6>[ 0.103055] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10117 06:49:28.042214 <6>[ 0.103072] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10118 06:49:28.045425 <6>[ 0.103120] smp: Brought up 1 node, 8 CPUs
10119 06:49:28.052317 <6>[ 0.244461] SMP: Total of 8 processors activated.
10120 06:49:28.055443 <6>[ 0.249382] CPU features: detected: 32-bit EL0 Support
10121 06:49:28.066891 <6>[ 0.254745] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10122 06:49:28.073116 <6>[ 0.263600] CPU features: detected: Common not Private translations
10123 06:49:28.078510 <6>[ 0.270075] CPU features: detected: CRC32 instructions
10124 06:49:28.085284 <6>[ 0.275427] CPU features: detected: RCpc load-acquire (LDAPR)
10125 06:49:28.088531 <6>[ 0.281424] CPU features: detected: LSE atomic instructions
10126 06:49:28.095352 <6>[ 0.287242] CPU features: detected: Privileged Access Never
10127 06:49:28.101438 <6>[ 0.293057] CPU features: detected: RAS Extension Support
10128 06:49:28.108927 <6>[ 0.298666] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10129 06:49:28.112041 <6>[ 0.305886] CPU: All CPU(s) started at EL2
10130 06:49:28.118741 <6>[ 0.310230] alternatives: applying system-wide alternatives
10131 06:49:28.128075 <6>[ 0.320186] devtmpfs: initialized
10132 06:49:28.142422 <6>[ 0.328462] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10133 06:49:28.148261 <6>[ 0.338422] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10134 06:49:28.157417 <6>[ 0.346437] pinctrl core: initialized pinctrl subsystem
10135 06:49:28.158659 <6>[ 0.353105] DMI not present or invalid.
10136 06:49:28.164887 <6>[ 0.357506] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10137 06:49:28.175010 <6>[ 0.364349] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10138 06:49:28.181641 <6>[ 0.371794] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10139 06:49:28.191902 <6>[ 0.379884] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10140 06:49:28.195019 <6>[ 0.388040] audit: initializing netlink subsys (disabled)
10141 06:49:28.205453 <5>[ 0.393734] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10142 06:49:28.211566 <6>[ 0.394436] thermal_sys: Registered thermal governor 'step_wise'
10143 06:49:28.218052 <6>[ 0.401700] thermal_sys: Registered thermal governor 'power_allocator'
10144 06:49:28.220855 <6>[ 0.407954] cpuidle: using governor menu
10145 06:49:28.228246 <6>[ 0.418913] NET: Registered PF_QIPCRTR protocol family
10146 06:49:28.234493 <6>[ 0.424398] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10147 06:49:28.237441 <6>[ 0.431500] ASID allocator initialised with 32768 entries
10148 06:49:28.244948 <6>[ 0.438043] Serial: AMBA PL011 UART driver
10149 06:49:28.253921 <4>[ 0.446805] Trying to register duplicate clock ID: 134
10150 06:49:28.307767 <6>[ 0.503801] KASLR enabled
10151 06:49:28.321888 <6>[ 0.511411] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10152 06:49:28.328451 <6>[ 0.518424] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10153 06:49:28.335297 <6>[ 0.524913] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10154 06:49:28.341744 <6>[ 0.531920] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10155 06:49:28.348409 <6>[ 0.538406] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10156 06:49:28.355447 <6>[ 0.545407] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10157 06:49:28.361212 <6>[ 0.551892] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10158 06:49:28.367748 <6>[ 0.558895] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10159 06:49:28.371118 <6>[ 0.566325] ACPI: Interpreter disabled.
10160 06:49:28.379961 <6>[ 0.572713] iommu: Default domain type: Translated
10161 06:49:28.386559 <6>[ 0.577864] iommu: DMA domain TLB invalidation policy: strict mode
10162 06:49:28.389968 <5>[ 0.584519] SCSI subsystem initialized
10163 06:49:28.396047 <6>[ 0.588766] usbcore: registered new interface driver usbfs
10164 06:49:28.403644 <6>[ 0.594495] usbcore: registered new interface driver hub
10165 06:49:28.405994 <6>[ 0.600047] usbcore: registered new device driver usb
10166 06:49:28.413726 <6>[ 0.606157] pps_core: LinuxPPS API ver. 1 registered
10167 06:49:28.423549 <6>[ 0.611350] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10168 06:49:28.426795 <6>[ 0.620693] PTP clock support registered
10169 06:49:28.430249 <6>[ 0.624930] EDAC MC: Ver: 3.0.0
10170 06:49:28.437376 <6>[ 0.630104] FPGA manager framework
10171 06:49:28.443619 <6>[ 0.633778] Advanced Linux Sound Architecture Driver Initialized.
10172 06:49:28.446764 <6>[ 0.640535] vgaarb: loaded
10173 06:49:28.453634 <6>[ 0.643684] clocksource: Switched to clocksource arch_sys_counter
10174 06:49:28.457203 <5>[ 0.650125] VFS: Disk quotas dquot_6.6.0
10175 06:49:28.463977 <6>[ 0.654310] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10176 06:49:28.467719 <6>[ 0.661501] pnp: PnP ACPI: disabled
10177 06:49:28.475460 <6>[ 0.668148] NET: Registered PF_INET protocol family
10178 06:49:28.482761 <6>[ 0.673529] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10179 06:49:28.493794 <6>[ 0.683559] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10180 06:49:28.503842 <6>[ 0.692341] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10181 06:49:28.510992 <6>[ 0.700311] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10182 06:49:28.517674 <6>[ 0.708712] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10183 06:49:28.527717 <6>[ 0.717372] TCP: Hash tables configured (established 32768 bind 32768)
10184 06:49:28.534238 <6>[ 0.724227] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10185 06:49:28.541631 <6>[ 0.731246] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10186 06:49:28.547441 <6>[ 0.738768] NET: Registered PF_UNIX/PF_LOCAL protocol family
10187 06:49:28.554198 <6>[ 0.744910] RPC: Registered named UNIX socket transport module.
10188 06:49:28.557492 <6>[ 0.751064] RPC: Registered udp transport module.
10189 06:49:28.564028 <6>[ 0.755994] RPC: Registered tcp transport module.
10190 06:49:28.570858 <6>[ 0.760925] RPC: Registered tcp NFSv4.1 backchannel transport module.
10191 06:49:28.573681 <6>[ 0.767590] PCI: CLS 0 bytes, default 64
10192 06:49:28.577675 <6>[ 0.771959] Unpacking initramfs...
10193 06:49:28.587254 <6>[ 0.775657] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10194 06:49:28.594787 <6>[ 0.784293] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10195 06:49:28.600337 <6>[ 0.793126] kvm [1]: IPA Size Limit: 40 bits
10196 06:49:28.603971 <6>[ 0.797652] kvm [1]: GICv3: no GICV resource entry
10197 06:49:28.610939 <6>[ 0.802669] kvm [1]: disabling GICv2 emulation
10198 06:49:28.616938 <6>[ 0.807351] kvm [1]: GIC system register CPU interface enabled
10199 06:49:28.620124 <6>[ 0.813514] kvm [1]: vgic interrupt IRQ18
10200 06:49:28.626766 <6>[ 0.817871] kvm [1]: VHE mode initialized successfully
10201 06:49:28.630832 <5>[ 0.824312] Initialise system trusted keyrings
10202 06:49:28.636679 <6>[ 0.829150] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10203 06:49:28.646342 <6>[ 0.839416] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10204 06:49:28.653219 <5>[ 0.845817] NFS: Registering the id_resolver key type
10205 06:49:28.656518 <5>[ 0.851114] Key type id_resolver registered
10206 06:49:28.663305 <5>[ 0.855529] Key type id_legacy registered
10207 06:49:28.669519 <6>[ 0.859807] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10208 06:49:28.676232 <6>[ 0.866729] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10209 06:49:28.682715 <6>[ 0.874457] 9p: Installing v9fs 9p2000 file system support
10210 06:49:28.719619 <5>[ 0.912497] Key type asymmetric registered
10211 06:49:28.723451 <5>[ 0.916831] Asymmetric key parser 'x509' registered
10212 06:49:28.733130 <6>[ 0.921994] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10213 06:49:28.736095 <6>[ 0.929606] io scheduler mq-deadline registered
10214 06:49:28.739111 <6>[ 0.934363] io scheduler kyber registered
10215 06:49:28.759003 <6>[ 0.951498] EINJ: ACPI disabled.
10216 06:49:28.790374 <4>[ 0.976795] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10217 06:49:28.800153 <4>[ 0.987440] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10218 06:49:28.816499 <6>[ 1.008680] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10219 06:49:28.824163 <6>[ 1.016736] printk: console [ttyS0] disabled
10220 06:49:28.852261 <6>[ 1.041371] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10221 06:49:28.858319 <6>[ 1.050860] printk: console [ttyS0] enabled
10222 06:49:28.861665 <6>[ 1.050860] printk: console [ttyS0] enabled
10223 06:49:28.867983 <6>[ 1.059753] printk: bootconsole [mtk8250] disabled
10224 06:49:28.871715 <6>[ 1.059753] printk: bootconsole [mtk8250] disabled
10225 06:49:28.878436 <6>[ 1.071013] SuperH (H)SCI(F) driver initialized
10226 06:49:28.882502 <6>[ 1.076293] msm_serial: driver initialized
10227 06:49:28.895911 <6>[ 1.085267] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10228 06:49:28.906478 <6>[ 1.093813] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10229 06:49:28.912644 <6>[ 1.102354] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10230 06:49:28.922572 <6>[ 1.110984] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10231 06:49:28.932259 <6>[ 1.119702] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10232 06:49:28.939246 <6>[ 1.128423] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10233 06:49:28.949123 <6>[ 1.136963] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10234 06:49:28.954984 <6>[ 1.145767] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10235 06:49:28.965653 <6>[ 1.154315] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10236 06:49:28.977248 <6>[ 1.169926] loop: module loaded
10237 06:49:28.983521 <6>[ 1.175947] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10238 06:49:29.006112 <4>[ 1.199360] mtk-pmic-keys: Failed to locate of_node [id: -1]
10239 06:49:29.013548 <6>[ 1.206342] megasas: 07.719.03.00-rc1
10240 06:49:29.024401 <6>[ 1.216463] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10241 06:49:29.031156 <6>[ 1.223117] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10242 06:49:29.046412 <6>[ 1.239585] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10243 06:49:29.102433 <6>[ 1.288617] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10244 06:49:29.323931 <6>[ 1.516330] Freeing initrd memory: 17380K
10245 06:49:29.333775 <6>[ 1.526461] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10246 06:49:29.344429 <6>[ 1.537513] tun: Universal TUN/TAP device driver, 1.6
10247 06:49:29.348112 <6>[ 1.543577] thunder_xcv, ver 1.0
10248 06:49:29.351209 <6>[ 1.547082] thunder_bgx, ver 1.0
10249 06:49:29.354142 <6>[ 1.550578] nicpf, ver 1.0
10250 06:49:29.364996 <6>[ 1.554612] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10251 06:49:29.368839 <6>[ 1.562089] hns3: Copyright (c) 2017 Huawei Corporation.
10252 06:49:29.373200 <6>[ 1.567679] hclge is initializing
10253 06:49:29.378949 <6>[ 1.571256] e1000: Intel(R) PRO/1000 Network Driver
10254 06:49:29.385719 <6>[ 1.576386] e1000: Copyright (c) 1999-2006 Intel Corporation.
10255 06:49:29.388627 <6>[ 1.582401] e1000e: Intel(R) PRO/1000 Network Driver
10256 06:49:29.394763 <6>[ 1.587617] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10257 06:49:29.401194 <6>[ 1.593802] igb: Intel(R) Gigabit Ethernet Network Driver
10258 06:49:29.408334 <6>[ 1.599453] igb: Copyright (c) 2007-2014 Intel Corporation.
10259 06:49:29.414832 <6>[ 1.605288] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10260 06:49:29.421493 <6>[ 1.611807] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10261 06:49:29.424362 <6>[ 1.618271] sky2: driver version 1.30
10262 06:49:29.431356 <6>[ 1.623264] VFIO - User Level meta-driver version: 0.3
10263 06:49:29.438431 <6>[ 1.631455] usbcore: registered new interface driver usb-storage
10264 06:49:29.444924 <6>[ 1.637906] usbcore: registered new device driver onboard-usb-hub
10265 06:49:29.454474 <6>[ 1.647056] mt6397-rtc mt6359-rtc: registered as rtc0
10266 06:49:29.464230 <6>[ 1.652522] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:49:33 UTC (1706942973)
10267 06:49:29.467795 <6>[ 1.662084] i2c_dev: i2c /dev entries driver
10268 06:49:29.483975 <6>[ 1.673809] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10269 06:49:29.503769 <6>[ 1.696772] cpu cpu0: EM: created perf domain
10270 06:49:29.506557 <6>[ 1.701685] cpu cpu4: EM: created perf domain
10271 06:49:29.514052 <6>[ 1.706928] sdhci: Secure Digital Host Controller Interface driver
10272 06:49:29.521040 <6>[ 1.713361] sdhci: Copyright(c) Pierre Ossman
10273 06:49:29.527648 <6>[ 1.718264] Synopsys Designware Multimedia Card Interface Driver
10274 06:49:29.534584 <6>[ 1.724855] sdhci-pltfm: SDHCI platform and OF driver helper
10275 06:49:29.536794 <6>[ 1.725022] mmc0: CQHCI version 5.10
10276 06:49:29.543598 <6>[ 1.734973] ledtrig-cpu: registered to indicate activity on CPUs
10277 06:49:29.550351 <6>[ 1.742065] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10278 06:49:29.556554 <6>[ 1.749096] usbcore: registered new interface driver usbhid
10279 06:49:29.560411 <6>[ 1.754917] usbhid: USB HID core driver
10280 06:49:29.566700 <6>[ 1.759114] spi_master spi0: will run message pump with realtime priority
10281 06:49:29.608956 <6>[ 1.795497] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10282 06:49:29.628273 <6>[ 1.811099] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10283 06:49:29.631633 <6>[ 1.824717] mmc0: Command Queue Engine enabled
10284 06:49:29.638300 <6>[ 1.829487] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10285 06:49:29.645027 <6>[ 1.836410] cros-ec-spi spi0.0: Chrome EC device registered
10286 06:49:29.648161 <6>[ 1.836726] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10287 06:49:29.660034 <6>[ 1.853207] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10288 06:49:29.668270 <6>[ 1.860697] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10289 06:49:29.678062 <6>[ 1.864489] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10290 06:49:29.681505 <6>[ 1.866559] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10291 06:49:29.687763 <6>[ 1.876285] NET: Registered PF_PACKET protocol family
10292 06:49:29.694186 <6>[ 1.881105] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10293 06:49:29.697392 <6>[ 1.885810] 9pnet: Installing 9P2000 support
10294 06:49:29.704682 <5>[ 1.896825] Key type dns_resolver registered
10295 06:49:29.708247 <6>[ 1.901762] registered taskstats version 1
10296 06:49:29.714408 <5>[ 1.906140] Loading compiled-in X.509 certificates
10297 06:49:29.742203 <4>[ 1.928316] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10298 06:49:29.753068 <4>[ 1.938996] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10299 06:49:29.758263 <3>[ 1.949523] debugfs: File 'uA_load' in directory '/' already present!
10300 06:49:29.765729 <3>[ 1.956280] debugfs: File 'min_uV' in directory '/' already present!
10301 06:49:29.772465 <3>[ 1.962894] debugfs: File 'max_uV' in directory '/' already present!
10302 06:49:29.778363 <3>[ 1.969509] debugfs: File 'constraint_flags' in directory '/' already present!
10303 06:49:29.788912 <3>[ 1.978849] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10304 06:49:29.798202 <6>[ 1.991034] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10305 06:49:29.804936 <6>[ 1.997949] xhci-mtk 11200000.usb: xHCI Host Controller
10306 06:49:29.811419 <6>[ 2.003446] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10307 06:49:29.821767 <6>[ 2.011281] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10308 06:49:29.828012 <6>[ 2.020695] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10309 06:49:29.834836 <6>[ 2.026758] xhci-mtk 11200000.usb: xHCI Host Controller
10310 06:49:29.841419 <6>[ 2.032234] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10311 06:49:29.847842 <6>[ 2.039877] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10312 06:49:29.855940 <6>[ 2.047505] hub 1-0:1.0: USB hub found
10313 06:49:29.858097 <6>[ 2.051511] hub 1-0:1.0: 1 port detected
10314 06:49:29.865340 <6>[ 2.055787] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10315 06:49:29.872854 <6>[ 2.064305] hub 2-0:1.0: USB hub found
10316 06:49:29.874856 <6>[ 2.068306] hub 2-0:1.0: 1 port detected
10317 06:49:29.881709 <6>[ 2.074922] mtk-msdc 11f70000.mmc: Got CD GPIO
10318 06:49:29.893607 <6>[ 2.083300] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10319 06:49:29.901330 <6>[ 2.091320] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10320 06:49:29.910570 <4>[ 2.099208] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10321 06:49:29.920067 <6>[ 2.108728] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10322 06:49:29.927230 <6>[ 2.116806] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10323 06:49:29.933805 <6>[ 2.124869] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10324 06:49:29.943727 <6>[ 2.132796] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10325 06:49:29.950035 <6>[ 2.140613] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10326 06:49:29.960026 <6>[ 2.148429] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10327 06:49:29.970379 <6>[ 2.158764] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10328 06:49:29.976870 <6>[ 2.167124] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10329 06:49:29.986821 <6>[ 2.175468] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10330 06:49:29.993121 <6>[ 2.183816] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10331 06:49:30.003843 <6>[ 2.192154] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10332 06:49:30.009702 <6>[ 2.200493] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10333 06:49:30.019564 <6>[ 2.208831] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10334 06:49:30.026337 <6>[ 2.217169] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10335 06:49:30.035949 <6>[ 2.225507] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10336 06:49:30.042388 <6>[ 2.233846] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10337 06:49:30.052483 <6>[ 2.242183] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10338 06:49:30.058863 <6>[ 2.250521] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10339 06:49:30.069221 <6>[ 2.258867] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10340 06:49:30.076431 <6>[ 2.267206] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10341 06:49:30.085812 <6>[ 2.275544] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10342 06:49:30.092856 <6>[ 2.284273] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10343 06:49:30.099046 <6>[ 2.291404] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10344 06:49:30.105600 <6>[ 2.298159] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10345 06:49:30.112628 <6>[ 2.304918] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10346 06:49:30.119294 <6>[ 2.311826] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10347 06:49:30.128845 <6>[ 2.318685] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10348 06:49:30.139738 <6>[ 2.327836] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10349 06:49:30.148665 <6>[ 2.336955] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10350 06:49:30.159642 <6>[ 2.346248] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10351 06:49:30.165324 <6>[ 2.355714] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10352 06:49:30.175463 <6>[ 2.365179] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10353 06:49:30.185259 <6>[ 2.374297] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10354 06:49:30.195067 <6>[ 2.383764] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10355 06:49:30.205082 <6>[ 2.392883] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10356 06:49:30.215493 <6>[ 2.402176] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10357 06:49:30.225723 <6>[ 2.412336] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10358 06:49:30.235027 <6>[ 2.424007] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10359 06:49:30.241456 <6>[ 2.433702] Trying to probe devices needed for running init ...
10360 06:49:30.285729 <6>[ 2.475950] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10361 06:49:30.441432 <6>[ 2.633996] hub 1-1:1.0: USB hub found
10362 06:49:30.444277 <6>[ 2.638503] hub 1-1:1.0: 4 ports detected
10363 06:49:30.453915 <6>[ 2.646969] hub 1-1:1.0: USB hub found
10364 06:49:30.456927 <6>[ 2.651304] hub 1-1:1.0: 4 ports detected
10365 06:49:30.566267 <6>[ 2.756257] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10366 06:49:30.594098 <6>[ 2.787451] hub 2-1:1.0: USB hub found
10367 06:49:30.597350 <6>[ 2.792035] hub 2-1:1.0: 3 ports detected
10368 06:49:30.606916 <6>[ 2.799417] hub 2-1:1.0: USB hub found
10369 06:49:30.609768 <6>[ 2.803928] hub 2-1:1.0: 3 ports detected
10370 06:49:30.777935 <6>[ 2.968046] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10371 06:49:30.909626 <6>[ 3.102718] hub 1-1.4:1.0: USB hub found
10372 06:49:30.912914 <6>[ 3.107272] hub 1-1.4:1.0: 2 ports detected
10373 06:49:30.921423 <6>[ 3.114369] hub 1-1.4:1.0: USB hub found
10374 06:49:30.925145 <6>[ 3.118907] hub 1-1.4:1.0: 2 ports detected
10375 06:49:30.990034 <6>[ 3.180032] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10376 06:49:31.222146 <6>[ 3.411991] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10377 06:49:31.414121 <6>[ 3.604005] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10378 06:49:42.543015 <6>[ 14.740969] ALSA device list:
10379 06:49:42.549503 <6>[ 14.744262] No soundcards found.
10380 06:49:42.557980 <6>[ 14.752045] Freeing unused kernel memory: 8448K
10381 06:49:42.560909 <6>[ 14.757092] Run /init as init process
10382 06:49:42.572051 Loading, please wait...
10383 06:49:42.592318 Starting version 247.3-7+deb11u2
10384 06:49:42.796959 <6>[ 14.987574] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10385 06:49:42.810577 <6>[ 15.004780] remoteproc remoteproc0: scp is available
10386 06:49:42.816881 <6>[ 15.010610] remoteproc remoteproc0: powering up scp
10387 06:49:42.823793 <6>[ 15.015782] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10388 06:49:42.830282 <6>[ 15.024265] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10389 06:49:42.848862 <3>[ 15.040404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10390 06:49:42.856793 <6>[ 15.041837] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10391 06:49:42.865529 <6>[ 15.042174] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10392 06:49:42.872680 <6>[ 15.042199] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10393 06:49:42.882161 <6>[ 15.042209] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10394 06:49:42.888477 <3>[ 15.048530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10395 06:49:42.895878 <6>[ 15.057096] mc: Linux media interface: v0.10
10396 06:49:42.899258 <6>[ 15.057466] usbcore: registered new device driver r8152-cfgselector
10397 06:49:42.909280 <3>[ 15.063880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10398 06:49:42.916445 <3>[ 15.063984] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10399 06:49:42.926172 <3>[ 15.063989] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10400 06:49:42.933081 <3>[ 15.063992] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10401 06:49:42.943010 <3>[ 15.063999] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10402 06:49:42.949686 <3>[ 15.064002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10403 06:49:42.956430 <3>[ 15.064054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10404 06:49:42.966092 <4>[ 15.075858] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10405 06:49:42.973177 <3>[ 15.081584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10406 06:49:42.982222 <4>[ 15.084756] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10407 06:49:42.985422 <4>[ 15.084756] Fallback method does not support PEC.
10408 06:49:42.993115 <4>[ 15.090377] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10409 06:49:43.002928 <3>[ 15.094020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10410 06:49:43.009713 <3>[ 15.094026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10411 06:49:43.019592 <3>[ 15.094058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10412 06:49:43.027189 <3>[ 15.099227] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10413 06:49:43.035621 <3>[ 15.119460] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10414 06:49:43.045185 <3>[ 15.124778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10415 06:49:43.052259 <3>[ 15.124780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10416 06:49:43.058524 <3>[ 15.124784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10417 06:49:43.068184 <3>[ 15.124786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10418 06:49:43.075129 <3>[ 15.124806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10419 06:49:43.085219 <6>[ 15.156848] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10420 06:49:43.091204 <6>[ 15.156884] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10421 06:49:43.098904 <6>[ 15.156892] remoteproc remoteproc0: remote processor scp is now up
10422 06:49:43.105375 <6>[ 15.165066] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10423 06:49:43.114298 <6>[ 15.172910] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10424 06:49:43.118113 <6>[ 15.186220] pci_bus 0000:00: root bus resource [bus 00-ff]
10425 06:49:43.130115 <6>[ 15.195231] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10426 06:49:43.138112 <6>[ 15.195449] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10427 06:49:43.147874 <6>[ 15.195784] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10428 06:49:43.154156 <6>[ 15.201588] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10429 06:49:43.164318 <6>[ 15.206247] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10430 06:49:43.170389 <6>[ 15.219439] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10431 06:49:43.180951 <6>[ 15.226802] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10432 06:49:43.187093 <6>[ 15.227049] videodev: Linux video capture interface: v2.00
10433 06:49:43.197202 <4>[ 15.231390] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10434 06:49:43.203798 <4>[ 15.231396] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10435 06:49:43.207534 <6>[ 15.236127] Bluetooth: Core ver 2.22
10436 06:49:43.213634 <6>[ 15.243545] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10437 06:49:43.220035 <6>[ 15.251670] NET: Registered PF_BLUETOOTH protocol family
10438 06:49:43.226691 <6>[ 15.259670] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10439 06:49:43.233388 <6>[ 15.267804] Bluetooth: HCI device and connection manager initialized
10440 06:49:43.236837 <6>[ 15.275884] pci 0000:00:00.0: supports D1 D2
10441 06:49:43.243791 <6>[ 15.279789] r8152 2-1.3:1.0 eth0: v1.12.13
10442 06:49:43.246865 <6>[ 15.279840] usbcore: registered new interface driver r8152
10443 06:49:43.253358 <6>[ 15.282876] Bluetooth: HCI socket layer initialized
10444 06:49:43.259291 <6>[ 15.291369] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10445 06:49:43.266400 <6>[ 15.297799] Bluetooth: L2CAP socket layer initialized
10446 06:49:43.273390 <6>[ 15.306035] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10447 06:49:43.280620 <6>[ 15.313014] Bluetooth: SCO socket layer initialized
10448 06:49:43.286112 <6>[ 15.318846] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10449 06:49:43.292577 <6>[ 15.319297] usbcore: registered new interface driver cdc_ether
10450 06:49:43.299138 <6>[ 15.319615] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10451 06:49:43.309270 <6>[ 15.322718] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10452 06:49:43.317354 <6>[ 15.323000] usbcore: registered new interface driver uvcvideo
10453 06:49:43.322619 <6>[ 15.337242] usbcore: registered new interface driver r8153_ecm
10454 06:49:43.328789 <6>[ 15.346119] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10455 06:49:43.335921 <6>[ 15.346740] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10456 06:49:43.342766 <6>[ 15.369500] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10457 06:49:43.349459 <6>[ 15.370773] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10458 06:49:43.355169 <6>[ 15.407819] usbcore: registered new interface driver btusb
10459 06:49:43.365469 <4>[ 15.408817] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10460 06:49:43.371949 <3>[ 15.408828] Bluetooth: hci0: Failed to load firmware file (-2)
10461 06:49:43.378114 <3>[ 15.408833] Bluetooth: hci0: Failed to set up firmware (-2)
10462 06:49:43.388727 <4>[ 15.408838] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10463 06:49:43.395118 <6>[ 15.413599] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10464 06:49:43.402265 <6>[ 15.595962] pci 0000:01:00.0: supports D1 D2
10465 06:49:43.408362 <6>[ 15.600482] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10466 06:49:43.424302 <6>[ 15.615715] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10467 06:49:43.431543 <6>[ 15.622611] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10468 06:49:43.437474 <6>[ 15.630697] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10469 06:49:43.447211 <6>[ 15.638692] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10470 06:49:43.454353 <6>[ 15.646692] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10471 06:49:43.463942 <6>[ 15.654693] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10472 06:49:43.468082 <6>[ 15.662693] pci 0000:00:00.0: PCI bridge to [bus 01]
10473 06:49:43.478255 <6>[ 15.667909] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10474 06:49:43.483574 <6>[ 15.676043] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10475 06:49:43.490324 <6>[ 15.682830] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10476 06:49:43.496693 <6>[ 15.689503] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10477 06:49:43.512140 <5>[ 15.702811] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10478 06:49:43.530678 <5>[ 15.721674] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10479 06:49:43.537066 <5>[ 15.728938] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10480 06:49:43.547922 <4>[ 15.737378] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10481 06:49:43.549944 <6>[ 15.746291] cfg80211: failed to load regulatory.db
10482 06:49:43.594200 <6>[ 15.782728] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10483 06:49:43.598149 <6>[ 15.790227] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10484 06:49:43.622149 <6>[ 15.816865] mt7921e 0000:01:00.0: ASIC revision: 79610010
10485 06:49:43.724466 <6>[ 15.915420] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10486 06:49:43.727426 <6>[ 15.915420]
10487 06:49:43.730643 Begin: Loading essential drivers ... done.
10488 06:49:43.734656 Begin: Running /scripts/init-premount ... done.
10489 06:49:43.740341 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10490 06:49:43.750363 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10491 06:49:43.754205 Device /sys/class/net/enx00e04c6803bd found
10492 06:49:43.754673 done.
10493 06:49:43.788992 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10494 06:49:43.994446 <6>[ 16.185783] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10495 06:49:44.833723 <6>[ 17.028908] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10496 06:49:44.930327 <6>[ 17.124765] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10497 06:49:44.958432 IP-Config: no response after 2 secs - giving up
10498 06:49:45.005664 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10499 06:49:45.034109 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10500 06:49:45.739870 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10501 06:49:45.746640 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10502 06:49:45.752355 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10503 06:49:45.760068 host : mt8192-asurada-spherion-r0-cbg-4
10504 06:49:45.765914 domain : lava-rack
10505 06:49:45.769203 rootserver: 192.168.201.1 rootpath:
10506 06:49:45.772212 filename :
10507 06:49:45.868946 done.
10508 06:49:45.875563 Begin: Running /scripts/nfs-bottom ... done.
10509 06:49:45.895255 Begin: Running /scripts/init-bottom ... done.
10510 06:49:47.102545 <6>[ 19.297486] NET: Registered PF_INET6 protocol family
10511 06:49:47.110134 <6>[ 19.305141] Segment Routing with IPv6
10512 06:49:47.113566 <6>[ 19.309142] In-situ OAM (IOAM) with IPv6
10513 06:49:47.258891 <30>[ 19.434002] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10514 06:49:47.265781 <30>[ 19.458557] systemd[1]: Detected architecture arm64.
10515 06:49:47.284398
10516 06:49:47.287708 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10517 06:49:47.288178
10518 06:49:47.303941 <30>[ 19.498477] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10519 06:49:48.154273 <30>[ 20.345909] systemd[1]: Queued start job for default target Graphical Interface.
10520 06:49:48.183334 <30>[ 20.378400] systemd[1]: Created slice system-getty.slice.
10521 06:49:48.190401 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10522 06:49:48.206199 <30>[ 20.401391] systemd[1]: Created slice system-modprobe.slice.
10523 06:49:48.212644 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10524 06:49:48.230037 <30>[ 20.425250] systemd[1]: Created slice system-serial\x2dgetty.slice.
10525 06:49:48.239990 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10526 06:49:48.253653 <30>[ 20.449012] systemd[1]: Created slice User and Session Slice.
10527 06:49:48.261227 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10528 06:49:48.280903 <30>[ 20.472244] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10529 06:49:48.290450 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10530 06:49:48.308833 <30>[ 20.500235] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10531 06:49:48.315696 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10532 06:49:48.335601 <30>[ 20.524060] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10533 06:49:48.341934 <30>[ 20.536200] systemd[1]: Reached target Local Encrypted Volumes.
10534 06:49:48.349189 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10535 06:49:48.365434 <30>[ 20.560582] systemd[1]: Reached target Paths.
10536 06:49:48.372479 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10537 06:49:48.385420 <30>[ 20.579973] systemd[1]: Reached target Remote File Systems.
10538 06:49:48.391547 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10539 06:49:48.409684 <30>[ 20.604329] systemd[1]: Reached target Slices.
10540 06:49:48.416018 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10541 06:49:48.429304 <30>[ 20.623983] systemd[1]: Reached target Swap.
10542 06:49:48.432383 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10543 06:49:48.452893 <30>[ 20.644461] systemd[1]: Listening on initctl Compatibility Named Pipe.
10544 06:49:48.459477 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10545 06:49:48.465554 <30>[ 20.660719] systemd[1]: Listening on Journal Audit Socket.
10546 06:49:48.472542 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10547 06:49:48.490068 <30>[ 20.685303] systemd[1]: Listening on Journal Socket (/dev/log).
10548 06:49:48.496482 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10549 06:49:48.514062 <30>[ 20.708571] systemd[1]: Listening on Journal Socket.
10550 06:49:48.520061 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10551 06:49:48.537650 <30>[ 20.729633] systemd[1]: Listening on Network Service Netlink Socket.
10552 06:49:48.544220 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10553 06:49:48.560269 <30>[ 20.755247] systemd[1]: Listening on udev Control Socket.
10554 06:49:48.566366 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10555 06:49:48.581631 <30>[ 20.776406] systemd[1]: Listening on udev Kernel Socket.
10556 06:49:48.587898 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10557 06:49:48.629140 <30>[ 20.823975] systemd[1]: Mounting Huge Pages File System...
10558 06:49:48.635266 Mounting [0;1;39mHuge Pages File System[0m...
10559 06:49:48.652785 <30>[ 20.848153] systemd[1]: Mounting POSIX Message Queue File System...
10560 06:49:48.659068 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10561 06:49:48.680928 <30>[ 20.876142] systemd[1]: Mounting Kernel Debug File System...
10562 06:49:48.686692 Mounting [0;1;39mKernel Debug File System[0m...
10563 06:49:48.704201 <30>[ 20.896386] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10564 06:49:48.726395 <30>[ 20.918651] systemd[1]: Starting Create list of static device nodes for the current kernel...
10565 06:49:48.733205 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10566 06:49:48.753501 <30>[ 20.948822] systemd[1]: Starting Load Kernel Module configfs...
10567 06:49:48.759685 Starting [0;1;39mLoad Kernel Module configfs[0m...
10568 06:49:48.777097 <30>[ 20.972597] systemd[1]: Starting Load Kernel Module drm...
10569 06:49:48.784459 Starting [0;1;39mLoad Kernel Module drm[0m...
10570 06:49:48.800950 <30>[ 20.996345] systemd[1]: Starting Load Kernel Module fuse...
10571 06:49:48.807951 Starting [0;1;39mLoad Kernel Module fuse[0m...
10572 06:49:48.844482 <30>[ 21.036142] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10573 06:49:48.851518 <6>[ 21.046682] fuse: init (API version 7.37)
10574 06:49:48.885813 <30>[ 21.080553] systemd[1]: Starting Journal Service...
10575 06:49:48.889218 Starting [0;1;39mJournal Service[0m...
10576 06:49:48.912748 <30>[ 21.108097] systemd[1]: Starting Load Kernel Modules...
10577 06:49:48.919969 Starting [0;1;39mLoad Kernel Modules[0m...
10578 06:49:48.940143 <30>[ 21.132275] systemd[1]: Starting Remount Root and Kernel File Systems...
10579 06:49:48.946653 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10580 06:49:48.966081 <30>[ 21.161172] systemd[1]: Starting Coldplug All udev Devices...
10581 06:49:48.973259 Starting [0;1;39mColdplug All udev Devices[0m...
10582 06:49:48.997184 <30>[ 21.192639] systemd[1]: Mounted Huge Pages File System.
10583 06:49:49.010615 [[0;32m OK [0m] Mounted [0;<3>[ 21.200176] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10584 06:49:49.014042 1;39mHuge Pages File System[0m.
10585 06:49:49.029884 <30>[ 21.224438] systemd[1]: Mounted POSIX Message Queue File System.
10586 06:49:49.040101 <3>[ 21.229942] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10587 06:49:49.045723 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10588 06:49:49.061030 <30>[ 21.256294] systemd[1]: Mounted Kernel Debug File System.
10589 06:49:49.067925 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10590 06:49:49.080060 <3>[ 21.271950] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10591 06:49:49.090346 <30>[ 21.282239] systemd[1]: Finished Create list of static device nodes for the current kernel.
10592 06:49:49.097369 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10593 06:49:49.107328 <3>[ 21.299373] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10594 06:49:49.114287 <30>[ 21.309610] systemd[1]: modprobe@configfs.service: Succeeded.
10595 06:49:49.120836 <30>[ 21.316543] systemd[1]: Finished Load Kernel Module configfs.
10596 06:49:49.128299 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10597 06:49:49.146721 <3>[ 21.338562] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10598 06:49:49.153927 <30>[ 21.348954] systemd[1]: modprobe@drm.service: Succeeded.
10599 06:49:49.161459 <30>[ 21.356412] systemd[1]: Finished Load Kernel Module drm.
10600 06:49:49.175189 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 21.365936] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10601 06:49:49.175784 l Module drm[0m.
10602 06:49:49.194350 <30>[ 21.389627] systemd[1]: modprobe@fuse.service: Succeeded.
10603 06:49:49.201808 <30>[ 21.396773] systemd[1]: Finished Load Kernel Module fuse.
10604 06:49:49.216256 [[0;32m OK [0m] Finished [0<3>[ 21.404602] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10605 06:49:49.219641 ;1;39mLoad Kernel Module fuse[0m.
10606 06:49:49.235204 <30>[ 21.430228] systemd[1]: Finished Load Kernel Modules.
10607 06:49:49.245166 <3>[ 21.435551] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10608 06:49:49.248828 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10609 06:49:49.266653 <30>[ 21.460900] systemd[1]: Finished Remount Root and Kernel File Systems.
10610 06:49:49.276011 <3>[ 21.465398] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10611 06:49:49.282499 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10612 06:49:49.305689 <3>[ 21.497821] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10613 06:49:49.332827 <30>[ 21.528283] systemd[1]: Mounting FUSE Control File System...
10614 06:49:49.339648 Mounting [0;1;39mFUSE Control File System[0m...
10615 06:49:49.360872 <30>[ 21.552547] systemd[1]: Mounting Kernel Configuration File System...
10616 06:49:49.363949 Mounting [0;1;39mKernel Configuration File System[0m...
10617 06:49:49.390778 <30>[ 21.582673] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10618 06:49:49.400441 <30>[ 21.592040] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10619 06:49:49.442866 <30>[ 21.637495] systemd[1]: Starting Load/Save Random Seed...
10620 06:49:49.448466 Starting [0;1;39mLoad/Save Random Seed[0m...
10621 06:49:49.470424 <4>[ 21.655756] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10622 06:49:49.479825 <3>[ 21.671431] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10623 06:49:49.483159 <30>[ 21.676929] systemd[1]: Starting Apply Kernel Variables...
10624 06:49:49.489705 Starting [0;1;39mApply Kernel Variables[0m...
10625 06:49:49.515444 <30>[ 21.710342] systemd[1]: Starting Create System Users...
10626 06:49:49.521923 Starting [0;1;39mCreate System Users[0m...
10627 06:49:49.544192 <30>[ 21.739381] systemd[1]: Started Journal Service.
10628 06:49:49.551471 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10629 06:49:49.578151 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10630 06:49:49.596243 See 'systemctl status systemd-udev-trigger.service' for details.
10631 06:49:49.616680 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10632 06:49:49.633447 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10633 06:49:49.654506 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10634 06:49:49.674299 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10635 06:49:49.694386 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10636 06:49:49.733347 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10637 06:49:49.755158 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10638 06:49:49.789810 <46>[ 21.982155] systemd-journald[301]: Received client request to flush runtime journal.
10639 06:49:50.655776 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10640 06:49:50.662840 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10641 06:49:50.677238 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10642 06:49:50.728224 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10643 06:49:51.220913 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10644 06:49:51.262174 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10645 06:49:51.317712 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10646 06:49:51.366779 Starting [0;1;39mNetwork Service[0m...
10647 06:49:51.676575 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10648 06:49:51.699257 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10649 06:49:51.747984 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10650 06:49:52.029644 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10651 06:49:52.047581 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10652 06:49:52.088994 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10653 06:49:52.108422 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10654 06:49:52.124478 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10655 06:49:52.145815 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10656 06:49:52.164976 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10657 06:49:52.241040 Starting [0;1;39mNetwork Name Resolution[0m...
10658 06:49:52.270532 Starting [0;1;39mNetwork Time Synchronization[0m...
10659 06:49:52.293713 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10660 06:49:52.371568 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10661 06:49:52.519017 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10662 06:49:52.537216 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10663 06:49:52.556293 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10664 06:49:52.568361 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10665 06:49:52.584137 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10666 06:49:52.701052 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10667 06:49:52.746885 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10668 06:49:52.773157 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10669 06:49:52.794376 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10670 06:49:52.807962 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10671 06:49:53.074463 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10672 06:49:53.088056 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10673 06:49:53.104274 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10674 06:49:53.148615 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10675 06:49:53.576846 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10676 06:49:53.921025 Starting [0;1;39mUser Login Management[0m...
10677 06:49:53.937893 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10678 06:49:53.954769 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10679 06:49:53.971296 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10680 06:49:54.004488 Starting [0;1;39mPermit User Sessions[0m...
10681 06:49:54.140846 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10682 06:49:54.205658 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10683 06:49:54.236324 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10684 06:49:54.258527 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10685 06:49:54.279999 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10686 06:49:54.301185 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10687 06:49:54.317721 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10688 06:49:54.334827 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10689 06:49:54.383647 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10690 06:49:54.435942 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10691 06:49:54.489307
10692 06:49:54.490040
10693 06:49:54.492547 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10694 06:49:54.493102
10695 06:49:54.526935 debian-bullseye-arm64 login: root (automatic login)
10696 06:49:54.527554
10697 06:49:54.528079
10698 06:49:54.846408 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
10699 06:49:54.847001
10700 06:49:54.852074 The programs included with the Debian GNU/Linux system are free software;
10701 06:49:54.858940 the exact distribution terms for each program are described in the
10702 06:49:54.862325 individual files in /usr/share/doc/*/copyright.
10703 06:49:54.862841
10704 06:49:54.868825 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10705 06:49:54.871909 permitted by applicable law.
10706 06:49:54.971448 Matched prompt #10: / #
10708 06:49:54.972877 Setting prompt string to ['/ #']
10709 06:49:54.973365 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10711 06:49:54.974430 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10712 06:49:54.974906 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10713 06:49:54.975296 Setting prompt string to ['/ #']
10714 06:49:54.975633 Forcing a shell prompt, looking for ['/ #']
10716 06:49:55.026599 / #
10717 06:49:55.027241 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10718 06:49:55.027686 Waiting using forced prompt support (timeout 00:02:30)
10719 06:49:55.033670
10720 06:49:55.034602 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10721 06:49:55.035111 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10723 06:49:55.136475 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694863/extract-nfsrootfs-kuz9jy9o'
10724 06:49:55.143793 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694863/extract-nfsrootfs-kuz9jy9o'
10726 06:49:55.245502 / # export NFS_SERVER_IP='192.168.201.1'
10727 06:49:55.252863 export NFS_SERVER_IP='192.168.201.1'
10728 06:49:55.253800 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10729 06:49:55.254314 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10730 06:49:55.254789 end: 2 depthcharge-action (duration 00:01:26) [common]
10731 06:49:55.255293 start: 3 lava-test-retry (timeout 00:01:00) [common]
10732 06:49:55.255767 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10733 06:49:55.256194 Using namespace: common
10735 06:49:55.357303 / # #
10736 06:49:55.357482 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10737 06:49:55.362678 #
10738 06:49:55.362968 Using /lava-12694863
10740 06:49:55.463715 / # export SHELL=/bin/sh
10741 06:49:55.470275 export SHELL=/bin/sh
10743 06:49:55.572145 / # . /lava-12694863/environment
10744 06:49:55.579133 . /lava-12694863/environment
10746 06:49:55.686837 / # /lava-12694863/bin/lava-test-runner /lava-12694863/0
10747 06:49:55.687473 Test shell timeout: 10s (minimum of the action and connection timeout)
10748 06:49:55.693826 /lava-12694863/bin/lava-test-runner /lava-12694863/0
10749 06:49:55.948168 + export TESTRUN_ID=0_dmesg
10750 06:49:55.951973 + cd /lava-12694863/0/tests/0_dmesg
10751 06:49:55.955561 + cat uuid
10752 06:49:55.970020 + UUID=12694863_<8>[ 28.162718] <LAVA_SIGNAL_STARTRUN 0_dmesg 12694863_1.6.2.3.1>
10753 06:49:55.970589 1.6.2.3.1
10754 06:49:55.970993 + set +x
10755 06:49:55.971639 Received signal: <STARTRUN> 0_dmesg 12694863_1.6.2.3.1
10756 06:49:55.972173 Starting test lava.0_dmesg (12694863_1.6.2.3.1)
10757 06:49:55.972772 Skipping test definition patterns.
10758 06:49:55.976574 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10759 06:49:56.080399 <8>[ 28.273518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10760 06:49:56.081357 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10762 06:49:56.155871 <8>[ 28.348943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10763 06:49:56.156775 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10765 06:49:56.228937 <8>[ 28.421507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10766 06:49:56.229862 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10768 06:49:56.231733 + set +x
10769 06:49:56.234994 <8>[ 28.431129] <LAVA_SIGNAL_ENDRUN 0_dmesg 12694863_1.6.2.3.1>
10770 06:49:56.235912 Received signal: <ENDRUN> 0_dmesg 12694863_1.6.2.3.1
10771 06:49:56.236546 Ending use of test pattern.
10772 06:49:56.237131 Ending test lava.0_dmesg (12694863_1.6.2.3.1), duration 0.26
10774 06:49:56.243330 <LAVA_TEST_RUNNER EXIT>
10775 06:49:56.244053 ok: lava_test_shell seems to have completed
10776 06:49:56.244627 alert: pass
crit: pass
emerg: pass
10777 06:49:56.245128 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10778 06:49:56.245579 end: 3 lava-test-retry (duration 00:00:01) [common]
10779 06:49:56.246031 start: 4 lava-test-retry (timeout 00:01:00) [common]
10780 06:49:56.246473 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10781 06:49:56.246825 Using namespace: common
10783 06:49:56.348058 / # #
10784 06:49:56.348702 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10785 06:49:56.349346 Using /lava-12694863
10787 06:49:56.450473 export SHELL=/bin/sh
10788 06:49:56.451264 #
10790 06:49:56.552869 / # export SHELL=/bin/sh. /lava-12694863/environment
10791 06:49:56.553650
10793 06:49:56.655126 / # . /lava-12694863/environment/lava-12694863/bin/lava-test-runner /lava-12694863/1
10794 06:49:56.655739 Test shell timeout: 10s (minimum of the action and connection timeout)
10795 06:49:56.656312
10796 06:49:56.662125 / # /lava-12694863/bin/lava-test-runner /lava-12694863/1
10797 06:49:56.789131 + export TESTRUN_ID=1_bootrr
10798 06:49:56.792448 + cd /lava-12694863/1/tests/1_bootrr
10799 06:49:56.795857 + cat uuid
10800 06:49:56.805732 + <8>[ 29.002080] <LAVA_SIGNAL_STARTRUN 1_bootrr 12694863_1.6.2.3.5>
10801 06:49:56.806428 Received signal: <STARTRUN> 1_bootrr 12694863_1.6.2.3.5
10802 06:49:56.806779 Starting test lava.1_bootrr (12694863_1.6.2.3.5)
10803 06:49:56.807172 Skipping test definition patterns.
10804 06:49:56.809458 UUID=12694863_1.6.2.3.5
10805 06:49:56.809885 + set +x
10806 06:49:56.822044 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12694863/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
10807 06:49:56.825133 + cd /opt/bootrr/libexec/bootrr
10808 06:49:56.825563 + sh helpers/bootrr-auto
10809 06:49:56.893935 /lava-12694863/1/../bin/lava-test-case
10810 06:49:56.930587 <8>[ 29.123466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10811 06:49:56.931444 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10813 06:49:56.979661 /lava-12694863/1/../bin/lava-test-case
10814 06:49:57.008563 <8>[ 29.201882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10815 06:49:57.009463 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10817 06:49:57.033677 /lava-12694863/1/../bin/lava-test-case
10818 06:49:57.059676 <8>[ 29.252149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
10819 06:49:57.060601 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
10821 06:49:57.116261 /lava-12694863/1/../bin/lava-test-case
10822 06:49:57.143693 <8>[ 29.336859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10823 06:49:57.144538 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10825 06:49:57.183782 /lava-12694863/1/../bin/lava-test-case
10826 06:49:57.213362 <8>[ 29.405809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10827 06:49:57.214205 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10829 06:49:57.247095 /lava-12694863/1/../bin/lava-test-case
10830 06:49:57.271408 <8>[ 29.463779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10831 06:49:57.271771 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10833 06:49:57.301051 /lava-12694863/1/../bin/lava-test-case
10834 06:49:57.322250 <8>[ 29.515358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10835 06:49:57.323120 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10837 06:49:57.356298 /lava-12694863/1/../bin/lava-test-case
10838 06:49:57.385192 <8>[ 29.578929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10839 06:49:57.385544 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10841 06:49:57.405273 /lava-12694863/1/../bin/lava-test-case
10842 06:49:57.432229 <8>[ 29.625136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10843 06:49:57.432661 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10845 06:49:57.473662 /lava-12694863/1/../bin/lava-test-case
10846 06:49:57.501749 <8>[ 29.695122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10847 06:49:57.502305 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10849 06:49:57.526205 /lava-12694863/1/../bin/lava-test-case
10850 06:49:57.554664 <8>[ 29.747648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10851 06:49:57.555465 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10853 06:49:57.592370 /lava-12694863/1/../bin/lava-test-case
10854 06:49:57.622065 <8>[ 29.815381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10855 06:49:57.622920 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10857 06:49:57.658811 /lava-12694863/1/../bin/lava-test-case
10858 06:49:57.686781 <8>[ 29.879662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10859 06:49:57.687654 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10861 06:49:57.723131 /lava-12694863/1/../bin/lava-test-case
10862 06:49:57.750883 <8>[ 29.943801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10863 06:49:57.751765 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10865 06:49:57.789152 /lava-12694863/1/../bin/lava-test-case
10866 06:49:57.812553 <8>[ 30.006253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10867 06:49:57.813086 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10869 06:49:57.833919 /lava-12694863/1/../bin/lava-test-case
10870 06:49:57.858645 <8>[ 30.052047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10871 06:49:57.859594 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10873 06:49:57.892981 /lava-12694863/1/../bin/lava-test-case
10874 06:49:57.924060 <8>[ 30.116985] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10875 06:49:57.924898 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10877 06:49:57.945173 /lava-12694863/1/../bin/lava-test-case
10878 06:49:57.973599 <8>[ 30.166228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10879 06:49:57.974453 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10881 06:49:58.006188 /lava-12694863/1/../bin/lava-test-case
10882 06:49:58.026478 <8>[ 30.219915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10883 06:49:58.026849 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10885 06:49:58.045598 /lava-12694863/1/../bin/lava-test-case
10886 06:49:58.066674 <8>[ 30.259933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10887 06:49:58.067051 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10889 06:49:58.101517 /lava-12694863/1/../bin/lava-test-case
10890 06:49:58.123261 <8>[ 30.316732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10891 06:49:58.124058 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10893 06:49:58.143874 /lava-12694863/1/../bin/lava-test-case
10894 06:49:58.167144 <8>[ 30.360132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10895 06:49:58.167514 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10897 06:49:58.197160 /lava-12694863/1/../bin/lava-test-case
10898 06:49:58.219420 <8>[ 30.412835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10899 06:49:58.220188 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10901 06:49:58.242051 /lava-12694863/1/../bin/lava-test-case
10902 06:49:58.265763 <8>[ 30.459322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10903 06:49:58.266617 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10905 06:49:58.300543 /lava-12694863/1/../bin/lava-test-case
10906 06:49:58.328624 <8>[ 30.521723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10907 06:49:58.329551 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10909 06:49:58.362881 /lava-12694863/1/../bin/lava-test-case
10910 06:49:58.394025 <8>[ 30.587112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10911 06:49:58.394871 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10913 06:49:58.423712 /lava-12694863/1/../bin/lava-test-case
10914 06:49:58.453222 <8>[ 30.646624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10915 06:49:58.454004 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10917 06:49:58.485275 /lava-12694863/1/../bin/lava-test-case
10918 06:49:58.510688 <8>[ 30.704025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10919 06:49:58.511682 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10921 06:49:58.535236 /lava-12694863/1/../bin/lava-test-case
10922 06:49:58.563666 <8>[ 30.756754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10923 06:49:58.564560 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10925 06:49:58.595261 /lava-12694863/1/../bin/lava-test-case
10926 06:49:58.623531 <8>[ 30.817100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10927 06:49:58.624447 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10929 06:49:58.659256 /lava-12694863/1/../bin/lava-test-case
10930 06:49:58.688747 <8>[ 30.882210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10931 06:49:58.689597 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10933 06:49:58.724338 /lava-12694863/1/../bin/lava-test-case
10934 06:49:58.753735 <8>[ 30.946970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10935 06:49:58.754625 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10937 06:49:58.792514 /lava-12694863/1/../bin/lava-test-case
10938 06:49:58.822925 <8>[ 31.016097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10939 06:49:58.823788 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10941 06:49:58.845696 /lava-12694863/1/../bin/lava-test-case
10942 06:49:58.876349 <8>[ 31.069645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10943 06:49:58.877154 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10945 06:49:58.912412 /lava-12694863/1/../bin/lava-test-case
10946 06:49:58.939775 <8>[ 31.132278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10947 06:49:58.940643 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10949 06:49:58.974243 /lava-12694863/1/../bin/lava-test-case
10950 06:49:59.006113 <8>[ 31.199291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10951 06:49:59.006877 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10953 06:49:59.028530 /lava-12694863/1/../bin/lava-test-case
10954 06:49:59.057975 <8>[ 31.251299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10955 06:49:59.058846 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10957 06:49:59.094332 /lava-12694863/1/../bin/lava-test-case
10958 06:49:59.123276 <8>[ 31.316331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10959 06:49:59.124275 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10961 06:49:59.152166 /lava-12694863/1/../bin/lava-test-case
10962 06:49:59.182044 <8>[ 31.375174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10963 06:49:59.182884 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10965 06:49:59.216970 /lava-12694863/1/../bin/lava-test-case
10966 06:49:59.248376 <8>[ 31.441260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10967 06:49:59.249352 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10969 06:49:59.271001 /lava-12694863/1/../bin/lava-test-case
10970 06:49:59.298113 <8>[ 31.491360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10971 06:49:59.299096 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10973 06:49:59.333239 /lava-12694863/1/../bin/lava-test-case
10974 06:49:59.363672 <8>[ 31.556983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10975 06:49:59.364507 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10977 06:49:59.386934 /lava-12694863/1/../bin/lava-test-case
10978 06:49:59.415956 <8>[ 31.609150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10979 06:49:59.416834 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10981 06:49:59.450074 /lava-12694863/1/../bin/lava-test-case
10982 06:49:59.478163 <8>[ 31.670972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
10983 06:49:59.479010 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
10985 06:49:59.505087 /lava-12694863/1/../bin/lava-test-case
10986 06:49:59.533803 <8>[ 31.727229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
10987 06:49:59.534667 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
10989 06:49:59.571024 /lava-12694863/1/../bin/lava-test-case
10990 06:49:59.602952 <8>[ 31.795416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
10991 06:49:59.603901 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
10993 06:49:59.625626 /lava-12694863/1/../bin/lava-test-case
10994 06:49:59.656519 <8>[ 31.849882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
10995 06:49:59.657466 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
10997 06:49:59.691976 /lava-12694863/1/../bin/lava-test-case
10998 06:49:59.721607 <8>[ 31.914803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
10999 06:49:59.722358 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11001 06:49:59.741229 /lava-12694863/1/../bin/lava-test-case
11002 06:49:59.771762 <8>[ 31.965110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11003 06:49:59.772576 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11005 06:49:59.804835 /lava-12694863/1/../bin/lava-test-case
11006 06:49:59.832694 <8>[ 32.026608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11007 06:49:59.833075 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11009 06:49:59.870663 /lava-12694863/1/../bin/lava-test-case
11010 06:49:59.892254 <8>[ 32.086127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11011 06:49:59.892614 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11013 06:49:59.914052 /lava-12694863/1/../bin/lava-test-case
11014 06:49:59.938787 <8>[ 32.132324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11015 06:49:59.939600 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11017 06:49:59.976597 /lava-12694863/1/../bin/lava-test-case
11018 06:50:00.005190 <8>[ 32.198904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11019 06:50:00.005544 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11021 06:50:00.027390 /lava-12694863/1/../bin/lava-test-case
11022 06:50:00.053216 <8>[ 32.247016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11023 06:50:00.053583 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11025 06:50:00.084300 /lava-12694863/1/../bin/lava-test-case
11026 06:50:00.111333 <8>[ 32.305097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11027 06:50:00.111611 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11029 06:50:00.145815 /lava-12694863/1/../bin/lava-test-case
11030 06:50:00.174284 <8>[ 32.367312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11031 06:50:00.175127 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11033 06:50:00.213689 /lava-12694863/1/../bin/lava-test-case
11034 06:50:00.242966 <8>[ 32.436256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11035 06:50:00.243812 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11037 06:50:00.281356 /lava-12694863/1/../bin/lava-test-case
11038 06:50:00.311055 <8>[ 32.504057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11039 06:50:00.311817 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11041 06:50:00.348105 /lava-12694863/1/../bin/lava-test-case
11042 06:50:00.379061 <8>[ 32.571955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11043 06:50:00.379882 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11045 06:50:00.400170 /lava-12694863/1/../bin/lava-test-case
11046 06:50:00.429090 <8>[ 32.622237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11047 06:50:00.429559 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11049 06:50:00.466080 /lava-12694863/1/../bin/lava-test-case
11050 06:50:00.495020 <8>[ 32.688807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11051 06:50:00.495815 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11053 06:50:00.535424 /lava-12694863/1/../bin/lava-test-case
11054 06:50:00.567698 <8>[ 32.761347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11055 06:50:00.568444 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11057 06:50:00.591318 /lava-12694863/1/../bin/lava-test-case
11058 06:50:00.622025 <8>[ 32.815251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11059 06:50:00.622934 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11061 06:50:00.653871 /lava-12694863/1/../bin/lava-test-case
11062 06:50:00.681036 <8>[ 32.874615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11063 06:50:00.681546 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11065 06:50:00.704479 /lava-12694863/1/../bin/lava-test-case
11066 06:50:00.736826 <8>[ 32.929981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11067 06:50:00.737692 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11069 06:50:00.777370 /lava-12694863/1/../bin/lava-test-case
11070 06:50:00.805069 <8>[ 32.998937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11071 06:50:00.805356 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11073 06:50:00.826826 /lava-12694863/1/../bin/lava-test-case
11074 06:50:00.848673 <8>[ 33.041947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11075 06:50:00.849484 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11077 06:50:00.886358 /lava-12694863/1/../bin/lava-test-case
11078 06:50:00.918648 <8>[ 33.112014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11079 06:50:00.919392 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11081 06:50:00.953906 /lava-12694863/1/../bin/lava-test-case
11082 06:50:00.983647 <8>[ 33.177346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11083 06:50:00.984334 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11085 06:50:01.018258 /lava-12694863/1/../bin/lava-test-case
11086 06:50:01.047651 <8>[ 33.241313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11087 06:50:01.048492 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11089 06:50:01.088625 /lava-12694863/1/../bin/lava-test-case
11090 06:50:01.118776 <8>[ 33.312261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11091 06:50:01.119655 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11093 06:50:01.156814 /lava-12694863/1/../bin/lava-test-case
11094 06:50:01.187954 <8>[ 33.381208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11095 06:50:01.188860 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11097 06:50:01.228403 /lava-12694863/1/../bin/lava-test-case
11098 06:50:01.254593 <8>[ 33.447629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11099 06:50:01.255443 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11101 06:50:01.295087 /lava-12694863/1/../bin/lava-test-case
11102 06:50:01.331050 <8>[ 33.523942] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11103 06:50:01.331908 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11105 06:50:01.369890 /lava-12694863/1/../bin/lava-test-case
11106 06:50:01.400444 <8>[ 33.594307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11107 06:50:01.401327 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11109 06:50:01.438871 /lava-12694863/1/../bin/lava-test-case
11110 06:50:01.470575 <8>[ 33.664320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11111 06:50:01.471411 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11113 06:50:01.508316 /lava-12694863/1/../bin/lava-test-case
11114 06:50:01.538980 <8>[ 33.732453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11115 06:50:01.539867 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11117 06:50:01.580467 /lava-12694863/1/../bin/lava-test-case
11118 06:50:01.610467 <8>[ 33.804394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11119 06:50:01.611365 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11121 06:50:01.645229 /lava-12694863/1/../bin/lava-test-case
11122 06:50:01.678242 <8>[ 33.871882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11123 06:50:01.678961 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11125 06:50:01.711818 /lava-12694863/1/../bin/lava-test-case
11126 06:50:01.741602 <8>[ 33.935527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11127 06:50:01.742337 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11129 06:50:01.773854 /lava-12694863/1/../bin/lava-test-case
11130 06:50:01.803141 <8>[ 33.996578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11131 06:50:01.803972 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11133 06:50:01.838488 /lava-12694863/1/../bin/lava-test-case
11134 06:50:01.869457 <8>[ 34.063322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11135 06:50:01.870237 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11137 06:50:01.897745 /lava-12694863/1/../bin/lava-test-case
11138 06:50:01.924500 <8>[ 34.118033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11139 06:50:01.925426 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11141 06:50:01.961832 /lava-12694863/1/../bin/lava-test-case
11142 06:50:01.989069 <8>[ 34.183013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11143 06:50:01.989425 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11145 06:50:02.008472 /lava-12694863/1/../bin/lava-test-case
11146 06:50:02.032186 <8>[ 34.225933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11147 06:50:02.032548 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11149 06:50:02.063001 /lava-12694863/1/../bin/lava-test-case
11150 06:50:02.091586 <8>[ 34.285360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11151 06:50:02.092470 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11153 06:50:02.114999 /lava-12694863/1/../bin/lava-test-case
11154 06:50:02.141105 <8>[ 34.334737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11155 06:50:02.141474 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11157 06:50:02.172595 /lava-12694863/1/../bin/lava-test-case
11158 06:50:02.197396 <8>[ 34.390716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11159 06:50:02.198481 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11161 06:50:02.226487 /lava-12694863/1/../bin/lava-test-case
11162 06:50:02.256158 <8>[ 34.449752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11163 06:50:02.256925 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11165 06:50:02.293376 /lava-12694863/1/../bin/lava-test-case
11166 06:50:02.324099 <8>[ 34.517965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11167 06:50:02.324940 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11169 06:50:02.347508 /lava-12694863/1/../bin/lava-test-case
11170 06:50:02.376384 <8>[ 34.569641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11171 06:50:02.377325 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11173 06:50:02.414213 /lava-12694863/1/../bin/lava-test-case
11174 06:50:02.437825 <8>[ 34.631146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11175 06:50:02.438699 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11177 06:50:02.461199 /lava-12694863/1/../bin/lava-test-case
11178 06:50:02.491244 <8>[ 34.684882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11179 06:50:02.492112 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11181 06:50:02.527387 /lava-12694863/1/../bin/lava-test-case
11182 06:50:02.552215 <8>[ 34.745689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11183 06:50:02.553401 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11185 06:50:02.590939 /lava-12694863/1/../bin/lava-test-case
11186 06:50:02.612416 <8>[ 34.806316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11187 06:50:02.613145 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11189 06:50:02.633897 /lava-12694863/1/../bin/lava-test-case
11190 06:50:02.657338 <8>[ 34.851100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11191 06:50:02.658234 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11193 06:50:02.692113 /lava-12694863/1/../bin/lava-test-case
11194 06:50:02.715533 <8>[ 34.910002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11195 06:50:02.715826 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11197 06:50:02.736611 /lava-12694863/1/../bin/lava-test-case
11198 06:50:02.760594 <8>[ 34.953565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11199 06:50:02.761283 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11201 06:50:02.794757 /lava-12694863/1/../bin/lava-test-case
11202 06:50:02.820116 <8>[ 35.014440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11203 06:50:02.820405 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11205 06:50:02.839343 /lava-12694863/1/../bin/lava-test-case
11206 06:50:02.865128 <8>[ 35.058790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11207 06:50:02.865528 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11209 06:50:03.922109 /lava-12694863/1/../bin/lava-test-case
11210 06:50:03.955433 <8>[ 36.148989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11211 06:50:03.956275 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11213 06:50:03.977046 /lava-12694863/1/../bin/lava-test-case
11214 06:50:04.001435 <8>[ 36.195774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11215 06:50:04.001790 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11217 06:50:05.038761 /lava-12694863/1/../bin/lava-test-case
11218 06:50:05.071307 <8>[ 37.265093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11219 06:50:05.072148 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11221 06:50:05.092891 /lava-12694863/1/../bin/lava-test-case
11222 06:50:05.122066 <8>[ 37.315916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11223 06:50:05.122795 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11225 06:50:06.170058 /lava-12694863/1/../bin/lava-test-case
11226 06:50:06.200653 <8>[ 38.394979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11227 06:50:06.201518 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11229 06:50:06.225170 /lava-12694863/1/../bin/lava-test-case
11230 06:50:06.256260 <8>[ 38.450000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11231 06:50:06.257155 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11233 06:50:07.303608 /lava-12694863/1/../bin/lava-test-case
11234 06:50:07.336001 <8>[ 39.530634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11235 06:50:07.336871 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11237 06:50:07.357499 /lava-12694863/1/../bin/lava-test-case
11238 06:50:07.387778 <8>[ 39.581691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11239 06:50:07.388621 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11241 06:50:08.440609 /lava-12694863/1/../bin/lava-test-case
11242 06:50:08.476215 <8>[ 40.670552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11243 06:50:08.477116 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11245 06:50:08.497513 /lava-12694863/1/../bin/lava-test-case
11246 06:50:08.527295 <8>[ 40.721879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11247 06:50:08.528078 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11249 06:50:09.575347 /lava-12694863/1/../bin/lava-test-case
11250 06:50:09.609402 <8>[ 41.802936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11251 06:50:09.610261 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11253 06:50:09.631568 /lava-12694863/1/../bin/lava-test-case
11254 06:50:09.663961 <8>[ 41.858366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11255 06:50:09.664864 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11257 06:50:10.713739 /lava-12694863/1/../bin/lava-test-case
11258 06:50:10.744980 <8>[ 42.939969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11259 06:50:10.745777 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11261 06:50:10.767238 /lava-12694863/1/../bin/lava-test-case
11262 06:50:10.792191 <8>[ 42.987363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11263 06:50:10.792547 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11265 06:50:10.815082 /lava-12694863/1/../bin/lava-test-case
11266 06:50:10.841796 <8>[ 43.036569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11267 06:50:10.842509 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11269 06:50:11.883017 /lava-12694863/1/../bin/lava-test-case
11270 06:50:11.914209 <8>[ 44.109097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11271 06:50:11.915060 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11273 06:50:11.936898 /lava-12694863/1/../bin/lava-test-case
11274 06:50:11.968379 <8>[ 44.163231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11275 06:50:11.969173 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11277 06:50:12.005976 /lava-12694863/1/../bin/lava-test-case
11278 06:50:12.035530 <8>[ 44.229135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11279 06:50:12.036276 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11281 06:50:12.058416 /lava-12694863/1/../bin/lava-test-case
11282 06:50:12.086282 <8>[ 44.280862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11283 06:50:12.087332 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11285 06:50:12.121210 /lava-12694863/1/../bin/lava-test-case
11286 06:50:12.146589 <8>[ 44.341046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11287 06:50:12.147389 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11289 06:50:12.177898 /lava-12694863/1/../bin/lava-test-case
11290 06:50:12.196244 <8>[ 44.391511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11291 06:50:12.196945 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11293 06:50:12.236597 /lava-12694863/1/../bin/lava-test-case
11294 06:50:12.266344 <8>[ 44.460217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11295 06:50:12.267133 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11297 06:50:12.288597 /lava-12694863/1/../bin/lava-test-case
11298 06:50:12.319337 <8>[ 44.513697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11299 06:50:12.320150 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11301 06:50:12.357623 /lava-12694863/1/../bin/lava-test-case
11302 06:50:12.387398 <8>[ 44.581662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11303 06:50:12.388194 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11305 06:50:12.423857 /lava-12694863/1/../bin/lava-test-case
11306 06:50:12.450374 <8>[ 44.644823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11307 06:50:12.451094 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11309 06:50:12.472510 /lava-12694863/1/../bin/lava-test-case
11310 06:50:12.499992 <8>[ 44.695214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11311 06:50:12.500272 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11313 06:50:12.533440 /lava-12694863/1/../bin/lava-test-case
11314 06:50:12.561590 <8>[ 44.756640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11315 06:50:12.562379 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11317 06:50:12.590101 /lava-12694863/1/../bin/lava-test-case
11318 06:50:12.613573 <8>[ 44.808173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11319 06:50:12.614305 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11321 06:50:12.648332 /lava-12694863/1/../bin/lava-test-case
11322 06:50:12.677600 <8>[ 44.872516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11323 06:50:12.678290 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11325 06:50:12.701236 /lava-12694863/1/../bin/lava-test-case
11326 06:50:12.729085 <8>[ 44.923889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11327 06:50:12.729775 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11329 06:50:12.764697 /lava-12694863/1/../bin/lava-test-case
11330 06:50:12.793133 <8>[ 44.988121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11331 06:50:12.793930 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11333 06:50:12.815121 /lava-12694863/1/../bin/lava-test-case
11334 06:50:12.843552 <8>[ 45.038422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11335 06:50:12.844247 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11337 06:50:12.879311 /lava-12694863/1/../bin/lava-test-case
11338 06:50:12.907232 <8>[ 45.102648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11339 06:50:12.907925 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11341 06:50:12.936432 /lava-12694863/1/../bin/lava-test-case
11342 06:50:12.964828 <8>[ 45.159611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11343 06:50:12.965607 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11345 06:50:12.999630 /lava-12694863/1/../bin/lava-test-case
11346 06:50:13.026637 <8>[ 45.221699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11347 06:50:13.027328 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11349 06:50:13.048487 /lava-12694863/1/../bin/lava-test-case
11350 06:50:13.078223 <8>[ 45.273558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11351 06:50:13.078927 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11353 06:50:13.962794 <6>[ 46.164548] vpu: disabling
11354 06:50:13.966657 <6>[ 46.167667] vproc2: disabling
11355 06:50:13.970210 <6>[ 46.170997] vproc1: disabling
11356 06:50:13.973441 <6>[ 46.174305] vaud18: disabling
11357 06:50:13.979652 <6>[ 46.177814] vsram_others: disabling
11358 06:50:13.982701 <6>[ 46.181838] va09: disabling
11359 06:50:13.986428 <6>[ 46.185005] vsram_md: disabling
11360 06:50:13.989268 <6>[ 46.188568] Vgpu: disabling
11361 06:50:14.131786 /lava-12694863/1/../bin/lava-test-case
11362 06:50:14.162552 <8>[ 46.357642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11363 06:50:14.163364 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11365 06:50:15.208273 /lava-12694863/1/../bin/lava-test-case
11366 06:50:15.241001 <8>[ 47.435489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11367 06:50:15.241703 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11369 06:50:15.261881 /lava-12694863/1/../bin/lava-test-case
11370 06:50:15.289084 <8>[ 47.484411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11371 06:50:15.289778 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11373 06:50:15.324451 /lava-12694863/1/../bin/lava-test-case
11374 06:50:15.355300 <8>[ 47.550292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11375 06:50:15.356092 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11377 06:50:15.375576 /lava-12694863/1/../bin/lava-test-case
11378 06:50:15.404129 <8>[ 47.599111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11379 06:50:15.405021 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11381 06:50:15.437043 /lava-12694863/1/../bin/lava-test-case
11382 06:50:15.466994 <8>[ 47.660777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11383 06:50:15.467855 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11385 06:50:15.487901 /lava-12694863/1/../bin/lava-test-case
11386 06:50:15.515061 <8>[ 47.710704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11387 06:50:15.515838 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11389 06:50:15.556060 /lava-12694863/1/../bin/lava-test-case
11390 06:50:15.586493 <8>[ 47.781937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11391 06:50:15.587475 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11393 06:50:15.607495 /lava-12694863/1/../bin/lava-test-case
11394 06:50:15.637261 <8>[ 47.831471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11395 06:50:15.638053 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11397 06:50:15.670283 /lava-12694863/1/../bin/lava-test-case
11398 06:50:15.700563 <8>[ 47.895924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11399 06:50:15.701337 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11401 06:50:15.723482 /lava-12694863/1/../bin/lava-test-case
11402 06:50:15.753840 <8>[ 47.949111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11403 06:50:15.754628 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11405 06:50:15.791382 /lava-12694863/1/../bin/lava-test-case
11406 06:50:15.819094 <8>[ 48.014411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11407 06:50:15.819937 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11409 06:50:15.842120 /lava-12694863/1/../bin/lava-test-case
11410 06:50:15.870988 <8>[ 48.065765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11411 06:50:15.871886 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11413 06:50:15.911844 /lava-12694863/1/../bin/lava-test-case
11414 06:50:15.938704 <8>[ 48.134219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11415 06:50:15.939486 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11417 06:50:15.960198 /lava-12694863/1/../bin/lava-test-case
11418 06:50:15.988035 <8>[ 48.183328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11419 06:50:15.988765 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11421 06:50:16.024131 /lava-12694863/1/../bin/lava-test-case
11422 06:50:16.054647 <8>[ 48.249959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11423 06:50:16.055333 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11425 06:50:16.077155 /lava-12694863/1/../bin/lava-test-case
11426 06:50:16.108528 <8>[ 48.303784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11427 06:50:16.109350 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11429 06:50:16.142037 /lava-12694863/1/../bin/lava-test-case
11430 06:50:16.173780 <8>[ 48.368843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11431 06:50:16.174652 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11433 06:50:16.195036 /lava-12694863/1/../bin/lava-test-case
11434 06:50:16.226101 <8>[ 48.419956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11435 06:50:16.226841 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11437 06:50:16.264778 /lava-12694863/1/../bin/lava-test-case
11438 06:50:16.292157 <8>[ 48.487160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11439 06:50:16.293012 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11441 06:50:16.311777 /lava-12694863/1/../bin/lava-test-case
11442 06:50:16.340308 <8>[ 48.535647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11443 06:50:16.341260 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11445 06:50:16.376206 /lava-12694863/1/../bin/lava-test-case
11446 06:50:16.405432 <8>[ 48.600973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11447 06:50:16.406255 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11449 06:50:17.438854 /lava-12694863/1/../bin/lava-test-case
11450 06:50:17.469034 <8>[ 49.664690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11451 06:50:17.469850 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11453 06:50:18.501766 /lava-12694863/1/../bin/lava-test-case
11454 06:50:18.533848 <8>[ 50.729249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11455 06:50:18.534771 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11456 06:50:18.535318 Bad test result: blocked
11457 06:50:18.556383 /lava-12694863/1/../bin/lava-test-case
11458 06:50:18.584440 <8>[ 50.779347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11459 06:50:18.585421 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11461 06:50:19.634652 /lava-12694863/1/../bin/lava-test-case
11462 06:50:19.668599 <8>[ 51.864276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11463 06:50:19.669554 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11465 06:50:19.690021 /lava-12694863/1/../bin/lava-test-case
11466 06:50:19.719782 <8>[ 51.914922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11467 06:50:19.720676 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11469 06:50:19.754529 /lava-12694863/1/../bin/lava-test-case
11470 06:50:19.784941 <8>[ 51.981070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11471 06:50:19.785784 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11473 06:50:19.820678 /lava-12694863/1/../bin/lava-test-case
11474 06:50:19.849825 <8>[ 52.044722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11475 06:50:19.850656 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11477 06:50:19.872512 /lava-12694863/1/../bin/lava-test-case
11478 06:50:19.904394 <8>[ 52.100391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11479 06:50:19.905281 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11481 06:50:19.939674 /lava-12694863/1/../bin/lava-test-case
11482 06:50:19.970766 <8>[ 52.166145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11483 06:50:19.971616 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11485 06:50:20.000006 /lava-12694863/1/../bin/lava-test-case
11486 06:50:20.031077 <8>[ 52.226568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11487 06:50:20.031824 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11489 06:50:21.068796 /lava-12694863/1/../bin/lava-test-case
11490 06:50:21.099800 <8>[ 53.295548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11491 06:50:21.100639 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11493 06:50:21.119377 /lava-12694863/1/../bin/lava-test-case
11494 06:50:21.149163 <8>[ 53.343916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11495 06:50:21.150031 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11497 06:50:22.191637 /lava-12694863/1/../bin/lava-test-case
11498 06:50:22.222102 <8>[ 54.417878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11499 06:50:22.222986 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11501 06:50:22.243706 /lava-12694863/1/../bin/lava-test-case
11502 06:50:22.272857 <8>[ 54.469481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11503 06:50:22.273217 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11505 06:50:23.313657 /lava-12694863/1/../bin/lava-test-case
11506 06:50:23.348159 <8>[ 55.543813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11507 06:50:23.348985 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11509 06:50:23.369807 /lava-12694863/1/../bin/lava-test-case
11510 06:50:23.399152 <8>[ 55.595393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11511 06:50:23.399985 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11513 06:50:24.446060 /lava-12694863/1/../bin/lava-test-case
11514 06:50:24.479651 <8>[ 56.675879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11515 06:50:24.480477 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11517 06:50:24.502229 /lava-12694863/1/../bin/lava-test-case
11518 06:50:24.523156 <8>[ 56.719358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11519 06:50:24.523971 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11521 06:50:24.559137 /lava-12694863/1/../bin/lava-test-case
11522 06:50:24.587593 <8>[ 56.784136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11523 06:50:24.588282 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11525 06:50:24.619308 /lava-12694863/1/../bin/lava-test-case
11526 06:50:24.641279 <8>[ 56.838142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11527 06:50:24.641646 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11529 06:50:24.662258 /lava-12694863/1/../bin/lava-test-case
11530 06:50:24.685484 <8>[ 56.882345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11531 06:50:24.685844 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11533 06:50:24.716849 /lava-12694863/1/../bin/lava-test-case
11534 06:50:24.739685 <8>[ 56.935998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11535 06:50:24.740534 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11537 06:50:24.771156 /lava-12694863/1/../bin/lava-test-case
11538 06:50:24.799739 <8>[ 56.995945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11539 06:50:24.800627 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11541 06:50:24.835637 /lava-12694863/1/../bin/lava-test-case
11542 06:50:24.865558 <8>[ 57.061998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11543 06:50:24.866452 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11545 06:50:24.890401 /lava-12694863/1/../bin/lava-test-case
11546 06:50:24.918433 <8>[ 57.114740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11547 06:50:24.919360 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11549 06:50:24.955763 /lava-12694863/1/../bin/lava-test-case
11550 06:50:24.983715 <8>[ 57.179740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11551 06:50:24.984597 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11553 06:50:24.989834 + set +x
11554 06:50:24.992849 Received signal: <ENDRUN> 1_bootrr 12694863_1.6.2.3.5
11555 06:50:24.993340 Ending use of test pattern.
11556 06:50:24.993707 Ending test lava.1_bootrr (12694863_1.6.2.3.5), duration 28.19
11558 06:50:24.995768 <8>[ 57.192072] <LAVA_SIGNAL_ENDRUN 1_bootrr 12694863_1.6.2.3.5>
11559 06:50:25.000285 <LAVA_TEST_RUNNER EXIT>
11560 06:50:25.001079 ok: lava_test_shell seems to have completed
11561 06:50:25.007923 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11562 06:50:25.008748 end: 4.1 lava-test-shell (duration 00:00:29) [common]
11563 06:50:25.009233 end: 4 lava-test-retry (duration 00:00:29) [common]
11564 06:50:25.009715 start: 5 finalize (timeout 00:07:37) [common]
11565 06:50:25.010199 start: 5.1 power-off (timeout 00:00:30) [common]
11566 06:50:25.011131 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11567 06:50:25.138214 >> Command sent successfully.
11568 06:50:25.142632 Returned 0 in 0 seconds
11569 06:50:25.243704 end: 5.1 power-off (duration 00:00:00) [common]
11571 06:50:25.245452 start: 5.2 read-feedback (timeout 00:07:37) [common]
11572 06:50:25.246797 Listened to connection for namespace 'common' for up to 1s
11573 06:50:26.247390 Finalising connection for namespace 'common'
11574 06:50:26.248084 Disconnecting from shell: Finalise
11575 06:50:26.248521 / #
11576 06:50:26.349624 end: 5.2 read-feedback (duration 00:00:01) [common]
11577 06:50:26.350473 end: 5 finalize (duration 00:00:01) [common]
11578 06:50:26.351132 Cleaning after the job
11579 06:50:26.351708 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/ramdisk
11580 06:50:26.365306 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/kernel
11581 06:50:26.401585 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/dtb
11582 06:50:26.401897 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/nfsrootfs
11583 06:50:26.480287 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694863/tftp-deploy-urr229ql/modules
11584 06:50:26.487899 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694863
11585 06:50:26.871385 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694863
11586 06:50:26.871565 Job finished correctly