Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 13
- Kernel Errors: 35
1 06:53:01.789686 lava-dispatcher, installed at version: 2023.10
2 06:53:01.789902 start: 0 validate
3 06:53:01.790037 Start time: 2024-02-03 06:53:01.790029+00:00 (UTC)
4 06:53:01.790207 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:53:01.790351 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 06:53:02.056211 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:53:02.056421 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:53:02.313638 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:53:02.313809 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:53:02.579217 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:53:02.579397 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 06:53:02.844972 validate duration: 1.05
14 06:53:02.845244 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:53:02.845338 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:53:02.845428 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:53:02.845548 Not decompressing ramdisk as can be used compressed.
18 06:53:02.845631 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 06:53:02.845698 saving as /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/ramdisk/rootfs.cpio.gz
20 06:53:02.845760 total size: 34390042 (32 MB)
21 06:53:02.846807 progress 0 % (0 MB)
22 06:53:02.855944 progress 5 % (1 MB)
23 06:53:02.865080 progress 10 % (3 MB)
24 06:53:02.874171 progress 15 % (4 MB)
25 06:53:02.883225 progress 20 % (6 MB)
26 06:53:02.892283 progress 25 % (8 MB)
27 06:53:02.901135 progress 30 % (9 MB)
28 06:53:02.910204 progress 35 % (11 MB)
29 06:53:02.919275 progress 40 % (13 MB)
30 06:53:02.928391 progress 45 % (14 MB)
31 06:53:02.937273 progress 50 % (16 MB)
32 06:53:02.946327 progress 55 % (18 MB)
33 06:53:02.955131 progress 60 % (19 MB)
34 06:53:02.964260 progress 65 % (21 MB)
35 06:53:02.973254 progress 70 % (22 MB)
36 06:53:02.982348 progress 75 % (24 MB)
37 06:53:02.991582 progress 80 % (26 MB)
38 06:53:03.000755 progress 85 % (27 MB)
39 06:53:03.009694 progress 90 % (29 MB)
40 06:53:03.018842 progress 95 % (31 MB)
41 06:53:03.028013 progress 100 % (32 MB)
42 06:53:03.028274 32 MB downloaded in 0.18 s (179.70 MB/s)
43 06:53:03.028498 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:53:03.028760 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:53:03.028847 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:53:03.028929 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:53:03.029076 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 06:53:03.029143 saving as /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/kernel/Image
50 06:53:03.029204 total size: 51532288 (49 MB)
51 06:53:03.029265 No compression specified
52 06:53:03.030408 progress 0 % (0 MB)
53 06:53:03.045337 progress 5 % (2 MB)
54 06:53:03.059288 progress 10 % (4 MB)
55 06:53:03.072988 progress 15 % (7 MB)
56 06:53:03.086683 progress 20 % (9 MB)
57 06:53:03.100461 progress 25 % (12 MB)
58 06:53:03.114210 progress 30 % (14 MB)
59 06:53:03.127754 progress 35 % (17 MB)
60 06:53:03.141474 progress 40 % (19 MB)
61 06:53:03.155060 progress 45 % (22 MB)
62 06:53:03.169535 progress 50 % (24 MB)
63 06:53:03.183207 progress 55 % (27 MB)
64 06:53:03.196877 progress 60 % (29 MB)
65 06:53:03.210556 progress 65 % (31 MB)
66 06:53:03.224199 progress 70 % (34 MB)
67 06:53:03.237686 progress 75 % (36 MB)
68 06:53:03.251151 progress 80 % (39 MB)
69 06:53:03.264629 progress 85 % (41 MB)
70 06:53:03.278133 progress 90 % (44 MB)
71 06:53:03.291685 progress 95 % (46 MB)
72 06:53:03.304988 progress 100 % (49 MB)
73 06:53:03.305220 49 MB downloaded in 0.28 s (178.05 MB/s)
74 06:53:03.305369 end: 1.2.1 http-download (duration 00:00:00) [common]
76 06:53:03.305605 end: 1.2 download-retry (duration 00:00:00) [common]
77 06:53:03.305696 start: 1.3 download-retry (timeout 00:10:00) [common]
78 06:53:03.305782 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 06:53:03.305932 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 06:53:03.306004 saving as /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/dtb/mt8192-asurada-spherion-r0.dtb
81 06:53:03.306065 total size: 47278 (0 MB)
82 06:53:03.306125 No compression specified
83 06:53:03.307353 progress 69 % (0 MB)
84 06:53:03.307639 progress 100 % (0 MB)
85 06:53:03.307794 0 MB downloaded in 0.00 s (26.11 MB/s)
86 06:53:03.307917 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:53:03.308135 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:53:03.308217 start: 1.4 download-retry (timeout 00:10:00) [common]
90 06:53:03.308324 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 06:53:03.308458 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 06:53:03.308529 saving as /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/modules/modules.tar
93 06:53:03.308589 total size: 8624064 (8 MB)
94 06:53:03.308649 Using unxz to decompress xz
95 06:53:03.312588 progress 0 % (0 MB)
96 06:53:03.334045 progress 5 % (0 MB)
97 06:53:03.357800 progress 10 % (0 MB)
98 06:53:03.382816 progress 15 % (1 MB)
99 06:53:03.406962 progress 20 % (1 MB)
100 06:53:03.431538 progress 25 % (2 MB)
101 06:53:03.457743 progress 30 % (2 MB)
102 06:53:03.483987 progress 35 % (2 MB)
103 06:53:03.507275 progress 40 % (3 MB)
104 06:53:03.531600 progress 45 % (3 MB)
105 06:53:03.557130 progress 50 % (4 MB)
106 06:53:03.581861 progress 55 % (4 MB)
107 06:53:03.606498 progress 60 % (4 MB)
108 06:53:03.634106 progress 65 % (5 MB)
109 06:53:03.658960 progress 70 % (5 MB)
110 06:53:03.682571 progress 75 % (6 MB)
111 06:53:03.709882 progress 80 % (6 MB)
112 06:53:03.735578 progress 85 % (7 MB)
113 06:53:03.760876 progress 90 % (7 MB)
114 06:53:03.792323 progress 95 % (7 MB)
115 06:53:03.820168 progress 100 % (8 MB)
116 06:53:03.825127 8 MB downloaded in 0.52 s (15.92 MB/s)
117 06:53:03.825363 end: 1.4.1 http-download (duration 00:00:01) [common]
119 06:53:03.825625 end: 1.4 download-retry (duration 00:00:01) [common]
120 06:53:03.825718 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 06:53:03.825815 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 06:53:03.825894 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:53:03.825985 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 06:53:03.826206 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1
125 06:53:03.826340 makedir: /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin
126 06:53:03.826447 makedir: /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/tests
127 06:53:03.826545 makedir: /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/results
128 06:53:03.826660 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-add-keys
129 06:53:03.826806 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-add-sources
130 06:53:03.826940 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-background-process-start
131 06:53:03.827067 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-background-process-stop
132 06:53:03.827193 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-common-functions
133 06:53:03.827317 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-echo-ipv4
134 06:53:03.827442 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-install-packages
135 06:53:03.827566 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-installed-packages
136 06:53:03.827689 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-os-build
137 06:53:03.827813 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-probe-channel
138 06:53:03.827936 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-probe-ip
139 06:53:03.828060 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-target-ip
140 06:53:03.828183 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-target-mac
141 06:53:03.828351 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-target-storage
142 06:53:03.828482 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-test-case
143 06:53:03.828610 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-test-event
144 06:53:03.828733 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-test-feedback
145 06:53:03.828858 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-test-raise
146 06:53:03.828984 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-test-reference
147 06:53:03.829108 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-test-runner
148 06:53:03.829232 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-test-set
149 06:53:03.829356 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-test-shell
150 06:53:03.829483 Updating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-install-packages (oe)
151 06:53:03.829634 Updating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/bin/lava-installed-packages (oe)
152 06:53:03.829761 Creating /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/environment
153 06:53:03.829862 LAVA metadata
154 06:53:03.829933 - LAVA_JOB_ID=12694812
155 06:53:03.829994 - LAVA_DISPATCHER_IP=192.168.201.1
156 06:53:03.830095 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 06:53:03.830160 skipped lava-vland-overlay
158 06:53:03.830233 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 06:53:03.830311 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 06:53:03.830379 skipped lava-multinode-overlay
161 06:53:03.830453 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 06:53:03.830537 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 06:53:03.830611 Loading test definitions
164 06:53:03.830702 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 06:53:03.830774 Using /lava-12694812 at stage 0
166 06:53:03.831080 uuid=12694812_1.5.2.3.1 testdef=None
167 06:53:03.831166 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 06:53:03.831248 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 06:53:03.831779 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 06:53:03.832002 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 06:53:03.832758 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 06:53:03.832984 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 06:53:03.833571 runner path: /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/0/tests/0_cros-ec test_uuid 12694812_1.5.2.3.1
176 06:53:03.833723 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 06:53:03.833922 Creating lava-test-runner.conf files
179 06:53:03.833983 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694812/lava-overlay-vfk2hjn1/lava-12694812/0 for stage 0
180 06:53:03.834071 - 0_cros-ec
181 06:53:03.834172 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 06:53:03.834353 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 06:53:03.841327 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 06:53:03.841435 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 06:53:03.841525 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 06:53:03.841626 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 06:53:03.841714 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 06:53:04.862746 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 06:53:04.863114 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 06:53:04.863239 extracting modules file /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694812/extract-overlay-ramdisk-q2blq24r/ramdisk
191 06:53:05.096446 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 06:53:05.096668 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 06:53:05.096800 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694812/compress-overlay-ev8l6wi0/overlay-1.5.2.4.tar.gz to ramdisk
194 06:53:05.096872 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694812/compress-overlay-ev8l6wi0/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694812/extract-overlay-ramdisk-q2blq24r/ramdisk
195 06:53:05.104265 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 06:53:05.104464 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 06:53:05.104556 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 06:53:05.104647 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 06:53:05.104721 Building ramdisk /var/lib/lava/dispatcher/tmp/12694812/extract-overlay-ramdisk-q2blq24r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694812/extract-overlay-ramdisk-q2blq24r/ramdisk
200 06:53:05.950562 >> 271099 blocks
201 06:53:10.700743 rename /var/lib/lava/dispatcher/tmp/12694812/extract-overlay-ramdisk-q2blq24r/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/ramdisk/ramdisk.cpio.gz
202 06:53:10.701214 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 06:53:10.701418 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 06:53:10.701580 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 06:53:10.701747 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/kernel/Image'
206 06:53:23.954427 Returned 0 in 13 seconds
207 06:53:24.055054 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/kernel/image.itb
208 06:53:24.766958 output: FIT description: Kernel Image image with one or more FDT blobs
209 06:53:24.767328 output: Created: Sat Feb 3 06:53:24 2024
210 06:53:24.767441 output: Image 0 (kernel-1)
211 06:53:24.767544 output: Description:
212 06:53:24.767631 output: Created: Sat Feb 3 06:53:24 2024
213 06:53:24.767717 output: Type: Kernel Image
214 06:53:24.767796 output: Compression: lzma compressed
215 06:53:24.767892 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
216 06:53:24.767988 output: Architecture: AArch64
217 06:53:24.768082 output: OS: Linux
218 06:53:24.768176 output: Load Address: 0x00000000
219 06:53:24.768273 output: Entry Point: 0x00000000
220 06:53:24.768404 output: Hash algo: crc32
221 06:53:24.768498 output: Hash value: 380e7c3c
222 06:53:24.768593 output: Image 1 (fdt-1)
223 06:53:24.768685 output: Description: mt8192-asurada-spherion-r0
224 06:53:24.768775 output: Created: Sat Feb 3 06:53:24 2024
225 06:53:24.768866 output: Type: Flat Device Tree
226 06:53:24.768957 output: Compression: uncompressed
227 06:53:24.769046 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 06:53:24.769137 output: Architecture: AArch64
229 06:53:24.769239 output: Hash algo: crc32
230 06:53:24.769327 output: Hash value: cc4352de
231 06:53:24.769409 output: Image 2 (ramdisk-1)
232 06:53:24.769490 output: Description: unavailable
233 06:53:24.769577 output: Created: Sat Feb 3 06:53:24 2024
234 06:53:24.769663 output: Type: RAMDisk Image
235 06:53:24.769744 output: Compression: Unknown Compression
236 06:53:24.769825 output: Data Size: 47541966 Bytes = 46427.70 KiB = 45.34 MiB
237 06:53:24.769906 output: Architecture: AArch64
238 06:53:24.769987 output: OS: Linux
239 06:53:24.770068 output: Load Address: unavailable
240 06:53:24.770149 output: Entry Point: unavailable
241 06:53:24.770240 output: Hash algo: crc32
242 06:53:24.770322 output: Hash value: 89e3405b
243 06:53:24.770403 output: Default Configuration: 'conf-1'
244 06:53:24.770485 output: Configuration 0 (conf-1)
245 06:53:24.770540 output: Description: mt8192-asurada-spherion-r0
246 06:53:24.770593 output: Kernel: kernel-1
247 06:53:24.770645 output: Init Ramdisk: ramdisk-1
248 06:53:24.770696 output: FDT: fdt-1
249 06:53:24.770747 output: Loadables: kernel-1
250 06:53:24.770798 output:
251 06:53:24.770995 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 06:53:24.771091 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 06:53:24.771188 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 06:53:24.771281 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 06:53:24.771360 No LXC device requested
256 06:53:24.771439 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 06:53:24.771520 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 06:53:24.771597 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 06:53:24.771665 Checking files for TFTP limit of 4294967296 bytes.
260 06:53:24.772169 end: 1 tftp-deploy (duration 00:00:22) [common]
261 06:53:24.772270 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 06:53:24.772402 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 06:53:24.772525 substitutions:
264 06:53:24.772591 - {DTB}: 12694812/tftp-deploy-j7wt1w4y/dtb/mt8192-asurada-spherion-r0.dtb
265 06:53:24.772656 - {INITRD}: 12694812/tftp-deploy-j7wt1w4y/ramdisk/ramdisk.cpio.gz
266 06:53:24.772715 - {KERNEL}: 12694812/tftp-deploy-j7wt1w4y/kernel/Image
267 06:53:24.772772 - {LAVA_MAC}: None
268 06:53:24.772827 - {PRESEED_CONFIG}: None
269 06:53:24.772882 - {PRESEED_LOCAL}: None
270 06:53:24.772935 - {RAMDISK}: 12694812/tftp-deploy-j7wt1w4y/ramdisk/ramdisk.cpio.gz
271 06:53:24.772989 - {ROOT_PART}: None
272 06:53:24.773041 - {ROOT}: None
273 06:53:24.773095 - {SERVER_IP}: 192.168.201.1
274 06:53:24.773147 - {TEE}: None
275 06:53:24.773200 Parsed boot commands:
276 06:53:24.773253 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 06:53:24.773426 Parsed boot commands: tftpboot 192.168.201.1 12694812/tftp-deploy-j7wt1w4y/kernel/image.itb 12694812/tftp-deploy-j7wt1w4y/kernel/cmdline
278 06:53:24.773512 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 06:53:24.773598 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 06:53:24.773689 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 06:53:24.773770 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 06:53:24.773836 Not connected, no need to disconnect.
283 06:53:24.773907 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 06:53:24.774008 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 06:53:24.774074 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 06:53:24.777885 Setting prompt string to ['lava-test: # ']
287 06:53:24.778293 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 06:53:24.778438 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 06:53:24.778611 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 06:53:24.778738 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 06:53:24.778978 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 06:53:29.923474 >> Command sent successfully.
293 06:53:29.934340 Returned 0 in 5 seconds
294 06:53:30.035521 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 06:53:30.036975 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 06:53:30.037509 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 06:53:30.037932 Setting prompt string to 'Starting depthcharge on Spherion...'
299 06:53:30.038430 Changing prompt to 'Starting depthcharge on Spherion...'
300 06:53:30.038901 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 06:53:30.040507 [Enter `^Ec?' for help]
302 06:53:30.199118
303 06:53:30.199618
304 06:53:30.199968 F0: 102B 0000
305 06:53:30.200347
306 06:53:30.200667 F3: 1001 0000 [0200]
307 06:53:30.201143
308 06:53:30.202646 F3: 1001 0000
309 06:53:30.203070
310 06:53:30.203404 F7: 102D 0000
311 06:53:30.203718
312 06:53:30.206566 F1: 0000 0000
313 06:53:30.206995
314 06:53:30.207464 V0: 0000 0000 [0001]
315 06:53:30.207926
316 06:53:30.208249 00: 0007 8000
317 06:53:30.208675
318 06:53:30.209650 01: 0000 0000
319 06:53:30.210080
320 06:53:30.210415 BP: 0C00 0209 [0000]
321 06:53:30.210726
322 06:53:30.213687 G0: 1182 0000
323 06:53:30.214159
324 06:53:30.214499 EC: 0000 0021 [4000]
325 06:53:30.214814
326 06:53:30.216993 S7: 0000 0000 [0000]
327 06:53:30.217456
328 06:53:30.217796 CC: 0000 0000 [0001]
329 06:53:30.218115
330 06:53:30.220490 T0: 0000 0040 [010F]
331 06:53:30.220917
332 06:53:30.221258 Jump to BL
333 06:53:30.221573
334 06:53:30.246644
335 06:53:30.247375
336 06:53:30.247950
337 06:53:30.254110 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 06:53:30.257787 ARM64: Exception handlers installed.
339 06:53:30.261142 ARM64: Testing exception
340 06:53:30.261566 ARM64: Done test exception
341 06:53:30.268501 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 06:53:30.279878 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 06:53:30.286192 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 06:53:30.296637 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 06:53:30.303700 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 06:53:30.313966 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 06:53:30.324367 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 06:53:30.331384 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 06:53:30.348599 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 06:53:30.352108 WDT: Last reset was cold boot
351 06:53:30.355520 SPI1(PAD0) initialized at 2873684 Hz
352 06:53:30.359148 SPI5(PAD0) initialized at 992727 Hz
353 06:53:30.362581 VBOOT: Loading verstage.
354 06:53:30.369210 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 06:53:30.373262 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 06:53:30.376634 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 06:53:30.379489 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 06:53:30.385995 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 06:53:30.392800 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 06:53:30.404059 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 06:53:30.404637
362 06:53:30.404974
363 06:53:30.414222 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 06:53:30.417706 ARM64: Exception handlers installed.
365 06:53:30.421133 ARM64: Testing exception
366 06:53:30.421591 ARM64: Done test exception
367 06:53:30.428008 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 06:53:30.431379 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 06:53:30.444556 Probing TPM: . done!
370 06:53:30.445106 TPM ready after 0 ms
371 06:53:30.452492 Connected to device vid:did:rid of 1ae0:0028:00
372 06:53:30.459490 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 06:53:30.519799 Initialized TPM device CR50 revision 0
374 06:53:30.529690 tlcl_send_startup: Startup return code is 0
375 06:53:30.530120 TPM: setup succeeded
376 06:53:30.540795 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 06:53:30.549855 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 06:53:30.562473 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 06:53:30.570409 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 06:53:30.573446 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 06:53:30.578980 in-header: 03 07 00 00 08 00 00 00
382 06:53:30.582675 in-data: aa e4 47 04 13 02 00 00
383 06:53:30.586282 Chrome EC: UHEPI supported
384 06:53:30.593601 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 06:53:30.597154 in-header: 03 95 00 00 08 00 00 00
386 06:53:30.597573 in-data: 18 20 20 08 00 00 00 00
387 06:53:30.600726 Phase 1
388 06:53:30.605030 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 06:53:30.608537 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 06:53:30.615463 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 06:53:30.618827 Recovery requested (1009000e)
392 06:53:30.625470 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 06:53:30.631381 tlcl_extend: response is 0
394 06:53:30.641256 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 06:53:30.644859 tlcl_extend: response is 0
396 06:53:30.651053 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 06:53:30.671569 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 06:53:30.678388 BS: bootblock times (exec / console): total (unknown) / 149 ms
399 06:53:30.678918
400 06:53:30.679378
401 06:53:30.688407 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 06:53:30.691818 ARM64: Exception handlers installed.
403 06:53:30.694834 ARM64: Testing exception
404 06:53:30.695269 ARM64: Done test exception
405 06:53:30.717030 pmic_efuse_setting: Set efuses in 11 msecs
406 06:53:30.720474 pmwrap_interface_init: Select PMIF_VLD_RDY
407 06:53:30.727232 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 06:53:30.730610 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 06:53:30.737505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 06:53:30.741506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 06:53:30.745100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 06:53:30.752404 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 06:53:30.756057 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 06:53:30.760644 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 06:53:30.763639 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 06:53:30.768182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 06:53:30.775803 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 06:53:30.779490 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 06:53:30.783625 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 06:53:30.791089 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 06:53:30.794416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 06:53:30.801937 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 06:53:30.805966 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 06:53:30.813120 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 06:53:30.816851 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 06:53:30.824239 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 06:53:30.828226 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 06:53:30.835497 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 06:53:30.839280 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 06:53:30.846470 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 06:53:30.849900 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 06:53:30.857647 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 06:53:30.861167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 06:53:30.869020 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 06:53:30.872101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 06:53:30.876366 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 06:53:30.883942 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 06:53:30.886724 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 06:53:30.890912 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 06:53:30.897725 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 06:53:30.901738 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 06:53:30.905136 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 06:53:30.912628 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 06:53:30.916828 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 06:53:30.920207 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 06:53:30.924217 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 06:53:30.931459 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 06:53:30.935173 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 06:53:30.938838 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 06:53:30.942904 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 06:53:30.946308 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 06:53:30.949946 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 06:53:30.953640 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 06:53:30.961384 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 06:53:30.965473 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 06:53:30.968980 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 06:53:30.973064 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 06:53:30.980102 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 06:53:30.987565 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 06:53:30.991362 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 06:53:31.002624 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 06:53:31.010101 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 06:53:31.013619 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 06:53:31.017624 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 06:53:31.024802 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 06:53:31.028832 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 06:53:31.035918 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 06:53:31.039940 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 06:53:31.043360 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 06:53:31.054579 [RTC]rtc_get_frequency_meter,154: input=15, output=758
471 06:53:31.064018 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 06:53:31.074196 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 06:53:31.083713 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 06:53:31.093616 [RTC]rtc_get_frequency_meter,154: input=16, output=783
475 06:53:31.102635 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 06:53:31.112428 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 06:53:31.116246 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 06:53:31.119680 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 06:53:31.123808 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 06:53:31.131370 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 06:53:31.134946 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 06:53:31.138414 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 06:53:31.143141 ADC[4]: Raw value=906203 ID=7
484 06:53:31.143568 ADC[3]: Raw value=213810 ID=1
485 06:53:31.146593 RAM Code: 0x71
486 06:53:31.150100 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 06:53:31.154392 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 06:53:31.161745 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 06:53:31.168681 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 06:53:31.172403 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 06:53:31.176357 in-header: 03 07 00 00 08 00 00 00
492 06:53:31.179779 in-data: aa e4 47 04 13 02 00 00
493 06:53:31.183087 Chrome EC: UHEPI supported
494 06:53:31.187041 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 06:53:31.191315 in-header: 03 95 00 00 08 00 00 00
496 06:53:31.195122 in-data: 18 20 20 08 00 00 00 00
497 06:53:31.198716 MRC: failed to locate region type 0.
498 06:53:31.206224 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 06:53:31.209460 DRAM-K: Running full calibration
500 06:53:31.213157 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 06:53:31.217013 header.status = 0x0
502 06:53:31.220919 header.version = 0x6 (expected: 0x6)
503 06:53:31.224722 header.size = 0xd00 (expected: 0xd00)
504 06:53:31.225217 header.flags = 0x0
505 06:53:31.231789 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 06:53:31.249633 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 06:53:31.257330 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 06:53:31.257768 dram_init: ddr_geometry: 2
509 06:53:31.261448 [EMI] MDL number = 2
510 06:53:31.261945 [EMI] Get MDL freq = 0
511 06:53:31.265579 dram_init: ddr_type: 0
512 06:53:31.266101 is_discrete_lpddr4: 1
513 06:53:31.269209 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 06:53:31.269722
515 06:53:31.270294
516 06:53:31.272911 [Bian_co] ETT version 0.0.0.1
517 06:53:31.276808 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 06:53:31.277262
519 06:53:31.280872 dramc_set_vcore_voltage set vcore to 650000
520 06:53:31.283900 Read voltage for 800, 4
521 06:53:31.284367 Vio18 = 0
522 06:53:31.287900 Vcore = 650000
523 06:53:31.288369 Vdram = 0
524 06:53:31.288854 Vddq = 0
525 06:53:31.289187 Vmddr = 0
526 06:53:31.291391 dram_init: config_dvfs: 1
527 06:53:31.295270 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 06:53:31.303463 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 06:53:31.306594 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 06:53:31.310381 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 06:53:31.314500 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 06:53:31.317779 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 06:53:31.318222 MEM_TYPE=3, freq_sel=18
534 06:53:31.321393 sv_algorithm_assistance_LP4_1600
535 06:53:31.324747 ============ PULL DRAM RESETB DOWN ============
536 06:53:31.332126 ========== PULL DRAM RESETB DOWN end =========
537 06:53:31.335230 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 06:53:31.338279 ===================================
539 06:53:31.341786 LPDDR4 DRAM CONFIGURATION
540 06:53:31.345829 ===================================
541 06:53:31.346351 EX_ROW_EN[0] = 0x0
542 06:53:31.349120 EX_ROW_EN[1] = 0x0
543 06:53:31.349732 LP4Y_EN = 0x0
544 06:53:31.353286 WORK_FSP = 0x0
545 06:53:31.353713 WL = 0x2
546 06:53:31.354053 RL = 0x2
547 06:53:31.356766 BL = 0x2
548 06:53:31.357337 RPST = 0x0
549 06:53:31.361096 RD_PRE = 0x0
550 06:53:31.361523 WR_PRE = 0x1
551 06:53:31.364585 WR_PST = 0x0
552 06:53:31.365054 DBI_WR = 0x0
553 06:53:31.368207 DBI_RD = 0x0
554 06:53:31.368698 OTF = 0x1
555 06:53:31.371767 ===================================
556 06:53:31.374610 ===================================
557 06:53:31.377827 ANA top config
558 06:53:31.381069 ===================================
559 06:53:31.381497 DLL_ASYNC_EN = 0
560 06:53:31.384576 ALL_SLAVE_EN = 1
561 06:53:31.387816 NEW_RANK_MODE = 1
562 06:53:31.391567 DLL_IDLE_MODE = 1
563 06:53:31.391990 LP45_APHY_COMB_EN = 1
564 06:53:31.395005 TX_ODT_DIS = 1
565 06:53:31.397830 NEW_8X_MODE = 1
566 06:53:31.401903 ===================================
567 06:53:31.405401 ===================================
568 06:53:31.408876 data_rate = 1600
569 06:53:31.409320 CKR = 1
570 06:53:31.411600 DQ_P2S_RATIO = 8
571 06:53:31.415083 ===================================
572 06:53:31.418250 CA_P2S_RATIO = 8
573 06:53:31.421835 DQ_CA_OPEN = 0
574 06:53:31.425396 DQ_SEMI_OPEN = 0
575 06:53:31.428822 CA_SEMI_OPEN = 0
576 06:53:31.429295 CA_FULL_RATE = 0
577 06:53:31.431558 DQ_CKDIV4_EN = 1
578 06:53:31.434995 CA_CKDIV4_EN = 1
579 06:53:31.438475 CA_PREDIV_EN = 0
580 06:53:31.441995 PH8_DLY = 0
581 06:53:31.445270 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 06:53:31.445737 DQ_AAMCK_DIV = 4
583 06:53:31.448494 CA_AAMCK_DIV = 4
584 06:53:31.451512 CA_ADMCK_DIV = 4
585 06:53:31.455126 DQ_TRACK_CA_EN = 0
586 06:53:31.458399 CA_PICK = 800
587 06:53:31.461926 CA_MCKIO = 800
588 06:53:31.462350 MCKIO_SEMI = 0
589 06:53:31.465020 PLL_FREQ = 3068
590 06:53:31.469155 DQ_UI_PI_RATIO = 32
591 06:53:31.472675 CA_UI_PI_RATIO = 0
592 06:53:31.476572 ===================================
593 06:53:31.480018 ===================================
594 06:53:31.480667 memory_type:LPDDR4
595 06:53:31.484173 GP_NUM : 10
596 06:53:31.484679 SRAM_EN : 1
597 06:53:31.487709 MD32_EN : 0
598 06:53:31.491178 ===================================
599 06:53:31.491599 [ANA_INIT] >>>>>>>>>>>>>>
600 06:53:31.495185 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 06:53:31.499011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 06:53:31.502751 ===================================
603 06:53:31.506185 data_rate = 1600,PCW = 0X7600
604 06:53:31.509003 ===================================
605 06:53:31.512425 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 06:53:31.515894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 06:53:31.522703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 06:53:31.525599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 06:53:31.529499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 06:53:31.532815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 06:53:31.535759 [ANA_INIT] flow start
612 06:53:31.539542 [ANA_INIT] PLL >>>>>>>>
613 06:53:31.539960 [ANA_INIT] PLL <<<<<<<<
614 06:53:31.542939 [ANA_INIT] MIDPI >>>>>>>>
615 06:53:31.546492 [ANA_INIT] MIDPI <<<<<<<<
616 06:53:31.549246 [ANA_INIT] DLL >>>>>>>>
617 06:53:31.549663 [ANA_INIT] flow end
618 06:53:31.552648 ============ LP4 DIFF to SE enter ============
619 06:53:31.559523 ============ LP4 DIFF to SE exit ============
620 06:53:31.560027 [ANA_INIT] <<<<<<<<<<<<<
621 06:53:31.563003 [Flow] Enable top DCM control >>>>>
622 06:53:31.566036 [Flow] Enable top DCM control <<<<<
623 06:53:31.569378 Enable DLL master slave shuffle
624 06:53:31.576091 ==============================================================
625 06:53:31.576623 Gating Mode config
626 06:53:31.582652 ==============================================================
627 06:53:31.586045 Config description:
628 06:53:31.593035 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 06:53:31.599851 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 06:53:31.606042 SELPH_MODE 0: By rank 1: By Phase
631 06:53:31.613059 ==============================================================
632 06:53:31.613482 GAT_TRACK_EN = 1
633 06:53:31.616077 RX_GATING_MODE = 2
634 06:53:31.619355 RX_GATING_TRACK_MODE = 2
635 06:53:31.622789 SELPH_MODE = 1
636 06:53:31.626305 PICG_EARLY_EN = 1
637 06:53:31.629810 VALID_LAT_VALUE = 1
638 06:53:31.636073 ==============================================================
639 06:53:31.639424 Enter into Gating configuration >>>>
640 06:53:31.643247 Exit from Gating configuration <<<<
641 06:53:31.643688 Enter into DVFS_PRE_config >>>>>
642 06:53:31.656558 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 06:53:31.659299 Exit from DVFS_PRE_config <<<<<
644 06:53:31.663080 Enter into PICG configuration >>>>
645 06:53:31.666545 Exit from PICG configuration <<<<
646 06:53:31.667007 [RX_INPUT] configuration >>>>>
647 06:53:31.669882 [RX_INPUT] configuration <<<<<
648 06:53:31.676889 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 06:53:31.679639 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 06:53:31.686505 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 06:53:31.693217 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 06:53:31.699596 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 06:53:31.706547 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 06:53:31.710203 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 06:53:31.713203 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 06:53:31.716654 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 06:53:31.723396 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 06:53:31.726850 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 06:53:31.729892 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 06:53:31.733739 ===================================
661 06:53:31.736681 LPDDR4 DRAM CONFIGURATION
662 06:53:31.740068 ===================================
663 06:53:31.743527 EX_ROW_EN[0] = 0x0
664 06:53:31.743987 EX_ROW_EN[1] = 0x0
665 06:53:31.746952 LP4Y_EN = 0x0
666 06:53:31.747625 WORK_FSP = 0x0
667 06:53:31.749756 WL = 0x2
668 06:53:31.750405 RL = 0x2
669 06:53:31.753795 BL = 0x2
670 06:53:31.754455 RPST = 0x0
671 06:53:31.757001 RD_PRE = 0x0
672 06:53:31.757628 WR_PRE = 0x1
673 06:53:31.760206 WR_PST = 0x0
674 06:53:31.760904 DBI_WR = 0x0
675 06:53:31.763532 DBI_RD = 0x0
676 06:53:31.764211 OTF = 0x1
677 06:53:31.766590 ===================================
678 06:53:31.769845 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 06:53:31.776910 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 06:53:31.780274 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 06:53:31.783115 ===================================
682 06:53:31.786627 LPDDR4 DRAM CONFIGURATION
683 06:53:31.790040 ===================================
684 06:53:31.790453 EX_ROW_EN[0] = 0x10
685 06:53:31.793387 EX_ROW_EN[1] = 0x0
686 06:53:31.793793 LP4Y_EN = 0x0
687 06:53:31.796918 WORK_FSP = 0x0
688 06:53:31.800336 WL = 0x2
689 06:53:31.800800 RL = 0x2
690 06:53:31.803884 BL = 0x2
691 06:53:31.804376 RPST = 0x0
692 06:53:31.806631 RD_PRE = 0x0
693 06:53:31.807113 WR_PRE = 0x1
694 06:53:31.810014 WR_PST = 0x0
695 06:53:31.810485 DBI_WR = 0x0
696 06:53:31.813640 DBI_RD = 0x0
697 06:53:31.814188 OTF = 0x1
698 06:53:31.817030 ===================================
699 06:53:31.823183 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 06:53:31.827119 nWR fixed to 40
701 06:53:31.830409 [ModeRegInit_LP4] CH0 RK0
702 06:53:31.830900 [ModeRegInit_LP4] CH0 RK1
703 06:53:31.834119 [ModeRegInit_LP4] CH1 RK0
704 06:53:31.837142 [ModeRegInit_LP4] CH1 RK1
705 06:53:31.837563 match AC timing 13
706 06:53:31.843913 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 06:53:31.847524 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 06:53:31.850465 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 06:53:31.857719 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 06:53:31.860533 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 06:53:31.861013 [EMI DOE] emi_dcm 0
712 06:53:31.867437 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 06:53:31.867747 ==
714 06:53:31.870991 Dram Type= 6, Freq= 0, CH_0, rank 0
715 06:53:31.874516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 06:53:31.874955 ==
717 06:53:31.880702 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 06:53:31.884364 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 06:53:31.894663 [CA 0] Center 36 (6~67) winsize 62
720 06:53:31.897930 [CA 1] Center 36 (6~67) winsize 62
721 06:53:31.901449 [CA 2] Center 34 (4~65) winsize 62
722 06:53:31.904949 [CA 3] Center 34 (4~64) winsize 61
723 06:53:31.908376 [CA 4] Center 33 (3~64) winsize 62
724 06:53:31.911166 [CA 5] Center 32 (3~62) winsize 60
725 06:53:31.911462
726 06:53:31.914712 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 06:53:31.915011
728 06:53:31.918013 [CATrainingPosCal] consider 1 rank data
729 06:53:31.921360 u2DelayCellTimex100 = 270/100 ps
730 06:53:31.924807 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 06:53:31.927632 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 06:53:31.934377 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 06:53:31.937909 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 06:53:31.941437 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 06:53:31.944867 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 06:53:31.945167
737 06:53:31.948162 CA PerBit enable=1, Macro0, CA PI delay=32
738 06:53:31.948494
739 06:53:31.951534 [CBTSetCACLKResult] CA Dly = 32
740 06:53:31.951975 CS Dly: 4 (0~35)
741 06:53:31.952369 ==
742 06:53:31.954852 Dram Type= 6, Freq= 0, CH_0, rank 1
743 06:53:31.961880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 06:53:31.962313 ==
745 06:53:31.964601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 06:53:31.971665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 06:53:31.980518 [CA 0] Center 36 (6~67) winsize 62
748 06:53:31.984283 [CA 1] Center 36 (6~67) winsize 62
749 06:53:31.987406 [CA 2] Center 34 (3~65) winsize 63
750 06:53:31.991154 [CA 3] Center 33 (3~64) winsize 62
751 06:53:31.994151 [CA 4] Center 33 (3~63) winsize 61
752 06:53:31.997777 [CA 5] Center 32 (2~63) winsize 62
753 06:53:31.998237
754 06:53:32.000894 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 06:53:32.001318
756 06:53:32.004382 [CATrainingPosCal] consider 2 rank data
757 06:53:32.007467 u2DelayCellTimex100 = 270/100 ps
758 06:53:32.010868 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 06:53:32.014330 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 06:53:32.021251 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 06:53:32.024687 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 06:53:32.028224 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 06:53:32.030875 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 06:53:32.031169
765 06:53:32.034254 CA PerBit enable=1, Macro0, CA PI delay=32
766 06:53:32.034553
767 06:53:32.037516 [CBTSetCACLKResult] CA Dly = 32
768 06:53:32.037825 CS Dly: 5 (0~37)
769 06:53:32.038063
770 06:53:32.041025 ----->DramcWriteLeveling(PI) begin...
771 06:53:32.044364 ==
772 06:53:32.044668 Dram Type= 6, Freq= 0, CH_0, rank 0
773 06:53:32.052014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 06:53:32.052432 ==
775 06:53:32.052688 Write leveling (Byte 0): 35 => 35
776 06:53:32.055215 Write leveling (Byte 1): 31 => 31
777 06:53:32.059466 DramcWriteLeveling(PI) end<-----
778 06:53:32.059880
779 06:53:32.060264 ==
780 06:53:32.063666 Dram Type= 6, Freq= 0, CH_0, rank 0
781 06:53:32.067291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 06:53:32.067595 ==
783 06:53:32.070058 [Gating] SW mode calibration
784 06:53:32.077717 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 06:53:32.080889 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 06:53:32.087764 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 06:53:32.091098 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 06:53:32.094475 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 06:53:32.101035 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 06:53:32.104112 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 06:53:32.107658 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 06:53:32.114375 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 06:53:32.117783 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 06:53:32.121057 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 06:53:32.127570 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 06:53:32.131139 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 06:53:32.134185 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 06:53:32.137840 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 06:53:32.144516 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 06:53:32.147840 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 06:53:32.151384 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 06:53:32.157525 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 06:53:32.160870 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
804 06:53:32.164753 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 06:53:32.171398 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 06:53:32.174272 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 06:53:32.177738 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 06:53:32.184591 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 06:53:32.188188 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 06:53:32.191129 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 06:53:32.198248 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 06:53:32.201109 0 9 8 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
813 06:53:32.204513 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 06:53:32.211471 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 06:53:32.214689 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 06:53:32.218122 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 06:53:32.221460 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 06:53:32.227794 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 06:53:32.231280 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
820 06:53:32.234704 0 10 8 | B1->B0 | 3333 2323 | 0 1 | (0 0) (1 0)
821 06:53:32.241054 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
822 06:53:32.244556 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 06:53:32.247777 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 06:53:32.254654 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 06:53:32.257472 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 06:53:32.261256 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 06:53:32.268234 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 06:53:32.271544 0 11 8 | B1->B0 | 2c2c 4040 | 1 0 | (0 0) (0 0)
829 06:53:32.274830 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 06:53:32.281600 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 06:53:32.284389 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 06:53:32.287952 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 06:53:32.294758 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 06:53:32.297683 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 06:53:32.300983 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 06:53:32.308185 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 06:53:32.311007 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 06:53:32.314389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 06:53:32.317731 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 06:53:32.324574 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 06:53:32.328061 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 06:53:32.331334 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 06:53:32.338066 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 06:53:32.341587 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 06:53:32.344989 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 06:53:32.351707 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 06:53:32.354885 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 06:53:32.357719 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 06:53:32.364486 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 06:53:32.368244 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 06:53:32.371519 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 06:53:32.378256 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 06:53:32.381943 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 06:53:32.385055 Total UI for P1: 0, mck2ui 16
855 06:53:32.388067 best dqsien dly found for B0: ( 0, 14, 6)
856 06:53:32.391219 Total UI for P1: 0, mck2ui 16
857 06:53:32.394531 best dqsien dly found for B1: ( 0, 14, 10)
858 06:53:32.398665 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 06:53:32.401932 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 06:53:32.402014
861 06:53:32.405501 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 06:53:32.408711 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 06:53:32.412106 [Gating] SW calibration Done
864 06:53:32.412189 ==
865 06:53:32.415675 Dram Type= 6, Freq= 0, CH_0, rank 0
866 06:53:32.419072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 06:53:32.419155 ==
868 06:53:32.421965 RX Vref Scan: 0
869 06:53:32.422050
870 06:53:32.422136 RX Vref 0 -> 0, step: 1
871 06:53:32.422217
872 06:53:32.425271 RX Delay -130 -> 252, step: 16
873 06:53:32.428573 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 06:53:32.435377 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 06:53:32.438867 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 06:53:32.442112 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 06:53:32.445499 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 06:53:32.449020 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 06:53:32.455261 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 06:53:32.458580 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 06:53:32.461972 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 06:53:32.465514 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 06:53:32.468940 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 06:53:32.475178 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 06:53:32.478694 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 06:53:32.481994 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 06:53:32.485217 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 06:53:32.488582 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 06:53:32.491860 ==
890 06:53:32.491943 Dram Type= 6, Freq= 0, CH_0, rank 0
891 06:53:32.498871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 06:53:32.498954 ==
893 06:53:32.499020 DQS Delay:
894 06:53:32.501922 DQS0 = 0, DQS1 = 0
895 06:53:32.502004 DQM Delay:
896 06:53:32.505787 DQM0 = 90, DQM1 = 81
897 06:53:32.505869 DQ Delay:
898 06:53:32.509098 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 06:53:32.512552 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
900 06:53:32.515770 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
901 06:53:32.519002 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
902 06:53:32.519085
903 06:53:32.519150
904 06:53:32.519211 ==
905 06:53:32.522334 Dram Type= 6, Freq= 0, CH_0, rank 0
906 06:53:32.525740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 06:53:32.525828 ==
908 06:53:32.525937
909 06:53:32.526004
910 06:53:32.529142 TX Vref Scan disable
911 06:53:32.529224 == TX Byte 0 ==
912 06:53:32.535917 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
913 06:53:32.539423 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
914 06:53:32.539506 == TX Byte 1 ==
915 06:53:32.545650 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 06:53:32.548877 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 06:53:32.548960 ==
918 06:53:32.552429 Dram Type= 6, Freq= 0, CH_0, rank 0
919 06:53:32.555927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 06:53:32.556010 ==
921 06:53:32.570107 TX Vref=22, minBit 10, minWin=27, winSum=448
922 06:53:32.573358 TX Vref=24, minBit 8, minWin=27, winSum=451
923 06:53:32.576890 TX Vref=26, minBit 5, minWin=28, winSum=456
924 06:53:32.580251 TX Vref=28, minBit 8, minWin=28, winSum=457
925 06:53:32.583631 TX Vref=30, minBit 8, minWin=28, winSum=456
926 06:53:32.590266 TX Vref=32, minBit 10, minWin=27, winSum=456
927 06:53:32.593679 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 28
928 06:53:32.593761
929 06:53:32.596972 Final TX Range 1 Vref 28
930 06:53:32.597069
931 06:53:32.597140 ==
932 06:53:32.600485 Dram Type= 6, Freq= 0, CH_0, rank 0
933 06:53:32.603985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 06:53:32.606631 ==
935 06:53:32.606738
936 06:53:32.606834
937 06:53:32.606971 TX Vref Scan disable
938 06:53:32.610383 == TX Byte 0 ==
939 06:53:32.613619 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
940 06:53:32.620551 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
941 06:53:32.620658 == TX Byte 1 ==
942 06:53:32.623960 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 06:53:32.627331 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 06:53:32.630523
945 06:53:32.630604 [DATLAT]
946 06:53:32.630669 Freq=800, CH0 RK0
947 06:53:32.630730
948 06:53:32.633998 DATLAT Default: 0xa
949 06:53:32.634108 0, 0xFFFF, sum = 0
950 06:53:32.637273 1, 0xFFFF, sum = 0
951 06:53:32.637359 2, 0xFFFF, sum = 0
952 06:53:32.640423 3, 0xFFFF, sum = 0
953 06:53:32.640506 4, 0xFFFF, sum = 0
954 06:53:32.643576 5, 0xFFFF, sum = 0
955 06:53:32.647003 6, 0xFFFF, sum = 0
956 06:53:32.647086 7, 0xFFFF, sum = 0
957 06:53:32.650540 8, 0xFFFF, sum = 0
958 06:53:32.650624 9, 0x0, sum = 1
959 06:53:32.650691 10, 0x0, sum = 2
960 06:53:32.654005 11, 0x0, sum = 3
961 06:53:32.654089 12, 0x0, sum = 4
962 06:53:32.657297 best_step = 10
963 06:53:32.657381
964 06:53:32.657466 ==
965 06:53:32.660554 Dram Type= 6, Freq= 0, CH_0, rank 0
966 06:53:32.664208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 06:53:32.664332 ==
968 06:53:32.666957 RX Vref Scan: 1
969 06:53:32.667041
970 06:53:32.667128 Set Vref Range= 32 -> 127
971 06:53:32.667210
972 06:53:32.670385 RX Vref 32 -> 127, step: 1
973 06:53:32.670469
974 06:53:32.673690 RX Delay -95 -> 252, step: 8
975 06:53:32.673774
976 06:53:32.677058 Set Vref, RX VrefLevel [Byte0]: 32
977 06:53:32.680425 [Byte1]: 32
978 06:53:32.680509
979 06:53:32.683768 Set Vref, RX VrefLevel [Byte0]: 33
980 06:53:32.687121 [Byte1]: 33
981 06:53:32.690621
982 06:53:32.690701 Set Vref, RX VrefLevel [Byte0]: 34
983 06:53:32.694410 [Byte1]: 34
984 06:53:32.698468
985 06:53:32.698549 Set Vref, RX VrefLevel [Byte0]: 35
986 06:53:32.701806 [Byte1]: 35
987 06:53:32.705885
988 06:53:32.705987 Set Vref, RX VrefLevel [Byte0]: 36
989 06:53:32.709449 [Byte1]: 36
990 06:53:32.714095
991 06:53:32.714176 Set Vref, RX VrefLevel [Byte0]: 37
992 06:53:32.717544 [Byte1]: 37
993 06:53:32.721715
994 06:53:32.721796 Set Vref, RX VrefLevel [Byte0]: 38
995 06:53:32.725045 [Byte1]: 38
996 06:53:32.728987
997 06:53:32.729096 Set Vref, RX VrefLevel [Byte0]: 39
998 06:53:32.732772 [Byte1]: 39
999 06:53:32.736803
1000 06:53:32.736884 Set Vref, RX VrefLevel [Byte0]: 40
1001 06:53:32.740002 [Byte1]: 40
1002 06:53:32.744066
1003 06:53:32.744147 Set Vref, RX VrefLevel [Byte0]: 41
1004 06:53:32.747496 [Byte1]: 41
1005 06:53:32.752084
1006 06:53:32.752176 Set Vref, RX VrefLevel [Byte0]: 42
1007 06:53:32.754748 [Byte1]: 42
1008 06:53:32.759345
1009 06:53:32.759429 Set Vref, RX VrefLevel [Byte0]: 43
1010 06:53:32.762679 [Byte1]: 43
1011 06:53:32.766636
1012 06:53:32.766717 Set Vref, RX VrefLevel [Byte0]: 44
1013 06:53:32.770112 [Byte1]: 44
1014 06:53:32.774436
1015 06:53:32.774516 Set Vref, RX VrefLevel [Byte0]: 45
1016 06:53:32.777933 [Byte1]: 45
1017 06:53:32.781781
1018 06:53:32.781861 Set Vref, RX VrefLevel [Byte0]: 46
1019 06:53:32.785068 [Byte1]: 46
1020 06:53:32.789826
1021 06:53:32.789907 Set Vref, RX VrefLevel [Byte0]: 47
1022 06:53:32.792686 [Byte1]: 47
1023 06:53:32.797321
1024 06:53:32.797404 Set Vref, RX VrefLevel [Byte0]: 48
1025 06:53:32.800474 [Byte1]: 48
1026 06:53:32.804630
1027 06:53:32.804711 Set Vref, RX VrefLevel [Byte0]: 49
1028 06:53:32.807999 [Byte1]: 49
1029 06:53:32.812754
1030 06:53:32.812834 Set Vref, RX VrefLevel [Byte0]: 50
1031 06:53:32.816004 [Byte1]: 50
1032 06:53:32.820178
1033 06:53:32.820283 Set Vref, RX VrefLevel [Byte0]: 51
1034 06:53:32.823011 [Byte1]: 51
1035 06:53:32.827997
1036 06:53:32.828077 Set Vref, RX VrefLevel [Byte0]: 52
1037 06:53:32.830746 [Byte1]: 52
1038 06:53:32.835481
1039 06:53:32.835561 Set Vref, RX VrefLevel [Byte0]: 53
1040 06:53:32.838137 [Byte1]: 53
1041 06:53:32.843067
1042 06:53:32.843146 Set Vref, RX VrefLevel [Byte0]: 54
1043 06:53:32.846073 [Byte1]: 54
1044 06:53:32.850386
1045 06:53:32.850466 Set Vref, RX VrefLevel [Byte0]: 55
1046 06:53:32.853991 [Byte1]: 55
1047 06:53:32.857872
1048 06:53:32.857952 Set Vref, RX VrefLevel [Byte0]: 56
1049 06:53:32.861207 [Byte1]: 56
1050 06:53:32.865576
1051 06:53:32.865655 Set Vref, RX VrefLevel [Byte0]: 57
1052 06:53:32.869057 [Byte1]: 57
1053 06:53:32.873616
1054 06:53:32.873695 Set Vref, RX VrefLevel [Byte0]: 58
1055 06:53:32.876250 [Byte1]: 58
1056 06:53:32.881119
1057 06:53:32.881199 Set Vref, RX VrefLevel [Byte0]: 59
1058 06:53:32.883898 [Byte1]: 59
1059 06:53:32.888549
1060 06:53:32.888628 Set Vref, RX VrefLevel [Byte0]: 60
1061 06:53:32.892014 [Byte1]: 60
1062 06:53:32.895980
1063 06:53:32.896060 Set Vref, RX VrefLevel [Byte0]: 61
1064 06:53:32.899298 [Byte1]: 61
1065 06:53:32.903305
1066 06:53:32.903384 Set Vref, RX VrefLevel [Byte0]: 62
1067 06:53:32.906590 [Byte1]: 62
1068 06:53:32.911277
1069 06:53:32.911363 Set Vref, RX VrefLevel [Byte0]: 63
1070 06:53:32.914503 [Byte1]: 63
1071 06:53:32.919084
1072 06:53:32.919163 Set Vref, RX VrefLevel [Byte0]: 64
1073 06:53:32.921946 [Byte1]: 64
1074 06:53:32.926618
1075 06:53:32.926699 Set Vref, RX VrefLevel [Byte0]: 65
1076 06:53:32.929500 [Byte1]: 65
1077 06:53:32.933739
1078 06:53:32.933817 Set Vref, RX VrefLevel [Byte0]: 66
1079 06:53:32.937217 [Byte1]: 66
1080 06:53:32.941449
1081 06:53:32.941529 Set Vref, RX VrefLevel [Byte0]: 67
1082 06:53:32.945036 [Byte1]: 67
1083 06:53:32.949078
1084 06:53:32.949158 Set Vref, RX VrefLevel [Byte0]: 68
1085 06:53:32.952445 [Byte1]: 68
1086 06:53:32.957072
1087 06:53:32.957152 Set Vref, RX VrefLevel [Byte0]: 69
1088 06:53:32.960256 [Byte1]: 69
1089 06:53:32.964623
1090 06:53:32.964699 Set Vref, RX VrefLevel [Byte0]: 70
1091 06:53:32.967926 [Byte1]: 70
1092 06:53:32.972046
1093 06:53:32.972151 Set Vref, RX VrefLevel [Byte0]: 71
1094 06:53:32.974961 [Byte1]: 71
1095 06:53:32.979535
1096 06:53:32.979618 Set Vref, RX VrefLevel [Byte0]: 72
1097 06:53:32.982821 [Byte1]: 72
1098 06:53:32.986948
1099 06:53:32.987026 Set Vref, RX VrefLevel [Byte0]: 73
1100 06:53:32.990695 [Byte1]: 73
1101 06:53:32.994829
1102 06:53:32.994907 Set Vref, RX VrefLevel [Byte0]: 74
1103 06:53:32.998180 [Byte1]: 74
1104 06:53:33.002352
1105 06:53:33.002434 Set Vref, RX VrefLevel [Byte0]: 75
1106 06:53:33.005802 [Byte1]: 75
1107 06:53:33.009710
1108 06:53:33.009789 Set Vref, RX VrefLevel [Byte0]: 76
1109 06:53:33.013005 [Byte1]: 76
1110 06:53:33.017687
1111 06:53:33.017766 Final RX Vref Byte 0 = 59 to rank0
1112 06:53:33.021070 Final RX Vref Byte 1 = 61 to rank0
1113 06:53:33.024260 Final RX Vref Byte 0 = 59 to rank1
1114 06:53:33.027432 Final RX Vref Byte 1 = 61 to rank1==
1115 06:53:33.030797 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 06:53:33.037681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 06:53:33.037761 ==
1118 06:53:33.037824 DQS Delay:
1119 06:53:33.037882 DQS0 = 0, DQS1 = 0
1120 06:53:33.041295 DQM Delay:
1121 06:53:33.041374 DQM0 = 92, DQM1 = 86
1122 06:53:33.044130 DQ Delay:
1123 06:53:33.047525 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1124 06:53:33.051017 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1125 06:53:33.051123 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1126 06:53:33.054496 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1127 06:53:33.057634
1128 06:53:33.057725
1129 06:53:33.064444 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1130 06:53:33.067779 CH0 RK0: MR19=606, MR18=4D43
1131 06:53:33.073903 CH0_RK0: MR19=0x606, MR18=0x4D43, DQSOSC=390, MR23=63, INC=97, DEC=64
1132 06:53:33.073984
1133 06:53:33.077934 ----->DramcWriteLeveling(PI) begin...
1134 06:53:33.078015 ==
1135 06:53:33.080470 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 06:53:33.084001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 06:53:33.084082 ==
1138 06:53:33.087464 Write leveling (Byte 0): 33 => 33
1139 06:53:33.090828 Write leveling (Byte 1): 28 => 28
1140 06:53:33.094320 DramcWriteLeveling(PI) end<-----
1141 06:53:33.094400
1142 06:53:33.094462 ==
1143 06:53:33.097932 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 06:53:33.100994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 06:53:33.101074 ==
1146 06:53:33.104175 [Gating] SW mode calibration
1147 06:53:33.111095 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 06:53:33.117901 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 06:53:33.161740 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 06:53:33.162322 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 06:53:33.162406 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1152 06:53:33.163019 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 06:53:33.163283 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 06:53:33.163361 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 06:53:33.163433 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 06:53:33.163493 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 06:53:33.163558 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 06:53:33.163625 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 06:53:33.205677 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 06:53:33.206499 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 06:53:33.206582 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 06:53:33.206830 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 06:53:33.206895 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 06:53:33.206964 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 06:53:33.207210 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 06:53:33.207272 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 06:53:33.207362 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1168 06:53:33.207466 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 06:53:33.233256 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 06:53:33.233857 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 06:53:33.233946 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 06:53:33.234221 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 06:53:33.234286 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 06:53:33.234345 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 06:53:33.237902 0 9 8 | B1->B0 | 2e2e 2929 | 0 1 | (0 0) (1 1)
1176 06:53:33.241134 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 06:53:33.244153 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 06:53:33.248034 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 06:53:33.254665 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 06:53:33.258182 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 06:53:33.260909 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 06:53:33.264275 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (0 0) (1 0)
1183 06:53:33.271042 0 10 8 | B1->B0 | 2929 2626 | 0 1 | (0 0) (1 1)
1184 06:53:33.274210 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1185 06:53:33.277777 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 06:53:33.284456 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 06:53:33.287890 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 06:53:33.291230 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 06:53:33.296119 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 06:53:33.299580 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 06:53:33.307143 0 11 8 | B1->B0 | 3b3b 3a3a | 0 0 | (1 1) (0 0)
1192 06:53:33.309982 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 06:53:33.313541 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 06:53:33.318006 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 06:53:33.324427 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 06:53:33.327669 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 06:53:33.330513 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 06:53:33.337441 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 06:53:33.341001 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1200 06:53:33.344456 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 06:53:33.351128 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 06:53:33.354260 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 06:53:33.357852 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 06:53:33.364418 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 06:53:33.367504 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 06:53:33.371014 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 06:53:33.377915 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 06:53:33.381290 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 06:53:33.384514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 06:53:33.387539 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 06:53:33.394559 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 06:53:33.398031 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 06:53:33.401344 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 06:53:33.407588 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 06:53:33.411075 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1216 06:53:33.414560 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 06:53:33.417493 Total UI for P1: 0, mck2ui 16
1218 06:53:33.420867 best dqsien dly found for B0: ( 0, 14, 8)
1219 06:53:33.424268 Total UI for P1: 0, mck2ui 16
1220 06:53:33.427580 best dqsien dly found for B1: ( 0, 14, 8)
1221 06:53:33.431028 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1222 06:53:33.434039 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 06:53:33.434143
1224 06:53:33.437543 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 06:53:33.444259 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 06:53:33.444409 [Gating] SW calibration Done
1227 06:53:33.444500 ==
1228 06:53:33.447775 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 06:53:33.454253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 06:53:33.454332 ==
1231 06:53:33.454394 RX Vref Scan: 0
1232 06:53:33.454452
1233 06:53:33.457854 RX Vref 0 -> 0, step: 1
1234 06:53:33.457933
1235 06:53:33.461263 RX Delay -130 -> 252, step: 16
1236 06:53:33.464114 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1237 06:53:33.467648 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1238 06:53:33.471014 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1239 06:53:33.477566 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1240 06:53:33.481041 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1241 06:53:33.484088 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1242 06:53:33.487730 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1243 06:53:33.491370 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1244 06:53:33.497679 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 06:53:33.500995 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1246 06:53:33.504446 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1247 06:53:33.507884 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1248 06:53:33.511179 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1249 06:53:33.517913 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1250 06:53:33.521386 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1251 06:53:33.524168 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1252 06:53:33.524248 ==
1253 06:53:33.527628 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 06:53:33.531091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 06:53:33.531173 ==
1256 06:53:33.534504 DQS Delay:
1257 06:53:33.534611 DQS0 = 0, DQS1 = 0
1258 06:53:33.537983 DQM Delay:
1259 06:53:33.538089 DQM0 = 93, DQM1 = 84
1260 06:53:33.538179 DQ Delay:
1261 06:53:33.541113 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1262 06:53:33.544275 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =109
1263 06:53:33.547568 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
1264 06:53:33.551048 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1265 06:53:33.551128
1266 06:53:33.551191
1267 06:53:33.554579 ==
1268 06:53:33.554657 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 06:53:33.560919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 06:53:33.560995 ==
1271 06:53:33.561055
1272 06:53:33.561111
1273 06:53:33.564551 TX Vref Scan disable
1274 06:53:33.564622 == TX Byte 0 ==
1275 06:53:33.568069 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1276 06:53:33.574531 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1277 06:53:33.574605 == TX Byte 1 ==
1278 06:53:33.577447 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1279 06:53:33.584255 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1280 06:53:33.584376 ==
1281 06:53:33.587750 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 06:53:33.591158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 06:53:33.591256 ==
1284 06:53:33.604975 TX Vref=22, minBit 1, minWin=28, winSum=451
1285 06:53:33.608309 TX Vref=24, minBit 1, minWin=28, winSum=452
1286 06:53:33.611726 TX Vref=26, minBit 1, minWin=28, winSum=457
1287 06:53:33.615163 TX Vref=28, minBit 4, minWin=28, winSum=458
1288 06:53:33.617943 TX Vref=30, minBit 7, minWin=28, winSum=459
1289 06:53:33.621139 TX Vref=32, minBit 6, minWin=28, winSum=454
1290 06:53:33.628072 [TxChooseVref] Worse bit 7, Min win 28, Win sum 459, Final Vref 30
1291 06:53:33.628176
1292 06:53:33.631381 Final TX Range 1 Vref 30
1293 06:53:33.631495
1294 06:53:33.631586 ==
1295 06:53:33.634491 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 06:53:33.638250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 06:53:33.638331 ==
1298 06:53:33.638393
1299 06:53:33.638450
1300 06:53:33.641508 TX Vref Scan disable
1301 06:53:33.645149 == TX Byte 0 ==
1302 06:53:33.647877 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1303 06:53:33.651572 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1304 06:53:33.654583 == TX Byte 1 ==
1305 06:53:33.658067 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1306 06:53:33.661424 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1307 06:53:33.665018
1308 06:53:33.665098 [DATLAT]
1309 06:53:33.665160 Freq=800, CH0 RK1
1310 06:53:33.665218
1311 06:53:33.668389 DATLAT Default: 0xa
1312 06:53:33.668468 0, 0xFFFF, sum = 0
1313 06:53:33.671166 1, 0xFFFF, sum = 0
1314 06:53:33.671246 2, 0xFFFF, sum = 0
1315 06:53:33.674779 3, 0xFFFF, sum = 0
1316 06:53:33.674859 4, 0xFFFF, sum = 0
1317 06:53:33.678300 5, 0xFFFF, sum = 0
1318 06:53:33.681087 6, 0xFFFF, sum = 0
1319 06:53:33.681167 7, 0xFFFF, sum = 0
1320 06:53:33.684755 8, 0xFFFF, sum = 0
1321 06:53:33.684835 9, 0x0, sum = 1
1322 06:53:33.684899 10, 0x0, sum = 2
1323 06:53:33.688037 11, 0x0, sum = 3
1324 06:53:33.688145 12, 0x0, sum = 4
1325 06:53:33.691482 best_step = 10
1326 06:53:33.691587
1327 06:53:33.691676 ==
1328 06:53:33.694706 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 06:53:33.697449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 06:53:33.697523 ==
1331 06:53:33.700983 RX Vref Scan: 0
1332 06:53:33.701076
1333 06:53:33.701137 RX Vref 0 -> 0, step: 1
1334 06:53:33.701195
1335 06:53:33.704400 RX Delay -95 -> 252, step: 8
1336 06:53:33.711219 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1337 06:53:33.714733 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1338 06:53:33.717989 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1339 06:53:33.721424 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1340 06:53:33.724305 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1341 06:53:33.731501 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1342 06:53:33.734875 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1343 06:53:33.738333 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1344 06:53:33.741184 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1345 06:53:33.744704 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1346 06:53:33.751557 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1347 06:53:33.754823 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1348 06:53:33.757965 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1349 06:53:33.761708 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1350 06:53:33.764832 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1351 06:53:33.771232 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1352 06:53:33.771312 ==
1353 06:53:33.774956 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 06:53:33.778041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 06:53:33.778149 ==
1356 06:53:33.778244 DQS Delay:
1357 06:53:33.781238 DQS0 = 0, DQS1 = 0
1358 06:53:33.781342 DQM Delay:
1359 06:53:33.784981 DQM0 = 93, DQM1 = 83
1360 06:53:33.785082 DQ Delay:
1361 06:53:33.787997 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1362 06:53:33.791432 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1363 06:53:33.794552 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1364 06:53:33.797848 DQ12 =92, DQ13 =84, DQ14 =92, DQ15 =92
1365 06:53:33.797939
1366 06:53:33.798018
1367 06:53:33.804976 [DQSOSCAuto] RK1, (LSB)MR18= 0x4717, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1368 06:53:33.808524 CH0 RK1: MR19=606, MR18=4717
1369 06:53:33.815275 CH0_RK1: MR19=0x606, MR18=0x4717, DQSOSC=392, MR23=63, INC=96, DEC=64
1370 06:53:33.818194 [RxdqsGatingPostProcess] freq 800
1371 06:53:33.824960 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 06:53:33.825038 Pre-setting of DQS Precalculation
1373 06:53:33.831274 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 06:53:33.831353 ==
1375 06:53:33.834890 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 06:53:33.838317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 06:53:33.838390 ==
1378 06:53:33.845277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 06:53:33.851576 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 06:53:33.859292 [CA 0] Center 36 (6~67) winsize 62
1381 06:53:33.862643 [CA 1] Center 36 (6~67) winsize 62
1382 06:53:33.865969 [CA 2] Center 35 (5~65) winsize 61
1383 06:53:33.869443 [CA 3] Center 34 (4~65) winsize 62
1384 06:53:33.872967 [CA 4] Center 34 (4~65) winsize 62
1385 06:53:33.876461 [CA 5] Center 34 (4~64) winsize 61
1386 06:53:33.876559
1387 06:53:33.879765 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1388 06:53:33.879862
1389 06:53:33.883165 [CATrainingPosCal] consider 1 rank data
1390 06:53:33.886261 u2DelayCellTimex100 = 270/100 ps
1391 06:53:33.889414 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1392 06:53:33.892619 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 06:53:33.899661 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1394 06:53:33.902862 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1395 06:53:33.905931 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 06:53:33.909436 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 06:53:33.909513
1398 06:53:33.913060 CA PerBit enable=1, Macro0, CA PI delay=34
1399 06:53:33.913139
1400 06:53:33.915896 [CBTSetCACLKResult] CA Dly = 34
1401 06:53:33.915997 CS Dly: 5 (0~36)
1402 06:53:33.919364 ==
1403 06:53:33.919466 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 06:53:33.926075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 06:53:33.926193 ==
1406 06:53:33.929505 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 06:53:33.936534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 06:53:33.945526 [CA 0] Center 36 (6~67) winsize 62
1409 06:53:33.948973 [CA 1] Center 36 (6~67) winsize 62
1410 06:53:33.952523 [CA 2] Center 35 (5~66) winsize 62
1411 06:53:33.955993 [CA 3] Center 35 (5~65) winsize 61
1412 06:53:33.959474 [CA 4] Center 34 (4~65) winsize 62
1413 06:53:33.962936 [CA 5] Center 34 (4~65) winsize 62
1414 06:53:33.963007
1415 06:53:33.966403 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 06:53:33.966473
1417 06:53:33.970681 [CATrainingPosCal] consider 2 rank data
1418 06:53:33.974094 u2DelayCellTimex100 = 270/100 ps
1419 06:53:33.977652 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 06:53:33.981921 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 06:53:33.985441 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1422 06:53:33.989600 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1423 06:53:33.993060 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 06:53:33.996576 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 06:53:33.996656
1426 06:53:33.999335 CA PerBit enable=1, Macro0, CA PI delay=34
1427 06:53:33.999414
1428 06:53:34.002825 [CBTSetCACLKResult] CA Dly = 34
1429 06:53:34.002934 CS Dly: 6 (0~38)
1430 06:53:34.003029
1431 06:53:34.006397 ----->DramcWriteLeveling(PI) begin...
1432 06:53:34.006502 ==
1433 06:53:34.009800 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 06:53:34.016592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 06:53:34.016671 ==
1436 06:53:34.019663 Write leveling (Byte 0): 25 => 25
1437 06:53:34.019743 Write leveling (Byte 1): 29 => 29
1438 06:53:34.023162 DramcWriteLeveling(PI) end<-----
1439 06:53:34.023241
1440 06:53:34.026663 ==
1441 06:53:34.026745 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 06:53:34.033171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 06:53:34.033250 ==
1444 06:53:34.036613 [Gating] SW mode calibration
1445 06:53:34.043089 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 06:53:34.046290 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 06:53:34.053191 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 06:53:34.056753 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1449 06:53:34.060268 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 06:53:34.063002 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 06:53:34.070057 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 06:53:34.073506 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 06:53:34.076583 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 06:53:34.083275 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 06:53:34.086658 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 06:53:34.089499 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 06:53:34.096323 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 06:53:34.099727 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 06:53:34.103136 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 06:53:34.110068 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 06:53:34.112867 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 06:53:34.116322 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 06:53:34.123317 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1464 06:53:34.126715 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1465 06:53:34.129970 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 06:53:34.133406 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 06:53:34.140742 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 06:53:34.143750 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 06:53:34.146789 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 06:53:34.153506 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 06:53:34.156614 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 06:53:34.160101 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1473 06:53:34.167224 0 9 8 | B1->B0 | 3131 3333 | 0 1 | (0 0) (0 0)
1474 06:53:34.170451 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 06:53:34.173689 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 06:53:34.180070 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 06:53:34.183788 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 06:53:34.187292 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 06:53:34.193955 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1480 06:53:34.196960 0 10 4 | B1->B0 | 3131 2c2c | 1 1 | (1 0) (1 1)
1481 06:53:34.200222 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
1482 06:53:34.206983 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 06:53:34.210393 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 06:53:34.213860 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 06:53:34.216743 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 06:53:34.224067 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 06:53:34.227039 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 06:53:34.230616 0 11 4 | B1->B0 | 2c2c 3939 | 0 0 | (0 0) (0 0)
1489 06:53:34.237092 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1490 06:53:34.240569 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 06:53:34.244017 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 06:53:34.250249 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 06:53:34.253710 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 06:53:34.257004 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 06:53:34.263999 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1496 06:53:34.267059 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1497 06:53:34.270655 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 06:53:34.277378 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 06:53:34.280501 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 06:53:34.284196 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 06:53:34.287573 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 06:53:34.294046 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 06:53:34.297569 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 06:53:34.300760 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 06:53:34.307202 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 06:53:34.310674 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 06:53:34.314104 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 06:53:34.321032 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 06:53:34.324072 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 06:53:34.327552 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 06:53:34.334332 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 06:53:34.337798 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1513 06:53:34.341225 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 06:53:34.344026 Total UI for P1: 0, mck2ui 16
1515 06:53:34.347546 best dqsien dly found for B0: ( 0, 14, 4)
1516 06:53:34.350927 Total UI for P1: 0, mck2ui 16
1517 06:53:34.354339 best dqsien dly found for B1: ( 0, 14, 4)
1518 06:53:34.357052 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1519 06:53:34.360461 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1520 06:53:34.360542
1521 06:53:34.363824 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1522 06:53:34.370506 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1523 06:53:34.370587 [Gating] SW calibration Done
1524 06:53:34.370650 ==
1525 06:53:34.373970 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 06:53:34.380921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 06:53:34.381034 ==
1528 06:53:34.381131 RX Vref Scan: 0
1529 06:53:34.381206
1530 06:53:34.384255 RX Vref 0 -> 0, step: 1
1531 06:53:34.384373
1532 06:53:34.387445 RX Delay -130 -> 252, step: 16
1533 06:53:34.390735 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1534 06:53:34.394143 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1535 06:53:34.397576 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1536 06:53:34.403992 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1537 06:53:34.407334 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1538 06:53:34.410848 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1539 06:53:34.414013 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1540 06:53:34.417492 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1541 06:53:34.420923 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1542 06:53:34.427686 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1543 06:53:34.430948 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1544 06:53:34.434057 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1545 06:53:34.437658 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1546 06:53:34.444472 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1547 06:53:34.447213 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1548 06:53:34.451136 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1549 06:53:34.451217 ==
1550 06:53:34.453930 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 06:53:34.457433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 06:53:34.457515 ==
1553 06:53:34.460781 DQS Delay:
1554 06:53:34.460862 DQS0 = 0, DQS1 = 0
1555 06:53:34.464118 DQM Delay:
1556 06:53:34.464199 DQM0 = 93, DQM1 = 87
1557 06:53:34.464263 DQ Delay:
1558 06:53:34.467540 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1559 06:53:34.471021 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1560 06:53:34.473861 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1561 06:53:34.477121 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1562 06:53:34.477202
1563 06:53:34.477265
1564 06:53:34.477324 ==
1565 06:53:34.480463 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 06:53:34.487606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 06:53:34.487687 ==
1568 06:53:34.487751
1569 06:53:34.487810
1570 06:53:34.487867 TX Vref Scan disable
1571 06:53:34.491545 == TX Byte 0 ==
1572 06:53:34.494786 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1573 06:53:34.501485 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1574 06:53:34.501566 == TX Byte 1 ==
1575 06:53:34.504433 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1576 06:53:34.508301 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1577 06:53:34.511471 ==
1578 06:53:34.514599 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 06:53:34.517933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 06:53:34.518014 ==
1581 06:53:34.530891 TX Vref=22, minBit 1, minWin=26, winSum=438
1582 06:53:34.534356 TX Vref=24, minBit 0, minWin=26, winSum=440
1583 06:53:34.538534 TX Vref=26, minBit 3, minWin=27, winSum=447
1584 06:53:34.541901 TX Vref=28, minBit 1, minWin=27, winSum=447
1585 06:53:34.544723 TX Vref=30, minBit 1, minWin=27, winSum=449
1586 06:53:34.548088 TX Vref=32, minBit 2, minWin=26, winSum=446
1587 06:53:34.555313 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 30
1588 06:53:34.555395
1589 06:53:34.558457 Final TX Range 1 Vref 30
1590 06:53:34.558538
1591 06:53:34.558601 ==
1592 06:53:34.561439 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 06:53:34.564842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 06:53:34.564924 ==
1595 06:53:34.564988
1596 06:53:34.565046
1597 06:53:34.568212 TX Vref Scan disable
1598 06:53:34.571844 == TX Byte 0 ==
1599 06:53:34.575336 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1600 06:53:34.578727 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1601 06:53:34.582064 == TX Byte 1 ==
1602 06:53:34.585253 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1603 06:53:34.588054 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1604 06:53:34.588134
1605 06:53:34.588198 [DATLAT]
1606 06:53:34.591524 Freq=800, CH1 RK0
1607 06:53:34.591605
1608 06:53:34.595015 DATLAT Default: 0xa
1609 06:53:34.595096 0, 0xFFFF, sum = 0
1610 06:53:34.598254 1, 0xFFFF, sum = 0
1611 06:53:34.598336 2, 0xFFFF, sum = 0
1612 06:53:34.601981 3, 0xFFFF, sum = 0
1613 06:53:34.602063 4, 0xFFFF, sum = 0
1614 06:53:34.605303 5, 0xFFFF, sum = 0
1615 06:53:34.605386 6, 0xFFFF, sum = 0
1616 06:53:34.608778 7, 0xFFFF, sum = 0
1617 06:53:34.608860 8, 0xFFFF, sum = 0
1618 06:53:34.611579 9, 0x0, sum = 1
1619 06:53:34.611680 10, 0x0, sum = 2
1620 06:53:34.614931 11, 0x0, sum = 3
1621 06:53:34.615012 12, 0x0, sum = 4
1622 06:53:34.615077 best_step = 10
1623 06:53:34.615135
1624 06:53:34.618192 ==
1625 06:53:34.622014 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 06:53:34.625139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 06:53:34.625220 ==
1628 06:53:34.625283 RX Vref Scan: 1
1629 06:53:34.625343
1630 06:53:34.628502 Set Vref Range= 32 -> 127
1631 06:53:34.628582
1632 06:53:34.631717 RX Vref 32 -> 127, step: 1
1633 06:53:34.631798
1634 06:53:34.635310 RX Delay -79 -> 252, step: 8
1635 06:53:34.635391
1636 06:53:34.638676 Set Vref, RX VrefLevel [Byte0]: 32
1637 06:53:34.642283 [Byte1]: 32
1638 06:53:34.642364
1639 06:53:34.644970 Set Vref, RX VrefLevel [Byte0]: 33
1640 06:53:34.648572 [Byte1]: 33
1641 06:53:34.648652
1642 06:53:34.652047 Set Vref, RX VrefLevel [Byte0]: 34
1643 06:53:34.655295 [Byte1]: 34
1644 06:53:34.655375
1645 06:53:34.658808 Set Vref, RX VrefLevel [Byte0]: 35
1646 06:53:34.662316 [Byte1]: 35
1647 06:53:34.665795
1648 06:53:34.665882 Set Vref, RX VrefLevel [Byte0]: 36
1649 06:53:34.669175 [Byte1]: 36
1650 06:53:34.673215
1651 06:53:34.673294 Set Vref, RX VrefLevel [Byte0]: 37
1652 06:53:34.676488 [Byte1]: 37
1653 06:53:34.680945
1654 06:53:34.681025 Set Vref, RX VrefLevel [Byte0]: 38
1655 06:53:34.684164 [Byte1]: 38
1656 06:53:34.688884
1657 06:53:34.688964 Set Vref, RX VrefLevel [Byte0]: 39
1658 06:53:34.691902 [Byte1]: 39
1659 06:53:34.695922
1660 06:53:34.696001 Set Vref, RX VrefLevel [Byte0]: 40
1661 06:53:34.699549 [Byte1]: 40
1662 06:53:34.703469
1663 06:53:34.703549 Set Vref, RX VrefLevel [Byte0]: 41
1664 06:53:34.706769 [Byte1]: 41
1665 06:53:34.711193
1666 06:53:34.711274 Set Vref, RX VrefLevel [Byte0]: 42
1667 06:53:34.714516 [Byte1]: 42
1668 06:53:34.718596
1669 06:53:34.718676 Set Vref, RX VrefLevel [Byte0]: 43
1670 06:53:34.722145 [Byte1]: 43
1671 06:53:34.726114
1672 06:53:34.726194 Set Vref, RX VrefLevel [Byte0]: 44
1673 06:53:34.729315 [Byte1]: 44
1674 06:53:34.733657
1675 06:53:34.733737 Set Vref, RX VrefLevel [Byte0]: 45
1676 06:53:34.736857 [Byte1]: 45
1677 06:53:34.741419
1678 06:53:34.741499 Set Vref, RX VrefLevel [Byte0]: 46
1679 06:53:34.744779 [Byte1]: 46
1680 06:53:34.748945
1681 06:53:34.749031 Set Vref, RX VrefLevel [Byte0]: 47
1682 06:53:34.752263 [Byte1]: 47
1683 06:53:34.756306
1684 06:53:34.756402 Set Vref, RX VrefLevel [Byte0]: 48
1685 06:53:34.759731 [Byte1]: 48
1686 06:53:34.763862
1687 06:53:34.763942 Set Vref, RX VrefLevel [Byte0]: 49
1688 06:53:34.767319 [Byte1]: 49
1689 06:53:34.771565
1690 06:53:34.771645 Set Vref, RX VrefLevel [Byte0]: 50
1691 06:53:34.775163 [Byte1]: 50
1692 06:53:34.779118
1693 06:53:34.779198 Set Vref, RX VrefLevel [Byte0]: 51
1694 06:53:34.782441 [Byte1]: 51
1695 06:53:34.786553
1696 06:53:34.786633 Set Vref, RX VrefLevel [Byte0]: 52
1697 06:53:34.789838 [Byte1]: 52
1698 06:53:34.794083
1699 06:53:34.794163 Set Vref, RX VrefLevel [Byte0]: 53
1700 06:53:34.797437 [Byte1]: 53
1701 06:53:34.802051
1702 06:53:34.802132 Set Vref, RX VrefLevel [Byte0]: 54
1703 06:53:34.804765 [Byte1]: 54
1704 06:53:34.809246
1705 06:53:34.809326 Set Vref, RX VrefLevel [Byte0]: 55
1706 06:53:34.812389 [Byte1]: 55
1707 06:53:34.816579
1708 06:53:34.816658 Set Vref, RX VrefLevel [Byte0]: 56
1709 06:53:34.820032 [Byte1]: 56
1710 06:53:34.824415
1711 06:53:34.824495 Set Vref, RX VrefLevel [Byte0]: 57
1712 06:53:34.827362 [Byte1]: 57
1713 06:53:34.831548
1714 06:53:34.831628 Set Vref, RX VrefLevel [Byte0]: 58
1715 06:53:34.834984 [Byte1]: 58
1716 06:53:34.839655
1717 06:53:34.839735 Set Vref, RX VrefLevel [Byte0]: 59
1718 06:53:34.842727 [Byte1]: 59
1719 06:53:34.846788
1720 06:53:34.846868 Set Vref, RX VrefLevel [Byte0]: 60
1721 06:53:34.850472 [Byte1]: 60
1722 06:53:34.854522
1723 06:53:34.854627 Set Vref, RX VrefLevel [Byte0]: 61
1724 06:53:34.858146 [Byte1]: 61
1725 06:53:34.862222
1726 06:53:34.862294 Set Vref, RX VrefLevel [Byte0]: 62
1727 06:53:34.865618 [Byte1]: 62
1728 06:53:34.869808
1729 06:53:34.869904 Set Vref, RX VrefLevel [Byte0]: 63
1730 06:53:34.873197 [Byte1]: 63
1731 06:53:34.877338
1732 06:53:34.877411 Set Vref, RX VrefLevel [Byte0]: 64
1733 06:53:34.880639 [Byte1]: 64
1734 06:53:34.884821
1735 06:53:34.884893 Set Vref, RX VrefLevel [Byte0]: 65
1736 06:53:34.888176 [Byte1]: 65
1737 06:53:34.892318
1738 06:53:34.892400 Set Vref, RX VrefLevel [Byte0]: 66
1739 06:53:34.895575 [Byte1]: 66
1740 06:53:34.899584
1741 06:53:34.899663 Set Vref, RX VrefLevel [Byte0]: 67
1742 06:53:34.903078 [Byte1]: 67
1743 06:53:34.907058
1744 06:53:34.907137 Set Vref, RX VrefLevel [Byte0]: 68
1745 06:53:34.910499 [Byte1]: 68
1746 06:53:34.914630
1747 06:53:34.914708 Set Vref, RX VrefLevel [Byte0]: 69
1748 06:53:34.918100 [Byte1]: 69
1749 06:53:34.922373
1750 06:53:34.922451 Set Vref, RX VrefLevel [Byte0]: 70
1751 06:53:34.925738 [Byte1]: 70
1752 06:53:34.930430
1753 06:53:34.930512 Set Vref, RX VrefLevel [Byte0]: 71
1754 06:53:34.933395 [Byte1]: 71
1755 06:53:34.937654
1756 06:53:34.937756 Set Vref, RX VrefLevel [Byte0]: 72
1757 06:53:34.940712 [Byte1]: 72
1758 06:53:34.945287
1759 06:53:34.945363 Set Vref, RX VrefLevel [Byte0]: 73
1760 06:53:34.948415 [Byte1]: 73
1761 06:53:34.952701
1762 06:53:34.952803 Set Vref, RX VrefLevel [Byte0]: 74
1763 06:53:34.955678 [Byte1]: 74
1764 06:53:34.960433
1765 06:53:34.960509 Final RX Vref Byte 0 = 56 to rank0
1766 06:53:34.963337 Final RX Vref Byte 1 = 54 to rank0
1767 06:53:34.966810 Final RX Vref Byte 0 = 56 to rank1
1768 06:53:34.970185 Final RX Vref Byte 1 = 54 to rank1==
1769 06:53:34.973547 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 06:53:34.980241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 06:53:34.980382 ==
1772 06:53:34.980466 DQS Delay:
1773 06:53:34.980544 DQS0 = 0, DQS1 = 0
1774 06:53:34.983528 DQM Delay:
1775 06:53:34.983609 DQM0 = 95, DQM1 = 90
1776 06:53:34.986988 DQ Delay:
1777 06:53:34.990634 DQ0 =96, DQ1 =88, DQ2 =88, DQ3 =92
1778 06:53:34.990713 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1779 06:53:34.993957 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1780 06:53:35.000107 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1781 06:53:35.000187
1782 06:53:35.000266
1783 06:53:35.006700 [DQSOSCAuto] RK0, (LSB)MR18= 0x304d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1784 06:53:35.010521 CH1 RK0: MR19=606, MR18=304D
1785 06:53:35.016732 CH1_RK0: MR19=0x606, MR18=0x304D, DQSOSC=390, MR23=63, INC=97, DEC=64
1786 06:53:35.016812
1787 06:53:35.020173 ----->DramcWriteLeveling(PI) begin...
1788 06:53:35.020280 ==
1789 06:53:35.023722 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 06:53:35.027251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 06:53:35.027332 ==
1792 06:53:35.030705 Write leveling (Byte 0): 27 => 27
1793 06:53:35.033507 Write leveling (Byte 1): 27 => 27
1794 06:53:35.037093 DramcWriteLeveling(PI) end<-----
1795 06:53:35.037172
1796 06:53:35.037234 ==
1797 06:53:35.040481 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 06:53:35.043694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 06:53:35.043773 ==
1800 06:53:35.047163 [Gating] SW mode calibration
1801 06:53:35.053871 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 06:53:35.060163 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 06:53:35.063915 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1804 06:53:35.067326 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1805 06:53:35.073441 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 06:53:35.077095 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 06:53:35.080185 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 06:53:35.086711 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 06:53:35.090451 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 06:53:35.093412 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 06:53:35.100438 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 06:53:35.103838 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 06:53:35.106660 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 06:53:35.113440 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 06:53:35.117261 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 06:53:35.120436 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 06:53:35.123523 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 06:53:35.130440 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 06:53:35.133811 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1820 06:53:35.137236 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1821 06:53:35.143552 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 06:53:35.146980 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 06:53:35.150321 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 06:53:35.157338 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 06:53:35.160803 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 06:53:35.164127 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 06:53:35.170701 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 06:53:35.174206 0 9 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
1829 06:53:35.177098 0 9 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1830 06:53:35.184172 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 06:53:35.187499 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 06:53:35.190984 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 06:53:35.194540 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 06:53:35.200542 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 06:53:35.203983 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
1836 06:53:35.207432 0 10 4 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
1837 06:53:35.214123 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
1838 06:53:35.217477 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 06:53:35.221030 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 06:53:35.227815 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 06:53:35.231038 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 06:53:35.234220 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 06:53:35.240752 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1844 06:53:35.244293 0 11 4 | B1->B0 | 3939 3030 | 0 0 | (1 1) (0 0)
1845 06:53:35.247710 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 06:53:35.251355 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 06:53:35.257988 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 06:53:35.260759 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 06:53:35.264305 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 06:53:35.271360 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 06:53:35.274757 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 06:53:35.277595 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1853 06:53:35.284511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 06:53:35.287856 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 06:53:35.291185 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 06:53:35.298014 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 06:53:35.300779 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 06:53:35.304280 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 06:53:35.310896 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 06:53:35.314247 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 06:53:35.318002 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 06:53:35.324647 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 06:53:35.327644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 06:53:35.330790 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 06:53:35.338116 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 06:53:35.341323 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 06:53:35.344495 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 06:53:35.347824 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1869 06:53:35.354506 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 06:53:35.358067 Total UI for P1: 0, mck2ui 16
1871 06:53:35.361521 best dqsien dly found for B0: ( 0, 14, 6)
1872 06:53:35.364085 Total UI for P1: 0, mck2ui 16
1873 06:53:35.367455 best dqsien dly found for B1: ( 0, 14, 4)
1874 06:53:35.371105 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1875 06:53:35.374300 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1876 06:53:35.374379
1877 06:53:35.377729 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1878 06:53:35.381183 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1879 06:53:35.384540 [Gating] SW calibration Done
1880 06:53:35.384619 ==
1881 06:53:35.387943 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 06:53:35.391433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 06:53:35.391513 ==
1884 06:53:35.394223 RX Vref Scan: 0
1885 06:53:35.394302
1886 06:53:35.394364 RX Vref 0 -> 0, step: 1
1887 06:53:35.394442
1888 06:53:35.398143 RX Delay -130 -> 252, step: 16
1889 06:53:35.401468 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1890 06:53:35.407689 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1891 06:53:35.411271 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1892 06:53:35.414553 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1893 06:53:35.418033 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1894 06:53:35.421574 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1895 06:53:35.427604 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1896 06:53:35.431079 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1897 06:53:35.434479 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1898 06:53:35.437738 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1899 06:53:35.441420 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1900 06:53:35.447865 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1901 06:53:35.451646 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1902 06:53:35.454705 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1903 06:53:35.458259 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1904 06:53:35.461466 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1905 06:53:35.461545 ==
1906 06:53:35.465049 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 06:53:35.471571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1908 06:53:35.471651 ==
1909 06:53:35.471714 DQS Delay:
1910 06:53:35.474985 DQS0 = 0, DQS1 = 0
1911 06:53:35.475064 DQM Delay:
1912 06:53:35.475127 DQM0 = 91, DQM1 = 87
1913 06:53:35.478231 DQ Delay:
1914 06:53:35.481110 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1915 06:53:35.484430 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1916 06:53:35.487739 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1917 06:53:35.491228 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1918 06:53:35.491307
1919 06:53:35.491369
1920 06:53:35.491426 ==
1921 06:53:35.494637 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 06:53:35.498235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 06:53:35.498340 ==
1924 06:53:35.498430
1925 06:53:35.498510
1926 06:53:35.501653 TX Vref Scan disable
1927 06:53:35.505014 == TX Byte 0 ==
1928 06:53:35.507809 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1929 06:53:35.511206 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1930 06:53:35.514662 == TX Byte 1 ==
1931 06:53:35.518021 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1932 06:53:35.521339 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1933 06:53:35.521419 ==
1934 06:53:35.524934 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 06:53:35.528171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 06:53:35.528276 ==
1937 06:53:35.542434 TX Vref=22, minBit 1, minWin=26, winSum=439
1938 06:53:35.545945 TX Vref=24, minBit 1, minWin=27, winSum=445
1939 06:53:35.549176 TX Vref=26, minBit 2, minWin=27, winSum=447
1940 06:53:35.552437 TX Vref=28, minBit 2, minWin=27, winSum=449
1941 06:53:35.555667 TX Vref=30, minBit 2, minWin=27, winSum=447
1942 06:53:35.558778 TX Vref=32, minBit 2, minWin=27, winSum=447
1943 06:53:35.565842 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 28
1944 06:53:35.565922
1945 06:53:35.568940 Final TX Range 1 Vref 28
1946 06:53:35.569020
1947 06:53:35.569082 ==
1948 06:53:35.572081 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 06:53:35.575668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 06:53:35.575746 ==
1951 06:53:35.575809
1952 06:53:35.575866
1953 06:53:35.579095 TX Vref Scan disable
1954 06:53:35.582339 == TX Byte 0 ==
1955 06:53:35.585582 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1956 06:53:35.589411 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1957 06:53:35.592853 == TX Byte 1 ==
1958 06:53:35.596122 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1959 06:53:35.599530 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1960 06:53:35.599609
1961 06:53:35.602308 [DATLAT]
1962 06:53:35.602387 Freq=800, CH1 RK1
1963 06:53:35.602450
1964 06:53:35.605697 DATLAT Default: 0xa
1965 06:53:35.605780 0, 0xFFFF, sum = 0
1966 06:53:35.609089 1, 0xFFFF, sum = 0
1967 06:53:35.609170 2, 0xFFFF, sum = 0
1968 06:53:35.612433 3, 0xFFFF, sum = 0
1969 06:53:35.612513 4, 0xFFFF, sum = 0
1970 06:53:35.615786 5, 0xFFFF, sum = 0
1971 06:53:35.615866 6, 0xFFFF, sum = 0
1972 06:53:35.619255 7, 0xFFFF, sum = 0
1973 06:53:35.619336 8, 0xFFFF, sum = 0
1974 06:53:35.622645 9, 0x0, sum = 1
1975 06:53:35.622754 10, 0x0, sum = 2
1976 06:53:35.626093 11, 0x0, sum = 3
1977 06:53:35.626174 12, 0x0, sum = 4
1978 06:53:35.628975 best_step = 10
1979 06:53:35.629054
1980 06:53:35.629115 ==
1981 06:53:35.632269 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 06:53:35.636006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 06:53:35.636116 ==
1984 06:53:35.639214 RX Vref Scan: 0
1985 06:53:35.639292
1986 06:53:35.639354 RX Vref 0 -> 0, step: 1
1987 06:53:35.639412
1988 06:53:35.642597 RX Delay -79 -> 252, step: 8
1989 06:53:35.646091 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1990 06:53:35.653095 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1991 06:53:35.655677 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1992 06:53:35.659216 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1993 06:53:35.662579 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1994 06:53:35.665776 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1995 06:53:35.672328 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1996 06:53:35.675766 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1997 06:53:35.679310 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1998 06:53:35.682600 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1999 06:53:35.686000 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2000 06:53:35.692246 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2001 06:53:35.695811 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2002 06:53:35.698788 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2003 06:53:35.702453 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2004 06:53:35.705824 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2005 06:53:35.705903 ==
2006 06:53:35.709070 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 06:53:35.715633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 06:53:35.715712 ==
2009 06:53:35.715775 DQS Delay:
2010 06:53:35.718840 DQS0 = 0, DQS1 = 0
2011 06:53:35.718919 DQM Delay:
2012 06:53:35.718981 DQM0 = 97, DQM1 = 91
2013 06:53:35.722233 DQ Delay:
2014 06:53:35.725644 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2015 06:53:35.729061 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2016 06:53:35.732537 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2017 06:53:35.735952 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2018 06:53:35.736031
2019 06:53:35.736093
2020 06:53:35.742952 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2021 06:53:35.746200 CH1 RK1: MR19=606, MR18=440E
2022 06:53:35.752276 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2023 06:53:35.755806 [RxdqsGatingPostProcess] freq 800
2024 06:53:35.759159 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2025 06:53:35.762691 Pre-setting of DQS Precalculation
2026 06:53:35.769487 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2027 06:53:35.776226 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2028 06:53:35.782706 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2029 06:53:35.782803
2030 06:53:35.782899
2031 06:53:35.786042 [Calibration Summary] 1600 Mbps
2032 06:53:35.786121 CH 0, Rank 0
2033 06:53:35.789439 SW Impedance : PASS
2034 06:53:35.793007 DUTY Scan : NO K
2035 06:53:35.793087 ZQ Calibration : PASS
2036 06:53:35.795795 Jitter Meter : NO K
2037 06:53:35.799291 CBT Training : PASS
2038 06:53:35.799370 Write leveling : PASS
2039 06:53:35.802703 RX DQS gating : PASS
2040 06:53:35.806136 RX DQ/DQS(RDDQC) : PASS
2041 06:53:35.806215 TX DQ/DQS : PASS
2042 06:53:35.809342 RX DATLAT : PASS
2043 06:53:35.809420 RX DQ/DQS(Engine): PASS
2044 06:53:35.812594 TX OE : NO K
2045 06:53:35.812673 All Pass.
2046 06:53:35.812735
2047 06:53:35.816391 CH 0, Rank 1
2048 06:53:35.816470 SW Impedance : PASS
2049 06:53:35.819435 DUTY Scan : NO K
2050 06:53:35.823058 ZQ Calibration : PASS
2051 06:53:35.823137 Jitter Meter : NO K
2052 06:53:35.825997 CBT Training : PASS
2053 06:53:35.829402 Write leveling : PASS
2054 06:53:35.829481 RX DQS gating : PASS
2055 06:53:35.832832 RX DQ/DQS(RDDQC) : PASS
2056 06:53:35.836068 TX DQ/DQS : PASS
2057 06:53:35.836148 RX DATLAT : PASS
2058 06:53:35.839290 RX DQ/DQS(Engine): PASS
2059 06:53:35.842550 TX OE : NO K
2060 06:53:35.842628 All Pass.
2061 06:53:35.842690
2062 06:53:35.842760 CH 1, Rank 0
2063 06:53:35.845868 SW Impedance : PASS
2064 06:53:35.849304 DUTY Scan : NO K
2065 06:53:35.849384 ZQ Calibration : PASS
2066 06:53:35.852938 Jitter Meter : NO K
2067 06:53:35.853017 CBT Training : PASS
2068 06:53:35.856153 Write leveling : PASS
2069 06:53:35.859625 RX DQS gating : PASS
2070 06:53:35.859704 RX DQ/DQS(RDDQC) : PASS
2071 06:53:35.863180 TX DQ/DQS : PASS
2072 06:53:35.866582 RX DATLAT : PASS
2073 06:53:35.866661 RX DQ/DQS(Engine): PASS
2074 06:53:35.869266 TX OE : NO K
2075 06:53:35.869346 All Pass.
2076 06:53:35.869408
2077 06:53:35.872806 CH 1, Rank 1
2078 06:53:35.872897 SW Impedance : PASS
2079 06:53:35.876178 DUTY Scan : NO K
2080 06:53:35.879660 ZQ Calibration : PASS
2081 06:53:35.879739 Jitter Meter : NO K
2082 06:53:35.883090 CBT Training : PASS
2083 06:53:35.886201 Write leveling : PASS
2084 06:53:35.886294 RX DQS gating : PASS
2085 06:53:35.889480 RX DQ/DQS(RDDQC) : PASS
2086 06:53:35.889559 TX DQ/DQS : PASS
2087 06:53:35.892732 RX DATLAT : PASS
2088 06:53:35.896193 RX DQ/DQS(Engine): PASS
2089 06:53:35.896272 TX OE : NO K
2090 06:53:35.899658 All Pass.
2091 06:53:35.899736
2092 06:53:35.899798 DramC Write-DBI off
2093 06:53:35.903224 PER_BANK_REFRESH: Hybrid Mode
2094 06:53:35.906720 TX_TRACKING: ON
2095 06:53:35.906799 [GetDramInforAfterCalByMRR] Vendor 6.
2096 06:53:35.912948 [GetDramInforAfterCalByMRR] Revision 606.
2097 06:53:35.916276 [GetDramInforAfterCalByMRR] Revision 2 0.
2098 06:53:35.916367 MR0 0x3b3b
2099 06:53:35.916429 MR8 0x5151
2100 06:53:35.919744 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 06:53:35.919823
2102 06:53:35.923284 MR0 0x3b3b
2103 06:53:35.923362 MR8 0x5151
2104 06:53:35.926847 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 06:53:35.926955
2106 06:53:35.936184 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2107 06:53:35.939463 [FAST_K] Save calibration result to emmc
2108 06:53:35.942782 [FAST_K] Save calibration result to emmc
2109 06:53:35.946258 dram_init: config_dvfs: 1
2110 06:53:35.949693 dramc_set_vcore_voltage set vcore to 662500
2111 06:53:35.953081 Read voltage for 1200, 2
2112 06:53:35.953162 Vio18 = 0
2113 06:53:35.953224 Vcore = 662500
2114 06:53:35.956440 Vdram = 0
2115 06:53:35.956520 Vddq = 0
2116 06:53:35.956583 Vmddr = 0
2117 06:53:35.962699 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2118 06:53:35.966286 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2119 06:53:35.969919 MEM_TYPE=3, freq_sel=15
2120 06:53:35.972965 sv_algorithm_assistance_LP4_1600
2121 06:53:35.976046 ============ PULL DRAM RESETB DOWN ============
2122 06:53:35.979402 ========== PULL DRAM RESETB DOWN end =========
2123 06:53:35.986330 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 06:53:35.989900 ===================================
2125 06:53:35.989980 LPDDR4 DRAM CONFIGURATION
2126 06:53:35.993404 ===================================
2127 06:53:35.996659 EX_ROW_EN[0] = 0x0
2128 06:53:35.999765 EX_ROW_EN[1] = 0x0
2129 06:53:35.999856 LP4Y_EN = 0x0
2130 06:53:36.002876 WORK_FSP = 0x0
2131 06:53:36.002956 WL = 0x4
2132 06:53:36.006302 RL = 0x4
2133 06:53:36.006382 BL = 0x2
2134 06:53:36.009904 RPST = 0x0
2135 06:53:36.009990 RD_PRE = 0x0
2136 06:53:36.012894 WR_PRE = 0x1
2137 06:53:36.012999 WR_PST = 0x0
2138 06:53:36.016695 DBI_WR = 0x0
2139 06:53:36.016800 DBI_RD = 0x0
2140 06:53:36.019527 OTF = 0x1
2141 06:53:36.023054 ===================================
2142 06:53:36.026487 ===================================
2143 06:53:36.026567 ANA top config
2144 06:53:36.029917 ===================================
2145 06:53:36.032999 DLL_ASYNC_EN = 0
2146 06:53:36.036709 ALL_SLAVE_EN = 0
2147 06:53:36.036814 NEW_RANK_MODE = 1
2148 06:53:36.039503 DLL_IDLE_MODE = 1
2149 06:53:36.042833 LP45_APHY_COMB_EN = 1
2150 06:53:36.046587 TX_ODT_DIS = 1
2151 06:53:36.049898 NEW_8X_MODE = 1
2152 06:53:36.053204 ===================================
2153 06:53:36.056515 ===================================
2154 06:53:36.056621 data_rate = 2400
2155 06:53:36.059779 CKR = 1
2156 06:53:36.063270 DQ_P2S_RATIO = 8
2157 06:53:36.066713 ===================================
2158 06:53:36.070134 CA_P2S_RATIO = 8
2159 06:53:36.073374 DQ_CA_OPEN = 0
2160 06:53:36.076759 DQ_SEMI_OPEN = 0
2161 06:53:36.076843 CA_SEMI_OPEN = 0
2162 06:53:36.079932 CA_FULL_RATE = 0
2163 06:53:36.083078 DQ_CKDIV4_EN = 0
2164 06:53:36.086878 CA_CKDIV4_EN = 0
2165 06:53:36.090030 CA_PREDIV_EN = 0
2166 06:53:36.093054 PH8_DLY = 17
2167 06:53:36.093189 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2168 06:53:36.096477 DQ_AAMCK_DIV = 4
2169 06:53:36.099987 CA_AAMCK_DIV = 4
2170 06:53:36.103551 CA_ADMCK_DIV = 4
2171 06:53:36.106862 DQ_TRACK_CA_EN = 0
2172 06:53:36.110101 CA_PICK = 1200
2173 06:53:36.110182 CA_MCKIO = 1200
2174 06:53:36.113177 MCKIO_SEMI = 0
2175 06:53:36.116251 PLL_FREQ = 2366
2176 06:53:36.119720 DQ_UI_PI_RATIO = 32
2177 06:53:36.122957 CA_UI_PI_RATIO = 0
2178 06:53:36.126546 ===================================
2179 06:53:36.130088 ===================================
2180 06:53:36.133550 memory_type:LPDDR4
2181 06:53:36.133630 GP_NUM : 10
2182 06:53:36.136282 SRAM_EN : 1
2183 06:53:36.136401 MD32_EN : 0
2184 06:53:36.139698 ===================================
2185 06:53:36.143027 [ANA_INIT] >>>>>>>>>>>>>>
2186 06:53:36.146467 <<<<<< [CONFIGURE PHASE]: ANA_TX
2187 06:53:36.149816 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2188 06:53:36.153000 ===================================
2189 06:53:36.156548 data_rate = 2400,PCW = 0X5b00
2190 06:53:36.159866 ===================================
2191 06:53:36.163255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2192 06:53:36.167124 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 06:53:36.173814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 06:53:36.176492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2195 06:53:36.180024 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2196 06:53:36.183442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2197 06:53:36.186816 [ANA_INIT] flow start
2198 06:53:36.190288 [ANA_INIT] PLL >>>>>>>>
2199 06:53:36.190371 [ANA_INIT] PLL <<<<<<<<
2200 06:53:36.193101 [ANA_INIT] MIDPI >>>>>>>>
2201 06:53:36.196471 [ANA_INIT] MIDPI <<<<<<<<
2202 06:53:36.199667 [ANA_INIT] DLL >>>>>>>>
2203 06:53:36.199746 [ANA_INIT] DLL <<<<<<<<
2204 06:53:36.202984 [ANA_INIT] flow end
2205 06:53:36.206697 ============ LP4 DIFF to SE enter ============
2206 06:53:36.210012 ============ LP4 DIFF to SE exit ============
2207 06:53:36.213528 [ANA_INIT] <<<<<<<<<<<<<
2208 06:53:36.216244 [Flow] Enable top DCM control >>>>>
2209 06:53:36.219635 [Flow] Enable top DCM control <<<<<
2210 06:53:36.222973 Enable DLL master slave shuffle
2211 06:53:36.229776 ==============================================================
2212 06:53:36.229859 Gating Mode config
2213 06:53:36.236165 ==============================================================
2214 06:53:36.236271 Config description:
2215 06:53:36.246681 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2216 06:53:36.253553 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2217 06:53:36.259537 SELPH_MODE 0: By rank 1: By Phase
2218 06:53:36.262841 ==============================================================
2219 06:53:36.266347 GAT_TRACK_EN = 1
2220 06:53:36.269775 RX_GATING_MODE = 2
2221 06:53:36.273118 RX_GATING_TRACK_MODE = 2
2222 06:53:36.276251 SELPH_MODE = 1
2223 06:53:36.279530 PICG_EARLY_EN = 1
2224 06:53:36.282949 VALID_LAT_VALUE = 1
2225 06:53:36.286335 ==============================================================
2226 06:53:36.289772 Enter into Gating configuration >>>>
2227 06:53:36.293113 Exit from Gating configuration <<<<
2228 06:53:36.296659 Enter into DVFS_PRE_config >>>>>
2229 06:53:36.309653 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2230 06:53:36.312981 Exit from DVFS_PRE_config <<<<<
2231 06:53:36.316153 Enter into PICG configuration >>>>
2232 06:53:36.316259 Exit from PICG configuration <<<<
2233 06:53:36.319970 [RX_INPUT] configuration >>>>>
2234 06:53:36.323068 [RX_INPUT] configuration <<<<<
2235 06:53:36.329823 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2236 06:53:36.333210 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2237 06:53:36.339545 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 06:53:36.346599 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 06:53:36.352895 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 06:53:36.359561 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 06:53:36.362831 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2242 06:53:36.366119 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2243 06:53:36.369824 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2244 06:53:36.376104 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2245 06:53:36.379511 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2246 06:53:36.382831 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2247 06:53:36.386548 ===================================
2248 06:53:36.389879 LPDDR4 DRAM CONFIGURATION
2249 06:53:36.393276 ===================================
2250 06:53:36.396709 EX_ROW_EN[0] = 0x0
2251 06:53:36.396789 EX_ROW_EN[1] = 0x0
2252 06:53:36.400146 LP4Y_EN = 0x0
2253 06:53:36.400225 WORK_FSP = 0x0
2254 06:53:36.403622 WL = 0x4
2255 06:53:36.403702 RL = 0x4
2256 06:53:36.406414 BL = 0x2
2257 06:53:36.406494 RPST = 0x0
2258 06:53:36.409867 RD_PRE = 0x0
2259 06:53:36.409946 WR_PRE = 0x1
2260 06:53:36.413298 WR_PST = 0x0
2261 06:53:36.413378 DBI_WR = 0x0
2262 06:53:36.416702 DBI_RD = 0x0
2263 06:53:36.416782 OTF = 0x1
2264 06:53:36.420136 ===================================
2265 06:53:36.423030 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2266 06:53:36.429764 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2267 06:53:36.433124 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 06:53:36.436338 ===================================
2269 06:53:36.439818 LPDDR4 DRAM CONFIGURATION
2270 06:53:36.443418 ===================================
2271 06:53:36.443498 EX_ROW_EN[0] = 0x10
2272 06:53:36.446685 EX_ROW_EN[1] = 0x0
2273 06:53:36.446769 LP4Y_EN = 0x0
2274 06:53:36.449728 WORK_FSP = 0x0
2275 06:53:36.449809 WL = 0x4
2276 06:53:36.452983 RL = 0x4
2277 06:53:36.453062 BL = 0x2
2278 06:53:36.456214 RPST = 0x0
2279 06:53:36.459513 RD_PRE = 0x0
2280 06:53:36.459596 WR_PRE = 0x1
2281 06:53:36.463483 WR_PST = 0x0
2282 06:53:36.463563 DBI_WR = 0x0
2283 06:53:36.466275 DBI_RD = 0x0
2284 06:53:36.466354 OTF = 0x1
2285 06:53:36.469734 ===================================
2286 06:53:36.476815 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2287 06:53:36.476895 ==
2288 06:53:36.480125 Dram Type= 6, Freq= 0, CH_0, rank 0
2289 06:53:36.483542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2290 06:53:36.483640 ==
2291 06:53:36.486334 [Duty_Offset_Calibration]
2292 06:53:36.486414 B0:2 B1:1 CA:1
2293 06:53:36.489729
2294 06:53:36.489807 [DutyScan_Calibration_Flow] k_type=0
2295 06:53:36.500647
2296 06:53:36.500737 ==CLK 0==
2297 06:53:36.504278 Final CLK duty delay cell = 0
2298 06:53:36.507703 [0] MAX Duty = 5187%(X100), DQS PI = 24
2299 06:53:36.511144 [0] MIN Duty = 4875%(X100), DQS PI = 0
2300 06:53:36.511222 [0] AVG Duty = 5031%(X100)
2301 06:53:36.513968
2302 06:53:36.514047 CH0 CLK Duty spec in!! Max-Min= 312%
2303 06:53:36.520840 [DutyScan_Calibration_Flow] ====Done====
2304 06:53:36.520919
2305 06:53:36.524228 [DutyScan_Calibration_Flow] k_type=1
2306 06:53:36.539455
2307 06:53:36.539533 ==DQS 0 ==
2308 06:53:36.542883 Final DQS duty delay cell = -4
2309 06:53:36.546390 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2310 06:53:36.549752 [-4] MIN Duty = 4782%(X100), DQS PI = 62
2311 06:53:36.552863 [-4] AVG Duty = 4953%(X100)
2312 06:53:36.552942
2313 06:53:36.553004 ==DQS 1 ==
2314 06:53:36.556236 Final DQS duty delay cell = 0
2315 06:53:36.559397 [0] MAX Duty = 5156%(X100), DQS PI = 62
2316 06:53:36.563018 [0] MIN Duty = 5000%(X100), DQS PI = 36
2317 06:53:36.566035 [0] AVG Duty = 5078%(X100)
2318 06:53:36.566113
2319 06:53:36.569468 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2320 06:53:36.569547
2321 06:53:36.572976 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2322 06:53:36.576332 [DutyScan_Calibration_Flow] ====Done====
2323 06:53:36.576411
2324 06:53:36.579703 [DutyScan_Calibration_Flow] k_type=3
2325 06:53:36.596321
2326 06:53:36.596414 ==DQM 0 ==
2327 06:53:36.599727 Final DQM duty delay cell = 0
2328 06:53:36.603081 [0] MAX Duty = 5156%(X100), DQS PI = 30
2329 06:53:36.606472 [0] MIN Duty = 4875%(X100), DQS PI = 58
2330 06:53:36.606550 [0] AVG Duty = 5015%(X100)
2331 06:53:36.609739
2332 06:53:36.609818 ==DQM 1 ==
2333 06:53:36.613055 Final DQM duty delay cell = 0
2334 06:53:36.616779 [0] MAX Duty = 5093%(X100), DQS PI = 0
2335 06:53:36.619545 [0] MIN Duty = 5031%(X100), DQS PI = 16
2336 06:53:36.619625 [0] AVG Duty = 5062%(X100)
2337 06:53:36.623051
2338 06:53:36.626398 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2339 06:53:36.626477
2340 06:53:36.629801 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2341 06:53:36.633243 [DutyScan_Calibration_Flow] ====Done====
2342 06:53:36.633322
2343 06:53:36.636014 [DutyScan_Calibration_Flow] k_type=2
2344 06:53:36.652806
2345 06:53:36.652885 ==DQ 0 ==
2346 06:53:36.656159 Final DQ duty delay cell = 0
2347 06:53:36.659356 [0] MAX Duty = 5031%(X100), DQS PI = 26
2348 06:53:36.662938 [0] MIN Duty = 4906%(X100), DQS PI = 0
2349 06:53:36.663017 [0] AVG Duty = 4968%(X100)
2350 06:53:36.663079
2351 06:53:36.666301 ==DQ 1 ==
2352 06:53:36.669895 Final DQ duty delay cell = 0
2353 06:53:36.672673 [0] MAX Duty = 5093%(X100), DQS PI = 10
2354 06:53:36.676587 [0] MIN Duty = 4969%(X100), DQS PI = 14
2355 06:53:36.676667 [0] AVG Duty = 5031%(X100)
2356 06:53:36.676729
2357 06:53:36.679642 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2358 06:53:36.679721
2359 06:53:36.682807 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2360 06:53:36.689726 [DutyScan_Calibration_Flow] ====Done====
2361 06:53:36.689805 ==
2362 06:53:36.692604 Dram Type= 6, Freq= 0, CH_1, rank 0
2363 06:53:36.696189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 06:53:36.696268 ==
2365 06:53:36.699941 [Duty_Offset_Calibration]
2366 06:53:36.700024 B0:1 B1:0 CA:0
2367 06:53:36.700085
2368 06:53:36.702734 [DutyScan_Calibration_Flow] k_type=0
2369 06:53:36.711701
2370 06:53:36.711804 ==CLK 0==
2371 06:53:36.715442 Final CLK duty delay cell = -4
2372 06:53:36.718774 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2373 06:53:36.722147 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2374 06:53:36.725397 [-4] AVG Duty = 4937%(X100)
2375 06:53:36.725475
2376 06:53:36.728722 CH1 CLK Duty spec in!! Max-Min= 125%
2377 06:53:36.732034 [DutyScan_Calibration_Flow] ====Done====
2378 06:53:36.732112
2379 06:53:36.735563 [DutyScan_Calibration_Flow] k_type=1
2380 06:53:36.751526
2381 06:53:36.751605 ==DQS 0 ==
2382 06:53:36.755035 Final DQS duty delay cell = 0
2383 06:53:36.758583 [0] MAX Duty = 5094%(X100), DQS PI = 24
2384 06:53:36.762052 [0] MIN Duty = 4875%(X100), DQS PI = 0
2385 06:53:36.762132 [0] AVG Duty = 4984%(X100)
2386 06:53:36.765493
2387 06:53:36.765571 ==DQS 1 ==
2388 06:53:36.768978 Final DQS duty delay cell = 0
2389 06:53:36.771642 [0] MAX Duty = 5187%(X100), DQS PI = 18
2390 06:53:36.775159 [0] MIN Duty = 4969%(X100), DQS PI = 8
2391 06:53:36.775239 [0] AVG Duty = 5078%(X100)
2392 06:53:36.775302
2393 06:53:36.782109 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2394 06:53:36.782189
2395 06:53:36.784894 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2396 06:53:36.788361 [DutyScan_Calibration_Flow] ====Done====
2397 06:53:36.788441
2398 06:53:36.791796 [DutyScan_Calibration_Flow] k_type=3
2399 06:53:36.808271
2400 06:53:36.808423 ==DQM 0 ==
2401 06:53:36.811420 Final DQM duty delay cell = 0
2402 06:53:36.814904 [0] MAX Duty = 5156%(X100), DQS PI = 6
2403 06:53:36.818088 [0] MIN Duty = 5031%(X100), DQS PI = 0
2404 06:53:36.818168 [0] AVG Duty = 5093%(X100)
2405 06:53:36.818231
2406 06:53:36.821775 ==DQM 1 ==
2407 06:53:36.824766 Final DQM duty delay cell = 0
2408 06:53:36.828544 [0] MAX Duty = 5031%(X100), DQS PI = 16
2409 06:53:36.831591 [0] MIN Duty = 4907%(X100), DQS PI = 34
2410 06:53:36.831680 [0] AVG Duty = 4969%(X100)
2411 06:53:36.831743
2412 06:53:36.838095 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2413 06:53:36.838175
2414 06:53:36.841471 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2415 06:53:36.844973 [DutyScan_Calibration_Flow] ====Done====
2416 06:53:36.845052
2417 06:53:36.848184 [DutyScan_Calibration_Flow] k_type=2
2418 06:53:36.864192
2419 06:53:36.864278 ==DQ 0 ==
2420 06:53:36.867791 Final DQ duty delay cell = -4
2421 06:53:36.870565 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2422 06:53:36.873826 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2423 06:53:36.877341 [-4] AVG Duty = 4984%(X100)
2424 06:53:36.877420
2425 06:53:36.877482 ==DQ 1 ==
2426 06:53:36.880826 Final DQ duty delay cell = 0
2427 06:53:36.884248 [0] MAX Duty = 5125%(X100), DQS PI = 20
2428 06:53:36.887710 [0] MIN Duty = 4969%(X100), DQS PI = 12
2429 06:53:36.887789 [0] AVG Duty = 5047%(X100)
2430 06:53:36.890589
2431 06:53:36.894074 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2432 06:53:36.894154
2433 06:53:36.897580 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2434 06:53:36.900995 [DutyScan_Calibration_Flow] ====Done====
2435 06:53:36.904420 nWR fixed to 30
2436 06:53:36.904501 [ModeRegInit_LP4] CH0 RK0
2437 06:53:36.907759 [ModeRegInit_LP4] CH0 RK1
2438 06:53:36.911030 [ModeRegInit_LP4] CH1 RK0
2439 06:53:36.911110 [ModeRegInit_LP4] CH1 RK1
2440 06:53:36.914196 match AC timing 7
2441 06:53:36.917788 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2442 06:53:36.920933 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2443 06:53:36.927658 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2444 06:53:36.930580 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2445 06:53:36.937513 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2446 06:53:36.937595 ==
2447 06:53:36.941231 Dram Type= 6, Freq= 0, CH_0, rank 0
2448 06:53:36.944427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 06:53:36.944508 ==
2450 06:53:36.950957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2451 06:53:36.954602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2452 06:53:36.963974 [CA 0] Center 39 (8~70) winsize 63
2453 06:53:36.967610 [CA 1] Center 39 (8~70) winsize 63
2454 06:53:36.970551 [CA 2] Center 35 (5~66) winsize 62
2455 06:53:36.974072 [CA 3] Center 34 (4~65) winsize 62
2456 06:53:36.977748 [CA 4] Center 33 (3~64) winsize 62
2457 06:53:36.981158 [CA 5] Center 32 (3~62) winsize 60
2458 06:53:36.981239
2459 06:53:36.983901 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2460 06:53:36.984007
2461 06:53:36.987342 [CATrainingPosCal] consider 1 rank data
2462 06:53:36.990712 u2DelayCellTimex100 = 270/100 ps
2463 06:53:36.994314 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2464 06:53:36.997748 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2465 06:53:37.003961 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2466 06:53:37.007425 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2467 06:53:37.011019 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2468 06:53:37.013943 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2469 06:53:37.014024
2470 06:53:37.017515 CA PerBit enable=1, Macro0, CA PI delay=32
2471 06:53:37.017596
2472 06:53:37.020855 [CBTSetCACLKResult] CA Dly = 32
2473 06:53:37.020936 CS Dly: 6 (0~37)
2474 06:53:37.020998 ==
2475 06:53:37.024184 Dram Type= 6, Freq= 0, CH_0, rank 1
2476 06:53:37.031231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 06:53:37.031312 ==
2478 06:53:37.034573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 06:53:37.040712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2480 06:53:37.050264 [CA 0] Center 38 (8~69) winsize 62
2481 06:53:37.053615 [CA 1] Center 38 (8~69) winsize 62
2482 06:53:37.056893 [CA 2] Center 35 (4~66) winsize 63
2483 06:53:37.060154 [CA 3] Center 34 (4~65) winsize 62
2484 06:53:37.063418 [CA 4] Center 33 (3~64) winsize 62
2485 06:53:37.066567 [CA 5] Center 32 (2~62) winsize 61
2486 06:53:37.066647
2487 06:53:37.069732 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2488 06:53:37.069812
2489 06:53:37.073613 [CATrainingPosCal] consider 2 rank data
2490 06:53:37.077242 u2DelayCellTimex100 = 270/100 ps
2491 06:53:37.079953 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2492 06:53:37.083689 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2493 06:53:37.089976 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2494 06:53:37.093391 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2495 06:53:37.097010 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2496 06:53:37.100311 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2497 06:53:37.100406
2498 06:53:37.103223 CA PerBit enable=1, Macro0, CA PI delay=32
2499 06:53:37.103303
2500 06:53:37.106644 [CBTSetCACLKResult] CA Dly = 32
2501 06:53:37.106725 CS Dly: 6 (0~38)
2502 06:53:37.106789
2503 06:53:37.110134 ----->DramcWriteLeveling(PI) begin...
2504 06:53:37.113553 ==
2505 06:53:37.113633 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 06:53:37.120441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 06:53:37.120522 ==
2508 06:53:37.123829 Write leveling (Byte 0): 33 => 33
2509 06:53:37.127275 Write leveling (Byte 1): 28 => 28
2510 06:53:37.127355 DramcWriteLeveling(PI) end<-----
2511 06:53:37.130068
2512 06:53:37.130157 ==
2513 06:53:37.133329 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 06:53:37.136617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 06:53:37.136699 ==
2516 06:53:37.140501 [Gating] SW mode calibration
2517 06:53:37.147266 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2518 06:53:37.149972 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2519 06:53:37.156759 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2520 06:53:37.160166 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2521 06:53:37.163502 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 06:53:37.170461 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 06:53:37.173607 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 06:53:37.176869 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 06:53:37.183794 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2526 06:53:37.187000 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2527 06:53:37.190246 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
2528 06:53:37.197063 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 06:53:37.200429 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 06:53:37.203471 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 06:53:37.207298 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 06:53:37.213744 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 06:53:37.217003 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2534 06:53:37.220476 1 0 28 | B1->B0 | 2929 4444 | 0 0 | (0 0) (0 0)
2535 06:53:37.227287 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2536 06:53:37.230824 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 06:53:37.234193 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 06:53:37.240315 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 06:53:37.243689 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 06:53:37.247063 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 06:53:37.253642 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 06:53:37.257143 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2543 06:53:37.260660 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 06:53:37.267565 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 06:53:37.270364 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 06:53:37.273852 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 06:53:37.277193 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 06:53:37.284144 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 06:53:37.287585 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 06:53:37.291029 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 06:53:37.297443 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 06:53:37.300658 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 06:53:37.304105 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 06:53:37.310721 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 06:53:37.314134 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 06:53:37.317482 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 06:53:37.324114 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 06:53:37.327558 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2559 06:53:37.330581 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 06:53:37.334154 Total UI for P1: 0, mck2ui 16
2561 06:53:37.337631 best dqsien dly found for B0: ( 1, 3, 28)
2562 06:53:37.341031 Total UI for P1: 0, mck2ui 16
2563 06:53:37.344522 best dqsien dly found for B1: ( 1, 3, 28)
2564 06:53:37.347765 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2565 06:53:37.351182 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2566 06:53:37.351262
2567 06:53:37.353959 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2568 06:53:37.360508 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2569 06:53:37.360587 [Gating] SW calibration Done
2570 06:53:37.360650 ==
2571 06:53:37.364196 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 06:53:37.370788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 06:53:37.370868 ==
2574 06:53:37.370930 RX Vref Scan: 0
2575 06:53:37.370988
2576 06:53:37.374129 RX Vref 0 -> 0, step: 1
2577 06:53:37.374208
2578 06:53:37.377703 RX Delay -40 -> 252, step: 8
2579 06:53:37.381232 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2580 06:53:37.384146 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2581 06:53:37.387376 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2582 06:53:37.394299 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2583 06:53:37.397787 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2584 06:53:37.401186 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2585 06:53:37.404596 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2586 06:53:37.407355 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2587 06:53:37.410838 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2588 06:53:37.417791 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2589 06:53:37.420738 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2590 06:53:37.424406 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2591 06:53:37.427556 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2592 06:53:37.431100 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2593 06:53:37.437515 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2594 06:53:37.440843 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2595 06:53:37.440923 ==
2596 06:53:37.444526 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 06:53:37.447440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 06:53:37.447520 ==
2599 06:53:37.451016 DQS Delay:
2600 06:53:37.451096 DQS0 = 0, DQS1 = 0
2601 06:53:37.451160 DQM Delay:
2602 06:53:37.454640 DQM0 = 121, DQM1 = 113
2603 06:53:37.454803 DQ Delay:
2604 06:53:37.457915 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2605 06:53:37.461328 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2606 06:53:37.464851 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2607 06:53:37.471452 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2608 06:53:37.471530
2609 06:53:37.471592
2610 06:53:37.471649 ==
2611 06:53:37.474617 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 06:53:37.478364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 06:53:37.478443 ==
2614 06:53:37.478505
2615 06:53:37.478562
2616 06:53:37.481127 TX Vref Scan disable
2617 06:53:37.481211 == TX Byte 0 ==
2618 06:53:37.487788 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2619 06:53:37.491189 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2620 06:53:37.491268 == TX Byte 1 ==
2621 06:53:37.498122 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2622 06:53:37.501580 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2623 06:53:37.501659 ==
2624 06:53:37.504293 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 06:53:37.507717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 06:53:37.507805 ==
2627 06:53:37.521014 TX Vref=22, minBit 4, minWin=24, winSum=406
2628 06:53:37.523722 TX Vref=24, minBit 0, minWin=25, winSum=415
2629 06:53:37.527076 TX Vref=26, minBit 0, minWin=26, winSum=419
2630 06:53:37.530405 TX Vref=28, minBit 0, minWin=26, winSum=423
2631 06:53:37.534082 TX Vref=30, minBit 0, minWin=26, winSum=424
2632 06:53:37.540212 TX Vref=32, minBit 4, minWin=25, winSum=420
2633 06:53:37.544088 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
2634 06:53:37.544167
2635 06:53:37.547306 Final TX Range 1 Vref 30
2636 06:53:37.547385
2637 06:53:37.547449 ==
2638 06:53:37.550752 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 06:53:37.553969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 06:53:37.554048 ==
2641 06:53:37.557171
2642 06:53:37.557249
2643 06:53:37.557311 TX Vref Scan disable
2644 06:53:37.560464 == TX Byte 0 ==
2645 06:53:37.563701 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2646 06:53:37.570535 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2647 06:53:37.570615 == TX Byte 1 ==
2648 06:53:37.573588 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2649 06:53:37.580193 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2650 06:53:37.580296
2651 06:53:37.580374 [DATLAT]
2652 06:53:37.580434 Freq=1200, CH0 RK0
2653 06:53:37.580490
2654 06:53:37.583452 DATLAT Default: 0xd
2655 06:53:37.583531 0, 0xFFFF, sum = 0
2656 06:53:37.586723 1, 0xFFFF, sum = 0
2657 06:53:37.589945 2, 0xFFFF, sum = 0
2658 06:53:37.590025 3, 0xFFFF, sum = 0
2659 06:53:37.593379 4, 0xFFFF, sum = 0
2660 06:53:37.593459 5, 0xFFFF, sum = 0
2661 06:53:37.596874 6, 0xFFFF, sum = 0
2662 06:53:37.596956 7, 0xFFFF, sum = 0
2663 06:53:37.600438 8, 0xFFFF, sum = 0
2664 06:53:37.600518 9, 0xFFFF, sum = 0
2665 06:53:37.603857 10, 0xFFFF, sum = 0
2666 06:53:37.603929 11, 0xFFFF, sum = 0
2667 06:53:37.607237 12, 0x0, sum = 1
2668 06:53:37.607306 13, 0x0, sum = 2
2669 06:53:37.610039 14, 0x0, sum = 3
2670 06:53:37.610108 15, 0x0, sum = 4
2671 06:53:37.610168 best_step = 13
2672 06:53:37.613408
2673 06:53:37.613502 ==
2674 06:53:37.616949 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 06:53:37.620335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 06:53:37.620418 ==
2677 06:53:37.620476 RX Vref Scan: 1
2678 06:53:37.620531
2679 06:53:37.623751 Set Vref Range= 32 -> 127
2680 06:53:37.623856
2681 06:53:37.627168 RX Vref 32 -> 127, step: 1
2682 06:53:37.627272
2683 06:53:37.630648 RX Delay -13 -> 252, step: 4
2684 06:53:37.630717
2685 06:53:37.633428 Set Vref, RX VrefLevel [Byte0]: 32
2686 06:53:37.636940 [Byte1]: 32
2687 06:53:37.637018
2688 06:53:37.640231 Set Vref, RX VrefLevel [Byte0]: 33
2689 06:53:37.643684 [Byte1]: 33
2690 06:53:37.643779
2691 06:53:37.646925 Set Vref, RX VrefLevel [Byte0]: 34
2692 06:53:37.650233 [Byte1]: 34
2693 06:53:37.654915
2694 06:53:37.654995 Set Vref, RX VrefLevel [Byte0]: 35
2695 06:53:37.658322 [Byte1]: 35
2696 06:53:37.662574
2697 06:53:37.662671 Set Vref, RX VrefLevel [Byte0]: 36
2698 06:53:37.666460 [Byte1]: 36
2699 06:53:37.670587
2700 06:53:37.670666 Set Vref, RX VrefLevel [Byte0]: 37
2701 06:53:37.673808 [Byte1]: 37
2702 06:53:37.678355
2703 06:53:37.678436 Set Vref, RX VrefLevel [Byte0]: 38
2704 06:53:37.681547 [Byte1]: 38
2705 06:53:37.686473
2706 06:53:37.686553 Set Vref, RX VrefLevel [Byte0]: 39
2707 06:53:37.689448 [Byte1]: 39
2708 06:53:37.694160
2709 06:53:37.694240 Set Vref, RX VrefLevel [Byte0]: 40
2710 06:53:37.697178 [Byte1]: 40
2711 06:53:37.702063
2712 06:53:37.702143 Set Vref, RX VrefLevel [Byte0]: 41
2713 06:53:37.705164 [Byte1]: 41
2714 06:53:37.709917
2715 06:53:37.709997 Set Vref, RX VrefLevel [Byte0]: 42
2716 06:53:37.713348 [Byte1]: 42
2717 06:53:37.717597
2718 06:53:37.717677 Set Vref, RX VrefLevel [Byte0]: 43
2719 06:53:37.721003 [Byte1]: 43
2720 06:53:37.725813
2721 06:53:37.725891 Set Vref, RX VrefLevel [Byte0]: 44
2722 06:53:37.729320 [Byte1]: 44
2723 06:53:37.733618
2724 06:53:37.733700 Set Vref, RX VrefLevel [Byte0]: 45
2725 06:53:37.737119 [Byte1]: 45
2726 06:53:37.741323
2727 06:53:37.741400 Set Vref, RX VrefLevel [Byte0]: 46
2728 06:53:37.744722 [Byte1]: 46
2729 06:53:37.749436
2730 06:53:37.749514 Set Vref, RX VrefLevel [Byte0]: 47
2731 06:53:37.752775 [Byte1]: 47
2732 06:53:37.757519
2733 06:53:37.757597 Set Vref, RX VrefLevel [Byte0]: 48
2734 06:53:37.760896 [Byte1]: 48
2735 06:53:37.765121
2736 06:53:37.765200 Set Vref, RX VrefLevel [Byte0]: 49
2737 06:53:37.768628 [Byte1]: 49
2738 06:53:37.773063
2739 06:53:37.773174 Set Vref, RX VrefLevel [Byte0]: 50
2740 06:53:37.776308 [Byte1]: 50
2741 06:53:37.780718
2742 06:53:37.780797 Set Vref, RX VrefLevel [Byte0]: 51
2743 06:53:37.784228 [Byte1]: 51
2744 06:53:37.788549
2745 06:53:37.788628 Set Vref, RX VrefLevel [Byte0]: 52
2746 06:53:37.791949 [Byte1]: 52
2747 06:53:37.796638
2748 06:53:37.796717 Set Vref, RX VrefLevel [Byte0]: 53
2749 06:53:37.799957 [Byte1]: 53
2750 06:53:37.804937
2751 06:53:37.805018 Set Vref, RX VrefLevel [Byte0]: 54
2752 06:53:37.807964 [Byte1]: 54
2753 06:53:37.812622
2754 06:53:37.812700 Set Vref, RX VrefLevel [Byte0]: 55
2755 06:53:37.816149 [Byte1]: 55
2756 06:53:37.820205
2757 06:53:37.820306 Set Vref, RX VrefLevel [Byte0]: 56
2758 06:53:37.823983 [Byte1]: 56
2759 06:53:37.828038
2760 06:53:37.828117 Set Vref, RX VrefLevel [Byte0]: 57
2761 06:53:37.831592 [Byte1]: 57
2762 06:53:37.836245
2763 06:53:37.836363 Set Vref, RX VrefLevel [Byte0]: 58
2764 06:53:37.839673 [Byte1]: 58
2765 06:53:37.843766
2766 06:53:37.843844 Set Vref, RX VrefLevel [Byte0]: 59
2767 06:53:37.847333 [Byte1]: 59
2768 06:53:37.852077
2769 06:53:37.852155 Set Vref, RX VrefLevel [Byte0]: 60
2770 06:53:37.855582 [Byte1]: 60
2771 06:53:37.859600
2772 06:53:37.859681 Set Vref, RX VrefLevel [Byte0]: 61
2773 06:53:37.863025 [Byte1]: 61
2774 06:53:37.867785
2775 06:53:37.867865 Set Vref, RX VrefLevel [Byte0]: 62
2776 06:53:37.871265 [Byte1]: 62
2777 06:53:37.875471
2778 06:53:37.875552 Set Vref, RX VrefLevel [Byte0]: 63
2779 06:53:37.878912 [Byte1]: 63
2780 06:53:37.883564
2781 06:53:37.883643 Set Vref, RX VrefLevel [Byte0]: 64
2782 06:53:37.887063 [Byte1]: 64
2783 06:53:37.891683
2784 06:53:37.891763 Set Vref, RX VrefLevel [Byte0]: 65
2785 06:53:37.894364 [Byte1]: 65
2786 06:53:37.899259
2787 06:53:37.899342 Set Vref, RX VrefLevel [Byte0]: 66
2788 06:53:37.902349 [Byte1]: 66
2789 06:53:37.907166
2790 06:53:37.907297 Set Vref, RX VrefLevel [Byte0]: 67
2791 06:53:37.910394 [Byte1]: 67
2792 06:53:37.915151
2793 06:53:37.915238 Set Vref, RX VrefLevel [Byte0]: 68
2794 06:53:37.918304 [Byte1]: 68
2795 06:53:37.922783
2796 06:53:37.922863 Set Vref, RX VrefLevel [Byte0]: 69
2797 06:53:37.926403 [Byte1]: 69
2798 06:53:37.930655
2799 06:53:37.930736 Final RX Vref Byte 0 = 58 to rank0
2800 06:53:37.934077 Final RX Vref Byte 1 = 48 to rank0
2801 06:53:37.937512 Final RX Vref Byte 0 = 58 to rank1
2802 06:53:37.940776 Final RX Vref Byte 1 = 48 to rank1==
2803 06:53:37.944243 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 06:53:37.947818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 06:53:37.951265 ==
2806 06:53:37.951348 DQS Delay:
2807 06:53:37.951412 DQS0 = 0, DQS1 = 0
2808 06:53:37.954026 DQM Delay:
2809 06:53:37.954107 DQM0 = 120, DQM1 = 112
2810 06:53:37.957433 DQ Delay:
2811 06:53:37.960912 DQ0 =118, DQ1 =122, DQ2 =120, DQ3 =118
2812 06:53:37.964212 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2813 06:53:37.967636 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2814 06:53:37.971278 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2815 06:53:37.971359
2816 06:53:37.971422
2817 06:53:37.977559 [DQSOSCAuto] RK0, (LSB)MR18= 0x1710, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2818 06:53:37.981027 CH0 RK0: MR19=404, MR18=1710
2819 06:53:37.987920 CH0_RK0: MR19=0x404, MR18=0x1710, DQSOSC=401, MR23=63, INC=40, DEC=27
2820 06:53:37.988001
2821 06:53:37.991374 ----->DramcWriteLeveling(PI) begin...
2822 06:53:37.991457 ==
2823 06:53:37.994164 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 06:53:37.997691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 06:53:37.997772 ==
2826 06:53:38.000987 Write leveling (Byte 0): 36 => 36
2827 06:53:38.004433 Write leveling (Byte 1): 29 => 29
2828 06:53:38.007761 DramcWriteLeveling(PI) end<-----
2829 06:53:38.007837
2830 06:53:38.007898 ==
2831 06:53:38.011057 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 06:53:38.015112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 06:53:38.018095 ==
2834 06:53:38.018184 [Gating] SW mode calibration
2835 06:53:38.027880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 06:53:38.031050 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 06:53:38.034475 0 15 0 | B1->B0 | 3131 2a2a | 1 1 | (0 0) (0 0)
2838 06:53:38.041420 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 06:53:38.044106 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 06:53:38.047812 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 06:53:38.054273 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 06:53:38.057940 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 06:53:38.061136 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2844 06:53:38.067654 0 15 28 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
2845 06:53:38.071414 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2846 06:53:38.074175 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 06:53:38.081255 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 06:53:38.084774 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 06:53:38.088065 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 06:53:38.094206 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 06:53:38.097700 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2852 06:53:38.101084 1 0 28 | B1->B0 | 3f3f 3838 | 0 0 | (1 1) (0 0)
2853 06:53:38.104434 1 1 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
2854 06:53:38.111051 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 06:53:38.114444 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 06:53:38.118019 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 06:53:38.124753 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 06:53:38.127526 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 06:53:38.131003 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 06:53:38.137920 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 06:53:38.141206 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2862 06:53:38.144597 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 06:53:38.151137 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 06:53:38.154625 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 06:53:38.157889 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 06:53:38.164479 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 06:53:38.167737 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 06:53:38.171278 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 06:53:38.177990 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 06:53:38.180900 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 06:53:38.184507 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 06:53:38.190750 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 06:53:38.194188 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 06:53:38.197473 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 06:53:38.204544 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2876 06:53:38.207942 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2877 06:53:38.211200 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 06:53:38.214518 Total UI for P1: 0, mck2ui 16
2879 06:53:38.217768 best dqsien dly found for B0: ( 1, 3, 28)
2880 06:53:38.221177 Total UI for P1: 0, mck2ui 16
2881 06:53:38.224015 best dqsien dly found for B1: ( 1, 3, 26)
2882 06:53:38.227328 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2883 06:53:38.230875 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2884 06:53:38.230954
2885 06:53:38.234322 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2886 06:53:38.237859 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2887 06:53:38.241358 [Gating] SW calibration Done
2888 06:53:38.241483 ==
2889 06:53:38.244783 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 06:53:38.251021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 06:53:38.251120 ==
2892 06:53:38.251198 RX Vref Scan: 0
2893 06:53:38.251269
2894 06:53:38.254523 RX Vref 0 -> 0, step: 1
2895 06:53:38.254631
2896 06:53:38.258157 RX Delay -40 -> 252, step: 8
2897 06:53:38.261140 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2898 06:53:38.264597 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2899 06:53:38.268182 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2900 06:53:38.271100 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2901 06:53:38.278280 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2902 06:53:38.281712 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2903 06:53:38.285119 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2904 06:53:38.287770 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2905 06:53:38.291331 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2906 06:53:38.295153 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2907 06:53:38.301755 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2908 06:53:38.305070 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2909 06:53:38.308196 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2910 06:53:38.310967 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2911 06:53:38.317672 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2912 06:53:38.321017 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2913 06:53:38.321096 ==
2914 06:53:38.324537 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 06:53:38.328012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 06:53:38.328092 ==
2917 06:53:38.331311 DQS Delay:
2918 06:53:38.331390 DQS0 = 0, DQS1 = 0
2919 06:53:38.331452 DQM Delay:
2920 06:53:38.334688 DQM0 = 122, DQM1 = 112
2921 06:53:38.334767 DQ Delay:
2922 06:53:38.338109 DQ0 =119, DQ1 =123, DQ2 =123, DQ3 =119
2923 06:53:38.341707 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2924 06:53:38.344406 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2925 06:53:38.347840 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2926 06:53:38.351337
2927 06:53:38.351415
2928 06:53:38.351476 ==
2929 06:53:38.354761 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 06:53:38.358310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 06:53:38.358390 ==
2932 06:53:38.358451
2933 06:53:38.358509
2934 06:53:38.361128 TX Vref Scan disable
2935 06:53:38.361207 == TX Byte 0 ==
2936 06:53:38.367989 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2937 06:53:38.371412 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2938 06:53:38.371490 == TX Byte 1 ==
2939 06:53:38.377903 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2940 06:53:38.381657 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2941 06:53:38.381739 ==
2942 06:53:38.384705 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 06:53:38.388013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 06:53:38.388110 ==
2945 06:53:38.401184 TX Vref=22, minBit 5, minWin=25, winSum=418
2946 06:53:38.404427 TX Vref=24, minBit 3, minWin=25, winSum=417
2947 06:53:38.407509 TX Vref=26, minBit 10, minWin=25, winSum=419
2948 06:53:38.411161 TX Vref=28, minBit 5, minWin=25, winSum=426
2949 06:53:38.414178 TX Vref=30, minBit 12, minWin=25, winSum=422
2950 06:53:38.420749 TX Vref=32, minBit 10, minWin=25, winSum=426
2951 06:53:38.423987 [TxChooseVref] Worse bit 5, Min win 25, Win sum 426, Final Vref 28
2952 06:53:38.424073
2953 06:53:38.427406 Final TX Range 1 Vref 28
2954 06:53:38.427511
2955 06:53:38.427597 ==
2956 06:53:38.431133 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 06:53:38.434473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 06:53:38.437835 ==
2959 06:53:38.437911
2960 06:53:38.437972
2961 06:53:38.438030 TX Vref Scan disable
2962 06:53:38.441250 == TX Byte 0 ==
2963 06:53:38.444079 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2964 06:53:38.450996 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2965 06:53:38.451105 == TX Byte 1 ==
2966 06:53:38.454422 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2967 06:53:38.460580 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2968 06:53:38.460696
2969 06:53:38.460761 [DATLAT]
2970 06:53:38.460819 Freq=1200, CH0 RK1
2971 06:53:38.460875
2972 06:53:38.464018 DATLAT Default: 0xd
2973 06:53:38.464096 0, 0xFFFF, sum = 0
2974 06:53:38.467550 1, 0xFFFF, sum = 0
2975 06:53:38.467630 2, 0xFFFF, sum = 0
2976 06:53:38.471062 3, 0xFFFF, sum = 0
2977 06:53:38.474395 4, 0xFFFF, sum = 0
2978 06:53:38.474475 5, 0xFFFF, sum = 0
2979 06:53:38.477793 6, 0xFFFF, sum = 0
2980 06:53:38.477873 7, 0xFFFF, sum = 0
2981 06:53:38.481249 8, 0xFFFF, sum = 0
2982 06:53:38.481329 9, 0xFFFF, sum = 0
2983 06:53:38.483976 10, 0xFFFF, sum = 0
2984 06:53:38.484056 11, 0xFFFF, sum = 0
2985 06:53:38.487382 12, 0x0, sum = 1
2986 06:53:38.487462 13, 0x0, sum = 2
2987 06:53:38.490776 14, 0x0, sum = 3
2988 06:53:38.490856 15, 0x0, sum = 4
2989 06:53:38.490920 best_step = 13
2990 06:53:38.494241
2991 06:53:38.494320 ==
2992 06:53:38.497617 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 06:53:38.500802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 06:53:38.500882 ==
2995 06:53:38.500944 RX Vref Scan: 0
2996 06:53:38.501002
2997 06:53:38.503967 RX Vref 0 -> 0, step: 1
2998 06:53:38.504045
2999 06:53:38.507733 RX Delay -13 -> 252, step: 4
3000 06:53:38.510630 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3001 06:53:38.517806 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3002 06:53:38.520655 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3003 06:53:38.524222 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3004 06:53:38.527449 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3005 06:53:38.531283 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3006 06:53:38.534099 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3007 06:53:38.541050 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3008 06:53:38.544264 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3009 06:53:38.547709 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3010 06:53:38.550995 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3011 06:53:38.554617 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3012 06:53:38.561397 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3013 06:53:38.564209 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3014 06:53:38.567784 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3015 06:53:38.571329 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3016 06:53:38.571411 ==
3017 06:53:38.574861 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 06:53:38.581087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 06:53:38.581166 ==
3020 06:53:38.581229 DQS Delay:
3021 06:53:38.581287 DQS0 = 0, DQS1 = 0
3022 06:53:38.584605 DQM Delay:
3023 06:53:38.584684 DQM0 = 120, DQM1 = 110
3024 06:53:38.587756 DQ Delay:
3025 06:53:38.591219 DQ0 =120, DQ1 =120, DQ2 =116, DQ3 =118
3026 06:53:38.594743 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3027 06:53:38.598173 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =100
3028 06:53:38.601657 DQ12 =116, DQ13 =116, DQ14 =122, DQ15 =118
3029 06:53:38.601736
3030 06:53:38.601797
3031 06:53:38.607915 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3032 06:53:38.611280 CH0 RK1: MR19=403, MR18=10F1
3033 06:53:38.618028 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3034 06:53:38.621441 [RxdqsGatingPostProcess] freq 1200
3035 06:53:38.628205 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3036 06:53:38.631379 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 06:53:38.631458 best DQS1 dly(2T, 0.5T) = (0, 11)
3038 06:53:38.634554 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 06:53:38.638265 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3040 06:53:38.641195 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 06:53:38.644437 best DQS1 dly(2T, 0.5T) = (0, 11)
3042 06:53:38.648097 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 06:53:38.651502 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3044 06:53:38.654734 Pre-setting of DQS Precalculation
3045 06:53:38.661737 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3046 06:53:38.661817 ==
3047 06:53:38.665135 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 06:53:38.668200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 06:53:38.668280 ==
3050 06:53:38.674915 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3051 06:53:38.678104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3052 06:53:38.687769 [CA 0] Center 37 (7~67) winsize 61
3053 06:53:38.690589 [CA 1] Center 37 (7~68) winsize 62
3054 06:53:38.693935 [CA 2] Center 35 (5~65) winsize 61
3055 06:53:38.697365 [CA 3] Center 34 (5~64) winsize 60
3056 06:53:38.700790 [CA 4] Center 34 (4~64) winsize 61
3057 06:53:38.704090 [CA 5] Center 33 (3~63) winsize 61
3058 06:53:38.704169
3059 06:53:38.707512 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3060 06:53:38.707592
3061 06:53:38.711106 [CATrainingPosCal] consider 1 rank data
3062 06:53:38.714494 u2DelayCellTimex100 = 270/100 ps
3063 06:53:38.717769 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3064 06:53:38.721103 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 06:53:38.727816 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3066 06:53:38.731231 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3067 06:53:38.734077 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3068 06:53:38.737546 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3069 06:53:38.737626
3070 06:53:38.740932 CA PerBit enable=1, Macro0, CA PI delay=33
3071 06:53:38.741012
3072 06:53:38.744369 [CBTSetCACLKResult] CA Dly = 33
3073 06:53:38.744475 CS Dly: 7 (0~38)
3074 06:53:38.744542 ==
3075 06:53:38.747725 Dram Type= 6, Freq= 0, CH_1, rank 1
3076 06:53:38.754778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 06:53:38.754858 ==
3078 06:53:38.757724 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 06:53:38.764443 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3080 06:53:38.773493 [CA 0] Center 37 (7~68) winsize 62
3081 06:53:38.776670 [CA 1] Center 37 (7~68) winsize 62
3082 06:53:38.779649 [CA 2] Center 35 (5~65) winsize 61
3083 06:53:38.783353 [CA 3] Center 34 (4~65) winsize 62
3084 06:53:38.786430 [CA 4] Center 34 (4~65) winsize 62
3085 06:53:38.789704 [CA 5] Center 34 (4~64) winsize 61
3086 06:53:38.789783
3087 06:53:38.792956 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3088 06:53:38.793035
3089 06:53:38.796266 [CATrainingPosCal] consider 2 rank data
3090 06:53:38.799607 u2DelayCellTimex100 = 270/100 ps
3091 06:53:38.803550 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3092 06:53:38.806294 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 06:53:38.813329 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3094 06:53:38.816752 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3095 06:53:38.819535 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 06:53:38.822993 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3097 06:53:38.823072
3098 06:53:38.826798 CA PerBit enable=1, Macro0, CA PI delay=33
3099 06:53:38.826878
3100 06:53:38.830218 [CBTSetCACLKResult] CA Dly = 33
3101 06:53:38.830297 CS Dly: 8 (0~40)
3102 06:53:38.830360
3103 06:53:38.833047 ----->DramcWriteLeveling(PI) begin...
3104 06:53:38.836560 ==
3105 06:53:38.836639 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 06:53:38.843461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 06:53:38.843540 ==
3108 06:53:38.846927 Write leveling (Byte 0): 26 => 26
3109 06:53:38.850385 Write leveling (Byte 1): 27 => 27
3110 06:53:38.850464 DramcWriteLeveling(PI) end<-----
3111 06:53:38.850527
3112 06:53:38.853107 ==
3113 06:53:38.856605 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 06:53:38.860078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 06:53:38.860158 ==
3116 06:53:38.863495 [Gating] SW mode calibration
3117 06:53:38.870350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3118 06:53:38.873614 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3119 06:53:38.880409 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 06:53:38.883412 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 06:53:38.886535 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 06:53:38.893492 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 06:53:38.896730 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 06:53:38.900242 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 06:53:38.907115 0 15 24 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 0)
3126 06:53:38.910053 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 06:53:38.913771 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 06:53:38.916787 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 06:53:38.923769 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 06:53:38.926930 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 06:53:38.930269 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 06:53:38.937288 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 06:53:38.940677 1 0 24 | B1->B0 | 3232 3f3f | 1 0 | (0 0) (1 1)
3134 06:53:38.943458 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 06:53:38.950538 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 06:53:38.954140 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 06:53:38.957464 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 06:53:38.963682 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 06:53:38.967000 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 06:53:38.970536 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 06:53:38.977384 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3142 06:53:38.980740 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 06:53:38.984188 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 06:53:38.990980 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 06:53:38.993605 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 06:53:38.997075 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 06:53:39.000972 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 06:53:39.007199 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 06:53:39.010878 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 06:53:39.013751 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 06:53:39.020817 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 06:53:39.024171 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 06:53:39.027544 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 06:53:39.033968 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 06:53:39.037467 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 06:53:39.040893 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 06:53:39.047680 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3158 06:53:39.051041 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3159 06:53:39.054378 Total UI for P1: 0, mck2ui 16
3160 06:53:39.057956 best dqsien dly found for B1: ( 1, 3, 24)
3161 06:53:39.060712 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 06:53:39.064207 Total UI for P1: 0, mck2ui 16
3163 06:53:39.067720 best dqsien dly found for B0: ( 1, 3, 26)
3164 06:53:39.071072 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3165 06:53:39.074428 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3166 06:53:39.074507
3167 06:53:39.077955 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3168 06:53:39.081206 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3169 06:53:39.084075 [Gating] SW calibration Done
3170 06:53:39.084180 ==
3171 06:53:39.087440 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 06:53:39.094807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 06:53:39.094888 ==
3174 06:53:39.094950 RX Vref Scan: 0
3175 06:53:39.095008
3176 06:53:39.097579 RX Vref 0 -> 0, step: 1
3177 06:53:39.097658
3178 06:53:39.100987 RX Delay -40 -> 252, step: 8
3179 06:53:39.104438 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3180 06:53:39.107859 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3181 06:53:39.111123 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3182 06:53:39.114462 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3183 06:53:39.121249 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3184 06:53:39.124499 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3185 06:53:39.128189 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3186 06:53:39.131248 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3187 06:53:39.134761 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3188 06:53:39.141255 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3189 06:53:39.144780 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3190 06:53:39.148163 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3191 06:53:39.151354 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3192 06:53:39.154480 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3193 06:53:39.161233 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3194 06:53:39.164217 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3195 06:53:39.164357 ==
3196 06:53:39.168120 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 06:53:39.170928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 06:53:39.171007 ==
3199 06:53:39.171071 DQS Delay:
3200 06:53:39.174715 DQS0 = 0, DQS1 = 0
3201 06:53:39.174794 DQM Delay:
3202 06:53:39.178212 DQM0 = 120, DQM1 = 116
3203 06:53:39.178292 DQ Delay:
3204 06:53:39.181637 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3205 06:53:39.184385 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3206 06:53:39.187909 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3207 06:53:39.191275 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3208 06:53:39.194864
3209 06:53:39.194942
3210 06:53:39.195004 ==
3211 06:53:39.198258 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 06:53:39.201275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 06:53:39.201355 ==
3214 06:53:39.201418
3215 06:53:39.201477
3216 06:53:39.204764 TX Vref Scan disable
3217 06:53:39.204843 == TX Byte 0 ==
3218 06:53:39.211048 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3219 06:53:39.214416 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3220 06:53:39.214495 == TX Byte 1 ==
3221 06:53:39.221097 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3222 06:53:39.224807 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3223 06:53:39.224888 ==
3224 06:53:39.227771 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 06:53:39.231467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 06:53:39.231579 ==
3227 06:53:39.243144 TX Vref=22, minBit 11, minWin=24, winSum=409
3228 06:53:39.246425 TX Vref=24, minBit 9, minWin=25, winSum=418
3229 06:53:39.249814 TX Vref=26, minBit 9, minWin=25, winSum=424
3230 06:53:39.253448 TX Vref=28, minBit 9, minWin=25, winSum=425
3231 06:53:39.256301 TX Vref=30, minBit 9, minWin=26, winSum=432
3232 06:53:39.263520 TX Vref=32, minBit 10, minWin=25, winSum=431
3233 06:53:39.267011 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3234 06:53:39.267093
3235 06:53:39.269868 Final TX Range 1 Vref 30
3236 06:53:39.269949
3237 06:53:39.270012 ==
3238 06:53:39.273397 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 06:53:39.276616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 06:53:39.276696 ==
3241 06:53:39.276760
3242 06:53:39.280372
3243 06:53:39.280453 TX Vref Scan disable
3244 06:53:39.283398 == TX Byte 0 ==
3245 06:53:39.286777 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3246 06:53:39.290224 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3247 06:53:39.293554 == TX Byte 1 ==
3248 06:53:39.296774 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3249 06:53:39.300220 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3250 06:53:39.300337
3251 06:53:39.303674 [DATLAT]
3252 06:53:39.303754 Freq=1200, CH1 RK0
3253 06:53:39.303817
3254 06:53:39.306867 DATLAT Default: 0xd
3255 06:53:39.306948 0, 0xFFFF, sum = 0
3256 06:53:39.310333 1, 0xFFFF, sum = 0
3257 06:53:39.310414 2, 0xFFFF, sum = 0
3258 06:53:39.313585 3, 0xFFFF, sum = 0
3259 06:53:39.313666 4, 0xFFFF, sum = 0
3260 06:53:39.317166 5, 0xFFFF, sum = 0
3261 06:53:39.317247 6, 0xFFFF, sum = 0
3262 06:53:39.319914 7, 0xFFFF, sum = 0
3263 06:53:39.319996 8, 0xFFFF, sum = 0
3264 06:53:39.323280 9, 0xFFFF, sum = 0
3265 06:53:39.326520 10, 0xFFFF, sum = 0
3266 06:53:39.326602 11, 0xFFFF, sum = 0
3267 06:53:39.329963 12, 0x0, sum = 1
3268 06:53:39.330046 13, 0x0, sum = 2
3269 06:53:39.330112 14, 0x0, sum = 3
3270 06:53:39.333437 15, 0x0, sum = 4
3271 06:53:39.333521 best_step = 13
3272 06:53:39.333586
3273 06:53:39.333646 ==
3274 06:53:39.336859 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 06:53:39.343688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 06:53:39.343771 ==
3277 06:53:39.343836 RX Vref Scan: 1
3278 06:53:39.343896
3279 06:53:39.347115 Set Vref Range= 32 -> 127
3280 06:53:39.347197
3281 06:53:39.350297 RX Vref 32 -> 127, step: 1
3282 06:53:39.350380
3283 06:53:39.353589 RX Delay -5 -> 252, step: 4
3284 06:53:39.353671
3285 06:53:39.356909 Set Vref, RX VrefLevel [Byte0]: 32
3286 06:53:39.360147 [Byte1]: 32
3287 06:53:39.360229
3288 06:53:39.363742 Set Vref, RX VrefLevel [Byte0]: 33
3289 06:53:39.367259 [Byte1]: 33
3290 06:53:39.367369
3291 06:53:39.369977 Set Vref, RX VrefLevel [Byte0]: 34
3292 06:53:39.373443 [Byte1]: 34
3293 06:53:39.377609
3294 06:53:39.377697 Set Vref, RX VrefLevel [Byte0]: 35
3295 06:53:39.380238 [Byte1]: 35
3296 06:53:39.385281
3297 06:53:39.385374 Set Vref, RX VrefLevel [Byte0]: 36
3298 06:53:39.388719 [Byte1]: 36
3299 06:53:39.393248
3300 06:53:39.393329 Set Vref, RX VrefLevel [Byte0]: 37
3301 06:53:39.399522 [Byte1]: 37
3302 06:53:39.399625
3303 06:53:39.402694 Set Vref, RX VrefLevel [Byte0]: 38
3304 06:53:39.406314 [Byte1]: 38
3305 06:53:39.406396
3306 06:53:39.409346 Set Vref, RX VrefLevel [Byte0]: 39
3307 06:53:39.413018 [Byte1]: 39
3308 06:53:39.416161
3309 06:53:39.416243 Set Vref, RX VrefLevel [Byte0]: 40
3310 06:53:39.420057 [Byte1]: 40
3311 06:53:39.424200
3312 06:53:39.424274 Set Vref, RX VrefLevel [Byte0]: 41
3313 06:53:39.427675 [Byte1]: 41
3314 06:53:39.432211
3315 06:53:39.432347 Set Vref, RX VrefLevel [Byte0]: 42
3316 06:53:39.435782 [Byte1]: 42
3317 06:53:39.439857
3318 06:53:39.439936 Set Vref, RX VrefLevel [Byte0]: 43
3319 06:53:39.443190 [Byte1]: 43
3320 06:53:39.447877
3321 06:53:39.447956 Set Vref, RX VrefLevel [Byte0]: 44
3322 06:53:39.451370 [Byte1]: 44
3323 06:53:39.456077
3324 06:53:39.456156 Set Vref, RX VrefLevel [Byte0]: 45
3325 06:53:39.459139 [Byte1]: 45
3326 06:53:39.463861
3327 06:53:39.463939 Set Vref, RX VrefLevel [Byte0]: 46
3328 06:53:39.467180 [Byte1]: 46
3329 06:53:39.471877
3330 06:53:39.471956 Set Vref, RX VrefLevel [Byte0]: 47
3331 06:53:39.474606 [Byte1]: 47
3332 06:53:39.479390
3333 06:53:39.479470 Set Vref, RX VrefLevel [Byte0]: 48
3334 06:53:39.482957 [Byte1]: 48
3335 06:53:39.487018
3336 06:53:39.487097 Set Vref, RX VrefLevel [Byte0]: 49
3337 06:53:39.490512 [Byte1]: 49
3338 06:53:39.494716
3339 06:53:39.498221 Set Vref, RX VrefLevel [Byte0]: 50
3340 06:53:39.501640 [Byte1]: 50
3341 06:53:39.501720
3342 06:53:39.505078 Set Vref, RX VrefLevel [Byte0]: 51
3343 06:53:39.508344 [Byte1]: 51
3344 06:53:39.508423
3345 06:53:39.511710 Set Vref, RX VrefLevel [Byte0]: 52
3346 06:53:39.515149 [Byte1]: 52
3347 06:53:39.518374
3348 06:53:39.518453 Set Vref, RX VrefLevel [Byte0]: 53
3349 06:53:39.521565 [Byte1]: 53
3350 06:53:39.526555
3351 06:53:39.526634 Set Vref, RX VrefLevel [Byte0]: 54
3352 06:53:39.529643 [Byte1]: 54
3353 06:53:39.534222
3354 06:53:39.534301 Set Vref, RX VrefLevel [Byte0]: 55
3355 06:53:39.537495 [Byte1]: 55
3356 06:53:39.542463
3357 06:53:39.542542 Set Vref, RX VrefLevel [Byte0]: 56
3358 06:53:39.545265 [Byte1]: 56
3359 06:53:39.549827
3360 06:53:39.549907 Set Vref, RX VrefLevel [Byte0]: 57
3361 06:53:39.553281 [Byte1]: 57
3362 06:53:39.558134
3363 06:53:39.558215 Set Vref, RX VrefLevel [Byte0]: 58
3364 06:53:39.561258 [Byte1]: 58
3365 06:53:39.565551
3366 06:53:39.565633 Set Vref, RX VrefLevel [Byte0]: 59
3367 06:53:39.568913 [Byte1]: 59
3368 06:53:39.573286
3369 06:53:39.573367 Set Vref, RX VrefLevel [Byte0]: 60
3370 06:53:39.576602 [Byte1]: 60
3371 06:53:39.581442
3372 06:53:39.581522 Set Vref, RX VrefLevel [Byte0]: 61
3373 06:53:39.584760 [Byte1]: 61
3374 06:53:39.588898
3375 06:53:39.588979 Set Vref, RX VrefLevel [Byte0]: 62
3376 06:53:39.592454 [Byte1]: 62
3377 06:53:39.597210
3378 06:53:39.597291 Set Vref, RX VrefLevel [Byte0]: 63
3379 06:53:39.600729 [Byte1]: 63
3380 06:53:39.604687
3381 06:53:39.604767 Set Vref, RX VrefLevel [Byte0]: 64
3382 06:53:39.608142 [Byte1]: 64
3383 06:53:39.613037
3384 06:53:39.613118 Set Vref, RX VrefLevel [Byte0]: 65
3385 06:53:39.616346 [Byte1]: 65
3386 06:53:39.620366
3387 06:53:39.620447 Set Vref, RX VrefLevel [Byte0]: 66
3388 06:53:39.623708 [Byte1]: 66
3389 06:53:39.628579
3390 06:53:39.628659 Set Vref, RX VrefLevel [Byte0]: 67
3391 06:53:39.631886 [Byte1]: 67
3392 06:53:39.636419
3393 06:53:39.636537 Final RX Vref Byte 0 = 57 to rank0
3394 06:53:39.639764 Final RX Vref Byte 1 = 55 to rank0
3395 06:53:39.643102 Final RX Vref Byte 0 = 57 to rank1
3396 06:53:39.646182 Final RX Vref Byte 1 = 55 to rank1==
3397 06:53:39.650102 Dram Type= 6, Freq= 0, CH_1, rank 0
3398 06:53:39.653234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3399 06:53:39.656247 ==
3400 06:53:39.656371 DQS Delay:
3401 06:53:39.656435 DQS0 = 0, DQS1 = 0
3402 06:53:39.659995 DQM Delay:
3403 06:53:39.660101 DQM0 = 120, DQM1 = 117
3404 06:53:39.663151 DQ Delay:
3405 06:53:39.666437 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3406 06:53:39.670230 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3407 06:53:39.673172 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3408 06:53:39.676259 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3409 06:53:39.676382
3410 06:53:39.676448
3411 06:53:39.683319 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3412 06:53:39.686585 CH1 RK0: MR19=404, MR18=114
3413 06:53:39.693587 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3414 06:53:39.693668
3415 06:53:39.697047 ----->DramcWriteLeveling(PI) begin...
3416 06:53:39.697130 ==
3417 06:53:39.699998 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 06:53:39.703362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 06:53:39.703444 ==
3420 06:53:39.706677 Write leveling (Byte 0): 26 => 26
3421 06:53:39.710266 Write leveling (Byte 1): 27 => 27
3422 06:53:39.713751 DramcWriteLeveling(PI) end<-----
3423 06:53:39.713832
3424 06:53:39.713895 ==
3425 06:53:39.716512 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 06:53:39.719912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 06:53:39.719992 ==
3428 06:53:39.723241 [Gating] SW mode calibration
3429 06:53:39.729993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3430 06:53:39.736825 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3431 06:53:39.740109 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 06:53:39.746715 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 06:53:39.749974 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 06:53:39.753222 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 06:53:39.760098 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 06:53:39.763442 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3437 06:53:39.766605 0 15 24 | B1->B0 | 2b2b 3434 | 0 1 | (1 0) (1 0)
3438 06:53:39.773277 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3439 06:53:39.776855 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 06:53:39.779931 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 06:53:39.784001 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 06:53:39.790366 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 06:53:39.793458 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 06:53:39.797107 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3445 06:53:39.803299 1 0 24 | B1->B0 | 4040 2c2c | 1 1 | (0 0) (0 0)
3446 06:53:39.806821 1 0 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
3447 06:53:39.810223 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 06:53:39.817098 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 06:53:39.819791 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 06:53:39.823180 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 06:53:39.830394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 06:53:39.833670 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3453 06:53:39.836564 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3454 06:53:39.843533 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3455 06:53:39.847005 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 06:53:39.849752 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 06:53:39.856471 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 06:53:39.859842 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 06:53:39.863145 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 06:53:39.869456 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 06:53:39.872802 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 06:53:39.876116 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 06:53:39.883147 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 06:53:39.886403 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 06:53:39.889603 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 06:53:39.896584 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 06:53:39.899818 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 06:53:39.903135 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3469 06:53:39.906247 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3470 06:53:39.913546 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3471 06:53:39.916705 Total UI for P1: 0, mck2ui 16
3472 06:53:39.919580 best dqsien dly found for B1: ( 1, 3, 22)
3473 06:53:39.922909 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 06:53:39.926335 Total UI for P1: 0, mck2ui 16
3475 06:53:39.929882 best dqsien dly found for B0: ( 1, 3, 26)
3476 06:53:39.933235 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3477 06:53:39.936533 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3478 06:53:39.936614
3479 06:53:39.940052 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3480 06:53:39.942815 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3481 06:53:39.946216 [Gating] SW calibration Done
3482 06:53:39.946296 ==
3483 06:53:39.949838 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 06:53:39.956040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 06:53:39.956121 ==
3486 06:53:39.956185 RX Vref Scan: 0
3487 06:53:39.956243
3488 06:53:39.959329 RX Vref 0 -> 0, step: 1
3489 06:53:39.959409
3490 06:53:39.963215 RX Delay -40 -> 252, step: 8
3491 06:53:39.965819 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3492 06:53:39.969197 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3493 06:53:39.972674 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3494 06:53:39.979819 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3495 06:53:39.982457 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3496 06:53:39.986262 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3497 06:53:39.989690 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3498 06:53:39.992453 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3499 06:53:39.995741 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3500 06:53:40.002354 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3501 06:53:40.006090 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3502 06:53:40.009149 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3503 06:53:40.012702 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3504 06:53:40.018929 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3505 06:53:40.022672 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3506 06:53:40.025656 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3507 06:53:40.025737 ==
3508 06:53:40.028847 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 06:53:40.032722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 06:53:40.032803 ==
3511 06:53:40.035521 DQS Delay:
3512 06:53:40.035601 DQS0 = 0, DQS1 = 0
3513 06:53:40.038851 DQM Delay:
3514 06:53:40.038932 DQM0 = 120, DQM1 = 117
3515 06:53:40.038995 DQ Delay:
3516 06:53:40.045843 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3517 06:53:40.049390 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3518 06:53:40.052225 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3519 06:53:40.055739 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3520 06:53:40.055819
3521 06:53:40.055882
3522 06:53:40.055940 ==
3523 06:53:40.059005 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 06:53:40.061925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 06:53:40.062006 ==
3526 06:53:40.062070
3527 06:53:40.062127
3528 06:53:40.065414 TX Vref Scan disable
3529 06:53:40.068625 == TX Byte 0 ==
3530 06:53:40.071967 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3531 06:53:40.075268 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3532 06:53:40.078758 == TX Byte 1 ==
3533 06:53:40.082455 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3534 06:53:40.085327 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3535 06:53:40.085408 ==
3536 06:53:40.088651 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 06:53:40.091980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 06:53:40.095052 ==
3539 06:53:40.105198 TX Vref=22, minBit 9, minWin=25, winSum=420
3540 06:53:40.108530 TX Vref=24, minBit 1, minWin=26, winSum=428
3541 06:53:40.111980 TX Vref=26, minBit 9, minWin=26, winSum=431
3542 06:53:40.115161 TX Vref=28, minBit 9, minWin=26, winSum=434
3543 06:53:40.119195 TX Vref=30, minBit 9, minWin=26, winSum=431
3544 06:53:40.122400 TX Vref=32, minBit 9, minWin=26, winSum=430
3545 06:53:40.128620 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3546 06:53:40.128701
3547 06:53:40.132429 Final TX Range 1 Vref 28
3548 06:53:40.132510
3549 06:53:40.132572 ==
3550 06:53:40.135530 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 06:53:40.138531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 06:53:40.138612 ==
3553 06:53:40.138675
3554 06:53:40.142251
3555 06:53:40.142332 TX Vref Scan disable
3556 06:53:40.145491 == TX Byte 0 ==
3557 06:53:40.148755 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3558 06:53:40.152488 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3559 06:53:40.155279 == TX Byte 1 ==
3560 06:53:40.158678 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3561 06:53:40.162082 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3562 06:53:40.162163
3563 06:53:40.165554 [DATLAT]
3564 06:53:40.165634 Freq=1200, CH1 RK1
3565 06:53:40.165697
3566 06:53:40.169053 DATLAT Default: 0xd
3567 06:53:40.169133 0, 0xFFFF, sum = 0
3568 06:53:40.172432 1, 0xFFFF, sum = 0
3569 06:53:40.172514 2, 0xFFFF, sum = 0
3570 06:53:40.175166 3, 0xFFFF, sum = 0
3571 06:53:40.175248 4, 0xFFFF, sum = 0
3572 06:53:40.178614 5, 0xFFFF, sum = 0
3573 06:53:40.178696 6, 0xFFFF, sum = 0
3574 06:53:40.181733 7, 0xFFFF, sum = 0
3575 06:53:40.181847 8, 0xFFFF, sum = 0
3576 06:53:40.185293 9, 0xFFFF, sum = 0
3577 06:53:40.188705 10, 0xFFFF, sum = 0
3578 06:53:40.188787 11, 0xFFFF, sum = 0
3579 06:53:40.192204 12, 0x0, sum = 1
3580 06:53:40.192309 13, 0x0, sum = 2
3581 06:53:40.192394 14, 0x0, sum = 3
3582 06:53:40.195755 15, 0x0, sum = 4
3583 06:53:40.195836 best_step = 13
3584 06:53:40.195900
3585 06:53:40.195958 ==
3586 06:53:40.198509 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 06:53:40.205650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 06:53:40.205731 ==
3589 06:53:40.205834 RX Vref Scan: 0
3590 06:53:40.205893
3591 06:53:40.208827 RX Vref 0 -> 0, step: 1
3592 06:53:40.208907
3593 06:53:40.212239 RX Delay -5 -> 252, step: 4
3594 06:53:40.215587 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3595 06:53:40.218786 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3596 06:53:40.225722 iDelay=195, Bit 2, Center 112 (51 ~ 174) 124
3597 06:53:40.229056 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3598 06:53:40.232440 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3599 06:53:40.235181 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3600 06:53:40.238547 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3601 06:53:40.245421 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3602 06:53:40.248695 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3603 06:53:40.251793 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3604 06:53:40.254986 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3605 06:53:40.258442 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3606 06:53:40.265190 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3607 06:53:40.268386 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3608 06:53:40.271605 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3609 06:53:40.275602 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3610 06:53:40.275683 ==
3611 06:53:40.278192 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 06:53:40.284979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 06:53:40.285062 ==
3614 06:53:40.285125 DQS Delay:
3615 06:53:40.288931 DQS0 = 0, DQS1 = 0
3616 06:53:40.289011 DQM Delay:
3617 06:53:40.289075 DQM0 = 120, DQM1 = 118
3618 06:53:40.291576 DQ Delay:
3619 06:53:40.295011 DQ0 =122, DQ1 =116, DQ2 =112, DQ3 =116
3620 06:53:40.298559 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3621 06:53:40.302060 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3622 06:53:40.304859 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3623 06:53:40.304939
3624 06:53:40.305002
3625 06:53:40.314871 [DQSOSCAuto] RK1, (LSB)MR18= 0xfeb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3626 06:53:40.314953 CH1 RK1: MR19=403, MR18=FEB
3627 06:53:40.321409 CH1_RK1: MR19=0x403, MR18=0xFEB, DQSOSC=404, MR23=63, INC=40, DEC=26
3628 06:53:40.325168 [RxdqsGatingPostProcess] freq 1200
3629 06:53:40.331867 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3630 06:53:40.335304 best DQS0 dly(2T, 0.5T) = (0, 11)
3631 06:53:40.338127 best DQS1 dly(2T, 0.5T) = (0, 11)
3632 06:53:40.341564 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3633 06:53:40.345092 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3634 06:53:40.345172 best DQS0 dly(2T, 0.5T) = (0, 11)
3635 06:53:40.348488 best DQS1 dly(2T, 0.5T) = (0, 11)
3636 06:53:40.351911 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3637 06:53:40.354604 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3638 06:53:40.358122 Pre-setting of DQS Precalculation
3639 06:53:40.364760 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3640 06:53:40.371616 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3641 06:53:40.378283 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3642 06:53:40.378369
3643 06:53:40.378433
3644 06:53:40.381636 [Calibration Summary] 2400 Mbps
3645 06:53:40.381717 CH 0, Rank 0
3646 06:53:40.384643 SW Impedance : PASS
3647 06:53:40.387878 DUTY Scan : NO K
3648 06:53:40.387958 ZQ Calibration : PASS
3649 06:53:40.391750 Jitter Meter : NO K
3650 06:53:40.394631 CBT Training : PASS
3651 06:53:40.394712 Write leveling : PASS
3652 06:53:40.397981 RX DQS gating : PASS
3653 06:53:40.401571 RX DQ/DQS(RDDQC) : PASS
3654 06:53:40.401651 TX DQ/DQS : PASS
3655 06:53:40.405003 RX DATLAT : PASS
3656 06:53:40.408440 RX DQ/DQS(Engine): PASS
3657 06:53:40.408520 TX OE : NO K
3658 06:53:40.408583 All Pass.
3659 06:53:40.411259
3660 06:53:40.411339 CH 0, Rank 1
3661 06:53:40.414781 SW Impedance : PASS
3662 06:53:40.414861 DUTY Scan : NO K
3663 06:53:40.418099 ZQ Calibration : PASS
3664 06:53:40.418180 Jitter Meter : NO K
3665 06:53:40.421418 CBT Training : PASS
3666 06:53:40.424818 Write leveling : PASS
3667 06:53:40.424898 RX DQS gating : PASS
3668 06:53:40.428262 RX DQ/DQS(RDDQC) : PASS
3669 06:53:40.431417 TX DQ/DQS : PASS
3670 06:53:40.431498 RX DATLAT : PASS
3671 06:53:40.435172 RX DQ/DQS(Engine): PASS
3672 06:53:40.438258 TX OE : NO K
3673 06:53:40.438339 All Pass.
3674 06:53:40.438402
3675 06:53:40.438460 CH 1, Rank 0
3676 06:53:40.441454 SW Impedance : PASS
3677 06:53:40.444794 DUTY Scan : NO K
3678 06:53:40.444874 ZQ Calibration : PASS
3679 06:53:40.447953 Jitter Meter : NO K
3680 06:53:40.451475 CBT Training : PASS
3681 06:53:40.451557 Write leveling : PASS
3682 06:53:40.454963 RX DQS gating : PASS
3683 06:53:40.458439 RX DQ/DQS(RDDQC) : PASS
3684 06:53:40.458519 TX DQ/DQS : PASS
3685 06:53:40.461144 RX DATLAT : PASS
3686 06:53:40.461225 RX DQ/DQS(Engine): PASS
3687 06:53:40.464614 TX OE : NO K
3688 06:53:40.464695 All Pass.
3689 06:53:40.464777
3690 06:53:40.468020 CH 1, Rank 1
3691 06:53:40.468104 SW Impedance : PASS
3692 06:53:40.471512 DUTY Scan : NO K
3693 06:53:40.474849 ZQ Calibration : PASS
3694 06:53:40.474930 Jitter Meter : NO K
3695 06:53:40.478151 CBT Training : PASS
3696 06:53:40.481585 Write leveling : PASS
3697 06:53:40.481666 RX DQS gating : PASS
3698 06:53:40.484887 RX DQ/DQS(RDDQC) : PASS
3699 06:53:40.488418 TX DQ/DQS : PASS
3700 06:53:40.488498 RX DATLAT : PASS
3701 06:53:40.491397 RX DQ/DQS(Engine): PASS
3702 06:53:40.494805 TX OE : NO K
3703 06:53:40.494886 All Pass.
3704 06:53:40.494949
3705 06:53:40.495008 DramC Write-DBI off
3706 06:53:40.498005 PER_BANK_REFRESH: Hybrid Mode
3707 06:53:40.501410 TX_TRACKING: ON
3708 06:53:40.507781 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3709 06:53:40.511082 [FAST_K] Save calibration result to emmc
3710 06:53:40.518255 dramc_set_vcore_voltage set vcore to 650000
3711 06:53:40.518336 Read voltage for 600, 5
3712 06:53:40.521634 Vio18 = 0
3713 06:53:40.521745 Vcore = 650000
3714 06:53:40.521811 Vdram = 0
3715 06:53:40.524252 Vddq = 0
3716 06:53:40.524396 Vmddr = 0
3717 06:53:40.527917 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3718 06:53:40.534800 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3719 06:53:40.538015 MEM_TYPE=3, freq_sel=19
3720 06:53:40.538118 sv_algorithm_assistance_LP4_1600
3721 06:53:40.544644 ============ PULL DRAM RESETB DOWN ============
3722 06:53:40.548071 ========== PULL DRAM RESETB DOWN end =========
3723 06:53:40.551242 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3724 06:53:40.554463 ===================================
3725 06:53:40.558176 LPDDR4 DRAM CONFIGURATION
3726 06:53:40.561580 ===================================
3727 06:53:40.564420 EX_ROW_EN[0] = 0x0
3728 06:53:40.564502 EX_ROW_EN[1] = 0x0
3729 06:53:40.567949 LP4Y_EN = 0x0
3730 06:53:40.568061 WORK_FSP = 0x0
3731 06:53:40.571297 WL = 0x2
3732 06:53:40.571398 RL = 0x2
3733 06:53:40.574845 BL = 0x2
3734 06:53:40.574937 RPST = 0x0
3735 06:53:40.577606 RD_PRE = 0x0
3736 06:53:40.577715 WR_PRE = 0x1
3737 06:53:40.581006 WR_PST = 0x0
3738 06:53:40.581117 DBI_WR = 0x0
3739 06:53:40.584579 DBI_RD = 0x0
3740 06:53:40.584686 OTF = 0x1
3741 06:53:40.588152 ===================================
3742 06:53:40.591013 ===================================
3743 06:53:40.594485 ANA top config
3744 06:53:40.597909 ===================================
3745 06:53:40.601170 DLL_ASYNC_EN = 0
3746 06:53:40.601266 ALL_SLAVE_EN = 1
3747 06:53:40.604577 NEW_RANK_MODE = 1
3748 06:53:40.607896 DLL_IDLE_MODE = 1
3749 06:53:40.611256 LP45_APHY_COMB_EN = 1
3750 06:53:40.611337 TX_ODT_DIS = 1
3751 06:53:40.614973 NEW_8X_MODE = 1
3752 06:53:40.617617 ===================================
3753 06:53:40.621332 ===================================
3754 06:53:40.624582 data_rate = 1200
3755 06:53:40.627724 CKR = 1
3756 06:53:40.631051 DQ_P2S_RATIO = 8
3757 06:53:40.634495 ===================================
3758 06:53:40.638037 CA_P2S_RATIO = 8
3759 06:53:40.638117 DQ_CA_OPEN = 0
3760 06:53:40.641448 DQ_SEMI_OPEN = 0
3761 06:53:40.644210 CA_SEMI_OPEN = 0
3762 06:53:40.647708 CA_FULL_RATE = 0
3763 06:53:40.651095 DQ_CKDIV4_EN = 1
3764 06:53:40.654605 CA_CKDIV4_EN = 1
3765 06:53:40.654711 CA_PREDIV_EN = 0
3766 06:53:40.658043 PH8_DLY = 0
3767 06:53:40.660759 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3768 06:53:40.664132 DQ_AAMCK_DIV = 4
3769 06:53:40.667980 CA_AAMCK_DIV = 4
3770 06:53:40.671080 CA_ADMCK_DIV = 4
3771 06:53:40.671163 DQ_TRACK_CA_EN = 0
3772 06:53:40.674157 CA_PICK = 600
3773 06:53:40.677664 CA_MCKIO = 600
3774 06:53:40.681118 MCKIO_SEMI = 0
3775 06:53:40.684495 PLL_FREQ = 2288
3776 06:53:40.687309 DQ_UI_PI_RATIO = 32
3777 06:53:40.690817 CA_UI_PI_RATIO = 0
3778 06:53:40.694341 ===================================
3779 06:53:40.697193 ===================================
3780 06:53:40.697304 memory_type:LPDDR4
3781 06:53:40.700753 GP_NUM : 10
3782 06:53:40.704095 SRAM_EN : 1
3783 06:53:40.704220 MD32_EN : 0
3784 06:53:40.707400 ===================================
3785 06:53:40.710645 [ANA_INIT] >>>>>>>>>>>>>>
3786 06:53:40.714101 <<<<<< [CONFIGURE PHASE]: ANA_TX
3787 06:53:40.717430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3788 06:53:40.720208 ===================================
3789 06:53:40.723653 data_rate = 1200,PCW = 0X5800
3790 06:53:40.727252 ===================================
3791 06:53:40.730083 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3792 06:53:40.733492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3793 06:53:40.740048 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3794 06:53:40.743561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3795 06:53:40.746716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3796 06:53:40.749963 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3797 06:53:40.753190 [ANA_INIT] flow start
3798 06:53:40.756929 [ANA_INIT] PLL >>>>>>>>
3799 06:53:40.757010 [ANA_INIT] PLL <<<<<<<<
3800 06:53:40.760408 [ANA_INIT] MIDPI >>>>>>>>
3801 06:53:40.763060 [ANA_INIT] MIDPI <<<<<<<<
3802 06:53:40.766515 [ANA_INIT] DLL >>>>>>>>
3803 06:53:40.766621 [ANA_INIT] flow end
3804 06:53:40.770191 ============ LP4 DIFF to SE enter ============
3805 06:53:40.776389 ============ LP4 DIFF to SE exit ============
3806 06:53:40.776470 [ANA_INIT] <<<<<<<<<<<<<
3807 06:53:40.779698 [Flow] Enable top DCM control >>>>>
3808 06:53:40.783119 [Flow] Enable top DCM control <<<<<
3809 06:53:40.786427 Enable DLL master slave shuffle
3810 06:53:40.793172 ==============================================================
3811 06:53:40.793279 Gating Mode config
3812 06:53:40.799439 ==============================================================
3813 06:53:40.802907 Config description:
3814 06:53:40.812862 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3815 06:53:40.819787 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3816 06:53:40.823236 SELPH_MODE 0: By rank 1: By Phase
3817 06:53:40.829456 ==============================================================
3818 06:53:40.832968 GAT_TRACK_EN = 1
3819 06:53:40.836469 RX_GATING_MODE = 2
3820 06:53:40.836544 RX_GATING_TRACK_MODE = 2
3821 06:53:40.839318 SELPH_MODE = 1
3822 06:53:40.842799 PICG_EARLY_EN = 1
3823 06:53:40.846074 VALID_LAT_VALUE = 1
3824 06:53:40.853319 ==============================================================
3825 06:53:40.856274 Enter into Gating configuration >>>>
3826 06:53:40.859322 Exit from Gating configuration <<<<
3827 06:53:40.862907 Enter into DVFS_PRE_config >>>>>
3828 06:53:40.872981 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3829 06:53:40.876475 Exit from DVFS_PRE_config <<<<<
3830 06:53:40.879209 Enter into PICG configuration >>>>
3831 06:53:40.882588 Exit from PICG configuration <<<<
3832 06:53:40.886156 [RX_INPUT] configuration >>>>>
3833 06:53:40.889689 [RX_INPUT] configuration <<<<<
3834 06:53:40.892482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3835 06:53:40.899119 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3836 06:53:40.905686 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3837 06:53:40.912537 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3838 06:53:40.916095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3839 06:53:40.922300 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3840 06:53:40.925525 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3841 06:53:40.932512 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3842 06:53:40.935951 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3843 06:53:40.939678 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3844 06:53:40.942280 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3845 06:53:40.949379 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3846 06:53:40.952214 ===================================
3847 06:53:40.952340 LPDDR4 DRAM CONFIGURATION
3848 06:53:40.956213 ===================================
3849 06:53:40.959015 EX_ROW_EN[0] = 0x0
3850 06:53:40.962680 EX_ROW_EN[1] = 0x0
3851 06:53:40.962760 LP4Y_EN = 0x0
3852 06:53:40.966067 WORK_FSP = 0x0
3853 06:53:40.966147 WL = 0x2
3854 06:53:40.969373 RL = 0x2
3855 06:53:40.969453 BL = 0x2
3856 06:53:40.972525 RPST = 0x0
3857 06:53:40.972605 RD_PRE = 0x0
3858 06:53:40.975729 WR_PRE = 0x1
3859 06:53:40.975809 WR_PST = 0x0
3860 06:53:40.979344 DBI_WR = 0x0
3861 06:53:40.979424 DBI_RD = 0x0
3862 06:53:40.982585 OTF = 0x1
3863 06:53:40.986854 ===================================
3864 06:53:40.989255 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3865 06:53:40.992393 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3866 06:53:40.999223 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3867 06:53:41.002125 ===================================
3868 06:53:41.002204 LPDDR4 DRAM CONFIGURATION
3869 06:53:41.005696 ===================================
3870 06:53:41.009175 EX_ROW_EN[0] = 0x10
3871 06:53:41.012481 EX_ROW_EN[1] = 0x0
3872 06:53:41.012560 LP4Y_EN = 0x0
3873 06:53:41.015759 WORK_FSP = 0x0
3874 06:53:41.015838 WL = 0x2
3875 06:53:41.018804 RL = 0x2
3876 06:53:41.018883 BL = 0x2
3877 06:53:41.022031 RPST = 0x0
3878 06:53:41.022109 RD_PRE = 0x0
3879 06:53:41.025338 WR_PRE = 0x1
3880 06:53:41.025417 WR_PST = 0x0
3881 06:53:41.029023 DBI_WR = 0x0
3882 06:53:41.029102 DBI_RD = 0x0
3883 06:53:41.032393 OTF = 0x1
3884 06:53:41.035600 ===================================
3885 06:53:41.042046 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3886 06:53:41.045356 nWR fixed to 30
3887 06:53:41.045435 [ModeRegInit_LP4] CH0 RK0
3888 06:53:41.048755 [ModeRegInit_LP4] CH0 RK1
3889 06:53:41.052131 [ModeRegInit_LP4] CH1 RK0
3890 06:53:41.055570 [ModeRegInit_LP4] CH1 RK1
3891 06:53:41.055652 match AC timing 17
3892 06:53:41.062257 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3893 06:53:41.064936 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3894 06:53:41.068387 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3895 06:53:41.075424 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3896 06:53:41.078795 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3897 06:53:41.078876 ==
3898 06:53:41.082186 Dram Type= 6, Freq= 0, CH_0, rank 0
3899 06:53:41.085289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3900 06:53:41.085380 ==
3901 06:53:41.091630 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3902 06:53:41.098303 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3903 06:53:41.101661 [CA 0] Center 35 (5~66) winsize 62
3904 06:53:41.104856 [CA 1] Center 35 (5~66) winsize 62
3905 06:53:41.108615 [CA 2] Center 33 (3~64) winsize 62
3906 06:53:41.112021 [CA 3] Center 33 (2~64) winsize 63
3907 06:53:41.114781 [CA 4] Center 33 (2~64) winsize 63
3908 06:53:41.118205 [CA 5] Center 32 (2~63) winsize 62
3909 06:53:41.118287
3910 06:53:41.121518 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3911 06:53:41.121598
3912 06:53:41.124907 [CATrainingPosCal] consider 1 rank data
3913 06:53:41.128130 u2DelayCellTimex100 = 270/100 ps
3914 06:53:41.131424 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3915 06:53:41.134974 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3916 06:53:41.138300 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3917 06:53:41.141783 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3918 06:53:41.145130 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3919 06:53:41.148280 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3920 06:53:41.148398
3921 06:53:41.154789 CA PerBit enable=1, Macro0, CA PI delay=32
3922 06:53:41.154870
3923 06:53:41.154934 [CBTSetCACLKResult] CA Dly = 32
3924 06:53:41.158206 CS Dly: 4 (0~35)
3925 06:53:41.158287 ==
3926 06:53:41.161552 Dram Type= 6, Freq= 0, CH_0, rank 1
3927 06:53:41.165023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 06:53:41.165116 ==
3929 06:53:41.171855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 06:53:41.178732 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3931 06:53:41.181437 [CA 0] Center 35 (5~66) winsize 62
3932 06:53:41.184972 [CA 1] Center 35 (5~66) winsize 62
3933 06:53:41.188256 [CA 2] Center 34 (3~65) winsize 63
3934 06:53:41.191615 [CA 3] Center 33 (3~64) winsize 62
3935 06:53:41.194891 [CA 4] Center 33 (2~64) winsize 63
3936 06:53:41.198198 [CA 5] Center 32 (2~63) winsize 62
3937 06:53:41.198279
3938 06:53:41.201536 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3939 06:53:41.201617
3940 06:53:41.205012 [CATrainingPosCal] consider 2 rank data
3941 06:53:41.208510 u2DelayCellTimex100 = 270/100 ps
3942 06:53:41.211860 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3943 06:53:41.215072 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3944 06:53:41.218251 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3945 06:53:41.221376 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3946 06:53:41.225068 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3947 06:53:41.228264 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3948 06:53:41.228378
3949 06:53:41.235058 CA PerBit enable=1, Macro0, CA PI delay=32
3950 06:53:41.235139
3951 06:53:41.235202 [CBTSetCACLKResult] CA Dly = 32
3952 06:53:41.238261 CS Dly: 4 (0~36)
3953 06:53:41.238342
3954 06:53:41.241692 ----->DramcWriteLeveling(PI) begin...
3955 06:53:41.241774 ==
3956 06:53:41.244519 Dram Type= 6, Freq= 0, CH_0, rank 0
3957 06:53:41.247844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 06:53:41.247925 ==
3959 06:53:41.251250 Write leveling (Byte 0): 34 => 34
3960 06:53:41.254601 Write leveling (Byte 1): 32 => 32
3961 06:53:41.258070 DramcWriteLeveling(PI) end<-----
3962 06:53:41.258150
3963 06:53:41.258219 ==
3964 06:53:41.261340 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 06:53:41.264508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 06:53:41.267715 ==
3967 06:53:41.267795 [Gating] SW mode calibration
3968 06:53:41.277709 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3969 06:53:41.281313 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3970 06:53:41.284807 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 06:53:41.291030 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 06:53:41.294291 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 06:53:41.297833 0 9 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (0 0)
3974 06:53:41.304518 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3975 06:53:41.307754 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 06:53:41.310772 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 06:53:41.317633 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 06:53:41.320959 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 06:53:41.324603 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 06:53:41.330942 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 06:53:41.334199 0 10 12 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
3982 06:53:41.337790 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3983 06:53:41.344452 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 06:53:41.347767 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 06:53:41.350789 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 06:53:41.357704 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 06:53:41.361189 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 06:53:41.364053 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 06:53:41.370847 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3990 06:53:41.374296 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 06:53:41.377560 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 06:53:41.380825 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 06:53:41.387696 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 06:53:41.391209 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 06:53:41.393975 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 06:53:41.401096 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 06:53:41.403853 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 06:53:41.407313 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 06:53:41.414127 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 06:53:41.417327 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 06:53:41.420515 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 06:53:41.427415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 06:53:41.430848 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 06:53:41.434302 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 06:53:41.440456 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4006 06:53:41.443781 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 06:53:41.447066 Total UI for P1: 0, mck2ui 16
4008 06:53:41.450802 best dqsien dly found for B0: ( 0, 13, 12)
4009 06:53:41.454037 Total UI for P1: 0, mck2ui 16
4010 06:53:41.457130 best dqsien dly found for B1: ( 0, 13, 14)
4011 06:53:41.460978 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4012 06:53:41.463883 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4013 06:53:41.463962
4014 06:53:41.467235 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4015 06:53:41.470784 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4016 06:53:41.473950 [Gating] SW calibration Done
4017 06:53:41.474029 ==
4018 06:53:41.477290 Dram Type= 6, Freq= 0, CH_0, rank 0
4019 06:53:41.480636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 06:53:41.483980 ==
4021 06:53:41.484058 RX Vref Scan: 0
4022 06:53:41.484121
4023 06:53:41.487229 RX Vref 0 -> 0, step: 1
4024 06:53:41.487308
4025 06:53:41.490555 RX Delay -230 -> 252, step: 16
4026 06:53:41.494079 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4027 06:53:41.496970 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4028 06:53:41.500323 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4029 06:53:41.507286 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4030 06:53:41.510708 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4031 06:53:41.514221 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4032 06:53:41.516984 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4033 06:53:41.521027 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4034 06:53:41.527110 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4035 06:53:41.530465 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4036 06:53:41.533569 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4037 06:53:41.537537 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4038 06:53:41.543793 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4039 06:53:41.547310 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4040 06:53:41.550795 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4041 06:53:41.554201 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4042 06:53:41.554280 ==
4043 06:53:41.557452 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 06:53:41.563643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 06:53:41.563724 ==
4046 06:53:41.563786 DQS Delay:
4047 06:53:41.563843 DQS0 = 0, DQS1 = 0
4048 06:53:41.567019 DQM Delay:
4049 06:53:41.567098 DQM0 = 52, DQM1 = 45
4050 06:53:41.570374 DQ Delay:
4051 06:53:41.570452 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4052 06:53:41.573630 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4053 06:53:41.577444 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4054 06:53:41.580547 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =57
4055 06:53:41.580626
4056 06:53:41.584037
4057 06:53:41.584140 ==
4058 06:53:41.587464 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 06:53:41.590772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 06:53:41.590852 ==
4061 06:53:41.590914
4062 06:53:41.590971
4063 06:53:41.593691 TX Vref Scan disable
4064 06:53:41.593771 == TX Byte 0 ==
4065 06:53:41.600647 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4066 06:53:41.603613 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4067 06:53:41.603692 == TX Byte 1 ==
4068 06:53:41.610717 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4069 06:53:41.613506 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4070 06:53:41.613585 ==
4071 06:53:41.616992 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 06:53:41.620418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 06:53:41.620497 ==
4074 06:53:41.620559
4075 06:53:41.620617
4076 06:53:41.623792 TX Vref Scan disable
4077 06:53:41.627309 == TX Byte 0 ==
4078 06:53:41.630675 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4079 06:53:41.633493 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4080 06:53:41.637056 == TX Byte 1 ==
4081 06:53:41.640434 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4082 06:53:41.643677 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4083 06:53:41.643760
4084 06:53:41.646948 [DATLAT]
4085 06:53:41.647027 Freq=600, CH0 RK0
4086 06:53:41.647091
4087 06:53:41.650319 DATLAT Default: 0x9
4088 06:53:41.650398 0, 0xFFFF, sum = 0
4089 06:53:41.654008 1, 0xFFFF, sum = 0
4090 06:53:41.654088 2, 0xFFFF, sum = 0
4091 06:53:41.656696 3, 0xFFFF, sum = 0
4092 06:53:41.656777 4, 0xFFFF, sum = 0
4093 06:53:41.660712 5, 0xFFFF, sum = 0
4094 06:53:41.660792 6, 0xFFFF, sum = 0
4095 06:53:41.663826 7, 0xFFFF, sum = 0
4096 06:53:41.663906 8, 0x0, sum = 1
4097 06:53:41.667069 9, 0x0, sum = 2
4098 06:53:41.667153 10, 0x0, sum = 3
4099 06:53:41.670433 11, 0x0, sum = 4
4100 06:53:41.670513 best_step = 9
4101 06:53:41.670575
4102 06:53:41.670632 ==
4103 06:53:41.673987 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 06:53:41.680180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 06:53:41.680292 ==
4106 06:53:41.680392 RX Vref Scan: 1
4107 06:53:41.680450
4108 06:53:41.683597 RX Vref 0 -> 0, step: 1
4109 06:53:41.683678
4110 06:53:41.686967 RX Delay -179 -> 252, step: 8
4111 06:53:41.687048
4112 06:53:41.690278 Set Vref, RX VrefLevel [Byte0]: 58
4113 06:53:41.693568 [Byte1]: 48
4114 06:53:41.693648
4115 06:53:41.696907 Final RX Vref Byte 0 = 58 to rank0
4116 06:53:41.700222 Final RX Vref Byte 1 = 48 to rank0
4117 06:53:41.703394 Final RX Vref Byte 0 = 58 to rank1
4118 06:53:41.706626 Final RX Vref Byte 1 = 48 to rank1==
4119 06:53:41.709935 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 06:53:41.713355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 06:53:41.713436 ==
4122 06:53:41.716432 DQS Delay:
4123 06:53:41.716512 DQS0 = 0, DQS1 = 0
4124 06:53:41.716575 DQM Delay:
4125 06:53:41.719779 DQM0 = 52, DQM1 = 45
4126 06:53:41.719877 DQ Delay:
4127 06:53:41.723284 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4128 06:53:41.726371 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =60
4129 06:53:41.729715 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4130 06:53:41.733250 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4131 06:53:41.733328
4132 06:53:41.733390
4133 06:53:41.743590 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4134 06:53:41.743670 CH0 RK0: MR19=808, MR18=6D60
4135 06:53:41.749755 CH0_RK0: MR19=0x808, MR18=0x6D60, DQSOSC=389, MR23=63, INC=173, DEC=115
4136 06:53:41.749834
4137 06:53:41.753041 ----->DramcWriteLeveling(PI) begin...
4138 06:53:41.756387 ==
4139 06:53:41.756469 Dram Type= 6, Freq= 0, CH_0, rank 1
4140 06:53:41.763282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 06:53:41.763364 ==
4142 06:53:41.766812 Write leveling (Byte 0): 35 => 35
4143 06:53:41.770140 Write leveling (Byte 1): 30 => 30
4144 06:53:41.773307 DramcWriteLeveling(PI) end<-----
4145 06:53:41.773388
4146 06:53:41.773451 ==
4147 06:53:41.776456 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 06:53:41.779695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 06:53:41.779775 ==
4150 06:53:41.783173 [Gating] SW mode calibration
4151 06:53:41.789519 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4152 06:53:41.792862 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4153 06:53:41.799511 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4154 06:53:41.803077 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 06:53:41.806497 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 06:53:41.812758 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4157 06:53:41.816073 0 9 16 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
4158 06:53:41.819462 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 06:53:41.826183 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 06:53:41.829895 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 06:53:41.833080 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 06:53:41.839505 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 06:53:41.843030 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 06:53:41.845933 0 10 12 | B1->B0 | 2828 2727 | 0 1 | (0 0) (0 0)
4165 06:53:41.853189 0 10 16 | B1->B0 | 4141 4141 | 1 0 | (0 0) (0 0)
4166 06:53:41.856457 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 06:53:41.859730 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 06:53:41.866491 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 06:53:41.869307 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 06:53:41.872812 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 06:53:41.879389 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4172 06:53:41.882638 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4173 06:53:41.886050 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4174 06:53:41.893039 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 06:53:41.895784 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 06:53:41.899072 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 06:53:41.906027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 06:53:41.909318 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 06:53:41.912756 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 06:53:41.916302 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 06:53:41.922533 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 06:53:41.926004 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 06:53:41.929416 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 06:53:41.936164 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 06:53:41.939697 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 06:53:41.942515 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 06:53:41.949617 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4188 06:53:41.952678 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4189 06:53:41.955810 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 06:53:41.959407 Total UI for P1: 0, mck2ui 16
4191 06:53:41.962814 best dqsien dly found for B0: ( 0, 13, 12)
4192 06:53:41.966005 Total UI for P1: 0, mck2ui 16
4193 06:53:41.969484 best dqsien dly found for B1: ( 0, 13, 14)
4194 06:53:41.972538 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4195 06:53:41.976121 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4196 06:53:41.976202
4197 06:53:41.982613 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4198 06:53:41.986498 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4199 06:53:41.986603 [Gating] SW calibration Done
4200 06:53:41.989668 ==
4201 06:53:41.993197 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 06:53:41.996333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 06:53:41.996414 ==
4204 06:53:41.996475 RX Vref Scan: 0
4205 06:53:41.996533
4206 06:53:41.999762 RX Vref 0 -> 0, step: 1
4207 06:53:41.999840
4208 06:53:42.002608 RX Delay -230 -> 252, step: 16
4209 06:53:42.006127 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4210 06:53:42.009553 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4211 06:53:42.016088 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4212 06:53:42.019688 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4213 06:53:42.022907 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4214 06:53:42.026308 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4215 06:53:42.029726 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4216 06:53:42.036110 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4217 06:53:42.039417 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4218 06:53:42.042993 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4219 06:53:42.046414 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4220 06:53:42.052626 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4221 06:53:42.056157 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4222 06:53:42.059458 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4223 06:53:42.062852 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4224 06:53:42.069616 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4225 06:53:42.069726 ==
4226 06:53:42.072498 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 06:53:42.075951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 06:53:42.076055 ==
4229 06:53:42.076145 DQS Delay:
4230 06:53:42.079452 DQS0 = 0, DQS1 = 0
4231 06:53:42.079533 DQM Delay:
4232 06:53:42.082909 DQM0 = 52, DQM1 = 43
4233 06:53:42.082988 DQ Delay:
4234 06:53:42.085532 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4235 06:53:42.089275 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4236 06:53:42.092379 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4237 06:53:42.096099 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4238 06:53:42.096178
4239 06:53:42.096239
4240 06:53:42.096327 ==
4241 06:53:42.099028 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 06:53:42.102509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 06:53:42.102588 ==
4244 06:53:42.102649
4245 06:53:42.102707
4246 06:53:42.106102 TX Vref Scan disable
4247 06:53:42.109106 == TX Byte 0 ==
4248 06:53:42.112820 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4249 06:53:42.115566 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4250 06:53:42.119004 == TX Byte 1 ==
4251 06:53:42.122337 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4252 06:53:42.125609 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4253 06:53:42.125817 ==
4254 06:53:42.129331 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 06:53:42.135522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 06:53:42.135603 ==
4257 06:53:42.135666
4258 06:53:42.135724
4259 06:53:42.135780 TX Vref Scan disable
4260 06:53:42.140232 == TX Byte 0 ==
4261 06:53:42.143573 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4262 06:53:42.150408 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4263 06:53:42.150489 == TX Byte 1 ==
4264 06:53:42.153176 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4265 06:53:42.160207 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4266 06:53:42.160317
4267 06:53:42.160382 [DATLAT]
4268 06:53:42.160441 Freq=600, CH0 RK1
4269 06:53:42.160498
4270 06:53:42.163394 DATLAT Default: 0x9
4271 06:53:42.163473 0, 0xFFFF, sum = 0
4272 06:53:42.166629 1, 0xFFFF, sum = 0
4273 06:53:42.169939 2, 0xFFFF, sum = 0
4274 06:53:42.170021 3, 0xFFFF, sum = 0
4275 06:53:42.173410 4, 0xFFFF, sum = 0
4276 06:53:42.173492 5, 0xFFFF, sum = 0
4277 06:53:42.176867 6, 0xFFFF, sum = 0
4278 06:53:42.176948 7, 0xFFFF, sum = 0
4279 06:53:42.180375 8, 0x0, sum = 1
4280 06:53:42.180458 9, 0x0, sum = 2
4281 06:53:42.180550 10, 0x0, sum = 3
4282 06:53:42.183076 11, 0x0, sum = 4
4283 06:53:42.183158 best_step = 9
4284 06:53:42.183221
4285 06:53:42.186475 ==
4286 06:53:42.186556 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 06:53:42.193512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 06:53:42.193594 ==
4289 06:53:42.193657 RX Vref Scan: 0
4290 06:53:42.193715
4291 06:53:42.196974 RX Vref 0 -> 0, step: 1
4292 06:53:42.197054
4293 06:53:42.199767 RX Delay -163 -> 252, step: 8
4294 06:53:42.203154 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4295 06:53:42.209645 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4296 06:53:42.213555 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4297 06:53:42.216790 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4298 06:53:42.220003 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4299 06:53:42.223049 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4300 06:53:42.229616 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4301 06:53:42.232820 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4302 06:53:42.236239 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4303 06:53:42.239432 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4304 06:53:42.243127 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4305 06:53:42.249477 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4306 06:53:42.253248 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4307 06:53:42.255987 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4308 06:53:42.259460 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4309 06:53:42.266358 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4310 06:53:42.266438 ==
4311 06:53:42.269240 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 06:53:42.272587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 06:53:42.272668 ==
4314 06:53:42.272734 DQS Delay:
4315 06:53:42.275962 DQS0 = 0, DQS1 = 0
4316 06:53:42.276043 DQM Delay:
4317 06:53:42.279802 DQM0 = 54, DQM1 = 47
4318 06:53:42.279888 DQ Delay:
4319 06:53:42.282472 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4320 06:53:42.285948 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4321 06:53:42.289354 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4322 06:53:42.292871 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4323 06:53:42.292951
4324 06:53:42.293013
4325 06:53:42.299198 [DQSOSCAuto] RK1, (LSB)MR18= 0x6020, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4326 06:53:42.303079 CH0 RK1: MR19=808, MR18=6020
4327 06:53:42.309473 CH0_RK1: MR19=0x808, MR18=0x6020, DQSOSC=391, MR23=63, INC=171, DEC=114
4328 06:53:42.312892 [RxdqsGatingPostProcess] freq 600
4329 06:53:42.318983 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4330 06:53:42.322183 Pre-setting of DQS Precalculation
4331 06:53:42.325431 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4332 06:53:42.325511 ==
4333 06:53:42.328915 Dram Type= 6, Freq= 0, CH_1, rank 0
4334 06:53:42.332393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 06:53:42.332474 ==
4336 06:53:42.338759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4337 06:53:42.345674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4338 06:53:42.348691 [CA 0] Center 36 (5~67) winsize 63
4339 06:53:42.352024 [CA 1] Center 36 (5~67) winsize 63
4340 06:53:42.355409 [CA 2] Center 34 (4~65) winsize 62
4341 06:53:42.359066 [CA 3] Center 34 (4~65) winsize 62
4342 06:53:42.362072 [CA 4] Center 34 (4~65) winsize 62
4343 06:53:42.365655 [CA 5] Center 33 (3~64) winsize 62
4344 06:53:42.365734
4345 06:53:42.368670 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4346 06:53:42.368749
4347 06:53:42.372069 [CATrainingPosCal] consider 1 rank data
4348 06:53:42.375536 u2DelayCellTimex100 = 270/100 ps
4349 06:53:42.379033 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4350 06:53:42.382434 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4351 06:53:42.385266 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4352 06:53:42.388820 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4353 06:53:42.391948 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4354 06:53:42.398437 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4355 06:53:42.398517
4356 06:53:42.401750 CA PerBit enable=1, Macro0, CA PI delay=33
4357 06:53:42.401830
4358 06:53:42.405120 [CBTSetCACLKResult] CA Dly = 33
4359 06:53:42.405209 CS Dly: 6 (0~37)
4360 06:53:42.405273 ==
4361 06:53:42.408649 Dram Type= 6, Freq= 0, CH_1, rank 1
4362 06:53:42.412079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 06:53:42.415502 ==
4364 06:53:42.418833 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4365 06:53:42.425450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4366 06:53:42.428801 [CA 0] Center 36 (5~67) winsize 63
4367 06:53:42.432260 [CA 1] Center 36 (5~67) winsize 63
4368 06:53:42.435046 [CA 2] Center 34 (4~65) winsize 62
4369 06:53:42.438701 [CA 3] Center 34 (4~65) winsize 62
4370 06:53:42.442134 [CA 4] Center 35 (4~66) winsize 63
4371 06:53:42.444929 [CA 5] Center 34 (3~65) winsize 63
4372 06:53:42.445037
4373 06:53:42.448494 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4374 06:53:42.448575
4375 06:53:42.451896 [CATrainingPosCal] consider 2 rank data
4376 06:53:42.455366 u2DelayCellTimex100 = 270/100 ps
4377 06:53:42.458713 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4378 06:53:42.461838 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4379 06:53:42.464970 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4380 06:53:42.468606 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 06:53:42.475001 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 06:53:42.478354 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 06:53:42.478435
4384 06:53:42.482105 CA PerBit enable=1, Macro0, CA PI delay=33
4385 06:53:42.482186
4386 06:53:42.484966 [CBTSetCACLKResult] CA Dly = 33
4387 06:53:42.485046 CS Dly: 7 (0~39)
4388 06:53:42.485114
4389 06:53:42.488468 ----->DramcWriteLeveling(PI) begin...
4390 06:53:42.488550 ==
4391 06:53:42.491438 Dram Type= 6, Freq= 0, CH_1, rank 0
4392 06:53:42.498611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 06:53:42.498692 ==
4394 06:53:42.501800 Write leveling (Byte 0): 30 => 30
4395 06:53:42.505077 Write leveling (Byte 1): 29 => 29
4396 06:53:42.505158 DramcWriteLeveling(PI) end<-----
4397 06:53:42.505221
4398 06:53:42.508275 ==
4399 06:53:42.512040 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 06:53:42.515160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 06:53:42.515241 ==
4402 06:53:42.518674 [Gating] SW mode calibration
4403 06:53:42.524953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4404 06:53:42.528189 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4405 06:53:42.535411 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4406 06:53:42.538176 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 06:53:42.541724 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4408 06:53:42.548703 0 9 12 | B1->B0 | 2f2f 2e2e | 1 0 | (1 0) (0 0)
4409 06:53:42.551501 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4410 06:53:42.554908 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 06:53:42.561871 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 06:53:42.564661 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 06:53:42.568152 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 06:53:42.574994 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 06:53:42.578160 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 06:53:42.581751 0 10 12 | B1->B0 | 3838 3a3a | 0 0 | (0 0) (0 0)
4417 06:53:42.588272 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 06:53:42.591404 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 06:53:42.594700 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 06:53:42.601510 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 06:53:42.604607 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 06:53:42.608156 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 06:53:42.611184 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 06:53:42.618163 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 06:53:42.621146 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 06:53:42.624426 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 06:53:42.631332 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 06:53:42.634525 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 06:53:42.638175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 06:53:42.644327 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 06:53:42.647671 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 06:53:42.651151 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 06:53:42.658154 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 06:53:42.661547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 06:53:42.665090 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 06:53:42.671454 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 06:53:42.674951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 06:53:42.678455 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 06:53:42.685114 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4440 06:53:42.687867 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4441 06:53:42.691390 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4442 06:53:42.694674 Total UI for P1: 0, mck2ui 16
4443 06:53:42.698098 best dqsien dly found for B0: ( 0, 13, 12)
4444 06:53:42.704138 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 06:53:42.704217 Total UI for P1: 0, mck2ui 16
4446 06:53:42.707624 best dqsien dly found for B1: ( 0, 13, 12)
4447 06:53:42.714448 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4448 06:53:42.717735 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4449 06:53:42.717814
4450 06:53:42.721367 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4451 06:53:42.724169 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4452 06:53:42.727578 [Gating] SW calibration Done
4453 06:53:42.727660 ==
4454 06:53:42.730903 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 06:53:42.734721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 06:53:42.734801 ==
4457 06:53:42.737843 RX Vref Scan: 0
4458 06:53:42.737922
4459 06:53:42.737984 RX Vref 0 -> 0, step: 1
4460 06:53:42.738042
4461 06:53:42.741437 RX Delay -230 -> 252, step: 16
4462 06:53:42.744674 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4463 06:53:42.751398 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4464 06:53:42.754287 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4465 06:53:42.757703 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4466 06:53:42.761115 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4467 06:53:42.764492 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4468 06:53:42.770889 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4469 06:53:42.774443 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4470 06:53:42.778016 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4471 06:53:42.781279 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4472 06:53:42.787438 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4473 06:53:42.790900 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4474 06:53:42.794275 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4475 06:53:42.797701 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4476 06:53:42.801067 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4477 06:53:42.807944 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4478 06:53:42.808023 ==
4479 06:53:42.811326 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 06:53:42.814077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 06:53:42.814157 ==
4482 06:53:42.814219 DQS Delay:
4483 06:53:42.817393 DQS0 = 0, DQS1 = 0
4484 06:53:42.817472 DQM Delay:
4485 06:53:42.821036 DQM0 = 51, DQM1 = 49
4486 06:53:42.821116 DQ Delay:
4487 06:53:42.824297 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4488 06:53:42.827438 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =41
4489 06:53:42.830689 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4490 06:53:42.834215 DQ12 =65, DQ13 =57, DQ14 =49, DQ15 =65
4491 06:53:42.834294
4492 06:53:42.834359
4493 06:53:42.834416 ==
4494 06:53:42.837701 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 06:53:42.841100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 06:53:42.844670 ==
4497 06:53:42.844751
4498 06:53:42.844813
4499 06:53:42.844872 TX Vref Scan disable
4500 06:53:42.847946 == TX Byte 0 ==
4501 06:53:42.850667 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4502 06:53:42.854154 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4503 06:53:42.857653 == TX Byte 1 ==
4504 06:53:42.861089 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4505 06:53:42.864358 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4506 06:53:42.867484 ==
4507 06:53:42.867565 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 06:53:42.874286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 06:53:42.874368 ==
4510 06:53:42.874431
4511 06:53:42.874490
4512 06:53:42.874546 TX Vref Scan disable
4513 06:53:42.879322 == TX Byte 0 ==
4514 06:53:42.882201 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4515 06:53:42.888437 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4516 06:53:42.888519 == TX Byte 1 ==
4517 06:53:42.891933 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4518 06:53:42.898775 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4519 06:53:42.898886
4520 06:53:42.898950 [DATLAT]
4521 06:53:42.899009 Freq=600, CH1 RK0
4522 06:53:42.899065
4523 06:53:42.902156 DATLAT Default: 0x9
4524 06:53:42.902235 0, 0xFFFF, sum = 0
4525 06:53:42.905566 1, 0xFFFF, sum = 0
4526 06:53:42.908968 2, 0xFFFF, sum = 0
4527 06:53:42.909051 3, 0xFFFF, sum = 0
4528 06:53:42.911782 4, 0xFFFF, sum = 0
4529 06:53:42.911863 5, 0xFFFF, sum = 0
4530 06:53:42.915229 6, 0xFFFF, sum = 0
4531 06:53:42.915310 7, 0xFFFF, sum = 0
4532 06:53:42.918393 8, 0x0, sum = 1
4533 06:53:42.918473 9, 0x0, sum = 2
4534 06:53:42.918537 10, 0x0, sum = 3
4535 06:53:42.921778 11, 0x0, sum = 4
4536 06:53:42.921858 best_step = 9
4537 06:53:42.921920
4538 06:53:42.921977 ==
4539 06:53:42.925336 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 06:53:42.932104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 06:53:42.932209 ==
4542 06:53:42.932328 RX Vref Scan: 1
4543 06:53:42.932404
4544 06:53:42.935287 RX Vref 0 -> 0, step: 1
4545 06:53:42.935366
4546 06:53:42.938245 RX Delay -163 -> 252, step: 8
4547 06:53:42.938324
4548 06:53:42.941504 Set Vref, RX VrefLevel [Byte0]: 57
4549 06:53:42.944878 [Byte1]: 55
4550 06:53:42.944957
4551 06:53:42.948237 Final RX Vref Byte 0 = 57 to rank0
4552 06:53:42.951739 Final RX Vref Byte 1 = 55 to rank0
4553 06:53:42.955075 Final RX Vref Byte 0 = 57 to rank1
4554 06:53:42.958412 Final RX Vref Byte 1 = 55 to rank1==
4555 06:53:42.961810 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 06:53:42.965085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 06:53:42.965166 ==
4558 06:53:42.968513 DQS Delay:
4559 06:53:42.968596 DQS0 = 0, DQS1 = 0
4560 06:53:42.968664 DQM Delay:
4561 06:53:42.971888 DQM0 = 48, DQM1 = 44
4562 06:53:42.971992 DQ Delay:
4563 06:53:42.975293 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4564 06:53:42.978746 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4565 06:53:42.982133 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4566 06:53:42.984968 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4567 06:53:42.985048
4568 06:53:42.985109
4569 06:53:42.995270 [DQSOSCAuto] RK0, (LSB)MR18= 0x486d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4570 06:53:42.998346 CH1 RK0: MR19=808, MR18=486D
4571 06:53:43.001748 CH1_RK0: MR19=0x808, MR18=0x486D, DQSOSC=389, MR23=63, INC=173, DEC=115
4572 06:53:43.001827
4573 06:53:43.005033 ----->DramcWriteLeveling(PI) begin...
4574 06:53:43.008479 ==
4575 06:53:43.012135 Dram Type= 6, Freq= 0, CH_1, rank 1
4576 06:53:43.015427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 06:53:43.015507 ==
4578 06:53:43.018248 Write leveling (Byte 0): 30 => 30
4579 06:53:43.021887 Write leveling (Byte 1): 31 => 31
4580 06:53:43.025038 DramcWriteLeveling(PI) end<-----
4581 06:53:43.025145
4582 06:53:43.025235 ==
4583 06:53:43.028763 Dram Type= 6, Freq= 0, CH_1, rank 1
4584 06:53:43.032090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 06:53:43.032170 ==
4586 06:53:43.034806 [Gating] SW mode calibration
4587 06:53:43.041607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4588 06:53:43.048031 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4589 06:53:43.051492 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4590 06:53:43.055036 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 06:53:43.058568 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 06:53:43.065102 0 9 12 | B1->B0 | 2a2a 2e2e | 0 1 | (1 0) (1 0)
4593 06:53:43.067917 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 06:53:43.071805 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 06:53:43.078438 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 06:53:43.081882 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 06:53:43.084598 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 06:53:43.091458 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 06:53:43.094984 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 06:53:43.098496 0 10 12 | B1->B0 | 3b3b 3535 | 1 0 | (0 0) (0 0)
4601 06:53:43.104519 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 06:53:43.107961 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 06:53:43.111190 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 06:53:43.117946 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 06:53:43.121612 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 06:53:43.124576 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 06:53:43.131367 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 06:53:43.134963 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4609 06:53:43.137953 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 06:53:43.144921 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 06:53:43.147594 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 06:53:43.150870 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 06:53:43.158092 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 06:53:43.160906 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 06:53:43.164378 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 06:53:43.171228 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 06:53:43.174727 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 06:53:43.178058 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 06:53:43.184381 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 06:53:43.188005 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 06:53:43.191054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 06:53:43.197815 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 06:53:43.201225 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4624 06:53:43.204673 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4625 06:53:43.208013 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 06:53:43.211365 Total UI for P1: 0, mck2ui 16
4627 06:53:43.214111 best dqsien dly found for B0: ( 0, 13, 12)
4628 06:53:43.217622 Total UI for P1: 0, mck2ui 16
4629 06:53:43.221140 best dqsien dly found for B1: ( 0, 13, 10)
4630 06:53:43.224441 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4631 06:53:43.231164 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4632 06:53:43.231243
4633 06:53:43.234286 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4634 06:53:43.237587 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4635 06:53:43.241480 [Gating] SW calibration Done
4636 06:53:43.241559 ==
4637 06:53:43.244549 Dram Type= 6, Freq= 0, CH_1, rank 1
4638 06:53:43.247756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 06:53:43.247836 ==
4640 06:53:43.250877 RX Vref Scan: 0
4641 06:53:43.250987
4642 06:53:43.251053 RX Vref 0 -> 0, step: 1
4643 06:53:43.251112
4644 06:53:43.254149 RX Delay -230 -> 252, step: 16
4645 06:53:43.257597 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4646 06:53:43.264412 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4647 06:53:43.267512 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4648 06:53:43.270925 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4649 06:53:43.274251 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4650 06:53:43.277827 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4651 06:53:43.284060 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4652 06:53:43.287601 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4653 06:53:43.290975 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4654 06:53:43.294299 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4655 06:53:43.300997 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4656 06:53:43.304022 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4657 06:53:43.307602 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4658 06:53:43.311218 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4659 06:53:43.317769 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4660 06:53:43.321205 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4661 06:53:43.321285 ==
4662 06:53:43.323961 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 06:53:43.327479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 06:53:43.327559 ==
4665 06:53:43.327621 DQS Delay:
4666 06:53:43.330763 DQS0 = 0, DQS1 = 0
4667 06:53:43.330842 DQM Delay:
4668 06:53:43.334100 DQM0 = 48, DQM1 = 48
4669 06:53:43.334179 DQ Delay:
4670 06:53:43.337527 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =49
4671 06:53:43.340716 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =49
4672 06:53:43.344162 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4673 06:53:43.347749 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4674 06:53:43.347832
4675 06:53:43.347894
4676 06:53:43.347952 ==
4677 06:53:43.351124 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 06:53:43.354282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 06:53:43.357473 ==
4680 06:53:43.357552
4681 06:53:43.357614
4682 06:53:43.357672 TX Vref Scan disable
4683 06:53:43.360480 == TX Byte 0 ==
4684 06:53:43.364128 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4685 06:53:43.367127 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4686 06:53:43.370783 == TX Byte 1 ==
4687 06:53:43.373905 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4688 06:53:43.380814 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4689 06:53:43.380897 ==
4690 06:53:43.383604 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 06:53:43.386953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 06:53:43.387033 ==
4693 06:53:43.387095
4694 06:53:43.387152
4695 06:53:43.390393 TX Vref Scan disable
4696 06:53:43.393804 == TX Byte 0 ==
4697 06:53:43.397356 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4698 06:53:43.400175 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4699 06:53:43.403557 == TX Byte 1 ==
4700 06:53:43.407066 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4701 06:53:43.410273 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4702 06:53:43.410353
4703 06:53:43.410415 [DATLAT]
4704 06:53:43.413462 Freq=600, CH1 RK1
4705 06:53:43.413566
4706 06:53:43.413633 DATLAT Default: 0x9
4707 06:53:43.417243 0, 0xFFFF, sum = 0
4708 06:53:43.417325 1, 0xFFFF, sum = 0
4709 06:53:43.420465 2, 0xFFFF, sum = 0
4710 06:53:43.423766 3, 0xFFFF, sum = 0
4711 06:53:43.423848 4, 0xFFFF, sum = 0
4712 06:53:43.427181 5, 0xFFFF, sum = 0
4713 06:53:43.427263 6, 0xFFFF, sum = 0
4714 06:53:43.430726 7, 0xFFFF, sum = 0
4715 06:53:43.430808 8, 0x0, sum = 1
4716 06:53:43.430872 9, 0x0, sum = 2
4717 06:53:43.433477 10, 0x0, sum = 3
4718 06:53:43.433559 11, 0x0, sum = 4
4719 06:53:43.436838 best_step = 9
4720 06:53:43.436918
4721 06:53:43.436981 ==
4722 06:53:43.440170 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 06:53:43.443438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 06:53:43.443519 ==
4725 06:53:43.446941 RX Vref Scan: 0
4726 06:53:43.447021
4727 06:53:43.447084 RX Vref 0 -> 0, step: 1
4728 06:53:43.447143
4729 06:53:43.450288 RX Delay -163 -> 252, step: 8
4730 06:53:43.457263 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4731 06:53:43.460731 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4732 06:53:43.464106 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4733 06:53:43.467641 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4734 06:53:43.470721 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4735 06:53:43.477310 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4736 06:53:43.480833 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4737 06:53:43.484131 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4738 06:53:43.487318 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4739 06:53:43.493843 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4740 06:53:43.497473 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4741 06:53:43.500206 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4742 06:53:43.504132 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4743 06:53:43.507714 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4744 06:53:43.513894 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4745 06:53:43.517219 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4746 06:53:43.517300 ==
4747 06:53:43.520414 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 06:53:43.523783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 06:53:43.523867 ==
4750 06:53:43.527247 DQS Delay:
4751 06:53:43.527328 DQS0 = 0, DQS1 = 0
4752 06:53:43.527391 DQM Delay:
4753 06:53:43.530544 DQM0 = 48, DQM1 = 46
4754 06:53:43.530624 DQ Delay:
4755 06:53:43.533803 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4756 06:53:43.537329 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4757 06:53:43.540717 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4758 06:53:43.544131 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4759 06:53:43.544212
4760 06:53:43.544275
4761 06:53:43.554288 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4762 06:53:43.554371 CH1 RK1: MR19=808, MR18=6B22
4763 06:53:43.560549 CH1_RK1: MR19=0x808, MR18=0x6B22, DQSOSC=389, MR23=63, INC=173, DEC=115
4764 06:53:43.563926 [RxdqsGatingPostProcess] freq 600
4765 06:53:43.570291 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4766 06:53:43.573934 Pre-setting of DQS Precalculation
4767 06:53:43.576972 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4768 06:53:43.584074 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4769 06:53:43.593563 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4770 06:53:43.593645
4771 06:53:43.593708
4772 06:53:43.597075 [Calibration Summary] 1200 Mbps
4773 06:53:43.597156 CH 0, Rank 0
4774 06:53:43.600409 SW Impedance : PASS
4775 06:53:43.600490 DUTY Scan : NO K
4776 06:53:43.603806 ZQ Calibration : PASS
4777 06:53:43.607064 Jitter Meter : NO K
4778 06:53:43.607145 CBT Training : PASS
4779 06:53:43.610197 Write leveling : PASS
4780 06:53:43.610278 RX DQS gating : PASS
4781 06:53:43.613237 RX DQ/DQS(RDDQC) : PASS
4782 06:53:43.616646 TX DQ/DQS : PASS
4783 06:53:43.616727 RX DATLAT : PASS
4784 06:53:43.620133 RX DQ/DQS(Engine): PASS
4785 06:53:43.623413 TX OE : NO K
4786 06:53:43.623495 All Pass.
4787 06:53:43.623559
4788 06:53:43.623618 CH 0, Rank 1
4789 06:53:43.626738 SW Impedance : PASS
4790 06:53:43.629889 DUTY Scan : NO K
4791 06:53:43.629970 ZQ Calibration : PASS
4792 06:53:43.633302 Jitter Meter : NO K
4793 06:53:43.636648 CBT Training : PASS
4794 06:53:43.636728 Write leveling : PASS
4795 06:53:43.640011 RX DQS gating : PASS
4796 06:53:43.643171 RX DQ/DQS(RDDQC) : PASS
4797 06:53:43.643250 TX DQ/DQS : PASS
4798 06:53:43.646592 RX DATLAT : PASS
4799 06:53:43.650126 RX DQ/DQS(Engine): PASS
4800 06:53:43.650205 TX OE : NO K
4801 06:53:43.653350 All Pass.
4802 06:53:43.653429
4803 06:53:43.653490 CH 1, Rank 0
4804 06:53:43.656593 SW Impedance : PASS
4805 06:53:43.656672 DUTY Scan : NO K
4806 06:53:43.660051 ZQ Calibration : PASS
4807 06:53:43.662925 Jitter Meter : NO K
4808 06:53:43.663004 CBT Training : PASS
4809 06:53:43.666301 Write leveling : PASS
4810 06:53:43.666380 RX DQS gating : PASS
4811 06:53:43.669781 RX DQ/DQS(RDDQC) : PASS
4812 06:53:43.673185 TX DQ/DQS : PASS
4813 06:53:43.673265 RX DATLAT : PASS
4814 06:53:43.676657 RX DQ/DQS(Engine): PASS
4815 06:53:43.680149 TX OE : NO K
4816 06:53:43.680229 All Pass.
4817 06:53:43.680299
4818 06:53:43.680390 CH 1, Rank 1
4819 06:53:43.682931 SW Impedance : PASS
4820 06:53:43.686635 DUTY Scan : NO K
4821 06:53:43.686714 ZQ Calibration : PASS
4822 06:53:43.690140 Jitter Meter : NO K
4823 06:53:43.693306 CBT Training : PASS
4824 06:53:43.693394 Write leveling : PASS
4825 06:53:43.696377 RX DQS gating : PASS
4826 06:53:43.699652 RX DQ/DQS(RDDQC) : PASS
4827 06:53:43.699731 TX DQ/DQS : PASS
4828 06:53:43.703086 RX DATLAT : PASS
4829 06:53:43.706462 RX DQ/DQS(Engine): PASS
4830 06:53:43.706540 TX OE : NO K
4831 06:53:43.706603 All Pass.
4832 06:53:43.709952
4833 06:53:43.710030 DramC Write-DBI off
4834 06:53:43.713397 PER_BANK_REFRESH: Hybrid Mode
4835 06:53:43.713476 TX_TRACKING: ON
4836 06:53:43.723056 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4837 06:53:43.726329 [FAST_K] Save calibration result to emmc
4838 06:53:43.730096 dramc_set_vcore_voltage set vcore to 662500
4839 06:53:43.733079 Read voltage for 933, 3
4840 06:53:43.733158 Vio18 = 0
4841 06:53:43.736572 Vcore = 662500
4842 06:53:43.736651 Vdram = 0
4843 06:53:43.736712 Vddq = 0
4844 06:53:43.736770 Vmddr = 0
4845 06:53:43.743051 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4846 06:53:43.749643 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4847 06:53:43.749723 MEM_TYPE=3, freq_sel=17
4848 06:53:43.752750 sv_algorithm_assistance_LP4_1600
4849 06:53:43.755994 ============ PULL DRAM RESETB DOWN ============
4850 06:53:43.762731 ========== PULL DRAM RESETB DOWN end =========
4851 06:53:43.765776 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4852 06:53:43.769713 ===================================
4853 06:53:43.773084 LPDDR4 DRAM CONFIGURATION
4854 06:53:43.775936 ===================================
4855 06:53:43.776015 EX_ROW_EN[0] = 0x0
4856 06:53:43.779400 EX_ROW_EN[1] = 0x0
4857 06:53:43.779478 LP4Y_EN = 0x0
4858 06:53:43.782866 WORK_FSP = 0x0
4859 06:53:43.782945 WL = 0x3
4860 06:53:43.786288 RL = 0x3
4861 06:53:43.789106 BL = 0x2
4862 06:53:43.789185 RPST = 0x0
4863 06:53:43.792507 RD_PRE = 0x0
4864 06:53:43.792585 WR_PRE = 0x1
4865 06:53:43.795928 WR_PST = 0x0
4866 06:53:43.796007 DBI_WR = 0x0
4867 06:53:43.799466 DBI_RD = 0x0
4868 06:53:43.799545 OTF = 0x1
4869 06:53:43.802707 ===================================
4870 06:53:43.805844 ===================================
4871 06:53:43.809075 ANA top config
4872 06:53:43.812254 ===================================
4873 06:53:43.812372 DLL_ASYNC_EN = 0
4874 06:53:43.815622 ALL_SLAVE_EN = 1
4875 06:53:43.819133 NEW_RANK_MODE = 1
4876 06:53:43.822529 DLL_IDLE_MODE = 1
4877 06:53:43.822608 LP45_APHY_COMB_EN = 1
4878 06:53:43.826009 TX_ODT_DIS = 1
4879 06:53:43.829364 NEW_8X_MODE = 1
4880 06:53:43.832782 ===================================
4881 06:53:43.836293 ===================================
4882 06:53:43.839008 data_rate = 1866
4883 06:53:43.842390 CKR = 1
4884 06:53:43.842470 DQ_P2S_RATIO = 8
4885 06:53:43.845730 ===================================
4886 06:53:43.849056 CA_P2S_RATIO = 8
4887 06:53:43.852320 DQ_CA_OPEN = 0
4888 06:53:43.856067 DQ_SEMI_OPEN = 0
4889 06:53:43.859341 CA_SEMI_OPEN = 0
4890 06:53:43.862255 CA_FULL_RATE = 0
4891 06:53:43.862335 DQ_CKDIV4_EN = 1
4892 06:53:43.865558 CA_CKDIV4_EN = 1
4893 06:53:43.868716 CA_PREDIV_EN = 0
4894 06:53:43.872551 PH8_DLY = 0
4895 06:53:43.875608 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4896 06:53:43.879177 DQ_AAMCK_DIV = 4
4897 06:53:43.879257 CA_AAMCK_DIV = 4
4898 06:53:43.882226 CA_ADMCK_DIV = 4
4899 06:53:43.885614 DQ_TRACK_CA_EN = 0
4900 06:53:43.889195 CA_PICK = 933
4901 06:53:43.892405 CA_MCKIO = 933
4902 06:53:43.895812 MCKIO_SEMI = 0
4903 06:53:43.898626 PLL_FREQ = 3732
4904 06:53:43.898707 DQ_UI_PI_RATIO = 32
4905 06:53:43.902104 CA_UI_PI_RATIO = 0
4906 06:53:43.905579 ===================================
4907 06:53:43.909021 ===================================
4908 06:53:43.912439 memory_type:LPDDR4
4909 06:53:43.915615 GP_NUM : 10
4910 06:53:43.915695 SRAM_EN : 1
4911 06:53:43.918988 MD32_EN : 0
4912 06:53:43.921882 ===================================
4913 06:53:43.925153 [ANA_INIT] >>>>>>>>>>>>>>
4914 06:53:43.925232 <<<<<< [CONFIGURE PHASE]: ANA_TX
4915 06:53:43.932191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4916 06:53:43.932272 ===================================
4917 06:53:43.935585 data_rate = 1866,PCW = 0X8f00
4918 06:53:43.939061 ===================================
4919 06:53:43.942032 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4920 06:53:43.948660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4921 06:53:43.955431 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4922 06:53:43.958932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4923 06:53:43.961667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4924 06:53:43.965022 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4925 06:53:43.968257 [ANA_INIT] flow start
4926 06:53:43.968394 [ANA_INIT] PLL >>>>>>>>
4927 06:53:43.972071 [ANA_INIT] PLL <<<<<<<<
4928 06:53:43.975198 [ANA_INIT] MIDPI >>>>>>>>
4929 06:53:43.978243 [ANA_INIT] MIDPI <<<<<<<<
4930 06:53:43.978322 [ANA_INIT] DLL >>>>>>>>
4931 06:53:43.981789 [ANA_INIT] flow end
4932 06:53:43.985001 ============ LP4 DIFF to SE enter ============
4933 06:53:43.988273 ============ LP4 DIFF to SE exit ============
4934 06:53:43.991592 [ANA_INIT] <<<<<<<<<<<<<
4935 06:53:43.994772 [Flow] Enable top DCM control >>>>>
4936 06:53:43.998721 [Flow] Enable top DCM control <<<<<
4937 06:53:44.001315 Enable DLL master slave shuffle
4938 06:53:44.008230 ==============================================================
4939 06:53:44.008317 Gating Mode config
4940 06:53:44.014589 ==============================================================
4941 06:53:44.014670 Config description:
4942 06:53:44.024936 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4943 06:53:44.031482 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4944 06:53:44.038259 SELPH_MODE 0: By rank 1: By Phase
4945 06:53:44.041704 ==============================================================
4946 06:53:44.044527 GAT_TRACK_EN = 1
4947 06:53:44.048028 RX_GATING_MODE = 2
4948 06:53:44.051493 RX_GATING_TRACK_MODE = 2
4949 06:53:44.054789 SELPH_MODE = 1
4950 06:53:44.058265 PICG_EARLY_EN = 1
4951 06:53:44.061074 VALID_LAT_VALUE = 1
4952 06:53:44.064589 ==============================================================
4953 06:53:44.068029 Enter into Gating configuration >>>>
4954 06:53:44.071528 Exit from Gating configuration <<<<
4955 06:53:44.074988 Enter into DVFS_PRE_config >>>>>
4956 06:53:44.088086 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4957 06:53:44.091315 Exit from DVFS_PRE_config <<<<<
4958 06:53:44.094869 Enter into PICG configuration >>>>
4959 06:53:44.094949 Exit from PICG configuration <<<<
4960 06:53:44.097910 [RX_INPUT] configuration >>>>>
4961 06:53:44.101086 [RX_INPUT] configuration <<<<<
4962 06:53:44.107723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4963 06:53:44.111112 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4964 06:53:44.118069 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4965 06:53:44.124256 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4966 06:53:44.131032 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4967 06:53:44.137403 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4968 06:53:44.141181 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4969 06:53:44.144246 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4970 06:53:44.150772 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4971 06:53:44.154115 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4972 06:53:44.157497 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4973 06:53:44.160688 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4974 06:53:44.164161 ===================================
4975 06:53:44.167724 LPDDR4 DRAM CONFIGURATION
4976 06:53:44.171107 ===================================
4977 06:53:44.173903 EX_ROW_EN[0] = 0x0
4978 06:53:44.173983 EX_ROW_EN[1] = 0x0
4979 06:53:44.177311 LP4Y_EN = 0x0
4980 06:53:44.177393 WORK_FSP = 0x0
4981 06:53:44.180723 WL = 0x3
4982 06:53:44.180804 RL = 0x3
4983 06:53:44.184154 BL = 0x2
4984 06:53:44.184234 RPST = 0x0
4985 06:53:44.187523 RD_PRE = 0x0
4986 06:53:44.187604 WR_PRE = 0x1
4987 06:53:44.190959 WR_PST = 0x0
4988 06:53:44.191039 DBI_WR = 0x0
4989 06:53:44.193696 DBI_RD = 0x0
4990 06:53:44.193776 OTF = 0x1
4991 06:53:44.197138 ===================================
4992 06:53:44.204217 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4993 06:53:44.207154 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4994 06:53:44.210650 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4995 06:53:44.213747 ===================================
4996 06:53:44.217182 LPDDR4 DRAM CONFIGURATION
4997 06:53:44.220684 ===================================
4998 06:53:44.223561 EX_ROW_EN[0] = 0x10
4999 06:53:44.223634 EX_ROW_EN[1] = 0x0
5000 06:53:44.227063 LP4Y_EN = 0x0
5001 06:53:44.227134 WORK_FSP = 0x0
5002 06:53:44.230557 WL = 0x3
5003 06:53:44.230656 RL = 0x3
5004 06:53:44.233983 BL = 0x2
5005 06:53:44.234076 RPST = 0x0
5006 06:53:44.237453 RD_PRE = 0x0
5007 06:53:44.237521 WR_PRE = 0x1
5008 06:53:44.240556 WR_PST = 0x0
5009 06:53:44.240625 DBI_WR = 0x0
5010 06:53:44.243545 DBI_RD = 0x0
5011 06:53:44.243614 OTF = 0x1
5012 06:53:44.247257 ===================================
5013 06:53:44.253636 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5014 06:53:44.258568 nWR fixed to 30
5015 06:53:44.261980 [ModeRegInit_LP4] CH0 RK0
5016 06:53:44.262056 [ModeRegInit_LP4] CH0 RK1
5017 06:53:44.264992 [ModeRegInit_LP4] CH1 RK0
5018 06:53:44.268577 [ModeRegInit_LP4] CH1 RK1
5019 06:53:44.268656 match AC timing 9
5020 06:53:44.274787 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5021 06:53:44.278231 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5022 06:53:44.281751 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5023 06:53:44.288497 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5024 06:53:44.291976 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5025 06:53:44.292073 ==
5026 06:53:44.294646 Dram Type= 6, Freq= 0, CH_0, rank 0
5027 06:53:44.298070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5028 06:53:44.298165 ==
5029 06:53:44.304927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5030 06:53:44.311626 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5031 06:53:44.314831 [CA 0] Center 37 (6~68) winsize 63
5032 06:53:44.317965 [CA 1] Center 37 (7~68) winsize 62
5033 06:53:44.321582 [CA 2] Center 34 (4~65) winsize 62
5034 06:53:44.324619 [CA 3] Center 34 (3~65) winsize 63
5035 06:53:44.328209 [CA 4] Center 33 (3~64) winsize 62
5036 06:53:44.331217 [CA 5] Center 32 (2~62) winsize 61
5037 06:53:44.331319
5038 06:53:44.334651 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5039 06:53:44.334750
5040 06:53:44.338125 [CATrainingPosCal] consider 1 rank data
5041 06:53:44.341633 u2DelayCellTimex100 = 270/100 ps
5042 06:53:44.345280 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5043 06:53:44.348264 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5044 06:53:44.351745 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5045 06:53:44.354547 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5046 06:53:44.357880 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5047 06:53:44.361239 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5048 06:53:44.364449
5049 06:53:44.368183 CA PerBit enable=1, Macro0, CA PI delay=32
5050 06:53:44.368262
5051 06:53:44.371380 [CBTSetCACLKResult] CA Dly = 32
5052 06:53:44.371460 CS Dly: 5 (0~36)
5053 06:53:44.371522 ==
5054 06:53:44.374577 Dram Type= 6, Freq= 0, CH_0, rank 1
5055 06:53:44.378146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5056 06:53:44.378226 ==
5057 06:53:44.384168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5058 06:53:44.391005 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5059 06:53:44.394573 [CA 0] Center 37 (6~68) winsize 63
5060 06:53:44.397488 [CA 1] Center 37 (6~68) winsize 63
5061 06:53:44.401086 [CA 2] Center 34 (4~65) winsize 62
5062 06:53:44.404587 [CA 3] Center 34 (3~65) winsize 63
5063 06:53:44.407351 [CA 4] Center 33 (3~63) winsize 61
5064 06:53:44.410908 [CA 5] Center 32 (2~63) winsize 62
5065 06:53:44.410987
5066 06:53:44.414433 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5067 06:53:44.414511
5068 06:53:44.417202 [CATrainingPosCal] consider 2 rank data
5069 06:53:44.420610 u2DelayCellTimex100 = 270/100 ps
5070 06:53:44.423997 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5071 06:53:44.427194 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5072 06:53:44.430946 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5073 06:53:44.437584 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5074 06:53:44.440780 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5075 06:53:44.443716 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5076 06:53:44.443795
5077 06:53:44.447211 CA PerBit enable=1, Macro0, CA PI delay=32
5078 06:53:44.447290
5079 06:53:44.450697 [CBTSetCACLKResult] CA Dly = 32
5080 06:53:44.450776 CS Dly: 5 (0~37)
5081 06:53:44.450838
5082 06:53:44.454073 ----->DramcWriteLeveling(PI) begin...
5083 06:53:44.454153 ==
5084 06:53:44.457522 Dram Type= 6, Freq= 0, CH_0, rank 0
5085 06:53:44.463811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5086 06:53:44.463894 ==
5087 06:53:44.467329 Write leveling (Byte 0): 32 => 32
5088 06:53:44.471012 Write leveling (Byte 1): 27 => 27
5089 06:53:44.471092 DramcWriteLeveling(PI) end<-----
5090 06:53:44.473756
5091 06:53:44.473835 ==
5092 06:53:44.477163 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 06:53:44.480626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 06:53:44.480705 ==
5095 06:53:44.484100 [Gating] SW mode calibration
5096 06:53:44.490666 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5097 06:53:44.493940 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5098 06:53:44.500615 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5099 06:53:44.503742 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 06:53:44.506982 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 06:53:44.513840 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 06:53:44.516772 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 06:53:44.520223 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 06:53:44.526656 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5105 06:53:44.530184 0 14 28 | B1->B0 | 3333 2525 | 0 0 | (0 1) (1 0)
5106 06:53:44.533487 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5107 06:53:44.540382 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 06:53:44.543592 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 06:53:44.546784 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 06:53:44.553673 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 06:53:44.556951 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 06:53:44.560518 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 06:53:44.566799 0 15 28 | B1->B0 | 2525 3838 | 0 1 | (0 0) (0 0)
5114 06:53:44.570235 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5115 06:53:44.573664 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 06:53:44.580546 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 06:53:44.583193 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 06:53:44.586520 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 06:53:44.593403 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 06:53:44.596851 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 06:53:44.600451 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5122 06:53:44.603148 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5123 06:53:44.610293 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 06:53:44.613545 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 06:53:44.616748 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 06:53:44.623497 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 06:53:44.626688 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 06:53:44.629920 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 06:53:44.636971 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 06:53:44.640154 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 06:53:44.643696 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 06:53:44.650042 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 06:53:44.653449 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 06:53:44.656646 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 06:53:44.663346 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 06:53:44.667002 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5137 06:53:44.670478 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5138 06:53:44.673267 Total UI for P1: 0, mck2ui 16
5139 06:53:44.676663 best dqsien dly found for B0: ( 1, 2, 24)
5140 06:53:44.683575 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 06:53:44.683655 Total UI for P1: 0, mck2ui 16
5142 06:53:44.690264 best dqsien dly found for B1: ( 1, 2, 28)
5143 06:53:44.693733 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5144 06:53:44.696519 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5145 06:53:44.696618
5146 06:53:44.699988 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5147 06:53:44.703455 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5148 06:53:44.706929 [Gating] SW calibration Done
5149 06:53:44.707009 ==
5150 06:53:44.710374 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 06:53:44.713208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 06:53:44.713288 ==
5153 06:53:44.716688 RX Vref Scan: 0
5154 06:53:44.716767
5155 06:53:44.716829 RX Vref 0 -> 0, step: 1
5156 06:53:44.716887
5157 06:53:44.720000 RX Delay -80 -> 252, step: 8
5158 06:53:44.723210 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5159 06:53:44.729724 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5160 06:53:44.733068 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5161 06:53:44.736478 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5162 06:53:44.739846 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5163 06:53:44.743297 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5164 06:53:44.746823 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5165 06:53:44.752899 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5166 06:53:44.756805 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5167 06:53:44.759917 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5168 06:53:44.762936 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5169 06:53:44.766674 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5170 06:53:44.769691 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5171 06:53:44.776604 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5172 06:53:44.779545 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5173 06:53:44.783014 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5174 06:53:44.783130 ==
5175 06:53:44.786511 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 06:53:44.789367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 06:53:44.789450 ==
5178 06:53:44.792721 DQS Delay:
5179 06:53:44.792800 DQS0 = 0, DQS1 = 0
5180 06:53:44.792862 DQM Delay:
5181 06:53:44.796229 DQM0 = 104, DQM1 = 93
5182 06:53:44.796347 DQ Delay:
5183 06:53:44.799644 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5184 06:53:44.803102 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5185 06:53:44.805912 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5186 06:53:44.809410 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5187 06:53:44.812785
5188 06:53:44.812864
5189 06:53:44.812953 ==
5190 06:53:44.816336 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 06:53:44.819154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 06:53:44.819233 ==
5193 06:53:44.819294
5194 06:53:44.819352
5195 06:53:44.822506 TX Vref Scan disable
5196 06:53:44.822585 == TX Byte 0 ==
5197 06:53:44.829163 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5198 06:53:44.832523 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5199 06:53:44.832612 == TX Byte 1 ==
5200 06:53:44.839252 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5201 06:53:44.842311 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5202 06:53:44.842391 ==
5203 06:53:44.845585 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 06:53:44.849200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 06:53:44.849280 ==
5206 06:53:44.849341
5207 06:53:44.849399
5208 06:53:44.852629 TX Vref Scan disable
5209 06:53:44.856012 == TX Byte 0 ==
5210 06:53:44.859471 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5211 06:53:44.862188 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5212 06:53:44.865549 == TX Byte 1 ==
5213 06:53:44.869407 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5214 06:53:44.872191 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5215 06:53:44.872321
5216 06:53:44.876047 [DATLAT]
5217 06:53:44.876126 Freq=933, CH0 RK0
5218 06:53:44.876188
5219 06:53:44.879312 DATLAT Default: 0xd
5220 06:53:44.879391 0, 0xFFFF, sum = 0
5221 06:53:44.882180 1, 0xFFFF, sum = 0
5222 06:53:44.882261 2, 0xFFFF, sum = 0
5223 06:53:44.885656 3, 0xFFFF, sum = 0
5224 06:53:44.885745 4, 0xFFFF, sum = 0
5225 06:53:44.889379 5, 0xFFFF, sum = 0
5226 06:53:44.889460 6, 0xFFFF, sum = 0
5227 06:53:44.892533 7, 0xFFFF, sum = 0
5228 06:53:44.892617 8, 0xFFFF, sum = 0
5229 06:53:44.895479 9, 0xFFFF, sum = 0
5230 06:53:44.895559 10, 0x0, sum = 1
5231 06:53:44.898998 11, 0x0, sum = 2
5232 06:53:44.899078 12, 0x0, sum = 3
5233 06:53:44.902362 13, 0x0, sum = 4
5234 06:53:44.902442 best_step = 11
5235 06:53:44.902567
5236 06:53:44.902657 ==
5237 06:53:44.905526 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 06:53:44.912272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 06:53:44.912362 ==
5240 06:53:44.912424 RX Vref Scan: 1
5241 06:53:44.912482
5242 06:53:44.915641 RX Vref 0 -> 0, step: 1
5243 06:53:44.915719
5244 06:53:44.919184 RX Delay -53 -> 252, step: 4
5245 06:53:44.919263
5246 06:53:44.921979 Set Vref, RX VrefLevel [Byte0]: 58
5247 06:53:44.925521 [Byte1]: 48
5248 06:53:44.925600
5249 06:53:44.928853 Final RX Vref Byte 0 = 58 to rank0
5250 06:53:44.932104 Final RX Vref Byte 1 = 48 to rank0
5251 06:53:44.935462 Final RX Vref Byte 0 = 58 to rank1
5252 06:53:44.938259 Final RX Vref Byte 1 = 48 to rank1==
5253 06:53:44.941838 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 06:53:44.945311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 06:53:44.945390 ==
5256 06:53:44.948762 DQS Delay:
5257 06:53:44.948840 DQS0 = 0, DQS1 = 0
5258 06:53:44.951899 DQM Delay:
5259 06:53:44.951996 DQM0 = 105, DQM1 = 95
5260 06:53:44.952059 DQ Delay:
5261 06:53:44.955041 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5262 06:53:44.958599 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5263 06:53:44.961997 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =88
5264 06:53:44.969099 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5265 06:53:44.969206
5266 06:53:44.969295
5267 06:53:44.975012 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5268 06:53:44.978514 CH0 RK0: MR19=505, MR18=332B
5269 06:53:44.985081 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5270 06:53:44.985160
5271 06:53:44.988446 ----->DramcWriteLeveling(PI) begin...
5272 06:53:44.988526 ==
5273 06:53:44.991924 Dram Type= 6, Freq= 0, CH_0, rank 1
5274 06:53:44.995442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 06:53:44.995521 ==
5276 06:53:44.998241 Write leveling (Byte 0): 36 => 36
5277 06:53:45.001621 Write leveling (Byte 1): 29 => 29
5278 06:53:45.004969 DramcWriteLeveling(PI) end<-----
5279 06:53:45.005048
5280 06:53:45.005109 ==
5281 06:53:45.008735 Dram Type= 6, Freq= 0, CH_0, rank 1
5282 06:53:45.011830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 06:53:45.011909 ==
5284 06:53:45.015099 [Gating] SW mode calibration
5285 06:53:45.021985 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5286 06:53:45.028475 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5287 06:53:45.031797 0 14 0 | B1->B0 | 3333 3332 | 1 1 | (1 1) (0 0)
5288 06:53:45.035190 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 06:53:45.041807 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 06:53:45.045227 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 06:53:45.048717 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 06:53:45.055029 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 06:53:45.058187 0 14 24 | B1->B0 | 3333 3232 | 1 1 | (0 0) (1 1)
5294 06:53:45.061596 0 14 28 | B1->B0 | 2b2b 3030 | 1 1 | (1 1) (1 0)
5295 06:53:45.068555 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5296 06:53:45.071766 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 06:53:45.075031 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 06:53:45.081443 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 06:53:45.084997 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 06:53:45.088339 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 06:53:45.094929 0 15 24 | B1->B0 | 2525 2625 | 0 1 | (0 0) (0 0)
5302 06:53:45.098330 0 15 28 | B1->B0 | 3535 3333 | 0 0 | (0 0) (0 0)
5303 06:53:45.101788 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5304 06:53:45.108062 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 06:53:45.111613 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 06:53:45.114917 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 06:53:45.121245 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 06:53:45.124566 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 06:53:45.127713 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 06:53:45.134557 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5311 06:53:45.137674 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 06:53:45.141444 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 06:53:45.147693 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 06:53:45.151344 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 06:53:45.154693 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 06:53:45.160982 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 06:53:45.164442 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 06:53:45.167772 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 06:53:45.171088 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 06:53:45.177906 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 06:53:45.181363 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 06:53:45.184559 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 06:53:45.191011 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 06:53:45.194327 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 06:53:45.197684 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 06:53:45.204058 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5327 06:53:45.207586 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5328 06:53:45.211209 Total UI for P1: 0, mck2ui 16
5329 06:53:45.214649 best dqsien dly found for B1: ( 1, 2, 28)
5330 06:53:45.217967 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 06:53:45.221268 Total UI for P1: 0, mck2ui 16
5332 06:53:45.224035 best dqsien dly found for B0: ( 1, 2, 30)
5333 06:53:45.227490 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5334 06:53:45.231089 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5335 06:53:45.231168
5336 06:53:45.237948 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5337 06:53:45.240694 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5338 06:53:45.244628 [Gating] SW calibration Done
5339 06:53:45.244707 ==
5340 06:53:45.247617 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 06:53:45.251015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 06:53:45.251095 ==
5343 06:53:45.251156 RX Vref Scan: 0
5344 06:53:45.251214
5345 06:53:45.254205 RX Vref 0 -> 0, step: 1
5346 06:53:45.254284
5347 06:53:45.257416 RX Delay -80 -> 252, step: 8
5348 06:53:45.261163 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5349 06:53:45.264224 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5350 06:53:45.270773 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5351 06:53:45.274111 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5352 06:53:45.277541 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5353 06:53:45.280846 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5354 06:53:45.284295 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5355 06:53:45.287095 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5356 06:53:45.293729 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5357 06:53:45.297495 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5358 06:53:45.300778 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5359 06:53:45.304153 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5360 06:53:45.307649 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5361 06:53:45.310745 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5362 06:53:45.317399 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5363 06:53:45.320783 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5364 06:53:45.320863 ==
5365 06:53:45.324113 Dram Type= 6, Freq= 0, CH_0, rank 1
5366 06:53:45.326943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5367 06:53:45.327033 ==
5368 06:53:45.327097 DQS Delay:
5369 06:53:45.331010 DQS0 = 0, DQS1 = 0
5370 06:53:45.331089 DQM Delay:
5371 06:53:45.333834 DQM0 = 106, DQM1 = 94
5372 06:53:45.333913 DQ Delay:
5373 06:53:45.337296 DQ0 =103, DQ1 =111, DQ2 =103, DQ3 =103
5374 06:53:45.340614 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5375 06:53:45.344097 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5376 06:53:45.347664 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5377 06:53:45.347743
5378 06:53:45.347805
5379 06:53:45.347862 ==
5380 06:53:45.350389 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 06:53:45.357487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 06:53:45.357567 ==
5383 06:53:45.357630
5384 06:53:45.357687
5385 06:53:45.357743 TX Vref Scan disable
5386 06:53:45.360967 == TX Byte 0 ==
5387 06:53:45.364490 Update DQ dly =721 (2 ,6, 17) DQ OEN =(2 ,3)
5388 06:53:45.367805 Update DQM dly =721 (2 ,6, 17) DQM OEN =(2 ,3)
5389 06:53:45.371196 == TX Byte 1 ==
5390 06:53:45.374224 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5391 06:53:45.378041 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5392 06:53:45.381121 ==
5393 06:53:45.384096 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 06:53:45.387538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 06:53:45.387617 ==
5396 06:53:45.387679
5397 06:53:45.387737
5398 06:53:45.390799 TX Vref Scan disable
5399 06:53:45.390878 == TX Byte 0 ==
5400 06:53:45.397645 Update DQ dly =720 (2 ,6, 16) DQ OEN =(2 ,3)
5401 06:53:45.401073 Update DQM dly =720 (2 ,6, 16) DQM OEN =(2 ,3)
5402 06:53:45.401153 == TX Byte 1 ==
5403 06:53:45.407887 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5404 06:53:45.411241 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5405 06:53:45.411338
5406 06:53:45.411400 [DATLAT]
5407 06:53:45.414085 Freq=933, CH0 RK1
5408 06:53:45.414164
5409 06:53:45.414226 DATLAT Default: 0xb
5410 06:53:45.417294 0, 0xFFFF, sum = 0
5411 06:53:45.417400 1, 0xFFFF, sum = 0
5412 06:53:45.421311 2, 0xFFFF, sum = 0
5413 06:53:45.421405 3, 0xFFFF, sum = 0
5414 06:53:45.424416 4, 0xFFFF, sum = 0
5415 06:53:45.424496 5, 0xFFFF, sum = 0
5416 06:53:45.427700 6, 0xFFFF, sum = 0
5417 06:53:45.431092 7, 0xFFFF, sum = 0
5418 06:53:45.431172 8, 0xFFFF, sum = 0
5419 06:53:45.433962 9, 0xFFFF, sum = 0
5420 06:53:45.434042 10, 0x0, sum = 1
5421 06:53:45.434105 11, 0x0, sum = 2
5422 06:53:45.437468 12, 0x0, sum = 3
5423 06:53:45.437550 13, 0x0, sum = 4
5424 06:53:45.440868 best_step = 11
5425 06:53:45.440947
5426 06:53:45.441009 ==
5427 06:53:45.444202 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 06:53:45.447594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 06:53:45.447673 ==
5430 06:53:45.451141 RX Vref Scan: 0
5431 06:53:45.451220
5432 06:53:45.451289 RX Vref 0 -> 0, step: 1
5433 06:53:45.451351
5434 06:53:45.454039 RX Delay -45 -> 252, step: 4
5435 06:53:45.461369 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5436 06:53:45.464572 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5437 06:53:45.468436 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5438 06:53:45.471097 iDelay=199, Bit 3, Center 102 (11 ~ 194) 184
5439 06:53:45.474713 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5440 06:53:45.481464 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5441 06:53:45.484841 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5442 06:53:45.488339 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5443 06:53:45.491697 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5444 06:53:45.494968 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5445 06:53:45.497969 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5446 06:53:45.504504 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5447 06:53:45.508297 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5448 06:53:45.511705 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5449 06:53:45.514703 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5450 06:53:45.517891 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5451 06:53:45.521264 ==
5452 06:53:45.524520 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 06:53:45.527790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 06:53:45.527870 ==
5455 06:53:45.527933 DQS Delay:
5456 06:53:45.531330 DQS0 = 0, DQS1 = 0
5457 06:53:45.531409 DQM Delay:
5458 06:53:45.534447 DQM0 = 104, DQM1 = 94
5459 06:53:45.534527 DQ Delay:
5460 06:53:45.537667 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5461 06:53:45.541187 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5462 06:53:45.544560 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5463 06:53:45.548048 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5464 06:53:45.548153
5465 06:53:45.548243
5466 06:53:45.557613 [DQSOSCAuto] RK1, (LSB)MR18= 0x2701, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5467 06:53:45.557694 CH0 RK1: MR19=505, MR18=2701
5468 06:53:45.564498 CH0_RK1: MR19=0x505, MR18=0x2701, DQSOSC=409, MR23=63, INC=64, DEC=43
5469 06:53:45.567972 [RxdqsGatingPostProcess] freq 933
5470 06:53:45.574546 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5471 06:53:45.577947 best DQS0 dly(2T, 0.5T) = (0, 10)
5472 06:53:45.581369 best DQS1 dly(2T, 0.5T) = (0, 10)
5473 06:53:45.584659 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5474 06:53:45.588076 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5475 06:53:45.591530 best DQS0 dly(2T, 0.5T) = (0, 10)
5476 06:53:45.591609 best DQS1 dly(2T, 0.5T) = (0, 10)
5477 06:53:45.594303 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5478 06:53:45.597820 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5479 06:53:45.601230 Pre-setting of DQS Precalculation
5480 06:53:45.608174 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5481 06:53:45.608254 ==
5482 06:53:45.611466 Dram Type= 6, Freq= 0, CH_1, rank 0
5483 06:53:45.614652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 06:53:45.614737 ==
5485 06:53:45.620933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5486 06:53:45.628023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5487 06:53:45.630926 [CA 0] Center 36 (6~67) winsize 62
5488 06:53:45.634362 [CA 1] Center 37 (6~68) winsize 63
5489 06:53:45.637640 [CA 2] Center 35 (5~65) winsize 61
5490 06:53:45.641119 [CA 3] Center 34 (4~65) winsize 62
5491 06:53:45.644073 [CA 4] Center 34 (4~65) winsize 62
5492 06:53:45.647512 [CA 5] Center 33 (3~64) winsize 62
5493 06:53:45.647591
5494 06:53:45.651215 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5495 06:53:45.651294
5496 06:53:45.654015 [CATrainingPosCal] consider 1 rank data
5497 06:53:45.657762 u2DelayCellTimex100 = 270/100 ps
5498 06:53:45.660666 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5499 06:53:45.663957 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5500 06:53:45.667534 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5501 06:53:45.670800 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5502 06:53:45.674189 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5503 06:53:45.677481 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5504 06:53:45.677589
5505 06:53:45.680794 CA PerBit enable=1, Macro0, CA PI delay=33
5506 06:53:45.684188
5507 06:53:45.684267 [CBTSetCACLKResult] CA Dly = 33
5508 06:53:45.687493 CS Dly: 6 (0~37)
5509 06:53:45.687572 ==
5510 06:53:45.690966 Dram Type= 6, Freq= 0, CH_1, rank 1
5511 06:53:45.694479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 06:53:45.694559 ==
5513 06:53:45.700750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5514 06:53:45.707022 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5515 06:53:45.710518 [CA 0] Center 37 (6~68) winsize 63
5516 06:53:45.713987 [CA 1] Center 37 (6~68) winsize 63
5517 06:53:45.717495 [CA 2] Center 34 (4~65) winsize 62
5518 06:53:45.720722 [CA 3] Center 34 (4~65) winsize 62
5519 06:53:45.724136 [CA 4] Center 34 (4~65) winsize 62
5520 06:53:45.727557 [CA 5] Center 34 (4~64) winsize 61
5521 06:53:45.727635
5522 06:53:45.730321 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5523 06:53:45.730400
5524 06:53:45.733890 [CATrainingPosCal] consider 2 rank data
5525 06:53:45.737304 u2DelayCellTimex100 = 270/100 ps
5526 06:53:45.740588 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5527 06:53:45.743932 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5528 06:53:45.747177 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5529 06:53:45.750272 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5530 06:53:45.753668 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5531 06:53:45.757522 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5532 06:53:45.757603
5533 06:53:45.763652 CA PerBit enable=1, Macro0, CA PI delay=34
5534 06:53:45.763740
5535 06:53:45.763804 [CBTSetCACLKResult] CA Dly = 34
5536 06:53:45.766974 CS Dly: 7 (0~39)
5537 06:53:45.767054
5538 06:53:45.770412 ----->DramcWriteLeveling(PI) begin...
5539 06:53:45.770497 ==
5540 06:53:45.774040 Dram Type= 6, Freq= 0, CH_1, rank 0
5541 06:53:45.777122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 06:53:45.777202 ==
5543 06:53:45.780258 Write leveling (Byte 0): 26 => 26
5544 06:53:45.783829 Write leveling (Byte 1): 29 => 29
5545 06:53:45.787227 DramcWriteLeveling(PI) end<-----
5546 06:53:45.787305
5547 06:53:45.787367 ==
5548 06:53:45.790791 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 06:53:45.794024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 06:53:45.797191 ==
5551 06:53:45.797270 [Gating] SW mode calibration
5552 06:53:45.807265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5553 06:53:45.810763 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5554 06:53:45.814131 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 06:53:45.820441 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 06:53:45.823709 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 06:53:45.827157 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 06:53:45.833394 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 06:53:45.836860 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5560 06:53:45.840242 0 14 24 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (0 0)
5561 06:53:45.846945 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
5562 06:53:45.850181 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 06:53:45.853693 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 06:53:45.860592 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 06:53:45.863846 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 06:53:45.867299 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 06:53:45.873225 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 06:53:45.876621 0 15 24 | B1->B0 | 2727 3535 | 0 0 | (0 0) (0 0)
5569 06:53:45.880100 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5570 06:53:45.886777 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 06:53:45.890171 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 06:53:45.893452 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 06:53:45.900441 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 06:53:45.903382 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 06:53:45.906922 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 06:53:45.913012 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5577 06:53:45.916568 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5578 06:53:45.919623 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 06:53:45.926404 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 06:53:45.929740 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 06:53:45.933116 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 06:53:45.939395 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 06:53:45.942971 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 06:53:45.946473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 06:53:45.949745 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 06:53:45.955917 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 06:53:45.959185 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 06:53:45.966396 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 06:53:45.969269 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 06:53:45.972631 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 06:53:45.975964 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 06:53:45.982772 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5593 06:53:45.986220 Total UI for P1: 0, mck2ui 16
5594 06:53:45.989581 best dqsien dly found for B0: ( 1, 2, 22)
5595 06:53:45.993033 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 06:53:45.995766 Total UI for P1: 0, mck2ui 16
5597 06:53:45.999128 best dqsien dly found for B1: ( 1, 2, 24)
5598 06:53:46.002541 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5599 06:53:46.005985 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5600 06:53:46.006065
5601 06:53:46.009439 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5602 06:53:46.012790 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5603 06:53:46.016099 [Gating] SW calibration Done
5604 06:53:46.016179 ==
5605 06:53:46.019350 Dram Type= 6, Freq= 0, CH_1, rank 0
5606 06:53:46.025970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 06:53:46.026050 ==
5608 06:53:46.026113 RX Vref Scan: 0
5609 06:53:46.026171
5610 06:53:46.029200 RX Vref 0 -> 0, step: 1
5611 06:53:46.029280
5612 06:53:46.032139 RX Delay -80 -> 252, step: 8
5613 06:53:46.035878 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5614 06:53:46.038775 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5615 06:53:46.042589 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5616 06:53:46.045507 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5617 06:53:46.048770 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5618 06:53:46.055512 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5619 06:53:46.058978 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5620 06:53:46.062241 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5621 06:53:46.065749 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5622 06:53:46.068978 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5623 06:53:46.072334 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5624 06:53:46.078638 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5625 06:53:46.082114 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5626 06:53:46.085668 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5627 06:53:46.088949 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5628 06:53:46.095806 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5629 06:53:46.095886 ==
5630 06:53:46.098565 Dram Type= 6, Freq= 0, CH_1, rank 0
5631 06:53:46.101994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 06:53:46.102075 ==
5633 06:53:46.102138 DQS Delay:
5634 06:53:46.105338 DQS0 = 0, DQS1 = 0
5635 06:53:46.105418 DQM Delay:
5636 06:53:46.108808 DQM0 = 101, DQM1 = 99
5637 06:53:46.108889 DQ Delay:
5638 06:53:46.112243 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5639 06:53:46.115609 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5640 06:53:46.118462 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5641 06:53:46.121930 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5642 06:53:46.122009
5643 06:53:46.122071
5644 06:53:46.122128 ==
5645 06:53:46.125291 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 06:53:46.128737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 06:53:46.132211 ==
5648 06:53:46.132312
5649 06:53:46.132390
5650 06:53:46.132449 TX Vref Scan disable
5651 06:53:46.135501 == TX Byte 0 ==
5652 06:53:46.138651 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5653 06:53:46.141818 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5654 06:53:46.145275 == TX Byte 1 ==
5655 06:53:46.148411 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5656 06:53:46.152007 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5657 06:53:46.154872 ==
5658 06:53:46.158484 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 06:53:46.161946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 06:53:46.162026 ==
5661 06:53:46.162089
5662 06:53:46.162147
5663 06:53:46.164801 TX Vref Scan disable
5664 06:53:46.164880 == TX Byte 0 ==
5665 06:53:46.171512 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5666 06:53:46.175126 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5667 06:53:46.175206 == TX Byte 1 ==
5668 06:53:46.181672 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5669 06:53:46.185120 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5670 06:53:46.185199
5671 06:53:46.185261 [DATLAT]
5672 06:53:46.188404 Freq=933, CH1 RK0
5673 06:53:46.188484
5674 06:53:46.188545 DATLAT Default: 0xd
5675 06:53:46.191645 0, 0xFFFF, sum = 0
5676 06:53:46.191725 1, 0xFFFF, sum = 0
5677 06:53:46.194936 2, 0xFFFF, sum = 0
5678 06:53:46.195017 3, 0xFFFF, sum = 0
5679 06:53:46.198138 4, 0xFFFF, sum = 0
5680 06:53:46.198218 5, 0xFFFF, sum = 0
5681 06:53:46.201934 6, 0xFFFF, sum = 0
5682 06:53:46.202014 7, 0xFFFF, sum = 0
5683 06:53:46.204721 8, 0xFFFF, sum = 0
5684 06:53:46.208211 9, 0xFFFF, sum = 0
5685 06:53:46.208322 10, 0x0, sum = 1
5686 06:53:46.208389 11, 0x0, sum = 2
5687 06:53:46.211800 12, 0x0, sum = 3
5688 06:53:46.211880 13, 0x0, sum = 4
5689 06:53:46.215160 best_step = 11
5690 06:53:46.215239
5691 06:53:46.215301 ==
5692 06:53:46.218604 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 06:53:46.221338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 06:53:46.221444 ==
5695 06:53:46.225395 RX Vref Scan: 1
5696 06:53:46.225474
5697 06:53:46.225536 RX Vref 0 -> 0, step: 1
5698 06:53:46.225595
5699 06:53:46.228149 RX Delay -45 -> 252, step: 4
5700 06:53:46.228228
5701 06:53:46.231688 Set Vref, RX VrefLevel [Byte0]: 57
5702 06:53:46.234515 [Byte1]: 55
5703 06:53:46.238648
5704 06:53:46.238728 Final RX Vref Byte 0 = 57 to rank0
5705 06:53:46.242083 Final RX Vref Byte 1 = 55 to rank0
5706 06:53:46.245446 Final RX Vref Byte 0 = 57 to rank1
5707 06:53:46.248786 Final RX Vref Byte 1 = 55 to rank1==
5708 06:53:46.252086 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 06:53:46.258747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 06:53:46.258830 ==
5711 06:53:46.258893 DQS Delay:
5712 06:53:46.258952 DQS0 = 0, DQS1 = 0
5713 06:53:46.262233 DQM Delay:
5714 06:53:46.262313 DQM0 = 103, DQM1 = 99
5715 06:53:46.265469 DQ Delay:
5716 06:53:46.268791 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5717 06:53:46.271984 DQ4 =102, DQ5 =114, DQ6 =112, DQ7 =104
5718 06:53:46.275684 DQ8 =90, DQ9 =92, DQ10 =102, DQ11 =94
5719 06:53:46.279030 DQ12 =104, DQ13 =106, DQ14 =106, DQ15 =104
5720 06:53:46.279108
5721 06:53:46.279169
5722 06:53:46.285582 [DQSOSCAuto] RK0, (LSB)MR18= 0x1930, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5723 06:53:46.289051 CH1 RK0: MR19=505, MR18=1930
5724 06:53:46.295315 CH1_RK0: MR19=0x505, MR18=0x1930, DQSOSC=406, MR23=63, INC=65, DEC=43
5725 06:53:46.295395
5726 06:53:46.298909 ----->DramcWriteLeveling(PI) begin...
5727 06:53:46.299019 ==
5728 06:53:46.301981 Dram Type= 6, Freq= 0, CH_1, rank 1
5729 06:53:46.305664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 06:53:46.305743 ==
5731 06:53:46.308643 Write leveling (Byte 0): 26 => 26
5732 06:53:46.312461 Write leveling (Byte 1): 31 => 31
5733 06:53:46.315820 DramcWriteLeveling(PI) end<-----
5734 06:53:46.315898
5735 06:53:46.315960 ==
5736 06:53:46.318604 Dram Type= 6, Freq= 0, CH_1, rank 1
5737 06:53:46.321999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 06:53:46.325544 ==
5739 06:53:46.325623 [Gating] SW mode calibration
5740 06:53:46.335857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5741 06:53:46.338712 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5742 06:53:46.342237 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 06:53:46.349089 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 06:53:46.352421 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 06:53:46.355712 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 06:53:46.362076 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 06:53:46.365413 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5748 06:53:46.368840 0 14 24 | B1->B0 | 2828 3030 | 0 0 | (0 0) (0 0)
5749 06:53:46.375638 0 14 28 | B1->B0 | 2323 2828 | 0 0 | (1 0) (0 0)
5750 06:53:46.378889 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 06:53:46.382227 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 06:53:46.388429 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 06:53:46.391735 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 06:53:46.395562 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 06:53:46.401786 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 06:53:46.405264 0 15 24 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 0)
5757 06:53:46.408539 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5758 06:53:46.415345 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 06:53:46.418886 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 06:53:46.421924 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 06:53:46.425364 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 06:53:46.432007 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 06:53:46.435730 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 06:53:46.439159 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5765 06:53:46.445508 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5766 06:53:46.448449 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 06:53:46.451900 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 06:53:46.458631 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 06:53:46.462035 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 06:53:46.465461 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 06:53:46.472107 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 06:53:46.474939 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 06:53:46.478402 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 06:53:46.485048 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 06:53:46.488414 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 06:53:46.491811 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 06:53:46.498763 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 06:53:46.502199 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 06:53:46.505481 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5780 06:53:46.512049 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5781 06:53:46.515445 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5782 06:53:46.518808 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 06:53:46.521581 Total UI for P1: 0, mck2ui 16
5784 06:53:46.525008 best dqsien dly found for B0: ( 1, 2, 28)
5785 06:53:46.528466 Total UI for P1: 0, mck2ui 16
5786 06:53:46.531627 best dqsien dly found for B1: ( 1, 2, 24)
5787 06:53:46.535550 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5788 06:53:46.538768 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5789 06:53:46.538848
5790 06:53:46.541991 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5791 06:53:46.548267 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5792 06:53:46.548390 [Gating] SW calibration Done
5793 06:53:46.548453 ==
5794 06:53:46.551875 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 06:53:46.558630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 06:53:46.558712 ==
5797 06:53:46.558774 RX Vref Scan: 0
5798 06:53:46.558832
5799 06:53:46.562034 RX Vref 0 -> 0, step: 1
5800 06:53:46.562118
5801 06:53:46.565331 RX Delay -80 -> 252, step: 8
5802 06:53:46.568198 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5803 06:53:46.571593 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5804 06:53:46.574995 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5805 06:53:46.578268 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5806 06:53:46.585007 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5807 06:53:46.588397 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5808 06:53:46.591640 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5809 06:53:46.595130 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5810 06:53:46.598568 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5811 06:53:46.601314 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5812 06:53:46.608304 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5813 06:53:46.611471 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5814 06:53:46.614756 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5815 06:53:46.618532 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5816 06:53:46.621601 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5817 06:53:46.628352 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5818 06:53:46.628432 ==
5819 06:53:46.631550 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 06:53:46.635056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 06:53:46.635137 ==
5822 06:53:46.635200 DQS Delay:
5823 06:53:46.638270 DQS0 = 0, DQS1 = 0
5824 06:53:46.638349 DQM Delay:
5825 06:53:46.641723 DQM0 = 105, DQM1 = 99
5826 06:53:46.641803 DQ Delay:
5827 06:53:46.645134 DQ0 =107, DQ1 =103, DQ2 =95, DQ3 =99
5828 06:53:46.648561 DQ4 =99, DQ5 =119, DQ6 =119, DQ7 =103
5829 06:53:46.651272 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5830 06:53:46.654617 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5831 06:53:46.654697
5832 06:53:46.654759
5833 06:53:46.654816 ==
5834 06:53:46.657834 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 06:53:46.664508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 06:53:46.664589 ==
5837 06:53:46.664652
5838 06:53:46.664709
5839 06:53:46.664764 TX Vref Scan disable
5840 06:53:46.668759 == TX Byte 0 ==
5841 06:53:46.671715 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5842 06:53:46.675186 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5843 06:53:46.678347 == TX Byte 1 ==
5844 06:53:46.681850 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5845 06:53:46.685394 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5846 06:53:46.688913 ==
5847 06:53:46.691734 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 06:53:46.695217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 06:53:46.695325 ==
5850 06:53:46.695415
5851 06:53:46.695501
5852 06:53:46.698590 TX Vref Scan disable
5853 06:53:46.698675 == TX Byte 0 ==
5854 06:53:46.704906 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5855 06:53:46.708589 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5856 06:53:46.708669 == TX Byte 1 ==
5857 06:53:46.714997 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5858 06:53:46.718369 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5859 06:53:46.718473
5860 06:53:46.718564 [DATLAT]
5861 06:53:46.721928 Freq=933, CH1 RK1
5862 06:53:46.722035
5863 06:53:46.722132 DATLAT Default: 0xb
5864 06:53:46.725531 0, 0xFFFF, sum = 0
5865 06:53:46.725612 1, 0xFFFF, sum = 0
5866 06:53:46.728167 2, 0xFFFF, sum = 0
5867 06:53:46.728276 3, 0xFFFF, sum = 0
5868 06:53:46.732044 4, 0xFFFF, sum = 0
5869 06:53:46.732114 5, 0xFFFF, sum = 0
5870 06:53:46.734814 6, 0xFFFF, sum = 0
5871 06:53:46.734887 7, 0xFFFF, sum = 0
5872 06:53:46.738279 8, 0xFFFF, sum = 0
5873 06:53:46.742007 9, 0xFFFF, sum = 0
5874 06:53:46.742114 10, 0x0, sum = 1
5875 06:53:46.742207 11, 0x0, sum = 2
5876 06:53:46.744993 12, 0x0, sum = 3
5877 06:53:46.745070 13, 0x0, sum = 4
5878 06:53:46.748473 best_step = 11
5879 06:53:46.748546
5880 06:53:46.748604 ==
5881 06:53:46.751891 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 06:53:46.754778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 06:53:46.754859 ==
5884 06:53:46.758432 RX Vref Scan: 0
5885 06:53:46.758537
5886 06:53:46.758611 RX Vref 0 -> 0, step: 1
5887 06:53:46.758691
5888 06:53:46.761341 RX Delay -45 -> 252, step: 4
5889 06:53:46.768516 iDelay=203, Bit 0, Center 108 (23 ~ 194) 172
5890 06:53:46.772077 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5891 06:53:46.775520 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5892 06:53:46.778992 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5893 06:53:46.782195 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5894 06:53:46.789065 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5895 06:53:46.792095 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5896 06:53:46.795349 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5897 06:53:46.798929 iDelay=203, Bit 8, Center 90 (11 ~ 170) 160
5898 06:53:46.802072 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5899 06:53:46.809498 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5900 06:53:46.812411 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5901 06:53:46.816168 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5902 06:53:46.819574 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5903 06:53:46.822738 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5904 06:53:46.829213 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5905 06:53:46.829726 ==
5906 06:53:46.832452 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 06:53:46.836050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 06:53:46.836622 ==
5909 06:53:46.837044 DQS Delay:
5910 06:53:46.839315 DQS0 = 0, DQS1 = 0
5911 06:53:46.839848 DQM Delay:
5912 06:53:46.842457 DQM0 = 104, DQM1 = 100
5913 06:53:46.842867 DQ Delay:
5914 06:53:46.845793 DQ0 =108, DQ1 =102, DQ2 =94, DQ3 =100
5915 06:53:46.849160 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5916 06:53:46.852278 DQ8 =90, DQ9 =90, DQ10 =98, DQ11 =94
5917 06:53:46.856029 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5918 06:53:46.856624
5919 06:53:46.856986
5920 06:53:46.865609 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5921 06:53:46.868844 CH1 RK1: MR19=505, MR18=2E02
5922 06:53:46.872251 CH1_RK1: MR19=0x505, MR18=0x2E02, DQSOSC=407, MR23=63, INC=65, DEC=43
5923 06:53:46.875879 [RxdqsGatingPostProcess] freq 933
5924 06:53:46.882692 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5925 06:53:46.885853 best DQS0 dly(2T, 0.5T) = (0, 10)
5926 06:53:46.889719 best DQS1 dly(2T, 0.5T) = (0, 10)
5927 06:53:46.892261 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5928 06:53:46.895962 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5929 06:53:46.899120 best DQS0 dly(2T, 0.5T) = (0, 10)
5930 06:53:46.902545 best DQS1 dly(2T, 0.5T) = (0, 10)
5931 06:53:46.905492 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5932 06:53:46.905971 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5933 06:53:46.909350 Pre-setting of DQS Precalculation
5934 06:53:46.915807 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5935 06:53:46.922171 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5936 06:53:46.929305 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5937 06:53:46.929906
5938 06:53:46.930263
5939 06:53:46.932205 [Calibration Summary] 1866 Mbps
5940 06:53:46.935895 CH 0, Rank 0
5941 06:53:46.936662 SW Impedance : PASS
5942 06:53:46.938890 DUTY Scan : NO K
5943 06:53:46.942427 ZQ Calibration : PASS
5944 06:53:46.943015 Jitter Meter : NO K
5945 06:53:46.945501 CBT Training : PASS
5946 06:53:46.945955 Write leveling : PASS
5947 06:53:46.948777 RX DQS gating : PASS
5948 06:53:46.951978 RX DQ/DQS(RDDQC) : PASS
5949 06:53:46.952605 TX DQ/DQS : PASS
5950 06:53:46.955379 RX DATLAT : PASS
5951 06:53:46.958731 RX DQ/DQS(Engine): PASS
5952 06:53:46.959313 TX OE : NO K
5953 06:53:46.962180 All Pass.
5954 06:53:46.962587
5955 06:53:46.962913 CH 0, Rank 1
5956 06:53:46.965191 SW Impedance : PASS
5957 06:53:46.965601 DUTY Scan : NO K
5958 06:53:46.968888 ZQ Calibration : PASS
5959 06:53:46.972374 Jitter Meter : NO K
5960 06:53:46.972800 CBT Training : PASS
5961 06:53:46.975187 Write leveling : PASS
5962 06:53:46.978834 RX DQS gating : PASS
5963 06:53:46.979351 RX DQ/DQS(RDDQC) : PASS
5964 06:53:46.982372 TX DQ/DQS : PASS
5965 06:53:46.985410 RX DATLAT : PASS
5966 06:53:46.985823 RX DQ/DQS(Engine): PASS
5967 06:53:46.988654 TX OE : NO K
5968 06:53:46.989070 All Pass.
5969 06:53:46.989396
5970 06:53:46.992512 CH 1, Rank 0
5971 06:53:46.993070 SW Impedance : PASS
5972 06:53:46.995270 DUTY Scan : NO K
5973 06:53:46.998466 ZQ Calibration : PASS
5974 06:53:46.998926 Jitter Meter : NO K
5975 06:53:47.002054 CBT Training : PASS
5976 06:53:47.002599 Write leveling : PASS
5977 06:53:47.005212 RX DQS gating : PASS
5978 06:53:47.008949 RX DQ/DQS(RDDQC) : PASS
5979 06:53:47.009500 TX DQ/DQS : PASS
5980 06:53:47.012235 RX DATLAT : PASS
5981 06:53:47.015877 RX DQ/DQS(Engine): PASS
5982 06:53:47.016474 TX OE : NO K
5983 06:53:47.019080 All Pass.
5984 06:53:47.019619
5985 06:53:47.019981 CH 1, Rank 1
5986 06:53:47.022088 SW Impedance : PASS
5987 06:53:47.022543 DUTY Scan : NO K
5988 06:53:47.024950 ZQ Calibration : PASS
5989 06:53:47.028613 Jitter Meter : NO K
5990 06:53:47.029162 CBT Training : PASS
5991 06:53:47.031738 Write leveling : PASS
5992 06:53:47.034950 RX DQS gating : PASS
5993 06:53:47.035493 RX DQ/DQS(RDDQC) : PASS
5994 06:53:47.038542 TX DQ/DQS : PASS
5995 06:53:47.041946 RX DATLAT : PASS
5996 06:53:47.042495 RX DQ/DQS(Engine): PASS
5997 06:53:47.045315 TX OE : NO K
5998 06:53:47.045783 All Pass.
5999 06:53:47.046137
6000 06:53:47.048339 DramC Write-DBI off
6001 06:53:47.051655 PER_BANK_REFRESH: Hybrid Mode
6002 06:53:47.052206 TX_TRACKING: ON
6003 06:53:47.061839 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6004 06:53:47.065131 [FAST_K] Save calibration result to emmc
6005 06:53:47.068419 dramc_set_vcore_voltage set vcore to 650000
6006 06:53:47.071488 Read voltage for 400, 6
6007 06:53:47.071942 Vio18 = 0
6008 06:53:47.072326 Vcore = 650000
6009 06:53:47.075007 Vdram = 0
6010 06:53:47.075420 Vddq = 0
6011 06:53:47.075751 Vmddr = 0
6012 06:53:47.082059 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6013 06:53:47.084688 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6014 06:53:47.088234 MEM_TYPE=3, freq_sel=20
6015 06:53:47.091872 sv_algorithm_assistance_LP4_800
6016 06:53:47.094924 ============ PULL DRAM RESETB DOWN ============
6017 06:53:47.098272 ========== PULL DRAM RESETB DOWN end =========
6018 06:53:47.104735 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6019 06:53:47.107952 ===================================
6020 06:53:47.108445 LPDDR4 DRAM CONFIGURATION
6021 06:53:47.111632 ===================================
6022 06:53:47.114529 EX_ROW_EN[0] = 0x0
6023 06:53:47.117849 EX_ROW_EN[1] = 0x0
6024 06:53:47.118303 LP4Y_EN = 0x0
6025 06:53:47.121531 WORK_FSP = 0x0
6026 06:53:47.122080 WL = 0x2
6027 06:53:47.124701 RL = 0x2
6028 06:53:47.125158 BL = 0x2
6029 06:53:47.128319 RPST = 0x0
6030 06:53:47.128873 RD_PRE = 0x0
6031 06:53:47.131441 WR_PRE = 0x1
6032 06:53:47.131895 WR_PST = 0x0
6033 06:53:47.134962 DBI_WR = 0x0
6034 06:53:47.135418 DBI_RD = 0x0
6035 06:53:47.137622 OTF = 0x1
6036 06:53:47.141112 ===================================
6037 06:53:47.144355 ===================================
6038 06:53:47.144980 ANA top config
6039 06:53:47.147936 ===================================
6040 06:53:47.151261 DLL_ASYNC_EN = 0
6041 06:53:47.154491 ALL_SLAVE_EN = 1
6042 06:53:47.157851 NEW_RANK_MODE = 1
6043 06:53:47.158315 DLL_IDLE_MODE = 1
6044 06:53:47.161104 LP45_APHY_COMB_EN = 1
6045 06:53:47.164650 TX_ODT_DIS = 1
6046 06:53:47.167967 NEW_8X_MODE = 1
6047 06:53:47.171214 ===================================
6048 06:53:47.174755 ===================================
6049 06:53:47.177542 data_rate = 800
6050 06:53:47.177959 CKR = 1
6051 06:53:47.181075 DQ_P2S_RATIO = 4
6052 06:53:47.184253 ===================================
6053 06:53:47.187785 CA_P2S_RATIO = 4
6054 06:53:47.191316 DQ_CA_OPEN = 0
6055 06:53:47.194289 DQ_SEMI_OPEN = 1
6056 06:53:47.194721 CA_SEMI_OPEN = 1
6057 06:53:47.197592 CA_FULL_RATE = 0
6058 06:53:47.201207 DQ_CKDIV4_EN = 0
6059 06:53:47.204335 CA_CKDIV4_EN = 1
6060 06:53:47.207528 CA_PREDIV_EN = 0
6061 06:53:47.210961 PH8_DLY = 0
6062 06:53:47.211505 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6063 06:53:47.214495 DQ_AAMCK_DIV = 0
6064 06:53:47.218016 CA_AAMCK_DIV = 0
6065 06:53:47.221020 CA_ADMCK_DIV = 4
6066 06:53:47.224500 DQ_TRACK_CA_EN = 0
6067 06:53:47.227888 CA_PICK = 800
6068 06:53:47.231254 CA_MCKIO = 400
6069 06:53:47.231672 MCKIO_SEMI = 400
6070 06:53:47.234733 PLL_FREQ = 3016
6071 06:53:47.237697 DQ_UI_PI_RATIO = 32
6072 06:53:47.241126 CA_UI_PI_RATIO = 32
6073 06:53:47.244068 ===================================
6074 06:53:47.247563 ===================================
6075 06:53:47.250918 memory_type:LPDDR4
6076 06:53:47.251561 GP_NUM : 10
6077 06:53:47.254317 SRAM_EN : 1
6078 06:53:47.257602 MD32_EN : 0
6079 06:53:47.260715 ===================================
6080 06:53:47.261289 [ANA_INIT] >>>>>>>>>>>>>>
6081 06:53:47.263987 <<<<<< [CONFIGURE PHASE]: ANA_TX
6082 06:53:47.267282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6083 06:53:47.270734 ===================================
6084 06:53:47.273539 data_rate = 800,PCW = 0X7400
6085 06:53:47.277052 ===================================
6086 06:53:47.280483 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6087 06:53:47.287100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6088 06:53:47.297342 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6089 06:53:47.300594 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6090 06:53:47.303823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6091 06:53:47.310327 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6092 06:53:47.310756 [ANA_INIT] flow start
6093 06:53:47.313972 [ANA_INIT] PLL >>>>>>>>
6094 06:53:47.314386 [ANA_INIT] PLL <<<<<<<<
6095 06:53:47.317542 [ANA_INIT] MIDPI >>>>>>>>
6096 06:53:47.320264 [ANA_INIT] MIDPI <<<<<<<<
6097 06:53:47.324210 [ANA_INIT] DLL >>>>>>>>
6098 06:53:47.324824 [ANA_INIT] flow end
6099 06:53:47.327412 ============ LP4 DIFF to SE enter ============
6100 06:53:47.333541 ============ LP4 DIFF to SE exit ============
6101 06:53:47.333979 [ANA_INIT] <<<<<<<<<<<<<
6102 06:53:47.337000 [Flow] Enable top DCM control >>>>>
6103 06:53:47.340546 [Flow] Enable top DCM control <<<<<
6104 06:53:47.343902 Enable DLL master slave shuffle
6105 06:53:47.350396 ==============================================================
6106 06:53:47.351021 Gating Mode config
6107 06:53:47.356679 ==============================================================
6108 06:53:47.360035 Config description:
6109 06:53:47.369990 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6110 06:53:47.376876 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6111 06:53:47.380274 SELPH_MODE 0: By rank 1: By Phase
6112 06:53:47.386777 ==============================================================
6113 06:53:47.390161 GAT_TRACK_EN = 0
6114 06:53:47.393573 RX_GATING_MODE = 2
6115 06:53:47.393985 RX_GATING_TRACK_MODE = 2
6116 06:53:47.396793 SELPH_MODE = 1
6117 06:53:47.400149 PICG_EARLY_EN = 1
6118 06:53:47.403655 VALID_LAT_VALUE = 1
6119 06:53:47.409913 ==============================================================
6120 06:53:47.413193 Enter into Gating configuration >>>>
6121 06:53:47.416624 Exit from Gating configuration <<<<
6122 06:53:47.420026 Enter into DVFS_PRE_config >>>>>
6123 06:53:47.430182 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6124 06:53:47.433472 Exit from DVFS_PRE_config <<<<<
6125 06:53:47.436457 Enter into PICG configuration >>>>
6126 06:53:47.440080 Exit from PICG configuration <<<<
6127 06:53:47.443076 [RX_INPUT] configuration >>>>>
6128 06:53:47.446376 [RX_INPUT] configuration <<<<<
6129 06:53:47.450021 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6130 06:53:47.456444 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6131 06:53:47.462732 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6132 06:53:47.469799 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6133 06:53:47.475970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 06:53:47.479252 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 06:53:47.485875 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6136 06:53:47.489251 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6137 06:53:47.492755 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6138 06:53:47.496061 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6139 06:53:47.499547 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6140 06:53:47.506119 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6141 06:53:47.509919 ===================================
6142 06:53:47.512469 LPDDR4 DRAM CONFIGURATION
6143 06:53:47.515772 ===================================
6144 06:53:47.516187 EX_ROW_EN[0] = 0x0
6145 06:53:47.519125 EX_ROW_EN[1] = 0x0
6146 06:53:47.519541 LP4Y_EN = 0x0
6147 06:53:47.522874 WORK_FSP = 0x0
6148 06:53:47.523407 WL = 0x2
6149 06:53:47.526254 RL = 0x2
6150 06:53:47.526774 BL = 0x2
6151 06:53:47.529641 RPST = 0x0
6152 06:53:47.530136 RD_PRE = 0x0
6153 06:53:47.533035 WR_PRE = 0x1
6154 06:53:47.533505 WR_PST = 0x0
6155 06:53:47.535725 DBI_WR = 0x0
6156 06:53:47.536161 DBI_RD = 0x0
6157 06:53:47.539238 OTF = 0x1
6158 06:53:47.542798 ===================================
6159 06:53:47.546150 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6160 06:53:47.549469 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6161 06:53:47.555960 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6162 06:53:47.559366 ===================================
6163 06:53:47.559796 LPDDR4 DRAM CONFIGURATION
6164 06:53:47.562599 ===================================
6165 06:53:47.566147 EX_ROW_EN[0] = 0x10
6166 06:53:47.569186 EX_ROW_EN[1] = 0x0
6167 06:53:47.569622 LP4Y_EN = 0x0
6168 06:53:47.572875 WORK_FSP = 0x0
6169 06:53:47.573287 WL = 0x2
6170 06:53:47.575748 RL = 0x2
6171 06:53:47.576169 BL = 0x2
6172 06:53:47.579078 RPST = 0x0
6173 06:53:47.579546 RD_PRE = 0x0
6174 06:53:47.582506 WR_PRE = 0x1
6175 06:53:47.582922 WR_PST = 0x0
6176 06:53:47.585929 DBI_WR = 0x0
6177 06:53:47.586344 DBI_RD = 0x0
6178 06:53:47.588946 OTF = 0x1
6179 06:53:47.592623 ===================================
6180 06:53:47.599180 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6181 06:53:47.602733 nWR fixed to 30
6182 06:53:47.603153 [ModeRegInit_LP4] CH0 RK0
6183 06:53:47.606118 [ModeRegInit_LP4] CH0 RK1
6184 06:53:47.609539 [ModeRegInit_LP4] CH1 RK0
6185 06:53:47.612984 [ModeRegInit_LP4] CH1 RK1
6186 06:53:47.613475 match AC timing 19
6187 06:53:47.619248 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6188 06:53:47.622686 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6189 06:53:47.626042 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6190 06:53:47.632359 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6191 06:53:47.635663 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6192 06:53:47.636109 ==
6193 06:53:47.639130 Dram Type= 6, Freq= 0, CH_0, rank 0
6194 06:53:47.642516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6195 06:53:47.642939 ==
6196 06:53:47.648826 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6197 06:53:47.655652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6198 06:53:47.658967 [CA 0] Center 36 (8~64) winsize 57
6199 06:53:47.659379 [CA 1] Center 36 (8~64) winsize 57
6200 06:53:47.662244 [CA 2] Center 36 (8~64) winsize 57
6201 06:53:47.665747 [CA 3] Center 36 (8~64) winsize 57
6202 06:53:47.668604 [CA 4] Center 36 (8~64) winsize 57
6203 06:53:47.672012 [CA 5] Center 36 (8~64) winsize 57
6204 06:53:47.672627
6205 06:53:47.675437 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6206 06:53:47.675848
6207 06:53:47.682571 [CATrainingPosCal] consider 1 rank data
6208 06:53:47.683094 u2DelayCellTimex100 = 270/100 ps
6209 06:53:47.688603 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 06:53:47.691892 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 06:53:47.695251 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 06:53:47.698819 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 06:53:47.701694 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 06:53:47.705046 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 06:53:47.705460
6216 06:53:47.708775 CA PerBit enable=1, Macro0, CA PI delay=36
6217 06:53:47.709186
6218 06:53:47.712057 [CBTSetCACLKResult] CA Dly = 36
6219 06:53:47.715080 CS Dly: 1 (0~32)
6220 06:53:47.715492 ==
6221 06:53:47.718816 Dram Type= 6, Freq= 0, CH_0, rank 1
6222 06:53:47.721861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6223 06:53:47.722273 ==
6224 06:53:47.728733 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6225 06:53:47.731948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6226 06:53:47.735197 [CA 0] Center 36 (8~64) winsize 57
6227 06:53:47.738605 [CA 1] Center 36 (8~64) winsize 57
6228 06:53:47.742053 [CA 2] Center 36 (8~64) winsize 57
6229 06:53:47.744978 [CA 3] Center 36 (8~64) winsize 57
6230 06:53:47.748589 [CA 4] Center 36 (8~64) winsize 57
6231 06:53:47.752157 [CA 5] Center 36 (8~64) winsize 57
6232 06:53:47.752749
6233 06:53:47.755493 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6234 06:53:47.755907
6235 06:53:47.758316 [CATrainingPosCal] consider 2 rank data
6236 06:53:47.761717 u2DelayCellTimex100 = 270/100 ps
6237 06:53:47.765404 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 06:53:47.768137 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 06:53:47.771748 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 06:53:47.775050 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 06:53:47.781872 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 06:53:47.784766 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 06:53:47.785177
6244 06:53:47.788127 CA PerBit enable=1, Macro0, CA PI delay=36
6245 06:53:47.788599
6246 06:53:47.791776 [CBTSetCACLKResult] CA Dly = 36
6247 06:53:47.792333 CS Dly: 1 (0~32)
6248 06:53:47.792678
6249 06:53:47.794795 ----->DramcWriteLeveling(PI) begin...
6250 06:53:47.795213 ==
6251 06:53:47.798332 Dram Type= 6, Freq= 0, CH_0, rank 0
6252 06:53:47.805196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 06:53:47.805620 ==
6254 06:53:47.805949 Write leveling (Byte 0): 40 => 8
6255 06:53:47.808880 Write leveling (Byte 1): 40 => 8
6256 06:53:47.811557 DramcWriteLeveling(PI) end<-----
6257 06:53:47.811969
6258 06:53:47.812326 ==
6259 06:53:47.814922 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 06:53:47.822218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 06:53:47.822778 ==
6262 06:53:47.824910 [Gating] SW mode calibration
6263 06:53:47.831641 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6264 06:53:47.834859 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6265 06:53:47.841493 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6266 06:53:47.844785 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 06:53:47.848363 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 06:53:47.854960 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 06:53:47.858249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 06:53:47.861616 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 06:53:47.868254 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 06:53:47.871565 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 06:53:47.874867 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 06:53:47.877604 Total UI for P1: 0, mck2ui 16
6275 06:53:47.880968 best dqsien dly found for B0: ( 0, 14, 24)
6276 06:53:47.884479 Total UI for P1: 0, mck2ui 16
6277 06:53:47.887855 best dqsien dly found for B1: ( 0, 14, 24)
6278 06:53:47.891638 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6279 06:53:47.894608 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6280 06:53:47.895033
6281 06:53:47.901348 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6282 06:53:47.904488 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6283 06:53:47.904908 [Gating] SW calibration Done
6284 06:53:47.907336 ==
6285 06:53:47.910738 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 06:53:47.914196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 06:53:47.914615 ==
6288 06:53:47.914945 RX Vref Scan: 0
6289 06:53:47.915246
6290 06:53:47.917779 RX Vref 0 -> 0, step: 1
6291 06:53:47.918193
6292 06:53:47.921339 RX Delay -410 -> 252, step: 16
6293 06:53:47.924101 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6294 06:53:47.927457 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6295 06:53:47.934351 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6296 06:53:47.937048 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6297 06:53:47.940913 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6298 06:53:47.944442 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6299 06:53:47.950494 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6300 06:53:47.954205 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6301 06:53:47.957674 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6302 06:53:47.961019 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6303 06:53:47.967402 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6304 06:53:47.970676 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6305 06:53:47.973799 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6306 06:53:47.980529 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6307 06:53:47.984118 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6308 06:53:47.986926 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6309 06:53:47.987331 ==
6310 06:53:47.991027 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 06:53:47.993990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 06:53:47.996894 ==
6313 06:53:47.997432 DQS Delay:
6314 06:53:47.997897 DQS0 = 27, DQS1 = 35
6315 06:53:48.000371 DQM Delay:
6316 06:53:48.000780 DQM0 = 11, DQM1 = 12
6317 06:53:48.003712 DQ Delay:
6318 06:53:48.004117 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6319 06:53:48.007385 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6320 06:53:48.010443 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6321 06:53:48.014008 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6322 06:53:48.014498
6323 06:53:48.014822
6324 06:53:48.015114 ==
6325 06:53:48.016868 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 06:53:48.023957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 06:53:48.024521 ==
6328 06:53:48.024852
6329 06:53:48.025152
6330 06:53:48.025432 TX Vref Scan disable
6331 06:53:48.027334 == TX Byte 0 ==
6332 06:53:48.030613 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6333 06:53:48.033367 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6334 06:53:48.036880 == TX Byte 1 ==
6335 06:53:48.040247 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 06:53:48.044037 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 06:53:48.047034 ==
6338 06:53:48.047599 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 06:53:48.053404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 06:53:48.054022 ==
6341 06:53:48.054595
6342 06:53:48.055014
6343 06:53:48.056624 TX Vref Scan disable
6344 06:53:48.057074 == TX Byte 0 ==
6345 06:53:48.060638 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 06:53:48.066921 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 06:53:48.067473 == TX Byte 1 ==
6348 06:53:48.070255 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 06:53:48.073717 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 06:53:48.076576
6351 06:53:48.076986 [DATLAT]
6352 06:53:48.077309 Freq=400, CH0 RK0
6353 06:53:48.077624
6354 06:53:48.079983 DATLAT Default: 0xf
6355 06:53:48.080456 0, 0xFFFF, sum = 0
6356 06:53:48.083388 1, 0xFFFF, sum = 0
6357 06:53:48.083802 2, 0xFFFF, sum = 0
6358 06:53:48.086651 3, 0xFFFF, sum = 0
6359 06:53:48.087184 4, 0xFFFF, sum = 0
6360 06:53:48.090184 5, 0xFFFF, sum = 0
6361 06:53:48.093530 6, 0xFFFF, sum = 0
6362 06:53:48.094051 7, 0xFFFF, sum = 0
6363 06:53:48.096946 8, 0xFFFF, sum = 0
6364 06:53:48.097364 9, 0xFFFF, sum = 0
6365 06:53:48.100280 10, 0xFFFF, sum = 0
6366 06:53:48.100727 11, 0xFFFF, sum = 0
6367 06:53:48.103482 12, 0xFFFF, sum = 0
6368 06:53:48.103898 13, 0x0, sum = 1
6369 06:53:48.106464 14, 0x0, sum = 2
6370 06:53:48.106897 15, 0x0, sum = 3
6371 06:53:48.110075 16, 0x0, sum = 4
6372 06:53:48.110496 best_step = 14
6373 06:53:48.110819
6374 06:53:48.111119 ==
6375 06:53:48.113022 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 06:53:48.116766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 06:53:48.117297 ==
6378 06:53:48.119766 RX Vref Scan: 1
6379 06:53:48.120363
6380 06:53:48.123379 RX Vref 0 -> 0, step: 1
6381 06:53:48.123898
6382 06:53:48.124335 RX Delay -311 -> 252, step: 8
6383 06:53:48.126799
6384 06:53:48.127302 Set Vref, RX VrefLevel [Byte0]: 58
6385 06:53:48.129957 [Byte1]: 48
6386 06:53:48.135060
6387 06:53:48.135473 Final RX Vref Byte 0 = 58 to rank0
6388 06:53:48.138553 Final RX Vref Byte 1 = 48 to rank0
6389 06:53:48.142035 Final RX Vref Byte 0 = 58 to rank1
6390 06:53:48.144828 Final RX Vref Byte 1 = 48 to rank1==
6391 06:53:48.148356 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 06:53:48.155611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 06:53:48.156094 ==
6394 06:53:48.156478 DQS Delay:
6395 06:53:48.158478 DQS0 = 28, DQS1 = 36
6396 06:53:48.158892 DQM Delay:
6397 06:53:48.159217 DQM0 = 11, DQM1 = 13
6398 06:53:48.161518 DQ Delay:
6399 06:53:48.164941 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6400 06:53:48.165356 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6401 06:53:48.168917 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6402 06:53:48.171577 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6403 06:53:48.171992
6404 06:53:48.172354
6405 06:53:48.182187 [DQSOSCAuto] RK0, (LSB)MR18= 0xc7b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6406 06:53:48.184988 CH0 RK0: MR19=C0C, MR18=C7B3
6407 06:53:48.191921 CH0_RK0: MR19=0xC0C, MR18=0xC7B3, DQSOSC=385, MR23=63, INC=398, DEC=265
6408 06:53:48.192495 ==
6409 06:53:48.195528 Dram Type= 6, Freq= 0, CH_0, rank 1
6410 06:53:48.198435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 06:53:48.198962 ==
6412 06:53:48.201695 [Gating] SW mode calibration
6413 06:53:48.208532 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6414 06:53:48.211733 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6415 06:53:48.218568 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6416 06:53:48.221906 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6417 06:53:48.224947 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6418 06:53:48.231850 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 06:53:48.234653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 06:53:48.238627 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 06:53:48.245229 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 06:53:48.248510 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 06:53:48.252037 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 06:53:48.255636 Total UI for P1: 0, mck2ui 16
6425 06:53:48.258365 best dqsien dly found for B0: ( 0, 14, 24)
6426 06:53:48.261906 Total UI for P1: 0, mck2ui 16
6427 06:53:48.264658 best dqsien dly found for B1: ( 0, 14, 24)
6428 06:53:48.268638 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6429 06:53:48.271803 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6430 06:53:48.274852
6431 06:53:48.277934 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6432 06:53:48.281390 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6433 06:53:48.284863 [Gating] SW calibration Done
6434 06:53:48.285526 ==
6435 06:53:48.288032 Dram Type= 6, Freq= 0, CH_0, rank 1
6436 06:53:48.291460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 06:53:48.292118 ==
6438 06:53:48.292796 RX Vref Scan: 0
6439 06:53:48.293203
6440 06:53:48.294238 RX Vref 0 -> 0, step: 1
6441 06:53:48.294865
6442 06:53:48.297758 RX Delay -410 -> 252, step: 16
6443 06:53:48.301158 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6444 06:53:48.307871 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6445 06:53:48.311267 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6446 06:53:48.314963 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6447 06:53:48.318597 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6448 06:53:48.325087 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6449 06:53:48.328033 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6450 06:53:48.331721 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6451 06:53:48.334902 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6452 06:53:48.341238 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6453 06:53:48.344671 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6454 06:53:48.348131 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6455 06:53:48.351375 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6456 06:53:48.357902 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6457 06:53:48.361091 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6458 06:53:48.364396 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6459 06:53:48.364812 ==
6460 06:53:48.367901 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 06:53:48.370989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 06:53:48.374759 ==
6463 06:53:48.375219 DQS Delay:
6464 06:53:48.375562 DQS0 = 19, DQS1 = 35
6465 06:53:48.377878 DQM Delay:
6466 06:53:48.378288 DQM0 = 5, DQM1 = 12
6467 06:53:48.381116 DQ Delay:
6468 06:53:48.381627 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6469 06:53:48.384679 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6470 06:53:48.387936 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6471 06:53:48.391346 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6472 06:53:48.391917
6473 06:53:48.392248
6474 06:53:48.392609 ==
6475 06:53:48.394494 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 06:53:48.401131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 06:53:48.401634 ==
6478 06:53:48.401980
6479 06:53:48.402340
6480 06:53:48.402636 TX Vref Scan disable
6481 06:53:48.404694 == TX Byte 0 ==
6482 06:53:48.408002 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6483 06:53:48.411243 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6484 06:53:48.414593 == TX Byte 1 ==
6485 06:53:48.418381 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6486 06:53:48.420928 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6487 06:53:48.421341 ==
6488 06:53:48.424515 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 06:53:48.431196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 06:53:48.431752 ==
6491 06:53:48.432112
6492 06:53:48.432520
6493 06:53:48.432848 TX Vref Scan disable
6494 06:53:48.434644 == TX Byte 0 ==
6495 06:53:48.438270 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6496 06:53:48.441658 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6497 06:53:48.444144 == TX Byte 1 ==
6498 06:53:48.447784 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6499 06:53:48.451168 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6500 06:53:48.451681
6501 06:53:48.455130 [DATLAT]
6502 06:53:48.455640 Freq=400, CH0 RK1
6503 06:53:48.455969
6504 06:53:48.457646 DATLAT Default: 0xe
6505 06:53:48.458057 0, 0xFFFF, sum = 0
6506 06:53:48.461415 1, 0xFFFF, sum = 0
6507 06:53:48.461854 2, 0xFFFF, sum = 0
6508 06:53:48.464267 3, 0xFFFF, sum = 0
6509 06:53:48.464798 4, 0xFFFF, sum = 0
6510 06:53:48.467660 5, 0xFFFF, sum = 0
6511 06:53:48.468182 6, 0xFFFF, sum = 0
6512 06:53:48.471066 7, 0xFFFF, sum = 0
6513 06:53:48.471481 8, 0xFFFF, sum = 0
6514 06:53:48.474312 9, 0xFFFF, sum = 0
6515 06:53:48.474727 10, 0xFFFF, sum = 0
6516 06:53:48.478010 11, 0xFFFF, sum = 0
6517 06:53:48.481499 12, 0xFFFF, sum = 0
6518 06:53:48.482126 13, 0x0, sum = 1
6519 06:53:48.482468 14, 0x0, sum = 2
6520 06:53:48.484392 15, 0x0, sum = 3
6521 06:53:48.484811 16, 0x0, sum = 4
6522 06:53:48.487811 best_step = 14
6523 06:53:48.488223
6524 06:53:48.488619 ==
6525 06:53:48.491599 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 06:53:48.494968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 06:53:48.495482 ==
6528 06:53:48.498075 RX Vref Scan: 0
6529 06:53:48.498570
6530 06:53:48.498898 RX Vref 0 -> 0, step: 1
6531 06:53:48.499201
6532 06:53:48.501209 RX Delay -311 -> 252, step: 8
6533 06:53:48.509230 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6534 06:53:48.512227 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6535 06:53:48.515624 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6536 06:53:48.519187 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6537 06:53:48.525738 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6538 06:53:48.529150 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6539 06:53:48.532742 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6540 06:53:48.535753 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6541 06:53:48.542449 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6542 06:53:48.546058 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6543 06:53:48.548793 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6544 06:53:48.552494 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6545 06:53:48.559182 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6546 06:53:48.562001 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6547 06:53:48.565755 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6548 06:53:48.571917 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6549 06:53:48.572359 ==
6550 06:53:48.575477 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 06:53:48.579002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 06:53:48.579434 ==
6553 06:53:48.579758 DQS Delay:
6554 06:53:48.582005 DQS0 = 24, DQS1 = 32
6555 06:53:48.582602 DQM Delay:
6556 06:53:48.585384 DQM0 = 8, DQM1 = 9
6557 06:53:48.585790 DQ Delay:
6558 06:53:48.588930 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6559 06:53:48.592653 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6560 06:53:48.595400 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6561 06:53:48.598620 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6562 06:53:48.599032
6563 06:53:48.599352
6564 06:53:48.605733 [DQSOSCAuto] RK1, (LSB)MR18= 0xb455, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6565 06:53:48.608414 CH0 RK1: MR19=C0C, MR18=B455
6566 06:53:48.615311 CH0_RK1: MR19=0xC0C, MR18=0xB455, DQSOSC=387, MR23=63, INC=394, DEC=262
6567 06:53:48.618613 [RxdqsGatingPostProcess] freq 400
6568 06:53:48.622084 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6569 06:53:48.625383 best DQS0 dly(2T, 0.5T) = (0, 10)
6570 06:53:48.628658 best DQS1 dly(2T, 0.5T) = (0, 10)
6571 06:53:48.632134 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6572 06:53:48.635184 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6573 06:53:48.639169 best DQS0 dly(2T, 0.5T) = (0, 10)
6574 06:53:48.641729 best DQS1 dly(2T, 0.5T) = (0, 10)
6575 06:53:48.645609 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6576 06:53:48.648553 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6577 06:53:48.651911 Pre-setting of DQS Precalculation
6578 06:53:48.655640 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6579 06:53:48.656159 ==
6580 06:53:48.658908 Dram Type= 6, Freq= 0, CH_1, rank 0
6581 06:53:48.665236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 06:53:48.665643 ==
6583 06:53:48.668876 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6584 06:53:48.675489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6585 06:53:48.678158 [CA 0] Center 36 (8~64) winsize 57
6586 06:53:48.682121 [CA 1] Center 36 (8~64) winsize 57
6587 06:53:48.685613 [CA 2] Center 36 (8~64) winsize 57
6588 06:53:48.688774 [CA 3] Center 36 (8~64) winsize 57
6589 06:53:48.691806 [CA 4] Center 36 (8~64) winsize 57
6590 06:53:48.694870 [CA 5] Center 36 (8~64) winsize 57
6591 06:53:48.695371
6592 06:53:48.698532 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6593 06:53:48.699046
6594 06:53:48.702033 [CATrainingPosCal] consider 1 rank data
6595 06:53:48.705235 u2DelayCellTimex100 = 270/100 ps
6596 06:53:48.708142 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 06:53:48.711776 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 06:53:48.715254 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 06:53:48.718540 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 06:53:48.722042 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 06:53:48.727951 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 06:53:48.728527
6603 06:53:48.732147 CA PerBit enable=1, Macro0, CA PI delay=36
6604 06:53:48.732708
6605 06:53:48.734937 [CBTSetCACLKResult] CA Dly = 36
6606 06:53:48.735441 CS Dly: 1 (0~32)
6607 06:53:48.735769 ==
6608 06:53:48.738170 Dram Type= 6, Freq= 0, CH_1, rank 1
6609 06:53:48.741482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 06:53:48.744866 ==
6611 06:53:48.748396 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6612 06:53:48.755238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6613 06:53:48.758407 [CA 0] Center 36 (8~64) winsize 57
6614 06:53:48.761532 [CA 1] Center 36 (8~64) winsize 57
6615 06:53:48.764853 [CA 2] Center 36 (8~64) winsize 57
6616 06:53:48.768226 [CA 3] Center 36 (8~64) winsize 57
6617 06:53:48.771718 [CA 4] Center 36 (8~64) winsize 57
6618 06:53:48.774479 [CA 5] Center 36 (8~64) winsize 57
6619 06:53:48.774922
6620 06:53:48.778202 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6621 06:53:48.778714
6622 06:53:48.781302 [CATrainingPosCal] consider 2 rank data
6623 06:53:48.784403 u2DelayCellTimex100 = 270/100 ps
6624 06:53:48.788130 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 06:53:48.791425 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 06:53:48.794959 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 06:53:48.798058 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 06:53:48.801015 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 06:53:48.804195 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 06:53:48.804691
6631 06:53:48.808046 CA PerBit enable=1, Macro0, CA PI delay=36
6632 06:53:48.811372
6633 06:53:48.811872 [CBTSetCACLKResult] CA Dly = 36
6634 06:53:48.814803 CS Dly: 1 (0~32)
6635 06:53:48.815306
6636 06:53:48.818234 ----->DramcWriteLeveling(PI) begin...
6637 06:53:48.818718 ==
6638 06:53:48.820917 Dram Type= 6, Freq= 0, CH_1, rank 0
6639 06:53:48.824658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 06:53:48.825228 ==
6641 06:53:48.827948 Write leveling (Byte 0): 40 => 8
6642 06:53:48.831533 Write leveling (Byte 1): 40 => 8
6643 06:53:48.834946 DramcWriteLeveling(PI) end<-----
6644 06:53:48.835452
6645 06:53:48.835781 ==
6646 06:53:48.837332 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 06:53:48.840839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 06:53:48.841255 ==
6649 06:53:48.844275 [Gating] SW mode calibration
6650 06:53:48.851123 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6651 06:53:48.857887 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6652 06:53:48.860493 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6653 06:53:48.867754 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6654 06:53:48.871127 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6655 06:53:48.874245 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 06:53:48.880887 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 06:53:48.884309 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 06:53:48.887831 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 06:53:48.894823 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 06:53:48.897292 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 06:53:48.901179 Total UI for P1: 0, mck2ui 16
6662 06:53:48.904212 best dqsien dly found for B0: ( 0, 14, 24)
6663 06:53:48.907699 Total UI for P1: 0, mck2ui 16
6664 06:53:48.910758 best dqsien dly found for B1: ( 0, 14, 24)
6665 06:53:48.913965 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6666 06:53:48.917148 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6667 06:53:48.917559
6668 06:53:48.920481 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6669 06:53:48.924188 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6670 06:53:48.927288 [Gating] SW calibration Done
6671 06:53:48.927699 ==
6672 06:53:48.930454 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 06:53:48.933686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 06:53:48.934177 ==
6675 06:53:48.937197 RX Vref Scan: 0
6676 06:53:48.937752
6677 06:53:48.940739 RX Vref 0 -> 0, step: 1
6678 06:53:48.941207
6679 06:53:48.941550 RX Delay -410 -> 252, step: 16
6680 06:53:48.946977 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6681 06:53:48.950670 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6682 06:53:48.954305 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6683 06:53:48.957711 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6684 06:53:48.964064 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6685 06:53:48.967064 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6686 06:53:48.970562 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6687 06:53:48.974391 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6688 06:53:48.980628 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6689 06:53:48.984052 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6690 06:53:48.986945 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6691 06:53:48.990615 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6692 06:53:48.996814 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6693 06:53:49.000353 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6694 06:53:49.003665 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6695 06:53:49.010106 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6696 06:53:49.010327 ==
6697 06:53:49.013597 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 06:53:49.017136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 06:53:49.017356 ==
6700 06:53:49.017527 DQS Delay:
6701 06:53:49.019871 DQS0 = 35, DQS1 = 35
6702 06:53:49.020091 DQM Delay:
6703 06:53:49.023316 DQM0 = 17, DQM1 = 13
6704 06:53:49.023534 DQ Delay:
6705 06:53:49.026589 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6706 06:53:49.029960 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6707 06:53:49.033387 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6708 06:53:49.036899 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6709 06:53:49.037213
6710 06:53:49.037468
6711 06:53:49.037638 ==
6712 06:53:49.039929 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 06:53:49.043536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 06:53:49.043756 ==
6715 06:53:49.043957
6716 06:53:49.044119
6717 06:53:49.046793 TX Vref Scan disable
6718 06:53:49.047022 == TX Byte 0 ==
6719 06:53:49.053267 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6720 06:53:49.056923 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6721 06:53:49.057144 == TX Byte 1 ==
6722 06:53:49.063259 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 06:53:49.066846 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 06:53:49.067124 ==
6725 06:53:49.069816 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 06:53:49.073539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 06:53:49.073820 ==
6728 06:53:49.074079
6729 06:53:49.074263
6730 06:53:49.077216 TX Vref Scan disable
6731 06:53:49.080126 == TX Byte 0 ==
6732 06:53:49.083573 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 06:53:49.087112 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 06:53:49.087338 == TX Byte 1 ==
6735 06:53:49.093380 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 06:53:49.096971 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 06:53:49.097051
6738 06:53:49.097114 [DATLAT]
6739 06:53:49.099690 Freq=400, CH1 RK0
6740 06:53:49.099771
6741 06:53:49.099833 DATLAT Default: 0xf
6742 06:53:49.103338 0, 0xFFFF, sum = 0
6743 06:53:49.103420 1, 0xFFFF, sum = 0
6744 06:53:49.106211 2, 0xFFFF, sum = 0
6745 06:53:49.106292 3, 0xFFFF, sum = 0
6746 06:53:49.109715 4, 0xFFFF, sum = 0
6747 06:53:49.109797 5, 0xFFFF, sum = 0
6748 06:53:49.113197 6, 0xFFFF, sum = 0
6749 06:53:49.116028 7, 0xFFFF, sum = 0
6750 06:53:49.116110 8, 0xFFFF, sum = 0
6751 06:53:49.119833 9, 0xFFFF, sum = 0
6752 06:53:49.119915 10, 0xFFFF, sum = 0
6753 06:53:49.123300 11, 0xFFFF, sum = 0
6754 06:53:49.123381 12, 0xFFFF, sum = 0
6755 06:53:49.126712 13, 0x0, sum = 1
6756 06:53:49.126794 14, 0x0, sum = 2
6757 06:53:49.129744 15, 0x0, sum = 3
6758 06:53:49.129825 16, 0x0, sum = 4
6759 06:53:49.129890 best_step = 14
6760 06:53:49.133216
6761 06:53:49.133302 ==
6762 06:53:49.136150 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 06:53:49.139664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 06:53:49.139745 ==
6765 06:53:49.139809 RX Vref Scan: 1
6766 06:53:49.139868
6767 06:53:49.143156 RX Vref 0 -> 0, step: 1
6768 06:53:49.143239
6769 06:53:49.146085 RX Delay -311 -> 252, step: 8
6770 06:53:49.146165
6771 06:53:49.149525 Set Vref, RX VrefLevel [Byte0]: 57
6772 06:53:49.153090 [Byte1]: 55
6773 06:53:49.156555
6774 06:53:49.156635 Final RX Vref Byte 0 = 57 to rank0
6775 06:53:49.160116 Final RX Vref Byte 1 = 55 to rank0
6776 06:53:49.163408 Final RX Vref Byte 0 = 57 to rank1
6777 06:53:49.166791 Final RX Vref Byte 1 = 55 to rank1==
6778 06:53:49.170066 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 06:53:49.176245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 06:53:49.176374 ==
6781 06:53:49.176439 DQS Delay:
6782 06:53:49.179700 DQS0 = 28, DQS1 = 32
6783 06:53:49.179780 DQM Delay:
6784 06:53:49.179843 DQM0 = 10, DQM1 = 9
6785 06:53:49.183199 DQ Delay:
6786 06:53:49.186522 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6787 06:53:49.186603 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6788 06:53:49.189942 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6789 06:53:49.192734 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6790 06:53:49.192838
6791 06:53:49.192903
6792 06:53:49.202710 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6793 06:53:49.206494 CH1 RK0: MR19=C0C, MR18=90C7
6794 06:53:49.213072 CH1_RK0: MR19=0xC0C, MR18=0x90C7, DQSOSC=385, MR23=63, INC=398, DEC=265
6795 06:53:49.213155 ==
6796 06:53:49.216047 Dram Type= 6, Freq= 0, CH_1, rank 1
6797 06:53:49.219620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 06:53:49.219786 ==
6799 06:53:49.222914 [Gating] SW mode calibration
6800 06:53:49.229844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6801 06:53:49.233096 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6802 06:53:49.239627 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6803 06:53:49.243227 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6804 06:53:49.246133 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6805 06:53:49.253546 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 06:53:49.256919 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 06:53:49.259517 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 06:53:49.266298 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 06:53:49.269712 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 06:53:49.273170 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 06:53:49.276584 Total UI for P1: 0, mck2ui 16
6812 06:53:49.280070 best dqsien dly found for B0: ( 0, 14, 24)
6813 06:53:49.282854 Total UI for P1: 0, mck2ui 16
6814 06:53:49.286416 best dqsien dly found for B1: ( 0, 14, 24)
6815 06:53:49.290090 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6816 06:53:49.293326 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6817 06:53:49.293779
6818 06:53:49.299495 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6819 06:53:49.303042 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6820 06:53:49.306573 [Gating] SW calibration Done
6821 06:53:49.306990 ==
6822 06:53:49.309697 Dram Type= 6, Freq= 0, CH_1, rank 1
6823 06:53:49.312920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 06:53:49.313339 ==
6825 06:53:49.313666 RX Vref Scan: 0
6826 06:53:49.313972
6827 06:53:49.316379 RX Vref 0 -> 0, step: 1
6828 06:53:49.316796
6829 06:53:49.319495 RX Delay -410 -> 252, step: 16
6830 06:53:49.322976 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6831 06:53:49.329541 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6832 06:53:49.333144 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6833 06:53:49.336495 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6834 06:53:49.339643 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6835 06:53:49.346288 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6836 06:53:49.349802 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6837 06:53:49.352589 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6838 06:53:49.356060 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6839 06:53:49.362535 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6840 06:53:49.366276 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6841 06:53:49.368979 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6842 06:53:49.372472 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6843 06:53:49.379342 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6844 06:53:49.382757 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6845 06:53:49.386046 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6846 06:53:49.386371 ==
6847 06:53:49.389549 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 06:53:49.392566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 06:53:49.395937 ==
6850 06:53:49.396490 DQS Delay:
6851 06:53:49.396764 DQS0 = 35, DQS1 = 35
6852 06:53:49.398951 DQM Delay:
6853 06:53:49.399271 DQM0 = 19, DQM1 = 15
6854 06:53:49.402243 DQ Delay:
6855 06:53:49.405444 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6856 06:53:49.405771 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6857 06:53:49.409161 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6858 06:53:49.412153 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6859 06:53:49.412669
6860 06:53:49.415719
6861 06:53:49.416163 ==
6862 06:53:49.419178 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 06:53:49.421999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 06:53:49.422438 ==
6865 06:53:49.422627
6866 06:53:49.422693
6867 06:53:49.425248 TX Vref Scan disable
6868 06:53:49.425353 == TX Byte 0 ==
6869 06:53:49.428801 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6870 06:53:49.435484 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6871 06:53:49.435593 == TX Byte 1 ==
6872 06:53:49.438669 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6873 06:53:49.445294 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6874 06:53:49.445396 ==
6875 06:53:49.448706 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 06:53:49.451761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 06:53:49.451874 ==
6878 06:53:49.451971
6879 06:53:49.452064
6880 06:53:49.455276 TX Vref Scan disable
6881 06:53:49.455383 == TX Byte 0 ==
6882 06:53:49.458829 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6883 06:53:49.465064 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6884 06:53:49.465181 == TX Byte 1 ==
6885 06:53:49.468533 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6886 06:53:49.475282 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6887 06:53:49.475363
6888 06:53:49.475443 [DATLAT]
6889 06:53:49.475556 Freq=400, CH1 RK1
6890 06:53:49.475647
6891 06:53:49.478869 DATLAT Default: 0xe
6892 06:53:49.478985 0, 0xFFFF, sum = 0
6893 06:53:49.481619 1, 0xFFFF, sum = 0
6894 06:53:49.485257 2, 0xFFFF, sum = 0
6895 06:53:49.485362 3, 0xFFFF, sum = 0
6896 06:53:49.488192 4, 0xFFFF, sum = 0
6897 06:53:49.488332 5, 0xFFFF, sum = 0
6898 06:53:49.491949 6, 0xFFFF, sum = 0
6899 06:53:49.492046 7, 0xFFFF, sum = 0
6900 06:53:49.495510 8, 0xFFFF, sum = 0
6901 06:53:49.495671 9, 0xFFFF, sum = 0
6902 06:53:49.498474 10, 0xFFFF, sum = 0
6903 06:53:49.498579 11, 0xFFFF, sum = 0
6904 06:53:49.501900 12, 0xFFFF, sum = 0
6905 06:53:49.502058 13, 0x0, sum = 1
6906 06:53:49.505410 14, 0x0, sum = 2
6907 06:53:49.505607 15, 0x0, sum = 3
6908 06:53:49.508241 16, 0x0, sum = 4
6909 06:53:49.508430 best_step = 14
6910 06:53:49.508613
6911 06:53:49.508785 ==
6912 06:53:49.511671 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 06:53:49.515091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 06:53:49.515284 ==
6915 06:53:49.518807 RX Vref Scan: 0
6916 06:53:49.518989
6917 06:53:49.522171 RX Vref 0 -> 0, step: 1
6918 06:53:49.522464
6919 06:53:49.522735 RX Delay -311 -> 252, step: 8
6920 06:53:49.530522 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6921 06:53:49.534128 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6922 06:53:49.537642 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6923 06:53:49.541010 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6924 06:53:49.547139 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6925 06:53:49.550644 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6926 06:53:49.554031 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6927 06:53:49.557349 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6928 06:53:49.564325 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6929 06:53:49.567717 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6930 06:53:49.570737 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6931 06:53:49.574229 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6932 06:53:49.580996 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6933 06:53:49.583865 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6934 06:53:49.587626 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6935 06:53:49.593876 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6936 06:53:49.594194 ==
6937 06:53:49.597119 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 06:53:49.600654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 06:53:49.600845 ==
6940 06:53:49.600996 DQS Delay:
6941 06:53:49.604307 DQS0 = 28, DQS1 = 36
6942 06:53:49.604561 DQM Delay:
6943 06:53:49.607465 DQM0 = 11, DQM1 = 14
6944 06:53:49.607623 DQ Delay:
6945 06:53:49.610405 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =4
6946 06:53:49.613972 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6947 06:53:49.617310 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6948 06:53:49.620683 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6949 06:53:49.620826
6950 06:53:49.620950
6951 06:53:49.627042 [DQSOSCAuto] RK1, (LSB)MR18= 0xc252, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6952 06:53:49.630652 CH1 RK1: MR19=C0C, MR18=C252
6953 06:53:49.637184 CH1_RK1: MR19=0xC0C, MR18=0xC252, DQSOSC=385, MR23=63, INC=398, DEC=265
6954 06:53:49.640597 [RxdqsGatingPostProcess] freq 400
6955 06:53:49.643487 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6956 06:53:49.647002 best DQS0 dly(2T, 0.5T) = (0, 10)
6957 06:53:49.650001 best DQS1 dly(2T, 0.5T) = (0, 10)
6958 06:53:49.653250 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6959 06:53:49.656866 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6960 06:53:49.660259 best DQS0 dly(2T, 0.5T) = (0, 10)
6961 06:53:49.663671 best DQS1 dly(2T, 0.5T) = (0, 10)
6962 06:53:49.666719 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6963 06:53:49.670394 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6964 06:53:49.673199 Pre-setting of DQS Precalculation
6965 06:53:49.680190 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6966 06:53:49.686347 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6967 06:53:49.692873 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6968 06:53:49.692986
6969 06:53:49.693083
6970 06:53:49.696305 [Calibration Summary] 800 Mbps
6971 06:53:49.696415 CH 0, Rank 0
6972 06:53:49.700105 SW Impedance : PASS
6973 06:53:49.703095 DUTY Scan : NO K
6974 06:53:49.703179 ZQ Calibration : PASS
6975 06:53:49.706518 Jitter Meter : NO K
6976 06:53:49.706599 CBT Training : PASS
6977 06:53:49.710051 Write leveling : PASS
6978 06:53:49.713040 RX DQS gating : PASS
6979 06:53:49.713151 RX DQ/DQS(RDDQC) : PASS
6980 06:53:49.716261 TX DQ/DQS : PASS
6981 06:53:49.719795 RX DATLAT : PASS
6982 06:53:49.720100 RX DQ/DQS(Engine): PASS
6983 06:53:49.722841 TX OE : NO K
6984 06:53:49.723161 All Pass.
6985 06:53:49.723413
6986 06:53:49.726605 CH 0, Rank 1
6987 06:53:49.726923 SW Impedance : PASS
6988 06:53:49.729964 DUTY Scan : NO K
6989 06:53:49.733522 ZQ Calibration : PASS
6990 06:53:49.733936 Jitter Meter : NO K
6991 06:53:49.736318 CBT Training : PASS
6992 06:53:49.739805 Write leveling : NO K
6993 06:53:49.740128 RX DQS gating : PASS
6994 06:53:49.743288 RX DQ/DQS(RDDQC) : PASS
6995 06:53:49.746222 TX DQ/DQS : PASS
6996 06:53:49.746542 RX DATLAT : PASS
6997 06:53:49.749867 RX DQ/DQS(Engine): PASS
6998 06:53:49.750224 TX OE : NO K
6999 06:53:49.753413 All Pass.
7000 06:53:49.753729
7001 06:53:49.753977 CH 1, Rank 0
7002 06:53:49.756165 SW Impedance : PASS
7003 06:53:49.756521 DUTY Scan : NO K
7004 06:53:49.759448 ZQ Calibration : PASS
7005 06:53:49.763195 Jitter Meter : NO K
7006 06:53:49.763559 CBT Training : PASS
7007 06:53:49.766474 Write leveling : PASS
7008 06:53:49.770074 RX DQS gating : PASS
7009 06:53:49.770527 RX DQ/DQS(RDDQC) : PASS
7010 06:53:49.772969 TX DQ/DQS : PASS
7011 06:53:49.776484 RX DATLAT : PASS
7012 06:53:49.776765 RX DQ/DQS(Engine): PASS
7013 06:53:49.780082 TX OE : NO K
7014 06:53:49.780462 All Pass.
7015 06:53:49.780702
7016 06:53:49.782861 CH 1, Rank 1
7017 06:53:49.783045 SW Impedance : PASS
7018 06:53:49.786352 DUTY Scan : NO K
7019 06:53:49.789306 ZQ Calibration : PASS
7020 06:53:49.789508 Jitter Meter : NO K
7021 06:53:49.793007 CBT Training : PASS
7022 06:53:49.796437 Write leveling : NO K
7023 06:53:49.796559 RX DQS gating : PASS
7024 06:53:49.799336 RX DQ/DQS(RDDQC) : PASS
7025 06:53:49.802740 TX DQ/DQS : PASS
7026 06:53:49.802854 RX DATLAT : PASS
7027 06:53:49.806158 RX DQ/DQS(Engine): PASS
7028 06:53:49.806271 TX OE : NO K
7029 06:53:49.809603 All Pass.
7030 06:53:49.809754
7031 06:53:49.809848 DramC Write-DBI off
7032 06:53:49.813030 PER_BANK_REFRESH: Hybrid Mode
7033 06:53:49.816292 TX_TRACKING: ON
7034 06:53:49.823069 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7035 06:53:49.826114 [FAST_K] Save calibration result to emmc
7036 06:53:49.832279 dramc_set_vcore_voltage set vcore to 725000
7037 06:53:49.832408 Read voltage for 1600, 0
7038 06:53:49.835934 Vio18 = 0
7039 06:53:49.836049 Vcore = 725000
7040 06:53:49.836139 Vdram = 0
7041 06:53:49.836228 Vddq = 0
7042 06:53:49.838989 Vmddr = 0
7043 06:53:49.842616 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7044 06:53:49.849408 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7045 06:53:49.852266 MEM_TYPE=3, freq_sel=13
7046 06:53:49.852409 sv_algorithm_assistance_LP4_3733
7047 06:53:49.858935 ============ PULL DRAM RESETB DOWN ============
7048 06:53:49.862320 ========== PULL DRAM RESETB DOWN end =========
7049 06:53:49.865624 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7050 06:53:49.868846 ===================================
7051 06:53:49.872243 LPDDR4 DRAM CONFIGURATION
7052 06:53:49.875798 ===================================
7053 06:53:49.878834 EX_ROW_EN[0] = 0x0
7054 06:53:49.878975 EX_ROW_EN[1] = 0x0
7055 06:53:49.882365 LP4Y_EN = 0x0
7056 06:53:49.882506 WORK_FSP = 0x1
7057 06:53:49.886053 WL = 0x5
7058 06:53:49.886205 RL = 0x5
7059 06:53:49.888871 BL = 0x2
7060 06:53:49.889013 RPST = 0x0
7061 06:53:49.892492 RD_PRE = 0x0
7062 06:53:49.892572 WR_PRE = 0x1
7063 06:53:49.895280 WR_PST = 0x1
7064 06:53:49.895359 DBI_WR = 0x0
7065 06:53:49.898892 DBI_RD = 0x0
7066 06:53:49.898972 OTF = 0x1
7067 06:53:49.902435 ===================================
7068 06:53:49.905448 ===================================
7069 06:53:49.908997 ANA top config
7070 06:53:49.911905 ===================================
7071 06:53:49.915357 DLL_ASYNC_EN = 0
7072 06:53:49.915437 ALL_SLAVE_EN = 0
7073 06:53:49.918823 NEW_RANK_MODE = 1
7074 06:53:49.922408 DLL_IDLE_MODE = 1
7075 06:53:49.925065 LP45_APHY_COMB_EN = 1
7076 06:53:49.928676 TX_ODT_DIS = 0
7077 06:53:49.928756 NEW_8X_MODE = 1
7078 06:53:49.932139 ===================================
7079 06:53:49.935038 ===================================
7080 06:53:49.938610 data_rate = 3200
7081 06:53:49.942014 CKR = 1
7082 06:53:49.945438 DQ_P2S_RATIO = 8
7083 06:53:49.948789 ===================================
7084 06:53:49.952214 CA_P2S_RATIO = 8
7085 06:53:49.952306 DQ_CA_OPEN = 0
7086 06:53:49.955425 DQ_SEMI_OPEN = 0
7087 06:53:49.958746 CA_SEMI_OPEN = 0
7088 06:53:49.961976 CA_FULL_RATE = 0
7089 06:53:49.965303 DQ_CKDIV4_EN = 0
7090 06:53:49.968809 CA_CKDIV4_EN = 0
7091 06:53:49.968927 CA_PREDIV_EN = 0
7092 06:53:49.971970 PH8_DLY = 12
7093 06:53:49.975085 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7094 06:53:49.978352 DQ_AAMCK_DIV = 4
7095 06:53:49.981836 CA_AAMCK_DIV = 4
7096 06:53:49.985192 CA_ADMCK_DIV = 4
7097 06:53:49.985271 DQ_TRACK_CA_EN = 0
7098 06:53:49.988642 CA_PICK = 1600
7099 06:53:49.992035 CA_MCKIO = 1600
7100 06:53:49.995075 MCKIO_SEMI = 0
7101 06:53:49.998596 PLL_FREQ = 3068
7102 06:53:50.001578 DQ_UI_PI_RATIO = 32
7103 06:53:50.005070 CA_UI_PI_RATIO = 0
7104 06:53:50.008726 ===================================
7105 06:53:50.011818 ===================================
7106 06:53:50.011898 memory_type:LPDDR4
7107 06:53:50.015213 GP_NUM : 10
7108 06:53:50.018462 SRAM_EN : 1
7109 06:53:50.018542 MD32_EN : 0
7110 06:53:50.021921 ===================================
7111 06:53:50.024721 [ANA_INIT] >>>>>>>>>>>>>>
7112 06:53:50.028374 <<<<<< [CONFIGURE PHASE]: ANA_TX
7113 06:53:50.031924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7114 06:53:50.035379 ===================================
7115 06:53:50.038184 data_rate = 3200,PCW = 0X7600
7116 06:53:50.041933 ===================================
7117 06:53:50.045368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7118 06:53:50.048778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7119 06:53:50.055209 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7120 06:53:50.058482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7121 06:53:50.062117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7122 06:53:50.064784 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7123 06:53:50.068127 [ANA_INIT] flow start
7124 06:53:50.071681 [ANA_INIT] PLL >>>>>>>>
7125 06:53:50.071821 [ANA_INIT] PLL <<<<<<<<
7126 06:53:50.075367 [ANA_INIT] MIDPI >>>>>>>>
7127 06:53:50.078895 [ANA_INIT] MIDPI <<<<<<<<
7128 06:53:50.078975 [ANA_INIT] DLL >>>>>>>>
7129 06:53:50.081625 [ANA_INIT] DLL <<<<<<<<
7130 06:53:50.085303 [ANA_INIT] flow end
7131 06:53:50.088969 ============ LP4 DIFF to SE enter ============
7132 06:53:50.091589 ============ LP4 DIFF to SE exit ============
7133 06:53:50.095502 [ANA_INIT] <<<<<<<<<<<<<
7134 06:53:50.098449 [Flow] Enable top DCM control >>>>>
7135 06:53:50.101487 [Flow] Enable top DCM control <<<<<
7136 06:53:50.105009 Enable DLL master slave shuffle
7137 06:53:50.107998 ==============================================================
7138 06:53:50.111839 Gating Mode config
7139 06:53:50.118207 ==============================================================
7140 06:53:50.118315 Config description:
7141 06:53:50.128118 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7142 06:53:50.134891 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7143 06:53:50.141392 SELPH_MODE 0: By rank 1: By Phase
7144 06:53:50.144872 ==============================================================
7145 06:53:50.148321 GAT_TRACK_EN = 1
7146 06:53:50.151119 RX_GATING_MODE = 2
7147 06:53:50.154412 RX_GATING_TRACK_MODE = 2
7148 06:53:50.157932 SELPH_MODE = 1
7149 06:53:50.161263 PICG_EARLY_EN = 1
7150 06:53:50.164736 VALID_LAT_VALUE = 1
7151 06:53:50.168195 ==============================================================
7152 06:53:50.171003 Enter into Gating configuration >>>>
7153 06:53:50.174366 Exit from Gating configuration <<<<
7154 06:53:50.177882 Enter into DVFS_PRE_config >>>>>
7155 06:53:50.191382 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7156 06:53:50.194979 Exit from DVFS_PRE_config <<<<<
7157 06:53:50.195059 Enter into PICG configuration >>>>
7158 06:53:50.197946 Exit from PICG configuration <<<<
7159 06:53:50.201481 [RX_INPUT] configuration >>>>>
7160 06:53:50.204333 [RX_INPUT] configuration <<<<<
7161 06:53:50.211283 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7162 06:53:50.214643 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7163 06:53:50.221198 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7164 06:53:50.227861 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7165 06:53:50.234243 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 06:53:50.241322 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 06:53:50.244610 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7168 06:53:50.247479 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7169 06:53:50.250953 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7170 06:53:50.257356 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7171 06:53:50.260711 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7172 06:53:50.264103 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7173 06:53:50.267297 ===================================
7174 06:53:50.270898 LPDDR4 DRAM CONFIGURATION
7175 06:53:50.274203 ===================================
7176 06:53:50.277359 EX_ROW_EN[0] = 0x0
7177 06:53:50.277508 EX_ROW_EN[1] = 0x0
7178 06:53:50.280953 LP4Y_EN = 0x0
7179 06:53:50.281027 WORK_FSP = 0x1
7180 06:53:50.283865 WL = 0x5
7181 06:53:50.283941 RL = 0x5
7182 06:53:50.287408 BL = 0x2
7183 06:53:50.287485 RPST = 0x0
7184 06:53:50.290744 RD_PRE = 0x0
7185 06:53:50.290828 WR_PRE = 0x1
7186 06:53:50.294286 WR_PST = 0x1
7187 06:53:50.294367 DBI_WR = 0x0
7188 06:53:50.297152 DBI_RD = 0x0
7189 06:53:50.297224 OTF = 0x1
7190 06:53:50.300538 ===================================
7191 06:53:50.307589 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7192 06:53:50.310443 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7193 06:53:50.313900 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7194 06:53:50.317305 ===================================
7195 06:53:50.320666 LPDDR4 DRAM CONFIGURATION
7196 06:53:50.324029 ===================================
7197 06:53:50.327445 EX_ROW_EN[0] = 0x10
7198 06:53:50.327523 EX_ROW_EN[1] = 0x0
7199 06:53:50.330237 LP4Y_EN = 0x0
7200 06:53:50.330315 WORK_FSP = 0x1
7201 06:53:50.334167 WL = 0x5
7202 06:53:50.334250 RL = 0x5
7203 06:53:50.337376 BL = 0x2
7204 06:53:50.337464 RPST = 0x0
7205 06:53:50.340488 RD_PRE = 0x0
7206 06:53:50.340637 WR_PRE = 0x1
7207 06:53:50.343762 WR_PST = 0x1
7208 06:53:50.343879 DBI_WR = 0x0
7209 06:53:50.346824 DBI_RD = 0x0
7210 06:53:50.346934 OTF = 0x1
7211 06:53:50.350554 ===================================
7212 06:53:50.356833 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7213 06:53:50.356958 ==
7214 06:53:50.360706 Dram Type= 6, Freq= 0, CH_0, rank 0
7215 06:53:50.367270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7216 06:53:50.367442 ==
7217 06:53:50.367598 [Duty_Offset_Calibration]
7218 06:53:50.370476 B0:2 B1:1 CA:1
7219 06:53:50.370680
7220 06:53:50.373661 [DutyScan_Calibration_Flow] k_type=0
7221 06:53:50.382897
7222 06:53:50.383165 ==CLK 0==
7223 06:53:50.386094 Final CLK duty delay cell = 0
7224 06:53:50.389464 [0] MAX Duty = 5156%(X100), DQS PI = 22
7225 06:53:50.392914 [0] MIN Duty = 4907%(X100), DQS PI = 0
7226 06:53:50.393151 [0] AVG Duty = 5031%(X100)
7227 06:53:50.396376
7228 06:53:50.396611 CH0 CLK Duty spec in!! Max-Min= 249%
7229 06:53:50.402737 [DutyScan_Calibration_Flow] ====Done====
7230 06:53:50.402978
7231 06:53:50.406442 [DutyScan_Calibration_Flow] k_type=1
7232 06:53:50.421705
7233 06:53:50.421788 ==DQS 0 ==
7234 06:53:50.425259 Final DQS duty delay cell = -4
7235 06:53:50.428739 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7236 06:53:50.431436 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7237 06:53:50.434969 [-4] AVG Duty = 4891%(X100)
7238 06:53:50.435043
7239 06:53:50.435122 ==DQS 1 ==
7240 06:53:50.438461 Final DQS duty delay cell = 0
7241 06:53:50.441916 [0] MAX Duty = 5187%(X100), DQS PI = 20
7242 06:53:50.444676 [0] MIN Duty = 5031%(X100), DQS PI = 52
7243 06:53:50.448104 [0] AVG Duty = 5109%(X100)
7244 06:53:50.448180
7245 06:53:50.451559 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7246 06:53:50.451634
7247 06:53:50.455016 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7248 06:53:50.458299 [DutyScan_Calibration_Flow] ====Done====
7249 06:53:50.458379
7250 06:53:50.461581 [DutyScan_Calibration_Flow] k_type=3
7251 06:53:50.478843
7252 06:53:50.478952 ==DQM 0 ==
7253 06:53:50.482051 Final DQM duty delay cell = 0
7254 06:53:50.485259 [0] MAX Duty = 5218%(X100), DQS PI = 32
7255 06:53:50.488331 [0] MIN Duty = 4907%(X100), DQS PI = 0
7256 06:53:50.488442 [0] AVG Duty = 5062%(X100)
7257 06:53:50.491438
7258 06:53:50.491601 ==DQM 1 ==
7259 06:53:50.495120 Final DQM duty delay cell = -4
7260 06:53:50.498147 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7261 06:53:50.501626 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7262 06:53:50.505029 [-4] AVG Duty = 4906%(X100)
7263 06:53:50.505184
7264 06:53:50.508606 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7265 06:53:50.508778
7266 06:53:50.512172 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7267 06:53:50.514957 [DutyScan_Calibration_Flow] ====Done====
7268 06:53:50.515148
7269 06:53:50.518640 [DutyScan_Calibration_Flow] k_type=2
7270 06:53:50.536397
7271 06:53:50.536838 ==DQ 0 ==
7272 06:53:50.539961 Final DQ duty delay cell = 0
7273 06:53:50.542748 [0] MAX Duty = 5062%(X100), DQS PI = 26
7274 06:53:50.546301 [0] MIN Duty = 4907%(X100), DQS PI = 0
7275 06:53:50.546819 [0] AVG Duty = 4984%(X100)
7276 06:53:50.547323
7277 06:53:50.549928 ==DQ 1 ==
7278 06:53:50.553205 Final DQ duty delay cell = 0
7279 06:53:50.556704 [0] MAX Duty = 5156%(X100), DQS PI = 22
7280 06:53:50.559562 [0] MIN Duty = 4907%(X100), DQS PI = 34
7281 06:53:50.560050 [0] AVG Duty = 5031%(X100)
7282 06:53:50.560489
7283 06:53:50.563011 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7284 06:53:50.566335
7285 06:53:50.569875 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7286 06:53:50.572965 [DutyScan_Calibration_Flow] ====Done====
7287 06:53:50.573479 ==
7288 06:53:50.575854 Dram Type= 6, Freq= 0, CH_1, rank 0
7289 06:53:50.579359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7290 06:53:50.579805 ==
7291 06:53:50.582441 [Duty_Offset_Calibration]
7292 06:53:50.582922 B0:1 B1:0 CA:0
7293 06:53:50.583311
7294 06:53:50.585685 [DutyScan_Calibration_Flow] k_type=0
7295 06:53:50.595514
7296 06:53:50.596171 ==CLK 0==
7297 06:53:50.598853 Final CLK duty delay cell = -4
7298 06:53:50.602176 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7299 06:53:50.605578 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7300 06:53:50.608870 [-4] AVG Duty = 4906%(X100)
7301 06:53:50.609306
7302 06:53:50.612541 CH1 CLK Duty spec in!! Max-Min= 125%
7303 06:53:50.615458 [DutyScan_Calibration_Flow] ====Done====
7304 06:53:50.615964
7305 06:53:50.619086 [DutyScan_Calibration_Flow] k_type=1
7306 06:53:50.635792
7307 06:53:50.636359 ==DQS 0 ==
7308 06:53:50.638931 Final DQS duty delay cell = 0
7309 06:53:50.642418 [0] MAX Duty = 5094%(X100), DQS PI = 22
7310 06:53:50.645279 [0] MIN Duty = 4844%(X100), DQS PI = 42
7311 06:53:50.648717 [0] AVG Duty = 4969%(X100)
7312 06:53:50.649128
7313 06:53:50.649472 ==DQS 1 ==
7314 06:53:50.652118 Final DQS duty delay cell = 0
7315 06:53:50.655498 [0] MAX Duty = 5249%(X100), DQS PI = 16
7316 06:53:50.658984 [0] MIN Duty = 4969%(X100), DQS PI = 6
7317 06:53:50.662105 [0] AVG Duty = 5109%(X100)
7318 06:53:50.662546
7319 06:53:50.665583 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7320 06:53:50.666050
7321 06:53:50.669152 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7322 06:53:50.671966 [DutyScan_Calibration_Flow] ====Done====
7323 06:53:50.672479
7324 06:53:50.675279 [DutyScan_Calibration_Flow] k_type=3
7325 06:53:50.692422
7326 06:53:50.692892 ==DQM 0 ==
7327 06:53:50.695693 Final DQM duty delay cell = 0
7328 06:53:50.699061 [0] MAX Duty = 5187%(X100), DQS PI = 10
7329 06:53:50.702380 [0] MIN Duty = 4969%(X100), DQS PI = 48
7330 06:53:50.705591 [0] AVG Duty = 5078%(X100)
7331 06:53:50.706043
7332 06:53:50.706407 ==DQM 1 ==
7333 06:53:50.708983 Final DQM duty delay cell = 0
7334 06:53:50.712593 [0] MAX Duty = 5093%(X100), DQS PI = 16
7335 06:53:50.715156 [0] MIN Duty = 4907%(X100), DQS PI = 50
7336 06:53:50.718571 [0] AVG Duty = 5000%(X100)
7337 06:53:50.719045
7338 06:53:50.722487 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7339 06:53:50.722931
7340 06:53:50.725883 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7341 06:53:50.728457 [DutyScan_Calibration_Flow] ====Done====
7342 06:53:50.728865
7343 06:53:50.731850 [DutyScan_Calibration_Flow] k_type=2
7344 06:53:50.748411
7345 06:53:50.748931 ==DQ 0 ==
7346 06:53:50.751669 Final DQ duty delay cell = -4
7347 06:53:50.755323 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7348 06:53:50.758244 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7349 06:53:50.761831 [-4] AVG Duty = 4968%(X100)
7350 06:53:50.762307
7351 06:53:50.762701 ==DQ 1 ==
7352 06:53:50.765334 Final DQ duty delay cell = 0
7353 06:53:50.768741 [0] MAX Duty = 5156%(X100), DQS PI = 18
7354 06:53:50.772183 [0] MIN Duty = 4938%(X100), DQS PI = 8
7355 06:53:50.775015 [0] AVG Duty = 5047%(X100)
7356 06:53:50.775530
7357 06:53:50.778693 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7358 06:53:50.779287
7359 06:53:50.781595 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7360 06:53:50.785107 [DutyScan_Calibration_Flow] ====Done====
7361 06:53:50.788409 nWR fixed to 30
7362 06:53:50.788826 [ModeRegInit_LP4] CH0 RK0
7363 06:53:50.791952 [ModeRegInit_LP4] CH0 RK1
7364 06:53:50.794803 [ModeRegInit_LP4] CH1 RK0
7365 06:53:50.798346 [ModeRegInit_LP4] CH1 RK1
7366 06:53:50.799091 match AC timing 5
7367 06:53:50.805513 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7368 06:53:50.808823 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7369 06:53:50.811427 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7370 06:53:50.818582 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7371 06:53:50.821471 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7372 06:53:50.821881 [MiockJmeterHQA]
7373 06:53:50.822198
7374 06:53:50.825084 [DramcMiockJmeter] u1RxGatingPI = 0
7375 06:53:50.828501 0 : 4253, 4027
7376 06:53:50.829239 4 : 4252, 4026
7377 06:53:50.831901 8 : 4370, 4142
7378 06:53:50.832580 12 : 4368, 4140
7379 06:53:50.833177 16 : 4365, 4140
7380 06:53:50.834739 20 : 4255, 4029
7381 06:53:50.835291 24 : 4252, 4027
7382 06:53:50.838222 28 : 4253, 4026
7383 06:53:50.838676 32 : 4363, 4138
7384 06:53:50.841898 36 : 4252, 4027
7385 06:53:50.842348 40 : 4363, 4137
7386 06:53:50.844633 44 : 4253, 4027
7387 06:53:50.845116 48 : 4252, 4027
7388 06:53:50.845582 52 : 4250, 4027
7389 06:53:50.848043 56 : 4252, 4029
7390 06:53:50.848555 60 : 4360, 4138
7391 06:53:50.851829 64 : 4252, 4030
7392 06:53:50.852267 68 : 4361, 4137
7393 06:53:50.855058 72 : 4252, 4027
7394 06:53:50.855535 76 : 4250, 4027
7395 06:53:50.855976 80 : 4250, 4027
7396 06:53:50.857959 84 : 4360, 4137
7397 06:53:50.858404 88 : 4250, 248
7398 06:53:50.861603 92 : 4250, 0
7399 06:53:50.862081 96 : 4361, 0
7400 06:53:50.862452 100 : 4250, 0
7401 06:53:50.864544 104 : 4250, 0
7402 06:53:50.865089 108 : 4360, 0
7403 06:53:50.868105 112 : 4250, 0
7404 06:53:50.868729 116 : 4250, 0
7405 06:53:50.869231 120 : 4249, 0
7406 06:53:50.871258 124 : 4361, 0
7407 06:53:50.871556 128 : 4361, 0
7408 06:53:50.874602 132 : 4249, 0
7409 06:53:50.874914 136 : 4250, 0
7410 06:53:50.875154 140 : 4250, 0
7411 06:53:50.877741 144 : 4250, 0
7412 06:53:50.877969 148 : 4250, 0
7413 06:53:50.881508 152 : 4250, 0
7414 06:53:50.881733 156 : 4252, 0
7415 06:53:50.881910 160 : 4360, 0
7416 06:53:50.884356 164 : 4360, 0
7417 06:53:50.884564 168 : 4250, 0
7418 06:53:50.884730 172 : 4361, 0
7419 06:53:50.887997 176 : 4360, 0
7420 06:53:50.888228 180 : 4361, 0
7421 06:53:50.891325 184 : 4250, 0
7422 06:53:50.891609 188 : 4361, 0
7423 06:53:50.891847 192 : 4361, 0
7424 06:53:50.894945 196 : 4250, 0
7425 06:53:50.895177 200 : 4250, 0
7426 06:53:50.897822 204 : 4250, 1325
7427 06:53:50.898055 208 : 4250, 4007
7428 06:53:50.901431 212 : 4360, 4138
7429 06:53:50.901663 216 : 4250, 4027
7430 06:53:50.904251 220 : 4252, 4029
7431 06:53:50.904501 224 : 4360, 4138
7432 06:53:50.904680 228 : 4360, 4138
7433 06:53:50.907631 232 : 4248, 4024
7434 06:53:50.907716 236 : 4363, 4139
7435 06:53:50.911027 240 : 4360, 4138
7436 06:53:50.911113 244 : 4250, 4027
7437 06:53:50.914305 248 : 4249, 4027
7438 06:53:50.914391 252 : 4252, 4029
7439 06:53:50.918054 256 : 4250, 4027
7440 06:53:50.918150 260 : 4250, 4027
7441 06:53:50.921058 264 : 4249, 4027
7442 06:53:50.921169 268 : 4252, 4029
7443 06:53:50.924163 272 : 4250, 4027
7444 06:53:50.924248 276 : 4360, 4138
7445 06:53:50.927882 280 : 4360, 4138
7446 06:53:50.928430 284 : 4250, 4026
7447 06:53:50.929091 288 : 4363, 4139
7448 06:53:50.931351 292 : 4360, 4138
7449 06:53:50.931809 296 : 4250, 4027
7450 06:53:50.934811 300 : 4249, 4027
7451 06:53:50.935230 304 : 4252, 4029
7452 06:53:50.938197 308 : 4250, 3992
7453 06:53:50.938656 312 : 4250, 2114
7454 06:53:50.939020
7455 06:53:50.941539 MIOCK jitter meter ch=0
7456 06:53:50.942045
7457 06:53:50.944787 1T = (312-88) = 224 dly cells
7458 06:53:50.951514 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7459 06:53:50.952009 ==
7460 06:53:50.954330 Dram Type= 6, Freq= 0, CH_0, rank 0
7461 06:53:50.957829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7462 06:53:50.958291 ==
7463 06:53:50.964512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7464 06:53:50.967900 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7465 06:53:50.971146 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7466 06:53:50.977294 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7467 06:53:50.986235 [CA 0] Center 43 (12~74) winsize 63
7468 06:53:50.989374 [CA 1] Center 43 (13~74) winsize 62
7469 06:53:50.992669 [CA 2] Center 38 (9~68) winsize 60
7470 06:53:50.995893 [CA 3] Center 38 (8~68) winsize 61
7471 06:53:50.999494 [CA 4] Center 37 (7~67) winsize 61
7472 06:53:51.002562 [CA 5] Center 35 (6~65) winsize 60
7473 06:53:51.002974
7474 06:53:51.006321 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7475 06:53:51.006731
7476 06:53:51.009237 [CATrainingPosCal] consider 1 rank data
7477 06:53:51.012822 u2DelayCellTimex100 = 290/100 ps
7478 06:53:51.016561 CA0 delay=43 (12~74),Diff = 8 PI (26 cell)
7479 06:53:51.022883 CA1 delay=43 (13~74),Diff = 8 PI (26 cell)
7480 06:53:51.026358 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7481 06:53:51.029810 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7482 06:53:51.033089 CA4 delay=37 (7~67),Diff = 2 PI (6 cell)
7483 06:53:51.036280 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7484 06:53:51.036771
7485 06:53:51.039552 CA PerBit enable=1, Macro0, CA PI delay=35
7486 06:53:51.039982
7487 06:53:51.042383 [CBTSetCACLKResult] CA Dly = 35
7488 06:53:51.045928 CS Dly: 9 (0~40)
7489 06:53:51.049387 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7490 06:53:51.052201 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7491 06:53:51.052413 ==
7492 06:53:51.055708 Dram Type= 6, Freq= 0, CH_0, rank 1
7493 06:53:51.059356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7494 06:53:51.062209 ==
7495 06:53:51.065804 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7496 06:53:51.069331 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7497 06:53:51.075768 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7498 06:53:51.079137 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7499 06:53:51.089139 [CA 0] Center 42 (12~72) winsize 61
7500 06:53:51.092447 [CA 1] Center 42 (12~73) winsize 62
7501 06:53:51.096239 [CA 2] Center 37 (8~67) winsize 60
7502 06:53:51.099426 [CA 3] Center 37 (7~68) winsize 62
7503 06:53:51.102446 [CA 4] Center 35 (6~65) winsize 60
7504 06:53:51.106010 [CA 5] Center 35 (5~65) winsize 61
7505 06:53:51.106163
7506 06:53:51.109468 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7507 06:53:51.109623
7508 06:53:51.112981 [CATrainingPosCal] consider 2 rank data
7509 06:53:51.115784 u2DelayCellTimex100 = 290/100 ps
7510 06:53:51.119150 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7511 06:53:51.126234 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7512 06:53:51.129085 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7513 06:53:51.132634 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7514 06:53:51.136012 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7515 06:53:51.139293 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7516 06:53:51.139601
7517 06:53:51.142707 CA PerBit enable=1, Macro0, CA PI delay=35
7518 06:53:51.142930
7519 06:53:51.146012 [CBTSetCACLKResult] CA Dly = 35
7520 06:53:51.149249 CS Dly: 9 (0~41)
7521 06:53:51.152669 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7522 06:53:51.156271 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7523 06:53:51.156485
7524 06:53:51.159049 ----->DramcWriteLeveling(PI) begin...
7525 06:53:51.159232 ==
7526 06:53:51.162567 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 06:53:51.165976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 06:53:51.169544 ==
7529 06:53:51.169748 Write leveling (Byte 0): 37 => 37
7530 06:53:51.172985 Write leveling (Byte 1): 27 => 27
7531 06:53:51.176404 DramcWriteLeveling(PI) end<-----
7532 06:53:51.176870
7533 06:53:51.177116 ==
7534 06:53:51.179478 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 06:53:51.186366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 06:53:51.186656 ==
7537 06:53:51.189214 [Gating] SW mode calibration
7538 06:53:51.196519 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7539 06:53:51.199789 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7540 06:53:51.205947 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7541 06:53:51.209459 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 06:53:51.212732 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7543 06:53:51.216111 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7544 06:53:51.222675 1 4 16 | B1->B0 | 2424 3636 | 0 1 | (0 0) (1 1)
7545 06:53:51.225735 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7546 06:53:51.232766 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 06:53:51.236031 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7548 06:53:51.239540 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 06:53:51.242564 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7550 06:53:51.249420 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7551 06:53:51.252584 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7552 06:53:51.255827 1 5 16 | B1->B0 | 3434 2828 | 0 0 | (0 0) (1 0)
7553 06:53:51.262585 1 5 20 | B1->B0 | 2828 2424 | 0 0 | (1 0) (0 0)
7554 06:53:51.265638 1 5 24 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
7555 06:53:51.268787 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7556 06:53:51.275863 1 6 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
7557 06:53:51.278710 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7558 06:53:51.282222 1 6 8 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
7559 06:53:51.288573 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7560 06:53:51.292036 1 6 16 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
7561 06:53:51.295467 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7562 06:53:51.301991 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 06:53:51.304986 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 06:53:51.308486 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 06:53:51.315443 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 06:53:51.318861 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7567 06:53:51.322404 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 06:53:51.328642 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7569 06:53:51.331877 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 06:53:51.335259 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 06:53:51.341762 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 06:53:51.344985 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 06:53:51.348257 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 06:53:51.355169 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 06:53:51.358190 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 06:53:51.361877 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 06:53:51.368393 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 06:53:51.371580 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 06:53:51.374925 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 06:53:51.381452 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 06:53:51.384691 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 06:53:51.388394 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7583 06:53:51.394733 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 06:53:51.398003 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7585 06:53:51.401463 Total UI for P1: 0, mck2ui 16
7586 06:53:51.405035 best dqsien dly found for B0: ( 1, 9, 10)
7587 06:53:51.407792 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 06:53:51.411400 Total UI for P1: 0, mck2ui 16
7589 06:53:51.414289 best dqsien dly found for B1: ( 1, 9, 18)
7590 06:53:51.417878 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7591 06:53:51.421377 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7592 06:53:51.421796
7593 06:53:51.427997 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7594 06:53:51.431393 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7595 06:53:51.431812 [Gating] SW calibration Done
7596 06:53:51.434812 ==
7597 06:53:51.438136 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 06:53:51.441698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 06:53:51.442117 ==
7600 06:53:51.442444 RX Vref Scan: 0
7601 06:53:51.442755
7602 06:53:51.444275 RX Vref 0 -> 0, step: 1
7603 06:53:51.444722
7604 06:53:51.447668 RX Delay 0 -> 252, step: 8
7605 06:53:51.450911 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7606 06:53:51.455170 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7607 06:53:51.457659 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7608 06:53:51.464164 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7609 06:53:51.467352 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7610 06:53:51.471161 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7611 06:53:51.474169 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7612 06:53:51.477329 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7613 06:53:51.484266 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7614 06:53:51.487719 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7615 06:53:51.490998 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7616 06:53:51.494106 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7617 06:53:51.497675 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7618 06:53:51.504166 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7619 06:53:51.507304 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7620 06:53:51.510602 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7621 06:53:51.511050 ==
7622 06:53:51.514288 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 06:53:51.517843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 06:53:51.518274 ==
7625 06:53:51.521183 DQS Delay:
7626 06:53:51.521593 DQS0 = 0, DQS1 = 0
7627 06:53:51.523924 DQM Delay:
7628 06:53:51.524433 DQM0 = 137, DQM1 = 129
7629 06:53:51.527322 DQ Delay:
7630 06:53:51.530897 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7631 06:53:51.534447 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7632 06:53:51.537190 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7633 06:53:51.540441 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
7634 06:53:51.540987
7635 06:53:51.541324
7636 06:53:51.541633 ==
7637 06:53:51.543932 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 06:53:51.547428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 06:53:51.547875 ==
7640 06:53:51.548282
7641 06:53:51.548794
7642 06:53:51.550953 TX Vref Scan disable
7643 06:53:51.554546 == TX Byte 0 ==
7644 06:53:51.557910 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7645 06:53:51.560818 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7646 06:53:51.564372 == TX Byte 1 ==
7647 06:53:51.567643 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7648 06:53:51.570422 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7649 06:53:51.570899 ==
7650 06:53:51.573804 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 06:53:51.580578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 06:53:51.580994 ==
7653 06:53:51.592960
7654 06:53:51.596607 TX Vref early break, caculate TX vref
7655 06:53:51.599552 TX Vref=16, minBit 0, minWin=23, winSum=379
7656 06:53:51.602831 TX Vref=18, minBit 0, minWin=22, winSum=388
7657 06:53:51.606525 TX Vref=20, minBit 0, minWin=23, winSum=398
7658 06:53:51.609915 TX Vref=22, minBit 0, minWin=24, winSum=403
7659 06:53:51.612632 TX Vref=24, minBit 7, minWin=24, winSum=413
7660 06:53:51.619942 TX Vref=26, minBit 1, minWin=25, winSum=423
7661 06:53:51.623129 TX Vref=28, minBit 1, minWin=25, winSum=420
7662 06:53:51.626203 TX Vref=30, minBit 1, minWin=24, winSum=404
7663 06:53:51.629412 TX Vref=32, minBit 0, minWin=24, winSum=404
7664 06:53:51.632887 TX Vref=34, minBit 1, minWin=23, winSum=393
7665 06:53:51.639731 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 26
7666 06:53:51.640346
7667 06:53:51.642785 Final TX Range 0 Vref 26
7668 06:53:51.643374
7669 06:53:51.643897 ==
7670 06:53:51.646300 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 06:53:51.649732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 06:53:51.650152 ==
7673 06:53:51.650511
7674 06:53:51.650867
7675 06:53:51.652591 TX Vref Scan disable
7676 06:53:51.659397 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7677 06:53:51.659816 == TX Byte 0 ==
7678 06:53:51.662858 u2DelayCellOfst[0]=13 cells (4 PI)
7679 06:53:51.666543 u2DelayCellOfst[1]=16 cells (5 PI)
7680 06:53:51.669518 u2DelayCellOfst[2]=13 cells (4 PI)
7681 06:53:51.673051 u2DelayCellOfst[3]=10 cells (3 PI)
7682 06:53:51.675940 u2DelayCellOfst[4]=10 cells (3 PI)
7683 06:53:51.679311 u2DelayCellOfst[5]=0 cells (0 PI)
7684 06:53:51.682789 u2DelayCellOfst[6]=20 cells (6 PI)
7685 06:53:51.683219 u2DelayCellOfst[7]=20 cells (6 PI)
7686 06:53:51.689465 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7687 06:53:51.692942 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7688 06:53:51.693508 == TX Byte 1 ==
7689 06:53:51.695878 u2DelayCellOfst[8]=0 cells (0 PI)
7690 06:53:51.699395 u2DelayCellOfst[9]=0 cells (0 PI)
7691 06:53:51.702856 u2DelayCellOfst[10]=10 cells (3 PI)
7692 06:53:51.706262 u2DelayCellOfst[11]=3 cells (1 PI)
7693 06:53:51.709422 u2DelayCellOfst[12]=10 cells (3 PI)
7694 06:53:51.712713 u2DelayCellOfst[13]=13 cells (4 PI)
7695 06:53:51.715887 u2DelayCellOfst[14]=16 cells (5 PI)
7696 06:53:51.718955 u2DelayCellOfst[15]=10 cells (3 PI)
7697 06:53:51.722971 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7698 06:53:51.728985 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7699 06:53:51.729305 DramC Write-DBI on
7700 06:53:51.729619 ==
7701 06:53:51.732193 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 06:53:51.735535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 06:53:51.739070 ==
7704 06:53:51.739153
7705 06:53:51.739238
7706 06:53:51.739319 TX Vref Scan disable
7707 06:53:51.742345 == TX Byte 0 ==
7708 06:53:51.745617 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7709 06:53:51.748712 == TX Byte 1 ==
7710 06:53:51.752337 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7711 06:53:51.755720 DramC Write-DBI off
7712 06:53:51.755804
7713 06:53:51.755889 [DATLAT]
7714 06:53:51.755969 Freq=1600, CH0 RK0
7715 06:53:51.756047
7716 06:53:51.758601 DATLAT Default: 0xf
7717 06:53:51.758707 0, 0xFFFF, sum = 0
7718 06:53:51.762142 1, 0xFFFF, sum = 0
7719 06:53:51.765132 2, 0xFFFF, sum = 0
7720 06:53:51.765217 3, 0xFFFF, sum = 0
7721 06:53:51.768629 4, 0xFFFF, sum = 0
7722 06:53:51.768714 5, 0xFFFF, sum = 0
7723 06:53:51.772097 6, 0xFFFF, sum = 0
7724 06:53:51.772181 7, 0xFFFF, sum = 0
7725 06:53:51.775371 8, 0xFFFF, sum = 0
7726 06:53:51.775455 9, 0xFFFF, sum = 0
7727 06:53:51.778629 10, 0xFFFF, sum = 0
7728 06:53:51.778715 11, 0xFFFF, sum = 0
7729 06:53:51.781991 12, 0xFFFF, sum = 0
7730 06:53:51.782104 13, 0xFFFF, sum = 0
7731 06:53:51.785514 14, 0x0, sum = 1
7732 06:53:51.785629 15, 0x0, sum = 2
7733 06:53:51.788496 16, 0x0, sum = 3
7734 06:53:51.788578 17, 0x0, sum = 4
7735 06:53:51.792199 best_step = 15
7736 06:53:51.792294
7737 06:53:51.792362 ==
7738 06:53:51.795143 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 06:53:51.798865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 06:53:51.798952 ==
7741 06:53:51.802329 RX Vref Scan: 1
7742 06:53:51.802456
7743 06:53:51.802565 Set Vref Range= 24 -> 127
7744 06:53:51.802647
7745 06:53:51.805234 RX Vref 24 -> 127, step: 1
7746 06:53:51.805369
7747 06:53:51.809130 RX Delay 27 -> 252, step: 4
7748 06:53:51.809230
7749 06:53:51.811895 Set Vref, RX VrefLevel [Byte0]: 24
7750 06:53:51.815239 [Byte1]: 24
7751 06:53:51.815360
7752 06:53:51.818887 Set Vref, RX VrefLevel [Byte0]: 25
7753 06:53:51.822288 [Byte1]: 25
7754 06:53:51.822470
7755 06:53:51.825671 Set Vref, RX VrefLevel [Byte0]: 26
7756 06:53:51.829094 [Byte1]: 26
7757 06:53:51.832606
7758 06:53:51.832686 Set Vref, RX VrefLevel [Byte0]: 27
7759 06:53:51.835717 [Byte1]: 27
7760 06:53:51.839635
7761 06:53:51.839725 Set Vref, RX VrefLevel [Byte0]: 28
7762 06:53:51.842988 [Byte1]: 28
7763 06:53:51.847307
7764 06:53:51.847413 Set Vref, RX VrefLevel [Byte0]: 29
7765 06:53:51.850896 [Byte1]: 29
7766 06:53:51.855136
7767 06:53:51.855241 Set Vref, RX VrefLevel [Byte0]: 30
7768 06:53:51.858505 [Byte1]: 30
7769 06:53:51.862308
7770 06:53:51.862408 Set Vref, RX VrefLevel [Byte0]: 31
7771 06:53:51.866080 [Byte1]: 31
7772 06:53:51.870081
7773 06:53:51.870162 Set Vref, RX VrefLevel [Byte0]: 32
7774 06:53:51.873164 [Byte1]: 32
7775 06:53:51.877613
7776 06:53:51.877694 Set Vref, RX VrefLevel [Byte0]: 33
7777 06:53:51.880885 [Byte1]: 33
7778 06:53:51.884855
7779 06:53:51.888091 Set Vref, RX VrefLevel [Byte0]: 34
7780 06:53:51.891526 [Byte1]: 34
7781 06:53:51.891608
7782 06:53:51.895184 Set Vref, RX VrefLevel [Byte0]: 35
7783 06:53:51.897949 [Byte1]: 35
7784 06:53:51.898054
7785 06:53:51.901597 Set Vref, RX VrefLevel [Byte0]: 36
7786 06:53:51.904607 [Byte1]: 36
7787 06:53:51.904711
7788 06:53:51.908405 Set Vref, RX VrefLevel [Byte0]: 37
7789 06:53:51.911288 [Byte1]: 37
7790 06:53:51.914913
7791 06:53:51.915023 Set Vref, RX VrefLevel [Byte0]: 38
7792 06:53:51.918351 [Byte1]: 38
7793 06:53:51.923003
7794 06:53:51.923104 Set Vref, RX VrefLevel [Byte0]: 39
7795 06:53:51.925959 [Byte1]: 39
7796 06:53:51.930099
7797 06:53:51.930185 Set Vref, RX VrefLevel [Byte0]: 40
7798 06:53:51.933704 [Byte1]: 40
7799 06:53:51.937828
7800 06:53:51.937933 Set Vref, RX VrefLevel [Byte0]: 41
7801 06:53:51.941242 [Byte1]: 41
7802 06:53:51.945920
7803 06:53:51.946006 Set Vref, RX VrefLevel [Byte0]: 42
7804 06:53:51.948606 [Byte1]: 42
7805 06:53:51.952772
7806 06:53:51.952864 Set Vref, RX VrefLevel [Byte0]: 43
7807 06:53:51.956618 [Byte1]: 43
7808 06:53:51.960573
7809 06:53:51.960681 Set Vref, RX VrefLevel [Byte0]: 44
7810 06:53:51.964194 [Byte1]: 44
7811 06:53:51.968192
7812 06:53:51.968323 Set Vref, RX VrefLevel [Byte0]: 45
7813 06:53:51.971543 [Byte1]: 45
7814 06:53:51.975503
7815 06:53:51.975652 Set Vref, RX VrefLevel [Byte0]: 46
7816 06:53:51.978861 [Byte1]: 46
7817 06:53:51.983619
7818 06:53:51.983881 Set Vref, RX VrefLevel [Byte0]: 47
7819 06:53:51.986591 [Byte1]: 47
7820 06:53:51.990557
7821 06:53:51.990821 Set Vref, RX VrefLevel [Byte0]: 48
7822 06:53:51.994230 [Byte1]: 48
7823 06:53:51.998564
7824 06:53:51.998869 Set Vref, RX VrefLevel [Byte0]: 49
7825 06:53:52.001907 [Byte1]: 49
7826 06:53:52.005806
7827 06:53:52.006374 Set Vref, RX VrefLevel [Byte0]: 50
7828 06:53:52.009489 [Byte1]: 50
7829 06:53:52.013823
7830 06:53:52.014265 Set Vref, RX VrefLevel [Byte0]: 51
7831 06:53:52.016615 [Byte1]: 51
7832 06:53:52.021058
7833 06:53:52.021488 Set Vref, RX VrefLevel [Byte0]: 52
7834 06:53:52.024453 [Byte1]: 52
7835 06:53:52.028473
7836 06:53:52.028904 Set Vref, RX VrefLevel [Byte0]: 53
7837 06:53:52.031930 [Byte1]: 53
7838 06:53:52.036521
7839 06:53:52.036956 Set Vref, RX VrefLevel [Byte0]: 54
7840 06:53:52.039326 [Byte1]: 54
7841 06:53:52.043725
7842 06:53:52.044137 Set Vref, RX VrefLevel [Byte0]: 55
7843 06:53:52.047355 [Byte1]: 55
7844 06:53:52.050777
7845 06:53:52.051188 Set Vref, RX VrefLevel [Byte0]: 56
7846 06:53:52.054389 [Byte1]: 56
7847 06:53:52.058873
7848 06:53:52.059291 Set Vref, RX VrefLevel [Byte0]: 57
7849 06:53:52.062037 [Byte1]: 57
7850 06:53:52.066214
7851 06:53:52.066435 Set Vref, RX VrefLevel [Byte0]: 58
7852 06:53:52.069005 [Byte1]: 58
7853 06:53:52.073147
7854 06:53:52.073229 Set Vref, RX VrefLevel [Byte0]: 59
7855 06:53:52.076747 [Byte1]: 59
7856 06:53:52.081028
7857 06:53:52.081108 Set Vref, RX VrefLevel [Byte0]: 60
7858 06:53:52.084585 [Byte1]: 60
7859 06:53:52.088733
7860 06:53:52.088838 Set Vref, RX VrefLevel [Byte0]: 61
7861 06:53:52.091681 [Byte1]: 61
7862 06:53:52.096137
7863 06:53:52.096217 Set Vref, RX VrefLevel [Byte0]: 62
7864 06:53:52.099178 [Byte1]: 62
7865 06:53:52.103290
7866 06:53:52.103376 Set Vref, RX VrefLevel [Byte0]: 63
7867 06:53:52.106545 [Byte1]: 63
7868 06:53:52.110844
7869 06:53:52.110975 Set Vref, RX VrefLevel [Byte0]: 64
7870 06:53:52.114549 [Byte1]: 64
7871 06:53:52.118600
7872 06:53:52.118743 Set Vref, RX VrefLevel [Byte0]: 65
7873 06:53:52.122297 [Byte1]: 65
7874 06:53:52.126582
7875 06:53:52.126761 Set Vref, RX VrefLevel [Byte0]: 66
7876 06:53:52.129428 [Byte1]: 66
7877 06:53:52.133743
7878 06:53:52.133822 Set Vref, RX VrefLevel [Byte0]: 67
7879 06:53:52.137217 [Byte1]: 67
7880 06:53:52.140959
7881 06:53:52.141064 Set Vref, RX VrefLevel [Byte0]: 68
7882 06:53:52.144420 [Byte1]: 68
7883 06:53:52.148840
7884 06:53:52.148919 Set Vref, RX VrefLevel [Byte0]: 69
7885 06:53:52.152469 [Byte1]: 69
7886 06:53:52.156022
7887 06:53:52.156128 Set Vref, RX VrefLevel [Byte0]: 70
7888 06:53:52.159504 [Byte1]: 70
7889 06:53:52.163916
7890 06:53:52.163995 Set Vref, RX VrefLevel [Byte0]: 71
7891 06:53:52.167264 [Byte1]: 71
7892 06:53:52.171307
7893 06:53:52.171390 Set Vref, RX VrefLevel [Byte0]: 72
7894 06:53:52.174702 [Byte1]: 72
7895 06:53:52.178598
7896 06:53:52.178685 Set Vref, RX VrefLevel [Byte0]: 73
7897 06:53:52.182224 [Byte1]: 73
7898 06:53:52.186650
7899 06:53:52.186757 Set Vref, RX VrefLevel [Byte0]: 74
7900 06:53:52.189721 [Byte1]: 74
7901 06:53:52.193953
7902 06:53:52.194034 Set Vref, RX VrefLevel [Byte0]: 75
7903 06:53:52.196856 [Byte1]: 75
7904 06:53:52.201239
7905 06:53:52.201318 Set Vref, RX VrefLevel [Byte0]: 76
7906 06:53:52.204822 [Byte1]: 76
7907 06:53:52.208841
7908 06:53:52.208921 Set Vref, RX VrefLevel [Byte0]: 77
7909 06:53:52.212091 [Byte1]: 77
7910 06:53:52.216602
7911 06:53:52.216694 Final RX Vref Byte 0 = 54 to rank0
7912 06:53:52.220331 Final RX Vref Byte 1 = 61 to rank0
7913 06:53:52.223270 Final RX Vref Byte 0 = 54 to rank1
7914 06:53:52.226655 Final RX Vref Byte 1 = 61 to rank1==
7915 06:53:52.230185 Dram Type= 6, Freq= 0, CH_0, rank 0
7916 06:53:52.236720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7917 06:53:52.236929 ==
7918 06:53:52.237049 DQS Delay:
7919 06:53:52.237155 DQS0 = 0, DQS1 = 0
7920 06:53:52.240006 DQM Delay:
7921 06:53:52.240163 DQM0 = 133, DQM1 = 127
7922 06:53:52.243174 DQ Delay:
7923 06:53:52.246524 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =130
7924 06:53:52.250037 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =138
7925 06:53:52.253447 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7926 06:53:52.257102 DQ12 =130, DQ13 =134, DQ14 =138, DQ15 =134
7927 06:53:52.257427
7928 06:53:52.257632
7929 06:53:52.257834
7930 06:53:52.259900 [DramC_TX_OE_Calibration] TA2
7931 06:53:52.263271 Original DQ_B0 (3 6) =30, OEN = 27
7932 06:53:52.267002 Original DQ_B1 (3 6) =30, OEN = 27
7933 06:53:52.269889 24, 0x0, End_B0=24 End_B1=24
7934 06:53:52.270307 25, 0x0, End_B0=25 End_B1=25
7935 06:53:52.273387 26, 0x0, End_B0=26 End_B1=26
7936 06:53:52.276760 27, 0x0, End_B0=27 End_B1=27
7937 06:53:52.280163 28, 0x0, End_B0=28 End_B1=28
7938 06:53:52.280660 29, 0x0, End_B0=29 End_B1=29
7939 06:53:52.283507 30, 0x0, End_B0=30 End_B1=30
7940 06:53:52.287036 31, 0x4141, End_B0=30 End_B1=30
7941 06:53:52.290116 Byte0 end_step=30 best_step=27
7942 06:53:52.293289 Byte1 end_step=30 best_step=27
7943 06:53:52.296443 Byte0 TX OE(2T, 0.5T) = (3, 3)
7944 06:53:52.296993 Byte1 TX OE(2T, 0.5T) = (3, 3)
7945 06:53:52.299953
7946 06:53:52.300403
7947 06:53:52.306544 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7948 06:53:52.310085 CH0 RK0: MR19=303, MR18=2521
7949 06:53:52.316358 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7950 06:53:52.316778
7951 06:53:52.319837 ----->DramcWriteLeveling(PI) begin...
7952 06:53:52.320403 ==
7953 06:53:52.323375 Dram Type= 6, Freq= 0, CH_0, rank 1
7954 06:53:52.325988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 06:53:52.326456 ==
7956 06:53:52.330034 Write leveling (Byte 0): 37 => 37
7957 06:53:52.333216 Write leveling (Byte 1): 25 => 25
7958 06:53:52.336334 DramcWriteLeveling(PI) end<-----
7959 06:53:52.336749
7960 06:53:52.337074 ==
7961 06:53:52.339691 Dram Type= 6, Freq= 0, CH_0, rank 1
7962 06:53:52.342958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7963 06:53:52.343367 ==
7964 06:53:52.346111 [Gating] SW mode calibration
7965 06:53:52.352832 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7966 06:53:52.359689 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7967 06:53:52.363241 1 4 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7968 06:53:52.369469 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7969 06:53:52.372998 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 06:53:52.376480 1 4 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7971 06:53:52.379219 1 4 16 | B1->B0 | 3030 3838 | 1 0 | (0 0) (0 0)
7972 06:53:52.386080 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7973 06:53:52.389679 1 4 24 | B1->B0 | 3434 3a3a | 1 1 | (1 1) (0 0)
7974 06:53:52.392851 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7975 06:53:52.399710 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7976 06:53:52.402484 1 5 4 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7977 06:53:52.405893 1 5 8 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
7978 06:53:52.412811 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
7979 06:53:52.415944 1 5 16 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (1 0)
7980 06:53:52.419120 1 5 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
7981 06:53:52.425697 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 06:53:52.429377 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7983 06:53:52.432630 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7984 06:53:52.439299 1 6 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7985 06:53:52.442470 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7986 06:53:52.445984 1 6 12 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)
7987 06:53:52.452177 1 6 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7988 06:53:52.455858 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 06:53:52.458988 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 06:53:52.465463 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 06:53:52.468925 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 06:53:52.472199 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 06:53:52.478402 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 06:53:52.481819 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7995 06:53:52.485220 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7996 06:53:52.492252 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 06:53:52.495543 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 06:53:52.498932 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 06:53:52.505485 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 06:53:52.508837 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 06:53:52.511592 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 06:53:52.518516 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 06:53:52.522002 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 06:53:52.525399 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 06:53:52.531835 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 06:53:52.535299 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 06:53:52.538291 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 06:53:52.545045 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 06:53:52.547997 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 06:53:52.551582 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8011 06:53:52.558635 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8012 06:53:52.561861 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 06:53:52.564924 Total UI for P1: 0, mck2ui 16
8014 06:53:52.568156 best dqsien dly found for B0: ( 1, 9, 14)
8015 06:53:52.571595 Total UI for P1: 0, mck2ui 16
8016 06:53:52.574686 best dqsien dly found for B1: ( 1, 9, 14)
8017 06:53:52.578053 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8018 06:53:52.581787 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8019 06:53:52.582083
8020 06:53:52.585071 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8021 06:53:52.588364 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8022 06:53:52.591325 [Gating] SW calibration Done
8023 06:53:52.591677 ==
8024 06:53:52.594745 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 06:53:52.598416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 06:53:52.598808 ==
8027 06:53:52.601470 RX Vref Scan: 0
8028 06:53:52.601764
8029 06:53:52.604824 RX Vref 0 -> 0, step: 1
8030 06:53:52.605135
8031 06:53:52.605371 RX Delay 0 -> 252, step: 8
8032 06:53:52.611785 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8033 06:53:52.614506 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8034 06:53:52.618003 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8035 06:53:52.621753 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8036 06:53:52.625257 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8037 06:53:52.631827 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8038 06:53:52.634656 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8039 06:53:52.637869 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8040 06:53:52.641392 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8041 06:53:52.644743 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8042 06:53:52.651385 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8043 06:53:52.654563 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8044 06:53:52.658532 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8045 06:53:52.661216 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8046 06:53:52.664755 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8047 06:53:52.671197 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8048 06:53:52.671734 ==
8049 06:53:52.674393 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 06:53:52.677785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 06:53:52.678330 ==
8052 06:53:52.678836 DQS Delay:
8053 06:53:52.681749 DQS0 = 0, DQS1 = 0
8054 06:53:52.682311 DQM Delay:
8055 06:53:52.684932 DQM0 = 136, DQM1 = 128
8056 06:53:52.685508 DQ Delay:
8057 06:53:52.688020 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8058 06:53:52.691309 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8059 06:53:52.695073 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8060 06:53:52.698110 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8061 06:53:52.698698
8062 06:53:52.699173
8063 06:53:52.701073 ==
8064 06:53:52.704787 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 06:53:52.708230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 06:53:52.708695 ==
8067 06:53:52.709023
8068 06:53:52.709326
8069 06:53:52.711387 TX Vref Scan disable
8070 06:53:52.711802 == TX Byte 0 ==
8071 06:53:52.718217 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8072 06:53:52.721040 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8073 06:53:52.721456 == TX Byte 1 ==
8074 06:53:52.728106 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8075 06:53:52.730891 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8076 06:53:52.731328 ==
8077 06:53:52.734533 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 06:53:52.737886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 06:53:52.738307 ==
8080 06:53:52.754043
8081 06:53:52.756835 TX Vref early break, caculate TX vref
8082 06:53:52.760208 TX Vref=16, minBit 1, minWin=22, winSum=388
8083 06:53:52.763512 TX Vref=18, minBit 1, minWin=23, winSum=394
8084 06:53:52.767075 TX Vref=20, minBit 1, minWin=23, winSum=402
8085 06:53:52.770255 TX Vref=22, minBit 1, minWin=24, winSum=410
8086 06:53:52.773935 TX Vref=24, minBit 3, minWin=24, winSum=416
8087 06:53:52.780436 TX Vref=26, minBit 1, minWin=25, winSum=422
8088 06:53:52.783976 TX Vref=28, minBit 3, minWin=25, winSum=426
8089 06:53:52.787299 TX Vref=30, minBit 4, minWin=24, winSum=415
8090 06:53:52.790357 TX Vref=32, minBit 1, minWin=25, winSum=411
8091 06:53:52.793624 TX Vref=34, minBit 4, minWin=24, winSum=407
8092 06:53:52.797401 TX Vref=36, minBit 0, minWin=24, winSum=396
8093 06:53:52.803621 [TxChooseVref] Worse bit 3, Min win 25, Win sum 426, Final Vref 28
8094 06:53:52.804042
8095 06:53:52.807100 Final TX Range 0 Vref 28
8096 06:53:52.807548
8097 06:53:52.807881 ==
8098 06:53:52.810619 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 06:53:52.813450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 06:53:52.813871 ==
8101 06:53:52.814202
8102 06:53:52.814509
8103 06:53:52.816918 TX Vref Scan disable
8104 06:53:52.823568 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8105 06:53:52.823986 == TX Byte 0 ==
8106 06:53:52.826632 u2DelayCellOfst[0]=13 cells (4 PI)
8107 06:53:52.830485 u2DelayCellOfst[1]=16 cells (5 PI)
8108 06:53:52.834046 u2DelayCellOfst[2]=13 cells (4 PI)
8109 06:53:52.837470 u2DelayCellOfst[3]=13 cells (4 PI)
8110 06:53:52.840204 u2DelayCellOfst[4]=10 cells (3 PI)
8111 06:53:52.843609 u2DelayCellOfst[5]=0 cells (0 PI)
8112 06:53:52.846926 u2DelayCellOfst[6]=16 cells (5 PI)
8113 06:53:52.850399 u2DelayCellOfst[7]=16 cells (5 PI)
8114 06:53:52.853719 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8115 06:53:52.857121 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8116 06:53:52.859929 == TX Byte 1 ==
8117 06:53:52.863352 u2DelayCellOfst[8]=0 cells (0 PI)
8118 06:53:52.863886 u2DelayCellOfst[9]=3 cells (1 PI)
8119 06:53:52.866977 u2DelayCellOfst[10]=6 cells (2 PI)
8120 06:53:52.870147 u2DelayCellOfst[11]=3 cells (1 PI)
8121 06:53:52.873661 u2DelayCellOfst[12]=10 cells (3 PI)
8122 06:53:52.877219 u2DelayCellOfst[13]=10 cells (3 PI)
8123 06:53:52.880000 u2DelayCellOfst[14]=13 cells (4 PI)
8124 06:53:52.883342 u2DelayCellOfst[15]=10 cells (3 PI)
8125 06:53:52.886716 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8126 06:53:52.893493 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8127 06:53:52.893979 DramC Write-DBI on
8128 06:53:52.894346 ==
8129 06:53:52.896617 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 06:53:52.903163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 06:53:52.903660 ==
8132 06:53:52.904127
8133 06:53:52.904600
8134 06:53:52.904908 TX Vref Scan disable
8135 06:53:52.907267 == TX Byte 0 ==
8136 06:53:52.911140 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8137 06:53:52.914056 == TX Byte 1 ==
8138 06:53:52.917350 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8139 06:53:52.920467 DramC Write-DBI off
8140 06:53:52.920896
8141 06:53:52.921226 [DATLAT]
8142 06:53:52.921678 Freq=1600, CH0 RK1
8143 06:53:52.922004
8144 06:53:52.924192 DATLAT Default: 0xf
8145 06:53:52.924633 0, 0xFFFF, sum = 0
8146 06:53:52.927056 1, 0xFFFF, sum = 0
8147 06:53:52.930524 2, 0xFFFF, sum = 0
8148 06:53:52.930946 3, 0xFFFF, sum = 0
8149 06:53:52.933649 4, 0xFFFF, sum = 0
8150 06:53:52.934072 5, 0xFFFF, sum = 0
8151 06:53:52.936946 6, 0xFFFF, sum = 0
8152 06:53:52.937369 7, 0xFFFF, sum = 0
8153 06:53:52.940751 8, 0xFFFF, sum = 0
8154 06:53:52.941171 9, 0xFFFF, sum = 0
8155 06:53:52.944051 10, 0xFFFF, sum = 0
8156 06:53:52.944632 11, 0xFFFF, sum = 0
8157 06:53:52.947507 12, 0xFFFF, sum = 0
8158 06:53:52.947977 13, 0xFFFF, sum = 0
8159 06:53:52.950314 14, 0x0, sum = 1
8160 06:53:52.950753 15, 0x0, sum = 2
8161 06:53:52.953804 16, 0x0, sum = 3
8162 06:53:52.954335 17, 0x0, sum = 4
8163 06:53:52.957021 best_step = 15
8164 06:53:52.957525
8165 06:53:52.957868 ==
8166 06:53:52.960154 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 06:53:52.963868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 06:53:52.964443 ==
8169 06:53:52.966917 RX Vref Scan: 0
8170 06:53:52.967331
8171 06:53:52.967662 RX Vref 0 -> 0, step: 1
8172 06:53:52.968041
8173 06:53:52.970450 RX Delay 19 -> 252, step: 4
8174 06:53:52.973398 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8175 06:53:52.980245 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8176 06:53:52.983493 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8177 06:53:52.987312 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8178 06:53:52.990485 iDelay=191, Bit 4, Center 138 (87 ~ 190) 104
8179 06:53:52.993290 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8180 06:53:53.000105 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8181 06:53:53.003297 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8182 06:53:53.006585 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8183 06:53:53.010518 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8184 06:53:53.013551 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8185 06:53:53.020257 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8186 06:53:53.023432 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8187 06:53:53.026608 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8188 06:53:53.030174 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8189 06:53:53.036885 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8190 06:53:53.037308 ==
8191 06:53:53.039874 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 06:53:53.043758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 06:53:53.044170 ==
8194 06:53:53.044550 DQS Delay:
8195 06:53:53.046977 DQS0 = 0, DQS1 = 0
8196 06:53:53.047442 DQM Delay:
8197 06:53:53.049939 DQM0 = 134, DQM1 = 127
8198 06:53:53.050551 DQ Delay:
8199 06:53:53.053877 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8200 06:53:53.056927 DQ4 =138, DQ5 =126, DQ6 =140, DQ7 =140
8201 06:53:53.059963 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8202 06:53:53.063021 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8203 06:53:53.063430
8204 06:53:53.063754
8205 06:53:53.064053
8206 06:53:53.066301 [DramC_TX_OE_Calibration] TA2
8207 06:53:53.069581 Original DQ_B0 (3 6) =30, OEN = 27
8208 06:53:53.073213 Original DQ_B1 (3 6) =30, OEN = 27
8209 06:53:53.076702 24, 0x0, End_B0=24 End_B1=24
8210 06:53:53.080121 25, 0x0, End_B0=25 End_B1=25
8211 06:53:53.080579 26, 0x0, End_B0=26 End_B1=26
8212 06:53:53.082923 27, 0x0, End_B0=27 End_B1=27
8213 06:53:53.086530 28, 0x0, End_B0=28 End_B1=28
8214 06:53:53.089986 29, 0x0, End_B0=29 End_B1=29
8215 06:53:53.093264 30, 0x0, End_B0=30 End_B1=30
8216 06:53:53.093682 31, 0x4141, End_B0=30 End_B1=30
8217 06:53:53.096639 Byte0 end_step=30 best_step=27
8218 06:53:53.099617 Byte1 end_step=30 best_step=27
8219 06:53:53.103086 Byte0 TX OE(2T, 0.5T) = (3, 3)
8220 06:53:53.106504 Byte1 TX OE(2T, 0.5T) = (3, 3)
8221 06:53:53.107004
8222 06:53:53.107334
8223 06:53:53.113104 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
8224 06:53:53.116423 CH0 RK1: MR19=303, MR18=1F08
8225 06:53:53.122905 CH0_RK1: MR19=0x303, MR18=0x1F08, DQSOSC=394, MR23=63, INC=23, DEC=15
8226 06:53:53.126132 [RxdqsGatingPostProcess] freq 1600
8227 06:53:53.133051 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8228 06:53:53.133545 best DQS0 dly(2T, 0.5T) = (1, 1)
8229 06:53:53.136591 best DQS1 dly(2T, 0.5T) = (1, 1)
8230 06:53:53.139621 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8231 06:53:53.143348 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8232 06:53:53.146820 best DQS0 dly(2T, 0.5T) = (1, 1)
8233 06:53:53.149968 best DQS1 dly(2T, 0.5T) = (1, 1)
8234 06:53:53.153147 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8235 06:53:53.156365 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8236 06:53:53.159631 Pre-setting of DQS Precalculation
8237 06:53:53.162837 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8238 06:53:53.163285 ==
8239 06:53:53.166559 Dram Type= 6, Freq= 0, CH_1, rank 0
8240 06:53:53.173111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 06:53:53.173551 ==
8242 06:53:53.176224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8243 06:53:53.182813 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8244 06:53:53.186288 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8245 06:53:53.193180 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8246 06:53:53.200991 [CA 0] Center 42 (13~72) winsize 60
8247 06:53:53.203779 [CA 1] Center 42 (13~72) winsize 60
8248 06:53:53.207498 [CA 2] Center 38 (9~68) winsize 60
8249 06:53:53.210622 [CA 3] Center 38 (9~67) winsize 59
8250 06:53:53.214054 [CA 4] Center 38 (9~68) winsize 60
8251 06:53:53.217087 [CA 5] Center 38 (9~67) winsize 59
8252 06:53:53.217530
8253 06:53:53.220255 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8254 06:53:53.220741
8255 06:53:53.223562 [CATrainingPosCal] consider 1 rank data
8256 06:53:53.226836 u2DelayCellTimex100 = 290/100 ps
8257 06:53:53.230117 CA0 delay=42 (13~72),Diff = 4 PI (13 cell)
8258 06:53:53.236918 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8259 06:53:53.240245 CA2 delay=38 (9~68),Diff = 0 PI (0 cell)
8260 06:53:53.243442 CA3 delay=38 (9~67),Diff = 0 PI (0 cell)
8261 06:53:53.247294 CA4 delay=38 (9~68),Diff = 0 PI (0 cell)
8262 06:53:53.250237 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8263 06:53:53.250781
8264 06:53:53.253394 CA PerBit enable=1, Macro0, CA PI delay=38
8265 06:53:53.253824
8266 06:53:53.257426 [CBTSetCACLKResult] CA Dly = 38
8267 06:53:53.260521 CS Dly: 11 (0~42)
8268 06:53:53.263392 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8269 06:53:53.266822 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8270 06:53:53.267247 ==
8271 06:53:53.270181 Dram Type= 6, Freq= 0, CH_1, rank 1
8272 06:53:53.273570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 06:53:53.273995 ==
8274 06:53:53.280035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8275 06:53:53.283309 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8276 06:53:53.290266 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8277 06:53:53.293293 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8278 06:53:53.303654 [CA 0] Center 42 (12~72) winsize 61
8279 06:53:53.307062 [CA 1] Center 42 (12~72) winsize 61
8280 06:53:53.310554 [CA 2] Center 38 (9~68) winsize 60
8281 06:53:53.314305 [CA 3] Center 37 (8~67) winsize 60
8282 06:53:53.317495 [CA 4] Center 38 (8~68) winsize 61
8283 06:53:53.320322 [CA 5] Center 36 (7~66) winsize 60
8284 06:53:53.320742
8285 06:53:53.323812 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8286 06:53:53.324228
8287 06:53:53.327294 [CATrainingPosCal] consider 2 rank data
8288 06:53:53.330875 u2DelayCellTimex100 = 290/100 ps
8289 06:53:53.333868 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8290 06:53:53.340437 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8291 06:53:53.343897 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8292 06:53:53.347316 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8293 06:53:53.350052 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8294 06:53:53.353418 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8295 06:53:53.353927
8296 06:53:53.356610 CA PerBit enable=1, Macro0, CA PI delay=37
8297 06:53:53.357023
8298 06:53:53.360184 [CBTSetCACLKResult] CA Dly = 37
8299 06:53:53.363520 CS Dly: 12 (0~45)
8300 06:53:53.366815 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8301 06:53:53.369755 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8302 06:53:53.370043
8303 06:53:53.372994 ----->DramcWriteLeveling(PI) begin...
8304 06:53:53.373077 ==
8305 06:53:53.376514 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 06:53:53.379906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 06:53:53.383449 ==
8308 06:53:53.383524 Write leveling (Byte 0): 24 => 24
8309 06:53:53.386256 Write leveling (Byte 1): 27 => 27
8310 06:53:53.389627 DramcWriteLeveling(PI) end<-----
8311 06:53:53.389732
8312 06:53:53.389823 ==
8313 06:53:53.392987 Dram Type= 6, Freq= 0, CH_1, rank 0
8314 06:53:53.399856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 06:53:53.399955 ==
8316 06:53:53.400046 [Gating] SW mode calibration
8317 06:53:53.409411 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8318 06:53:53.413015 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8319 06:53:53.419755 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 06:53:53.423169 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 06:53:53.426643 1 4 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
8322 06:53:53.429437 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8323 06:53:53.436547 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 06:53:53.439927 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 06:53:53.443363 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 06:53:53.449560 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 06:53:53.453140 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 06:53:53.456364 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 06:53:53.463009 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
8330 06:53:53.466337 1 5 12 | B1->B0 | 2c2c 2323 | 1 0 | (0 1) (0 0)
8331 06:53:53.469744 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 06:53:53.476247 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 06:53:53.479609 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 06:53:53.482958 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 06:53:53.489760 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 06:53:53.493266 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 06:53:53.496878 1 6 8 | B1->B0 | 2424 4242 | 0 0 | (0 0) (0 0)
8338 06:53:53.503043 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 06:53:53.506481 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 06:53:53.509216 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 06:53:53.515970 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 06:53:53.519732 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 06:53:53.522880 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 06:53:53.529457 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 06:53:53.532840 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8346 06:53:53.535652 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8347 06:53:53.542487 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 06:53:53.546098 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 06:53:53.549332 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 06:53:53.555891 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 06:53:53.559631 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 06:53:53.562763 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 06:53:53.569301 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 06:53:53.572616 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 06:53:53.575888 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 06:53:53.582876 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 06:53:53.585988 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 06:53:53.589204 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 06:53:53.592769 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 06:53:53.599617 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 06:53:53.602419 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8362 06:53:53.605840 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8363 06:53:53.613105 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 06:53:53.616027 Total UI for P1: 0, mck2ui 16
8365 06:53:53.619173 best dqsien dly found for B0: ( 1, 9, 10)
8366 06:53:53.622600 Total UI for P1: 0, mck2ui 16
8367 06:53:53.625702 best dqsien dly found for B1: ( 1, 9, 10)
8368 06:53:53.629378 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8369 06:53:53.632649 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8370 06:53:53.633091
8371 06:53:53.635665 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8372 06:53:53.638944 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8373 06:53:53.642095 [Gating] SW calibration Done
8374 06:53:53.642498 ==
8375 06:53:53.645615 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 06:53:53.649175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 06:53:53.649581 ==
8378 06:53:53.652399 RX Vref Scan: 0
8379 06:53:53.652841
8380 06:53:53.655430 RX Vref 0 -> 0, step: 1
8381 06:53:53.655911
8382 06:53:53.656248 RX Delay 0 -> 252, step: 8
8383 06:53:53.662114 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8384 06:53:53.665777 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8385 06:53:53.668880 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8386 06:53:53.671986 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8387 06:53:53.675400 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8388 06:53:53.678731 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8389 06:53:53.685437 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8390 06:53:53.688890 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8391 06:53:53.692265 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8392 06:53:53.695366 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8393 06:53:53.698740 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8394 06:53:53.705570 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8395 06:53:53.708495 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8396 06:53:53.711966 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8397 06:53:53.715270 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8398 06:53:53.722011 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8399 06:53:53.722432 ==
8400 06:53:53.725455 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 06:53:53.728859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 06:53:53.729281 ==
8403 06:53:53.729610 DQS Delay:
8404 06:53:53.732359 DQS0 = 0, DQS1 = 0
8405 06:53:53.732782 DQM Delay:
8406 06:53:53.735166 DQM0 = 136, DQM1 = 132
8407 06:53:53.735581 DQ Delay:
8408 06:53:53.738460 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8409 06:53:53.741755 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8410 06:53:53.745635 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8411 06:53:53.748482 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8412 06:53:53.748894
8413 06:53:53.749230
8414 06:53:53.749526 ==
8415 06:53:53.751714 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 06:53:53.758340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 06:53:53.758790 ==
8418 06:53:53.759162
8419 06:53:53.759619
8420 06:53:53.759958 TX Vref Scan disable
8421 06:53:53.762509 == TX Byte 0 ==
8422 06:53:53.765348 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8423 06:53:53.772901 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8424 06:53:53.773321 == TX Byte 1 ==
8425 06:53:53.775673 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8426 06:53:53.782384 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8427 06:53:53.782803 ==
8428 06:53:53.785604 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 06:53:53.788627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 06:53:53.789053 ==
8431 06:53:53.801478
8432 06:53:53.804240 TX Vref early break, caculate TX vref
8433 06:53:53.807835 TX Vref=16, minBit 9, minWin=22, winSum=377
8434 06:53:53.811133 TX Vref=18, minBit 5, minWin=23, winSum=387
8435 06:53:53.814446 TX Vref=20, minBit 0, minWin=24, winSum=400
8436 06:53:53.817847 TX Vref=22, minBit 9, minWin=24, winSum=409
8437 06:53:53.820661 TX Vref=24, minBit 0, minWin=25, winSum=414
8438 06:53:53.827474 TX Vref=26, minBit 0, minWin=25, winSum=424
8439 06:53:53.830863 TX Vref=28, minBit 0, minWin=25, winSum=430
8440 06:53:53.834355 TX Vref=30, minBit 2, minWin=25, winSum=422
8441 06:53:53.837242 TX Vref=32, minBit 0, minWin=24, winSum=416
8442 06:53:53.840806 TX Vref=34, minBit 6, minWin=24, winSum=407
8443 06:53:53.847597 [TxChooseVref] Worse bit 0, Min win 25, Win sum 430, Final Vref 28
8444 06:53:53.847778
8445 06:53:53.850972 Final TX Range 0 Vref 28
8446 06:53:53.851152
8447 06:53:53.851293 ==
8448 06:53:53.854065 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 06:53:53.857224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 06:53:53.857405 ==
8451 06:53:53.857566
8452 06:53:53.857740
8453 06:53:53.860934 TX Vref Scan disable
8454 06:53:53.867596 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8455 06:53:53.867807 == TX Byte 0 ==
8456 06:53:53.870869 u2DelayCellOfst[0]=16 cells (5 PI)
8457 06:53:53.874325 u2DelayCellOfst[1]=10 cells (3 PI)
8458 06:53:53.877109 u2DelayCellOfst[2]=0 cells (0 PI)
8459 06:53:53.880941 u2DelayCellOfst[3]=6 cells (2 PI)
8460 06:53:53.884333 u2DelayCellOfst[4]=6 cells (2 PI)
8461 06:53:53.887588 u2DelayCellOfst[5]=16 cells (5 PI)
8462 06:53:53.890668 u2DelayCellOfst[6]=16 cells (5 PI)
8463 06:53:53.890878 u2DelayCellOfst[7]=6 cells (2 PI)
8464 06:53:53.897343 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8465 06:53:53.900473 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8466 06:53:53.900912 == TX Byte 1 ==
8467 06:53:53.903914 u2DelayCellOfst[8]=0 cells (0 PI)
8468 06:53:53.907220 u2DelayCellOfst[9]=3 cells (1 PI)
8469 06:53:53.910640 u2DelayCellOfst[10]=13 cells (4 PI)
8470 06:53:53.913820 u2DelayCellOfst[11]=3 cells (1 PI)
8471 06:53:53.917634 u2DelayCellOfst[12]=13 cells (4 PI)
8472 06:53:53.920871 u2DelayCellOfst[13]=16 cells (5 PI)
8473 06:53:53.924165 u2DelayCellOfst[14]=16 cells (5 PI)
8474 06:53:53.927504 u2DelayCellOfst[15]=16 cells (5 PI)
8475 06:53:53.930904 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8476 06:53:53.937108 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8477 06:53:53.937438 DramC Write-DBI on
8478 06:53:53.937769 ==
8479 06:53:53.940564 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 06:53:53.944011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 06:53:53.944370 ==
8482 06:53:53.944707
8483 06:53:53.947540
8484 06:53:53.947967 TX Vref Scan disable
8485 06:53:53.950989 == TX Byte 0 ==
8486 06:53:53.954443 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8487 06:53:53.957141 == TX Byte 1 ==
8488 06:53:53.960492 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8489 06:53:53.961000 DramC Write-DBI off
8490 06:53:53.961419
8491 06:53:53.964535 [DATLAT]
8492 06:53:53.964962 Freq=1600, CH1 RK0
8493 06:53:53.965395
8494 06:53:53.967530 DATLAT Default: 0xf
8495 06:53:53.968077 0, 0xFFFF, sum = 0
8496 06:53:53.970788 1, 0xFFFF, sum = 0
8497 06:53:53.971224 2, 0xFFFF, sum = 0
8498 06:53:53.974182 3, 0xFFFF, sum = 0
8499 06:53:53.974662 4, 0xFFFF, sum = 0
8500 06:53:53.977505 5, 0xFFFF, sum = 0
8501 06:53:53.977939 6, 0xFFFF, sum = 0
8502 06:53:53.980581 7, 0xFFFF, sum = 0
8503 06:53:53.983994 8, 0xFFFF, sum = 0
8504 06:53:53.984464 9, 0xFFFF, sum = 0
8505 06:53:53.987319 10, 0xFFFF, sum = 0
8506 06:53:53.987744 11, 0xFFFF, sum = 0
8507 06:53:53.990672 12, 0xFFFF, sum = 0
8508 06:53:53.991093 13, 0xFFFF, sum = 0
8509 06:53:53.994306 14, 0x0, sum = 1
8510 06:53:53.994758 15, 0x0, sum = 2
8511 06:53:53.997135 16, 0x0, sum = 3
8512 06:53:53.997553 17, 0x0, sum = 4
8513 06:53:54.000395 best_step = 15
8514 06:53:54.000813
8515 06:53:54.001138 ==
8516 06:53:54.004012 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 06:53:54.007006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 06:53:54.007492 ==
8519 06:53:54.007828 RX Vref Scan: 1
8520 06:53:54.008132
8521 06:53:54.010651 Set Vref Range= 24 -> 127
8522 06:53:54.011080
8523 06:53:54.013649 RX Vref 24 -> 127, step: 1
8524 06:53:54.014123
8525 06:53:54.017034 RX Delay 27 -> 252, step: 4
8526 06:53:54.017485
8527 06:53:54.020551 Set Vref, RX VrefLevel [Byte0]: 24
8528 06:53:54.023867 [Byte1]: 24
8529 06:53:54.024283
8530 06:53:54.026988 Set Vref, RX VrefLevel [Byte0]: 25
8531 06:53:54.030162 [Byte1]: 25
8532 06:53:54.030595
8533 06:53:54.033974 Set Vref, RX VrefLevel [Byte0]: 26
8534 06:53:54.037377 [Byte1]: 26
8535 06:53:54.040872
8536 06:53:54.041287 Set Vref, RX VrefLevel [Byte0]: 27
8537 06:53:54.044591 [Byte1]: 27
8538 06:53:54.048446
8539 06:53:54.048865 Set Vref, RX VrefLevel [Byte0]: 28
8540 06:53:54.051861 [Byte1]: 28
8541 06:53:54.056095
8542 06:53:54.056545 Set Vref, RX VrefLevel [Byte0]: 29
8543 06:53:54.058874 [Byte1]: 29
8544 06:53:54.063048
8545 06:53:54.063465 Set Vref, RX VrefLevel [Byte0]: 30
8546 06:53:54.066479 [Byte1]: 30
8547 06:53:54.070514
8548 06:53:54.070830 Set Vref, RX VrefLevel [Byte0]: 31
8549 06:53:54.073639 [Byte1]: 31
8550 06:53:54.077931
8551 06:53:54.078227 Set Vref, RX VrefLevel [Byte0]: 32
8552 06:53:54.081357 [Byte1]: 32
8553 06:53:54.086044
8554 06:53:54.086342 Set Vref, RX VrefLevel [Byte0]: 33
8555 06:53:54.089190 [Byte1]: 33
8556 06:53:54.093144
8557 06:53:54.093438 Set Vref, RX VrefLevel [Byte0]: 34
8558 06:53:54.096258 [Byte1]: 34
8559 06:53:54.100900
8560 06:53:54.101196 Set Vref, RX VrefLevel [Byte0]: 35
8561 06:53:54.103715 [Byte1]: 35
8562 06:53:54.108589
8563 06:53:54.108893 Set Vref, RX VrefLevel [Byte0]: 36
8564 06:53:54.111891 [Byte1]: 36
8565 06:53:54.115979
8566 06:53:54.116276 Set Vref, RX VrefLevel [Byte0]: 37
8567 06:53:54.119328 [Byte1]: 37
8568 06:53:54.123311
8569 06:53:54.123607 Set Vref, RX VrefLevel [Byte0]: 38
8570 06:53:54.126457 [Byte1]: 38
8571 06:53:54.130736
8572 06:53:54.131030 Set Vref, RX VrefLevel [Byte0]: 39
8573 06:53:54.134232 [Byte1]: 39
8574 06:53:54.138313
8575 06:53:54.138609 Set Vref, RX VrefLevel [Byte0]: 40
8576 06:53:54.141524 [Byte1]: 40
8577 06:53:54.145719
8578 06:53:54.146014 Set Vref, RX VrefLevel [Byte0]: 41
8579 06:53:54.149355 [Byte1]: 41
8580 06:53:54.153526
8581 06:53:54.153822 Set Vref, RX VrefLevel [Byte0]: 42
8582 06:53:54.156733 [Byte1]: 42
8583 06:53:54.161453
8584 06:53:54.161751 Set Vref, RX VrefLevel [Byte0]: 43
8585 06:53:54.164160 [Byte1]: 43
8586 06:53:54.168344
8587 06:53:54.168641 Set Vref, RX VrefLevel [Byte0]: 44
8588 06:53:54.171804 [Byte1]: 44
8589 06:53:54.175852
8590 06:53:54.176147 Set Vref, RX VrefLevel [Byte0]: 45
8591 06:53:54.179210 [Byte1]: 45
8592 06:53:54.183880
8593 06:53:54.184176 Set Vref, RX VrefLevel [Byte0]: 46
8594 06:53:54.187059 [Byte1]: 46
8595 06:53:54.191015
8596 06:53:54.191312 Set Vref, RX VrefLevel [Byte0]: 47
8597 06:53:54.194265 [Byte1]: 47
8598 06:53:54.198438
8599 06:53:54.198734 Set Vref, RX VrefLevel [Byte0]: 48
8600 06:53:54.201850 [Byte1]: 48
8601 06:53:54.206201
8602 06:53:54.206497 Set Vref, RX VrefLevel [Byte0]: 49
8603 06:53:54.209295 [Byte1]: 49
8604 06:53:54.213441
8605 06:53:54.213739 Set Vref, RX VrefLevel [Byte0]: 50
8606 06:53:54.216684 [Byte1]: 50
8607 06:53:54.220999
8608 06:53:54.221342 Set Vref, RX VrefLevel [Byte0]: 51
8609 06:53:54.227937 [Byte1]: 51
8610 06:53:54.228232
8611 06:53:54.230776 Set Vref, RX VrefLevel [Byte0]: 52
8612 06:53:54.234228 [Byte1]: 52
8613 06:53:54.234525
8614 06:53:54.237646 Set Vref, RX VrefLevel [Byte0]: 53
8615 06:53:54.241114 [Byte1]: 53
8616 06:53:54.241410
8617 06:53:54.244366 Set Vref, RX VrefLevel [Byte0]: 54
8618 06:53:54.247586 [Byte1]: 54
8619 06:53:54.251322
8620 06:53:54.251620 Set Vref, RX VrefLevel [Byte0]: 55
8621 06:53:54.254399 [Byte1]: 55
8622 06:53:54.258982
8623 06:53:54.259279 Set Vref, RX VrefLevel [Byte0]: 56
8624 06:53:54.262449 [Byte1]: 56
8625 06:53:54.266528
8626 06:53:54.266822 Set Vref, RX VrefLevel [Byte0]: 57
8627 06:53:54.269688 [Byte1]: 57
8628 06:53:54.273746
8629 06:53:54.273969 Set Vref, RX VrefLevel [Byte0]: 58
8630 06:53:54.277385 [Byte1]: 58
8631 06:53:54.281281
8632 06:53:54.281468 Set Vref, RX VrefLevel [Byte0]: 59
8633 06:53:54.284725 [Byte1]: 59
8634 06:53:54.288856
8635 06:53:54.289044 Set Vref, RX VrefLevel [Byte0]: 60
8636 06:53:54.292154 [Byte1]: 60
8637 06:53:54.296472
8638 06:53:54.296649 Set Vref, RX VrefLevel [Byte0]: 61
8639 06:53:54.299728 [Byte1]: 61
8640 06:53:54.303883
8641 06:53:54.304061 Set Vref, RX VrefLevel [Byte0]: 62
8642 06:53:54.307334 [Byte1]: 62
8643 06:53:54.311465
8644 06:53:54.311673 Set Vref, RX VrefLevel [Byte0]: 63
8645 06:53:54.314769 [Byte1]: 63
8646 06:53:54.319269
8647 06:53:54.319522 Set Vref, RX VrefLevel [Byte0]: 64
8648 06:53:54.322294 [Byte1]: 64
8649 06:53:54.327071
8650 06:53:54.327485 Set Vref, RX VrefLevel [Byte0]: 65
8651 06:53:54.329972 [Byte1]: 65
8652 06:53:54.334844
8653 06:53:54.335261 Set Vref, RX VrefLevel [Byte0]: 66
8654 06:53:54.337541 [Byte1]: 66
8655 06:53:54.341723
8656 06:53:54.342137 Set Vref, RX VrefLevel [Byte0]: 67
8657 06:53:54.345240 [Byte1]: 67
8658 06:53:54.349281
8659 06:53:54.349695 Set Vref, RX VrefLevel [Byte0]: 68
8660 06:53:54.352500 [Byte1]: 68
8661 06:53:54.356731
8662 06:53:54.356953 Set Vref, RX VrefLevel [Byte0]: 69
8663 06:53:54.360159 [Byte1]: 69
8664 06:53:54.364236
8665 06:53:54.364430 Set Vref, RX VrefLevel [Byte0]: 70
8666 06:53:54.367469 [Byte1]: 70
8667 06:53:54.371940
8668 06:53:54.372133 Set Vref, RX VrefLevel [Byte0]: 71
8669 06:53:54.375320 [Byte1]: 71
8670 06:53:54.379010
8671 06:53:54.379159 Set Vref, RX VrefLevel [Byte0]: 72
8672 06:53:54.382513 [Byte1]: 72
8673 06:53:54.386463
8674 06:53:54.386612 Set Vref, RX VrefLevel [Byte0]: 73
8675 06:53:54.390317 [Byte1]: 73
8676 06:53:54.394041
8677 06:53:54.394225 Set Vref, RX VrefLevel [Byte0]: 74
8678 06:53:54.397635 [Byte1]: 74
8679 06:53:54.401924
8680 06:53:54.402072 Set Vref, RX VrefLevel [Byte0]: 75
8681 06:53:54.405618 [Byte1]: 75
8682 06:53:54.409503
8683 06:53:54.409673 Set Vref, RX VrefLevel [Byte0]: 76
8684 06:53:54.412647 [Byte1]: 76
8685 06:53:54.416832
8686 06:53:54.417067 Final RX Vref Byte 0 = 57 to rank0
8687 06:53:54.420337 Final RX Vref Byte 1 = 57 to rank0
8688 06:53:54.423830 Final RX Vref Byte 0 = 57 to rank1
8689 06:53:54.427521 Final RX Vref Byte 1 = 57 to rank1==
8690 06:53:54.430416 Dram Type= 6, Freq= 0, CH_1, rank 0
8691 06:53:54.437065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8692 06:53:54.437364 ==
8693 06:53:54.437621 DQS Delay:
8694 06:53:54.437843 DQS0 = 0, DQS1 = 0
8695 06:53:54.440027 DQM Delay:
8696 06:53:54.440355 DQM0 = 134, DQM1 = 131
8697 06:53:54.443445 DQ Delay:
8698 06:53:54.446857 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8699 06:53:54.450331 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8700 06:53:54.453858 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8701 06:53:54.456740 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8702 06:53:54.457041
8703 06:53:54.457272
8704 06:53:54.457485
8705 06:53:54.460026 [DramC_TX_OE_Calibration] TA2
8706 06:53:54.463571 Original DQ_B0 (3 6) =30, OEN = 27
8707 06:53:54.466827 Original DQ_B1 (3 6) =30, OEN = 27
8708 06:53:54.470071 24, 0x0, End_B0=24 End_B1=24
8709 06:53:54.470183 25, 0x0, End_B0=25 End_B1=25
8710 06:53:54.473779 26, 0x0, End_B0=26 End_B1=26
8711 06:53:54.477067 27, 0x0, End_B0=27 End_B1=27
8712 06:53:54.480124 28, 0x0, End_B0=28 End_B1=28
8713 06:53:54.480222 29, 0x0, End_B0=29 End_B1=29
8714 06:53:54.483552 30, 0x0, End_B0=30 End_B1=30
8715 06:53:54.487000 31, 0x5151, End_B0=30 End_B1=30
8716 06:53:54.490260 Byte0 end_step=30 best_step=27
8717 06:53:54.493322 Byte1 end_step=30 best_step=27
8718 06:53:54.496563 Byte0 TX OE(2T, 0.5T) = (3, 3)
8719 06:53:54.496664 Byte1 TX OE(2T, 0.5T) = (3, 3)
8720 06:53:54.499854
8721 06:53:54.499955
8722 06:53:54.506544 [DQSOSCAuto] RK0, (LSB)MR18= 0x1522, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8723 06:53:54.510005 CH1 RK0: MR19=303, MR18=1522
8724 06:53:54.516444 CH1_RK0: MR19=0x303, MR18=0x1522, DQSOSC=392, MR23=63, INC=24, DEC=16
8725 06:53:54.516642
8726 06:53:54.520104 ----->DramcWriteLeveling(PI) begin...
8727 06:53:54.520327 ==
8728 06:53:54.523638 Dram Type= 6, Freq= 0, CH_1, rank 1
8729 06:53:54.526916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8730 06:53:54.527123 ==
8731 06:53:54.529836 Write leveling (Byte 0): 25 => 25
8732 06:53:54.533705 Write leveling (Byte 1): 28 => 28
8733 06:53:54.537186 DramcWriteLeveling(PI) end<-----
8734 06:53:54.537484
8735 06:53:54.537718 ==
8736 06:53:54.540559 Dram Type= 6, Freq= 0, CH_1, rank 1
8737 06:53:54.544015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 06:53:54.544446 ==
8739 06:53:54.547197 [Gating] SW mode calibration
8740 06:53:54.553620 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8741 06:53:54.560562 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8742 06:53:54.563315 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 06:53:54.566783 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 06:53:54.573785 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8745 06:53:54.576732 1 4 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 1)
8746 06:53:54.580115 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 06:53:54.586843 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 06:53:54.590054 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 06:53:54.593573 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 06:53:54.600135 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 06:53:54.603279 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8752 06:53:54.607083 1 5 8 | B1->B0 | 3131 3434 | 0 1 | (0 1) (1 0)
8753 06:53:54.613443 1 5 12 | B1->B0 | 2424 2b2b | 0 0 | (1 1) (0 0)
8754 06:53:54.616327 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 06:53:54.619781 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 06:53:54.626595 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 06:53:54.630017 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 06:53:54.633354 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 06:53:54.639578 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 06:53:54.643333 1 6 8 | B1->B0 | 3a3a 2323 | 0 0 | (0 0) (0 0)
8761 06:53:54.646241 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8762 06:53:54.652791 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 06:53:54.655867 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 06:53:54.659820 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 06:53:54.665873 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 06:53:54.669582 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 06:53:54.672861 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8768 06:53:54.679655 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8769 06:53:54.682380 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8770 06:53:54.685922 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8771 06:53:54.692772 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 06:53:54.695942 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 06:53:54.699132 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 06:53:54.705406 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 06:53:54.709163 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 06:53:54.712411 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 06:53:54.718865 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 06:53:54.722095 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 06:53:54.725479 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 06:53:54.732267 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 06:53:54.735812 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 06:53:54.739172 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 06:53:54.741863 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8784 06:53:54.748920 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8785 06:53:54.752326 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8786 06:53:54.755515 Total UI for P1: 0, mck2ui 16
8787 06:53:54.758639 best dqsien dly found for B1: ( 1, 9, 6)
8788 06:53:54.762551 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 06:53:54.765672 Total UI for P1: 0, mck2ui 16
8790 06:53:54.768924 best dqsien dly found for B0: ( 1, 9, 12)
8791 06:53:54.771850 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8792 06:53:54.774904 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8793 06:53:54.778901
8794 06:53:54.781771 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8795 06:53:54.785000 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8796 06:53:54.788609 [Gating] SW calibration Done
8797 06:53:54.788841 ==
8798 06:53:54.791954 Dram Type= 6, Freq= 0, CH_1, rank 1
8799 06:53:54.795452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 06:53:54.795685 ==
8801 06:53:54.795868 RX Vref Scan: 0
8802 06:53:54.796041
8803 06:53:54.798918 RX Vref 0 -> 0, step: 1
8804 06:53:54.799149
8805 06:53:54.801577 RX Delay 0 -> 252, step: 8
8806 06:53:54.805327 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8807 06:53:54.808780 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8808 06:53:54.815040 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8809 06:53:54.818342 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8810 06:53:54.821794 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8811 06:53:54.825090 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8812 06:53:54.828607 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8813 06:53:54.832579 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8814 06:53:54.838682 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8815 06:53:54.841903 iDelay=208, Bit 9, Center 123 (72 ~ 175) 104
8816 06:53:54.845124 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8817 06:53:54.848597 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8818 06:53:54.855495 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8819 06:53:54.858261 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8820 06:53:54.862222 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8821 06:53:54.865397 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8822 06:53:54.865865 ==
8823 06:53:54.868804 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 06:53:54.874823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 06:53:54.875237 ==
8826 06:53:54.875569 DQS Delay:
8827 06:53:54.875922 DQS0 = 0, DQS1 = 0
8828 06:53:54.878781 DQM Delay:
8829 06:53:54.879188 DQM0 = 136, DQM1 = 134
8830 06:53:54.882106 DQ Delay:
8831 06:53:54.885342 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8832 06:53:54.888358 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8833 06:53:54.891588 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8834 06:53:54.895188 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8835 06:53:54.895613
8836 06:53:54.896100
8837 06:53:54.896569 ==
8838 06:53:54.898332 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 06:53:54.901721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 06:53:54.905337 ==
8841 06:53:54.905744
8842 06:53:54.906065
8843 06:53:54.906363 TX Vref Scan disable
8844 06:53:54.908739 == TX Byte 0 ==
8845 06:53:54.911435 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8846 06:53:54.915284 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8847 06:53:54.918700 == TX Byte 1 ==
8848 06:53:54.921848 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8849 06:53:54.925236 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8850 06:53:54.925649 ==
8851 06:53:54.928749 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 06:53:54.934977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 06:53:54.935449 ==
8854 06:53:54.946924
8855 06:53:54.949612 TX Vref early break, caculate TX vref
8856 06:53:54.953610 TX Vref=16, minBit 2, minWin=23, winSum=384
8857 06:53:54.956359 TX Vref=18, minBit 0, minWin=23, winSum=392
8858 06:53:54.959967 TX Vref=20, minBit 1, minWin=24, winSum=402
8859 06:53:54.963371 TX Vref=22, minBit 0, minWin=24, winSum=412
8860 06:53:54.966706 TX Vref=24, minBit 0, minWin=25, winSum=419
8861 06:53:54.973033 TX Vref=26, minBit 0, minWin=25, winSum=422
8862 06:53:54.976400 TX Vref=28, minBit 0, minWin=25, winSum=429
8863 06:53:54.979837 TX Vref=30, minBit 0, minWin=25, winSum=418
8864 06:53:54.983420 TX Vref=32, minBit 0, minWin=25, winSum=414
8865 06:53:54.986885 TX Vref=34, minBit 0, minWin=24, winSum=403
8866 06:53:54.992959 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 28
8867 06:53:54.993368
8868 06:53:54.996216 Final TX Range 0 Vref 28
8869 06:53:54.996676
8870 06:53:54.996999 ==
8871 06:53:55.000060 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 06:53:55.003324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 06:53:55.003773 ==
8874 06:53:55.004099
8875 06:53:55.004443
8876 06:53:55.006669 TX Vref Scan disable
8877 06:53:55.013300 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8878 06:53:55.013720 == TX Byte 0 ==
8879 06:53:55.016452 u2DelayCellOfst[0]=16 cells (5 PI)
8880 06:53:55.019468 u2DelayCellOfst[1]=10 cells (3 PI)
8881 06:53:55.023082 u2DelayCellOfst[2]=0 cells (0 PI)
8882 06:53:55.026344 u2DelayCellOfst[3]=6 cells (2 PI)
8883 06:53:55.029388 u2DelayCellOfst[4]=10 cells (3 PI)
8884 06:53:55.033399 u2DelayCellOfst[5]=16 cells (5 PI)
8885 06:53:55.036136 u2DelayCellOfst[6]=20 cells (6 PI)
8886 06:53:55.036602 u2DelayCellOfst[7]=6 cells (2 PI)
8887 06:53:55.043049 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8888 06:53:55.046405 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8889 06:53:55.046824 == TX Byte 1 ==
8890 06:53:55.049805 u2DelayCellOfst[8]=0 cells (0 PI)
8891 06:53:55.053091 u2DelayCellOfst[9]=3 cells (1 PI)
8892 06:53:55.056408 u2DelayCellOfst[10]=10 cells (3 PI)
8893 06:53:55.059781 u2DelayCellOfst[11]=6 cells (2 PI)
8894 06:53:55.063221 u2DelayCellOfst[12]=13 cells (4 PI)
8895 06:53:55.066640 u2DelayCellOfst[13]=13 cells (4 PI)
8896 06:53:55.069564 u2DelayCellOfst[14]=16 cells (5 PI)
8897 06:53:55.072936 u2DelayCellOfst[15]=16 cells (5 PI)
8898 06:53:55.076405 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8899 06:53:55.079878 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8900 06:53:55.082985 DramC Write-DBI on
8901 06:53:55.083424 ==
8902 06:53:55.086067 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 06:53:55.089619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 06:53:55.089980 ==
8905 06:53:55.090294
8906 06:53:55.093099
8907 06:53:55.093509 TX Vref Scan disable
8908 06:53:55.096456 == TX Byte 0 ==
8909 06:53:55.099971 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8910 06:53:55.103290 == TX Byte 1 ==
8911 06:53:55.106480 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8912 06:53:55.106895 DramC Write-DBI off
8913 06:53:55.107252
8914 06:53:55.109766 [DATLAT]
8915 06:53:55.110177 Freq=1600, CH1 RK1
8916 06:53:55.110503
8917 06:53:55.112823 DATLAT Default: 0xf
8918 06:53:55.113233 0, 0xFFFF, sum = 0
8919 06:53:55.116337 1, 0xFFFF, sum = 0
8920 06:53:55.116759 2, 0xFFFF, sum = 0
8921 06:53:55.119850 3, 0xFFFF, sum = 0
8922 06:53:55.120269 4, 0xFFFF, sum = 0
8923 06:53:55.122639 5, 0xFFFF, sum = 0
8924 06:53:55.123052 6, 0xFFFF, sum = 0
8925 06:53:55.126064 7, 0xFFFF, sum = 0
8926 06:53:55.129254 8, 0xFFFF, sum = 0
8927 06:53:55.129671 9, 0xFFFF, sum = 0
8928 06:53:55.133019 10, 0xFFFF, sum = 0
8929 06:53:55.133467 11, 0xFFFF, sum = 0
8930 06:53:55.136140 12, 0xFFFF, sum = 0
8931 06:53:55.136605 13, 0xFFFF, sum = 0
8932 06:53:55.139462 14, 0x0, sum = 1
8933 06:53:55.139874 15, 0x0, sum = 2
8934 06:53:55.142871 16, 0x0, sum = 3
8935 06:53:55.143291 17, 0x0, sum = 4
8936 06:53:55.143738 best_step = 15
8937 06:53:55.145974
8938 06:53:55.146495 ==
8939 06:53:55.149681 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 06:53:55.152447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 06:53:55.152864 ==
8942 06:53:55.153189 RX Vref Scan: 0
8943 06:53:55.153496
8944 06:53:55.155653 RX Vref 0 -> 0, step: 1
8945 06:53:55.156066
8946 06:53:55.159542 RX Delay 19 -> 252, step: 4
8947 06:53:55.162836 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8948 06:53:55.169055 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8949 06:53:55.172460 iDelay=195, Bit 2, Center 124 (75 ~ 174) 100
8950 06:53:55.175974 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8951 06:53:55.179402 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8952 06:53:55.182779 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8953 06:53:55.186245 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8954 06:53:55.192645 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8955 06:53:55.195827 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8956 06:53:55.199118 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8957 06:53:55.202577 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8958 06:53:55.205961 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8959 06:53:55.212601 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8960 06:53:55.215846 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8961 06:53:55.219177 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8962 06:53:55.222357 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8963 06:53:55.222775 ==
8964 06:53:55.225746 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 06:53:55.232441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 06:53:55.232859 ==
8967 06:53:55.233184 DQS Delay:
8968 06:53:55.233490 DQS0 = 0, DQS1 = 0
8969 06:53:55.235795 DQM Delay:
8970 06:53:55.236209 DQM0 = 134, DQM1 = 130
8971 06:53:55.239323 DQ Delay:
8972 06:53:55.242866 DQ0 =138, DQ1 =132, DQ2 =124, DQ3 =130
8973 06:53:55.245634 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8974 06:53:55.249636 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8975 06:53:55.253158 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8976 06:53:55.253574
8977 06:53:55.254008
8978 06:53:55.254340
8979 06:53:55.255996 [DramC_TX_OE_Calibration] TA2
8980 06:53:55.259032 Original DQ_B0 (3 6) =30, OEN = 27
8981 06:53:55.262273 Original DQ_B1 (3 6) =30, OEN = 27
8982 06:53:55.265842 24, 0x0, End_B0=24 End_B1=24
8983 06:53:55.266264 25, 0x0, End_B0=25 End_B1=25
8984 06:53:55.269287 26, 0x0, End_B0=26 End_B1=26
8985 06:53:55.272619 27, 0x0, End_B0=27 End_B1=27
8986 06:53:55.275674 28, 0x0, End_B0=28 End_B1=28
8987 06:53:55.276097 29, 0x0, End_B0=29 End_B1=29
8988 06:53:55.278784 30, 0x0, End_B0=30 End_B1=30
8989 06:53:55.282550 31, 0x4141, End_B0=30 End_B1=30
8990 06:53:55.285687 Byte0 end_step=30 best_step=27
8991 06:53:55.289219 Byte1 end_step=30 best_step=27
8992 06:53:55.292457 Byte0 TX OE(2T, 0.5T) = (3, 3)
8993 06:53:55.295317 Byte1 TX OE(2T, 0.5T) = (3, 3)
8994 06:53:55.295732
8995 06:53:55.296063
8996 06:53:55.302355 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
8997 06:53:55.305450 CH1 RK1: MR19=303, MR18=2409
8998 06:53:55.312423 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
8999 06:53:55.315307 [RxdqsGatingPostProcess] freq 1600
9000 06:53:55.318652 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9001 06:53:55.321941 best DQS0 dly(2T, 0.5T) = (1, 1)
9002 06:53:55.325796 best DQS1 dly(2T, 0.5T) = (1, 1)
9003 06:53:55.328402 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9004 06:53:55.332381 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9005 06:53:55.335788 best DQS0 dly(2T, 0.5T) = (1, 1)
9006 06:53:55.338598 best DQS1 dly(2T, 0.5T) = (1, 1)
9007 06:53:55.342079 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9008 06:53:55.345486 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9009 06:53:55.348916 Pre-setting of DQS Precalculation
9010 06:53:55.351820 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9011 06:53:55.358906 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9012 06:53:55.365154 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9013 06:53:55.365587
9014 06:53:55.368669
9015 06:53:55.369068 [Calibration Summary] 3200 Mbps
9016 06:53:55.372081 CH 0, Rank 0
9017 06:53:55.372701 SW Impedance : PASS
9018 06:53:55.375298 DUTY Scan : NO K
9019 06:53:55.378550 ZQ Calibration : PASS
9020 06:53:55.379122 Jitter Meter : NO K
9021 06:53:55.381719 CBT Training : PASS
9022 06:53:55.385333 Write leveling : PASS
9023 06:53:55.385940 RX DQS gating : PASS
9024 06:53:55.388132 RX DQ/DQS(RDDQC) : PASS
9025 06:53:55.391757 TX DQ/DQS : PASS
9026 06:53:55.392341 RX DATLAT : PASS
9027 06:53:55.394996 RX DQ/DQS(Engine): PASS
9028 06:53:55.398426 TX OE : PASS
9029 06:53:55.399009 All Pass.
9030 06:53:55.399509
9031 06:53:55.399880 CH 0, Rank 1
9032 06:53:55.401938 SW Impedance : PASS
9033 06:53:55.405571 DUTY Scan : NO K
9034 06:53:55.406177 ZQ Calibration : PASS
9035 06:53:55.408646 Jitter Meter : NO K
9036 06:53:55.411886 CBT Training : PASS
9037 06:53:55.412498 Write leveling : PASS
9038 06:53:55.414854 RX DQS gating : PASS
9039 06:53:55.415418 RX DQ/DQS(RDDQC) : PASS
9040 06:53:55.418426 TX DQ/DQS : PASS
9041 06:53:55.421636 RX DATLAT : PASS
9042 06:53:55.422094 RX DQ/DQS(Engine): PASS
9043 06:53:55.425363 TX OE : PASS
9044 06:53:55.425797 All Pass.
9045 06:53:55.426125
9046 06:53:55.428693 CH 1, Rank 0
9047 06:53:55.429106 SW Impedance : PASS
9048 06:53:55.431741 DUTY Scan : NO K
9049 06:53:55.434983 ZQ Calibration : PASS
9050 06:53:55.435402 Jitter Meter : NO K
9051 06:53:55.438193 CBT Training : PASS
9052 06:53:55.442099 Write leveling : PASS
9053 06:53:55.442535 RX DQS gating : PASS
9054 06:53:55.444805 RX DQ/DQS(RDDQC) : PASS
9055 06:53:55.448069 TX DQ/DQS : PASS
9056 06:53:55.448543 RX DATLAT : PASS
9057 06:53:55.451721 RX DQ/DQS(Engine): PASS
9058 06:53:55.455167 TX OE : PASS
9059 06:53:55.455587 All Pass.
9060 06:53:55.455914
9061 06:53:55.456218 CH 1, Rank 1
9062 06:53:55.458591 SW Impedance : PASS
9063 06:53:55.461268 DUTY Scan : NO K
9064 06:53:55.461685 ZQ Calibration : PASS
9065 06:53:55.464891 Jitter Meter : NO K
9066 06:53:55.465308 CBT Training : PASS
9067 06:53:55.468393 Write leveling : PASS
9068 06:53:55.471758 RX DQS gating : PASS
9069 06:53:55.472177 RX DQ/DQS(RDDQC) : PASS
9070 06:53:55.474674 TX DQ/DQS : PASS
9071 06:53:55.478576 RX DATLAT : PASS
9072 06:53:55.478997 RX DQ/DQS(Engine): PASS
9073 06:53:55.481271 TX OE : PASS
9074 06:53:55.481689 All Pass.
9075 06:53:55.482060
9076 06:53:55.484833 DramC Write-DBI on
9077 06:53:55.488209 PER_BANK_REFRESH: Hybrid Mode
9078 06:53:55.488711 TX_TRACKING: ON
9079 06:53:55.498074 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9080 06:53:55.504729 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9081 06:53:55.511554 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9082 06:53:55.517874 [FAST_K] Save calibration result to emmc
9083 06:53:55.518506 sync common calibartion params.
9084 06:53:55.521314 sync cbt_mode0:1, 1:1
9085 06:53:55.524586 dram_init: ddr_geometry: 2
9086 06:53:55.525241 dram_init: ddr_geometry: 2
9087 06:53:55.527675 dram_init: ddr_geometry: 2
9088 06:53:55.531357 0:dram_rank_size:100000000
9089 06:53:55.534294 1:dram_rank_size:100000000
9090 06:53:55.537983 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9091 06:53:55.541100 DFS_SHUFFLE_HW_MODE: ON
9092 06:53:55.544359 dramc_set_vcore_voltage set vcore to 725000
9093 06:53:55.547503 Read voltage for 1600, 0
9094 06:53:55.548032 Vio18 = 0
9095 06:53:55.551106 Vcore = 725000
9096 06:53:55.551541 Vdram = 0
9097 06:53:55.551861 Vddq = 0
9098 06:53:55.552158 Vmddr = 0
9099 06:53:55.554453 switch to 3200 Mbps bootup
9100 06:53:55.557857 [DramcRunTimeConfig]
9101 06:53:55.558266 PHYPLL
9102 06:53:55.558589 DPM_CONTROL_AFTERK: ON
9103 06:53:55.561085 PER_BANK_REFRESH: ON
9104 06:53:55.564237 REFRESH_OVERHEAD_REDUCTION: ON
9105 06:53:55.564725 CMD_PICG_NEW_MODE: OFF
9106 06:53:55.567753 XRTWTW_NEW_MODE: ON
9107 06:53:55.571046 XRTRTR_NEW_MODE: ON
9108 06:53:55.571642 TX_TRACKING: ON
9109 06:53:55.574502 RDSEL_TRACKING: OFF
9110 06:53:55.575038 DQS Precalculation for DVFS: ON
9111 06:53:55.578027 RX_TRACKING: OFF
9112 06:53:55.578623 HW_GATING DBG: ON
9113 06:53:55.580811 ZQCS_ENABLE_LP4: ON
9114 06:53:55.581343 RX_PICG_NEW_MODE: ON
9115 06:53:55.584149 TX_PICG_NEW_MODE: ON
9116 06:53:55.587661 ENABLE_RX_DCM_DPHY: ON
9117 06:53:55.591268 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9118 06:53:55.591881 DUMMY_READ_FOR_TRACKING: OFF
9119 06:53:55.594079 !!! SPM_CONTROL_AFTERK: OFF
9120 06:53:55.597428 !!! SPM could not control APHY
9121 06:53:55.601043 IMPEDANCE_TRACKING: ON
9122 06:53:55.601624 TEMP_SENSOR: ON
9123 06:53:55.604171 HW_SAVE_FOR_SR: OFF
9124 06:53:55.604732 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9125 06:53:55.610811 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9126 06:53:55.611335 Read ODT Tracking: ON
9127 06:53:55.614230 Refresh Rate DeBounce: ON
9128 06:53:55.617390 DFS_NO_QUEUE_FLUSH: ON
9129 06:53:55.617799 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9130 06:53:55.620835 ENABLE_DFS_RUNTIME_MRW: OFF
9131 06:53:55.624391 DDR_RESERVE_NEW_MODE: ON
9132 06:53:55.627001 MR_CBT_SWITCH_FREQ: ON
9133 06:53:55.627435 =========================
9134 06:53:55.647011 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9135 06:53:55.650420 dram_init: ddr_geometry: 2
9136 06:53:55.668620 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9137 06:53:55.671737 dram_init: dram init end (result: 0)
9138 06:53:55.678638 DRAM-K: Full calibration passed in 24458 msecs
9139 06:53:55.681801 MRC: failed to locate region type 0.
9140 06:53:55.682368 DRAM rank0 size:0x100000000,
9141 06:53:55.685072 DRAM rank1 size=0x100000000
9142 06:53:55.694891 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9143 06:53:55.701870 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9144 06:53:55.708143 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9145 06:53:55.714903 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9146 06:53:55.718491 DRAM rank0 size:0x100000000,
9147 06:53:55.721566 DRAM rank1 size=0x100000000
9148 06:53:55.722170 CBMEM:
9149 06:53:55.724841 IMD: root @ 0xfffff000 254 entries.
9150 06:53:55.728412 IMD: root @ 0xffffec00 62 entries.
9151 06:53:55.731895 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9152 06:53:55.735209 WARNING: RO_VPD is uninitialized or empty.
9153 06:53:55.741457 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9154 06:53:55.749073 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9155 06:53:55.761400 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9156 06:53:55.772639 BS: romstage times (exec / console): total (unknown) / 23985 ms
9157 06:53:55.773223
9158 06:53:55.773691
9159 06:53:55.782887 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9160 06:53:55.786318 ARM64: Exception handlers installed.
9161 06:53:55.788981 ARM64: Testing exception
9162 06:53:55.792539 ARM64: Done test exception
9163 06:53:55.792968 Enumerating buses...
9164 06:53:55.795681 Show all devs... Before device enumeration.
9165 06:53:55.798880 Root Device: enabled 1
9166 06:53:55.802272 CPU_CLUSTER: 0: enabled 1
9167 06:53:55.802689 CPU: 00: enabled 1
9168 06:53:55.805623 Compare with tree...
9169 06:53:55.806040 Root Device: enabled 1
9170 06:53:55.808920 CPU_CLUSTER: 0: enabled 1
9171 06:53:55.812165 CPU: 00: enabled 1
9172 06:53:55.812643 Root Device scanning...
9173 06:53:55.815930 scan_static_bus for Root Device
9174 06:53:55.819116 CPU_CLUSTER: 0 enabled
9175 06:53:55.822141 scan_static_bus for Root Device done
9176 06:53:55.825697 scan_bus: bus Root Device finished in 8 msecs
9177 06:53:55.826116 done
9178 06:53:55.832263 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9179 06:53:55.835324 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9180 06:53:55.842640 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9181 06:53:55.845700 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9182 06:53:55.849073 Allocating resources...
9183 06:53:55.852510 Reading resources...
9184 06:53:55.855999 Root Device read_resources bus 0 link: 0
9185 06:53:55.856538 DRAM rank0 size:0x100000000,
9186 06:53:55.858804 DRAM rank1 size=0x100000000
9187 06:53:55.862295 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9188 06:53:55.865636 CPU: 00 missing read_resources
9189 06:53:55.871912 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9190 06:53:55.875389 Root Device read_resources bus 0 link: 0 done
9191 06:53:55.875918 Done reading resources.
9192 06:53:55.882185 Show resources in subtree (Root Device)...After reading.
9193 06:53:55.885346 Root Device child on link 0 CPU_CLUSTER: 0
9194 06:53:55.889135 CPU_CLUSTER: 0 child on link 0 CPU: 00
9195 06:53:55.899155 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9196 06:53:55.899580 CPU: 00
9197 06:53:55.901708 Root Device assign_resources, bus 0 link: 0
9198 06:53:55.905274 CPU_CLUSTER: 0 missing set_resources
9199 06:53:55.911802 Root Device assign_resources, bus 0 link: 0 done
9200 06:53:55.912219 Done setting resources.
9201 06:53:55.918765 Show resources in subtree (Root Device)...After assigning values.
9202 06:53:55.922171 Root Device child on link 0 CPU_CLUSTER: 0
9203 06:53:55.925055 CPU_CLUSTER: 0 child on link 0 CPU: 00
9204 06:53:55.935185 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9205 06:53:55.935607 CPU: 00
9206 06:53:55.938700 Done allocating resources.
9207 06:53:55.944733 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9208 06:53:55.945150 Enabling resources...
9209 06:53:55.945481 done.
9210 06:53:55.951610 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9211 06:53:55.952029 Initializing devices...
9212 06:53:55.955237 Root Device init
9213 06:53:55.955710 init hardware done!
9214 06:53:55.958163 0x00000018: ctrlr->caps
9215 06:53:55.961729 52.000 MHz: ctrlr->f_max
9216 06:53:55.962328 0.400 MHz: ctrlr->f_min
9217 06:53:55.964900 0x40ff8080: ctrlr->voltages
9218 06:53:55.968335 sclk: 390625
9219 06:53:55.968752 Bus Width = 1
9220 06:53:55.969080 sclk: 390625
9221 06:53:55.971444 Bus Width = 1
9222 06:53:55.971986 Early init status = 3
9223 06:53:55.978286 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9224 06:53:55.981769 in-header: 03 fc 00 00 01 00 00 00
9225 06:53:55.982186 in-data: 00
9226 06:53:55.988033 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9227 06:53:55.991920 in-header: 03 fd 00 00 00 00 00 00
9228 06:53:55.995146 in-data:
9229 06:53:55.998361 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9230 06:53:56.002358 in-header: 03 fc 00 00 01 00 00 00
9231 06:53:56.005456 in-data: 00
9232 06:53:56.009393 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9233 06:53:56.014143 in-header: 03 fd 00 00 00 00 00 00
9234 06:53:56.018054 in-data:
9235 06:53:56.021664 [SSUSB] Setting up USB HOST controller...
9236 06:53:56.024347 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9237 06:53:56.027700 [SSUSB] phy power-on done.
9238 06:53:56.031353 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9239 06:53:56.037510 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9240 06:53:56.040935 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9241 06:53:56.047811 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9242 06:53:56.054007 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9243 06:53:56.061036 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9244 06:53:56.067855 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9245 06:53:56.074072 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9246 06:53:56.077180 SPM: binary array size = 0x9dc
9247 06:53:56.080967 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9248 06:53:56.087486 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9249 06:53:56.093941 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9250 06:53:56.097458 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9251 06:53:56.103828 configure_display: Starting display init
9252 06:53:56.137601 anx7625_power_on_init: Init interface.
9253 06:53:56.141182 anx7625_disable_pd_protocol: Disabled PD feature.
9254 06:53:56.144639 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9255 06:53:56.172220 anx7625_start_dp_work: Secure OCM version=00
9256 06:53:56.174961 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9257 06:53:56.190136 sp_tx_get_edid_block: EDID Block = 1
9258 06:53:56.292713 Extracted contents:
9259 06:53:56.296236 header: 00 ff ff ff ff ff ff 00
9260 06:53:56.299038 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9261 06:53:56.302531 version: 01 04
9262 06:53:56.306026 basic params: 95 1f 11 78 0a
9263 06:53:56.309211 chroma info: 76 90 94 55 54 90 27 21 50 54
9264 06:53:56.312490 established: 00 00 00
9265 06:53:56.318850 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9266 06:53:56.322404 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9267 06:53:56.329292 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9268 06:53:56.335466 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9269 06:53:56.342781 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9270 06:53:56.345552 extensions: 00
9271 06:53:56.345992 checksum: fb
9272 06:53:56.346325
9273 06:53:56.349397 Manufacturer: IVO Model 57d Serial Number 0
9274 06:53:56.352682 Made week 0 of 2020
9275 06:53:56.353132 EDID version: 1.4
9276 06:53:56.355753 Digital display
9277 06:53:56.359003 6 bits per primary color channel
9278 06:53:56.359454 DisplayPort interface
9279 06:53:56.362875 Maximum image size: 31 cm x 17 cm
9280 06:53:56.366014 Gamma: 220%
9281 06:53:56.366430 Check DPMS levels
9282 06:53:56.369087 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9283 06:53:56.372646 First detailed timing is preferred timing
9284 06:53:56.376260 Established timings supported:
9285 06:53:56.378862 Standard timings supported:
9286 06:53:56.382591 Detailed timings
9287 06:53:56.385383 Hex of detail: 383680a07038204018303c0035ae10000019
9288 06:53:56.389089 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9289 06:53:56.395816 0780 0798 07c8 0820 hborder 0
9290 06:53:56.399151 0438 043b 0447 0458 vborder 0
9291 06:53:56.402068 -hsync -vsync
9292 06:53:56.402580 Did detailed timing
9293 06:53:56.408868 Hex of detail: 000000000000000000000000000000000000
9294 06:53:56.409315 Manufacturer-specified data, tag 0
9295 06:53:56.415781 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9296 06:53:56.416231 ASCII string: InfoVision
9297 06:53:56.422070 Hex of detail: 000000fe00523134304e574635205248200a
9298 06:53:56.425525 ASCII string: R140NWF5 RH
9299 06:53:56.426061 Checksum
9300 06:53:56.426513 Checksum: 0xfb (valid)
9301 06:53:56.432315 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9302 06:53:56.435243 DSI data_rate: 832800000 bps
9303 06:53:56.442116 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9304 06:53:56.445454 anx7625_parse_edid: pixelclock(138800).
9305 06:53:56.448755 hactive(1920), hsync(48), hfp(24), hbp(88)
9306 06:53:56.452378 vactive(1080), vsync(12), vfp(3), vbp(17)
9307 06:53:56.455389 anx7625_dsi_config: config dsi.
9308 06:53:56.461974 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9309 06:53:56.474949 anx7625_dsi_config: success to config DSI
9310 06:53:56.478155 anx7625_dp_start: MIPI phy setup OK.
9311 06:53:56.481636 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9312 06:53:56.484946 mtk_ddp_mode_set invalid vrefresh 60
9313 06:53:56.488191 main_disp_path_setup
9314 06:53:56.488808 ovl_layer_smi_id_en
9315 06:53:56.491507 ovl_layer_smi_id_en
9316 06:53:56.491994 ccorr_config
9317 06:53:56.492501 aal_config
9318 06:53:56.494410 gamma_config
9319 06:53:56.494958 postmask_config
9320 06:53:56.497548 dither_config
9321 06:53:56.501047 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9322 06:53:56.507609 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9323 06:53:56.510766 Root Device init finished in 553 msecs
9324 06:53:56.514730 CPU_CLUSTER: 0 init
9325 06:53:56.521394 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9326 06:53:56.527526 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9327 06:53:56.528095 APU_MBOX 0x190000b0 = 0x10001
9328 06:53:56.530942 APU_MBOX 0x190001b0 = 0x10001
9329 06:53:56.534143 APU_MBOX 0x190005b0 = 0x10001
9330 06:53:56.537610 APU_MBOX 0x190006b0 = 0x10001
9331 06:53:56.543992 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9332 06:53:56.553638 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9333 06:53:56.566481 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9334 06:53:56.572705 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9335 06:53:56.584369 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9336 06:53:56.593635 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9337 06:53:56.597084 CPU_CLUSTER: 0 init finished in 81 msecs
9338 06:53:56.600390 Devices initialized
9339 06:53:56.603297 Show all devs... After init.
9340 06:53:56.603706 Root Device: enabled 1
9341 06:53:56.606870 CPU_CLUSTER: 0: enabled 1
9342 06:53:56.610146 CPU: 00: enabled 1
9343 06:53:56.613257 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9344 06:53:56.616758 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9345 06:53:56.620253 ELOG: NV offset 0x57f000 size 0x1000
9346 06:53:56.627093 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9347 06:53:56.633148 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9348 06:53:56.636185 ELOG: Event(17) added with size 13 at 2024-02-03 06:51:13 UTC
9349 06:53:56.642741 out: cmd=0x121: 03 db 21 01 00 00 00 00
9350 06:53:56.646441 in-header: 03 e1 00 00 2c 00 00 00
9351 06:53:56.656043 in-data: 7e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9352 06:53:56.662668 ELOG: Event(A1) added with size 10 at 2024-02-03 06:51:13 UTC
9353 06:53:56.668976 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9354 06:53:56.676017 ELOG: Event(A0) added with size 9 at 2024-02-03 06:51:13 UTC
9355 06:53:56.679550 elog_add_boot_reason: Logged dev mode boot
9356 06:53:56.685651 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9357 06:53:56.685732 Finalize devices...
9358 06:53:56.689031 Devices finalized
9359 06:53:56.692403 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9360 06:53:56.695880 Writing coreboot table at 0xffe64000
9361 06:53:56.699322 0. 000000000010a000-0000000000113fff: RAMSTAGE
9362 06:53:56.702668 1. 0000000040000000-00000000400fffff: RAM
9363 06:53:56.708886 2. 0000000040100000-000000004032afff: RAMSTAGE
9364 06:53:56.712446 3. 000000004032b000-00000000545fffff: RAM
9365 06:53:56.715795 4. 0000000054600000-000000005465ffff: BL31
9366 06:53:56.719062 5. 0000000054660000-00000000ffe63fff: RAM
9367 06:53:56.725609 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9368 06:53:56.729044 7. 0000000100000000-000000023fffffff: RAM
9369 06:53:56.732528 Passing 5 GPIOs to payload:
9370 06:53:56.735283 NAME | PORT | POLARITY | VALUE
9371 06:53:56.738834 EC in RW | 0x000000aa | low | undefined
9372 06:53:56.745436 EC interrupt | 0x00000005 | low | undefined
9373 06:53:56.748631 TPM interrupt | 0x000000ab | high | undefined
9374 06:53:56.755216 SD card detect | 0x00000011 | high | undefined
9375 06:53:56.758704 speaker enable | 0x00000093 | high | undefined
9376 06:53:56.762013 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9377 06:53:56.765425 in-header: 03 f9 00 00 02 00 00 00
9378 06:53:56.768582 in-data: 02 00
9379 06:53:56.771997 ADC[4]: Raw value=904357 ID=7
9380 06:53:56.772077 ADC[3]: Raw value=213441 ID=1
9381 06:53:56.775187 RAM Code: 0x71
9382 06:53:56.778462 ADC[6]: Raw value=75332 ID=0
9383 06:53:56.778543 ADC[5]: Raw value=212703 ID=1
9384 06:53:56.782109 SKU Code: 0x1
9385 06:53:56.785000 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3253
9386 06:53:56.788256 coreboot table: 964 bytes.
9387 06:53:56.791688 IMD ROOT 0. 0xfffff000 0x00001000
9388 06:53:56.795059 IMD SMALL 1. 0xffffe000 0x00001000
9389 06:53:56.798550 RO MCACHE 2. 0xffffc000 0x00001104
9390 06:53:56.802103 CONSOLE 3. 0xfff7c000 0x00080000
9391 06:53:56.805430 FMAP 4. 0xfff7b000 0x00000452
9392 06:53:56.808824 TIME STAMP 5. 0xfff7a000 0x00000910
9393 06:53:56.811688 VBOOT WORK 6. 0xfff66000 0x00014000
9394 06:53:56.815120 RAMOOPS 7. 0xffe66000 0x00100000
9395 06:53:56.818687 COREBOOT 8. 0xffe64000 0x00002000
9396 06:53:56.821443 IMD small region:
9397 06:53:56.824831 IMD ROOT 0. 0xffffec00 0x00000400
9398 06:53:56.828109 VPD 1. 0xffffeb80 0x0000006c
9399 06:53:56.831633 MMC STATUS 2. 0xffffeb60 0x00000004
9400 06:53:56.835201 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9401 06:53:56.838654 Probing TPM: done!
9402 06:53:56.842086 Connected to device vid:did:rid of 1ae0:0028:00
9403 06:53:56.852480 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9404 06:53:56.855968 Initialized TPM device CR50 revision 0
9405 06:53:56.860235 Checking cr50 for pending updates
9406 06:53:56.863480 Reading cr50 TPM mode
9407 06:53:56.871816 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9408 06:53:56.878159 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9409 06:53:56.918351 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9410 06:53:56.921707 Checking segment from ROM address 0x40100000
9411 06:53:56.925235 Checking segment from ROM address 0x4010001c
9412 06:53:56.931847 Loading segment from ROM address 0x40100000
9413 06:53:56.931929 code (compression=0)
9414 06:53:56.938591 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9415 06:53:56.948262 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9416 06:53:56.948364 it's not compressed!
9417 06:53:56.955159 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9418 06:53:56.958585 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9419 06:53:56.978592 Loading segment from ROM address 0x4010001c
9420 06:53:56.978673 Entry Point 0x80000000
9421 06:53:56.982098 Loaded segments
9422 06:53:56.985515 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9423 06:53:56.992091 Jumping to boot code at 0x80000000(0xffe64000)
9424 06:53:56.999180 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9425 06:53:57.005610 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9426 06:53:57.013190 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9427 06:53:57.016744 Checking segment from ROM address 0x40100000
9428 06:53:57.020172 Checking segment from ROM address 0x4010001c
9429 06:53:57.026426 Loading segment from ROM address 0x40100000
9430 06:53:57.026515 code (compression=1)
9431 06:53:57.033352 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9432 06:53:57.043072 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9433 06:53:57.043155 using LZMA
9434 06:53:57.051537 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9435 06:53:57.058589 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9436 06:53:57.062049 Loading segment from ROM address 0x4010001c
9437 06:53:57.062159 Entry Point 0x54601000
9438 06:53:57.064801 Loaded segments
9439 06:53:57.068169 NOTICE: MT8192 bl31_setup
9440 06:53:57.075166 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9441 06:53:57.078570 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9442 06:53:57.082048 WARNING: region 0:
9443 06:53:57.085603 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 06:53:57.085846 WARNING: region 1:
9445 06:53:57.091841 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9446 06:53:57.095277 WARNING: region 2:
9447 06:53:57.098514 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9448 06:53:57.102123 WARNING: region 3:
9449 06:53:57.105556 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9450 06:53:57.108943 WARNING: region 4:
9451 06:53:57.115493 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9452 06:53:57.115912 WARNING: region 5:
9453 06:53:57.119347 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 06:53:57.122477 WARNING: region 6:
9455 06:53:57.125864 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 06:53:57.126283 WARNING: region 7:
9457 06:53:57.132088 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 06:53:57.138879 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9459 06:53:57.142587 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9460 06:53:57.145570 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9461 06:53:57.152148 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9462 06:53:57.155966 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9463 06:53:57.159183 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9464 06:53:57.165610 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9465 06:53:57.169100 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9466 06:53:57.175555 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9467 06:53:57.178972 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9468 06:53:57.182340 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9469 06:53:57.188710 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9470 06:53:57.192160 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9471 06:53:57.195758 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9472 06:53:57.202571 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9473 06:53:57.205892 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9474 06:53:57.209296 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9475 06:53:57.215606 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9476 06:53:57.219082 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9477 06:53:57.222294 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9478 06:53:57.229332 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9479 06:53:57.232821 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9480 06:53:57.239375 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9481 06:53:57.242560 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9482 06:53:57.246088 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9483 06:53:57.252357 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9484 06:53:57.256158 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9485 06:53:57.262435 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9486 06:53:57.265903 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9487 06:53:57.268916 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9488 06:53:57.275929 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9489 06:53:57.279025 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9490 06:53:57.282248 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9491 06:53:57.289176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9492 06:53:57.291955 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9493 06:53:57.295488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9494 06:53:57.298913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9495 06:53:57.306151 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9496 06:53:57.308824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9497 06:53:57.312074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9498 06:53:57.315673 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9499 06:53:57.322768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9500 06:53:57.326274 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9501 06:53:57.329013 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9502 06:53:57.332620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9503 06:53:57.339178 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9504 06:53:57.342544 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9505 06:53:57.346102 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9506 06:53:57.353079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9507 06:53:57.356708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9508 06:53:57.359922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9509 06:53:57.366502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9510 06:53:57.369509 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9511 06:53:57.376510 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9512 06:53:57.379222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9513 06:53:57.386194 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9514 06:53:57.389830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9515 06:53:57.392451 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9516 06:53:57.399690 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9517 06:53:57.403105 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9518 06:53:57.409865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9519 06:53:57.412795 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9520 06:53:57.419171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9521 06:53:57.422644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9522 06:53:57.429028 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9523 06:53:57.432573 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9524 06:53:57.436169 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9525 06:53:57.442406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9526 06:53:57.446288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9527 06:53:57.452010 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9528 06:53:57.455303 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9529 06:53:57.458717 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9530 06:53:57.465980 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9531 06:53:57.469501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9532 06:53:57.476094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9533 06:53:57.479261 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9534 06:53:57.485760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9535 06:53:57.489213 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9536 06:53:57.496071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9537 06:53:57.499573 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9538 06:53:57.502985 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9539 06:53:57.509362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9540 06:53:57.512821 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9541 06:53:57.519659 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9542 06:53:57.523012 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9543 06:53:57.529568 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9544 06:53:57.532837 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9545 06:53:57.535802 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9546 06:53:57.542565 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9547 06:53:57.545691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9548 06:53:57.552316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9549 06:53:57.555712 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9550 06:53:57.562758 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9551 06:53:57.566029 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9552 06:53:57.569155 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9553 06:53:57.575770 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9554 06:53:57.579182 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9555 06:53:57.582527 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9556 06:53:57.589753 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9557 06:53:57.592695 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9558 06:53:57.595855 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9559 06:53:57.599356 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9560 06:53:57.606298 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9561 06:53:57.609749 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9562 06:53:57.616607 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9563 06:53:57.619383 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9564 06:53:57.622814 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9565 06:53:57.629627 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9566 06:53:57.633193 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9567 06:53:57.639444 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9568 06:53:57.642963 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9569 06:53:57.646362 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9570 06:53:57.652444 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9571 06:53:57.655624 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9572 06:53:57.662238 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9573 06:53:57.665723 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9574 06:53:57.668949 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9575 06:53:57.676168 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9576 06:53:57.679203 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9577 06:53:57.682556 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9578 06:53:57.686273 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9579 06:53:57.689429 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9580 06:53:57.696250 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9581 06:53:57.699540 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9582 06:53:57.702669 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9583 06:53:57.709090 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9584 06:53:57.712468 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9585 06:53:57.719412 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9586 06:53:57.722848 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9587 06:53:57.726335 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9588 06:53:57.732589 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9589 06:53:57.736081 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9590 06:53:57.742893 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9591 06:53:57.746257 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9592 06:53:57.749210 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9593 06:53:57.756164 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9594 06:53:57.759471 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9595 06:53:57.762984 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9596 06:53:57.769176 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9597 06:53:57.772641 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9598 06:53:57.779043 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9599 06:53:57.782888 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9600 06:53:57.786019 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9601 06:53:57.792514 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9602 06:53:57.796118 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9603 06:53:57.799162 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9604 06:53:57.806053 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9605 06:53:57.809292 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9606 06:53:57.816193 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9607 06:53:57.819364 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9608 06:53:57.822795 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9609 06:53:57.829146 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9610 06:53:57.832862 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9611 06:53:57.839318 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9612 06:53:57.843118 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9613 06:53:57.846303 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9614 06:53:57.852638 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9615 06:53:57.856127 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9616 06:53:57.859735 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9617 06:53:57.865788 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9618 06:53:57.869302 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9619 06:53:57.876194 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9620 06:53:57.879495 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9621 06:53:57.882976 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9622 06:53:57.889167 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9623 06:53:57.892966 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9624 06:53:57.899717 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9625 06:53:57.902362 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9626 06:53:57.905840 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9627 06:53:57.912384 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9628 06:53:57.916034 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9629 06:53:57.922573 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9630 06:53:57.925966 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9631 06:53:57.929378 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9632 06:53:57.935589 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9633 06:53:57.938999 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9634 06:53:57.946127 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9635 06:53:57.949192 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9636 06:53:57.952202 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9637 06:53:57.959696 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9638 06:53:57.963005 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9639 06:53:57.966307 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9640 06:53:57.972744 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9641 06:53:57.976192 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9642 06:53:57.983023 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9643 06:53:57.986435 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9644 06:53:57.989227 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9645 06:53:57.996074 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9646 06:53:57.999662 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9647 06:53:58.005942 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9648 06:53:58.009225 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9649 06:53:58.015697 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9650 06:53:58.019171 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9651 06:53:58.022400 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9652 06:53:58.029022 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9653 06:53:58.032505 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9654 06:53:58.039116 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9655 06:53:58.042338 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9656 06:53:58.045779 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9657 06:53:58.052800 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9658 06:53:58.055554 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9659 06:53:58.062861 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9660 06:53:58.066352 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9661 06:53:58.069827 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9662 06:53:58.075898 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9663 06:53:58.078960 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9664 06:53:58.085917 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9665 06:53:58.089116 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9666 06:53:58.095462 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9667 06:53:58.099207 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9668 06:53:58.102947 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9669 06:53:58.108967 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9670 06:53:58.112222 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9671 06:53:58.119346 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9672 06:53:58.122303 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9673 06:53:58.125850 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9674 06:53:58.132769 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9675 06:53:58.135962 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9676 06:53:58.142475 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9677 06:53:58.145624 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9678 06:53:58.152247 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9679 06:53:58.155758 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9680 06:53:58.159031 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9681 06:53:58.165337 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9682 06:53:58.168701 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9683 06:53:58.175619 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9684 06:53:58.179145 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9685 06:53:58.181907 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9686 06:53:58.188690 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9687 06:53:58.192171 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9688 06:53:58.195308 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9689 06:53:58.198995 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9690 06:53:58.205425 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9691 06:53:58.208917 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9692 06:53:58.212107 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9693 06:53:58.218777 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9694 06:53:58.222022 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9695 06:53:58.225394 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9696 06:53:58.231775 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9697 06:53:58.234974 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9698 06:53:58.241789 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9699 06:53:58.244970 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9700 06:53:58.248396 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9701 06:53:58.255331 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9702 06:53:58.258773 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9703 06:53:58.264003 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9704 06:53:58.268584 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9705 06:53:58.271954 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9706 06:53:58.275388 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9707 06:53:58.281630 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9708 06:53:58.284958 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9709 06:53:58.291906 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9710 06:53:58.294728 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9711 06:53:58.298176 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9712 06:53:58.304930 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9713 06:53:58.308131 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9714 06:53:58.311642 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9715 06:53:58.317962 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9716 06:53:58.321528 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9717 06:53:58.324785 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9718 06:53:58.331199 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9719 06:53:58.334906 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9720 06:53:58.341167 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9721 06:53:58.344910 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9722 06:53:58.347934 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9723 06:53:58.354759 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9724 06:53:58.358137 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9725 06:53:58.361763 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9726 06:53:58.368497 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9727 06:53:58.371563 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9728 06:53:58.374768 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9729 06:53:58.377969 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9730 06:53:58.384745 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9731 06:53:58.388220 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9732 06:53:58.391729 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9733 06:53:58.394463 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9734 06:53:58.397889 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9735 06:53:58.404939 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9736 06:53:58.408342 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9737 06:53:58.411891 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9738 06:53:58.418393 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9739 06:53:58.421677 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9740 06:53:58.425047 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9741 06:53:58.431269 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9742 06:53:58.434721 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9743 06:53:58.441570 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9744 06:53:58.444785 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9745 06:53:58.447803 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9746 06:53:58.454839 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9747 06:53:58.458030 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9748 06:53:58.461212 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9749 06:53:58.467808 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9750 06:53:58.471226 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9751 06:53:58.477544 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9752 06:53:58.480980 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9753 06:53:58.487801 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9754 06:53:58.491559 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9755 06:53:58.494769 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9756 06:53:58.501059 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9757 06:53:58.504732 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9758 06:53:58.511881 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9759 06:53:58.515008 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9760 06:53:58.518168 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9761 06:53:58.524465 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9762 06:53:58.527837 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9763 06:53:58.534328 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9764 06:53:58.537433 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9765 06:53:58.541275 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9766 06:53:58.548041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9767 06:53:58.550842 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9768 06:53:58.557512 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9769 06:53:58.560868 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9770 06:53:58.567546 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9771 06:53:58.571034 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9772 06:53:58.574296 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9773 06:53:58.580540 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9774 06:53:58.583793 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9775 06:53:58.590717 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9776 06:53:58.594016 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9777 06:53:58.597109 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9778 06:53:58.603972 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9779 06:53:58.607434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9780 06:53:58.614286 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9781 06:53:58.616940 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9782 06:53:58.620350 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9783 06:53:58.627237 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9784 06:53:58.630501 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9785 06:53:58.637257 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9786 06:53:58.640505 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9787 06:53:58.643771 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9788 06:53:58.650594 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9789 06:53:58.654168 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9790 06:53:58.660365 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9791 06:53:58.663861 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9792 06:53:58.667304 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9793 06:53:58.673844 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9794 06:53:58.676766 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9795 06:53:58.683211 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9796 06:53:58.686572 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9797 06:53:58.690474 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9798 06:53:58.696627 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9799 06:53:58.700163 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9800 06:53:58.706373 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9801 06:53:58.710160 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9802 06:53:58.716219 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9803 06:53:58.719874 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9804 06:53:58.723496 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9805 06:53:58.730681 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9806 06:53:58.733254 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9807 06:53:58.739840 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9808 06:53:58.743387 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9809 06:53:58.746974 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9810 06:53:58.753377 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9811 06:53:58.756886 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9812 06:53:58.763731 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9813 06:53:58.766468 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9814 06:53:58.773243 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9815 06:53:58.776640 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9816 06:53:58.780051 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9817 06:53:58.787221 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9818 06:53:58.790128 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9819 06:53:58.796775 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9820 06:53:58.800099 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9821 06:53:58.803700 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9822 06:53:58.810583 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9823 06:53:58.813616 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9824 06:53:58.820305 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9825 06:53:58.823742 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9826 06:53:58.829949 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9827 06:53:58.833220 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9828 06:53:58.836413 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9829 06:53:58.843463 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9830 06:53:58.846374 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9831 06:53:58.853104 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9832 06:53:58.856368 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9833 06:53:58.863312 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9834 06:53:58.866687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9835 06:53:58.870126 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9836 06:53:58.876372 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9837 06:53:58.879823 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9838 06:53:58.886821 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9839 06:53:58.890231 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9840 06:53:58.896472 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9841 06:53:58.899935 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9842 06:53:58.906150 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9843 06:53:58.909745 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9844 06:53:58.912798 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9845 06:53:58.919409 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9846 06:53:58.922882 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9847 06:53:58.929602 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9848 06:53:58.933296 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9849 06:53:58.940007 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9850 06:53:58.943603 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9851 06:53:58.946892 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9852 06:53:58.953151 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9853 06:53:58.956649 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9854 06:53:58.963248 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9855 06:53:58.966226 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9856 06:53:58.973003 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9857 06:53:58.976374 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9858 06:53:58.983023 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9859 06:53:58.986487 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9860 06:53:58.989954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9861 06:53:58.996345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9862 06:53:58.999745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9863 06:53:59.005921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9864 06:53:59.009564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9865 06:53:59.016394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9866 06:53:59.019530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9867 06:53:59.026349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9868 06:53:59.028933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9869 06:53:59.032606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9870 06:53:59.038920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9871 06:53:59.042299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9872 06:53:59.049718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9873 06:53:59.052447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9874 06:53:59.059229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9875 06:53:59.062939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9876 06:53:59.069713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9877 06:53:59.072724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9878 06:53:59.079212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9879 06:53:59.082610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9880 06:53:59.088894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9881 06:53:59.092615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9882 06:53:59.099262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9883 06:53:59.102262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9884 06:53:59.108842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9885 06:53:59.112539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9886 06:53:59.118719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9887 06:53:59.122443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9888 06:53:59.129142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9889 06:53:59.132216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9890 06:53:59.138862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9891 06:53:59.142009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9892 06:53:59.148884 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9893 06:53:59.149467 INFO: [APUAPC] vio 0
9894 06:53:59.155266 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9895 06:53:59.158794 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9896 06:53:59.162191 INFO: [APUAPC] D0_APC_0: 0x400510
9897 06:53:59.165702 INFO: [APUAPC] D0_APC_1: 0x0
9898 06:53:59.169207 INFO: [APUAPC] D0_APC_2: 0x1540
9899 06:53:59.171927 INFO: [APUAPC] D0_APC_3: 0x0
9900 06:53:59.175440 INFO: [APUAPC] D1_APC_0: 0xffffffff
9901 06:53:59.178736 INFO: [APUAPC] D1_APC_1: 0xffffffff
9902 06:53:59.182415 INFO: [APUAPC] D1_APC_2: 0x3fffff
9903 06:53:59.185090 INFO: [APUAPC] D1_APC_3: 0x0
9904 06:53:59.188673 INFO: [APUAPC] D2_APC_0: 0xffffffff
9905 06:53:59.192018 INFO: [APUAPC] D2_APC_1: 0xffffffff
9906 06:53:59.195336 INFO: [APUAPC] D2_APC_2: 0x3fffff
9907 06:53:59.199089 INFO: [APUAPC] D2_APC_3: 0x0
9908 06:53:59.202445 INFO: [APUAPC] D3_APC_0: 0xffffffff
9909 06:53:59.205617 INFO: [APUAPC] D3_APC_1: 0xffffffff
9910 06:53:59.209066 INFO: [APUAPC] D3_APC_2: 0x3fffff
9911 06:53:59.209482 INFO: [APUAPC] D3_APC_3: 0x0
9912 06:53:59.211775 INFO: [APUAPC] D4_APC_0: 0xffffffff
9913 06:53:59.218556 INFO: [APUAPC] D4_APC_1: 0xffffffff
9914 06:53:59.221934 INFO: [APUAPC] D4_APC_2: 0x3fffff
9915 06:53:59.222345 INFO: [APUAPC] D4_APC_3: 0x0
9916 06:53:59.225596 INFO: [APUAPC] D5_APC_0: 0xffffffff
9917 06:53:59.228922 INFO: [APUAPC] D5_APC_1: 0xffffffff
9918 06:53:59.231974 INFO: [APUAPC] D5_APC_2: 0x3fffff
9919 06:53:59.235343 INFO: [APUAPC] D5_APC_3: 0x0
9920 06:53:59.238832 INFO: [APUAPC] D6_APC_0: 0xffffffff
9921 06:53:59.242014 INFO: [APUAPC] D6_APC_1: 0xffffffff
9922 06:53:59.245580 INFO: [APUAPC] D6_APC_2: 0x3fffff
9923 06:53:59.248486 INFO: [APUAPC] D6_APC_3: 0x0
9924 06:53:59.251899 INFO: [APUAPC] D7_APC_0: 0xffffffff
9925 06:53:59.255065 INFO: [APUAPC] D7_APC_1: 0xffffffff
9926 06:53:59.258667 INFO: [APUAPC] D7_APC_2: 0x3fffff
9927 06:53:59.261814 INFO: [APUAPC] D7_APC_3: 0x0
9928 06:53:59.265483 INFO: [APUAPC] D8_APC_0: 0xffffffff
9929 06:53:59.268759 INFO: [APUAPC] D8_APC_1: 0xffffffff
9930 06:53:59.272118 INFO: [APUAPC] D8_APC_2: 0x3fffff
9931 06:53:59.275675 INFO: [APUAPC] D8_APC_3: 0x0
9932 06:53:59.278637 INFO: [APUAPC] D9_APC_0: 0xffffffff
9933 06:53:59.282531 INFO: [APUAPC] D9_APC_1: 0xffffffff
9934 06:53:59.285180 INFO: [APUAPC] D9_APC_2: 0x3fffff
9935 06:53:59.288448 INFO: [APUAPC] D9_APC_3: 0x0
9936 06:53:59.291608 INFO: [APUAPC] D10_APC_0: 0xffffffff
9937 06:53:59.294764 INFO: [APUAPC] D10_APC_1: 0xffffffff
9938 06:53:59.298063 INFO: [APUAPC] D10_APC_2: 0x3fffff
9939 06:53:59.301377 INFO: [APUAPC] D10_APC_3: 0x0
9940 06:53:59.304899 INFO: [APUAPC] D11_APC_0: 0xffffffff
9941 06:53:59.308331 INFO: [APUAPC] D11_APC_1: 0xffffffff
9942 06:53:59.311804 INFO: [APUAPC] D11_APC_2: 0x3fffff
9943 06:53:59.315264 INFO: [APUAPC] D11_APC_3: 0x0
9944 06:53:59.318547 INFO: [APUAPC] D12_APC_0: 0xffffffff
9945 06:53:59.321489 INFO: [APUAPC] D12_APC_1: 0xffffffff
9946 06:53:59.324874 INFO: [APUAPC] D12_APC_2: 0x3fffff
9947 06:53:59.328564 INFO: [APUAPC] D12_APC_3: 0x0
9948 06:53:59.332109 INFO: [APUAPC] D13_APC_0: 0xffffffff
9949 06:53:59.335677 INFO: [APUAPC] D13_APC_1: 0xffffffff
9950 06:53:59.339079 INFO: [APUAPC] D13_APC_2: 0x3fffff
9951 06:53:59.341289 INFO: [APUAPC] D13_APC_3: 0x0
9952 06:53:59.344775 INFO: [APUAPC] D14_APC_0: 0xffffffff
9953 06:53:59.348239 INFO: [APUAPC] D14_APC_1: 0xffffffff
9954 06:53:59.351554 INFO: [APUAPC] D14_APC_2: 0x3fffff
9955 06:53:59.355136 INFO: [APUAPC] D14_APC_3: 0x0
9956 06:53:59.358446 INFO: [APUAPC] D15_APC_0: 0xffffffff
9957 06:53:59.362236 INFO: [APUAPC] D15_APC_1: 0xffffffff
9958 06:53:59.364820 INFO: [APUAPC] D15_APC_2: 0x3fffff
9959 06:53:59.368314 INFO: [APUAPC] D15_APC_3: 0x0
9960 06:53:59.371216 INFO: [APUAPC] APC_CON: 0x4
9961 06:53:59.375196 INFO: [NOCDAPC] D0_APC_0: 0x0
9962 06:53:59.377975 INFO: [NOCDAPC] D0_APC_1: 0x0
9963 06:53:59.381443 INFO: [NOCDAPC] D1_APC_0: 0x0
9964 06:53:59.384723 INFO: [NOCDAPC] D1_APC_1: 0xfff
9965 06:53:59.385238 INFO: [NOCDAPC] D2_APC_0: 0x0
9966 06:53:59.388049 INFO: [NOCDAPC] D2_APC_1: 0xfff
9967 06:53:59.391200 INFO: [NOCDAPC] D3_APC_0: 0x0
9968 06:53:59.394874 INFO: [NOCDAPC] D3_APC_1: 0xfff
9969 06:53:59.398019 INFO: [NOCDAPC] D4_APC_0: 0x0
9970 06:53:59.400956 INFO: [NOCDAPC] D4_APC_1: 0xfff
9971 06:53:59.404614 INFO: [NOCDAPC] D5_APC_0: 0x0
9972 06:53:59.407921 INFO: [NOCDAPC] D5_APC_1: 0xfff
9973 06:53:59.410902 INFO: [NOCDAPC] D6_APC_0: 0x0
9974 06:53:59.414446 INFO: [NOCDAPC] D6_APC_1: 0xfff
9975 06:53:59.417574 INFO: [NOCDAPC] D7_APC_0: 0x0
9976 06:53:59.418009 INFO: [NOCDAPC] D7_APC_1: 0xfff
9977 06:53:59.421310 INFO: [NOCDAPC] D8_APC_0: 0x0
9978 06:53:59.424394 INFO: [NOCDAPC] D8_APC_1: 0xfff
9979 06:53:59.427510 INFO: [NOCDAPC] D9_APC_0: 0x0
9980 06:53:59.431125 INFO: [NOCDAPC] D9_APC_1: 0xfff
9981 06:53:59.434806 INFO: [NOCDAPC] D10_APC_0: 0x0
9982 06:53:59.437668 INFO: [NOCDAPC] D10_APC_1: 0xfff
9983 06:53:59.440999 INFO: [NOCDAPC] D11_APC_0: 0x0
9984 06:53:59.444470 INFO: [NOCDAPC] D11_APC_1: 0xfff
9985 06:53:59.447676 INFO: [NOCDAPC] D12_APC_0: 0x0
9986 06:53:59.451231 INFO: [NOCDAPC] D12_APC_1: 0xfff
9987 06:53:59.454769 INFO: [NOCDAPC] D13_APC_0: 0x0
9988 06:53:59.457368 INFO: [NOCDAPC] D13_APC_1: 0xfff
9989 06:53:59.460983 INFO: [NOCDAPC] D14_APC_0: 0x0
9990 06:53:59.461532 INFO: [NOCDAPC] D14_APC_1: 0xfff
9991 06:53:59.464376 INFO: [NOCDAPC] D15_APC_0: 0x0
9992 06:53:59.467994 INFO: [NOCDAPC] D15_APC_1: 0xfff
9993 06:53:59.470623 INFO: [NOCDAPC] APC_CON: 0x4
9994 06:53:59.474049 INFO: [APUAPC] set_apusys_apc done
9995 06:53:59.477506 INFO: [DEVAPC] devapc_init done
9996 06:53:59.480713 INFO: GICv3 without legacy support detected.
9997 06:53:59.487517 INFO: ARM GICv3 driver initialized in EL3
9998 06:53:59.490845 INFO: Maximum SPI INTID supported: 639
9999 06:53:59.494083 INFO: BL31: Initializing runtime services
10000 06:53:59.501020 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10001 06:53:59.504062 INFO: SPM: enable CPC mode
10002 06:53:59.507536 INFO: mcdi ready for mcusys-off-idle and system suspend
10003 06:53:59.511128 INFO: BL31: Preparing for EL3 exit to normal world
10004 06:53:59.517330 INFO: Entry point address = 0x80000000
10005 06:53:59.517790 INFO: SPSR = 0x8
10006 06:53:59.523343
10007 06:53:59.523798
10008 06:53:59.524154
10009 06:53:59.526949 Starting depthcharge on Spherion...
10010 06:53:59.527365
10011 06:53:59.527730 Wipe memory regions:
10012 06:53:59.528076
10013 06:53:59.530526 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10014 06:53:59.531024 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10015 06:53:59.531421 Setting prompt string to ['asurada:']
10016 06:53:59.531786 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10017 06:53:59.532475 [0x00000040000000, 0x00000054600000)
10018 06:53:59.652217
10019 06:53:59.652407 [0x00000054660000, 0x00000080000000)
10020 06:53:59.912356
10021 06:53:59.912877 [0x000000821a7280, 0x000000ffe64000)
10022 06:54:00.656751
10023 06:54:00.657265 [0x00000100000000, 0x00000240000000)
10024 06:54:02.542736
10025 06:54:02.545821 Initializing XHCI USB controller at 0x11200000.
10026 06:54:03.584181
10027 06:54:03.587175 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10028 06:54:03.587289
10029 06:54:03.587371
10030 06:54:03.587433
10031 06:54:03.587710 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10033 06:54:03.688062 asurada: tftpboot 192.168.201.1 12694812/tftp-deploy-j7wt1w4y/kernel/image.itb 12694812/tftp-deploy-j7wt1w4y/kernel/cmdline
10034 06:54:03.688219 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10035 06:54:03.688363 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10036 06:54:03.692612 tftpboot 192.168.201.1 12694812/tftp-deploy-j7wt1w4y/kernel/image.ittp-deploy-j7wt1w4y/kernel/cmdline
10037 06:54:03.692696
10038 06:54:03.692759 Waiting for link
10039 06:54:03.852800
10040 06:54:03.852934 R8152: Initializing
10041 06:54:03.853004
10042 06:54:03.856084 Version 9 (ocp_data = 6010)
10043 06:54:03.856166
10044 06:54:03.859496 R8152: Done initializing
10045 06:54:03.859577
10046 06:54:03.859641 Adding net device
10047 06:54:05.806380
10048 06:54:05.806890 done.
10049 06:54:05.807230
10050 06:54:05.807544 MAC: 00:e0:4c:78:7a:aa
10051 06:54:05.807847
10052 06:54:05.809562 Sending DHCP discover... done.
10053 06:54:05.809980
10054 06:54:05.812672 Waiting for reply... done.
10055 06:54:05.813091
10056 06:54:05.815987 Sending DHCP request... done.
10057 06:54:05.816461
10058 06:54:05.819682 Waiting for reply... done.
10059 06:54:05.820096
10060 06:54:05.820548 My ip is 192.168.201.12
10061 06:54:05.820869
10062 06:54:05.823219 The DHCP server ip is 192.168.201.1
10063 06:54:05.823638
10064 06:54:05.829463 TFTP server IP predefined by user: 192.168.201.1
10065 06:54:05.829884
10066 06:54:05.836409 Bootfile predefined by user: 12694812/tftp-deploy-j7wt1w4y/kernel/image.itb
10067 06:54:05.836832
10068 06:54:05.837253 Sending tftp read request... done.
10069 06:54:05.839836
10070 06:54:05.845763 Waiting for the transfer...
10071 06:54:05.846179
10072 06:54:06.165230 00000000 ################################################################
10073 06:54:06.165361
10074 06:54:06.430860 00080000 ################################################################
10075 06:54:06.431020
10076 06:54:06.690531 00100000 ################################################################
10077 06:54:06.690662
10078 06:54:06.938506 00180000 ################################################################
10079 06:54:06.938640
10080 06:54:07.203003 00200000 ################################################################
10081 06:54:07.203165
10082 06:54:07.471070 00280000 ################################################################
10083 06:54:07.471225
10084 06:54:07.728972 00300000 ################################################################
10085 06:54:07.729125
10086 06:54:07.986318 00380000 ################################################################
10087 06:54:07.986450
10088 06:54:08.264958 00400000 ################################################################
10089 06:54:08.265125
10090 06:54:08.544095 00480000 ################################################################
10091 06:54:08.544227
10092 06:54:08.837373 00500000 ################################################################
10093 06:54:08.837515
10094 06:54:09.113021 00580000 ################################################################
10095 06:54:09.113149
10096 06:54:09.383236 00600000 ################################################################
10097 06:54:09.383366
10098 06:54:09.642400 00680000 ################################################################
10099 06:54:09.642531
10100 06:54:09.900447 00700000 ################################################################
10101 06:54:09.900613
10102 06:54:10.173673 00780000 ################################################################
10103 06:54:10.173802
10104 06:54:10.455931 00800000 ################################################################
10105 06:54:10.456056
10106 06:54:10.718094 00880000 ################################################################
10107 06:54:10.718217
10108 06:54:10.995578 00900000 ################################################################
10109 06:54:10.995732
10110 06:54:11.249276 00980000 ################################################################
10111 06:54:11.249404
10112 06:54:11.507931 00a00000 ################################################################
10113 06:54:11.508060
10114 06:54:11.777480 00a80000 ################################################################
10115 06:54:11.777604
10116 06:54:12.033698 00b00000 ################################################################
10117 06:54:12.033838
10118 06:54:12.305154 00b80000 ################################################################
10119 06:54:12.305286
10120 06:54:12.556940 00c00000 ################################################################
10121 06:54:12.557066
10122 06:54:12.814575 00c80000 ################################################################
10123 06:54:12.814695
10124 06:54:13.104104 00d00000 ################################################################
10125 06:54:13.104324
10126 06:54:13.369598 00d80000 ################################################################
10127 06:54:13.369722
10128 06:54:13.644021 00e00000 ################################################################
10129 06:54:13.644175
10130 06:54:13.921097 00e80000 ################################################################
10131 06:54:13.921226
10132 06:54:14.192662 00f00000 ################################################################
10133 06:54:14.192787
10134 06:54:14.486801 00f80000 ################################################################
10135 06:54:14.486929
10136 06:54:14.784409 01000000 ################################################################
10137 06:54:14.784542
10138 06:54:15.083525 01080000 ################################################################
10139 06:54:15.083668
10140 06:54:15.383929 01100000 ################################################################
10141 06:54:15.384061
10142 06:54:15.676515 01180000 ################################################################
10143 06:54:15.676640
10144 06:54:15.961903 01200000 ################################################################
10145 06:54:15.962032
10146 06:54:16.252432 01280000 ################################################################
10147 06:54:16.252570
10148 06:54:16.527271 01300000 ################################################################
10149 06:54:16.527402
10150 06:54:16.807142 01380000 ################################################################
10151 06:54:16.807268
10152 06:54:17.090337 01400000 ################################################################
10153 06:54:17.090467
10154 06:54:17.348441 01480000 ################################################################
10155 06:54:17.348568
10156 06:54:17.631274 01500000 ################################################################
10157 06:54:17.631397
10158 06:54:17.914579 01580000 ################################################################
10159 06:54:17.914713
10160 06:54:18.162997 01600000 ################################################################
10161 06:54:18.163155
10162 06:54:18.442812 01680000 ################################################################
10163 06:54:18.443075
10164 06:54:18.696807 01700000 ################################################################
10165 06:54:18.696938
10166 06:54:18.958685 01780000 ################################################################
10167 06:54:18.958840
10168 06:54:19.239801 01800000 ################################################################
10169 06:54:19.239957
10170 06:54:19.525481 01880000 ################################################################
10171 06:54:19.525636
10172 06:54:19.809264 01900000 ################################################################
10173 06:54:19.809399
10174 06:54:20.078539 01980000 ################################################################
10175 06:54:20.078670
10176 06:54:20.336260 01a00000 ################################################################
10177 06:54:20.336415
10178 06:54:20.596867 01a80000 ################################################################
10179 06:54:20.596999
10180 06:54:20.882428 01b00000 ################################################################
10181 06:54:20.882561
10182 06:54:21.157582 01b80000 ################################################################
10183 06:54:21.157713
10184 06:54:21.416358 01c00000 ################################################################
10185 06:54:21.416486
10186 06:54:21.674640 01c80000 ################################################################
10187 06:54:21.674769
10188 06:54:21.928427 01d00000 ################################################################
10189 06:54:21.928561
10190 06:54:22.198555 01d80000 ################################################################
10191 06:54:22.198721
10192 06:54:22.462971 01e00000 ################################################################
10193 06:54:22.463100
10194 06:54:22.720682 01e80000 ################################################################
10195 06:54:22.720822
10196 06:54:22.982446 01f00000 ################################################################
10197 06:54:22.982578
10198 06:54:23.251940 01f80000 ################################################################
10199 06:54:23.252079
10200 06:54:23.523544 02000000 ################################################################
10201 06:54:23.523671
10202 06:54:23.779819 02080000 ################################################################
10203 06:54:23.779955
10204 06:54:24.061451 02100000 ################################################################
10205 06:54:24.061587
10206 06:54:24.329413 02180000 ################################################################
10207 06:54:24.329570
10208 06:54:24.593148 02200000 ################################################################
10209 06:54:24.593348
10210 06:54:24.863457 02280000 ################################################################
10211 06:54:24.863594
10212 06:54:25.145836 02300000 ################################################################
10213 06:54:25.145993
10214 06:54:25.402003 02380000 ################################################################
10215 06:54:25.402134
10216 06:54:25.660698 02400000 ################################################################
10217 06:54:25.660830
10218 06:54:25.913272 02480000 ################################################################
10219 06:54:25.913432
10220 06:54:26.175311 02500000 ################################################################
10221 06:54:26.175442
10222 06:54:26.437978 02580000 ################################################################
10223 06:54:26.438111
10224 06:54:26.692482 02600000 ################################################################
10225 06:54:26.692613
10226 06:54:26.954086 02680000 ################################################################
10227 06:54:26.954224
10228 06:54:27.213223 02700000 ################################################################
10229 06:54:27.213355
10230 06:54:27.466052 02780000 ################################################################
10231 06:54:27.466185
10232 06:54:27.719959 02800000 ################################################################
10233 06:54:27.720089
10234 06:54:27.981119 02880000 ################################################################
10235 06:54:27.981248
10236 06:54:28.248471 02900000 ################################################################
10237 06:54:28.248596
10238 06:54:28.504514 02980000 ################################################################
10239 06:54:28.504645
10240 06:54:28.771017 02a00000 ################################################################
10241 06:54:28.771151
10242 06:54:29.025786 02a80000 ################################################################
10243 06:54:29.025918
10244 06:54:29.303729 02b00000 ################################################################
10245 06:54:29.303860
10246 06:54:29.555406 02b80000 ################################################################
10247 06:54:29.555536
10248 06:54:29.803032 02c00000 ################################################################
10249 06:54:29.803167
10250 06:54:30.071903 02c80000 ################################################################
10251 06:54:30.072035
10252 06:54:30.329261 02d00000 ################################################################
10253 06:54:30.329393
10254 06:54:30.590150 02d80000 ################################################################
10255 06:54:30.590278
10256 06:54:30.849293 02e00000 ################################################################
10257 06:54:30.849421
10258 06:54:31.128675 02e80000 ################################################################
10259 06:54:31.128805
10260 06:54:31.419195 02f00000 ################################################################
10261 06:54:31.419352
10262 06:54:31.697454 02f80000 ################################################################
10263 06:54:31.697669
10264 06:54:31.980755 03000000 ################################################################
10265 06:54:31.980923
10266 06:54:32.239328 03080000 ################################################################
10267 06:54:32.239459
10268 06:54:32.513345 03100000 ################################################################
10269 06:54:32.513479
10270 06:54:32.787688 03180000 ################################################################
10271 06:54:32.787814
10272 06:54:33.078515 03200000 ################################################################
10273 06:54:33.078644
10274 06:54:33.369083 03280000 ################################################################
10275 06:54:33.369215
10276 06:54:33.656629 03300000 ################################################################
10277 06:54:33.656762
10278 06:54:33.939766 03380000 ################################################################
10279 06:54:33.939897
10280 06:54:34.191818 03400000 ################################################################
10281 06:54:34.191950
10282 06:54:34.469726 03480000 ################################################################
10283 06:54:34.469853
10284 06:54:34.749721 03500000 ################################################################
10285 06:54:34.749855
10286 06:54:35.028988 03580000 ################################################################
10287 06:54:35.029119
10288 06:54:35.319627 03600000 ################################################################
10289 06:54:35.319759
10290 06:54:35.611306 03680000 ################################################################
10291 06:54:35.611434
10292 06:54:35.906947 03700000 ################################################################
10293 06:54:35.907078
10294 06:54:36.192851 03780000 ################################################################
10295 06:54:36.192980
10296 06:54:36.558644 03800000 ################################################################
10297 06:54:36.559175
10298 06:54:36.818705 03880000 ################################################# done.
10299 06:54:36.818836
10300 06:54:36.821955 The bootfile was 59641862 bytes long.
10301 06:54:36.822037
10302 06:54:36.825301 Sending tftp read request... done.
10303 06:54:36.825392
10304 06:54:36.829123 Waiting for the transfer...
10305 06:54:36.829289
10306 06:54:36.832067 00000000 # done.
10307 06:54:36.832162
10308 06:54:36.838825 Command line loaded dynamically from TFTP file: 12694812/tftp-deploy-j7wt1w4y/kernel/cmdline
10309 06:54:36.838936
10310 06:54:36.851998 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10311 06:54:36.852138
10312 06:54:36.852244 Loading FIT.
10313 06:54:36.852362
10314 06:54:36.855600 Image ramdisk-1 has 47541966 bytes.
10315 06:54:36.856011
10316 06:54:36.859010 Image fdt-1 has 47278 bytes.
10317 06:54:36.859420
10318 06:54:36.862651 Image kernel-1 has 12050581 bytes.
10319 06:54:36.863156
10320 06:54:36.872646 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10321 06:54:36.873164
10322 06:54:36.889164 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10323 06:54:36.889685
10324 06:54:36.895835 Choosing best match conf-1 for compat google,spherion-rev2.
10325 06:54:36.896379
10326 06:54:36.903471 Connected to device vid:did:rid of 1ae0:0028:00
10327 06:54:36.911658
10328 06:54:36.915315 tpm_get_response: command 0x17b, return code 0x0
10329 06:54:36.915823
10330 06:54:36.918313 ec_init: CrosEC protocol v3 supported (256, 248)
10331 06:54:36.923346
10332 06:54:36.926504 tpm_cleanup: add release locality here.
10333 06:54:36.926922
10334 06:54:36.927247 Shutting down all USB controllers.
10335 06:54:36.929602
10336 06:54:36.930044 Removing current net device
10337 06:54:36.930398
10338 06:54:36.936461 Exiting depthcharge with code 4 at timestamp: 66686735
10339 06:54:36.936878
10340 06:54:36.940197 LZMA decompressing kernel-1 to 0x821a6718
10341 06:54:36.940661
10342 06:54:36.942961 LZMA decompressing kernel-1 to 0x40000000
10343 06:54:38.442147
10344 06:54:38.442689 jumping to kernel
10345 06:54:38.444760 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10346 06:54:38.445232 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10347 06:54:38.445679 Setting prompt string to ['Linux version [0-9]']
10348 06:54:38.446032 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10349 06:54:38.446370 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10350 06:54:38.525551
10351 06:54:38.528419 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10352 06:54:38.532450 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10353 06:54:38.532909 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10354 06:54:38.533264 Setting prompt string to []
10355 06:54:38.533648 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10356 06:54:38.534005 Using line separator: #'\n'#
10357 06:54:38.534303 No login prompt set.
10358 06:54:38.534616 Parsing kernel messages
10359 06:54:38.535038 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10360 06:54:38.535583 [login-action] Waiting for messages, (timeout 00:03:46)
10361 06:54:38.552125 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10362 06:54:38.554917 [ 0.000000] random: crng init done
10363 06:54:38.561405 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10364 06:54:38.565373 [ 0.000000] efi: UEFI not found.
10365 06:54:38.572133 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10366 06:54:38.578546 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10367 06:54:38.587897 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10368 06:54:38.598172 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10369 06:54:38.604430 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10370 06:54:38.611440 [ 0.000000] printk: bootconsole [mtk8250] enabled
10371 06:54:38.618113 [ 0.000000] NUMA: No NUMA configuration found
10372 06:54:38.624746 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10373 06:54:38.627904 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10374 06:54:38.631384 [ 0.000000] Zone ranges:
10375 06:54:38.637989 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10376 06:54:38.641890 [ 0.000000] DMA32 empty
10377 06:54:38.648620 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10378 06:54:38.651506 [ 0.000000] Movable zone start for each node
10379 06:54:38.654602 [ 0.000000] Early memory node ranges
10380 06:54:38.661665 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10381 06:54:38.668482 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10382 06:54:38.675292 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10383 06:54:38.678326 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10384 06:54:38.684976 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10385 06:54:38.691024 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10386 06:54:38.749761 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10387 06:54:38.756482 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10388 06:54:38.763391 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10389 06:54:38.766430 [ 0.000000] psci: probing for conduit method from DT.
10390 06:54:38.773290 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10391 06:54:38.776065 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10392 06:54:38.783301 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10393 06:54:38.785960 [ 0.000000] psci: SMC Calling Convention v1.2
10394 06:54:38.792654 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10395 06:54:38.796458 [ 0.000000] Detected VIPT I-cache on CPU0
10396 06:54:38.803071 [ 0.000000] CPU features: detected: GIC system register CPU interface
10397 06:54:38.809633 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10398 06:54:38.815820 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10399 06:54:38.822713 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10400 06:54:38.829307 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10401 06:54:38.839380 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10402 06:54:38.842818 [ 0.000000] alternatives: applying boot alternatives
10403 06:54:38.849459 [ 0.000000] Fallback order for Node 0: 0
10404 06:54:38.855770 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10405 06:54:38.859079 [ 0.000000] Policy zone: Normal
10406 06:54:38.872634 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10407 06:54:38.881801 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10408 06:54:38.894231 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10409 06:54:38.904365 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10410 06:54:38.911226 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10411 06:54:38.914419 <6>[ 0.000000] software IO TLB: area num 8.
10412 06:54:38.972007 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10413 06:54:39.120943 <6>[ 0.000000] Memory: 7920828K/8385536K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 431940K reserved, 32768K cma-reserved)
10414 06:54:39.127359 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10415 06:54:39.134576 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10416 06:54:39.137734 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10417 06:54:39.143796 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10418 06:54:39.150633 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10419 06:54:39.153992 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10420 06:54:39.164395 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10421 06:54:39.170627 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10422 06:54:39.177062 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10423 06:54:39.183720 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10424 06:54:39.186922 <6>[ 0.000000] GICv3: 608 SPIs implemented
10425 06:54:39.190344 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10426 06:54:39.197012 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10427 06:54:39.200474 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10428 06:54:39.207478 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10429 06:54:39.219975 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10430 06:54:39.233231 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10431 06:54:39.240401 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10432 06:54:39.247621 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10433 06:54:39.260791 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10434 06:54:39.267645 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10435 06:54:39.274368 <6>[ 0.009184] Console: colour dummy device 80x25
10436 06:54:39.284386 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10437 06:54:39.290454 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10438 06:54:39.293778 <6>[ 0.029224] LSM: Security Framework initializing
10439 06:54:39.300442 <6>[ 0.034164] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10440 06:54:39.310463 <6>[ 0.042026] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10441 06:54:39.317153 <6>[ 0.051444] cblist_init_generic: Setting adjustable number of callback queues.
10442 06:54:39.324067 <6>[ 0.058935] cblist_init_generic: Setting shift to 3 and lim to 1.
10443 06:54:39.334326 <6>[ 0.065312] cblist_init_generic: Setting adjustable number of callback queues.
10444 06:54:39.337548 <6>[ 0.072740] cblist_init_generic: Setting shift to 3 and lim to 1.
10445 06:54:39.343923 <6>[ 0.079142] rcu: Hierarchical SRCU implementation.
10446 06:54:39.350468 <6>[ 0.084158] rcu: Max phase no-delay instances is 1000.
10447 06:54:39.357413 <6>[ 0.091180] EFI services will not be available.
10448 06:54:39.360621 <6>[ 0.096128] smp: Bringing up secondary CPUs ...
10449 06:54:39.368847 <6>[ 0.101181] Detected VIPT I-cache on CPU1
10450 06:54:39.375810 <6>[ 0.101251] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10451 06:54:39.381574 <6>[ 0.101282] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10452 06:54:39.384662 <6>[ 0.101622] Detected VIPT I-cache on CPU2
10453 06:54:39.391564 <6>[ 0.101670] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10454 06:54:39.398095 <6>[ 0.101686] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10455 06:54:39.404970 <6>[ 0.101942] Detected VIPT I-cache on CPU3
10456 06:54:39.411498 <6>[ 0.101989] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10457 06:54:39.418348 <6>[ 0.102002] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10458 06:54:39.421743 <6>[ 0.102307] CPU features: detected: Spectre-v4
10459 06:54:39.428259 <6>[ 0.102314] CPU features: detected: Spectre-BHB
10460 06:54:39.431631 <6>[ 0.102318] Detected PIPT I-cache on CPU4
10461 06:54:39.438679 <6>[ 0.102376] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10462 06:54:39.444805 <6>[ 0.102392] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10463 06:54:39.451027 <6>[ 0.102680] Detected PIPT I-cache on CPU5
10464 06:54:39.458158 <6>[ 0.102742] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10465 06:54:39.464963 <6>[ 0.102759] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10466 06:54:39.467747 <6>[ 0.103043] Detected PIPT I-cache on CPU6
10467 06:54:39.475021 <6>[ 0.103106] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10468 06:54:39.481372 <6>[ 0.103123] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10469 06:54:39.484712 <6>[ 0.103420] Detected PIPT I-cache on CPU7
10470 06:54:39.494522 <6>[ 0.103484] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10471 06:54:39.501232 <6>[ 0.103501] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10472 06:54:39.504397 <6>[ 0.103547] smp: Brought up 1 node, 8 CPUs
10473 06:54:39.507960 <6>[ 0.244735] SMP: Total of 8 processors activated.
10474 06:54:39.514838 <6>[ 0.249656] CPU features: detected: 32-bit EL0 Support
10475 06:54:39.524274 <6>[ 0.255019] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10476 06:54:39.531010 <6>[ 0.263820] CPU features: detected: Common not Private translations
10477 06:54:39.534158 <6>[ 0.270295] CPU features: detected: CRC32 instructions
10478 06:54:39.540793 <6>[ 0.275680] CPU features: detected: RCpc load-acquire (LDAPR)
10479 06:54:39.547745 <6>[ 0.281640] CPU features: detected: LSE atomic instructions
10480 06:54:39.554229 <6>[ 0.287422] CPU features: detected: Privileged Access Never
10481 06:54:39.557527 <6>[ 0.293201] CPU features: detected: RAS Extension Support
10482 06:54:39.564406 <6>[ 0.298810] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10483 06:54:39.571157 <6>[ 0.306031] CPU: All CPU(s) started at EL2
10484 06:54:39.577189 <6>[ 0.310348] alternatives: applying system-wide alternatives
10485 06:54:39.586178 <6>[ 0.321068] devtmpfs: initialized
10486 06:54:39.601418 <6>[ 0.329943] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10487 06:54:39.608032 <6>[ 0.339903] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10488 06:54:39.614955 <6>[ 0.348110] pinctrl core: initialized pinctrl subsystem
10489 06:54:39.618078 <6>[ 0.354763] DMI not present or invalid.
10490 06:54:39.624506 <6>[ 0.359178] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10491 06:54:39.634571 <6>[ 0.366047] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10492 06:54:39.640829 <6>[ 0.373632] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10493 06:54:39.650700 <6>[ 0.381860] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10494 06:54:39.653685 <6>[ 0.390101] audit: initializing netlink subsys (disabled)
10495 06:54:39.664212 <5>[ 0.395790] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10496 06:54:39.670965 <6>[ 0.396489] thermal_sys: Registered thermal governor 'step_wise'
10497 06:54:39.677583 <6>[ 0.403758] thermal_sys: Registered thermal governor 'power_allocator'
10498 06:54:39.680970 <6>[ 0.410013] cpuidle: using governor menu
10499 06:54:39.687172 <6>[ 0.420969] NET: Registered PF_QIPCRTR protocol family
10500 06:54:39.693625 <6>[ 0.426443] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10501 06:54:39.700405 <6>[ 0.433545] ASID allocator initialised with 32768 entries
10502 06:54:39.703338 <6>[ 0.440109] Serial: AMBA PL011 UART driver
10503 06:54:39.713678 <4>[ 0.448897] Trying to register duplicate clock ID: 134
10504 06:54:39.767585 <6>[ 0.506078] KASLR enabled
10505 06:54:39.781401 <6>[ 0.513683] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10506 06:54:39.788243 <6>[ 0.520695] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10507 06:54:39.795000 <6>[ 0.527184] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10508 06:54:39.801734 <6>[ 0.534187] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10509 06:54:39.808808 <6>[ 0.540674] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10510 06:54:39.815165 <6>[ 0.547675] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10511 06:54:39.821719 <6>[ 0.554164] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10512 06:54:39.828252 <6>[ 0.561170] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10513 06:54:39.831726 <6>[ 0.568624] ACPI: Interpreter disabled.
10514 06:54:39.839984 <6>[ 0.575080] iommu: Default domain type: Translated
10515 06:54:39.846462 <6>[ 0.580193] iommu: DMA domain TLB invalidation policy: strict mode
10516 06:54:39.849888 <5>[ 0.586861] SCSI subsystem initialized
10517 06:54:39.856166 <6>[ 0.591105] usbcore: registered new interface driver usbfs
10518 06:54:39.863038 <6>[ 0.596836] usbcore: registered new interface driver hub
10519 06:54:39.865877 <6>[ 0.602387] usbcore: registered new device driver usb
10520 06:54:39.873440 <6>[ 0.608510] pps_core: LinuxPPS API ver. 1 registered
10521 06:54:39.882833 <6>[ 0.613705] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10522 06:54:39.886080 <6>[ 0.623048] PTP clock support registered
10523 06:54:39.889601 <6>[ 0.627287] EDAC MC: Ver: 3.0.0
10524 06:54:39.897334 <6>[ 0.632481] FPGA manager framework
10525 06:54:39.900932 <6>[ 0.636156] Advanced Linux Sound Architecture Driver Initialized.
10526 06:54:39.904543 <6>[ 0.642907] vgaarb: loaded
10527 06:54:39.911283 <6>[ 0.646047] clocksource: Switched to clocksource arch_sys_counter
10528 06:54:39.917451 <5>[ 0.652492] VFS: Disk quotas dquot_6.6.0
10529 06:54:39.924372 <6>[ 0.656681] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10530 06:54:39.927506 <6>[ 0.663870] pnp: PnP ACPI: disabled
10531 06:54:39.935349 <6>[ 0.670526] NET: Registered PF_INET protocol family
10532 06:54:39.945442 <6>[ 0.676114] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10533 06:54:39.956713 <6>[ 0.688431] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10534 06:54:39.966308 <6>[ 0.697243] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10535 06:54:39.973035 <6>[ 0.705215] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10536 06:54:39.982841 <6>[ 0.713915] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10537 06:54:39.989423 <6>[ 0.723663] TCP: Hash tables configured (established 65536 bind 65536)
10538 06:54:39.996008 <6>[ 0.730529] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10539 06:54:40.006597 <6>[ 0.737725] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10540 06:54:40.012399 <6>[ 0.745426] NET: Registered PF_UNIX/PF_LOCAL protocol family
10541 06:54:40.016069 <6>[ 0.751574] RPC: Registered named UNIX socket transport module.
10542 06:54:40.022776 <6>[ 0.757725] RPC: Registered udp transport module.
10543 06:54:40.025636 <6>[ 0.762657] RPC: Registered tcp transport module.
10544 06:54:40.032685 <6>[ 0.767589] RPC: Registered tcp NFSv4.1 backchannel transport module.
10545 06:54:40.039563 <6>[ 0.774256] PCI: CLS 0 bytes, default 64
10546 06:54:40.042864 <6>[ 0.778601] Unpacking initramfs...
10547 06:54:40.066797 <6>[ 0.798158] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10548 06:54:40.076718 <6>[ 0.806825] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10549 06:54:40.079850 <6>[ 0.815679] kvm [1]: IPA Size Limit: 40 bits
10550 06:54:40.086055 <6>[ 0.820204] kvm [1]: GICv3: no GICV resource entry
10551 06:54:40.089814 <6>[ 0.825226] kvm [1]: disabling GICv2 emulation
10552 06:54:40.096382 <6>[ 0.829907] kvm [1]: GIC system register CPU interface enabled
10553 06:54:40.099905 <6>[ 0.836061] kvm [1]: vgic interrupt IRQ18
10554 06:54:40.106299 <6>[ 0.840409] kvm [1]: VHE mode initialized successfully
10555 06:54:40.112869 <5>[ 0.846905] Initialise system trusted keyrings
10556 06:54:40.119348 <6>[ 0.851721] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10557 06:54:40.126711 <6>[ 0.861631] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10558 06:54:40.132837 <5>[ 0.868008] NFS: Registering the id_resolver key type
10559 06:54:40.136414 <5>[ 0.873303] Key type id_resolver registered
10560 06:54:40.143383 <5>[ 0.877717] Key type id_legacy registered
10561 06:54:40.149640 <6>[ 0.881992] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10562 06:54:40.156529 <6>[ 0.888916] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10563 06:54:40.163106 <6>[ 0.896636] 9p: Installing v9fs 9p2000 file system support
10564 06:54:40.198391 <5>[ 0.933741] Key type asymmetric registered
10565 06:54:40.201857 <5>[ 0.938072] Asymmetric key parser 'x509' registered
10566 06:54:40.211686 <6>[ 0.943210] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10567 06:54:40.215665 <6>[ 0.950826] io scheduler mq-deadline registered
10568 06:54:40.218633 <6>[ 0.955587] io scheduler kyber registered
10569 06:54:40.237486 <6>[ 0.972730] EINJ: ACPI disabled.
10570 06:54:40.269075 <4>[ 0.997937] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 06:54:40.278987 <4>[ 1.008561] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10572 06:54:40.293747 <6>[ 1.029123] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10573 06:54:40.301522 <6>[ 1.037059] printk: console [ttyS0] disabled
10574 06:54:40.329733 <6>[ 1.061707] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10575 06:54:40.336817 <6>[ 1.071186] printk: console [ttyS0] enabled
10576 06:54:40.340055 <6>[ 1.071186] printk: console [ttyS0] enabled
10577 06:54:40.346546 <6>[ 1.080079] printk: bootconsole [mtk8250] disabled
10578 06:54:40.349975 <6>[ 1.080079] printk: bootconsole [mtk8250] disabled
10579 06:54:40.356802 <6>[ 1.091283] SuperH (H)SCI(F) driver initialized
10580 06:54:40.359707 <6>[ 1.096570] msm_serial: driver initialized
10581 06:54:40.373643 <6>[ 1.105590] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10582 06:54:40.383593 <6>[ 1.114143] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10583 06:54:40.390280 <6>[ 1.122685] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10584 06:54:40.400238 <6>[ 1.131313] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10585 06:54:40.406939 <6>[ 1.140018] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10586 06:54:40.416673 <6>[ 1.148731] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10587 06:54:40.426992 <6>[ 1.157270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10588 06:54:40.433287 <6>[ 1.166084] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10589 06:54:40.443544 <6>[ 1.174629] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10590 06:54:40.455217 <6>[ 1.190423] loop: module loaded
10591 06:54:40.461746 <6>[ 1.196420] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10592 06:54:40.484331 <4>[ 1.219626] mtk-pmic-keys: Failed to locate of_node [id: -1]
10593 06:54:40.490869 <6>[ 1.226523] megasas: 07.719.03.00-rc1
10594 06:54:40.500500 <6>[ 1.235985] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10595 06:54:40.510271 <6>[ 1.245427] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10596 06:54:40.526979 <6>[ 1.261790] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10597 06:54:40.583215 <6>[ 1.311447] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10598 06:54:42.065306 <6>[ 2.800905] Freeing initrd memory: 46424K
10599 06:54:42.076170 <6>[ 2.811239] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10600 06:54:42.086786 <6>[ 2.822105] tun: Universal TUN/TAP device driver, 1.6
10601 06:54:42.089958 <6>[ 2.828161] thunder_xcv, ver 1.0
10602 06:54:42.093351 <6>[ 2.831666] thunder_bgx, ver 1.0
10603 06:54:42.096318 <6>[ 2.835164] nicpf, ver 1.0
10604 06:54:42.106948 <6>[ 2.839162] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10605 06:54:42.110623 <6>[ 2.846638] hns3: Copyright (c) 2017 Huawei Corporation.
10606 06:54:42.117170 <6>[ 2.852229] hclge is initializing
10607 06:54:42.120466 <6>[ 2.855810] e1000: Intel(R) PRO/1000 Network Driver
10608 06:54:42.127339 <6>[ 2.860938] e1000: Copyright (c) 1999-2006 Intel Corporation.
10609 06:54:42.130534 <6>[ 2.866950] e1000e: Intel(R) PRO/1000 Network Driver
10610 06:54:42.137076 <6>[ 2.872165] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10611 06:54:42.143018 <6>[ 2.878350] igb: Intel(R) Gigabit Ethernet Network Driver
10612 06:54:42.150194 <6>[ 2.883999] igb: Copyright (c) 2007-2014 Intel Corporation.
10613 06:54:42.156921 <6>[ 2.889834] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10614 06:54:42.163232 <6>[ 2.896352] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10615 06:54:42.166870 <6>[ 2.902812] sky2: driver version 1.30
10616 06:54:42.172920 <6>[ 2.907791] VFIO - User Level meta-driver version: 0.3
10617 06:54:42.180373 <6>[ 2.916028] usbcore: registered new interface driver usb-storage
10618 06:54:42.186507 <6>[ 2.922467] usbcore: registered new device driver onboard-usb-hub
10619 06:54:42.196198 <6>[ 2.931578] mt6397-rtc mt6359-rtc: registered as rtc0
10620 06:54:42.206351 <6>[ 2.937038] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:51:59 UTC (1706943119)
10621 06:54:42.208915 <6>[ 2.946618] i2c_dev: i2c /dev entries driver
10622 06:54:42.225853 <6>[ 2.958288] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10623 06:54:42.245705 <6>[ 2.981271] cpu cpu0: EM: created perf domain
10624 06:54:42.248996 <6>[ 2.986217] cpu cpu4: EM: created perf domain
10625 06:54:42.256225 <6>[ 2.991816] sdhci: Secure Digital Host Controller Interface driver
10626 06:54:42.263595 <6>[ 2.998252] sdhci: Copyright(c) Pierre Ossman
10627 06:54:42.269615 <6>[ 3.003195] Synopsys Designware Multimedia Card Interface Driver
10628 06:54:42.276751 <6>[ 3.009827] sdhci-pltfm: SDHCI platform and OF driver helper
10629 06:54:42.279740 <6>[ 3.009952] mmc0: CQHCI version 5.10
10630 06:54:42.285932 <6>[ 3.019931] ledtrig-cpu: registered to indicate activity on CPUs
10631 06:54:42.293110 <6>[ 3.027040] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10632 06:54:42.299416 <6>[ 3.034103] usbcore: registered new interface driver usbhid
10633 06:54:42.303093 <6>[ 3.039924] usbhid: USB HID core driver
10634 06:54:42.309025 <6>[ 3.044125] spi_master spi0: will run message pump with realtime priority
10635 06:54:42.356643 <6>[ 3.085180] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10636 06:54:42.376110 <6>[ 3.101006] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10637 06:54:42.379294 <6>[ 3.114589] mmc0: Command Queue Engine enabled
10638 06:54:42.386177 <6>[ 3.119394] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10639 06:54:42.392718 <6>[ 3.126498] cros-ec-spi spi0.0: Chrome EC device registered
10640 06:54:42.395913 <6>[ 3.126803] mmcblk0: mmc0:0001 DA4128 116 GiB
10641 06:54:42.406525 <6>[ 3.141991] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10642 06:54:42.414376 <6>[ 3.149589] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10643 06:54:42.420947 <6>[ 3.155691] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10644 06:54:42.427610 <6>[ 3.161804] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10645 06:54:42.437348 <6>[ 3.165969] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10646 06:54:42.443844 <6>[ 3.178725] NET: Registered PF_PACKET protocol family
10647 06:54:42.447554 <6>[ 3.184154] 9pnet: Installing 9P2000 support
10648 06:54:42.453813 <5>[ 3.188729] Key type dns_resolver registered
10649 06:54:42.457502 <6>[ 3.193828] registered taskstats version 1
10650 06:54:42.463702 <5>[ 3.198251] Loading compiled-in X.509 certificates
10651 06:54:42.493893 <4>[ 3.221936] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 06:54:42.503389 <4>[ 3.232749] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 06:54:42.509607 <3>[ 3.243348] debugfs: File 'uA_load' in directory '/' already present!
10654 06:54:42.516450 <3>[ 3.250062] debugfs: File 'min_uV' in directory '/' already present!
10655 06:54:42.523359 <3>[ 3.256674] debugfs: File 'max_uV' in directory '/' already present!
10656 06:54:42.529808 <3>[ 3.263284] debugfs: File 'constraint_flags' in directory '/' already present!
10657 06:54:42.541548 <3>[ 3.273560] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10658 06:54:42.554486 <6>[ 3.290255] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10659 06:54:42.561709 <6>[ 3.297106] xhci-mtk 11200000.usb: xHCI Host Controller
10660 06:54:42.568338 <6>[ 3.302612] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10661 06:54:42.578706 <6>[ 3.310524] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10662 06:54:42.585011 <6>[ 3.319966] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10663 06:54:42.591813 <6>[ 3.326057] xhci-mtk 11200000.usb: xHCI Host Controller
10664 06:54:42.598473 <6>[ 3.331538] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10665 06:54:42.604803 <6>[ 3.339200] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10666 06:54:42.611789 <6>[ 3.347045] hub 1-0:1.0: USB hub found
10667 06:54:42.615411 <6>[ 3.351072] hub 1-0:1.0: 1 port detected
10668 06:54:42.624670 <6>[ 3.355378] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10669 06:54:42.628173 <6>[ 3.364107] hub 2-0:1.0: USB hub found
10670 06:54:42.631681 <6>[ 3.368128] hub 2-0:1.0: 1 port detected
10671 06:54:42.639447 <6>[ 3.374937] mtk-msdc 11f70000.mmc: Got CD GPIO
10672 06:54:42.653235 <6>[ 3.385476] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10673 06:54:42.660348 <6>[ 3.393504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10674 06:54:42.669924 <4>[ 3.401438] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10675 06:54:42.679689 <6>[ 3.411000] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10676 06:54:42.686341 <6>[ 3.419077] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10677 06:54:42.693182 <6>[ 3.427092] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10678 06:54:42.702913 <6>[ 3.435012] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10679 06:54:42.709688 <6>[ 3.442829] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10680 06:54:42.719555 <6>[ 3.450646] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10681 06:54:42.729877 <6>[ 3.461040] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10682 06:54:42.736480 <6>[ 3.469403] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10683 06:54:42.746461 <6>[ 3.477749] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10684 06:54:42.752803 <6>[ 3.486090] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10685 06:54:42.762561 <6>[ 3.494436] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10686 06:54:42.769221 <6>[ 3.502777] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10687 06:54:42.778978 <6>[ 3.511115] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10688 06:54:42.785951 <6>[ 3.519453] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10689 06:54:42.795888 <6>[ 3.527794] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10690 06:54:42.802320 <6>[ 3.536133] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10691 06:54:42.812086 <6>[ 3.544471] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10692 06:54:42.821983 <6>[ 3.552810] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10693 06:54:42.828784 <6>[ 3.561148] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10694 06:54:42.838272 <6>[ 3.569486] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10695 06:54:42.845521 <6>[ 3.577824] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10696 06:54:42.851632 <6>[ 3.586547] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10697 06:54:42.858424 <6>[ 3.593682] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10698 06:54:42.864914 <6>[ 3.600441] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10699 06:54:42.874736 <6>[ 3.607203] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10700 06:54:42.881809 <6>[ 3.614144] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10701 06:54:42.888264 <6>[ 3.620995] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10702 06:54:42.897868 <6>[ 3.630124] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10703 06:54:42.907896 <6>[ 3.639241] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10704 06:54:42.917987 <6>[ 3.648534] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10705 06:54:42.927368 <6>[ 3.658001] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10706 06:54:42.937380 <6>[ 3.667467] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10707 06:54:42.943806 <6>[ 3.676585] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10708 06:54:42.954230 <6>[ 3.686053] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10709 06:54:42.963744 <6>[ 3.695171] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10710 06:54:42.973734 <6>[ 3.704466] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10711 06:54:42.983689 <6>[ 3.714626] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10712 06:54:42.994216 <6>[ 3.726344] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10713 06:54:43.046143 <6>[ 3.778325] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10714 06:54:43.200516 <6>[ 3.936461] hub 1-1:1.0: USB hub found
10715 06:54:43.203950 <6>[ 3.940969] hub 1-1:1.0: 4 ports detected
10716 06:54:43.213590 <6>[ 3.949580] hub 1-1:1.0: USB hub found
10717 06:54:43.217074 <6>[ 3.953922] hub 1-1:1.0: 4 ports detected
10718 06:54:43.326274 <6>[ 4.058690] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10719 06:54:43.352237 <6>[ 4.088199] hub 2-1:1.0: USB hub found
10720 06:54:43.356079 <6>[ 4.092691] hub 2-1:1.0: 3 ports detected
10721 06:54:43.365466 <6>[ 4.100838] hub 2-1:1.0: USB hub found
10722 06:54:43.368438 <6>[ 4.105286] hub 2-1:1.0: 3 ports detected
10723 06:54:43.541819 <6>[ 4.274349] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10724 06:54:43.674046 <6>[ 4.409967] hub 1-1.4:1.0: USB hub found
10725 06:54:43.677539 <6>[ 4.414604] hub 1-1.4:1.0: 2 ports detected
10726 06:54:43.686249 <6>[ 4.421984] hub 1-1.4:1.0: USB hub found
10727 06:54:43.689538 <6>[ 4.426549] hub 1-1.4:1.0: 2 ports detected
10728 06:54:43.758339 <6>[ 4.490452] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10729 06:54:43.985733 <6>[ 4.718363] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10730 06:54:44.177883 <6>[ 4.910348] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10731 06:54:55.275050 <6>[ 16.015352] ALSA device list:
10732 06:54:55.281735 <6>[ 16.018638] No soundcards found.
10733 06:54:55.290050 <6>[ 16.026624] Freeing unused kernel memory: 8448K
10734 06:54:55.293207 <6>[ 16.031625] Run /init as init process
10735 06:54:55.340775 <6>[ 16.077597] NET: Registered PF_INET6 protocol family
10736 06:54:55.347463 <6>[ 16.083832] Segment Routing with IPv6
10737 06:54:55.350395 <6>[ 16.087769] In-situ OAM (IOAM) with IPv6
10738 06:54:55.384190 <30>[ 16.101380] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10739 06:54:55.387875 <30>[ 16.125336] systemd[1]: Detected architecture arm64.
10740 06:54:55.388452
10741 06:54:55.393986 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10742 06:54:55.394403
10743 06:54:55.409674 <30>[ 16.146411] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10744 06:54:55.549790 <30>[ 16.283169] systemd[1]: Queued start job for default target Graphical Interface.
10745 06:54:55.590291 <30>[ 16.327092] systemd[1]: Created slice system-getty.slice.
10746 06:54:55.596869 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10747 06:54:55.614056 <30>[ 16.350911] systemd[1]: Created slice system-modprobe.slice.
10748 06:54:55.620960 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10749 06:54:55.638944 <30>[ 16.375584] systemd[1]: Created slice system-serial\x2dgetty.slice.
10750 06:54:55.648584 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10751 06:54:55.662017 <30>[ 16.398721] systemd[1]: Created slice User and Session Slice.
10752 06:54:55.668430 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10753 06:54:55.689291 <30>[ 16.423056] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10754 06:54:55.699254 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10755 06:54:55.717230 <30>[ 16.451042] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10756 06:54:55.723912 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10757 06:54:55.748694 <30>[ 16.478815] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10758 06:54:55.755543 <30>[ 16.491067] systemd[1]: Reached target Local Encrypted Volumes.
10759 06:54:55.762035 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10760 06:54:55.778080 <30>[ 16.514834] systemd[1]: Reached target Paths.
10761 06:54:55.781777 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10762 06:54:55.797430 <30>[ 16.534307] systemd[1]: Reached target Remote File Systems.
10763 06:54:55.804398 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10764 06:54:55.817482 <30>[ 16.554288] systemd[1]: Reached target Slices.
10765 06:54:55.820638 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10766 06:54:55.837865 <30>[ 16.574748] systemd[1]: Reached target Swap.
10767 06:54:55.841203 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10768 06:54:55.861555 <30>[ 16.594839] systemd[1]: Listening on initctl Compatibility Named Pipe.
10769 06:54:55.867862 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10770 06:54:55.882506 <30>[ 16.619705] systemd[1]: Listening on Journal Audit Socket.
10771 06:54:55.888988 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10772 06:54:55.906384 <30>[ 16.643445] systemd[1]: Listening on Journal Socket (/dev/log).
10773 06:54:55.913458 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10774 06:54:55.930412 <30>[ 16.667512] systemd[1]: Listening on Journal Socket.
10775 06:54:55.937200 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10776 06:54:55.953197 <30>[ 16.686980] systemd[1]: Listening on Network Service Netlink Socket.
10777 06:54:55.959975 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10778 06:54:55.975074 <30>[ 16.711506] systemd[1]: Listening on udev Control Socket.
10779 06:54:55.980940 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10780 06:54:55.998369 <30>[ 16.735378] systemd[1]: Listening on udev Kernel Socket.
10781 06:54:56.004980 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10782 06:54:56.045719 <30>[ 16.782455] systemd[1]: Mounting Huge Pages File System...
10783 06:54:56.052516 Mounting [0;1;39mHuge Pages File System[0m...
10784 06:54:56.067643 <30>[ 16.804850] systemd[1]: Mounting POSIX Message Queue File System...
10785 06:54:56.074774 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10786 06:54:56.129590 <30>[ 16.866633] systemd[1]: Mounting Kernel Debug File System...
10787 06:54:56.136211 Mounting [0;1;39mKernel Debug File System[0m...
10788 06:54:56.152878 <30>[ 16.886745] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10789 06:54:56.166195 <30>[ 16.899677] systemd[1]: Starting Create list of static device nodes for the current kernel...
10790 06:54:56.172478 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10791 06:54:56.209645 <30>[ 16.946660] systemd[1]: Starting Load Kernel Module configfs...
10792 06:54:56.216227 Starting [0;1;39mLoad Kernel Module configfs[0m...
10793 06:54:56.237903 <30>[ 16.974476] systemd[1]: Starting Load Kernel Module drm...
10794 06:54:56.244451 Starting [0;1;39mLoad Kernel Module drm[0m...
10795 06:54:56.261521 <30>[ 16.994706] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10796 06:54:56.297744 <30>[ 17.034910] systemd[1]: Starting Journal Service...
10797 06:54:56.301314 Starting [0;1;39mJournal Service[0m...
10798 06:54:56.320624 <30>[ 17.057331] systemd[1]: Starting Load Kernel Modules...
10799 06:54:56.327270 Starting [0;1;39mLoad Kernel Modules[0m...
10800 06:54:56.347459 <30>[ 17.080780] systemd[1]: Starting Remount Root and Kernel File Systems...
10801 06:54:56.353789 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10802 06:54:56.368777 <30>[ 17.105902] systemd[1]: Starting Coldplug All udev Devices...
10803 06:54:56.375612 Starting [0;1;39mColdplug All udev Devices[0m...
10804 06:54:56.393259 <30>[ 17.130423] systemd[1]: Started Journal Service.
10805 06:54:56.400192 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10806 06:54:56.415887 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10807 06:54:56.434463 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10808 06:54:56.451195 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10809 06:54:56.470115 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10810 06:54:56.487297 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10811 06:54:56.503674 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10812 06:54:56.523276 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10813 06:54:56.543542 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10814 06:54:56.557086 See 'systemctl status systemd-remount-fs.service' for details.
10815 06:54:56.617441 Mounting [0;1;39mKernel Configuration File System[0m...
10816 06:54:56.638338 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10817 06:54:56.653624 <46>[ 17.387027] systemd-journald[185]: Received client request to flush runtime journal.
10818 06:54:56.662607 Starting [0;1;39mLoad/Save Random Seed[0m...
10819 06:54:56.682888 Starting [0;1;39mApply Kernel Variables[0m...
10820 06:54:56.702577 Starting [0;1;39mCreate System Users[0m...
10821 06:54:56.722553 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10822 06:54:56.738479 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10823 06:54:56.758549 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10824 06:54:56.770952 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10825 06:54:56.787460 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10826 06:54:56.802868 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10827 06:54:56.845968 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10828 06:54:56.878832 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10829 06:54:56.890060 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10830 06:54:56.909539 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10831 06:54:56.969568 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10832 06:54:56.994280 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10833 06:54:57.020210 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10834 06:54:57.039391 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10835 06:54:57.082791 Starting [0;1;39mNetwork Service[0m...
10836 06:54:57.104480 Starting [0;1;39mNetwork Time Synchronization[0m...
10837 06:54:57.135944 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10838 06:54:57.172023 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10839 06:54:57.186574 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10840 06:54:57.213768 <6>[ 17.947515] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10841 06:54:57.220398 <4>[ 17.947931] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10842 06:54:57.227136 <6>[ 17.947984] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10843 06:54:57.233744 <6>[ 17.954661] remoteproc remoteproc0: scp is available
10844 06:54:57.236711 <6>[ 17.954739] remoteproc remoteproc0: powering up scp
10845 06:54:57.246640 <6>[ 17.954744] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10846 06:54:57.253520 <6>[ 17.954761] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10847 06:54:57.260095 <6>[ 17.955226] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10848 06:54:57.270324 <6>[ 17.955239] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10849 06:54:57.277101 [[0;32m OK [<6>[ 18.013175] usbcore: registered new device driver r8152-cfgselector
10850 06:54:57.283249 <6>[ 18.016296] mc: Linux media interface: v0.10
10851 06:54:57.290012 0m] Found device<4>[ 18.016296] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10852 06:54:57.293363 [0;1;39m/dev/ttyS0[0m.
10853 06:54:57.306033 <3>[ 18.039997] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 06:54:57.316179 <3>[ 18.049310] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10855 06:54:57.326178 <3>[ 18.058566] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 06:54:57.336214 <3>[ 18.068650] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 06:54:57.342303 <6>[ 18.068702] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10858 06:54:57.349220 <3>[ 18.076929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 06:54:57.359045 <6>[ 18.079970] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10860 06:54:57.365633 <6>[ 18.079975] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10861 06:54:57.372470 <6>[ 18.079979] remoteproc remoteproc0: remote processor scp is now up
10862 06:54:57.378721 <6>[ 18.080295] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10863 06:54:57.386039 <6>[ 18.080300] pci_bus 0000:00: root bus resource [bus 00-ff]
10864 06:54:57.392830 <6>[ 18.080304] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10865 06:54:57.403020 <6>[ 18.080307] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10866 06:54:57.409697 <6>[ 18.080333] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10867 06:54:57.416263 <6>[ 18.080346] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10868 06:54:57.419444 <6>[ 18.080408] pci 0000:00:00.0: supports D1 D2
10869 06:54:57.425812 <6>[ 18.080409] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10870 06:54:57.435561 <6>[ 18.081589] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10871 06:54:57.442098 <6>[ 18.081683] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10872 06:54:57.448780 <6>[ 18.081709] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10873 06:54:57.455933 <6>[ 18.081727] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10874 06:54:57.465720 <6>[ 18.081742] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10875 06:54:57.468817 <6>[ 18.081845] pci 0000:01:00.0: supports D1 D2
10876 06:54:57.476015 <6>[ 18.081846] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10877 06:54:57.482642 <6>[ 18.086134] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10878 06:54:57.489253 <3>[ 18.092950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10879 06:54:57.499499 <6>[ 18.101328] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10880 06:54:57.506594 <3>[ 18.108343] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 06:54:57.517462 <3>[ 18.108350] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10882 06:54:57.524193 <4>[ 18.112014] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10883 06:54:57.526809 <4>[ 18.112014] Fallback method does not support PEC.
10884 06:54:57.536974 <6>[ 18.115384] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10885 06:54:57.543532 <3>[ 18.121822] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10886 06:54:57.553833 <6>[ 18.122911] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10887 06:54:57.563576 <6>[ 18.125766] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10888 06:54:57.569796 <3>[ 18.127138] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 06:54:57.579851 <6>[ 18.127473] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10890 06:54:57.586457 <3>[ 18.134668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10891 06:54:57.596310 <6>[ 18.144615] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10892 06:54:57.603016 <3>[ 18.150734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10893 06:54:57.613795 <6>[ 18.152886] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10894 06:54:57.624365 <6>[ 18.153208] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10895 06:54:57.630853 <6>[ 18.158221] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10896 06:54:57.640872 <3>[ 18.162735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10897 06:54:57.647301 <6>[ 18.162739] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10898 06:54:57.651021 <6>[ 18.163406] videodev: Linux video capture interface: v2.00
10899 06:54:57.660999 <6>[ 18.165150] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10900 06:54:57.667635 <6>[ 18.167357] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10901 06:54:57.674713 <6>[ 18.169611] pci 0000:00:00.0: PCI bridge to [bus 01]
10902 06:54:57.680958 <3>[ 18.178028] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10903 06:54:57.688404 <6>[ 18.184124] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10904 06:54:57.698477 <3>[ 18.191605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10905 06:54:57.701686 <6>[ 18.192473] Bluetooth: Core ver 2.22
10906 06:54:57.708402 <6>[ 18.192604] NET: Registered PF_BLUETOOTH protocol family
10907 06:54:57.715067 <6>[ 18.192610] Bluetooth: HCI device and connection manager initialized
10908 06:54:57.718023 <6>[ 18.192637] Bluetooth: HCI socket layer initialized
10909 06:54:57.724579 <6>[ 18.192645] Bluetooth: L2CAP socket layer initialized
10910 06:54:57.728025 <6>[ 18.192658] Bluetooth: SCO socket layer initialized
10911 06:54:57.735401 <6>[ 18.199299] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10912 06:54:57.742505 <3>[ 18.206530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10913 06:54:57.749235 <6>[ 18.221837] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10914 06:54:57.759223 <3>[ 18.224781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 06:54:57.765394 <3>[ 18.224792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 06:54:57.772120 <3>[ 18.224814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 06:54:57.778870 <6>[ 18.233193] r8152 2-1.3:1.0 eth0: v1.12.13
10918 06:54:57.785281 <6>[ 18.233465] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10919 06:54:57.791969 <6>[ 18.233510] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10920 06:54:57.801645 <6>[ 18.241828] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10921 06:54:57.808273 <6>[ 18.242116] usbcore: registered new interface driver btusb
10922 06:54:57.818577 <4>[ 18.245195] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10923 06:54:57.824833 <3>[ 18.245210] Bluetooth: hci0: Failed to load firmware file (-2)
10924 06:54:57.831541 <3>[ 18.245214] Bluetooth: hci0: Failed to set up firmware (-2)
10925 06:54:57.841768 <4>[ 18.245217] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10926 06:54:57.848415 <6>[ 18.249694] usbcore: registered new interface driver r8152
10927 06:54:57.854976 <6>[ 18.257693] usbcore: registered new interface driver uvcvideo
10928 06:54:57.859053 <6>[ 18.259164] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10929 06:54:57.869084 <5>[ 18.259508] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10930 06:54:57.875924 <5>[ 18.268553] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10931 06:54:57.881922 <5>[ 18.268790] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10932 06:54:57.892086 <4>[ 18.268853] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10933 06:54:57.898635 <6>[ 18.268860] cfg80211: failed to load regulatory.db
10934 06:54:57.902018 <6>[ 18.287992] usbcore: registered new interface driver cdc_ether
10935 06:54:57.912125 <3>[ 18.302846] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 06:54:57.918656 <6>[ 18.314168] usbcore: registered new interface driver r8153_ecm
10937 06:54:57.925399 <3>[ 18.331379] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10938 06:54:57.935058 <3>[ 18.358597] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 06:54:57.941649 <3>[ 18.359346] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10940 06:54:57.948849 <6>[ 18.361417] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10941 06:54:57.958418 <6>[ 18.366516] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10942 06:54:57.964888 <3>[ 18.394423] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 06:54:57.971623 <6>[ 18.402263] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10944 06:54:57.981675 <3>[ 18.431949] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 06:54:57.984994 <6>[ 18.460207] mt7921e 0000:01:00.0: ASIC revision: 79610010
10946 06:54:57.995133 <3>[ 18.482064] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 06:54:58.004914 <6>[ 18.577227] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10948 06:54:58.005221 <6>[ 18.577227]
10949 06:54:58.014581 <3>[ 18.606111] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 06:54:58.021122 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10951 06:54:58.042504 <3>[ 18.776410] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 06:54:58.137381 <6>[ 18.870529] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10953 06:54:58.177298 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10954 06:54:58.193637 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10955 06:54:58.209516 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10956 06:54:58.225332 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10957 06:54:58.244838 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10958 06:54:58.284758 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10959 06:54:58.302836 Starting [0;1;39mNetwork Name Resolution[0m...
10960 06:54:58.323465 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10961 06:54:58.338022 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10962 06:54:58.357643 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10963 06:54:58.376595 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10964 06:54:58.393504 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10965 06:54:58.417575 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10966 06:54:58.433216 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10967 06:54:58.449612 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10968 06:54:58.494158 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10969 06:54:58.524744 Starting [0;1;39mUser Login Management[0m...
10970 06:54:58.542577 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10971 06:54:58.559365 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10972 06:54:58.574528 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10973 06:54:58.593681 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10974 06:54:58.612869 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10975 06:54:58.646255 Starting [0;1;39mPermit User Sessions[0m...
10976 06:54:58.663989 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10977 06:54:58.682112 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10978 06:54:58.722835 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10979 06:54:58.743385 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10980 06:54:58.757606 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10981 06:54:58.773696 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10982 06:54:58.789687 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10983 06:54:58.846314 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10984 06:54:58.881188 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10985 06:54:58.927087
10986 06:54:58.927618
10987 06:54:58.930927 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10988 06:54:58.931493
10989 06:54:58.933958 debian-bullseye-arm64 login: root (automatic login)
10990 06:54:58.934416
10991 06:54:58.934768
10992 06:54:58.959337 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
10993 06:54:58.959831
10994 06:54:58.965229 The programs included with the Debian GNU/Linux system are free software;
10995 06:54:58.972226 the exact distribution terms for each program are described in the
10996 06:54:58.975287 individual files in /usr/share/doc/*/copyright.
10997 06:54:58.975698
10998 06:54:58.985694 Debian GNU/Linux comes with ABSOLUTELY NO WARR<6>[ 19.722014] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10999 06:54:58.989027 ANTY, to the extent
11000 06:54:58.989479 permitted by applicable law.
11001 06:54:58.990943 Matched prompt #10: / #
11003 06:54:58.991925 Setting prompt string to ['/ #']
11004 06:54:58.992432 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11006 06:54:58.993404 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11007 06:54:58.993834 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
11008 06:54:58.994175 Setting prompt string to ['/ #']
11009 06:54:58.994622 Forcing a shell prompt, looking for ['/ #']
11011 06:54:59.045491 / #
11012 06:54:59.046041 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11013 06:54:59.046441 Waiting using forced prompt support (timeout 00:02:30)
11014 06:54:59.052038
11015 06:54:59.052832 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11016 06:54:59.053314 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
11017 06:54:59.053777 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11018 06:54:59.054360 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
11019 06:54:59.054814 end: 2 depthcharge-action (duration 00:01:34) [common]
11020 06:54:59.055254 start: 3 lava-test-retry (timeout 00:05:00) [common]
11021 06:54:59.055681 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11022 06:54:59.056048 Using namespace: common
11024 06:54:59.157106 / # #
11025 06:54:59.157694 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11026 06:54:59.158184 <6>[ 19.800072] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11027 06:54:59.158521 <6>[ 19.808065] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11028 06:54:59.163090 #
11029 06:54:59.163924 Using /lava-12694812
11031 06:54:59.265095 / # export SHELL=/bin/sh
11032 06:54:59.271872 export SHELL=/bin/sh
11034 06:54:59.373452 / # . /lava-12694812/environment
11035 06:54:59.378851 . /lava-12694812/environment
11037 06:54:59.479465 / # /lava-12694812/bin/lava-test-runner /lava-12694812/0
11038 06:54:59.479631 Test shell timeout: 10s (minimum of the action and connection timeout)
11039 06:54:59.484959 /lava-12694812/bin/lava-test-runner /lava-12694812/0
11040 06:54:59.504993 + export TESTRUN_ID=0_cros-ec
11041 06:54:59.511506 +<8>[ 20.247626] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12694812_1.5.2.3.1>
11042 06:54:59.511781 Received signal: <STARTRUN> 0_cros-ec 12694812_1.5.2.3.1
11043 06:54:59.511858 Starting test lava.0_cros-ec (12694812_1.5.2.3.1)
11044 06:54:59.511944 Skipping test definition patterns.
11045 06:54:59.514924 cd /lava-12694812/0/tests/0_cros-ec
11046 06:54:59.517933 + cat uuid
11047 06:54:59.518017 + UUID=12694812_1.5.2.3.1
11048 06:54:59.518081 + set +x
11049 06:54:59.524479 + python3 -m cros.runners.lava_runner -v
11050 06:54:59.883724 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11051 06:54:59.890788 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11052 06:54:59.893951
11053 06:54:59.897219 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11055 06:54:59.900701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11056 06:54:59.907336 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11057 06:54:59.913764 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11058 06:54:59.913850
11059 06:54:59.920861 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8
11060 06:54:59.920973 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_accel_iio_data_is_<8', 'result': 'unknown'}
11061 06:54:59.927383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8>[ 20.663162] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12694812_1.5.2.3.1>
11062 06:54:59.927643 Received signal: <ENDRUN> 0_cros-ec 12694812_1.5.2.3.1
11063 06:54:59.927725 Ending use of test pattern.
11064 06:54:59.927786 Ending test lava.0_cros-ec (12694812_1.5.2.3.1), duration 0.42
11066 06:54:59.930698 valid RESULT=skip>
11067 06:54:59.933967 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11068 06:54:59.940376 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11069 06:54:59.940459
11070 06:54:59.946809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11071 06:54:59.947070 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11073 06:54:59.953886 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11074 06:54:59.960434 Checks the standard ABI for the main Embedded Controller. ... ok
11075 06:54:59.960518
11076 06:54:59.963769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11077 06:54:59.964024 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11079 06:54:59.970233 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11080 06:54:59.977118 Checks the main Embedded controller character device. ... ok
11081 06:54:59.977202
11082 06:54:59.980426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11083 06:54:59.980681 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11085 06:54:59.987049 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11086 06:54:59.993559 Checks basic comunication with the main Embedded controller. ... ok
11087 06:54:59.993719
11088 06:55:00.000836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11089 06:55:00.001180 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11091 06:55:00.003306 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11092 06:55:00.009771 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11093 06:55:00.013697
11094 06:55:00.016802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11095 06:55:00.017147 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11097 06:55:00.023511 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11098 06:55:00.029875 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11099 06:55:00.030046
11100 06:55:00.036406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11101 06:55:00.036793 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11103 06:55:00.043218 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11104 06:55:00.050388 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11105 06:55:00.050637
11106 06:55:00.056724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11107 06:55:00.057228 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11109 06:55:00.059725 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11110 06:55:00.069946 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11111 06:55:00.070340
11112 06:55:00.073141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11113 06:55:00.073938 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11115 06:55:00.079600 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11116 06:55:00.086550 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11117 06:55:00.089986
11118 06:55:00.093081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11119 06:55:00.093760 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11121 06:55:00.099619 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11122 06:55:00.106156 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11123 06:55:00.106665
11124 06:55:00.112704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11125 06:55:00.113387 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11127 06:55:00.115998 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11128 06:55:00.126522 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11129 06:55:00.127045
11130 06:55:00.132888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11131 06:55:00.133666 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11133 06:55:00.136103 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11134 06:55:00.145975 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11135 06:55:00.146475
11136 06:55:00.152611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11137 06:55:00.153462 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11139 06:55:00.159728 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11140 06:55:00.162705 Check the cros battery ABI. ... skipped 'No BAT found'
11141 06:55:00.165953
11142 06:55:00.168877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11143 06:55:00.169557 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11145 06:55:00.175579 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11146 06:55:00.182186 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11147 06:55:00.182612
11148 06:55:00.192420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11149 06:55:00.193281 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11151 06:55:00.195655 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11152 06:55:00.202407 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11153 06:55:00.202830
11154 06:55:00.208802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11155 06:55:00.209374 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11157 06:55:00.215263 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11158 06:55:00.221650 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11159 06:55:00.221858
11160 06:55:00.228219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11161 06:55:00.228401
11162 06:55:00.228698 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11164 06:55:00.234824 ----------------------------------------------------------------------
11165 06:55:00.238080 Ran 18 tests in 0.007s
11166 06:55:00.238199
11167 06:55:00.238280 OK (skipped=15)
11168 06:55:00.238357 + set +x
11169 06:55:00.241452 <LAVA_TEST_RUNNER EXIT>
11170 06:55:00.241724 ok: lava_test_shell seems to have completed
11171 06:55:00.241918 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11172 06:55:00.242028 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11173 06:55:00.242123 end: 3 lava-test-retry (duration 00:00:01) [common]
11174 06:55:00.242221 start: 4 finalize (timeout 00:08:03) [common]
11175 06:55:00.242320 start: 4.1 power-off (timeout 00:00:30) [common]
11176 06:55:00.242485 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11177 06:55:00.319696 >> Command sent successfully.
11178 06:55:00.324074 Returned 0 in 0 seconds
11179 06:55:00.424919 end: 4.1 power-off (duration 00:00:00) [common]
11181 06:55:00.426323 start: 4.2 read-feedback (timeout 00:08:02) [common]
11182 06:55:00.427479 Listened to connection for namespace 'common' for up to 1s
11183 06:55:01.428194 Finalising connection for namespace 'common'
11184 06:55:01.428898 Disconnecting from shell: Finalise
11185 06:55:01.429311 / #
11186 06:55:01.530393 end: 4.2 read-feedback (duration 00:00:01) [common]
11187 06:55:01.531011 end: 4 finalize (duration 00:00:01) [common]
11188 06:55:01.531569 Cleaning after the job
11189 06:55:01.532034 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/ramdisk
11190 06:55:01.560621 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/kernel
11191 06:55:01.578941 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/dtb
11192 06:55:01.579200 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694812/tftp-deploy-j7wt1w4y/modules
11193 06:55:01.588869 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694812
11194 06:55:01.714653 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694812
11195 06:55:01.714827 Job finished correctly