Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 16
- Kernel Errors: 35
1 06:51:15.918603 lava-dispatcher, installed at version: 2023.10
2 06:51:15.918809 start: 0 validate
3 06:51:15.918949 Start time: 2024-02-03 06:51:15.918941+00:00 (UTC)
4 06:51:15.919070 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:51:15.919202 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 06:51:16.194399 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:51:16.195160 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:51:16.466630 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:51:16.467461 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:51:16.731606 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:51:16.732402 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 06:51:17.003009 validate duration: 1.08
14 06:51:17.004398 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:51:17.005000 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:51:17.005515 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:51:17.006144 Not decompressing ramdisk as can be used compressed.
18 06:51:17.006629 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 06:51:17.007023 saving as /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/ramdisk/rootfs.cpio.gz
20 06:51:17.007392 total size: 43284872 (41 MB)
21 06:51:17.013481 progress 0 % (0 MB)
22 06:51:17.050382 progress 5 % (2 MB)
23 06:51:17.065669 progress 10 % (4 MB)
24 06:51:17.077633 progress 15 % (6 MB)
25 06:51:17.088894 progress 20 % (8 MB)
26 06:51:17.099926 progress 25 % (10 MB)
27 06:51:17.111244 progress 30 % (12 MB)
28 06:51:17.122379 progress 35 % (14 MB)
29 06:51:17.133630 progress 40 % (16 MB)
30 06:51:17.144828 progress 45 % (18 MB)
31 06:51:17.156244 progress 50 % (20 MB)
32 06:51:17.167471 progress 55 % (22 MB)
33 06:51:17.178847 progress 60 % (24 MB)
34 06:51:17.190082 progress 65 % (26 MB)
35 06:51:17.201514 progress 70 % (28 MB)
36 06:51:17.212887 progress 75 % (30 MB)
37 06:51:17.224237 progress 80 % (33 MB)
38 06:51:17.235400 progress 85 % (35 MB)
39 06:51:17.246483 progress 90 % (37 MB)
40 06:51:17.257382 progress 95 % (39 MB)
41 06:51:17.268152 progress 100 % (41 MB)
42 06:51:17.268396 41 MB downloaded in 0.26 s (158.14 MB/s)
43 06:51:17.268557 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:51:17.268847 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:51:17.268934 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:51:17.269019 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:51:17.269167 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 06:51:17.269237 saving as /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/kernel/Image
50 06:51:17.269302 total size: 51532288 (49 MB)
51 06:51:17.269364 No compression specified
52 06:51:17.270608 progress 0 % (0 MB)
53 06:51:17.284427 progress 5 % (2 MB)
54 06:51:17.297797 progress 10 % (4 MB)
55 06:51:17.311271 progress 15 % (7 MB)
56 06:51:17.324646 progress 20 % (9 MB)
57 06:51:17.338062 progress 25 % (12 MB)
58 06:51:17.351403 progress 30 % (14 MB)
59 06:51:17.364891 progress 35 % (17 MB)
60 06:51:17.378512 progress 40 % (19 MB)
61 06:51:17.391852 progress 45 % (22 MB)
62 06:51:17.405425 progress 50 % (24 MB)
63 06:51:17.418775 progress 55 % (27 MB)
64 06:51:17.432311 progress 60 % (29 MB)
65 06:51:17.445708 progress 65 % (31 MB)
66 06:51:17.459052 progress 70 % (34 MB)
67 06:51:17.472439 progress 75 % (36 MB)
68 06:51:17.485878 progress 80 % (39 MB)
69 06:51:17.499270 progress 85 % (41 MB)
70 06:51:17.512585 progress 90 % (44 MB)
71 06:51:17.525678 progress 95 % (46 MB)
72 06:51:17.538647 progress 100 % (49 MB)
73 06:51:17.538847 49 MB downloaded in 0.27 s (182.33 MB/s)
74 06:51:17.538996 end: 1.2.1 http-download (duration 00:00:00) [common]
76 06:51:17.539221 end: 1.2 download-retry (duration 00:00:00) [common]
77 06:51:17.539311 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:51:17.539396 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:51:17.539532 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 06:51:17.539604 saving as /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/dtb/mt8192-asurada-spherion-r0.dtb
81 06:51:17.539665 total size: 47278 (0 MB)
82 06:51:17.539726 No compression specified
83 06:51:17.540921 progress 69 % (0 MB)
84 06:51:17.541192 progress 100 % (0 MB)
85 06:51:17.541346 0 MB downloaded in 0.00 s (26.87 MB/s)
86 06:51:17.541469 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:51:17.541687 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:51:17.541771 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:51:17.541856 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:51:17.541970 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 06:51:17.542037 saving as /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/modules/modules.tar
93 06:51:17.542097 total size: 8624064 (8 MB)
94 06:51:17.542158 Using unxz to decompress xz
95 06:51:17.546379 progress 0 % (0 MB)
96 06:51:17.567053 progress 5 % (0 MB)
97 06:51:17.590448 progress 10 % (0 MB)
98 06:51:17.613523 progress 15 % (1 MB)
99 06:51:17.636609 progress 20 % (1 MB)
100 06:51:17.660759 progress 25 % (2 MB)
101 06:51:17.686529 progress 30 % (2 MB)
102 06:51:17.712656 progress 35 % (2 MB)
103 06:51:17.735975 progress 40 % (3 MB)
104 06:51:17.760021 progress 45 % (3 MB)
105 06:51:17.784856 progress 50 % (4 MB)
106 06:51:17.809012 progress 55 % (4 MB)
107 06:51:17.833435 progress 60 % (4 MB)
108 06:51:17.860597 progress 65 % (5 MB)
109 06:51:17.885123 progress 70 % (5 MB)
110 06:51:17.908332 progress 75 % (6 MB)
111 06:51:17.935346 progress 80 % (6 MB)
112 06:51:17.960673 progress 85 % (7 MB)
113 06:51:17.985312 progress 90 % (7 MB)
114 06:51:18.016397 progress 95 % (7 MB)
115 06:51:18.044136 progress 100 % (8 MB)
116 06:51:18.049072 8 MB downloaded in 0.51 s (16.22 MB/s)
117 06:51:18.049325 end: 1.4.1 http-download (duration 00:00:01) [common]
119 06:51:18.049593 end: 1.4 download-retry (duration 00:00:01) [common]
120 06:51:18.049686 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 06:51:18.049785 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 06:51:18.049866 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:51:18.049950 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 06:51:18.050177 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw
125 06:51:18.050316 makedir: /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin
126 06:51:18.050424 makedir: /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/tests
127 06:51:18.050524 makedir: /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/results
128 06:51:18.050648 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-add-keys
129 06:51:18.050800 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-add-sources
130 06:51:18.051034 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-background-process-start
131 06:51:18.051170 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-background-process-stop
132 06:51:18.051301 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-common-functions
133 06:51:18.051429 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-echo-ipv4
134 06:51:18.051557 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-install-packages
135 06:51:18.051685 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-installed-packages
136 06:51:18.051811 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-os-build
137 06:51:18.051938 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-probe-channel
138 06:51:18.052067 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-probe-ip
139 06:51:18.052194 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-target-ip
140 06:51:18.052322 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-target-mac
141 06:51:18.052448 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-target-storage
142 06:51:18.052580 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-test-case
143 06:51:18.052713 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-test-event
144 06:51:18.052912 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-test-feedback
145 06:51:18.053078 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-test-raise
146 06:51:18.053210 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-test-reference
147 06:51:18.053338 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-test-runner
148 06:51:18.053467 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-test-set
149 06:51:18.053596 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-test-shell
150 06:51:18.053728 Updating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-install-packages (oe)
151 06:51:18.053884 Updating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/bin/lava-installed-packages (oe)
152 06:51:18.054009 Creating /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/environment
153 06:51:18.054112 LAVA metadata
154 06:51:18.054187 - LAVA_JOB_ID=12694836
155 06:51:18.054253 - LAVA_DISPATCHER_IP=192.168.201.1
156 06:51:18.054358 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 06:51:18.054426 skipped lava-vland-overlay
158 06:51:18.054500 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 06:51:18.054582 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 06:51:18.054648 skipped lava-multinode-overlay
161 06:51:18.054721 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 06:51:18.054806 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 06:51:18.054879 Loading test definitions
164 06:51:18.054973 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 06:51:18.055069 Using /lava-12694836 at stage 0
166 06:51:18.055384 uuid=12694836_1.5.2.3.1 testdef=None
167 06:51:18.055472 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 06:51:18.055556 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 06:51:18.056087 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 06:51:18.056307 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 06:51:18.056925 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 06:51:18.057211 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 06:51:18.058242 runner path: /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/0/tests/0_igt-gpu-panfrost test_uuid 12694836_1.5.2.3.1
176 06:51:18.058403 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 06:51:18.058614 Creating lava-test-runner.conf files
179 06:51:18.058678 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694836/lava-overlay-lmj4kvbw/lava-12694836/0 for stage 0
180 06:51:18.058767 - 0_igt-gpu-panfrost
181 06:51:18.058864 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 06:51:18.058947 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 06:51:18.065637 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 06:51:18.065741 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 06:51:18.065829 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 06:51:18.065913 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 06:51:18.066003 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 06:51:19.454955 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 06:51:19.455348 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 06:51:19.455460 extracting modules file /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694836/extract-overlay-ramdisk-4qvv1jqe/ramdisk
191 06:51:19.681923 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 06:51:19.682092 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 06:51:19.682187 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694836/compress-overlay-ww9nh0q1/overlay-1.5.2.4.tar.gz to ramdisk
194 06:51:19.682259 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694836/compress-overlay-ww9nh0q1/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694836/extract-overlay-ramdisk-4qvv1jqe/ramdisk
195 06:51:19.688698 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 06:51:19.688852 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 06:51:19.688940 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 06:51:19.689026 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 06:51:19.689101 Building ramdisk /var/lib/lava/dispatcher/tmp/12694836/extract-overlay-ramdisk-4qvv1jqe/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694836/extract-overlay-ramdisk-4qvv1jqe/ramdisk
200 06:51:20.769572 >> 370008 blocks
201 06:51:26.464311 rename /var/lib/lava/dispatcher/tmp/12694836/extract-overlay-ramdisk-4qvv1jqe/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/ramdisk/ramdisk.cpio.gz
202 06:51:26.464812 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 06:51:26.464939 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 06:51:26.465039 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 06:51:26.465151 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/kernel/Image'
206 06:51:38.682934 Returned 0 in 12 seconds
207 06:51:38.784058 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/kernel/image.itb
208 06:51:39.649049 output: FIT description: Kernel Image image with one or more FDT blobs
209 06:51:39.649418 output: Created: Sat Feb 3 06:51:39 2024
210 06:51:39.649492 output: Image 0 (kernel-1)
211 06:51:39.649556 output: Description:
212 06:51:39.649615 output: Created: Sat Feb 3 06:51:39 2024
213 06:51:39.649715 output: Type: Kernel Image
214 06:51:39.649776 output: Compression: lzma compressed
215 06:51:39.649837 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
216 06:51:39.649898 output: Architecture: AArch64
217 06:51:39.649958 output: OS: Linux
218 06:51:39.650016 output: Load Address: 0x00000000
219 06:51:39.650077 output: Entry Point: 0x00000000
220 06:51:39.650137 output: Hash algo: crc32
221 06:51:39.650196 output: Hash value: 380e7c3c
222 06:51:39.650253 output: Image 1 (fdt-1)
223 06:51:39.650309 output: Description: mt8192-asurada-spherion-r0
224 06:51:39.650362 output: Created: Sat Feb 3 06:51:39 2024
225 06:51:39.650415 output: Type: Flat Device Tree
226 06:51:39.650468 output: Compression: uncompressed
227 06:51:39.650520 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 06:51:39.650573 output: Architecture: AArch64
229 06:51:39.650624 output: Hash algo: crc32
230 06:51:39.650676 output: Hash value: cc4352de
231 06:51:39.650728 output: Image 2 (ramdisk-1)
232 06:51:39.650781 output: Description: unavailable
233 06:51:39.650833 output: Created: Sat Feb 3 06:51:39 2024
234 06:51:39.650885 output: Type: RAMDisk Image
235 06:51:39.650937 output: Compression: Unknown Compression
236 06:51:39.650989 output: Data Size: 56431790 Bytes = 55109.17 KiB = 53.82 MiB
237 06:51:39.651042 output: Architecture: AArch64
238 06:51:39.651094 output: OS: Linux
239 06:51:39.651146 output: Load Address: unavailable
240 06:51:39.651198 output: Entry Point: unavailable
241 06:51:39.651250 output: Hash algo: crc32
242 06:51:39.651302 output: Hash value: 88a1f52d
243 06:51:39.651354 output: Default Configuration: 'conf-1'
244 06:51:39.651406 output: Configuration 0 (conf-1)
245 06:51:39.651458 output: Description: mt8192-asurada-spherion-r0
246 06:51:39.651510 output: Kernel: kernel-1
247 06:51:39.651562 output: Init Ramdisk: ramdisk-1
248 06:51:39.651613 output: FDT: fdt-1
249 06:51:39.651665 output: Loadables: kernel-1
250 06:51:39.651718 output:
251 06:51:39.651914 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 06:51:39.652008 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 06:51:39.652109 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 06:51:39.652203 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 06:51:39.652287 No LXC device requested
256 06:51:39.652366 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 06:51:39.652449 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 06:51:39.652526 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 06:51:39.652594 Checking files for TFTP limit of 4294967296 bytes.
260 06:51:39.653146 end: 1 tftp-deploy (duration 00:00:23) [common]
261 06:51:39.653254 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 06:51:39.653344 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 06:51:39.653465 substitutions:
264 06:51:39.653531 - {DTB}: 12694836/tftp-deploy-8v56v5jm/dtb/mt8192-asurada-spherion-r0.dtb
265 06:51:39.653595 - {INITRD}: 12694836/tftp-deploy-8v56v5jm/ramdisk/ramdisk.cpio.gz
266 06:51:39.653654 - {KERNEL}: 12694836/tftp-deploy-8v56v5jm/kernel/Image
267 06:51:39.653712 - {LAVA_MAC}: None
268 06:51:39.653768 - {PRESEED_CONFIG}: None
269 06:51:39.653823 - {PRESEED_LOCAL}: None
270 06:51:39.653877 - {RAMDISK}: 12694836/tftp-deploy-8v56v5jm/ramdisk/ramdisk.cpio.gz
271 06:51:39.653931 - {ROOT_PART}: None
272 06:51:39.653985 - {ROOT}: None
273 06:51:39.654038 - {SERVER_IP}: 192.168.201.1
274 06:51:39.654091 - {TEE}: None
275 06:51:39.654144 Parsed boot commands:
276 06:51:39.654197 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 06:51:39.654376 Parsed boot commands: tftpboot 192.168.201.1 12694836/tftp-deploy-8v56v5jm/kernel/image.itb 12694836/tftp-deploy-8v56v5jm/kernel/cmdline
278 06:51:39.654467 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 06:51:39.654553 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 06:51:39.654648 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 06:51:39.654737 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 06:51:39.654808 Not connected, no need to disconnect.
283 06:51:39.654882 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 06:51:39.654963 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 06:51:39.655030 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 06:51:39.659017 Setting prompt string to ['lava-test: # ']
287 06:51:39.659378 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 06:51:39.659487 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 06:51:39.659582 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 06:51:39.659713 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 06:51:39.659945 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 06:51:44.801389 >> Command sent successfully.
293 06:51:44.812952 Returned 0 in 5 seconds
294 06:51:44.914112 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 06:51:44.915644 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 06:51:44.916148 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 06:51:44.916666 Setting prompt string to 'Starting depthcharge on Spherion...'
299 06:51:44.916990 Changing prompt to 'Starting depthcharge on Spherion...'
300 06:51:44.917208 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 06:51:44.917917 [Enter `^Ec?' for help]
302 06:51:45.086374
303 06:51:45.086995
304 06:51:45.087498 F0: 102B 0000
305 06:51:45.087857
306 06:51:45.088175 F3: 1001 0000 [0200]
307 06:51:45.089681
308 06:51:45.090151 F3: 1001 0000
309 06:51:45.090497
310 06:51:45.090816 F7: 102D 0000
311 06:51:45.091123
312 06:51:45.092955 F1: 0000 0000
313 06:51:45.093395
314 06:51:45.093756 V0: 0000 0000 [0001]
315 06:51:45.094083
316 06:51:45.094394 00: 0007 8000
317 06:51:45.097621
318 06:51:45.098056 01: 0000 0000
319 06:51:45.098409
320 06:51:45.098731 BP: 0C00 0209 [0000]
321 06:51:45.099041
322 06:51:45.100511 G0: 1182 0000
323 06:51:45.100979
324 06:51:45.101324 EC: 0000 0021 [4000]
325 06:51:45.101646
326 06:51:45.104263 S7: 0000 0000 [0000]
327 06:51:45.104699
328 06:51:45.105102 CC: 0000 0000 [0001]
329 06:51:45.105425
330 06:51:45.108457 T0: 0000 0040 [010F]
331 06:51:45.108935
332 06:51:45.109282 Jump to BL
333 06:51:45.109606
334 06:51:45.133334
335 06:51:45.133900
336 06:51:45.134253
337 06:51:45.140452 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 06:51:45.145051 ARM64: Exception handlers installed.
339 06:51:45.147536 ARM64: Testing exception
340 06:51:45.151267 ARM64: Done test exception
341 06:51:45.157670 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 06:51:45.167444 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 06:51:45.175092 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 06:51:45.185107 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 06:51:45.192113 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 06:51:45.198018 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 06:51:45.209854 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 06:51:45.216537 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 06:51:45.236083 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 06:51:45.239488 WDT: Last reset was cold boot
351 06:51:45.243647 SPI1(PAD0) initialized at 2873684 Hz
352 06:51:45.246208 SPI5(PAD0) initialized at 992727 Hz
353 06:51:45.249846 VBOOT: Loading verstage.
354 06:51:45.256172 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 06:51:45.260350 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 06:51:45.262719 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 06:51:45.265981 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 06:51:45.273684 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 06:51:45.280353 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 06:51:45.291393 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 06:51:45.291975
362 06:51:45.292353
363 06:51:45.301299 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 06:51:45.304348 ARM64: Exception handlers installed.
365 06:51:45.307733 ARM64: Testing exception
366 06:51:45.308228 ARM64: Done test exception
367 06:51:45.314321 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 06:51:45.318760 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 06:51:45.332521 Probing TPM: . done!
370 06:51:45.333176 TPM ready after 0 ms
371 06:51:45.339390 Connected to device vid:did:rid of 1ae0:0028:00
372 06:51:45.345635 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 06:51:45.350658 Initialized TPM device CR50 revision 0
374 06:51:45.399468 tlcl_send_startup: Startup return code is 0
375 06:51:45.400016 TPM: setup succeeded
376 06:51:45.411743 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 06:51:45.419965 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 06:51:45.430347 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 06:51:45.439747 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 06:51:45.442372 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 06:51:45.446603 in-header: 03 07 00 00 08 00 00 00
382 06:51:45.449373 in-data: aa e4 47 04 13 02 00 00
383 06:51:45.452741 Chrome EC: UHEPI supported
384 06:51:45.459334 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 06:51:45.462332 in-header: 03 9d 00 00 08 00 00 00
386 06:51:45.466301 in-data: 10 20 20 08 00 00 00 00
387 06:51:45.466893 Phase 1
388 06:51:45.469329 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 06:51:45.476575 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 06:51:45.482622 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 06:51:45.486731 Recovery requested (1009000e)
392 06:51:45.489454 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 06:51:45.497861 tlcl_extend: response is 0
394 06:51:45.505637 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 06:51:45.511226 tlcl_extend: response is 0
396 06:51:45.518318 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 06:51:45.538871 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 06:51:45.545497 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 06:51:45.546035
400 06:51:45.546413
401 06:51:45.555471 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 06:51:45.558508 ARM64: Exception handlers installed.
403 06:51:45.561825 ARM64: Testing exception
404 06:51:45.562301 ARM64: Done test exception
405 06:51:45.585885 pmic_efuse_setting: Set efuses in 11 msecs
406 06:51:45.588383 pmwrap_interface_init: Select PMIF_VLD_RDY
407 06:51:45.595132 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 06:51:45.598184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 06:51:45.602053 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 06:51:45.609531 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 06:51:45.612410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 06:51:45.616068 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 06:51:45.623497 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 06:51:45.626730 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 06:51:45.632890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 06:51:45.636793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 06:51:45.639948 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 06:51:45.646878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 06:51:45.649918 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 06:51:45.656296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 06:51:45.663973 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 06:51:45.666487 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 06:51:45.673191 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 06:51:45.680811 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 06:51:45.684244 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 06:51:45.690792 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 06:51:45.694350 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 06:51:45.700776 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 06:51:45.707810 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 06:51:45.711160 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 06:51:45.718099 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 06:51:45.724508 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 06:51:45.728177 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 06:51:45.734634 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 06:51:45.737406 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 06:51:45.744317 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 06:51:45.748893 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 06:51:45.754187 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 06:51:45.757811 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 06:51:45.764321 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 06:51:45.767518 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 06:51:45.774027 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 06:51:45.777995 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 06:51:45.785041 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 06:51:45.787520 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 06:51:45.791222 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 06:51:45.797763 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 06:51:45.800874 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 06:51:45.804118 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 06:51:45.810654 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 06:51:45.815328 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 06:51:45.817934 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 06:51:45.820529 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 06:51:45.827367 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 06:51:45.831380 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 06:51:45.834260 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 06:51:45.837525 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 06:51:45.847371 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 06:51:45.854585 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 06:51:45.861080 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 06:51:45.868118 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 06:51:45.877112 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 06:51:45.880878 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 06:51:45.887098 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 06:51:45.890419 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 06:51:45.897464 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
467 06:51:45.903997 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 06:51:45.906943 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 06:51:45.910785 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 06:51:45.921191 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 06:51:45.931111 [RTC]rtc_get_frequency_meter,154: input=23, output=950
472 06:51:45.939935 [RTC]rtc_get_frequency_meter,154: input=19, output=857
473 06:51:45.949794 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 06:51:45.959933 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 06:51:45.969495 [RTC]rtc_get_frequency_meter,154: input=16, output=788
476 06:51:45.979207 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 06:51:45.982038 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 06:51:45.988931 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 06:51:45.992520 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 06:51:45.995796 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 06:51:46.002513 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 06:51:46.005467 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 06:51:46.009874 ADC[4]: Raw value=670063 ID=5
484 06:51:46.010349 ADC[3]: Raw value=212917 ID=1
485 06:51:46.012313 RAM Code: 0x51
486 06:51:46.015631 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 06:51:46.022618 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 06:51:46.029218 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 06:51:46.036043 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 06:51:46.039419 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 06:51:46.043175 in-header: 03 07 00 00 08 00 00 00
492 06:51:46.046001 in-data: aa e4 47 04 13 02 00 00
493 06:51:46.049272 Chrome EC: UHEPI supported
494 06:51:46.056050 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 06:51:46.058591 in-header: 03 d5 00 00 08 00 00 00
496 06:51:46.062339 in-data: 98 20 60 08 00 00 00 00
497 06:51:46.066827 MRC: failed to locate region type 0.
498 06:51:46.072036 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 06:51:46.075749 DRAM-K: Running full calibration
500 06:51:46.079615 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 06:51:46.082292 header.status = 0x0
502 06:51:46.086781 header.version = 0x6 (expected: 0x6)
503 06:51:46.088843 header.size = 0xd00 (expected: 0xd00)
504 06:51:46.089402 header.flags = 0x0
505 06:51:46.096344 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 06:51:46.114057 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 06:51:46.120833 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 06:51:46.124131 dram_init: ddr_geometry: 0
509 06:51:46.124612 [EMI] MDL number = 0
510 06:51:46.127944 [EMI] Get MDL freq = 0
511 06:51:46.130976 dram_init: ddr_type: 0
512 06:51:46.131558 is_discrete_lpddr4: 1
513 06:51:46.134856 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 06:51:46.135455
515 06:51:46.135874
516 06:51:46.137947 [Bian_co] ETT version 0.0.0.1
517 06:51:46.144803 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 06:51:46.145301
519 06:51:46.147572 dramc_set_vcore_voltage set vcore to 650000
520 06:51:46.148052 Read voltage for 800, 4
521 06:51:46.151701 Vio18 = 0
522 06:51:46.152240 Vcore = 650000
523 06:51:46.152594 Vdram = 0
524 06:51:46.154008 Vddq = 0
525 06:51:46.154441 Vmddr = 0
526 06:51:46.158396 dram_init: config_dvfs: 1
527 06:51:46.161096 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 06:51:46.168001 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 06:51:46.171035 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 06:51:46.174785 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 06:51:46.177869 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 06:51:46.180860 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 06:51:46.184119 MEM_TYPE=3, freq_sel=18
534 06:51:46.187796 sv_algorithm_assistance_LP4_1600
535 06:51:46.191263 ============ PULL DRAM RESETB DOWN ============
536 06:51:46.194762 ========== PULL DRAM RESETB DOWN end =========
537 06:51:46.201436 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 06:51:46.204767 ===================================
539 06:51:46.205370 LPDDR4 DRAM CONFIGURATION
540 06:51:46.208697 ===================================
541 06:51:46.211469 EX_ROW_EN[0] = 0x0
542 06:51:46.214505 EX_ROW_EN[1] = 0x0
543 06:51:46.215049 LP4Y_EN = 0x0
544 06:51:46.217743 WORK_FSP = 0x0
545 06:51:46.218195 WL = 0x2
546 06:51:46.221195 RL = 0x2
547 06:51:46.221629 BL = 0x2
548 06:51:46.224322 RPST = 0x0
549 06:51:46.224818 RD_PRE = 0x0
550 06:51:46.228552 WR_PRE = 0x1
551 06:51:46.229218 WR_PST = 0x0
552 06:51:46.231253 DBI_WR = 0x0
553 06:51:46.231843 DBI_RD = 0x0
554 06:51:46.234420 OTF = 0x1
555 06:51:46.237748 ===================================
556 06:51:46.241007 ===================================
557 06:51:46.241492 ANA top config
558 06:51:46.244442 ===================================
559 06:51:46.247936 DLL_ASYNC_EN = 0
560 06:51:46.251372 ALL_SLAVE_EN = 1
561 06:51:46.251964 NEW_RANK_MODE = 1
562 06:51:46.254918 DLL_IDLE_MODE = 1
563 06:51:46.257854 LP45_APHY_COMB_EN = 1
564 06:51:46.261233 TX_ODT_DIS = 1
565 06:51:46.264693 NEW_8X_MODE = 1
566 06:51:46.267879 ===================================
567 06:51:46.272613 ===================================
568 06:51:46.273360 data_rate = 1600
569 06:51:46.274493 CKR = 1
570 06:51:46.278113 DQ_P2S_RATIO = 8
571 06:51:46.281554 ===================================
572 06:51:46.284427 CA_P2S_RATIO = 8
573 06:51:46.287482 DQ_CA_OPEN = 0
574 06:51:46.291181 DQ_SEMI_OPEN = 0
575 06:51:46.291661 CA_SEMI_OPEN = 0
576 06:51:46.294527 CA_FULL_RATE = 0
577 06:51:46.297705 DQ_CKDIV4_EN = 1
578 06:51:46.301232 CA_CKDIV4_EN = 1
579 06:51:46.304228 CA_PREDIV_EN = 0
580 06:51:46.307767 PH8_DLY = 0
581 06:51:46.308205 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 06:51:46.311038 DQ_AAMCK_DIV = 4
583 06:51:46.314219 CA_AAMCK_DIV = 4
584 06:51:46.317968 CA_ADMCK_DIV = 4
585 06:51:46.321535 DQ_TRACK_CA_EN = 0
586 06:51:46.324665 CA_PICK = 800
587 06:51:46.325350 CA_MCKIO = 800
588 06:51:46.328102 MCKIO_SEMI = 0
589 06:51:46.331157 PLL_FREQ = 3068
590 06:51:46.334597 DQ_UI_PI_RATIO = 32
591 06:51:46.337952 CA_UI_PI_RATIO = 0
592 06:51:46.341212 ===================================
593 06:51:46.344677 ===================================
594 06:51:46.348673 memory_type:LPDDR4
595 06:51:46.349412 GP_NUM : 10
596 06:51:46.351832 SRAM_EN : 1
597 06:51:46.352437 MD32_EN : 0
598 06:51:46.354082 ===================================
599 06:51:46.357615 [ANA_INIT] >>>>>>>>>>>>>>
600 06:51:46.361480 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 06:51:46.364870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 06:51:46.367934 ===================================
603 06:51:46.371463 data_rate = 1600,PCW = 0X7600
604 06:51:46.374210 ===================================
605 06:51:46.377820 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 06:51:46.381296 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 06:51:46.388040 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 06:51:46.391017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 06:51:46.399124 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 06:51:46.400969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 06:51:46.401410 [ANA_INIT] flow start
612 06:51:46.404115 [ANA_INIT] PLL >>>>>>>>
613 06:51:46.404549 [ANA_INIT] PLL <<<<<<<<
614 06:51:46.407810 [ANA_INIT] MIDPI >>>>>>>>
615 06:51:46.410944 [ANA_INIT] MIDPI <<<<<<<<
616 06:51:46.414067 [ANA_INIT] DLL >>>>>>>>
617 06:51:46.414615 [ANA_INIT] flow end
618 06:51:46.417469 ============ LP4 DIFF to SE enter ============
619 06:51:46.424935 ============ LP4 DIFF to SE exit ============
620 06:51:46.425485 [ANA_INIT] <<<<<<<<<<<<<
621 06:51:46.427726 [Flow] Enable top DCM control >>>>>
622 06:51:46.431224 [Flow] Enable top DCM control <<<<<
623 06:51:46.434734 Enable DLL master slave shuffle
624 06:51:46.440933 ==============================================================
625 06:51:46.441482 Gating Mode config
626 06:51:46.448362 ==============================================================
627 06:51:46.452076 Config description:
628 06:51:46.461270 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 06:51:46.468875 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 06:51:46.471743 SELPH_MODE 0: By rank 1: By Phase
631 06:51:46.478187 ==============================================================
632 06:51:46.481078 GAT_TRACK_EN = 1
633 06:51:46.481780 RX_GATING_MODE = 2
634 06:51:46.485007 RX_GATING_TRACK_MODE = 2
635 06:51:46.487417 SELPH_MODE = 1
636 06:51:46.490995 PICG_EARLY_EN = 1
637 06:51:46.494389 VALID_LAT_VALUE = 1
638 06:51:46.501314 ==============================================================
639 06:51:46.504380 Enter into Gating configuration >>>>
640 06:51:46.507816 Exit from Gating configuration <<<<
641 06:51:46.511836 Enter into DVFS_PRE_config >>>>>
642 06:51:46.520999 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 06:51:46.524278 Exit from DVFS_PRE_config <<<<<
644 06:51:46.527894 Enter into PICG configuration >>>>
645 06:51:46.531470 Exit from PICG configuration <<<<
646 06:51:46.535598 [RX_INPUT] configuration >>>>>
647 06:51:46.536129 [RX_INPUT] configuration <<<<<
648 06:51:46.541082 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 06:51:46.547679 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 06:51:46.551637 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 06:51:46.557720 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 06:51:46.564428 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 06:51:46.571180 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 06:51:46.574636 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 06:51:46.578082 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 06:51:46.584206 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 06:51:46.587378 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 06:51:46.592020 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 06:51:46.599094 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 06:51:46.600749 ===================================
661 06:51:46.601187 LPDDR4 DRAM CONFIGURATION
662 06:51:46.604639 ===================================
663 06:51:46.607553 EX_ROW_EN[0] = 0x0
664 06:51:46.607982 EX_ROW_EN[1] = 0x0
665 06:51:46.611393 LP4Y_EN = 0x0
666 06:51:46.611923 WORK_FSP = 0x0
667 06:51:46.614196 WL = 0x2
668 06:51:46.614626 RL = 0x2
669 06:51:46.617361 BL = 0x2
670 06:51:46.617790 RPST = 0x0
671 06:51:46.621695 RD_PRE = 0x0
672 06:51:46.624451 WR_PRE = 0x1
673 06:51:46.624906 WR_PST = 0x0
674 06:51:46.627470 DBI_WR = 0x0
675 06:51:46.627898 DBI_RD = 0x0
676 06:51:46.630889 OTF = 0x1
677 06:51:46.635654 ===================================
678 06:51:46.638201 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 06:51:46.640764 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 06:51:46.644343 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 06:51:46.647542 ===================================
682 06:51:46.650803 LPDDR4 DRAM CONFIGURATION
683 06:51:46.654443 ===================================
684 06:51:46.657621 EX_ROW_EN[0] = 0x10
685 06:51:46.658049 EX_ROW_EN[1] = 0x0
686 06:51:46.661136 LP4Y_EN = 0x0
687 06:51:46.661666 WORK_FSP = 0x0
688 06:51:46.664179 WL = 0x2
689 06:51:46.664738 RL = 0x2
690 06:51:46.667990 BL = 0x2
691 06:51:46.668523 RPST = 0x0
692 06:51:46.671012 RD_PRE = 0x0
693 06:51:46.671539 WR_PRE = 0x1
694 06:51:46.674640 WR_PST = 0x0
695 06:51:46.675072 DBI_WR = 0x0
696 06:51:46.677931 DBI_RD = 0x0
697 06:51:46.678467 OTF = 0x1
698 06:51:46.681178 ===================================
699 06:51:46.687304 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 06:51:46.692187 nWR fixed to 40
701 06:51:46.695631 [ModeRegInit_LP4] CH0 RK0
702 06:51:46.696159 [ModeRegInit_LP4] CH0 RK1
703 06:51:46.699296 [ModeRegInit_LP4] CH1 RK0
704 06:51:46.702674 [ModeRegInit_LP4] CH1 RK1
705 06:51:46.703177 match AC timing 12
706 06:51:46.708810 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 06:51:46.712265 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 06:51:46.715470 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 06:51:46.722342 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 06:51:46.725505 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 06:51:46.728806 [EMI DOE] emi_dcm 0
712 06:51:46.732321 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 06:51:46.732864 ==
714 06:51:46.735280 Dram Type= 6, Freq= 0, CH_0, rank 0
715 06:51:46.738794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 06:51:46.739229 ==
717 06:51:46.745887 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 06:51:46.751915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 06:51:46.760855 [CA 0] Center 37 (7~68) winsize 62
720 06:51:46.763958 [CA 1] Center 37 (7~68) winsize 62
721 06:51:46.767840 [CA 2] Center 35 (5~66) winsize 62
722 06:51:46.769718 [CA 3] Center 35 (5~66) winsize 62
723 06:51:46.772883 [CA 4] Center 34 (4~65) winsize 62
724 06:51:46.776151 [CA 5] Center 33 (3~64) winsize 62
725 06:51:46.776690
726 06:51:46.779821 [CmdBusTrainingLP45] Vref(ca) range 1: 30
727 06:51:46.780346
728 06:51:46.784431 [CATrainingPosCal] consider 1 rank data
729 06:51:46.786695 u2DelayCellTimex100 = 270/100 ps
730 06:51:46.789817 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 06:51:46.793156 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 06:51:46.800130 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 06:51:46.803052 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 06:51:46.806541 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
735 06:51:46.811035 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 06:51:46.811574
737 06:51:46.813721 CA PerBit enable=1, Macro0, CA PI delay=33
738 06:51:46.814155
739 06:51:46.817651 [CBTSetCACLKResult] CA Dly = 33
740 06:51:46.818166 CS Dly: 5 (0~36)
741 06:51:46.818520 ==
742 06:51:46.820108 Dram Type= 6, Freq= 0, CH_0, rank 1
743 06:51:46.826913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 06:51:46.827449 ==
745 06:51:46.830360 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 06:51:46.836451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 06:51:46.845301 [CA 0] Center 37 (6~68) winsize 63
748 06:51:46.849473 [CA 1] Center 37 (6~68) winsize 63
749 06:51:46.852047 [CA 2] Center 35 (4~66) winsize 63
750 06:51:46.855860 [CA 3] Center 34 (4~65) winsize 62
751 06:51:46.859738 [CA 4] Center 33 (3~64) winsize 62
752 06:51:46.862643 [CA 5] Center 33 (3~64) winsize 62
753 06:51:46.863079
754 06:51:46.865625 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 06:51:46.866057
756 06:51:46.870750 [CATrainingPosCal] consider 2 rank data
757 06:51:46.873399 u2DelayCellTimex100 = 270/100 ps
758 06:51:46.875898 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 06:51:46.879038 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 06:51:46.885524 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 06:51:46.888898 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
762 06:51:46.891990 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 06:51:46.895586 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 06:51:46.896119
765 06:51:46.898778 CA PerBit enable=1, Macro0, CA PI delay=33
766 06:51:46.899220
767 06:51:46.901900 [CBTSetCACLKResult] CA Dly = 33
768 06:51:46.902337 CS Dly: 6 (0~38)
769 06:51:46.902684
770 06:51:46.905637 ----->DramcWriteLeveling(PI) begin...
771 06:51:46.909081 ==
772 06:51:46.913442 Dram Type= 6, Freq= 0, CH_0, rank 0
773 06:51:46.916173 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 06:51:46.916604 ==
775 06:51:46.919409 Write leveling (Byte 0): 29 => 29
776 06:51:46.922775 Write leveling (Byte 1): 28 => 28
777 06:51:46.927189 DramcWriteLeveling(PI) end<-----
778 06:51:46.927875
779 06:51:46.928396 ==
780 06:51:46.929125 Dram Type= 6, Freq= 0, CH_0, rank 0
781 06:51:46.932810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 06:51:46.933342 ==
783 06:51:46.936109 [Gating] SW mode calibration
784 06:51:46.942304 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 06:51:46.946483 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 06:51:46.952433 0 6 0 | B1->B0 | 3434 3333 | 0 0 | (1 1) (0 1)
787 06:51:46.955997 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 06:51:46.959209 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 06:51:46.965686 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 06:51:46.968827 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 06:51:46.974514 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 06:51:46.978949 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 06:51:46.982279 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 06:51:46.985871 0 7 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
795 06:51:46.993241 0 7 4 | B1->B0 | 3737 4444 | 0 0 | (0 0) (0 0)
796 06:51:46.995356 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 06:51:46.999557 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 06:51:47.005584 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 06:51:47.009263 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 06:51:47.012394 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 06:51:47.019145 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 06:51:47.022773 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 06:51:47.025680 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
804 06:51:47.031944 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 06:51:47.036380 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 06:51:47.039266 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 06:51:47.042294 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 06:51:47.049272 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 06:51:47.052334 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 06:51:47.055617 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 06:51:47.062281 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 06:51:47.065330 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 06:51:47.069111 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 06:51:47.075462 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 06:51:47.079912 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 06:51:47.082624 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 06:51:47.088775 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 06:51:47.093483 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
819 06:51:47.095649 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
820 06:51:47.103015 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
821 06:51:47.103585 Total UI for P1: 0, mck2ui 16
822 06:51:47.108683 best dqsien dly found for B0: ( 0, 10, 2)
823 06:51:47.109226 Total UI for P1: 0, mck2ui 16
824 06:51:47.115531 best dqsien dly found for B1: ( 0, 10, 2)
825 06:51:47.118759 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
826 06:51:47.122482 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
827 06:51:47.122953
828 06:51:47.125769 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
829 06:51:47.129140 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
830 06:51:47.132480 [Gating] SW calibration Done
831 06:51:47.133179 ==
832 06:51:47.135994 Dram Type= 6, Freq= 0, CH_0, rank 0
833 06:51:47.139617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
834 06:51:47.140122 ==
835 06:51:47.140532 RX Vref Scan: 0
836 06:51:47.141022
837 06:51:47.142999 RX Vref 0 -> 0, step: 1
838 06:51:47.143544
839 06:51:47.146171 RX Delay -130 -> 252, step: 16
840 06:51:47.149962 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
841 06:51:47.152830 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
842 06:51:47.160270 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
843 06:51:47.162884 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
844 06:51:47.166756 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
845 06:51:47.169286 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
846 06:51:47.173285 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
847 06:51:47.180106 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
848 06:51:47.182518 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
849 06:51:47.185641 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
850 06:51:47.189183 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
851 06:51:47.192678 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
852 06:51:47.199772 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
853 06:51:47.203142 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
854 06:51:47.206529 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
855 06:51:47.209930 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
856 06:51:47.210574 ==
857 06:51:47.213347 Dram Type= 6, Freq= 0, CH_0, rank 0
858 06:51:47.219810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
859 06:51:47.220636 ==
860 06:51:47.221108 DQS Delay:
861 06:51:47.222432 DQS0 = 0, DQS1 = 0
862 06:51:47.223111 DQM Delay:
863 06:51:47.223717 DQM0 = 84, DQM1 = 75
864 06:51:47.225766 DQ Delay:
865 06:51:47.229359 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
866 06:51:47.232757 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
867 06:51:47.236364 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
868 06:51:47.239917 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
869 06:51:47.240481
870 06:51:47.240878
871 06:51:47.241228 ==
872 06:51:47.242768 Dram Type= 6, Freq= 0, CH_0, rank 0
873 06:51:47.246156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
874 06:51:47.246752 ==
875 06:51:47.247300
876 06:51:47.247640
877 06:51:47.249235 TX Vref Scan disable
878 06:51:47.249777 == TX Byte 0 ==
879 06:51:47.255692 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
880 06:51:47.259120 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
881 06:51:47.259655 == TX Byte 1 ==
882 06:51:47.266772 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
883 06:51:47.270024 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
884 06:51:47.270623 ==
885 06:51:47.272808 Dram Type= 6, Freq= 0, CH_0, rank 0
886 06:51:47.275879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
887 06:51:47.276589 ==
888 06:51:47.289677 TX Vref=22, minBit 4, minWin=26, winSum=440
889 06:51:47.293125 TX Vref=24, minBit 0, minWin=27, winSum=447
890 06:51:47.296802 TX Vref=26, minBit 0, minWin=27, winSum=447
891 06:51:47.300408 TX Vref=28, minBit 4, minWin=27, winSum=452
892 06:51:47.302998 TX Vref=30, minBit 0, minWin=28, winSum=454
893 06:51:47.309449 TX Vref=32, minBit 0, minWin=28, winSum=452
894 06:51:47.313209 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
895 06:51:47.313725
896 06:51:47.316768 Final TX Range 1 Vref 30
897 06:51:47.317203
898 06:51:47.317544 ==
899 06:51:47.319540 Dram Type= 6, Freq= 0, CH_0, rank 0
900 06:51:47.323536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
901 06:51:47.324061 ==
902 06:51:47.325992
903 06:51:47.326421
904 06:51:47.326762 TX Vref Scan disable
905 06:51:47.329757 == TX Byte 0 ==
906 06:51:47.333064 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
907 06:51:47.336202 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
908 06:51:47.340377 == TX Byte 1 ==
909 06:51:47.342817 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
910 06:51:47.346825 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
911 06:51:47.349465
912 06:51:47.349891 [DATLAT]
913 06:51:47.350233 Freq=800, CH0 RK0
914 06:51:47.350556
915 06:51:47.353000 DATLAT Default: 0xa
916 06:51:47.353433 0, 0xFFFF, sum = 0
917 06:51:47.356331 1, 0xFFFF, sum = 0
918 06:51:47.356793 2, 0xFFFF, sum = 0
919 06:51:47.359743 3, 0xFFFF, sum = 0
920 06:51:47.360297 4, 0xFFFF, sum = 0
921 06:51:47.363327 5, 0xFFFF, sum = 0
922 06:51:47.366168 6, 0xFFFF, sum = 0
923 06:51:47.366606 7, 0xFFFF, sum = 0
924 06:51:47.366955 8, 0x0, sum = 1
925 06:51:47.369313 9, 0x0, sum = 2
926 06:51:47.369749 10, 0x0, sum = 3
927 06:51:47.373015 11, 0x0, sum = 4
928 06:51:47.373527 best_step = 9
929 06:51:47.373869
930 06:51:47.374183 ==
931 06:51:47.376450 Dram Type= 6, Freq= 0, CH_0, rank 0
932 06:51:47.383846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
933 06:51:47.384372 ==
934 06:51:47.384741 RX Vref Scan: 1
935 06:51:47.385066
936 06:51:47.386028 Set Vref Range= 32 -> 127
937 06:51:47.386458
938 06:51:47.389652 RX Vref 32 -> 127, step: 1
939 06:51:47.390171
940 06:51:47.390517 RX Delay -95 -> 252, step: 8
941 06:51:47.392826
942 06:51:47.393257 Set Vref, RX VrefLevel [Byte0]: 32
943 06:51:47.396898 [Byte1]: 32
944 06:51:47.400682
945 06:51:47.401154 Set Vref, RX VrefLevel [Byte0]: 33
946 06:51:47.403665 [Byte1]: 33
947 06:51:47.408053
948 06:51:47.408570 Set Vref, RX VrefLevel [Byte0]: 34
949 06:51:47.411880 [Byte1]: 34
950 06:51:47.416658
951 06:51:47.417124 Set Vref, RX VrefLevel [Byte0]: 35
952 06:51:47.419278 [Byte1]: 35
953 06:51:47.423249
954 06:51:47.423772 Set Vref, RX VrefLevel [Byte0]: 36
955 06:51:47.426889 [Byte1]: 36
956 06:51:47.431169
957 06:51:47.431694 Set Vref, RX VrefLevel [Byte0]: 37
958 06:51:47.434699 [Byte1]: 37
959 06:51:47.438650
960 06:51:47.439277 Set Vref, RX VrefLevel [Byte0]: 38
961 06:51:47.441827 [Byte1]: 38
962 06:51:47.445957
963 06:51:47.446469 Set Vref, RX VrefLevel [Byte0]: 39
964 06:51:47.449596 [Byte1]: 39
965 06:51:47.453576
966 06:51:47.454091 Set Vref, RX VrefLevel [Byte0]: 40
967 06:51:47.456690 [Byte1]: 40
968 06:51:47.461265
969 06:51:47.461708 Set Vref, RX VrefLevel [Byte0]: 41
970 06:51:47.465063 [Byte1]: 41
971 06:51:47.469316
972 06:51:47.469747 Set Vref, RX VrefLevel [Byte0]: 42
973 06:51:47.471985 [Byte1]: 42
974 06:51:47.476125
975 06:51:47.476633 Set Vref, RX VrefLevel [Byte0]: 43
976 06:51:47.480034 [Byte1]: 43
977 06:51:47.484033
978 06:51:47.484561 Set Vref, RX VrefLevel [Byte0]: 44
979 06:51:47.487026 [Byte1]: 44
980 06:51:47.491793
981 06:51:47.492284 Set Vref, RX VrefLevel [Byte0]: 45
982 06:51:47.494974 [Byte1]: 45
983 06:51:47.499576
984 06:51:47.500126 Set Vref, RX VrefLevel [Byte0]: 46
985 06:51:47.502667 [Byte1]: 46
986 06:51:47.507054
987 06:51:47.507591 Set Vref, RX VrefLevel [Byte0]: 47
988 06:51:47.510987 [Byte1]: 47
989 06:51:47.514380
990 06:51:47.514804 Set Vref, RX VrefLevel [Byte0]: 48
991 06:51:47.517723 [Byte1]: 48
992 06:51:47.521789
993 06:51:47.522266 Set Vref, RX VrefLevel [Byte0]: 49
994 06:51:47.525219 [Byte1]: 49
995 06:51:47.529654
996 06:51:47.530078 Set Vref, RX VrefLevel [Byte0]: 50
997 06:51:47.532797 [Byte1]: 50
998 06:51:47.537479
999 06:51:47.537986 Set Vref, RX VrefLevel [Byte0]: 51
1000 06:51:47.541970 [Byte1]: 51
1001 06:51:47.545251
1002 06:51:47.545679 Set Vref, RX VrefLevel [Byte0]: 52
1003 06:51:47.548164 [Byte1]: 52
1004 06:51:47.552430
1005 06:51:47.552899 Set Vref, RX VrefLevel [Byte0]: 53
1006 06:51:47.556069 [Byte1]: 53
1007 06:51:47.561242
1008 06:51:47.561783 Set Vref, RX VrefLevel [Byte0]: 54
1009 06:51:47.563376 [Byte1]: 54
1010 06:51:47.567334
1011 06:51:47.571333 Set Vref, RX VrefLevel [Byte0]: 55
1012 06:51:47.571857 [Byte1]: 55
1013 06:51:47.575939
1014 06:51:47.576453 Set Vref, RX VrefLevel [Byte0]: 56
1015 06:51:47.579295 [Byte1]: 56
1016 06:51:47.583236
1017 06:51:47.583742 Set Vref, RX VrefLevel [Byte0]: 57
1018 06:51:47.586074 [Byte1]: 57
1019 06:51:47.590195
1020 06:51:47.590693 Set Vref, RX VrefLevel [Byte0]: 58
1021 06:51:47.593588 [Byte1]: 58
1022 06:51:47.597587
1023 06:51:47.598015 Set Vref, RX VrefLevel [Byte0]: 59
1024 06:51:47.601297 [Byte1]: 59
1025 06:51:47.606011
1026 06:51:47.606438 Set Vref, RX VrefLevel [Byte0]: 60
1027 06:51:47.608699 [Byte1]: 60
1028 06:51:47.613090
1029 06:51:47.613720 Set Vref, RX VrefLevel [Byte0]: 61
1030 06:51:47.616668 [Byte1]: 61
1031 06:51:47.620853
1032 06:51:47.621388 Set Vref, RX VrefLevel [Byte0]: 62
1033 06:51:47.624009 [Byte1]: 62
1034 06:51:47.628597
1035 06:51:47.629119 Set Vref, RX VrefLevel [Byte0]: 63
1036 06:51:47.631734 [Byte1]: 63
1037 06:51:47.635779
1038 06:51:47.636347 Set Vref, RX VrefLevel [Byte0]: 64
1039 06:51:47.640226 [Byte1]: 64
1040 06:51:47.643416
1041 06:51:47.643939 Set Vref, RX VrefLevel [Byte0]: 65
1042 06:51:47.647084 [Byte1]: 65
1043 06:51:47.651192
1044 06:51:47.651765 Set Vref, RX VrefLevel [Byte0]: 66
1045 06:51:47.654436 [Byte1]: 66
1046 06:51:47.659022
1047 06:51:47.659582 Set Vref, RX VrefLevel [Byte0]: 67
1048 06:51:47.663011 [Byte1]: 67
1049 06:51:47.666864
1050 06:51:47.667332 Set Vref, RX VrefLevel [Byte0]: 68
1051 06:51:47.669989 [Byte1]: 68
1052 06:51:47.674756
1053 06:51:47.675221 Set Vref, RX VrefLevel [Byte0]: 69
1054 06:51:47.676935 [Byte1]: 69
1055 06:51:47.681248
1056 06:51:47.681672 Set Vref, RX VrefLevel [Byte0]: 70
1057 06:51:47.684618 [Byte1]: 70
1058 06:51:47.688966
1059 06:51:47.689388 Set Vref, RX VrefLevel [Byte0]: 71
1060 06:51:47.692321 [Byte1]: 71
1061 06:51:47.696563
1062 06:51:47.696815 Set Vref, RX VrefLevel [Byte0]: 72
1063 06:51:47.700226 [Byte1]: 72
1064 06:51:47.704046
1065 06:51:47.704274 Set Vref, RX VrefLevel [Byte0]: 73
1066 06:51:47.707780 [Byte1]: 73
1067 06:51:47.711800
1068 06:51:47.712059 Set Vref, RX VrefLevel [Byte0]: 74
1069 06:51:47.714779 [Byte1]: 74
1070 06:51:47.719631
1071 06:51:47.719879 Final RX Vref Byte 0 = 54 to rank0
1072 06:51:47.722641 Final RX Vref Byte 1 = 55 to rank0
1073 06:51:47.725528 Final RX Vref Byte 0 = 54 to rank1
1074 06:51:47.729510 Final RX Vref Byte 1 = 55 to rank1==
1075 06:51:47.733309 Dram Type= 6, Freq= 0, CH_0, rank 0
1076 06:51:47.739393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1077 06:51:47.739759 ==
1078 06:51:47.740049 DQS Delay:
1079 06:51:47.740316 DQS0 = 0, DQS1 = 0
1080 06:51:47.743157 DQM Delay:
1081 06:51:47.743580 DQM0 = 83, DQM1 = 73
1082 06:51:47.746173 DQ Delay:
1083 06:51:47.750083 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1084 06:51:47.750646 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1085 06:51:47.752879 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1086 06:51:47.756025 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1087 06:51:47.759274
1088 06:51:47.759836
1089 06:51:47.766164 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1090 06:51:47.769360 CH0 RK0: MR19=606, MR18=3232
1091 06:51:47.775945 CH0_RK0: MR19=0x606, MR18=0x3232, DQSOSC=397, MR23=63, INC=93, DEC=62
1092 06:51:47.776491
1093 06:51:47.779353 ----->DramcWriteLeveling(PI) begin...
1094 06:51:47.779927 ==
1095 06:51:47.783251 Dram Type= 6, Freq= 0, CH_0, rank 1
1096 06:51:47.785907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1097 06:51:47.786378 ==
1098 06:51:47.789193 Write leveling (Byte 0): 29 => 29
1099 06:51:47.792760 Write leveling (Byte 1): 29 => 29
1100 06:51:47.795787 DramcWriteLeveling(PI) end<-----
1101 06:51:47.796258
1102 06:51:47.796627 ==
1103 06:51:47.799417 Dram Type= 6, Freq= 0, CH_0, rank 1
1104 06:51:47.804000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1105 06:51:47.804472 ==
1106 06:51:47.806197 [Gating] SW mode calibration
1107 06:51:47.812361 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1108 06:51:47.819809 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1109 06:51:47.822800 0 6 0 | B1->B0 | 3131 3232 | 0 0 | (0 1) (0 0)
1110 06:51:47.825759 0 6 4 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1111 06:51:47.832621 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 06:51:47.835637 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 06:51:47.839823 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 06:51:47.846671 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 06:51:47.849142 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 06:51:47.853194 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1117 06:51:47.859201 0 7 0 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
1118 06:51:47.863328 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 06:51:47.865576 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 06:51:47.872621 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 06:51:47.876013 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 06:51:47.879404 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 06:51:47.885790 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 06:51:47.889071 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 06:51:47.893277 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1126 06:51:47.899377 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1127 06:51:47.902382 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 06:51:47.906212 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 06:51:47.909338 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 06:51:47.915671 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 06:51:47.919248 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 06:51:47.922901 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 06:51:47.929238 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 06:51:47.932414 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 06:51:47.936023 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 06:51:47.942887 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 06:51:47.945902 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 06:51:47.949007 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 06:51:47.955806 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 06:51:47.958987 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 06:51:47.962661 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1142 06:51:47.970076 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1143 06:51:47.973084 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1144 06:51:47.975984 Total UI for P1: 0, mck2ui 16
1145 06:51:47.979150 best dqsien dly found for B0: ( 0, 10, 2)
1146 06:51:47.982918 Total UI for P1: 0, mck2ui 16
1147 06:51:47.985811 best dqsien dly found for B1: ( 0, 10, 2)
1148 06:51:47.989108 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1149 06:51:47.992426 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1150 06:51:47.992945
1151 06:51:47.995952 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1152 06:51:47.999128 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1153 06:51:48.002246 [Gating] SW calibration Done
1154 06:51:48.002709 ==
1155 06:51:48.007244 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 06:51:48.009456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1157 06:51:48.009932 ==
1158 06:51:48.053475 RX Vref Scan: 0
1159 06:51:48.054106
1160 06:51:48.054490 RX Vref 0 -> 0, step: 1
1161 06:51:48.054842
1162 06:51:48.055551 RX Delay -130 -> 252, step: 16
1163 06:51:48.055933 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1164 06:51:48.056270 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1165 06:51:48.056597 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1166 06:51:48.056976 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1167 06:51:48.057304 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1168 06:51:48.057617 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1169 06:51:48.058046 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1170 06:51:48.058565 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1171 06:51:48.058906 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1172 06:51:48.060526 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1173 06:51:48.064123 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1174 06:51:48.064597 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1175 06:51:48.070945 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1176 06:51:48.074303 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1177 06:51:48.077560 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1178 06:51:48.080626 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1179 06:51:48.081152 ==
1180 06:51:48.083949 Dram Type= 6, Freq= 0, CH_0, rank 1
1181 06:51:48.090405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1182 06:51:48.090954 ==
1183 06:51:48.091327 DQS Delay:
1184 06:51:48.094432 DQS0 = 0, DQS1 = 0
1185 06:51:48.094906 DQM Delay:
1186 06:51:48.095282 DQM0 = 84, DQM1 = 74
1187 06:51:48.097257 DQ Delay:
1188 06:51:48.100586 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1189 06:51:48.103486 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1190 06:51:48.107357 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1191 06:51:48.110761 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1192 06:51:48.111303
1193 06:51:48.111766
1194 06:51:48.112121 ==
1195 06:51:48.113540 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 06:51:48.118526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1197 06:51:48.119154 ==
1198 06:51:48.119539
1199 06:51:48.119888
1200 06:51:48.120624 TX Vref Scan disable
1201 06:51:48.121222 == TX Byte 0 ==
1202 06:51:48.126854 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1203 06:51:48.130824 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1204 06:51:48.131375 == TX Byte 1 ==
1205 06:51:48.138097 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1206 06:51:48.141231 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1207 06:51:48.141708 ==
1208 06:51:48.143801 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 06:51:48.147171 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1210 06:51:48.147648 ==
1211 06:51:48.161200 TX Vref=22, minBit 0, minWin=27, winSum=447
1212 06:51:48.164149 TX Vref=24, minBit 0, minWin=28, winSum=453
1213 06:51:48.168053 TX Vref=26, minBit 0, minWin=28, winSum=454
1214 06:51:48.170992 TX Vref=28, minBit 2, minWin=28, winSum=459
1215 06:51:48.174500 TX Vref=30, minBit 2, minWin=28, winSum=460
1216 06:51:48.178137 TX Vref=32, minBit 0, minWin=28, winSum=459
1217 06:51:48.184921 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 30
1218 06:51:48.185479
1219 06:51:48.188058 Final TX Range 1 Vref 30
1220 06:51:48.188530
1221 06:51:48.189035 ==
1222 06:51:48.191198 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 06:51:48.194557 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1224 06:51:48.195025 ==
1225 06:51:48.195394
1226 06:51:48.197355
1227 06:51:48.197871 TX Vref Scan disable
1228 06:51:48.201460 == TX Byte 0 ==
1229 06:51:48.204626 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1230 06:51:48.207817 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1231 06:51:48.210760 == TX Byte 1 ==
1232 06:51:48.214247 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1233 06:51:48.218708 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1234 06:51:48.220635
1235 06:51:48.221173 [DATLAT]
1236 06:51:48.221553 Freq=800, CH0 RK1
1237 06:51:48.221904
1238 06:51:48.224369 DATLAT Default: 0x9
1239 06:51:48.224883 0, 0xFFFF, sum = 0
1240 06:51:48.227803 1, 0xFFFF, sum = 0
1241 06:51:48.228278 2, 0xFFFF, sum = 0
1242 06:51:48.230862 3, 0xFFFF, sum = 0
1243 06:51:48.231409 4, 0xFFFF, sum = 0
1244 06:51:48.234288 5, 0xFFFF, sum = 0
1245 06:51:48.234770 6, 0xFFFF, sum = 0
1246 06:51:48.237541 7, 0xFFFF, sum = 0
1247 06:51:48.238018 8, 0x0, sum = 1
1248 06:51:48.240915 9, 0x0, sum = 2
1249 06:51:48.241396 10, 0x0, sum = 3
1250 06:51:48.244447 11, 0x0, sum = 4
1251 06:51:48.245124 best_step = 9
1252 06:51:48.245504
1253 06:51:48.245850 ==
1254 06:51:48.247746 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 06:51:48.254928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1256 06:51:48.255467 ==
1257 06:51:48.255844 RX Vref Scan: 0
1258 06:51:48.256195
1259 06:51:48.258328 RX Vref 0 -> 0, step: 1
1260 06:51:48.258891
1261 06:51:48.260907 RX Delay -95 -> 252, step: 8
1262 06:51:48.265114 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1263 06:51:48.267232 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1264 06:51:48.273978 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1265 06:51:48.277410 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1266 06:51:48.280940 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1267 06:51:48.284252 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1268 06:51:48.287500 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1269 06:51:48.291833 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1270 06:51:48.297644 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1271 06:51:48.300844 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1272 06:51:48.304309 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1273 06:51:48.307670 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1274 06:51:48.310738 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1275 06:51:48.317854 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1276 06:51:48.320726 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1277 06:51:48.324074 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1278 06:51:48.324557 ==
1279 06:51:48.327521 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 06:51:48.330345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1281 06:51:48.333879 ==
1282 06:51:48.334317 DQS Delay:
1283 06:51:48.334691 DQS0 = 0, DQS1 = 0
1284 06:51:48.337381 DQM Delay:
1285 06:51:48.337798 DQM0 = 86, DQM1 = 74
1286 06:51:48.340516 DQ Delay:
1287 06:51:48.340969 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1288 06:51:48.344007 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1289 06:51:48.347179 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1290 06:51:48.350938 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1291 06:51:48.351364
1292 06:51:48.353938
1293 06:51:48.360786 [DQSOSCAuto] RK1, (LSB)MR18= 0x4949, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1294 06:51:48.364425 CH0 RK1: MR19=606, MR18=4949
1295 06:51:48.370738 CH0_RK1: MR19=0x606, MR18=0x4949, DQSOSC=391, MR23=63, INC=96, DEC=64
1296 06:51:48.371159 [RxdqsGatingPostProcess] freq 800
1297 06:51:48.377059 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1298 06:51:48.380739 Pre-setting of DQS Precalculation
1299 06:51:48.384308 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1300 06:51:48.387906 ==
1301 06:51:48.390527 Dram Type= 6, Freq= 0, CH_1, rank 0
1302 06:51:48.393880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1303 06:51:48.394301 ==
1304 06:51:48.397048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1305 06:51:48.403504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1306 06:51:48.413500 [CA 0] Center 36 (6~67) winsize 62
1307 06:51:48.416965 [CA 1] Center 36 (5~67) winsize 63
1308 06:51:48.419886 [CA 2] Center 34 (4~65) winsize 62
1309 06:51:48.423524 [CA 3] Center 34 (4~65) winsize 62
1310 06:51:48.426724 [CA 4] Center 33 (3~64) winsize 62
1311 06:51:48.430430 [CA 5] Center 33 (3~64) winsize 62
1312 06:51:48.430849
1313 06:51:48.433012 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1314 06:51:48.433428
1315 06:51:48.436748 [CATrainingPosCal] consider 1 rank data
1316 06:51:48.439958 u2DelayCellTimex100 = 270/100 ps
1317 06:51:48.443442 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1318 06:51:48.446786 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1319 06:51:48.453487 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1320 06:51:48.457114 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1321 06:51:48.459815 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1322 06:51:48.463669 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1323 06:51:48.464085
1324 06:51:48.466644 CA PerBit enable=1, Macro0, CA PI delay=33
1325 06:51:48.467063
1326 06:51:48.469727 [CBTSetCACLKResult] CA Dly = 33
1327 06:51:48.470345 CS Dly: 4 (0~35)
1328 06:51:48.473386 ==
1329 06:51:48.473777 Dram Type= 6, Freq= 0, CH_1, rank 1
1330 06:51:48.480787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1331 06:51:48.481318 ==
1332 06:51:48.484410 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1333 06:51:48.490564 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1334 06:51:48.500276 [CA 0] Center 36 (6~67) winsize 62
1335 06:51:48.502567 [CA 1] Center 36 (5~67) winsize 63
1336 06:51:48.505929 [CA 2] Center 34 (4~65) winsize 62
1337 06:51:48.509489 [CA 3] Center 34 (4~65) winsize 62
1338 06:51:48.512386 [CA 4] Center 33 (2~64) winsize 63
1339 06:51:48.515819 [CA 5] Center 33 (3~63) winsize 61
1340 06:51:48.516491
1341 06:51:48.519016 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1342 06:51:48.519640
1343 06:51:48.522726 [CATrainingPosCal] consider 2 rank data
1344 06:51:48.525916 u2DelayCellTimex100 = 270/100 ps
1345 06:51:48.529286 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1346 06:51:48.535865 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1347 06:51:48.539502 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1348 06:51:48.542424 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1349 06:51:48.545620 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1350 06:51:48.549429 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1351 06:51:48.549848
1352 06:51:48.552215 CA PerBit enable=1, Macro0, CA PI delay=33
1353 06:51:48.552745
1354 06:51:48.555511 [CBTSetCACLKResult] CA Dly = 33
1355 06:51:48.556004 CS Dly: 4 (0~36)
1356 06:51:48.556341
1357 06:51:48.559208 ----->DramcWriteLeveling(PI) begin...
1358 06:51:48.562303 ==
1359 06:51:48.565711 Dram Type= 6, Freq= 0, CH_1, rank 0
1360 06:51:48.569531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1361 06:51:48.569996 ==
1362 06:51:48.572346 Write leveling (Byte 0): 24 => 24
1363 06:51:48.575609 Write leveling (Byte 1): 28 => 28
1364 06:51:48.579350 DramcWriteLeveling(PI) end<-----
1365 06:51:48.579813
1366 06:51:48.580183 ==
1367 06:51:48.582099 Dram Type= 6, Freq= 0, CH_1, rank 0
1368 06:51:48.585952 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1369 06:51:48.586417 ==
1370 06:51:48.588604 [Gating] SW mode calibration
1371 06:51:48.595660 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1372 06:51:48.598839 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1373 06:51:48.606421 0 6 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
1374 06:51:48.609269 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 06:51:48.612471 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 06:51:48.619228 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 06:51:48.622476 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 06:51:48.626910 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 06:51:48.632220 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1380 06:51:48.635703 0 6 28 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
1381 06:51:48.639485 0 7 0 | B1->B0 | 3030 3d3d | 0 0 | (0 0) (0 0)
1382 06:51:48.645504 0 7 4 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
1383 06:51:48.648975 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 06:51:48.654437 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 06:51:48.658834 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 06:51:48.661999 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 06:51:48.665728 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1388 06:51:48.672498 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1389 06:51:48.675850 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1390 06:51:48.678725 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 06:51:48.686471 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 06:51:48.688854 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 06:51:48.691975 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 06:51:48.698801 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 06:51:48.701872 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 06:51:48.705229 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 06:51:48.712313 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 06:51:48.715498 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 06:51:48.718560 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 06:51:48.722319 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 06:51:48.729009 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 06:51:48.732568 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 06:51:48.735360 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 06:51:48.742080 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1405 06:51:48.746225 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1406 06:51:48.748448 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1407 06:51:48.751916 Total UI for P1: 0, mck2ui 16
1408 06:51:48.755447 best dqsien dly found for B0: ( 0, 9, 30)
1409 06:51:48.758733 Total UI for P1: 0, mck2ui 16
1410 06:51:48.761716 best dqsien dly found for B1: ( 0, 9, 30)
1411 06:51:48.765394 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1412 06:51:48.768497 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1413 06:51:48.769073
1414 06:51:48.775077 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1415 06:51:48.779034 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1416 06:51:48.781916 [Gating] SW calibration Done
1417 06:51:48.782393 ==
1418 06:51:48.785237 Dram Type= 6, Freq= 0, CH_1, rank 0
1419 06:51:48.788369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1420 06:51:48.788885 ==
1421 06:51:48.789365 RX Vref Scan: 0
1422 06:51:48.789815
1423 06:51:48.792292 RX Vref 0 -> 0, step: 1
1424 06:51:48.792804
1425 06:51:48.796800 RX Delay -130 -> 252, step: 16
1426 06:51:48.799469 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1427 06:51:48.801987 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1428 06:51:48.808556 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1429 06:51:48.813493 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1430 06:51:48.815531 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1431 06:51:48.818621 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1432 06:51:48.821618 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1433 06:51:48.828206 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1434 06:51:48.831764 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1435 06:51:48.835066 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1436 06:51:48.838148 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1437 06:51:48.841785 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1438 06:51:48.848151 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1439 06:51:48.851816 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1440 06:51:48.855189 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1441 06:51:48.858512 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1442 06:51:48.859087 ==
1443 06:51:48.861469 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 06:51:48.868487 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1445 06:51:48.869009 ==
1446 06:51:48.869379 DQS Delay:
1447 06:51:48.869727 DQS0 = 0, DQS1 = 0
1448 06:51:48.872103 DQM Delay:
1449 06:51:48.872567 DQM0 = 80, DQM1 = 72
1450 06:51:48.875065 DQ Delay:
1451 06:51:48.878806 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1452 06:51:48.879276 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1453 06:51:48.883324 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1454 06:51:48.888754 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1455 06:51:48.889298
1456 06:51:48.889667
1457 06:51:48.890012 ==
1458 06:51:48.893294 Dram Type= 6, Freq= 0, CH_1, rank 0
1459 06:51:48.895161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1460 06:51:48.895632 ==
1461 06:51:48.896003
1462 06:51:48.896353
1463 06:51:48.898686 TX Vref Scan disable
1464 06:51:48.899156 == TX Byte 0 ==
1465 06:51:48.905282 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1466 06:51:48.908622 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1467 06:51:48.909153 == TX Byte 1 ==
1468 06:51:48.915673 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1469 06:51:48.918555 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1470 06:51:48.919027 ==
1471 06:51:48.921971 Dram Type= 6, Freq= 0, CH_1, rank 0
1472 06:51:48.925239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1473 06:51:48.925712 ==
1474 06:51:48.939138 TX Vref=22, minBit 8, minWin=27, winSum=446
1475 06:51:48.942411 TX Vref=24, minBit 8, minWin=27, winSum=447
1476 06:51:48.945648 TX Vref=26, minBit 9, minWin=27, winSum=451
1477 06:51:48.949067 TX Vref=28, minBit 3, minWin=28, winSum=455
1478 06:51:48.952313 TX Vref=30, minBit 3, minWin=28, winSum=455
1479 06:51:48.959047 TX Vref=32, minBit 0, minWin=28, winSum=453
1480 06:51:48.962372 [TxChooseVref] Worse bit 3, Min win 28, Win sum 455, Final Vref 28
1481 06:51:48.962919
1482 06:51:48.965792 Final TX Range 1 Vref 28
1483 06:51:48.966264
1484 06:51:48.966633 ==
1485 06:51:48.969045 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 06:51:48.972181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1487 06:51:48.972794 ==
1488 06:51:48.975999
1489 06:51:48.976564
1490 06:51:48.976984 TX Vref Scan disable
1491 06:51:48.979341 == TX Byte 0 ==
1492 06:51:48.982703 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1493 06:51:48.985920 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1494 06:51:48.989045 == TX Byte 1 ==
1495 06:51:48.993075 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1496 06:51:48.995965 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1497 06:51:48.999637
1498 06:51:49.000108 [DATLAT]
1499 06:51:49.000477 Freq=800, CH1 RK0
1500 06:51:49.001175
1501 06:51:49.002583 DATLAT Default: 0xa
1502 06:51:49.003049 0, 0xFFFF, sum = 0
1503 06:51:49.005805 1, 0xFFFF, sum = 0
1504 06:51:49.006312 2, 0xFFFF, sum = 0
1505 06:51:49.008933 3, 0xFFFF, sum = 0
1506 06:51:49.009408 4, 0xFFFF, sum = 0
1507 06:51:49.013113 5, 0xFFFF, sum = 0
1508 06:51:49.013700 6, 0xFFFF, sum = 0
1509 06:51:49.016144 7, 0xFFFF, sum = 0
1510 06:51:49.016954 8, 0x0, sum = 1
1511 06:51:49.020057 9, 0x0, sum = 2
1512 06:51:49.020594 10, 0x0, sum = 3
1513 06:51:49.022612 11, 0x0, sum = 4
1514 06:51:49.023086 best_step = 9
1515 06:51:49.023455
1516 06:51:49.023799 ==
1517 06:51:49.026410 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 06:51:49.032431 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1519 06:51:49.033069 ==
1520 06:51:49.033455 RX Vref Scan: 1
1521 06:51:49.033804
1522 06:51:49.035778 Set Vref Range= 32 -> 127
1523 06:51:49.036503
1524 06:51:49.039411 RX Vref 32 -> 127, step: 1
1525 06:51:49.039879
1526 06:51:49.040249 RX Delay -111 -> 252, step: 8
1527 06:51:49.040598
1528 06:51:49.042610 Set Vref, RX VrefLevel [Byte0]: 32
1529 06:51:49.046169 [Byte1]: 32
1530 06:51:49.049738
1531 06:51:49.050202 Set Vref, RX VrefLevel [Byte0]: 33
1532 06:51:49.053113 [Byte1]: 33
1533 06:51:49.057532
1534 06:51:49.058005 Set Vref, RX VrefLevel [Byte0]: 34
1535 06:51:49.060755 [Byte1]: 34
1536 06:51:49.065185
1537 06:51:49.065603 Set Vref, RX VrefLevel [Byte0]: 35
1538 06:51:49.069156 [Byte1]: 35
1539 06:51:49.072961
1540 06:51:49.073474 Set Vref, RX VrefLevel [Byte0]: 36
1541 06:51:49.076106 [Byte1]: 36
1542 06:51:49.081392
1543 06:51:49.081980 Set Vref, RX VrefLevel [Byte0]: 37
1544 06:51:49.086993 [Byte1]: 37
1545 06:51:49.087556
1546 06:51:49.090576 Set Vref, RX VrefLevel [Byte0]: 38
1547 06:51:49.094051 [Byte1]: 38
1548 06:51:49.094619
1549 06:51:49.096990 Set Vref, RX VrefLevel [Byte0]: 39
1550 06:51:49.100037 [Byte1]: 39
1551 06:51:49.100502
1552 06:51:49.103701 Set Vref, RX VrefLevel [Byte0]: 40
1553 06:51:49.107396 [Byte1]: 40
1554 06:51:49.113036
1555 06:51:49.113589 Set Vref, RX VrefLevel [Byte0]: 41
1556 06:51:49.114347 [Byte1]: 41
1557 06:51:49.118647
1558 06:51:49.119112 Set Vref, RX VrefLevel [Byte0]: 42
1559 06:51:49.121917 [Byte1]: 42
1560 06:51:49.127059
1561 06:51:49.127622 Set Vref, RX VrefLevel [Byte0]: 43
1562 06:51:49.129388 [Byte1]: 43
1563 06:51:49.133931
1564 06:51:49.134531 Set Vref, RX VrefLevel [Byte0]: 44
1565 06:51:49.137081 [Byte1]: 44
1566 06:51:49.142003
1567 06:51:49.142579 Set Vref, RX VrefLevel [Byte0]: 45
1568 06:51:49.145057 [Byte1]: 45
1569 06:51:49.150454
1570 06:51:49.151032 Set Vref, RX VrefLevel [Byte0]: 46
1571 06:51:49.152679 [Byte1]: 46
1572 06:51:49.157045
1573 06:51:49.157508 Set Vref, RX VrefLevel [Byte0]: 47
1574 06:51:49.160006 [Byte1]: 47
1575 06:51:49.164790
1576 06:51:49.165293 Set Vref, RX VrefLevel [Byte0]: 48
1577 06:51:49.168263 [Byte1]: 48
1578 06:51:49.172288
1579 06:51:49.172880 Set Vref, RX VrefLevel [Byte0]: 49
1580 06:51:49.175539 [Byte1]: 49
1581 06:51:49.180068
1582 06:51:49.180534 Set Vref, RX VrefLevel [Byte0]: 50
1583 06:51:49.183370 [Byte1]: 50
1584 06:51:49.188739
1585 06:51:49.189210 Set Vref, RX VrefLevel [Byte0]: 51
1586 06:51:49.191977 [Byte1]: 51
1587 06:51:49.194988
1588 06:51:49.195533 Set Vref, RX VrefLevel [Byte0]: 52
1589 06:51:49.198425 [Byte1]: 52
1590 06:51:49.202441
1591 06:51:49.202906 Set Vref, RX VrefLevel [Byte0]: 53
1592 06:51:49.206805 [Byte1]: 53
1593 06:51:49.211051
1594 06:51:49.211629 Set Vref, RX VrefLevel [Byte0]: 54
1595 06:51:49.214985 [Byte1]: 54
1596 06:51:49.218332
1597 06:51:49.218795 Set Vref, RX VrefLevel [Byte0]: 55
1598 06:51:49.221918 [Byte1]: 55
1599 06:51:49.225763
1600 06:51:49.226227 Set Vref, RX VrefLevel [Byte0]: 56
1601 06:51:49.229174 [Byte1]: 56
1602 06:51:49.233382
1603 06:51:49.233910 Set Vref, RX VrefLevel [Byte0]: 57
1604 06:51:49.236801 [Byte1]: 57
1605 06:51:49.242143
1606 06:51:49.242699 Set Vref, RX VrefLevel [Byte0]: 58
1607 06:51:49.244082 [Byte1]: 58
1608 06:51:49.248867
1609 06:51:49.252184 Set Vref, RX VrefLevel [Byte0]: 59
1610 06:51:49.252652 [Byte1]: 59
1611 06:51:49.256949
1612 06:51:49.257489 Set Vref, RX VrefLevel [Byte0]: 60
1613 06:51:49.259729 [Byte1]: 60
1614 06:51:49.264921
1615 06:51:49.265464 Set Vref, RX VrefLevel [Byte0]: 61
1616 06:51:49.267389 [Byte1]: 61
1617 06:51:49.271855
1618 06:51:49.272424 Set Vref, RX VrefLevel [Byte0]: 62
1619 06:51:49.275004 [Byte1]: 62
1620 06:51:49.279643
1621 06:51:49.280111 Set Vref, RX VrefLevel [Byte0]: 63
1622 06:51:49.282406 [Byte1]: 63
1623 06:51:49.287634
1624 06:51:49.288205 Set Vref, RX VrefLevel [Byte0]: 64
1625 06:51:49.290544 [Byte1]: 64
1626 06:51:49.295271
1627 06:51:49.295745 Set Vref, RX VrefLevel [Byte0]: 65
1628 06:51:49.297874 [Byte1]: 65
1629 06:51:49.302999
1630 06:51:49.303468 Set Vref, RX VrefLevel [Byte0]: 66
1631 06:51:49.305239 [Byte1]: 66
1632 06:51:49.309980
1633 06:51:49.310547 Set Vref, RX VrefLevel [Byte0]: 67
1634 06:51:49.312944 [Byte1]: 67
1635 06:51:49.317473
1636 06:51:49.317939 Set Vref, RX VrefLevel [Byte0]: 68
1637 06:51:49.321318 [Byte1]: 68
1638 06:51:49.325174
1639 06:51:49.325927 Set Vref, RX VrefLevel [Byte0]: 69
1640 06:51:49.328134 [Byte1]: 69
1641 06:51:49.334036
1642 06:51:49.334726 Set Vref, RX VrefLevel [Byte0]: 70
1643 06:51:49.335787 [Byte1]: 70
1644 06:51:49.341272
1645 06:51:49.341863 Set Vref, RX VrefLevel [Byte0]: 71
1646 06:51:49.344447 [Byte1]: 71
1647 06:51:49.348253
1648 06:51:49.348930 Set Vref, RX VrefLevel [Byte0]: 72
1649 06:51:49.351759 [Byte1]: 72
1650 06:51:49.355973
1651 06:51:49.356524 Set Vref, RX VrefLevel [Byte0]: 73
1652 06:51:49.359195 [Byte1]: 73
1653 06:51:49.364016
1654 06:51:49.364580 Set Vref, RX VrefLevel [Byte0]: 74
1655 06:51:49.367034 [Byte1]: 74
1656 06:51:49.371315
1657 06:51:49.371808 Set Vref, RX VrefLevel [Byte0]: 75
1658 06:51:49.374840 [Byte1]: 75
1659 06:51:49.379012
1660 06:51:49.379474 Set Vref, RX VrefLevel [Byte0]: 76
1661 06:51:49.381855 [Byte1]: 76
1662 06:51:49.386942
1663 06:51:49.387470 Final RX Vref Byte 0 = 56 to rank0
1664 06:51:49.389639 Final RX Vref Byte 1 = 56 to rank0
1665 06:51:49.392945 Final RX Vref Byte 0 = 56 to rank1
1666 06:51:49.396282 Final RX Vref Byte 1 = 56 to rank1==
1667 06:51:49.399687 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 06:51:49.406179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1669 06:51:49.406826 ==
1670 06:51:49.407366 DQS Delay:
1671 06:51:49.407719 DQS0 = 0, DQS1 = 0
1672 06:51:49.409742 DQM Delay:
1673 06:51:49.410233 DQM0 = 79, DQM1 = 71
1674 06:51:49.413147 DQ Delay:
1675 06:51:49.417016 DQ0 =84, DQ1 =72, DQ2 =72, DQ3 =76
1676 06:51:49.417445 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1677 06:51:49.420265 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1678 06:51:49.426841 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1679 06:51:49.427368
1680 06:51:49.427853
1681 06:51:49.433011 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1682 06:51:49.436684 CH1 RK0: MR19=606, MR18=5454
1683 06:51:49.443044 CH1_RK0: MR19=0x606, MR18=0x5454, DQSOSC=388, MR23=63, INC=98, DEC=65
1684 06:51:49.443511
1685 06:51:49.446974 ----->DramcWriteLeveling(PI) begin...
1686 06:51:49.447494 ==
1687 06:51:49.450022 Dram Type= 6, Freq= 0, CH_1, rank 1
1688 06:51:49.452872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1689 06:51:49.453324 ==
1690 06:51:49.457090 Write leveling (Byte 0): 24 => 24
1691 06:51:49.460231 Write leveling (Byte 1): 25 => 25
1692 06:51:49.463646 DramcWriteLeveling(PI) end<-----
1693 06:51:49.464166
1694 06:51:49.464500 ==
1695 06:51:49.466788 Dram Type= 6, Freq= 0, CH_1, rank 1
1696 06:51:49.469534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1697 06:51:49.469982 ==
1698 06:51:49.473600 [Gating] SW mode calibration
1699 06:51:49.479845 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1700 06:51:49.486618 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1701 06:51:49.490778 0 6 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1702 06:51:49.493318 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1703 06:51:49.499947 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1704 06:51:49.503390 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1705 06:51:49.506770 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1706 06:51:49.513312 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1707 06:51:49.516244 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1708 06:51:49.519953 0 6 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1709 06:51:49.526960 0 7 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
1710 06:51:49.530205 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1711 06:51:49.533167 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1712 06:51:49.536697 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1713 06:51:49.543181 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1714 06:51:49.546549 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1715 06:51:49.550317 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1716 06:51:49.557183 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1717 06:51:49.560188 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1718 06:51:49.563716 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 06:51:49.570435 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 06:51:49.573916 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 06:51:49.576195 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 06:51:49.583215 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 06:51:49.586727 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 06:51:49.589688 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 06:51:49.597076 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 06:51:49.600873 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 06:51:49.603237 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 06:51:49.609926 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 06:51:49.613222 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 06:51:49.616649 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 06:51:49.623343 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 06:51:49.626745 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1733 06:51:49.630388 Total UI for P1: 0, mck2ui 16
1734 06:51:49.634011 best dqsien dly found for B0: ( 0, 9, 26)
1735 06:51:49.636647 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1736 06:51:49.640004 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1737 06:51:49.643969 Total UI for P1: 0, mck2ui 16
1738 06:51:49.646586 best dqsien dly found for B1: ( 0, 9, 30)
1739 06:51:49.649749 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1740 06:51:49.657337 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1741 06:51:49.657893
1742 06:51:49.659588 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1743 06:51:49.663334 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1744 06:51:49.666612 [Gating] SW calibration Done
1745 06:51:49.667286 ==
1746 06:51:49.669949 Dram Type= 6, Freq= 0, CH_1, rank 1
1747 06:51:49.673006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1748 06:51:49.673469 ==
1749 06:51:49.676135 RX Vref Scan: 0
1750 06:51:49.676783
1751 06:51:49.677167 RX Vref 0 -> 0, step: 1
1752 06:51:49.677512
1753 06:51:49.679802 RX Delay -130 -> 252, step: 16
1754 06:51:49.683138 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1755 06:51:49.689541 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1756 06:51:49.693062 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1757 06:51:49.696364 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1758 06:51:49.699677 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1759 06:51:49.703362 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1760 06:51:49.706816 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1761 06:51:49.713655 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1762 06:51:49.716957 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1763 06:51:49.720143 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1764 06:51:49.723307 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1765 06:51:49.726385 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1766 06:51:49.733394 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1767 06:51:49.738718 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1768 06:51:49.740260 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1769 06:51:49.743052 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1770 06:51:49.743591 ==
1771 06:51:49.746189 Dram Type= 6, Freq= 0, CH_1, rank 1
1772 06:51:49.753405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1773 06:51:49.753957 ==
1774 06:51:49.754324 DQS Delay:
1775 06:51:49.757357 DQS0 = 0, DQS1 = 0
1776 06:51:49.757817 DQM Delay:
1777 06:51:49.758185 DQM0 = 83, DQM1 = 71
1778 06:51:49.759562 DQ Delay:
1779 06:51:49.763758 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1780 06:51:49.766401 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =77
1781 06:51:49.769624 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1782 06:51:49.773512 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1783 06:51:49.773980
1784 06:51:49.774348
1785 06:51:49.774688 ==
1786 06:51:49.776347 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 06:51:49.779648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1788 06:51:49.780131 ==
1789 06:51:49.780499
1790 06:51:49.780895
1791 06:51:49.783660 TX Vref Scan disable
1792 06:51:49.784110 == TX Byte 0 ==
1793 06:51:49.789789 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1794 06:51:49.793603 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1795 06:51:49.794129 == TX Byte 1 ==
1796 06:51:49.800452 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1797 06:51:49.803564 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1798 06:51:49.803989 ==
1799 06:51:49.806631 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 06:51:49.810355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1801 06:51:49.810887 ==
1802 06:51:49.824282 TX Vref=22, minBit 10, minWin=27, winSum=450
1803 06:51:49.828539 TX Vref=24, minBit 0, minWin=28, winSum=453
1804 06:51:49.830164 TX Vref=26, minBit 3, minWin=28, winSum=456
1805 06:51:49.833816 TX Vref=28, minBit 3, minWin=28, winSum=458
1806 06:51:49.837024 TX Vref=30, minBit 0, minWin=28, winSum=455
1807 06:51:49.844218 TX Vref=32, minBit 0, minWin=28, winSum=454
1808 06:51:49.846915 [TxChooseVref] Worse bit 3, Min win 28, Win sum 458, Final Vref 28
1809 06:51:49.847383
1810 06:51:49.849880 Final TX Range 1 Vref 28
1811 06:51:49.850348
1812 06:51:49.850712 ==
1813 06:51:49.853723 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 06:51:49.856680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1815 06:51:49.857148 ==
1816 06:51:49.859937
1817 06:51:49.860353
1818 06:51:49.860684 TX Vref Scan disable
1819 06:51:49.864333 == TX Byte 0 ==
1820 06:51:49.866739 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1821 06:51:49.871063 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1822 06:51:49.873634 == TX Byte 1 ==
1823 06:51:49.877078 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1824 06:51:49.881461 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1825 06:51:49.883521
1826 06:51:49.884093 [DATLAT]
1827 06:51:49.884464 Freq=800, CH1 RK1
1828 06:51:49.884856
1829 06:51:49.887133 DATLAT Default: 0x9
1830 06:51:49.887670 0, 0xFFFF, sum = 0
1831 06:51:49.890590 1, 0xFFFF, sum = 0
1832 06:51:49.891151 2, 0xFFFF, sum = 0
1833 06:51:49.893223 3, 0xFFFF, sum = 0
1834 06:51:49.893691 4, 0xFFFF, sum = 0
1835 06:51:49.896841 5, 0xFFFF, sum = 0
1836 06:51:49.900095 6, 0xFFFF, sum = 0
1837 06:51:49.900697 7, 0xFFFF, sum = 0
1838 06:51:49.901129 8, 0x0, sum = 1
1839 06:51:49.903107 9, 0x0, sum = 2
1840 06:51:49.903576 10, 0x0, sum = 3
1841 06:51:49.906354 11, 0x0, sum = 4
1842 06:51:49.906826 best_step = 9
1843 06:51:49.907194
1844 06:51:49.907535 ==
1845 06:51:49.910455 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 06:51:49.916533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1847 06:51:49.917042 ==
1848 06:51:49.917415 RX Vref Scan: 0
1849 06:51:49.917761
1850 06:51:49.919874 RX Vref 0 -> 0, step: 1
1851 06:51:49.920295
1852 06:51:49.923701 RX Delay -111 -> 252, step: 8
1853 06:51:49.926758 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1854 06:51:49.929647 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1855 06:51:49.937417 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1856 06:51:49.940590 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1857 06:51:49.943373 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1858 06:51:49.946478 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1859 06:51:49.950771 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1860 06:51:49.957696 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1861 06:51:49.960016 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1862 06:51:49.963208 iDelay=217, Bit 9, Center 56 (-63 ~ 176) 240
1863 06:51:49.966587 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1864 06:51:49.969934 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1865 06:51:49.977390 iDelay=217, Bit 12, Center 84 (-39 ~ 208) 248
1866 06:51:49.980580 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1867 06:51:49.982966 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1868 06:51:49.986477 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1869 06:51:49.987012 ==
1870 06:51:49.989992 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 06:51:49.996686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1872 06:51:49.997245 ==
1873 06:51:49.997581 DQS Delay:
1874 06:51:49.997931 DQS0 = 0, DQS1 = 0
1875 06:51:49.999679 DQM Delay:
1876 06:51:50.000257 DQM0 = 82, DQM1 = 72
1877 06:51:50.002973 DQ Delay:
1878 06:51:50.006765 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1879 06:51:50.010334 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1880 06:51:50.010917 DQ8 =56, DQ9 =56, DQ10 =72, DQ11 =64
1881 06:51:50.016353 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
1882 06:51:50.016882
1883 06:51:50.017395
1884 06:51:50.023236 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d3d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1885 06:51:50.026585 CH1 RK1: MR19=606, MR18=3D3D
1886 06:51:50.033673 CH1_RK1: MR19=0x606, MR18=0x3D3D, DQSOSC=394, MR23=63, INC=95, DEC=63
1887 06:51:50.036644 [RxdqsGatingPostProcess] freq 800
1888 06:51:50.040123 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1889 06:51:50.044123 Pre-setting of DQS Precalculation
1890 06:51:50.049833 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1891 06:51:50.056679 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1892 06:51:50.063176 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1893 06:51:50.063789
1894 06:51:50.064166
1895 06:51:50.066481 [Calibration Summary] 1600 Mbps
1896 06:51:50.066946 CH 0, Rank 0
1897 06:51:50.070425 SW Impedance : PASS
1898 06:51:50.070989 DUTY Scan : NO K
1899 06:51:50.073164 ZQ Calibration : PASS
1900 06:51:50.076868 Jitter Meter : NO K
1901 06:51:50.077287 CBT Training : PASS
1902 06:51:50.080681 Write leveling : PASS
1903 06:51:50.083913 RX DQS gating : PASS
1904 06:51:50.084415 RX DQ/DQS(RDDQC) : PASS
1905 06:51:50.086706 TX DQ/DQS : PASS
1906 06:51:50.089983 RX DATLAT : PASS
1907 06:51:50.090549 RX DQ/DQS(Engine): PASS
1908 06:51:50.093304 TX OE : NO K
1909 06:51:50.093885 All Pass.
1910 06:51:50.094257
1911 06:51:50.096937 CH 0, Rank 1
1912 06:51:50.097497 SW Impedance : PASS
1913 06:51:50.100460 DUTY Scan : NO K
1914 06:51:50.103637 ZQ Calibration : PASS
1915 06:51:50.104107 Jitter Meter : NO K
1916 06:51:50.106897 CBT Training : PASS
1917 06:51:50.109717 Write leveling : PASS
1918 06:51:50.110182 RX DQS gating : PASS
1919 06:51:50.112866 RX DQ/DQS(RDDQC) : PASS
1920 06:51:50.113331 TX DQ/DQS : PASS
1921 06:51:50.116660 RX DATLAT : PASS
1922 06:51:50.120292 RX DQ/DQS(Engine): PASS
1923 06:51:50.120845 TX OE : NO K
1924 06:51:50.124182 All Pass.
1925 06:51:50.124684
1926 06:51:50.125081 CH 1, Rank 0
1927 06:51:50.127035 SW Impedance : PASS
1928 06:51:50.127489 DUTY Scan : NO K
1929 06:51:50.129773 ZQ Calibration : PASS
1930 06:51:50.133151 Jitter Meter : NO K
1931 06:51:50.133571 CBT Training : PASS
1932 06:51:50.136694 Write leveling : PASS
1933 06:51:50.140367 RX DQS gating : PASS
1934 06:51:50.140953 RX DQ/DQS(RDDQC) : PASS
1935 06:51:50.143498 TX DQ/DQS : PASS
1936 06:51:50.144078 RX DATLAT : PASS
1937 06:51:50.147267 RX DQ/DQS(Engine): PASS
1938 06:51:50.150288 TX OE : NO K
1939 06:51:50.150813 All Pass.
1940 06:51:50.151155
1941 06:51:50.151467 CH 1, Rank 1
1942 06:51:50.153363 SW Impedance : PASS
1943 06:51:50.157119 DUTY Scan : NO K
1944 06:51:50.157623 ZQ Calibration : PASS
1945 06:51:50.160628 Jitter Meter : NO K
1946 06:51:50.163282 CBT Training : PASS
1947 06:51:50.163784 Write leveling : PASS
1948 06:51:50.166418 RX DQS gating : PASS
1949 06:51:50.170220 RX DQ/DQS(RDDQC) : PASS
1950 06:51:50.170868 TX DQ/DQS : PASS
1951 06:51:50.173360 RX DATLAT : PASS
1952 06:51:50.178578 RX DQ/DQS(Engine): PASS
1953 06:51:50.179108 TX OE : NO K
1954 06:51:50.179894 All Pass.
1955 06:51:50.180242
1956 06:51:50.180557 DramC Write-DBI off
1957 06:51:50.182925 PER_BANK_REFRESH: Hybrid Mode
1958 06:51:50.183491 TX_TRACKING: ON
1959 06:51:50.186852 [GetDramInforAfterCalByMRR] Vendor 6.
1960 06:51:50.193368 [GetDramInforAfterCalByMRR] Revision 606.
1961 06:51:50.196490 [GetDramInforAfterCalByMRR] Revision 2 0.
1962 06:51:50.197054 MR0 0x3939
1963 06:51:50.197398 MR8 0x1111
1964 06:51:50.199935 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1965 06:51:50.203382
1966 06:51:50.203897 MR0 0x3939
1967 06:51:50.204233 MR8 0x1111
1968 06:51:50.207307 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1969 06:51:50.207731
1970 06:51:50.216128 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1971 06:51:50.219927 [FAST_K] Save calibration result to emmc
1972 06:51:50.222585 [FAST_K] Save calibration result to emmc
1973 06:51:50.226517 dram_init: config_dvfs: 1
1974 06:51:50.229093 dramc_set_vcore_voltage set vcore to 662500
1975 06:51:50.233938 Read voltage for 1200, 2
1976 06:51:50.234456 Vio18 = 0
1977 06:51:50.234793 Vcore = 662500
1978 06:51:50.235737 Vdram = 0
1979 06:51:50.236190 Vddq = 0
1980 06:51:50.236546 Vmddr = 0
1981 06:51:50.242509 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1982 06:51:50.246029 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1983 06:51:50.249359 MEM_TYPE=3, freq_sel=15
1984 06:51:50.252685 sv_algorithm_assistance_LP4_1600
1985 06:51:50.256163 ============ PULL DRAM RESETB DOWN ============
1986 06:51:50.259765 ========== PULL DRAM RESETB DOWN end =========
1987 06:51:50.266040 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1988 06:51:50.269322 ===================================
1989 06:51:50.272896 LPDDR4 DRAM CONFIGURATION
1990 06:51:50.276338 ===================================
1991 06:51:50.277126 EX_ROW_EN[0] = 0x0
1992 06:51:50.279284 EX_ROW_EN[1] = 0x0
1993 06:51:50.279765 LP4Y_EN = 0x0
1994 06:51:50.282779 WORK_FSP = 0x0
1995 06:51:50.283241 WL = 0x4
1996 06:51:50.286367 RL = 0x4
1997 06:51:50.286923 BL = 0x2
1998 06:51:50.289192 RPST = 0x0
1999 06:51:50.289683 RD_PRE = 0x0
2000 06:51:50.292615 WR_PRE = 0x1
2001 06:51:50.293174 WR_PST = 0x0
2002 06:51:50.296309 DBI_WR = 0x0
2003 06:51:50.296821 DBI_RD = 0x0
2004 06:51:50.299801 OTF = 0x1
2005 06:51:50.302842 ===================================
2006 06:51:50.305496 ===================================
2007 06:51:50.305969 ANA top config
2008 06:51:50.308598 ===================================
2009 06:51:50.312695 DLL_ASYNC_EN = 0
2010 06:51:50.316218 ALL_SLAVE_EN = 0
2011 06:51:50.319577 NEW_RANK_MODE = 1
2012 06:51:50.320152 DLL_IDLE_MODE = 1
2013 06:51:50.323062 LP45_APHY_COMB_EN = 1
2014 06:51:50.325400 TX_ODT_DIS = 1
2015 06:51:50.329066 NEW_8X_MODE = 1
2016 06:51:50.332842 ===================================
2017 06:51:50.335746 ===================================
2018 06:51:50.338879 data_rate = 2400
2019 06:51:50.339450 CKR = 1
2020 06:51:50.342918 DQ_P2S_RATIO = 8
2021 06:51:50.346199 ===================================
2022 06:51:50.349692 CA_P2S_RATIO = 8
2023 06:51:50.352823 DQ_CA_OPEN = 0
2024 06:51:50.355906 DQ_SEMI_OPEN = 0
2025 06:51:50.358976 CA_SEMI_OPEN = 0
2026 06:51:50.359473 CA_FULL_RATE = 0
2027 06:51:50.361985 DQ_CKDIV4_EN = 0
2028 06:51:50.365929 CA_CKDIV4_EN = 0
2029 06:51:50.369513 CA_PREDIV_EN = 0
2030 06:51:50.372533 PH8_DLY = 17
2031 06:51:50.375742 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2032 06:51:50.376315 DQ_AAMCK_DIV = 4
2033 06:51:50.379327 CA_AAMCK_DIV = 4
2034 06:51:50.382815 CA_ADMCK_DIV = 4
2035 06:51:50.386033 DQ_TRACK_CA_EN = 0
2036 06:51:50.388934 CA_PICK = 1200
2037 06:51:50.392255 CA_MCKIO = 1200
2038 06:51:50.395635 MCKIO_SEMI = 0
2039 06:51:50.396223 PLL_FREQ = 2366
2040 06:51:50.399030 DQ_UI_PI_RATIO = 32
2041 06:51:50.402666 CA_UI_PI_RATIO = 0
2042 06:51:50.406040 ===================================
2043 06:51:50.409296 ===================================
2044 06:51:50.412624 memory_type:LPDDR4
2045 06:51:50.413168 GP_NUM : 10
2046 06:51:50.415288 SRAM_EN : 1
2047 06:51:50.419498 MD32_EN : 0
2048 06:51:50.422851 ===================================
2049 06:51:50.423449 [ANA_INIT] >>>>>>>>>>>>>>
2050 06:51:50.425945 <<<<<< [CONFIGURE PHASE]: ANA_TX
2051 06:51:50.428936 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2052 06:51:50.432601 ===================================
2053 06:51:50.436692 data_rate = 2400,PCW = 0X5b00
2054 06:51:50.438565 ===================================
2055 06:51:50.442315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2056 06:51:50.448838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2057 06:51:50.452307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2058 06:51:50.458763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2059 06:51:50.462333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2060 06:51:50.465407 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2061 06:51:50.465899 [ANA_INIT] flow start
2062 06:51:50.468815 [ANA_INIT] PLL >>>>>>>>
2063 06:51:50.472212 [ANA_INIT] PLL <<<<<<<<
2064 06:51:50.476166 [ANA_INIT] MIDPI >>>>>>>>
2065 06:51:50.476828 [ANA_INIT] MIDPI <<<<<<<<
2066 06:51:50.479291 [ANA_INIT] DLL >>>>>>>>
2067 06:51:50.482825 [ANA_INIT] DLL <<<<<<<<
2068 06:51:50.483369 [ANA_INIT] flow end
2069 06:51:50.485229 ============ LP4 DIFF to SE enter ============
2070 06:51:50.492338 ============ LP4 DIFF to SE exit ============
2071 06:51:50.492891 [ANA_INIT] <<<<<<<<<<<<<
2072 06:51:50.495689 [Flow] Enable top DCM control >>>>>
2073 06:51:50.498464 [Flow] Enable top DCM control <<<<<
2074 06:51:50.502298 Enable DLL master slave shuffle
2075 06:51:50.509051 ==============================================================
2076 06:51:50.509756 Gating Mode config
2077 06:51:50.515597 ==============================================================
2078 06:51:50.518632 Config description:
2079 06:51:50.525786 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2080 06:51:50.532261 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2081 06:51:50.539244 SELPH_MODE 0: By rank 1: By Phase
2082 06:51:50.545299 ==============================================================
2083 06:51:50.548999 GAT_TRACK_EN = 1
2084 06:51:50.549441 RX_GATING_MODE = 2
2085 06:51:50.552335 RX_GATING_TRACK_MODE = 2
2086 06:51:50.555853 SELPH_MODE = 1
2087 06:51:50.559156 PICG_EARLY_EN = 1
2088 06:51:50.562376 VALID_LAT_VALUE = 1
2089 06:51:50.569227 ==============================================================
2090 06:51:50.572066 Enter into Gating configuration >>>>
2091 06:51:50.576034 Exit from Gating configuration <<<<
2092 06:51:50.579071 Enter into DVFS_PRE_config >>>>>
2093 06:51:50.588489 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2094 06:51:50.592492 Exit from DVFS_PRE_config <<<<<
2095 06:51:50.595720 Enter into PICG configuration >>>>
2096 06:51:50.598304 Exit from PICG configuration <<<<
2097 06:51:50.603380 [RX_INPUT] configuration >>>>>
2098 06:51:50.603948 [RX_INPUT] configuration <<<<<
2099 06:51:50.608787 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2100 06:51:50.615296 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2101 06:51:50.619026 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2102 06:51:50.625583 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2103 06:51:50.632179 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2104 06:51:50.639791 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2105 06:51:50.642056 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2106 06:51:50.645630 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2107 06:51:50.652444 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2108 06:51:50.656283 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2109 06:51:50.658975 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2110 06:51:50.665805 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2111 06:51:50.668481 ===================================
2112 06:51:50.669146 LPDDR4 DRAM CONFIGURATION
2113 06:51:50.672590 ===================================
2114 06:51:50.675677 EX_ROW_EN[0] = 0x0
2115 06:51:50.676228 EX_ROW_EN[1] = 0x0
2116 06:51:50.678921 LP4Y_EN = 0x0
2117 06:51:50.679475 WORK_FSP = 0x0
2118 06:51:50.681958 WL = 0x4
2119 06:51:50.685735 RL = 0x4
2120 06:51:50.686290 BL = 0x2
2121 06:51:50.688541 RPST = 0x0
2122 06:51:50.689234 RD_PRE = 0x0
2123 06:51:50.692004 WR_PRE = 0x1
2124 06:51:50.692555 WR_PST = 0x0
2125 06:51:50.695270 DBI_WR = 0x0
2126 06:51:50.695735 DBI_RD = 0x0
2127 06:51:50.698634 OTF = 0x1
2128 06:51:50.702280 ===================================
2129 06:51:50.705271 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2130 06:51:50.708476 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2131 06:51:50.711929 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 06:51:50.715107 ===================================
2133 06:51:50.718649 LPDDR4 DRAM CONFIGURATION
2134 06:51:50.721959 ===================================
2135 06:51:50.724834 EX_ROW_EN[0] = 0x10
2136 06:51:50.725348 EX_ROW_EN[1] = 0x0
2137 06:51:50.728460 LP4Y_EN = 0x0
2138 06:51:50.728972 WORK_FSP = 0x0
2139 06:51:50.731800 WL = 0x4
2140 06:51:50.732267 RL = 0x4
2141 06:51:50.735431 BL = 0x2
2142 06:51:50.735993 RPST = 0x0
2143 06:51:50.738203 RD_PRE = 0x0
2144 06:51:50.738722 WR_PRE = 0x1
2145 06:51:50.741968 WR_PST = 0x0
2146 06:51:50.742566 DBI_WR = 0x0
2147 06:51:50.745508 DBI_RD = 0x0
2148 06:51:50.748406 OTF = 0x1
2149 06:51:50.752139 ===================================
2150 06:51:50.755388 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2151 06:51:50.755973 ==
2152 06:51:50.759669 Dram Type= 6, Freq= 0, CH_0, rank 0
2153 06:51:50.764893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2154 06:51:50.765502 ==
2155 06:51:50.768007 [Duty_Offset_Calibration]
2156 06:51:50.768491 B0:0 B1:2 CA:1
2157 06:51:50.769061
2158 06:51:50.771446 [DutyScan_Calibration_Flow] k_type=0
2159 06:51:50.781844
2160 06:51:50.782452 ==CLK 0==
2161 06:51:50.784607 Final CLK duty delay cell = 0
2162 06:51:50.787619 [0] MAX Duty = 5093%(X100), DQS PI = 12
2163 06:51:50.791113 [0] MIN Duty = 4938%(X100), DQS PI = 52
2164 06:51:50.791730 [0] AVG Duty = 5015%(X100)
2165 06:51:50.794084
2166 06:51:50.797390 CH0 CLK Duty spec in!! Max-Min= 155%
2167 06:51:50.801466 [DutyScan_Calibration_Flow] ====Done====
2168 06:51:50.801961
2169 06:51:50.804874 [DutyScan_Calibration_Flow] k_type=1
2170 06:51:50.820188
2171 06:51:50.820799 ==DQS 0 ==
2172 06:51:50.823525 Final DQS duty delay cell = 0
2173 06:51:50.827253 [0] MAX Duty = 5125%(X100), DQS PI = 30
2174 06:51:50.830338 [0] MIN Duty = 5031%(X100), DQS PI = 4
2175 06:51:50.830826 [0] AVG Duty = 5078%(X100)
2176 06:51:50.833089
2177 06:51:50.833570 ==DQS 1 ==
2178 06:51:50.837355 Final DQS duty delay cell = 0
2179 06:51:50.839691 [0] MAX Duty = 5031%(X100), DQS PI = 52
2180 06:51:50.843354 [0] MIN Duty = 4906%(X100), DQS PI = 16
2181 06:51:50.846868 [0] AVG Duty = 4968%(X100)
2182 06:51:50.847533
2183 06:51:50.850028 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2184 06:51:50.850514
2185 06:51:50.853390 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2186 06:51:50.856698 [DutyScan_Calibration_Flow] ====Done====
2187 06:51:50.857331
2188 06:51:50.860326 [DutyScan_Calibration_Flow] k_type=3
2189 06:51:50.877346
2190 06:51:50.877941 ==DQM 0 ==
2191 06:51:50.880889 Final DQM duty delay cell = 0
2192 06:51:50.884363 [0] MAX Duty = 5156%(X100), DQS PI = 20
2193 06:51:50.887448 [0] MIN Duty = 5000%(X100), DQS PI = 40
2194 06:51:50.888011 [0] AVG Duty = 5078%(X100)
2195 06:51:50.891309
2196 06:51:50.891865 ==DQM 1 ==
2197 06:51:50.894387 Final DQM duty delay cell = 4
2198 06:51:50.897780 [4] MAX Duty = 5187%(X100), DQS PI = 54
2199 06:51:50.901029 [4] MIN Duty = 5000%(X100), DQS PI = 18
2200 06:51:50.904360 [4] AVG Duty = 5093%(X100)
2201 06:51:50.905140
2202 06:51:50.907056 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2203 06:51:50.907529
2204 06:51:50.910820 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2205 06:51:50.914348 [DutyScan_Calibration_Flow] ====Done====
2206 06:51:50.914913
2207 06:51:50.917605 [DutyScan_Calibration_Flow] k_type=2
2208 06:51:50.932670
2209 06:51:50.933263 ==DQ 0 ==
2210 06:51:50.935901 Final DQ duty delay cell = -4
2211 06:51:50.938890 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2212 06:51:50.942976 [-4] MIN Duty = 4813%(X100), DQS PI = 44
2213 06:51:50.945718 [-4] AVG Duty = 4937%(X100)
2214 06:51:50.946191
2215 06:51:50.946607 ==DQ 1 ==
2216 06:51:50.950176 Final DQ duty delay cell = -4
2217 06:51:50.953499 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2218 06:51:50.955880 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2219 06:51:50.959506 [-4] AVG Duty = 4969%(X100)
2220 06:51:50.960065
2221 06:51:50.962086 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2222 06:51:50.962839
2223 06:51:50.965319 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2224 06:51:50.969040 [DutyScan_Calibration_Flow] ====Done====
2225 06:51:50.969522 ==
2226 06:51:50.971808 Dram Type= 6, Freq= 0, CH_1, rank 0
2227 06:51:50.975457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2228 06:51:50.976030 ==
2229 06:51:50.978746 [Duty_Offset_Calibration]
2230 06:51:50.979214 B0:0 B1:5 CA:-5
2231 06:51:50.979587
2232 06:51:50.982015 [DutyScan_Calibration_Flow] k_type=0
2233 06:51:50.993241
2234 06:51:50.993824 ==CLK 0==
2235 06:51:50.996192 Final CLK duty delay cell = 0
2236 06:51:50.999431 [0] MAX Duty = 5125%(X100), DQS PI = 16
2237 06:51:51.002629 [0] MIN Duty = 4875%(X100), DQS PI = 46
2238 06:51:51.003200 [0] AVG Duty = 5000%(X100)
2239 06:51:51.005851
2240 06:51:51.009316 CH1 CLK Duty spec in!! Max-Min= 250%
2241 06:51:51.013358 [DutyScan_Calibration_Flow] ====Done====
2242 06:51:51.013833
2243 06:51:51.016526 [DutyScan_Calibration_Flow] k_type=1
2244 06:51:51.031326
2245 06:51:51.031895 ==DQS 0 ==
2246 06:51:51.035748 Final DQS duty delay cell = 0
2247 06:51:51.038088 [0] MAX Duty = 5125%(X100), DQS PI = 16
2248 06:51:51.041740 [0] MIN Duty = 4907%(X100), DQS PI = 24
2249 06:51:51.042228 [0] AVG Duty = 5016%(X100)
2250 06:51:51.045020
2251 06:51:51.045587 ==DQS 1 ==
2252 06:51:51.047816 Final DQS duty delay cell = -4
2253 06:51:51.051265 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2254 06:51:51.054664 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2255 06:51:51.057999 [-4] AVG Duty = 4953%(X100)
2256 06:51:51.058469
2257 06:51:51.061358 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2258 06:51:51.061826
2259 06:51:51.064827 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2260 06:51:51.068862 [DutyScan_Calibration_Flow] ====Done====
2261 06:51:51.069291
2262 06:51:51.071605 [DutyScan_Calibration_Flow] k_type=3
2263 06:51:51.087223
2264 06:51:51.087787 ==DQM 0 ==
2265 06:51:51.091044 Final DQM duty delay cell = -4
2266 06:51:51.093258 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2267 06:51:51.096745 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2268 06:51:51.100275 [-4] AVG Duty = 4953%(X100)
2269 06:51:51.100893
2270 06:51:51.101271 ==DQM 1 ==
2271 06:51:51.103612 Final DQM duty delay cell = -4
2272 06:51:51.106367 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2273 06:51:51.110416 [-4] MIN Duty = 4906%(X100), DQS PI = 58
2274 06:51:51.112989 [-4] AVG Duty = 5000%(X100)
2275 06:51:51.113606
2276 06:51:51.117053 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2277 06:51:51.117538
2278 06:51:51.121104 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2279 06:51:51.123267 [DutyScan_Calibration_Flow] ====Done====
2280 06:51:51.123740
2281 06:51:51.127328 [DutyScan_Calibration_Flow] k_type=2
2282 06:51:51.143853
2283 06:51:51.144379 ==DQ 0 ==
2284 06:51:51.147124 Final DQ duty delay cell = 0
2285 06:51:51.150598 [0] MAX Duty = 5062%(X100), DQS PI = 0
2286 06:51:51.154611 [0] MIN Duty = 4938%(X100), DQS PI = 44
2287 06:51:51.155147 [0] AVG Duty = 5000%(X100)
2288 06:51:51.155523
2289 06:51:51.157268 ==DQ 1 ==
2290 06:51:51.160538 Final DQ duty delay cell = 0
2291 06:51:51.163819 [0] MAX Duty = 5000%(X100), DQS PI = 6
2292 06:51:51.166839 [0] MIN Duty = 4907%(X100), DQS PI = 0
2293 06:51:51.167329 [0] AVG Duty = 4953%(X100)
2294 06:51:51.167800
2295 06:51:51.170157 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2296 06:51:51.173793
2297 06:51:51.174211 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2298 06:51:51.180540 [DutyScan_Calibration_Flow] ====Done====
2299 06:51:51.183259 nWR fixed to 30
2300 06:51:51.183683 [ModeRegInit_LP4] CH0 RK0
2301 06:51:51.186662 [ModeRegInit_LP4] CH0 RK1
2302 06:51:51.190310 [ModeRegInit_LP4] CH1 RK0
2303 06:51:51.190702 [ModeRegInit_LP4] CH1 RK1
2304 06:51:51.193423 match AC timing 6
2305 06:51:51.196494 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2306 06:51:51.200535 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2307 06:51:51.207628 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2308 06:51:51.209850 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2309 06:51:51.216675 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2310 06:51:51.217038 ==
2311 06:51:51.219583 Dram Type= 6, Freq= 0, CH_0, rank 0
2312 06:51:51.224014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2313 06:51:51.224318 ==
2314 06:51:51.229513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2315 06:51:51.236819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2316 06:51:51.243518 [CA 0] Center 39 (9~70) winsize 62
2317 06:51:51.246505 [CA 1] Center 39 (9~70) winsize 62
2318 06:51:51.249901 [CA 2] Center 36 (5~67) winsize 63
2319 06:51:51.253732 [CA 3] Center 35 (5~66) winsize 62
2320 06:51:51.256991 [CA 4] Center 34 (4~65) winsize 62
2321 06:51:51.259841 [CA 5] Center 33 (3~64) winsize 62
2322 06:51:51.260454
2323 06:51:51.263310 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2324 06:51:51.263861
2325 06:51:51.266702 [CATrainingPosCal] consider 1 rank data
2326 06:51:51.269770 u2DelayCellTimex100 = 270/100 ps
2327 06:51:51.273285 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2328 06:51:51.279831 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2329 06:51:51.283790 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2330 06:51:51.286305 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2331 06:51:51.290191 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2332 06:51:51.293761 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2333 06:51:51.294293
2334 06:51:51.296967 CA PerBit enable=1, Macro0, CA PI delay=33
2335 06:51:51.297510
2336 06:51:51.300273 [CBTSetCACLKResult] CA Dly = 33
2337 06:51:51.300875 CS Dly: 7 (0~38)
2338 06:51:51.303045 ==
2339 06:51:51.306290 Dram Type= 6, Freq= 0, CH_0, rank 1
2340 06:51:51.309917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2341 06:51:51.310385 ==
2342 06:51:51.312823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2343 06:51:51.320218 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2344 06:51:51.328925 [CA 0] Center 39 (8~70) winsize 63
2345 06:51:51.332629 [CA 1] Center 39 (8~70) winsize 63
2346 06:51:51.335461 [CA 2] Center 36 (5~67) winsize 63
2347 06:51:51.339110 [CA 3] Center 35 (4~66) winsize 63
2348 06:51:51.341733 [CA 4] Center 33 (3~64) winsize 62
2349 06:51:51.345396 [CA 5] Center 34 (3~65) winsize 63
2350 06:51:51.345862
2351 06:51:51.348701 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2352 06:51:51.349205
2353 06:51:51.351958 [CATrainingPosCal] consider 2 rank data
2354 06:51:51.356008 u2DelayCellTimex100 = 270/100 ps
2355 06:51:51.358588 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2356 06:51:51.366483 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2357 06:51:51.368834 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2358 06:51:51.371853 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2359 06:51:51.374911 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2360 06:51:51.378530 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2361 06:51:51.379088
2362 06:51:51.382051 CA PerBit enable=1, Macro0, CA PI delay=33
2363 06:51:51.382635
2364 06:51:51.384694 [CBTSetCACLKResult] CA Dly = 33
2365 06:51:51.388356 CS Dly: 7 (0~39)
2366 06:51:51.388961
2367 06:51:51.393413 ----->DramcWriteLeveling(PI) begin...
2368 06:51:51.393995 ==
2369 06:51:51.395128 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 06:51:51.398123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2371 06:51:51.398600 ==
2372 06:51:51.401513 Write leveling (Byte 0): 27 => 27
2373 06:51:51.405463 Write leveling (Byte 1): 27 => 27
2374 06:51:51.408334 DramcWriteLeveling(PI) end<-----
2375 06:51:51.408928
2376 06:51:51.409303 ==
2377 06:51:51.411697 Dram Type= 6, Freq= 0, CH_0, rank 0
2378 06:51:51.414499 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2379 06:51:51.415020 ==
2380 06:51:51.418877 [Gating] SW mode calibration
2381 06:51:51.424626 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2382 06:51:51.431543 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2383 06:51:51.435163 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2384 06:51:51.438757 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2385 06:51:51.444511 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2386 06:51:51.448085 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2387 06:51:51.451518 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2388 06:51:51.458063 0 11 20 | B1->B0 | 2e2e 2a2a | 0 0 | (1 0) (1 0)
2389 06:51:51.462132 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2390 06:51:51.464829 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2391 06:51:51.468019 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2392 06:51:51.475712 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2393 06:51:51.478298 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2394 06:51:51.481704 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2395 06:51:51.488333 0 12 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2396 06:51:51.491543 0 12 20 | B1->B0 | 3c3c 3f3f | 1 0 | (0 0) (0 0)
2397 06:51:51.495207 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2398 06:51:51.501969 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2399 06:51:51.505423 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2400 06:51:51.509075 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2401 06:51:51.515663 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2402 06:51:51.518239 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2403 06:51:51.521433 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2404 06:51:51.528668 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2405 06:51:51.532204 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2406 06:51:51.535119 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 06:51:51.541388 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 06:51:51.545436 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 06:51:51.548247 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 06:51:51.555504 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 06:51:51.558325 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 06:51:51.561292 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 06:51:51.568241 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 06:51:51.571258 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 06:51:51.575063 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 06:51:51.578169 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 06:51:51.584785 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 06:51:51.588464 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 06:51:51.592064 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2420 06:51:51.597796 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2421 06:51:51.600997 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2422 06:51:51.604689 Total UI for P1: 0, mck2ui 16
2423 06:51:51.607835 best dqsien dly found for B0: ( 0, 15, 20)
2424 06:51:51.611078 Total UI for P1: 0, mck2ui 16
2425 06:51:51.614274 best dqsien dly found for B1: ( 0, 15, 18)
2426 06:51:51.618541 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2427 06:51:51.621004 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2428 06:51:51.621247
2429 06:51:51.624632 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2430 06:51:51.627943 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2431 06:51:51.632052 [Gating] SW calibration Done
2432 06:51:51.632474 ==
2433 06:51:51.634513 Dram Type= 6, Freq= 0, CH_0, rank 0
2434 06:51:51.641064 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2435 06:51:51.641371 ==
2436 06:51:51.641610 RX Vref Scan: 0
2437 06:51:51.641835
2438 06:51:51.644664 RX Vref 0 -> 0, step: 1
2439 06:51:51.644927
2440 06:51:51.647926 RX Delay -40 -> 252, step: 8
2441 06:51:51.651282 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2442 06:51:51.654635 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2443 06:51:51.657446 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2444 06:51:51.661683 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2445 06:51:51.667911 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2446 06:51:51.671495 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2447 06:51:51.674331 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2448 06:51:51.679076 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2449 06:51:51.681197 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2450 06:51:51.687798 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2451 06:51:51.691393 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2452 06:51:51.694622 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2453 06:51:51.698419 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2454 06:51:51.702153 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2455 06:51:51.707891 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2456 06:51:51.711154 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2457 06:51:51.711681 ==
2458 06:51:51.714528 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 06:51:51.718009 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2460 06:51:51.718481 ==
2461 06:51:51.718854 DQS Delay:
2462 06:51:51.721206 DQS0 = 0, DQS1 = 0
2463 06:51:51.721671 DQM Delay:
2464 06:51:51.724806 DQM0 = 115, DQM1 = 106
2465 06:51:51.725272 DQ Delay:
2466 06:51:51.727845 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2467 06:51:51.731196 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2468 06:51:51.735525 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2469 06:51:51.738222 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
2470 06:51:51.738792
2471 06:51:51.741396
2472 06:51:51.741860 ==
2473 06:51:51.745004 Dram Type= 6, Freq= 0, CH_0, rank 0
2474 06:51:51.747849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2475 06:51:51.748419 ==
2476 06:51:51.748835
2477 06:51:51.749184
2478 06:51:51.753220 TX Vref Scan disable
2479 06:51:51.753687 == TX Byte 0 ==
2480 06:51:51.754773 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2481 06:51:51.761859 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2482 06:51:51.762467 == TX Byte 1 ==
2483 06:51:51.768227 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2484 06:51:51.771429 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2485 06:51:51.772020 ==
2486 06:51:51.774604 Dram Type= 6, Freq= 0, CH_0, rank 0
2487 06:51:51.777764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2488 06:51:51.778449 ==
2489 06:51:51.790286 TX Vref=22, minBit 8, minWin=25, winSum=419
2490 06:51:51.793287 TX Vref=24, minBit 10, minWin=25, winSum=428
2491 06:51:51.797134 TX Vref=26, minBit 8, minWin=24, winSum=430
2492 06:51:51.799574 TX Vref=28, minBit 8, minWin=26, winSum=434
2493 06:51:51.804234 TX Vref=30, minBit 10, minWin=26, winSum=437
2494 06:51:51.809754 TX Vref=32, minBit 10, minWin=26, winSum=434
2495 06:51:51.813223 [TxChooseVref] Worse bit 10, Min win 26, Win sum 437, Final Vref 30
2496 06:51:51.813900
2497 06:51:51.816506 Final TX Range 1 Vref 30
2498 06:51:51.817109
2499 06:51:51.817487 ==
2500 06:51:51.819885 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 06:51:51.823284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2502 06:51:51.826222 ==
2503 06:51:51.826693
2504 06:51:51.827063
2505 06:51:51.827406 TX Vref Scan disable
2506 06:51:51.830307 == TX Byte 0 ==
2507 06:51:51.833243 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2508 06:51:51.837334 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2509 06:51:51.839964 == TX Byte 1 ==
2510 06:51:51.842799 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2511 06:51:51.850697 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2512 06:51:51.851237
2513 06:51:51.851609 [DATLAT]
2514 06:51:51.851954 Freq=1200, CH0 RK0
2515 06:51:51.852288
2516 06:51:51.854761 DATLAT Default: 0xd
2517 06:51:51.855316 0, 0xFFFF, sum = 0
2518 06:51:51.856441 1, 0xFFFF, sum = 0
2519 06:51:51.856952 2, 0xFFFF, sum = 0
2520 06:51:51.860514 3, 0xFFFF, sum = 0
2521 06:51:51.861102 4, 0xFFFF, sum = 0
2522 06:51:51.864032 5, 0xFFFF, sum = 0
2523 06:51:51.867517 6, 0xFFFF, sum = 0
2524 06:51:51.868088 7, 0xFFFF, sum = 0
2525 06:51:51.870368 8, 0xFFFF, sum = 0
2526 06:51:51.870836 9, 0xFFFF, sum = 0
2527 06:51:51.873753 10, 0xFFFF, sum = 0
2528 06:51:51.874376 11, 0x0, sum = 1
2529 06:51:51.876554 12, 0x0, sum = 2
2530 06:51:51.877178 13, 0x0, sum = 3
2531 06:51:51.877558 14, 0x0, sum = 4
2532 06:51:51.880822 best_step = 12
2533 06:51:51.881383
2534 06:51:51.881755 ==
2535 06:51:51.883195 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 06:51:51.886889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2537 06:51:51.887449 ==
2538 06:51:51.890513 RX Vref Scan: 1
2539 06:51:51.891069
2540 06:51:51.893060 Set Vref Range= 32 -> 127
2541 06:51:51.893526
2542 06:51:51.893893 RX Vref 32 -> 127, step: 1
2543 06:51:51.894236
2544 06:51:51.897009 RX Delay -21 -> 252, step: 4
2545 06:51:51.897477
2546 06:51:51.900008 Set Vref, RX VrefLevel [Byte0]: 32
2547 06:51:51.903140 [Byte1]: 32
2548 06:51:51.907037
2549 06:51:51.907502 Set Vref, RX VrefLevel [Byte0]: 33
2550 06:51:51.910309 [Byte1]: 33
2551 06:51:51.914931
2552 06:51:51.915399 Set Vref, RX VrefLevel [Byte0]: 34
2553 06:51:51.917836 [Byte1]: 34
2554 06:51:51.923264
2555 06:51:51.923833 Set Vref, RX VrefLevel [Byte0]: 35
2556 06:51:51.926436 [Byte1]: 35
2557 06:51:51.930442
2558 06:51:51.931173 Set Vref, RX VrefLevel [Byte0]: 36
2559 06:51:51.933972 [Byte1]: 36
2560 06:51:51.938988
2561 06:51:51.939604 Set Vref, RX VrefLevel [Byte0]: 37
2562 06:51:51.942661 [Byte1]: 37
2563 06:51:51.946476
2564 06:51:51.947039 Set Vref, RX VrefLevel [Byte0]: 38
2565 06:51:51.949852 [Byte1]: 38
2566 06:51:51.954411
2567 06:51:51.954877 Set Vref, RX VrefLevel [Byte0]: 39
2568 06:51:51.957938 [Byte1]: 39
2569 06:51:51.962258
2570 06:51:51.962817 Set Vref, RX VrefLevel [Byte0]: 40
2571 06:51:51.965597 [Byte1]: 40
2572 06:51:51.970633
2573 06:51:51.971184 Set Vref, RX VrefLevel [Byte0]: 41
2574 06:51:51.973316 [Byte1]: 41
2575 06:51:51.978014
2576 06:51:51.978538 Set Vref, RX VrefLevel [Byte0]: 42
2577 06:51:51.981026 [Byte1]: 42
2578 06:51:51.986538
2579 06:51:51.987095 Set Vref, RX VrefLevel [Byte0]: 43
2580 06:51:51.989195 [Byte1]: 43
2581 06:51:51.993809
2582 06:51:51.994346 Set Vref, RX VrefLevel [Byte0]: 44
2583 06:51:51.997750 [Byte1]: 44
2584 06:51:52.002273
2585 06:51:52.002886 Set Vref, RX VrefLevel [Byte0]: 45
2586 06:51:52.005810 [Byte1]: 45
2587 06:51:52.011957
2588 06:51:52.012463 Set Vref, RX VrefLevel [Byte0]: 46
2589 06:51:52.013451 [Byte1]: 46
2590 06:51:52.017795
2591 06:51:52.018257 Set Vref, RX VrefLevel [Byte0]: 47
2592 06:51:52.021561 [Byte1]: 47
2593 06:51:52.026213
2594 06:51:52.026782 Set Vref, RX VrefLevel [Byte0]: 48
2595 06:51:52.029661 [Byte1]: 48
2596 06:51:52.033290
2597 06:51:52.033750 Set Vref, RX VrefLevel [Byte0]: 49
2598 06:51:52.037141 [Byte1]: 49
2599 06:51:52.041621
2600 06:51:52.042111 Set Vref, RX VrefLevel [Byte0]: 50
2601 06:51:52.044364 [Byte1]: 50
2602 06:51:52.049273
2603 06:51:52.049839 Set Vref, RX VrefLevel [Byte0]: 51
2604 06:51:52.052558 [Byte1]: 51
2605 06:51:52.057531
2606 06:51:52.058055 Set Vref, RX VrefLevel [Byte0]: 52
2607 06:51:52.060873 [Byte1]: 52
2608 06:51:52.065392
2609 06:51:52.065946 Set Vref, RX VrefLevel [Byte0]: 53
2610 06:51:52.069537 [Byte1]: 53
2611 06:51:52.073685
2612 06:51:52.074153 Set Vref, RX VrefLevel [Byte0]: 54
2613 06:51:52.076425 [Byte1]: 54
2614 06:51:52.081060
2615 06:51:52.081587 Set Vref, RX VrefLevel [Byte0]: 55
2616 06:51:52.083993 [Byte1]: 55
2617 06:51:52.089730
2618 06:51:52.090263 Set Vref, RX VrefLevel [Byte0]: 56
2619 06:51:52.092300 [Byte1]: 56
2620 06:51:52.096833
2621 06:51:52.097301 Set Vref, RX VrefLevel [Byte0]: 57
2622 06:51:52.099888 [Byte1]: 57
2623 06:51:52.104788
2624 06:51:52.105337 Set Vref, RX VrefLevel [Byte0]: 58
2625 06:51:52.108172 [Byte1]: 58
2626 06:51:52.113316
2627 06:51:52.113884 Set Vref, RX VrefLevel [Byte0]: 59
2628 06:51:52.115625 [Byte1]: 59
2629 06:51:52.120817
2630 06:51:52.121317 Set Vref, RX VrefLevel [Byte0]: 60
2631 06:51:52.123882 [Byte1]: 60
2632 06:51:52.128266
2633 06:51:52.128901 Set Vref, RX VrefLevel [Byte0]: 61
2634 06:51:52.131518 [Byte1]: 61
2635 06:51:52.136393
2636 06:51:52.136975 Set Vref, RX VrefLevel [Byte0]: 62
2637 06:51:52.139673 [Byte1]: 62
2638 06:51:52.144349
2639 06:51:52.144876 Set Vref, RX VrefLevel [Byte0]: 63
2640 06:51:52.147628 [Byte1]: 63
2641 06:51:52.152483
2642 06:51:52.152986 Set Vref, RX VrefLevel [Byte0]: 64
2643 06:51:52.155754 [Byte1]: 64
2644 06:51:52.160317
2645 06:51:52.160926 Set Vref, RX VrefLevel [Byte0]: 65
2646 06:51:52.163380 [Byte1]: 65
2647 06:51:52.168158
2648 06:51:52.168767 Set Vref, RX VrefLevel [Byte0]: 66
2649 06:51:52.171317 [Byte1]: 66
2650 06:51:52.176155
2651 06:51:52.176739 Final RX Vref Byte 0 = 46 to rank0
2652 06:51:52.179232 Final RX Vref Byte 1 = 49 to rank0
2653 06:51:52.182870 Final RX Vref Byte 0 = 46 to rank1
2654 06:51:52.186201 Final RX Vref Byte 1 = 49 to rank1==
2655 06:51:52.189789 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 06:51:52.196249 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2657 06:51:52.196888 ==
2658 06:51:52.197276 DQS Delay:
2659 06:51:52.197626 DQS0 = 0, DQS1 = 0
2660 06:51:52.199573 DQM Delay:
2661 06:51:52.200036 DQM0 = 114, DQM1 = 105
2662 06:51:52.202386 DQ Delay:
2663 06:51:52.206039 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2664 06:51:52.209473 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2665 06:51:52.212323 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2666 06:51:52.215489 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2667 06:51:52.216030
2668 06:51:52.216396
2669 06:51:52.222996 [DQSOSCAuto] RK0, (LSB)MR18= 0x404, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2670 06:51:52.226987 CH0 RK0: MR19=404, MR18=404
2671 06:51:52.233083 CH0_RK0: MR19=0x404, MR18=0x404, DQSOSC=408, MR23=63, INC=39, DEC=26
2672 06:51:52.233547
2673 06:51:52.236181 ----->DramcWriteLeveling(PI) begin...
2674 06:51:52.236651 ==
2675 06:51:52.240091 Dram Type= 6, Freq= 0, CH_0, rank 1
2676 06:51:52.242968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2677 06:51:52.243502 ==
2678 06:51:52.247133 Write leveling (Byte 0): 29 => 29
2679 06:51:52.249534 Write leveling (Byte 1): 25 => 25
2680 06:51:52.252545 DramcWriteLeveling(PI) end<-----
2681 06:51:52.253255
2682 06:51:52.253661 ==
2683 06:51:52.256527 Dram Type= 6, Freq= 0, CH_0, rank 1
2684 06:51:52.259083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2685 06:51:52.262266 ==
2686 06:51:52.262697 [Gating] SW mode calibration
2687 06:51:52.272743 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2688 06:51:52.275766 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2689 06:51:52.279392 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2690 06:51:52.286281 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2691 06:51:52.289271 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2692 06:51:52.292452 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2693 06:51:52.299741 0 11 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2694 06:51:52.302972 0 11 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2695 06:51:52.305581 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2696 06:51:52.312448 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2697 06:51:52.315580 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2698 06:51:52.318804 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2699 06:51:52.325307 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2700 06:51:52.328841 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2701 06:51:52.332455 0 12 16 | B1->B0 | 2727 3636 | 1 1 | (0 0) (0 0)
2702 06:51:52.338894 0 12 20 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
2703 06:51:52.342341 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2704 06:51:52.345472 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2705 06:51:52.352162 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2706 06:51:52.356068 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2707 06:51:52.358822 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2708 06:51:52.365595 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2709 06:51:52.368653 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2710 06:51:52.371811 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2711 06:51:52.379739 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 06:51:52.381544 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 06:51:52.385132 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 06:51:52.392611 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 06:51:52.395324 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 06:51:52.398542 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 06:51:52.405785 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 06:51:52.408825 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 06:51:52.412448 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 06:51:52.418655 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 06:51:52.421481 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 06:51:52.424701 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 06:51:52.432265 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 06:51:52.434972 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 06:51:52.437978 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2726 06:51:52.441089 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2727 06:51:52.445182 Total UI for P1: 0, mck2ui 16
2728 06:51:52.448375 best dqsien dly found for B0: ( 0, 15, 16)
2729 06:51:52.454407 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2730 06:51:52.458426 Total UI for P1: 0, mck2ui 16
2731 06:51:52.461321 best dqsien dly found for B1: ( 0, 15, 20)
2732 06:51:52.465083 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2733 06:51:52.467871 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2734 06:51:52.468487
2735 06:51:52.471401 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2736 06:51:52.474876 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2737 06:51:52.478163 [Gating] SW calibration Done
2738 06:51:52.478733 ==
2739 06:51:52.481685 Dram Type= 6, Freq= 0, CH_0, rank 1
2740 06:51:52.484948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2741 06:51:52.485522 ==
2742 06:51:52.487470 RX Vref Scan: 0
2743 06:51:52.487984
2744 06:51:52.491181 RX Vref 0 -> 0, step: 1
2745 06:51:52.491645
2746 06:51:52.492016 RX Delay -40 -> 252, step: 8
2747 06:51:52.497591 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2748 06:51:52.501180 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2749 06:51:52.505040 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2750 06:51:52.507953 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2751 06:51:52.511262 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2752 06:51:52.517533 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2753 06:51:52.520989 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2754 06:51:52.524197 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2755 06:51:52.527626 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2756 06:51:52.531192 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2757 06:51:52.538034 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2758 06:51:52.541108 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2759 06:51:52.543921 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2760 06:51:52.547506 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2761 06:51:52.551162 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2762 06:51:52.558587 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2763 06:51:52.559152 ==
2764 06:51:52.561153 Dram Type= 6, Freq= 0, CH_0, rank 1
2765 06:51:52.564944 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2766 06:51:52.565517 ==
2767 06:51:52.565891 DQS Delay:
2768 06:51:52.568086 DQS0 = 0, DQS1 = 0
2769 06:51:52.568652 DQM Delay:
2770 06:51:52.570796 DQM0 = 114, DQM1 = 107
2771 06:51:52.571360 DQ Delay:
2772 06:51:52.573981 DQ0 =107, DQ1 =115, DQ2 =111, DQ3 =111
2773 06:51:52.577410 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2774 06:51:52.581411 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2775 06:51:52.584350 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2776 06:51:52.584965
2777 06:51:52.585343
2778 06:51:52.587453 ==
2779 06:51:52.587921 Dram Type= 6, Freq= 0, CH_0, rank 1
2780 06:51:52.595039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2781 06:51:52.595508 ==
2782 06:51:52.595877
2783 06:51:52.596220
2784 06:51:52.597237 TX Vref Scan disable
2785 06:51:52.597701 == TX Byte 0 ==
2786 06:51:52.601110 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2787 06:51:52.607677 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2788 06:51:52.608249 == TX Byte 1 ==
2789 06:51:52.610840 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2790 06:51:52.617377 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2791 06:51:52.617849 ==
2792 06:51:52.620849 Dram Type= 6, Freq= 0, CH_0, rank 1
2793 06:51:52.624866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2794 06:51:52.625336 ==
2795 06:51:52.636201 TX Vref=22, minBit 8, minWin=25, winSum=418
2796 06:51:52.639489 TX Vref=24, minBit 8, minWin=25, winSum=425
2797 06:51:52.642771 TX Vref=26, minBit 9, minWin=26, winSum=429
2798 06:51:52.646336 TX Vref=28, minBit 10, minWin=26, winSum=435
2799 06:51:52.649196 TX Vref=30, minBit 9, minWin=26, winSum=437
2800 06:51:52.655782 TX Vref=32, minBit 8, minWin=26, winSum=434
2801 06:51:52.660102 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
2802 06:51:52.660642
2803 06:51:52.662440 Final TX Range 1 Vref 30
2804 06:51:52.662905
2805 06:51:52.663270 ==
2806 06:51:52.666183 Dram Type= 6, Freq= 0, CH_0, rank 1
2807 06:51:52.669347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2808 06:51:52.671930 ==
2809 06:51:52.672350
2810 06:51:52.672682
2811 06:51:52.673032 TX Vref Scan disable
2812 06:51:52.675938 == TX Byte 0 ==
2813 06:51:52.679618 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2814 06:51:52.685636 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2815 06:51:52.686063 == TX Byte 1 ==
2816 06:51:52.690124 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2817 06:51:52.697070 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2818 06:51:52.697522
2819 06:51:52.697858 [DATLAT]
2820 06:51:52.698291 Freq=1200, CH0 RK1
2821 06:51:52.698617
2822 06:51:52.699685 DATLAT Default: 0xc
2823 06:51:52.700107 0, 0xFFFF, sum = 0
2824 06:51:52.702131 1, 0xFFFF, sum = 0
2825 06:51:52.705744 2, 0xFFFF, sum = 0
2826 06:51:52.706175 3, 0xFFFF, sum = 0
2827 06:51:52.709042 4, 0xFFFF, sum = 0
2828 06:51:52.709471 5, 0xFFFF, sum = 0
2829 06:51:52.712624 6, 0xFFFF, sum = 0
2830 06:51:52.713094 7, 0xFFFF, sum = 0
2831 06:51:52.716568 8, 0xFFFF, sum = 0
2832 06:51:52.717083 9, 0xFFFF, sum = 0
2833 06:51:52.719216 10, 0xFFFF, sum = 0
2834 06:51:52.719644 11, 0x0, sum = 1
2835 06:51:52.722176 12, 0x0, sum = 2
2836 06:51:52.722626 13, 0x0, sum = 3
2837 06:51:52.725646 14, 0x0, sum = 4
2838 06:51:52.726120 best_step = 12
2839 06:51:52.726459
2840 06:51:52.726772 ==
2841 06:51:52.729024 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 06:51:52.732232 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2843 06:51:52.732685 ==
2844 06:51:52.735421 RX Vref Scan: 0
2845 06:51:52.735842
2846 06:51:52.739094 RX Vref 0 -> 0, step: 1
2847 06:51:52.739607
2848 06:51:52.739952 RX Delay -21 -> 252, step: 4
2849 06:51:52.746177 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2850 06:51:52.750313 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2851 06:51:52.753310 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2852 06:51:52.756368 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2853 06:51:52.759661 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2854 06:51:52.766590 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2855 06:51:52.770565 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2856 06:51:52.773137 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2857 06:51:52.776391 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2858 06:51:52.779573 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2859 06:51:52.786181 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2860 06:51:52.789715 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2861 06:51:52.793195 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2862 06:51:52.796389 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2863 06:51:52.799872 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2864 06:51:52.807418 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2865 06:51:52.807961 ==
2866 06:51:52.810235 Dram Type= 6, Freq= 0, CH_0, rank 1
2867 06:51:52.813302 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2868 06:51:52.813728 ==
2869 06:51:52.814063 DQS Delay:
2870 06:51:52.816106 DQS0 = 0, DQS1 = 0
2871 06:51:52.816525 DQM Delay:
2872 06:51:52.819763 DQM0 = 114, DQM1 = 105
2873 06:51:52.820187 DQ Delay:
2874 06:51:52.823381 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2875 06:51:52.828431 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =124
2876 06:51:52.829480 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2877 06:51:52.832945 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2878 06:51:52.833366
2879 06:51:52.833697
2880 06:51:52.843743 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2881 06:51:52.846248 CH0 RK1: MR19=404, MR18=E0E
2882 06:51:52.849413 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2883 06:51:52.853108 [RxdqsGatingPostProcess] freq 1200
2884 06:51:52.859209 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2885 06:51:52.863313 Pre-setting of DQS Precalculation
2886 06:51:52.866297 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2887 06:51:52.866720 ==
2888 06:51:52.869165 Dram Type= 6, Freq= 0, CH_1, rank 0
2889 06:51:52.876971 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2890 06:51:52.877654 ==
2891 06:51:52.879303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2892 06:51:52.886604 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2893 06:51:52.894806 [CA 0] Center 37 (7~68) winsize 62
2894 06:51:52.898822 [CA 1] Center 37 (7~68) winsize 62
2895 06:51:52.901342 [CA 2] Center 34 (4~65) winsize 62
2896 06:51:52.904891 [CA 3] Center 33 (3~64) winsize 62
2897 06:51:52.908326 [CA 4] Center 32 (1~63) winsize 63
2898 06:51:52.911467 [CA 5] Center 32 (2~63) winsize 62
2899 06:51:52.912217
2900 06:51:52.914422 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2901 06:51:52.915011
2902 06:51:52.917994 [CATrainingPosCal] consider 1 rank data
2903 06:51:52.922081 u2DelayCellTimex100 = 270/100 ps
2904 06:51:52.924598 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2905 06:51:52.928600 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2906 06:51:52.934663 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2907 06:51:52.938138 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2908 06:51:52.941639 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2909 06:51:52.945776 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2910 06:51:52.946257
2911 06:51:52.947824 CA PerBit enable=1, Macro0, CA PI delay=32
2912 06:51:52.948310
2913 06:51:52.951479 [CBTSetCACLKResult] CA Dly = 32
2914 06:51:52.952066 CS Dly: 6 (0~37)
2915 06:51:52.952564 ==
2916 06:51:52.954808 Dram Type= 6, Freq= 0, CH_1, rank 1
2917 06:51:52.961634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2918 06:51:52.962189 ==
2919 06:51:52.965266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2920 06:51:52.971679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2921 06:51:52.980133 [CA 0] Center 37 (7~68) winsize 62
2922 06:51:52.983319 [CA 1] Center 37 (7~68) winsize 62
2923 06:51:52.987216 [CA 2] Center 34 (3~65) winsize 63
2924 06:51:52.989691 [CA 3] Center 33 (3~64) winsize 62
2925 06:51:52.992996 [CA 4] Center 32 (2~63) winsize 62
2926 06:51:52.996595 [CA 5] Center 32 (1~63) winsize 63
2927 06:51:52.997129
2928 06:51:53.000068 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2929 06:51:53.000551
2930 06:51:53.003116 [CATrainingPosCal] consider 2 rank data
2931 06:51:53.007205 u2DelayCellTimex100 = 270/100 ps
2932 06:51:53.009775 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2933 06:51:53.016261 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2934 06:51:53.019831 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2935 06:51:53.022718 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2936 06:51:53.026372 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2937 06:51:53.029835 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2938 06:51:53.030401
2939 06:51:53.032580 CA PerBit enable=1, Macro0, CA PI delay=32
2940 06:51:53.033134
2941 06:51:53.036957 [CBTSetCACLKResult] CA Dly = 32
2942 06:51:53.037504 CS Dly: 6 (0~38)
2943 06:51:53.039650
2944 06:51:53.043473 ----->DramcWriteLeveling(PI) begin...
2945 06:51:53.044076 ==
2946 06:51:53.046394 Dram Type= 6, Freq= 0, CH_1, rank 0
2947 06:51:53.049405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2948 06:51:53.049835 ==
2949 06:51:53.053202 Write leveling (Byte 0): 22 => 22
2950 06:51:53.057063 Write leveling (Byte 1): 22 => 22
2951 06:51:53.059173 DramcWriteLeveling(PI) end<-----
2952 06:51:53.059601
2953 06:51:53.059939 ==
2954 06:51:53.062864 Dram Type= 6, Freq= 0, CH_1, rank 0
2955 06:51:53.066712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2956 06:51:53.067242 ==
2957 06:51:53.069923 [Gating] SW mode calibration
2958 06:51:53.075843 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2959 06:51:53.083873 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2960 06:51:53.086762 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2961 06:51:53.089210 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2962 06:51:53.096610 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2963 06:51:53.099916 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2964 06:51:53.102918 0 11 16 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (0 1)
2965 06:51:53.109689 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2966 06:51:53.112945 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2967 06:51:53.116252 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 06:51:53.119577 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2969 06:51:53.126676 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2970 06:51:53.129392 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 06:51:53.132513 0 12 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2972 06:51:53.140358 0 12 16 | B1->B0 | 2f2f 4343 | 0 0 | (1 1) (0 0)
2973 06:51:53.143081 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 06:51:53.146110 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 06:51:53.153014 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 06:51:53.156299 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 06:51:53.159665 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 06:51:53.165592 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 06:51:53.169354 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 06:51:53.172249 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2981 06:51:53.179196 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2982 06:51:53.182396 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2983 06:51:53.185610 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 06:51:53.192998 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 06:51:53.195793 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 06:51:53.199172 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 06:51:53.206281 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 06:51:53.209860 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 06:51:53.213075 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 06:51:53.219495 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 06:51:53.222814 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 06:51:53.226038 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 06:51:53.232294 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 06:51:53.235534 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 06:51:53.239119 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 06:51:53.246304 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2997 06:51:53.248868 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2998 06:51:53.253007 Total UI for P1: 0, mck2ui 16
2999 06:51:53.256123 best dqsien dly found for B0: ( 0, 15, 16)
3000 06:51:53.259546 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3001 06:51:53.262855 Total UI for P1: 0, mck2ui 16
3002 06:51:53.266225 best dqsien dly found for B1: ( 0, 15, 18)
3003 06:51:53.269209 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3004 06:51:53.272096 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3005 06:51:53.272563
3006 06:51:53.275945 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3007 06:51:53.282594 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3008 06:51:53.283167 [Gating] SW calibration Done
3009 06:51:53.283540 ==
3010 06:51:53.285743 Dram Type= 6, Freq= 0, CH_1, rank 0
3011 06:51:53.292526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3012 06:51:53.293103 ==
3013 06:51:53.293642 RX Vref Scan: 0
3014 06:51:53.294134
3015 06:51:53.295494 RX Vref 0 -> 0, step: 1
3016 06:51:53.295962
3017 06:51:53.299615 RX Delay -40 -> 252, step: 8
3018 06:51:53.302609 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3019 06:51:53.305844 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3020 06:51:53.309444 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3021 06:51:53.312741 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3022 06:51:53.319098 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3023 06:51:53.322003 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3024 06:51:53.325765 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3025 06:51:53.329255 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3026 06:51:53.332616 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3027 06:51:53.339182 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3028 06:51:53.342735 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3029 06:51:53.345669 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3030 06:51:53.348765 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3031 06:51:53.352142 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3032 06:51:53.359451 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3033 06:51:53.362863 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3034 06:51:53.363433 ==
3035 06:51:53.365251 Dram Type= 6, Freq= 0, CH_1, rank 0
3036 06:51:53.369056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3037 06:51:53.369627 ==
3038 06:51:53.372579 DQS Delay:
3039 06:51:53.373090 DQS0 = 0, DQS1 = 0
3040 06:51:53.373467 DQM Delay:
3041 06:51:53.375343 DQM0 = 116, DQM1 = 108
3042 06:51:53.375810 DQ Delay:
3043 06:51:53.379335 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3044 06:51:53.381850 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3045 06:51:53.385294 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3046 06:51:53.392032 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3047 06:51:53.392561
3048 06:51:53.392975
3049 06:51:53.393322 ==
3050 06:51:53.395271 Dram Type= 6, Freq= 0, CH_1, rank 0
3051 06:51:53.398876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3052 06:51:53.399452 ==
3053 06:51:53.399831
3054 06:51:53.400180
3055 06:51:53.402151 TX Vref Scan disable
3056 06:51:53.402620 == TX Byte 0 ==
3057 06:51:53.408962 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3058 06:51:53.411946 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3059 06:51:53.412416 == TX Byte 1 ==
3060 06:51:53.419063 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3061 06:51:53.421540 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3062 06:51:53.422014 ==
3063 06:51:53.426018 Dram Type= 6, Freq= 0, CH_1, rank 0
3064 06:51:53.428883 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3065 06:51:53.429357 ==
3066 06:51:53.440917 TX Vref=22, minBit 0, minWin=25, winSum=417
3067 06:51:53.444420 TX Vref=24, minBit 1, minWin=26, winSum=426
3068 06:51:53.447785 TX Vref=26, minBit 1, minWin=26, winSum=429
3069 06:51:53.452142 TX Vref=28, minBit 8, minWin=26, winSum=432
3070 06:51:53.454850 TX Vref=30, minBit 8, minWin=26, winSum=433
3071 06:51:53.457605 TX Vref=32, minBit 8, minWin=26, winSum=428
3072 06:51:53.464107 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
3073 06:51:53.464638
3074 06:51:53.467508 Final TX Range 1 Vref 30
3075 06:51:53.467978
3076 06:51:53.468349 ==
3077 06:51:53.470872 Dram Type= 6, Freq= 0, CH_1, rank 0
3078 06:51:53.474963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3079 06:51:53.475440 ==
3080 06:51:53.477811
3081 06:51:53.478276
3082 06:51:53.478647 TX Vref Scan disable
3083 06:51:53.481291 == TX Byte 0 ==
3084 06:51:53.484188 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3085 06:51:53.487789 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3086 06:51:53.493047 == TX Byte 1 ==
3087 06:51:53.494193 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3088 06:51:53.497586 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3089 06:51:53.498125
3090 06:51:53.500996 [DATLAT]
3091 06:51:53.501464 Freq=1200, CH1 RK0
3092 06:51:53.501839
3093 06:51:53.504288 DATLAT Default: 0xd
3094 06:51:53.504779 0, 0xFFFF, sum = 0
3095 06:51:53.507346 1, 0xFFFF, sum = 0
3096 06:51:53.507822 2, 0xFFFF, sum = 0
3097 06:51:53.510607 3, 0xFFFF, sum = 0
3098 06:51:53.511079 4, 0xFFFF, sum = 0
3099 06:51:53.514646 5, 0xFFFF, sum = 0
3100 06:51:53.515400 6, 0xFFFF, sum = 0
3101 06:51:53.517652 7, 0xFFFF, sum = 0
3102 06:51:53.518130 8, 0xFFFF, sum = 0
3103 06:51:53.521308 9, 0xFFFF, sum = 0
3104 06:51:53.524398 10, 0xFFFF, sum = 0
3105 06:51:53.524917 11, 0x0, sum = 1
3106 06:51:53.525414 12, 0x0, sum = 2
3107 06:51:53.527922 13, 0x0, sum = 3
3108 06:51:53.528397 14, 0x0, sum = 4
3109 06:51:53.531124 best_step = 12
3110 06:51:53.531682
3111 06:51:53.532203 ==
3112 06:51:53.534332 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 06:51:53.537352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3114 06:51:53.537827 ==
3115 06:51:53.541332 RX Vref Scan: 1
3116 06:51:53.541799
3117 06:51:53.542168 Set Vref Range= 32 -> 127
3118 06:51:53.542691
3119 06:51:53.544363 RX Vref 32 -> 127, step: 1
3120 06:51:53.544884
3121 06:51:53.548054 RX Delay -29 -> 252, step: 4
3122 06:51:53.548559
3123 06:51:53.551055 Set Vref, RX VrefLevel [Byte0]: 32
3124 06:51:53.554814 [Byte1]: 32
3125 06:51:53.555278
3126 06:51:53.557627 Set Vref, RX VrefLevel [Byte0]: 33
3127 06:51:53.560872 [Byte1]: 33
3128 06:51:53.565381
3129 06:51:53.565908 Set Vref, RX VrefLevel [Byte0]: 34
3130 06:51:53.568796 [Byte1]: 34
3131 06:51:53.573344
3132 06:51:53.573832 Set Vref, RX VrefLevel [Byte0]: 35
3133 06:51:53.576886 [Byte1]: 35
3134 06:51:53.581551
3135 06:51:53.582125 Set Vref, RX VrefLevel [Byte0]: 36
3136 06:51:53.584642 [Byte1]: 36
3137 06:51:53.589363
3138 06:51:53.589877 Set Vref, RX VrefLevel [Byte0]: 37
3139 06:51:53.592554 [Byte1]: 37
3140 06:51:53.597137
3141 06:51:53.597651 Set Vref, RX VrefLevel [Byte0]: 38
3142 06:51:53.600505 [Byte1]: 38
3143 06:51:53.605736
3144 06:51:53.606236 Set Vref, RX VrefLevel [Byte0]: 39
3145 06:51:53.609113 [Byte1]: 39
3146 06:51:53.614458
3147 06:51:53.614978 Set Vref, RX VrefLevel [Byte0]: 40
3148 06:51:53.616702 [Byte1]: 40
3149 06:51:53.621074
3150 06:51:53.621501 Set Vref, RX VrefLevel [Byte0]: 41
3151 06:51:53.624414 [Byte1]: 41
3152 06:51:53.628781
3153 06:51:53.629207 Set Vref, RX VrefLevel [Byte0]: 42
3154 06:51:53.632519 [Byte1]: 42
3155 06:51:53.636794
3156 06:51:53.637220 Set Vref, RX VrefLevel [Byte0]: 43
3157 06:51:53.643609 [Byte1]: 43
3158 06:51:53.644119
3159 06:51:53.646887 Set Vref, RX VrefLevel [Byte0]: 44
3160 06:51:53.650212 [Byte1]: 44
3161 06:51:53.650757
3162 06:51:53.654171 Set Vref, RX VrefLevel [Byte0]: 45
3163 06:51:53.656569 [Byte1]: 45
3164 06:51:53.660585
3165 06:51:53.661154 Set Vref, RX VrefLevel [Byte0]: 46
3166 06:51:53.663911 [Byte1]: 46
3167 06:51:53.670292
3168 06:51:53.670809 Set Vref, RX VrefLevel [Byte0]: 47
3169 06:51:53.672175 [Byte1]: 47
3170 06:51:53.676533
3171 06:51:53.677056 Set Vref, RX VrefLevel [Byte0]: 48
3172 06:51:53.680087 [Byte1]: 48
3173 06:51:53.685127
3174 06:51:53.685554 Set Vref, RX VrefLevel [Byte0]: 49
3175 06:51:53.687840 [Byte1]: 49
3176 06:51:53.693201
3177 06:51:53.693622 Set Vref, RX VrefLevel [Byte0]: 50
3178 06:51:53.695788 [Byte1]: 50
3179 06:51:53.701317
3180 06:51:53.701954 Set Vref, RX VrefLevel [Byte0]: 51
3181 06:51:53.704186 [Byte1]: 51
3182 06:51:53.708763
3183 06:51:53.709279 Set Vref, RX VrefLevel [Byte0]: 52
3184 06:51:53.712267 [Byte1]: 52
3185 06:51:53.716518
3186 06:51:53.717081 Set Vref, RX VrefLevel [Byte0]: 53
3187 06:51:53.720099 [Byte1]: 53
3188 06:51:53.725172
3189 06:51:53.725611 Set Vref, RX VrefLevel [Byte0]: 54
3190 06:51:53.728164 [Byte1]: 54
3191 06:51:53.732525
3192 06:51:53.733211 Set Vref, RX VrefLevel [Byte0]: 55
3193 06:51:53.736017 [Byte1]: 55
3194 06:51:53.740368
3195 06:51:53.740910 Set Vref, RX VrefLevel [Byte0]: 56
3196 06:51:53.744649 [Byte1]: 56
3197 06:51:53.749530
3198 06:51:53.750044 Set Vref, RX VrefLevel [Byte0]: 57
3199 06:51:53.752221 [Byte1]: 57
3200 06:51:53.756187
3201 06:51:53.756621 Set Vref, RX VrefLevel [Byte0]: 58
3202 06:51:53.759415 [Byte1]: 58
3203 06:51:53.764864
3204 06:51:53.765446 Set Vref, RX VrefLevel [Byte0]: 59
3205 06:51:53.768006 [Byte1]: 59
3206 06:51:53.771890
3207 06:51:53.775186 Set Vref, RX VrefLevel [Byte0]: 60
3208 06:51:53.775765 [Byte1]: 60
3209 06:51:53.780349
3210 06:51:53.780902 Set Vref, RX VrefLevel [Byte0]: 61
3211 06:51:53.783220 [Byte1]: 61
3212 06:51:53.787918
3213 06:51:53.788356 Set Vref, RX VrefLevel [Byte0]: 62
3214 06:51:53.791602 [Byte1]: 62
3215 06:51:53.796201
3216 06:51:53.796694 Set Vref, RX VrefLevel [Byte0]: 63
3217 06:51:53.799498 [Byte1]: 63
3218 06:51:53.805757
3219 06:51:53.806243 Set Vref, RX VrefLevel [Byte0]: 64
3220 06:51:53.807276 [Byte1]: 64
3221 06:51:53.812782
3222 06:51:53.813285 Set Vref, RX VrefLevel [Byte0]: 65
3223 06:51:53.815679 [Byte1]: 65
3224 06:51:53.820324
3225 06:51:53.820807 Set Vref, RX VrefLevel [Byte0]: 66
3226 06:51:53.824138 [Byte1]: 66
3227 06:51:53.828791
3228 06:51:53.829219 Set Vref, RX VrefLevel [Byte0]: 67
3229 06:51:53.831895 [Byte1]: 67
3230 06:51:53.835681
3231 06:51:53.836108 Final RX Vref Byte 0 = 56 to rank0
3232 06:51:53.838973 Final RX Vref Byte 1 = 49 to rank0
3233 06:51:53.842700 Final RX Vref Byte 0 = 56 to rank1
3234 06:51:53.845526 Final RX Vref Byte 1 = 49 to rank1==
3235 06:51:53.849378 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 06:51:53.855749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3237 06:51:53.856219 ==
3238 06:51:53.856588 DQS Delay:
3239 06:51:53.856995 DQS0 = 0, DQS1 = 0
3240 06:51:53.858963 DQM Delay:
3241 06:51:53.859442 DQM0 = 115, DQM1 = 105
3242 06:51:53.862893 DQ Delay:
3243 06:51:53.865803 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3244 06:51:53.869470 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3245 06:51:53.872661 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3246 06:51:53.876595 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3247 06:51:53.877178
3248 06:51:53.877555
3249 06:51:53.882818 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3250 06:51:53.886085 CH1 RK0: MR19=404, MR18=1A1A
3251 06:51:53.892927 CH1_RK0: MR19=0x404, MR18=0x1A1A, DQSOSC=400, MR23=63, INC=40, DEC=27
3252 06:51:53.893399
3253 06:51:53.895983 ----->DramcWriteLeveling(PI) begin...
3254 06:51:53.896457 ==
3255 06:51:53.899039 Dram Type= 6, Freq= 0, CH_1, rank 1
3256 06:51:53.902855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3257 06:51:53.903329 ==
3258 06:51:53.906039 Write leveling (Byte 0): 22 => 22
3259 06:51:53.909270 Write leveling (Byte 1): 22 => 22
3260 06:51:53.912849 DramcWriteLeveling(PI) end<-----
3261 06:51:53.913383
3262 06:51:53.913755 ==
3263 06:51:53.916042 Dram Type= 6, Freq= 0, CH_1, rank 1
3264 06:51:53.922282 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3265 06:51:53.922844 ==
3266 06:51:53.923216 [Gating] SW mode calibration
3267 06:51:53.932341 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3268 06:51:53.936048 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3269 06:51:53.939275 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3270 06:51:53.945850 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3271 06:51:53.949355 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3272 06:51:53.952241 0 11 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
3273 06:51:53.959106 0 11 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
3274 06:51:53.962720 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3275 06:51:53.966274 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3276 06:51:53.972085 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3277 06:51:53.975906 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3278 06:51:53.979854 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3279 06:51:53.985709 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3280 06:51:53.989321 0 12 12 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
3281 06:51:53.992448 0 12 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
3282 06:51:53.999373 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3283 06:51:54.002438 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3284 06:51:54.005671 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3285 06:51:54.012091 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 06:51:54.015416 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3287 06:51:54.019170 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3288 06:51:54.026698 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3289 06:51:54.030088 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3290 06:51:54.032920 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 06:51:54.035435 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 06:51:54.042181 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 06:51:54.045703 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 06:51:54.048908 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 06:51:54.056181 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 06:51:54.059289 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 06:51:54.062172 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 06:51:54.070659 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 06:51:54.072183 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 06:51:54.075248 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 06:51:54.082023 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 06:51:54.085733 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 06:51:54.089097 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 06:51:54.096257 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3305 06:51:54.098808 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3306 06:51:54.102393 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3307 06:51:54.105861 Total UI for P1: 0, mck2ui 16
3308 06:51:54.108970 best dqsien dly found for B0: ( 0, 15, 14)
3309 06:51:54.112146 Total UI for P1: 0, mck2ui 16
3310 06:51:54.115393 best dqsien dly found for B1: ( 0, 15, 16)
3311 06:51:54.119149 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3312 06:51:54.122637 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3313 06:51:54.123028
3314 06:51:54.125802 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3315 06:51:54.132217 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3316 06:51:54.132521 [Gating] SW calibration Done
3317 06:51:54.135412 ==
3318 06:51:54.138966 Dram Type= 6, Freq= 0, CH_1, rank 1
3319 06:51:54.142216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3320 06:51:54.142516 ==
3321 06:51:54.142754 RX Vref Scan: 0
3322 06:51:54.142978
3323 06:51:54.145734 RX Vref 0 -> 0, step: 1
3324 06:51:54.146033
3325 06:51:54.148801 RX Delay -40 -> 252, step: 8
3326 06:51:54.152328 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3327 06:51:54.155886 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
3328 06:51:54.158925 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3329 06:51:54.166014 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3330 06:51:54.168948 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3331 06:51:54.172830 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3332 06:51:54.175785 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3333 06:51:54.178351 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3334 06:51:54.185003 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3335 06:51:54.188825 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3336 06:51:54.191605 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3337 06:51:54.195584 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3338 06:51:54.199050 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3339 06:51:54.205383 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3340 06:51:54.208837 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3341 06:51:54.212194 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3342 06:51:54.212500 ==
3343 06:51:54.215832 Dram Type= 6, Freq= 0, CH_1, rank 1
3344 06:51:54.218770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3345 06:51:54.219136 ==
3346 06:51:54.221640 DQS Delay:
3347 06:51:54.221942 DQS0 = 0, DQS1 = 0
3348 06:51:54.225114 DQM Delay:
3349 06:51:54.225483 DQM0 = 116, DQM1 = 105
3350 06:51:54.229349 DQ Delay:
3351 06:51:54.232208 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3352 06:51:54.235176 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3353 06:51:54.239089 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3354 06:51:54.242196 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3355 06:51:54.242591
3356 06:51:54.242840
3357 06:51:54.243062 ==
3358 06:51:54.244451 Dram Type= 6, Freq= 0, CH_1, rank 1
3359 06:51:54.247964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3360 06:51:54.248333 ==
3361 06:51:54.248576
3362 06:51:54.248837
3363 06:51:54.251289 TX Vref Scan disable
3364 06:51:54.254675 == TX Byte 0 ==
3365 06:51:54.257888 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3366 06:51:54.261576 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3367 06:51:54.264837 == TX Byte 1 ==
3368 06:51:54.268110 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3369 06:51:54.272066 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3370 06:51:54.272428 ==
3371 06:51:54.275047 Dram Type= 6, Freq= 0, CH_1, rank 1
3372 06:51:54.278781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3373 06:51:54.282002 ==
3374 06:51:54.292039 TX Vref=22, minBit 9, minWin=25, winSum=422
3375 06:51:54.294538 TX Vref=24, minBit 0, minWin=26, winSum=427
3376 06:51:54.297957 TX Vref=26, minBit 9, minWin=25, winSum=426
3377 06:51:54.301655 TX Vref=28, minBit 3, minWin=26, winSum=432
3378 06:51:54.304523 TX Vref=30, minBit 9, minWin=26, winSum=433
3379 06:51:54.307875 TX Vref=32, minBit 0, minWin=26, winSum=428
3380 06:51:54.315210 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3381 06:51:54.315750
3382 06:51:54.317970 Final TX Range 1 Vref 30
3383 06:51:54.318429
3384 06:51:54.318927 ==
3385 06:51:54.321346 Dram Type= 6, Freq= 0, CH_1, rank 1
3386 06:51:54.324828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3387 06:51:54.325317 ==
3388 06:51:54.325806
3389 06:51:54.328304
3390 06:51:54.328845 TX Vref Scan disable
3391 06:51:54.331848 == TX Byte 0 ==
3392 06:51:54.334868 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3393 06:51:54.338349 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3394 06:51:54.341240 == TX Byte 1 ==
3395 06:51:54.344590 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3396 06:51:54.348020 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3397 06:51:54.348594
3398 06:51:54.351202 [DATLAT]
3399 06:51:54.351688 Freq=1200, CH1 RK1
3400 06:51:54.352185
3401 06:51:54.356370 DATLAT Default: 0xc
3402 06:51:54.356984 0, 0xFFFF, sum = 0
3403 06:51:54.357857 1, 0xFFFF, sum = 0
3404 06:51:54.358390 2, 0xFFFF, sum = 0
3405 06:51:54.361213 3, 0xFFFF, sum = 0
3406 06:51:54.361688 4, 0xFFFF, sum = 0
3407 06:51:54.364556 5, 0xFFFF, sum = 0
3408 06:51:54.365058 6, 0xFFFF, sum = 0
3409 06:51:54.367890 7, 0xFFFF, sum = 0
3410 06:51:54.368364 8, 0xFFFF, sum = 0
3411 06:51:54.371807 9, 0xFFFF, sum = 0
3412 06:51:54.375615 10, 0xFFFF, sum = 0
3413 06:51:54.376096 11, 0x0, sum = 1
3414 06:51:54.376475 12, 0x0, sum = 2
3415 06:51:54.378533 13, 0x0, sum = 3
3416 06:51:54.379105 14, 0x0, sum = 4
3417 06:51:54.381234 best_step = 12
3418 06:51:54.381700
3419 06:51:54.382070 ==
3420 06:51:54.384668 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 06:51:54.388918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3422 06:51:54.389489 ==
3423 06:51:54.391559 RX Vref Scan: 0
3424 06:51:54.392118
3425 06:51:54.392492 RX Vref 0 -> 0, step: 1
3426 06:51:54.392880
3427 06:51:54.394242 RX Delay -29 -> 252, step: 4
3428 06:51:54.401239 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3429 06:51:54.405425 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3430 06:51:54.408954 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3431 06:51:54.411908 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3432 06:51:54.414709 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3433 06:51:54.421567 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3434 06:51:54.425074 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3435 06:51:54.428266 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3436 06:51:54.431750 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3437 06:51:54.435145 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3438 06:51:54.442427 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3439 06:51:54.444524 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3440 06:51:54.448145 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3441 06:51:54.451802 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3442 06:51:54.454761 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3443 06:51:54.461419 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3444 06:51:54.461967 ==
3445 06:51:54.464689 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 06:51:54.468133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3447 06:51:54.468606 ==
3448 06:51:54.469042 DQS Delay:
3449 06:51:54.471624 DQS0 = 0, DQS1 = 0
3450 06:51:54.472094 DQM Delay:
3451 06:51:54.475242 DQM0 = 114, DQM1 = 103
3452 06:51:54.475807 DQ Delay:
3453 06:51:54.477845 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =112
3454 06:51:54.481827 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3455 06:51:54.484659 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3456 06:51:54.488340 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3457 06:51:54.488927
3458 06:51:54.489312
3459 06:51:54.498537 [DQSOSCAuto] RK1, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3460 06:51:54.501492 CH1 RK1: MR19=404, MR18=606
3461 06:51:54.504928 CH1_RK1: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
3462 06:51:54.508105 [RxdqsGatingPostProcess] freq 1200
3463 06:51:54.515227 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3464 06:51:54.518165 Pre-setting of DQS Precalculation
3465 06:51:54.521384 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3466 06:51:54.531949 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3467 06:51:54.539065 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3468 06:51:54.539625
3469 06:51:54.539995
3470 06:51:54.542255 [Calibration Summary] 2400 Mbps
3471 06:51:54.542817 CH 0, Rank 0
3472 06:51:54.546273 SW Impedance : PASS
3473 06:51:54.546841 DUTY Scan : NO K
3474 06:51:54.548820 ZQ Calibration : PASS
3475 06:51:54.551574 Jitter Meter : NO K
3476 06:51:54.552039 CBT Training : PASS
3477 06:51:54.554837 Write leveling : PASS
3478 06:51:54.555318 RX DQS gating : PASS
3479 06:51:54.558304 RX DQ/DQS(RDDQC) : PASS
3480 06:51:54.561416 TX DQ/DQS : PASS
3481 06:51:54.561880 RX DATLAT : PASS
3482 06:51:54.564582 RX DQ/DQS(Engine): PASS
3483 06:51:54.568674 TX OE : NO K
3484 06:51:54.569389 All Pass.
3485 06:51:54.569807
3486 06:51:54.570155 CH 0, Rank 1
3487 06:51:54.571391 SW Impedance : PASS
3488 06:51:54.574919 DUTY Scan : NO K
3489 06:51:54.575574 ZQ Calibration : PASS
3490 06:51:54.577995 Jitter Meter : NO K
3491 06:51:54.581816 CBT Training : PASS
3492 06:51:54.582275 Write leveling : PASS
3493 06:51:54.584753 RX DQS gating : PASS
3494 06:51:54.587798 RX DQ/DQS(RDDQC) : PASS
3495 06:51:54.588260 TX DQ/DQS : PASS
3496 06:51:54.591250 RX DATLAT : PASS
3497 06:51:54.594627 RX DQ/DQS(Engine): PASS
3498 06:51:54.595087 TX OE : NO K
3499 06:51:54.597817 All Pass.
3500 06:51:54.598368
3501 06:51:54.598755 CH 1, Rank 0
3502 06:51:54.601491 SW Impedance : PASS
3503 06:51:54.601950 DUTY Scan : NO K
3504 06:51:54.604322 ZQ Calibration : PASS
3505 06:51:54.607967 Jitter Meter : NO K
3506 06:51:54.608426 CBT Training : PASS
3507 06:51:54.611858 Write leveling : PASS
3508 06:51:54.615140 RX DQS gating : PASS
3509 06:51:54.615699 RX DQ/DQS(RDDQC) : PASS
3510 06:51:54.617805 TX DQ/DQS : PASS
3511 06:51:54.618267 RX DATLAT : PASS
3512 06:51:54.621196 RX DQ/DQS(Engine): PASS
3513 06:51:54.624954 TX OE : NO K
3514 06:51:54.625507 All Pass.
3515 06:51:54.625883
3516 06:51:54.626254 CH 1, Rank 1
3517 06:51:54.627840 SW Impedance : PASS
3518 06:51:54.631027 DUTY Scan : NO K
3519 06:51:54.631496 ZQ Calibration : PASS
3520 06:51:54.635248 Jitter Meter : NO K
3521 06:51:54.638243 CBT Training : PASS
3522 06:51:54.638812 Write leveling : PASS
3523 06:51:54.641419 RX DQS gating : PASS
3524 06:51:54.644596 RX DQ/DQS(RDDQC) : PASS
3525 06:51:54.645110 TX DQ/DQS : PASS
3526 06:51:54.647332 RX DATLAT : PASS
3527 06:51:54.651028 RX DQ/DQS(Engine): PASS
3528 06:51:54.651560 TX OE : NO K
3529 06:51:54.655100 All Pass.
3530 06:51:54.655716
3531 06:51:54.656153 DramC Write-DBI off
3532 06:51:54.658835 PER_BANK_REFRESH: Hybrid Mode
3533 06:51:54.659479 TX_TRACKING: ON
3534 06:51:54.667650 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3535 06:51:54.671036 [FAST_K] Save calibration result to emmc
3536 06:51:54.674826 dramc_set_vcore_voltage set vcore to 650000
3537 06:51:54.677810 Read voltage for 600, 5
3538 06:51:54.678269 Vio18 = 0
3539 06:51:54.681739 Vcore = 650000
3540 06:51:54.682298 Vdram = 0
3541 06:51:54.682668 Vddq = 0
3542 06:51:54.683011 Vmddr = 0
3543 06:51:54.687518 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3544 06:51:54.695601 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3545 06:51:54.696204 MEM_TYPE=3, freq_sel=19
3546 06:51:54.697398 sv_algorithm_assistance_LP4_1600
3547 06:51:54.701047 ============ PULL DRAM RESETB DOWN ============
3548 06:51:54.707467 ========== PULL DRAM RESETB DOWN end =========
3549 06:51:54.711081 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3550 06:51:54.714519 ===================================
3551 06:51:54.717642 LPDDR4 DRAM CONFIGURATION
3552 06:51:54.720763 ===================================
3553 06:51:54.721229 EX_ROW_EN[0] = 0x0
3554 06:51:54.723980 EX_ROW_EN[1] = 0x0
3555 06:51:54.724440 LP4Y_EN = 0x0
3556 06:51:54.727796 WORK_FSP = 0x0
3557 06:51:54.728259 WL = 0x2
3558 06:51:54.730814 RL = 0x2
3559 06:51:54.734261 BL = 0x2
3560 06:51:54.734723 RPST = 0x0
3561 06:51:54.737283 RD_PRE = 0x0
3562 06:51:54.737743 WR_PRE = 0x1
3563 06:51:54.741208 WR_PST = 0x0
3564 06:51:54.741738 DBI_WR = 0x0
3565 06:51:54.743981 DBI_RD = 0x0
3566 06:51:54.744441 OTF = 0x1
3567 06:51:54.747961 ===================================
3568 06:51:54.750708 ===================================
3569 06:51:54.754017 ANA top config
3570 06:51:54.757165 ===================================
3571 06:51:54.757636 DLL_ASYNC_EN = 0
3572 06:51:54.760935 ALL_SLAVE_EN = 1
3573 06:51:54.763571 NEW_RANK_MODE = 1
3574 06:51:54.767143 DLL_IDLE_MODE = 1
3575 06:51:54.767608 LP45_APHY_COMB_EN = 1
3576 06:51:54.770223 TX_ODT_DIS = 1
3577 06:51:54.774501 NEW_8X_MODE = 1
3578 06:51:54.777631 ===================================
3579 06:51:54.780308 ===================================
3580 06:51:54.783680 data_rate = 1200
3581 06:51:54.786877 CKR = 1
3582 06:51:54.790266 DQ_P2S_RATIO = 8
3583 06:51:54.793772 ===================================
3584 06:51:54.794243 CA_P2S_RATIO = 8
3585 06:51:54.796880 DQ_CA_OPEN = 0
3586 06:51:54.800010 DQ_SEMI_OPEN = 0
3587 06:51:54.803322 CA_SEMI_OPEN = 0
3588 06:51:54.806672 CA_FULL_RATE = 0
3589 06:51:54.810296 DQ_CKDIV4_EN = 1
3590 06:51:54.810775 CA_CKDIV4_EN = 1
3591 06:51:54.813482 CA_PREDIV_EN = 0
3592 06:51:54.816988 PH8_DLY = 0
3593 06:51:54.820304 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3594 06:51:54.822969 DQ_AAMCK_DIV = 4
3595 06:51:54.826578 CA_AAMCK_DIV = 4
3596 06:51:54.827150 CA_ADMCK_DIV = 4
3597 06:51:54.829856 DQ_TRACK_CA_EN = 0
3598 06:51:54.833374 CA_PICK = 600
3599 06:51:54.836517 CA_MCKIO = 600
3600 06:51:54.839665 MCKIO_SEMI = 0
3601 06:51:54.843153 PLL_FREQ = 2288
3602 06:51:54.846718 DQ_UI_PI_RATIO = 32
3603 06:51:54.847283 CA_UI_PI_RATIO = 0
3604 06:51:54.849894 ===================================
3605 06:51:54.853238 ===================================
3606 06:51:54.856777 memory_type:LPDDR4
3607 06:51:54.860500 GP_NUM : 10
3608 06:51:54.861004 SRAM_EN : 1
3609 06:51:54.863406 MD32_EN : 0
3610 06:51:54.866167 ===================================
3611 06:51:54.870161 [ANA_INIT] >>>>>>>>>>>>>>
3612 06:51:54.873154 <<<<<< [CONFIGURE PHASE]: ANA_TX
3613 06:51:54.876155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3614 06:51:54.879657 ===================================
3615 06:51:54.880127 data_rate = 1200,PCW = 0X5800
3616 06:51:54.882813 ===================================
3617 06:51:54.886794 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3618 06:51:54.892662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3619 06:51:54.899840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3620 06:51:54.902918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3621 06:51:54.906630 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3622 06:51:54.909395 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3623 06:51:54.913806 [ANA_INIT] flow start
3624 06:51:54.916668 [ANA_INIT] PLL >>>>>>>>
3625 06:51:54.917204 [ANA_INIT] PLL <<<<<<<<
3626 06:51:54.919355 [ANA_INIT] MIDPI >>>>>>>>
3627 06:51:54.922766 [ANA_INIT] MIDPI <<<<<<<<
3628 06:51:54.923304 [ANA_INIT] DLL >>>>>>>>
3629 06:51:54.925972 [ANA_INIT] flow end
3630 06:51:54.929175 ============ LP4 DIFF to SE enter ============
3631 06:51:54.932540 ============ LP4 DIFF to SE exit ============
3632 06:51:54.935700 [ANA_INIT] <<<<<<<<<<<<<
3633 06:51:54.939256 [Flow] Enable top DCM control >>>>>
3634 06:51:54.942678 [Flow] Enable top DCM control <<<<<
3635 06:51:54.946009 Enable DLL master slave shuffle
3636 06:51:54.952415 ==============================================================
3637 06:51:54.953096 Gating Mode config
3638 06:51:54.959086 ==============================================================
3639 06:51:54.962593 Config description:
3640 06:51:54.969524 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3641 06:51:54.975852 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3642 06:51:54.982629 SELPH_MODE 0: By rank 1: By Phase
3643 06:51:54.986263 ==============================================================
3644 06:51:54.989029 GAT_TRACK_EN = 1
3645 06:51:54.992528 RX_GATING_MODE = 2
3646 06:51:54.995792 RX_GATING_TRACK_MODE = 2
3647 06:51:54.999817 SELPH_MODE = 1
3648 06:51:55.002582 PICG_EARLY_EN = 1
3649 06:51:55.006103 VALID_LAT_VALUE = 1
3650 06:51:55.012290 ==============================================================
3651 06:51:55.015650 Enter into Gating configuration >>>>
3652 06:51:55.018870 Exit from Gating configuration <<<<
3653 06:51:55.022787 Enter into DVFS_PRE_config >>>>>
3654 06:51:55.032251 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3655 06:51:55.035667 Exit from DVFS_PRE_config <<<<<
3656 06:51:55.038567 Enter into PICG configuration >>>>
3657 06:51:55.041735 Exit from PICG configuration <<<<
3658 06:51:55.045450 [RX_INPUT] configuration >>>>>
3659 06:51:55.046093 [RX_INPUT] configuration <<<<<
3660 06:51:55.052208 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3661 06:51:55.058848 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3662 06:51:55.062079 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3663 06:51:55.069248 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3664 06:51:55.075689 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3665 06:51:55.082212 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3666 06:51:55.085085 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3667 06:51:55.088216 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3668 06:51:55.095073 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3669 06:51:55.098788 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3670 06:51:55.101961 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3671 06:51:55.108569 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3672 06:51:55.111829 ===================================
3673 06:51:55.112584 LPDDR4 DRAM CONFIGURATION
3674 06:51:55.115457 ===================================
3675 06:51:55.118712 EX_ROW_EN[0] = 0x0
3676 06:51:55.119456 EX_ROW_EN[1] = 0x0
3677 06:51:55.121851 LP4Y_EN = 0x0
3678 06:51:55.125920 WORK_FSP = 0x0
3679 06:51:55.126620 WL = 0x2
3680 06:51:55.128374 RL = 0x2
3681 06:51:55.129018 BL = 0x2
3682 06:51:55.131730 RPST = 0x0
3683 06:51:55.132380 RD_PRE = 0x0
3684 06:51:55.134603 WR_PRE = 0x1
3685 06:51:55.135181 WR_PST = 0x0
3686 06:51:55.138091 DBI_WR = 0x0
3687 06:51:55.138559 DBI_RD = 0x0
3688 06:51:55.141983 OTF = 0x1
3689 06:51:55.144817 ===================================
3690 06:51:55.148176 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3691 06:51:55.151710 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3692 06:51:55.158485 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3693 06:51:55.161839 ===================================
3694 06:51:55.162415 LPDDR4 DRAM CONFIGURATION
3695 06:51:55.164836 ===================================
3696 06:51:55.168250 EX_ROW_EN[0] = 0x10
3697 06:51:55.168882 EX_ROW_EN[1] = 0x0
3698 06:51:55.171646 LP4Y_EN = 0x0
3699 06:51:55.172113 WORK_FSP = 0x0
3700 06:51:55.174524 WL = 0x2
3701 06:51:55.178000 RL = 0x2
3702 06:51:55.178471 BL = 0x2
3703 06:51:55.181347 RPST = 0x0
3704 06:51:55.181913 RD_PRE = 0x0
3705 06:51:55.184480 WR_PRE = 0x1
3706 06:51:55.185070 WR_PST = 0x0
3707 06:51:55.187914 DBI_WR = 0x0
3708 06:51:55.188485 DBI_RD = 0x0
3709 06:51:55.191801 OTF = 0x1
3710 06:51:55.194575 ===================================
3711 06:51:55.200841 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3712 06:51:55.204694 nWR fixed to 30
3713 06:51:55.205321 [ModeRegInit_LP4] CH0 RK0
3714 06:51:55.207503 [ModeRegInit_LP4] CH0 RK1
3715 06:51:55.211124 [ModeRegInit_LP4] CH1 RK0
3716 06:51:55.211694 [ModeRegInit_LP4] CH1 RK1
3717 06:51:55.214439 match AC timing 16
3718 06:51:55.217984 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3719 06:51:55.220908 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3720 06:51:55.228112 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3721 06:51:55.231447 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3722 06:51:55.237865 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3723 06:51:55.238338 ==
3724 06:51:55.241369 Dram Type= 6, Freq= 0, CH_0, rank 0
3725 06:51:55.243512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3726 06:51:55.243985 ==
3727 06:51:55.250266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3728 06:51:55.256870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3729 06:51:55.260809 [CA 0] Center 35 (5~66) winsize 62
3730 06:51:55.263675 [CA 1] Center 35 (5~66) winsize 62
3731 06:51:55.266792 [CA 2] Center 34 (4~65) winsize 62
3732 06:51:55.270288 [CA 3] Center 34 (4~65) winsize 62
3733 06:51:55.273332 [CA 4] Center 33 (3~64) winsize 62
3734 06:51:55.277472 [CA 5] Center 33 (3~64) winsize 62
3735 06:51:55.278144
3736 06:51:55.280160 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3737 06:51:55.280627
3738 06:51:55.283499 [CATrainingPosCal] consider 1 rank data
3739 06:51:55.287458 u2DelayCellTimex100 = 270/100 ps
3740 06:51:55.290031 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3741 06:51:55.293705 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3742 06:51:55.297016 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3743 06:51:55.300368 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3744 06:51:55.303719 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3745 06:51:55.306764 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3746 06:51:55.307232
3747 06:51:55.313374 CA PerBit enable=1, Macro0, CA PI delay=33
3748 06:51:55.313938
3749 06:51:55.314327 [CBTSetCACLKResult] CA Dly = 33
3750 06:51:55.316945 CS Dly: 4 (0~35)
3751 06:51:55.317413 ==
3752 06:51:55.319826 Dram Type= 6, Freq= 0, CH_0, rank 1
3753 06:51:55.323847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3754 06:51:55.324421 ==
3755 06:51:55.330046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3756 06:51:55.337650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3757 06:51:55.339799 [CA 0] Center 35 (5~66) winsize 62
3758 06:51:55.343308 [CA 1] Center 35 (5~66) winsize 62
3759 06:51:55.347230 [CA 2] Center 34 (4~65) winsize 62
3760 06:51:55.350015 [CA 3] Center 34 (4~65) winsize 62
3761 06:51:55.352941 [CA 4] Center 33 (3~64) winsize 62
3762 06:51:55.356239 [CA 5] Center 33 (3~64) winsize 62
3763 06:51:55.356737
3764 06:51:55.360292 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3765 06:51:55.361054
3766 06:51:55.363322 [CATrainingPosCal] consider 2 rank data
3767 06:51:55.366850 u2DelayCellTimex100 = 270/100 ps
3768 06:51:55.369742 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3769 06:51:55.372886 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3770 06:51:55.376912 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3771 06:51:55.379897 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3772 06:51:55.383091 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3773 06:51:55.390370 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3774 06:51:55.390905
3775 06:51:55.393405 CA PerBit enable=1, Macro0, CA PI delay=33
3776 06:51:55.393875
3777 06:51:55.396367 [CBTSetCACLKResult] CA Dly = 33
3778 06:51:55.396871 CS Dly: 5 (0~37)
3779 06:51:55.397248
3780 06:51:55.400063 ----->DramcWriteLeveling(PI) begin...
3781 06:51:55.400631 ==
3782 06:51:55.403119 Dram Type= 6, Freq= 0, CH_0, rank 0
3783 06:51:55.405968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3784 06:51:55.409223 ==
3785 06:51:55.412811 Write leveling (Byte 0): 31 => 31
3786 06:51:55.413282 Write leveling (Byte 1): 29 => 29
3787 06:51:55.415927 DramcWriteLeveling(PI) end<-----
3788 06:51:55.416399
3789 06:51:55.417074 ==
3790 06:51:55.419315 Dram Type= 6, Freq= 0, CH_0, rank 0
3791 06:51:55.425733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3792 06:51:55.426207 ==
3793 06:51:55.429462 [Gating] SW mode calibration
3794 06:51:55.435966 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3795 06:51:55.439118 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3796 06:51:55.445464 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3797 06:51:55.448942 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3798 06:51:55.452141 0 5 8 | B1->B0 | 3232 3131 | 0 0 | (0 1) (0 1)
3799 06:51:55.458601 0 5 12 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
3800 06:51:55.462117 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3801 06:51:55.466099 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3802 06:51:55.472810 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3803 06:51:55.476058 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3804 06:51:55.479036 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3805 06:51:55.485675 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3806 06:51:55.488567 0 6 8 | B1->B0 | 2f2f 3333 | 0 0 | (0 0) (1 1)
3807 06:51:55.492314 0 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3808 06:51:55.495549 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3809 06:51:55.501899 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3810 06:51:55.506222 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3811 06:51:55.509256 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3812 06:51:55.515717 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3813 06:51:55.518681 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3814 06:51:55.522006 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3815 06:51:55.528645 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 06:51:55.532196 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 06:51:55.535108 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 06:51:55.541987 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 06:51:55.545568 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 06:51:55.549228 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 06:51:55.555818 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 06:51:55.558661 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 06:51:55.561595 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 06:51:55.568408 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 06:51:55.572077 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 06:51:55.574783 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 06:51:55.581777 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 06:51:55.585399 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 06:51:55.588153 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 06:51:55.595311 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3831 06:51:55.598101 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3832 06:51:55.601705 Total UI for P1: 0, mck2ui 16
3833 06:51:55.605055 best dqsien dly found for B0: ( 0, 9, 8)
3834 06:51:55.608283 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3835 06:51:55.612332 Total UI for P1: 0, mck2ui 16
3836 06:51:55.615146 best dqsien dly found for B1: ( 0, 9, 12)
3837 06:51:55.618572 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3838 06:51:55.620991 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
3839 06:51:55.621463
3840 06:51:55.628401 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3841 06:51:55.631480 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
3842 06:51:55.631965 [Gating] SW calibration Done
3843 06:51:55.634469 ==
3844 06:51:55.638344 Dram Type= 6, Freq= 0, CH_0, rank 0
3845 06:51:55.642092 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3846 06:51:55.642564 ==
3847 06:51:55.642937 RX Vref Scan: 0
3848 06:51:55.643285
3849 06:51:55.644839 RX Vref 0 -> 0, step: 1
3850 06:51:55.645305
3851 06:51:55.647881 RX Delay -230 -> 252, step: 16
3852 06:51:55.651745 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3853 06:51:55.654477 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3854 06:51:55.662149 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3855 06:51:55.664546 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3856 06:51:55.667688 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3857 06:51:55.671739 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3858 06:51:55.677966 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3859 06:51:55.680796 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3860 06:51:55.684857 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3861 06:51:55.689431 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3862 06:51:55.694222 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3863 06:51:55.698057 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3864 06:51:55.700521 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3865 06:51:55.703674 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3866 06:51:55.710182 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3867 06:51:55.714630 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3868 06:51:55.715185 ==
3869 06:51:55.717021 Dram Type= 6, Freq= 0, CH_0, rank 0
3870 06:51:55.721436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3871 06:51:55.721903 ==
3872 06:51:55.724452 DQS Delay:
3873 06:51:55.725000 DQS0 = 0, DQS1 = 0
3874 06:51:55.725379 DQM Delay:
3875 06:51:55.727141 DQM0 = 38, DQM1 = 33
3876 06:51:55.727604 DQ Delay:
3877 06:51:55.730463 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3878 06:51:55.733266 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3879 06:51:55.737135 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3880 06:51:55.739890 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3881 06:51:55.740325
3882 06:51:55.740913
3883 06:51:55.741278 ==
3884 06:51:55.744332 Dram Type= 6, Freq= 0, CH_0, rank 0
3885 06:51:55.750251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3886 06:51:55.750804 ==
3887 06:51:55.751176
3888 06:51:55.751515
3889 06:51:55.751866 TX Vref Scan disable
3890 06:51:55.754076 == TX Byte 0 ==
3891 06:51:55.756836 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3892 06:51:55.763056 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3893 06:51:55.763583 == TX Byte 1 ==
3894 06:51:55.766761 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3895 06:51:55.773495 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3896 06:51:55.774016 ==
3897 06:51:55.776617 Dram Type= 6, Freq= 0, CH_0, rank 0
3898 06:51:55.779975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3899 06:51:55.780453 ==
3900 06:51:55.780970
3901 06:51:55.781344
3902 06:51:55.783567 TX Vref Scan disable
3903 06:51:55.786332 == TX Byte 0 ==
3904 06:51:55.790038 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3905 06:51:55.793329 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3906 06:51:55.796990 == TX Byte 1 ==
3907 06:51:55.799714 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3908 06:51:55.803363 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3909 06:51:55.803975
3910 06:51:55.804377 [DATLAT]
3911 06:51:55.806927 Freq=600, CH0 RK0
3912 06:51:55.807536
3913 06:51:55.810077 DATLAT Default: 0x9
3914 06:51:55.810593 0, 0xFFFF, sum = 0
3915 06:51:55.813482 1, 0xFFFF, sum = 0
3916 06:51:55.814009 2, 0xFFFF, sum = 0
3917 06:51:55.816480 3, 0xFFFF, sum = 0
3918 06:51:55.817113 4, 0xFFFF, sum = 0
3919 06:51:55.820345 5, 0xFFFF, sum = 0
3920 06:51:55.821004 6, 0xFFFF, sum = 0
3921 06:51:55.823222 7, 0x0, sum = 1
3922 06:51:55.823690 8, 0x0, sum = 2
3923 06:51:55.824125 9, 0x0, sum = 3
3924 06:51:55.826407 10, 0x0, sum = 4
3925 06:51:55.826967 best_step = 8
3926 06:51:55.827366
3927 06:51:55.830258 ==
3928 06:51:55.830893 Dram Type= 6, Freq= 0, CH_0, rank 0
3929 06:51:55.836430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3930 06:51:55.837225 ==
3931 06:51:55.837779 RX Vref Scan: 1
3932 06:51:55.838142
3933 06:51:55.839473 RX Vref 0 -> 0, step: 1
3934 06:51:55.839933
3935 06:51:55.843355 RX Delay -195 -> 252, step: 8
3936 06:51:55.843962
3937 06:51:55.846032 Set Vref, RX VrefLevel [Byte0]: 46
3938 06:51:55.849425 [Byte1]: 49
3939 06:51:55.849886
3940 06:51:55.853974 Final RX Vref Byte 0 = 46 to rank0
3941 06:51:55.856212 Final RX Vref Byte 1 = 49 to rank0
3942 06:51:55.859415 Final RX Vref Byte 0 = 46 to rank1
3943 06:51:55.863102 Final RX Vref Byte 1 = 49 to rank1==
3944 06:51:55.866770 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 06:51:55.869524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3946 06:51:55.869990 ==
3947 06:51:55.872520 DQS Delay:
3948 06:51:55.873092 DQS0 = 0, DQS1 = 0
3949 06:51:55.875963 DQM Delay:
3950 06:51:55.876422 DQM0 = 40, DQM1 = 30
3951 06:51:55.876892 DQ Delay:
3952 06:51:55.879455 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
3953 06:51:55.882967 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
3954 06:51:55.885920 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3955 06:51:55.889492 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3956 06:51:55.890020
3957 06:51:55.893222
3958 06:51:55.899050 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
3959 06:51:55.903240 CH0 RK0: MR19=808, MR18=5D5D
3960 06:51:55.909293 CH0_RK0: MR19=0x808, MR18=0x5D5D, DQSOSC=392, MR23=63, INC=170, DEC=113
3961 06:51:55.909760
3962 06:51:55.912631 ----->DramcWriteLeveling(PI) begin...
3963 06:51:55.913232 ==
3964 06:51:55.916697 Dram Type= 6, Freq= 0, CH_0, rank 1
3965 06:51:55.919519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3966 06:51:55.920128 ==
3967 06:51:55.922729 Write leveling (Byte 0): 30 => 30
3968 06:51:55.926754 Write leveling (Byte 1): 29 => 29
3969 06:51:55.929228 DramcWriteLeveling(PI) end<-----
3970 06:51:55.929733
3971 06:51:55.930104 ==
3972 06:51:55.932425 Dram Type= 6, Freq= 0, CH_0, rank 1
3973 06:51:55.935846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3974 06:51:55.936340 ==
3975 06:51:55.939192 [Gating] SW mode calibration
3976 06:51:55.945626 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3977 06:51:55.952808 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3978 06:51:55.955853 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 06:51:55.958727 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 06:51:55.965801 0 5 8 | B1->B0 | 3333 3030 | 0 0 | (0 1) (1 1)
3981 06:51:55.968626 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3982 06:51:55.972181 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 06:51:55.979595 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 06:51:55.982326 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 06:51:55.985451 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 06:51:55.992036 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 06:51:55.995492 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 06:51:55.999040 0 6 8 | B1->B0 | 3030 3131 | 0 0 | (1 1) (0 0)
3989 06:51:56.005407 0 6 12 | B1->B0 | 4545 4545 | 1 0 | (0 0) (0 0)
3990 06:51:56.008941 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 06:51:56.011999 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 06:51:56.018805 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 06:51:56.021656 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 06:51:56.025183 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 06:51:56.032771 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 06:51:56.035328 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3997 06:51:56.038805 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 06:51:56.045095 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 06:51:56.049072 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 06:51:56.051526 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 06:51:56.058525 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 06:51:56.061602 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 06:51:56.065193 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 06:51:56.071898 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 06:51:56.075117 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 06:51:56.079430 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 06:51:56.085125 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 06:51:56.088466 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 06:51:56.091629 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 06:51:56.099026 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 06:51:56.101145 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 06:51:56.105243 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4013 06:51:56.108449 Total UI for P1: 0, mck2ui 16
4014 06:51:56.110967 best dqsien dly found for B0: ( 0, 9, 6)
4015 06:51:56.118333 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 06:51:56.118881 Total UI for P1: 0, mck2ui 16
4017 06:51:56.121903 best dqsien dly found for B1: ( 0, 9, 8)
4018 06:51:56.127441 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4019 06:51:56.131399 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4020 06:51:56.131990
4021 06:51:56.134208 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4022 06:51:56.137215 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4023 06:51:56.141048 [Gating] SW calibration Done
4024 06:51:56.141552 ==
4025 06:51:56.144060 Dram Type= 6, Freq= 0, CH_0, rank 1
4026 06:51:56.147871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4027 06:51:56.148468 ==
4028 06:51:56.150789 RX Vref Scan: 0
4029 06:51:56.151264
4030 06:51:56.151746 RX Vref 0 -> 0, step: 1
4031 06:51:56.152199
4032 06:51:56.154462 RX Delay -230 -> 252, step: 16
4033 06:51:56.158083 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4034 06:51:56.164028 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4035 06:51:56.167154 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4036 06:51:56.171084 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4037 06:51:56.175695 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4038 06:51:56.178106 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4039 06:51:56.184165 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4040 06:51:56.187225 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4041 06:51:56.191433 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4042 06:51:56.194018 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4043 06:51:56.200587 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4044 06:51:56.204047 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4045 06:51:56.207694 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4046 06:51:56.210819 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4047 06:51:56.217079 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4048 06:51:56.220799 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4049 06:51:56.221282 ==
4050 06:51:56.223637 Dram Type= 6, Freq= 0, CH_0, rank 1
4051 06:51:56.228031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4052 06:51:56.228689 ==
4053 06:51:56.230795 DQS Delay:
4054 06:51:56.231310 DQS0 = 0, DQS1 = 0
4055 06:51:56.231815 DQM Delay:
4056 06:51:56.233861 DQM0 = 42, DQM1 = 33
4057 06:51:56.234346 DQ Delay:
4058 06:51:56.237325 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4059 06:51:56.240458 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =57
4060 06:51:56.244151 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4061 06:51:56.247006 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4062 06:51:56.247485
4063 06:51:56.247963
4064 06:51:56.248409 ==
4065 06:51:56.250385 Dram Type= 6, Freq= 0, CH_0, rank 1
4066 06:51:56.257325 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4067 06:51:56.257859 ==
4068 06:51:56.258342
4069 06:51:56.258796
4070 06:51:56.259236 TX Vref Scan disable
4071 06:51:56.260367 == TX Byte 0 ==
4072 06:51:56.264111 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4073 06:51:56.270251 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4074 06:51:56.270794 == TX Byte 1 ==
4075 06:51:56.273891 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4076 06:51:56.280481 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4077 06:51:56.280997 ==
4078 06:51:56.283971 Dram Type= 6, Freq= 0, CH_0, rank 1
4079 06:51:56.286987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4080 06:51:56.287466 ==
4081 06:51:56.287948
4082 06:51:56.288401
4083 06:51:56.290449 TX Vref Scan disable
4084 06:51:56.293887 == TX Byte 0 ==
4085 06:51:56.297389 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4086 06:51:56.300193 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4087 06:51:56.303886 == TX Byte 1 ==
4088 06:51:56.306791 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4089 06:51:56.310331 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4090 06:51:56.310809
4091 06:51:56.311292 [DATLAT]
4092 06:51:56.313609 Freq=600, CH0 RK1
4093 06:51:56.314088
4094 06:51:56.316896 DATLAT Default: 0x8
4095 06:51:56.317424 0, 0xFFFF, sum = 0
4096 06:51:56.320394 1, 0xFFFF, sum = 0
4097 06:51:56.321065 2, 0xFFFF, sum = 0
4098 06:51:56.324012 3, 0xFFFF, sum = 0
4099 06:51:56.324500 4, 0xFFFF, sum = 0
4100 06:51:56.327432 5, 0xFFFF, sum = 0
4101 06:51:56.328028 6, 0xFFFF, sum = 0
4102 06:51:56.330034 7, 0x0, sum = 1
4103 06:51:56.330608 8, 0x0, sum = 2
4104 06:51:56.330987 9, 0x0, sum = 3
4105 06:51:56.333326 10, 0x0, sum = 4
4106 06:51:56.333796 best_step = 8
4107 06:51:56.334164
4108 06:51:56.334507 ==
4109 06:51:56.336841 Dram Type= 6, Freq= 0, CH_0, rank 1
4110 06:51:56.343485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4111 06:51:56.343959 ==
4112 06:51:56.344335 RX Vref Scan: 0
4113 06:51:56.344684
4114 06:51:56.346377 RX Vref 0 -> 0, step: 1
4115 06:51:56.346844
4116 06:51:56.349534 RX Delay -195 -> 252, step: 8
4117 06:51:56.356489 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4118 06:51:56.359746 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4119 06:51:56.363904 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4120 06:51:56.366488 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4121 06:51:56.370631 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4122 06:51:56.376564 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4123 06:51:56.380235 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4124 06:51:56.384021 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4125 06:51:56.386205 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4126 06:51:56.389795 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4127 06:51:56.396374 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4128 06:51:56.399744 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4129 06:51:56.403186 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4130 06:51:56.406092 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4131 06:51:56.412884 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4132 06:51:56.416887 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4133 06:51:56.417316 ==
4134 06:51:56.419357 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 06:51:56.422993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4136 06:51:56.423422 ==
4137 06:51:56.427565 DQS Delay:
4138 06:51:56.428074 DQS0 = 0, DQS1 = 0
4139 06:51:56.429154 DQM Delay:
4140 06:51:56.429580 DQM0 = 41, DQM1 = 32
4141 06:51:56.429919 DQ Delay:
4142 06:51:56.432782 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4143 06:51:56.436435 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4144 06:51:56.440115 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4145 06:51:56.442844 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4146 06:51:56.443374
4147 06:51:56.443712
4148 06:51:56.452766 [DQSOSCAuto] RK1, (LSB)MR18= 0x6363, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4149 06:51:56.455798 CH0 RK1: MR19=808, MR18=6363
4150 06:51:56.462556 CH0_RK1: MR19=0x808, MR18=0x6363, DQSOSC=391, MR23=63, INC=171, DEC=114
4151 06:51:56.462994 [RxdqsGatingPostProcess] freq 600
4152 06:51:56.469336 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4153 06:51:56.473079 Pre-setting of DQS Precalculation
4154 06:51:56.475917 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4155 06:51:56.479299 ==
4156 06:51:56.481972 Dram Type= 6, Freq= 0, CH_1, rank 0
4157 06:51:56.486595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4158 06:51:56.487021 ==
4159 06:51:56.489410 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4160 06:51:56.495528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4161 06:51:56.499365 [CA 0] Center 35 (5~66) winsize 62
4162 06:51:56.502635 [CA 1] Center 35 (4~66) winsize 63
4163 06:51:56.505820 [CA 2] Center 33 (3~64) winsize 62
4164 06:51:56.509093 [CA 3] Center 33 (3~64) winsize 62
4165 06:51:56.512109 [CA 4] Center 33 (2~64) winsize 63
4166 06:51:56.516277 [CA 5] Center 33 (2~64) winsize 63
4167 06:51:56.516850
4168 06:51:56.519131 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4169 06:51:56.519556
4170 06:51:56.522137 [CATrainingPosCal] consider 1 rank data
4171 06:51:56.525573 u2DelayCellTimex100 = 270/100 ps
4172 06:51:56.529212 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4173 06:51:56.535391 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4174 06:51:56.538564 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4175 06:51:56.541984 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4176 06:51:56.545429 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4177 06:51:56.548933 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4178 06:51:56.549367
4179 06:51:56.552109 CA PerBit enable=1, Macro0, CA PI delay=33
4180 06:51:56.552542
4181 06:51:56.555073 [CBTSetCACLKResult] CA Dly = 33
4182 06:51:56.558373 CS Dly: 3 (0~34)
4183 06:51:56.558804 ==
4184 06:51:56.562186 Dram Type= 6, Freq= 0, CH_1, rank 1
4185 06:51:56.565032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4186 06:51:56.565465 ==
4187 06:51:56.572395 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4188 06:51:56.575228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4189 06:51:56.579068 [CA 0] Center 35 (5~66) winsize 62
4190 06:51:56.582636 [CA 1] Center 34 (4~65) winsize 62
4191 06:51:56.586159 [CA 2] Center 33 (3~64) winsize 62
4192 06:51:56.588919 [CA 3] Center 33 (3~64) winsize 62
4193 06:51:56.593162 [CA 4] Center 32 (2~63) winsize 62
4194 06:51:56.596095 [CA 5] Center 32 (2~63) winsize 62
4195 06:51:56.596618
4196 06:51:56.599608 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4197 06:51:56.600203
4198 06:51:56.602126 [CATrainingPosCal] consider 2 rank data
4199 06:51:56.605583 u2DelayCellTimex100 = 270/100 ps
4200 06:51:56.608905 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4201 06:51:56.616048 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4202 06:51:56.619094 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4203 06:51:56.622581 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4204 06:51:56.625651 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4205 06:51:56.628821 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4206 06:51:56.629243
4207 06:51:56.631955 CA PerBit enable=1, Macro0, CA PI delay=32
4208 06:51:56.632483
4209 06:51:56.635890 [CBTSetCACLKResult] CA Dly = 32
4210 06:51:56.638719 CS Dly: 3 (0~35)
4211 06:51:56.639346
4212 06:51:56.641533 ----->DramcWriteLeveling(PI) begin...
4213 06:51:56.642006 ==
4214 06:51:56.645082 Dram Type= 6, Freq= 0, CH_1, rank 0
4215 06:51:56.648825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4216 06:51:56.649246 ==
4217 06:51:56.651450 Write leveling (Byte 0): 25 => 25
4218 06:51:56.654917 Write leveling (Byte 1): 30 => 30
4219 06:51:56.658336 DramcWriteLeveling(PI) end<-----
4220 06:51:56.658753
4221 06:51:56.659086 ==
4222 06:51:56.662107 Dram Type= 6, Freq= 0, CH_1, rank 0
4223 06:51:56.665468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4224 06:51:56.665891 ==
4225 06:51:56.668058 [Gating] SW mode calibration
4226 06:51:56.675145 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4227 06:51:56.681305 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4228 06:51:56.684939 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 06:51:56.687996 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4230 06:51:56.695323 0 5 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
4231 06:51:56.698465 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 06:51:56.701352 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 06:51:56.708399 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 06:51:56.711109 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 06:51:56.714615 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 06:51:56.721797 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 06:51:56.724763 0 6 4 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
4238 06:51:56.727910 0 6 8 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
4239 06:51:56.734478 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 06:51:56.738066 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 06:51:56.741254 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 06:51:56.747499 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 06:51:56.751019 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 06:51:56.754132 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 06:51:56.761534 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 06:51:56.764537 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4247 06:51:56.767524 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 06:51:56.774735 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 06:51:56.777987 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 06:51:56.780276 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 06:51:56.787235 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 06:51:56.790357 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 06:51:56.794139 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 06:51:56.800647 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 06:51:56.803966 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 06:51:56.807082 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 06:51:56.813975 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 06:51:56.817690 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 06:51:56.820773 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 06:51:56.827272 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 06:51:56.830372 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 06:51:56.834080 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4263 06:51:56.841018 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 06:51:56.841539 Total UI for P1: 0, mck2ui 16
4265 06:51:56.847040 best dqsien dly found for B0: ( 0, 9, 8)
4266 06:51:56.847483 Total UI for P1: 0, mck2ui 16
4267 06:51:56.850557 best dqsien dly found for B1: ( 0, 9, 10)
4268 06:51:56.856496 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4269 06:51:56.860275 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4270 06:51:56.860948
4271 06:51:56.863997 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4272 06:51:56.866544 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4273 06:51:56.870228 [Gating] SW calibration Done
4274 06:51:56.870743 ==
4275 06:51:56.874305 Dram Type= 6, Freq= 0, CH_1, rank 0
4276 06:51:56.876914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4277 06:51:56.877384 ==
4278 06:51:56.880434 RX Vref Scan: 0
4279 06:51:56.881131
4280 06:51:56.881738 RX Vref 0 -> 0, step: 1
4281 06:51:56.882115
4282 06:51:56.883343 RX Delay -230 -> 252, step: 16
4283 06:51:56.886601 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4284 06:51:56.893526 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4285 06:51:56.896342 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4286 06:51:56.899841 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4287 06:51:56.904123 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4288 06:51:56.909518 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4289 06:51:56.912656 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4290 06:51:56.916462 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4291 06:51:56.920221 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4292 06:51:56.923730 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4293 06:51:56.930303 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4294 06:51:56.932800 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4295 06:51:56.936380 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4296 06:51:56.942594 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4297 06:51:56.945520 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4298 06:51:56.950001 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4299 06:51:56.950317 ==
4300 06:51:56.952697 Dram Type= 6, Freq= 0, CH_1, rank 0
4301 06:51:56.956412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4302 06:51:56.956834 ==
4303 06:51:56.958979 DQS Delay:
4304 06:51:56.959272 DQS0 = 0, DQS1 = 0
4305 06:51:56.962362 DQM Delay:
4306 06:51:56.962656 DQM0 = 39, DQM1 = 32
4307 06:51:56.962887 DQ Delay:
4308 06:51:56.965608 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4309 06:51:56.968982 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4310 06:51:56.972520 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4311 06:51:56.975440 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4312 06:51:56.975918
4313 06:51:56.978603
4314 06:51:56.979125 ==
4315 06:51:56.982487 Dram Type= 6, Freq= 0, CH_1, rank 0
4316 06:51:56.985276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4317 06:51:56.985743 ==
4318 06:51:56.986049
4319 06:51:56.986330
4320 06:51:56.988777 TX Vref Scan disable
4321 06:51:56.989176 == TX Byte 0 ==
4322 06:51:56.995633 Update DQ dly =569 (2 ,1, 25) DQ OEN =(1 ,6)
4323 06:51:56.998864 Update DQM dly =569 (2 ,1, 25) DQM OEN =(1 ,6)
4324 06:51:56.999349 == TX Byte 1 ==
4325 06:51:57.005468 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4326 06:51:57.008876 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4327 06:51:57.009403 ==
4328 06:51:57.011899 Dram Type= 6, Freq= 0, CH_1, rank 0
4329 06:51:57.015198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4330 06:51:57.015660 ==
4331 06:51:57.016097
4332 06:51:57.016445
4333 06:51:57.018219 TX Vref Scan disable
4334 06:51:57.021902 == TX Byte 0 ==
4335 06:51:57.025245 Update DQ dly =569 (2 ,1, 25) DQ OEN =(1 ,6)
4336 06:51:57.028395 Update DQM dly =569 (2 ,1, 25) DQM OEN =(1 ,6)
4337 06:51:57.031829 == TX Byte 1 ==
4338 06:51:57.035797 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4339 06:51:57.041256 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4340 06:51:57.041833
4341 06:51:57.042211 [DATLAT]
4342 06:51:57.042554 Freq=600, CH1 RK0
4343 06:51:57.042904
4344 06:51:57.045170 DATLAT Default: 0x9
4345 06:51:57.045644 0, 0xFFFF, sum = 0
4346 06:51:57.048200 1, 0xFFFF, sum = 0
4347 06:51:57.052569 2, 0xFFFF, sum = 0
4348 06:51:57.053208 3, 0xFFFF, sum = 0
4349 06:51:57.055102 4, 0xFFFF, sum = 0
4350 06:51:57.055567 5, 0xFFFF, sum = 0
4351 06:51:57.058033 6, 0xFFFF, sum = 0
4352 06:51:57.058498 7, 0x0, sum = 1
4353 06:51:57.058867 8, 0x0, sum = 2
4354 06:51:57.062850 9, 0x0, sum = 3
4355 06:51:57.063428 10, 0x0, sum = 4
4356 06:51:57.064452 best_step = 8
4357 06:51:57.064951
4358 06:51:57.065317 ==
4359 06:51:57.068162 Dram Type= 6, Freq= 0, CH_1, rank 0
4360 06:51:57.071438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4361 06:51:57.071964 ==
4362 06:51:57.076112 RX Vref Scan: 1
4363 06:51:57.076646
4364 06:51:57.077095 RX Vref 0 -> 0, step: 1
4365 06:51:57.077505
4366 06:51:57.078210 RX Delay -195 -> 252, step: 8
4367 06:51:57.078569
4368 06:51:57.081320 Set Vref, RX VrefLevel [Byte0]: 56
4369 06:51:57.084794 [Byte1]: 49
4370 06:51:57.088478
4371 06:51:57.089108 Final RX Vref Byte 0 = 56 to rank0
4372 06:51:57.091847 Final RX Vref Byte 1 = 49 to rank0
4373 06:51:57.095431 Final RX Vref Byte 0 = 56 to rank1
4374 06:51:57.098438 Final RX Vref Byte 1 = 49 to rank1==
4375 06:51:57.101993 Dram Type= 6, Freq= 0, CH_1, rank 0
4376 06:51:57.109036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4377 06:51:57.109511 ==
4378 06:51:57.109879 DQS Delay:
4379 06:51:57.110226 DQS0 = 0, DQS1 = 0
4380 06:51:57.112475 DQM Delay:
4381 06:51:57.113079 DQM0 = 37, DQM1 = 30
4382 06:51:57.115615 DQ Delay:
4383 06:51:57.119080 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4384 06:51:57.123152 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4385 06:51:57.123751 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4386 06:51:57.128874 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4387 06:51:57.129335
4388 06:51:57.129807
4389 06:51:57.135586 [DQSOSCAuto] RK0, (LSB)MR18= 0x7272, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4390 06:51:57.138254 CH1 RK0: MR19=808, MR18=7272
4391 06:51:57.145213 CH1_RK0: MR19=0x808, MR18=0x7272, DQSOSC=388, MR23=63, INC=174, DEC=116
4392 06:51:57.145916
4393 06:51:57.148783 ----->DramcWriteLeveling(PI) begin...
4394 06:51:57.149312 ==
4395 06:51:57.151974 Dram Type= 6, Freq= 0, CH_1, rank 1
4396 06:51:57.154871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4397 06:51:57.155334 ==
4398 06:51:57.158303 Write leveling (Byte 0): 31 => 31
4399 06:51:57.161843 Write leveling (Byte 1): 27 => 27
4400 06:51:57.164583 DramcWriteLeveling(PI) end<-----
4401 06:51:57.165108
4402 06:51:57.165488 ==
4403 06:51:57.169092 Dram Type= 6, Freq= 0, CH_1, rank 1
4404 06:51:57.172335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4405 06:51:57.172789 ==
4406 06:51:57.175066 [Gating] SW mode calibration
4407 06:51:57.181200 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 06:51:57.189415 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4409 06:51:57.191265 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 06:51:57.198026 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4411 06:51:57.202370 0 5 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
4412 06:51:57.204508 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 06:51:57.211147 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 06:51:57.215159 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 06:51:57.217920 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 06:51:57.224727 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 06:51:57.228263 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 06:51:57.231013 0 6 4 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (0 0)
4419 06:51:57.237637 0 6 8 | B1->B0 | 3535 4040 | 0 0 | (1 1) (0 0)
4420 06:51:57.242415 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 06:51:57.244625 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 06:51:57.247794 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 06:51:57.254116 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 06:51:57.257993 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 06:51:57.261267 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 06:51:57.268054 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4427 06:51:57.271143 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4428 06:51:57.274601 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 06:51:57.281150 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 06:51:57.284055 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 06:51:57.287495 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 06:51:57.294852 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 06:51:57.298743 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 06:51:57.300479 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 06:51:57.307225 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 06:51:57.310677 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 06:51:57.314538 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 06:51:57.320881 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 06:51:57.324298 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 06:51:57.328034 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 06:51:57.333630 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 06:51:57.337052 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4443 06:51:57.340675 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4444 06:51:57.343850 Total UI for P1: 0, mck2ui 16
4445 06:51:57.347519 best dqsien dly found for B0: ( 0, 9, 4)
4446 06:51:57.353694 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 06:51:57.354117 Total UI for P1: 0, mck2ui 16
4448 06:51:57.360221 best dqsien dly found for B1: ( 0, 9, 8)
4449 06:51:57.363937 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4450 06:51:57.366989 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4451 06:51:57.367536
4452 06:51:57.370483 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4453 06:51:57.373687 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4454 06:51:57.376829 [Gating] SW calibration Done
4455 06:51:57.377364 ==
4456 06:51:57.380774 Dram Type= 6, Freq= 0, CH_1, rank 1
4457 06:51:57.383984 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4458 06:51:57.384502 ==
4459 06:51:57.387001 RX Vref Scan: 0
4460 06:51:57.387500
4461 06:51:57.387843 RX Vref 0 -> 0, step: 1
4462 06:51:57.388163
4463 06:51:57.390089 RX Delay -230 -> 252, step: 16
4464 06:51:57.394028 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4465 06:51:57.400348 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4466 06:51:57.403565 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4467 06:51:57.406860 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4468 06:51:57.410999 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4469 06:51:57.417895 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4470 06:51:57.419944 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4471 06:51:57.424388 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4472 06:51:57.427054 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4473 06:51:57.430881 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4474 06:51:57.436807 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4475 06:51:57.440770 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4476 06:51:57.443937 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4477 06:51:57.447214 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4478 06:51:57.453130 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4479 06:51:57.456470 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4480 06:51:57.456927 ==
4481 06:51:57.459853 Dram Type= 6, Freq= 0, CH_1, rank 1
4482 06:51:57.464112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4483 06:51:57.464537 ==
4484 06:51:57.466584 DQS Delay:
4485 06:51:57.467018 DQS0 = 0, DQS1 = 0
4486 06:51:57.469686 DQM Delay:
4487 06:51:57.470114 DQM0 = 39, DQM1 = 33
4488 06:51:57.470446 DQ Delay:
4489 06:51:57.472847 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4490 06:51:57.476933 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4491 06:51:57.479739 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4492 06:51:57.482895 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4493 06:51:57.483316
4494 06:51:57.483650
4495 06:51:57.483961 ==
4496 06:51:57.486476 Dram Type= 6, Freq= 0, CH_1, rank 1
4497 06:51:57.493267 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4498 06:51:57.493778 ==
4499 06:51:57.494118
4500 06:51:57.494430
4501 06:51:57.496066 TX Vref Scan disable
4502 06:51:57.496415 == TX Byte 0 ==
4503 06:51:57.499938 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4504 06:51:57.506393 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4505 06:51:57.506924 == TX Byte 1 ==
4506 06:51:57.509536 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4507 06:51:57.516080 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4508 06:51:57.516506 ==
4509 06:51:57.519837 Dram Type= 6, Freq= 0, CH_1, rank 1
4510 06:51:57.524033 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4511 06:51:57.524556 ==
4512 06:51:57.524942
4513 06:51:57.525258
4514 06:51:57.525923 TX Vref Scan disable
4515 06:51:57.529276 == TX Byte 0 ==
4516 06:51:57.533200 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4517 06:51:57.536093 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4518 06:51:57.539500 == TX Byte 1 ==
4519 06:51:57.542647 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4520 06:51:57.546470 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4521 06:51:57.546942
4522 06:51:57.549896 [DATLAT]
4523 06:51:57.550414 Freq=600, CH1 RK1
4524 06:51:57.550748
4525 06:51:57.552486 DATLAT Default: 0x8
4526 06:51:57.552977 0, 0xFFFF, sum = 0
4527 06:51:57.555657 1, 0xFFFF, sum = 0
4528 06:51:57.556080 2, 0xFFFF, sum = 0
4529 06:51:57.558969 3, 0xFFFF, sum = 0
4530 06:51:57.559393 4, 0xFFFF, sum = 0
4531 06:51:57.562461 5, 0xFFFF, sum = 0
4532 06:51:57.562883 6, 0xFFFF, sum = 0
4533 06:51:57.566035 7, 0x0, sum = 1
4534 06:51:57.566717 8, 0x0, sum = 2
4535 06:51:57.569005 9, 0x0, sum = 3
4536 06:51:57.569429 10, 0x0, sum = 4
4537 06:51:57.572701 best_step = 8
4538 06:51:57.573274
4539 06:51:57.573668 ==
4540 06:51:57.575622 Dram Type= 6, Freq= 0, CH_1, rank 1
4541 06:51:57.578733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4542 06:51:57.579256 ==
4543 06:51:57.582328 RX Vref Scan: 0
4544 06:51:57.582856
4545 06:51:57.583311 RX Vref 0 -> 0, step: 1
4546 06:51:57.583641
4547 06:51:57.585989 RX Delay -195 -> 252, step: 8
4548 06:51:57.592559 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4549 06:51:57.596086 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4550 06:51:57.598787 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4551 06:51:57.602839 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4552 06:51:57.608788 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4553 06:51:57.612657 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4554 06:51:57.616197 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4555 06:51:57.619789 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4556 06:51:57.622628 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4557 06:51:57.628614 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4558 06:51:57.632677 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4559 06:51:57.635809 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4560 06:51:57.639357 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4561 06:51:57.645676 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4562 06:51:57.649897 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4563 06:51:57.652157 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4564 06:51:57.652626 ==
4565 06:51:57.656586 Dram Type= 6, Freq= 0, CH_1, rank 1
4566 06:51:57.658888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4567 06:51:57.662434 ==
4568 06:51:57.663011 DQS Delay:
4569 06:51:57.663389 DQS0 = 0, DQS1 = 0
4570 06:51:57.665308 DQM Delay:
4571 06:51:57.665792 DQM0 = 37, DQM1 = 29
4572 06:51:57.668681 DQ Delay:
4573 06:51:57.672773 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4574 06:51:57.673247 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4575 06:51:57.675116 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4576 06:51:57.679822 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4577 06:51:57.681803
4578 06:51:57.682271
4579 06:51:57.688663 [DQSOSCAuto] RK1, (LSB)MR18= 0x5656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4580 06:51:57.691559 CH1 RK1: MR19=808, MR18=5656
4581 06:51:57.698687 CH1_RK1: MR19=0x808, MR18=0x5656, DQSOSC=393, MR23=63, INC=169, DEC=113
4582 06:51:57.701962 [RxdqsGatingPostProcess] freq 600
4583 06:51:57.705523 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4584 06:51:57.708322 Pre-setting of DQS Precalculation
4585 06:51:57.714643 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4586 06:51:57.721396 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4587 06:51:57.728022 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4588 06:51:57.728405
4589 06:51:57.728648
4590 06:51:57.731743 [Calibration Summary] 1200 Mbps
4591 06:51:57.732238 CH 0, Rank 0
4592 06:51:57.735061 SW Impedance : PASS
4593 06:51:57.738086 DUTY Scan : NO K
4594 06:51:57.738556 ZQ Calibration : PASS
4595 06:51:57.742853 Jitter Meter : NO K
4596 06:51:57.744508 CBT Training : PASS
4597 06:51:57.745141 Write leveling : PASS
4598 06:51:57.748418 RX DQS gating : PASS
4599 06:51:57.751063 RX DQ/DQS(RDDQC) : PASS
4600 06:51:57.751534 TX DQ/DQS : PASS
4601 06:51:57.755058 RX DATLAT : PASS
4602 06:51:57.757840 RX DQ/DQS(Engine): PASS
4603 06:51:57.758326 TX OE : NO K
4604 06:51:57.758707 All Pass.
4605 06:51:57.759058
4606 06:51:57.761917 CH 0, Rank 1
4607 06:51:57.764856 SW Impedance : PASS
4608 06:51:57.765400 DUTY Scan : NO K
4609 06:51:57.769099 ZQ Calibration : PASS
4610 06:51:57.769649 Jitter Meter : NO K
4611 06:51:57.771544 CBT Training : PASS
4612 06:51:57.774528 Write leveling : PASS
4613 06:51:57.775097 RX DQS gating : PASS
4614 06:51:57.778096 RX DQ/DQS(RDDQC) : PASS
4615 06:51:57.780907 TX DQ/DQS : PASS
4616 06:51:57.781384 RX DATLAT : PASS
4617 06:51:57.784915 RX DQ/DQS(Engine): PASS
4618 06:51:57.787531 TX OE : NO K
4619 06:51:57.787998 All Pass.
4620 06:51:57.788372
4621 06:51:57.788753 CH 1, Rank 0
4622 06:51:57.791321 SW Impedance : PASS
4623 06:51:57.794935 DUTY Scan : NO K
4624 06:51:57.795541 ZQ Calibration : PASS
4625 06:51:57.797871 Jitter Meter : NO K
4626 06:51:57.801346 CBT Training : PASS
4627 06:51:57.801814 Write leveling : PASS
4628 06:51:57.804518 RX DQS gating : PASS
4629 06:51:57.807813 RX DQ/DQS(RDDQC) : PASS
4630 06:51:57.808434 TX DQ/DQS : PASS
4631 06:51:57.811123 RX DATLAT : PASS
4632 06:51:57.814236 RX DQ/DQS(Engine): PASS
4633 06:51:57.814705 TX OE : NO K
4634 06:51:57.817890 All Pass.
4635 06:51:57.818410
4636 06:51:57.818810 CH 1, Rank 1
4637 06:51:57.820344 SW Impedance : PASS
4638 06:51:57.820866 DUTY Scan : NO K
4639 06:51:57.824628 ZQ Calibration : PASS
4640 06:51:57.827745 Jitter Meter : NO K
4641 06:51:57.828303 CBT Training : PASS
4642 06:51:57.831797 Write leveling : PASS
4643 06:51:57.832360 RX DQS gating : PASS
4644 06:51:57.834669 RX DQ/DQS(RDDQC) : PASS
4645 06:51:57.837171 TX DQ/DQS : PASS
4646 06:51:57.837644 RX DATLAT : PASS
4647 06:51:57.840815 RX DQ/DQS(Engine): PASS
4648 06:51:57.845262 TX OE : NO K
4649 06:51:57.845741 All Pass.
4650 06:51:57.846118
4651 06:51:57.847009 DramC Write-DBI off
4652 06:51:57.847476 PER_BANK_REFRESH: Hybrid Mode
4653 06:51:57.850837 TX_TRACKING: ON
4654 06:51:57.857158 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4655 06:51:57.863723 [FAST_K] Save calibration result to emmc
4656 06:51:57.867121 dramc_set_vcore_voltage set vcore to 662500
4657 06:51:57.867676 Read voltage for 933, 3
4658 06:51:57.870645 Vio18 = 0
4659 06:51:57.871204 Vcore = 662500
4660 06:51:57.871580 Vdram = 0
4661 06:51:57.874440 Vddq = 0
4662 06:51:57.874976 Vmddr = 0
4663 06:51:57.877380 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4664 06:51:57.883638 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4665 06:51:57.886614 MEM_TYPE=3, freq_sel=17
4666 06:51:57.890228 sv_algorithm_assistance_LP4_1600
4667 06:51:57.893507 ============ PULL DRAM RESETB DOWN ============
4668 06:51:57.896884 ========== PULL DRAM RESETB DOWN end =========
4669 06:51:57.903500 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4670 06:51:57.906832 ===================================
4671 06:51:57.907391 LPDDR4 DRAM CONFIGURATION
4672 06:51:57.910177 ===================================
4673 06:51:57.913732 EX_ROW_EN[0] = 0x0
4674 06:51:57.916808 EX_ROW_EN[1] = 0x0
4675 06:51:57.917368 LP4Y_EN = 0x0
4676 06:51:57.920166 WORK_FSP = 0x0
4677 06:51:57.920783 WL = 0x3
4678 06:51:57.924121 RL = 0x3
4679 06:51:57.924658 BL = 0x2
4680 06:51:57.926816 RPST = 0x0
4681 06:51:57.927286 RD_PRE = 0x0
4682 06:51:57.930421 WR_PRE = 0x1
4683 06:51:57.930891 WR_PST = 0x0
4684 06:51:57.933665 DBI_WR = 0x0
4685 06:51:57.934228 DBI_RD = 0x0
4686 06:51:57.936801 OTF = 0x1
4687 06:51:57.940003 ===================================
4688 06:51:57.942978 ===================================
4689 06:51:57.943448 ANA top config
4690 06:51:57.946151 ===================================
4691 06:51:57.951210 DLL_ASYNC_EN = 0
4692 06:51:57.952635 ALL_SLAVE_EN = 1
4693 06:51:57.956265 NEW_RANK_MODE = 1
4694 06:51:57.956765 DLL_IDLE_MODE = 1
4695 06:51:57.959671 LP45_APHY_COMB_EN = 1
4696 06:51:57.962716 TX_ODT_DIS = 1
4697 06:51:57.965805 NEW_8X_MODE = 1
4698 06:51:57.969312 ===================================
4699 06:51:57.972793 ===================================
4700 06:51:57.975800 data_rate = 1866
4701 06:51:57.976414 CKR = 1
4702 06:51:57.979341 DQ_P2S_RATIO = 8
4703 06:51:57.982737 ===================================
4704 06:51:57.985842 CA_P2S_RATIO = 8
4705 06:51:57.989827 DQ_CA_OPEN = 0
4706 06:51:57.992806 DQ_SEMI_OPEN = 0
4707 06:51:57.995813 CA_SEMI_OPEN = 0
4708 06:51:57.996449 CA_FULL_RATE = 0
4709 06:51:57.999076 DQ_CKDIV4_EN = 1
4710 06:51:58.003355 CA_CKDIV4_EN = 1
4711 06:51:58.005614 CA_PREDIV_EN = 0
4712 06:51:58.009417 PH8_DLY = 0
4713 06:51:58.012138 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4714 06:51:58.012758 DQ_AAMCK_DIV = 4
4715 06:51:58.016049 CA_AAMCK_DIV = 4
4716 06:51:58.019340 CA_ADMCK_DIV = 4
4717 06:51:58.022262 DQ_TRACK_CA_EN = 0
4718 06:51:58.025715 CA_PICK = 933
4719 06:51:58.028791 CA_MCKIO = 933
4720 06:51:58.032893 MCKIO_SEMI = 0
4721 06:51:58.033481 PLL_FREQ = 3732
4722 06:51:58.035765 DQ_UI_PI_RATIO = 32
4723 06:51:58.038959 CA_UI_PI_RATIO = 0
4724 06:51:58.043124 ===================================
4725 06:51:58.045396 ===================================
4726 06:51:58.048512 memory_type:LPDDR4
4727 06:51:58.049058 GP_NUM : 10
4728 06:51:58.052299 SRAM_EN : 1
4729 06:51:58.055626 MD32_EN : 0
4730 06:51:58.058552 ===================================
4731 06:51:58.059041 [ANA_INIT] >>>>>>>>>>>>>>
4732 06:51:58.063043 <<<<<< [CONFIGURE PHASE]: ANA_TX
4733 06:51:58.065403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4734 06:51:58.068391 ===================================
4735 06:51:58.072520 data_rate = 1866,PCW = 0X8f00
4736 06:51:58.075243 ===================================
4737 06:51:58.078398 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4738 06:51:58.085109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4739 06:51:58.089748 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4740 06:51:58.094942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4741 06:51:58.098702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4742 06:51:58.102246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4743 06:51:58.105240 [ANA_INIT] flow start
4744 06:51:58.105834 [ANA_INIT] PLL >>>>>>>>
4745 06:51:58.108558 [ANA_INIT] PLL <<<<<<<<
4746 06:51:58.111772 [ANA_INIT] MIDPI >>>>>>>>
4747 06:51:58.112348 [ANA_INIT] MIDPI <<<<<<<<
4748 06:51:58.114764 [ANA_INIT] DLL >>>>>>>>
4749 06:51:58.118425 [ANA_INIT] flow end
4750 06:51:58.122903 ============ LP4 DIFF to SE enter ============
4751 06:51:58.124835 ============ LP4 DIFF to SE exit ============
4752 06:51:58.127934 [ANA_INIT] <<<<<<<<<<<<<
4753 06:51:58.132026 [Flow] Enable top DCM control >>>>>
4754 06:51:58.135274 [Flow] Enable top DCM control <<<<<
4755 06:51:58.137714 Enable DLL master slave shuffle
4756 06:51:58.142152 ==============================================================
4757 06:51:58.144594 Gating Mode config
4758 06:51:58.151786 ==============================================================
4759 06:51:58.152351 Config description:
4760 06:51:58.162327 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4761 06:51:58.167514 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4762 06:51:58.175004 SELPH_MODE 0: By rank 1: By Phase
4763 06:51:58.177600 ==============================================================
4764 06:51:58.181615 GAT_TRACK_EN = 1
4765 06:51:58.184160 RX_GATING_MODE = 2
4766 06:51:58.188122 RX_GATING_TRACK_MODE = 2
4767 06:51:58.190707 SELPH_MODE = 1
4768 06:51:58.194281 PICG_EARLY_EN = 1
4769 06:51:58.197291 VALID_LAT_VALUE = 1
4770 06:51:58.201302 ==============================================================
4771 06:51:58.205100 Enter into Gating configuration >>>>
4772 06:51:58.208330 Exit from Gating configuration <<<<
4773 06:51:58.210903 Enter into DVFS_PRE_config >>>>>
4774 06:51:58.224260 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4775 06:51:58.226982 Exit from DVFS_PRE_config <<<<<
4776 06:51:58.231646 Enter into PICG configuration >>>>
4777 06:51:58.233640 Exit from PICG configuration <<<<
4778 06:51:58.234111 [RX_INPUT] configuration >>>>>
4779 06:51:58.237623 [RX_INPUT] configuration <<<<<
4780 06:51:58.244085 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4781 06:51:58.246801 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4782 06:51:58.253450 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4783 06:51:58.260590 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4784 06:51:58.266477 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4785 06:51:58.273211 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4786 06:51:58.276842 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4787 06:51:58.279976 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4788 06:51:58.286257 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4789 06:51:58.290269 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4790 06:51:58.293400 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4791 06:51:58.299669 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4792 06:51:58.300141 ===================================
4793 06:51:58.303360 LPDDR4 DRAM CONFIGURATION
4794 06:51:58.306286 ===================================
4795 06:51:58.309602 EX_ROW_EN[0] = 0x0
4796 06:51:58.310090 EX_ROW_EN[1] = 0x0
4797 06:51:58.313071 LP4Y_EN = 0x0
4798 06:51:58.313675 WORK_FSP = 0x0
4799 06:51:58.316126 WL = 0x3
4800 06:51:58.316597 RL = 0x3
4801 06:51:58.319634 BL = 0x2
4802 06:51:58.323008 RPST = 0x0
4803 06:51:58.323543 RD_PRE = 0x0
4804 06:51:58.326275 WR_PRE = 0x1
4805 06:51:58.326834 WR_PST = 0x0
4806 06:51:58.329394 DBI_WR = 0x0
4807 06:51:58.329857 DBI_RD = 0x0
4808 06:51:58.333620 OTF = 0x1
4809 06:51:58.336357 ===================================
4810 06:51:58.339171 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4811 06:51:58.342622 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4812 06:51:58.346375 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4813 06:51:58.349130 ===================================
4814 06:51:58.352968 LPDDR4 DRAM CONFIGURATION
4815 06:51:58.355842 ===================================
4816 06:51:58.359207 EX_ROW_EN[0] = 0x10
4817 06:51:58.359676 EX_ROW_EN[1] = 0x0
4818 06:51:58.362853 LP4Y_EN = 0x0
4819 06:51:58.363400 WORK_FSP = 0x0
4820 06:51:58.365717 WL = 0x3
4821 06:51:58.366186 RL = 0x3
4822 06:51:58.369909 BL = 0x2
4823 06:51:58.370374 RPST = 0x0
4824 06:51:58.372927 RD_PRE = 0x0
4825 06:51:58.375408 WR_PRE = 0x1
4826 06:51:58.375876 WR_PST = 0x0
4827 06:51:58.379336 DBI_WR = 0x0
4828 06:51:58.379806 DBI_RD = 0x0
4829 06:51:58.382225 OTF = 0x1
4830 06:51:58.385737 ===================================
4831 06:51:58.389495 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4832 06:51:58.395062 nWR fixed to 30
4833 06:51:58.397481 [ModeRegInit_LP4] CH0 RK0
4834 06:51:58.397955 [ModeRegInit_LP4] CH0 RK1
4835 06:51:58.400814 [ModeRegInit_LP4] CH1 RK0
4836 06:51:58.404398 [ModeRegInit_LP4] CH1 RK1
4837 06:51:58.404909 match AC timing 8
4838 06:51:58.411397 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4839 06:51:58.414196 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4840 06:51:58.418403 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4841 06:51:58.424407 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4842 06:51:58.427529 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4843 06:51:58.428001 ==
4844 06:51:58.431084 Dram Type= 6, Freq= 0, CH_0, rank 0
4845 06:51:58.434353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4846 06:51:58.434922 ==
4847 06:51:58.440792 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4848 06:51:58.447318 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4849 06:51:58.451446 [CA 0] Center 38 (8~69) winsize 62
4850 06:51:58.454275 [CA 1] Center 38 (8~69) winsize 62
4851 06:51:58.457369 [CA 2] Center 36 (5~67) winsize 63
4852 06:51:58.460635 [CA 3] Center 35 (5~66) winsize 62
4853 06:51:58.464245 [CA 4] Center 34 (4~65) winsize 62
4854 06:51:58.467761 [CA 5] Center 34 (4~65) winsize 62
4855 06:51:58.468328
4856 06:51:58.470721 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4857 06:51:58.471284
4858 06:51:58.473915 [CATrainingPosCal] consider 1 rank data
4859 06:51:58.477406 u2DelayCellTimex100 = 270/100 ps
4860 06:51:58.480905 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4861 06:51:58.483854 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4862 06:51:58.487205 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4863 06:51:58.490774 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4864 06:51:58.494214 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4865 06:51:58.500412 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4866 06:51:58.500968
4867 06:51:58.504142 CA PerBit enable=1, Macro0, CA PI delay=34
4868 06:51:58.504830
4869 06:51:58.507135 [CBTSetCACLKResult] CA Dly = 34
4870 06:51:58.507693 CS Dly: 7 (0~38)
4871 06:51:58.508062 ==
4872 06:51:58.510595 Dram Type= 6, Freq= 0, CH_0, rank 1
4873 06:51:58.514620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4874 06:51:58.517999 ==
4875 06:51:58.520789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4876 06:51:58.527774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4877 06:51:58.530306 [CA 0] Center 38 (8~69) winsize 62
4878 06:51:58.533546 [CA 1] Center 38 (7~69) winsize 63
4879 06:51:58.537556 [CA 2] Center 36 (6~67) winsize 62
4880 06:51:58.540337 [CA 3] Center 35 (5~66) winsize 62
4881 06:51:58.543513 [CA 4] Center 34 (4~65) winsize 62
4882 06:51:58.547137 [CA 5] Center 34 (4~65) winsize 62
4883 06:51:58.547607
4884 06:51:58.550420 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4885 06:51:58.550892
4886 06:51:58.553617 [CATrainingPosCal] consider 2 rank data
4887 06:51:58.557482 u2DelayCellTimex100 = 270/100 ps
4888 06:51:58.560599 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4889 06:51:58.564120 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4890 06:51:58.567076 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4891 06:51:58.570662 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4892 06:51:58.577324 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4893 06:51:58.580008 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4894 06:51:58.580477
4895 06:51:58.583290 CA PerBit enable=1, Macro0, CA PI delay=34
4896 06:51:58.583756
4897 06:51:58.586833 [CBTSetCACLKResult] CA Dly = 34
4898 06:51:58.587401 CS Dly: 7 (0~39)
4899 06:51:58.587778
4900 06:51:58.589813 ----->DramcWriteLeveling(PI) begin...
4901 06:51:58.590288 ==
4902 06:51:58.593630 Dram Type= 6, Freq= 0, CH_0, rank 0
4903 06:51:58.600111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4904 06:51:58.600670 ==
4905 06:51:58.603087 Write leveling (Byte 0): 30 => 30
4906 06:51:58.607781 Write leveling (Byte 1): 29 => 29
4907 06:51:58.608349 DramcWriteLeveling(PI) end<-----
4908 06:51:58.608772
4909 06:51:58.609832 ==
4910 06:51:58.613390 Dram Type= 6, Freq= 0, CH_0, rank 0
4911 06:51:58.617291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4912 06:51:58.617767 ==
4913 06:51:58.620255 [Gating] SW mode calibration
4914 06:51:58.626221 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4915 06:51:58.630506 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4916 06:51:58.636266 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4917 06:51:58.641819 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4918 06:51:58.643854 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4919 06:51:58.649854 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4920 06:51:58.653049 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4921 06:51:58.655968 0 10 20 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
4922 06:51:58.663485 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
4923 06:51:58.666408 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4924 06:51:58.669828 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4925 06:51:58.675972 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4926 06:51:58.679245 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4927 06:51:58.683749 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4928 06:51:58.690860 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4929 06:51:58.692864 0 11 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4930 06:51:58.695960 0 11 24 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4931 06:51:58.703468 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4932 06:51:58.706231 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4933 06:51:58.709035 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4934 06:51:58.716395 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4935 06:51:58.718971 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4936 06:51:58.722033 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4937 06:51:58.729443 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4938 06:51:58.732331 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4939 06:51:58.736437 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 06:51:58.741784 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 06:51:58.745185 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 06:51:58.749115 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 06:51:58.755368 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 06:51:58.759752 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 06:51:58.761851 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 06:51:58.768013 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 06:51:58.771795 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 06:51:58.774866 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 06:51:58.781882 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 06:51:58.784851 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 06:51:58.788418 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 06:51:58.795429 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4953 06:51:58.798447 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4954 06:51:58.801746 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4955 06:51:58.804943 Total UI for P1: 0, mck2ui 16
4956 06:51:58.808384 best dqsien dly found for B0: ( 0, 14, 18)
4957 06:51:58.811440 Total UI for P1: 0, mck2ui 16
4958 06:51:58.815016 best dqsien dly found for B1: ( 0, 14, 20)
4959 06:51:58.818568 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
4960 06:51:58.821100 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4961 06:51:58.821568
4962 06:51:58.827993 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
4963 06:51:58.831548 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4964 06:51:58.832016 [Gating] SW calibration Done
4965 06:51:58.834819 ==
4966 06:51:58.837883 Dram Type= 6, Freq= 0, CH_0, rank 0
4967 06:51:58.841155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4968 06:51:58.841624 ==
4969 06:51:58.841990 RX Vref Scan: 0
4970 06:51:58.842334
4971 06:51:58.844664 RX Vref 0 -> 0, step: 1
4972 06:51:58.845176
4973 06:51:58.848841 RX Delay -80 -> 252, step: 8
4974 06:51:58.851872 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4975 06:51:58.855210 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4976 06:51:58.857475 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4977 06:51:58.864774 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4978 06:51:58.870739 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4979 06:51:58.871687 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
4980 06:51:58.874547 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4981 06:51:58.878045 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4982 06:51:58.884394 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4983 06:51:58.887788 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4984 06:51:58.890726 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4985 06:51:58.893780 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4986 06:51:58.897729 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4987 06:51:58.903958 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4988 06:51:58.907368 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
4989 06:51:58.910441 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4990 06:51:58.910911 ==
4991 06:51:58.913732 Dram Type= 6, Freq= 0, CH_0, rank 0
4992 06:51:58.917573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4993 06:51:58.918040 ==
4994 06:51:58.920837 DQS Delay:
4995 06:51:58.921421 DQS0 = 0, DQS1 = 0
4996 06:51:58.923911 DQM Delay:
4997 06:51:58.924488 DQM0 = 95, DQM1 = 84
4998 06:51:58.924907 DQ Delay:
4999 06:51:58.927307 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5000 06:51:58.930414 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5001 06:51:58.933979 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5002 06:51:58.937867 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5003 06:51:58.938335
5004 06:51:58.938702
5005 06:51:58.940746 ==
5006 06:51:58.943464 Dram Type= 6, Freq= 0, CH_0, rank 0
5007 06:51:58.947513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5008 06:51:58.948066 ==
5009 06:51:58.948439
5010 06:51:58.948840
5011 06:51:58.950112 TX Vref Scan disable
5012 06:51:58.950574 == TX Byte 0 ==
5013 06:51:58.953864 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5014 06:51:58.960460 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5015 06:51:58.960984 == TX Byte 1 ==
5016 06:51:58.966950 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5017 06:51:58.971128 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5018 06:51:58.971690 ==
5019 06:51:58.974432 Dram Type= 6, Freq= 0, CH_0, rank 0
5020 06:51:58.977030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5021 06:51:58.977604 ==
5022 06:51:58.977982
5023 06:51:58.978327
5024 06:51:58.980847 TX Vref Scan disable
5025 06:51:58.983240 == TX Byte 0 ==
5026 06:51:58.987356 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5027 06:51:58.989491 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5028 06:51:58.993642 == TX Byte 1 ==
5029 06:51:58.996777 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5030 06:51:59.000611 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5031 06:51:59.001222
5032 06:51:59.002804 [DATLAT]
5033 06:51:59.003267 Freq=933, CH0 RK0
5034 06:51:59.003637
5035 06:51:59.006694 DATLAT Default: 0xd
5036 06:51:59.007270 0, 0xFFFF, sum = 0
5037 06:51:59.009900 1, 0xFFFF, sum = 0
5038 06:51:59.010372 2, 0xFFFF, sum = 0
5039 06:51:59.012985 3, 0xFFFF, sum = 0
5040 06:51:59.013595 4, 0xFFFF, sum = 0
5041 06:51:59.016421 5, 0xFFFF, sum = 0
5042 06:51:59.016929 6, 0xFFFF, sum = 0
5043 06:51:59.020595 7, 0xFFFF, sum = 0
5044 06:51:59.021218 8, 0xFFFF, sum = 0
5045 06:51:59.022819 9, 0xFFFF, sum = 0
5046 06:51:59.023293 10, 0x0, sum = 1
5047 06:51:59.026884 11, 0x0, sum = 2
5048 06:51:59.027472 12, 0x0, sum = 3
5049 06:51:59.029925 13, 0x0, sum = 4
5050 06:51:59.030459 best_step = 11
5051 06:51:59.030900
5052 06:51:59.031254 ==
5053 06:51:59.032815 Dram Type= 6, Freq= 0, CH_0, rank 0
5054 06:51:59.040062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5055 06:51:59.040653 ==
5056 06:51:59.041068 RX Vref Scan: 1
5057 06:51:59.041413
5058 06:51:59.043051 RX Vref 0 -> 0, step: 1
5059 06:51:59.043513
5060 06:51:59.046642 RX Delay -69 -> 252, step: 4
5061 06:51:59.047104
5062 06:51:59.049594 Set Vref, RX VrefLevel [Byte0]: 46
5063 06:51:59.052873 [Byte1]: 49
5064 06:51:59.053545
5065 06:51:59.056104 Final RX Vref Byte 0 = 46 to rank0
5066 06:51:59.059389 Final RX Vref Byte 1 = 49 to rank0
5067 06:51:59.064625 Final RX Vref Byte 0 = 46 to rank1
5068 06:51:59.065829 Final RX Vref Byte 1 = 49 to rank1==
5069 06:51:59.069167 Dram Type= 6, Freq= 0, CH_0, rank 0
5070 06:51:59.072506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5071 06:51:59.073041 ==
5072 06:51:59.075877 DQS Delay:
5073 06:51:59.076463 DQS0 = 0, DQS1 = 0
5074 06:51:59.079415 DQM Delay:
5075 06:51:59.079996 DQM0 = 96, DQM1 = 87
5076 06:51:59.080488 DQ Delay:
5077 06:51:59.083904 DQ0 =92, DQ1 =100, DQ2 =94, DQ3 =92
5078 06:51:59.085768 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5079 06:51:59.088996 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5080 06:51:59.092468 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =98
5081 06:51:59.093013
5082 06:51:59.095858
5083 06:51:59.102764 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5084 06:51:59.106069 CH0 RK0: MR19=505, MR18=1F1F
5085 06:51:59.112034 CH0_RK0: MR19=0x505, MR18=0x1F1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5086 06:51:59.112568
5087 06:51:59.115529 ----->DramcWriteLeveling(PI) begin...
5088 06:51:59.116100 ==
5089 06:51:59.119289 Dram Type= 6, Freq= 0, CH_0, rank 1
5090 06:51:59.122690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5091 06:51:59.123185 ==
5092 06:51:59.127377 Write leveling (Byte 0): 29 => 29
5093 06:51:59.128250 Write leveling (Byte 1): 28 => 28
5094 06:51:59.132513 DramcWriteLeveling(PI) end<-----
5095 06:51:59.133088
5096 06:51:59.133458 ==
5097 06:51:59.135267 Dram Type= 6, Freq= 0, CH_0, rank 1
5098 06:51:59.138510 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5099 06:51:59.138969 ==
5100 06:51:59.142033 [Gating] SW mode calibration
5101 06:51:59.148508 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5102 06:51:59.155195 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5103 06:51:59.158227 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 06:51:59.162368 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 06:51:59.169352 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 06:51:59.171530 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 06:51:59.175122 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 06:51:59.181561 0 10 20 | B1->B0 | 3232 2a2a | 0 0 | (0 1) (1 1)
5109 06:51:59.184659 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5110 06:51:59.188234 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 06:51:59.194780 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 06:51:59.198307 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 06:51:59.201944 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 06:51:59.208321 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 06:51:59.211275 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 06:51:59.214618 0 11 20 | B1->B0 | 2f2f 3535 | 0 0 | (0 0) (0 0)
5117 06:51:59.221383 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5118 06:51:59.224470 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 06:51:59.228283 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 06:51:59.234453 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 06:51:59.238416 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 06:51:59.241639 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 06:51:59.247964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 06:51:59.251028 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5125 06:51:59.254565 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 06:51:59.261237 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 06:51:59.264361 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 06:51:59.267893 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 06:51:59.275248 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 06:51:59.277576 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 06:51:59.281097 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 06:51:59.288110 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 06:51:59.291110 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 06:51:59.294070 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 06:51:59.301175 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 06:51:59.304849 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 06:51:59.307934 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 06:51:59.313854 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 06:51:59.317539 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 06:51:59.320526 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5141 06:51:59.327820 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 06:51:59.328380 Total UI for P1: 0, mck2ui 16
5143 06:51:59.333673 best dqsien dly found for B0: ( 0, 14, 20)
5144 06:51:59.334143 Total UI for P1: 0, mck2ui 16
5145 06:51:59.336653 best dqsien dly found for B1: ( 0, 14, 20)
5146 06:51:59.344230 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5147 06:51:59.347161 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5148 06:51:59.347686
5149 06:51:59.350272 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5150 06:51:59.353475 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5151 06:51:59.357598 [Gating] SW calibration Done
5152 06:51:59.358063 ==
5153 06:51:59.359876 Dram Type= 6, Freq= 0, CH_0, rank 1
5154 06:51:59.363435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5155 06:51:59.364084 ==
5156 06:51:59.366622 RX Vref Scan: 0
5157 06:51:59.367141
5158 06:51:59.367481 RX Vref 0 -> 0, step: 1
5159 06:51:59.368070
5160 06:51:59.370165 RX Delay -80 -> 252, step: 8
5161 06:51:59.373384 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5162 06:51:59.379930 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5163 06:51:59.384111 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5164 06:51:59.387047 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5165 06:51:59.390025 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5166 06:51:59.393549 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5167 06:51:59.397203 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5168 06:51:59.403693 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5169 06:51:59.406628 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5170 06:51:59.409905 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5171 06:51:59.413306 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5172 06:51:59.417166 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5173 06:51:59.423315 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5174 06:51:59.426708 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5175 06:51:59.429679 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5176 06:51:59.433316 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5177 06:51:59.433920 ==
5178 06:51:59.436260 Dram Type= 6, Freq= 0, CH_0, rank 1
5179 06:51:59.439355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5180 06:51:59.442929 ==
5181 06:51:59.443464 DQS Delay:
5182 06:51:59.443833 DQS0 = 0, DQS1 = 0
5183 06:51:59.446258 DQM Delay:
5184 06:51:59.446720 DQM0 = 97, DQM1 = 85
5185 06:51:59.449542 DQ Delay:
5186 06:51:59.452667 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5187 06:51:59.453163 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =107
5188 06:51:59.456123 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5189 06:51:59.463731 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =95
5190 06:51:59.464272
5191 06:51:59.464660
5192 06:51:59.465042 ==
5193 06:51:59.466219 Dram Type= 6, Freq= 0, CH_0, rank 1
5194 06:51:59.469721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5195 06:51:59.470238 ==
5196 06:51:59.470644
5197 06:51:59.470985
5198 06:51:59.472994 TX Vref Scan disable
5199 06:51:59.473454 == TX Byte 0 ==
5200 06:51:59.479781 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5201 06:51:59.483126 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5202 06:51:59.483696 == TX Byte 1 ==
5203 06:51:59.489608 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5204 06:51:59.492860 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5205 06:51:59.493393 ==
5206 06:51:59.496226 Dram Type= 6, Freq= 0, CH_0, rank 1
5207 06:51:59.499620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5208 06:51:59.500173 ==
5209 06:51:59.500545
5210 06:51:59.502166
5211 06:51:59.502624 TX Vref Scan disable
5212 06:51:59.506456 == TX Byte 0 ==
5213 06:51:59.509045 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5214 06:51:59.512247 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5215 06:51:59.516018 == TX Byte 1 ==
5216 06:51:59.518972 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5217 06:51:59.525918 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5218 06:51:59.526484
5219 06:51:59.526856 [DATLAT]
5220 06:51:59.527199 Freq=933, CH0 RK1
5221 06:51:59.527530
5222 06:51:59.529080 DATLAT Default: 0xb
5223 06:51:59.529546 0, 0xFFFF, sum = 0
5224 06:51:59.532018 1, 0xFFFF, sum = 0
5225 06:51:59.532496 2, 0xFFFF, sum = 0
5226 06:51:59.535250 3, 0xFFFF, sum = 0
5227 06:51:59.538635 4, 0xFFFF, sum = 0
5228 06:51:59.539108 5, 0xFFFF, sum = 0
5229 06:51:59.541832 6, 0xFFFF, sum = 0
5230 06:51:59.542429 7, 0xFFFF, sum = 0
5231 06:51:59.545210 8, 0xFFFF, sum = 0
5232 06:51:59.545888 9, 0xFFFF, sum = 0
5233 06:51:59.548943 10, 0x0, sum = 1
5234 06:51:59.549540 11, 0x0, sum = 2
5235 06:51:59.551916 12, 0x0, sum = 3
5236 06:51:59.552388 13, 0x0, sum = 4
5237 06:51:59.552816 best_step = 11
5238 06:51:59.553170
5239 06:51:59.554953 ==
5240 06:51:59.558204 Dram Type= 6, Freq= 0, CH_0, rank 1
5241 06:51:59.562110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5242 06:51:59.562687 ==
5243 06:51:59.563063 RX Vref Scan: 0
5244 06:51:59.563405
5245 06:51:59.565081 RX Vref 0 -> 0, step: 1
5246 06:51:59.565546
5247 06:51:59.568851 RX Delay -69 -> 252, step: 4
5248 06:51:59.571846 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5249 06:51:59.578287 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5250 06:51:59.581710 iDelay=199, Bit 2, Center 98 (7 ~ 190) 184
5251 06:51:59.585357 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5252 06:51:59.588463 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5253 06:51:59.591924 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5254 06:51:59.598296 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5255 06:51:59.602792 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5256 06:51:59.604955 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5257 06:51:59.607943 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5258 06:51:59.611852 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5259 06:51:59.618007 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5260 06:51:59.621112 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5261 06:51:59.626359 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5262 06:51:59.627867 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5263 06:51:59.631992 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5264 06:51:59.632493 ==
5265 06:51:59.634418 Dram Type= 6, Freq= 0, CH_0, rank 1
5266 06:51:59.640832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5267 06:51:59.641297 ==
5268 06:51:59.641662 DQS Delay:
5269 06:51:59.644122 DQS0 = 0, DQS1 = 0
5270 06:51:59.644581 DQM Delay:
5271 06:51:59.645004 DQM0 = 98, DQM1 = 86
5272 06:51:59.647806 DQ Delay:
5273 06:51:59.650494 DQ0 =94, DQ1 =100, DQ2 =98, DQ3 =92
5274 06:51:59.654076 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5275 06:51:59.657220 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5276 06:51:59.661295 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =96
5277 06:51:59.661712
5278 06:51:59.662046
5279 06:51:59.667742 [DQSOSCAuto] RK1, (LSB)MR18= 0x2727, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5280 06:51:59.670425 CH0 RK1: MR19=505, MR18=2727
5281 06:51:59.677836 CH0_RK1: MR19=0x505, MR18=0x2727, DQSOSC=409, MR23=63, INC=64, DEC=43
5282 06:51:59.680995 [RxdqsGatingPostProcess] freq 933
5283 06:51:59.684077 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5284 06:51:59.687111 Pre-setting of DQS Precalculation
5285 06:51:59.693890 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5286 06:51:59.694313 ==
5287 06:51:59.697265 Dram Type= 6, Freq= 0, CH_1, rank 0
5288 06:51:59.700451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5289 06:51:59.700992 ==
5290 06:51:59.707537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5291 06:51:59.714771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5292 06:51:59.717569 [CA 0] Center 37 (6~68) winsize 63
5293 06:51:59.720653 [CA 1] Center 37 (6~68) winsize 63
5294 06:51:59.723656 [CA 2] Center 34 (4~65) winsize 62
5295 06:51:59.727348 [CA 3] Center 34 (4~65) winsize 62
5296 06:51:59.730473 [CA 4] Center 33 (3~64) winsize 62
5297 06:51:59.733520 [CA 5] Center 33 (2~64) winsize 63
5298 06:51:59.733942
5299 06:51:59.738293 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5300 06:51:59.738717
5301 06:51:59.740076 [CATrainingPosCal] consider 1 rank data
5302 06:51:59.744443 u2DelayCellTimex100 = 270/100 ps
5303 06:51:59.746866 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5304 06:51:59.750329 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5305 06:51:59.753439 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5306 06:51:59.756811 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5307 06:51:59.760018 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5308 06:51:59.763468 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5309 06:51:59.763894
5310 06:51:59.770006 CA PerBit enable=1, Macro0, CA PI delay=33
5311 06:51:59.770430
5312 06:51:59.770765 [CBTSetCACLKResult] CA Dly = 33
5313 06:51:59.773587 CS Dly: 5 (0~36)
5314 06:51:59.774032 ==
5315 06:51:59.777009 Dram Type= 6, Freq= 0, CH_1, rank 1
5316 06:51:59.780306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5317 06:51:59.780764 ==
5318 06:51:59.786557 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5319 06:51:59.793302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5320 06:51:59.796658 [CA 0] Center 37 (6~68) winsize 63
5321 06:51:59.799735 [CA 1] Center 37 (6~68) winsize 63
5322 06:51:59.803095 [CA 2] Center 34 (4~65) winsize 62
5323 06:51:59.806674 [CA 3] Center 34 (4~65) winsize 62
5324 06:51:59.809911 [CA 4] Center 33 (3~64) winsize 62
5325 06:51:59.813360 [CA 5] Center 33 (3~64) winsize 62
5326 06:51:59.813825
5327 06:51:59.816870 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5328 06:51:59.817331
5329 06:51:59.819758 [CATrainingPosCal] consider 2 rank data
5330 06:51:59.823204 u2DelayCellTimex100 = 270/100 ps
5331 06:51:59.826170 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5332 06:51:59.829693 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5333 06:51:59.834077 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5334 06:51:59.836864 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5335 06:51:59.839605 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5336 06:51:59.843251 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5337 06:51:59.846516
5338 06:51:59.850053 CA PerBit enable=1, Macro0, CA PI delay=33
5339 06:51:59.850513
5340 06:51:59.853147 [CBTSetCACLKResult] CA Dly = 33
5341 06:51:59.853699 CS Dly: 5 (0~37)
5342 06:51:59.854065
5343 06:51:59.856611 ----->DramcWriteLeveling(PI) begin...
5344 06:51:59.857163 ==
5345 06:51:59.860307 Dram Type= 6, Freq= 0, CH_1, rank 0
5346 06:51:59.866088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5347 06:51:59.866645 ==
5348 06:51:59.869345 Write leveling (Byte 0): 26 => 26
5349 06:51:59.869808 Write leveling (Byte 1): 25 => 25
5350 06:51:59.873176 DramcWriteLeveling(PI) end<-----
5351 06:51:59.873712
5352 06:51:59.874079 ==
5353 06:51:59.875907 Dram Type= 6, Freq= 0, CH_1, rank 0
5354 06:51:59.882972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5355 06:51:59.883531 ==
5356 06:51:59.885632 [Gating] SW mode calibration
5357 06:51:59.893079 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5358 06:51:59.895983 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5359 06:51:59.902613 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 06:51:59.906064 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 06:51:59.909064 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 06:51:59.915494 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5363 06:51:59.918770 0 10 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5364 06:51:59.923484 0 10 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
5365 06:51:59.928824 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5366 06:51:59.931871 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 06:51:59.936218 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 06:51:59.943082 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 06:51:59.945225 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 06:51:59.948943 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 06:51:59.956592 0 11 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5372 06:51:59.958986 0 11 20 | B1->B0 | 2d2d 4242 | 0 0 | (0 0) (0 0)
5373 06:51:59.962279 0 11 24 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5374 06:51:59.968674 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 06:51:59.971923 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 06:51:59.975582 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 06:51:59.982407 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 06:51:59.985334 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 06:51:59.988639 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5380 06:51:59.995306 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5381 06:51:59.999043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 06:52:00.001397 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 06:52:00.008446 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 06:52:00.011478 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 06:52:00.015092 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 06:52:00.021776 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 06:52:00.025598 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 06:52:00.028223 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 06:52:00.032035 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 06:52:00.037935 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 06:52:00.041329 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 06:52:00.044280 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 06:52:00.051343 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 06:52:00.054749 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 06:52:00.057674 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5396 06:52:00.061175 Total UI for P1: 0, mck2ui 16
5397 06:52:00.064463 best dqsien dly found for B0: ( 0, 14, 14)
5398 06:52:00.071232 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5399 06:52:00.074870 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 06:52:00.077973 Total UI for P1: 0, mck2ui 16
5401 06:52:00.081216 best dqsien dly found for B1: ( 0, 14, 18)
5402 06:52:00.084335 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5403 06:52:00.088195 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5404 06:52:00.088828
5405 06:52:00.091195 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5406 06:52:00.095134 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5407 06:52:00.098773 [Gating] SW calibration Done
5408 06:52:00.099286 ==
5409 06:52:00.100826 Dram Type= 6, Freq= 0, CH_1, rank 0
5410 06:52:00.107879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5411 06:52:00.108470 ==
5412 06:52:00.109018 RX Vref Scan: 0
5413 06:52:00.109478
5414 06:52:00.111453 RX Vref 0 -> 0, step: 1
5415 06:52:00.112035
5416 06:52:00.114224 RX Delay -80 -> 252, step: 8
5417 06:52:00.117672 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5418 06:52:00.121005 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5419 06:52:00.124825 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5420 06:52:00.127777 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5421 06:52:00.134109 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5422 06:52:00.137385 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5423 06:52:00.140545 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5424 06:52:00.144078 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5425 06:52:00.147669 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5426 06:52:00.151065 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5427 06:52:00.157637 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5428 06:52:00.161972 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5429 06:52:00.164016 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5430 06:52:00.167935 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5431 06:52:00.170567 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5432 06:52:00.177196 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5433 06:52:00.177761 ==
5434 06:52:00.180575 Dram Type= 6, Freq= 0, CH_1, rank 0
5435 06:52:00.184502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5436 06:52:00.185159 ==
5437 06:52:00.185641 DQS Delay:
5438 06:52:00.187109 DQS0 = 0, DQS1 = 0
5439 06:52:00.187584 DQM Delay:
5440 06:52:00.191202 DQM0 = 95, DQM1 = 88
5441 06:52:00.191782 DQ Delay:
5442 06:52:00.194753 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5443 06:52:00.197723 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5444 06:52:00.200568 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5445 06:52:00.205743 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5446 06:52:00.206320
5447 06:52:00.206809
5448 06:52:00.207263 ==
5449 06:52:00.208068 Dram Type= 6, Freq= 0, CH_1, rank 0
5450 06:52:00.211959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5451 06:52:00.212547 ==
5452 06:52:00.213670
5453 06:52:00.214142
5454 06:52:00.214619 TX Vref Scan disable
5455 06:52:00.217260 == TX Byte 0 ==
5456 06:52:00.220192 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5457 06:52:00.223278 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5458 06:52:00.226864 == TX Byte 1 ==
5459 06:52:00.231060 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5460 06:52:00.234095 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5461 06:52:00.234576 ==
5462 06:52:00.237180 Dram Type= 6, Freq= 0, CH_1, rank 0
5463 06:52:00.243288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5464 06:52:00.243770 ==
5465 06:52:00.244249
5466 06:52:00.244701
5467 06:52:00.245184 TX Vref Scan disable
5468 06:52:00.247867 == TX Byte 0 ==
5469 06:52:00.251219 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5470 06:52:00.257948 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5471 06:52:00.258452 == TX Byte 1 ==
5472 06:52:00.260876 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5473 06:52:00.267569 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5474 06:52:00.268074
5475 06:52:00.268517 [DATLAT]
5476 06:52:00.268993 Freq=933, CH1 RK0
5477 06:52:00.269401
5478 06:52:00.270823 DATLAT Default: 0xd
5479 06:52:00.271252 0, 0xFFFF, sum = 0
5480 06:52:00.275054 1, 0xFFFF, sum = 0
5481 06:52:00.275491 2, 0xFFFF, sum = 0
5482 06:52:00.278247 3, 0xFFFF, sum = 0
5483 06:52:00.281700 4, 0xFFFF, sum = 0
5484 06:52:00.282140 5, 0xFFFF, sum = 0
5485 06:52:00.284170 6, 0xFFFF, sum = 0
5486 06:52:00.284606 7, 0xFFFF, sum = 0
5487 06:52:00.287860 8, 0xFFFF, sum = 0
5488 06:52:00.288413 9, 0xFFFF, sum = 0
5489 06:52:00.291139 10, 0x0, sum = 1
5490 06:52:00.291719 11, 0x0, sum = 2
5491 06:52:00.294422 12, 0x0, sum = 3
5492 06:52:00.294859 13, 0x0, sum = 4
5493 06:52:00.295207 best_step = 11
5494 06:52:00.295523
5495 06:52:00.297573 ==
5496 06:52:00.300688 Dram Type= 6, Freq= 0, CH_1, rank 0
5497 06:52:00.303899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5498 06:52:00.304332 ==
5499 06:52:00.304670 RX Vref Scan: 1
5500 06:52:00.305033
5501 06:52:00.307397 RX Vref 0 -> 0, step: 1
5502 06:52:00.307837
5503 06:52:00.311079 RX Delay -69 -> 252, step: 4
5504 06:52:00.311622
5505 06:52:00.315223 Set Vref, RX VrefLevel [Byte0]: 56
5506 06:52:00.317074 [Byte1]: 49
5507 06:52:00.317502
5508 06:52:00.320785 Final RX Vref Byte 0 = 56 to rank0
5509 06:52:00.324069 Final RX Vref Byte 1 = 49 to rank0
5510 06:52:00.327455 Final RX Vref Byte 0 = 56 to rank1
5511 06:52:00.331048 Final RX Vref Byte 1 = 49 to rank1==
5512 06:52:00.333519 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 06:52:00.337327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5514 06:52:00.340517 ==
5515 06:52:00.340972 DQS Delay:
5516 06:52:00.341311 DQS0 = 0, DQS1 = 0
5517 06:52:00.345273 DQM Delay:
5518 06:52:00.345789 DQM0 = 93, DQM1 = 88
5519 06:52:00.346970 DQ Delay:
5520 06:52:00.351204 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5521 06:52:00.353335 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5522 06:52:00.357426 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5523 06:52:00.359826 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5524 06:52:00.360263
5525 06:52:00.360824
5526 06:52:00.366757 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5527 06:52:00.370001 CH1 RK0: MR19=505, MR18=3939
5528 06:52:00.376280 CH1_RK0: MR19=0x505, MR18=0x3939, DQSOSC=404, MR23=63, INC=66, DEC=44
5529 06:52:00.376818
5530 06:52:00.379814 ----->DramcWriteLeveling(PI) begin...
5531 06:52:00.380350 ==
5532 06:52:00.384071 Dram Type= 6, Freq= 0, CH_1, rank 1
5533 06:52:00.386370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5534 06:52:00.386850 ==
5535 06:52:00.389938 Write leveling (Byte 0): 23 => 23
5536 06:52:00.393334 Write leveling (Byte 1): 25 => 25
5537 06:52:00.397129 DramcWriteLeveling(PI) end<-----
5538 06:52:00.397681
5539 06:52:00.398171 ==
5540 06:52:00.399855 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 06:52:00.403864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5542 06:52:00.404344 ==
5543 06:52:00.406398 [Gating] SW mode calibration
5544 06:52:00.413614 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5545 06:52:00.419542 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5546 06:52:00.422784 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 06:52:00.429504 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 06:52:00.433002 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 06:52:00.436097 0 10 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5550 06:52:00.443021 0 10 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
5551 06:52:00.446446 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (1 0)
5552 06:52:00.449049 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 06:52:00.456546 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 06:52:00.459178 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 06:52:00.463504 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 06:52:00.469519 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 06:52:00.472833 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 06:52:00.476057 0 11 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
5559 06:52:00.484245 0 11 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5560 06:52:00.486393 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 06:52:00.489155 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 06:52:00.495832 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 06:52:00.499578 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 06:52:00.502284 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 06:52:00.509178 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 06:52:00.513419 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5567 06:52:00.515272 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 06:52:00.522598 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 06:52:00.525529 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 06:52:00.528468 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 06:52:00.535035 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 06:52:00.538443 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 06:52:00.541759 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 06:52:00.548176 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 06:52:00.551782 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 06:52:00.555083 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 06:52:00.561578 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 06:52:00.564655 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 06:52:00.568043 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 06:52:00.575555 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 06:52:00.578444 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 06:52:00.581398 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5583 06:52:00.587442 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5584 06:52:00.591268 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 06:52:00.594702 Total UI for P1: 0, mck2ui 16
5586 06:52:00.597903 best dqsien dly found for B0: ( 0, 14, 18)
5587 06:52:00.600912 Total UI for P1: 0, mck2ui 16
5588 06:52:00.604398 best dqsien dly found for B1: ( 0, 14, 22)
5589 06:52:00.607382 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5590 06:52:00.611406 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5591 06:52:00.611942
5592 06:52:00.614196 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5593 06:52:00.617804 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5594 06:52:00.620811 [Gating] SW calibration Done
5595 06:52:00.621504 ==
5596 06:52:00.623753 Dram Type= 6, Freq= 0, CH_1, rank 1
5597 06:52:00.627429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5598 06:52:00.630663 ==
5599 06:52:00.631151 RX Vref Scan: 0
5600 06:52:00.631702
5601 06:52:00.633720 RX Vref 0 -> 0, step: 1
5602 06:52:00.634211
5603 06:52:00.637271 RX Delay -80 -> 252, step: 8
5604 06:52:00.640449 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5605 06:52:00.643942 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5606 06:52:00.647290 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5607 06:52:00.650930 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5608 06:52:00.655393 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5609 06:52:00.660439 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5610 06:52:00.663683 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5611 06:52:00.667619 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5612 06:52:00.670556 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5613 06:52:00.675497 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5614 06:52:00.680865 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5615 06:52:00.683823 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5616 06:52:00.687644 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5617 06:52:00.690275 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5618 06:52:00.693550 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5619 06:52:00.700329 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5620 06:52:00.700996 ==
5621 06:52:00.703898 Dram Type= 6, Freq= 0, CH_1, rank 1
5622 06:52:00.707233 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5623 06:52:00.707712 ==
5624 06:52:00.708078 DQS Delay:
5625 06:52:00.710104 DQS0 = 0, DQS1 = 0
5626 06:52:00.710667 DQM Delay:
5627 06:52:00.713277 DQM0 = 95, DQM1 = 85
5628 06:52:00.713753 DQ Delay:
5629 06:52:00.716381 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5630 06:52:00.720158 DQ4 =95, DQ5 =107, DQ6 =99, DQ7 =91
5631 06:52:00.723390 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =75
5632 06:52:00.726625 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =95
5633 06:52:00.727160
5634 06:52:00.727537
5635 06:52:00.727883 ==
5636 06:52:00.730075 Dram Type= 6, Freq= 0, CH_1, rank 1
5637 06:52:00.732888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5638 06:52:00.733363 ==
5639 06:52:00.733734
5640 06:52:00.736629
5641 06:52:00.737219 TX Vref Scan disable
5642 06:52:00.739769 == TX Byte 0 ==
5643 06:52:00.743318 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5644 06:52:00.746807 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5645 06:52:00.749799 == TX Byte 1 ==
5646 06:52:00.752982 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5647 06:52:00.756301 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5648 06:52:00.756921 ==
5649 06:52:00.761757 Dram Type= 6, Freq= 0, CH_1, rank 1
5650 06:52:00.766361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5651 06:52:00.766926 ==
5652 06:52:00.767301
5653 06:52:00.767648
5654 06:52:00.767979 TX Vref Scan disable
5655 06:52:00.770714 == TX Byte 0 ==
5656 06:52:00.773806 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5657 06:52:00.780264 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5658 06:52:00.780858 == TX Byte 1 ==
5659 06:52:00.783646 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5660 06:52:00.790397 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5661 06:52:00.790933
5662 06:52:00.791312 [DATLAT]
5663 06:52:00.791660 Freq=933, CH1 RK1
5664 06:52:00.791991
5665 06:52:00.793465 DATLAT Default: 0xb
5666 06:52:00.793935 0, 0xFFFF, sum = 0
5667 06:52:00.797169 1, 0xFFFF, sum = 0
5668 06:52:00.797742 2, 0xFFFF, sum = 0
5669 06:52:00.801379 3, 0xFFFF, sum = 0
5670 06:52:00.803950 4, 0xFFFF, sum = 0
5671 06:52:00.804504 5, 0xFFFF, sum = 0
5672 06:52:00.806739 6, 0xFFFF, sum = 0
5673 06:52:00.807285 7, 0xFFFF, sum = 0
5674 06:52:00.811274 8, 0xFFFF, sum = 0
5675 06:52:00.811796 9, 0xFFFF, sum = 0
5676 06:52:00.814438 10, 0x0, sum = 1
5677 06:52:00.814918 11, 0x0, sum = 2
5678 06:52:00.817079 12, 0x0, sum = 3
5679 06:52:00.817552 13, 0x0, sum = 4
5680 06:52:00.817945 best_step = 11
5681 06:52:00.818344
5682 06:52:00.820343 ==
5683 06:52:00.823550 Dram Type= 6, Freq= 0, CH_1, rank 1
5684 06:52:00.826808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5685 06:52:00.827280 ==
5686 06:52:00.827653 RX Vref Scan: 0
5687 06:52:00.827997
5688 06:52:00.830237 RX Vref 0 -> 0, step: 1
5689 06:52:00.830775
5690 06:52:00.833361 RX Delay -77 -> 252, step: 4
5691 06:52:00.840172 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5692 06:52:00.843494 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5693 06:52:00.846596 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5694 06:52:00.850152 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5695 06:52:00.853445 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5696 06:52:00.857552 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5697 06:52:00.862902 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5698 06:52:00.866457 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5699 06:52:00.870218 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5700 06:52:00.873374 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5701 06:52:00.876867 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5702 06:52:00.883680 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5703 06:52:00.886819 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5704 06:52:00.889751 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5705 06:52:00.893107 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5706 06:52:00.896556 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5707 06:52:00.897141 ==
5708 06:52:00.899724 Dram Type= 6, Freq= 0, CH_1, rank 1
5709 06:52:00.906345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5710 06:52:00.906887 ==
5711 06:52:00.907262 DQS Delay:
5712 06:52:00.909202 DQS0 = 0, DQS1 = 0
5713 06:52:00.909672 DQM Delay:
5714 06:52:00.910045 DQM0 = 95, DQM1 = 87
5715 06:52:00.913904 DQ Delay:
5716 06:52:00.916340 DQ0 =96, DQ1 =92, DQ2 =88, DQ3 =92
5717 06:52:00.919797 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =94
5718 06:52:00.922520 DQ8 =74, DQ9 =76, DQ10 =86, DQ11 =80
5719 06:52:00.926830 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5720 06:52:00.927396
5721 06:52:00.927770
5722 06:52:00.932829 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5723 06:52:00.935798 CH1 RK1: MR19=505, MR18=2222
5724 06:52:00.943311 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5725 06:52:00.946188 [RxdqsGatingPostProcess] freq 933
5726 06:52:00.949198 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5727 06:52:00.952427 Pre-setting of DQS Precalculation
5728 06:52:00.959683 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5729 06:52:00.966086 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5730 06:52:00.972355 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5731 06:52:00.972880
5732 06:52:00.973390
5733 06:52:00.975730 [Calibration Summary] 1866 Mbps
5734 06:52:00.976292 CH 0, Rank 0
5735 06:52:00.979642 SW Impedance : PASS
5736 06:52:00.982958 DUTY Scan : NO K
5737 06:52:00.983562 ZQ Calibration : PASS
5738 06:52:00.985554 Jitter Meter : NO K
5739 06:52:00.989483 CBT Training : PASS
5740 06:52:00.989947 Write leveling : PASS
5741 06:52:00.992688 RX DQS gating : PASS
5742 06:52:00.996072 RX DQ/DQS(RDDQC) : PASS
5743 06:52:00.996645 TX DQ/DQS : PASS
5744 06:52:00.999324 RX DATLAT : PASS
5745 06:52:01.002283 RX DQ/DQS(Engine): PASS
5746 06:52:01.002858 TX OE : NO K
5747 06:52:01.005960 All Pass.
5748 06:52:01.006531
5749 06:52:01.006899 CH 0, Rank 1
5750 06:52:01.009617 SW Impedance : PASS
5751 06:52:01.010181 DUTY Scan : NO K
5752 06:52:01.012332 ZQ Calibration : PASS
5753 06:52:01.015530 Jitter Meter : NO K
5754 06:52:01.015994 CBT Training : PASS
5755 06:52:01.019353 Write leveling : PASS
5756 06:52:01.022669 RX DQS gating : PASS
5757 06:52:01.023228 RX DQ/DQS(RDDQC) : PASS
5758 06:52:01.026373 TX DQ/DQS : PASS
5759 06:52:01.026839 RX DATLAT : PASS
5760 06:52:01.029331 RX DQ/DQS(Engine): PASS
5761 06:52:01.032859 TX OE : NO K
5762 06:52:01.033425 All Pass.
5763 06:52:01.033795
5764 06:52:01.034134 CH 1, Rank 0
5765 06:52:01.035511 SW Impedance : PASS
5766 06:52:01.038795 DUTY Scan : NO K
5767 06:52:01.039377 ZQ Calibration : PASS
5768 06:52:01.042196 Jitter Meter : NO K
5769 06:52:01.045552 CBT Training : PASS
5770 06:52:01.046053 Write leveling : PASS
5771 06:52:01.048625 RX DQS gating : PASS
5772 06:52:01.052019 RX DQ/DQS(RDDQC) : PASS
5773 06:52:01.052481 TX DQ/DQS : PASS
5774 06:52:01.055999 RX DATLAT : PASS
5775 06:52:01.061006 RX DQ/DQS(Engine): PASS
5776 06:52:01.061537 TX OE : NO K
5777 06:52:01.062352 All Pass.
5778 06:52:01.062743
5779 06:52:01.063367 CH 1, Rank 1
5780 06:52:01.065490 SW Impedance : PASS
5781 06:52:01.065992 DUTY Scan : NO K
5782 06:52:01.068834 ZQ Calibration : PASS
5783 06:52:01.071664 Jitter Meter : NO K
5784 06:52:01.072191 CBT Training : PASS
5785 06:52:01.075410 Write leveling : PASS
5786 06:52:01.078917 RX DQS gating : PASS
5787 06:52:01.079377 RX DQ/DQS(RDDQC) : PASS
5788 06:52:01.082099 TX DQ/DQS : PASS
5789 06:52:01.082573 RX DATLAT : PASS
5790 06:52:01.085043 RX DQ/DQS(Engine): PASS
5791 06:52:01.088062 TX OE : NO K
5792 06:52:01.088543 All Pass.
5793 06:52:01.089042
5794 06:52:01.091968 DramC Write-DBI off
5795 06:52:01.094980 PER_BANK_REFRESH: Hybrid Mode
5796 06:52:01.095478 TX_TRACKING: ON
5797 06:52:01.105566 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5798 06:52:01.108832 [FAST_K] Save calibration result to emmc
5799 06:52:01.112579 dramc_set_vcore_voltage set vcore to 650000
5800 06:52:01.113125 Read voltage for 400, 6
5801 06:52:01.115684 Vio18 = 0
5802 06:52:01.116210 Vcore = 650000
5803 06:52:01.116546 Vdram = 0
5804 06:52:01.118651 Vddq = 0
5805 06:52:01.119176 Vmddr = 0
5806 06:52:01.125175 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5807 06:52:01.128436 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5808 06:52:01.131469 MEM_TYPE=3, freq_sel=20
5809 06:52:01.134582 sv_algorithm_assistance_LP4_800
5810 06:52:01.138818 ============ PULL DRAM RESETB DOWN ============
5811 06:52:01.142001 ========== PULL DRAM RESETB DOWN end =========
5812 06:52:01.148362 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5813 06:52:01.151584 ===================================
5814 06:52:01.152004 LPDDR4 DRAM CONFIGURATION
5815 06:52:01.155779 ===================================
5816 06:52:01.158654 EX_ROW_EN[0] = 0x0
5817 06:52:01.159219 EX_ROW_EN[1] = 0x0
5818 06:52:01.161595 LP4Y_EN = 0x0
5819 06:52:01.164463 WORK_FSP = 0x0
5820 06:52:01.164971 WL = 0x2
5821 06:52:01.168221 RL = 0x2
5822 06:52:01.168846 BL = 0x2
5823 06:52:01.171625 RPST = 0x0
5824 06:52:01.172200 RD_PRE = 0x0
5825 06:52:01.174847 WR_PRE = 0x1
5826 06:52:01.175418 WR_PST = 0x0
5827 06:52:01.178267 DBI_WR = 0x0
5828 06:52:01.178838 DBI_RD = 0x0
5829 06:52:01.181750 OTF = 0x1
5830 06:52:01.184566 ===================================
5831 06:52:01.187754 ===================================
5832 06:52:01.188212 ANA top config
5833 06:52:01.191233 ===================================
5834 06:52:01.194907 DLL_ASYNC_EN = 0
5835 06:52:01.198016 ALL_SLAVE_EN = 1
5836 06:52:01.198581 NEW_RANK_MODE = 1
5837 06:52:01.201039 DLL_IDLE_MODE = 1
5838 06:52:01.204213 LP45_APHY_COMB_EN = 1
5839 06:52:01.207993 TX_ODT_DIS = 1
5840 06:52:01.211561 NEW_8X_MODE = 1
5841 06:52:01.214857 ===================================
5842 06:52:01.217832 ===================================
5843 06:52:01.218299 data_rate = 800
5844 06:52:01.221031 CKR = 1
5845 06:52:01.224819 DQ_P2S_RATIO = 4
5846 06:52:01.227598 ===================================
5847 06:52:01.231084 CA_P2S_RATIO = 4
5848 06:52:01.234639 DQ_CA_OPEN = 0
5849 06:52:01.237900 DQ_SEMI_OPEN = 1
5850 06:52:01.238386 CA_SEMI_OPEN = 1
5851 06:52:01.241456 CA_FULL_RATE = 0
5852 06:52:01.245615 DQ_CKDIV4_EN = 0
5853 06:52:01.248141 CA_CKDIV4_EN = 1
5854 06:52:01.250878 CA_PREDIV_EN = 0
5855 06:52:01.254222 PH8_DLY = 0
5856 06:52:01.254739 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5857 06:52:01.257462 DQ_AAMCK_DIV = 0
5858 06:52:01.261105 CA_AAMCK_DIV = 0
5859 06:52:01.264535 CA_ADMCK_DIV = 4
5860 06:52:01.267562 DQ_TRACK_CA_EN = 0
5861 06:52:01.270972 CA_PICK = 800
5862 06:52:01.273893 CA_MCKIO = 400
5863 06:52:01.274313 MCKIO_SEMI = 400
5864 06:52:01.278359 PLL_FREQ = 3016
5865 06:52:01.280467 DQ_UI_PI_RATIO = 32
5866 06:52:01.284104 CA_UI_PI_RATIO = 32
5867 06:52:01.287303 ===================================
5868 06:52:01.290834 ===================================
5869 06:52:01.293803 memory_type:LPDDR4
5870 06:52:01.294221 GP_NUM : 10
5871 06:52:01.296884 SRAM_EN : 1
5872 06:52:01.300488 MD32_EN : 0
5873 06:52:01.304585 ===================================
5874 06:52:01.305182 [ANA_INIT] >>>>>>>>>>>>>>
5875 06:52:01.307375 <<<<<< [CONFIGURE PHASE]: ANA_TX
5876 06:52:01.311249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5877 06:52:01.314372 ===================================
5878 06:52:01.316884 data_rate = 800,PCW = 0X7400
5879 06:52:01.321417 ===================================
5880 06:52:01.323427 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5881 06:52:01.330298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5882 06:52:01.340416 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5883 06:52:01.343554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5884 06:52:01.350480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5885 06:52:01.353901 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5886 06:52:01.354420 [ANA_INIT] flow start
5887 06:52:01.358378 [ANA_INIT] PLL >>>>>>>>
5888 06:52:01.360483 [ANA_INIT] PLL <<<<<<<<
5889 06:52:01.361019 [ANA_INIT] MIDPI >>>>>>>>
5890 06:52:01.363513 [ANA_INIT] MIDPI <<<<<<<<
5891 06:52:01.367273 [ANA_INIT] DLL >>>>>>>>
5892 06:52:01.367693 [ANA_INIT] flow end
5893 06:52:01.374156 ============ LP4 DIFF to SE enter ============
5894 06:52:01.376817 ============ LP4 DIFF to SE exit ============
5895 06:52:01.377239 [ANA_INIT] <<<<<<<<<<<<<
5896 06:52:01.380428 [Flow] Enable top DCM control >>>>>
5897 06:52:01.383922 [Flow] Enable top DCM control <<<<<
5898 06:52:01.387898 Enable DLL master slave shuffle
5899 06:52:01.393301 ==============================================================
5900 06:52:01.396462 Gating Mode config
5901 06:52:01.400341 ==============================================================
5902 06:52:01.403329 Config description:
5903 06:52:01.413375 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5904 06:52:01.419848 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5905 06:52:01.423155 SELPH_MODE 0: By rank 1: By Phase
5906 06:52:01.430669 ==============================================================
5907 06:52:01.433704 GAT_TRACK_EN = 0
5908 06:52:01.436228 RX_GATING_MODE = 2
5909 06:52:01.439781 RX_GATING_TRACK_MODE = 2
5910 06:52:01.443045 SELPH_MODE = 1
5911 06:52:01.443513 PICG_EARLY_EN = 1
5912 06:52:01.447286 VALID_LAT_VALUE = 1
5913 06:52:01.453300 ==============================================================
5914 06:52:01.455910 Enter into Gating configuration >>>>
5915 06:52:01.459643 Exit from Gating configuration <<<<
5916 06:52:01.462903 Enter into DVFS_PRE_config >>>>>
5917 06:52:01.472786 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5918 06:52:01.476162 Exit from DVFS_PRE_config <<<<<
5919 06:52:01.479664 Enter into PICG configuration >>>>
5920 06:52:01.482732 Exit from PICG configuration <<<<
5921 06:52:01.486924 [RX_INPUT] configuration >>>>>
5922 06:52:01.489431 [RX_INPUT] configuration <<<<<
5923 06:52:01.492883 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5924 06:52:01.500001 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5925 06:52:01.505959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5926 06:52:01.512617 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5927 06:52:01.519622 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5928 06:52:01.526085 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5929 06:52:01.529307 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5930 06:52:01.532780 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5931 06:52:01.536102 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5932 06:52:01.542300 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5933 06:52:01.545156 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5934 06:52:01.549774 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5935 06:52:01.552214 ===================================
5936 06:52:01.555688 LPDDR4 DRAM CONFIGURATION
5937 06:52:01.559135 ===================================
5938 06:52:01.559602 EX_ROW_EN[0] = 0x0
5939 06:52:01.562269 EX_ROW_EN[1] = 0x0
5940 06:52:01.562839 LP4Y_EN = 0x0
5941 06:52:01.564992 WORK_FSP = 0x0
5942 06:52:01.568494 WL = 0x2
5943 06:52:01.569152 RL = 0x2
5944 06:52:01.571849 BL = 0x2
5945 06:52:01.572312 RPST = 0x0
5946 06:52:01.578116 RD_PRE = 0x0
5947 06:52:01.578653 WR_PRE = 0x1
5948 06:52:01.579394 WR_PST = 0x0
5949 06:52:01.579768 DBI_WR = 0x0
5950 06:52:01.581975 DBI_RD = 0x0
5951 06:52:01.582440 OTF = 0x1
5952 06:52:01.584859 ===================================
5953 06:52:01.588642 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5954 06:52:01.595150 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5955 06:52:01.598830 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5956 06:52:01.601767 ===================================
5957 06:52:01.605972 LPDDR4 DRAM CONFIGURATION
5958 06:52:01.608048 ===================================
5959 06:52:01.608513 EX_ROW_EN[0] = 0x10
5960 06:52:01.612054 EX_ROW_EN[1] = 0x0
5961 06:52:01.612514 LP4Y_EN = 0x0
5962 06:52:01.614705 WORK_FSP = 0x0
5963 06:52:01.615165 WL = 0x2
5964 06:52:01.619098 RL = 0x2
5965 06:52:01.621517 BL = 0x2
5966 06:52:01.621981 RPST = 0x0
5967 06:52:01.625348 RD_PRE = 0x0
5968 06:52:01.626083 WR_PRE = 0x1
5969 06:52:01.628533 WR_PST = 0x0
5970 06:52:01.629029 DBI_WR = 0x0
5971 06:52:01.631463 DBI_RD = 0x0
5972 06:52:01.632026 OTF = 0x1
5973 06:52:01.635377 ===================================
5974 06:52:01.641680 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5975 06:52:01.645531 nWR fixed to 30
5976 06:52:01.648629 [ModeRegInit_LP4] CH0 RK0
5977 06:52:01.649222 [ModeRegInit_LP4] CH0 RK1
5978 06:52:01.652002 [ModeRegInit_LP4] CH1 RK0
5979 06:52:01.655780 [ModeRegInit_LP4] CH1 RK1
5980 06:52:01.656409 match AC timing 18
5981 06:52:01.662214 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5982 06:52:01.665285 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5983 06:52:01.668744 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5984 06:52:01.675891 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5985 06:52:01.678970 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5986 06:52:01.679435 ==
5987 06:52:01.682000 Dram Type= 6, Freq= 0, CH_0, rank 0
5988 06:52:01.684857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5989 06:52:01.685342 ==
5990 06:52:01.691560 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5991 06:52:01.698306 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5992 06:52:01.701427 [CA 0] Center 36 (8~64) winsize 57
5993 06:52:01.705005 [CA 1] Center 36 (8~64) winsize 57
5994 06:52:01.708273 [CA 2] Center 36 (8~64) winsize 57
5995 06:52:01.711867 [CA 3] Center 36 (8~64) winsize 57
5996 06:52:01.712445 [CA 4] Center 36 (8~64) winsize 57
5997 06:52:01.715062 [CA 5] Center 36 (8~64) winsize 57
5998 06:52:01.715634
5999 06:52:01.721293 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6000 06:52:01.721848
6001 06:52:01.724566 [CATrainingPosCal] consider 1 rank data
6002 06:52:01.728354 u2DelayCellTimex100 = 270/100 ps
6003 06:52:01.731379 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6004 06:52:01.734543 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6005 06:52:01.737887 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6006 06:52:01.741486 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6007 06:52:01.745048 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6008 06:52:01.747628 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6009 06:52:01.748088
6010 06:52:01.751318 CA PerBit enable=1, Macro0, CA PI delay=36
6011 06:52:01.751793
6012 06:52:01.754946 [CBTSetCACLKResult] CA Dly = 36
6013 06:52:01.758163 CS Dly: 1 (0~32)
6014 06:52:01.758856 ==
6015 06:52:01.761656 Dram Type= 6, Freq= 0, CH_0, rank 1
6016 06:52:01.764593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6017 06:52:01.765216 ==
6018 06:52:01.770955 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6019 06:52:01.777344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6020 06:52:01.780648 [CA 0] Center 36 (8~64) winsize 57
6021 06:52:01.784063 [CA 1] Center 36 (8~64) winsize 57
6022 06:52:01.784528 [CA 2] Center 36 (8~64) winsize 57
6023 06:52:01.787112 [CA 3] Center 36 (8~64) winsize 57
6024 06:52:01.791251 [CA 4] Center 36 (8~64) winsize 57
6025 06:52:01.793976 [CA 5] Center 36 (8~64) winsize 57
6026 06:52:01.794437
6027 06:52:01.797449 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6028 06:52:01.797911
6029 06:52:01.804498 [CATrainingPosCal] consider 2 rank data
6030 06:52:01.805005 u2DelayCellTimex100 = 270/100 ps
6031 06:52:01.810614 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6032 06:52:01.814752 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6033 06:52:01.817388 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6034 06:52:01.821327 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6035 06:52:01.824576 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6036 06:52:01.828113 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6037 06:52:01.828690
6038 06:52:01.830410 CA PerBit enable=1, Macro0, CA PI delay=36
6039 06:52:01.830870
6040 06:52:01.834536 [CBTSetCACLKResult] CA Dly = 36
6041 06:52:01.837157 CS Dly: 1 (0~32)
6042 06:52:01.837827
6043 06:52:01.840536 ----->DramcWriteLeveling(PI) begin...
6044 06:52:01.841054 ==
6045 06:52:01.843605 Dram Type= 6, Freq= 0, CH_0, rank 0
6046 06:52:01.847098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6047 06:52:01.847605 ==
6048 06:52:01.850283 Write leveling (Byte 0): 32 => 0
6049 06:52:01.853991 Write leveling (Byte 1): 32 => 0
6050 06:52:01.857678 DramcWriteLeveling(PI) end<-----
6051 06:52:01.858441
6052 06:52:01.858875 ==
6053 06:52:01.861573 Dram Type= 6, Freq= 0, CH_0, rank 0
6054 06:52:01.864204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6055 06:52:01.864667 ==
6056 06:52:01.867169 [Gating] SW mode calibration
6057 06:52:01.873569 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6058 06:52:01.881141 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6059 06:52:01.883832 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6060 06:52:01.887610 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6061 06:52:01.894026 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6062 06:52:01.897233 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6063 06:52:01.901643 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6064 06:52:01.906666 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6065 06:52:01.910313 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6066 06:52:01.914623 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6067 06:52:01.919936 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6068 06:52:01.920503 Total UI for P1: 0, mck2ui 16
6069 06:52:01.927378 best dqsien dly found for B0: ( 0, 10, 16)
6070 06:52:01.927950 Total UI for P1: 0, mck2ui 16
6071 06:52:01.933416 best dqsien dly found for B1: ( 0, 10, 24)
6072 06:52:01.936144 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6073 06:52:01.940872 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6074 06:52:01.941611
6075 06:52:01.943409 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6076 06:52:01.946955 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6077 06:52:01.949580 [Gating] SW calibration Done
6078 06:52:01.950179 ==
6079 06:52:01.953141 Dram Type= 6, Freq= 0, CH_0, rank 0
6080 06:52:01.956253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6081 06:52:01.956873 ==
6082 06:52:01.959753 RX Vref Scan: 0
6083 06:52:01.960212
6084 06:52:01.960575 RX Vref 0 -> 0, step: 1
6085 06:52:01.962557
6086 06:52:01.963013 RX Delay -410 -> 252, step: 16
6087 06:52:01.969454 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6088 06:52:01.973225 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6089 06:52:01.976062 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6090 06:52:01.979537 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6091 06:52:01.986709 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6092 06:52:01.989611 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6093 06:52:01.993489 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6094 06:52:01.995946 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6095 06:52:02.002777 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6096 06:52:02.005869 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6097 06:52:02.010436 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6098 06:52:02.012821 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6099 06:52:02.018998 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6100 06:52:02.022425 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6101 06:52:02.025612 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6102 06:52:02.032496 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6103 06:52:02.033093 ==
6104 06:52:02.036543 Dram Type= 6, Freq= 0, CH_0, rank 0
6105 06:52:02.039092 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6106 06:52:02.039563 ==
6107 06:52:02.039930 DQS Delay:
6108 06:52:02.043138 DQS0 = 51, DQS1 = 59
6109 06:52:02.043612 DQM Delay:
6110 06:52:02.046270 DQM0 = 12, DQM1 = 16
6111 06:52:02.046734 DQ Delay:
6112 06:52:02.049139 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6113 06:52:02.052343 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6114 06:52:02.055820 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6115 06:52:02.058897 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6116 06:52:02.059466
6117 06:52:02.059839
6118 06:52:02.060184 ==
6119 06:52:02.063773 Dram Type= 6, Freq= 0, CH_0, rank 0
6120 06:52:02.066109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6121 06:52:02.066580 ==
6122 06:52:02.066949
6123 06:52:02.067285
6124 06:52:02.069672 TX Vref Scan disable
6125 06:52:02.070136 == TX Byte 0 ==
6126 06:52:02.075613 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6127 06:52:02.078945 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6128 06:52:02.079507 == TX Byte 1 ==
6129 06:52:02.086615 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6130 06:52:02.088372 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6131 06:52:02.088891 ==
6132 06:52:02.091817 Dram Type= 6, Freq= 0, CH_0, rank 0
6133 06:52:02.095626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6134 06:52:02.096163 ==
6135 06:52:02.098670
6136 06:52:02.099223
6137 06:52:02.099592 TX Vref Scan disable
6138 06:52:02.101970 == TX Byte 0 ==
6139 06:52:02.104915 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6140 06:52:02.108679 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6141 06:52:02.112029 == TX Byte 1 ==
6142 06:52:02.114856 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6143 06:52:02.118525 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6144 06:52:02.119076
6145 06:52:02.121789 [DATLAT]
6146 06:52:02.122322 Freq=400, CH0 RK0
6147 06:52:02.122694
6148 06:52:02.125090 DATLAT Default: 0xf
6149 06:52:02.125716 0, 0xFFFF, sum = 0
6150 06:52:02.128072 1, 0xFFFF, sum = 0
6151 06:52:02.128544 2, 0xFFFF, sum = 0
6152 06:52:02.131281 3, 0xFFFF, sum = 0
6153 06:52:02.131752 4, 0xFFFF, sum = 0
6154 06:52:02.134904 5, 0xFFFF, sum = 0
6155 06:52:02.135468 6, 0xFFFF, sum = 0
6156 06:52:02.138968 7, 0xFFFF, sum = 0
6157 06:52:02.139437 8, 0xFFFF, sum = 0
6158 06:52:02.142319 9, 0xFFFF, sum = 0
6159 06:52:02.142908 10, 0xFFFF, sum = 0
6160 06:52:02.144515 11, 0xFFFF, sum = 0
6161 06:52:02.145039 12, 0x0, sum = 1
6162 06:52:02.148275 13, 0x0, sum = 2
6163 06:52:02.148878 14, 0x0, sum = 3
6164 06:52:02.151856 15, 0x0, sum = 4
6165 06:52:02.152327 best_step = 13
6166 06:52:02.152696
6167 06:52:02.153103 ==
6168 06:52:02.154820 Dram Type= 6, Freq= 0, CH_0, rank 0
6169 06:52:02.161829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6170 06:52:02.162305 ==
6171 06:52:02.162671 RX Vref Scan: 1
6172 06:52:02.163015
6173 06:52:02.165200 RX Vref 0 -> 0, step: 1
6174 06:52:02.165661
6175 06:52:02.167769 RX Delay -359 -> 252, step: 8
6176 06:52:02.168230
6177 06:52:02.171276 Set Vref, RX VrefLevel [Byte0]: 46
6178 06:52:02.174573 [Byte1]: 49
6179 06:52:02.177516
6180 06:52:02.177995 Final RX Vref Byte 0 = 46 to rank0
6181 06:52:02.181437 Final RX Vref Byte 1 = 49 to rank0
6182 06:52:02.185027 Final RX Vref Byte 0 = 46 to rank1
6183 06:52:02.188268 Final RX Vref Byte 1 = 49 to rank1==
6184 06:52:02.191033 Dram Type= 6, Freq= 0, CH_0, rank 0
6185 06:52:02.197899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6186 06:52:02.198458 ==
6187 06:52:02.198855 DQS Delay:
6188 06:52:02.201602 DQS0 = 52, DQS1 = 68
6189 06:52:02.202177 DQM Delay:
6190 06:52:02.202552 DQM0 = 9, DQM1 = 16
6191 06:52:02.205056 DQ Delay:
6192 06:52:02.205526 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6193 06:52:02.208399 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6194 06:52:02.210808 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6195 06:52:02.215137 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6196 06:52:02.215688
6197 06:52:02.216064
6198 06:52:02.224553 [DQSOSCAuto] RK0, (LSB)MR18= 0xa5a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6199 06:52:02.227566 CH0 RK0: MR19=C0C, MR18=A5A5
6200 06:52:02.234373 CH0_RK0: MR19=0xC0C, MR18=0xA5A5, DQSOSC=389, MR23=63, INC=390, DEC=260
6201 06:52:02.234915 ==
6202 06:52:02.237433 Dram Type= 6, Freq= 0, CH_0, rank 1
6203 06:52:02.241409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6204 06:52:02.241996 ==
6205 06:52:02.244381 [Gating] SW mode calibration
6206 06:52:02.250681 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6207 06:52:02.253657 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6208 06:52:02.260562 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6209 06:52:02.264345 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6210 06:52:02.268088 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6211 06:52:02.274284 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6212 06:52:02.277473 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6213 06:52:02.280815 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6214 06:52:02.287847 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6215 06:52:02.291072 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6216 06:52:02.294307 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6217 06:52:02.297430 Total UI for P1: 0, mck2ui 16
6218 06:52:02.300863 best dqsien dly found for B0: ( 0, 10, 16)
6219 06:52:02.303757 Total UI for P1: 0, mck2ui 16
6220 06:52:02.307300 best dqsien dly found for B1: ( 0, 10, 24)
6221 06:52:02.310465 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6222 06:52:02.313888 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6223 06:52:02.317128
6224 06:52:02.321972 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6225 06:52:02.324303 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6226 06:52:02.327145 [Gating] SW calibration Done
6227 06:52:02.327610 ==
6228 06:52:02.330673 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 06:52:02.333414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6230 06:52:02.333895 ==
6231 06:52:02.336829 RX Vref Scan: 0
6232 06:52:02.337400
6233 06:52:02.337771 RX Vref 0 -> 0, step: 1
6234 06:52:02.338196
6235 06:52:02.339992 RX Delay -410 -> 252, step: 16
6236 06:52:02.343204 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6237 06:52:02.350165 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6238 06:52:02.353281 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6239 06:52:02.357068 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6240 06:52:02.359680 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6241 06:52:02.366547 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6242 06:52:02.369906 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6243 06:52:02.373105 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6244 06:52:02.376746 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6245 06:52:02.384190 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6246 06:52:02.386577 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6247 06:52:02.389971 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6248 06:52:02.397161 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6249 06:52:02.399597 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6250 06:52:02.403065 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6251 06:52:02.407403 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6252 06:52:02.407945 ==
6253 06:52:02.409578 Dram Type= 6, Freq= 0, CH_0, rank 1
6254 06:52:02.416924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6255 06:52:02.417522 ==
6256 06:52:02.417902 DQS Delay:
6257 06:52:02.419878 DQS0 = 43, DQS1 = 59
6258 06:52:02.420485 DQM Delay:
6259 06:52:02.422703 DQM0 = 7, DQM1 = 15
6260 06:52:02.423166 DQ Delay:
6261 06:52:02.426057 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6262 06:52:02.429419 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6263 06:52:02.429884 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6264 06:52:02.436112 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6265 06:52:02.436681
6266 06:52:02.437111
6267 06:52:02.437459 ==
6268 06:52:02.441211 Dram Type= 6, Freq= 0, CH_0, rank 1
6269 06:52:02.442515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6270 06:52:02.442981 ==
6271 06:52:02.443351
6272 06:52:02.443694
6273 06:52:02.445812 TX Vref Scan disable
6274 06:52:02.446273 == TX Byte 0 ==
6275 06:52:02.449530 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6276 06:52:02.455858 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6277 06:52:02.456330 == TX Byte 1 ==
6278 06:52:02.459456 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6279 06:52:02.465690 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6280 06:52:02.466350 ==
6281 06:52:02.468913 Dram Type= 6, Freq= 0, CH_0, rank 1
6282 06:52:02.472122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6283 06:52:02.472588 ==
6284 06:52:02.473006
6285 06:52:02.473365
6286 06:52:02.475489 TX Vref Scan disable
6287 06:52:02.475949 == TX Byte 0 ==
6288 06:52:02.482504 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6289 06:52:02.485857 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6290 06:52:02.486428 == TX Byte 1 ==
6291 06:52:02.492162 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6292 06:52:02.495328 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6293 06:52:02.495790
6294 06:52:02.496158 [DATLAT]
6295 06:52:02.501879 Freq=400, CH0 RK1
6296 06:52:02.502340
6297 06:52:02.502704 DATLAT Default: 0xd
6298 06:52:02.503395 0, 0xFFFF, sum = 0
6299 06:52:02.503764 1, 0xFFFF, sum = 0
6300 06:52:02.506276 2, 0xFFFF, sum = 0
6301 06:52:02.506699 3, 0xFFFF, sum = 0
6302 06:52:02.508597 4, 0xFFFF, sum = 0
6303 06:52:02.509090 5, 0xFFFF, sum = 0
6304 06:52:02.512157 6, 0xFFFF, sum = 0
6305 06:52:02.512581 7, 0xFFFF, sum = 0
6306 06:52:02.516556 8, 0xFFFF, sum = 0
6307 06:52:02.516882 9, 0xFFFF, sum = 0
6308 06:52:02.518489 10, 0xFFFF, sum = 0
6309 06:52:02.518904 11, 0xFFFF, sum = 0
6310 06:52:02.522498 12, 0x0, sum = 1
6311 06:52:02.522817 13, 0x0, sum = 2
6312 06:52:02.526219 14, 0x0, sum = 3
6313 06:52:02.526540 15, 0x0, sum = 4
6314 06:52:02.528479 best_step = 13
6315 06:52:02.528726
6316 06:52:02.528906 ==
6317 06:52:02.532965 Dram Type= 6, Freq= 0, CH_0, rank 1
6318 06:52:02.535887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6319 06:52:02.536304 ==
6320 06:52:02.538865 RX Vref Scan: 0
6321 06:52:02.539424
6322 06:52:02.539818 RX Vref 0 -> 0, step: 1
6323 06:52:02.540137
6324 06:52:02.541812 RX Delay -359 -> 252, step: 8
6325 06:52:02.550173 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6326 06:52:02.553546 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6327 06:52:02.556867 iDelay=217, Bit 2, Center -40 (-287 ~ 208) 496
6328 06:52:02.560055 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6329 06:52:02.566530 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6330 06:52:02.569990 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6331 06:52:02.573363 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6332 06:52:02.576975 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6333 06:52:02.583453 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6334 06:52:02.586913 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6335 06:52:02.589761 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6336 06:52:02.597147 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6337 06:52:02.600603 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6338 06:52:02.603498 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6339 06:52:02.606444 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6340 06:52:02.612636 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6341 06:52:02.613080 ==
6342 06:52:02.616782 Dram Type= 6, Freq= 0, CH_0, rank 1
6343 06:52:02.619653 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6344 06:52:02.620074 ==
6345 06:52:02.620408 DQS Delay:
6346 06:52:02.622709 DQS0 = 52, DQS1 = 60
6347 06:52:02.623130 DQM Delay:
6348 06:52:02.625948 DQM0 = 11, DQM1 = 10
6349 06:52:02.626368 DQ Delay:
6350 06:52:02.629412 DQ0 =4, DQ1 =16, DQ2 =12, DQ3 =4
6351 06:52:02.633190 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6352 06:52:02.636517 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6353 06:52:02.639730 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6354 06:52:02.640146
6355 06:52:02.640476
6356 06:52:02.646036 [DQSOSCAuto] RK1, (LSB)MR18= 0xbbbb, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6357 06:52:02.649499 CH0 RK1: MR19=C0C, MR18=BBBB
6358 06:52:02.656013 CH0_RK1: MR19=0xC0C, MR18=0xBBBB, DQSOSC=386, MR23=63, INC=396, DEC=264
6359 06:52:02.659280 [RxdqsGatingPostProcess] freq 400
6360 06:52:02.665702 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6361 06:52:02.669098 Pre-setting of DQS Precalculation
6362 06:52:02.672181 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6363 06:52:02.672824 ==
6364 06:52:02.675696 Dram Type= 6, Freq= 0, CH_1, rank 0
6365 06:52:02.678750 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6366 06:52:02.682043 ==
6367 06:52:02.685869 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6368 06:52:02.691947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6369 06:52:02.695104 [CA 0] Center 36 (8~64) winsize 57
6370 06:52:02.698635 [CA 1] Center 36 (8~64) winsize 57
6371 06:52:02.701915 [CA 2] Center 36 (8~64) winsize 57
6372 06:52:02.705919 [CA 3] Center 36 (8~64) winsize 57
6373 06:52:02.708722 [CA 4] Center 36 (8~64) winsize 57
6374 06:52:02.712454 [CA 5] Center 36 (8~64) winsize 57
6375 06:52:02.712790
6376 06:52:02.716200 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6377 06:52:02.716498
6378 06:52:02.718273 [CATrainingPosCal] consider 1 rank data
6379 06:52:02.721746 u2DelayCellTimex100 = 270/100 ps
6380 06:52:02.725372 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6381 06:52:02.729068 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6382 06:52:02.731738 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6383 06:52:02.735527 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6384 06:52:02.738663 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6385 06:52:02.743317 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6386 06:52:02.743845
6387 06:52:02.748593 CA PerBit enable=1, Macro0, CA PI delay=36
6388 06:52:02.749147
6389 06:52:02.749485 [CBTSetCACLKResult] CA Dly = 36
6390 06:52:02.751442 CS Dly: 1 (0~32)
6391 06:52:02.751902 ==
6392 06:52:02.754769 Dram Type= 6, Freq= 0, CH_1, rank 1
6393 06:52:02.758346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6394 06:52:02.758875 ==
6395 06:52:02.765500 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6396 06:52:02.772085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6397 06:52:02.775203 [CA 0] Center 36 (8~64) winsize 57
6398 06:52:02.778029 [CA 1] Center 36 (8~64) winsize 57
6399 06:52:02.781638 [CA 2] Center 36 (8~64) winsize 57
6400 06:52:02.784502 [CA 3] Center 36 (8~64) winsize 57
6401 06:52:02.784959 [CA 4] Center 36 (8~64) winsize 57
6402 06:52:02.787808 [CA 5] Center 36 (8~64) winsize 57
6403 06:52:02.788229
6404 06:52:02.795365 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6405 06:52:02.795899
6406 06:52:02.798504 [CATrainingPosCal] consider 2 rank data
6407 06:52:02.801449 u2DelayCellTimex100 = 270/100 ps
6408 06:52:02.804362 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6409 06:52:02.808069 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6410 06:52:02.811289 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6411 06:52:02.814681 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6412 06:52:02.818408 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6413 06:52:02.822329 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6414 06:52:02.822909
6415 06:52:02.824948 CA PerBit enable=1, Macro0, CA PI delay=36
6416 06:52:02.825507
6417 06:52:02.828271 [CBTSetCACLKResult] CA Dly = 36
6418 06:52:02.831655 CS Dly: 1 (0~32)
6419 06:52:02.832122
6420 06:52:02.835088 ----->DramcWriteLeveling(PI) begin...
6421 06:52:02.835657 ==
6422 06:52:02.837471 Dram Type= 6, Freq= 0, CH_1, rank 0
6423 06:52:02.841934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6424 06:52:02.842404 ==
6425 06:52:02.844355 Write leveling (Byte 0): 32 => 0
6426 06:52:02.847800 Write leveling (Byte 1): 32 => 0
6427 06:52:02.850711 DramcWriteLeveling(PI) end<-----
6428 06:52:02.851176
6429 06:52:02.851541 ==
6430 06:52:02.854306 Dram Type= 6, Freq= 0, CH_1, rank 0
6431 06:52:02.857661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6432 06:52:02.858129 ==
6433 06:52:02.861183 [Gating] SW mode calibration
6434 06:52:02.867937 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6435 06:52:02.874735 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6436 06:52:02.878048 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 06:52:02.880637 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 06:52:02.887682 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 06:52:02.890535 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 06:52:02.893964 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 06:52:02.901239 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 06:52:02.903911 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 06:52:02.907319 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6444 06:52:02.913466 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 06:52:02.917101 Total UI for P1: 0, mck2ui 16
6446 06:52:02.920700 best dqsien dly found for B0: ( 0, 10, 16)
6447 06:52:02.923798 Total UI for P1: 0, mck2ui 16
6448 06:52:02.927759 best dqsien dly found for B1: ( 0, 10, 16)
6449 06:52:02.930235 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6450 06:52:02.934925 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6451 06:52:02.935505
6452 06:52:02.938728 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6453 06:52:02.940082 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6454 06:52:02.943478 [Gating] SW calibration Done
6455 06:52:02.943946 ==
6456 06:52:02.947354 Dram Type= 6, Freq= 0, CH_1, rank 0
6457 06:52:02.950159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6458 06:52:02.950629 ==
6459 06:52:02.953990 RX Vref Scan: 0
6460 06:52:02.954561
6461 06:52:02.957298 RX Vref 0 -> 0, step: 1
6462 06:52:02.957765
6463 06:52:02.958134 RX Delay -410 -> 252, step: 16
6464 06:52:02.963884 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6465 06:52:02.967996 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6466 06:52:02.970301 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6467 06:52:02.976749 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6468 06:52:02.980635 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6469 06:52:02.983248 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6470 06:52:02.987215 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6471 06:52:02.993769 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6472 06:52:02.996529 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6473 06:52:02.999959 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6474 06:52:03.003320 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6475 06:52:03.010397 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6476 06:52:03.012948 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6477 06:52:03.017162 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6478 06:52:03.019940 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6479 06:52:03.027186 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6480 06:52:03.027767 ==
6481 06:52:03.030252 Dram Type= 6, Freq= 0, CH_1, rank 0
6482 06:52:03.033566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6483 06:52:03.034144 ==
6484 06:52:03.034517 DQS Delay:
6485 06:52:03.036353 DQS0 = 43, DQS1 = 59
6486 06:52:03.036858 DQM Delay:
6487 06:52:03.041061 DQM0 = 6, DQM1 = 15
6488 06:52:03.041631 DQ Delay:
6489 06:52:03.043129 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6490 06:52:03.046697 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6491 06:52:03.050123 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6492 06:52:03.053415 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6493 06:52:03.053882
6494 06:52:03.054249
6495 06:52:03.054588 ==
6496 06:52:03.056941 Dram Type= 6, Freq= 0, CH_1, rank 0
6497 06:52:03.059955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6498 06:52:03.060526 ==
6499 06:52:03.060928
6500 06:52:03.061274
6501 06:52:03.062955 TX Vref Scan disable
6502 06:52:03.063420 == TX Byte 0 ==
6503 06:52:03.070529 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6504 06:52:03.073156 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6505 06:52:03.075937 == TX Byte 1 ==
6506 06:52:03.079951 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6507 06:52:03.082926 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6508 06:52:03.083497 ==
6509 06:52:03.087360 Dram Type= 6, Freq= 0, CH_1, rank 0
6510 06:52:03.089547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6511 06:52:03.090018 ==
6512 06:52:03.093681
6513 06:52:03.094148
6514 06:52:03.094516 TX Vref Scan disable
6515 06:52:03.095879 == TX Byte 0 ==
6516 06:52:03.100403 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6517 06:52:03.103054 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6518 06:52:03.107190 == TX Byte 1 ==
6519 06:52:03.109345 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6520 06:52:03.112913 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6521 06:52:03.113382
6522 06:52:03.116353 [DATLAT]
6523 06:52:03.116952 Freq=400, CH1 RK0
6524 06:52:03.117332
6525 06:52:03.119323 DATLAT Default: 0xf
6526 06:52:03.119889 0, 0xFFFF, sum = 0
6527 06:52:03.123134 1, 0xFFFF, sum = 0
6528 06:52:03.123723 2, 0xFFFF, sum = 0
6529 06:52:03.125955 3, 0xFFFF, sum = 0
6530 06:52:03.126524 4, 0xFFFF, sum = 0
6531 06:52:03.129002 5, 0xFFFF, sum = 0
6532 06:52:03.129475 6, 0xFFFF, sum = 0
6533 06:52:03.132632 7, 0xFFFF, sum = 0
6534 06:52:03.133236 8, 0xFFFF, sum = 0
6535 06:52:03.136160 9, 0xFFFF, sum = 0
6536 06:52:03.136789 10, 0xFFFF, sum = 0
6537 06:52:03.140228 11, 0xFFFF, sum = 0
6538 06:52:03.141018 12, 0x0, sum = 1
6539 06:52:03.142229 13, 0x0, sum = 2
6540 06:52:03.142700 14, 0x0, sum = 3
6541 06:52:03.146407 15, 0x0, sum = 4
6542 06:52:03.146880 best_step = 13
6543 06:52:03.147248
6544 06:52:03.147632 ==
6545 06:52:03.149232 Dram Type= 6, Freq= 0, CH_1, rank 0
6546 06:52:03.155884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6547 06:52:03.156482 ==
6548 06:52:03.156895 RX Vref Scan: 1
6549 06:52:03.157241
6550 06:52:03.158710 RX Vref 0 -> 0, step: 1
6551 06:52:03.159173
6552 06:52:03.162068 RX Delay -359 -> 252, step: 8
6553 06:52:03.162533
6554 06:52:03.165951 Set Vref, RX VrefLevel [Byte0]: 56
6555 06:52:03.168797 [Byte1]: 49
6556 06:52:03.172240
6557 06:52:03.172749 Final RX Vref Byte 0 = 56 to rank0
6558 06:52:03.175297 Final RX Vref Byte 1 = 49 to rank0
6559 06:52:03.179227 Final RX Vref Byte 0 = 56 to rank1
6560 06:52:03.182520 Final RX Vref Byte 1 = 49 to rank1==
6561 06:52:03.185457 Dram Type= 6, Freq= 0, CH_1, rank 0
6562 06:52:03.192047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6563 06:52:03.192601 ==
6564 06:52:03.193128 DQS Delay:
6565 06:52:03.195491 DQS0 = 52, DQS1 = 64
6566 06:52:03.195973 DQM Delay:
6567 06:52:03.196462 DQM0 = 10, DQM1 = 15
6568 06:52:03.198473 DQ Delay:
6569 06:52:03.202729 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6570 06:52:03.203169 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6571 06:52:03.205728 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6572 06:52:03.209138 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6573 06:52:03.209579
6574 06:52:03.211817
6575 06:52:03.219570 [DQSOSCAuto] RK0, (LSB)MR18= 0xdcdc, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6576 06:52:03.221743 CH1 RK0: MR19=C0C, MR18=DCDC
6577 06:52:03.228345 CH1_RK0: MR19=0xC0C, MR18=0xDCDC, DQSOSC=382, MR23=63, INC=404, DEC=269
6578 06:52:03.228904 ==
6579 06:52:03.231854 Dram Type= 6, Freq= 0, CH_1, rank 1
6580 06:52:03.234870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6581 06:52:03.235383 ==
6582 06:52:03.238274 [Gating] SW mode calibration
6583 06:52:03.244944 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6584 06:52:03.252265 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6585 06:52:03.254818 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6586 06:52:03.259102 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6587 06:52:03.265243 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6588 06:52:03.268254 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6589 06:52:03.271686 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6590 06:52:03.274911 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6591 06:52:03.281891 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6592 06:52:03.284575 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6593 06:52:03.287953 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6594 06:52:03.291504 Total UI for P1: 0, mck2ui 16
6595 06:52:03.294537 best dqsien dly found for B0: ( 0, 10, 16)
6596 06:52:03.298025 Total UI for P1: 0, mck2ui 16
6597 06:52:03.301755 best dqsien dly found for B1: ( 0, 10, 16)
6598 06:52:03.304757 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6599 06:52:03.311807 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6600 06:52:03.312341
6601 06:52:03.315243 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6602 06:52:03.318141 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6603 06:52:03.322684 [Gating] SW calibration Done
6604 06:52:03.323250 ==
6605 06:52:03.324406 Dram Type= 6, Freq= 0, CH_1, rank 1
6606 06:52:03.327725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6607 06:52:03.328192 ==
6608 06:52:03.330793 RX Vref Scan: 0
6609 06:52:03.331328
6610 06:52:03.331703 RX Vref 0 -> 0, step: 1
6611 06:52:03.332054
6612 06:52:03.334988 RX Delay -410 -> 252, step: 16
6613 06:52:03.341132 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6614 06:52:03.344183 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6615 06:52:03.347851 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6616 06:52:03.350593 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6617 06:52:03.357410 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6618 06:52:03.361029 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6619 06:52:03.364239 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6620 06:52:03.367543 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6621 06:52:03.374225 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6622 06:52:03.377543 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6623 06:52:03.380877 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6624 06:52:03.384380 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6625 06:52:03.391954 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6626 06:52:03.394618 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6627 06:52:03.397999 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6628 06:52:03.401205 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6629 06:52:03.404066 ==
6630 06:52:03.407284 Dram Type= 6, Freq= 0, CH_1, rank 1
6631 06:52:03.410565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6632 06:52:03.411033 ==
6633 06:52:03.411399 DQS Delay:
6634 06:52:03.413644 DQS0 = 43, DQS1 = 59
6635 06:52:03.414105 DQM Delay:
6636 06:52:03.417110 DQM0 = 10, DQM1 = 17
6637 06:52:03.417658 DQ Delay:
6638 06:52:03.420843 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6639 06:52:03.424212 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6640 06:52:03.428414 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6641 06:52:03.430610 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6642 06:52:03.431077
6643 06:52:03.431446
6644 06:52:03.431784 ==
6645 06:52:03.433522 Dram Type= 6, Freq= 0, CH_1, rank 1
6646 06:52:03.437183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6647 06:52:03.437748 ==
6648 06:52:03.438123
6649 06:52:03.438512
6650 06:52:03.440349 TX Vref Scan disable
6651 06:52:03.440850 == TX Byte 0 ==
6652 06:52:03.446954 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6653 06:52:03.450793 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6654 06:52:03.451371 == TX Byte 1 ==
6655 06:52:03.457146 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6656 06:52:03.460264 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6657 06:52:03.460772 ==
6658 06:52:03.463902 Dram Type= 6, Freq= 0, CH_1, rank 1
6659 06:52:03.467204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6660 06:52:03.467917 ==
6661 06:52:03.468303
6662 06:52:03.468646
6663 06:52:03.469919 TX Vref Scan disable
6664 06:52:03.470382 == TX Byte 0 ==
6665 06:52:03.476979 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6666 06:52:03.480065 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6667 06:52:03.480531 == TX Byte 1 ==
6668 06:52:03.486710 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6669 06:52:03.490095 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6670 06:52:03.490599
6671 06:52:03.490968 [DATLAT]
6672 06:52:03.494187 Freq=400, CH1 RK1
6673 06:52:03.494649
6674 06:52:03.495012 DATLAT Default: 0xd
6675 06:52:03.497149 0, 0xFFFF, sum = 0
6676 06:52:03.497616 1, 0xFFFF, sum = 0
6677 06:52:03.499955 2, 0xFFFF, sum = 0
6678 06:52:03.500513 3, 0xFFFF, sum = 0
6679 06:52:03.503626 4, 0xFFFF, sum = 0
6680 06:52:03.504245 5, 0xFFFF, sum = 0
6681 06:52:03.506999 6, 0xFFFF, sum = 0
6682 06:52:03.507564 7, 0xFFFF, sum = 0
6683 06:52:03.510205 8, 0xFFFF, sum = 0
6684 06:52:03.510838 9, 0xFFFF, sum = 0
6685 06:52:03.512850 10, 0xFFFF, sum = 0
6686 06:52:03.516539 11, 0xFFFF, sum = 0
6687 06:52:03.517134 12, 0x0, sum = 1
6688 06:52:03.517523 13, 0x0, sum = 2
6689 06:52:03.519359 14, 0x0, sum = 3
6690 06:52:03.519827 15, 0x0, sum = 4
6691 06:52:03.522863 best_step = 13
6692 06:52:03.523334
6693 06:52:03.523778 ==
6694 06:52:03.526188 Dram Type= 6, Freq= 0, CH_1, rank 1
6695 06:52:03.530881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6696 06:52:03.531346 ==
6697 06:52:03.533239 RX Vref Scan: 0
6698 06:52:03.533759
6699 06:52:03.534146 RX Vref 0 -> 0, step: 1
6700 06:52:03.534496
6701 06:52:03.536473 RX Delay -359 -> 252, step: 8
6702 06:52:03.544292 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6703 06:52:03.547953 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6704 06:52:03.551948 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6705 06:52:03.555106 iDelay=225, Bit 3, Center -40 (-287 ~ 208) 496
6706 06:52:03.561076 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6707 06:52:03.564850 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6708 06:52:03.568988 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6709 06:52:03.571410 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6710 06:52:03.577670 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6711 06:52:03.581856 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6712 06:52:03.584352 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6713 06:52:03.590684 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6714 06:52:03.594375 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6715 06:52:03.597691 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6716 06:52:03.600829 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6717 06:52:03.607624 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6718 06:52:03.608179 ==
6719 06:52:03.611140 Dram Type= 6, Freq= 0, CH_1, rank 1
6720 06:52:03.613982 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6721 06:52:03.614449 ==
6722 06:52:03.615027 DQS Delay:
6723 06:52:03.618044 DQS0 = 48, DQS1 = 64
6724 06:52:03.618506 DQM Delay:
6725 06:52:03.621569 DQM0 = 10, DQM1 = 15
6726 06:52:03.622029 DQ Delay:
6727 06:52:03.624015 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6728 06:52:03.627596 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6729 06:52:03.632085 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6730 06:52:03.633862 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6731 06:52:03.634324
6732 06:52:03.634692
6733 06:52:03.640744 [DQSOSCAuto] RK1, (LSB)MR18= 0xa3a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6734 06:52:03.645080 CH1 RK1: MR19=C0C, MR18=A3A3
6735 06:52:03.651106 CH1_RK1: MR19=0xC0C, MR18=0xA3A3, DQSOSC=389, MR23=63, INC=390, DEC=260
6736 06:52:03.654550 [RxdqsGatingPostProcess] freq 400
6737 06:52:03.660542 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6738 06:52:03.664857 Pre-setting of DQS Precalculation
6739 06:52:03.667202 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6740 06:52:03.674188 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6741 06:52:03.680939 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6742 06:52:03.681406
6743 06:52:03.681773
6744 06:52:03.683694 [Calibration Summary] 800 Mbps
6745 06:52:03.687813 CH 0, Rank 0
6746 06:52:03.688275 SW Impedance : PASS
6747 06:52:03.690551 DUTY Scan : NO K
6748 06:52:03.693881 ZQ Calibration : PASS
6749 06:52:03.694346 Jitter Meter : NO K
6750 06:52:03.697553 CBT Training : PASS
6751 06:52:03.700615 Write leveling : PASS
6752 06:52:03.701198 RX DQS gating : PASS
6753 06:52:03.704217 RX DQ/DQS(RDDQC) : PASS
6754 06:52:03.704679 TX DQ/DQS : PASS
6755 06:52:03.708644 RX DATLAT : PASS
6756 06:52:03.710873 RX DQ/DQS(Engine): PASS
6757 06:52:03.711335 TX OE : NO K
6758 06:52:03.714089 All Pass.
6759 06:52:03.714550
6760 06:52:03.714916 CH 0, Rank 1
6761 06:52:03.717163 SW Impedance : PASS
6762 06:52:03.717627 DUTY Scan : NO K
6763 06:52:03.720235 ZQ Calibration : PASS
6764 06:52:03.724001 Jitter Meter : NO K
6765 06:52:03.724539 CBT Training : PASS
6766 06:52:03.727506 Write leveling : NO K
6767 06:52:03.730498 RX DQS gating : PASS
6768 06:52:03.731051 RX DQ/DQS(RDDQC) : PASS
6769 06:52:03.735035 TX DQ/DQS : PASS
6770 06:52:03.737030 RX DATLAT : PASS
6771 06:52:03.737496 RX DQ/DQS(Engine): PASS
6772 06:52:03.740283 TX OE : NO K
6773 06:52:03.740791 All Pass.
6774 06:52:03.741175
6775 06:52:03.743675 CH 1, Rank 0
6776 06:52:03.744136 SW Impedance : PASS
6777 06:52:03.747317 DUTY Scan : NO K
6778 06:52:03.750646 ZQ Calibration : PASS
6779 06:52:03.751202 Jitter Meter : NO K
6780 06:52:03.753516 CBT Training : PASS
6781 06:52:03.757228 Write leveling : PASS
6782 06:52:03.757790 RX DQS gating : PASS
6783 06:52:03.760265 RX DQ/DQS(RDDQC) : PASS
6784 06:52:03.760774 TX DQ/DQS : PASS
6785 06:52:03.763441 RX DATLAT : PASS
6786 06:52:03.766858 RX DQ/DQS(Engine): PASS
6787 06:52:03.767403 TX OE : NO K
6788 06:52:03.770250 All Pass.
6789 06:52:03.770715
6790 06:52:03.771085 CH 1, Rank 1
6791 06:52:03.774877 SW Impedance : PASS
6792 06:52:03.775434 DUTY Scan : NO K
6793 06:52:03.777078 ZQ Calibration : PASS
6794 06:52:03.779688 Jitter Meter : NO K
6795 06:52:03.780152 CBT Training : PASS
6796 06:52:03.782803 Write leveling : NO K
6797 06:52:03.786526 RX DQS gating : PASS
6798 06:52:03.786988 RX DQ/DQS(RDDQC) : PASS
6799 06:52:03.789669 TX DQ/DQS : PASS
6800 06:52:03.793352 RX DATLAT : PASS
6801 06:52:03.793816 RX DQ/DQS(Engine): PASS
6802 06:52:03.796808 TX OE : NO K
6803 06:52:03.797281 All Pass.
6804 06:52:03.797655
6805 06:52:03.800463 DramC Write-DBI off
6806 06:52:03.803133 PER_BANK_REFRESH: Hybrid Mode
6807 06:52:03.803598 TX_TRACKING: ON
6808 06:52:03.813080 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6809 06:52:03.816292 [FAST_K] Save calibration result to emmc
6810 06:52:03.819911 dramc_set_vcore_voltage set vcore to 725000
6811 06:52:03.823223 Read voltage for 1600, 0
6812 06:52:03.823689 Vio18 = 0
6813 06:52:03.824056 Vcore = 725000
6814 06:52:03.826464 Vdram = 0
6815 06:52:03.826929 Vddq = 0
6816 06:52:03.827299 Vmddr = 0
6817 06:52:03.832762 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6818 06:52:03.836250 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6819 06:52:03.839207 MEM_TYPE=3, freq_sel=13
6820 06:52:03.842634 sv_algorithm_assistance_LP4_3733
6821 06:52:03.846600 ============ PULL DRAM RESETB DOWN ============
6822 06:52:03.852394 ========== PULL DRAM RESETB DOWN end =========
6823 06:52:03.856062 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6824 06:52:03.858965 ===================================
6825 06:52:03.863204 LPDDR4 DRAM CONFIGURATION
6826 06:52:03.866188 ===================================
6827 06:52:03.866759 EX_ROW_EN[0] = 0x0
6828 06:52:03.869445 EX_ROW_EN[1] = 0x0
6829 06:52:03.870010 LP4Y_EN = 0x0
6830 06:52:03.872243 WORK_FSP = 0x1
6831 06:52:03.872841 WL = 0x5
6832 06:52:03.875896 RL = 0x5
6833 06:52:03.876461 BL = 0x2
6834 06:52:03.878716 RPST = 0x0
6835 06:52:03.879367 RD_PRE = 0x0
6836 06:52:03.882594 WR_PRE = 0x1
6837 06:52:03.885929 WR_PST = 0x1
6838 06:52:03.886395 DBI_WR = 0x0
6839 06:52:03.888836 DBI_RD = 0x0
6840 06:52:03.889299 OTF = 0x1
6841 06:52:03.891984 ===================================
6842 06:52:03.895211 ===================================
6843 06:52:03.895677 ANA top config
6844 06:52:03.898549 ===================================
6845 06:52:03.902808 DLL_ASYNC_EN = 0
6846 06:52:03.905321 ALL_SLAVE_EN = 0
6847 06:52:03.908984 NEW_RANK_MODE = 1
6848 06:52:03.912633 DLL_IDLE_MODE = 1
6849 06:52:03.913274 LP45_APHY_COMB_EN = 1
6850 06:52:03.915783 TX_ODT_DIS = 0
6851 06:52:03.918953 NEW_8X_MODE = 1
6852 06:52:03.922007 ===================================
6853 06:52:03.925255 ===================================
6854 06:52:03.929438 data_rate = 3200
6855 06:52:03.932533 CKR = 1
6856 06:52:03.933029 DQ_P2S_RATIO = 8
6857 06:52:03.935298 ===================================
6858 06:52:03.939412 CA_P2S_RATIO = 8
6859 06:52:03.941671 DQ_CA_OPEN = 0
6860 06:52:03.945688 DQ_SEMI_OPEN = 0
6861 06:52:03.949578 CA_SEMI_OPEN = 0
6862 06:52:03.951626 CA_FULL_RATE = 0
6863 06:52:03.952091 DQ_CKDIV4_EN = 0
6864 06:52:03.955132 CA_CKDIV4_EN = 0
6865 06:52:03.958435 CA_PREDIV_EN = 0
6866 06:52:03.962512 PH8_DLY = 12
6867 06:52:03.964988 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6868 06:52:03.968512 DQ_AAMCK_DIV = 4
6869 06:52:03.969117 CA_AAMCK_DIV = 4
6870 06:52:03.972324 CA_ADMCK_DIV = 4
6871 06:52:03.975021 DQ_TRACK_CA_EN = 0
6872 06:52:03.978498 CA_PICK = 1600
6873 06:52:03.981712 CA_MCKIO = 1600
6874 06:52:03.984899 MCKIO_SEMI = 0
6875 06:52:03.989231 PLL_FREQ = 3068
6876 06:52:03.991642 DQ_UI_PI_RATIO = 32
6877 06:52:03.992210 CA_UI_PI_RATIO = 0
6878 06:52:03.994959 ===================================
6879 06:52:03.997876 ===================================
6880 06:52:04.001705 memory_type:LPDDR4
6881 06:52:04.004996 GP_NUM : 10
6882 06:52:04.005462 SRAM_EN : 1
6883 06:52:04.007762 MD32_EN : 0
6884 06:52:04.011676 ===================================
6885 06:52:04.014719 [ANA_INIT] >>>>>>>>>>>>>>
6886 06:52:04.018111 <<<<<< [CONFIGURE PHASE]: ANA_TX
6887 06:52:04.021168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6888 06:52:04.025086 ===================================
6889 06:52:04.025649 data_rate = 3200,PCW = 0X7600
6890 06:52:04.027691 ===================================
6891 06:52:04.032881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6892 06:52:04.037622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6893 06:52:04.044614 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6894 06:52:04.048767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6895 06:52:04.052490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6896 06:52:04.054730 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6897 06:52:04.057741 [ANA_INIT] flow start
6898 06:52:04.061492 [ANA_INIT] PLL >>>>>>>>
6899 06:52:04.062049 [ANA_INIT] PLL <<<<<<<<
6900 06:52:04.063993 [ANA_INIT] MIDPI >>>>>>>>
6901 06:52:04.067970 [ANA_INIT] MIDPI <<<<<<<<
6902 06:52:04.068507 [ANA_INIT] DLL >>>>>>>>
6903 06:52:04.071431 [ANA_INIT] DLL <<<<<<<<
6904 06:52:04.074491 [ANA_INIT] flow end
6905 06:52:04.077675 ============ LP4 DIFF to SE enter ============
6906 06:52:04.083014 ============ LP4 DIFF to SE exit ============
6907 06:52:04.083933 [ANA_INIT] <<<<<<<<<<<<<
6908 06:52:04.087423 [Flow] Enable top DCM control >>>>>
6909 06:52:04.090560 [Flow] Enable top DCM control <<<<<
6910 06:52:04.094154 Enable DLL master slave shuffle
6911 06:52:04.097351 ==============================================================
6912 06:52:04.100681 Gating Mode config
6913 06:52:04.107955 ==============================================================
6914 06:52:04.108517 Config description:
6915 06:52:04.117686 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6916 06:52:04.124005 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6917 06:52:04.127694 SELPH_MODE 0: By rank 1: By Phase
6918 06:52:04.134175 ==============================================================
6919 06:52:04.137492 GAT_TRACK_EN = 1
6920 06:52:04.140338 RX_GATING_MODE = 2
6921 06:52:04.144114 RX_GATING_TRACK_MODE = 2
6922 06:52:04.147137 SELPH_MODE = 1
6923 06:52:04.150039 PICG_EARLY_EN = 1
6924 06:52:04.153751 VALID_LAT_VALUE = 1
6925 06:52:04.158691 ==============================================================
6926 06:52:04.160095 Enter into Gating configuration >>>>
6927 06:52:04.163589 Exit from Gating configuration <<<<
6928 06:52:04.167419 Enter into DVFS_PRE_config >>>>>
6929 06:52:04.180989 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6930 06:52:04.181597 Exit from DVFS_PRE_config <<<<<
6931 06:52:04.184372 Enter into PICG configuration >>>>
6932 06:52:04.187162 Exit from PICG configuration <<<<
6933 06:52:04.190098 [RX_INPUT] configuration >>>>>
6934 06:52:04.194524 [RX_INPUT] configuration <<<<<
6935 06:52:04.200098 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6936 06:52:04.204045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6937 06:52:04.211531 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6938 06:52:04.216620 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6939 06:52:04.223566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6940 06:52:04.229784 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6941 06:52:04.233174 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6942 06:52:04.236234 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6943 06:52:04.239953 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6944 06:52:04.246491 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6945 06:52:04.249763 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6946 06:52:04.253086 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6947 06:52:04.256377 ===================================
6948 06:52:04.259774 LPDDR4 DRAM CONFIGURATION
6949 06:52:04.262581 ===================================
6950 06:52:04.266868 EX_ROW_EN[0] = 0x0
6951 06:52:04.267339 EX_ROW_EN[1] = 0x0
6952 06:52:04.269354 LP4Y_EN = 0x0
6953 06:52:04.269823 WORK_FSP = 0x1
6954 06:52:04.273302 WL = 0x5
6955 06:52:04.273774 RL = 0x5
6956 06:52:04.276506 BL = 0x2
6957 06:52:04.277060 RPST = 0x0
6958 06:52:04.279778 RD_PRE = 0x0
6959 06:52:04.280323 WR_PRE = 0x1
6960 06:52:04.282869 WR_PST = 0x1
6961 06:52:04.283341 DBI_WR = 0x0
6962 06:52:04.286025 DBI_RD = 0x0
6963 06:52:04.286495 OTF = 0x1
6964 06:52:04.289221 ===================================
6965 06:52:04.295775 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6966 06:52:04.299323 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6967 06:52:04.302551 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6968 06:52:04.305814 ===================================
6969 06:52:04.309319 LPDDR4 DRAM CONFIGURATION
6970 06:52:04.312779 ===================================
6971 06:52:04.315845 EX_ROW_EN[0] = 0x10
6972 06:52:04.316404 EX_ROW_EN[1] = 0x0
6973 06:52:04.319150 LP4Y_EN = 0x0
6974 06:52:04.319706 WORK_FSP = 0x1
6975 06:52:04.322531 WL = 0x5
6976 06:52:04.323260 RL = 0x5
6977 06:52:04.325243 BL = 0x2
6978 06:52:04.325710 RPST = 0x0
6979 06:52:04.328948 RD_PRE = 0x0
6980 06:52:04.329501 WR_PRE = 0x1
6981 06:52:04.332337 WR_PST = 0x1
6982 06:52:04.332922 DBI_WR = 0x0
6983 06:52:04.335781 DBI_RD = 0x0
6984 06:52:04.336320 OTF = 0x1
6985 06:52:04.339078 ===================================
6986 06:52:04.345343 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6987 06:52:04.345820 ==
6988 06:52:04.348760 Dram Type= 6, Freq= 0, CH_0, rank 0
6989 06:52:04.355788 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6990 06:52:04.356317 ==
6991 06:52:04.356696 [Duty_Offset_Calibration]
6992 06:52:04.359170 B0:0 B1:2 CA:1
6993 06:52:04.359695
6994 06:52:04.361914 [DutyScan_Calibration_Flow] k_type=0
6995 06:52:04.371978
6996 06:52:04.372541 ==CLK 0==
6997 06:52:04.375473 Final CLK duty delay cell = 0
6998 06:52:04.378629 [0] MAX Duty = 5156%(X100), DQS PI = 20
6999 06:52:04.381426 [0] MIN Duty = 4938%(X100), DQS PI = 54
7000 06:52:04.382167 [0] AVG Duty = 5047%(X100)
7001 06:52:04.382589
7002 06:52:04.385156 CH0 CLK Duty spec in!! Max-Min= 218%
7003 06:52:04.391402 [DutyScan_Calibration_Flow] ====Done====
7004 06:52:04.391947
7005 06:52:04.394504 [DutyScan_Calibration_Flow] k_type=1
7006 06:52:04.411757
7007 06:52:04.412323 ==DQS 0 ==
7008 06:52:04.415205 Final DQS duty delay cell = 0
7009 06:52:04.418281 [0] MAX Duty = 5156%(X100), DQS PI = 32
7010 06:52:04.421381 [0] MIN Duty = 5031%(X100), DQS PI = 8
7011 06:52:04.422006 [0] AVG Duty = 5093%(X100)
7012 06:52:04.425137
7013 06:52:04.425698 ==DQS 1 ==
7014 06:52:04.428176 Final DQS duty delay cell = 0
7015 06:52:04.431106 [0] MAX Duty = 5031%(X100), DQS PI = 2
7016 06:52:04.434681 [0] MIN Duty = 4876%(X100), DQS PI = 16
7017 06:52:04.438245 [0] AVG Duty = 4953%(X100)
7018 06:52:04.438719
7019 06:52:04.441406 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7020 06:52:04.441960
7021 06:52:04.444417 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7022 06:52:04.448353 [DutyScan_Calibration_Flow] ====Done====
7023 06:52:04.448889
7024 06:52:04.451810 [DutyScan_Calibration_Flow] k_type=3
7025 06:52:04.468600
7026 06:52:04.469188 ==DQM 0 ==
7027 06:52:04.472380 Final DQM duty delay cell = 0
7028 06:52:04.474994 [0] MAX Duty = 5187%(X100), DQS PI = 22
7029 06:52:04.478439 [0] MIN Duty = 4907%(X100), DQS PI = 56
7030 06:52:04.481851 [0] AVG Duty = 5047%(X100)
7031 06:52:04.482444
7032 06:52:04.482880 ==DQM 1 ==
7033 06:52:04.485731 Final DQM duty delay cell = 0
7034 06:52:04.488365 [0] MAX Duty = 5062%(X100), DQS PI = 52
7035 06:52:04.491704 [0] MIN Duty = 4782%(X100), DQS PI = 14
7036 06:52:04.495104 [0] AVG Duty = 4922%(X100)
7037 06:52:04.495594
7038 06:52:04.500021 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7039 06:52:04.500490
7040 06:52:04.502168 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7041 06:52:04.505020 [DutyScan_Calibration_Flow] ====Done====
7042 06:52:04.505491
7043 06:52:04.508111 [DutyScan_Calibration_Flow] k_type=2
7044 06:52:04.525262
7045 06:52:04.525819 ==DQ 0 ==
7046 06:52:04.527972 Final DQ duty delay cell = 0
7047 06:52:04.531492 [0] MAX Duty = 5218%(X100), DQS PI = 18
7048 06:52:04.534908 [0] MIN Duty = 4938%(X100), DQS PI = 56
7049 06:52:04.535472 [0] AVG Duty = 5078%(X100)
7050 06:52:04.538051
7051 06:52:04.538617 ==DQ 1 ==
7052 06:52:04.541788 Final DQ duty delay cell = -4
7053 06:52:04.545632 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7054 06:52:04.548152 [-4] MIN Duty = 4844%(X100), DQS PI = 36
7055 06:52:04.548695 [-4] AVG Duty = 4969%(X100)
7056 06:52:04.551534
7057 06:52:04.555169 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7058 06:52:04.555719
7059 06:52:04.558507 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7060 06:52:04.561554 [DutyScan_Calibration_Flow] ====Done====
7061 06:52:04.562025 ==
7062 06:52:04.564656 Dram Type= 6, Freq= 0, CH_1, rank 0
7063 06:52:04.568286 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7064 06:52:04.568884 ==
7065 06:52:04.571626 [Duty_Offset_Calibration]
7066 06:52:04.572093 B0:0 B1:4 CA:-5
7067 06:52:04.572466
7068 06:52:04.575132 [DutyScan_Calibration_Flow] k_type=0
7069 06:52:04.585066
7070 06:52:04.585532 ==CLK 0==
7071 06:52:04.588863 Final CLK duty delay cell = 0
7072 06:52:04.592362 [0] MAX Duty = 5156%(X100), DQS PI = 22
7073 06:52:04.595832 [0] MIN Duty = 4906%(X100), DQS PI = 50
7074 06:52:04.596384 [0] AVG Duty = 5031%(X100)
7075 06:52:04.598730
7076 06:52:04.599264 CH1 CLK Duty spec in!! Max-Min= 250%
7077 06:52:04.606442 [DutyScan_Calibration_Flow] ====Done====
7078 06:52:04.607007
7079 06:52:04.609048 [DutyScan_Calibration_Flow] k_type=1
7080 06:52:04.624662
7081 06:52:04.625239 ==DQS 0 ==
7082 06:52:04.627590 Final DQS duty delay cell = 0
7083 06:52:04.631082 [0] MAX Duty = 5187%(X100), DQS PI = 20
7084 06:52:04.634185 [0] MIN Duty = 4876%(X100), DQS PI = 44
7085 06:52:04.638476 [0] AVG Duty = 5031%(X100)
7086 06:52:04.638948
7087 06:52:04.639324 ==DQS 1 ==
7088 06:52:04.640989 Final DQS duty delay cell = -4
7089 06:52:04.644453 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7090 06:52:04.647649 [-4] MIN Duty = 4875%(X100), DQS PI = 38
7091 06:52:04.651318 [-4] AVG Duty = 4937%(X100)
7092 06:52:04.651876
7093 06:52:04.654716 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7094 06:52:04.655180
7095 06:52:04.657385 CH1 DQS 1 Duty spec in!! Max-Min= 125%
7096 06:52:04.661243 [DutyScan_Calibration_Flow] ====Done====
7097 06:52:04.661701
7098 06:52:04.664273 [DutyScan_Calibration_Flow] k_type=3
7099 06:52:04.680262
7100 06:52:04.681016 ==DQM 0 ==
7101 06:52:04.683185 Final DQM duty delay cell = -4
7102 06:52:04.686781 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7103 06:52:04.690811 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7104 06:52:04.693329 [-4] AVG Duty = 4937%(X100)
7105 06:52:04.693800
7106 06:52:04.694248 ==DQM 1 ==
7107 06:52:04.698197 Final DQM duty delay cell = -4
7108 06:52:04.700837 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7109 06:52:04.703965 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7110 06:52:04.707131 [-4] AVG Duty = 5000%(X100)
7111 06:52:04.707717
7112 06:52:04.709748 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7113 06:52:04.710218
7114 06:52:04.713228 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7115 06:52:04.716797 [DutyScan_Calibration_Flow] ====Done====
7116 06:52:04.717406
7117 06:52:04.719719 [DutyScan_Calibration_Flow] k_type=2
7118 06:52:04.738131
7119 06:52:04.738694 ==DQ 0 ==
7120 06:52:04.740931 Final DQ duty delay cell = 0
7121 06:52:04.744399 [0] MAX Duty = 5093%(X100), DQS PI = 18
7122 06:52:04.748283 [0] MIN Duty = 4938%(X100), DQS PI = 46
7123 06:52:04.748938 [0] AVG Duty = 5015%(X100)
7124 06:52:04.751403
7125 06:52:04.751974 ==DQ 1 ==
7126 06:52:04.754169 Final DQ duty delay cell = 0
7127 06:52:04.757632 [0] MAX Duty = 5031%(X100), DQS PI = 4
7128 06:52:04.762567 [0] MIN Duty = 4876%(X100), DQS PI = 28
7129 06:52:04.763131 [0] AVG Duty = 4953%(X100)
7130 06:52:04.763511
7131 06:52:04.764834 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7132 06:52:04.767547
7133 06:52:04.770831 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7134 06:52:04.775003 [DutyScan_Calibration_Flow] ====Done====
7135 06:52:04.779200 nWR fixed to 30
7136 06:52:04.779772 [ModeRegInit_LP4] CH0 RK0
7137 06:52:04.780937 [ModeRegInit_LP4] CH0 RK1
7138 06:52:04.784584 [ModeRegInit_LP4] CH1 RK0
7139 06:52:04.787753 [ModeRegInit_LP4] CH1 RK1
7140 06:52:04.788317 match AC timing 4
7141 06:52:04.794009 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7142 06:52:04.797395 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7143 06:52:04.800482 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7144 06:52:04.807701 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7145 06:52:04.810395 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7146 06:52:04.810986 [MiockJmeterHQA]
7147 06:52:04.811362
7148 06:52:04.814190 [DramcMiockJmeter] u1RxGatingPI = 0
7149 06:52:04.817239 0 : 4254, 4029
7150 06:52:04.817735 4 : 4363, 4137
7151 06:52:04.820953 8 : 4257, 4029
7152 06:52:04.821434 12 : 4252, 4027
7153 06:52:04.821937 16 : 4253, 4027
7154 06:52:04.824058 20 : 4252, 4027
7155 06:52:04.824532 24 : 4255, 4029
7156 06:52:04.826971 28 : 4253, 4027
7157 06:52:04.827557 32 : 4253, 4027
7158 06:52:04.830304 36 : 4368, 4142
7159 06:52:04.830779 40 : 4253, 4027
7160 06:52:04.833683 44 : 4253, 4026
7161 06:52:04.834313 48 : 4252, 4027
7162 06:52:04.834701 52 : 4363, 4137
7163 06:52:04.837146 56 : 4253, 4026
7164 06:52:04.837622 60 : 4360, 4138
7165 06:52:04.840287 64 : 4250, 4027
7166 06:52:04.840792 68 : 4250, 4027
7167 06:52:04.844485 72 : 4250, 4026
7168 06:52:04.845221 76 : 4250, 4026
7169 06:52:04.847308 80 : 4360, 4138
7170 06:52:04.847783 84 : 4250, 4026
7171 06:52:04.848158 88 : 4361, 4137
7172 06:52:04.849819 92 : 4250, 4026
7173 06:52:04.850427 96 : 4250, 4026
7174 06:52:04.853420 100 : 4250, 3169
7175 06:52:04.854125 104 : 4250, 0
7176 06:52:04.856599 108 : 4360, 0
7177 06:52:04.857108 112 : 4250, 0
7178 06:52:04.857491 116 : 4255, 0
7179 06:52:04.859946 120 : 4250, 0
7180 06:52:04.860424 124 : 4250, 0
7181 06:52:04.863324 128 : 4363, 0
7182 06:52:04.863910 132 : 4250, 0
7183 06:52:04.864296 136 : 4250, 0
7184 06:52:04.866449 140 : 4361, 0
7185 06:52:04.866927 144 : 4360, 0
7186 06:52:04.870146 148 : 4361, 0
7187 06:52:04.870622 152 : 4250, 0
7188 06:52:04.871002 156 : 4361, 0
7189 06:52:04.874408 160 : 4250, 0
7190 06:52:04.874991 164 : 4250, 0
7191 06:52:04.875373 168 : 4250, 0
7192 06:52:04.876415 172 : 4250, 0
7193 06:52:04.876948 176 : 4250, 0
7194 06:52:04.879474 180 : 4361, 0
7195 06:52:04.879950 184 : 4360, 0
7196 06:52:04.880331 188 : 4248, 0
7197 06:52:04.883951 192 : 4250, 0
7198 06:52:04.884605 196 : 4360, 0
7199 06:52:04.886423 200 : 4361, 0
7200 06:52:04.887008 204 : 4250, 0
7201 06:52:04.887532 208 : 4250, 0
7202 06:52:04.889753 212 : 4250, 0
7203 06:52:04.890226 216 : 4250, 0
7204 06:52:04.892881 220 : 4250, 39
7205 06:52:04.893356 224 : 4361, 3734
7206 06:52:04.895927 228 : 4250, 4027
7207 06:52:04.896334 232 : 4250, 4027
7208 06:52:04.896689 236 : 4253, 4026
7209 06:52:04.899216 240 : 4250, 4026
7210 06:52:04.899686 244 : 4250, 4027
7211 06:52:04.903117 248 : 4250, 4027
7212 06:52:04.903592 252 : 4250, 4027
7213 06:52:04.906210 256 : 4250, 4026
7214 06:52:04.906782 260 : 4250, 4027
7215 06:52:04.909513 264 : 4360, 4138
7216 06:52:04.909985 268 : 4360, 4138
7217 06:52:04.913044 272 : 4248, 4025
7218 06:52:04.913726 276 : 4361, 4137
7219 06:52:04.917296 280 : 4360, 4138
7220 06:52:04.917767 284 : 4250, 4026
7221 06:52:04.919457 288 : 4250, 4027
7222 06:52:04.919932 292 : 4250, 4026
7223 06:52:04.920310 296 : 4250, 4027
7224 06:52:04.922656 300 : 4250, 4026
7225 06:52:04.923127 304 : 4250, 4026
7226 06:52:04.925958 308 : 4250, 4026
7227 06:52:04.926588 312 : 4250, 4027
7228 06:52:04.929322 316 : 4360, 4138
7229 06:52:04.929892 320 : 4361, 4137
7230 06:52:04.932354 324 : 4250, 4026
7231 06:52:04.933044 328 : 4361, 4137
7232 06:52:04.936818 332 : 4360, 4137
7233 06:52:04.937450 336 : 4250, 3940
7234 06:52:04.939117 340 : 4250, 1932
7235 06:52:04.939683
7236 06:52:04.940196 MIOCK jitter meter ch=0
7237 06:52:04.940747
7238 06:52:04.942519 1T = (340-104) = 236 dly cells
7239 06:52:04.949031 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7240 06:52:04.949554 ==
7241 06:52:04.952453 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 06:52:04.955766 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7243 06:52:04.956323 ==
7244 06:52:04.962315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7245 06:52:04.965378 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7246 06:52:04.972106 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7247 06:52:04.975728 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7248 06:52:04.985045 [CA 0] Center 42 (12~73) winsize 62
7249 06:52:04.988411 [CA 1] Center 42 (12~73) winsize 62
7250 06:52:04.991467 [CA 2] Center 39 (9~69) winsize 61
7251 06:52:04.996183 [CA 3] Center 38 (9~68) winsize 60
7252 06:52:04.998587 [CA 4] Center 37 (7~67) winsize 61
7253 06:52:05.001928 [CA 5] Center 36 (6~66) winsize 61
7254 06:52:05.002396
7255 06:52:05.004820 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7256 06:52:05.005288
7257 06:52:05.008189 [CATrainingPosCal] consider 1 rank data
7258 06:52:05.012269 u2DelayCellTimex100 = 275/100 ps
7259 06:52:05.014770 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7260 06:52:05.021556 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7261 06:52:05.025284 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7262 06:52:05.028286 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7263 06:52:05.031480 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7264 06:52:05.035399 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7265 06:52:05.035867
7266 06:52:05.038379 CA PerBit enable=1, Macro0, CA PI delay=36
7267 06:52:05.038934
7268 06:52:05.041483 [CBTSetCACLKResult] CA Dly = 36
7269 06:52:05.045545 CS Dly: 10 (0~41)
7270 06:52:05.047708 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7271 06:52:05.051937 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7272 06:52:05.052500 ==
7273 06:52:05.054805 Dram Type= 6, Freq= 0, CH_0, rank 1
7274 06:52:05.058210 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7275 06:52:05.060965 ==
7276 06:52:05.064856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7277 06:52:05.067933 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7278 06:52:05.074332 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7279 06:52:05.080966 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7280 06:52:05.087488 [CA 0] Center 42 (12~73) winsize 62
7281 06:52:05.091194 [CA 1] Center 42 (12~73) winsize 62
7282 06:52:05.094423 [CA 2] Center 38 (9~68) winsize 60
7283 06:52:05.097501 [CA 3] Center 37 (8~67) winsize 60
7284 06:52:05.101011 [CA 4] Center 36 (6~66) winsize 61
7285 06:52:05.104436 [CA 5] Center 36 (6~66) winsize 61
7286 06:52:05.105048
7287 06:52:05.107869 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7288 06:52:05.108404
7289 06:52:05.111231 [CATrainingPosCal] consider 2 rank data
7290 06:52:05.114283 u2DelayCellTimex100 = 275/100 ps
7291 06:52:05.117923 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7292 06:52:05.124514 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7293 06:52:05.128153 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7294 06:52:05.131264 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7295 06:52:05.134087 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7296 06:52:05.137409 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7297 06:52:05.137870
7298 06:52:05.141017 CA PerBit enable=1, Macro0, CA PI delay=36
7299 06:52:05.141481
7300 06:52:05.144106 [CBTSetCACLKResult] CA Dly = 36
7301 06:52:05.146919 CS Dly: 10 (0~42)
7302 06:52:05.151272 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7303 06:52:05.153766 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7304 06:52:05.154092
7305 06:52:05.156823 ----->DramcWriteLeveling(PI) begin...
7306 06:52:05.157155 ==
7307 06:52:05.160596 Dram Type= 6, Freq= 0, CH_0, rank 0
7308 06:52:05.166796 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7309 06:52:05.167202 ==
7310 06:52:05.171310 Write leveling (Byte 0): 30 => 30
7311 06:52:05.171790 Write leveling (Byte 1): 26 => 26
7312 06:52:05.173650 DramcWriteLeveling(PI) end<-----
7313 06:52:05.173977
7314 06:52:05.176851 ==
7315 06:52:05.177176 Dram Type= 6, Freq= 0, CH_0, rank 0
7316 06:52:05.183378 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7317 06:52:05.183764 ==
7318 06:52:05.186751 [Gating] SW mode calibration
7319 06:52:05.193637 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7320 06:52:05.196755 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7321 06:52:05.204027 0 12 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7322 06:52:05.206962 0 12 4 | B1->B0 | 2a29 3434 | 1 1 | (0 0) (1 1)
7323 06:52:05.209670 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7324 06:52:05.216787 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7325 06:52:05.220571 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7326 06:52:05.223358 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7327 06:52:05.230241 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7328 06:52:05.233343 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7329 06:52:05.236766 0 13 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7330 06:52:05.243536 0 13 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7331 06:52:05.246917 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7332 06:52:05.249367 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7333 06:52:05.256128 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7334 06:52:05.259961 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7335 06:52:05.263005 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7336 06:52:05.269693 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7337 06:52:05.273449 0 14 0 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7338 06:52:05.276837 0 14 4 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
7339 06:52:05.282734 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7340 06:52:05.286315 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7341 06:52:05.289152 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7342 06:52:05.296607 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7343 06:52:05.299914 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7344 06:52:05.302794 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7345 06:52:05.308917 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7346 06:52:05.312512 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7347 06:52:05.315717 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7348 06:52:05.322697 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 06:52:05.325621 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 06:52:05.328813 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 06:52:05.335319 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 06:52:05.339530 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 06:52:05.342150 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 06:52:05.348859 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 06:52:05.351969 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 06:52:05.355147 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 06:52:05.362123 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 06:52:05.365510 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 06:52:05.369643 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 06:52:05.375486 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7361 06:52:05.379035 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7362 06:52:05.381743 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7363 06:52:05.388577 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7364 06:52:05.389165 Total UI for P1: 0, mck2ui 16
7365 06:52:05.394802 best dqsien dly found for B0: ( 1, 1, 0)
7366 06:52:05.395393 Total UI for P1: 0, mck2ui 16
7367 06:52:05.397914 best dqsien dly found for B1: ( 1, 1, 4)
7368 06:52:05.405238 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7369 06:52:05.408235 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7370 06:52:05.408702
7371 06:52:05.411578 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7372 06:52:05.415215 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7373 06:52:05.417908 [Gating] SW calibration Done
7374 06:52:05.418376 ==
7375 06:52:05.421412 Dram Type= 6, Freq= 0, CH_0, rank 0
7376 06:52:05.424577 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7377 06:52:05.425180 ==
7378 06:52:05.428218 RX Vref Scan: 0
7379 06:52:05.428842
7380 06:52:05.429364 RX Vref 0 -> 0, step: 1
7381 06:52:05.429724
7382 06:52:05.431576 RX Delay 0 -> 252, step: 8
7383 06:52:05.434150 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
7384 06:52:05.437413 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7385 06:52:05.444964 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7386 06:52:05.447813 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7387 06:52:05.450952 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7388 06:52:05.454092 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7389 06:52:05.457670 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7390 06:52:05.464426 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
7391 06:52:05.467854 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7392 06:52:05.470677 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7393 06:52:05.473954 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7394 06:52:05.481598 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7395 06:52:05.484147 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7396 06:52:05.487276 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7397 06:52:05.490833 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7398 06:52:05.494381 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7399 06:52:05.497251 ==
7400 06:52:05.497718 Dram Type= 6, Freq= 0, CH_0, rank 0
7401 06:52:05.503848 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7402 06:52:05.504321 ==
7403 06:52:05.504693 DQS Delay:
7404 06:52:05.506894 DQS0 = 0, DQS1 = 0
7405 06:52:05.507361 DQM Delay:
7406 06:52:05.511388 DQM0 = 129, DQM1 = 123
7407 06:52:05.511955 DQ Delay:
7408 06:52:05.514003 DQ0 =123, DQ1 =131, DQ2 =127, DQ3 =127
7409 06:52:05.516840 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =135
7410 06:52:05.520539 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
7411 06:52:05.523785 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7412 06:52:05.524301
7413 06:52:05.524667
7414 06:52:05.525051 ==
7415 06:52:05.526887 Dram Type= 6, Freq= 0, CH_0, rank 0
7416 06:52:05.534416 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7417 06:52:05.534885 ==
7418 06:52:05.535259
7419 06:52:05.535601
7420 06:52:05.535934 TX Vref Scan disable
7421 06:52:05.537586 == TX Byte 0 ==
7422 06:52:05.540696 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7423 06:52:05.549254 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7424 06:52:05.549810 == TX Byte 1 ==
7425 06:52:05.550850 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7426 06:52:05.557348 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7427 06:52:05.557818 ==
7428 06:52:05.560399 Dram Type= 6, Freq= 0, CH_0, rank 0
7429 06:52:05.563751 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7430 06:52:05.564287 ==
7431 06:52:05.577256
7432 06:52:05.581223 TX Vref early break, caculate TX vref
7433 06:52:05.584893 TX Vref=16, minBit 8, minWin=22, winSum=374
7434 06:52:05.588005 TX Vref=18, minBit 7, minWin=23, winSum=381
7435 06:52:05.590613 TX Vref=20, minBit 11, minWin=22, winSum=385
7436 06:52:05.594171 TX Vref=22, minBit 8, minWin=23, winSum=392
7437 06:52:05.598591 TX Vref=24, minBit 9, minWin=24, winSum=404
7438 06:52:05.603674 TX Vref=26, minBit 8, minWin=25, winSum=413
7439 06:52:05.607531 TX Vref=28, minBit 2, minWin=25, winSum=413
7440 06:52:05.611313 TX Vref=30, minBit 7, minWin=24, winSum=403
7441 06:52:05.613841 TX Vref=32, minBit 8, minWin=23, winSum=398
7442 06:52:05.617566 TX Vref=34, minBit 3, minWin=23, winSum=393
7443 06:52:05.620127 TX Vref=36, minBit 3, minWin=23, winSum=384
7444 06:52:05.626769 [TxChooseVref] Worse bit 8, Min win 25, Win sum 413, Final Vref 26
7445 06:52:05.627238
7446 06:52:05.630508 Final TX Range 0 Vref 26
7447 06:52:05.631074
7448 06:52:05.631448 ==
7449 06:52:05.633466 Dram Type= 6, Freq= 0, CH_0, rank 0
7450 06:52:05.637404 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7451 06:52:05.637873 ==
7452 06:52:05.638245
7453 06:52:05.640592
7454 06:52:05.641208 TX Vref Scan disable
7455 06:52:05.647011 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7456 06:52:05.647475 == TX Byte 0 ==
7457 06:52:05.650126 u2DelayCellOfst[0]=10 cells (3 PI)
7458 06:52:05.653432 u2DelayCellOfst[1]=17 cells (5 PI)
7459 06:52:05.657379 u2DelayCellOfst[2]=10 cells (3 PI)
7460 06:52:05.660138 u2DelayCellOfst[3]=10 cells (3 PI)
7461 06:52:05.663553 u2DelayCellOfst[4]=7 cells (2 PI)
7462 06:52:05.666989 u2DelayCellOfst[5]=0 cells (0 PI)
7463 06:52:05.670404 u2DelayCellOfst[6]=17 cells (5 PI)
7464 06:52:05.673159 u2DelayCellOfst[7]=17 cells (5 PI)
7465 06:52:05.676703 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7466 06:52:05.680003 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7467 06:52:05.683308 == TX Byte 1 ==
7468 06:52:05.686710 u2DelayCellOfst[8]=3 cells (1 PI)
7469 06:52:05.689907 u2DelayCellOfst[9]=0 cells (0 PI)
7470 06:52:05.693854 u2DelayCellOfst[10]=10 cells (3 PI)
7471 06:52:05.696840 u2DelayCellOfst[11]=7 cells (2 PI)
7472 06:52:05.697310 u2DelayCellOfst[12]=17 cells (5 PI)
7473 06:52:05.700351 u2DelayCellOfst[13]=14 cells (4 PI)
7474 06:52:05.703842 u2DelayCellOfst[14]=17 cells (5 PI)
7475 06:52:05.707099 u2DelayCellOfst[15]=14 cells (4 PI)
7476 06:52:05.714053 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7477 06:52:05.717129 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7478 06:52:05.717600 DramC Write-DBI on
7479 06:52:05.719767 ==
7480 06:52:05.723054 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 06:52:05.726668 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7482 06:52:05.727354 ==
7483 06:52:05.727785
7484 06:52:05.728134
7485 06:52:05.730332 TX Vref Scan disable
7486 06:52:05.731123 == TX Byte 0 ==
7487 06:52:05.736409 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7488 06:52:05.737095 == TX Byte 1 ==
7489 06:52:05.739943 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7490 06:52:05.743345 DramC Write-DBI off
7491 06:52:05.744121
7492 06:52:05.744519 [DATLAT]
7493 06:52:05.746440 Freq=1600, CH0 RK0
7494 06:52:05.747150
7495 06:52:05.747691 DATLAT Default: 0xf
7496 06:52:05.750033 0, 0xFFFF, sum = 0
7497 06:52:05.750705 1, 0xFFFF, sum = 0
7498 06:52:05.753514 2, 0xFFFF, sum = 0
7499 06:52:05.754103 3, 0xFFFF, sum = 0
7500 06:52:05.756805 4, 0xFFFF, sum = 0
7501 06:52:05.757280 5, 0xFFFF, sum = 0
7502 06:52:05.759652 6, 0xFFFF, sum = 0
7503 06:52:05.760276 7, 0xFFFF, sum = 0
7504 06:52:05.764159 8, 0xFFFF, sum = 0
7505 06:52:05.765989 9, 0xFFFF, sum = 0
7506 06:52:05.766464 10, 0xFFFF, sum = 0
7507 06:52:05.769949 11, 0xFFFF, sum = 0
7508 06:52:05.770421 12, 0x8FFF, sum = 0
7509 06:52:05.773281 13, 0x0, sum = 1
7510 06:52:05.773845 14, 0x0, sum = 2
7511 06:52:05.776010 15, 0x0, sum = 3
7512 06:52:05.776481 16, 0x0, sum = 4
7513 06:52:05.776934 best_step = 14
7514 06:52:05.779778
7515 06:52:05.780346 ==
7516 06:52:05.783568 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 06:52:05.786049 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7518 06:52:05.786609 ==
7519 06:52:05.786984 RX Vref Scan: 1
7520 06:52:05.787332
7521 06:52:05.789119 Set Vref Range= 24 -> 127
7522 06:52:05.789717
7523 06:52:05.792756 RX Vref 24 -> 127, step: 1
7524 06:52:05.793226
7525 06:52:05.796770 RX Delay 11 -> 252, step: 4
7526 06:52:05.797246
7527 06:52:05.800040 Set Vref, RX VrefLevel [Byte0]: 24
7528 06:52:05.803295 [Byte1]: 24
7529 06:52:05.803923
7530 06:52:05.805980 Set Vref, RX VrefLevel [Byte0]: 25
7531 06:52:05.808852 [Byte1]: 25
7532 06:52:05.809318
7533 06:52:05.812350 Set Vref, RX VrefLevel [Byte0]: 26
7534 06:52:05.815945 [Byte1]: 26
7535 06:52:05.819692
7536 06:52:05.820361 Set Vref, RX VrefLevel [Byte0]: 27
7537 06:52:05.822652 [Byte1]: 27
7538 06:52:05.827528
7539 06:52:05.828061 Set Vref, RX VrefLevel [Byte0]: 28
7540 06:52:05.830513 [Byte1]: 28
7541 06:52:05.834877
7542 06:52:05.835341 Set Vref, RX VrefLevel [Byte0]: 29
7543 06:52:05.838081 [Byte1]: 29
7544 06:52:05.842453
7545 06:52:05.843019 Set Vref, RX VrefLevel [Byte0]: 30
7546 06:52:05.845669 [Byte1]: 30
7547 06:52:05.850285
7548 06:52:05.850825 Set Vref, RX VrefLevel [Byte0]: 31
7549 06:52:05.853874 [Byte1]: 31
7550 06:52:05.858149
7551 06:52:05.858681 Set Vref, RX VrefLevel [Byte0]: 32
7552 06:52:05.860666 [Byte1]: 32
7553 06:52:05.865265
7554 06:52:05.865731 Set Vref, RX VrefLevel [Byte0]: 33
7555 06:52:05.869011 [Byte1]: 33
7556 06:52:05.872874
7557 06:52:05.873397 Set Vref, RX VrefLevel [Byte0]: 34
7558 06:52:05.876101 [Byte1]: 34
7559 06:52:05.880351
7560 06:52:05.880874 Set Vref, RX VrefLevel [Byte0]: 35
7561 06:52:05.883820 [Byte1]: 35
7562 06:52:05.888230
7563 06:52:05.888831 Set Vref, RX VrefLevel [Byte0]: 36
7564 06:52:05.891355 [Byte1]: 36
7565 06:52:05.895670
7566 06:52:05.896134 Set Vref, RX VrefLevel [Byte0]: 37
7567 06:52:05.899017 [Byte1]: 37
7568 06:52:05.903429
7569 06:52:05.904000 Set Vref, RX VrefLevel [Byte0]: 38
7570 06:52:05.906309 [Byte1]: 38
7571 06:52:05.910950
7572 06:52:05.911486 Set Vref, RX VrefLevel [Byte0]: 39
7573 06:52:05.914141 [Byte1]: 39
7574 06:52:05.918565
7575 06:52:05.919125 Set Vref, RX VrefLevel [Byte0]: 40
7576 06:52:05.921386 [Byte1]: 40
7577 06:52:05.926244
7578 06:52:05.926815 Set Vref, RX VrefLevel [Byte0]: 41
7579 06:52:05.929375 [Byte1]: 41
7580 06:52:05.934380
7581 06:52:05.934913 Set Vref, RX VrefLevel [Byte0]: 42
7582 06:52:05.936950 [Byte1]: 42
7583 06:52:05.941411
7584 06:52:05.942175 Set Vref, RX VrefLevel [Byte0]: 43
7585 06:52:05.944641 [Byte1]: 43
7586 06:52:05.948644
7587 06:52:05.949155 Set Vref, RX VrefLevel [Byte0]: 44
7588 06:52:05.952280 [Byte1]: 44
7589 06:52:05.956452
7590 06:52:05.957081 Set Vref, RX VrefLevel [Byte0]: 45
7591 06:52:05.959751 [Byte1]: 45
7592 06:52:05.963804
7593 06:52:05.964271 Set Vref, RX VrefLevel [Byte0]: 46
7594 06:52:05.967261 [Byte1]: 46
7595 06:52:05.971954
7596 06:52:05.972506 Set Vref, RX VrefLevel [Byte0]: 47
7597 06:52:05.975032 [Byte1]: 47
7598 06:52:05.979334
7599 06:52:05.979804 Set Vref, RX VrefLevel [Byte0]: 48
7600 06:52:05.982474 [Byte1]: 48
7601 06:52:05.986847
7602 06:52:05.987470 Set Vref, RX VrefLevel [Byte0]: 49
7603 06:52:05.990161 [Byte1]: 49
7604 06:52:05.994573
7605 06:52:05.995038 Set Vref, RX VrefLevel [Byte0]: 50
7606 06:52:05.998450 [Byte1]: 50
7607 06:52:06.003117
7608 06:52:06.003583 Set Vref, RX VrefLevel [Byte0]: 51
7609 06:52:06.005334 [Byte1]: 51
7610 06:52:06.009947
7611 06:52:06.010411 Set Vref, RX VrefLevel [Byte0]: 52
7612 06:52:06.012956 [Byte1]: 52
7613 06:52:06.017349
7614 06:52:06.017812 Set Vref, RX VrefLevel [Byte0]: 53
7615 06:52:06.020819 [Byte1]: 53
7616 06:52:06.025571
7617 06:52:06.026036 Set Vref, RX VrefLevel [Byte0]: 54
7618 06:52:06.028375 [Byte1]: 54
7619 06:52:06.032751
7620 06:52:06.033331 Set Vref, RX VrefLevel [Byte0]: 55
7621 06:52:06.035727 [Byte1]: 55
7622 06:52:06.040806
7623 06:52:06.041338 Set Vref, RX VrefLevel [Byte0]: 56
7624 06:52:06.043760 [Byte1]: 56
7625 06:52:06.048329
7626 06:52:06.049079 Set Vref, RX VrefLevel [Byte0]: 57
7627 06:52:06.050961 [Byte1]: 57
7628 06:52:06.055472
7629 06:52:06.056082 Set Vref, RX VrefLevel [Byte0]: 58
7630 06:52:06.058508 [Byte1]: 58
7631 06:52:06.063251
7632 06:52:06.063834 Set Vref, RX VrefLevel [Byte0]: 59
7633 06:52:06.066206 [Byte1]: 59
7634 06:52:06.070809
7635 06:52:06.071316 Set Vref, RX VrefLevel [Byte0]: 60
7636 06:52:06.075094 [Byte1]: 60
7637 06:52:06.078644
7638 06:52:06.079226 Set Vref, RX VrefLevel [Byte0]: 61
7639 06:52:06.081551 [Byte1]: 61
7640 06:52:06.085880
7641 06:52:06.086345 Set Vref, RX VrefLevel [Byte0]: 62
7642 06:52:06.089591 [Byte1]: 62
7643 06:52:06.094277
7644 06:52:06.094743 Set Vref, RX VrefLevel [Byte0]: 63
7645 06:52:06.097257 [Byte1]: 63
7646 06:52:06.101292
7647 06:52:06.101755 Set Vref, RX VrefLevel [Byte0]: 64
7648 06:52:06.104772 [Byte1]: 64
7649 06:52:06.108700
7650 06:52:06.109214 Set Vref, RX VrefLevel [Byte0]: 65
7651 06:52:06.111928 [Byte1]: 65
7652 06:52:06.116195
7653 06:52:06.116662 Set Vref, RX VrefLevel [Byte0]: 66
7654 06:52:06.119746 [Byte1]: 66
7655 06:52:06.124028
7656 06:52:06.124445 Set Vref, RX VrefLevel [Byte0]: 67
7657 06:52:06.127014 [Byte1]: 67
7658 06:52:06.131576
7659 06:52:06.131994 Set Vref, RX VrefLevel [Byte0]: 68
7660 06:52:06.134540 [Byte1]: 68
7661 06:52:06.139586
7662 06:52:06.140108 Set Vref, RX VrefLevel [Byte0]: 69
7663 06:52:06.143287 [Byte1]: 69
7664 06:52:06.146464
7665 06:52:06.146890 Set Vref, RX VrefLevel [Byte0]: 70
7666 06:52:06.150130 [Byte1]: 70
7667 06:52:06.155201
7668 06:52:06.157943 Final RX Vref Byte 0 = 54 to rank0
7669 06:52:06.158441 Final RX Vref Byte 1 = 53 to rank0
7670 06:52:06.161030 Final RX Vref Byte 0 = 54 to rank1
7671 06:52:06.164846 Final RX Vref Byte 1 = 53 to rank1==
7672 06:52:06.167705 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 06:52:06.174325 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7674 06:52:06.174815 ==
7675 06:52:06.175151 DQS Delay:
7676 06:52:06.177263 DQS0 = 0, DQS1 = 0
7677 06:52:06.177682 DQM Delay:
7678 06:52:06.178017 DQM0 = 126, DQM1 = 120
7679 06:52:06.181079 DQ Delay:
7680 06:52:06.184161 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7681 06:52:06.187242 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7682 06:52:06.190445 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7683 06:52:06.193994 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7684 06:52:06.194418
7685 06:52:06.194755
7686 06:52:06.195065
7687 06:52:06.197174 [DramC_TX_OE_Calibration] TA2
7688 06:52:06.200779 Original DQ_B0 (3 6) =30, OEN = 27
7689 06:52:06.203569 Original DQ_B1 (3 6) =30, OEN = 27
7690 06:52:06.207265 24, 0x0, End_B0=24 End_B1=24
7691 06:52:06.207762 25, 0x0, End_B0=25 End_B1=25
7692 06:52:06.210728 26, 0x0, End_B0=26 End_B1=26
7693 06:52:06.213541 27, 0x0, End_B0=27 End_B1=27
7694 06:52:06.217419 28, 0x0, End_B0=28 End_B1=28
7695 06:52:06.220745 29, 0x0, End_B0=29 End_B1=29
7696 06:52:06.221247 30, 0x0, End_B0=30 End_B1=30
7697 06:52:06.224978 31, 0x4545, End_B0=30 End_B1=30
7698 06:52:06.226908 Byte0 end_step=30 best_step=27
7699 06:52:06.231360 Byte1 end_step=30 best_step=27
7700 06:52:06.234146 Byte0 TX OE(2T, 0.5T) = (3, 3)
7701 06:52:06.236813 Byte1 TX OE(2T, 0.5T) = (3, 3)
7702 06:52:06.237277
7703 06:52:06.237613
7704 06:52:06.243686 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7705 06:52:06.246433 CH0 RK0: MR19=303, MR18=1C1C
7706 06:52:06.253333 CH0_RK0: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
7707 06:52:06.253827
7708 06:52:06.256900 ----->DramcWriteLeveling(PI) begin...
7709 06:52:06.257328 ==
7710 06:52:06.261018 Dram Type= 6, Freq= 0, CH_0, rank 1
7711 06:52:06.263491 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7712 06:52:06.263914 ==
7713 06:52:06.266937 Write leveling (Byte 0): 29 => 29
7714 06:52:06.270005 Write leveling (Byte 1): 26 => 26
7715 06:52:06.273466 DramcWriteLeveling(PI) end<-----
7716 06:52:06.273886
7717 06:52:06.274216 ==
7718 06:52:06.276676 Dram Type= 6, Freq= 0, CH_0, rank 1
7719 06:52:06.279894 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7720 06:52:06.280319 ==
7721 06:52:06.283616 [Gating] SW mode calibration
7722 06:52:06.290830 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7723 06:52:06.296548 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7724 06:52:06.299882 0 12 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7725 06:52:06.308614 0 12 4 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
7726 06:52:06.309844 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7727 06:52:06.313345 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7728 06:52:06.319841 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7729 06:52:06.323189 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7730 06:52:06.326401 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7731 06:52:06.333324 0 12 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7732 06:52:06.336948 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
7733 06:52:06.340522 0 13 4 | B1->B0 | 3131 2323 | 1 0 | (0 1) (0 0)
7734 06:52:06.346104 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7735 06:52:06.349438 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7736 06:52:06.353451 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7737 06:52:06.359856 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7738 06:52:06.363185 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7739 06:52:06.366298 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7740 06:52:06.372777 0 14 0 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7741 06:52:06.376687 0 14 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7742 06:52:06.379258 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7743 06:52:06.386081 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7744 06:52:06.390337 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7745 06:52:06.392776 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7746 06:52:06.396266 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7747 06:52:06.402790 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7748 06:52:06.406036 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7749 06:52:06.409140 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7750 06:52:06.415703 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 06:52:06.418976 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 06:52:06.422892 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 06:52:06.429150 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 06:52:06.432828 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 06:52:06.435906 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 06:52:06.442848 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 06:52:06.446131 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 06:52:06.449383 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 06:52:06.455895 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 06:52:06.458568 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 06:52:06.462608 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 06:52:06.468839 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 06:52:06.473127 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7764 06:52:06.475723 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7765 06:52:06.482302 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7766 06:52:06.482833 Total UI for P1: 0, mck2ui 16
7767 06:52:06.489114 best dqsien dly found for B0: ( 1, 0, 30)
7768 06:52:06.492375 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7769 06:52:06.496213 Total UI for P1: 0, mck2ui 16
7770 06:52:06.498789 best dqsien dly found for B1: ( 1, 1, 2)
7771 06:52:06.501980 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7772 06:52:06.505536 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7773 06:52:06.506007
7774 06:52:06.508583 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7775 06:52:06.512300 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7776 06:52:06.514853 [Gating] SW calibration Done
7777 06:52:06.515321 ==
7778 06:52:06.519125 Dram Type= 6, Freq= 0, CH_0, rank 1
7779 06:52:06.521695 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7780 06:52:06.525614 ==
7781 06:52:06.526170 RX Vref Scan: 0
7782 06:52:06.526539
7783 06:52:06.529043 RX Vref 0 -> 0, step: 1
7784 06:52:06.529507
7785 06:52:06.529878 RX Delay 0 -> 252, step: 8
7786 06:52:06.535822 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7787 06:52:06.538824 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7788 06:52:06.542027 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7789 06:52:06.545795 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7790 06:52:06.548324 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7791 06:52:06.555789 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7792 06:52:06.558208 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7793 06:52:06.561655 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7794 06:52:06.565178 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7795 06:52:06.568664 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7796 06:52:06.575377 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7797 06:52:06.578190 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7798 06:52:06.582066 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7799 06:52:06.585221 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7800 06:52:06.591304 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7801 06:52:06.594622 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7802 06:52:06.595219 ==
7803 06:52:06.598058 Dram Type= 6, Freq= 0, CH_0, rank 1
7804 06:52:06.601468 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7805 06:52:06.601950 ==
7806 06:52:06.604872 DQS Delay:
7807 06:52:06.605341 DQS0 = 0, DQS1 = 0
7808 06:52:06.605713 DQM Delay:
7809 06:52:06.607963 DQM0 = 130, DQM1 = 124
7810 06:52:06.608430 DQ Delay:
7811 06:52:06.610878 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7812 06:52:06.614586 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7813 06:52:06.618033 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7814 06:52:06.624572 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7815 06:52:06.625188
7816 06:52:06.625563
7817 06:52:06.625908 ==
7818 06:52:06.628160 Dram Type= 6, Freq= 0, CH_0, rank 1
7819 06:52:06.631579 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7820 06:52:06.632140 ==
7821 06:52:06.632519
7822 06:52:06.632961
7823 06:52:06.634273 TX Vref Scan disable
7824 06:52:06.634740 == TX Byte 0 ==
7825 06:52:06.641699 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7826 06:52:06.644454 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7827 06:52:06.645076 == TX Byte 1 ==
7828 06:52:06.651925 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7829 06:52:06.654158 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7830 06:52:06.654731 ==
7831 06:52:06.657810 Dram Type= 6, Freq= 0, CH_0, rank 1
7832 06:52:06.660628 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7833 06:52:06.661143 ==
7834 06:52:06.676084
7835 06:52:06.679590 TX Vref early break, caculate TX vref
7836 06:52:06.682989 TX Vref=16, minBit 8, minWin=22, winSum=371
7837 06:52:06.686001 TX Vref=18, minBit 9, minWin=23, winSum=383
7838 06:52:06.689124 TX Vref=20, minBit 9, minWin=23, winSum=394
7839 06:52:06.692360 TX Vref=22, minBit 11, minWin=23, winSum=402
7840 06:52:06.697208 TX Vref=24, minBit 1, minWin=24, winSum=405
7841 06:52:06.702657 TX Vref=26, minBit 8, minWin=24, winSum=407
7842 06:52:06.706080 TX Vref=28, minBit 1, minWin=24, winSum=413
7843 06:52:06.708928 TX Vref=30, minBit 3, minWin=24, winSum=407
7844 06:52:06.712425 TX Vref=32, minBit 8, minWin=24, winSum=402
7845 06:52:06.715608 TX Vref=34, minBit 8, minWin=23, winSum=395
7846 06:52:06.718966 TX Vref=36, minBit 8, minWin=23, winSum=387
7847 06:52:06.725440 [TxChooseVref] Worse bit 1, Min win 24, Win sum 413, Final Vref 28
7848 06:52:06.725913
7849 06:52:06.729529 Final TX Range 0 Vref 28
7850 06:52:06.729995
7851 06:52:06.730365 ==
7852 06:52:06.732131 Dram Type= 6, Freq= 0, CH_0, rank 1
7853 06:52:06.735738 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7854 06:52:06.736287 ==
7855 06:52:06.736756
7856 06:52:06.737141
7857 06:52:06.738843 TX Vref Scan disable
7858 06:52:06.745978 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7859 06:52:06.746513 == TX Byte 0 ==
7860 06:52:06.749264 u2DelayCellOfst[0]=14 cells (4 PI)
7861 06:52:06.751947 u2DelayCellOfst[1]=17 cells (5 PI)
7862 06:52:06.755831 u2DelayCellOfst[2]=14 cells (4 PI)
7863 06:52:06.758624 u2DelayCellOfst[3]=14 cells (4 PI)
7864 06:52:06.762540 u2DelayCellOfst[4]=10 cells (3 PI)
7865 06:52:06.765657 u2DelayCellOfst[5]=0 cells (0 PI)
7866 06:52:06.769081 u2DelayCellOfst[6]=17 cells (5 PI)
7867 06:52:06.772598 u2DelayCellOfst[7]=17 cells (5 PI)
7868 06:52:06.775576 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7869 06:52:06.779132 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7870 06:52:06.782891 == TX Byte 1 ==
7871 06:52:06.785267 u2DelayCellOfst[8]=0 cells (0 PI)
7872 06:52:06.788658 u2DelayCellOfst[9]=0 cells (0 PI)
7873 06:52:06.792030 u2DelayCellOfst[10]=10 cells (3 PI)
7874 06:52:06.795851 u2DelayCellOfst[11]=3 cells (1 PI)
7875 06:52:06.798560 u2DelayCellOfst[12]=14 cells (4 PI)
7876 06:52:06.801690 u2DelayCellOfst[13]=14 cells (4 PI)
7877 06:52:06.802154 u2DelayCellOfst[14]=17 cells (5 PI)
7878 06:52:06.804844 u2DelayCellOfst[15]=14 cells (4 PI)
7879 06:52:06.811476 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7880 06:52:06.814973 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7881 06:52:06.818783 DramC Write-DBI on
7882 06:52:06.819245 ==
7883 06:52:06.821741 Dram Type= 6, Freq= 0, CH_0, rank 1
7884 06:52:06.825071 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7885 06:52:06.825537 ==
7886 06:52:06.825905
7887 06:52:06.826246
7888 06:52:06.828198 TX Vref Scan disable
7889 06:52:06.828673 == TX Byte 0 ==
7890 06:52:06.834902 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7891 06:52:06.835462 == TX Byte 1 ==
7892 06:52:06.837720 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7893 06:52:06.841270 DramC Write-DBI off
7894 06:52:06.841733
7895 06:52:06.842147 [DATLAT]
7896 06:52:06.844660 Freq=1600, CH0 RK1
7897 06:52:06.845175
7898 06:52:06.845550 DATLAT Default: 0xe
7899 06:52:06.848026 0, 0xFFFF, sum = 0
7900 06:52:06.848532 1, 0xFFFF, sum = 0
7901 06:52:06.851529 2, 0xFFFF, sum = 0
7902 06:52:06.852003 3, 0xFFFF, sum = 0
7903 06:52:06.855601 4, 0xFFFF, sum = 0
7904 06:52:06.857794 5, 0xFFFF, sum = 0
7905 06:52:06.858282 6, 0xFFFF, sum = 0
7906 06:52:06.860946 7, 0xFFFF, sum = 0
7907 06:52:06.861421 8, 0xFFFF, sum = 0
7908 06:52:06.864502 9, 0xFFFF, sum = 0
7909 06:52:06.865021 10, 0xFFFF, sum = 0
7910 06:52:06.867572 11, 0xFFFF, sum = 0
7911 06:52:06.868062 12, 0x8FFF, sum = 0
7912 06:52:06.871599 13, 0x0, sum = 1
7913 06:52:06.872258 14, 0x0, sum = 2
7914 06:52:06.875221 15, 0x0, sum = 3
7915 06:52:06.875768 16, 0x0, sum = 4
7916 06:52:06.877662 best_step = 14
7917 06:52:06.878088
7918 06:52:06.878444 ==
7919 06:52:06.881188 Dram Type= 6, Freq= 0, CH_0, rank 1
7920 06:52:06.884522 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7921 06:52:06.885156 ==
7922 06:52:06.885537 RX Vref Scan: 0
7923 06:52:06.887774
7924 06:52:06.888359 RX Vref 0 -> 0, step: 1
7925 06:52:06.888781
7926 06:52:06.891293 RX Delay 11 -> 252, step: 4
7927 06:52:06.894365 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7928 06:52:06.901036 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7929 06:52:06.905012 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7930 06:52:06.907534 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7931 06:52:06.911392 iDelay=195, Bit 4, Center 128 (71 ~ 186) 116
7932 06:52:06.914138 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7933 06:52:06.920591 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7934 06:52:06.924455 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7935 06:52:06.927913 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7936 06:52:06.931012 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7937 06:52:06.934114 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7938 06:52:06.940602 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7939 06:52:06.943970 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7940 06:52:06.947076 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7941 06:52:06.950411 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7942 06:52:06.957181 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7943 06:52:06.957768 ==
7944 06:52:06.960479 Dram Type= 6, Freq= 0, CH_0, rank 1
7945 06:52:06.963662 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7946 06:52:06.964257 ==
7947 06:52:06.964696 DQS Delay:
7948 06:52:06.967562 DQS0 = 0, DQS1 = 0
7949 06:52:06.968032 DQM Delay:
7950 06:52:06.970559 DQM0 = 128, DQM1 = 120
7951 06:52:06.971129 DQ Delay:
7952 06:52:06.973762 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
7953 06:52:06.977254 DQ4 =128, DQ5 =118, DQ6 =138, DQ7 =138
7954 06:52:06.980091 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7955 06:52:06.984489 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7956 06:52:06.985020
7957 06:52:06.985396
7958 06:52:06.986714
7959 06:52:06.987182 [DramC_TX_OE_Calibration] TA2
7960 06:52:06.989779 Original DQ_B0 (3 6) =30, OEN = 27
7961 06:52:06.993089 Original DQ_B1 (3 6) =30, OEN = 27
7962 06:52:06.996534 24, 0x0, End_B0=24 End_B1=24
7963 06:52:06.999779 25, 0x0, End_B0=25 End_B1=25
7964 06:52:07.003518 26, 0x0, End_B0=26 End_B1=26
7965 06:52:07.004016 27, 0x0, End_B0=27 End_B1=27
7966 06:52:07.006269 28, 0x0, End_B0=28 End_B1=28
7967 06:52:07.009707 29, 0x0, End_B0=29 End_B1=29
7968 06:52:07.013539 30, 0x0, End_B0=30 End_B1=30
7969 06:52:07.016813 31, 0x4141, End_B0=30 End_B1=30
7970 06:52:07.017397 Byte0 end_step=30 best_step=27
7971 06:52:07.020474 Byte1 end_step=30 best_step=27
7972 06:52:07.023514 Byte0 TX OE(2T, 0.5T) = (3, 3)
7973 06:52:07.027231 Byte1 TX OE(2T, 0.5T) = (3, 3)
7974 06:52:07.027804
7975 06:52:07.028181
7976 06:52:07.034359 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7977 06:52:07.036641 CH0 RK1: MR19=303, MR18=2323
7978 06:52:07.043458 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
7979 06:52:07.047706 [RxdqsGatingPostProcess] freq 1600
7980 06:52:07.053002 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7981 06:52:07.057214 Pre-setting of DQS Precalculation
7982 06:52:07.059552 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7983 06:52:07.060028 ==
7984 06:52:07.063084 Dram Type= 6, Freq= 0, CH_1, rank 0
7985 06:52:07.066836 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7986 06:52:07.067449 ==
7987 06:52:07.073438 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7988 06:52:07.076123 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7989 06:52:07.082926 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7990 06:52:07.086867 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7991 06:52:07.095439 [CA 0] Center 41 (11~71) winsize 61
7992 06:52:07.098623 [CA 1] Center 40 (10~70) winsize 61
7993 06:52:07.101973 [CA 2] Center 36 (6~66) winsize 61
7994 06:52:07.105187 [CA 3] Center 35 (6~65) winsize 60
7995 06:52:07.108377 [CA 4] Center 33 (3~63) winsize 61
7996 06:52:07.113060 [CA 5] Center 33 (4~63) winsize 60
7997 06:52:07.113608
7998 06:52:07.116385 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7999 06:52:07.116899
8000 06:52:07.118532 [CATrainingPosCal] consider 1 rank data
8001 06:52:07.122523 u2DelayCellTimex100 = 275/100 ps
8002 06:52:07.125410 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8003 06:52:07.132470 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8004 06:52:07.135653 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8005 06:52:07.139213 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8006 06:52:07.142620 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
8007 06:52:07.145307 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8008 06:52:07.145781
8009 06:52:07.148359 CA PerBit enable=1, Macro0, CA PI delay=33
8010 06:52:07.148859
8011 06:52:07.151916 [CBTSetCACLKResult] CA Dly = 33
8012 06:52:07.155536 CS Dly: 8 (0~39)
8013 06:52:07.159005 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8014 06:52:07.161895 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8015 06:52:07.162360 ==
8016 06:52:07.164851 Dram Type= 6, Freq= 0, CH_1, rank 1
8017 06:52:07.168400 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8018 06:52:07.172301 ==
8019 06:52:07.174882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8020 06:52:07.178130 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8021 06:52:07.184889 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8022 06:52:07.191167 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8023 06:52:07.197532 [CA 0] Center 40 (10~70) winsize 61
8024 06:52:07.200792 [CA 1] Center 39 (9~70) winsize 62
8025 06:52:07.204539 [CA 2] Center 36 (7~65) winsize 59
8026 06:52:07.208143 [CA 3] Center 35 (6~65) winsize 60
8027 06:52:07.210746 [CA 4] Center 32 (3~62) winsize 60
8028 06:52:07.214429 [CA 5] Center 33 (3~63) winsize 61
8029 06:52:07.214751
8030 06:52:07.217736 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8031 06:52:07.218058
8032 06:52:07.220918 [CATrainingPosCal] consider 2 rank data
8033 06:52:07.224113 u2DelayCellTimex100 = 275/100 ps
8034 06:52:07.227460 CA0 delay=40 (11~70),Diff = 8 PI (28 cell)
8035 06:52:07.234504 CA1 delay=40 (10~70),Diff = 8 PI (28 cell)
8036 06:52:07.240196 CA2 delay=36 (7~65),Diff = 4 PI (14 cell)
8037 06:52:07.240944 CA3 delay=35 (6~65),Diff = 3 PI (10 cell)
8038 06:52:07.244142 CA4 delay=32 (3~62),Diff = 0 PI (0 cell)
8039 06:52:07.247658 CA5 delay=33 (4~63),Diff = 1 PI (3 cell)
8040 06:52:07.248054
8041 06:52:07.251182 CA PerBit enable=1, Macro0, CA PI delay=32
8042 06:52:07.251505
8043 06:52:07.253785 [CBTSetCACLKResult] CA Dly = 32
8044 06:52:07.257305 CS Dly: 9 (0~41)
8045 06:52:07.261136 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8046 06:52:07.264278 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8047 06:52:07.264695
8048 06:52:07.268627 ----->DramcWriteLeveling(PI) begin...
8049 06:52:07.269119 ==
8050 06:52:07.270578 Dram Type= 6, Freq= 0, CH_1, rank 0
8051 06:52:07.277114 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8052 06:52:07.277600 ==
8053 06:52:07.280882 Write leveling (Byte 0): 21 => 21
8054 06:52:07.281371 Write leveling (Byte 1): 22 => 22
8055 06:52:07.283851 DramcWriteLeveling(PI) end<-----
8056 06:52:07.284362
8057 06:52:07.284694 ==
8058 06:52:07.287235 Dram Type= 6, Freq= 0, CH_1, rank 0
8059 06:52:07.293988 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8060 06:52:07.294407 ==
8061 06:52:07.297176 [Gating] SW mode calibration
8062 06:52:07.303891 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8063 06:52:07.307201 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8064 06:52:07.313476 0 12 0 | B1->B0 | 2c2c 3434 | 1 0 | (0 0) (0 0)
8065 06:52:07.317110 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 06:52:07.319940 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 06:52:07.326979 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 06:52:07.329966 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 06:52:07.334092 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 06:52:07.339904 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8071 06:52:07.343714 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8072 06:52:07.347309 0 13 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
8073 06:52:07.353540 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8074 06:52:07.356513 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 06:52:07.359922 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 06:52:07.367505 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 06:52:07.369817 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 06:52:07.373720 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 06:52:07.379984 0 13 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8080 06:52:07.383399 0 14 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8081 06:52:07.386463 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 06:52:07.393670 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 06:52:07.396888 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 06:52:07.399941 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 06:52:07.406777 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 06:52:07.409186 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8087 06:52:07.412834 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8088 06:52:07.419728 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8089 06:52:07.423431 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8090 06:52:07.426748 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 06:52:07.432615 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 06:52:07.436228 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 06:52:07.439337 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 06:52:07.446439 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 06:52:07.449322 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 06:52:07.452921 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 06:52:07.458923 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 06:52:07.461997 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 06:52:07.465820 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 06:52:07.473569 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 06:52:07.475938 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 06:52:07.479127 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 06:52:07.485493 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8104 06:52:07.488847 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8105 06:52:07.491996 Total UI for P1: 0, mck2ui 16
8106 06:52:07.495182 best dqsien dly found for B0: ( 1, 0, 28)
8107 06:52:07.499157 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 06:52:07.502027 Total UI for P1: 0, mck2ui 16
8109 06:52:07.505087 best dqsien dly found for B1: ( 1, 1, 0)
8110 06:52:07.509342 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8111 06:52:07.512302 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8112 06:52:07.512925
8113 06:52:07.515647 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8114 06:52:07.521883 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8115 06:52:07.522418 [Gating] SW calibration Done
8116 06:52:07.522786 ==
8117 06:52:07.524990 Dram Type= 6, Freq= 0, CH_1, rank 0
8118 06:52:07.531748 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8119 06:52:07.532400 ==
8120 06:52:07.532843 RX Vref Scan: 0
8121 06:52:07.533209
8122 06:52:07.534885 RX Vref 0 -> 0, step: 1
8123 06:52:07.535460
8124 06:52:07.539072 RX Delay 0 -> 252, step: 8
8125 06:52:07.541897 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8126 06:52:07.545270 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8127 06:52:07.549164 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8128 06:52:07.554917 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8129 06:52:07.558248 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8130 06:52:07.561290 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8131 06:52:07.564942 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8132 06:52:07.568261 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8133 06:52:07.574934 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8134 06:52:07.577775 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8135 06:52:07.581524 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8136 06:52:07.584748 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8137 06:52:07.587956 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8138 06:52:07.594285 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8139 06:52:07.597429 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8140 06:52:07.600803 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8141 06:52:07.601572 ==
8142 06:52:07.604265 Dram Type= 6, Freq= 0, CH_1, rank 0
8143 06:52:07.607634 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8144 06:52:07.611738 ==
8145 06:52:07.612275 DQS Delay:
8146 06:52:07.612804 DQS0 = 0, DQS1 = 0
8147 06:52:07.614324 DQM Delay:
8148 06:52:07.614804 DQM0 = 130, DQM1 = 125
8149 06:52:07.617967 DQ Delay:
8150 06:52:07.621102 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8151 06:52:07.624438 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8152 06:52:07.627376 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8153 06:52:07.630782 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8154 06:52:07.631377
8155 06:52:07.631868
8156 06:52:07.632324 ==
8157 06:52:07.634109 Dram Type= 6, Freq= 0, CH_1, rank 0
8158 06:52:07.637582 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8159 06:52:07.638068 ==
8160 06:52:07.641170
8161 06:52:07.641648
8162 06:52:07.642134 TX Vref Scan disable
8163 06:52:07.643871 == TX Byte 0 ==
8164 06:52:07.647486 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8165 06:52:07.650291 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8166 06:52:07.654379 == TX Byte 1 ==
8167 06:52:07.657518 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8168 06:52:07.661010 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8169 06:52:07.661638 ==
8170 06:52:07.664193 Dram Type= 6, Freq= 0, CH_1, rank 0
8171 06:52:07.670743 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8172 06:52:07.671227 ==
8173 06:52:07.681439
8174 06:52:07.685168 TX Vref early break, caculate TX vref
8175 06:52:07.689362 TX Vref=16, minBit 3, minWin=21, winSum=367
8176 06:52:07.691607 TX Vref=18, minBit 3, minWin=22, winSum=375
8177 06:52:07.694845 TX Vref=20, minBit 3, minWin=22, winSum=384
8178 06:52:07.699040 TX Vref=22, minBit 3, minWin=23, winSum=393
8179 06:52:07.701175 TX Vref=24, minBit 0, minWin=24, winSum=400
8180 06:52:07.707914 TX Vref=26, minBit 3, minWin=23, winSum=410
8181 06:52:07.711183 TX Vref=28, minBit 1, minWin=24, winSum=413
8182 06:52:07.715194 TX Vref=30, minBit 1, minWin=24, winSum=403
8183 06:52:07.718511 TX Vref=32, minBit 3, minWin=23, winSum=399
8184 06:52:07.721345 TX Vref=34, minBit 3, minWin=23, winSum=390
8185 06:52:07.728059 [TxChooseVref] Worse bit 1, Min win 24, Win sum 413, Final Vref 28
8186 06:52:07.728480
8187 06:52:07.730877 Final TX Range 0 Vref 28
8188 06:52:07.731203
8189 06:52:07.731460 ==
8190 06:52:07.734250 Dram Type= 6, Freq= 0, CH_1, rank 0
8191 06:52:07.737866 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8192 06:52:07.738191 ==
8193 06:52:07.738446
8194 06:52:07.738683
8195 06:52:07.740962 TX Vref Scan disable
8196 06:52:07.747756 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8197 06:52:07.748176 == TX Byte 0 ==
8198 06:52:07.751240 u2DelayCellOfst[0]=17 cells (5 PI)
8199 06:52:07.754642 u2DelayCellOfst[1]=10 cells (3 PI)
8200 06:52:07.757593 u2DelayCellOfst[2]=0 cells (0 PI)
8201 06:52:07.761820 u2DelayCellOfst[3]=7 cells (2 PI)
8202 06:52:07.764330 u2DelayCellOfst[4]=10 cells (3 PI)
8203 06:52:07.768081 u2DelayCellOfst[5]=17 cells (5 PI)
8204 06:52:07.770755 u2DelayCellOfst[6]=17 cells (5 PI)
8205 06:52:07.774550 u2DelayCellOfst[7]=10 cells (3 PI)
8206 06:52:07.777607 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8207 06:52:07.780945 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8208 06:52:07.784766 == TX Byte 1 ==
8209 06:52:07.785330 u2DelayCellOfst[8]=0 cells (0 PI)
8210 06:52:07.787892 u2DelayCellOfst[9]=7 cells (2 PI)
8211 06:52:07.791219 u2DelayCellOfst[10]=10 cells (3 PI)
8212 06:52:07.794049 u2DelayCellOfst[11]=3 cells (1 PI)
8213 06:52:07.797571 u2DelayCellOfst[12]=17 cells (5 PI)
8214 06:52:07.801132 u2DelayCellOfst[13]=21 cells (6 PI)
8215 06:52:07.804910 u2DelayCellOfst[14]=21 cells (6 PI)
8216 06:52:07.808019 u2DelayCellOfst[15]=21 cells (6 PI)
8217 06:52:07.810570 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8218 06:52:07.818657 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8219 06:52:07.819121 DramC Write-DBI on
8220 06:52:07.819486 ==
8221 06:52:07.820753 Dram Type= 6, Freq= 0, CH_1, rank 0
8222 06:52:07.827555 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8223 06:52:07.828125 ==
8224 06:52:07.828498
8225 06:52:07.828885
8226 06:52:07.829222 TX Vref Scan disable
8227 06:52:07.831147 == TX Byte 0 ==
8228 06:52:07.834578 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8229 06:52:07.837803 == TX Byte 1 ==
8230 06:52:07.840782 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8231 06:52:07.844301 DramC Write-DBI off
8232 06:52:07.844806
8233 06:52:07.845180 [DATLAT]
8234 06:52:07.845529 Freq=1600, CH1 RK0
8235 06:52:07.845869
8236 06:52:07.847769 DATLAT Default: 0xf
8237 06:52:07.851103 0, 0xFFFF, sum = 0
8238 06:52:07.851575 1, 0xFFFF, sum = 0
8239 06:52:07.854148 2, 0xFFFF, sum = 0
8240 06:52:07.854670 3, 0xFFFF, sum = 0
8241 06:52:07.857516 4, 0xFFFF, sum = 0
8242 06:52:07.858149 5, 0xFFFF, sum = 0
8243 06:52:07.860569 6, 0xFFFF, sum = 0
8244 06:52:07.861095 7, 0xFFFF, sum = 0
8245 06:52:07.864177 8, 0xFFFF, sum = 0
8246 06:52:07.864649 9, 0xFFFF, sum = 0
8247 06:52:07.867276 10, 0xFFFF, sum = 0
8248 06:52:07.867750 11, 0xFFFF, sum = 0
8249 06:52:07.871064 12, 0x8FFF, sum = 0
8250 06:52:07.871539 13, 0x0, sum = 1
8251 06:52:07.874134 14, 0x0, sum = 2
8252 06:52:07.874608 15, 0x0, sum = 3
8253 06:52:07.877251 16, 0x0, sum = 4
8254 06:52:07.877820 best_step = 14
8255 06:52:07.878194
8256 06:52:07.878542 ==
8257 06:52:07.880594 Dram Type= 6, Freq= 0, CH_1, rank 0
8258 06:52:07.887162 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8259 06:52:07.887725 ==
8260 06:52:07.888101 RX Vref Scan: 1
8261 06:52:07.888446
8262 06:52:07.890551 Set Vref Range= 24 -> 127
8263 06:52:07.891018
8264 06:52:07.893899 RX Vref 24 -> 127, step: 1
8265 06:52:07.894517
8266 06:52:07.895058 RX Delay 3 -> 252, step: 4
8267 06:52:07.895446
8268 06:52:07.897197 Set Vref, RX VrefLevel [Byte0]: 24
8269 06:52:07.900304 [Byte1]: 24
8270 06:52:07.904485
8271 06:52:07.905020 Set Vref, RX VrefLevel [Byte0]: 25
8272 06:52:07.908322 [Byte1]: 25
8273 06:52:07.912620
8274 06:52:07.913130 Set Vref, RX VrefLevel [Byte0]: 26
8275 06:52:07.915149 [Byte1]: 26
8276 06:52:07.919833
8277 06:52:07.920375 Set Vref, RX VrefLevel [Byte0]: 27
8278 06:52:07.922985 [Byte1]: 27
8279 06:52:07.927475
8280 06:52:07.928015 Set Vref, RX VrefLevel [Byte0]: 28
8281 06:52:07.930594 [Byte1]: 28
8282 06:52:07.935170
8283 06:52:07.935703 Set Vref, RX VrefLevel [Byte0]: 29
8284 06:52:07.938994 [Byte1]: 29
8285 06:52:07.942695
8286 06:52:07.943158 Set Vref, RX VrefLevel [Byte0]: 30
8287 06:52:07.945386 [Byte1]: 30
8288 06:52:07.950056
8289 06:52:07.950594 Set Vref, RX VrefLevel [Byte0]: 31
8290 06:52:07.953701 [Byte1]: 31
8291 06:52:07.957567
8292 06:52:07.958028 Set Vref, RX VrefLevel [Byte0]: 32
8293 06:52:07.960910 [Byte1]: 32
8294 06:52:07.965157
8295 06:52:07.965616 Set Vref, RX VrefLevel [Byte0]: 33
8296 06:52:07.968987 [Byte1]: 33
8297 06:52:07.973269
8298 06:52:07.973729 Set Vref, RX VrefLevel [Byte0]: 34
8299 06:52:07.976976 [Byte1]: 34
8300 06:52:07.981066
8301 06:52:07.981528 Set Vref, RX VrefLevel [Byte0]: 35
8302 06:52:07.983739 [Byte1]: 35
8303 06:52:07.989098
8304 06:52:07.989661 Set Vref, RX VrefLevel [Byte0]: 36
8305 06:52:07.991556 [Byte1]: 36
8306 06:52:07.996812
8307 06:52:07.997297 Set Vref, RX VrefLevel [Byte0]: 37
8308 06:52:07.999610 [Byte1]: 37
8309 06:52:08.003783
8310 06:52:08.007065 Set Vref, RX VrefLevel [Byte0]: 38
8311 06:52:08.010084 [Byte1]: 38
8312 06:52:08.010548
8313 06:52:08.013134 Set Vref, RX VrefLevel [Byte0]: 39
8314 06:52:08.016605 [Byte1]: 39
8315 06:52:08.017134
8316 06:52:08.020351 Set Vref, RX VrefLevel [Byte0]: 40
8317 06:52:08.023143 [Byte1]: 40
8318 06:52:08.027717
8319 06:52:08.028222 Set Vref, RX VrefLevel [Byte0]: 41
8320 06:52:08.030233 [Byte1]: 41
8321 06:52:08.034894
8322 06:52:08.035412 Set Vref, RX VrefLevel [Byte0]: 42
8323 06:52:08.037842 [Byte1]: 42
8324 06:52:08.042262
8325 06:52:08.042819 Set Vref, RX VrefLevel [Byte0]: 43
8326 06:52:08.045328 [Byte1]: 43
8327 06:52:08.050298
8328 06:52:08.050857 Set Vref, RX VrefLevel [Byte0]: 44
8329 06:52:08.053030 [Byte1]: 44
8330 06:52:08.057398
8331 06:52:08.057854 Set Vref, RX VrefLevel [Byte0]: 45
8332 06:52:08.060329 [Byte1]: 45
8333 06:52:08.065389
8334 06:52:08.065843 Set Vref, RX VrefLevel [Byte0]: 46
8335 06:52:08.068051 [Byte1]: 46
8336 06:52:08.072912
8337 06:52:08.073600 Set Vref, RX VrefLevel [Byte0]: 47
8338 06:52:08.075943 [Byte1]: 47
8339 06:52:08.080392
8340 06:52:08.080992 Set Vref, RX VrefLevel [Byte0]: 48
8341 06:52:08.083478 [Byte1]: 48
8342 06:52:08.087930
8343 06:52:08.088471 Set Vref, RX VrefLevel [Byte0]: 49
8344 06:52:08.090933 [Byte1]: 49
8345 06:52:08.095688
8346 06:52:08.096210 Set Vref, RX VrefLevel [Byte0]: 50
8347 06:52:08.098991 [Byte1]: 50
8348 06:52:08.103008
8349 06:52:08.103506 Set Vref, RX VrefLevel [Byte0]: 51
8350 06:52:08.106506 [Byte1]: 51
8351 06:52:08.110768
8352 06:52:08.111225 Set Vref, RX VrefLevel [Byte0]: 52
8353 06:52:08.114045 [Byte1]: 52
8354 06:52:08.118235
8355 06:52:08.118690 Set Vref, RX VrefLevel [Byte0]: 53
8356 06:52:08.122065 [Byte1]: 53
8357 06:52:08.126353
8358 06:52:08.126813 Set Vref, RX VrefLevel [Byte0]: 54
8359 06:52:08.129439 [Byte1]: 54
8360 06:52:08.133728
8361 06:52:08.134271 Set Vref, RX VrefLevel [Byte0]: 55
8362 06:52:08.137546 [Byte1]: 55
8363 06:52:08.141631
8364 06:52:08.142179 Set Vref, RX VrefLevel [Byte0]: 56
8365 06:52:08.144591 [Byte1]: 56
8366 06:52:08.149658
8367 06:52:08.150216 Set Vref, RX VrefLevel [Byte0]: 57
8368 06:52:08.152440 [Byte1]: 57
8369 06:52:08.157048
8370 06:52:08.157597 Set Vref, RX VrefLevel [Byte0]: 58
8371 06:52:08.161375 [Byte1]: 58
8372 06:52:08.164544
8373 06:52:08.165127 Set Vref, RX VrefLevel [Byte0]: 59
8374 06:52:08.167536 [Byte1]: 59
8375 06:52:08.172132
8376 06:52:08.172854 Set Vref, RX VrefLevel [Byte0]: 60
8377 06:52:08.176340 [Byte1]: 60
8378 06:52:08.181067
8379 06:52:08.181595 Set Vref, RX VrefLevel [Byte0]: 61
8380 06:52:08.182956 [Byte1]: 61
8381 06:52:08.187264
8382 06:52:08.187794 Set Vref, RX VrefLevel [Byte0]: 62
8383 06:52:08.191240 [Byte1]: 62
8384 06:52:08.194693
8385 06:52:08.195146 Set Vref, RX VrefLevel [Byte0]: 63
8386 06:52:08.199289 [Byte1]: 63
8387 06:52:08.203275
8388 06:52:08.203809 Set Vref, RX VrefLevel [Byte0]: 64
8389 06:52:08.205762 [Byte1]: 64
8390 06:52:08.210690
8391 06:52:08.211221 Set Vref, RX VrefLevel [Byte0]: 65
8392 06:52:08.213758 [Byte1]: 65
8393 06:52:08.218360
8394 06:52:08.218815 Set Vref, RX VrefLevel [Byte0]: 66
8395 06:52:08.221053 [Byte1]: 66
8396 06:52:08.225629
8397 06:52:08.226102 Set Vref, RX VrefLevel [Byte0]: 67
8398 06:52:08.229045 [Byte1]: 67
8399 06:52:08.233453
8400 06:52:08.233912 Set Vref, RX VrefLevel [Byte0]: 68
8401 06:52:08.236840 [Byte1]: 68
8402 06:52:08.241347
8403 06:52:08.241809 Set Vref, RX VrefLevel [Byte0]: 69
8404 06:52:08.244483 [Byte1]: 69
8405 06:52:08.248984
8406 06:52:08.249615 Set Vref, RX VrefLevel [Byte0]: 70
8407 06:52:08.251909 [Byte1]: 70
8408 06:52:08.256163
8409 06:52:08.256632 Set Vref, RX VrefLevel [Byte0]: 71
8410 06:52:08.259454 [Byte1]: 71
8411 06:52:08.264054
8412 06:52:08.264534 Set Vref, RX VrefLevel [Byte0]: 72
8413 06:52:08.267570 [Byte1]: 72
8414 06:52:08.271958
8415 06:52:08.272488 Set Vref, RX VrefLevel [Byte0]: 73
8416 06:52:08.275829 [Byte1]: 73
8417 06:52:08.280154
8418 06:52:08.280620 Set Vref, RX VrefLevel [Byte0]: 74
8419 06:52:08.282819 [Byte1]: 74
8420 06:52:08.287691
8421 06:52:08.288365 Set Vref, RX VrefLevel [Byte0]: 75
8422 06:52:08.290187 [Byte1]: 75
8423 06:52:08.295624
8424 06:52:08.296316 Final RX Vref Byte 0 = 61 to rank0
8425 06:52:08.298640 Final RX Vref Byte 1 = 52 to rank0
8426 06:52:08.300918 Final RX Vref Byte 0 = 61 to rank1
8427 06:52:08.304821 Final RX Vref Byte 1 = 52 to rank1==
8428 06:52:08.307718 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 06:52:08.314167 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8430 06:52:08.314591 ==
8431 06:52:08.314924 DQS Delay:
8432 06:52:08.317533 DQS0 = 0, DQS1 = 0
8433 06:52:08.317952 DQM Delay:
8434 06:52:08.318288 DQM0 = 129, DQM1 = 123
8435 06:52:08.321408 DQ Delay:
8436 06:52:08.324834 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8437 06:52:08.327870 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8438 06:52:08.331045 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114
8439 06:52:08.334230 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =134
8440 06:52:08.334768
8441 06:52:08.335145
8442 06:52:08.335487
8443 06:52:08.337501 [DramC_TX_OE_Calibration] TA2
8444 06:52:08.340686 Original DQ_B0 (3 6) =30, OEN = 27
8445 06:52:08.343809 Original DQ_B1 (3 6) =30, OEN = 27
8446 06:52:08.347269 24, 0x0, End_B0=24 End_B1=24
8447 06:52:08.347827 25, 0x0, End_B0=25 End_B1=25
8448 06:52:08.351041 26, 0x0, End_B0=26 End_B1=26
8449 06:52:08.354127 27, 0x0, End_B0=27 End_B1=27
8450 06:52:08.357206 28, 0x0, End_B0=28 End_B1=28
8451 06:52:08.360444 29, 0x0, End_B0=29 End_B1=29
8452 06:52:08.361033 30, 0x0, End_B0=30 End_B1=30
8453 06:52:08.363807 31, 0x4141, End_B0=30 End_B1=30
8454 06:52:08.367577 Byte0 end_step=30 best_step=27
8455 06:52:08.371035 Byte1 end_step=30 best_step=27
8456 06:52:08.374186 Byte0 TX OE(2T, 0.5T) = (3, 3)
8457 06:52:08.377227 Byte1 TX OE(2T, 0.5T) = (3, 3)
8458 06:52:08.377699
8459 06:52:08.378066
8460 06:52:08.384752 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8461 06:52:08.387704 CH1 RK0: MR19=303, MR18=2929
8462 06:52:08.394609 CH1_RK0: MR19=0x303, MR18=0x2929, DQSOSC=389, MR23=63, INC=24, DEC=16
8463 06:52:08.395209
8464 06:52:08.397531 ----->DramcWriteLeveling(PI) begin...
8465 06:52:08.398007 ==
8466 06:52:08.400107 Dram Type= 6, Freq= 0, CH_1, rank 1
8467 06:52:08.403522 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8468 06:52:08.404087 ==
8469 06:52:08.406816 Write leveling (Byte 0): 21 => 21
8470 06:52:08.410675 Write leveling (Byte 1): 21 => 21
8471 06:52:08.413428 DramcWriteLeveling(PI) end<-----
8472 06:52:08.413902
8473 06:52:08.414275 ==
8474 06:52:08.416918 Dram Type= 6, Freq= 0, CH_1, rank 1
8475 06:52:08.420401 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8476 06:52:08.420907 ==
8477 06:52:08.423474 [Gating] SW mode calibration
8478 06:52:08.430849 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8479 06:52:08.436752 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8480 06:52:08.440640 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8481 06:52:08.447133 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8482 06:52:08.450129 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8483 06:52:08.453587 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8484 06:52:08.459995 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8485 06:52:08.463143 0 12 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8486 06:52:08.466582 0 12 24 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8487 06:52:08.473166 0 12 28 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8488 06:52:08.477160 0 13 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8489 06:52:08.480222 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8490 06:52:08.486478 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8491 06:52:08.489979 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8492 06:52:08.493441 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8493 06:52:08.499808 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8494 06:52:08.502895 0 13 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
8495 06:52:08.506529 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8496 06:52:08.513306 0 14 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8497 06:52:08.516163 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8498 06:52:08.519853 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8499 06:52:08.523013 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8500 06:52:08.529533 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8501 06:52:08.532795 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8502 06:52:08.537453 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8503 06:52:08.542241 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8504 06:52:08.546459 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8505 06:52:08.549246 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 06:52:08.556942 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 06:52:08.559546 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 06:52:08.562698 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 06:52:08.569415 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 06:52:08.572891 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 06:52:08.575974 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 06:52:08.582883 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 06:52:08.585929 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 06:52:08.589653 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 06:52:08.595665 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8516 06:52:08.601009 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8517 06:52:08.602500 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8518 06:52:08.609090 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8519 06:52:08.612244 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8520 06:52:08.615510 Total UI for P1: 0, mck2ui 16
8521 06:52:08.619705 best dqsien dly found for B0: ( 1, 0, 24)
8522 06:52:08.622573 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8523 06:52:08.628758 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8524 06:52:08.629331 Total UI for P1: 0, mck2ui 16
8525 06:52:08.635836 best dqsien dly found for B1: ( 1, 0, 30)
8526 06:52:08.639438 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8527 06:52:08.641925 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8528 06:52:08.642390
8529 06:52:08.645516 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8530 06:52:08.649088 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8531 06:52:08.652310 [Gating] SW calibration Done
8532 06:52:08.652918 ==
8533 06:52:08.655221 Dram Type= 6, Freq= 0, CH_1, rank 1
8534 06:52:08.658733 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8535 06:52:08.659278 ==
8536 06:52:08.662208 RX Vref Scan: 0
8537 06:52:08.662703
8538 06:52:08.663072 RX Vref 0 -> 0, step: 1
8539 06:52:08.663647
8540 06:52:08.666084 RX Delay 0 -> 252, step: 8
8541 06:52:08.668529 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8542 06:52:08.675400 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8543 06:52:08.678671 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8544 06:52:08.682350 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8545 06:52:08.685216 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8546 06:52:08.688438 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8547 06:52:08.695540 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8548 06:52:08.699020 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8549 06:52:08.702309 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8550 06:52:08.705432 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8551 06:52:08.708795 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8552 06:52:08.715319 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8553 06:52:08.718331 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8554 06:52:08.722083 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8555 06:52:08.724988 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8556 06:52:08.731363 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8557 06:52:08.731913 ==
8558 06:52:08.735020 Dram Type= 6, Freq= 0, CH_1, rank 1
8559 06:52:08.738105 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8560 06:52:08.738573 ==
8561 06:52:08.738939 DQS Delay:
8562 06:52:08.741689 DQS0 = 0, DQS1 = 0
8563 06:52:08.742149 DQM Delay:
8564 06:52:08.745654 DQM0 = 131, DQM1 = 124
8565 06:52:08.746192 DQ Delay:
8566 06:52:08.748469 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =131
8567 06:52:08.751739 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =131
8568 06:52:08.754742 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8569 06:52:08.758092 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8570 06:52:08.758635
8571 06:52:08.759002
8572 06:52:08.762363 ==
8573 06:52:08.762920 Dram Type= 6, Freq= 0, CH_1, rank 1
8574 06:52:08.768232 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8575 06:52:08.768842 ==
8576 06:52:08.769221
8577 06:52:08.769564
8578 06:52:08.771234 TX Vref Scan disable
8579 06:52:08.771720 == TX Byte 0 ==
8580 06:52:08.774756 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8581 06:52:08.781642 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8582 06:52:08.782199 == TX Byte 1 ==
8583 06:52:08.785007 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8584 06:52:08.791622 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8585 06:52:08.792208 ==
8586 06:52:08.795011 Dram Type= 6, Freq= 0, CH_1, rank 1
8587 06:52:08.798133 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8588 06:52:08.798702 ==
8589 06:52:08.810772
8590 06:52:08.814628 TX Vref early break, caculate TX vref
8591 06:52:08.817143 TX Vref=16, minBit 7, minWin=22, winSum=379
8592 06:52:08.819984 TX Vref=18, minBit 0, minWin=23, winSum=387
8593 06:52:08.823424 TX Vref=20, minBit 1, minWin=23, winSum=397
8594 06:52:08.826571 TX Vref=22, minBit 3, minWin=24, winSum=405
8595 06:52:08.830540 TX Vref=24, minBit 0, minWin=25, winSum=416
8596 06:52:08.837545 TX Vref=26, minBit 2, minWin=25, winSum=420
8597 06:52:08.840265 TX Vref=28, minBit 0, minWin=25, winSum=422
8598 06:52:08.843113 TX Vref=30, minBit 0, minWin=25, winSum=415
8599 06:52:08.846483 TX Vref=32, minBit 0, minWin=25, winSum=411
8600 06:52:08.850171 TX Vref=34, minBit 0, minWin=23, winSum=398
8601 06:52:08.856690 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8602 06:52:08.857207
8603 06:52:08.860052 Final TX Range 0 Vref 28
8604 06:52:08.860618
8605 06:52:08.861052 ==
8606 06:52:08.863019 Dram Type= 6, Freq= 0, CH_1, rank 1
8607 06:52:08.866417 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8608 06:52:08.866890 ==
8609 06:52:08.867265
8610 06:52:08.867612
8611 06:52:08.870435 TX Vref Scan disable
8612 06:52:08.876528 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8613 06:52:08.877151 == TX Byte 0 ==
8614 06:52:08.879636 u2DelayCellOfst[0]=17 cells (5 PI)
8615 06:52:08.883414 u2DelayCellOfst[1]=10 cells (3 PI)
8616 06:52:08.886521 u2DelayCellOfst[2]=0 cells (0 PI)
8617 06:52:08.890068 u2DelayCellOfst[3]=10 cells (3 PI)
8618 06:52:08.893304 u2DelayCellOfst[4]=10 cells (3 PI)
8619 06:52:08.896208 u2DelayCellOfst[5]=14 cells (4 PI)
8620 06:52:08.899248 u2DelayCellOfst[6]=14 cells (4 PI)
8621 06:52:08.903178 u2DelayCellOfst[7]=7 cells (2 PI)
8622 06:52:08.906963 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8623 06:52:08.909749 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8624 06:52:08.913059 == TX Byte 1 ==
8625 06:52:08.915809 u2DelayCellOfst[8]=0 cells (0 PI)
8626 06:52:08.916276 u2DelayCellOfst[9]=3 cells (1 PI)
8627 06:52:08.919572 u2DelayCellOfst[10]=10 cells (3 PI)
8628 06:52:08.923236 u2DelayCellOfst[11]=3 cells (1 PI)
8629 06:52:08.925650 u2DelayCellOfst[12]=14 cells (4 PI)
8630 06:52:08.928871 u2DelayCellOfst[13]=17 cells (5 PI)
8631 06:52:08.932577 u2DelayCellOfst[14]=17 cells (5 PI)
8632 06:52:08.936591 u2DelayCellOfst[15]=17 cells (5 PI)
8633 06:52:08.943071 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8634 06:52:08.945980 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8635 06:52:08.946452 DramC Write-DBI on
8636 06:52:08.946822 ==
8637 06:52:08.948805 Dram Type= 6, Freq= 0, CH_1, rank 1
8638 06:52:08.955885 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8639 06:52:08.956440 ==
8640 06:52:08.956866
8641 06:52:08.957226
8642 06:52:08.957686 TX Vref Scan disable
8643 06:52:08.959425 == TX Byte 0 ==
8644 06:52:08.962850 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8645 06:52:08.966519 == TX Byte 1 ==
8646 06:52:08.969320 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8647 06:52:08.973083 DramC Write-DBI off
8648 06:52:08.973558
8649 06:52:08.974039 [DATLAT]
8650 06:52:08.974400 Freq=1600, CH1 RK1
8651 06:52:08.974736
8652 06:52:08.976006 DATLAT Default: 0xe
8653 06:52:08.976526 0, 0xFFFF, sum = 0
8654 06:52:08.979148 1, 0xFFFF, sum = 0
8655 06:52:08.979620 2, 0xFFFF, sum = 0
8656 06:52:08.982691 3, 0xFFFF, sum = 0
8657 06:52:08.986063 4, 0xFFFF, sum = 0
8658 06:52:08.986537 5, 0xFFFF, sum = 0
8659 06:52:08.989449 6, 0xFFFF, sum = 0
8660 06:52:08.989922 7, 0xFFFF, sum = 0
8661 06:52:08.992806 8, 0xFFFF, sum = 0
8662 06:52:08.993404 9, 0xFFFF, sum = 0
8663 06:52:08.996154 10, 0xFFFF, sum = 0
8664 06:52:08.996656 11, 0xFFFF, sum = 0
8665 06:52:09.000040 12, 0x8F5F, sum = 0
8666 06:52:09.000693 13, 0x0, sum = 1
8667 06:52:09.002722 14, 0x0, sum = 2
8668 06:52:09.003195 15, 0x0, sum = 3
8669 06:52:09.006160 16, 0x0, sum = 4
8670 06:52:09.006734 best_step = 14
8671 06:52:09.007193
8672 06:52:09.007562 ==
8673 06:52:09.009395 Dram Type= 6, Freq= 0, CH_1, rank 1
8674 06:52:09.012486 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8675 06:52:09.016178 ==
8676 06:52:09.016642 RX Vref Scan: 0
8677 06:52:09.017150
8678 06:52:09.020212 RX Vref 0 -> 0, step: 1
8679 06:52:09.020880
8680 06:52:09.021271 RX Delay 3 -> 252, step: 4
8681 06:52:09.026389 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8682 06:52:09.030605 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8683 06:52:09.033212 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8684 06:52:09.036825 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8685 06:52:09.040589 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8686 06:52:09.046536 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8687 06:52:09.050249 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8688 06:52:09.053270 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8689 06:52:09.056419 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8690 06:52:09.062748 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8691 06:52:09.066136 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8692 06:52:09.069119 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8693 06:52:09.072790 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8694 06:52:09.076128 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8695 06:52:09.082638 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8696 06:52:09.086411 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8697 06:52:09.087048 ==
8698 06:52:09.089382 Dram Type= 6, Freq= 0, CH_1, rank 1
8699 06:52:09.092780 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8700 06:52:09.093349 ==
8701 06:52:09.095998 DQS Delay:
8702 06:52:09.096576 DQS0 = 0, DQS1 = 0
8703 06:52:09.097018 DQM Delay:
8704 06:52:09.098950 DQM0 = 127, DQM1 = 122
8705 06:52:09.099413 DQ Delay:
8706 06:52:09.102813 DQ0 =128, DQ1 =122, DQ2 =118, DQ3 =124
8707 06:52:09.106254 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8708 06:52:09.112853 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8709 06:52:09.115917 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8710 06:52:09.116385
8711 06:52:09.116801
8712 06:52:09.117159
8713 06:52:09.118813 [DramC_TX_OE_Calibration] TA2
8714 06:52:09.122325 Original DQ_B0 (3 6) =30, OEN = 27
8715 06:52:09.125615 Original DQ_B1 (3 6) =30, OEN = 27
8716 06:52:09.126083 24, 0x0, End_B0=24 End_B1=24
8717 06:52:09.128788 25, 0x0, End_B0=25 End_B1=25
8718 06:52:09.132274 26, 0x0, End_B0=26 End_B1=26
8719 06:52:09.135606 27, 0x0, End_B0=27 End_B1=27
8720 06:52:09.136078 28, 0x0, End_B0=28 End_B1=28
8721 06:52:09.139041 29, 0x0, End_B0=29 End_B1=29
8722 06:52:09.142494 30, 0x0, End_B0=30 End_B1=30
8723 06:52:09.145411 31, 0x4141, End_B0=30 End_B1=30
8724 06:52:09.148756 Byte0 end_step=30 best_step=27
8725 06:52:09.151994 Byte1 end_step=30 best_step=27
8726 06:52:09.152464 Byte0 TX OE(2T, 0.5T) = (3, 3)
8727 06:52:09.155823 Byte1 TX OE(2T, 0.5T) = (3, 3)
8728 06:52:09.156291
8729 06:52:09.156659
8730 06:52:09.166521 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8731 06:52:09.169313 CH1 RK1: MR19=303, MR18=1C1C
8732 06:52:09.172900 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8733 06:52:09.175752 [RxdqsGatingPostProcess] freq 1600
8734 06:52:09.182939 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8735 06:52:09.185914 Pre-setting of DQS Precalculation
8736 06:52:09.188447 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8737 06:52:09.199234 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8738 06:52:09.205077 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8739 06:52:09.205545
8740 06:52:09.205914
8741 06:52:09.208436 [Calibration Summary] 3200 Mbps
8742 06:52:09.209058 CH 0, Rank 0
8743 06:52:09.211537 SW Impedance : PASS
8744 06:52:09.212011 DUTY Scan : NO K
8745 06:52:09.215271 ZQ Calibration : PASS
8746 06:52:09.218697 Jitter Meter : NO K
8747 06:52:09.219257 CBT Training : PASS
8748 06:52:09.221733 Write leveling : PASS
8749 06:52:09.224989 RX DQS gating : PASS
8750 06:52:09.225457 RX DQ/DQS(RDDQC) : PASS
8751 06:52:09.228433 TX DQ/DQS : PASS
8752 06:52:09.232142 RX DATLAT : PASS
8753 06:52:09.232608 RX DQ/DQS(Engine): PASS
8754 06:52:09.235115 TX OE : PASS
8755 06:52:09.235583 All Pass.
8756 06:52:09.235952
8757 06:52:09.238591 CH 0, Rank 1
8758 06:52:09.239188 SW Impedance : PASS
8759 06:52:09.241699 DUTY Scan : NO K
8760 06:52:09.245067 ZQ Calibration : PASS
8761 06:52:09.245693 Jitter Meter : NO K
8762 06:52:09.248018 CBT Training : PASS
8763 06:52:09.248484 Write leveling : PASS
8764 06:52:09.252490 RX DQS gating : PASS
8765 06:52:09.255571 RX DQ/DQS(RDDQC) : PASS
8766 06:52:09.256077 TX DQ/DQS : PASS
8767 06:52:09.259036 RX DATLAT : PASS
8768 06:52:09.261966 RX DQ/DQS(Engine): PASS
8769 06:52:09.262576 TX OE : PASS
8770 06:52:09.265187 All Pass.
8771 06:52:09.265651
8772 06:52:09.266021 CH 1, Rank 0
8773 06:52:09.268182 SW Impedance : PASS
8774 06:52:09.268648 DUTY Scan : NO K
8775 06:52:09.271622 ZQ Calibration : PASS
8776 06:52:09.275045 Jitter Meter : NO K
8777 06:52:09.275612 CBT Training : PASS
8778 06:52:09.277725 Write leveling : PASS
8779 06:52:09.281455 RX DQS gating : PASS
8780 06:52:09.282016 RX DQ/DQS(RDDQC) : PASS
8781 06:52:09.285116 TX DQ/DQS : PASS
8782 06:52:09.289123 RX DATLAT : PASS
8783 06:52:09.289718 RX DQ/DQS(Engine): PASS
8784 06:52:09.291718 TX OE : PASS
8785 06:52:09.292287 All Pass.
8786 06:52:09.292663
8787 06:52:09.295146 CH 1, Rank 1
8788 06:52:09.295713 SW Impedance : PASS
8789 06:52:09.297765 DUTY Scan : NO K
8790 06:52:09.301016 ZQ Calibration : PASS
8791 06:52:09.301555 Jitter Meter : NO K
8792 06:52:09.304768 CBT Training : PASS
8793 06:52:09.308571 Write leveling : PASS
8794 06:52:09.309202 RX DQS gating : PASS
8795 06:52:09.312025 RX DQ/DQS(RDDQC) : PASS
8796 06:52:09.314169 TX DQ/DQS : PASS
8797 06:52:09.314887 RX DATLAT : PASS
8798 06:52:09.317565 RX DQ/DQS(Engine): PASS
8799 06:52:09.318120 TX OE : PASS
8800 06:52:09.321740 All Pass.
8801 06:52:09.322205
8802 06:52:09.322570 DramC Write-DBI on
8803 06:52:09.324255 PER_BANK_REFRESH: Hybrid Mode
8804 06:52:09.327719 TX_TRACKING: ON
8805 06:52:09.333932 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8806 06:52:09.344082 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8807 06:52:09.350704 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8808 06:52:09.354018 [FAST_K] Save calibration result to emmc
8809 06:52:09.357550 sync common calibartion params.
8810 06:52:09.358018 sync cbt_mode0:0, 1:0
8811 06:52:09.360905 dram_init: ddr_geometry: 0
8812 06:52:09.364479 dram_init: ddr_geometry: 0
8813 06:52:09.366893 dram_init: ddr_geometry: 0
8814 06:52:09.367392 0:dram_rank_size:80000000
8815 06:52:09.370874 1:dram_rank_size:80000000
8816 06:52:09.377648 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8817 06:52:09.378138 DFS_SHUFFLE_HW_MODE: ON
8818 06:52:09.383865 dramc_set_vcore_voltage set vcore to 725000
8819 06:52:09.384287 Read voltage for 1600, 0
8820 06:52:09.387339 Vio18 = 0
8821 06:52:09.387781 Vcore = 725000
8822 06:52:09.388122 Vdram = 0
8823 06:52:09.388440 Vddq = 0
8824 06:52:09.390625 Vmddr = 0
8825 06:52:09.393172 switch to 3200 Mbps bootup
8826 06:52:09.393615 [DramcRunTimeConfig]
8827 06:52:09.393958 PHYPLL
8828 06:52:09.396739 DPM_CONTROL_AFTERK: ON
8829 06:52:09.397163 PER_BANK_REFRESH: ON
8830 06:52:09.400032 REFRESH_OVERHEAD_REDUCTION: ON
8831 06:52:09.403393 CMD_PICG_NEW_MODE: OFF
8832 06:52:09.403912 XRTWTW_NEW_MODE: ON
8833 06:52:09.406644 XRTRTR_NEW_MODE: ON
8834 06:52:09.407071 TX_TRACKING: ON
8835 06:52:09.409716 RDSEL_TRACKING: OFF
8836 06:52:09.413458 DQS Precalculation for DVFS: ON
8837 06:52:09.413886 RX_TRACKING: OFF
8838 06:52:09.416378 HW_GATING DBG: ON
8839 06:52:09.416950 ZQCS_ENABLE_LP4: ON
8840 06:52:09.420569 RX_PICG_NEW_MODE: ON
8841 06:52:09.423163 TX_PICG_NEW_MODE: ON
8842 06:52:09.423681 ENABLE_RX_DCM_DPHY: ON
8843 06:52:09.427107 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8844 06:52:09.429937 DUMMY_READ_FOR_TRACKING: OFF
8845 06:52:09.433648 !!! SPM_CONTROL_AFTERK: OFF
8846 06:52:09.434197 !!! SPM could not control APHY
8847 06:52:09.436687 IMPEDANCE_TRACKING: ON
8848 06:52:09.440151 TEMP_SENSOR: ON
8849 06:52:09.440614 HW_SAVE_FOR_SR: OFF
8850 06:52:09.443175 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8851 06:52:09.446587 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8852 06:52:09.450502 Read ODT Tracking: ON
8853 06:52:09.451072 Refresh Rate DeBounce: ON
8854 06:52:09.452996 DFS_NO_QUEUE_FLUSH: ON
8855 06:52:09.456626 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8856 06:52:09.459801 ENABLE_DFS_RUNTIME_MRW: OFF
8857 06:52:09.460268 DDR_RESERVE_NEW_MODE: ON
8858 06:52:09.462861 MR_CBT_SWITCH_FREQ: ON
8859 06:52:09.466451 =========================
8860 06:52:09.484333 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8861 06:52:09.487966 dram_init: ddr_geometry: 0
8862 06:52:09.506185 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8863 06:52:09.508921 dram_init: dram init end (result: 0)
8864 06:52:09.516065 DRAM-K: Full calibration passed in 23429 msecs
8865 06:52:09.519606 MRC: failed to locate region type 0.
8866 06:52:09.520187 DRAM rank0 size:0x80000000,
8867 06:52:09.521988 DRAM rank1 size=0x80000000
8868 06:52:09.532640 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8869 06:52:09.538853 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8870 06:52:09.545169 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8871 06:52:09.552430 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8872 06:52:09.555009 DRAM rank0 size:0x80000000,
8873 06:52:09.559051 DRAM rank1 size=0x80000000
8874 06:52:09.559726 CBMEM:
8875 06:52:09.561682 IMD: root @ 0xfffff000 254 entries.
8876 06:52:09.564963 IMD: root @ 0xffffec00 62 entries.
8877 06:52:09.568815 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8878 06:52:09.572173 WARNING: RO_VPD is uninitialized or empty.
8879 06:52:09.579221 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8880 06:52:09.585206 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8881 06:52:09.598035 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8882 06:52:09.609291 BS: romstage times (exec / console): total (unknown) / 22969 ms
8883 06:52:09.609844
8884 06:52:09.610218
8885 06:52:09.620138 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8886 06:52:09.622643 ARM64: Exception handlers installed.
8887 06:52:09.625967 ARM64: Testing exception
8888 06:52:09.629398 ARM64: Done test exception
8889 06:52:09.629866 Enumerating buses...
8890 06:52:09.633077 Show all devs... Before device enumeration.
8891 06:52:09.636212 Root Device: enabled 1
8892 06:52:09.639712 CPU_CLUSTER: 0: enabled 1
8893 06:52:09.640182 CPU: 00: enabled 1
8894 06:52:09.642678 Compare with tree...
8895 06:52:09.643256 Root Device: enabled 1
8896 06:52:09.646070 CPU_CLUSTER: 0: enabled 1
8897 06:52:09.649340 CPU: 00: enabled 1
8898 06:52:09.649909 Root Device scanning...
8899 06:52:09.652275 scan_static_bus for Root Device
8900 06:52:09.655913 CPU_CLUSTER: 0 enabled
8901 06:52:09.659148 scan_static_bus for Root Device done
8902 06:52:09.662278 scan_bus: bus Root Device finished in 8 msecs
8903 06:52:09.662862 done
8904 06:52:09.669305 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8905 06:52:09.672206 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8906 06:52:09.678809 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8907 06:52:09.681729 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8908 06:52:09.685543 Allocating resources...
8909 06:52:09.688521 Reading resources...
8910 06:52:09.691736 Root Device read_resources bus 0 link: 0
8911 06:52:09.695139 DRAM rank0 size:0x80000000,
8912 06:52:09.695614 DRAM rank1 size=0x80000000
8913 06:52:09.698255 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8914 06:52:09.701968 CPU: 00 missing read_resources
8915 06:52:09.708359 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8916 06:52:09.711530 Root Device read_resources bus 0 link: 0 done
8917 06:52:09.712134 Done reading resources.
8918 06:52:09.718136 Show resources in subtree (Root Device)...After reading.
8919 06:52:09.721520 Root Device child on link 0 CPU_CLUSTER: 0
8920 06:52:09.724620 CPU_CLUSTER: 0 child on link 0 CPU: 00
8921 06:52:09.735038 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8922 06:52:09.735605 CPU: 00
8923 06:52:09.738378 Root Device assign_resources, bus 0 link: 0
8924 06:52:09.742268 CPU_CLUSTER: 0 missing set_resources
8925 06:52:09.748253 Root Device assign_resources, bus 0 link: 0 done
8926 06:52:09.748878 Done setting resources.
8927 06:52:09.755892 Show resources in subtree (Root Device)...After assigning values.
8928 06:52:09.758842 Root Device child on link 0 CPU_CLUSTER: 0
8929 06:52:09.761132 CPU_CLUSTER: 0 child on link 0 CPU: 00
8930 06:52:09.771183 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8931 06:52:09.771656 CPU: 00
8932 06:52:09.775756 Done allocating resources.
8933 06:52:09.781033 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8934 06:52:09.781502 Enabling resources...
8935 06:52:09.781946 done.
8936 06:52:09.788689 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8937 06:52:09.791090 Initializing devices...
8938 06:52:09.791655 Root Device init
8939 06:52:09.794306 init hardware done!
8940 06:52:09.794874 0x00000018: ctrlr->caps
8941 06:52:09.797620 52.000 MHz: ctrlr->f_max
8942 06:52:09.800445 0.400 MHz: ctrlr->f_min
8943 06:52:09.800981 0x40ff8080: ctrlr->voltages
8944 06:52:09.804198 sclk: 390625
8945 06:52:09.804819 Bus Width = 1
8946 06:52:09.805208 sclk: 390625
8947 06:52:09.807043 Bus Width = 1
8948 06:52:09.810715 Early init status = 3
8949 06:52:09.814081 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8950 06:52:09.817840 in-header: 03 fc 00 00 01 00 00 00
8951 06:52:09.820606 in-data: 00
8952 06:52:09.824405 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8953 06:52:09.827759 in-header: 03 fd 00 00 00 00 00 00
8954 06:52:09.831185 in-data:
8955 06:52:09.835533 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8956 06:52:09.838378 in-header: 03 fc 00 00 01 00 00 00
8957 06:52:09.840999 in-data: 00
8958 06:52:09.845208 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8959 06:52:09.849059 in-header: 03 fd 00 00 00 00 00 00
8960 06:52:09.852605 in-data:
8961 06:52:09.856125 [SSUSB] Setting up USB HOST controller...
8962 06:52:09.859918 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8963 06:52:09.862343 [SSUSB] phy power-on done.
8964 06:52:09.866348 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8965 06:52:09.872511 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8966 06:52:09.876789 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8967 06:52:09.882533 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8968 06:52:09.889474 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
8969 06:52:09.896343 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8970 06:52:09.902049 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8971 06:52:09.908849 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8972 06:52:09.912124 SPM: binary array size = 0x9dc
8973 06:52:09.915964 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8974 06:52:09.922018 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8975 06:52:09.928571 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8976 06:52:09.932152 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8977 06:52:09.939134 configure_display: Starting display init
8978 06:52:09.972378 anx7625_power_on_init: Init interface.
8979 06:52:09.975694 anx7625_disable_pd_protocol: Disabled PD feature.
8980 06:52:09.978739 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8981 06:52:10.007842 anx7625_start_dp_work: Secure OCM version=00
8982 06:52:10.010217 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8983 06:52:10.024946 sp_tx_get_edid_block: EDID Block = 1
8984 06:52:10.128601 Extracted contents:
8985 06:52:10.131097 header: 00 ff ff ff ff ff ff 00
8986 06:52:10.134411 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8987 06:52:10.137548 version: 01 04
8988 06:52:10.140633 basic params: 95 1f 11 78 0a
8989 06:52:10.145301 chroma info: 76 90 94 55 54 90 27 21 50 54
8990 06:52:10.147325 established: 00 00 00
8991 06:52:10.153540 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8992 06:52:10.157251 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8993 06:52:10.163978 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8994 06:52:10.170500 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8995 06:52:10.176968 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8996 06:52:10.180540 extensions: 00
8997 06:52:10.181248 checksum: fb
8998 06:52:10.181631
8999 06:52:10.183581 Manufacturer: IVO Model 57d Serial Number 0
9000 06:52:10.186933 Made week 0 of 2020
9001 06:52:10.190428 EDID version: 1.4
9002 06:52:10.190999 Digital display
9003 06:52:10.194809 6 bits per primary color channel
9004 06:52:10.195359 DisplayPort interface
9005 06:52:10.197421 Maximum image size: 31 cm x 17 cm
9006 06:52:10.200000 Gamma: 220%
9007 06:52:10.200610 Check DPMS levels
9008 06:52:10.204524 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9009 06:52:10.210666 First detailed timing is preferred timing
9010 06:52:10.211237 Established timings supported:
9011 06:52:10.213260 Standard timings supported:
9012 06:52:10.216810 Detailed timings
9013 06:52:10.220265 Hex of detail: 383680a07038204018303c0035ae10000019
9014 06:52:10.227150 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9015 06:52:10.230050 0780 0798 07c8 0820 hborder 0
9016 06:52:10.233050 0438 043b 0447 0458 vborder 0
9017 06:52:10.236313 -hsync -vsync
9018 06:52:10.236826 Did detailed timing
9019 06:52:10.243219 Hex of detail: 000000000000000000000000000000000000
9020 06:52:10.246674 Manufacturer-specified data, tag 0
9021 06:52:10.250415 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9022 06:52:10.253664 ASCII string: InfoVision
9023 06:52:10.257301 Hex of detail: 000000fe00523134304e574635205248200a
9024 06:52:10.259965 ASCII string: R140NWF5 RH
9025 06:52:10.260538 Checksum
9026 06:52:10.263497 Checksum: 0xfb (valid)
9027 06:52:10.266486 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9028 06:52:10.270982 DSI data_rate: 832800000 bps
9029 06:52:10.277522 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9030 06:52:10.279953 anx7625_parse_edid: pixelclock(138800).
9031 06:52:10.283520 hactive(1920), hsync(48), hfp(24), hbp(88)
9032 06:52:10.287672 vactive(1080), vsync(12), vfp(3), vbp(17)
9033 06:52:10.289416 anx7625_dsi_config: config dsi.
9034 06:52:10.296094 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9035 06:52:10.310826 anx7625_dsi_config: success to config DSI
9036 06:52:10.313230 anx7625_dp_start: MIPI phy setup OK.
9037 06:52:10.316308 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9038 06:52:10.319041 mtk_ddp_mode_set invalid vrefresh 60
9039 06:52:10.322714 main_disp_path_setup
9040 06:52:10.323302 ovl_layer_smi_id_en
9041 06:52:10.326045 ovl_layer_smi_id_en
9042 06:52:10.326510 ccorr_config
9043 06:52:10.326880 aal_config
9044 06:52:10.330103 gamma_config
9045 06:52:10.330568 postmask_config
9046 06:52:10.332916 dither_config
9047 06:52:10.336183 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9048 06:52:10.342893 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9049 06:52:10.345747 Root Device init finished in 551 msecs
9050 06:52:10.349797 CPU_CLUSTER: 0 init
9051 06:52:10.356471 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9052 06:52:10.360010 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9053 06:52:10.362854 APU_MBOX 0x190000b0 = 0x10001
9054 06:52:10.365763 APU_MBOX 0x190001b0 = 0x10001
9055 06:52:10.369148 APU_MBOX 0x190005b0 = 0x10001
9056 06:52:10.373101 APU_MBOX 0x190006b0 = 0x10001
9057 06:52:10.375499 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9058 06:52:10.389412 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9059 06:52:10.401091 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9060 06:52:10.407610 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9061 06:52:10.419224 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9062 06:52:10.428107 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9063 06:52:10.431744 CPU_CLUSTER: 0 init finished in 81 msecs
9064 06:52:10.434657 Devices initialized
9065 06:52:10.437859 Show all devs... After init.
9066 06:52:10.438343 Root Device: enabled 1
9067 06:52:10.441488 CPU_CLUSTER: 0: enabled 1
9068 06:52:10.444636 CPU: 00: enabled 1
9069 06:52:10.448080 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9070 06:52:10.451249 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9071 06:52:10.455316 ELOG: NV offset 0x57f000 size 0x1000
9072 06:52:10.461597 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9073 06:52:10.467732 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9074 06:52:10.471469 ELOG: Event(17) added with size 13 at 2024-02-03 06:52:10 UTC
9075 06:52:10.474423 out: cmd=0x121: 03 db 21 01 00 00 00 00
9076 06:52:10.479184 in-header: 03 f8 00 00 2c 00 00 00
9077 06:52:10.491856 in-data: 6b 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9078 06:52:10.498533 ELOG: Event(A1) added with size 10 at 2024-02-03 06:52:10 UTC
9079 06:52:10.504741 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9080 06:52:10.511855 ELOG: Event(A0) added with size 9 at 2024-02-03 06:52:10 UTC
9081 06:52:10.514673 elog_add_boot_reason: Logged dev mode boot
9082 06:52:10.517891 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9083 06:52:10.521227 Finalize devices...
9084 06:52:10.521694 Devices finalized
9085 06:52:10.528842 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9086 06:52:10.532574 Writing coreboot table at 0xffe64000
9087 06:52:10.535383 0. 000000000010a000-0000000000113fff: RAMSTAGE
9088 06:52:10.537745 1. 0000000040000000-00000000400fffff: RAM
9089 06:52:10.544809 2. 0000000040100000-000000004032afff: RAMSTAGE
9090 06:52:10.547765 3. 000000004032b000-00000000545fffff: RAM
9091 06:52:10.551310 4. 0000000054600000-000000005465ffff: BL31
9092 06:52:10.554484 5. 0000000054660000-00000000ffe63fff: RAM
9093 06:52:10.561543 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9094 06:52:10.565178 7. 0000000100000000-000000013fffffff: RAM
9095 06:52:10.567979 Passing 5 GPIOs to payload:
9096 06:52:10.571170 NAME | PORT | POLARITY | VALUE
9097 06:52:10.574218 EC in RW | 0x000000aa | low | undefined
9098 06:52:10.581414 EC interrupt | 0x00000005 | low | undefined
9099 06:52:10.584654 TPM interrupt | 0x000000ab | high | undefined
9100 06:52:10.591365 SD card detect | 0x00000011 | high | undefined
9101 06:52:10.595262 speaker enable | 0x00000093 | high | undefined
9102 06:52:10.597716 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9103 06:52:10.601009 in-header: 03 f8 00 00 02 00 00 00
9104 06:52:10.604523 in-data: 03 00
9105 06:52:10.605141 ADC[4]: Raw value=668958 ID=5
9106 06:52:10.607578 ADC[3]: Raw value=212180 ID=1
9107 06:52:10.610712 RAM Code: 0x51
9108 06:52:10.611178 ADC[6]: Raw value=74410 ID=0
9109 06:52:10.614687 ADC[5]: Raw value=211444 ID=1
9110 06:52:10.617530 SKU Code: 0x1
9111 06:52:10.622531 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1295
9112 06:52:10.624517 coreboot table: 964 bytes.
9113 06:52:10.627232 IMD ROOT 0. 0xfffff000 0x00001000
9114 06:52:10.630538 IMD SMALL 1. 0xffffe000 0x00001000
9115 06:52:10.634175 RO MCACHE 2. 0xffffc000 0x00001104
9116 06:52:10.637378 CONSOLE 3. 0xfff7c000 0x00080000
9117 06:52:10.640829 FMAP 4. 0xfff7b000 0x00000452
9118 06:52:10.644154 TIME STAMP 5. 0xfff7a000 0x00000910
9119 06:52:10.648125 VBOOT WORK 6. 0xfff66000 0x00014000
9120 06:52:10.650794 RAMOOPS 7. 0xffe66000 0x00100000
9121 06:52:10.654235 COREBOOT 8. 0xffe64000 0x00002000
9122 06:52:10.654794 IMD small region:
9123 06:52:10.656932 IMD ROOT 0. 0xffffec00 0x00000400
9124 06:52:10.663637 VPD 1. 0xffffeb80 0x0000006c
9125 06:52:10.668225 MMC STATUS 2. 0xffffeb60 0x00000004
9126 06:52:10.671325 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9127 06:52:10.674309 Probing TPM: done!
9128 06:52:10.678672 Connected to device vid:did:rid of 1ae0:0028:00
9129 06:52:10.687378 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9130 06:52:10.690309 Initialized TPM device CR50 revision 0
9131 06:52:10.694201 Checking cr50 for pending updates
9132 06:52:10.697737 Reading cr50 TPM mode
9133 06:52:10.706814 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9134 06:52:10.713412 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9135 06:52:10.753628 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9136 06:52:10.757039 Checking segment from ROM address 0x40100000
9137 06:52:10.763470 Checking segment from ROM address 0x4010001c
9138 06:52:10.766350 Loading segment from ROM address 0x40100000
9139 06:52:10.766911 code (compression=0)
9140 06:52:10.777033 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9141 06:52:10.783124 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9142 06:52:10.783758 it's not compressed!
9143 06:52:10.789940 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9144 06:52:10.793645 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9145 06:52:10.813153 Loading segment from ROM address 0x4010001c
9146 06:52:10.813778 Entry Point 0x80000000
9147 06:52:10.817010 Loaded segments
9148 06:52:10.823100 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9149 06:52:10.826765 Jumping to boot code at 0x80000000(0xffe64000)
9150 06:52:10.833551 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9151 06:52:10.839888 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9152 06:52:10.847933 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9153 06:52:10.851567 Checking segment from ROM address 0x40100000
9154 06:52:10.854927 Checking segment from ROM address 0x4010001c
9155 06:52:10.863051 Loading segment from ROM address 0x40100000
9156 06:52:10.863620 code (compression=1)
9157 06:52:10.868334 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9158 06:52:10.878509 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9159 06:52:10.879089 using LZMA
9160 06:52:10.886370 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9161 06:52:10.892669 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9162 06:52:10.896045 Loading segment from ROM address 0x4010001c
9163 06:52:10.896611 Entry Point 0x54601000
9164 06:52:10.899692 Loaded segments
9165 06:52:10.903681 NOTICE: MT8192 bl31_setup
9166 06:52:10.909671 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9167 06:52:10.912976 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9168 06:52:10.916325 WARNING: region 0:
9169 06:52:10.920117 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9170 06:52:10.920592 WARNING: region 1:
9171 06:52:10.926312 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9172 06:52:10.929690 WARNING: region 2:
9173 06:52:10.932928 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9174 06:52:10.936412 WARNING: region 3:
9175 06:52:10.939499 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9176 06:52:10.942953 WARNING: region 4:
9177 06:52:10.949895 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9178 06:52:10.950325 WARNING: region 5:
9179 06:52:10.953130 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9180 06:52:10.956538 WARNING: region 6:
9181 06:52:10.959683 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9182 06:52:10.963030 WARNING: region 7:
9183 06:52:10.966784 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9184 06:52:10.973385 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9185 06:52:10.977042 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9186 06:52:10.979831 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9187 06:52:10.986668 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9188 06:52:10.990182 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9189 06:52:10.992875 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9190 06:52:11.000880 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9191 06:52:11.003222 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9192 06:52:11.009681 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9193 06:52:11.012631 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9194 06:52:11.016488 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9195 06:52:11.022844 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9196 06:52:11.025850 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9197 06:52:11.029829 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9198 06:52:11.036079 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9199 06:52:11.039783 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9200 06:52:11.046742 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9201 06:52:11.050323 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9202 06:52:11.053660 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9203 06:52:11.059686 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9204 06:52:11.063052 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9205 06:52:11.066439 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9206 06:52:11.073452 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9207 06:52:11.076427 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9208 06:52:11.084376 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9209 06:52:11.086588 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9210 06:52:11.089875 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9211 06:52:11.096551 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9212 06:52:11.100822 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9213 06:52:11.106400 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9214 06:52:11.109366 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9215 06:52:11.112951 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9216 06:52:11.119298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9217 06:52:11.123374 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9218 06:52:11.126183 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9219 06:52:11.129452 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9220 06:52:11.136515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9221 06:52:11.140052 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9222 06:52:11.143909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9223 06:52:11.145764 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9224 06:52:11.153168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9225 06:52:11.156039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9226 06:52:11.159290 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9227 06:52:11.163047 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9228 06:52:11.169518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9229 06:52:11.172943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9230 06:52:11.175783 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9231 06:52:11.179652 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9232 06:52:11.186600 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9233 06:52:11.189469 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9234 06:52:11.196395 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9235 06:52:11.199395 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9236 06:52:11.205391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9237 06:52:11.209325 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9238 06:52:11.212412 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9239 06:52:11.219093 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9240 06:52:11.222466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9241 06:52:11.228673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9242 06:52:11.232363 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9243 06:52:11.240314 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9244 06:52:11.243036 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9245 06:52:11.248849 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9246 06:52:11.252664 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9247 06:52:11.257026 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9248 06:52:11.262453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9249 06:52:11.265527 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9250 06:52:11.273254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9251 06:52:11.275667 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9252 06:52:11.282717 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9253 06:52:11.285670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9254 06:52:11.289283 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9255 06:52:11.295432 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9256 06:52:11.299769 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9257 06:52:11.306090 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9258 06:52:11.308531 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9259 06:52:11.315912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9260 06:52:11.318683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9261 06:52:11.325532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9262 06:52:11.329105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9263 06:52:11.331744 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9264 06:52:11.338723 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9265 06:52:11.342900 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9266 06:52:11.349201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9267 06:52:11.351766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9268 06:52:11.358683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9269 06:52:11.362389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9270 06:52:11.367308 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9271 06:52:11.372043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9272 06:52:11.375160 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9273 06:52:11.382300 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9274 06:52:11.386007 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9275 06:52:11.392208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9276 06:52:11.396426 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9277 06:52:11.399345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9278 06:52:11.405632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9279 06:52:11.408911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9280 06:52:11.416445 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9281 06:52:11.419232 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9282 06:52:11.422590 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9283 06:52:11.425269 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9284 06:52:11.432140 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9285 06:52:11.435277 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9286 06:52:11.439056 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9287 06:52:11.445717 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9288 06:52:11.448680 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9289 06:52:11.452539 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9290 06:52:11.459182 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9291 06:52:11.462012 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9292 06:52:11.468900 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9293 06:52:11.472390 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9294 06:52:11.475324 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9295 06:52:11.481976 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9296 06:52:11.485480 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9297 06:52:11.491978 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9298 06:52:11.495569 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9299 06:52:11.498558 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9300 06:52:11.505595 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9301 06:52:11.508604 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9302 06:52:11.512020 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9303 06:52:11.518644 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9304 06:52:11.522459 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9305 06:52:11.525575 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9306 06:52:11.528568 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9307 06:52:11.535199 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9308 06:52:11.539076 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9309 06:52:11.542690 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9310 06:52:11.549044 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9311 06:52:11.551973 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9312 06:52:11.559035 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9313 06:52:11.562609 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9314 06:52:11.566256 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9315 06:52:11.572646 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9316 06:52:11.575521 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9317 06:52:11.579002 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9318 06:52:11.585548 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9319 06:52:11.589217 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9320 06:52:11.596499 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9321 06:52:11.599960 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9322 06:52:11.602223 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9323 06:52:11.609229 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9324 06:52:11.612396 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9325 06:52:11.619421 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9326 06:52:11.622420 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9327 06:52:11.625811 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9328 06:52:11.632050 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9329 06:52:11.635280 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9330 06:52:11.638795 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9331 06:52:11.645430 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9332 06:52:11.648566 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9333 06:52:11.655635 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9334 06:52:11.659112 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9335 06:52:11.661724 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9336 06:52:11.668789 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9337 06:52:11.673116 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9338 06:52:11.679013 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9339 06:52:11.682670 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9340 06:52:11.685606 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9341 06:52:11.692236 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9342 06:52:11.695276 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9343 06:52:11.698927 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9344 06:52:11.705035 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9345 06:52:11.709116 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9346 06:52:11.716088 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9347 06:52:11.719250 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9348 06:52:11.725187 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9349 06:52:11.728464 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9350 06:52:11.731420 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9351 06:52:11.738698 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9352 06:52:11.741743 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9353 06:52:11.744820 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9354 06:52:11.751209 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9355 06:52:11.754875 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9356 06:52:11.761336 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9357 06:52:11.765123 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9358 06:52:11.772008 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9359 06:52:11.774397 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9360 06:52:11.778342 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9361 06:52:11.784266 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9362 06:52:11.787656 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9363 06:52:11.791141 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9364 06:52:11.797489 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9365 06:52:11.801129 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9366 06:52:11.807904 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9367 06:52:11.810807 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9368 06:52:11.817149 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9369 06:52:11.820739 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9370 06:52:11.824166 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9371 06:52:11.830843 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9372 06:52:11.833604 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9373 06:52:11.840588 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9374 06:52:11.843926 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9375 06:52:11.846946 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9376 06:52:11.854039 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9377 06:52:11.856519 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9378 06:52:11.863174 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9379 06:52:11.866640 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9380 06:52:11.873238 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9381 06:52:11.876831 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9382 06:52:11.880080 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9383 06:52:11.886975 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9384 06:52:11.889894 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9385 06:52:11.896583 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9386 06:52:11.899787 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9387 06:52:11.906525 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9388 06:52:11.910130 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9389 06:52:11.914403 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9390 06:52:11.919681 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9391 06:52:11.922562 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9392 06:52:11.929527 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9393 06:52:11.933291 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9394 06:52:11.939341 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9395 06:52:11.942653 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9396 06:52:11.945509 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9397 06:52:11.952609 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9398 06:52:11.955691 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9399 06:52:11.962338 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9400 06:52:11.965656 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9401 06:52:11.972390 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9402 06:52:11.975804 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9403 06:52:11.979814 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9404 06:52:11.985295 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9405 06:52:11.988573 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9406 06:52:11.995711 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9407 06:52:11.998613 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9408 06:52:12.005483 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9409 06:52:12.008451 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9410 06:52:12.012020 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9411 06:52:12.019395 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9412 06:52:12.023884 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9413 06:52:12.024904 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9414 06:52:12.031503 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9415 06:52:12.035327 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9416 06:52:12.038667 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9417 06:52:12.042156 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9418 06:52:12.048020 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9419 06:52:12.052657 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9420 06:52:12.058479 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9421 06:52:12.061524 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9422 06:52:12.064459 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9423 06:52:12.071742 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9424 06:52:12.074252 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9425 06:52:12.077959 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9426 06:52:12.084533 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9427 06:52:12.087384 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9428 06:52:12.090755 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9429 06:52:12.097312 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9430 06:52:12.101286 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9431 06:52:12.107816 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9432 06:52:12.110568 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9433 06:52:12.113669 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9434 06:52:12.120387 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9435 06:52:12.124020 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9436 06:52:12.127239 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9437 06:52:12.134186 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9438 06:52:12.137520 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9439 06:52:12.143942 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9440 06:52:12.147000 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9441 06:52:12.150249 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9442 06:52:12.157336 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9443 06:52:12.160107 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9444 06:52:12.163710 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9445 06:52:12.171078 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9446 06:52:12.173851 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9447 06:52:12.177338 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9448 06:52:12.183560 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9449 06:52:12.187168 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9450 06:52:12.193396 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9451 06:52:12.196563 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9452 06:52:12.200244 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9453 06:52:12.206580 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9454 06:52:12.210092 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9455 06:52:12.213415 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9456 06:52:12.216598 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9457 06:52:12.220938 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9458 06:52:12.226913 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9459 06:52:12.229805 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9460 06:52:12.233214 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9461 06:52:12.237015 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9462 06:52:12.243233 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9463 06:52:12.247214 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9464 06:52:12.250129 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9465 06:52:12.256424 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9466 06:52:12.259618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9467 06:52:12.262750 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9468 06:52:12.269428 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9469 06:52:12.273240 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9470 06:52:12.279912 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9471 06:52:12.282870 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9472 06:52:12.289701 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9473 06:52:12.293195 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9474 06:52:12.296396 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9475 06:52:12.303334 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9476 06:52:12.306439 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9477 06:52:12.312478 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9478 06:52:12.315692 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9479 06:52:12.322681 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9480 06:52:12.325801 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9481 06:52:12.329153 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9482 06:52:12.335967 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9483 06:52:12.340339 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9484 06:52:12.345465 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9485 06:52:12.349285 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9486 06:52:12.352511 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9487 06:52:12.358775 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9488 06:52:12.362125 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9489 06:52:12.365782 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9490 06:52:12.372169 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9491 06:52:12.375619 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9492 06:52:12.382632 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9493 06:52:12.385737 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9494 06:52:12.391792 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9495 06:52:12.395860 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9496 06:52:12.401866 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9497 06:52:12.405636 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9498 06:52:12.409257 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9499 06:52:12.416073 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9500 06:52:12.419259 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9501 06:52:12.422009 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9502 06:52:12.428636 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9503 06:52:12.432211 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9504 06:52:12.439614 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9505 06:52:12.441504 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9506 06:52:12.445397 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9507 06:52:12.451676 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9508 06:52:12.455316 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9509 06:52:12.462060 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9510 06:52:12.464981 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9511 06:52:12.471739 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9512 06:52:12.475905 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9513 06:52:12.478796 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9514 06:52:12.485667 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9515 06:52:12.489055 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9516 06:52:12.494729 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9517 06:52:12.498558 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9518 06:52:12.501889 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9519 06:52:12.508288 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9520 06:52:12.511697 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9521 06:52:12.518777 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9522 06:52:12.521250 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9523 06:52:12.524665 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9524 06:52:12.531152 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9525 06:52:12.535671 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9526 06:52:12.541339 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9527 06:52:12.544634 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9528 06:52:12.551698 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9529 06:52:12.555803 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9530 06:52:12.557826 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9531 06:52:12.564619 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9532 06:52:12.568206 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9533 06:52:12.574811 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9534 06:52:12.577644 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9535 06:52:12.580760 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9536 06:52:12.587691 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9537 06:52:12.590723 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9538 06:52:12.597866 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9539 06:52:12.601174 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9540 06:52:12.607983 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9541 06:52:12.610770 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9542 06:52:12.614683 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9543 06:52:12.620625 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9544 06:52:12.624536 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9545 06:52:12.630491 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9546 06:52:12.633978 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9547 06:52:12.641695 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9548 06:52:12.643754 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9549 06:52:12.647690 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9550 06:52:12.653902 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9551 06:52:12.657097 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9552 06:52:12.663993 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9553 06:52:12.667611 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9554 06:52:12.674025 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9555 06:52:12.676913 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9556 06:52:12.683989 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9557 06:52:12.687057 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9558 06:52:12.690210 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9559 06:52:12.696679 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9560 06:52:12.700627 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9561 06:52:12.707505 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9562 06:52:12.710986 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9563 06:52:12.717214 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9564 06:52:12.721189 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9565 06:52:12.723553 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9566 06:52:12.730799 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9567 06:52:12.733603 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9568 06:52:12.739738 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9569 06:52:12.744025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9570 06:52:12.750305 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9571 06:52:12.753045 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9572 06:52:12.759475 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9573 06:52:12.763813 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9574 06:52:12.766459 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9575 06:52:12.773088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9576 06:52:12.776518 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9577 06:52:12.782960 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9578 06:52:12.786778 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9579 06:52:12.792506 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9580 06:52:12.795919 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9581 06:52:12.802785 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9582 06:52:12.806626 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9583 06:52:12.809431 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9584 06:52:12.816043 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9585 06:52:12.819155 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9586 06:52:12.826316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9587 06:52:12.830166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9588 06:52:12.832199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9589 06:52:12.839222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9590 06:52:12.843274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9591 06:52:12.849465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9592 06:52:12.852852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9593 06:52:12.859803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9594 06:52:12.862119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9595 06:52:12.869338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9596 06:52:12.872555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9597 06:52:12.878706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9598 06:52:12.882540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9599 06:52:12.889234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9600 06:52:12.891904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9601 06:52:12.899084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9602 06:52:12.901975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9603 06:52:12.909277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9604 06:52:12.912981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9605 06:52:12.919178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9606 06:52:12.921993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9607 06:52:12.928906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9608 06:52:12.931825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9609 06:52:12.938817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9610 06:52:12.942828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9611 06:52:12.948664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9612 06:52:12.951793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9613 06:52:12.958740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9614 06:52:12.961272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9615 06:52:12.968852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9616 06:52:12.972084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9617 06:52:12.978463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9618 06:52:12.981700 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9619 06:52:12.985396 INFO: [APUAPC] vio 0
9620 06:52:12.988191 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9621 06:52:12.994988 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9622 06:52:12.998542 INFO: [APUAPC] D0_APC_0: 0x400510
9623 06:52:12.999063 INFO: [APUAPC] D0_APC_1: 0x0
9624 06:52:13.002088 INFO: [APUAPC] D0_APC_2: 0x1540
9625 06:52:13.004813 INFO: [APUAPC] D0_APC_3: 0x0
9626 06:52:13.008100 INFO: [APUAPC] D1_APC_0: 0xffffffff
9627 06:52:13.012172 INFO: [APUAPC] D1_APC_1: 0xffffffff
9628 06:52:13.015221 INFO: [APUAPC] D1_APC_2: 0x3fffff
9629 06:52:13.018472 INFO: [APUAPC] D1_APC_3: 0x0
9630 06:52:13.021565 INFO: [APUAPC] D2_APC_0: 0xffffffff
9631 06:52:13.024908 INFO: [APUAPC] D2_APC_1: 0xffffffff
9632 06:52:13.028159 INFO: [APUAPC] D2_APC_2: 0x3fffff
9633 06:52:13.032390 INFO: [APUAPC] D2_APC_3: 0x0
9634 06:52:13.034708 INFO: [APUAPC] D3_APC_0: 0xffffffff
9635 06:52:13.038108 INFO: [APUAPC] D3_APC_1: 0xffffffff
9636 06:52:13.041355 INFO: [APUAPC] D3_APC_2: 0x3fffff
9637 06:52:13.044530 INFO: [APUAPC] D3_APC_3: 0x0
9638 06:52:13.048667 INFO: [APUAPC] D4_APC_0: 0xffffffff
9639 06:52:13.051303 INFO: [APUAPC] D4_APC_1: 0xffffffff
9640 06:52:13.054825 INFO: [APUAPC] D4_APC_2: 0x3fffff
9641 06:52:13.058941 INFO: [APUAPC] D4_APC_3: 0x0
9642 06:52:13.062076 INFO: [APUAPC] D5_APC_0: 0xffffffff
9643 06:52:13.065179 INFO: [APUAPC] D5_APC_1: 0xffffffff
9644 06:52:13.068303 INFO: [APUAPC] D5_APC_2: 0x3fffff
9645 06:52:13.071812 INFO: [APUAPC] D5_APC_3: 0x0
9646 06:52:13.075142 INFO: [APUAPC] D6_APC_0: 0xffffffff
9647 06:52:13.079812 INFO: [APUAPC] D6_APC_1: 0xffffffff
9648 06:52:13.081626 INFO: [APUAPC] D6_APC_2: 0x3fffff
9649 06:52:13.085011 INFO: [APUAPC] D6_APC_3: 0x0
9650 06:52:13.088281 INFO: [APUAPC] D7_APC_0: 0xffffffff
9651 06:52:13.091889 INFO: [APUAPC] D7_APC_1: 0xffffffff
9652 06:52:13.094917 INFO: [APUAPC] D7_APC_2: 0x3fffff
9653 06:52:13.097980 INFO: [APUAPC] D7_APC_3: 0x0
9654 06:52:13.101544 INFO: [APUAPC] D8_APC_0: 0xffffffff
9655 06:52:13.104434 INFO: [APUAPC] D8_APC_1: 0xffffffff
9656 06:52:13.108156 INFO: [APUAPC] D8_APC_2: 0x3fffff
9657 06:52:13.111576 INFO: [APUAPC] D8_APC_3: 0x0
9658 06:52:13.114528 INFO: [APUAPC] D9_APC_0: 0xffffffff
9659 06:52:13.117522 INFO: [APUAPC] D9_APC_1: 0xffffffff
9660 06:52:13.121398 INFO: [APUAPC] D9_APC_2: 0x3fffff
9661 06:52:13.121959 INFO: [APUAPC] D9_APC_3: 0x0
9662 06:52:13.127718 INFO: [APUAPC] D10_APC_0: 0xffffffff
9663 06:52:13.130989 INFO: [APUAPC] D10_APC_1: 0xffffffff
9664 06:52:13.134678 INFO: [APUAPC] D10_APC_2: 0x3fffff
9665 06:52:13.137380 INFO: [APUAPC] D10_APC_3: 0x0
9666 06:52:13.141104 INFO: [APUAPC] D11_APC_0: 0xffffffff
9667 06:52:13.144283 INFO: [APUAPC] D11_APC_1: 0xffffffff
9668 06:52:13.147319 INFO: [APUAPC] D11_APC_2: 0x3fffff
9669 06:52:13.150988 INFO: [APUAPC] D11_APC_3: 0x0
9670 06:52:13.154225 INFO: [APUAPC] D12_APC_0: 0xffffffff
9671 06:52:13.157627 INFO: [APUAPC] D12_APC_1: 0xffffffff
9672 06:52:13.160676 INFO: [APUAPC] D12_APC_2: 0x3fffff
9673 06:52:13.164593 INFO: [APUAPC] D12_APC_3: 0x0
9674 06:52:13.167502 INFO: [APUAPC] D13_APC_0: 0xffffffff
9675 06:52:13.171184 INFO: [APUAPC] D13_APC_1: 0xffffffff
9676 06:52:13.174467 INFO: [APUAPC] D13_APC_2: 0x3fffff
9677 06:52:13.177738 INFO: [APUAPC] D13_APC_3: 0x0
9678 06:52:13.181226 INFO: [APUAPC] D14_APC_0: 0xffffffff
9679 06:52:13.184376 INFO: [APUAPC] D14_APC_1: 0xffffffff
9680 06:52:13.187537 INFO: [APUAPC] D14_APC_2: 0x3fffff
9681 06:52:13.190273 INFO: [APUAPC] D14_APC_3: 0x0
9682 06:52:13.193914 INFO: [APUAPC] D15_APC_0: 0xffffffff
9683 06:52:13.197426 INFO: [APUAPC] D15_APC_1: 0xffffffff
9684 06:52:13.200771 INFO: [APUAPC] D15_APC_2: 0x3fffff
9685 06:52:13.203740 INFO: [APUAPC] D15_APC_3: 0x0
9686 06:52:13.208040 INFO: [APUAPC] APC_CON: 0x4
9687 06:52:13.208580 INFO: [NOCDAPC] D0_APC_0: 0x0
9688 06:52:13.210951 INFO: [NOCDAPC] D0_APC_1: 0x0
9689 06:52:13.213498 INFO: [NOCDAPC] D1_APC_0: 0x0
9690 06:52:13.217287 INFO: [NOCDAPC] D1_APC_1: 0xfff
9691 06:52:13.220381 INFO: [NOCDAPC] D2_APC_0: 0x0
9692 06:52:13.224305 INFO: [NOCDAPC] D2_APC_1: 0xfff
9693 06:52:13.227920 INFO: [NOCDAPC] D3_APC_0: 0x0
9694 06:52:13.231457 INFO: [NOCDAPC] D3_APC_1: 0xfff
9695 06:52:13.233984 INFO: [NOCDAPC] D4_APC_0: 0x0
9696 06:52:13.236808 INFO: [NOCDAPC] D4_APC_1: 0xfff
9697 06:52:13.237281 INFO: [NOCDAPC] D5_APC_0: 0x0
9698 06:52:13.239799 INFO: [NOCDAPC] D5_APC_1: 0xfff
9699 06:52:13.244199 INFO: [NOCDAPC] D6_APC_0: 0x0
9700 06:52:13.247318 INFO: [NOCDAPC] D6_APC_1: 0xfff
9701 06:52:13.250005 INFO: [NOCDAPC] D7_APC_0: 0x0
9702 06:52:13.253533 INFO: [NOCDAPC] D7_APC_1: 0xfff
9703 06:52:13.256450 INFO: [NOCDAPC] D8_APC_0: 0x0
9704 06:52:13.260001 INFO: [NOCDAPC] D8_APC_1: 0xfff
9705 06:52:13.263790 INFO: [NOCDAPC] D9_APC_0: 0x0
9706 06:52:13.267312 INFO: [NOCDAPC] D9_APC_1: 0xfff
9707 06:52:13.269542 INFO: [NOCDAPC] D10_APC_0: 0x0
9708 06:52:13.273933 INFO: [NOCDAPC] D10_APC_1: 0xfff
9709 06:52:13.276632 INFO: [NOCDAPC] D11_APC_0: 0x0
9710 06:52:13.277161 INFO: [NOCDAPC] D11_APC_1: 0xfff
9711 06:52:13.280088 INFO: [NOCDAPC] D12_APC_0: 0x0
9712 06:52:13.283388 INFO: [NOCDAPC] D12_APC_1: 0xfff
9713 06:52:13.286266 INFO: [NOCDAPC] D13_APC_0: 0x0
9714 06:52:13.290659 INFO: [NOCDAPC] D13_APC_1: 0xfff
9715 06:52:13.293107 INFO: [NOCDAPC] D14_APC_0: 0x0
9716 06:52:13.296610 INFO: [NOCDAPC] D14_APC_1: 0xfff
9717 06:52:13.299760 INFO: [NOCDAPC] D15_APC_0: 0x0
9718 06:52:13.303330 INFO: [NOCDAPC] D15_APC_1: 0xfff
9719 06:52:13.306412 INFO: [NOCDAPC] APC_CON: 0x4
9720 06:52:13.309895 INFO: [APUAPC] set_apusys_apc done
9721 06:52:13.312955 INFO: [DEVAPC] devapc_init done
9722 06:52:13.316427 INFO: GICv3 without legacy support detected.
9723 06:52:13.320184 INFO: ARM GICv3 driver initialized in EL3
9724 06:52:13.323633 INFO: Maximum SPI INTID supported: 639
9725 06:52:13.329488 INFO: BL31: Initializing runtime services
9726 06:52:13.332978 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9727 06:52:13.335991 INFO: SPM: enable CPC mode
9728 06:52:13.342871 INFO: mcdi ready for mcusys-off-idle and system suspend
9729 06:52:13.346347 INFO: BL31: Preparing for EL3 exit to normal world
9730 06:52:13.349759 INFO: Entry point address = 0x80000000
9731 06:52:13.352497 INFO: SPSR = 0x8
9732 06:52:13.357596
9733 06:52:13.358079
9734 06:52:13.358452
9735 06:52:13.361159 Starting depthcharge on Spherion...
9736 06:52:13.361629
9737 06:52:13.362001 Wipe memory regions:
9738 06:52:13.362350
9739 06:52:13.365078 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9740 06:52:13.365654 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9741 06:52:13.366110 Setting prompt string to ['asurada:']
9742 06:52:13.366552 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9743 06:52:13.367313 [0x00000040000000, 0x00000054600000)
9744 06:52:13.486704
9745 06:52:13.487272 [0x00000054660000, 0x00000080000000)
9746 06:52:13.747154
9747 06:52:13.747691 [0x000000821a7280, 0x000000ffe64000)
9748 06:52:14.492098
9749 06:52:14.492668 [0x00000100000000, 0x00000140000000)
9750 06:52:14.873258
9751 06:52:14.876399 Initializing XHCI USB controller at 0x11200000.
9752 06:52:15.914693
9753 06:52:15.917230 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9754 06:52:15.917699
9755 06:52:15.918069
9756 06:52:15.918414
9757 06:52:15.919210 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9759 06:52:16.020482 asurada: tftpboot 192.168.201.1 12694836/tftp-deploy-8v56v5jm/kernel/image.itb 12694836/tftp-deploy-8v56v5jm/kernel/cmdline
9760 06:52:16.021234 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9761 06:52:16.021749 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9762 06:52:16.026795 tftpboot 192.168.201.1 12694836/tftp-deploy-8v56v5jm/kernel/image.ittp-deploy-8v56v5jm/kernel/cmdline
9763 06:52:16.027371
9764 06:52:16.027745 Waiting for link
9765 06:52:16.187207
9766 06:52:16.187780 R8152: Initializing
9767 06:52:16.188160
9768 06:52:16.190304 Version 9 (ocp_data = 6010)
9769 06:52:16.190896
9770 06:52:16.193784 R8152: Done initializing
9771 06:52:16.194356
9772 06:52:16.194735 Adding net device
9773 06:52:18.201860
9774 06:52:18.202423 done.
9775 06:52:18.202797
9776 06:52:18.203142 MAC: 00:e0:4c:68:03:bd
9777 06:52:18.203474
9778 06:52:18.205381 Sending DHCP discover... done.
9779 06:52:18.205851
9780 06:52:28.740682 Waiting for reply... R8152: Bulk read error 0xffffffbf
9781 06:52:28.741313
9782 06:52:28.743383 Receive failed.
9783 06:52:28.743891
9784 06:52:28.744330 done.
9785 06:52:28.744681
9786 06:52:28.746273 Sending DHCP request... done.
9787 06:52:28.746739
9788 06:52:28.750048 Waiting for reply... done.
9789 06:52:28.750611
9790 06:52:28.753690 My ip is 192.168.201.16
9791 06:52:28.754158
9792 06:52:28.756782 The DHCP server ip is 192.168.201.1
9793 06:52:28.757459
9794 06:52:28.759845 TFTP server IP predefined by user: 192.168.201.1
9795 06:52:28.760423
9796 06:52:28.767817 Bootfile predefined by user: 12694836/tftp-deploy-8v56v5jm/kernel/image.itb
9797 06:52:28.768378
9798 06:52:28.769538 Sending tftp read request... done.
9799 06:52:28.770012
9800 06:52:28.777652 Waiting for the transfer...
9801 06:52:28.778216
9802 06:52:29.127624 00000000 ################################################################
9803 06:52:29.128132
9804 06:52:29.523371 00080000 ################################################################
9805 06:52:29.523518
9806 06:52:29.812233 00100000 ################################################################
9807 06:52:29.812377
9808 06:52:30.122870 00180000 ################################################################
9809 06:52:30.123005
9810 06:52:30.485564 00200000 ################################################################
9811 06:52:30.486095
9812 06:52:30.872704 00280000 ################################################################
9813 06:52:30.873281
9814 06:52:31.273326 00300000 ################################################################
9815 06:52:31.273920
9816 06:52:31.595887 00380000 ################################################################
9817 06:52:31.596033
9818 06:52:31.884839 00400000 ################################################################
9819 06:52:31.884980
9820 06:52:32.177078 00480000 ################################################################
9821 06:52:32.177216
9822 06:52:32.482564 00500000 ################################################################
9823 06:52:32.482730
9824 06:52:32.779636 00580000 ################################################################
9825 06:52:32.779778
9826 06:52:33.080617 00600000 ################################################################
9827 06:52:33.080766
9828 06:52:33.404148 00680000 ################################################################
9829 06:52:33.404287
9830 06:52:33.785537 00700000 ################################################################
9831 06:52:33.786082
9832 06:52:34.192753 00780000 ################################################################
9833 06:52:34.193281
9834 06:52:34.576821 00800000 ################################################################
9835 06:52:34.576966
9836 06:52:34.871401 00880000 ################################################################
9837 06:52:34.871569
9838 06:52:35.152573 00900000 ################################################################
9839 06:52:35.152761
9840 06:52:35.433412 00980000 ################################################################
9841 06:52:35.433545
9842 06:52:35.728109 00a00000 ################################################################
9843 06:52:35.728256
9844 06:52:36.009031 00a80000 ################################################################
9845 06:52:36.009180
9846 06:52:36.297760 00b00000 ################################################################
9847 06:52:36.297897
9848 06:52:36.594650 00b80000 ################################################################
9849 06:52:36.594788
9850 06:52:36.890751 00c00000 ################################################################
9851 06:52:36.890890
9852 06:52:37.179098 00c80000 ################################################################
9853 06:52:37.179238
9854 06:52:37.453934 00d00000 ################################################################
9855 06:52:37.454072
9856 06:52:37.735518 00d80000 ################################################################
9857 06:52:37.735661
9858 06:52:38.024856 00e00000 ################################################################
9859 06:52:38.024996
9860 06:52:38.311792 00e80000 ################################################################
9861 06:52:38.311937
9862 06:52:38.582342 00f00000 ################################################################
9863 06:52:38.582482
9864 06:52:38.855589 00f80000 ################################################################
9865 06:52:38.855759
9866 06:52:39.121171 01000000 ################################################################
9867 06:52:39.121328
9868 06:52:39.381583 01080000 ################################################################
9869 06:52:39.381721
9870 06:52:39.659961 01100000 ################################################################
9871 06:52:39.660097
9872 06:52:39.954304 01180000 ################################################################
9873 06:52:39.954442
9874 06:52:40.239906 01200000 ################################################################
9875 06:52:40.240048
9876 06:52:40.520364 01280000 ################################################################
9877 06:52:40.520501
9878 06:52:40.788122 01300000 ################################################################
9879 06:52:40.788262
9880 06:52:41.083819 01380000 ################################################################
9881 06:52:41.083987
9882 06:52:41.379222 01400000 ################################################################
9883 06:52:41.379389
9884 06:52:41.714912 01480000 ################################################################
9885 06:52:41.715427
9886 06:52:42.013863 01500000 ################################################################
9887 06:52:42.014001
9888 06:52:42.301970 01580000 ################################################################
9889 06:52:42.302105
9890 06:52:42.586257 01600000 ################################################################
9891 06:52:42.586397
9892 06:52:42.875988 01680000 ################################################################
9893 06:52:42.876129
9894 06:52:43.179553 01700000 ################################################################
9895 06:52:43.179689
9896 06:52:43.480635 01780000 ################################################################
9897 06:52:43.480820
9898 06:52:43.780929 01800000 ################################################################
9899 06:52:43.781073
9900 06:52:44.082398 01880000 ################################################################
9901 06:52:44.082538
9902 06:52:44.383105 01900000 ################################################################
9903 06:52:44.383246
9904 06:52:44.680977 01980000 ################################################################
9905 06:52:44.681119
9906 06:52:44.975624 01a00000 ################################################################
9907 06:52:44.975768
9908 06:52:45.267555 01a80000 ################################################################
9909 06:52:45.267696
9910 06:52:45.562106 01b00000 ################################################################
9911 06:52:45.562245
9912 06:52:45.860504 01b80000 ################################################################
9913 06:52:45.860732
9914 06:52:46.162764 01c00000 ################################################################
9915 06:52:46.162907
9916 06:52:46.531307 01c80000 ################################################################
9917 06:52:46.531871
9918 06:52:46.877825 01d00000 ################################################################
9919 06:52:46.877978
9920 06:52:47.245320 01d80000 ################################################################
9921 06:52:47.245831
9922 06:52:47.626957 01e00000 ################################################################
9923 06:52:47.627471
9924 06:52:48.014960 01e80000 ################################################################
9925 06:52:48.015482
9926 06:52:48.415918 01f00000 ################################################################
9927 06:52:48.416496
9928 06:52:48.856360 01f80000 ################################################################
9929 06:52:48.856938
9930 06:52:49.274699 02000000 ################################################################
9931 06:52:49.275248
9932 06:52:49.658894 02080000 ################################################################
9933 06:52:49.659494
9934 06:52:49.982466 02100000 ################################################################
9935 06:52:49.982610
9936 06:52:50.260319 02180000 ################################################################
9937 06:52:50.260490
9938 06:52:50.525232 02200000 ################################################################
9939 06:52:50.525417
9940 06:52:50.848847 02280000 ################################################################
9941 06:52:50.848987
9942 06:52:51.106944 02300000 ################################################################
9943 06:52:51.107079
9944 06:52:51.362395 02380000 ################################################################
9945 06:52:51.362541
9946 06:52:51.613496 02400000 ################################################################
9947 06:52:51.613636
9948 06:52:51.864698 02480000 ################################################################
9949 06:52:51.864866
9950 06:52:52.114910 02500000 ################################################################
9951 06:52:52.115043
9952 06:52:52.376250 02580000 ################################################################
9953 06:52:52.376395
9954 06:52:52.691685 02600000 ################################################################
9955 06:52:52.691851
9956 06:52:52.973588 02680000 ################################################################
9957 06:52:52.973724
9958 06:52:53.254377 02700000 ################################################################
9959 06:52:53.254525
9960 06:52:53.549981 02780000 ################################################################
9961 06:52:53.550127
9962 06:52:53.832181 02800000 ################################################################
9963 06:52:53.832320
9964 06:52:54.112312 02880000 ################################################################
9965 06:52:54.112454
9966 06:52:54.397533 02900000 ################################################################
9967 06:52:54.397669
9968 06:52:54.698350 02980000 ################################################################
9969 06:52:54.698489
9970 06:52:55.059450 02a00000 ################################################################
9971 06:52:55.059625
9972 06:52:55.397624 02a80000 ################################################################
9973 06:52:55.397764
9974 06:52:55.689907 02b00000 ################################################################
9975 06:52:55.690075
9976 06:52:55.992568 02b80000 ################################################################
9977 06:52:55.992740
9978 06:52:56.304957 02c00000 ################################################################
9979 06:52:56.305102
9980 06:52:56.636006 02c80000 ################################################################
9981 06:52:56.636156
9982 06:52:57.012762 02d00000 ################################################################
9983 06:52:57.013287
9984 06:52:57.388355 02d80000 ################################################################
9985 06:52:57.388866
9986 06:52:57.713758 02e00000 ################################################################
9987 06:52:57.713901
9988 06:52:58.088382 02e80000 ################################################################
9989 06:52:58.089004
9990 06:52:58.498346 02f00000 ################################################################
9991 06:52:58.498890
9992 06:52:58.931658 02f80000 ################################################################
9993 06:52:58.932167
9994 06:52:59.341917 03000000 ################################################################
9995 06:52:59.342094
9996 06:52:59.649578 03080000 ################################################################
9997 06:52:59.649723
9998 06:52:59.952359 03100000 ################################################################
9999 06:52:59.952524
10000 06:53:00.292646 03180000 ################################################################
10001 06:53:00.292805
10002 06:53:00.664558 03200000 ################################################################
10003 06:53:00.664739
10004 06:53:01.035812 03280000 ################################################################
10005 06:53:01.036455
10006 06:53:01.415638 03300000 ################################################################
10007 06:53:01.416109
10008 06:53:01.796405 03380000 ################################################################
10009 06:53:01.796894
10010 06:53:02.204375 03400000 ################################################################
10011 06:53:02.205037
10012 06:53:02.591067 03480000 ################################################################
10013 06:53:02.591718
10014 06:53:02.975097 03500000 ################################################################
10015 06:53:02.975613
10016 06:53:03.365183 03580000 ################################################################
10017 06:53:03.365804
10018 06:53:03.763993 03600000 ################################################################
10019 06:53:03.764523
10020 06:53:04.184833 03680000 ################################################################
10021 06:53:04.185368
10022 06:53:04.594778 03700000 ################################################################
10023 06:53:04.595363
10024 06:53:05.013183 03780000 ################################################################
10025 06:53:05.013726
10026 06:53:05.450782 03800000 ################################################################
10027 06:53:05.451322
10028 06:53:05.818674 03880000 ################################################################
10029 06:53:05.818813
10030 06:53:06.111416 03900000 ################################################################
10031 06:53:06.111573
10032 06:53:06.400050 03980000 ################################################################
10033 06:53:06.400191
10034 06:53:06.689923 03a00000 ################################################################
10035 06:53:06.690072
10036 06:53:06.993150 03a80000 ################################################################
10037 06:53:06.993295
10038 06:53:07.293344 03b00000 ################################################################
10039 06:53:07.293481
10040 06:53:07.596813 03b80000 ################################################################
10041 06:53:07.596951
10042 06:53:07.930786 03c00000 ################################################################
10043 06:53:07.931369
10044 06:53:08.361639 03c80000 ################################################################
10045 06:53:08.362272
10046 06:53:08.786476 03d00000 ################################################################
10047 06:53:08.786995
10048 06:53:09.079552 03d80000 ################################################################
10049 06:53:09.079719
10050 06:53:09.488981 03e00000 ################################################################
10051 06:53:09.489583
10052 06:53:09.872190 03e80000 ################################################################
10053 06:53:09.872334
10054 06:53:10.167769 03f00000 ################################################################
10055 06:53:10.167914
10056 06:53:10.493380 03f80000 ################################################################
10057 06:53:10.493524
10058 06:53:10.858615 04000000 ################################################################
10059 06:53:10.859234
10060 06:53:11.258237 04080000 ################################################################
10061 06:53:11.258841
10062 06:53:11.555905 04100000 ############################################## done.
10063 06:53:11.556409
10064 06:53:11.559327 The bootfile was 68531686 bytes long.
10065 06:53:11.559757
10066 06:53:11.562191 Sending tftp read request... done.
10067 06:53:11.562618
10068 06:53:11.566009 Waiting for the transfer...
10069 06:53:11.566436
10070 06:53:11.566813 00000000 # done.
10071 06:53:11.567152
10072 06:53:11.573721 Command line loaded dynamically from TFTP file: 12694836/tftp-deploy-8v56v5jm/kernel/cmdline
10073 06:53:11.574164
10074 06:53:11.586820 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10075 06:53:11.591257
10076 06:53:11.591793 Loading FIT.
10077 06:53:11.592128
10078 06:53:11.593703 Image ramdisk-1 has 56431790 bytes.
10079 06:53:11.594066
10080 06:53:11.596248 Image fdt-1 has 47278 bytes.
10081 06:53:11.596663
10082 06:53:11.599759 Image kernel-1 has 12050581 bytes.
10083 06:53:11.600278
10084 06:53:11.606305 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10085 06:53:11.606829
10086 06:53:11.625762 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10087 06:53:11.626310
10088 06:53:11.629266 Choosing best match conf-1 for compat google,spherion-rev3.
10089 06:53:11.634455
10090 06:53:11.638390 Connected to device vid:did:rid of 1ae0:0028:00
10091 06:53:11.645327
10092 06:53:11.648645 tpm_get_response: command 0x17b, return code 0x0
10093 06:53:11.649219
10094 06:53:11.651899 ec_init: CrosEC protocol v3 supported (256, 248)
10095 06:53:11.655971
10096 06:53:11.659527 tpm_cleanup: add release locality here.
10097 06:53:11.660052
10098 06:53:11.660395 Shutting down all USB controllers.
10099 06:53:11.662276
10100 06:53:11.662662 Removing current net device
10101 06:53:11.662981
10102 06:53:11.668800 Exiting depthcharge with code 4 at timestamp: 86532310
10103 06:53:11.669228
10104 06:53:11.671979 LZMA decompressing kernel-1 to 0x821a6718
10105 06:53:11.672402
10106 06:53:11.675532 LZMA decompressing kernel-1 to 0x40000000
10107 06:53:13.173698
10108 06:53:13.174264 jumping to kernel
10109 06:53:13.176475 end: 2.2.4 bootloader-commands (duration 00:01:00) [common]
10110 06:53:13.177067 start: 2.2.5 auto-login-action (timeout 00:03:26) [common]
10111 06:53:13.177484 Setting prompt string to ['Linux version [0-9]']
10112 06:53:13.177910 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10113 06:53:13.178309 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10114 06:53:13.225912
10115 06:53:13.228066 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10116 06:53:13.232145 start: 2.2.5.1 login-action (timeout 00:03:26) [common]
10117 06:53:13.232750 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10118 06:53:13.233155 Setting prompt string to []
10119 06:53:13.233584 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10120 06:53:13.234053 Using line separator: #'\n'#
10121 06:53:13.234553 No login prompt set.
10122 06:53:13.234921 Parsing kernel messages
10123 06:53:13.235265 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10124 06:53:13.235887 [login-action] Waiting for messages, (timeout 00:03:26)
10125 06:53:13.251519 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10126 06:53:13.255380 [ 0.000000] random: crng init done
10127 06:53:13.260993 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10128 06:53:13.264452 [ 0.000000] efi: UEFI not found.
10129 06:53:13.270751 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10130 06:53:13.281394 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10131 06:53:13.287561 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10132 06:53:13.300560 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10133 06:53:13.304661 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10134 06:53:13.310461 [ 0.000000] printk: bootconsole [mtk8250] enabled
10135 06:53:13.317240 [ 0.000000] NUMA: No NUMA configuration found
10136 06:53:13.324295 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10137 06:53:13.327377 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10138 06:53:13.331835 [ 0.000000] Zone ranges:
10139 06:53:13.337310 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10140 06:53:13.340812 [ 0.000000] DMA32 empty
10141 06:53:13.347229 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10142 06:53:13.350276 [ 0.000000] Movable zone start for each node
10143 06:53:13.353604 [ 0.000000] Early memory node ranges
10144 06:53:13.360160 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10145 06:53:13.366760 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10146 06:53:13.373313 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10147 06:53:13.380829 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10148 06:53:13.387040 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10149 06:53:13.393446 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10150 06:53:13.423200 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10151 06:53:13.429522 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10152 06:53:13.436336 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10153 06:53:13.438978 [ 0.000000] psci: probing for conduit method from DT.
10154 06:53:13.446145 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10155 06:53:13.449295 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10156 06:53:13.455853 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10157 06:53:13.459812 [ 0.000000] psci: SMC Calling Convention v1.2
10158 06:53:13.465812 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10159 06:53:13.470303 [ 0.000000] Detected VIPT I-cache on CPU0
10160 06:53:13.475987 [ 0.000000] CPU features: detected: GIC system register CPU interface
10161 06:53:13.482140 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10162 06:53:13.488544 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10163 06:53:13.495470 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10164 06:53:13.505236 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10165 06:53:13.512522 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10166 06:53:13.515368 [ 0.000000] alternatives: applying boot alternatives
10167 06:53:13.521507 [ 0.000000] Fallback order for Node 0: 0
10168 06:53:13.529622 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10169 06:53:13.531509 [ 0.000000] Policy zone: Normal
10170 06:53:13.545140 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10171 06:53:13.554662 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10172 06:53:13.565360 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10173 06:53:13.575067 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10174 06:53:13.582354 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10175 06:53:13.585198 <6>[ 0.000000] software IO TLB: area num 8.
10176 06:53:13.641317 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10177 06:53:13.721525 <6>[ 0.000000] Memory: 3797728K/4191232K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 360736K reserved, 32768K cma-reserved)
10178 06:53:13.727355 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10179 06:53:13.733758 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10180 06:53:13.737604 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10181 06:53:13.744310 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10182 06:53:13.750873 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10183 06:53:13.753460 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10184 06:53:13.763897 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10185 06:53:13.769912 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10186 06:53:13.777093 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10187 06:53:13.783257 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10188 06:53:13.787170 <6>[ 0.000000] GICv3: 608 SPIs implemented
10189 06:53:13.790371 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10190 06:53:13.796923 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10191 06:53:13.800549 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10192 06:53:13.806738 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10193 06:53:13.819869 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10194 06:53:13.832672 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10195 06:53:13.839288 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10196 06:53:13.847328 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10197 06:53:13.860330 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10198 06:53:13.866968 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10199 06:53:13.873372 <6>[ 0.009179] Console: colour dummy device 80x25
10200 06:53:13.883791 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10201 06:53:13.891004 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10202 06:53:13.893546 <6>[ 0.029248] LSM: Security Framework initializing
10203 06:53:13.901359 <6>[ 0.034163] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10204 06:53:13.909742 <6>[ 0.041768] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10205 06:53:13.916768 <6>[ 0.051049] cblist_init_generic: Setting adjustable number of callback queues.
10206 06:53:13.923539 <6>[ 0.058492] cblist_init_generic: Setting shift to 3 and lim to 1.
10207 06:53:13.933118 <6>[ 0.064830] cblist_init_generic: Setting adjustable number of callback queues.
10208 06:53:13.940049 <6>[ 0.072303] cblist_init_generic: Setting shift to 3 and lim to 1.
10209 06:53:13.943230 <6>[ 0.078703] rcu: Hierarchical SRCU implementation.
10210 06:53:13.951818 <6>[ 0.083749] rcu: Max phase no-delay instances is 1000.
10211 06:53:13.956425 <6>[ 0.090808] EFI services will not be available.
10212 06:53:13.959824 <6>[ 0.095760] smp: Bringing up secondary CPUs ...
10213 06:53:13.967703 <6>[ 0.100807] Detected VIPT I-cache on CPU1
10214 06:53:13.974882 <6>[ 0.100876] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10215 06:53:13.980572 <6>[ 0.100906] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10216 06:53:13.983913 <6>[ 0.101243] Detected VIPT I-cache on CPU2
10217 06:53:13.994083 <6>[ 0.101295] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10218 06:53:14.000955 <6>[ 0.101314] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10219 06:53:14.004421 <6>[ 0.101574] Detected VIPT I-cache on CPU3
10220 06:53:14.011614 <6>[ 0.101620] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10221 06:53:14.017706 <6>[ 0.101634] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10222 06:53:14.023472 <6>[ 0.101944] CPU features: detected: Spectre-v4
10223 06:53:14.028892 <6>[ 0.101951] CPU features: detected: Spectre-BHB
10224 06:53:14.030075 <6>[ 0.101955] Detected PIPT I-cache on CPU4
10225 06:53:14.037289 <6>[ 0.102011] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10226 06:53:14.046925 <6>[ 0.102027] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10227 06:53:14.050661 <6>[ 0.102316] Detected PIPT I-cache on CPU5
10228 06:53:14.056837 <6>[ 0.102376] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10229 06:53:14.063534 <6>[ 0.102393] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10230 06:53:14.066034 <6>[ 0.102673] Detected PIPT I-cache on CPU6
10231 06:53:14.076824 <6>[ 0.102733] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10232 06:53:14.082947 <6>[ 0.102750] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10233 06:53:14.085736 <6>[ 0.103049] Detected PIPT I-cache on CPU7
10234 06:53:14.092950 <6>[ 0.103107] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10235 06:53:14.099104 <6>[ 0.103123] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10236 06:53:14.102382 <6>[ 0.103169] smp: Brought up 1 node, 8 CPUs
10237 06:53:14.109612 <6>[ 0.244531] SMP: Total of 8 processors activated.
10238 06:53:14.117428 <6>[ 0.249483] CPU features: detected: 32-bit EL0 Support
10239 06:53:14.122607 <6>[ 0.254845] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10240 06:53:14.128604 <6>[ 0.263700] CPU features: detected: Common not Private translations
10241 06:53:14.136433 <6>[ 0.270176] CPU features: detected: CRC32 instructions
10242 06:53:14.142454 <6>[ 0.275527] CPU features: detected: RCpc load-acquire (LDAPR)
10243 06:53:14.145487 <6>[ 0.281487] CPU features: detected: LSE atomic instructions
10244 06:53:14.152031 <6>[ 0.287269] CPU features: detected: Privileged Access Never
10245 06:53:14.158436 <6>[ 0.293048] CPU features: detected: RAS Extension Support
10246 06:53:14.164853 <6>[ 0.298658] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10247 06:53:14.168378 <6>[ 0.305876] CPU: All CPU(s) started at EL2
10248 06:53:14.174859 <6>[ 0.310220] alternatives: applying system-wide alternatives
10249 06:53:14.184815 <6>[ 0.320133] devtmpfs: initialized
10250 06:53:14.200534 <6>[ 0.328470] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10251 06:53:14.206463 <6>[ 0.338434] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10252 06:53:14.213405 <6>[ 0.346669] pinctrl core: initialized pinctrl subsystem
10253 06:53:14.216037 <6>[ 0.353347] DMI not present or invalid.
10254 06:53:14.222718 <6>[ 0.357749] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10255 06:53:14.233727 <6>[ 0.364608] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10256 06:53:14.239253 <6>[ 0.372055] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10257 06:53:14.248767 <6>[ 0.380140] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10258 06:53:14.252437 <6>[ 0.388293] audit: initializing netlink subsys (disabled)
10259 06:53:14.262637 <5>[ 0.393986] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10260 06:53:14.268471 <6>[ 0.394682] thermal_sys: Registered thermal governor 'step_wise'
10261 06:53:14.275230 <6>[ 0.401948] thermal_sys: Registered thermal governor 'power_allocator'
10262 06:53:14.278277 <6>[ 0.408201] cpuidle: using governor menu
10263 06:53:14.284857 <6>[ 0.419162] NET: Registered PF_QIPCRTR protocol family
10264 06:53:14.291481 <6>[ 0.424634] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10265 06:53:14.298230 <6>[ 0.431737] ASID allocator initialised with 32768 entries
10266 06:53:14.301038 <6>[ 0.438278] Serial: AMBA PL011 UART driver
10267 06:53:14.311964 <4>[ 0.447037] Trying to register duplicate clock ID: 134
10268 06:53:14.364852 <6>[ 0.504110] KASLR enabled
10269 06:53:14.380282 <6>[ 0.511741] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10270 06:53:14.386231 <6>[ 0.518753] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10271 06:53:14.392633 <6>[ 0.525243] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10272 06:53:14.399141 <6>[ 0.532246] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10273 06:53:14.406177 <6>[ 0.538732] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10274 06:53:14.412119 <6>[ 0.545738] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10275 06:53:14.418657 <6>[ 0.552226] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10276 06:53:14.425849 <6>[ 0.559230] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10277 06:53:14.428456 <6>[ 0.566666] ACPI: Interpreter disabled.
10278 06:53:14.437925 <6>[ 0.573010] iommu: Default domain type: Translated
10279 06:53:14.444328 <6>[ 0.578158] iommu: DMA domain TLB invalidation policy: strict mode
10280 06:53:14.448200 <5>[ 0.584814] SCSI subsystem initialized
10281 06:53:14.453772 <6>[ 0.589042] usbcore: registered new interface driver usbfs
10282 06:53:14.460511 <6>[ 0.594775] usbcore: registered new interface driver hub
10283 06:53:14.465758 <6>[ 0.600326] usbcore: registered new device driver usb
10284 06:53:14.471150 <6>[ 0.606433] pps_core: LinuxPPS API ver. 1 registered
10285 06:53:14.480613 <6>[ 0.611624] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10286 06:53:14.484234 <6>[ 0.620968] PTP clock support registered
10287 06:53:14.487409 <6>[ 0.625207] EDAC MC: Ver: 3.0.0
10288 06:53:14.495075 <6>[ 0.630377] FPGA manager framework
10289 06:53:14.501325 <6>[ 0.634053] Advanced Linux Sound Architecture Driver Initialized.
10290 06:53:14.504598 <6>[ 0.640822] vgaarb: loaded
10291 06:53:14.511601 <6>[ 0.643958] clocksource: Switched to clocksource arch_sys_counter
10292 06:53:14.514960 <5>[ 0.650404] VFS: Disk quotas dquot_6.6.0
10293 06:53:14.521087 <6>[ 0.654589] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10294 06:53:14.524972 <6>[ 0.661783] pnp: PnP ACPI: disabled
10295 06:53:14.533338 <6>[ 0.668465] NET: Registered PF_INET protocol family
10296 06:53:14.539275 <6>[ 0.673848] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10297 06:53:14.552370 <6>[ 0.683860] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10298 06:53:14.561452 <6>[ 0.692640] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10299 06:53:14.567857 <6>[ 0.700612] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10300 06:53:14.576830 <6>[ 0.709010] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10301 06:53:14.585288 <6>[ 0.717668] TCP: Hash tables configured (established 32768 bind 32768)
10302 06:53:14.592619 <6>[ 0.724526] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10303 06:53:14.598636 <6>[ 0.731548] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10304 06:53:14.605519 <6>[ 0.739068] NET: Registered PF_UNIX/PF_LOCAL protocol family
10305 06:53:14.611803 <6>[ 0.745210] RPC: Registered named UNIX socket transport module.
10306 06:53:14.615917 <6>[ 0.751366] RPC: Registered udp transport module.
10307 06:53:14.621656 <6>[ 0.756295] RPC: Registered tcp transport module.
10308 06:53:14.629307 <6>[ 0.761225] RPC: Registered tcp NFSv4.1 backchannel transport module.
10309 06:53:14.631455 <6>[ 0.767893] PCI: CLS 0 bytes, default 64
10310 06:53:14.634914 <6>[ 0.772258] Unpacking initramfs...
10311 06:53:14.644965 <6>[ 0.775962] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10312 06:53:14.650867 <6>[ 0.784589] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10313 06:53:14.657599 <6>[ 0.793370] kvm [1]: IPA Size Limit: 40 bits
10314 06:53:14.661484 <6>[ 0.797895] kvm [1]: GICv3: no GICV resource entry
10315 06:53:14.668568 <6>[ 0.802915] kvm [1]: disabling GICv2 emulation
10316 06:53:14.674285 <6>[ 0.807604] kvm [1]: GIC system register CPU interface enabled
10317 06:53:14.677379 <6>[ 0.813759] kvm [1]: vgic interrupt IRQ18
10318 06:53:14.685585 <6>[ 0.818120] kvm [1]: VHE mode initialized successfully
10319 06:53:14.687974 <5>[ 0.824350] Initialise system trusted keyrings
10320 06:53:14.694217 <6>[ 0.829183] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10321 06:53:14.703756 <6>[ 0.839271] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10322 06:53:14.710312 <5>[ 0.845673] NFS: Registering the id_resolver key type
10323 06:53:14.713379 <5>[ 0.850975] Key type id_resolver registered
10324 06:53:14.720281 <5>[ 0.855390] Key type id_legacy registered
10325 06:53:14.727534 <6>[ 0.859672] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10326 06:53:14.733479 <6>[ 0.866598] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10327 06:53:14.741164 <6>[ 0.874297] 9p: Installing v9fs 9p2000 file system support
10328 06:53:14.776841 <5>[ 0.911888] Key type asymmetric registered
10329 06:53:14.779952 <5>[ 0.916220] Asymmetric key parser 'x509' registered
10330 06:53:14.789802 <6>[ 0.921361] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10331 06:53:14.792834 <6>[ 0.928977] io scheduler mq-deadline registered
10332 06:53:14.796272 <6>[ 0.933741] io scheduler kyber registered
10333 06:53:14.815658 <6>[ 0.950787] EINJ: ACPI disabled.
10334 06:53:14.846427 <4>[ 0.975505] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10335 06:53:14.857186 <4>[ 0.986124] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10336 06:53:14.870967 <6>[ 1.006654] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10337 06:53:14.878598 <6>[ 1.014609] printk: console [ttyS0] disabled
10338 06:53:14.907627 <6>[ 1.039233] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10339 06:53:14.913452 <6>[ 1.048699] printk: console [ttyS0] enabled
10340 06:53:14.917180 <6>[ 1.048699] printk: console [ttyS0] enabled
10341 06:53:14.923613 <6>[ 1.057595] printk: bootconsole [mtk8250] disabled
10342 06:53:14.927003 <6>[ 1.057595] printk: bootconsole [mtk8250] disabled
10343 06:53:14.933989 <6>[ 1.068671] SuperH (H)SCI(F) driver initialized
10344 06:53:14.936739 <6>[ 1.073945] msm_serial: driver initialized
10345 06:53:14.950986 <6>[ 1.082890] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10346 06:53:14.960635 <6>[ 1.091443] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10347 06:53:14.967851 <6>[ 1.099986] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10348 06:53:14.976878 <6>[ 1.108614] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10349 06:53:14.986894 <6>[ 1.117321] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10350 06:53:14.993665 <6>[ 1.126034] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10351 06:53:15.003779 <6>[ 1.134573] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10352 06:53:15.010797 <6>[ 1.143380] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10353 06:53:15.019776 <6>[ 1.151923] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10354 06:53:15.031917 <6>[ 1.167428] loop: module loaded
10355 06:53:15.038264 <6>[ 1.173367] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10356 06:53:15.061451 <4>[ 1.196403] mtk-pmic-keys: Failed to locate of_node [id: -1]
10357 06:53:15.067385 <6>[ 1.203130] megasas: 07.719.03.00-rc1
10358 06:53:15.077492 <6>[ 1.212730] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10359 06:53:15.083983 <6>[ 1.219313] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10360 06:53:15.100246 <6>[ 1.235703] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10361 06:53:15.156321 <6>[ 1.284659] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10362 06:53:17.046072 <6>[ 3.181533] Freeing initrd memory: 55108K
10363 06:53:17.055710 <6>[ 3.191652] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10364 06:53:17.067297 <6>[ 3.202760] tun: Universal TUN/TAP device driver, 1.6
10365 06:53:17.070508 <6>[ 3.208840] thunder_xcv, ver 1.0
10366 06:53:17.072897 <6>[ 3.212347] thunder_bgx, ver 1.0
10367 06:53:17.076628 <6>[ 3.215837] nicpf, ver 1.0
10368 06:53:17.087057 <6>[ 3.219870] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10369 06:53:17.090345 <6>[ 3.227346] hns3: Copyright (c) 2017 Huawei Corporation.
10370 06:53:17.097026 <6>[ 3.232934] hclge is initializing
10371 06:53:17.101009 <6>[ 3.236520] e1000: Intel(R) PRO/1000 Network Driver
10372 06:53:17.107602 <6>[ 3.241649] e1000: Copyright (c) 1999-2006 Intel Corporation.
10373 06:53:17.110413 <6>[ 3.247663] e1000e: Intel(R) PRO/1000 Network Driver
10374 06:53:17.117241 <6>[ 3.252878] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10375 06:53:17.123749 <6>[ 3.259066] igb: Intel(R) Gigabit Ethernet Network Driver
10376 06:53:17.130552 <6>[ 3.264716] igb: Copyright (c) 2007-2014 Intel Corporation.
10377 06:53:17.137257 <6>[ 3.270551] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10378 06:53:17.143219 <6>[ 3.277069] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10379 06:53:17.147314 <6>[ 3.283527] sky2: driver version 1.30
10380 06:53:17.153141 <6>[ 3.288517] VFIO - User Level meta-driver version: 0.3
10381 06:53:17.161510 <6>[ 3.296774] usbcore: registered new interface driver usb-storage
10382 06:53:17.167411 <6>[ 3.303218] usbcore: registered new device driver onboard-usb-hub
10383 06:53:17.177214 <6>[ 3.312382] mt6397-rtc mt6359-rtc: registered as rtc0
10384 06:53:17.186462 <6>[ 3.317852] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:53:17 UTC (1706943197)
10385 06:53:17.189909 <6>[ 3.327414] i2c_dev: i2c /dev entries driver
10386 06:53:17.206556 <6>[ 3.339225] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10387 06:53:17.226322 <6>[ 3.362204] cpu cpu0: EM: created perf domain
10388 06:53:17.230040 <6>[ 3.367108] cpu cpu4: EM: created perf domain
10389 06:53:17.236648 <6>[ 3.372661] sdhci: Secure Digital Host Controller Interface driver
10390 06:53:17.243745 <6>[ 3.379090] sdhci: Copyright(c) Pierre Ossman
10391 06:53:17.250213 <6>[ 3.383996] Synopsys Designware Multimedia Card Interface Driver
10392 06:53:17.257720 <6>[ 3.390621] sdhci-pltfm: SDHCI platform and OF driver helper
10393 06:53:17.260927 <6>[ 3.390777] mmc0: CQHCI version 5.10
10394 06:53:17.266806 <6>[ 3.400630] ledtrig-cpu: registered to indicate activity on CPUs
10395 06:53:17.273753 <6>[ 3.407588] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10396 06:53:17.279955 <6>[ 3.414622] usbcore: registered new interface driver usbhid
10397 06:53:17.283811 <6>[ 3.420444] usbhid: USB HID core driver
10398 06:53:17.289805 <6>[ 3.424634] spi_master spi0: will run message pump with realtime priority
10399 06:53:17.335017 <6>[ 3.460602] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10400 06:53:17.349892 <6>[ 3.475759] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10401 06:53:17.356627 <6>[ 3.490836] cros-ec-spi spi0.0: Chrome EC device registered
10402 06:53:17.360447 <6>[ 3.496859] mmc0: Command Queue Engine enabled
10403 06:53:17.367400 <6>[ 3.501607] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10404 06:53:17.374182 <6>[ 3.509113] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10405 06:53:17.381559 <6>[ 3.517789] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10406 06:53:17.389282 <6>[ 3.524967] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10407 06:53:17.396788 <6>[ 3.530894] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10408 06:53:17.406353 <6>[ 3.534671] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10409 06:53:17.412877 <6>[ 3.536796] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10410 06:53:17.415753 <6>[ 3.546363] NET: Registered PF_PACKET protocol family
10411 06:53:17.422262 <6>[ 3.557338] 9pnet: Installing 9P2000 support
10412 06:53:17.425368 <5>[ 3.561901] Key type dns_resolver registered
10413 06:53:17.431882 <6>[ 3.566855] registered taskstats version 1
10414 06:53:17.435046 <5>[ 3.571232] Loading compiled-in X.509 certificates
10415 06:53:17.462323 <4>[ 3.591325] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10416 06:53:17.471698 <4>[ 3.602032] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10417 06:53:17.478568 <3>[ 3.612611] debugfs: File 'uA_load' in directory '/' already present!
10418 06:53:17.484798 <3>[ 3.619314] debugfs: File 'min_uV' in directory '/' already present!
10419 06:53:17.492370 <3>[ 3.625924] debugfs: File 'max_uV' in directory '/' already present!
10420 06:53:17.499298 <3>[ 3.632531] debugfs: File 'constraint_flags' in directory '/' already present!
10421 06:53:17.509902 <3>[ 3.641873] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10422 06:53:17.520779 <6>[ 3.656306] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10423 06:53:17.527298 <6>[ 3.663071] xhci-mtk 11200000.usb: xHCI Host Controller
10424 06:53:17.535029 <6>[ 3.668563] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10425 06:53:17.543804 <6>[ 3.676396] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10426 06:53:17.550416 <6>[ 3.685828] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10427 06:53:17.557677 <6>[ 3.691894] xhci-mtk 11200000.usb: xHCI Host Controller
10428 06:53:17.563597 <6>[ 3.697370] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10429 06:53:17.570194 <6>[ 3.705016] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10430 06:53:17.576902 <6>[ 3.712686] hub 1-0:1.0: USB hub found
10431 06:53:17.580200 <6>[ 3.716696] hub 1-0:1.0: 1 port detected
10432 06:53:17.589743 <6>[ 3.720946] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10433 06:53:17.592881 <6>[ 3.729490] hub 2-0:1.0: USB hub found
10434 06:53:17.597184 <6>[ 3.733496] hub 2-0:1.0: 1 port detected
10435 06:53:17.603963 <6>[ 3.739636] mtk-msdc 11f70000.mmc: Got CD GPIO
10436 06:53:17.615780 <6>[ 3.747986] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10437 06:53:17.622220 <6>[ 3.756006] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10438 06:53:17.632512 <4>[ 3.763915] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10439 06:53:17.641639 <6>[ 3.773434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10440 06:53:17.648972 <6>[ 3.781510] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10441 06:53:17.658367 <6>[ 3.789645] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10442 06:53:17.665051 <6>[ 3.797573] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10443 06:53:17.671630 <6>[ 3.805447] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10444 06:53:17.681756 <6>[ 3.813273] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10445 06:53:17.690990 <6>[ 3.823647] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10446 06:53:17.698141 <6>[ 3.832009] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10447 06:53:17.707956 <6>[ 3.840370] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10448 06:53:17.717646 <6>[ 3.848710] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10449 06:53:17.724191 <6>[ 3.857058] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10450 06:53:17.734491 <6>[ 3.865397] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10451 06:53:17.741193 <6>[ 3.873744] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10452 06:53:17.750493 <6>[ 3.882082] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10453 06:53:17.758334 <6>[ 3.890429] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10454 06:53:17.767351 <6>[ 3.898777] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10455 06:53:17.773820 <6>[ 3.907125] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10456 06:53:17.783988 <6>[ 3.915464] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10457 06:53:17.790068 <6>[ 3.923803] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10458 06:53:17.800622 <6>[ 3.932140] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10459 06:53:17.807075 <6>[ 3.940477] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10460 06:53:17.813477 <6>[ 3.949255] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10461 06:53:17.820954 <6>[ 3.956447] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10462 06:53:17.827153 <6>[ 3.963192] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10463 06:53:17.835047 <6>[ 3.969914] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10464 06:53:17.844533 <6>[ 3.976820] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10465 06:53:17.851002 <6>[ 3.983682] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10466 06:53:17.860580 <6>[ 3.992812] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10467 06:53:17.871031 <6>[ 4.001931] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10468 06:53:17.880357 <6>[ 4.011223] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10469 06:53:17.891598 <6>[ 4.020714] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10470 06:53:17.897109 <6>[ 4.030189] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10471 06:53:17.907037 <6>[ 4.039307] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10472 06:53:17.916941 <6>[ 4.048771] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10473 06:53:17.927011 <6>[ 4.057888] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10474 06:53:17.936686 <6>[ 4.067180] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10475 06:53:17.946812 <6>[ 4.077340] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10476 06:53:17.956691 <6>[ 4.089236] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10477 06:53:17.987279 <6>[ 4.120286] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10478 06:53:18.015677 <6>[ 4.151762] hub 2-1:1.0: USB hub found
10479 06:53:18.019553 <6>[ 4.156251] hub 2-1:1.0: 3 ports detected
10480 06:53:18.027629 <6>[ 4.163712] hub 2-1:1.0: USB hub found
10481 06:53:18.031126 <6>[ 4.168153] hub 2-1:1.0: 3 ports detected
10482 06:53:18.139671 <6>[ 4.272164] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10483 06:53:18.294976 <6>[ 4.430301] hub 1-1:1.0: USB hub found
10484 06:53:18.297209 <6>[ 4.434787] hub 1-1:1.0: 4 ports detected
10485 06:53:18.307548 <6>[ 4.443279] hub 1-1:1.0: USB hub found
10486 06:53:18.311019 <6>[ 4.447639] hub 1-1:1.0: 4 ports detected
10487 06:53:18.372019 <6>[ 4.504551] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10488 06:53:18.631422 <6>[ 4.764270] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10489 06:53:18.764651 <6>[ 4.900159] hub 1-1.4:1.0: USB hub found
10490 06:53:18.768254 <6>[ 4.904825] hub 1-1.4:1.0: 2 ports detected
10491 06:53:18.776142 <6>[ 4.911932] hub 1-1.4:1.0: USB hub found
10492 06:53:18.779393 <6>[ 4.916447] hub 1-1.4:1.0: 2 ports detected
10493 06:53:19.075055 <6>[ 5.208247] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10494 06:53:19.268541 <6>[ 5.400245] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10495 06:53:30.232672 <6>[ 16.373232] ALSA device list:
10496 06:53:30.239098 <6>[ 16.376526] No soundcards found.
10497 06:53:30.247529 <6>[ 16.384389] Freeing unused kernel memory: 8448K
10498 06:53:30.250552 <6>[ 16.389364] Run /init as init process
10499 06:53:30.299642 <6>[ 16.436734] NET: Registered PF_INET6 protocol family
10500 06:53:30.307411 <6>[ 16.443329] Segment Routing with IPv6
10501 06:53:30.309058 <6>[ 16.447278] In-situ OAM (IOAM) with IPv6
10502 06:53:30.343691 <30>[ 16.461401] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10503 06:53:30.347087 <30>[ 16.485374] systemd[1]: Detected architecture arm64.
10504 06:53:30.350641
10505 06:53:30.354172 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10506 06:53:30.354742
10507 06:53:30.367107 <30>[ 16.504286] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10508 06:53:30.544477 <30>[ 16.678722] systemd[1]: Queued start job for default target Graphical Interface.
10509 06:53:30.591691 <30>[ 16.728803] systemd[1]: Created slice system-getty.slice.
10510 06:53:30.598197 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10511 06:53:30.615902 <30>[ 16.752779] systemd[1]: Created slice system-modprobe.slice.
10512 06:53:30.622664 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10513 06:53:30.639801 <30>[ 16.776924] systemd[1]: Created slice system-serial\x2dgetty.slice.
10514 06:53:30.649636 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10515 06:53:30.664434 <30>[ 16.801583] systemd[1]: Created slice User and Session Slice.
10516 06:53:30.671219 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10517 06:53:30.690767 <30>[ 16.824979] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10518 06:53:30.700320 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10519 06:53:30.718878 <30>[ 16.853043] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10520 06:53:30.726139 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10521 06:53:30.749642 <30>[ 16.880757] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10522 06:53:30.756371 <30>[ 16.893013] systemd[1]: Reached target Local Encrypted Volumes.
10523 06:53:30.762687 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10524 06:53:30.779170 <30>[ 16.916791] systemd[1]: Reached target Paths.
10525 06:53:30.782567 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10526 06:53:30.802762 <30>[ 16.940234] systemd[1]: Reached target Remote File Systems.
10527 06:53:30.809592 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10528 06:53:30.822763 <30>[ 16.960290] systemd[1]: Reached target Slices.
10529 06:53:30.827057 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10530 06:53:30.843430 <30>[ 16.980251] systemd[1]: Reached target Swap.
10531 06:53:30.846684 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10532 06:53:30.866929 <30>[ 17.000704] systemd[1]: Listening on initctl Compatibility Named Pipe.
10533 06:53:30.874516 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10534 06:53:30.889437 <30>[ 17.025671] systemd[1]: Listening on Journal Audit Socket.
10535 06:53:30.894695 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10536 06:53:30.911776 <30>[ 17.049372] systemd[1]: Listening on Journal Socket (/dev/log).
10537 06:53:30.918615 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10538 06:53:30.936147 <30>[ 17.073439] systemd[1]: Listening on Journal Socket.
10539 06:53:30.942847 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10540 06:53:30.955513 <30>[ 17.092809] systemd[1]: Listening on udev Control Socket.
10541 06:53:30.961908 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10542 06:53:30.980114 <30>[ 17.117294] systemd[1]: Listening on udev Kernel Socket.
10543 06:53:30.986054 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10544 06:53:31.039111 <30>[ 17.176484] systemd[1]: Mounting Huge Pages File System...
10545 06:53:31.046644 Mounting [0;1;39mHuge Pages File System[0m...
10546 06:53:31.060571 <30>[ 17.197790] systemd[1]: Mounting POSIX Message Queue File System...
10547 06:53:31.067976 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10548 06:53:31.084528 <30>[ 17.221821] systemd[1]: Mounting Kernel Debug File System...
10549 06:53:31.090634 Mounting [0;1;39mKernel Debug File System[0m...
10550 06:53:31.109746 <30>[ 17.244394] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10551 06:53:31.121382 <30>[ 17.255304] systemd[1]: Starting Create list of static device nodes for the current kernel...
10552 06:53:31.128231 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10553 06:53:31.171573 <30>[ 17.308976] systemd[1]: Starting Load Kernel Module configfs...
10554 06:53:31.178150 Starting [0;1;39mLoad Kernel Module configfs[0m...
10555 06:53:31.194560 <30>[ 17.332150] systemd[1]: Starting Load Kernel Module drm...
10556 06:53:31.201014 Starting [0;1;39mLoad Kernel Module drm[0m...
10557 06:53:31.219090 <30>[ 17.352733] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10558 06:53:31.271580 <30>[ 17.409099] systemd[1]: Starting Journal Service...
10559 06:53:31.274809 Starting [0;1;39mJournal Service[0m...
10560 06:53:31.295912 <30>[ 17.433239] systemd[1]: Starting Load Kernel Modules...
10561 06:53:31.302828 Starting [0;1;39mLoad Kernel Modules[0m...
10562 06:53:31.323142 <30>[ 17.456859] systemd[1]: Starting Remount Root and Kernel File Systems...
10563 06:53:31.329439 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10564 06:53:31.359624 <30>[ 17.496741] systemd[1]: Starting Coldplug All udev Devices...
10565 06:53:31.366618 Starting [0;1;39mColdplug All udev Devices[0m...
10566 06:53:31.382849 <30>[ 17.520188] systemd[1]: Started Journal Service.
10567 06:53:31.388933 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10568 06:53:31.404821 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10569 06:53:31.427869 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10570 06:53:31.443216 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10571 06:53:31.468030 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10572 06:53:31.484671 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10573 06:53:31.504908 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10574 06:53:31.520307 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10575 06:53:31.541141 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10576 06:53:31.554890 See 'systemctl status systemd-remount-fs.service' for details.
10577 06:53:31.607020 Mounting [0;1;39mKernel Configuration File System[0m...
10578 06:53:31.625964 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10579 06:53:31.639738 <46>[ 17.773725] systemd-journald[177]: Received client request to flush runtime journal.
10580 06:53:31.650008 Starting [0;1;39mLoad/Save Random Seed[0m...
10581 06:53:31.668782 Starting [0;1;39mApply Kernel Variables[0m...
10582 06:53:31.688314 Starting [0;1;39mCreate System Users[0m...
10583 06:53:31.709465 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10584 06:53:31.724331 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10585 06:53:31.743831 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10586 06:53:31.756632 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10587 06:53:31.772640 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10588 06:53:31.787681 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10589 06:53:31.835497 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10590 06:53:31.857160 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10591 06:53:31.871645 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10592 06:53:31.886752 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10593 06:53:31.919729 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10594 06:53:31.949442 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10595 06:53:31.971132 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10596 06:53:31.991184 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10597 06:53:32.057817 Starting [0;1;39mNetwork Time Synchronization[0m...
10598 06:53:32.083406 <6>[ 18.217839] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10599 06:53:32.090125 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10600 06:53:32.093657 <6>[ 18.231745] remoteproc remoteproc0: scp is available
10601 06:53:32.101942 <6>[ 18.238302] remoteproc remoteproc0: powering up scp
10602 06:53:32.110729 <6>[ 18.243579] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10603 06:53:32.117100 <6>[ 18.254127] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10604 06:53:32.123782 <3>[ 18.258721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10605 06:53:32.133939 <6>[ 18.263528] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10606 06:53:32.140587 <3>[ 18.269229] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10607 06:53:32.150389 <6>[ 18.275677] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10608 06:53:32.156850 <3>[ 18.284133] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10609 06:53:32.166743 <6>[ 18.293106] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10610 06:53:32.173624 <3>[ 18.300879] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10611 06:53:32.179517 <6>[ 18.301461] usbcore: registered new device driver r8152-cfgselector
10612 06:53:32.190232 <6>[ 18.313144] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10613 06:53:32.196480 <3>[ 18.317284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10614 06:53:32.203649 <4>[ 18.320955] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10615 06:53:32.212484 <4>[ 18.324515] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10616 06:53:32.219599 <3>[ 18.331446] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10617 06:53:32.226399 <3>[ 18.331452] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10618 06:53:32.236892 <3>[ 18.331455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10619 06:53:32.243036 <3>[ 18.336608] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10620 06:53:32.253499 <4>[ 18.342145] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10621 06:53:32.256394 <4>[ 18.342145] Fallback method does not support PEC.
10622 06:53:32.266810 <3>[ 18.349729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10623 06:53:32.272964 <3>[ 18.370581] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10624 06:53:32.283768 <3>[ 18.378422] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10625 06:53:32.290327 <3>[ 18.378432] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10626 06:53:32.293956 <6>[ 18.384193] mc: Linux media interface: v0.10
10627 06:53:32.303658 <6>[ 18.386193] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10628 06:53:32.310141 <6>[ 18.386551] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10629 06:53:32.320020 <3>[ 18.404521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10630 06:53:32.326241 <6>[ 18.408675] remoteproc remoteproc0: remote processor scp is now up
10631 06:53:32.333641 <3>[ 18.417364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10632 06:53:32.343487 <3>[ 18.429815] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10633 06:53:32.349676 <3>[ 18.433779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10634 06:53:32.356890 <6>[ 18.433821] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10635 06:53:32.363138 <6>[ 18.433832] pci_bus 0000:00: root bus resource [bus 00-ff]
10636 06:53:32.369560 <6>[ 18.433843] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10637 06:53:32.379445 <6>[ 18.433849] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10638 06:53:32.386673 <6>[ 18.433900] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10639 06:53:32.393167 <6>[ 18.433929] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10640 06:53:32.400151 <6>[ 18.434014] pci 0000:00:00.0: supports D1 D2
10641 06:53:32.406142 <6>[ 18.434017] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10642 06:53:32.413783 <6>[ 18.435686] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10643 06:53:32.420974 <6>[ 18.435856] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10644 06:53:32.429494 <6>[ 18.435889] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10645 06:53:32.436450 <6>[ 18.435910] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10646 06:53:32.442719 <6>[ 18.435929] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10647 06:53:32.447456 <6>[ 18.436071] pci 0000:01:00.0: supports D1 D2
10648 06:53:32.452797 <6>[ 18.436075] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10649 06:53:32.463645 <3>[ 18.438664] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10650 06:53:32.468798 <6>[ 18.438748] videodev: Linux video capture interface: v2.00
10651 06:53:32.475515 <3>[ 18.445213] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10652 06:53:32.482294 <6>[ 18.448166] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10653 06:53:32.492879 <6>[ 18.448236] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10654 06:53:32.499008 <6>[ 18.448251] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10655 06:53:32.509367 <6>[ 18.448273] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10656 06:53:32.516034 <6>[ 18.448289] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10657 06:53:32.522362 <6>[ 18.448305] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10658 06:53:32.528887 <6>[ 18.448324] pci 0000:00:00.0: PCI bridge to [bus 01]
10659 06:53:32.536697 <6>[ 18.448333] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10660 06:53:32.542620 <6>[ 18.448648] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10661 06:53:32.553898 <6>[ 18.452609] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10662 06:53:32.558415 <6>[ 18.454475] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10663 06:53:32.565773 <3>[ 18.462057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10664 06:53:32.576913 <6>[ 18.469965] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10665 06:53:32.580005 <6>[ 18.471408] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10666 06:53:32.590488 <3>[ 18.476494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10667 06:53:32.599943 <6>[ 18.578068] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10668 06:53:32.606746 <6>[ 18.586833] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10669 06:53:32.617126 <6>[ 18.590910] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10670 06:53:32.627273 <4>[ 18.616064] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10671 06:53:32.634174 <3>[ 18.635537] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10672 06:53:32.643721 <4>[ 18.642301] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10673 06:53:32.647183 <6>[ 18.651675] Bluetooth: Core ver 2.22
10674 06:53:32.655593 <6>[ 18.658663] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10675 06:53:32.660978 <6>[ 18.667175] NET: Registered PF_BLUETOOTH protocol family
10676 06:53:32.667786 <6>[ 18.672554] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10677 06:53:32.674437 <6>[ 18.679801] Bluetooth: HCI device and connection manager initialized
10678 06:53:32.677403 <6>[ 18.679827] Bluetooth: HCI socket layer initialized
10679 06:53:32.691935 <6>[ 18.687570] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10680 06:53:32.698110 <6>[ 18.695470] Bluetooth: L2CAP socket layer initialized
10681 06:53:32.701114 <6>[ 18.695489] Bluetooth: SCO socket layer initialized
10682 06:53:32.713799 <5>[ 18.697578] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10683 06:53:32.715330 <6>[ 18.701873] usbcore: registered new interface driver uvcvideo
10684 06:53:32.721477 <5>[ 18.707431] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10685 06:53:32.732155 <5>[ 18.707644] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10686 06:53:32.738899 <4>[ 18.707706] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10687 06:53:32.745229 <6>[ 18.707711] cfg80211: failed to load regulatory.db
10688 06:53:32.753613 <6>[ 18.712840] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10689 06:53:32.759790 <3>[ 18.719215] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10690 06:53:32.766952 <6>[ 18.742702] r8152 2-1.3:1.0 eth0: v1.12.13
10691 06:53:32.773425 <3>[ 18.768371] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10692 06:53:32.780084 <6>[ 18.768841] usbcore: registered new interface driver r8152
10693 06:53:32.787278 <6>[ 18.769876] usbcore: registered new interface driver btusb
10694 06:53:32.798047 <4>[ 18.778200] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10695 06:53:32.804875 <3>[ 18.778249] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10696 06:53:32.810510 <6>[ 18.788357] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10697 06:53:32.817545 <3>[ 18.789415] Bluetooth: hci0: Failed to load firmware file (-2)
10698 06:53:32.823849 <6>[ 18.797778] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10699 06:53:32.830680 <3>[ 18.803236] Bluetooth: hci0: Failed to set up firmware (-2)
10700 06:53:32.839809 <4>[ 18.803240] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10701 06:53:32.846607 <6>[ 18.803466] usbcore: registered new interface driver cdc_ether
10702 06:53:32.856679 <3>[ 18.807408] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10703 06:53:32.861333 <6>[ 18.816987] usbcore: registered new interface driver r8153_ecm
10704 06:53:32.866697 <6>[ 18.830658] mt7921e 0000:01:00.0: ASIC revision: 79610010
10705 06:53:32.877378 <3>[ 18.830732] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10706 06:53:32.884399 <6>[ 18.847253] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10707 06:53:32.889765 <3>[ 18.851073] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10708 06:53:32.899376 <6>[ 18.947329] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10709 06:53:32.899956 <6>[ 18.947329]
10710 06:53:32.905943 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10711 06:53:32.923192 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10712 06:53:32.960195 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10713 06:53:33.117686 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10714 06:53:33.130217 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10715 06:53:33.146881 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10716 06:53:33.170130 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 19.304076] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10717 06:53:33.172196 em Time Synchronized[0m.
10718 06:53:33.189947 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10719 06:53:33.234923 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10720 06:53:33.256301 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10721 06:53:33.271429 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10722 06:53:33.291738 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10723 06:53:33.305726 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10724 06:53:33.318783 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10725 06:53:33.339461 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10726 06:53:33.351405 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10727 06:53:33.366971 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10728 06:53:33.418897 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10729 06:53:33.451525 Starting [0;1;39mUser Login Management[0m...
10730 06:53:33.471459 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10731 06:53:33.495639 Starting [0;1;39mPermit User Sessions[0m...
10732 06:53:33.512577 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10733 06:53:33.529004 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10734 06:53:33.551204 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10735 06:53:33.570991 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10736 06:53:33.586936 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10737 06:53:33.603807 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10738 06:53:33.620568 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10739 06:53:33.639498 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10740 06:53:33.695486 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10741 06:53:33.723305 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10742 06:53:33.766772
10743 06:53:33.767331
10744 06:53:33.769859 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10745 06:53:33.770321
10746 06:53:33.773166 debian-bullseye-arm64 login: root (automatic login)
10747 06:53:33.773733
10748 06:53:33.774101
10749 06:53:33.788766 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
10750 06:53:33.789337
10751 06:53:33.794628 The programs included with the Debian GNU/Linux system are free software;
10752 06:53:33.801059 the exact distribution terms for each program are described in the
10753 06:53:33.805093 individual files in /usr/share/doc/*/copyright.
10754 06:53:33.805656
10755 06:53:33.811740 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10756 06:53:33.816399 permitted by applicable law.
10757 06:53:33.817955 Matched prompt #10: / #
10759 06:53:33.819068 Setting prompt string to ['/ #']
10760 06:53:33.819536 end: 2.2.5.1 login-action (duration 00:00:21) [common]
10762 06:53:33.820891 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10763 06:53:33.821390 start: 2.2.6 expect-shell-connection (timeout 00:03:06) [common]
10764 06:53:33.821788 Setting prompt string to ['/ #']
10765 06:53:33.822138 Forcing a shell prompt, looking for ['/ #']
10767 06:53:33.873006 / #
10768 06:53:33.873654 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10769 06:53:33.874224 Waiting using forced prompt support (timeout 00:02:30)
10770 06:53:33.879880
10771 06:53:33.880866 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10772 06:53:33.881396 start: 2.2.7 export-device-env (timeout 00:03:06) [common]
10773 06:53:33.881896 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10774 06:53:33.882353 end: 2.2 depthcharge-retry (duration 00:01:54) [common]
10775 06:53:33.882815 end: 2 depthcharge-action (duration 00:01:54) [common]
10776 06:53:33.883309 start: 3 lava-test-retry (timeout 00:07:43) [common]
10777 06:53:33.883763 start: 3.1 lava-test-shell (timeout 00:07:43) [common]
10778 06:53:33.884204 Using namespace: common
10780 06:53:33.985520 / # #
10781 06:53:33.986174 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10782 06:53:33.992395 #
10783 06:53:33.993353 Using /lava-12694836
10785 06:53:34.094622 / # export SHELL=/bin/sh
10786 06:53:34.095592 <6>[ 20.155883] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10787 06:53:34.101567 export SHELL=/bin/sh
10789 06:53:34.203405 / # . /lava-12694836/environment
10790 06:53:34.210290 . /lava-12694836/environment
10792 06:53:34.312055 / # /lava-12694836/bin/lava-test-runner /lava-12694836/0
10793 06:53:34.312700 Test shell timeout: 10s (minimum of the action and connection timeout)
10794 06:53:34.319250 /lava-12694836/bin/lava-test-runner /lava-12694836/0
10795 06:53:34.344234 + export TESTRUN_ID=0_igt-gpu-panf<8>[ 20.480612] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12694836_1.5.2.3.1>
10796 06:53:34.345131 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12694836_1.5.2.3.1
10797 06:53:34.345563 Starting test lava.0_igt-gpu-panfrost (12694836_1.5.2.3.1)
10798 06:53:34.346024 Skipping test definition patterns.
10799 06:53:34.347076 rost
10800 06:53:34.350253 + cd /lava-12694836/0/tests/0_igt-gpu-panfrost
10801 06:53:34.350834 + cat uuid
10802 06:53:34.353505 + UUID=12694836_1.5.2.3.1
10803 06:53:34.353972 + set +x
10804 06:53:34.363576 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
10805 06:53:34.377783 <8>[ 20.515094] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
10806 06:53:34.378712 Received signal: <TESTSET> START panfrost_gem_new
10807 06:53:34.379236 Starting test_set panfrost_gem_new
10808 06:53:34.393957 <14>[ 20.531908] [IGT] panfrost_gem_new: executing
10809 06:53:34.401069 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.538632] [IGT] panfrost_gem_new: exiting, ret=77
10810 06:53:34.405017 rch64) (Linux: 6.1.75-cip14 aarch64)
10811 06:53:34.416771 Test requirement not met in function drm_o<8>[ 20.551038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
10812 06:53:34.417598 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10814 06:53:34.420776 pen_driver, file ../lib/drmtest.c:621:
10815 06:53:34.421342 Test requirement: !(fd<0)
10816 06:53:34.427274 No known gpu found for chipset flags 0x32 (panfrost)
10817 06:53:34.430990 Last errno: 2, No such file or directory
10818 06:53:34.433478 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
10819 06:53:34.443220 <14>[ 20.581138] [IGT] panfrost_gem_new: executing
10820 06:53:34.453385 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.589039] [IGT] panfrost_gem_new: exiting, ret=77
10821 06:53:34.453940 .1.75-cip14 aarch64)
10822 06:53:34.466913 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 20.602933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
10823 06:53:34.467774 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10825 06:53:34.469556 c:621:
10826 06:53:34.470017 Test requirement: !(fd<0)
10827 06:53:34.476764 No known gpu found for chipset flags 0x32 (panfrost)
10828 06:53:34.479688 Last errno: 2, No such file or directory
10829 06:53:34.486875 [1mSubtest g<14>[ 20.622273] [IGT] panfrost_gem_new: executing
10830 06:53:34.487519 em-new-0: SKIP (0.000s)[0m
10831 06:53:34.493295 IGT<14>[ 20.629626] [IGT] panfrost_gem_new: exiting, ret=77
10832 06:53:34.499480 -Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
10833 06:53:34.505755 Test requirem<8>[ 20.642275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
10834 06:53:34.506589 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
10836 06:53:34.512853 ent not met in function drm_open<8>[ 20.652087] <LAVA_SIGNAL_TESTSET STOP>
10837 06:53:34.513760 Received signal: <TESTSET> STOP
10838 06:53:34.514177 Closing test_set panfrost_gem_new
10839 06:53:34.515620 _driver, file ../lib/drmtest.c:621:
10840 06:53:34.519149 Test requirement: !(fd<0)
10841 06:53:34.522740 No known gpu found for chipset flags 0x32 (panfrost)
10842 06:53:34.529603 Last errno: 2, No such file or directory
10843 06:53:34.533332 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
10844 06:53:34.545234 <8>[ 20.683118] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
10845 06:53:34.546088 Received signal: <TESTSET> START panfrost_get_param
10846 06:53:34.546566 Starting test_set panfrost_get_param
10847 06:53:34.576859 <14>[ 20.714813] [IGT] panfrost_get_param: executing
10848 06:53:34.587306 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.722910] [IGT] panfrost_get_param: exiting, ret=77
10849 06:53:34.590336 .1.75-cip14 aarch64)
10850 06:53:34.604084 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 20.737872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
10851 06:53:34.604660 c:621:
10852 06:53:34.605098 Test requirement: !(fd<0)
10853 06:53:34.605795 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
10855 06:53:34.609617 No known gpu found for chipset flags 0x32 (panfrost)
10856 06:53:34.613315 Last errno: 2, No such file or directory
10857 06:53:34.619813 [1mSubtest b<14>[ 20.756605] [IGT] panfrost_get_param: executing
10858 06:53:34.624783 ase-params: SKIP (0.000s)[0m
10859 06:53:34.626405 I<14>[ 20.763926] [IGT] panfrost_get_param: exiting, ret=77
10860 06:53:34.633361 GT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
10861 06:53:34.643782 Test requir<8>[ 20.776859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
10862 06:53:34.644636 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
10864 06:53:34.646273 ement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10865 06:53:34.649711 Test requirement: !(fd<0)
10866 06:53:34.656406 No known gpu found for chipset<14>[ 20.794885] [IGT] panfrost_get_param: executing
10867 06:53:34.659769 flags 0x32 (panfrost)
10868 06:53:34.666570 Last err<14>[ 20.802500] [IGT] panfrost_get_param: exiting, ret=77
10869 06:53:34.670638 no: 2, No such file or directory
10870 06:53:34.672698 [1mSubtest get-bad-param: SKIP (0.000s)[0m
10871 06:53:34.680382 <8>[ 20.815132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
10872 06:53:34.681579 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
10874 06:53:34.686041 IGT-Version: 1.27.1-g621c2d3 (aa<8>[ 20.824782] <LAVA_SIGNAL_TESTSET STOP>
10875 06:53:34.686769 Received signal: <TESTSET> STOP
10876 06:53:34.687158 Closing test_set panfrost_get_param
10877 06:53:34.689890 rch64) (Linux: 6.1.75-cip14 aarch64)
10878 06:53:34.696246 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10879 06:53:34.700230 Test requirement: !(fd<0)
10880 06:53:34.705879 No known gpu found for chipset flags 0x32 (panfrost)
10881 06:53:34.709451 Last errno: 2, No such file or directory
10882 06:53:34.712465 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
10883 06:53:34.715928 Received signal: <TESTSET> START panfrost_prime
10884 06:53:34.716390 Starting test_set panfrost_prime
10885 06:53:34.719457 <8>[ 20.854862] <LAVA_SIGNAL_TESTSET START panfrost_prime>
10886 06:53:34.743474 <14>[ 20.881481] [IGT] panfrost_prime: executing
10887 06:53:34.753567 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.889555] [IGT] panfrost_prime: exiting, ret=77
10888 06:53:34.754142 .1.75-cip14 aarch64)
10889 06:53:34.761568 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10890 06:53:34.771528 Test req<8>[ 20.904830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
10891 06:53:34.772098 uirement: !(fd<0)
10892 06:53:34.772792 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
10894 06:53:34.777092 No known gpu <8>[ 20.914411] <LAVA_SIGNAL_TESTSET STOP>
10895 06:53:34.777824 Received signal: <TESTSET> STOP
10896 06:53:34.778211 Closing test_set panfrost_prime
10897 06:53:34.780263 found for chipset flags 0x32 (panfrost)
10898 06:53:34.783097 Last errno: 2, No such file or directory
10899 06:53:34.786556 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
10900 06:53:34.807786 <8>[ 20.945052] <LAVA_SIGNAL_TESTSET START panfrost_submit>
10901 06:53:34.808646 Received signal: <TESTSET> START panfrost_submit
10902 06:53:34.809092 Starting test_set panfrost_submit
10903 06:53:34.839745 <14>[ 20.977312] [IGT] panfrost_submit: executing
10904 06:53:34.849441 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.985225] [IGT] panfrost_submit: exiting, ret=77
10905 06:53:34.850031 .1.75-cip14 aarch64)
10906 06:53:34.864280 Test requirement not met in function drm_open_driver, file<8>[ 20.998094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
10907 06:53:34.865179 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
10909 06:53:34.866455 ../lib/drmtest.c:621:
10910 06:53:34.866830 Test requirement: !(fd<0)
10911 06:53:34.874514 No known gpu found for chipset flags 0x32 (panfrost)
10912 06:53:34.876126 Last errno: 2, No such file or directory
10913 06:53:34.880209 [1mSubtest pan-submit: SKIP (0.000s)[0m
10914 06:53:34.888665 <14>[ 21.026845] [IGT] panfrost_submit: executing
10915 06:53:34.898878 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.034654] [IGT] panfrost_submit: exiting, ret=77
10916 06:53:34.899447 .1.75-cip14 aarch64)
10917 06:53:34.909201 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10918 06:53:34.914965 Test req<8>[ 21.049921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
10919 06:53:34.915948 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
10921 06:53:34.918634 uirement: !(fd<0)
10922 06:53:34.921988 No known gpu found for chipset flags 0x32 (panfrost)
10923 06:53:34.924827 Last errno: 2, No such file or directory
10924 06:53:34.933308 [1mSubtest pan-submit-error-<14>[ 21.070994] [IGT] panfrost_submit: executing
10925 06:53:34.935710 no-jc: SKIP (0.000s)[0m
10926 06:53:34.941352 IGT-Ve<14>[ 21.077768] [IGT] panfrost_submit: exiting, ret=77
10927 06:53:34.944877 rsion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
10928 06:53:34.958094 Test requirement not met in func<8>[ 21.091235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
10929 06:53:34.958966 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
10931 06:53:34.961495 tion drm_open_driver, file ../lib/drmtest.c:621:
10932 06:53:34.964812 Test requirement: !(fd<0)
10933 06:53:34.968534 No known gpu found for chipset flags 0x32 (panfrost)
10934 06:53:34.971632 Last errno: 2, No such file or directory
10935 06:53:34.978262 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
10936 06:53:34.984297 <14>[ 21.122124] [IGT] panfrost_submit: executing
10937 06:53:34.994191 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.129990] [IGT] panfrost_submit: exiting, ret=77
10938 06:53:34.994760 .1.75-cip14 aarch64)
10939 06:53:35.001685 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10940 06:53:35.011717 Test req<8>[ 21.145637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
10941 06:53:35.012594 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
10943 06:53:35.014539 uirement: !(fd<0)
10944 06:53:35.017516 No known gpu found for chipset flags 0x32 (panfrost)
10945 06:53:35.021323 Last errno: 2, No such file or directory
10946 06:53:35.027189 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
10947 06:53:35.039833 <14>[ 21.177816] [IGT] panfrost_submit: executing
10948 06:53:35.050059 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.185648] [IGT] panfrost_submit: exiting, ret=77
10949 06:53:35.050635 .1.75-cip14 aarch64)
10950 06:53:35.060568 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10951 06:53:35.071445 Test requirement: !(fd<0<8>[ 21.202146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
10952 06:53:35.072019 )
10953 06:53:35.072680 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
10955 06:53:35.074076 No known gpu found for chipset flags 0x32 (panfrost)
10956 06:53:35.078348 Last errno: 2, No such file or directory
10957 06:53:35.083326 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
10958 06:53:35.095980 <14>[ 21.233694] [IGT] panfrost_submit: executing
10959 06:53:35.105589 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.241404] [IGT] panfrost_submit: exiting, ret=77
10960 06:53:35.106156 .1.75-cip14 aarch64)
10961 06:53:35.112491 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10962 06:53:35.122345 Test req<8>[ 21.256628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
10963 06:53:35.123202 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
10965 06:53:35.126417 uirement: !(fd<0)
10966 06:53:35.129089 No known gpu found for chipset flags 0x32 (panfrost)
10967 06:53:35.132535 Last errno: 2, No such file or directory
10968 06:53:35.139443 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
10969 06:53:35.142307 <14>[ 21.280468] [IGT] panfrost_submit: executing
10970 06:53:35.142801
10971 06:53:35.152052 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 21.287726] [IGT] panfrost_submit: exiting, ret=77
10972 06:53:35.155761 rch64) (Linux: 6.1.75-cip14 aarch64)
10973 06:53:35.165438 Test requirement not met in function drm_o<8>[ 21.300177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
10974 06:53:35.166338 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
10976 06:53:35.168418 pen_driver, file ../lib/drmtest.c:621:
10977 06:53:35.172211 Test requirement: !(fd<0)
10978 06:53:35.176046 No known gpu found for chipset flags 0x32 (panfrost)
10979 06:53:35.179177 Last errno: 2, No such file or directory
10980 06:53:35.182082 [1mSubtest pan-reset: SKIP (0.000s)[0m
10981 06:53:35.191273 <14>[ 21.329289] [IGT] panfrost_submit: executing
10982 06:53:35.201179 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.337247] [IGT] panfrost_submit: exiting, ret=77
10983 06:53:35.201764 .1.75-cip14 aarch64)
10984 06:53:35.213708 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10985 06:53:35.218483 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
10987 06:53:35.221191 Test requirement: !(fd<0<8>[ 21.353546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
10988 06:53:35.221672 )
10989 06:53:35.224893 No known gpu found for chipset flags 0x32 (panfrost)
10990 06:53:35.227461 Last errno: 2, No such file or directory
10991 06:53:35.234012 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
10992 06:53:35.246828 <14>[ 21.384788] [IGT] panfrost_submit: executing
10993 06:53:35.256596 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.392608] [IGT] panfrost_submit: exiting, ret=77
10994 06:53:35.257209 .1.75-cip14 aarch64)
10995 06:53:35.273026 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 21.407109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
10996 06:53:35.273616 c:621:
10997 06:53:35.274278 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
10999 06:53:35.279793 Test requirement: !(fd<0<8>[ 21.417434] <LAVA_SIGNAL_TESTSET STOP>
11000 06:53:35.280277 )
11001 06:53:35.280915 Received signal: <TESTSET> STOP
11002 06:53:35.281300 Closing test_set panfrost_submit
11003 06:53:35.286239 No known gpu <8>[ 21.422880] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12694836_1.5.2.3.1>
11004 06:53:35.286983 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12694836_1.5.2.3.1
11005 06:53:35.287443 Ending use of test pattern.
11006 06:53:35.287799 Ending test lava.0_igt-gpu-panfrost (12694836_1.5.2.3.1), duration 0.94
11008 06:53:35.289493 found for chipset flags 0x32 (panfrost)
11009 06:53:35.292676 Last errno: 2, No such file or directory
11010 06:53:35.299604 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11011 06:53:35.300181 + set +x
11012 06:53:35.302910 <LAVA_TEST_RUNNER EXIT>
11013 06:53:35.303762 ok: lava_test_shell seems to have completed
11014 06:53:35.305588 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11015 06:53:35.306138 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11016 06:53:35.306616 end: 3 lava-test-retry (duration 00:00:01) [common]
11017 06:53:35.307107 start: 4 finalize (timeout 00:07:42) [common]
11018 06:53:35.307615 start: 4.1 power-off (timeout 00:00:30) [common]
11019 06:53:35.308415 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11020 06:53:35.433211 >> Command sent successfully.
11021 06:53:35.444952 Returned 0 in 0 seconds
11022 06:53:35.546363 end: 4.1 power-off (duration 00:00:00) [common]
11024 06:53:35.548014 start: 4.2 read-feedback (timeout 00:07:41) [common]
11025 06:53:35.549385 Listened to connection for namespace 'common' for up to 1s
11026 06:53:36.549065 Finalising connection for namespace 'common'
11027 06:53:36.549762 Disconnecting from shell: Finalise
11028 06:53:36.550195 / #
11029 06:53:36.651233 end: 4.2 read-feedback (duration 00:00:01) [common]
11030 06:53:36.651984 end: 4 finalize (duration 00:00:01) [common]
11031 06:53:36.652664 Cleaning after the job
11032 06:53:36.653277 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/ramdisk
11033 06:53:36.688153 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/kernel
11034 06:53:36.705153 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/dtb
11035 06:53:36.705433 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694836/tftp-deploy-8v56v5jm/modules
11036 06:53:36.714870 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694836
11037 06:53:36.834098 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694836
11038 06:53:36.834281 Job finished correctly