Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 35
1 06:47:06.064473 lava-dispatcher, installed at version: 2023.10
2 06:47:06.064691 start: 0 validate
3 06:47:06.064838 Start time: 2024-02-03 06:47:06.064829+00:00 (UTC)
4 06:47:06.065001 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:47:06.065134 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Finitrd.cpio.gz exists
6 06:47:06.332996 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:47:06.333165 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:47:12.338324 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:47:12.338982 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:47:12.611826 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:47:12.612193 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:47:13.146481 Using caching service: 'http://localhost/cache/?uri=%s'
13 06:47:13.147151 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 06:47:16.155289 validate duration: 10.09
16 06:47:16.155652 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:47:16.155788 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:47:16.155927 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:47:16.156088 Not decompressing ramdisk as can be used compressed.
20 06:47:16.156215 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/initrd.cpio.gz
21 06:47:16.156307 saving as /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/ramdisk/initrd.cpio.gz
22 06:47:16.156418 total size: 5628325 (5 MB)
23 06:47:16.157946 progress 0 % (0 MB)
24 06:47:16.160644 progress 5 % (0 MB)
25 06:47:16.163329 progress 10 % (0 MB)
26 06:47:16.165556 progress 15 % (0 MB)
27 06:47:16.168118 progress 20 % (1 MB)
28 06:47:16.170140 progress 25 % (1 MB)
29 06:47:16.171704 progress 30 % (1 MB)
30 06:47:16.173269 progress 35 % (1 MB)
31 06:47:16.174702 progress 40 % (2 MB)
32 06:47:16.176243 progress 45 % (2 MB)
33 06:47:16.177635 progress 50 % (2 MB)
34 06:47:16.179205 progress 55 % (2 MB)
35 06:47:16.180763 progress 60 % (3 MB)
36 06:47:16.182207 progress 65 % (3 MB)
37 06:47:16.183763 progress 70 % (3 MB)
38 06:47:16.185147 progress 75 % (4 MB)
39 06:47:16.186755 progress 80 % (4 MB)
40 06:47:16.188138 progress 85 % (4 MB)
41 06:47:16.189738 progress 90 % (4 MB)
42 06:47:16.191293 progress 95 % (5 MB)
43 06:47:16.192706 progress 100 % (5 MB)
44 06:47:16.192916 5 MB downloaded in 0.04 s (147.06 MB/s)
45 06:47:16.193071 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:47:16.193307 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:47:16.193390 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:47:16.193471 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:47:16.193651 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 06:47:16.193717 saving as /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/kernel/Image
52 06:47:16.193774 total size: 51532288 (49 MB)
53 06:47:16.193834 No compression specified
54 06:47:16.194911 progress 0 % (0 MB)
55 06:47:16.208582 progress 5 % (2 MB)
56 06:47:16.223034 progress 10 % (4 MB)
57 06:47:16.237262 progress 15 % (7 MB)
58 06:47:16.251900 progress 20 % (9 MB)
59 06:47:16.265978 progress 25 % (12 MB)
60 06:47:16.279849 progress 30 % (14 MB)
61 06:47:16.293702 progress 35 % (17 MB)
62 06:47:16.307202 progress 40 % (19 MB)
63 06:47:16.320396 progress 45 % (22 MB)
64 06:47:16.333892 progress 50 % (24 MB)
65 06:47:16.347354 progress 55 % (27 MB)
66 06:47:16.361209 progress 60 % (29 MB)
67 06:47:16.375324 progress 65 % (31 MB)
68 06:47:16.389957 progress 70 % (34 MB)
69 06:47:16.404824 progress 75 % (36 MB)
70 06:47:16.418494 progress 80 % (39 MB)
71 06:47:16.435261 progress 85 % (41 MB)
72 06:47:16.456833 progress 90 % (44 MB)
73 06:47:16.478216 progress 95 % (46 MB)
74 06:47:16.491809 progress 100 % (49 MB)
75 06:47:16.492060 49 MB downloaded in 0.30 s (164.76 MB/s)
76 06:47:16.492218 end: 1.2.1 http-download (duration 00:00:00) [common]
78 06:47:16.492455 end: 1.2 download-retry (duration 00:00:00) [common]
79 06:47:16.492540 start: 1.3 download-retry (timeout 00:10:00) [common]
80 06:47:16.492628 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 06:47:16.492813 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 06:47:16.492911 saving as /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/dtb/mt8192-asurada-spherion-r0.dtb
83 06:47:16.492974 total size: 47278 (0 MB)
84 06:47:16.493035 No compression specified
85 06:47:16.494190 progress 69 % (0 MB)
86 06:47:16.494470 progress 100 % (0 MB)
87 06:47:16.494627 0 MB downloaded in 0.00 s (27.31 MB/s)
88 06:47:16.494751 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:47:16.495030 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:47:16.495118 start: 1.4 download-retry (timeout 00:10:00) [common]
92 06:47:16.495199 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 06:47:16.495321 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/full.rootfs.tar.xz
94 06:47:16.495393 saving as /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/nfsrootfs/full.rootfs.tar
95 06:47:16.495453 total size: 198084472 (188 MB)
96 06:47:16.495552 Using unxz to decompress xz
97 06:47:16.499911 progress 0 % (0 MB)
98 06:47:17.078378 progress 5 % (9 MB)
99 06:47:17.587992 progress 10 % (18 MB)
100 06:47:18.187272 progress 15 % (28 MB)
101 06:47:18.492493 progress 20 % (37 MB)
102 06:47:18.984956 progress 25 % (47 MB)
103 06:47:19.577826 progress 30 % (56 MB)
104 06:47:20.162712 progress 35 % (66 MB)
105 06:47:20.744899 progress 40 % (75 MB)
106 06:47:21.349442 progress 45 % (85 MB)
107 06:47:21.978568 progress 50 % (94 MB)
108 06:47:22.616070 progress 55 % (103 MB)
109 06:47:23.301315 progress 60 % (113 MB)
110 06:47:23.716973 progress 65 % (122 MB)
111 06:47:23.833693 progress 70 % (132 MB)
112 06:47:23.988894 progress 75 % (141 MB)
113 06:47:24.067026 progress 80 % (151 MB)
114 06:47:24.117550 progress 85 % (160 MB)
115 06:47:24.215293 progress 90 % (170 MB)
116 06:47:24.602568 progress 95 % (179 MB)
117 06:47:25.205885 progress 100 % (188 MB)
118 06:47:25.210733 188 MB downloaded in 8.72 s (21.68 MB/s)
119 06:47:25.211140 end: 1.4.1 http-download (duration 00:00:09) [common]
121 06:47:25.211565 end: 1.4 download-retry (duration 00:00:09) [common]
122 06:47:25.211699 start: 1.5 download-retry (timeout 00:09:51) [common]
123 06:47:25.211830 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 06:47:25.212049 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 06:47:25.212152 saving as /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/modules/modules.tar
126 06:47:25.212246 total size: 8624064 (8 MB)
127 06:47:25.212342 Using unxz to decompress xz
128 06:47:25.218094 progress 0 % (0 MB)
129 06:47:25.240364 progress 5 % (0 MB)
130 06:47:25.265944 progress 10 % (0 MB)
131 06:47:25.291775 progress 15 % (1 MB)
132 06:47:25.316579 progress 20 % (1 MB)
133 06:47:25.341302 progress 25 % (2 MB)
134 06:47:25.368181 progress 30 % (2 MB)
135 06:47:25.396859 progress 35 % (2 MB)
136 06:47:25.422379 progress 40 % (3 MB)
137 06:47:25.448751 progress 45 % (3 MB)
138 06:47:25.476020 progress 50 % (4 MB)
139 06:47:25.502016 progress 55 % (4 MB)
140 06:47:25.528028 progress 60 % (4 MB)
141 06:47:25.557456 progress 65 % (5 MB)
142 06:47:25.583908 progress 70 % (5 MB)
143 06:47:25.610178 progress 75 % (6 MB)
144 06:47:25.638975 progress 80 % (6 MB)
145 06:47:25.665705 progress 85 % (7 MB)
146 06:47:25.691675 progress 90 % (7 MB)
147 06:47:25.724069 progress 95 % (7 MB)
148 06:47:25.752819 progress 100 % (8 MB)
149 06:47:25.757800 8 MB downloaded in 0.55 s (15.08 MB/s)
150 06:47:25.758178 end: 1.5.1 http-download (duration 00:00:01) [common]
152 06:47:25.758583 end: 1.5 download-retry (duration 00:00:01) [common]
153 06:47:25.758715 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 06:47:25.758850 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 06:47:29.520542 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12694808/extract-nfsrootfs-jye3qfhu
156 06:47:29.520742 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 06:47:29.520849 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 06:47:29.521024 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat
159 06:47:29.521160 makedir: /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin
160 06:47:29.521261 makedir: /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/tests
161 06:47:29.521358 makedir: /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/results
162 06:47:29.521462 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-add-keys
163 06:47:29.521925 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-add-sources
164 06:47:29.522055 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-background-process-start
165 06:47:29.522183 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-background-process-stop
166 06:47:29.522309 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-common-functions
167 06:47:29.522433 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-echo-ipv4
168 06:47:29.522557 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-install-packages
169 06:47:29.522681 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-installed-packages
170 06:47:29.522805 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-os-build
171 06:47:29.522928 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-probe-channel
172 06:47:29.523053 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-probe-ip
173 06:47:29.523176 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-target-ip
174 06:47:29.523298 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-target-mac
175 06:47:29.523420 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-target-storage
176 06:47:29.523544 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-test-case
177 06:47:29.523670 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-test-event
178 06:47:29.523793 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-test-feedback
179 06:47:29.523917 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-test-raise
180 06:47:29.524040 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-test-reference
181 06:47:29.524163 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-test-runner
182 06:47:29.524286 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-test-set
183 06:47:29.524408 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-test-shell
184 06:47:29.524532 Updating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-add-keys (debian)
185 06:47:29.524681 Updating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-add-sources (debian)
186 06:47:29.524820 Updating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-install-packages (debian)
187 06:47:29.524956 Updating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-installed-packages (debian)
188 06:47:29.525092 Updating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/bin/lava-os-build (debian)
189 06:47:29.525211 Creating /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/environment
190 06:47:29.525309 LAVA metadata
191 06:47:29.525378 - LAVA_JOB_ID=12694808
192 06:47:29.525439 - LAVA_DISPATCHER_IP=192.168.201.1
193 06:47:29.525555 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 06:47:29.525622 skipped lava-vland-overlay
195 06:47:29.525695 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 06:47:29.525773 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 06:47:29.525833 skipped lava-multinode-overlay
198 06:47:29.525905 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 06:47:29.525995 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 06:47:29.526069 Loading test definitions
201 06:47:29.526160 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 06:47:29.526231 Using /lava-12694808 at stage 0
203 06:47:29.526514 uuid=12694808_1.6.2.3.1 testdef=None
204 06:47:29.526602 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 06:47:29.526686 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 06:47:29.527139 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 06:47:29.527355 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 06:47:29.527908 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 06:47:29.528131 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 06:47:29.528668 runner path: /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/0/tests/0_timesync-off test_uuid 12694808_1.6.2.3.1
213 06:47:29.528820 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 06:47:29.529039 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 06:47:29.529111 Using /lava-12694808 at stage 0
217 06:47:29.529207 Fetching tests from https://github.com/kernelci/test-definitions.git
218 06:47:29.529284 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/0/tests/1_kselftest-alsa'
219 06:47:33.697910 Running '/usr/bin/git checkout kernelci.org
220 06:47:33.859197 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 06:47:33.860211 uuid=12694808_1.6.2.3.5 testdef=None
222 06:47:33.860429 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 06:47:33.860793 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 06:47:33.861927 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 06:47:33.862268 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 06:47:33.863761 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 06:47:33.864110 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 06:47:33.865544 runner path: /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/0/tests/1_kselftest-alsa test_uuid 12694808_1.6.2.3.5
232 06:47:33.865673 BOARD='mt8192-asurada-spherion-r0'
233 06:47:33.865764 BRANCH='cip'
234 06:47:33.865851 SKIPFILE='/dev/null'
235 06:47:33.865936 SKIP_INSTALL='True'
236 06:47:33.866021 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 06:47:33.866112 TST_CASENAME=''
238 06:47:33.866197 TST_CMDFILES='alsa'
239 06:47:33.866395 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 06:47:33.866715 Creating lava-test-runner.conf files
242 06:47:33.866813 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694808/lava-overlay-vwa2ceat/lava-12694808/0 for stage 0
243 06:47:33.866944 - 0_timesync-off
244 06:47:33.867046 - 1_kselftest-alsa
245 06:47:33.867180 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 06:47:33.867305 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 06:47:41.655138 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 06:47:41.655325 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 06:47:41.655419 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 06:47:41.655523 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 06:47:41.655617 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 06:47:41.839101 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 06:47:41.839521 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 06:47:41.839665 extracting modules file /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694808/extract-nfsrootfs-jye3qfhu
255 06:47:42.099769 extracting modules file /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694808/extract-overlay-ramdisk-waw9ov66/ramdisk
256 06:47:42.384851 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 06:47:42.385031 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 06:47:42.385152 [common] Applying overlay to NFS
259 06:47:42.385251 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694808/compress-overlay-xaqjxla4/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694808/extract-nfsrootfs-jye3qfhu
260 06:47:43.356567 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 06:47:43.356737 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 06:47:43.356833 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 06:47:43.356923 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 06:47:43.357003 Building ramdisk /var/lib/lava/dispatcher/tmp/12694808/extract-overlay-ramdisk-waw9ov66/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694808/extract-overlay-ramdisk-waw9ov66/ramdisk
265 06:47:43.692557 >> 130555 blocks
266 06:47:45.745177 rename /var/lib/lava/dispatcher/tmp/12694808/extract-overlay-ramdisk-waw9ov66/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/ramdisk/ramdisk.cpio.gz
267 06:47:45.745710 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 06:47:45.745834 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 06:47:45.745940 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 06:47:45.746061 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/kernel/Image'
271 06:47:59.691713 Returned 0 in 13 seconds
272 06:47:59.792424 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/kernel/image.itb
273 06:48:00.185451 output: FIT description: Kernel Image image with one or more FDT blobs
274 06:48:00.185875 output: Created: Sat Feb 3 06:48:00 2024
275 06:48:00.185954 output: Image 0 (kernel-1)
276 06:48:00.186017 output: Description:
277 06:48:00.186080 output: Created: Sat Feb 3 06:48:00 2024
278 06:48:00.186175 output: Type: Kernel Image
279 06:48:00.186234 output: Compression: lzma compressed
280 06:48:00.186293 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
281 06:48:00.186350 output: Architecture: AArch64
282 06:48:00.186408 output: OS: Linux
283 06:48:00.186466 output: Load Address: 0x00000000
284 06:48:00.186524 output: Entry Point: 0x00000000
285 06:48:00.186580 output: Hash algo: crc32
286 06:48:00.186636 output: Hash value: 380e7c3c
287 06:48:00.186688 output: Image 1 (fdt-1)
288 06:48:00.186776 output: Description: mt8192-asurada-spherion-r0
289 06:48:00.186828 output: Created: Sat Feb 3 06:48:00 2024
290 06:48:00.186881 output: Type: Flat Device Tree
291 06:48:00.186932 output: Compression: uncompressed
292 06:48:00.186983 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 06:48:00.187035 output: Architecture: AArch64
294 06:48:00.187086 output: Hash algo: crc32
295 06:48:00.187138 output: Hash value: cc4352de
296 06:48:00.187189 output: Image 2 (ramdisk-1)
297 06:48:00.187240 output: Description: unavailable
298 06:48:00.187291 output: Created: Sat Feb 3 06:48:00 2024
299 06:48:00.187343 output: Type: RAMDisk Image
300 06:48:00.187394 output: Compression: Unknown Compression
301 06:48:00.187445 output: Data Size: 18769502 Bytes = 18329.59 KiB = 17.90 MiB
302 06:48:00.187498 output: Architecture: AArch64
303 06:48:00.187549 output: OS: Linux
304 06:48:00.187600 output: Load Address: unavailable
305 06:48:00.187651 output: Entry Point: unavailable
306 06:48:00.187702 output: Hash algo: crc32
307 06:48:00.187753 output: Hash value: 5ac79c2f
308 06:48:00.187804 output: Default Configuration: 'conf-1'
309 06:48:00.187855 output: Configuration 0 (conf-1)
310 06:48:00.187905 output: Description: mt8192-asurada-spherion-r0
311 06:48:00.187957 output: Kernel: kernel-1
312 06:48:00.188008 output: Init Ramdisk: ramdisk-1
313 06:48:00.188059 output: FDT: fdt-1
314 06:48:00.188109 output: Loadables: kernel-1
315 06:48:00.188160 output:
316 06:48:00.188374 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 06:48:00.188472 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 06:48:00.188576 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 06:48:00.188671 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 06:48:00.188748 No LXC device requested
321 06:48:00.188824 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 06:48:00.188906 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 06:48:00.188983 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 06:48:00.189049 Checking files for TFTP limit of 4294967296 bytes.
325 06:48:00.189596 end: 1 tftp-deploy (duration 00:00:44) [common]
326 06:48:00.189701 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 06:48:00.189795 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 06:48:00.189920 substitutions:
329 06:48:00.189986 - {DTB}: 12694808/tftp-deploy-e5jug5ya/dtb/mt8192-asurada-spherion-r0.dtb
330 06:48:00.190050 - {INITRD}: 12694808/tftp-deploy-e5jug5ya/ramdisk/ramdisk.cpio.gz
331 06:48:00.190107 - {KERNEL}: 12694808/tftp-deploy-e5jug5ya/kernel/Image
332 06:48:00.190162 - {LAVA_MAC}: None
333 06:48:00.190217 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12694808/extract-nfsrootfs-jye3qfhu
334 06:48:00.190271 - {NFS_SERVER_IP}: 192.168.201.1
335 06:48:00.190326 - {PRESEED_CONFIG}: None
336 06:48:00.190379 - {PRESEED_LOCAL}: None
337 06:48:00.190433 - {RAMDISK}: 12694808/tftp-deploy-e5jug5ya/ramdisk/ramdisk.cpio.gz
338 06:48:00.190487 - {ROOT_PART}: None
339 06:48:00.190541 - {ROOT}: None
340 06:48:00.190593 - {SERVER_IP}: 192.168.201.1
341 06:48:00.190646 - {TEE}: None
342 06:48:00.190699 Parsed boot commands:
343 06:48:00.190751 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 06:48:00.190982 Parsed boot commands: tftpboot 192.168.201.1 12694808/tftp-deploy-e5jug5ya/kernel/image.itb 12694808/tftp-deploy-e5jug5ya/kernel/cmdline
345 06:48:00.191101 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 06:48:00.191216 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 06:48:00.191349 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 06:48:00.191435 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 06:48:00.191521 Not connected, no need to disconnect.
350 06:48:00.191594 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 06:48:00.191671 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 06:48:00.191742 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 06:48:00.195975 Setting prompt string to ['lava-test: # ']
354 06:48:00.196481 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 06:48:00.196644 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 06:48:00.196770 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 06:48:00.196899 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 06:48:00.197150 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 06:48:05.328428 >> Command sent successfully.
360 06:48:05.330843 Returned 0 in 5 seconds
361 06:48:05.431174 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 06:48:05.431592 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 06:48:05.431731 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 06:48:05.431853 Setting prompt string to 'Starting depthcharge on Spherion...'
366 06:48:05.431953 Changing prompt to 'Starting depthcharge on Spherion...'
367 06:48:05.432047 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 06:48:05.432428 [Enter `^Ec?' for help]
369 06:48:05.606800
370 06:48:05.607352
371 06:48:05.607705 F0: 102B 0000
372 06:48:05.608153
373 06:48:05.608555 F3: 1001 0000 [0200]
374 06:48:05.609659
375 06:48:05.610078 F3: 1001 0000
376 06:48:05.610413
377 06:48:05.610724 F7: 102D 0000
378 06:48:05.611023
379 06:48:05.613034 F1: 0000 0000
380 06:48:05.613452
381 06:48:05.613834 V0: 0000 0000 [0001]
382 06:48:05.614159
383 06:48:05.616217 00: 0007 8000
384 06:48:05.616656
385 06:48:05.616989 01: 0000 0000
386 06:48:05.617305
387 06:48:05.619928 BP: 0C00 0209 [0000]
388 06:48:05.620348
389 06:48:05.620678 G0: 1182 0000
390 06:48:05.620987
391 06:48:05.623351 EC: 0000 0021 [4000]
392 06:48:05.623771
393 06:48:05.624102 S7: 0000 0000 [0000]
394 06:48:05.624412
395 06:48:05.627390 CC: 0000 0000 [0001]
396 06:48:05.628053
397 06:48:05.628406 T0: 0000 0040 [010F]
398 06:48:05.628894
399 06:48:05.629222 Jump to BL
400 06:48:05.630157
401 06:48:05.653980
402 06:48:05.654522
403 06:48:05.654868
404 06:48:05.661335 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 06:48:05.664989 ARM64: Exception handlers installed.
406 06:48:05.667870 ARM64: Testing exception
407 06:48:05.671199 ARM64: Done test exception
408 06:48:05.678026 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 06:48:05.688414 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 06:48:05.695332 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 06:48:05.704902 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 06:48:05.711665 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 06:48:05.718151 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 06:48:05.731167 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 06:48:05.737669 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 06:48:05.756421 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 06:48:05.759537 WDT: Last reset was cold boot
418 06:48:05.762884 SPI1(PAD0) initialized at 2873684 Hz
419 06:48:05.766179 SPI5(PAD0) initialized at 992727 Hz
420 06:48:05.769712 VBOOT: Loading verstage.
421 06:48:05.776364 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 06:48:05.779371 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 06:48:05.783140 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 06:48:05.786048 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 06:48:05.793792 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 06:48:05.800609 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 06:48:05.811389 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 06:48:05.811828
429 06:48:05.812158
430 06:48:05.821422 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 06:48:05.824752 ARM64: Exception handlers installed.
432 06:48:05.828024 ARM64: Testing exception
433 06:48:05.828449 ARM64: Done test exception
434 06:48:05.834762 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 06:48:05.838083 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 06:48:05.852432 Probing TPM: . done!
437 06:48:05.852913 TPM ready after 0 ms
438 06:48:05.858901 Connected to device vid:did:rid of 1ae0:0028:00
439 06:48:05.866572 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 06:48:05.905152 Initialized TPM device CR50 revision 0
441 06:48:05.916818 tlcl_send_startup: Startup return code is 0
442 06:48:05.917259 TPM: setup succeeded
443 06:48:05.928459 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 06:48:05.937338 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 06:48:05.948588 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 06:48:05.957729 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 06:48:05.961160 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 06:48:05.967039 in-header: 03 07 00 00 08 00 00 00
449 06:48:05.970316 in-data: aa e4 47 04 13 02 00 00
450 06:48:05.974029 Chrome EC: UHEPI supported
451 06:48:05.981413 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 06:48:05.984693 in-header: 03 9d 00 00 08 00 00 00
453 06:48:05.988149 in-data: 10 20 20 08 00 00 00 00
454 06:48:05.988572 Phase 1
455 06:48:05.991814 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 06:48:05.998750 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 06:48:06.006427 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 06:48:06.009931 Recovery requested (1009000e)
459 06:48:06.015412 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 06:48:06.020778 tlcl_extend: response is 0
461 06:48:06.029278 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 06:48:06.034249 tlcl_extend: response is 0
463 06:48:06.041656 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 06:48:06.062007 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 06:48:06.069525 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 06:48:06.069968
467 06:48:06.070304
468 06:48:06.076882 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 06:48:06.080713 ARM64: Exception handlers installed.
470 06:48:06.084456 ARM64: Testing exception
471 06:48:06.087656 ARM64: Done test exception
472 06:48:06.104455 pmic_efuse_setting: Set efuses in 11 msecs
473 06:48:06.109811 pmwrap_interface_init: Select PMIF_VLD_RDY
474 06:48:06.117362 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 06:48:06.120946 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 06:48:06.124336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 06:48:06.131699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 06:48:06.135400 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 06:48:06.138678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 06:48:06.146512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 06:48:06.149530 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 06:48:06.153116 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 06:48:06.159810 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 06:48:06.163201 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 06:48:06.169793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 06:48:06.173170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 06:48:06.179843 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 06:48:06.186364 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 06:48:06.189674 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 06:48:06.196465 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 06:48:06.202767 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 06:48:06.206477 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 06:48:06.213728 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 06:48:06.217364 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 06:48:06.224615 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 06:48:06.231380 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 06:48:06.234841 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 06:48:06.241767 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 06:48:06.245326 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 06:48:06.252416 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 06:48:06.255927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 06:48:06.262748 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 06:48:06.266020 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 06:48:06.270056 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 06:48:06.277389 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 06:48:06.281111 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 06:48:06.285047 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 06:48:06.292713 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 06:48:06.296421 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 06:48:06.299835 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 06:48:06.306456 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 06:48:06.310056 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 06:48:06.313358 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 06:48:06.320018 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 06:48:06.323440 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 06:48:06.326455 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 06:48:06.333055 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 06:48:06.336778 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 06:48:06.340288 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 06:48:06.346514 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 06:48:06.349830 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 06:48:06.353157 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 06:48:06.356416 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 06:48:06.363374 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 06:48:06.369868 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 06:48:06.380035 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 06:48:06.383507 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 06:48:06.390153 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 06:48:06.400034 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 06:48:06.403671 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 06:48:06.410007 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 06:48:06.413229 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 06:48:06.420180 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2a
534 06:48:06.426866 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 06:48:06.429780 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 06:48:06.433110 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 06:48:06.444466 [RTC]rtc_get_frequency_meter,154: input=15, output=794
538 06:48:06.447824 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 06:48:06.454518 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 06:48:06.457679 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 06:48:06.461022 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 06:48:06.464402 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 06:48:06.468096 ADC[4]: Raw value=894821 ID=7
544 06:48:06.470989 ADC[3]: Raw value=213440 ID=1
545 06:48:06.471411 RAM Code: 0x71
546 06:48:06.477921 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 06:48:06.481236 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 06:48:06.491400 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 06:48:06.498239 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 06:48:06.502030 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 06:48:06.505326 in-header: 03 07 00 00 08 00 00 00
552 06:48:06.508277 in-data: aa e4 47 04 13 02 00 00
553 06:48:06.511573 Chrome EC: UHEPI supported
554 06:48:06.515241 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 06:48:06.520062 in-header: 03 d5 00 00 08 00 00 00
556 06:48:06.523111 in-data: 98 20 60 08 00 00 00 00
557 06:48:06.526978 MRC: failed to locate region type 0.
558 06:48:06.534608 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 06:48:06.537906 DRAM-K: Running full calibration
560 06:48:06.541408 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 06:48:06.545115 header.status = 0x0
562 06:48:06.548776 header.version = 0x6 (expected: 0x6)
563 06:48:06.552053 header.size = 0xd00 (expected: 0xd00)
564 06:48:06.552553 header.flags = 0x0
565 06:48:06.558924 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 06:48:06.576794 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
567 06:48:06.583386 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 06:48:06.586734 dram_init: ddr_geometry: 2
569 06:48:06.590262 [EMI] MDL number = 2
570 06:48:06.590795 [EMI] Get MDL freq = 0
571 06:48:06.593399 dram_init: ddr_type: 0
572 06:48:06.594023 is_discrete_lpddr4: 1
573 06:48:06.596639 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 06:48:06.597333
575 06:48:06.597819
576 06:48:06.600216 [Bian_co] ETT version 0.0.0.1
577 06:48:06.607103 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 06:48:06.607648
579 06:48:06.610518 dramc_set_vcore_voltage set vcore to 650000
580 06:48:06.611026 Read voltage for 800, 4
581 06:48:06.613579 Vio18 = 0
582 06:48:06.614017 Vcore = 650000
583 06:48:06.614404 Vdram = 0
584 06:48:06.617075 Vddq = 0
585 06:48:06.617543 Vmddr = 0
586 06:48:06.620594 dram_init: config_dvfs: 1
587 06:48:06.623759 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 06:48:06.630685 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 06:48:06.633764 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 06:48:06.637192 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 06:48:06.640392 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 06:48:06.644010 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 06:48:06.647219 MEM_TYPE=3, freq_sel=18
594 06:48:06.650493 sv_algorithm_assistance_LP4_1600
595 06:48:06.653466 ============ PULL DRAM RESETB DOWN ============
596 06:48:06.656946 ========== PULL DRAM RESETB DOWN end =========
597 06:48:06.663596 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 06:48:06.666730 ===================================
599 06:48:06.667207 LPDDR4 DRAM CONFIGURATION
600 06:48:06.670228 ===================================
601 06:48:06.673595 EX_ROW_EN[0] = 0x0
602 06:48:06.676807 EX_ROW_EN[1] = 0x0
603 06:48:06.677252 LP4Y_EN = 0x0
604 06:48:06.680149 WORK_FSP = 0x0
605 06:48:06.680572 WL = 0x2
606 06:48:06.683455 RL = 0x2
607 06:48:06.683873 BL = 0x2
608 06:48:06.686870 RPST = 0x0
609 06:48:06.687313 RD_PRE = 0x0
610 06:48:06.689930 WR_PRE = 0x1
611 06:48:06.690346 WR_PST = 0x0
612 06:48:06.693393 DBI_WR = 0x0
613 06:48:06.694031 DBI_RD = 0x0
614 06:48:06.696824 OTF = 0x1
615 06:48:06.700032 ===================================
616 06:48:06.703573 ===================================
617 06:48:06.704001 ANA top config
618 06:48:06.706669 ===================================
619 06:48:06.710233 DLL_ASYNC_EN = 0
620 06:48:06.713299 ALL_SLAVE_EN = 1
621 06:48:06.716761 NEW_RANK_MODE = 1
622 06:48:06.717182 DLL_IDLE_MODE = 1
623 06:48:06.719877 LP45_APHY_COMB_EN = 1
624 06:48:06.723461 TX_ODT_DIS = 1
625 06:48:06.726687 NEW_8X_MODE = 1
626 06:48:06.729963 ===================================
627 06:48:06.733388 ===================================
628 06:48:06.736510 data_rate = 1600
629 06:48:06.736926 CKR = 1
630 06:48:06.740272 DQ_P2S_RATIO = 8
631 06:48:06.743145 ===================================
632 06:48:06.746987 CA_P2S_RATIO = 8
633 06:48:06.750226 DQ_CA_OPEN = 0
634 06:48:06.753547 DQ_SEMI_OPEN = 0
635 06:48:06.754111 CA_SEMI_OPEN = 0
636 06:48:06.756737 CA_FULL_RATE = 0
637 06:48:06.760175 DQ_CKDIV4_EN = 1
638 06:48:06.763447 CA_CKDIV4_EN = 1
639 06:48:06.766707 CA_PREDIV_EN = 0
640 06:48:06.769935 PH8_DLY = 0
641 06:48:06.770354 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 06:48:06.773447 DQ_AAMCK_DIV = 4
643 06:48:06.776844 CA_AAMCK_DIV = 4
644 06:48:06.780052 CA_ADMCK_DIV = 4
645 06:48:06.783318 DQ_TRACK_CA_EN = 0
646 06:48:06.786793 CA_PICK = 800
647 06:48:06.790128 CA_MCKIO = 800
648 06:48:06.790583 MCKIO_SEMI = 0
649 06:48:06.793253 PLL_FREQ = 3068
650 06:48:06.796735 DQ_UI_PI_RATIO = 32
651 06:48:06.800448 CA_UI_PI_RATIO = 0
652 06:48:06.803607 ===================================
653 06:48:06.807161 ===================================
654 06:48:06.810237 memory_type:LPDDR4
655 06:48:06.810665 GP_NUM : 10
656 06:48:06.813541 SRAM_EN : 1
657 06:48:06.813971 MD32_EN : 0
658 06:48:06.817172 ===================================
659 06:48:06.820812 [ANA_INIT] >>>>>>>>>>>>>>
660 06:48:06.824342 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 06:48:06.828328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 06:48:06.832184 ===================================
663 06:48:06.832606 data_rate = 1600,PCW = 0X7600
664 06:48:06.835434 ===================================
665 06:48:06.839438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 06:48:06.846786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 06:48:06.850126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 06:48:06.853812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 06:48:06.857774 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 06:48:06.861410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 06:48:06.865559 [ANA_INIT] flow start
672 06:48:06.866059 [ANA_INIT] PLL >>>>>>>>
673 06:48:06.868931 [ANA_INIT] PLL <<<<<<<<
674 06:48:06.872264 [ANA_INIT] MIDPI >>>>>>>>
675 06:48:06.872782 [ANA_INIT] MIDPI <<<<<<<<
676 06:48:06.875802 [ANA_INIT] DLL >>>>>>>>
677 06:48:06.879918 [ANA_INIT] flow end
678 06:48:06.883582 ============ LP4 DIFF to SE enter ============
679 06:48:06.887066 ============ LP4 DIFF to SE exit ============
680 06:48:06.887529 [ANA_INIT] <<<<<<<<<<<<<
681 06:48:06.891511 [Flow] Enable top DCM control >>>>>
682 06:48:06.894644 [Flow] Enable top DCM control <<<<<
683 06:48:06.898759 Enable DLL master slave shuffle
684 06:48:06.902384 ==============================================================
685 06:48:06.906138 Gating Mode config
686 06:48:06.910143 ==============================================================
687 06:48:06.913660 Config description:
688 06:48:06.921050 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 06:48:06.927999 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 06:48:06.932154 SELPH_MODE 0: By rank 1: By Phase
691 06:48:06.939557 ==============================================================
692 06:48:06.943170 GAT_TRACK_EN = 1
693 06:48:06.946618 RX_GATING_MODE = 2
694 06:48:06.947218 RX_GATING_TRACK_MODE = 2
695 06:48:06.949988 SELPH_MODE = 1
696 06:48:06.953437 PICG_EARLY_EN = 1
697 06:48:06.956363 VALID_LAT_VALUE = 1
698 06:48:06.963606 ==============================================================
699 06:48:06.966551 Enter into Gating configuration >>>>
700 06:48:06.969911 Exit from Gating configuration <<<<
701 06:48:06.973335 Enter into DVFS_PRE_config >>>>>
702 06:48:06.983053 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 06:48:06.986434 Exit from DVFS_PRE_config <<<<<
704 06:48:06.990019 Enter into PICG configuration >>>>
705 06:48:06.993213 Exit from PICG configuration <<<<
706 06:48:06.996333 [RX_INPUT] configuration >>>>>
707 06:48:06.999841 [RX_INPUT] configuration <<<<<
708 06:48:07.003113 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 06:48:07.009893 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 06:48:07.016441 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 06:48:07.019892 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 06:48:07.026696 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 06:48:07.033303 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 06:48:07.036650 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 06:48:07.043057 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 06:48:07.046484 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 06:48:07.049890 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 06:48:07.053014 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 06:48:07.059855 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 06:48:07.063290 ===================================
721 06:48:07.063720 LPDDR4 DRAM CONFIGURATION
722 06:48:07.066604 ===================================
723 06:48:07.070210 EX_ROW_EN[0] = 0x0
724 06:48:07.070656 EX_ROW_EN[1] = 0x0
725 06:48:07.073557 LP4Y_EN = 0x0
726 06:48:07.076524 WORK_FSP = 0x0
727 06:48:07.076979 WL = 0x2
728 06:48:07.080280 RL = 0x2
729 06:48:07.080704 BL = 0x2
730 06:48:07.083495 RPST = 0x0
731 06:48:07.083920 RD_PRE = 0x0
732 06:48:07.086807 WR_PRE = 0x1
733 06:48:07.087349 WR_PST = 0x0
734 06:48:07.090141 DBI_WR = 0x0
735 06:48:07.090606 DBI_RD = 0x0
736 06:48:07.093415 OTF = 0x1
737 06:48:07.096685 ===================================
738 06:48:07.099753 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 06:48:07.103450 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 06:48:07.106753 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 06:48:07.109989 ===================================
742 06:48:07.113612 LPDDR4 DRAM CONFIGURATION
743 06:48:07.116585 ===================================
744 06:48:07.119899 EX_ROW_EN[0] = 0x10
745 06:48:07.120331 EX_ROW_EN[1] = 0x0
746 06:48:07.123494 LP4Y_EN = 0x0
747 06:48:07.123921 WORK_FSP = 0x0
748 06:48:07.126480 WL = 0x2
749 06:48:07.127000 RL = 0x2
750 06:48:07.129938 BL = 0x2
751 06:48:07.130366 RPST = 0x0
752 06:48:07.133288 RD_PRE = 0x0
753 06:48:07.133871 WR_PRE = 0x1
754 06:48:07.136774 WR_PST = 0x0
755 06:48:07.137200 DBI_WR = 0x0
756 06:48:07.139753 DBI_RD = 0x0
757 06:48:07.143483 OTF = 0x1
758 06:48:07.146572 ===================================
759 06:48:07.149725 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 06:48:07.155214 nWR fixed to 40
761 06:48:07.158560 [ModeRegInit_LP4] CH0 RK0
762 06:48:07.159003 [ModeRegInit_LP4] CH0 RK1
763 06:48:07.161698 [ModeRegInit_LP4] CH1 RK0
764 06:48:07.165013 [ModeRegInit_LP4] CH1 RK1
765 06:48:07.165440 match AC timing 13
766 06:48:07.172213 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 06:48:07.176047 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 06:48:07.179325 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 06:48:07.183345 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 06:48:07.186996 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 06:48:07.190931 [EMI DOE] emi_dcm 0
772 06:48:07.194029 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 06:48:07.194456 ==
774 06:48:07.197750 Dram Type= 6, Freq= 0, CH_0, rank 0
775 06:48:07.201449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 06:48:07.202016 ==
777 06:48:07.208638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 06:48:07.212386 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 06:48:07.222918 [CA 0] Center 38 (7~69) winsize 63
780 06:48:07.226536 [CA 1] Center 37 (7~68) winsize 62
781 06:48:07.230651 [CA 2] Center 35 (5~66) winsize 62
782 06:48:07.234183 [CA 3] Center 35 (5~66) winsize 62
783 06:48:07.237845 [CA 4] Center 34 (4~65) winsize 62
784 06:48:07.238309 [CA 5] Center 34 (4~65) winsize 62
785 06:48:07.241751
786 06:48:07.245687 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 06:48:07.246133
788 06:48:07.246580 [CATrainingPosCal] consider 1 rank data
789 06:48:07.249267 u2DelayCellTimex100 = 270/100 ps
790 06:48:07.253063 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 06:48:07.256595 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 06:48:07.260223 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 06:48:07.264037 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 06:48:07.267723 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 06:48:07.271263 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
796 06:48:07.271769
797 06:48:07.275189 CA PerBit enable=1, Macro0, CA PI delay=34
798 06:48:07.275795
799 06:48:07.278837 [CBTSetCACLKResult] CA Dly = 34
800 06:48:07.279281 CS Dly: 6 (0~37)
801 06:48:07.282811 ==
802 06:48:07.283240 Dram Type= 6, Freq= 0, CH_0, rank 1
803 06:48:07.286685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 06:48:07.290095 ==
805 06:48:07.293913 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 06:48:07.300807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 06:48:07.309314 [CA 0] Center 38 (7~69) winsize 63
808 06:48:07.312831 [CA 1] Center 37 (7~68) winsize 62
809 06:48:07.316684 [CA 2] Center 35 (5~66) winsize 62
810 06:48:07.320723 [CA 3] Center 35 (5~66) winsize 62
811 06:48:07.324816 [CA 4] Center 34 (4~65) winsize 62
812 06:48:07.325362 [CA 5] Center 34 (4~65) winsize 62
813 06:48:07.325766
814 06:48:07.328489 [CmdBusTrainingLP45] Vref(ca) range 1: 32
815 06:48:07.328913
816 06:48:07.332216 [CATrainingPosCal] consider 2 rank data
817 06:48:07.335972 u2DelayCellTimex100 = 270/100 ps
818 06:48:07.339563 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 06:48:07.343234 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 06:48:07.346840 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 06:48:07.350797 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 06:48:07.354594 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 06:48:07.358256 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 06:48:07.358739
825 06:48:07.361948 CA PerBit enable=1, Macro0, CA PI delay=34
826 06:48:07.362393
827 06:48:07.365220 [CBTSetCACLKResult] CA Dly = 34
828 06:48:07.365695 CS Dly: 6 (0~38)
829 06:48:07.366113
830 06:48:07.369293 ----->DramcWriteLeveling(PI) begin...
831 06:48:07.369850 ==
832 06:48:07.373040 Dram Type= 6, Freq= 0, CH_0, rank 0
833 06:48:07.376678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 06:48:07.377217 ==
835 06:48:07.380139 Write leveling (Byte 0): 33 => 33
836 06:48:07.383823 Write leveling (Byte 1): 29 => 29
837 06:48:07.387512 DramcWriteLeveling(PI) end<-----
838 06:48:07.387937
839 06:48:07.388267 ==
840 06:48:07.391621 Dram Type= 6, Freq= 0, CH_0, rank 0
841 06:48:07.395078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 06:48:07.395503 ==
843 06:48:07.399260 [Gating] SW mode calibration
844 06:48:07.406352 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 06:48:07.409799 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 06:48:07.413457 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 06:48:07.420807 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 06:48:07.424345 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
849 06:48:07.428479 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 06:48:07.432159 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 06:48:07.435901 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 06:48:07.439759 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 06:48:07.446981 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 06:48:07.450675 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 06:48:07.454418 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 06:48:07.458226 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 06:48:07.461764 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 06:48:07.469092 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 06:48:07.472994 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 06:48:07.476261 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 06:48:07.480287 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 06:48:07.483837 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 06:48:07.490928 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
864 06:48:07.494635 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
865 06:48:07.497751 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
866 06:48:07.501048 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 06:48:07.507851 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 06:48:07.511043 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 06:48:07.514571 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 06:48:07.521239 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 06:48:07.524222 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 06:48:07.527699 0 9 8 | B1->B0 | 2323 2323 | 1 1 | (1 1) (1 1)
873 06:48:07.534291 0 9 12 | B1->B0 | 2727 3232 | 1 1 | (1 1) (1 1)
874 06:48:07.537706 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 06:48:07.541067 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 06:48:07.547681 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 06:48:07.551240 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 06:48:07.554474 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 06:48:07.561301 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
880 06:48:07.564316 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
881 06:48:07.567877 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
882 06:48:07.574247 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 06:48:07.577600 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 06:48:07.581032 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 06:48:07.584441 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 06:48:07.590984 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 06:48:07.594329 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 06:48:07.597600 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
889 06:48:07.604590 0 11 12 | B1->B0 | 3434 3f3f | 1 1 | (0 0) (0 0)
890 06:48:07.607755 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 06:48:07.610944 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 06:48:07.617795 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 06:48:07.621541 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 06:48:07.624500 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 06:48:07.631022 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
896 06:48:07.634380 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 06:48:07.637726 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 06:48:07.644575 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 06:48:07.647841 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 06:48:07.651080 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 06:48:07.657706 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 06:48:07.661039 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 06:48:07.664338 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 06:48:07.671050 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 06:48:07.674368 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 06:48:07.677719 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 06:48:07.680985 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 06:48:07.687736 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 06:48:07.691359 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 06:48:07.694565 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 06:48:07.701313 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 06:48:07.704685 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 06:48:07.707957 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
914 06:48:07.711099 Total UI for P1: 0, mck2ui 16
915 06:48:07.714777 best dqsien dly found for B0: ( 0, 14, 10)
916 06:48:07.721433 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 06:48:07.721955 Total UI for P1: 0, mck2ui 16
918 06:48:07.728338 best dqsien dly found for B1: ( 0, 14, 12)
919 06:48:07.731318 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
920 06:48:07.734581 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 06:48:07.735009
922 06:48:07.737984 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
923 06:48:07.741293 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 06:48:07.744719 [Gating] SW calibration Done
925 06:48:07.745142 ==
926 06:48:07.748608 Dram Type= 6, Freq= 0, CH_0, rank 0
927 06:48:07.751442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 06:48:07.751872 ==
929 06:48:07.754692 RX Vref Scan: 0
930 06:48:07.755115
931 06:48:07.755463 RX Vref 0 -> 0, step: 1
932 06:48:07.755778
933 06:48:07.757897 RX Delay -130 -> 252, step: 16
934 06:48:07.761372 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
935 06:48:07.767793 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
936 06:48:07.771112 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 06:48:07.774431 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
938 06:48:07.778004 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
939 06:48:07.781167 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
940 06:48:07.787889 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 06:48:07.791273 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 06:48:07.794793 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 06:48:07.798025 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
944 06:48:07.801125 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
945 06:48:07.808008 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 06:48:07.811760 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 06:48:07.814773 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 06:48:07.818130 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 06:48:07.821364 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 06:48:07.824796 ==
951 06:48:07.825217 Dram Type= 6, Freq= 0, CH_0, rank 0
952 06:48:07.831370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 06:48:07.831792 ==
954 06:48:07.832126 DQS Delay:
955 06:48:07.834893 DQS0 = 0, DQS1 = 0
956 06:48:07.835422 DQM Delay:
957 06:48:07.838060 DQM0 = 81, DQM1 = 70
958 06:48:07.838483 DQ Delay:
959 06:48:07.841338 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =85
960 06:48:07.844849 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
961 06:48:07.848043 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
962 06:48:07.851480 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 06:48:07.851910
964 06:48:07.852245
965 06:48:07.852553 ==
966 06:48:07.855280 Dram Type= 6, Freq= 0, CH_0, rank 0
967 06:48:07.858634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 06:48:07.859059 ==
969 06:48:07.859391
970 06:48:07.859697
971 06:48:07.862038 TX Vref Scan disable
972 06:48:07.862604 == TX Byte 0 ==
973 06:48:07.868729 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
974 06:48:07.872130 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
975 06:48:07.872590 == TX Byte 1 ==
976 06:48:07.878846 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
977 06:48:07.882021 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
978 06:48:07.882441 ==
979 06:48:07.885524 Dram Type= 6, Freq= 0, CH_0, rank 0
980 06:48:07.888716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 06:48:07.889192 ==
982 06:48:07.902683 TX Vref=22, minBit 11, minWin=26, winSum=433
983 06:48:07.906043 TX Vref=24, minBit 14, minWin=26, winSum=436
984 06:48:07.909426 TX Vref=26, minBit 4, minWin=27, winSum=443
985 06:48:07.913103 TX Vref=28, minBit 11, minWin=27, winSum=446
986 06:48:07.916214 TX Vref=30, minBit 10, minWin=27, winSum=442
987 06:48:07.922783 TX Vref=32, minBit 5, minWin=27, winSum=442
988 06:48:07.926043 [TxChooseVref] Worse bit 11, Min win 27, Win sum 446, Final Vref 28
989 06:48:07.926721
990 06:48:07.929506 Final TX Range 1 Vref 28
991 06:48:07.929939
992 06:48:07.930274 ==
993 06:48:07.932862 Dram Type= 6, Freq= 0, CH_0, rank 0
994 06:48:07.936192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 06:48:07.939464 ==
996 06:48:07.939889
997 06:48:07.940224
998 06:48:07.940536 TX Vref Scan disable
999 06:48:07.942970 == TX Byte 0 ==
1000 06:48:07.946688 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1001 06:48:07.949890 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1002 06:48:07.953077 == TX Byte 1 ==
1003 06:48:07.956228 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1004 06:48:07.963080 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1005 06:48:07.963518
1006 06:48:07.964015 [DATLAT]
1007 06:48:07.964475 Freq=800, CH0 RK0
1008 06:48:07.964940
1009 06:48:07.966470 DATLAT Default: 0xa
1010 06:48:07.967301 0, 0xFFFF, sum = 0
1011 06:48:07.969565 1, 0xFFFF, sum = 0
1012 06:48:07.970011 2, 0xFFFF, sum = 0
1013 06:48:07.972876 3, 0xFFFF, sum = 0
1014 06:48:07.976170 4, 0xFFFF, sum = 0
1015 06:48:07.976761 5, 0xFFFF, sum = 0
1016 06:48:07.979406 6, 0xFFFF, sum = 0
1017 06:48:07.979992 7, 0xFFFF, sum = 0
1018 06:48:07.982814 8, 0xFFFF, sum = 0
1019 06:48:07.983285 9, 0x0, sum = 1
1020 06:48:07.983848 10, 0x0, sum = 2
1021 06:48:07.986127 11, 0x0, sum = 3
1022 06:48:07.986801 12, 0x0, sum = 4
1023 06:48:07.989546 best_step = 10
1024 06:48:07.990010
1025 06:48:07.990440 ==
1026 06:48:07.992808 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 06:48:07.996173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 06:48:07.996593 ==
1029 06:48:07.999382 RX Vref Scan: 1
1030 06:48:07.999799
1031 06:48:08.000132 Set Vref Range= 32 -> 127
1032 06:48:08.003162
1033 06:48:08.003582 RX Vref 32 -> 127, step: 1
1034 06:48:08.003963
1035 06:48:08.006431 RX Delay -111 -> 252, step: 8
1036 06:48:08.006851
1037 06:48:08.009688 Set Vref, RX VrefLevel [Byte0]: 32
1038 06:48:08.013083 [Byte1]: 32
1039 06:48:08.013752
1040 06:48:08.016163 Set Vref, RX VrefLevel [Byte0]: 33
1041 06:48:08.019673 [Byte1]: 33
1042 06:48:08.023547
1043 06:48:08.023957 Set Vref, RX VrefLevel [Byte0]: 34
1044 06:48:08.026811 [Byte1]: 34
1045 06:48:08.031159
1046 06:48:08.031632 Set Vref, RX VrefLevel [Byte0]: 35
1047 06:48:08.034463 [Byte1]: 35
1048 06:48:08.038636
1049 06:48:08.039044 Set Vref, RX VrefLevel [Byte0]: 36
1050 06:48:08.042099 [Byte1]: 36
1051 06:48:08.046428
1052 06:48:08.046821 Set Vref, RX VrefLevel [Byte0]: 37
1053 06:48:08.049433 [Byte1]: 37
1054 06:48:08.053582
1055 06:48:08.053661 Set Vref, RX VrefLevel [Byte0]: 38
1056 06:48:08.057139 [Byte1]: 38
1057 06:48:08.061267
1058 06:48:08.061371 Set Vref, RX VrefLevel [Byte0]: 39
1059 06:48:08.064720 [Byte1]: 39
1060 06:48:08.069078
1061 06:48:08.069160 Set Vref, RX VrefLevel [Byte0]: 40
1062 06:48:08.072412 [Byte1]: 40
1063 06:48:08.076529
1064 06:48:08.076611 Set Vref, RX VrefLevel [Byte0]: 41
1065 06:48:08.079751 [Byte1]: 41
1066 06:48:08.084520
1067 06:48:08.084632 Set Vref, RX VrefLevel [Byte0]: 42
1068 06:48:08.087758 [Byte1]: 42
1069 06:48:08.092172
1070 06:48:08.092341 Set Vref, RX VrefLevel [Byte0]: 43
1071 06:48:08.095467 [Byte1]: 43
1072 06:48:08.099710
1073 06:48:08.099812 Set Vref, RX VrefLevel [Byte0]: 44
1074 06:48:08.102994 [Byte1]: 44
1075 06:48:08.107341
1076 06:48:08.107453 Set Vref, RX VrefLevel [Byte0]: 45
1077 06:48:08.110703 [Byte1]: 45
1078 06:48:08.115448
1079 06:48:08.115584 Set Vref, RX VrefLevel [Byte0]: 46
1080 06:48:08.118709 [Byte1]: 46
1081 06:48:08.122761
1082 06:48:08.122866 Set Vref, RX VrefLevel [Byte0]: 47
1083 06:48:08.126302 [Byte1]: 47
1084 06:48:08.130258
1085 06:48:08.130339 Set Vref, RX VrefLevel [Byte0]: 48
1086 06:48:08.133991 [Byte1]: 48
1087 06:48:08.137833
1088 06:48:08.137916 Set Vref, RX VrefLevel [Byte0]: 49
1089 06:48:08.141440 [Byte1]: 49
1090 06:48:08.145326
1091 06:48:08.145408 Set Vref, RX VrefLevel [Byte0]: 50
1092 06:48:08.148751 [Byte1]: 50
1093 06:48:08.153001
1094 06:48:08.153082 Set Vref, RX VrefLevel [Byte0]: 51
1095 06:48:08.156256 [Byte1]: 51
1096 06:48:08.160818
1097 06:48:08.160900 Set Vref, RX VrefLevel [Byte0]: 52
1098 06:48:08.164145 [Byte1]: 52
1099 06:48:08.168303
1100 06:48:08.168381 Set Vref, RX VrefLevel [Byte0]: 53
1101 06:48:08.171595 [Byte1]: 53
1102 06:48:08.176156
1103 06:48:08.176232 Set Vref, RX VrefLevel [Byte0]: 54
1104 06:48:08.179396 [Byte1]: 54
1105 06:48:08.183643
1106 06:48:08.183719 Set Vref, RX VrefLevel [Byte0]: 55
1107 06:48:08.187107 [Byte1]: 55
1108 06:48:08.191205
1109 06:48:08.191307 Set Vref, RX VrefLevel [Byte0]: 56
1110 06:48:08.194335 [Byte1]: 56
1111 06:48:08.198955
1112 06:48:08.199056 Set Vref, RX VrefLevel [Byte0]: 57
1113 06:48:08.202345 [Byte1]: 57
1114 06:48:08.206734
1115 06:48:08.206811 Set Vref, RX VrefLevel [Byte0]: 58
1116 06:48:08.209780 [Byte1]: 58
1117 06:48:08.214334
1118 06:48:08.214409 Set Vref, RX VrefLevel [Byte0]: 59
1119 06:48:08.217719 [Byte1]: 59
1120 06:48:08.221844
1121 06:48:08.221920 Set Vref, RX VrefLevel [Byte0]: 60
1122 06:48:08.225015 [Byte1]: 60
1123 06:48:08.229400
1124 06:48:08.229534 Set Vref, RX VrefLevel [Byte0]: 61
1125 06:48:08.232791 [Byte1]: 61
1126 06:48:08.237270
1127 06:48:08.237345 Set Vref, RX VrefLevel [Byte0]: 62
1128 06:48:08.240305 [Byte1]: 62
1129 06:48:08.244568
1130 06:48:08.244645 Set Vref, RX VrefLevel [Byte0]: 63
1131 06:48:08.248055 [Byte1]: 63
1132 06:48:08.252516
1133 06:48:08.252598 Set Vref, RX VrefLevel [Byte0]: 64
1134 06:48:08.255849 [Byte1]: 64
1135 06:48:08.260154
1136 06:48:08.260249 Set Vref, RX VrefLevel [Byte0]: 65
1137 06:48:08.263529 [Byte1]: 65
1138 06:48:08.267896
1139 06:48:08.267997 Set Vref, RX VrefLevel [Byte0]: 66
1140 06:48:08.271363 [Byte1]: 66
1141 06:48:08.275598
1142 06:48:08.275719 Set Vref, RX VrefLevel [Byte0]: 67
1143 06:48:08.279046 [Byte1]: 67
1144 06:48:08.283089
1145 06:48:08.283224 Set Vref, RX VrefLevel [Byte0]: 68
1146 06:48:08.286608 [Byte1]: 68
1147 06:48:08.291404
1148 06:48:08.291821 Set Vref, RX VrefLevel [Byte0]: 69
1149 06:48:08.294304 [Byte1]: 69
1150 06:48:08.299124
1151 06:48:08.299758 Set Vref, RX VrefLevel [Byte0]: 70
1152 06:48:08.302132 [Byte1]: 70
1153 06:48:08.306553
1154 06:48:08.307100 Set Vref, RX VrefLevel [Byte0]: 71
1155 06:48:08.309610 [Byte1]: 71
1156 06:48:08.313865
1157 06:48:08.314545 Set Vref, RX VrefLevel [Byte0]: 72
1158 06:48:08.317334 [Byte1]: 72
1159 06:48:08.321448
1160 06:48:08.322028 Set Vref, RX VrefLevel [Byte0]: 73
1161 06:48:08.324974 [Byte1]: 73
1162 06:48:08.329045
1163 06:48:08.329637 Set Vref, RX VrefLevel [Byte0]: 74
1164 06:48:08.332783 [Byte1]: 74
1165 06:48:08.336656
1166 06:48:08.337171 Set Vref, RX VrefLevel [Byte0]: 75
1167 06:48:08.340426 [Byte1]: 75
1168 06:48:08.344556
1169 06:48:08.345170 Set Vref, RX VrefLevel [Byte0]: 76
1170 06:48:08.347776 [Byte1]: 76
1171 06:48:08.352354
1172 06:48:08.352767 Set Vref, RX VrefLevel [Byte0]: 77
1173 06:48:08.355328 [Byte1]: 77
1174 06:48:08.359678
1175 06:48:08.360243 Set Vref, RX VrefLevel [Byte0]: 78
1176 06:48:08.363066 [Byte1]: 78
1177 06:48:08.367399
1178 06:48:08.367770 Set Vref, RX VrefLevel [Byte0]: 79
1179 06:48:08.370545 [Byte1]: 79
1180 06:48:08.374840
1181 06:48:08.375133 Final RX Vref Byte 0 = 57 to rank0
1182 06:48:08.378359 Final RX Vref Byte 1 = 59 to rank0
1183 06:48:08.381633 Final RX Vref Byte 0 = 57 to rank1
1184 06:48:08.384990 Final RX Vref Byte 1 = 59 to rank1==
1185 06:48:08.388224 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 06:48:08.394834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 06:48:08.395140 ==
1188 06:48:08.395378 DQS Delay:
1189 06:48:08.395601 DQS0 = 0, DQS1 = 0
1190 06:48:08.398296 DQM Delay:
1191 06:48:08.398619 DQM0 = 82, DQM1 = 68
1192 06:48:08.401558 DQ Delay:
1193 06:48:08.404863 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1194 06:48:08.404947 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1195 06:48:08.408020 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =64
1196 06:48:08.411391 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1197 06:48:08.414789
1198 06:48:08.414899
1199 06:48:08.421239 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1200 06:48:08.424489 CH0 RK0: MR19=606, MR18=2C2B
1201 06:48:08.431169 CH0_RK0: MR19=0x606, MR18=0x2C2B, DQSOSC=398, MR23=63, INC=93, DEC=62
1202 06:48:08.431282
1203 06:48:08.434557 ----->DramcWriteLeveling(PI) begin...
1204 06:48:08.434670 ==
1205 06:48:08.437913 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 06:48:08.441145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 06:48:08.441223 ==
1208 06:48:08.444788 Write leveling (Byte 0): 31 => 31
1209 06:48:08.447927 Write leveling (Byte 1): 30 => 30
1210 06:48:08.451129 DramcWriteLeveling(PI) end<-----
1211 06:48:08.451205
1212 06:48:08.451296 ==
1213 06:48:08.454306 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 06:48:08.457908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 06:48:08.457991 ==
1216 06:48:08.460955 [Gating] SW mode calibration
1217 06:48:08.468038 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 06:48:08.474568 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 06:48:08.478068 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 06:48:08.481257 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1221 06:48:08.487617 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 06:48:08.491070 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 06:48:08.494387 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 06:48:08.501409 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 06:48:08.504659 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 06:48:08.508117 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 06:48:08.514509 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 06:48:08.517959 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 06:48:08.521324 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 06:48:08.527844 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 06:48:08.572123 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 06:48:08.572619 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 06:48:08.572966 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 06:48:08.573703 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 06:48:08.574045 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 06:48:08.574356 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1237 06:48:08.574697 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1238 06:48:08.575162 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1239 06:48:08.575468 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 06:48:08.575756 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 06:48:08.594480 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 06:48:08.594963 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 06:48:08.595307 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 06:48:08.596126 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 06:48:08.596610 0 9 8 | B1->B0 | 2323 2d2d | 1 1 | (1 1) (1 1)
1246 06:48:08.598121 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
1247 06:48:08.601391 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 06:48:08.604720 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 06:48:08.611404 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 06:48:08.614735 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 06:48:08.618406 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 06:48:08.624839 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1253 06:48:08.627955 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
1254 06:48:08.635203 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1255 06:48:08.637968 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 06:48:08.641341 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 06:48:08.644603 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 06:48:08.651274 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 06:48:08.654867 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 06:48:08.658211 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 06:48:08.661191 0 11 8 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
1262 06:48:08.667775 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 06:48:08.671231 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 06:48:08.674466 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 06:48:08.680970 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 06:48:08.684914 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 06:48:08.688172 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 06:48:08.692217 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1269 06:48:08.699546 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1270 06:48:08.702920 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1271 06:48:08.706354 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 06:48:08.709701 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 06:48:08.717027 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 06:48:08.720084 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 06:48:08.723417 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 06:48:08.730216 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 06:48:08.733786 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 06:48:08.736790 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 06:48:08.740184 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 06:48:08.747009 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 06:48:08.750402 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 06:48:08.753601 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 06:48:08.760067 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 06:48:08.763617 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1285 06:48:08.766916 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1286 06:48:08.773462 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 06:48:08.773603 Total UI for P1: 0, mck2ui 16
1288 06:48:08.780292 best dqsien dly found for B0: ( 0, 14, 6)
1289 06:48:08.780475 Total UI for P1: 0, mck2ui 16
1290 06:48:08.786954 best dqsien dly found for B1: ( 0, 14, 8)
1291 06:48:08.790482 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1292 06:48:08.793649 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1293 06:48:08.793794
1294 06:48:08.796989 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1295 06:48:08.800544 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 06:48:08.803836 [Gating] SW calibration Done
1297 06:48:08.803975 ==
1298 06:48:08.806986 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 06:48:08.810510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 06:48:08.810692 ==
1301 06:48:08.813646 RX Vref Scan: 0
1302 06:48:08.813812
1303 06:48:08.813962 RX Vref 0 -> 0, step: 1
1304 06:48:08.814108
1305 06:48:08.817202 RX Delay -130 -> 252, step: 16
1306 06:48:08.820485 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1307 06:48:08.827250 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1308 06:48:08.830258 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
1309 06:48:08.833439 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1310 06:48:08.836871 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1311 06:48:08.840125 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1312 06:48:08.843549 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1313 06:48:08.850441 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1314 06:48:08.853940 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1315 06:48:08.856854 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1316 06:48:08.860309 iDelay=206, Bit 10, Center 61 (-66 ~ 189) 256
1317 06:48:08.863771 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1318 06:48:08.870399 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1319 06:48:08.873671 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1320 06:48:08.877046 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1321 06:48:08.880247 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1322 06:48:08.880448 ==
1323 06:48:08.883934 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 06:48:08.890400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 06:48:08.890573 ==
1326 06:48:08.890745 DQS Delay:
1327 06:48:08.893850 DQS0 = 0, DQS1 = 0
1328 06:48:08.893933 DQM Delay:
1329 06:48:08.894005 DQM0 = 76, DQM1 = 68
1330 06:48:08.897076 DQ Delay:
1331 06:48:08.900496 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =69
1332 06:48:08.903875 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1333 06:48:08.907185 DQ8 =61, DQ9 =53, DQ10 =61, DQ11 =61
1334 06:48:08.910553 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1335 06:48:08.910666
1336 06:48:08.910736
1337 06:48:08.910798 ==
1338 06:48:08.913733 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 06:48:08.917008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 06:48:08.917120 ==
1341 06:48:08.917215
1342 06:48:08.917305
1343 06:48:08.920489 TX Vref Scan disable
1344 06:48:08.920573 == TX Byte 0 ==
1345 06:48:08.927179 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1346 06:48:08.930294 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1347 06:48:08.930415 == TX Byte 1 ==
1348 06:48:08.937191 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1349 06:48:08.940371 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1350 06:48:08.940457 ==
1351 06:48:08.943767 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 06:48:08.947146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 06:48:08.947251 ==
1354 06:48:08.960933 TX Vref=22, minBit 11, minWin=26, winSum=431
1355 06:48:08.964386 TX Vref=24, minBit 1, minWin=27, winSum=437
1356 06:48:08.967305 TX Vref=26, minBit 13, minWin=26, winSum=441
1357 06:48:08.970802 TX Vref=28, minBit 1, minWin=27, winSum=442
1358 06:48:08.974270 TX Vref=30, minBit 1, minWin=27, winSum=443
1359 06:48:08.980826 TX Vref=32, minBit 11, minWin=26, winSum=446
1360 06:48:08.984223 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 30
1361 06:48:08.984315
1362 06:48:08.987719 Final TX Range 1 Vref 30
1363 06:48:08.987796
1364 06:48:08.987859 ==
1365 06:48:08.990909 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 06:48:08.994377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 06:48:08.994466 ==
1368 06:48:08.997512
1369 06:48:08.997601
1370 06:48:08.997667 TX Vref Scan disable
1371 06:48:09.001166 == TX Byte 0 ==
1372 06:48:09.004178 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1373 06:48:09.007763 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1374 06:48:09.010904 == TX Byte 1 ==
1375 06:48:09.014491 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1376 06:48:09.017859 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1377 06:48:09.021048
1378 06:48:09.021123 [DATLAT]
1379 06:48:09.021214 Freq=800, CH0 RK1
1380 06:48:09.021278
1381 06:48:09.024527 DATLAT Default: 0xa
1382 06:48:09.024599 0, 0xFFFF, sum = 0
1383 06:48:09.027961 1, 0xFFFF, sum = 0
1384 06:48:09.028054 2, 0xFFFF, sum = 0
1385 06:48:09.031295 3, 0xFFFF, sum = 0
1386 06:48:09.031382 4, 0xFFFF, sum = 0
1387 06:48:09.034654 5, 0xFFFF, sum = 0
1388 06:48:09.034753 6, 0xFFFF, sum = 0
1389 06:48:09.038076 7, 0xFFFF, sum = 0
1390 06:48:09.038170 8, 0xFFFF, sum = 0
1391 06:48:09.041404 9, 0x0, sum = 1
1392 06:48:09.041529 10, 0x0, sum = 2
1393 06:48:09.044548 11, 0x0, sum = 3
1394 06:48:09.044645 12, 0x0, sum = 4
1395 06:48:09.048129 best_step = 10
1396 06:48:09.048212
1397 06:48:09.048277 ==
1398 06:48:09.051367 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 06:48:09.054757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 06:48:09.054842 ==
1401 06:48:09.058045 RX Vref Scan: 0
1402 06:48:09.058127
1403 06:48:09.058192 RX Vref 0 -> 0, step: 1
1404 06:48:09.058253
1405 06:48:09.061072 RX Delay -111 -> 252, step: 8
1406 06:48:09.067867 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1407 06:48:09.071201 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1408 06:48:09.074582 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1409 06:48:09.077849 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1410 06:48:09.081129 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1411 06:48:09.087909 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1412 06:48:09.091302 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1413 06:48:09.094722 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1414 06:48:09.097772 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1415 06:48:09.101031 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1416 06:48:09.107736 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1417 06:48:09.111075 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1418 06:48:09.114435 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1419 06:48:09.117983 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1420 06:48:09.121248 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1421 06:48:09.127922 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1422 06:48:09.128007 ==
1423 06:48:09.131163 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 06:48:09.134742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 06:48:09.134828 ==
1426 06:48:09.134894 DQS Delay:
1427 06:48:09.137867 DQS0 = 0, DQS1 = 0
1428 06:48:09.137949 DQM Delay:
1429 06:48:09.141225 DQM0 = 79, DQM1 = 70
1430 06:48:09.141307 DQ Delay:
1431 06:48:09.144526 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1432 06:48:09.147743 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1433 06:48:09.150971 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1434 06:48:09.154435 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =80
1435 06:48:09.154522
1436 06:48:09.154588
1437 06:48:09.161138 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1438 06:48:09.164550 CH0 RK1: MR19=606, MR18=4B27
1439 06:48:09.170898 CH0_RK1: MR19=0x606, MR18=0x4B27, DQSOSC=391, MR23=63, INC=96, DEC=64
1440 06:48:09.174249 [RxdqsGatingPostProcess] freq 800
1441 06:48:09.180921 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 06:48:09.184267 Pre-setting of DQS Precalculation
1443 06:48:09.187767 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 06:48:09.187850 ==
1445 06:48:09.191154 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 06:48:09.194513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 06:48:09.194597 ==
1448 06:48:09.201096 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 06:48:09.207304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 06:48:09.216245 [CA 0] Center 36 (6~66) winsize 61
1451 06:48:09.219578 [CA 1] Center 36 (6~67) winsize 62
1452 06:48:09.223014 [CA 2] Center 34 (4~64) winsize 61
1453 06:48:09.225995 [CA 3] Center 34 (4~64) winsize 61
1454 06:48:09.229491 [CA 4] Center 34 (4~64) winsize 61
1455 06:48:09.232553 [CA 5] Center 34 (4~64) winsize 61
1456 06:48:09.232666
1457 06:48:09.236064 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1458 06:48:09.236146
1459 06:48:09.239305 [CATrainingPosCal] consider 1 rank data
1460 06:48:09.242760 u2DelayCellTimex100 = 270/100 ps
1461 06:48:09.246217 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1462 06:48:09.249362 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 06:48:09.255868 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1464 06:48:09.259277 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1465 06:48:09.262533 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1466 06:48:09.265970 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 06:48:09.266051
1468 06:48:09.269323 CA PerBit enable=1, Macro0, CA PI delay=34
1469 06:48:09.269403
1470 06:48:09.272632 [CBTSetCACLKResult] CA Dly = 34
1471 06:48:09.272712 CS Dly: 5 (0~36)
1472 06:48:09.272776 ==
1473 06:48:09.275943 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 06:48:09.282660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 06:48:09.282744 ==
1476 06:48:09.286024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 06:48:09.292784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 06:48:09.302451 [CA 0] Center 36 (6~67) winsize 62
1479 06:48:09.306107 [CA 1] Center 36 (6~67) winsize 62
1480 06:48:09.309284 [CA 2] Center 35 (5~65) winsize 61
1481 06:48:09.312538 [CA 3] Center 33 (3~64) winsize 62
1482 06:48:09.315931 [CA 4] Center 34 (4~65) winsize 62
1483 06:48:09.319363 [CA 5] Center 33 (3~64) winsize 62
1484 06:48:09.319786
1485 06:48:09.322198 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1486 06:48:09.322656
1487 06:48:09.325939 [CATrainingPosCal] consider 2 rank data
1488 06:48:09.329179 u2DelayCellTimex100 = 270/100 ps
1489 06:48:09.332470 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1490 06:48:09.338945 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 06:48:09.342296 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1492 06:48:09.345595 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1493 06:48:09.349604 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1494 06:48:09.353226 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1495 06:48:09.353797
1496 06:48:09.356922 CA PerBit enable=1, Macro0, CA PI delay=34
1497 06:48:09.357454
1498 06:48:09.360384 [CBTSetCACLKResult] CA Dly = 34
1499 06:48:09.360857 CS Dly: 6 (0~38)
1500 06:48:09.361298
1501 06:48:09.364138 ----->DramcWriteLeveling(PI) begin...
1502 06:48:09.364491 ==
1503 06:48:09.367527 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 06:48:09.371244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 06:48:09.371503 ==
1506 06:48:09.374756 Write leveling (Byte 0): 26 => 26
1507 06:48:09.378463 Write leveling (Byte 1): 32 => 32
1508 06:48:09.382072 DramcWriteLeveling(PI) end<-----
1509 06:48:09.382235
1510 06:48:09.382433 ==
1511 06:48:09.385415 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 06:48:09.388388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 06:48:09.388559 ==
1514 06:48:09.391812 [Gating] SW mode calibration
1515 06:48:09.398636 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 06:48:09.405379 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 06:48:09.408760 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 06:48:09.411874 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 06:48:09.415239 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1520 06:48:09.421656 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 06:48:09.425011 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 06:48:09.428334 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 06:48:09.435088 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 06:48:09.438365 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 06:48:09.441723 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 06:48:09.448333 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 06:48:09.451671 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 06:48:09.455066 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 06:48:09.461743 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 06:48:09.465105 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 06:48:09.468218 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 06:48:09.474967 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 06:48:09.478304 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 06:48:09.481622 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1535 06:48:09.488159 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 06:48:09.491483 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 06:48:09.494953 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 06:48:09.501415 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 06:48:09.504940 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 06:48:09.508277 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 06:48:09.514853 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 06:48:09.518281 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 06:48:09.521527 0 9 8 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (0 0)
1544 06:48:09.528271 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 06:48:09.531456 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 06:48:09.534768 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 06:48:09.538235 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 06:48:09.545000 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 06:48:09.547983 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 06:48:09.551467 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 06:48:09.558186 0 10 8 | B1->B0 | 2727 2b2b | 0 0 | (1 1) (0 0)
1552 06:48:09.561700 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 06:48:09.564901 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 06:48:09.571386 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 06:48:09.575081 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 06:48:09.578024 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 06:48:09.584699 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 06:48:09.588108 0 11 4 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
1559 06:48:09.591409 0 11 8 | B1->B0 | 3b3b 3e3d | 0 1 | (0 0) (0 0)
1560 06:48:09.598238 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 06:48:09.601472 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 06:48:09.604519 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 06:48:09.611552 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 06:48:09.614975 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 06:48:09.618286 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 06:48:09.624929 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1567 06:48:09.628341 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1568 06:48:09.631444 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 06:48:09.634725 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 06:48:09.641418 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 06:48:09.644735 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 06:48:09.648410 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 06:48:09.654968 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 06:48:09.658298 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 06:48:09.661662 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 06:48:09.668550 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 06:48:09.671806 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 06:48:09.675074 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 06:48:09.681414 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 06:48:09.685055 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 06:48:09.688256 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 06:48:09.694902 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1583 06:48:09.698196 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1584 06:48:09.701663 Total UI for P1: 0, mck2ui 16
1585 06:48:09.704988 best dqsien dly found for B1: ( 0, 14, 4)
1586 06:48:09.708143 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 06:48:09.711352 Total UI for P1: 0, mck2ui 16
1588 06:48:09.714917 best dqsien dly found for B0: ( 0, 14, 8)
1589 06:48:09.718392 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1590 06:48:09.721795 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1591 06:48:09.721880
1592 06:48:09.724769 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1593 06:48:09.731461 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1594 06:48:09.731546 [Gating] SW calibration Done
1595 06:48:09.731614 ==
1596 06:48:09.734952 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 06:48:09.741728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 06:48:09.741839 ==
1599 06:48:09.741936 RX Vref Scan: 0
1600 06:48:09.742032
1601 06:48:09.745048 RX Vref 0 -> 0, step: 1
1602 06:48:09.745159
1603 06:48:09.748397 RX Delay -130 -> 252, step: 16
1604 06:48:09.751389 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1605 06:48:09.754825 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1606 06:48:09.758300 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1607 06:48:09.761713 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1608 06:48:09.768473 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1609 06:48:09.771705 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1610 06:48:09.775024 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1611 06:48:09.778273 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1612 06:48:09.781581 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1613 06:48:09.788313 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1614 06:48:09.791738 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1615 06:48:09.794946 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1616 06:48:09.798332 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1617 06:48:09.801776 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1618 06:48:09.808111 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1619 06:48:09.811748 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1620 06:48:09.811831 ==
1621 06:48:09.814804 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 06:48:09.818416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 06:48:09.818534 ==
1624 06:48:09.821717 DQS Delay:
1625 06:48:09.821806 DQS0 = 0, DQS1 = 0
1626 06:48:09.821876 DQM Delay:
1627 06:48:09.825174 DQM0 = 81, DQM1 = 72
1628 06:48:09.825269 DQ Delay:
1629 06:48:09.828073 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1630 06:48:09.831837 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1631 06:48:09.835328 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1632 06:48:09.838493 DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77
1633 06:48:09.838608
1634 06:48:09.838713
1635 06:48:09.838805 ==
1636 06:48:09.841689 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 06:48:09.848515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 06:48:09.848673 ==
1639 06:48:09.848798
1640 06:48:09.848915
1641 06:48:09.849025 TX Vref Scan disable
1642 06:48:09.852193 == TX Byte 0 ==
1643 06:48:09.855565 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1644 06:48:09.858813 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1645 06:48:09.862085 == TX Byte 1 ==
1646 06:48:09.865543 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1647 06:48:09.872025 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1648 06:48:09.872508 ==
1649 06:48:09.875493 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 06:48:09.878858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 06:48:09.879371 ==
1652 06:48:09.891671 TX Vref=22, minBit 8, minWin=27, winSum=447
1653 06:48:09.895207 TX Vref=24, minBit 8, minWin=27, winSum=447
1654 06:48:09.898395 TX Vref=26, minBit 11, minWin=27, winSum=452
1655 06:48:09.901693 TX Vref=28, minBit 1, minWin=28, winSum=457
1656 06:48:09.905204 TX Vref=30, minBit 1, minWin=28, winSum=456
1657 06:48:09.908610 TX Vref=32, minBit 8, minWin=28, winSum=458
1658 06:48:09.915330 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1659 06:48:09.915670
1660 06:48:09.918513 Final TX Range 1 Vref 32
1661 06:48:09.918881
1662 06:48:09.919216 ==
1663 06:48:09.921985 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 06:48:09.925300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 06:48:09.925770 ==
1666 06:48:09.926142
1667 06:48:09.926493
1668 06:48:09.929198 TX Vref Scan disable
1669 06:48:09.932450 == TX Byte 0 ==
1670 06:48:09.935858 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1671 06:48:09.939116 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1672 06:48:09.942697 == TX Byte 1 ==
1673 06:48:09.945513 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1674 06:48:09.949356 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1675 06:48:09.949791
1676 06:48:09.952381 [DATLAT]
1677 06:48:09.952791 Freq=800, CH1 RK0
1678 06:48:09.953181
1679 06:48:09.955749 DATLAT Default: 0xa
1680 06:48:09.956163 0, 0xFFFF, sum = 0
1681 06:48:09.958813 1, 0xFFFF, sum = 0
1682 06:48:09.959253 2, 0xFFFF, sum = 0
1683 06:48:09.962210 3, 0xFFFF, sum = 0
1684 06:48:09.962625 4, 0xFFFF, sum = 0
1685 06:48:09.965560 5, 0xFFFF, sum = 0
1686 06:48:09.965972 6, 0xFFFF, sum = 0
1687 06:48:09.968952 7, 0xFFFF, sum = 0
1688 06:48:09.969276 8, 0xFFFF, sum = 0
1689 06:48:09.972077 9, 0x0, sum = 1
1690 06:48:09.972158 10, 0x0, sum = 2
1691 06:48:09.975508 11, 0x0, sum = 3
1692 06:48:09.975590 12, 0x0, sum = 4
1693 06:48:09.978846 best_step = 10
1694 06:48:09.978926
1695 06:48:09.978989 ==
1696 06:48:09.982378 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 06:48:09.985692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 06:48:09.985773 ==
1699 06:48:09.985837 RX Vref Scan: 1
1700 06:48:09.988928
1701 06:48:09.989008 Set Vref Range= 32 -> 127
1702 06:48:09.989072
1703 06:48:09.992296 RX Vref 32 -> 127, step: 1
1704 06:48:09.992378
1705 06:48:09.995671 RX Delay -111 -> 252, step: 8
1706 06:48:09.995781
1707 06:48:09.999037 Set Vref, RX VrefLevel [Byte0]: 32
1708 06:48:10.002570 [Byte1]: 32
1709 06:48:10.002737
1710 06:48:10.005601 Set Vref, RX VrefLevel [Byte0]: 33
1711 06:48:10.008927 [Byte1]: 33
1712 06:48:10.012015
1713 06:48:10.012143 Set Vref, RX VrefLevel [Byte0]: 34
1714 06:48:10.015450 [Byte1]: 34
1715 06:48:10.019568
1716 06:48:10.019648 Set Vref, RX VrefLevel [Byte0]: 35
1717 06:48:10.022895 [Byte1]: 35
1718 06:48:10.027403
1719 06:48:10.027488 Set Vref, RX VrefLevel [Byte0]: 36
1720 06:48:10.030783 [Byte1]: 36
1721 06:48:10.035108
1722 06:48:10.035194 Set Vref, RX VrefLevel [Byte0]: 37
1723 06:48:10.038319 [Byte1]: 37
1724 06:48:10.042737
1725 06:48:10.042860 Set Vref, RX VrefLevel [Byte0]: 38
1726 06:48:10.045826 [Byte1]: 38
1727 06:48:10.050273
1728 06:48:10.050380 Set Vref, RX VrefLevel [Byte0]: 39
1729 06:48:10.053615 [Byte1]: 39
1730 06:48:10.058080
1731 06:48:10.058188 Set Vref, RX VrefLevel [Byte0]: 40
1732 06:48:10.061319 [Byte1]: 40
1733 06:48:10.065593
1734 06:48:10.065713 Set Vref, RX VrefLevel [Byte0]: 41
1735 06:48:10.069020 [Byte1]: 41
1736 06:48:10.073097
1737 06:48:10.073220 Set Vref, RX VrefLevel [Byte0]: 42
1738 06:48:10.076453 [Byte1]: 42
1739 06:48:10.081146
1740 06:48:10.081278 Set Vref, RX VrefLevel [Byte0]: 43
1741 06:48:10.084039 [Byte1]: 43
1742 06:48:10.088624
1743 06:48:10.088860 Set Vref, RX VrefLevel [Byte0]: 44
1744 06:48:10.092002 [Byte1]: 44
1745 06:48:10.096352
1746 06:48:10.096615 Set Vref, RX VrefLevel [Byte0]: 45
1747 06:48:10.099694 [Byte1]: 45
1748 06:48:10.104086
1749 06:48:10.104374 Set Vref, RX VrefLevel [Byte0]: 46
1750 06:48:10.107459 [Byte1]: 46
1751 06:48:10.111674
1752 06:48:10.115147 Set Vref, RX VrefLevel [Byte0]: 47
1753 06:48:10.115582 [Byte1]: 47
1754 06:48:10.119431
1755 06:48:10.119966 Set Vref, RX VrefLevel [Byte0]: 48
1756 06:48:10.122538 [Byte1]: 48
1757 06:48:10.126992
1758 06:48:10.127510 Set Vref, RX VrefLevel [Byte0]: 49
1759 06:48:10.130426 [Byte1]: 49
1760 06:48:10.134573
1761 06:48:10.135044 Set Vref, RX VrefLevel [Byte0]: 50
1762 06:48:10.138016 [Byte1]: 50
1763 06:48:10.142223
1764 06:48:10.142678 Set Vref, RX VrefLevel [Byte0]: 51
1765 06:48:10.145546 [Byte1]: 51
1766 06:48:10.149915
1767 06:48:10.150296 Set Vref, RX VrefLevel [Byte0]: 52
1768 06:48:10.153360 [Byte1]: 52
1769 06:48:10.157589
1770 06:48:10.157971 Set Vref, RX VrefLevel [Byte0]: 53
1771 06:48:10.161046 [Byte1]: 53
1772 06:48:10.165262
1773 06:48:10.165696 Set Vref, RX VrefLevel [Byte0]: 54
1774 06:48:10.168804 [Byte1]: 54
1775 06:48:10.172859
1776 06:48:10.173313 Set Vref, RX VrefLevel [Byte0]: 55
1777 06:48:10.176096 [Byte1]: 55
1778 06:48:10.180735
1779 06:48:10.181168 Set Vref, RX VrefLevel [Byte0]: 56
1780 06:48:10.183931 [Byte1]: 56
1781 06:48:10.188187
1782 06:48:10.188568 Set Vref, RX VrefLevel [Byte0]: 57
1783 06:48:10.191520 [Byte1]: 57
1784 06:48:10.195740
1785 06:48:10.196122 Set Vref, RX VrefLevel [Byte0]: 58
1786 06:48:10.199081 [Byte1]: 58
1787 06:48:10.203646
1788 06:48:10.204080 Set Vref, RX VrefLevel [Byte0]: 59
1789 06:48:10.206926 [Byte1]: 59
1790 06:48:10.211167
1791 06:48:10.211548 Set Vref, RX VrefLevel [Byte0]: 60
1792 06:48:10.214575 [Byte1]: 60
1793 06:48:10.218681
1794 06:48:10.219061 Set Vref, RX VrefLevel [Byte0]: 61
1795 06:48:10.221913 [Byte1]: 61
1796 06:48:10.226422
1797 06:48:10.226899 Set Vref, RX VrefLevel [Byte0]: 62
1798 06:48:10.229565 [Byte1]: 62
1799 06:48:10.233958
1800 06:48:10.234521 Set Vref, RX VrefLevel [Byte0]: 63
1801 06:48:10.237537 [Byte1]: 63
1802 06:48:10.241789
1803 06:48:10.242175 Set Vref, RX VrefLevel [Byte0]: 64
1804 06:48:10.245112 [Byte1]: 64
1805 06:48:10.249351
1806 06:48:10.249928 Set Vref, RX VrefLevel [Byte0]: 65
1807 06:48:10.252528 [Byte1]: 65
1808 06:48:10.256861
1809 06:48:10.257412 Set Vref, RX VrefLevel [Byte0]: 66
1810 06:48:10.260238 [Byte1]: 66
1811 06:48:10.264605
1812 06:48:10.265143 Set Vref, RX VrefLevel [Byte0]: 67
1813 06:48:10.268086 [Byte1]: 67
1814 06:48:10.272215
1815 06:48:10.272713 Set Vref, RX VrefLevel [Byte0]: 68
1816 06:48:10.275685 [Byte1]: 68
1817 06:48:10.279970
1818 06:48:10.280353 Set Vref, RX VrefLevel [Byte0]: 69
1819 06:48:10.283191 [Byte1]: 69
1820 06:48:10.287591
1821 06:48:10.288138 Set Vref, RX VrefLevel [Byte0]: 70
1822 06:48:10.291000 [Byte1]: 70
1823 06:48:10.295345
1824 06:48:10.295827 Set Vref, RX VrefLevel [Byte0]: 71
1825 06:48:10.298704 [Byte1]: 71
1826 06:48:10.302948
1827 06:48:10.303511 Set Vref, RX VrefLevel [Byte0]: 72
1828 06:48:10.306339 [Byte1]: 72
1829 06:48:10.310516
1830 06:48:10.311086 Set Vref, RX VrefLevel [Byte0]: 73
1831 06:48:10.313875 [Byte1]: 73
1832 06:48:10.318143
1833 06:48:10.318791 Set Vref, RX VrefLevel [Byte0]: 74
1834 06:48:10.321536 [Byte1]: 74
1835 06:48:10.325765
1836 06:48:10.326324 Set Vref, RX VrefLevel [Byte0]: 75
1837 06:48:10.329384 [Byte1]: 75
1838 06:48:10.333343
1839 06:48:10.333848 Set Vref, RX VrefLevel [Byte0]: 76
1840 06:48:10.336890 [Byte1]: 76
1841 06:48:10.340811
1842 06:48:10.340921 Final RX Vref Byte 0 = 56 to rank0
1843 06:48:10.344324 Final RX Vref Byte 1 = 52 to rank0
1844 06:48:10.347633 Final RX Vref Byte 0 = 56 to rank1
1845 06:48:10.350652 Final RX Vref Byte 1 = 52 to rank1==
1846 06:48:10.354313 Dram Type= 6, Freq= 0, CH_1, rank 0
1847 06:48:10.360707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 06:48:10.360813 ==
1849 06:48:10.360915 DQS Delay:
1850 06:48:10.361006 DQS0 = 0, DQS1 = 0
1851 06:48:10.364170 DQM Delay:
1852 06:48:10.364253 DQM0 = 80, DQM1 = 71
1853 06:48:10.367503 DQ Delay:
1854 06:48:10.370780 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1855 06:48:10.374368 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1856 06:48:10.374455 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1857 06:48:10.380969 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1858 06:48:10.381061
1859 06:48:10.381132
1860 06:48:10.387585 [DQSOSCAuto] RK0, (LSB)MR18= 0x111b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1861 06:48:10.391007 CH1 RK0: MR19=606, MR18=111B
1862 06:48:10.397316 CH1_RK0: MR19=0x606, MR18=0x111B, DQSOSC=403, MR23=63, INC=90, DEC=60
1863 06:48:10.397437
1864 06:48:10.400977 ----->DramcWriteLeveling(PI) begin...
1865 06:48:10.401179 ==
1866 06:48:10.404230 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 06:48:10.407583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 06:48:10.407796 ==
1869 06:48:10.410929 Write leveling (Byte 0): 27 => 27
1870 06:48:10.414380 Write leveling (Byte 1): 28 => 28
1871 06:48:10.417673 DramcWriteLeveling(PI) end<-----
1872 06:48:10.417934
1873 06:48:10.418093 ==
1874 06:48:10.420820 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 06:48:10.424530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 06:48:10.424831 ==
1877 06:48:10.427596 [Gating] SW mode calibration
1878 06:48:10.434327 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1879 06:48:10.441466 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1880 06:48:10.444445 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1881 06:48:10.447862 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1882 06:48:10.454318 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1883 06:48:10.457444 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 06:48:10.460965 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 06:48:10.467833 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 06:48:10.470921 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 06:48:10.474467 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 06:48:10.481079 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 06:48:10.484392 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 06:48:10.487798 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 06:48:10.494333 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 06:48:10.497545 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 06:48:10.500840 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 06:48:10.504444 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 06:48:10.511110 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 06:48:10.514471 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 06:48:10.517892 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1898 06:48:10.524585 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1899 06:48:10.528046 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 06:48:10.531371 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 06:48:10.537531 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 06:48:10.540814 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 06:48:10.544013 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 06:48:10.550658 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 06:48:10.554094 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1906 06:48:10.557393 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1907 06:48:10.563978 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 06:48:10.567307 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 06:48:10.570872 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 06:48:10.577485 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 06:48:10.580829 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 06:48:10.584127 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 06:48:10.590866 0 10 4 | B1->B0 | 3030 2828 | 0 0 | (0 1) (0 0)
1914 06:48:10.594261 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 06:48:10.597272 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 06:48:10.600989 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 06:48:10.607314 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 06:48:10.610772 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 06:48:10.614110 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 06:48:10.620907 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1921 06:48:10.624045 0 11 4 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (0 0)
1922 06:48:10.627506 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1923 06:48:10.634121 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 06:48:10.637464 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 06:48:10.640451 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 06:48:10.647659 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 06:48:10.650862 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 06:48:10.654196 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 06:48:10.660625 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 06:48:10.664151 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1931 06:48:10.667622 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 06:48:10.674234 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 06:48:10.677813 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 06:48:10.681113 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 06:48:10.684382 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 06:48:10.690948 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 06:48:10.694047 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 06:48:10.697644 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 06:48:10.704323 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 06:48:10.707688 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 06:48:10.710963 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 06:48:10.717590 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 06:48:10.721003 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 06:48:10.724172 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 06:48:10.731102 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1946 06:48:10.734255 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1947 06:48:10.737459 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 06:48:10.740990 Total UI for P1: 0, mck2ui 16
1949 06:48:10.744230 best dqsien dly found for B0: ( 0, 14, 6)
1950 06:48:10.747550 Total UI for P1: 0, mck2ui 16
1951 06:48:10.750928 best dqsien dly found for B1: ( 0, 14, 8)
1952 06:48:10.754306 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1953 06:48:10.757705 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1954 06:48:10.757783
1955 06:48:10.760956 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1956 06:48:10.767537 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1957 06:48:10.767652 [Gating] SW calibration Done
1958 06:48:10.767758 ==
1959 06:48:10.770754 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 06:48:10.777511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 06:48:10.777625 ==
1962 06:48:10.777726 RX Vref Scan: 0
1963 06:48:10.777818
1964 06:48:10.780851 RX Vref 0 -> 0, step: 1
1965 06:48:10.780935
1966 06:48:10.784477 RX Delay -130 -> 252, step: 16
1967 06:48:10.787424 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1968 06:48:10.791062 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1969 06:48:10.794418 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1970 06:48:10.800901 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1971 06:48:10.804249 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1972 06:48:10.807524 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1973 06:48:10.810767 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1974 06:48:10.814134 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1975 06:48:10.820792 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1976 06:48:10.824373 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1977 06:48:10.827740 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1978 06:48:10.830977 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1979 06:48:10.834243 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1980 06:48:10.840794 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1981 06:48:10.844512 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1982 06:48:10.847809 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1983 06:48:10.847946 ==
1984 06:48:10.851150 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 06:48:10.854268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 06:48:10.854365 ==
1987 06:48:10.857720 DQS Delay:
1988 06:48:10.857811 DQS0 = 0, DQS1 = 0
1989 06:48:10.857877 DQM Delay:
1990 06:48:10.861204 DQM0 = 79, DQM1 = 72
1991 06:48:10.861328 DQ Delay:
1992 06:48:10.864315 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1993 06:48:10.867562 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1994 06:48:10.870811 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1995 06:48:10.874272 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1996 06:48:10.874398
1997 06:48:10.874522
1998 06:48:10.874589 ==
1999 06:48:10.877375 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 06:48:10.884086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 06:48:10.884186 ==
2002 06:48:10.884273
2003 06:48:10.884358
2004 06:48:10.884448 TX Vref Scan disable
2005 06:48:10.887966 == TX Byte 0 ==
2006 06:48:10.891360 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2007 06:48:10.898080 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2008 06:48:10.898200 == TX Byte 1 ==
2009 06:48:10.901277 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2010 06:48:10.907883 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2011 06:48:10.907979 ==
2012 06:48:10.911309 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 06:48:10.914467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 06:48:10.914579 ==
2015 06:48:10.926926 TX Vref=22, minBit 0, minWin=28, winSum=452
2016 06:48:10.930308 TX Vref=24, minBit 0, minWin=28, winSum=455
2017 06:48:10.933810 TX Vref=26, minBit 3, minWin=28, winSum=460
2018 06:48:10.936997 TX Vref=28, minBit 13, minWin=28, winSum=462
2019 06:48:10.940350 TX Vref=30, minBit 9, minWin=28, winSum=462
2020 06:48:10.947007 TX Vref=32, minBit 3, minWin=28, winSum=460
2021 06:48:10.950301 [TxChooseVref] Worse bit 13, Min win 28, Win sum 462, Final Vref 28
2022 06:48:10.950386
2023 06:48:10.953711 Final TX Range 1 Vref 28
2024 06:48:10.953796
2025 06:48:10.953862 ==
2026 06:48:10.957077 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 06:48:10.960412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 06:48:10.960541 ==
2029 06:48:10.963703
2030 06:48:10.963789
2031 06:48:10.963856 TX Vref Scan disable
2032 06:48:10.966938 == TX Byte 0 ==
2033 06:48:10.970402 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2034 06:48:10.973491 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2035 06:48:10.977104 == TX Byte 1 ==
2036 06:48:10.980398 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2037 06:48:10.983802 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2038 06:48:10.983893
2039 06:48:10.987147 [DATLAT]
2040 06:48:10.987258 Freq=800, CH1 RK1
2041 06:48:10.987369
2042 06:48:10.990742 DATLAT Default: 0xa
2043 06:48:10.990856 0, 0xFFFF, sum = 0
2044 06:48:10.993952 1, 0xFFFF, sum = 0
2045 06:48:10.994063 2, 0xFFFF, sum = 0
2046 06:48:10.997253 3, 0xFFFF, sum = 0
2047 06:48:10.997365 4, 0xFFFF, sum = 0
2048 06:48:11.000526 5, 0xFFFF, sum = 0
2049 06:48:11.000621 6, 0xFFFF, sum = 0
2050 06:48:11.003796 7, 0xFFFF, sum = 0
2051 06:48:11.003910 8, 0xFFFF, sum = 0
2052 06:48:11.007030 9, 0x0, sum = 1
2053 06:48:11.007117 10, 0x0, sum = 2
2054 06:48:11.010615 11, 0x0, sum = 3
2055 06:48:11.010708 12, 0x0, sum = 4
2056 06:48:11.013822 best_step = 10
2057 06:48:11.013908
2058 06:48:11.013975 ==
2059 06:48:11.017156 Dram Type= 6, Freq= 0, CH_1, rank 1
2060 06:48:11.020648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2061 06:48:11.020737 ==
2062 06:48:11.023942 RX Vref Scan: 0
2063 06:48:11.024025
2064 06:48:11.024091 RX Vref 0 -> 0, step: 1
2065 06:48:11.024153
2066 06:48:11.027182 RX Delay -111 -> 252, step: 8
2067 06:48:11.033760 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2068 06:48:11.037100 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2069 06:48:11.040560 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2070 06:48:11.043928 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2071 06:48:11.047163 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2072 06:48:11.053853 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2073 06:48:11.057181 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2074 06:48:11.061095 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2075 06:48:11.064183 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2076 06:48:11.067512 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2077 06:48:11.074223 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2078 06:48:11.077432 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2079 06:48:11.080873 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2080 06:48:11.084218 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2081 06:48:11.087485 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2082 06:48:11.094166 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2083 06:48:11.094416 ==
2084 06:48:11.097310 Dram Type= 6, Freq= 0, CH_1, rank 1
2085 06:48:11.100614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2086 06:48:11.100860 ==
2087 06:48:11.101030 DQS Delay:
2088 06:48:11.104184 DQS0 = 0, DQS1 = 0
2089 06:48:11.104434 DQM Delay:
2090 06:48:11.107240 DQM0 = 77, DQM1 = 73
2091 06:48:11.107510 DQ Delay:
2092 06:48:11.110798 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2093 06:48:11.114170 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2094 06:48:11.117363 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =64
2095 06:48:11.120764 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76
2096 06:48:11.120927
2097 06:48:11.121120
2098 06:48:11.127461 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2099 06:48:11.130785 CH1 RK1: MR19=606, MR18=2139
2100 06:48:11.137214 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2101 06:48:11.140588 [RxdqsGatingPostProcess] freq 800
2102 06:48:11.147092 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2103 06:48:11.150542 Pre-setting of DQS Precalculation
2104 06:48:11.154048 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2105 06:48:11.160499 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2106 06:48:11.167499 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2107 06:48:11.167712
2108 06:48:11.167888
2109 06:48:11.170497 [Calibration Summary] 1600 Mbps
2110 06:48:11.173958 CH 0, Rank 0
2111 06:48:11.174116 SW Impedance : PASS
2112 06:48:11.177263 DUTY Scan : NO K
2113 06:48:11.180592 ZQ Calibration : PASS
2114 06:48:11.180750 Jitter Meter : NO K
2115 06:48:11.183987 CBT Training : PASS
2116 06:48:11.187375 Write leveling : PASS
2117 06:48:11.187534 RX DQS gating : PASS
2118 06:48:11.190532 RX DQ/DQS(RDDQC) : PASS
2119 06:48:11.190753 TX DQ/DQS : PASS
2120 06:48:11.193824 RX DATLAT : PASS
2121 06:48:11.197134 RX DQ/DQS(Engine): PASS
2122 06:48:11.197351 TX OE : NO K
2123 06:48:11.200658 All Pass.
2124 06:48:11.200816
2125 06:48:11.200940 CH 0, Rank 1
2126 06:48:11.204100 SW Impedance : PASS
2127 06:48:11.204257 DUTY Scan : NO K
2128 06:48:11.207305 ZQ Calibration : PASS
2129 06:48:11.210914 Jitter Meter : NO K
2130 06:48:11.211085 CBT Training : PASS
2131 06:48:11.214112 Write leveling : PASS
2132 06:48:11.217094 RX DQS gating : PASS
2133 06:48:11.217252 RX DQ/DQS(RDDQC) : PASS
2134 06:48:11.220471 TX DQ/DQS : PASS
2135 06:48:11.223936 RX DATLAT : PASS
2136 06:48:11.224096 RX DQ/DQS(Engine): PASS
2137 06:48:11.227277 TX OE : NO K
2138 06:48:11.227436 All Pass.
2139 06:48:11.227562
2140 06:48:11.230806 CH 1, Rank 0
2141 06:48:11.230985 SW Impedance : PASS
2142 06:48:11.233858 DUTY Scan : NO K
2143 06:48:11.234115 ZQ Calibration : PASS
2144 06:48:11.237375 Jitter Meter : NO K
2145 06:48:11.240658 CBT Training : PASS
2146 06:48:11.240817 Write leveling : PASS
2147 06:48:11.244041 RX DQS gating : PASS
2148 06:48:11.247420 RX DQ/DQS(RDDQC) : PASS
2149 06:48:11.247638 TX DQ/DQS : PASS
2150 06:48:11.250328 RX DATLAT : PASS
2151 06:48:11.253728 RX DQ/DQS(Engine): PASS
2152 06:48:11.253940 TX OE : NO K
2153 06:48:11.257087 All Pass.
2154 06:48:11.257289
2155 06:48:11.257487 CH 1, Rank 1
2156 06:48:11.260683 SW Impedance : PASS
2157 06:48:11.260884 DUTY Scan : NO K
2158 06:48:11.263943 ZQ Calibration : PASS
2159 06:48:11.267385 Jitter Meter : NO K
2160 06:48:11.267590 CBT Training : PASS
2161 06:48:11.270388 Write leveling : PASS
2162 06:48:11.273895 RX DQS gating : PASS
2163 06:48:11.274106 RX DQ/DQS(RDDQC) : PASS
2164 06:48:11.277307 TX DQ/DQS : PASS
2165 06:48:11.277546 RX DATLAT : PASS
2166 06:48:11.280866 RX DQ/DQS(Engine): PASS
2167 06:48:11.284089 TX OE : NO K
2168 06:48:11.284303 All Pass.
2169 06:48:11.284497
2170 06:48:11.287422 DramC Write-DBI off
2171 06:48:11.287630 PER_BANK_REFRESH: Hybrid Mode
2172 06:48:11.290749 TX_TRACKING: ON
2173 06:48:11.294067 [GetDramInforAfterCalByMRR] Vendor 6.
2174 06:48:11.297393 [GetDramInforAfterCalByMRR] Revision 606.
2175 06:48:11.300353 [GetDramInforAfterCalByMRR] Revision 2 0.
2176 06:48:11.300563 MR0 0x3b3b
2177 06:48:11.303802 MR8 0x5151
2178 06:48:11.307164 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 06:48:11.307360
2180 06:48:11.307487 MR0 0x3b3b
2181 06:48:11.310510 MR8 0x5151
2182 06:48:11.313811 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2183 06:48:11.313976
2184 06:48:11.320705 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2185 06:48:11.323983 [FAST_K] Save calibration result to emmc
2186 06:48:11.330469 [FAST_K] Save calibration result to emmc
2187 06:48:11.330725 dram_init: config_dvfs: 1
2188 06:48:11.333567 dramc_set_vcore_voltage set vcore to 662500
2189 06:48:11.337153 Read voltage for 1200, 2
2190 06:48:11.337268 Vio18 = 0
2191 06:48:11.340155 Vcore = 662500
2192 06:48:11.340237 Vdram = 0
2193 06:48:11.340303 Vddq = 0
2194 06:48:11.343742 Vmddr = 0
2195 06:48:11.346897 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2196 06:48:11.353577 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2197 06:48:11.353686 MEM_TYPE=3, freq_sel=15
2198 06:48:11.357019 sv_algorithm_assistance_LP4_1600
2199 06:48:11.363370 ============ PULL DRAM RESETB DOWN ============
2200 06:48:11.366684 ========== PULL DRAM RESETB DOWN end =========
2201 06:48:11.369893 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2202 06:48:11.373411 ===================================
2203 06:48:11.377124 LPDDR4 DRAM CONFIGURATION
2204 06:48:11.380350 ===================================
2205 06:48:11.383417 EX_ROW_EN[0] = 0x0
2206 06:48:11.383529 EX_ROW_EN[1] = 0x0
2207 06:48:11.386745 LP4Y_EN = 0x0
2208 06:48:11.386825 WORK_FSP = 0x0
2209 06:48:11.390179 WL = 0x4
2210 06:48:11.390259 RL = 0x4
2211 06:48:11.393461 BL = 0x2
2212 06:48:11.393608 RPST = 0x0
2213 06:48:11.396917 RD_PRE = 0x0
2214 06:48:11.396998 WR_PRE = 0x1
2215 06:48:11.400128 WR_PST = 0x0
2216 06:48:11.400208 DBI_WR = 0x0
2217 06:48:11.403473 DBI_RD = 0x0
2218 06:48:11.403553 OTF = 0x1
2219 06:48:11.406859 ===================================
2220 06:48:11.410056 ===================================
2221 06:48:11.413402 ANA top config
2222 06:48:11.416661 ===================================
2223 06:48:11.420060 DLL_ASYNC_EN = 0
2224 06:48:11.420164 ALL_SLAVE_EN = 0
2225 06:48:11.423318 NEW_RANK_MODE = 1
2226 06:48:11.426437 DLL_IDLE_MODE = 1
2227 06:48:11.430159 LP45_APHY_COMB_EN = 1
2228 06:48:11.430280 TX_ODT_DIS = 1
2229 06:48:11.433338 NEW_8X_MODE = 1
2230 06:48:11.436683 ===================================
2231 06:48:11.439761 ===================================
2232 06:48:11.443295 data_rate = 2400
2233 06:48:11.446717 CKR = 1
2234 06:48:11.449755 DQ_P2S_RATIO = 8
2235 06:48:11.453331 ===================================
2236 06:48:11.456674 CA_P2S_RATIO = 8
2237 06:48:11.456978 DQ_CA_OPEN = 0
2238 06:48:11.460218 DQ_SEMI_OPEN = 0
2239 06:48:11.463726 CA_SEMI_OPEN = 0
2240 06:48:11.467230 CA_FULL_RATE = 0
2241 06:48:11.470402 DQ_CKDIV4_EN = 0
2242 06:48:11.470826 CA_CKDIV4_EN = 0
2243 06:48:11.473537 CA_PREDIV_EN = 0
2244 06:48:11.476957 PH8_DLY = 17
2245 06:48:11.480412 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2246 06:48:11.483480 DQ_AAMCK_DIV = 4
2247 06:48:11.487115 CA_AAMCK_DIV = 4
2248 06:48:11.487539 CA_ADMCK_DIV = 4
2249 06:48:11.490276 DQ_TRACK_CA_EN = 0
2250 06:48:11.493757 CA_PICK = 1200
2251 06:48:11.496925 CA_MCKIO = 1200
2252 06:48:11.500281 MCKIO_SEMI = 0
2253 06:48:11.503693 PLL_FREQ = 2366
2254 06:48:11.506806 DQ_UI_PI_RATIO = 32
2255 06:48:11.510181 CA_UI_PI_RATIO = 0
2256 06:48:11.513519 ===================================
2257 06:48:11.516594 ===================================
2258 06:48:11.517013 memory_type:LPDDR4
2259 06:48:11.520050 GP_NUM : 10
2260 06:48:11.520464 SRAM_EN : 1
2261 06:48:11.523305 MD32_EN : 0
2262 06:48:11.526896 ===================================
2263 06:48:11.529954 [ANA_INIT] >>>>>>>>>>>>>>
2264 06:48:11.533568 <<<<<< [CONFIGURE PHASE]: ANA_TX
2265 06:48:11.536987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2266 06:48:11.540198 ===================================
2267 06:48:11.540619 data_rate = 2400,PCW = 0X5b00
2268 06:48:11.543364 ===================================
2269 06:48:11.550175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2270 06:48:11.553552 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 06:48:11.560299 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 06:48:11.563366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2273 06:48:11.566784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2274 06:48:11.570271 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2275 06:48:11.573783 [ANA_INIT] flow start
2276 06:48:11.577025 [ANA_INIT] PLL >>>>>>>>
2277 06:48:11.577441 [ANA_INIT] PLL <<<<<<<<
2278 06:48:11.580237 [ANA_INIT] MIDPI >>>>>>>>
2279 06:48:11.583674 [ANA_INIT] MIDPI <<<<<<<<
2280 06:48:11.584196 [ANA_INIT] DLL >>>>>>>>
2281 06:48:11.587054 [ANA_INIT] DLL <<<<<<<<
2282 06:48:11.590182 [ANA_INIT] flow end
2283 06:48:11.593378 ============ LP4 DIFF to SE enter ============
2284 06:48:11.597127 ============ LP4 DIFF to SE exit ============
2285 06:48:11.600356 [ANA_INIT] <<<<<<<<<<<<<
2286 06:48:11.603554 [Flow] Enable top DCM control >>>>>
2287 06:48:11.606849 [Flow] Enable top DCM control <<<<<
2288 06:48:11.610177 Enable DLL master slave shuffle
2289 06:48:11.613558 ==============================================================
2290 06:48:11.617173 Gating Mode config
2291 06:48:11.620611 ==============================================================
2292 06:48:11.623849 Config description:
2293 06:48:11.633649 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2294 06:48:11.640590 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2295 06:48:11.643817 SELPH_MODE 0: By rank 1: By Phase
2296 06:48:11.650405 ==============================================================
2297 06:48:11.653792 GAT_TRACK_EN = 1
2298 06:48:11.657217 RX_GATING_MODE = 2
2299 06:48:11.660436 RX_GATING_TRACK_MODE = 2
2300 06:48:11.663682 SELPH_MODE = 1
2301 06:48:11.664106 PICG_EARLY_EN = 1
2302 06:48:11.666964 VALID_LAT_VALUE = 1
2303 06:48:11.673963 ==============================================================
2304 06:48:11.677348 Enter into Gating configuration >>>>
2305 06:48:11.680469 Exit from Gating configuration <<<<
2306 06:48:11.683869 Enter into DVFS_PRE_config >>>>>
2307 06:48:11.693675 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2308 06:48:11.697115 Exit from DVFS_PRE_config <<<<<
2309 06:48:11.700485 Enter into PICG configuration >>>>
2310 06:48:11.703579 Exit from PICG configuration <<<<
2311 06:48:11.707039 [RX_INPUT] configuration >>>>>
2312 06:48:11.710260 [RX_INPUT] configuration <<<<<
2313 06:48:11.713578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2314 06:48:11.720519 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2315 06:48:11.726861 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 06:48:11.733726 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 06:48:11.740284 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2318 06:48:11.743797 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2319 06:48:11.750143 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2320 06:48:11.753955 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2321 06:48:11.757263 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2322 06:48:11.760442 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2323 06:48:11.764061 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2324 06:48:11.770453 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 06:48:11.773687 ===================================
2326 06:48:11.774111 LPDDR4 DRAM CONFIGURATION
2327 06:48:11.777173 ===================================
2328 06:48:11.780411 EX_ROW_EN[0] = 0x0
2329 06:48:11.783748 EX_ROW_EN[1] = 0x0
2330 06:48:11.784161 LP4Y_EN = 0x0
2331 06:48:11.787029 WORK_FSP = 0x0
2332 06:48:11.787446 WL = 0x4
2333 06:48:11.790385 RL = 0x4
2334 06:48:11.790802 BL = 0x2
2335 06:48:11.794082 RPST = 0x0
2336 06:48:11.794569 RD_PRE = 0x0
2337 06:48:11.797391 WR_PRE = 0x1
2338 06:48:11.797911 WR_PST = 0x0
2339 06:48:11.800619 DBI_WR = 0x0
2340 06:48:11.801063 DBI_RD = 0x0
2341 06:48:11.803910 OTF = 0x1
2342 06:48:11.807317 ===================================
2343 06:48:11.810412 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2344 06:48:11.814142 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2345 06:48:11.820553 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2346 06:48:11.824060 ===================================
2347 06:48:11.824472 LPDDR4 DRAM CONFIGURATION
2348 06:48:11.826902 ===================================
2349 06:48:11.830437 EX_ROW_EN[0] = 0x10
2350 06:48:11.833781 EX_ROW_EN[1] = 0x0
2351 06:48:11.834194 LP4Y_EN = 0x0
2352 06:48:11.837196 WORK_FSP = 0x0
2353 06:48:11.837765 WL = 0x4
2354 06:48:11.840494 RL = 0x4
2355 06:48:11.840976 BL = 0x2
2356 06:48:11.843688 RPST = 0x0
2357 06:48:11.844097 RD_PRE = 0x0
2358 06:48:11.847360 WR_PRE = 0x1
2359 06:48:11.847868 WR_PST = 0x0
2360 06:48:11.850454 DBI_WR = 0x0
2361 06:48:11.850890 DBI_RD = 0x0
2362 06:48:11.853791 OTF = 0x1
2363 06:48:11.857078 ===================================
2364 06:48:11.863614 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2365 06:48:11.864065 ==
2366 06:48:11.867215 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 06:48:11.870188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 06:48:11.870668 ==
2369 06:48:11.873552 [Duty_Offset_Calibration]
2370 06:48:11.873879 B0:2 B1:0 CA:3
2371 06:48:11.874165
2372 06:48:11.876994 [DutyScan_Calibration_Flow] k_type=0
2373 06:48:11.886686
2374 06:48:11.886972 ==CLK 0==
2375 06:48:11.890025 Final CLK duty delay cell = 0
2376 06:48:11.893355 [0] MAX Duty = 5031%(X100), DQS PI = 12
2377 06:48:11.896610 [0] MIN Duty = 4906%(X100), DQS PI = 54
2378 06:48:11.896901 [0] AVG Duty = 4968%(X100)
2379 06:48:11.900286
2380 06:48:11.903652 CH0 CLK Duty spec in!! Max-Min= 125%
2381 06:48:11.906886 [DutyScan_Calibration_Flow] ====Done====
2382 06:48:11.907173
2383 06:48:11.910205 [DutyScan_Calibration_Flow] k_type=1
2384 06:48:11.925033
2385 06:48:11.925359 ==DQS 0 ==
2386 06:48:11.928499 Final DQS duty delay cell = 0
2387 06:48:11.931743 [0] MAX Duty = 5062%(X100), DQS PI = 16
2388 06:48:11.935408 [0] MIN Duty = 4907%(X100), DQS PI = 44
2389 06:48:11.938665 [0] AVG Duty = 4984%(X100)
2390 06:48:11.938969
2391 06:48:11.939198 ==DQS 1 ==
2392 06:48:11.941703 Final DQS duty delay cell = -4
2393 06:48:11.945163 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2394 06:48:11.948287 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2395 06:48:11.951684 [-4] AVG Duty = 4922%(X100)
2396 06:48:11.951977
2397 06:48:11.955101 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2398 06:48:11.955418
2399 06:48:11.958382 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2400 06:48:11.961694 [DutyScan_Calibration_Flow] ====Done====
2401 06:48:11.961982
2402 06:48:11.964846 [DutyScan_Calibration_Flow] k_type=3
2403 06:48:11.982702
2404 06:48:11.982992 ==DQM 0 ==
2405 06:48:11.986175 Final DQM duty delay cell = 0
2406 06:48:11.989402 [0] MAX Duty = 5124%(X100), DQS PI = 28
2407 06:48:11.992605 [0] MIN Duty = 4876%(X100), DQS PI = 0
2408 06:48:11.992927 [0] AVG Duty = 5000%(X100)
2409 06:48:11.996108
2410 06:48:11.996426 ==DQM 1 ==
2411 06:48:11.999361 Final DQM duty delay cell = 4
2412 06:48:12.002699 [4] MAX Duty = 5124%(X100), DQS PI = 0
2413 06:48:12.005840 [4] MIN Duty = 5031%(X100), DQS PI = 12
2414 06:48:12.006130 [4] AVG Duty = 5077%(X100)
2415 06:48:12.009508
2416 06:48:12.012905 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2417 06:48:12.013261
2418 06:48:12.016224 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2419 06:48:12.019567 [DutyScan_Calibration_Flow] ====Done====
2420 06:48:12.019921
2421 06:48:12.022611 [DutyScan_Calibration_Flow] k_type=2
2422 06:48:12.037463
2423 06:48:12.037818 ==DQ 0 ==
2424 06:48:12.040685 Final DQ duty delay cell = -4
2425 06:48:12.044187 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2426 06:48:12.047684 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2427 06:48:12.050681 [-4] AVG Duty = 4969%(X100)
2428 06:48:12.050969
2429 06:48:12.051232 ==DQ 1 ==
2430 06:48:12.054418 Final DQ duty delay cell = -4
2431 06:48:12.057701 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2432 06:48:12.060777 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2433 06:48:12.064051 [-4] AVG Duty = 4938%(X100)
2434 06:48:12.064341
2435 06:48:12.067490 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2436 06:48:12.067802
2437 06:48:12.070879 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2438 06:48:12.073941 [DutyScan_Calibration_Flow] ====Done====
2439 06:48:12.074259 ==
2440 06:48:12.077431 Dram Type= 6, Freq= 0, CH_1, rank 0
2441 06:48:12.080590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 06:48:12.080899 ==
2443 06:48:12.083817 [Duty_Offset_Calibration]
2444 06:48:12.084162 B0:1 B1:-2 CA:0
2445 06:48:12.084434
2446 06:48:12.087078 [DutyScan_Calibration_Flow] k_type=0
2447 06:48:12.098135
2448 06:48:12.098438 ==CLK 0==
2449 06:48:12.101262 Final CLK duty delay cell = 0
2450 06:48:12.104467 [0] MAX Duty = 5031%(X100), DQS PI = 18
2451 06:48:12.107760 [0] MIN Duty = 4875%(X100), DQS PI = 58
2452 06:48:12.108077 [0] AVG Duty = 4953%(X100)
2453 06:48:12.111508
2454 06:48:12.114624 CH1 CLK Duty spec in!! Max-Min= 156%
2455 06:48:12.118052 [DutyScan_Calibration_Flow] ====Done====
2456 06:48:12.118358
2457 06:48:12.121326 [DutyScan_Calibration_Flow] k_type=1
2458 06:48:12.136696
2459 06:48:12.137174 ==DQS 0 ==
2460 06:48:12.140198 Final DQS duty delay cell = -4
2461 06:48:12.143467 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2462 06:48:12.146724 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2463 06:48:12.150012 [-4] AVG Duty = 4969%(X100)
2464 06:48:12.150509
2465 06:48:12.151003 ==DQS 1 ==
2466 06:48:12.153367 Final DQS duty delay cell = 0
2467 06:48:12.156412 [0] MAX Duty = 5093%(X100), DQS PI = 0
2468 06:48:12.159794 [0] MIN Duty = 4844%(X100), DQS PI = 26
2469 06:48:12.162877 [0] AVG Duty = 4968%(X100)
2470 06:48:12.163286
2471 06:48:12.166382 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2472 06:48:12.166812
2473 06:48:12.169701 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2474 06:48:12.173012 [DutyScan_Calibration_Flow] ====Done====
2475 06:48:12.173466
2476 06:48:12.176306 [DutyScan_Calibration_Flow] k_type=3
2477 06:48:12.193253
2478 06:48:12.193701 ==DQM 0 ==
2479 06:48:12.196553 Final DQM duty delay cell = 0
2480 06:48:12.199872 [0] MAX Duty = 5000%(X100), DQS PI = 24
2481 06:48:12.203440 [0] MIN Duty = 4844%(X100), DQS PI = 54
2482 06:48:12.203948 [0] AVG Duty = 4922%(X100)
2483 06:48:12.206720
2484 06:48:12.207230 ==DQM 1 ==
2485 06:48:12.210175 Final DQM duty delay cell = 0
2486 06:48:12.213273 [0] MAX Duty = 5031%(X100), DQS PI = 20
2487 06:48:12.216599 [0] MIN Duty = 4907%(X100), DQS PI = 0
2488 06:48:12.217128 [0] AVG Duty = 4969%(X100)
2489 06:48:12.219838
2490 06:48:12.223316 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2491 06:48:12.223766
2492 06:48:12.226677 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2493 06:48:12.229874 [DutyScan_Calibration_Flow] ====Done====
2494 06:48:12.230294
2495 06:48:12.233221 [DutyScan_Calibration_Flow] k_type=2
2496 06:48:12.249563
2497 06:48:12.249985 ==DQ 0 ==
2498 06:48:12.253318 Final DQ duty delay cell = 0
2499 06:48:12.256606 [0] MAX Duty = 5093%(X100), DQS PI = 20
2500 06:48:12.259858 [0] MIN Duty = 4938%(X100), DQS PI = 54
2501 06:48:12.260285 [0] AVG Duty = 5015%(X100)
2502 06:48:12.263165
2503 06:48:12.263579 ==DQ 1 ==
2504 06:48:12.266247 Final DQ duty delay cell = 0
2505 06:48:12.269465 [0] MAX Duty = 5125%(X100), DQS PI = 36
2506 06:48:12.273114 [0] MIN Duty = 4969%(X100), DQS PI = 26
2507 06:48:12.273810 [0] AVG Duty = 5047%(X100)
2508 06:48:12.274325
2509 06:48:12.276151 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2510 06:48:12.279863
2511 06:48:12.283161 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2512 06:48:12.286220 [DutyScan_Calibration_Flow] ====Done====
2513 06:48:12.289614 nWR fixed to 30
2514 06:48:12.290027 [ModeRegInit_LP4] CH0 RK0
2515 06:48:12.292801 [ModeRegInit_LP4] CH0 RK1
2516 06:48:12.296271 [ModeRegInit_LP4] CH1 RK0
2517 06:48:12.296744 [ModeRegInit_LP4] CH1 RK1
2518 06:48:12.299369 match AC timing 7
2519 06:48:12.302761 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2520 06:48:12.309634 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2521 06:48:12.312648 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2522 06:48:12.316063 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2523 06:48:12.322813 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2524 06:48:12.323247 ==
2525 06:48:12.326183 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 06:48:12.329468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 06:48:12.329927 ==
2528 06:48:12.336362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 06:48:12.342743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2530 06:48:12.349681 [CA 0] Center 40 (10~71) winsize 62
2531 06:48:12.352928 [CA 1] Center 39 (9~70) winsize 62
2532 06:48:12.356352 [CA 2] Center 36 (6~66) winsize 61
2533 06:48:12.359621 [CA 3] Center 35 (5~66) winsize 62
2534 06:48:12.363260 [CA 4] Center 34 (4~65) winsize 62
2535 06:48:12.366462 [CA 5] Center 33 (3~63) winsize 61
2536 06:48:12.366884
2537 06:48:12.369893 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2538 06:48:12.370307
2539 06:48:12.373225 [CATrainingPosCal] consider 1 rank data
2540 06:48:12.376407 u2DelayCellTimex100 = 270/100 ps
2541 06:48:12.379943 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2542 06:48:12.383321 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2543 06:48:12.389787 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2544 06:48:12.393074 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2545 06:48:12.396355 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2546 06:48:12.399760 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2547 06:48:12.400330
2548 06:48:12.403068 CA PerBit enable=1, Macro0, CA PI delay=33
2549 06:48:12.403597
2550 06:48:12.406281 [CBTSetCACLKResult] CA Dly = 33
2551 06:48:12.406693 CS Dly: 7 (0~38)
2552 06:48:12.409635 ==
2553 06:48:12.410045 Dram Type= 6, Freq= 0, CH_0, rank 1
2554 06:48:12.416652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 06:48:12.417079 ==
2556 06:48:12.419756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2557 06:48:12.426258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2558 06:48:12.435762 [CA 0] Center 40 (10~71) winsize 62
2559 06:48:12.438941 [CA 1] Center 40 (10~70) winsize 61
2560 06:48:12.442285 [CA 2] Center 35 (5~66) winsize 62
2561 06:48:12.445902 [CA 3] Center 35 (5~66) winsize 62
2562 06:48:12.449260 [CA 4] Center 34 (4~65) winsize 62
2563 06:48:12.452320 [CA 5] Center 33 (3~63) winsize 61
2564 06:48:12.452802
2565 06:48:12.455632 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2566 06:48:12.456077
2567 06:48:12.459118 [CATrainingPosCal] consider 2 rank data
2568 06:48:12.462388 u2DelayCellTimex100 = 270/100 ps
2569 06:48:12.465722 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2570 06:48:12.472325 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2571 06:48:12.475655 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2572 06:48:12.479046 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2573 06:48:12.482291 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2574 06:48:12.485759 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2575 06:48:12.486228
2576 06:48:12.488937 CA PerBit enable=1, Macro0, CA PI delay=33
2577 06:48:12.489374
2578 06:48:12.492123 [CBTSetCACLKResult] CA Dly = 33
2579 06:48:12.495394 CS Dly: 8 (0~40)
2580 06:48:12.495813
2581 06:48:12.498861 ----->DramcWriteLeveling(PI) begin...
2582 06:48:12.499370 ==
2583 06:48:12.502391 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 06:48:12.505570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 06:48:12.506054 ==
2586 06:48:12.509181 Write leveling (Byte 0): 33 => 33
2587 06:48:12.512463 Write leveling (Byte 1): 29 => 29
2588 06:48:12.515864 DramcWriteLeveling(PI) end<-----
2589 06:48:12.516422
2590 06:48:12.516765 ==
2591 06:48:12.518874 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 06:48:12.522380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 06:48:12.522836 ==
2594 06:48:12.525632 [Gating] SW mode calibration
2595 06:48:12.532257 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2596 06:48:12.538842 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2597 06:48:12.542219 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
2598 06:48:12.545386 0 15 4 | B1->B0 | 2a2a 3232 | 0 1 | (0 0) (1 1)
2599 06:48:12.552267 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 06:48:12.555448 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 06:48:12.558900 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 06:48:12.565662 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 06:48:12.568625 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 06:48:12.572249 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2605 06:48:12.575512 1 0 0 | B1->B0 | 3434 2929 | 0 0 | (0 1) (0 0)
2606 06:48:12.582105 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2607 06:48:12.585662 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 06:48:12.588970 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 06:48:12.595773 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 06:48:12.599005 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 06:48:12.602236 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 06:48:12.608845 1 0 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2613 06:48:12.612516 1 1 0 | B1->B0 | 2b2b 3737 | 0 1 | (0 0) (0 0)
2614 06:48:12.615611 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2615 06:48:12.622222 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 06:48:12.625404 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 06:48:12.628953 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 06:48:12.635657 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 06:48:12.638954 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 06:48:12.642188 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2621 06:48:12.649068 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2622 06:48:12.652251 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 06:48:12.655445 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 06:48:12.661992 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 06:48:12.665360 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 06:48:12.668892 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 06:48:12.672266 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 06:48:12.678967 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 06:48:12.682262 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 06:48:12.685422 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 06:48:12.692143 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 06:48:12.695409 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 06:48:12.698642 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 06:48:12.705668 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 06:48:12.708844 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 06:48:12.712136 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2637 06:48:12.718693 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2638 06:48:12.719175 Total UI for P1: 0, mck2ui 16
2639 06:48:12.725809 best dqsien dly found for B0: ( 1, 3, 28)
2640 06:48:12.729028 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2641 06:48:12.732277 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2642 06:48:12.735559 Total UI for P1: 0, mck2ui 16
2643 06:48:12.738857 best dqsien dly found for B1: ( 1, 4, 2)
2644 06:48:12.742539 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2645 06:48:12.745869 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2646 06:48:12.746256
2647 06:48:12.749399 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2648 06:48:12.755679 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2649 06:48:12.756102 [Gating] SW calibration Done
2650 06:48:12.756435 ==
2651 06:48:12.759188 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 06:48:12.765600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 06:48:12.766025 ==
2654 06:48:12.766357 RX Vref Scan: 0
2655 06:48:12.766670
2656 06:48:12.768914 RX Vref 0 -> 0, step: 1
2657 06:48:12.769369
2658 06:48:12.772089 RX Delay -40 -> 252, step: 8
2659 06:48:12.775681 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2660 06:48:12.779044 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2661 06:48:12.782228 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2662 06:48:12.788874 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2663 06:48:12.792268 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2664 06:48:12.795337 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2665 06:48:12.799011 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2666 06:48:12.802268 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2667 06:48:12.805453 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2668 06:48:12.812239 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2669 06:48:12.815362 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2670 06:48:12.819125 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2671 06:48:12.822358 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2672 06:48:12.825511 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2673 06:48:12.832062 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2674 06:48:12.835697 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2675 06:48:12.836275 ==
2676 06:48:12.839089 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 06:48:12.842272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 06:48:12.842695 ==
2679 06:48:12.845700 DQS Delay:
2680 06:48:12.846147 DQS0 = 0, DQS1 = 0
2681 06:48:12.846477 DQM Delay:
2682 06:48:12.848940 DQM0 = 112, DQM1 = 102
2683 06:48:12.849419 DQ Delay:
2684 06:48:12.852243 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2685 06:48:12.855703 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2686 06:48:12.858956 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2687 06:48:12.862217 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2688 06:48:12.865413
2689 06:48:12.865878
2690 06:48:12.866312 ==
2691 06:48:12.868936 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 06:48:12.872230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 06:48:12.872671 ==
2694 06:48:12.873097
2695 06:48:12.873532
2696 06:48:12.875608 TX Vref Scan disable
2697 06:48:12.876116 == TX Byte 0 ==
2698 06:48:12.882315 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2699 06:48:12.885833 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2700 06:48:12.886309 == TX Byte 1 ==
2701 06:48:12.892483 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2702 06:48:12.895264 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2703 06:48:12.895694 ==
2704 06:48:12.899021 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 06:48:12.902418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 06:48:12.902853 ==
2707 06:48:12.914718 TX Vref=22, minBit 7, minWin=25, winSum=418
2708 06:48:12.918226 TX Vref=24, minBit 1, minWin=25, winSum=421
2709 06:48:12.921512 TX Vref=26, minBit 7, minWin=26, winSum=429
2710 06:48:12.924854 TX Vref=28, minBit 0, minWin=27, winSum=439
2711 06:48:12.928137 TX Vref=30, minBit 2, minWin=26, winSum=430
2712 06:48:12.934834 TX Vref=32, minBit 2, minWin=26, winSum=428
2713 06:48:12.938162 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 28
2714 06:48:12.938588
2715 06:48:12.941506 Final TX Range 1 Vref 28
2716 06:48:12.942012
2717 06:48:12.942449 ==
2718 06:48:12.944760 Dram Type= 6, Freq= 0, CH_0, rank 0
2719 06:48:12.947992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2720 06:48:12.948422 ==
2721 06:48:12.951356
2722 06:48:12.951964
2723 06:48:12.952416 TX Vref Scan disable
2724 06:48:12.954508 == TX Byte 0 ==
2725 06:48:12.957903 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2726 06:48:12.961258 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2727 06:48:12.964430 == TX Byte 1 ==
2728 06:48:12.968129 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2729 06:48:12.971233 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2730 06:48:12.974483
2731 06:48:12.975062 [DATLAT]
2732 06:48:12.975411 Freq=1200, CH0 RK0
2733 06:48:12.975726
2734 06:48:12.977577 DATLAT Default: 0xd
2735 06:48:12.977993 0, 0xFFFF, sum = 0
2736 06:48:12.981314 1, 0xFFFF, sum = 0
2737 06:48:12.981781 2, 0xFFFF, sum = 0
2738 06:48:12.984517 3, 0xFFFF, sum = 0
2739 06:48:12.988013 4, 0xFFFF, sum = 0
2740 06:48:12.988436 5, 0xFFFF, sum = 0
2741 06:48:12.991196 6, 0xFFFF, sum = 0
2742 06:48:12.991615 7, 0xFFFF, sum = 0
2743 06:48:12.994493 8, 0xFFFF, sum = 0
2744 06:48:12.995102 9, 0xFFFF, sum = 0
2745 06:48:12.997693 10, 0xFFFF, sum = 0
2746 06:48:12.998325 11, 0xFFFF, sum = 0
2747 06:48:13.001162 12, 0x0, sum = 1
2748 06:48:13.001936 13, 0x0, sum = 2
2749 06:48:13.008910 14, 0x0, sum = 3
2750 06:48:13.009368 15, 0x0, sum = 4
2751 06:48:13.009775 best_step = 13
2752 06:48:13.010549
2753 06:48:13.010933 ==
2754 06:48:13.011306 Dram Type= 6, Freq= 0, CH_0, rank 0
2755 06:48:13.014593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2756 06:48:13.015111 ==
2757 06:48:13.015455 RX Vref Scan: 1
2758 06:48:13.015764
2759 06:48:13.017867 Set Vref Range= 32 -> 127
2760 06:48:13.018287
2761 06:48:13.021202 RX Vref 32 -> 127, step: 1
2762 06:48:13.021671
2763 06:48:13.024514 RX Delay -37 -> 252, step: 4
2764 06:48:13.024933
2765 06:48:13.027721 Set Vref, RX VrefLevel [Byte0]: 32
2766 06:48:13.030987 [Byte1]: 32
2767 06:48:13.031213
2768 06:48:13.034162 Set Vref, RX VrefLevel [Byte0]: 33
2769 06:48:13.037643 [Byte1]: 33
2770 06:48:13.040813
2771 06:48:13.041003 Set Vref, RX VrefLevel [Byte0]: 34
2772 06:48:13.044257 [Byte1]: 34
2773 06:48:13.049133
2774 06:48:13.049308 Set Vref, RX VrefLevel [Byte0]: 35
2775 06:48:13.052638 [Byte1]: 35
2776 06:48:13.056938
2777 06:48:13.057102 Set Vref, RX VrefLevel [Byte0]: 36
2778 06:48:13.059992 [Byte1]: 36
2779 06:48:13.064911
2780 06:48:13.065087 Set Vref, RX VrefLevel [Byte0]: 37
2781 06:48:13.068167 [Byte1]: 37
2782 06:48:13.072847
2783 06:48:13.073056 Set Vref, RX VrefLevel [Byte0]: 38
2784 06:48:13.076374 [Byte1]: 38
2785 06:48:13.080926
2786 06:48:13.081168 Set Vref, RX VrefLevel [Byte0]: 39
2787 06:48:13.084152 [Byte1]: 39
2788 06:48:13.089021
2789 06:48:13.089352 Set Vref, RX VrefLevel [Byte0]: 40
2790 06:48:13.092412 [Byte1]: 40
2791 06:48:13.097067
2792 06:48:13.097517 Set Vref, RX VrefLevel [Byte0]: 41
2793 06:48:13.100382 [Byte1]: 41
2794 06:48:13.105326
2795 06:48:13.105822 Set Vref, RX VrefLevel [Byte0]: 42
2796 06:48:13.108474 [Byte1]: 42
2797 06:48:13.112978
2798 06:48:13.113455 Set Vref, RX VrefLevel [Byte0]: 43
2799 06:48:13.116221 [Byte1]: 43
2800 06:48:13.121371
2801 06:48:13.121880 Set Vref, RX VrefLevel [Byte0]: 44
2802 06:48:13.124343 [Byte1]: 44
2803 06:48:13.129125
2804 06:48:13.129717 Set Vref, RX VrefLevel [Byte0]: 45
2805 06:48:13.132368 [Byte1]: 45
2806 06:48:13.136967
2807 06:48:13.137534 Set Vref, RX VrefLevel [Byte0]: 46
2808 06:48:13.140692 [Byte1]: 46
2809 06:48:13.145303
2810 06:48:13.145943 Set Vref, RX VrefLevel [Byte0]: 47
2811 06:48:13.148253 [Byte1]: 47
2812 06:48:13.152952
2813 06:48:13.153456 Set Vref, RX VrefLevel [Byte0]: 48
2814 06:48:13.156417 [Byte1]: 48
2815 06:48:13.161006
2816 06:48:13.161566 Set Vref, RX VrefLevel [Byte0]: 49
2817 06:48:13.164203 [Byte1]: 49
2818 06:48:13.169158
2819 06:48:13.169641 Set Vref, RX VrefLevel [Byte0]: 50
2820 06:48:13.172380 [Byte1]: 50
2821 06:48:13.177224
2822 06:48:13.177727 Set Vref, RX VrefLevel [Byte0]: 51
2823 06:48:13.180273 [Byte1]: 51
2824 06:48:13.185241
2825 06:48:13.185771 Set Vref, RX VrefLevel [Byte0]: 52
2826 06:48:13.188233 [Byte1]: 52
2827 06:48:13.192963
2828 06:48:13.193410 Set Vref, RX VrefLevel [Byte0]: 53
2829 06:48:13.196309 [Byte1]: 53
2830 06:48:13.201017
2831 06:48:13.201460 Set Vref, RX VrefLevel [Byte0]: 54
2832 06:48:13.204675 [Byte1]: 54
2833 06:48:13.209053
2834 06:48:13.209501 Set Vref, RX VrefLevel [Byte0]: 55
2835 06:48:13.212359 [Byte1]: 55
2836 06:48:13.216926
2837 06:48:13.217398 Set Vref, RX VrefLevel [Byte0]: 56
2838 06:48:13.220288 [Byte1]: 56
2839 06:48:13.225311
2840 06:48:13.225806 Set Vref, RX VrefLevel [Byte0]: 57
2841 06:48:13.228543 [Byte1]: 57
2842 06:48:13.233269
2843 06:48:13.233736 Set Vref, RX VrefLevel [Byte0]: 58
2844 06:48:13.236573 [Byte1]: 58
2845 06:48:13.241229
2846 06:48:13.241682 Set Vref, RX VrefLevel [Byte0]: 59
2847 06:48:13.244501 [Byte1]: 59
2848 06:48:13.249275
2849 06:48:13.249785 Set Vref, RX VrefLevel [Byte0]: 60
2850 06:48:13.252620 [Byte1]: 60
2851 06:48:13.257055
2852 06:48:13.257534 Set Vref, RX VrefLevel [Byte0]: 61
2853 06:48:13.260545 [Byte1]: 61
2854 06:48:13.265234
2855 06:48:13.265743 Set Vref, RX VrefLevel [Byte0]: 62
2856 06:48:13.268135 [Byte1]: 62
2857 06:48:13.273154
2858 06:48:13.273681 Set Vref, RX VrefLevel [Byte0]: 63
2859 06:48:13.276401 [Byte1]: 63
2860 06:48:13.281346
2861 06:48:13.281904 Set Vref, RX VrefLevel [Byte0]: 64
2862 06:48:13.284352 [Byte1]: 64
2863 06:48:13.289172
2864 06:48:13.289812 Set Vref, RX VrefLevel [Byte0]: 65
2865 06:48:13.292227 [Byte1]: 65
2866 06:48:13.296975
2867 06:48:13.297561 Set Vref, RX VrefLevel [Byte0]: 66
2868 06:48:13.300495 [Byte1]: 66
2869 06:48:13.304871
2870 06:48:13.305596 Set Vref, RX VrefLevel [Byte0]: 67
2871 06:48:13.308503 [Byte1]: 67
2872 06:48:13.313113
2873 06:48:13.313633 Set Vref, RX VrefLevel [Byte0]: 68
2874 06:48:13.316590 [Byte1]: 68
2875 06:48:13.321208
2876 06:48:13.321772 Set Vref, RX VrefLevel [Byte0]: 69
2877 06:48:13.324703 [Byte1]: 69
2878 06:48:13.329175
2879 06:48:13.329795 Set Vref, RX VrefLevel [Byte0]: 70
2880 06:48:13.332376 [Byte1]: 70
2881 06:48:13.337371
2882 06:48:13.337908 Set Vref, RX VrefLevel [Byte0]: 71
2883 06:48:13.340588 [Byte1]: 71
2884 06:48:13.345163
2885 06:48:13.345645 Set Vref, RX VrefLevel [Byte0]: 72
2886 06:48:13.351455 [Byte1]: 72
2887 06:48:13.351900
2888 06:48:13.354856 Set Vref, RX VrefLevel [Byte0]: 73
2889 06:48:13.358451 [Byte1]: 73
2890 06:48:13.358896
2891 06:48:13.361749 Set Vref, RX VrefLevel [Byte0]: 74
2892 06:48:13.364994 [Byte1]: 74
2893 06:48:13.369082
2894 06:48:13.369586 Set Vref, RX VrefLevel [Byte0]: 75
2895 06:48:13.372474 [Byte1]: 75
2896 06:48:13.377025
2897 06:48:13.377464 Final RX Vref Byte 0 = 63 to rank0
2898 06:48:13.380239 Final RX Vref Byte 1 = 52 to rank0
2899 06:48:13.383602 Final RX Vref Byte 0 = 63 to rank1
2900 06:48:13.387337 Final RX Vref Byte 1 = 52 to rank1==
2901 06:48:13.390553 Dram Type= 6, Freq= 0, CH_0, rank 0
2902 06:48:13.397292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 06:48:13.397794 ==
2904 06:48:13.398160 DQS Delay:
2905 06:48:13.398501 DQS0 = 0, DQS1 = 0
2906 06:48:13.400575 DQM Delay:
2907 06:48:13.400954 DQM0 = 111, DQM1 = 101
2908 06:48:13.403725 DQ Delay:
2909 06:48:13.407136 DQ0 =110, DQ1 =112, DQ2 =110, DQ3 =108
2910 06:48:13.410236 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2911 06:48:13.413813 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2912 06:48:13.417252 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2913 06:48:13.417832
2914 06:48:13.418194
2915 06:48:13.423816 [DQSOSCAuto] RK0, (LSB)MR18= 0x0, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2916 06:48:13.427196 CH0 RK0: MR19=404, MR18=0
2917 06:48:13.434147 CH0_RK0: MR19=0x404, MR18=0x0, DQSOSC=410, MR23=63, INC=39, DEC=26
2918 06:48:13.434593
2919 06:48:13.437241 ----->DramcWriteLeveling(PI) begin...
2920 06:48:13.437725 ==
2921 06:48:13.440627 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 06:48:13.443925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 06:48:13.444344 ==
2924 06:48:13.447330 Write leveling (Byte 0): 33 => 33
2925 06:48:13.450539 Write leveling (Byte 1): 29 => 29
2926 06:48:13.453621 DramcWriteLeveling(PI) end<-----
2927 06:48:13.454030
2928 06:48:13.454374 ==
2929 06:48:13.457133 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 06:48:13.460593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 06:48:13.461031 ==
2932 06:48:13.463732 [Gating] SW mode calibration
2933 06:48:13.470281 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2934 06:48:13.476938 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2935 06:48:13.480203 0 15 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2936 06:48:13.486608 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2937 06:48:13.489953 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2938 06:48:13.493298 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2939 06:48:13.496670 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2940 06:48:13.503298 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2941 06:48:13.506606 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2942 06:48:13.510079 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
2943 06:48:13.516478 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2944 06:48:13.519751 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2945 06:48:13.523523 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2946 06:48:13.529954 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2947 06:48:13.533353 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2948 06:48:13.536606 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2949 06:48:13.543036 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2950 06:48:13.546559 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2951 06:48:13.549701 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
2952 06:48:13.556344 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 06:48:13.559624 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 06:48:13.563150 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2955 06:48:13.569924 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2956 06:48:13.572926 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 06:48:13.576548 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2958 06:48:13.583163 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2959 06:48:13.586354 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2960 06:48:13.589853 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2961 06:48:13.596515 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 06:48:13.599518 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 06:48:13.602832 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 06:48:13.609962 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 06:48:13.613238 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 06:48:13.616602 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 06:48:13.619653 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 06:48:13.626176 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 06:48:13.629438 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 06:48:13.633154 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 06:48:13.639471 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 06:48:13.642860 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 06:48:13.646313 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 06:48:13.653123 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2975 06:48:13.656267 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2976 06:48:13.659556 Total UI for P1: 0, mck2ui 16
2977 06:48:13.662907 best dqsien dly found for B0: ( 1, 3, 28)
2978 06:48:13.666129 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 06:48:13.669366 Total UI for P1: 0, mck2ui 16
2980 06:48:13.672977 best dqsien dly found for B1: ( 1, 3, 30)
2981 06:48:13.676583 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2982 06:48:13.679695 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2983 06:48:13.679763
2984 06:48:13.686001 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2985 06:48:13.689738 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2986 06:48:13.689824 [Gating] SW calibration Done
2987 06:48:13.692979 ==
2988 06:48:13.696186 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 06:48:13.699402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 06:48:13.699505 ==
2991 06:48:13.699571 RX Vref Scan: 0
2992 06:48:13.699632
2993 06:48:13.702789 RX Vref 0 -> 0, step: 1
2994 06:48:13.702872
2995 06:48:13.706107 RX Delay -40 -> 252, step: 8
2996 06:48:13.709345 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2997 06:48:13.713080 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2998 06:48:13.719620 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2999 06:48:13.722738 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3000 06:48:13.726002 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3001 06:48:13.729649 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
3002 06:48:13.732875 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3003 06:48:13.736069 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3004 06:48:13.742519 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3005 06:48:13.746000 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
3006 06:48:13.749373 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3007 06:48:13.752723 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3008 06:48:13.756135 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
3009 06:48:13.762475 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3010 06:48:13.765973 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3011 06:48:13.769178 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
3012 06:48:13.769253 ==
3013 06:48:13.772435 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 06:48:13.775728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 06:48:13.775806 ==
3016 06:48:13.779403 DQS Delay:
3017 06:48:13.779476 DQS0 = 0, DQS1 = 0
3018 06:48:13.782723 DQM Delay:
3019 06:48:13.782795 DQM0 = 111, DQM1 = 101
3020 06:48:13.782855 DQ Delay:
3021 06:48:13.789427 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3022 06:48:13.792462 DQ4 =111, DQ5 =99, DQ6 =119, DQ7 =123
3023 06:48:13.795792 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3024 06:48:13.799404 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
3025 06:48:13.799482
3026 06:48:13.799544
3027 06:48:13.799607 ==
3028 06:48:13.802807 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 06:48:13.806035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 06:48:13.806139 ==
3031 06:48:13.806231
3032 06:48:13.806323
3033 06:48:13.809273 TX Vref Scan disable
3034 06:48:13.809369 == TX Byte 0 ==
3035 06:48:13.815890 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3036 06:48:13.819124 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3037 06:48:13.819198 == TX Byte 1 ==
3038 06:48:13.826038 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3039 06:48:13.829430 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3040 06:48:13.829535 ==
3041 06:48:13.832790 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 06:48:13.836121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 06:48:13.836193 ==
3044 06:48:13.849084 TX Vref=22, minBit 1, minWin=25, winSum=422
3045 06:48:13.852256 TX Vref=24, minBit 1, minWin=26, winSum=431
3046 06:48:13.855675 TX Vref=26, minBit 7, minWin=26, winSum=434
3047 06:48:13.859056 TX Vref=28, minBit 8, minWin=25, winSum=437
3048 06:48:13.862372 TX Vref=30, minBit 1, minWin=27, winSum=441
3049 06:48:13.865647 TX Vref=32, minBit 1, minWin=27, winSum=442
3050 06:48:13.872473 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 32
3051 06:48:13.872552
3052 06:48:13.875936 Final TX Range 1 Vref 32
3053 06:48:13.876011
3054 06:48:13.876075 ==
3055 06:48:13.879268 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 06:48:13.882550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 06:48:13.882620 ==
3058 06:48:13.882679
3059 06:48:13.885906
3060 06:48:13.885976 TX Vref Scan disable
3061 06:48:13.889243 == TX Byte 0 ==
3062 06:48:13.892524 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3063 06:48:13.895908 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3064 06:48:13.899149 == TX Byte 1 ==
3065 06:48:13.902453 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3066 06:48:13.905646 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3067 06:48:13.905745
3068 06:48:13.909111 [DATLAT]
3069 06:48:13.909216 Freq=1200, CH0 RK1
3070 06:48:13.909305
3071 06:48:13.912430 DATLAT Default: 0xd
3072 06:48:13.912527 0, 0xFFFF, sum = 0
3073 06:48:13.915524 1, 0xFFFF, sum = 0
3074 06:48:13.915601 2, 0xFFFF, sum = 0
3075 06:48:13.918908 3, 0xFFFF, sum = 0
3076 06:48:13.918986 4, 0xFFFF, sum = 0
3077 06:48:13.922561 5, 0xFFFF, sum = 0
3078 06:48:13.922632 6, 0xFFFF, sum = 0
3079 06:48:13.925820 7, 0xFFFF, sum = 0
3080 06:48:13.929137 8, 0xFFFF, sum = 0
3081 06:48:13.929235 9, 0xFFFF, sum = 0
3082 06:48:13.932472 10, 0xFFFF, sum = 0
3083 06:48:13.932556 11, 0xFFFF, sum = 0
3084 06:48:13.935870 12, 0x0, sum = 1
3085 06:48:13.935953 13, 0x0, sum = 2
3086 06:48:13.939173 14, 0x0, sum = 3
3087 06:48:13.939255 15, 0x0, sum = 4
3088 06:48:13.939321 best_step = 13
3089 06:48:13.939381
3090 06:48:13.942437 ==
3091 06:48:13.942514 Dram Type= 6, Freq= 0, CH_0, rank 1
3092 06:48:13.948979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 06:48:13.949055 ==
3094 06:48:13.949116 RX Vref Scan: 0
3095 06:48:13.949174
3096 06:48:13.952607 RX Vref 0 -> 0, step: 1
3097 06:48:13.952675
3098 06:48:13.955967 RX Delay -37 -> 252, step: 4
3099 06:48:13.959096 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3100 06:48:13.965817 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3101 06:48:13.969104 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3102 06:48:13.972587 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3103 06:48:13.975911 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3104 06:48:13.979119 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3105 06:48:13.982575 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3106 06:48:13.988993 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3107 06:48:13.992309 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3108 06:48:13.995646 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3109 06:48:13.999286 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3110 06:48:14.002400 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3111 06:48:14.009282 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3112 06:48:14.012617 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3113 06:48:14.015935 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3114 06:48:14.019126 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3115 06:48:14.019224 ==
3116 06:48:14.022496 Dram Type= 6, Freq= 0, CH_0, rank 1
3117 06:48:14.028938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 06:48:14.029013 ==
3119 06:48:14.029075 DQS Delay:
3120 06:48:14.029133 DQS0 = 0, DQS1 = 0
3121 06:48:14.032546 DQM Delay:
3122 06:48:14.032616 DQM0 = 111, DQM1 = 101
3123 06:48:14.035672 DQ Delay:
3124 06:48:14.039049 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3125 06:48:14.042808 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3126 06:48:14.045703 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =92
3127 06:48:14.049417 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3128 06:48:14.049522
3129 06:48:14.049587
3130 06:48:14.055954 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3131 06:48:14.059196 CH0 RK1: MR19=403, MR18=13FB
3132 06:48:14.065816 CH0_RK1: MR19=0x403, MR18=0x13FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3133 06:48:14.069111 [RxdqsGatingPostProcess] freq 1200
3134 06:48:14.075841 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3135 06:48:14.079121 best DQS0 dly(2T, 0.5T) = (0, 11)
3136 06:48:14.079222 best DQS1 dly(2T, 0.5T) = (0, 12)
3137 06:48:14.082378 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3138 06:48:14.085831 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3139 06:48:14.089096 best DQS0 dly(2T, 0.5T) = (0, 11)
3140 06:48:14.092327 best DQS1 dly(2T, 0.5T) = (0, 11)
3141 06:48:14.095975 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3142 06:48:14.099089 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3143 06:48:14.102587 Pre-setting of DQS Precalculation
3144 06:48:14.109038 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3145 06:48:14.109119 ==
3146 06:48:14.112395 Dram Type= 6, Freq= 0, CH_1, rank 0
3147 06:48:14.115842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3148 06:48:14.115918 ==
3149 06:48:14.122182 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3150 06:48:14.125531 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3151 06:48:14.135207 [CA 0] Center 37 (7~67) winsize 61
3152 06:48:14.138469 [CA 1] Center 37 (7~68) winsize 62
3153 06:48:14.142027 [CA 2] Center 34 (4~64) winsize 61
3154 06:48:14.145080 [CA 3] Center 33 (3~64) winsize 62
3155 06:48:14.148432 [CA 4] Center 34 (4~64) winsize 61
3156 06:48:14.151696 [CA 5] Center 33 (3~63) winsize 61
3157 06:48:14.151784
3158 06:48:14.155077 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3159 06:48:14.155154
3160 06:48:14.158696 [CATrainingPosCal] consider 1 rank data
3161 06:48:14.161959 u2DelayCellTimex100 = 270/100 ps
3162 06:48:14.165257 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3163 06:48:14.168542 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3164 06:48:14.175273 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3165 06:48:14.178404 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3166 06:48:14.182024 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3167 06:48:14.185232 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3168 06:48:14.185325
3169 06:48:14.188297 CA PerBit enable=1, Macro0, CA PI delay=33
3170 06:48:14.188372
3171 06:48:14.191839 [CBTSetCACLKResult] CA Dly = 33
3172 06:48:14.191916 CS Dly: 5 (0~36)
3173 06:48:14.194971 ==
3174 06:48:14.195094 Dram Type= 6, Freq= 0, CH_1, rank 1
3175 06:48:14.201829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 06:48:14.201906 ==
3177 06:48:14.205202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3178 06:48:14.211466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3179 06:48:14.220949 [CA 0] Center 37 (7~67) winsize 61
3180 06:48:14.224299 [CA 1] Center 37 (7~68) winsize 62
3181 06:48:14.227552 [CA 2] Center 34 (4~65) winsize 62
3182 06:48:14.230898 [CA 3] Center 33 (3~64) winsize 62
3183 06:48:14.234223 [CA 4] Center 34 (4~65) winsize 62
3184 06:48:14.237565 [CA 5] Center 33 (3~63) winsize 61
3185 06:48:14.237637
3186 06:48:14.240824 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3187 06:48:14.240893
3188 06:48:14.244174 [CATrainingPosCal] consider 2 rank data
3189 06:48:14.247523 u2DelayCellTimex100 = 270/100 ps
3190 06:48:14.250702 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3191 06:48:14.254180 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3192 06:48:14.260843 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3193 06:48:14.264190 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3194 06:48:14.267338 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3195 06:48:14.270830 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3196 06:48:14.270907
3197 06:48:14.274036 CA PerBit enable=1, Macro0, CA PI delay=33
3198 06:48:14.274115
3199 06:48:14.277367 [CBTSetCACLKResult] CA Dly = 33
3200 06:48:14.277443 CS Dly: 6 (0~39)
3201 06:48:14.277529
3202 06:48:14.280749 ----->DramcWriteLeveling(PI) begin...
3203 06:48:14.284096 ==
3204 06:48:14.287534 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 06:48:14.290918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 06:48:14.290996 ==
3207 06:48:14.294019 Write leveling (Byte 0): 25 => 25
3208 06:48:14.297496 Write leveling (Byte 1): 27 => 27
3209 06:48:14.300923 DramcWriteLeveling(PI) end<-----
3210 06:48:14.300996
3211 06:48:14.301065 ==
3212 06:48:14.304213 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 06:48:14.307405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 06:48:14.307482 ==
3215 06:48:14.310838 [Gating] SW mode calibration
3216 06:48:14.317501 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3217 06:48:14.320670 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3218 06:48:14.327480 0 15 0 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)
3219 06:48:14.330767 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3220 06:48:14.334016 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3221 06:48:14.340637 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3222 06:48:14.344450 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3223 06:48:14.347789 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3224 06:48:14.354236 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3225 06:48:14.357497 0 15 28 | B1->B0 | 2c2c 3030 | 0 0 | (0 0) (0 0)
3226 06:48:14.360742 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3227 06:48:14.367749 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3228 06:48:14.371041 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3229 06:48:14.374040 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3230 06:48:14.380889 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3231 06:48:14.384130 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3232 06:48:14.387678 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3233 06:48:14.390774 1 0 28 | B1->B0 | 3f3f 3635 | 1 1 | (0 0) (0 0)
3234 06:48:14.397727 1 1 0 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
3235 06:48:14.400915 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3236 06:48:14.404455 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 06:48:14.410875 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 06:48:14.414542 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 06:48:14.417507 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3240 06:48:14.424436 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 06:48:14.427769 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3242 06:48:14.431164 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 06:48:14.437743 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 06:48:14.440960 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 06:48:14.444441 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 06:48:14.450897 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 06:48:14.454262 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 06:48:14.457617 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 06:48:14.464139 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 06:48:14.467513 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 06:48:14.470772 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 06:48:14.477785 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 06:48:14.480735 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 06:48:14.484077 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 06:48:14.487619 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 06:48:14.494222 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 06:48:14.497472 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3258 06:48:14.501051 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3259 06:48:14.504213 Total UI for P1: 0, mck2ui 16
3260 06:48:14.507443 best dqsien dly found for B0: ( 1, 3, 28)
3261 06:48:14.510997 Total UI for P1: 0, mck2ui 16
3262 06:48:14.514022 best dqsien dly found for B1: ( 1, 3, 28)
3263 06:48:14.517576 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3264 06:48:14.520994 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3265 06:48:14.521076
3266 06:48:14.527497 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3267 06:48:14.530758 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3268 06:48:14.534042 [Gating] SW calibration Done
3269 06:48:14.534119 ==
3270 06:48:14.537400 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 06:48:14.540660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 06:48:14.540743 ==
3273 06:48:14.540807 RX Vref Scan: 0
3274 06:48:14.540867
3275 06:48:14.544269 RX Vref 0 -> 0, step: 1
3276 06:48:14.544352
3277 06:48:14.547499 RX Delay -40 -> 252, step: 8
3278 06:48:14.550792 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3279 06:48:14.554075 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3280 06:48:14.560566 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3281 06:48:14.564165 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3282 06:48:14.567418 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3283 06:48:14.570820 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3284 06:48:14.574059 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3285 06:48:14.580654 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3286 06:48:14.583970 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3287 06:48:14.587191 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3288 06:48:14.590512 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3289 06:48:14.593814 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3290 06:48:14.600670 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3291 06:48:14.603822 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3292 06:48:14.607396 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3293 06:48:14.610721 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3294 06:48:14.610798 ==
3295 06:48:14.613976 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 06:48:14.617507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 06:48:14.620520 ==
3298 06:48:14.620602 DQS Delay:
3299 06:48:14.620667 DQS0 = 0, DQS1 = 0
3300 06:48:14.624159 DQM Delay:
3301 06:48:14.624233 DQM0 = 115, DQM1 = 106
3302 06:48:14.627433 DQ Delay:
3303 06:48:14.630701 DQ0 =123, DQ1 =111, DQ2 =99, DQ3 =115
3304 06:48:14.633987 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3305 06:48:14.637303 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3306 06:48:14.640736 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3307 06:48:14.640819
3308 06:48:14.640884
3309 06:48:14.640943 ==
3310 06:48:14.644084 Dram Type= 6, Freq= 0, CH_1, rank 0
3311 06:48:14.647392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3312 06:48:14.647475 ==
3313 06:48:14.647539
3314 06:48:14.647599
3315 06:48:14.650772 TX Vref Scan disable
3316 06:48:14.654198 == TX Byte 0 ==
3317 06:48:14.657462 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3318 06:48:14.660862 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3319 06:48:14.664309 == TX Byte 1 ==
3320 06:48:14.667571 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3321 06:48:14.670800 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3322 06:48:14.670890 ==
3323 06:48:14.674197 Dram Type= 6, Freq= 0, CH_1, rank 0
3324 06:48:14.677428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3325 06:48:14.680554 ==
3326 06:48:14.690532 TX Vref=22, minBit 8, minWin=25, winSum=409
3327 06:48:14.693789 TX Vref=24, minBit 11, minWin=24, winSum=409
3328 06:48:14.697357 TX Vref=26, minBit 9, minWin=25, winSum=418
3329 06:48:14.700774 TX Vref=28, minBit 12, minWin=25, winSum=422
3330 06:48:14.704149 TX Vref=30, minBit 9, minWin=25, winSum=419
3331 06:48:14.710825 TX Vref=32, minBit 9, minWin=24, winSum=418
3332 06:48:14.714075 [TxChooseVref] Worse bit 12, Min win 25, Win sum 422, Final Vref 28
3333 06:48:14.714158
3334 06:48:14.717355 Final TX Range 1 Vref 28
3335 06:48:14.717471
3336 06:48:14.717553 ==
3337 06:48:14.720594 Dram Type= 6, Freq= 0, CH_1, rank 0
3338 06:48:14.723949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3339 06:48:14.724043 ==
3340 06:48:14.727248
3341 06:48:14.727330
3342 06:48:14.727395 TX Vref Scan disable
3343 06:48:14.730773 == TX Byte 0 ==
3344 06:48:14.734023 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3345 06:48:14.737192 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3346 06:48:14.740609 == TX Byte 1 ==
3347 06:48:14.743995 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3348 06:48:14.747588 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3349 06:48:14.750700
3350 06:48:14.750782 [DATLAT]
3351 06:48:14.750848 Freq=1200, CH1 RK0
3352 06:48:14.750909
3353 06:48:14.754050 DATLAT Default: 0xd
3354 06:48:14.754132 0, 0xFFFF, sum = 0
3355 06:48:14.757293 1, 0xFFFF, sum = 0
3356 06:48:14.757378 2, 0xFFFF, sum = 0
3357 06:48:14.760503 3, 0xFFFF, sum = 0
3358 06:48:14.760587 4, 0xFFFF, sum = 0
3359 06:48:14.763803 5, 0xFFFF, sum = 0
3360 06:48:14.767554 6, 0xFFFF, sum = 0
3361 06:48:14.767639 7, 0xFFFF, sum = 0
3362 06:48:14.770805 8, 0xFFFF, sum = 0
3363 06:48:14.770889 9, 0xFFFF, sum = 0
3364 06:48:14.774314 10, 0xFFFF, sum = 0
3365 06:48:14.774461 11, 0xFFFF, sum = 0
3366 06:48:14.777248 12, 0x0, sum = 1
3367 06:48:14.777384 13, 0x0, sum = 2
3368 06:48:14.780855 14, 0x0, sum = 3
3369 06:48:14.780951 15, 0x0, sum = 4
3370 06:48:14.781029 best_step = 13
3371 06:48:14.781102
3372 06:48:14.784187 ==
3373 06:48:14.787565 Dram Type= 6, Freq= 0, CH_1, rank 0
3374 06:48:14.790842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3375 06:48:14.790925 ==
3376 06:48:14.790991 RX Vref Scan: 1
3377 06:48:14.791051
3378 06:48:14.794141 Set Vref Range= 32 -> 127
3379 06:48:14.794228
3380 06:48:14.797308 RX Vref 32 -> 127, step: 1
3381 06:48:14.797405
3382 06:48:14.800511 RX Delay -21 -> 252, step: 4
3383 06:48:14.800593
3384 06:48:14.803832 Set Vref, RX VrefLevel [Byte0]: 32
3385 06:48:14.807203 [Byte1]: 32
3386 06:48:14.807289
3387 06:48:14.810936 Set Vref, RX VrefLevel [Byte0]: 33
3388 06:48:14.814201 [Byte1]: 33
3389 06:48:14.814281
3390 06:48:14.817237 Set Vref, RX VrefLevel [Byte0]: 34
3391 06:48:14.820536 [Byte1]: 34
3392 06:48:14.825176
3393 06:48:14.825292 Set Vref, RX VrefLevel [Byte0]: 35
3394 06:48:14.828173 [Byte1]: 35
3395 06:48:14.833068
3396 06:48:14.833187 Set Vref, RX VrefLevel [Byte0]: 36
3397 06:48:14.836241 [Byte1]: 36
3398 06:48:14.840774
3399 06:48:14.840854 Set Vref, RX VrefLevel [Byte0]: 37
3400 06:48:14.844281 [Byte1]: 37
3401 06:48:14.848694
3402 06:48:14.848805 Set Vref, RX VrefLevel [Byte0]: 38
3403 06:48:14.852174 [Byte1]: 38
3404 06:48:14.856694
3405 06:48:14.856774 Set Vref, RX VrefLevel [Byte0]: 39
3406 06:48:14.859914 [Byte1]: 39
3407 06:48:14.864738
3408 06:48:14.864820 Set Vref, RX VrefLevel [Byte0]: 40
3409 06:48:14.867766 [Byte1]: 40
3410 06:48:14.872538
3411 06:48:14.872623 Set Vref, RX VrefLevel [Byte0]: 41
3412 06:48:14.875744 [Byte1]: 41
3413 06:48:14.880399
3414 06:48:14.880479 Set Vref, RX VrefLevel [Byte0]: 42
3415 06:48:14.883550 [Byte1]: 42
3416 06:48:14.888248
3417 06:48:14.888329 Set Vref, RX VrefLevel [Byte0]: 43
3418 06:48:14.891544 [Byte1]: 43
3419 06:48:14.896095
3420 06:48:14.896176 Set Vref, RX VrefLevel [Byte0]: 44
3421 06:48:14.899403 [Byte1]: 44
3422 06:48:14.904097
3423 06:48:14.904179 Set Vref, RX VrefLevel [Byte0]: 45
3424 06:48:14.907342 [Byte1]: 45
3425 06:48:14.911969
3426 06:48:14.912050 Set Vref, RX VrefLevel [Byte0]: 46
3427 06:48:14.915578 [Byte1]: 46
3428 06:48:14.919995
3429 06:48:14.920076 Set Vref, RX VrefLevel [Byte0]: 47
3430 06:48:14.923154 [Byte1]: 47
3431 06:48:14.928113
3432 06:48:14.928221 Set Vref, RX VrefLevel [Byte0]: 48
3433 06:48:14.931428 [Byte1]: 48
3434 06:48:14.935928
3435 06:48:14.936034 Set Vref, RX VrefLevel [Byte0]: 49
3436 06:48:14.939125 [Byte1]: 49
3437 06:48:14.943628
3438 06:48:14.943732 Set Vref, RX VrefLevel [Byte0]: 50
3439 06:48:14.947211 [Byte1]: 50
3440 06:48:14.951615
3441 06:48:14.951713 Set Vref, RX VrefLevel [Byte0]: 51
3442 06:48:14.955208 [Byte1]: 51
3443 06:48:14.959493
3444 06:48:14.959602 Set Vref, RX VrefLevel [Byte0]: 52
3445 06:48:14.962896 [Byte1]: 52
3446 06:48:14.967443
3447 06:48:14.967523 Set Vref, RX VrefLevel [Byte0]: 53
3448 06:48:14.970824 [Byte1]: 53
3449 06:48:14.975740
3450 06:48:14.975823 Set Vref, RX VrefLevel [Byte0]: 54
3451 06:48:14.978876 [Byte1]: 54
3452 06:48:14.983418
3453 06:48:14.983497 Set Vref, RX VrefLevel [Byte0]: 55
3454 06:48:14.986752 [Byte1]: 55
3455 06:48:14.991188
3456 06:48:14.991265 Set Vref, RX VrefLevel [Byte0]: 56
3457 06:48:14.994498 [Byte1]: 56
3458 06:48:14.999268
3459 06:48:14.999371 Set Vref, RX VrefLevel [Byte0]: 57
3460 06:48:15.002410 [Byte1]: 57
3461 06:48:15.007162
3462 06:48:15.007264 Set Vref, RX VrefLevel [Byte0]: 58
3463 06:48:15.010316 [Byte1]: 58
3464 06:48:15.014966
3465 06:48:15.015049 Set Vref, RX VrefLevel [Byte0]: 59
3466 06:48:15.018460 [Byte1]: 59
3467 06:48:15.022847
3468 06:48:15.022925 Set Vref, RX VrefLevel [Byte0]: 60
3469 06:48:15.026193 [Byte1]: 60
3470 06:48:15.030896
3471 06:48:15.030974 Set Vref, RX VrefLevel [Byte0]: 61
3472 06:48:15.034168 [Byte1]: 61
3473 06:48:15.038693
3474 06:48:15.038777 Set Vref, RX VrefLevel [Byte0]: 62
3475 06:48:15.042304 [Byte1]: 62
3476 06:48:15.046726
3477 06:48:15.046809 Set Vref, RX VrefLevel [Byte0]: 63
3478 06:48:15.049983 [Byte1]: 63
3479 06:48:15.054808
3480 06:48:15.054890 Set Vref, RX VrefLevel [Byte0]: 64
3481 06:48:15.058152 [Byte1]: 64
3482 06:48:15.062786
3483 06:48:15.062868 Set Vref, RX VrefLevel [Byte0]: 65
3484 06:48:15.066010 [Byte1]: 65
3485 06:48:15.070455
3486 06:48:15.070537 Set Vref, RX VrefLevel [Byte0]: 66
3487 06:48:15.073701 [Byte1]: 66
3488 06:48:15.078293
3489 06:48:15.078366 Final RX Vref Byte 0 = 54 to rank0
3490 06:48:15.081998 Final RX Vref Byte 1 = 52 to rank0
3491 06:48:15.085215 Final RX Vref Byte 0 = 54 to rank1
3492 06:48:15.088555 Final RX Vref Byte 1 = 52 to rank1==
3493 06:48:15.091802 Dram Type= 6, Freq= 0, CH_1, rank 0
3494 06:48:15.098270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 06:48:15.098353 ==
3496 06:48:15.098418 DQS Delay:
3497 06:48:15.098479 DQS0 = 0, DQS1 = 0
3498 06:48:15.101720 DQM Delay:
3499 06:48:15.101799 DQM0 = 114, DQM1 = 106
3500 06:48:15.104861 DQ Delay:
3501 06:48:15.108263 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =110
3502 06:48:15.111907 DQ4 =112, DQ5 =122, DQ6 =128, DQ7 =112
3503 06:48:15.115042 DQ8 =94, DQ9 =100, DQ10 =104, DQ11 =100
3504 06:48:15.118549 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =112
3505 06:48:15.118663
3506 06:48:15.118758
3507 06:48:15.124889 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 416 ps
3508 06:48:15.128401 CH1 RK0: MR19=303, MR18=F0F6
3509 06:48:15.135356 CH1_RK0: MR19=0x303, MR18=0xF0F6, DQSOSC=414, MR23=63, INC=38, DEC=25
3510 06:48:15.135439
3511 06:48:15.138359 ----->DramcWriteLeveling(PI) begin...
3512 06:48:15.138441 ==
3513 06:48:15.141928 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 06:48:15.145124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 06:48:15.148683 ==
3516 06:48:15.148790 Write leveling (Byte 0): 26 => 26
3517 06:48:15.151969 Write leveling (Byte 1): 26 => 26
3518 06:48:15.155132 DramcWriteLeveling(PI) end<-----
3519 06:48:15.155209
3520 06:48:15.155273 ==
3521 06:48:15.158417 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 06:48:15.165021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 06:48:15.165109 ==
3524 06:48:15.165197 [Gating] SW mode calibration
3525 06:48:15.174937 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3526 06:48:15.178726 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3527 06:48:15.181935 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3528 06:48:15.188212 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 06:48:15.191806 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 06:48:15.195122 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3531 06:48:15.201640 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3532 06:48:15.204974 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3533 06:48:15.208521 0 15 24 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
3534 06:48:15.215188 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3535 06:48:15.218223 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 06:48:15.221721 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 06:48:15.228247 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 06:48:15.231823 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3539 06:48:15.235167 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3540 06:48:15.241847 1 0 20 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
3541 06:48:15.244968 1 0 24 | B1->B0 | 2929 4545 | 0 0 | (1 1) (0 0)
3542 06:48:15.248313 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3543 06:48:15.254866 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 06:48:15.258255 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 06:48:15.261507 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 06:48:15.268145 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 06:48:15.271399 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 06:48:15.274978 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 06:48:15.281466 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3550 06:48:15.284749 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3551 06:48:15.288084 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 06:48:15.294673 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 06:48:15.297911 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 06:48:15.301200 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 06:48:15.307876 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 06:48:15.311260 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 06:48:15.314551 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 06:48:15.318106 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 06:48:15.324696 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 06:48:15.328045 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 06:48:15.331365 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 06:48:15.337918 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 06:48:15.341349 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 06:48:15.344413 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 06:48:15.351193 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3566 06:48:15.354537 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 06:48:15.357664 Total UI for P1: 0, mck2ui 16
3568 06:48:15.361009 best dqsien dly found for B0: ( 1, 3, 24)
3569 06:48:15.364423 Total UI for P1: 0, mck2ui 16
3570 06:48:15.367744 best dqsien dly found for B1: ( 1, 3, 24)
3571 06:48:15.370952 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3572 06:48:15.374312 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3573 06:48:15.374392
3574 06:48:15.377696 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3575 06:48:15.381056 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3576 06:48:15.384508 [Gating] SW calibration Done
3577 06:48:15.384593 ==
3578 06:48:15.387778 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 06:48:15.391026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 06:48:15.394294 ==
3581 06:48:15.394374 RX Vref Scan: 0
3582 06:48:15.394461
3583 06:48:15.397677 RX Vref 0 -> 0, step: 1
3584 06:48:15.397754
3585 06:48:15.401051 RX Delay -40 -> 252, step: 8
3586 06:48:15.404263 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3587 06:48:15.407578 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3588 06:48:15.410766 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3589 06:48:15.414021 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3590 06:48:15.420784 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3591 06:48:15.424297 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3592 06:48:15.427474 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3593 06:48:15.430767 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3594 06:48:15.433937 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3595 06:48:15.437386 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3596 06:48:15.444113 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3597 06:48:15.447659 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3598 06:48:15.450683 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3599 06:48:15.453941 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3600 06:48:15.460657 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3601 06:48:15.464066 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3602 06:48:15.464154 ==
3603 06:48:15.467403 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 06:48:15.470836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 06:48:15.470921 ==
3606 06:48:15.474036 DQS Delay:
3607 06:48:15.474155 DQS0 = 0, DQS1 = 0
3608 06:48:15.474241 DQM Delay:
3609 06:48:15.477162 DQM0 = 110, DQM1 = 108
3610 06:48:15.477248 DQ Delay:
3611 06:48:15.480771 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3612 06:48:15.484043 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3613 06:48:15.487109 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3614 06:48:15.493890 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3615 06:48:15.493971
3616 06:48:15.494054
3617 06:48:15.494137 ==
3618 06:48:15.497085 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 06:48:15.500744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 06:48:15.500843 ==
3621 06:48:15.500909
3622 06:48:15.500967
3623 06:48:15.503658 TX Vref Scan disable
3624 06:48:15.503739 == TX Byte 0 ==
3625 06:48:15.510601 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3626 06:48:15.513784 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3627 06:48:15.513874 == TX Byte 1 ==
3628 06:48:15.520304 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3629 06:48:15.523584 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3630 06:48:15.523721 ==
3631 06:48:15.527077 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 06:48:15.530216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 06:48:15.530299 ==
3634 06:48:15.542855 TX Vref=22, minBit 10, minWin=25, winSum=421
3635 06:48:15.546258 TX Vref=24, minBit 1, minWin=26, winSum=428
3636 06:48:15.549377 TX Vref=26, minBit 0, minWin=26, winSum=430
3637 06:48:15.552788 TX Vref=28, minBit 9, minWin=26, winSum=435
3638 06:48:15.556206 TX Vref=30, minBit 9, minWin=25, winSum=431
3639 06:48:15.562410 TX Vref=32, minBit 1, minWin=26, winSum=435
3640 06:48:15.565964 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 28
3641 06:48:15.566091
3642 06:48:15.569285 Final TX Range 1 Vref 28
3643 06:48:15.569365
3644 06:48:15.569464 ==
3645 06:48:15.572812 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 06:48:15.576004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 06:48:15.579151 ==
3648 06:48:15.579226
3649 06:48:15.579307
3650 06:48:15.579388 TX Vref Scan disable
3651 06:48:15.582572 == TX Byte 0 ==
3652 06:48:15.586156 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3653 06:48:15.589415 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3654 06:48:15.592551 == TX Byte 1 ==
3655 06:48:15.595985 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3656 06:48:15.599559 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3657 06:48:15.602831
3658 06:48:15.602925 [DATLAT]
3659 06:48:15.603008 Freq=1200, CH1 RK1
3660 06:48:15.603088
3661 06:48:15.606097 DATLAT Default: 0xd
3662 06:48:15.606176 0, 0xFFFF, sum = 0
3663 06:48:15.609371 1, 0xFFFF, sum = 0
3664 06:48:15.609456 2, 0xFFFF, sum = 0
3665 06:48:15.612738 3, 0xFFFF, sum = 0
3666 06:48:15.616103 4, 0xFFFF, sum = 0
3667 06:48:15.616192 5, 0xFFFF, sum = 0
3668 06:48:15.619474 6, 0xFFFF, sum = 0
3669 06:48:15.619567 7, 0xFFFF, sum = 0
3670 06:48:15.622639 8, 0xFFFF, sum = 0
3671 06:48:15.622722 9, 0xFFFF, sum = 0
3672 06:48:15.625884 10, 0xFFFF, sum = 0
3673 06:48:15.625964 11, 0xFFFF, sum = 0
3674 06:48:15.629241 12, 0x0, sum = 1
3675 06:48:15.629324 13, 0x0, sum = 2
3676 06:48:15.632450 14, 0x0, sum = 3
3677 06:48:15.632529 15, 0x0, sum = 4
3678 06:48:15.635845 best_step = 13
3679 06:48:15.635922
3680 06:48:15.636004 ==
3681 06:48:15.639100 Dram Type= 6, Freq= 0, CH_1, rank 1
3682 06:48:15.642304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3683 06:48:15.642382 ==
3684 06:48:15.642464 RX Vref Scan: 0
3685 06:48:15.642547
3686 06:48:15.645600 RX Vref 0 -> 0, step: 1
3687 06:48:15.645685
3688 06:48:15.649147 RX Delay -21 -> 252, step: 4
3689 06:48:15.652357 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3690 06:48:15.658989 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3691 06:48:15.662425 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3692 06:48:15.665724 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3693 06:48:15.669073 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3694 06:48:15.672696 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3695 06:48:15.679187 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3696 06:48:15.682498 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3697 06:48:15.685907 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3698 06:48:15.689135 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3699 06:48:15.692214 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3700 06:48:15.698865 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3701 06:48:15.702428 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3702 06:48:15.705446 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3703 06:48:15.708874 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3704 06:48:15.712185 iDelay=195, Bit 15, Center 118 (51 ~ 186) 136
3705 06:48:15.715487 ==
3706 06:48:15.718815 Dram Type= 6, Freq= 0, CH_1, rank 1
3707 06:48:15.722147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3708 06:48:15.722257 ==
3709 06:48:15.722349 DQS Delay:
3710 06:48:15.725543 DQS0 = 0, DQS1 = 0
3711 06:48:15.725617 DQM Delay:
3712 06:48:15.728865 DQM0 = 111, DQM1 = 110
3713 06:48:15.728938 DQ Delay:
3714 06:48:15.732149 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3715 06:48:15.735447 DQ4 =110, DQ5 =120, DQ6 =120, DQ7 =108
3716 06:48:15.739060 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =104
3717 06:48:15.742256 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =118
3718 06:48:15.742364
3719 06:48:15.742454
3720 06:48:15.752331 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa09, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3721 06:48:15.752416 CH1 RK1: MR19=304, MR18=FA09
3722 06:48:15.758798 CH1_RK1: MR19=0x304, MR18=0xFA09, DQSOSC=406, MR23=63, INC=39, DEC=26
3723 06:48:15.762083 [RxdqsGatingPostProcess] freq 1200
3724 06:48:15.768814 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3725 06:48:15.772137 best DQS0 dly(2T, 0.5T) = (0, 11)
3726 06:48:15.775387 best DQS1 dly(2T, 0.5T) = (0, 11)
3727 06:48:15.778684 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3728 06:48:15.782180 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3729 06:48:15.785270 best DQS0 dly(2T, 0.5T) = (0, 11)
3730 06:48:15.788609 best DQS1 dly(2T, 0.5T) = (0, 11)
3731 06:48:15.792049 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3732 06:48:15.795088 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3733 06:48:15.795195 Pre-setting of DQS Precalculation
3734 06:48:15.801678 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3735 06:48:15.808433 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3736 06:48:15.815190 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3737 06:48:15.815290
3738 06:48:15.815356
3739 06:48:15.818521 [Calibration Summary] 2400 Mbps
3740 06:48:15.821706 CH 0, Rank 0
3741 06:48:15.821776 SW Impedance : PASS
3742 06:48:15.824973 DUTY Scan : NO K
3743 06:48:15.828291 ZQ Calibration : PASS
3744 06:48:15.828392 Jitter Meter : NO K
3745 06:48:15.831534 CBT Training : PASS
3746 06:48:15.834787 Write leveling : PASS
3747 06:48:15.834891 RX DQS gating : PASS
3748 06:48:15.838198 RX DQ/DQS(RDDQC) : PASS
3749 06:48:15.841494 TX DQ/DQS : PASS
3750 06:48:15.841573 RX DATLAT : PASS
3751 06:48:15.844966 RX DQ/DQS(Engine): PASS
3752 06:48:15.848036 TX OE : NO K
3753 06:48:15.848122 All Pass.
3754 06:48:15.848188
3755 06:48:15.848256 CH 0, Rank 1
3756 06:48:15.851462 SW Impedance : PASS
3757 06:48:15.854851 DUTY Scan : NO K
3758 06:48:15.854925 ZQ Calibration : PASS
3759 06:48:15.857984 Jitter Meter : NO K
3760 06:48:15.858062 CBT Training : PASS
3761 06:48:15.861286 Write leveling : PASS
3762 06:48:15.864657 RX DQS gating : PASS
3763 06:48:15.864730 RX DQ/DQS(RDDQC) : PASS
3764 06:48:15.868253 TX DQ/DQS : PASS
3765 06:48:15.871168 RX DATLAT : PASS
3766 06:48:15.871249 RX DQ/DQS(Engine): PASS
3767 06:48:15.874821 TX OE : NO K
3768 06:48:15.874916 All Pass.
3769 06:48:15.874981
3770 06:48:15.878080 CH 1, Rank 0
3771 06:48:15.878153 SW Impedance : PASS
3772 06:48:15.881196 DUTY Scan : NO K
3773 06:48:15.884521 ZQ Calibration : PASS
3774 06:48:15.884595 Jitter Meter : NO K
3775 06:48:15.888106 CBT Training : PASS
3776 06:48:15.891356 Write leveling : PASS
3777 06:48:15.891430 RX DQS gating : PASS
3778 06:48:15.894565 RX DQ/DQS(RDDQC) : PASS
3779 06:48:15.897885 TX DQ/DQS : PASS
3780 06:48:15.897966 RX DATLAT : PASS
3781 06:48:15.901140 RX DQ/DQS(Engine): PASS
3782 06:48:15.901237 TX OE : NO K
3783 06:48:15.904773 All Pass.
3784 06:48:15.904849
3785 06:48:15.904912 CH 1, Rank 1
3786 06:48:15.908144 SW Impedance : PASS
3787 06:48:15.908218 DUTY Scan : NO K
3788 06:48:15.911267 ZQ Calibration : PASS
3789 06:48:15.914487 Jitter Meter : NO K
3790 06:48:15.914564 CBT Training : PASS
3791 06:48:15.917902 Write leveling : PASS
3792 06:48:15.921201 RX DQS gating : PASS
3793 06:48:15.921332 RX DQ/DQS(RDDQC) : PASS
3794 06:48:15.924519 TX DQ/DQS : PASS
3795 06:48:15.927740 RX DATLAT : PASS
3796 06:48:15.927833 RX DQ/DQS(Engine): PASS
3797 06:48:15.931294 TX OE : NO K
3798 06:48:15.931369 All Pass.
3799 06:48:15.931432
3800 06:48:15.934544 DramC Write-DBI off
3801 06:48:15.937907 PER_BANK_REFRESH: Hybrid Mode
3802 06:48:15.937986 TX_TRACKING: ON
3803 06:48:15.947939 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3804 06:48:15.951068 [FAST_K] Save calibration result to emmc
3805 06:48:15.954345 dramc_set_vcore_voltage set vcore to 650000
3806 06:48:15.957631 Read voltage for 600, 5
3807 06:48:15.957710 Vio18 = 0
3808 06:48:15.957791 Vcore = 650000
3809 06:48:15.961129 Vdram = 0
3810 06:48:15.961206 Vddq = 0
3811 06:48:15.961267 Vmddr = 0
3812 06:48:15.967685 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3813 06:48:15.970883 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3814 06:48:15.974247 MEM_TYPE=3, freq_sel=19
3815 06:48:15.977507 sv_algorithm_assistance_LP4_1600
3816 06:48:15.980823 ============ PULL DRAM RESETB DOWN ============
3817 06:48:15.984083 ========== PULL DRAM RESETB DOWN end =========
3818 06:48:15.990784 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3819 06:48:15.994163 ===================================
3820 06:48:15.997304 LPDDR4 DRAM CONFIGURATION
3821 06:48:16.000790 ===================================
3822 06:48:16.000869 EX_ROW_EN[0] = 0x0
3823 06:48:16.003980 EX_ROW_EN[1] = 0x0
3824 06:48:16.004063 LP4Y_EN = 0x0
3825 06:48:16.007465 WORK_FSP = 0x0
3826 06:48:16.007539 WL = 0x2
3827 06:48:16.010869 RL = 0x2
3828 06:48:16.010953 BL = 0x2
3829 06:48:16.014050 RPST = 0x0
3830 06:48:16.014163 RD_PRE = 0x0
3831 06:48:16.017419 WR_PRE = 0x1
3832 06:48:16.017519 WR_PST = 0x0
3833 06:48:16.020828 DBI_WR = 0x0
3834 06:48:16.020901 DBI_RD = 0x0
3835 06:48:16.023984 OTF = 0x1
3836 06:48:16.027484 ===================================
3837 06:48:16.030807 ===================================
3838 06:48:16.030889 ANA top config
3839 06:48:16.034030 ===================================
3840 06:48:16.037417 DLL_ASYNC_EN = 0
3841 06:48:16.041070 ALL_SLAVE_EN = 1
3842 06:48:16.044196 NEW_RANK_MODE = 1
3843 06:48:16.044278 DLL_IDLE_MODE = 1
3844 06:48:16.047435 LP45_APHY_COMB_EN = 1
3845 06:48:16.050764 TX_ODT_DIS = 1
3846 06:48:16.053991 NEW_8X_MODE = 1
3847 06:48:16.057563 ===================================
3848 06:48:16.060626 ===================================
3849 06:48:16.064066 data_rate = 1200
3850 06:48:16.064141 CKR = 1
3851 06:48:16.067468 DQ_P2S_RATIO = 8
3852 06:48:16.070775 ===================================
3853 06:48:16.074176 CA_P2S_RATIO = 8
3854 06:48:16.077382 DQ_CA_OPEN = 0
3855 06:48:16.080659 DQ_SEMI_OPEN = 0
3856 06:48:16.083891 CA_SEMI_OPEN = 0
3857 06:48:16.083967 CA_FULL_RATE = 0
3858 06:48:16.087189 DQ_CKDIV4_EN = 1
3859 06:48:16.090484 CA_CKDIV4_EN = 1
3860 06:48:16.093834 CA_PREDIV_EN = 0
3861 06:48:16.097087 PH8_DLY = 0
3862 06:48:16.100510 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3863 06:48:16.100594 DQ_AAMCK_DIV = 4
3864 06:48:16.104066 CA_AAMCK_DIV = 4
3865 06:48:16.107275 CA_ADMCK_DIV = 4
3866 06:48:16.110405 DQ_TRACK_CA_EN = 0
3867 06:48:16.113658 CA_PICK = 600
3868 06:48:16.117026 CA_MCKIO = 600
3869 06:48:16.117109 MCKIO_SEMI = 0
3870 06:48:16.120563 PLL_FREQ = 2288
3871 06:48:16.123660 DQ_UI_PI_RATIO = 32
3872 06:48:16.126841 CA_UI_PI_RATIO = 0
3873 06:48:16.130241 ===================================
3874 06:48:16.133734 ===================================
3875 06:48:16.137038 memory_type:LPDDR4
3876 06:48:16.137143 GP_NUM : 10
3877 06:48:16.140178 SRAM_EN : 1
3878 06:48:16.143546 MD32_EN : 0
3879 06:48:16.146847 ===================================
3880 06:48:16.146923 [ANA_INIT] >>>>>>>>>>>>>>
3881 06:48:16.150053 <<<<<< [CONFIGURE PHASE]: ANA_TX
3882 06:48:16.153432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3883 06:48:16.156918 ===================================
3884 06:48:16.160148 data_rate = 1200,PCW = 0X5800
3885 06:48:16.163669 ===================================
3886 06:48:16.166791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3887 06:48:16.173527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3888 06:48:16.176783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3889 06:48:16.183469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3890 06:48:16.186657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3891 06:48:16.189987 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3892 06:48:16.193317 [ANA_INIT] flow start
3893 06:48:16.193423 [ANA_INIT] PLL >>>>>>>>
3894 06:48:16.196584 [ANA_INIT] PLL <<<<<<<<
3895 06:48:16.199895 [ANA_INIT] MIDPI >>>>>>>>
3896 06:48:16.199972 [ANA_INIT] MIDPI <<<<<<<<
3897 06:48:16.203014 [ANA_INIT] DLL >>>>>>>>
3898 06:48:16.206396 [ANA_INIT] flow end
3899 06:48:16.209662 ============ LP4 DIFF to SE enter ============
3900 06:48:16.213338 ============ LP4 DIFF to SE exit ============
3901 06:48:16.216529 [ANA_INIT] <<<<<<<<<<<<<
3902 06:48:16.219776 [Flow] Enable top DCM control >>>>>
3903 06:48:16.223159 [Flow] Enable top DCM control <<<<<
3904 06:48:16.226209 Enable DLL master slave shuffle
3905 06:48:16.229749 ==============================================================
3906 06:48:16.233075 Gating Mode config
3907 06:48:16.239464 ==============================================================
3908 06:48:16.239567 Config description:
3909 06:48:16.249584 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3910 06:48:16.256264 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3911 06:48:16.259762 SELPH_MODE 0: By rank 1: By Phase
3912 06:48:16.266056 ==============================================================
3913 06:48:16.269200 GAT_TRACK_EN = 1
3914 06:48:16.272731 RX_GATING_MODE = 2
3915 06:48:16.275985 RX_GATING_TRACK_MODE = 2
3916 06:48:16.279429 SELPH_MODE = 1
3917 06:48:16.282765 PICG_EARLY_EN = 1
3918 06:48:16.285654 VALID_LAT_VALUE = 1
3919 06:48:16.288981 ==============================================================
3920 06:48:16.292286 Enter into Gating configuration >>>>
3921 06:48:16.295718 Exit from Gating configuration <<<<
3922 06:48:16.298983 Enter into DVFS_PRE_config >>>>>
3923 06:48:16.312321 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3924 06:48:16.315496 Exit from DVFS_PRE_config <<<<<
3925 06:48:16.315641 Enter into PICG configuration >>>>
3926 06:48:16.318829 Exit from PICG configuration <<<<
3927 06:48:16.322528 [RX_INPUT] configuration >>>>>
3928 06:48:16.325712 [RX_INPUT] configuration <<<<<
3929 06:48:16.332400 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3930 06:48:16.335501 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3931 06:48:16.342048 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3932 06:48:16.348801 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3933 06:48:16.355784 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3934 06:48:16.362186 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3935 06:48:16.365505 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3936 06:48:16.368935 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3937 06:48:16.372241 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3938 06:48:16.378783 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3939 06:48:16.381843 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3940 06:48:16.385176 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3941 06:48:16.388508 ===================================
3942 06:48:16.392049 LPDDR4 DRAM CONFIGURATION
3943 06:48:16.395378 ===================================
3944 06:48:16.398703 EX_ROW_EN[0] = 0x0
3945 06:48:16.398811 EX_ROW_EN[1] = 0x0
3946 06:48:16.401895 LP4Y_EN = 0x0
3947 06:48:16.401992 WORK_FSP = 0x0
3948 06:48:16.405150 WL = 0x2
3949 06:48:16.405261 RL = 0x2
3950 06:48:16.408462 BL = 0x2
3951 06:48:16.408563 RPST = 0x0
3952 06:48:16.411570 RD_PRE = 0x0
3953 06:48:16.411671 WR_PRE = 0x1
3954 06:48:16.415077 WR_PST = 0x0
3955 06:48:16.415191 DBI_WR = 0x0
3956 06:48:16.418237 DBI_RD = 0x0
3957 06:48:16.418320 OTF = 0x1
3958 06:48:16.421506 ===================================
3959 06:48:16.428157 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3960 06:48:16.431743 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3961 06:48:16.435176 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3962 06:48:16.438354 ===================================
3963 06:48:16.441836 LPDDR4 DRAM CONFIGURATION
3964 06:48:16.445124 ===================================
3965 06:48:16.445228 EX_ROW_EN[0] = 0x10
3966 06:48:16.448454 EX_ROW_EN[1] = 0x0
3967 06:48:16.451682 LP4Y_EN = 0x0
3968 06:48:16.451767 WORK_FSP = 0x0
3969 06:48:16.455061 WL = 0x2
3970 06:48:16.455169 RL = 0x2
3971 06:48:16.458178 BL = 0x2
3972 06:48:16.458279 RPST = 0x0
3973 06:48:16.461366 RD_PRE = 0x0
3974 06:48:16.461468 WR_PRE = 0x1
3975 06:48:16.465061 WR_PST = 0x0
3976 06:48:16.465164 DBI_WR = 0x0
3977 06:48:16.468287 DBI_RD = 0x0
3978 06:48:16.468364 OTF = 0x1
3979 06:48:16.471586 ===================================
3980 06:48:16.478176 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3981 06:48:16.482827 nWR fixed to 30
3982 06:48:16.486030 [ModeRegInit_LP4] CH0 RK0
3983 06:48:16.486135 [ModeRegInit_LP4] CH0 RK1
3984 06:48:16.489269 [ModeRegInit_LP4] CH1 RK0
3985 06:48:16.492511 [ModeRegInit_LP4] CH1 RK1
3986 06:48:16.492614 match AC timing 17
3987 06:48:16.499168 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3988 06:48:16.502275 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3989 06:48:16.505911 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3990 06:48:16.512510 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3991 06:48:16.515559 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3992 06:48:16.515668 ==
3993 06:48:16.519127 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 06:48:16.522317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 06:48:16.522398 ==
3996 06:48:16.528907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3997 06:48:16.535453 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3998 06:48:16.539023 [CA 0] Center 37 (7~67) winsize 61
3999 06:48:16.542255 [CA 1] Center 36 (6~67) winsize 62
4000 06:48:16.545674 [CA 2] Center 35 (5~65) winsize 61
4001 06:48:16.549010 [CA 3] Center 35 (5~65) winsize 61
4002 06:48:16.552230 [CA 4] Center 34 (4~65) winsize 62
4003 06:48:16.555561 [CA 5] Center 34 (4~64) winsize 61
4004 06:48:16.555641
4005 06:48:16.558736 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4006 06:48:16.558808
4007 06:48:16.562163 [CATrainingPosCal] consider 1 rank data
4008 06:48:16.565516 u2DelayCellTimex100 = 270/100 ps
4009 06:48:16.568917 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4010 06:48:16.572164 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4011 06:48:16.575463 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4012 06:48:16.578705 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4013 06:48:16.582097 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4014 06:48:16.588657 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4015 06:48:16.588761
4016 06:48:16.591922 CA PerBit enable=1, Macro0, CA PI delay=34
4017 06:48:16.592030
4018 06:48:16.595161 [CBTSetCACLKResult] CA Dly = 34
4019 06:48:16.595261 CS Dly: 5 (0~36)
4020 06:48:16.595358 ==
4021 06:48:16.598630 Dram Type= 6, Freq= 0, CH_0, rank 1
4022 06:48:16.601880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 06:48:16.605075 ==
4024 06:48:16.608418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4025 06:48:16.614776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4026 06:48:16.618150 [CA 0] Center 37 (7~67) winsize 61
4027 06:48:16.621513 [CA 1] Center 36 (6~67) winsize 62
4028 06:48:16.624629 [CA 2] Center 35 (5~65) winsize 61
4029 06:48:16.628231 [CA 3] Center 35 (5~65) winsize 61
4030 06:48:16.631484 [CA 4] Center 34 (3~65) winsize 63
4031 06:48:16.634918 [CA 5] Center 33 (3~64) winsize 62
4032 06:48:16.635015
4033 06:48:16.638248 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4034 06:48:16.638333
4035 06:48:16.641492 [CATrainingPosCal] consider 2 rank data
4036 06:48:16.644713 u2DelayCellTimex100 = 270/100 ps
4037 06:48:16.647968 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4038 06:48:16.651200 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4039 06:48:16.657964 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4040 06:48:16.661182 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4041 06:48:16.664371 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4042 06:48:16.667968 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4043 06:48:16.668052
4044 06:48:16.671214 CA PerBit enable=1, Macro0, CA PI delay=34
4045 06:48:16.671297
4046 06:48:16.674456 [CBTSetCACLKResult] CA Dly = 34
4047 06:48:16.674540 CS Dly: 5 (0~36)
4048 06:48:16.674606
4049 06:48:16.677765 ----->DramcWriteLeveling(PI) begin...
4050 06:48:16.680937 ==
4051 06:48:16.684581 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 06:48:16.687889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 06:48:16.687966 ==
4054 06:48:16.691345 Write leveling (Byte 0): 31 => 31
4055 06:48:16.694714 Write leveling (Byte 1): 30 => 30
4056 06:48:16.698043 DramcWriteLeveling(PI) end<-----
4057 06:48:16.698117
4058 06:48:16.698177 ==
4059 06:48:16.701293 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 06:48:16.704553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 06:48:16.704653 ==
4062 06:48:16.707895 [Gating] SW mode calibration
4063 06:48:16.714549 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4064 06:48:16.717752 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4065 06:48:16.724365 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4066 06:48:16.727919 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4067 06:48:16.731090 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4068 06:48:16.737838 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4069 06:48:16.740982 0 9 16 | B1->B0 | 3030 2d2d | 1 0 | (1 1) (1 1)
4070 06:48:16.744483 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 06:48:16.750943 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 06:48:16.754415 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 06:48:16.757663 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 06:48:16.764256 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 06:48:16.767666 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4076 06:48:16.770925 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4077 06:48:16.777572 0 10 16 | B1->B0 | 3232 3939 | 0 0 | (0 0) (0 0)
4078 06:48:16.780678 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 06:48:16.784182 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 06:48:16.790854 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 06:48:16.793705 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 06:48:16.797421 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 06:48:16.803939 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 06:48:16.807225 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 06:48:16.810595 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4086 06:48:16.817250 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 06:48:16.820501 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 06:48:16.823608 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 06:48:16.830363 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 06:48:16.833627 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 06:48:16.837239 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 06:48:16.843821 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 06:48:16.846847 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 06:48:16.850125 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 06:48:16.856969 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 06:48:16.860357 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 06:48:16.863518 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 06:48:16.870203 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 06:48:16.873448 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 06:48:16.876848 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4101 06:48:16.883282 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4102 06:48:16.883365 Total UI for P1: 0, mck2ui 16
4103 06:48:16.890001 best dqsien dly found for B0: ( 0, 13, 12)
4104 06:48:16.893157 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 06:48:16.896475 Total UI for P1: 0, mck2ui 16
4106 06:48:16.899742 best dqsien dly found for B1: ( 0, 13, 16)
4107 06:48:16.903112 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4108 06:48:16.906781 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4109 06:48:16.906891
4110 06:48:16.910030 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4111 06:48:16.912979 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4112 06:48:16.916324 [Gating] SW calibration Done
4113 06:48:16.916426 ==
4114 06:48:16.919945 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 06:48:16.923234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 06:48:16.926358 ==
4117 06:48:16.926434 RX Vref Scan: 0
4118 06:48:16.926497
4119 06:48:16.929472 RX Vref 0 -> 0, step: 1
4120 06:48:16.929579
4121 06:48:16.933070 RX Delay -230 -> 252, step: 16
4122 06:48:16.936150 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4123 06:48:16.939780 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4124 06:48:16.943025 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4125 06:48:16.949546 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4126 06:48:16.952897 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4127 06:48:16.956205 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4128 06:48:16.959401 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4129 06:48:16.962603 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4130 06:48:16.969368 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4131 06:48:16.972725 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4132 06:48:16.976038 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4133 06:48:16.979463 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4134 06:48:16.985757 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4135 06:48:16.989142 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4136 06:48:16.992686 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4137 06:48:16.995802 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4138 06:48:16.995900 ==
4139 06:48:16.999133 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 06:48:17.005915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 06:48:17.005993 ==
4142 06:48:17.006056 DQS Delay:
4143 06:48:17.009163 DQS0 = 0, DQS1 = 0
4144 06:48:17.009262 DQM Delay:
4145 06:48:17.009351 DQM0 = 38, DQM1 = 31
4146 06:48:17.012430 DQ Delay:
4147 06:48:17.016039 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4148 06:48:17.019304 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4149 06:48:17.022568 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4150 06:48:17.025838 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4151 06:48:17.025914
4152 06:48:17.025977
4153 06:48:17.026035 ==
4154 06:48:17.029071 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 06:48:17.032530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 06:48:17.032605 ==
4157 06:48:17.032666
4158 06:48:17.032724
4159 06:48:17.035859 TX Vref Scan disable
4160 06:48:17.038989 == TX Byte 0 ==
4161 06:48:17.042201 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4162 06:48:17.045452 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4163 06:48:17.049155 == TX Byte 1 ==
4164 06:48:17.052345 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4165 06:48:17.055541 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4166 06:48:17.055620 ==
4167 06:48:17.058883 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 06:48:17.062512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 06:48:17.065855 ==
4170 06:48:17.065924
4171 06:48:17.065983
4172 06:48:17.066039 TX Vref Scan disable
4173 06:48:17.069432 == TX Byte 0 ==
4174 06:48:17.072769 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4175 06:48:17.076140 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4176 06:48:17.079329 == TX Byte 1 ==
4177 06:48:17.082720 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4178 06:48:17.089118 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4179 06:48:17.089193
4180 06:48:17.089255 [DATLAT]
4181 06:48:17.089313 Freq=600, CH0 RK0
4182 06:48:17.089368
4183 06:48:17.092440 DATLAT Default: 0x9
4184 06:48:17.092507 0, 0xFFFF, sum = 0
4185 06:48:17.095811 1, 0xFFFF, sum = 0
4186 06:48:17.095900 2, 0xFFFF, sum = 0
4187 06:48:17.099490 3, 0xFFFF, sum = 0
4188 06:48:17.102868 4, 0xFFFF, sum = 0
4189 06:48:17.102957 5, 0xFFFF, sum = 0
4190 06:48:17.105729 6, 0xFFFF, sum = 0
4191 06:48:17.105820 7, 0xFFFF, sum = 0
4192 06:48:17.108970 8, 0x0, sum = 1
4193 06:48:17.109057 9, 0x0, sum = 2
4194 06:48:17.109118 10, 0x0, sum = 3
4195 06:48:17.112538 11, 0x0, sum = 4
4196 06:48:17.112688 best_step = 9
4197 06:48:17.112781
4198 06:48:17.112873 ==
4199 06:48:17.115691 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 06:48:17.122545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 06:48:17.122663 ==
4202 06:48:17.122752 RX Vref Scan: 1
4203 06:48:17.122847
4204 06:48:17.125841 RX Vref 0 -> 0, step: 1
4205 06:48:17.125933
4206 06:48:17.129071 RX Delay -195 -> 252, step: 8
4207 06:48:17.129167
4208 06:48:17.132219 Set Vref, RX VrefLevel [Byte0]: 63
4209 06:48:17.135481 [Byte1]: 52
4210 06:48:17.135555
4211 06:48:17.138885 Final RX Vref Byte 0 = 63 to rank0
4212 06:48:17.142377 Final RX Vref Byte 1 = 52 to rank0
4213 06:48:17.145621 Final RX Vref Byte 0 = 63 to rank1
4214 06:48:17.149190 Final RX Vref Byte 1 = 52 to rank1==
4215 06:48:17.152508 Dram Type= 6, Freq= 0, CH_0, rank 0
4216 06:48:17.155761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 06:48:17.155833 ==
4218 06:48:17.159058 DQS Delay:
4219 06:48:17.159133 DQS0 = 0, DQS1 = 0
4220 06:48:17.162206 DQM Delay:
4221 06:48:17.162279 DQM0 = 35, DQM1 = 29
4222 06:48:17.162344 DQ Delay:
4223 06:48:17.165909 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4224 06:48:17.168824 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4225 06:48:17.172342 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4226 06:48:17.175611 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4227 06:48:17.175716
4228 06:48:17.175818
4229 06:48:17.185460 [DQSOSCAuto] RK0, (LSB)MR18= 0x4846, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4230 06:48:17.188925 CH0 RK0: MR19=808, MR18=4846
4231 06:48:17.195316 CH0_RK0: MR19=0x808, MR18=0x4846, DQSOSC=396, MR23=63, INC=167, DEC=111
4232 06:48:17.195423
4233 06:48:17.198570 ----->DramcWriteLeveling(PI) begin...
4234 06:48:17.198673 ==
4235 06:48:17.201919 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 06:48:17.205194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 06:48:17.205267 ==
4238 06:48:17.208527 Write leveling (Byte 0): 32 => 32
4239 06:48:17.212165 Write leveling (Byte 1): 30 => 30
4240 06:48:17.215332 DramcWriteLeveling(PI) end<-----
4241 06:48:17.215443
4242 06:48:17.215535 ==
4243 06:48:17.218774 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 06:48:17.221896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 06:48:17.221974 ==
4246 06:48:17.225444 [Gating] SW mode calibration
4247 06:48:17.232079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4248 06:48:17.238788 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4249 06:48:17.242021 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4250 06:48:17.245314 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4251 06:48:17.252022 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4252 06:48:17.255215 0 9 12 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 1)
4253 06:48:17.258470 0 9 16 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
4254 06:48:17.265033 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 06:48:17.268529 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 06:48:17.271943 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 06:48:17.275306 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 06:48:17.281973 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 06:48:17.285272 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 06:48:17.288571 0 10 12 | B1->B0 | 2525 3232 | 0 1 | (0 0) (0 0)
4261 06:48:17.295047 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4262 06:48:17.298436 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 06:48:17.301741 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 06:48:17.308163 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 06:48:17.311373 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 06:48:17.314721 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 06:48:17.321466 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 06:48:17.324696 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4269 06:48:17.328200 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4270 06:48:17.334653 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 06:48:17.338034 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 06:48:17.341193 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 06:48:17.347777 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 06:48:17.351069 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 06:48:17.354665 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 06:48:17.361382 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 06:48:17.364388 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 06:48:17.367822 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 06:48:17.374579 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 06:48:17.377819 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 06:48:17.381331 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 06:48:17.387858 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 06:48:17.391315 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 06:48:17.394479 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4285 06:48:17.397894 Total UI for P1: 0, mck2ui 16
4286 06:48:17.401053 best dqsien dly found for B0: ( 0, 13, 10)
4287 06:48:17.404666 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 06:48:17.407964 Total UI for P1: 0, mck2ui 16
4289 06:48:17.410963 best dqsien dly found for B1: ( 0, 13, 12)
4290 06:48:17.417585 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4291 06:48:17.420926 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4292 06:48:17.421031
4293 06:48:17.424605 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4294 06:48:17.427784 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4295 06:48:17.430943 [Gating] SW calibration Done
4296 06:48:17.431041 ==
4297 06:48:17.434223 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 06:48:17.437759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 06:48:17.437832 ==
4300 06:48:17.440837 RX Vref Scan: 0
4301 06:48:17.440965
4302 06:48:17.441059 RX Vref 0 -> 0, step: 1
4303 06:48:17.441143
4304 06:48:17.444098 RX Delay -230 -> 252, step: 16
4305 06:48:17.450700 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4306 06:48:17.454032 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4307 06:48:17.457338 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4308 06:48:17.460937 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4309 06:48:17.464171 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4310 06:48:17.470704 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4311 06:48:17.473833 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4312 06:48:17.477280 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4313 06:48:17.480462 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4314 06:48:17.487180 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4315 06:48:17.490503 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4316 06:48:17.493732 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4317 06:48:17.496928 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4318 06:48:17.503540 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4319 06:48:17.506796 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4320 06:48:17.510202 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4321 06:48:17.510305 ==
4322 06:48:17.513366 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 06:48:17.516644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 06:48:17.519950 ==
4325 06:48:17.520034 DQS Delay:
4326 06:48:17.520098 DQS0 = 0, DQS1 = 0
4327 06:48:17.523251 DQM Delay:
4328 06:48:17.523357 DQM0 = 34, DQM1 = 29
4329 06:48:17.526516 DQ Delay:
4330 06:48:17.526617 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4331 06:48:17.530091 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =41
4332 06:48:17.533427 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4333 06:48:17.536756 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4334 06:48:17.536864
4335 06:48:17.540031
4336 06:48:17.540130 ==
4337 06:48:17.543307 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 06:48:17.546557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 06:48:17.546658 ==
4340 06:48:17.546759
4341 06:48:17.546848
4342 06:48:17.550001 TX Vref Scan disable
4343 06:48:17.550092 == TX Byte 0 ==
4344 06:48:17.556645 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4345 06:48:17.560061 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4346 06:48:17.560171 == TX Byte 1 ==
4347 06:48:17.566579 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4348 06:48:17.569873 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4349 06:48:17.569965 ==
4350 06:48:17.572777 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 06:48:17.576517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 06:48:17.576595 ==
4353 06:48:17.576658
4354 06:48:17.576716
4355 06:48:17.579833 TX Vref Scan disable
4356 06:48:17.582972 == TX Byte 0 ==
4357 06:48:17.586086 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4358 06:48:17.589595 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4359 06:48:17.593064 == TX Byte 1 ==
4360 06:48:17.596303 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4361 06:48:17.599374 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4362 06:48:17.602830
4363 06:48:17.602904 [DATLAT]
4364 06:48:17.602965 Freq=600, CH0 RK1
4365 06:48:17.603024
4366 06:48:17.606249 DATLAT Default: 0x9
4367 06:48:17.606320 0, 0xFFFF, sum = 0
4368 06:48:17.609385 1, 0xFFFF, sum = 0
4369 06:48:17.609500 2, 0xFFFF, sum = 0
4370 06:48:17.612833 3, 0xFFFF, sum = 0
4371 06:48:17.612917 4, 0xFFFF, sum = 0
4372 06:48:17.616265 5, 0xFFFF, sum = 0
4373 06:48:17.619524 6, 0xFFFF, sum = 0
4374 06:48:17.619627 7, 0xFFFF, sum = 0
4375 06:48:17.619728 8, 0x0, sum = 1
4376 06:48:17.622814 9, 0x0, sum = 2
4377 06:48:17.622898 10, 0x0, sum = 3
4378 06:48:17.626010 11, 0x0, sum = 4
4379 06:48:17.626087 best_step = 9
4380 06:48:17.626165
4381 06:48:17.626226 ==
4382 06:48:17.629400 Dram Type= 6, Freq= 0, CH_0, rank 1
4383 06:48:17.636138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 06:48:17.636219 ==
4385 06:48:17.636282 RX Vref Scan: 0
4386 06:48:17.636342
4387 06:48:17.639366 RX Vref 0 -> 0, step: 1
4388 06:48:17.639448
4389 06:48:17.642603 RX Delay -195 -> 252, step: 8
4390 06:48:17.645906 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4391 06:48:17.652488 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4392 06:48:17.655698 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4393 06:48:17.659326 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4394 06:48:17.662398 iDelay=205, Bit 4, Center 28 (-131 ~ 188) 320
4395 06:48:17.668885 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4396 06:48:17.672131 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4397 06:48:17.675789 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4398 06:48:17.679112 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4399 06:48:17.682431 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4400 06:48:17.688842 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4401 06:48:17.692308 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4402 06:48:17.695417 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4403 06:48:17.698890 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4404 06:48:17.705324 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4405 06:48:17.708813 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4406 06:48:17.708915 ==
4407 06:48:17.712033 Dram Type= 6, Freq= 0, CH_0, rank 1
4408 06:48:17.715178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 06:48:17.715284 ==
4410 06:48:17.718794 DQS Delay:
4411 06:48:17.718892 DQS0 = 0, DQS1 = 0
4412 06:48:17.722033 DQM Delay:
4413 06:48:17.722106 DQM0 = 33, DQM1 = 28
4414 06:48:17.722181 DQ Delay:
4415 06:48:17.725095 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4416 06:48:17.728756 DQ4 =28, DQ5 =24, DQ6 =44, DQ7 =44
4417 06:48:17.731819 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4418 06:48:17.735163 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4419 06:48:17.735240
4420 06:48:17.735303
4421 06:48:17.745297 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4422 06:48:17.748654 CH0 RK1: MR19=808, MR18=6D3D
4423 06:48:17.751676 CH0_RK1: MR19=0x808, MR18=0x6D3D, DQSOSC=389, MR23=63, INC=173, DEC=115
4424 06:48:17.755007 [RxdqsGatingPostProcess] freq 600
4425 06:48:17.761877 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4426 06:48:17.765174 Pre-setting of DQS Precalculation
4427 06:48:17.768378 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4428 06:48:17.768459 ==
4429 06:48:17.774654 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 06:48:17.778068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 06:48:17.778142 ==
4432 06:48:17.781675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4433 06:48:17.787882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4434 06:48:17.791920 [CA 0] Center 35 (5~66) winsize 62
4435 06:48:17.795258 [CA 1] Center 36 (6~66) winsize 61
4436 06:48:17.798373 [CA 2] Center 34 (4~65) winsize 62
4437 06:48:17.801708 [CA 3] Center 34 (4~65) winsize 62
4438 06:48:17.805238 [CA 4] Center 34 (4~65) winsize 62
4439 06:48:17.808202 [CA 5] Center 33 (3~64) winsize 62
4440 06:48:17.808275
4441 06:48:17.811518 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4442 06:48:17.811621
4443 06:48:17.814825 [CATrainingPosCal] consider 1 rank data
4444 06:48:17.818105 u2DelayCellTimex100 = 270/100 ps
4445 06:48:17.821420 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4446 06:48:17.828280 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4447 06:48:17.831625 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4448 06:48:17.834778 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4449 06:48:17.838146 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4450 06:48:17.841470 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4451 06:48:17.841552
4452 06:48:17.844854 CA PerBit enable=1, Macro0, CA PI delay=33
4453 06:48:17.844951
4454 06:48:17.848187 [CBTSetCACLKResult] CA Dly = 33
4455 06:48:17.848287 CS Dly: 4 (0~35)
4456 06:48:17.851227 ==
4457 06:48:17.854621 Dram Type= 6, Freq= 0, CH_1, rank 1
4458 06:48:17.857913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 06:48:17.857986 ==
4460 06:48:17.861284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4461 06:48:17.868127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4462 06:48:17.871902 [CA 0] Center 36 (6~66) winsize 61
4463 06:48:17.875253 [CA 1] Center 36 (5~67) winsize 63
4464 06:48:17.878517 [CA 2] Center 34 (4~65) winsize 62
4465 06:48:17.881699 [CA 3] Center 34 (3~65) winsize 63
4466 06:48:17.885166 [CA 4] Center 34 (4~65) winsize 62
4467 06:48:17.888469 [CA 5] Center 33 (3~64) winsize 62
4468 06:48:17.888577
4469 06:48:17.891659 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4470 06:48:17.891766
4471 06:48:17.894884 [CATrainingPosCal] consider 2 rank data
4472 06:48:17.898152 u2DelayCellTimex100 = 270/100 ps
4473 06:48:17.901729 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4474 06:48:17.908379 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4475 06:48:17.911709 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4476 06:48:17.914808 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4477 06:48:17.918264 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4478 06:48:17.921470 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4479 06:48:17.921581
4480 06:48:17.924662 CA PerBit enable=1, Macro0, CA PI delay=33
4481 06:48:17.924735
4482 06:48:17.928073 [CBTSetCACLKResult] CA Dly = 33
4483 06:48:17.928180 CS Dly: 4 (0~36)
4484 06:48:17.931327
4485 06:48:17.934732 ----->DramcWriteLeveling(PI) begin...
4486 06:48:17.934835 ==
4487 06:48:17.937975 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 06:48:17.941283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 06:48:17.941383 ==
4490 06:48:17.944646 Write leveling (Byte 0): 29 => 29
4491 06:48:17.947646 Write leveling (Byte 1): 29 => 29
4492 06:48:17.951024 DramcWriteLeveling(PI) end<-----
4493 06:48:17.951100
4494 06:48:17.951162 ==
4495 06:48:17.954548 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 06:48:17.957854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 06:48:17.957936 ==
4498 06:48:17.961051 [Gating] SW mode calibration
4499 06:48:17.967688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4500 06:48:17.974104 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4501 06:48:17.977783 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4502 06:48:17.980676 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4503 06:48:17.987659 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4504 06:48:17.990820 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4505 06:48:17.994007 0 9 16 | B1->B0 | 2929 2424 | 0 0 | (1 0) (1 0)
4506 06:48:18.000771 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 06:48:18.004000 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 06:48:18.007273 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 06:48:18.013948 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 06:48:18.017127 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 06:48:18.020795 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4512 06:48:18.027459 0 10 12 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 0)
4513 06:48:18.030746 0 10 16 | B1->B0 | 4141 4040 | 1 1 | (0 0) (0 0)
4514 06:48:18.033924 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 06:48:18.040420 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 06:48:18.043731 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 06:48:18.047283 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 06:48:18.053876 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 06:48:18.057165 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4520 06:48:18.060379 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4521 06:48:18.067234 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 06:48:18.070487 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 06:48:18.073627 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 06:48:18.077210 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 06:48:18.083777 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 06:48:18.087148 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 06:48:18.090419 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 06:48:18.096956 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 06:48:18.100475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 06:48:18.103782 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 06:48:18.110383 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 06:48:18.113738 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 06:48:18.116856 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 06:48:18.123738 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 06:48:18.127057 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 06:48:18.130176 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4537 06:48:18.137037 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 06:48:18.137117 Total UI for P1: 0, mck2ui 16
4539 06:48:18.143543 best dqsien dly found for B0: ( 0, 13, 12)
4540 06:48:18.143625 Total UI for P1: 0, mck2ui 16
4541 06:48:18.150204 best dqsien dly found for B1: ( 0, 13, 12)
4542 06:48:18.153551 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4543 06:48:18.156660 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4544 06:48:18.156770
4545 06:48:18.159963 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4546 06:48:18.163289 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4547 06:48:18.166918 [Gating] SW calibration Done
4548 06:48:18.167003 ==
4549 06:48:18.170079 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 06:48:18.173512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 06:48:18.173594 ==
4552 06:48:18.176646 RX Vref Scan: 0
4553 06:48:18.176719
4554 06:48:18.176780 RX Vref 0 -> 0, step: 1
4555 06:48:18.176847
4556 06:48:18.180175 RX Delay -230 -> 252, step: 16
4557 06:48:18.186749 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4558 06:48:18.190098 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4559 06:48:18.193250 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4560 06:48:18.196646 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4561 06:48:18.199975 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4562 06:48:18.206911 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4563 06:48:18.210142 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4564 06:48:18.213382 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4565 06:48:18.216662 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4566 06:48:18.223218 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4567 06:48:18.226532 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4568 06:48:18.229902 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4569 06:48:18.233047 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4570 06:48:18.239968 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4571 06:48:18.243268 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4572 06:48:18.246400 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4573 06:48:18.246512 ==
4574 06:48:18.249773 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 06:48:18.253061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 06:48:18.253173 ==
4577 06:48:18.256456 DQS Delay:
4578 06:48:18.256561 DQS0 = 0, DQS1 = 0
4579 06:48:18.259931 DQM Delay:
4580 06:48:18.260040 DQM0 = 37, DQM1 = 28
4581 06:48:18.260132 DQ Delay:
4582 06:48:18.263143 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4583 06:48:18.266816 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4584 06:48:18.269713 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4585 06:48:18.272953 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4586 06:48:18.273061
4587 06:48:18.273153
4588 06:48:18.276433 ==
4589 06:48:18.279701 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 06:48:18.282880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 06:48:18.282988 ==
4592 06:48:18.283079
4593 06:48:18.283174
4594 06:48:18.286369 TX Vref Scan disable
4595 06:48:18.286474 == TX Byte 0 ==
4596 06:48:18.289914 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4597 06:48:18.296350 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4598 06:48:18.296457 == TX Byte 1 ==
4599 06:48:18.302816 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4600 06:48:18.306130 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4601 06:48:18.306214 ==
4602 06:48:18.309494 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 06:48:18.312827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 06:48:18.312926 ==
4605 06:48:18.313025
4606 06:48:18.313111
4607 06:48:18.316130 TX Vref Scan disable
4608 06:48:18.319263 == TX Byte 0 ==
4609 06:48:18.322557 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4610 06:48:18.325915 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4611 06:48:18.329149 == TX Byte 1 ==
4612 06:48:18.332429 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4613 06:48:18.335702 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4614 06:48:18.335798
4615 06:48:18.339203 [DATLAT]
4616 06:48:18.339302 Freq=600, CH1 RK0
4617 06:48:18.339401
4618 06:48:18.342578 DATLAT Default: 0x9
4619 06:48:18.342669 0, 0xFFFF, sum = 0
4620 06:48:18.346001 1, 0xFFFF, sum = 0
4621 06:48:18.346085 2, 0xFFFF, sum = 0
4622 06:48:18.349232 3, 0xFFFF, sum = 0
4623 06:48:18.349313 4, 0xFFFF, sum = 0
4624 06:48:18.352454 5, 0xFFFF, sum = 0
4625 06:48:18.352530 6, 0xFFFF, sum = 0
4626 06:48:18.355758 7, 0xFFFF, sum = 0
4627 06:48:18.355836 8, 0x0, sum = 1
4628 06:48:18.358985 9, 0x0, sum = 2
4629 06:48:18.359067 10, 0x0, sum = 3
4630 06:48:18.362421 11, 0x0, sum = 4
4631 06:48:18.362531 best_step = 9
4632 06:48:18.362624
4633 06:48:18.362723 ==
4634 06:48:18.365482 Dram Type= 6, Freq= 0, CH_1, rank 0
4635 06:48:18.372101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 06:48:18.372213 ==
4637 06:48:18.372307 RX Vref Scan: 1
4638 06:48:18.372405
4639 06:48:18.375407 RX Vref 0 -> 0, step: 1
4640 06:48:18.375494
4641 06:48:18.379055 RX Delay -195 -> 252, step: 8
4642 06:48:18.379132
4643 06:48:18.382259 Set Vref, RX VrefLevel [Byte0]: 54
4644 06:48:18.385303 [Byte1]: 52
4645 06:48:18.385415
4646 06:48:18.388689 Final RX Vref Byte 0 = 54 to rank0
4647 06:48:18.392151 Final RX Vref Byte 1 = 52 to rank0
4648 06:48:18.395323 Final RX Vref Byte 0 = 54 to rank1
4649 06:48:18.398433 Final RX Vref Byte 1 = 52 to rank1==
4650 06:48:18.402083 Dram Type= 6, Freq= 0, CH_1, rank 0
4651 06:48:18.405397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 06:48:18.405508 ==
4653 06:48:18.408769 DQS Delay:
4654 06:48:18.408878 DQS0 = 0, DQS1 = 0
4655 06:48:18.408970 DQM Delay:
4656 06:48:18.411816 DQM0 = 39, DQM1 = 27
4657 06:48:18.411914 DQ Delay:
4658 06:48:18.415388 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4659 06:48:18.418641 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4660 06:48:18.421936 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4661 06:48:18.424893 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4662 06:48:18.425000
4663 06:48:18.425092
4664 06:48:18.435025 [DQSOSCAuto] RK0, (LSB)MR18= 0x2330, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4665 06:48:18.438418 CH1 RK0: MR19=808, MR18=2330
4666 06:48:18.441710 CH1_RK0: MR19=0x808, MR18=0x2330, DQSOSC=400, MR23=63, INC=163, DEC=109
4667 06:48:18.444998
4668 06:48:18.448224 ----->DramcWriteLeveling(PI) begin...
4669 06:48:18.448323 ==
4670 06:48:18.451532 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 06:48:18.454909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 06:48:18.455017 ==
4673 06:48:18.458195 Write leveling (Byte 0): 30 => 30
4674 06:48:18.461763 Write leveling (Byte 1): 30 => 30
4675 06:48:18.464786 DramcWriteLeveling(PI) end<-----
4676 06:48:18.464859
4677 06:48:18.464921 ==
4678 06:48:18.468183 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 06:48:18.471318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 06:48:18.471434 ==
4681 06:48:18.474638 [Gating] SW mode calibration
4682 06:48:18.481291 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4683 06:48:18.488074 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4684 06:48:18.491373 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4685 06:48:18.494531 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4686 06:48:18.501131 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4687 06:48:18.504413 0 9 12 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (0 0)
4688 06:48:18.507760 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4689 06:48:18.514666 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 06:48:18.517960 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4691 06:48:18.521252 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 06:48:18.527801 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 06:48:18.531046 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 06:48:18.534064 0 10 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
4695 06:48:18.540983 0 10 12 | B1->B0 | 3333 3a3a | 0 1 | (0 0) (0 0)
4696 06:48:18.544248 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
4697 06:48:18.547730 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 06:48:18.554218 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 06:48:18.557351 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 06:48:18.560765 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 06:48:18.567200 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 06:48:18.570850 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 06:48:18.574106 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4704 06:48:18.580704 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 06:48:18.584028 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 06:48:18.587232 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 06:48:18.593793 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 06:48:18.596927 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 06:48:18.600378 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 06:48:18.603753 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 06:48:18.610320 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 06:48:18.613552 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 06:48:18.616897 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 06:48:18.623772 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 06:48:18.627069 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 06:48:18.630302 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 06:48:18.636803 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 06:48:18.640076 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 06:48:18.643710 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4720 06:48:18.646961 Total UI for P1: 0, mck2ui 16
4721 06:48:18.649891 best dqsien dly found for B0: ( 0, 13, 10)
4722 06:48:18.656501 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 06:48:18.659791 Total UI for P1: 0, mck2ui 16
4724 06:48:18.663058 best dqsien dly found for B1: ( 0, 13, 12)
4725 06:48:18.666802 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4726 06:48:18.670070 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4727 06:48:18.670157
4728 06:48:18.673031 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4729 06:48:18.676358 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4730 06:48:18.679989 [Gating] SW calibration Done
4731 06:48:18.680098 ==
4732 06:48:18.682945 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 06:48:18.686542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 06:48:18.686619 ==
4735 06:48:18.689759 RX Vref Scan: 0
4736 06:48:18.689866
4737 06:48:18.693249 RX Vref 0 -> 0, step: 1
4738 06:48:18.693356
4739 06:48:18.693448 RX Delay -230 -> 252, step: 16
4740 06:48:18.699525 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4741 06:48:18.702948 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4742 06:48:18.706177 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4743 06:48:18.709501 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4744 06:48:18.716432 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4745 06:48:18.719429 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4746 06:48:18.723024 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4747 06:48:18.726326 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4748 06:48:18.732733 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4749 06:48:18.736179 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4750 06:48:18.739527 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4751 06:48:18.742783 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4752 06:48:18.746202 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4753 06:48:18.752920 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4754 06:48:18.756218 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4755 06:48:18.759544 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4756 06:48:18.759626 ==
4757 06:48:18.762906 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 06:48:18.766181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 06:48:18.769388 ==
4760 06:48:18.769502 DQS Delay:
4761 06:48:18.769569 DQS0 = 0, DQS1 = 0
4762 06:48:18.772706 DQM Delay:
4763 06:48:18.772778 DQM0 = 35, DQM1 = 29
4764 06:48:18.776063 DQ Delay:
4765 06:48:18.779345 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4766 06:48:18.779429 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4767 06:48:18.782721 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4768 06:48:18.789255 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4769 06:48:18.789362
4770 06:48:18.789463
4771 06:48:18.789538 ==
4772 06:48:18.792683 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 06:48:18.796003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 06:48:18.796103 ==
4775 06:48:18.796193
4776 06:48:18.796289
4777 06:48:18.799127 TX Vref Scan disable
4778 06:48:18.799207 == TX Byte 0 ==
4779 06:48:18.805681 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4780 06:48:18.809067 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4781 06:48:18.809169 == TX Byte 1 ==
4782 06:48:18.815898 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4783 06:48:18.819054 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4784 06:48:18.819139 ==
4785 06:48:18.822468 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 06:48:18.825883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 06:48:18.825960 ==
4788 06:48:18.826027
4789 06:48:18.826090
4790 06:48:18.828883 TX Vref Scan disable
4791 06:48:18.832201 == TX Byte 0 ==
4792 06:48:18.835530 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4793 06:48:18.838784 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4794 06:48:18.842331 == TX Byte 1 ==
4795 06:48:18.845678 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4796 06:48:18.852168 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4797 06:48:18.852250
4798 06:48:18.852315 [DATLAT]
4799 06:48:18.852377 Freq=600, CH1 RK1
4800 06:48:18.852440
4801 06:48:18.855519 DATLAT Default: 0x9
4802 06:48:18.855591 0, 0xFFFF, sum = 0
4803 06:48:18.858879 1, 0xFFFF, sum = 0
4804 06:48:18.858961 2, 0xFFFF, sum = 0
4805 06:48:18.862375 3, 0xFFFF, sum = 0
4806 06:48:18.862458 4, 0xFFFF, sum = 0
4807 06:48:18.865547 5, 0xFFFF, sum = 0
4808 06:48:18.868814 6, 0xFFFF, sum = 0
4809 06:48:18.868893 7, 0xFFFF, sum = 0
4810 06:48:18.868960 8, 0x0, sum = 1
4811 06:48:18.872212 9, 0x0, sum = 2
4812 06:48:18.872285 10, 0x0, sum = 3
4813 06:48:18.875550 11, 0x0, sum = 4
4814 06:48:18.875621 best_step = 9
4815 06:48:18.875687
4816 06:48:18.875748 ==
4817 06:48:18.878925 Dram Type= 6, Freq= 0, CH_1, rank 1
4818 06:48:18.885544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4819 06:48:18.885621 ==
4820 06:48:18.885688 RX Vref Scan: 0
4821 06:48:18.885752
4822 06:48:18.888869 RX Vref 0 -> 0, step: 1
4823 06:48:18.888945
4824 06:48:18.892151 RX Delay -195 -> 252, step: 8
4825 06:48:18.895558 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4826 06:48:18.901761 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4827 06:48:18.905450 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4828 06:48:18.908608 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4829 06:48:18.911881 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4830 06:48:18.918326 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4831 06:48:18.921548 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4832 06:48:18.924976 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4833 06:48:18.928568 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4834 06:48:18.931685 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4835 06:48:18.938559 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4836 06:48:18.941807 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4837 06:48:18.945104 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4838 06:48:18.948433 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4839 06:48:18.955094 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4840 06:48:18.958332 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4841 06:48:18.958409 ==
4842 06:48:18.961815 Dram Type= 6, Freq= 0, CH_1, rank 1
4843 06:48:18.965166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4844 06:48:18.965241 ==
4845 06:48:18.968437 DQS Delay:
4846 06:48:18.968508 DQS0 = 0, DQS1 = 0
4847 06:48:18.968585 DQM Delay:
4848 06:48:18.971677 DQM0 = 36, DQM1 = 28
4849 06:48:18.971753 DQ Delay:
4850 06:48:18.974902 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4851 06:48:18.978137 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4852 06:48:18.981650 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4853 06:48:18.984904 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4854 06:48:18.985024
4855 06:48:18.985141
4856 06:48:18.994793 [DQSOSCAuto] RK1, (LSB)MR18= 0x395a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4857 06:48:18.998083 CH1 RK1: MR19=808, MR18=395A
4858 06:48:19.001732 CH1_RK1: MR19=0x808, MR18=0x395A, DQSOSC=392, MR23=63, INC=170, DEC=113
4859 06:48:19.005027 [RxdqsGatingPostProcess] freq 600
4860 06:48:19.011556 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4861 06:48:19.014883 Pre-setting of DQS Precalculation
4862 06:48:19.018003 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4863 06:48:19.028115 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4864 06:48:19.034747 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4865 06:48:19.034860
4866 06:48:19.034939
4867 06:48:19.037805 [Calibration Summary] 1200 Mbps
4868 06:48:19.037888 CH 0, Rank 0
4869 06:48:19.041189 SW Impedance : PASS
4870 06:48:19.041269 DUTY Scan : NO K
4871 06:48:19.044781 ZQ Calibration : PASS
4872 06:48:19.047870 Jitter Meter : NO K
4873 06:48:19.047950 CBT Training : PASS
4874 06:48:19.051185 Write leveling : PASS
4875 06:48:19.054261 RX DQS gating : PASS
4876 06:48:19.054335 RX DQ/DQS(RDDQC) : PASS
4877 06:48:19.057920 TX DQ/DQS : PASS
4878 06:48:19.061117 RX DATLAT : PASS
4879 06:48:19.061192 RX DQ/DQS(Engine): PASS
4880 06:48:19.064364 TX OE : NO K
4881 06:48:19.064473 All Pass.
4882 06:48:19.064549
4883 06:48:19.067611 CH 0, Rank 1
4884 06:48:19.067687 SW Impedance : PASS
4885 06:48:19.070829 DUTY Scan : NO K
4886 06:48:19.070940 ZQ Calibration : PASS
4887 06:48:19.074236 Jitter Meter : NO K
4888 06:48:19.077630 CBT Training : PASS
4889 06:48:19.077704 Write leveling : PASS
4890 06:48:19.080803 RX DQS gating : PASS
4891 06:48:19.084313 RX DQ/DQS(RDDQC) : PASS
4892 06:48:19.084387 TX DQ/DQS : PASS
4893 06:48:19.087682 RX DATLAT : PASS
4894 06:48:19.090697 RX DQ/DQS(Engine): PASS
4895 06:48:19.090812 TX OE : NO K
4896 06:48:19.094204 All Pass.
4897 06:48:19.094277
4898 06:48:19.094340 CH 1, Rank 0
4899 06:48:19.097426 SW Impedance : PASS
4900 06:48:19.097514 DUTY Scan : NO K
4901 06:48:19.100678 ZQ Calibration : PASS
4902 06:48:19.104047 Jitter Meter : NO K
4903 06:48:19.104121 CBT Training : PASS
4904 06:48:19.107426 Write leveling : PASS
4905 06:48:19.110695 RX DQS gating : PASS
4906 06:48:19.110776 RX DQ/DQS(RDDQC) : PASS
4907 06:48:19.113944 TX DQ/DQS : PASS
4908 06:48:19.117125 RX DATLAT : PASS
4909 06:48:19.117206 RX DQ/DQS(Engine): PASS
4910 06:48:19.120445 TX OE : NO K
4911 06:48:19.120515 All Pass.
4912 06:48:19.120582
4913 06:48:19.124130 CH 1, Rank 1
4914 06:48:19.124204 SW Impedance : PASS
4915 06:48:19.127047 DUTY Scan : NO K
4916 06:48:19.130603 ZQ Calibration : PASS
4917 06:48:19.130681 Jitter Meter : NO K
4918 06:48:19.133905 CBT Training : PASS
4919 06:48:19.133983 Write leveling : PASS
4920 06:48:19.137147 RX DQS gating : PASS
4921 06:48:19.140630 RX DQ/DQS(RDDQC) : PASS
4922 06:48:19.140709 TX DQ/DQS : PASS
4923 06:48:19.143639 RX DATLAT : PASS
4924 06:48:19.146998 RX DQ/DQS(Engine): PASS
4925 06:48:19.147070 TX OE : NO K
4926 06:48:19.150650 All Pass.
4927 06:48:19.150725
4928 06:48:19.150788 DramC Write-DBI off
4929 06:48:19.154051 PER_BANK_REFRESH: Hybrid Mode
4930 06:48:19.154134 TX_TRACKING: ON
4931 06:48:19.163770 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4932 06:48:19.167099 [FAST_K] Save calibration result to emmc
4933 06:48:19.170247 dramc_set_vcore_voltage set vcore to 662500
4934 06:48:19.173849 Read voltage for 933, 3
4935 06:48:19.173921 Vio18 = 0
4936 06:48:19.177166 Vcore = 662500
4937 06:48:19.177247 Vdram = 0
4938 06:48:19.177311 Vddq = 0
4939 06:48:19.180366 Vmddr = 0
4940 06:48:19.183577 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4941 06:48:19.190536 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4942 06:48:19.190612 MEM_TYPE=3, freq_sel=17
4943 06:48:19.193808 sv_algorithm_assistance_LP4_1600
4944 06:48:19.200108 ============ PULL DRAM RESETB DOWN ============
4945 06:48:19.203566 ========== PULL DRAM RESETB DOWN end =========
4946 06:48:19.206703 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4947 06:48:19.210352 ===================================
4948 06:48:19.213614 LPDDR4 DRAM CONFIGURATION
4949 06:48:19.216880 ===================================
4950 06:48:19.216987 EX_ROW_EN[0] = 0x0
4951 06:48:19.220154 EX_ROW_EN[1] = 0x0
4952 06:48:19.223452 LP4Y_EN = 0x0
4953 06:48:19.223562 WORK_FSP = 0x0
4954 06:48:19.226749 WL = 0x3
4955 06:48:19.226824 RL = 0x3
4956 06:48:19.229998 BL = 0x2
4957 06:48:19.230070 RPST = 0x0
4958 06:48:19.233421 RD_PRE = 0x0
4959 06:48:19.233507 WR_PRE = 0x1
4960 06:48:19.236839 WR_PST = 0x0
4961 06:48:19.236919 DBI_WR = 0x0
4962 06:48:19.240220 DBI_RD = 0x0
4963 06:48:19.240299 OTF = 0x1
4964 06:48:19.243111 ===================================
4965 06:48:19.246747 ===================================
4966 06:48:19.250070 ANA top config
4967 06:48:19.253798 ===================================
4968 06:48:19.253872 DLL_ASYNC_EN = 0
4969 06:48:19.256982 ALL_SLAVE_EN = 1
4970 06:48:19.260216 NEW_RANK_MODE = 1
4971 06:48:19.263468 DLL_IDLE_MODE = 1
4972 06:48:19.266715 LP45_APHY_COMB_EN = 1
4973 06:48:19.266792 TX_ODT_DIS = 1
4974 06:48:19.269894 NEW_8X_MODE = 1
4975 06:48:19.273322 ===================================
4976 06:48:19.276471 ===================================
4977 06:48:19.280131 data_rate = 1866
4978 06:48:19.283404 CKR = 1
4979 06:48:19.286518 DQ_P2S_RATIO = 8
4980 06:48:19.289841 ===================================
4981 06:48:19.289920 CA_P2S_RATIO = 8
4982 06:48:19.293122 DQ_CA_OPEN = 0
4983 06:48:19.296378 DQ_SEMI_OPEN = 0
4984 06:48:19.299844 CA_SEMI_OPEN = 0
4985 06:48:19.303188 CA_FULL_RATE = 0
4986 06:48:19.306334 DQ_CKDIV4_EN = 1
4987 06:48:19.306411 CA_CKDIV4_EN = 1
4988 06:48:19.309816 CA_PREDIV_EN = 0
4989 06:48:19.313021 PH8_DLY = 0
4990 06:48:19.316394 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4991 06:48:19.319650 DQ_AAMCK_DIV = 4
4992 06:48:19.322894 CA_AAMCK_DIV = 4
4993 06:48:19.322994 CA_ADMCK_DIV = 4
4994 06:48:19.326201 DQ_TRACK_CA_EN = 0
4995 06:48:19.329546 CA_PICK = 933
4996 06:48:19.332896 CA_MCKIO = 933
4997 06:48:19.335997 MCKIO_SEMI = 0
4998 06:48:19.339198 PLL_FREQ = 3732
4999 06:48:19.342763 DQ_UI_PI_RATIO = 32
5000 06:48:19.346126 CA_UI_PI_RATIO = 0
5001 06:48:19.346202 ===================================
5002 06:48:19.349529 ===================================
5003 06:48:19.352877 memory_type:LPDDR4
5004 06:48:19.356246 GP_NUM : 10
5005 06:48:19.356324 SRAM_EN : 1
5006 06:48:19.359565 MD32_EN : 0
5007 06:48:19.362814 ===================================
5008 06:48:19.365916 [ANA_INIT] >>>>>>>>>>>>>>
5009 06:48:19.369144 <<<<<< [CONFIGURE PHASE]: ANA_TX
5010 06:48:19.372635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5011 06:48:19.375969 ===================================
5012 06:48:19.376039 data_rate = 1866,PCW = 0X8f00
5013 06:48:19.379330 ===================================
5014 06:48:19.382712 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5015 06:48:19.389354 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5016 06:48:19.395817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5017 06:48:19.399127 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5018 06:48:19.402423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5019 06:48:19.405672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5020 06:48:19.409008 [ANA_INIT] flow start
5021 06:48:19.412330 [ANA_INIT] PLL >>>>>>>>
5022 06:48:19.412403 [ANA_INIT] PLL <<<<<<<<
5023 06:48:19.415528 [ANA_INIT] MIDPI >>>>>>>>
5024 06:48:19.419146 [ANA_INIT] MIDPI <<<<<<<<
5025 06:48:19.419245 [ANA_INIT] DLL >>>>>>>>
5026 06:48:19.422450 [ANA_INIT] flow end
5027 06:48:19.425801 ============ LP4 DIFF to SE enter ============
5028 06:48:19.428958 ============ LP4 DIFF to SE exit ============
5029 06:48:19.432439 [ANA_INIT] <<<<<<<<<<<<<
5030 06:48:19.435874 [Flow] Enable top DCM control >>>>>
5031 06:48:19.439037 [Flow] Enable top DCM control <<<<<
5032 06:48:19.442195 Enable DLL master slave shuffle
5033 06:48:19.448712 ==============================================================
5034 06:48:19.448792 Gating Mode config
5035 06:48:19.455468 ==============================================================
5036 06:48:19.455545 Config description:
5037 06:48:19.465228 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5038 06:48:19.472071 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5039 06:48:19.478638 SELPH_MODE 0: By rank 1: By Phase
5040 06:48:19.485230 ==============================================================
5041 06:48:19.485307 GAT_TRACK_EN = 1
5042 06:48:19.488616 RX_GATING_MODE = 2
5043 06:48:19.491974 RX_GATING_TRACK_MODE = 2
5044 06:48:19.495269 SELPH_MODE = 1
5045 06:48:19.498401 PICG_EARLY_EN = 1
5046 06:48:19.501749 VALID_LAT_VALUE = 1
5047 06:48:19.508241 ==============================================================
5048 06:48:19.511540 Enter into Gating configuration >>>>
5049 06:48:19.514821 Exit from Gating configuration <<<<
5050 06:48:19.518453 Enter into DVFS_PRE_config >>>>>
5051 06:48:19.528263 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5052 06:48:19.531392 Exit from DVFS_PRE_config <<<<<
5053 06:48:19.534712 Enter into PICG configuration >>>>
5054 06:48:19.538322 Exit from PICG configuration <<<<
5055 06:48:19.541423 [RX_INPUT] configuration >>>>>
5056 06:48:19.541531 [RX_INPUT] configuration <<<<<
5057 06:48:19.548293 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5058 06:48:19.554639 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5059 06:48:19.561534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5060 06:48:19.564876 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5061 06:48:19.571196 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5062 06:48:19.577959 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5063 06:48:19.581230 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5064 06:48:19.584552 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5065 06:48:19.591199 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5066 06:48:19.594360 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5067 06:48:19.597684 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5068 06:48:19.604584 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5069 06:48:19.607749 ===================================
5070 06:48:19.607840 LPDDR4 DRAM CONFIGURATION
5071 06:48:19.611036 ===================================
5072 06:48:19.614192 EX_ROW_EN[0] = 0x0
5073 06:48:19.617463 EX_ROW_EN[1] = 0x0
5074 06:48:19.617557 LP4Y_EN = 0x0
5075 06:48:19.620788 WORK_FSP = 0x0
5076 06:48:19.620856 WL = 0x3
5077 06:48:19.624323 RL = 0x3
5078 06:48:19.624399 BL = 0x2
5079 06:48:19.627621 RPST = 0x0
5080 06:48:19.627689 RD_PRE = 0x0
5081 06:48:19.630818 WR_PRE = 0x1
5082 06:48:19.630891 WR_PST = 0x0
5083 06:48:19.634121 DBI_WR = 0x0
5084 06:48:19.634197 DBI_RD = 0x0
5085 06:48:19.637449 OTF = 0x1
5086 06:48:19.640889 ===================================
5087 06:48:19.644044 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5088 06:48:19.647241 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5089 06:48:19.653891 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5090 06:48:19.657402 ===================================
5091 06:48:19.657489 LPDDR4 DRAM CONFIGURATION
5092 06:48:19.660496 ===================================
5093 06:48:19.663747 EX_ROW_EN[0] = 0x10
5094 06:48:19.667379 EX_ROW_EN[1] = 0x0
5095 06:48:19.667455 LP4Y_EN = 0x0
5096 06:48:19.670573 WORK_FSP = 0x0
5097 06:48:19.670647 WL = 0x3
5098 06:48:19.673961 RL = 0x3
5099 06:48:19.674037 BL = 0x2
5100 06:48:19.677243 RPST = 0x0
5101 06:48:19.677317 RD_PRE = 0x0
5102 06:48:19.680449 WR_PRE = 0x1
5103 06:48:19.680555 WR_PST = 0x0
5104 06:48:19.683805 DBI_WR = 0x0
5105 06:48:19.683910 DBI_RD = 0x0
5106 06:48:19.686922 OTF = 0x1
5107 06:48:19.690322 ===================================
5108 06:48:19.697117 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5109 06:48:19.700336 nWR fixed to 30
5110 06:48:19.700449 [ModeRegInit_LP4] CH0 RK0
5111 06:48:19.703724 [ModeRegInit_LP4] CH0 RK1
5112 06:48:19.707013 [ModeRegInit_LP4] CH1 RK0
5113 06:48:19.710292 [ModeRegInit_LP4] CH1 RK1
5114 06:48:19.710368 match AC timing 9
5115 06:48:19.716892 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5116 06:48:19.720123 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5117 06:48:19.723547 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5118 06:48:19.729944 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5119 06:48:19.733306 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5120 06:48:19.733412 ==
5121 06:48:19.736675 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 06:48:19.739931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 06:48:19.740046 ==
5124 06:48:19.746504 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5125 06:48:19.753030 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5126 06:48:19.756563 [CA 0] Center 38 (8~69) winsize 62
5127 06:48:19.759803 [CA 1] Center 38 (7~69) winsize 63
5128 06:48:19.763078 [CA 2] Center 35 (6~65) winsize 60
5129 06:48:19.766643 [CA 3] Center 34 (4~65) winsize 62
5130 06:48:19.769774 [CA 4] Center 34 (3~65) winsize 63
5131 06:48:19.772866 [CA 5] Center 33 (3~64) winsize 62
5132 06:48:19.772986
5133 06:48:19.776257 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5134 06:48:19.776359
5135 06:48:19.779924 [CATrainingPosCal] consider 1 rank data
5136 06:48:19.783240 u2DelayCellTimex100 = 270/100 ps
5137 06:48:19.786365 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5138 06:48:19.789727 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5139 06:48:19.792753 CA2 delay=35 (6~65),Diff = 2 PI (12 cell)
5140 06:48:19.796301 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5141 06:48:19.799699 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5142 06:48:19.802789 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5143 06:48:19.802870
5144 06:48:19.809438 CA PerBit enable=1, Macro0, CA PI delay=33
5145 06:48:19.809520
5146 06:48:19.812738 [CBTSetCACLKResult] CA Dly = 33
5147 06:48:19.812815 CS Dly: 6 (0~37)
5148 06:48:19.812877 ==
5149 06:48:19.816004 Dram Type= 6, Freq= 0, CH_0, rank 1
5150 06:48:19.819339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5151 06:48:19.819420 ==
5152 06:48:19.826039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5153 06:48:19.832541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5154 06:48:19.835990 [CA 0] Center 38 (8~69) winsize 62
5155 06:48:19.839333 [CA 1] Center 38 (7~69) winsize 63
5156 06:48:19.842613 [CA 2] Center 35 (5~66) winsize 62
5157 06:48:19.845791 [CA 3] Center 35 (5~66) winsize 62
5158 06:48:19.849086 [CA 4] Center 34 (4~65) winsize 62
5159 06:48:19.852467 [CA 5] Center 33 (3~64) winsize 62
5160 06:48:19.852545
5161 06:48:19.855770 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5162 06:48:19.855843
5163 06:48:19.859093 [CATrainingPosCal] consider 2 rank data
5164 06:48:19.862646 u2DelayCellTimex100 = 270/100 ps
5165 06:48:19.865814 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5166 06:48:19.869118 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5167 06:48:19.872367 CA2 delay=35 (6~65),Diff = 2 PI (12 cell)
5168 06:48:19.875764 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5169 06:48:19.879268 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5170 06:48:19.885720 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5171 06:48:19.885800
5172 06:48:19.889092 CA PerBit enable=1, Macro0, CA PI delay=33
5173 06:48:19.889172
5174 06:48:19.892360 [CBTSetCACLKResult] CA Dly = 33
5175 06:48:19.892429 CS Dly: 6 (0~38)
5176 06:48:19.892496
5177 06:48:19.895580 ----->DramcWriteLeveling(PI) begin...
5178 06:48:19.895694 ==
5179 06:48:19.898973 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 06:48:19.905768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 06:48:19.905872 ==
5182 06:48:19.908803 Write leveling (Byte 0): 31 => 31
5183 06:48:19.908907 Write leveling (Byte 1): 29 => 29
5184 06:48:19.912071 DramcWriteLeveling(PI) end<-----
5185 06:48:19.912183
5186 06:48:19.915359 ==
5187 06:48:19.915468 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 06:48:19.921986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 06:48:19.922089 ==
5190 06:48:19.925247 [Gating] SW mode calibration
5191 06:48:19.932151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5192 06:48:19.935389 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5193 06:48:19.941907 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5194 06:48:19.945465 0 14 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5195 06:48:19.948815 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5196 06:48:19.955250 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5197 06:48:19.958563 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 06:48:19.961822 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 06:48:19.968705 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5200 06:48:19.971772 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5201 06:48:19.975200 0 15 0 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
5202 06:48:19.981998 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5203 06:48:19.985060 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 06:48:19.988614 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5205 06:48:19.995091 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 06:48:19.998353 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 06:48:20.001744 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5208 06:48:20.008170 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 06:48:20.011446 1 0 0 | B1->B0 | 2727 3939 | 0 0 | (0 0) (0 0)
5210 06:48:20.014441 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5211 06:48:20.021291 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 06:48:20.024649 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 06:48:20.027842 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 06:48:20.034477 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 06:48:20.037723 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 06:48:20.040927 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5217 06:48:20.047906 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5218 06:48:20.051006 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5219 06:48:20.054346 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 06:48:20.060783 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 06:48:20.064390 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 06:48:20.067612 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 06:48:20.074136 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 06:48:20.077470 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 06:48:20.080638 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 06:48:20.087147 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 06:48:20.090478 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 06:48:20.093897 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 06:48:20.100509 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 06:48:20.104116 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 06:48:20.107127 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 06:48:20.114041 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5233 06:48:20.117331 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5234 06:48:20.120644 Total UI for P1: 0, mck2ui 16
5235 06:48:20.124048 best dqsien dly found for B0: ( 1, 2, 28)
5236 06:48:20.127046 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5237 06:48:20.130372 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5238 06:48:20.133833 Total UI for P1: 0, mck2ui 16
5239 06:48:20.137149 best dqsien dly found for B1: ( 1, 3, 4)
5240 06:48:20.140492 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5241 06:48:20.143869 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5242 06:48:20.147144
5243 06:48:20.150417 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5244 06:48:20.153671 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5245 06:48:20.156874 [Gating] SW calibration Done
5246 06:48:20.156982 ==
5247 06:48:20.160290 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 06:48:20.163669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 06:48:20.163773 ==
5250 06:48:20.163868 RX Vref Scan: 0
5251 06:48:20.163957
5252 06:48:20.166836 RX Vref 0 -> 0, step: 1
5253 06:48:20.166921
5254 06:48:20.170224 RX Delay -80 -> 252, step: 8
5255 06:48:20.173469 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5256 06:48:20.176837 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5257 06:48:20.183361 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5258 06:48:20.186687 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5259 06:48:20.190220 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5260 06:48:20.193421 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5261 06:48:20.196642 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5262 06:48:20.199992 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5263 06:48:20.206691 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5264 06:48:20.209973 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5265 06:48:20.213189 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5266 06:48:20.216432 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5267 06:48:20.220085 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5268 06:48:20.226533 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5269 06:48:20.229885 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5270 06:48:20.233106 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5271 06:48:20.233184 ==
5272 06:48:20.236318 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 06:48:20.239739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 06:48:20.239819 ==
5275 06:48:20.242999 DQS Delay:
5276 06:48:20.243077 DQS0 = 0, DQS1 = 0
5277 06:48:20.246407 DQM Delay:
5278 06:48:20.246484 DQM0 = 95, DQM1 = 83
5279 06:48:20.246554 DQ Delay:
5280 06:48:20.249927 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5281 06:48:20.252887 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5282 06:48:20.256221 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5283 06:48:20.259513 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5284 06:48:20.259588
5285 06:48:20.259659
5286 06:48:20.262869 ==
5287 06:48:20.266294 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 06:48:20.269742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 06:48:20.269821 ==
5290 06:48:20.269886
5291 06:48:20.269946
5292 06:48:20.272877 TX Vref Scan disable
5293 06:48:20.272959 == TX Byte 0 ==
5294 06:48:20.276194 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5295 06:48:20.282941 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5296 06:48:20.283020 == TX Byte 1 ==
5297 06:48:20.285892 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5298 06:48:20.292937 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5299 06:48:20.293020 ==
5300 06:48:20.296196 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 06:48:20.299299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 06:48:20.299376 ==
5303 06:48:20.299441
5304 06:48:20.299502
5305 06:48:20.302733 TX Vref Scan disable
5306 06:48:20.305877 == TX Byte 0 ==
5307 06:48:20.309270 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5308 06:48:20.312661 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5309 06:48:20.316011 == TX Byte 1 ==
5310 06:48:20.319187 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5311 06:48:20.322985 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5312 06:48:20.323067
5313 06:48:20.325994 [DATLAT]
5314 06:48:20.326074 Freq=933, CH0 RK0
5315 06:48:20.326142
5316 06:48:20.329338 DATLAT Default: 0xd
5317 06:48:20.329413 0, 0xFFFF, sum = 0
5318 06:48:20.332496 1, 0xFFFF, sum = 0
5319 06:48:20.332575 2, 0xFFFF, sum = 0
5320 06:48:20.335766 3, 0xFFFF, sum = 0
5321 06:48:20.335844 4, 0xFFFF, sum = 0
5322 06:48:20.339106 5, 0xFFFF, sum = 0
5323 06:48:20.339182 6, 0xFFFF, sum = 0
5324 06:48:20.342334 7, 0xFFFF, sum = 0
5325 06:48:20.342413 8, 0xFFFF, sum = 0
5326 06:48:20.345636 9, 0xFFFF, sum = 0
5327 06:48:20.345718 10, 0x0, sum = 1
5328 06:48:20.349164 11, 0x0, sum = 2
5329 06:48:20.349245 12, 0x0, sum = 3
5330 06:48:20.352169 13, 0x0, sum = 4
5331 06:48:20.352254 best_step = 11
5332 06:48:20.352318
5333 06:48:20.352378 ==
5334 06:48:20.355797 Dram Type= 6, Freq= 0, CH_0, rank 0
5335 06:48:20.358887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 06:48:20.362354 ==
5337 06:48:20.362446 RX Vref Scan: 1
5338 06:48:20.362512
5339 06:48:20.365705 RX Vref 0 -> 0, step: 1
5340 06:48:20.365788
5341 06:48:20.369016 RX Delay -69 -> 252, step: 4
5342 06:48:20.369099
5343 06:48:20.372228 Set Vref, RX VrefLevel [Byte0]: 63
5344 06:48:20.375809 [Byte1]: 52
5345 06:48:20.375901
5346 06:48:20.378806 Final RX Vref Byte 0 = 63 to rank0
5347 06:48:20.382160 Final RX Vref Byte 1 = 52 to rank0
5348 06:48:20.385469 Final RX Vref Byte 0 = 63 to rank1
5349 06:48:20.389092 Final RX Vref Byte 1 = 52 to rank1==
5350 06:48:20.392048 Dram Type= 6, Freq= 0, CH_0, rank 0
5351 06:48:20.395740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 06:48:20.395836 ==
5353 06:48:20.398690 DQS Delay:
5354 06:48:20.398772 DQS0 = 0, DQS1 = 0
5355 06:48:20.398838 DQM Delay:
5356 06:48:20.401949 DQM0 = 96, DQM1 = 82
5357 06:48:20.402038 DQ Delay:
5358 06:48:20.405656 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5359 06:48:20.408961 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =108
5360 06:48:20.412232 DQ8 =76, DQ9 =68, DQ10 =82, DQ11 =76
5361 06:48:20.415784 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5362 06:48:20.415869
5363 06:48:20.415938
5364 06:48:20.425520 [DQSOSCAuto] RK0, (LSB)MR18= 0x1716, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5365 06:48:20.425607 CH0 RK0: MR19=505, MR18=1716
5366 06:48:20.432073 CH0_RK0: MR19=0x505, MR18=0x1716, DQSOSC=414, MR23=63, INC=63, DEC=42
5367 06:48:20.432154
5368 06:48:20.435472 ----->DramcWriteLeveling(PI) begin...
5369 06:48:20.435552 ==
5370 06:48:20.438988 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 06:48:20.445703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 06:48:20.445784 ==
5373 06:48:20.448735 Write leveling (Byte 0): 35 => 35
5374 06:48:20.452031 Write leveling (Byte 1): 27 => 27
5375 06:48:20.452110 DramcWriteLeveling(PI) end<-----
5376 06:48:20.455422
5377 06:48:20.455509 ==
5378 06:48:20.458673 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 06:48:20.462122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 06:48:20.462204 ==
5381 06:48:20.465440 [Gating] SW mode calibration
5382 06:48:20.471951 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5383 06:48:20.475455 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5384 06:48:20.481791 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
5385 06:48:20.485294 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 06:48:20.488523 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 06:48:20.495197 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5388 06:48:20.498431 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 06:48:20.501747 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 06:48:20.508349 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5391 06:48:20.511649 0 14 28 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (0 1)
5392 06:48:20.515311 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5393 06:48:20.521719 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 06:48:20.524867 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 06:48:20.528171 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 06:48:20.534794 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 06:48:20.538085 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 06:48:20.541374 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 06:48:20.548265 0 15 28 | B1->B0 | 2727 3737 | 0 0 | (0 0) (0 0)
5400 06:48:20.551305 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5401 06:48:20.554630 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 06:48:20.561583 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 06:48:20.564616 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 06:48:20.568230 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 06:48:20.574909 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 06:48:20.577911 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 06:48:20.581186 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5408 06:48:20.587737 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5409 06:48:20.591292 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 06:48:20.594757 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 06:48:20.601154 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 06:48:20.604562 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 06:48:20.607802 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 06:48:20.614399 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 06:48:20.617693 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 06:48:20.621302 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 06:48:20.627819 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 06:48:20.631085 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 06:48:20.634560 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 06:48:20.640917 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 06:48:20.644502 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 06:48:20.647543 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 06:48:20.651214 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5424 06:48:20.657765 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 06:48:20.660976 Total UI for P1: 0, mck2ui 16
5426 06:48:20.664247 best dqsien dly found for B0: ( 1, 2, 28)
5427 06:48:20.667471 Total UI for P1: 0, mck2ui 16
5428 06:48:20.670824 best dqsien dly found for B1: ( 1, 2, 28)
5429 06:48:20.674039 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5430 06:48:20.677317 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5431 06:48:20.677432
5432 06:48:20.680829 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5433 06:48:20.684094 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5434 06:48:20.687330 [Gating] SW calibration Done
5435 06:48:20.687442 ==
5436 06:48:20.690506 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 06:48:20.693783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 06:48:20.693859 ==
5439 06:48:20.697272 RX Vref Scan: 0
5440 06:48:20.697372
5441 06:48:20.700492 RX Vref 0 -> 0, step: 1
5442 06:48:20.700599
5443 06:48:20.700690 RX Delay -80 -> 252, step: 8
5444 06:48:20.707032 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5445 06:48:20.710367 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5446 06:48:20.713959 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5447 06:48:20.717235 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5448 06:48:20.720172 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5449 06:48:20.726878 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5450 06:48:20.730368 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5451 06:48:20.733633 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5452 06:48:20.736894 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5453 06:48:20.740209 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5454 06:48:20.743493 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5455 06:48:20.750103 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5456 06:48:20.753412 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5457 06:48:20.756961 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5458 06:48:20.760214 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5459 06:48:20.763568 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5460 06:48:20.766788 ==
5461 06:48:20.770135 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 06:48:20.773467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 06:48:20.773553 ==
5464 06:48:20.773616 DQS Delay:
5465 06:48:20.776524 DQS0 = 0, DQS1 = 0
5466 06:48:20.776621 DQM Delay:
5467 06:48:20.779840 DQM0 = 92, DQM1 = 83
5468 06:48:20.779914 DQ Delay:
5469 06:48:20.783416 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =91
5470 06:48:20.786693 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5471 06:48:20.789775 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5472 06:48:20.793318 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =87
5473 06:48:20.793424
5474 06:48:20.793524
5475 06:48:20.793619 ==
5476 06:48:20.796449 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 06:48:20.799920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 06:48:20.800020 ==
5479 06:48:20.800119
5480 06:48:20.800206
5481 06:48:20.803271 TX Vref Scan disable
5482 06:48:20.806417 == TX Byte 0 ==
5483 06:48:20.809890 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5484 06:48:20.813297 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5485 06:48:20.816472 == TX Byte 1 ==
5486 06:48:20.819767 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5487 06:48:20.822983 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5488 06:48:20.823066 ==
5489 06:48:20.826333 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 06:48:20.832883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 06:48:20.832972 ==
5492 06:48:20.833040
5493 06:48:20.833118
5494 06:48:20.833185 TX Vref Scan disable
5495 06:48:20.837093 == TX Byte 0 ==
5496 06:48:20.840254 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5497 06:48:20.846797 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5498 06:48:20.846938 == TX Byte 1 ==
5499 06:48:20.850181 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5500 06:48:20.856940 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5501 06:48:20.857036
5502 06:48:20.857104 [DATLAT]
5503 06:48:20.857170 Freq=933, CH0 RK1
5504 06:48:20.857243
5505 06:48:20.860441 DATLAT Default: 0xb
5506 06:48:20.860517 0, 0xFFFF, sum = 0
5507 06:48:20.863483 1, 0xFFFF, sum = 0
5508 06:48:20.863562 2, 0xFFFF, sum = 0
5509 06:48:20.866739 3, 0xFFFF, sum = 0
5510 06:48:20.870284 4, 0xFFFF, sum = 0
5511 06:48:20.870355 5, 0xFFFF, sum = 0
5512 06:48:20.873618 6, 0xFFFF, sum = 0
5513 06:48:20.873690 7, 0xFFFF, sum = 0
5514 06:48:20.876872 8, 0xFFFF, sum = 0
5515 06:48:20.876943 9, 0xFFFF, sum = 0
5516 06:48:20.880090 10, 0x0, sum = 1
5517 06:48:20.880173 11, 0x0, sum = 2
5518 06:48:20.883595 12, 0x0, sum = 3
5519 06:48:20.883718 13, 0x0, sum = 4
5520 06:48:20.883818 best_step = 11
5521 06:48:20.883916
5522 06:48:20.886773 ==
5523 06:48:20.890069 Dram Type= 6, Freq= 0, CH_0, rank 1
5524 06:48:20.893368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 06:48:20.893491 ==
5526 06:48:20.893560 RX Vref Scan: 0
5527 06:48:20.893654
5528 06:48:20.896477 RX Vref 0 -> 0, step: 1
5529 06:48:20.896586
5530 06:48:20.900025 RX Delay -77 -> 252, step: 4
5531 06:48:20.906415 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5532 06:48:20.910017 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5533 06:48:20.913377 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5534 06:48:20.916643 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5535 06:48:20.919711 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5536 06:48:20.923167 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5537 06:48:20.929635 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5538 06:48:20.933130 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5539 06:48:20.936309 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5540 06:48:20.939561 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5541 06:48:20.942860 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5542 06:48:20.949431 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5543 06:48:20.952760 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5544 06:48:20.956014 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5545 06:48:20.959369 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5546 06:48:20.962892 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5547 06:48:20.962974 ==
5548 06:48:20.966189 Dram Type= 6, Freq= 0, CH_0, rank 1
5549 06:48:20.972641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 06:48:20.972734 ==
5551 06:48:20.972805 DQS Delay:
5552 06:48:20.975928 DQS0 = 0, DQS1 = 0
5553 06:48:20.976002 DQM Delay:
5554 06:48:20.976065 DQM0 = 92, DQM1 = 84
5555 06:48:20.979198 DQ Delay:
5556 06:48:20.982489 DQ0 =90, DQ1 =96, DQ2 =88, DQ3 =88
5557 06:48:20.985711 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =104
5558 06:48:20.989151 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =78
5559 06:48:20.992316 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =90
5560 06:48:20.992395
5561 06:48:20.992460
5562 06:48:20.999258 [DQSOSCAuto] RK1, (LSB)MR18= 0x3113, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5563 06:48:21.002519 CH0 RK1: MR19=505, MR18=3113
5564 06:48:21.008985 CH0_RK1: MR19=0x505, MR18=0x3113, DQSOSC=406, MR23=63, INC=65, DEC=43
5565 06:48:21.012399 [RxdqsGatingPostProcess] freq 933
5566 06:48:21.018999 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5567 06:48:21.019086 best DQS0 dly(2T, 0.5T) = (0, 10)
5568 06:48:21.022270 best DQS1 dly(2T, 0.5T) = (0, 11)
5569 06:48:21.025382 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5570 06:48:21.028705 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5571 06:48:21.031962 best DQS0 dly(2T, 0.5T) = (0, 10)
5572 06:48:21.035324 best DQS1 dly(2T, 0.5T) = (0, 10)
5573 06:48:21.038762 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5574 06:48:21.042089 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5575 06:48:21.045433 Pre-setting of DQS Precalculation
5576 06:48:21.051824 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5577 06:48:21.051923 ==
5578 06:48:21.055475 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 06:48:21.058711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 06:48:21.058789 ==
5581 06:48:21.065339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5582 06:48:21.068489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5583 06:48:21.072715 [CA 0] Center 37 (7~68) winsize 62
5584 06:48:21.075740 [CA 1] Center 37 (7~68) winsize 62
5585 06:48:21.079280 [CA 2] Center 34 (5~64) winsize 60
5586 06:48:21.082488 [CA 3] Center 34 (4~64) winsize 61
5587 06:48:21.085835 [CA 4] Center 35 (5~65) winsize 61
5588 06:48:21.089141 [CA 5] Center 33 (4~63) winsize 60
5589 06:48:21.089216
5590 06:48:21.092310 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5591 06:48:21.092408
5592 06:48:21.095768 [CATrainingPosCal] consider 1 rank data
5593 06:48:21.099040 u2DelayCellTimex100 = 270/100 ps
5594 06:48:21.102320 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5595 06:48:21.108789 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5596 06:48:21.112269 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5597 06:48:21.115642 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5598 06:48:21.118761 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5599 06:48:21.122222 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5600 06:48:21.122313
5601 06:48:21.125359 CA PerBit enable=1, Macro0, CA PI delay=33
5602 06:48:21.125459
5603 06:48:21.128775 [CBTSetCACLKResult] CA Dly = 33
5604 06:48:21.131964 CS Dly: 6 (0~37)
5605 06:48:21.132075 ==
5606 06:48:21.135211 Dram Type= 6, Freq= 0, CH_1, rank 1
5607 06:48:21.138605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 06:48:21.138686 ==
5609 06:48:21.145472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5610 06:48:21.148764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5611 06:48:21.152708 [CA 0] Center 37 (8~67) winsize 60
5612 06:48:21.156013 [CA 1] Center 38 (7~69) winsize 63
5613 06:48:21.159110 [CA 2] Center 35 (5~65) winsize 61
5614 06:48:21.162377 [CA 3] Center 34 (4~64) winsize 61
5615 06:48:21.166007 [CA 4] Center 35 (5~65) winsize 61
5616 06:48:21.168979 [CA 5] Center 33 (3~64) winsize 62
5617 06:48:21.169063
5618 06:48:21.172285 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5619 06:48:21.172368
5620 06:48:21.175861 [CATrainingPosCal] consider 2 rank data
5621 06:48:21.179140 u2DelayCellTimex100 = 270/100 ps
5622 06:48:21.182285 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5623 06:48:21.188828 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5624 06:48:21.192139 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5625 06:48:21.195737 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5626 06:48:21.199045 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5627 06:48:21.202321 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5628 06:48:21.202396
5629 06:48:21.205445 CA PerBit enable=1, Macro0, CA PI delay=33
5630 06:48:21.205535
5631 06:48:21.208766 [CBTSetCACLKResult] CA Dly = 33
5632 06:48:21.212356 CS Dly: 7 (0~39)
5633 06:48:21.212437
5634 06:48:21.215450 ----->DramcWriteLeveling(PI) begin...
5635 06:48:21.215552 ==
5636 06:48:21.218750 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 06:48:21.222049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 06:48:21.222128 ==
5639 06:48:21.225517 Write leveling (Byte 0): 25 => 25
5640 06:48:21.228886 Write leveling (Byte 1): 28 => 28
5641 06:48:21.232005 DramcWriteLeveling(PI) end<-----
5642 06:48:21.232088
5643 06:48:21.232185 ==
5644 06:48:21.235438 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 06:48:21.238658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 06:48:21.238740 ==
5647 06:48:21.241940 [Gating] SW mode calibration
5648 06:48:21.248492 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5649 06:48:21.255042 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5650 06:48:21.258684 0 14 0 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5651 06:48:21.261944 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 06:48:21.268538 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5653 06:48:21.271819 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5654 06:48:21.275257 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5655 06:48:21.281973 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5656 06:48:21.285281 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
5657 06:48:21.288467 0 14 28 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 1)
5658 06:48:21.295062 0 15 0 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
5659 06:48:21.298364 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 06:48:21.301770 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 06:48:21.308248 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 06:48:21.311433 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5663 06:48:21.314737 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5664 06:48:21.321537 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5665 06:48:21.324719 0 15 28 | B1->B0 | 2e2e 3434 | 1 0 | (0 0) (0 0)
5666 06:48:21.327946 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5667 06:48:21.334771 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 06:48:21.338010 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 06:48:21.341169 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 06:48:21.347776 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 06:48:21.351371 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 06:48:21.354685 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5673 06:48:21.361207 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5674 06:48:21.364470 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5675 06:48:21.367759 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 06:48:21.374342 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 06:48:21.377811 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 06:48:21.381187 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 06:48:21.384210 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 06:48:21.390838 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 06:48:21.394383 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 06:48:21.397709 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 06:48:21.404219 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 06:48:21.407789 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 06:48:21.410863 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 06:48:21.417347 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 06:48:21.420630 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 06:48:21.424187 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 06:48:21.430960 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5690 06:48:21.434170 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5691 06:48:21.437426 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 06:48:21.440900 Total UI for P1: 0, mck2ui 16
5693 06:48:21.444047 best dqsien dly found for B0: ( 1, 3, 0)
5694 06:48:21.447180 Total UI for P1: 0, mck2ui 16
5695 06:48:21.450765 best dqsien dly found for B1: ( 1, 2, 30)
5696 06:48:21.453854 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5697 06:48:21.457261 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5698 06:48:21.457341
5699 06:48:21.463966 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5700 06:48:21.467250 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5701 06:48:21.470526 [Gating] SW calibration Done
5702 06:48:21.470607 ==
5703 06:48:21.473797 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 06:48:21.476980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 06:48:21.477062 ==
5706 06:48:21.477129 RX Vref Scan: 0
5707 06:48:21.477189
5708 06:48:21.480635 RX Vref 0 -> 0, step: 1
5709 06:48:21.480710
5710 06:48:21.483750 RX Delay -80 -> 252, step: 8
5711 06:48:21.487013 iDelay=208, Bit 0, Center 103 (0 ~ 207) 208
5712 06:48:21.490363 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5713 06:48:21.496691 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5714 06:48:21.500287 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5715 06:48:21.503485 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5716 06:48:21.506711 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5717 06:48:21.510298 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5718 06:48:21.513636 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5719 06:48:21.520283 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5720 06:48:21.523431 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5721 06:48:21.526759 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5722 06:48:21.529953 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5723 06:48:21.533239 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5724 06:48:21.539988 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5725 06:48:21.543243 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5726 06:48:21.546632 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5727 06:48:21.546705 ==
5728 06:48:21.550085 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 06:48:21.553067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 06:48:21.553144 ==
5731 06:48:21.556408 DQS Delay:
5732 06:48:21.556489 DQS0 = 0, DQS1 = 0
5733 06:48:21.559703 DQM Delay:
5734 06:48:21.559779 DQM0 = 94, DQM1 = 87
5735 06:48:21.559846 DQ Delay:
5736 06:48:21.563165 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5737 06:48:21.566265 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5738 06:48:21.569602 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5739 06:48:21.573030 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5740 06:48:21.573104
5741 06:48:21.573168
5742 06:48:21.576317 ==
5743 06:48:21.579678 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 06:48:21.582886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 06:48:21.582960 ==
5746 06:48:21.583023
5747 06:48:21.583086
5748 06:48:21.586165 TX Vref Scan disable
5749 06:48:21.586238 == TX Byte 0 ==
5750 06:48:21.592807 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5751 06:48:21.596080 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5752 06:48:21.596160 == TX Byte 1 ==
5753 06:48:21.602765 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5754 06:48:21.606084 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5755 06:48:21.606175 ==
5756 06:48:21.609744 Dram Type= 6, Freq= 0, CH_1, rank 0
5757 06:48:21.612792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 06:48:21.612893 ==
5759 06:48:21.612994
5760 06:48:21.613084
5761 06:48:21.616113 TX Vref Scan disable
5762 06:48:21.619307 == TX Byte 0 ==
5763 06:48:21.622719 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5764 06:48:21.626087 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5765 06:48:21.629388 == TX Byte 1 ==
5766 06:48:21.632687 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5767 06:48:21.635902 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5768 06:48:21.636006
5769 06:48:21.639132 [DATLAT]
5770 06:48:21.639217 Freq=933, CH1 RK0
5771 06:48:21.639310
5772 06:48:21.642533 DATLAT Default: 0xd
5773 06:48:21.642606 0, 0xFFFF, sum = 0
5774 06:48:21.645839 1, 0xFFFF, sum = 0
5775 06:48:21.645916 2, 0xFFFF, sum = 0
5776 06:48:21.649124 3, 0xFFFF, sum = 0
5777 06:48:21.649232 4, 0xFFFF, sum = 0
5778 06:48:21.652603 5, 0xFFFF, sum = 0
5779 06:48:21.652681 6, 0xFFFF, sum = 0
5780 06:48:21.655790 7, 0xFFFF, sum = 0
5781 06:48:21.655905 8, 0xFFFF, sum = 0
5782 06:48:21.659151 9, 0xFFFF, sum = 0
5783 06:48:21.659227 10, 0x0, sum = 1
5784 06:48:21.662476 11, 0x0, sum = 2
5785 06:48:21.662567 12, 0x0, sum = 3
5786 06:48:21.665747 13, 0x0, sum = 4
5787 06:48:21.665834 best_step = 11
5788 06:48:21.665900
5789 06:48:21.665963 ==
5790 06:48:21.668984 Dram Type= 6, Freq= 0, CH_1, rank 0
5791 06:48:21.675733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 06:48:21.675817 ==
5793 06:48:21.675884 RX Vref Scan: 1
5794 06:48:21.675945
5795 06:48:21.678977 RX Vref 0 -> 0, step: 1
5796 06:48:21.679060
5797 06:48:21.682234 RX Delay -69 -> 252, step: 4
5798 06:48:21.682332
5799 06:48:21.685689 Set Vref, RX VrefLevel [Byte0]: 54
5800 06:48:21.688988 [Byte1]: 52
5801 06:48:21.689080
5802 06:48:21.692208 Final RX Vref Byte 0 = 54 to rank0
5803 06:48:21.695751 Final RX Vref Byte 1 = 52 to rank0
5804 06:48:21.699008 Final RX Vref Byte 0 = 54 to rank1
5805 06:48:21.702259 Final RX Vref Byte 1 = 52 to rank1==
5806 06:48:21.705442 Dram Type= 6, Freq= 0, CH_1, rank 0
5807 06:48:21.708836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 06:48:21.708912 ==
5809 06:48:21.711981 DQS Delay:
5810 06:48:21.712080 DQS0 = 0, DQS1 = 0
5811 06:48:21.712180 DQM Delay:
5812 06:48:21.715382 DQM0 = 96, DQM1 = 89
5813 06:48:21.715481 DQ Delay:
5814 06:48:21.718673 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =92
5815 06:48:21.722218 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =92
5816 06:48:21.725264 DQ8 =76, DQ9 =82, DQ10 =86, DQ11 =82
5817 06:48:21.728711 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5818 06:48:21.728793
5819 06:48:21.728858
5820 06:48:21.738696 [DQSOSCAuto] RK0, (LSB)MR18= 0x30c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5821 06:48:21.741790 CH1 RK0: MR19=505, MR18=30C
5822 06:48:21.745253 CH1_RK0: MR19=0x505, MR18=0x30C, DQSOSC=418, MR23=63, INC=62, DEC=41
5823 06:48:21.745334
5824 06:48:21.748677 ----->DramcWriteLeveling(PI) begin...
5825 06:48:21.751841 ==
5826 06:48:21.755098 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 06:48:21.758494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 06:48:21.758573 ==
5829 06:48:21.761695 Write leveling (Byte 0): 26 => 26
5830 06:48:21.765125 Write leveling (Byte 1): 27 => 27
5831 06:48:21.768376 DramcWriteLeveling(PI) end<-----
5832 06:48:21.768453
5833 06:48:21.768518 ==
5834 06:48:21.771745 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 06:48:21.774822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 06:48:21.774905 ==
5837 06:48:21.778395 [Gating] SW mode calibration
5838 06:48:21.784903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5839 06:48:21.791485 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5840 06:48:21.794817 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5841 06:48:21.798071 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5842 06:48:21.804896 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5843 06:48:21.808154 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5844 06:48:21.811645 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5845 06:48:21.818157 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5846 06:48:21.821436 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 1)
5847 06:48:21.824753 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
5848 06:48:21.831513 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5849 06:48:21.834907 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5850 06:48:21.838062 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5851 06:48:21.841108 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5852 06:48:21.847913 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5853 06:48:21.851257 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 06:48:21.854537 0 15 24 | B1->B0 | 2525 3434 | 1 0 | (0 0) (1 1)
5855 06:48:21.861335 0 15 28 | B1->B0 | 3d3d 4545 | 0 0 | (1 1) (0 0)
5856 06:48:21.864519 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 06:48:21.867700 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 06:48:21.874446 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 06:48:21.877784 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 06:48:21.881019 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 06:48:21.887889 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 06:48:21.891082 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 06:48:21.894657 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 06:48:21.901193 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 06:48:21.904308 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 06:48:21.907716 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 06:48:21.914409 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 06:48:21.917670 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 06:48:21.920945 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 06:48:21.927897 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 06:48:21.931158 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 06:48:21.934293 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 06:48:21.940744 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 06:48:21.944274 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 06:48:21.947714 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 06:48:21.954432 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 06:48:21.957788 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 06:48:21.960889 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5879 06:48:21.964269 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 06:48:21.967857 Total UI for P1: 0, mck2ui 16
5881 06:48:21.971041 best dqsien dly found for B0: ( 1, 2, 24)
5882 06:48:21.974260 Total UI for P1: 0, mck2ui 16
5883 06:48:21.977808 best dqsien dly found for B1: ( 1, 2, 26)
5884 06:48:21.981154 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5885 06:48:21.984454 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5886 06:48:21.987475
5887 06:48:21.990758 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5888 06:48:21.994289 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5889 06:48:21.997410 [Gating] SW calibration Done
5890 06:48:21.997499 ==
5891 06:48:22.000855 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 06:48:22.004180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 06:48:22.004276 ==
5894 06:48:22.007532 RX Vref Scan: 0
5895 06:48:22.007606
5896 06:48:22.007685 RX Vref 0 -> 0, step: 1
5897 06:48:22.007747
5898 06:48:22.010776 RX Delay -80 -> 252, step: 8
5899 06:48:22.013947 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5900 06:48:22.017148 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5901 06:48:22.023776 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5902 06:48:22.027128 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5903 06:48:22.030475 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5904 06:48:22.033806 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5905 06:48:22.037018 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5906 06:48:22.043966 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5907 06:48:22.046856 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5908 06:48:22.050191 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5909 06:48:22.053546 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5910 06:48:22.057090 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5911 06:48:22.060238 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5912 06:48:22.066724 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5913 06:48:22.070124 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5914 06:48:22.073671 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5915 06:48:22.073772 ==
5916 06:48:22.076859 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 06:48:22.080010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 06:48:22.080092 ==
5919 06:48:22.083640 DQS Delay:
5920 06:48:22.083749 DQS0 = 0, DQS1 = 0
5921 06:48:22.086814 DQM Delay:
5922 06:48:22.086887 DQM0 = 94, DQM1 = 88
5923 06:48:22.086949 DQ Delay:
5924 06:48:22.090012 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5925 06:48:22.093267 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5926 06:48:22.096848 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5927 06:48:22.099956 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5928 06:48:22.100059
5929 06:48:22.103176
5930 06:48:22.103282 ==
5931 06:48:22.106711 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 06:48:22.109961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 06:48:22.110039 ==
5934 06:48:22.110105
5935 06:48:22.110165
5936 06:48:22.113132 TX Vref Scan disable
5937 06:48:22.113203 == TX Byte 0 ==
5938 06:48:22.119692 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5939 06:48:22.122946 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5940 06:48:22.123020 == TX Byte 1 ==
5941 06:48:22.129809 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5942 06:48:22.133109 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5943 06:48:22.133182 ==
5944 06:48:22.136387 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 06:48:22.139735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 06:48:22.139814 ==
5947 06:48:22.139876
5948 06:48:22.139937
5949 06:48:22.142766 TX Vref Scan disable
5950 06:48:22.146485 == TX Byte 0 ==
5951 06:48:22.149728 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5952 06:48:22.153124 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5953 06:48:22.156275 == TX Byte 1 ==
5954 06:48:22.159622 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5955 06:48:22.162686 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5956 06:48:22.162766
5957 06:48:22.166109 [DATLAT]
5958 06:48:22.166183 Freq=933, CH1 RK1
5959 06:48:22.166246
5960 06:48:22.169334 DATLAT Default: 0xb
5961 06:48:22.169437 0, 0xFFFF, sum = 0
5962 06:48:22.172731 1, 0xFFFF, sum = 0
5963 06:48:22.172811 2, 0xFFFF, sum = 0
5964 06:48:22.176109 3, 0xFFFF, sum = 0
5965 06:48:22.176217 4, 0xFFFF, sum = 0
5966 06:48:22.179545 5, 0xFFFF, sum = 0
5967 06:48:22.179621 6, 0xFFFF, sum = 0
5968 06:48:22.182803 7, 0xFFFF, sum = 0
5969 06:48:22.182879 8, 0xFFFF, sum = 0
5970 06:48:22.185906 9, 0xFFFF, sum = 0
5971 06:48:22.186000 10, 0x0, sum = 1
5972 06:48:22.189234 11, 0x0, sum = 2
5973 06:48:22.189334 12, 0x0, sum = 3
5974 06:48:22.192478 13, 0x0, sum = 4
5975 06:48:22.192551 best_step = 11
5976 06:48:22.192613
5977 06:48:22.192671 ==
5978 06:48:22.195765 Dram Type= 6, Freq= 0, CH_1, rank 1
5979 06:48:22.202402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5980 06:48:22.202486 ==
5981 06:48:22.202550 RX Vref Scan: 0
5982 06:48:22.202609
5983 06:48:22.205627 RX Vref 0 -> 0, step: 1
5984 06:48:22.205698
5985 06:48:22.208965 RX Delay -69 -> 252, step: 4
5986 06:48:22.212141 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5987 06:48:22.219005 iDelay=203, Bit 1, Center 86 (-13 ~ 186) 200
5988 06:48:22.222307 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5989 06:48:22.225643 iDelay=203, Bit 3, Center 86 (-13 ~ 186) 200
5990 06:48:22.228761 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5991 06:48:22.232129 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5992 06:48:22.238526 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5993 06:48:22.242060 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5994 06:48:22.245298 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5995 06:48:22.248509 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5996 06:48:22.251853 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5997 06:48:22.255114 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5998 06:48:22.261683 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5999 06:48:22.265159 iDelay=203, Bit 13, Center 98 (3 ~ 194) 192
6000 06:48:22.268410 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
6001 06:48:22.271728 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
6002 06:48:22.271827 ==
6003 06:48:22.275179 Dram Type= 6, Freq= 0, CH_1, rank 1
6004 06:48:22.278403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6005 06:48:22.281832 ==
6006 06:48:22.281932 DQS Delay:
6007 06:48:22.282029 DQS0 = 0, DQS1 = 0
6008 06:48:22.284988 DQM Delay:
6009 06:48:22.285065 DQM0 = 91, DQM1 = 90
6010 06:48:22.288172 DQ Delay:
6011 06:48:22.291658 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =86
6012 06:48:22.294950 DQ4 =90, DQ5 =100, DQ6 =104, DQ7 =88
6013 06:48:22.298292 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =82
6014 06:48:22.301634 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
6015 06:48:22.301710
6016 06:48:22.301774
6017 06:48:22.308191 [DQSOSCAuto] RK1, (LSB)MR18= 0x1125, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
6018 06:48:22.311336 CH1 RK1: MR19=505, MR18=1125
6019 06:48:22.318323 CH1_RK1: MR19=0x505, MR18=0x1125, DQSOSC=410, MR23=63, INC=64, DEC=42
6020 06:48:22.321435 [RxdqsGatingPostProcess] freq 933
6021 06:48:22.324500 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6022 06:48:22.327704 best DQS0 dly(2T, 0.5T) = (0, 11)
6023 06:48:22.331342 best DQS1 dly(2T, 0.5T) = (0, 10)
6024 06:48:22.334653 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
6025 06:48:22.337778 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6026 06:48:22.341137 best DQS0 dly(2T, 0.5T) = (0, 10)
6027 06:48:22.344370 best DQS1 dly(2T, 0.5T) = (0, 10)
6028 06:48:22.347892 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6029 06:48:22.350917 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6030 06:48:22.354393 Pre-setting of DQS Precalculation
6031 06:48:22.358022 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6032 06:48:22.367860 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6033 06:48:22.374505 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6034 06:48:22.374609
6035 06:48:22.374701
6036 06:48:22.377565 [Calibration Summary] 1866 Mbps
6037 06:48:22.377657 CH 0, Rank 0
6038 06:48:22.380956 SW Impedance : PASS
6039 06:48:22.381032 DUTY Scan : NO K
6040 06:48:22.384357 ZQ Calibration : PASS
6041 06:48:22.387703 Jitter Meter : NO K
6042 06:48:22.387782 CBT Training : PASS
6043 06:48:22.390863 Write leveling : PASS
6044 06:48:22.394293 RX DQS gating : PASS
6045 06:48:22.394362 RX DQ/DQS(RDDQC) : PASS
6046 06:48:22.397651 TX DQ/DQS : PASS
6047 06:48:22.400920 RX DATLAT : PASS
6048 06:48:22.400997 RX DQ/DQS(Engine): PASS
6049 06:48:22.404127 TX OE : NO K
6050 06:48:22.404210 All Pass.
6051 06:48:22.404272
6052 06:48:22.407481 CH 0, Rank 1
6053 06:48:22.407550 SW Impedance : PASS
6054 06:48:22.410798 DUTY Scan : NO K
6055 06:48:22.414021 ZQ Calibration : PASS
6056 06:48:22.414114 Jitter Meter : NO K
6057 06:48:22.417115 CBT Training : PASS
6058 06:48:22.417217 Write leveling : PASS
6059 06:48:22.420452 RX DQS gating : PASS
6060 06:48:22.423739 RX DQ/DQS(RDDQC) : PASS
6061 06:48:22.423836 TX DQ/DQS : PASS
6062 06:48:22.427203 RX DATLAT : PASS
6063 06:48:22.430677 RX DQ/DQS(Engine): PASS
6064 06:48:22.430749 TX OE : NO K
6065 06:48:22.433713 All Pass.
6066 06:48:22.433809
6067 06:48:22.433900 CH 1, Rank 0
6068 06:48:22.437029 SW Impedance : PASS
6069 06:48:22.437127 DUTY Scan : NO K
6070 06:48:22.440260 ZQ Calibration : PASS
6071 06:48:22.443928 Jitter Meter : NO K
6072 06:48:22.444003 CBT Training : PASS
6073 06:48:22.447304 Write leveling : PASS
6074 06:48:22.450653 RX DQS gating : PASS
6075 06:48:22.450726 RX DQ/DQS(RDDQC) : PASS
6076 06:48:22.453663 TX DQ/DQS : PASS
6077 06:48:22.456888 RX DATLAT : PASS
6078 06:48:22.456957 RX DQ/DQS(Engine): PASS
6079 06:48:22.460096 TX OE : NO K
6080 06:48:22.460169 All Pass.
6081 06:48:22.460230
6082 06:48:22.463514 CH 1, Rank 1
6083 06:48:22.463586 SW Impedance : PASS
6084 06:48:22.466817 DUTY Scan : NO K
6085 06:48:22.470315 ZQ Calibration : PASS
6086 06:48:22.470391 Jitter Meter : NO K
6087 06:48:22.473562 CBT Training : PASS
6088 06:48:22.476881 Write leveling : PASS
6089 06:48:22.476951 RX DQS gating : PASS
6090 06:48:22.480231 RX DQ/DQS(RDDQC) : PASS
6091 06:48:22.480304 TX DQ/DQS : PASS
6092 06:48:22.483435 RX DATLAT : PASS
6093 06:48:22.486907 RX DQ/DQS(Engine): PASS
6094 06:48:22.487005 TX OE : NO K
6095 06:48:22.490158 All Pass.
6096 06:48:22.490271
6097 06:48:22.490365 DramC Write-DBI off
6098 06:48:22.493443 PER_BANK_REFRESH: Hybrid Mode
6099 06:48:22.496631 TX_TRACKING: ON
6100 06:48:22.503361 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6101 06:48:22.506683 [FAST_K] Save calibration result to emmc
6102 06:48:22.513279 dramc_set_vcore_voltage set vcore to 650000
6103 06:48:22.513385 Read voltage for 400, 6
6104 06:48:22.513501 Vio18 = 0
6105 06:48:22.516593 Vcore = 650000
6106 06:48:22.516663 Vdram = 0
6107 06:48:22.516722 Vddq = 0
6108 06:48:22.519749 Vmddr = 0
6109 06:48:22.522983 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6110 06:48:22.529624 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6111 06:48:22.533000 MEM_TYPE=3, freq_sel=20
6112 06:48:22.533071 sv_algorithm_assistance_LP4_800
6113 06:48:22.539640 ============ PULL DRAM RESETB DOWN ============
6114 06:48:22.543095 ========== PULL DRAM RESETB DOWN end =========
6115 06:48:22.546211 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6116 06:48:22.549766 ===================================
6117 06:48:22.553084 LPDDR4 DRAM CONFIGURATION
6118 06:48:22.556379 ===================================
6119 06:48:22.559758 EX_ROW_EN[0] = 0x0
6120 06:48:22.559858 EX_ROW_EN[1] = 0x0
6121 06:48:22.563066 LP4Y_EN = 0x0
6122 06:48:22.563154 WORK_FSP = 0x0
6123 06:48:22.566265 WL = 0x2
6124 06:48:22.566341 RL = 0x2
6125 06:48:22.569492 BL = 0x2
6126 06:48:22.569560 RPST = 0x0
6127 06:48:22.572755 RD_PRE = 0x0
6128 06:48:22.572831 WR_PRE = 0x1
6129 06:48:22.576167 WR_PST = 0x0
6130 06:48:22.576244 DBI_WR = 0x0
6131 06:48:22.579449 DBI_RD = 0x0
6132 06:48:22.579562 OTF = 0x1
6133 06:48:22.582818 ===================================
6134 06:48:22.586255 ===================================
6135 06:48:22.589538 ANA top config
6136 06:48:22.592632 ===================================
6137 06:48:22.596137 DLL_ASYNC_EN = 0
6138 06:48:22.596236 ALL_SLAVE_EN = 1
6139 06:48:22.599332 NEW_RANK_MODE = 1
6140 06:48:22.602681 DLL_IDLE_MODE = 1
6141 06:48:22.605911 LP45_APHY_COMB_EN = 1
6142 06:48:22.605987 TX_ODT_DIS = 1
6143 06:48:22.609160 NEW_8X_MODE = 1
6144 06:48:22.612491 ===================================
6145 06:48:22.616125 ===================================
6146 06:48:22.619132 data_rate = 800
6147 06:48:22.622554 CKR = 1
6148 06:48:22.625900 DQ_P2S_RATIO = 4
6149 06:48:22.629139 ===================================
6150 06:48:22.632486 CA_P2S_RATIO = 4
6151 06:48:22.632570 DQ_CA_OPEN = 0
6152 06:48:22.635784 DQ_SEMI_OPEN = 1
6153 06:48:22.639049 CA_SEMI_OPEN = 1
6154 06:48:22.642766 CA_FULL_RATE = 0
6155 06:48:22.645865 DQ_CKDIV4_EN = 0
6156 06:48:22.649126 CA_CKDIV4_EN = 1
6157 06:48:22.649210 CA_PREDIV_EN = 0
6158 06:48:22.652637 PH8_DLY = 0
6159 06:48:22.655955 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6160 06:48:22.658936 DQ_AAMCK_DIV = 0
6161 06:48:22.662362 CA_AAMCK_DIV = 0
6162 06:48:22.665654 CA_ADMCK_DIV = 4
6163 06:48:22.665725 DQ_TRACK_CA_EN = 0
6164 06:48:22.669265 CA_PICK = 800
6165 06:48:22.672522 CA_MCKIO = 400
6166 06:48:22.675860 MCKIO_SEMI = 400
6167 06:48:22.679125 PLL_FREQ = 3016
6168 06:48:22.682226 DQ_UI_PI_RATIO = 32
6169 06:48:22.685535 CA_UI_PI_RATIO = 32
6170 06:48:22.689097 ===================================
6171 06:48:22.692261 ===================================
6172 06:48:22.692365 memory_type:LPDDR4
6173 06:48:22.695721 GP_NUM : 10
6174 06:48:22.698959 SRAM_EN : 1
6175 06:48:22.699036 MD32_EN : 0
6176 06:48:22.702081 ===================================
6177 06:48:22.705459 [ANA_INIT] >>>>>>>>>>>>>>
6178 06:48:22.708727 <<<<<< [CONFIGURE PHASE]: ANA_TX
6179 06:48:22.712310 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6180 06:48:22.715465 ===================================
6181 06:48:22.718756 data_rate = 800,PCW = 0X7400
6182 06:48:22.722054 ===================================
6183 06:48:22.725209 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6184 06:48:22.728716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6185 06:48:22.741790 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6186 06:48:22.745074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6187 06:48:22.748683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6188 06:48:22.752008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6189 06:48:22.755128 [ANA_INIT] flow start
6190 06:48:22.758515 [ANA_INIT] PLL >>>>>>>>
6191 06:48:22.758600 [ANA_INIT] PLL <<<<<<<<
6192 06:48:22.761866 [ANA_INIT] MIDPI >>>>>>>>
6193 06:48:22.765216 [ANA_INIT] MIDPI <<<<<<<<
6194 06:48:22.765315 [ANA_INIT] DLL >>>>>>>>
6195 06:48:22.768591 [ANA_INIT] flow end
6196 06:48:22.771911 ============ LP4 DIFF to SE enter ============
6197 06:48:22.775201 ============ LP4 DIFF to SE exit ============
6198 06:48:22.778472 [ANA_INIT] <<<<<<<<<<<<<
6199 06:48:22.781722 [Flow] Enable top DCM control >>>>>
6200 06:48:22.785017 [Flow] Enable top DCM control <<<<<
6201 06:48:22.788592 Enable DLL master slave shuffle
6202 06:48:22.794985 ==============================================================
6203 06:48:22.795067 Gating Mode config
6204 06:48:22.801678 ==============================================================
6205 06:48:22.801788 Config description:
6206 06:48:22.811878 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6207 06:48:22.818131 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6208 06:48:22.824861 SELPH_MODE 0: By rank 1: By Phase
6209 06:48:22.828248 ==============================================================
6210 06:48:22.831601 GAT_TRACK_EN = 0
6211 06:48:22.834936 RX_GATING_MODE = 2
6212 06:48:22.838120 RX_GATING_TRACK_MODE = 2
6213 06:48:22.841226 SELPH_MODE = 1
6214 06:48:22.844832 PICG_EARLY_EN = 1
6215 06:48:22.848175 VALID_LAT_VALUE = 1
6216 06:48:22.854641 ==============================================================
6217 06:48:22.857776 Enter into Gating configuration >>>>
6218 06:48:22.861119 Exit from Gating configuration <<<<
6219 06:48:22.864635 Enter into DVFS_PRE_config >>>>>
6220 06:48:22.874288 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6221 06:48:22.877697 Exit from DVFS_PRE_config <<<<<
6222 06:48:22.880925 Enter into PICG configuration >>>>
6223 06:48:22.884633 Exit from PICG configuration <<<<
6224 06:48:22.887636 [RX_INPUT] configuration >>>>>
6225 06:48:22.887711 [RX_INPUT] configuration <<<<<
6226 06:48:22.894430 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6227 06:48:22.900993 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6228 06:48:22.904423 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6229 06:48:22.910899 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6230 06:48:22.917744 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6231 06:48:22.924182 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6232 06:48:22.927701 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6233 06:48:22.930986 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6234 06:48:22.937814 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6235 06:48:22.941044 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6236 06:48:22.944439 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6237 06:48:22.951122 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6238 06:48:22.954287 ===================================
6239 06:48:22.954397 LPDDR4 DRAM CONFIGURATION
6240 06:48:22.957560 ===================================
6241 06:48:22.960720 EX_ROW_EN[0] = 0x0
6242 06:48:22.960802 EX_ROW_EN[1] = 0x0
6243 06:48:22.964223 LP4Y_EN = 0x0
6244 06:48:22.964340 WORK_FSP = 0x0
6245 06:48:22.967337 WL = 0x2
6246 06:48:22.967442 RL = 0x2
6247 06:48:22.970718 BL = 0x2
6248 06:48:22.974137 RPST = 0x0
6249 06:48:22.974220 RD_PRE = 0x0
6250 06:48:22.977631 WR_PRE = 0x1
6251 06:48:22.977744 WR_PST = 0x0
6252 06:48:22.980662 DBI_WR = 0x0
6253 06:48:22.980779 DBI_RD = 0x0
6254 06:48:22.984276 OTF = 0x1
6255 06:48:22.987630 ===================================
6256 06:48:22.990886 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6257 06:48:22.994024 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6258 06:48:22.997571 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6259 06:48:23.000833 ===================================
6260 06:48:23.003740 LPDDR4 DRAM CONFIGURATION
6261 06:48:23.007121 ===================================
6262 06:48:23.010536 EX_ROW_EN[0] = 0x10
6263 06:48:23.010615 EX_ROW_EN[1] = 0x0
6264 06:48:23.013757 LP4Y_EN = 0x0
6265 06:48:23.013832 WORK_FSP = 0x0
6266 06:48:23.017031 WL = 0x2
6267 06:48:23.017129 RL = 0x2
6268 06:48:23.020282 BL = 0x2
6269 06:48:23.020388 RPST = 0x0
6270 06:48:23.023860 RD_PRE = 0x0
6271 06:48:23.027205 WR_PRE = 0x1
6272 06:48:23.027309 WR_PST = 0x0
6273 06:48:23.030476 DBI_WR = 0x0
6274 06:48:23.030556 DBI_RD = 0x0
6275 06:48:23.033758 OTF = 0x1
6276 06:48:23.037041 ===================================
6277 06:48:23.040144 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6278 06:48:23.045877 nWR fixed to 30
6279 06:48:23.049137 [ModeRegInit_LP4] CH0 RK0
6280 06:48:23.049237 [ModeRegInit_LP4] CH0 RK1
6281 06:48:23.052315 [ModeRegInit_LP4] CH1 RK0
6282 06:48:23.055535 [ModeRegInit_LP4] CH1 RK1
6283 06:48:23.055637 match AC timing 19
6284 06:48:23.062207 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6285 06:48:23.065634 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6286 06:48:23.068796 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6287 06:48:23.075330 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6288 06:48:23.078647 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6289 06:48:23.078774 ==
6290 06:48:23.081853 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 06:48:23.085600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 06:48:23.085682 ==
6293 06:48:23.091777 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6294 06:48:23.098665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6295 06:48:23.101818 [CA 0] Center 36 (8~64) winsize 57
6296 06:48:23.105145 [CA 1] Center 36 (8~64) winsize 57
6297 06:48:23.108791 [CA 2] Center 36 (8~64) winsize 57
6298 06:48:23.112093 [CA 3] Center 36 (8~64) winsize 57
6299 06:48:23.112168 [CA 4] Center 36 (8~64) winsize 57
6300 06:48:23.115411 [CA 5] Center 36 (8~64) winsize 57
6301 06:48:23.115482
6302 06:48:23.121948 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6303 06:48:23.122048
6304 06:48:23.125180 [CATrainingPosCal] consider 1 rank data
6305 06:48:23.128677 u2DelayCellTimex100 = 270/100 ps
6306 06:48:23.131668 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 06:48:23.135039 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 06:48:23.138366 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 06:48:23.141743 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 06:48:23.145245 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 06:48:23.148730 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 06:48:23.148814
6313 06:48:23.151590 CA PerBit enable=1, Macro0, CA PI delay=36
6314 06:48:23.151671
6315 06:48:23.154857 [CBTSetCACLKResult] CA Dly = 36
6316 06:48:23.158183 CS Dly: 1 (0~32)
6317 06:48:23.158267 ==
6318 06:48:23.161485 Dram Type= 6, Freq= 0, CH_0, rank 1
6319 06:48:23.165243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 06:48:23.165326 ==
6321 06:48:23.171542 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6322 06:48:23.178233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6323 06:48:23.178318 [CA 0] Center 36 (8~64) winsize 57
6324 06:48:23.181747 [CA 1] Center 36 (8~64) winsize 57
6325 06:48:23.185235 [CA 2] Center 36 (8~64) winsize 57
6326 06:48:23.188488 [CA 3] Center 36 (8~64) winsize 57
6327 06:48:23.191758 [CA 4] Center 36 (8~64) winsize 57
6328 06:48:23.194861 [CA 5] Center 36 (8~64) winsize 57
6329 06:48:23.194960
6330 06:48:23.198260 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6331 06:48:23.198334
6332 06:48:23.201554 [CATrainingPosCal] consider 2 rank data
6333 06:48:23.205091 u2DelayCellTimex100 = 270/100 ps
6334 06:48:23.208230 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 06:48:23.211659 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 06:48:23.218425 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 06:48:23.221430 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 06:48:23.224765 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 06:48:23.228075 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 06:48:23.228153
6341 06:48:23.231629 CA PerBit enable=1, Macro0, CA PI delay=36
6342 06:48:23.231734
6343 06:48:23.234881 [CBTSetCACLKResult] CA Dly = 36
6344 06:48:23.234955 CS Dly: 1 (0~32)
6345 06:48:23.235020
6346 06:48:23.238189 ----->DramcWriteLeveling(PI) begin...
6347 06:48:23.241525 ==
6348 06:48:23.244768 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 06:48:23.248039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 06:48:23.248138 ==
6351 06:48:23.251215 Write leveling (Byte 0): 40 => 8
6352 06:48:23.254624 Write leveling (Byte 1): 40 => 8
6353 06:48:23.257915 DramcWriteLeveling(PI) end<-----
6354 06:48:23.257988
6355 06:48:23.258054 ==
6356 06:48:23.261329 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 06:48:23.264630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 06:48:23.264704 ==
6359 06:48:23.267916 [Gating] SW mode calibration
6360 06:48:23.274443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6361 06:48:23.280981 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6362 06:48:23.284364 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6363 06:48:23.287762 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6364 06:48:23.290999 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6365 06:48:23.297860 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6366 06:48:23.301152 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6367 06:48:23.304521 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6368 06:48:23.311163 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6369 06:48:23.314137 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6370 06:48:23.317788 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6371 06:48:23.320871 Total UI for P1: 0, mck2ui 16
6372 06:48:23.324442 best dqsien dly found for B0: ( 0, 14, 24)
6373 06:48:23.327543 Total UI for P1: 0, mck2ui 16
6374 06:48:23.330778 best dqsien dly found for B1: ( 0, 14, 24)
6375 06:48:23.334278 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6376 06:48:23.340658 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6377 06:48:23.340740
6378 06:48:23.344025 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6379 06:48:23.347361 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6380 06:48:23.350841 [Gating] SW calibration Done
6381 06:48:23.350934 ==
6382 06:48:23.353981 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 06:48:23.357320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 06:48:23.357419 ==
6385 06:48:23.360690 RX Vref Scan: 0
6386 06:48:23.360761
6387 06:48:23.360820 RX Vref 0 -> 0, step: 1
6388 06:48:23.360877
6389 06:48:23.364102 RX Delay -410 -> 252, step: 16
6390 06:48:23.367333 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6391 06:48:23.374049 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6392 06:48:23.377427 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6393 06:48:23.380831 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6394 06:48:23.384041 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6395 06:48:23.390502 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6396 06:48:23.394007 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6397 06:48:23.397060 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6398 06:48:23.400353 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6399 06:48:23.407267 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6400 06:48:23.410444 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6401 06:48:23.413844 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6402 06:48:23.417149 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6403 06:48:23.423861 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6404 06:48:23.427184 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6405 06:48:23.430103 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6406 06:48:23.430198 ==
6407 06:48:23.433405 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 06:48:23.440168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 06:48:23.440264 ==
6410 06:48:23.440330 DQS Delay:
6411 06:48:23.443712 DQS0 = 59, DQS1 = 59
6412 06:48:23.443793 DQM Delay:
6413 06:48:23.443858 DQM0 = 17, DQM1 = 10
6414 06:48:23.447023 DQ Delay:
6415 06:48:23.450286 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6416 06:48:23.453520 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6417 06:48:23.456925 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6418 06:48:23.460321 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6419 06:48:23.460432
6420 06:48:23.460519
6421 06:48:23.460604 ==
6422 06:48:23.463535 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 06:48:23.466832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 06:48:23.466938 ==
6425 06:48:23.467029
6426 06:48:23.467119
6427 06:48:23.470165 TX Vref Scan disable
6428 06:48:23.470240 == TX Byte 0 ==
6429 06:48:23.476675 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6430 06:48:23.480060 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6431 06:48:23.480133 == TX Byte 1 ==
6432 06:48:23.483264 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6433 06:48:23.490008 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6434 06:48:23.490082 ==
6435 06:48:23.493487 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 06:48:23.496746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 06:48:23.496822 ==
6438 06:48:23.496886
6439 06:48:23.496943
6440 06:48:23.499845 TX Vref Scan disable
6441 06:48:23.499922 == TX Byte 0 ==
6442 06:48:23.506758 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6443 06:48:23.510169 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6444 06:48:23.510248 == TX Byte 1 ==
6445 06:48:23.516437 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6446 06:48:23.519984 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6447 06:48:23.520062
6448 06:48:23.520124 [DATLAT]
6449 06:48:23.523076 Freq=400, CH0 RK0
6450 06:48:23.523154
6451 06:48:23.523221 DATLAT Default: 0xf
6452 06:48:23.526432 0, 0xFFFF, sum = 0
6453 06:48:23.526512 1, 0xFFFF, sum = 0
6454 06:48:23.529711 2, 0xFFFF, sum = 0
6455 06:48:23.529796 3, 0xFFFF, sum = 0
6456 06:48:23.533010 4, 0xFFFF, sum = 0
6457 06:48:23.533094 5, 0xFFFF, sum = 0
6458 06:48:23.536262 6, 0xFFFF, sum = 0
6459 06:48:23.536347 7, 0xFFFF, sum = 0
6460 06:48:23.539754 8, 0xFFFF, sum = 0
6461 06:48:23.539838 9, 0xFFFF, sum = 0
6462 06:48:23.542960 10, 0xFFFF, sum = 0
6463 06:48:23.543045 11, 0xFFFF, sum = 0
6464 06:48:23.546474 12, 0xFFFF, sum = 0
6465 06:48:23.546559 13, 0x0, sum = 1
6466 06:48:23.549788 14, 0x0, sum = 2
6467 06:48:23.549872 15, 0x0, sum = 3
6468 06:48:23.553113 16, 0x0, sum = 4
6469 06:48:23.553197 best_step = 14
6470 06:48:23.553263
6471 06:48:23.553325 ==
6472 06:48:23.556392 Dram Type= 6, Freq= 0, CH_0, rank 0
6473 06:48:23.563179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 06:48:23.563264 ==
6475 06:48:23.563330 RX Vref Scan: 1
6476 06:48:23.563392
6477 06:48:23.566299 RX Vref 0 -> 0, step: 1
6478 06:48:23.566382
6479 06:48:23.569785 RX Delay -359 -> 252, step: 8
6480 06:48:23.569868
6481 06:48:23.573134 Set Vref, RX VrefLevel [Byte0]: 63
6482 06:48:23.576154 [Byte1]: 52
6483 06:48:23.576238
6484 06:48:23.579790 Final RX Vref Byte 0 = 63 to rank0
6485 06:48:23.582759 Final RX Vref Byte 1 = 52 to rank0
6486 06:48:23.586337 Final RX Vref Byte 0 = 63 to rank1
6487 06:48:23.589628 Final RX Vref Byte 1 = 52 to rank1==
6488 06:48:23.592881 Dram Type= 6, Freq= 0, CH_0, rank 0
6489 06:48:23.599465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 06:48:23.599549 ==
6491 06:48:23.599616 DQS Delay:
6492 06:48:23.599678 DQS0 = 60, DQS1 = 68
6493 06:48:23.602759 DQM Delay:
6494 06:48:23.602842 DQM0 = 14, DQM1 = 13
6495 06:48:23.606306 DQ Delay:
6496 06:48:23.609731 DQ0 =12, DQ1 =16, DQ2 =16, DQ3 =8
6497 06:48:23.609814 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6498 06:48:23.612712 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6499 06:48:23.615992 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6500 06:48:23.619242
6501 06:48:23.619325
6502 06:48:23.625870 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a87, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6503 06:48:23.629118 CH0 RK0: MR19=C0C, MR18=8A87
6504 06:48:23.635696 CH0_RK0: MR19=0xC0C, MR18=0x8A87, DQSOSC=392, MR23=63, INC=384, DEC=256
6505 06:48:23.635781 ==
6506 06:48:23.639187 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 06:48:23.642319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 06:48:23.642403 ==
6509 06:48:23.645903 [Gating] SW mode calibration
6510 06:48:23.652261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6511 06:48:23.658864 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6512 06:48:23.662513 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6513 06:48:23.665631 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6514 06:48:23.672282 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6515 06:48:23.675675 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6516 06:48:23.678944 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6517 06:48:23.685521 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6518 06:48:23.688921 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6519 06:48:23.692270 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6520 06:48:23.698727 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6521 06:48:23.698812 Total UI for P1: 0, mck2ui 16
6522 06:48:23.702297 best dqsien dly found for B0: ( 0, 14, 24)
6523 06:48:23.705691 Total UI for P1: 0, mck2ui 16
6524 06:48:23.709001 best dqsien dly found for B1: ( 0, 14, 24)
6525 06:48:23.715289 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6526 06:48:23.718643 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6527 06:48:23.718778
6528 06:48:23.722166 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6529 06:48:23.725174 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6530 06:48:23.728564 [Gating] SW calibration Done
6531 06:48:23.728678 ==
6532 06:48:23.731852 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 06:48:23.735205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 06:48:23.735311 ==
6535 06:48:23.738514 RX Vref Scan: 0
6536 06:48:23.738611
6537 06:48:23.738689 RX Vref 0 -> 0, step: 1
6538 06:48:23.738749
6539 06:48:23.742357 RX Delay -410 -> 252, step: 16
6540 06:48:23.748490 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6541 06:48:23.751875 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6542 06:48:23.755050 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6543 06:48:23.758288 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6544 06:48:23.765157 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6545 06:48:23.768197 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6546 06:48:23.771583 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6547 06:48:23.774907 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6548 06:48:23.781304 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6549 06:48:23.784640 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6550 06:48:23.787921 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6551 06:48:23.791637 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6552 06:48:23.798137 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6553 06:48:23.801371 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6554 06:48:23.804763 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6555 06:48:23.808001 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6556 06:48:23.811099 ==
6557 06:48:23.814769 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 06:48:23.818038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 06:48:23.818139 ==
6560 06:48:23.818235 DQS Delay:
6561 06:48:23.821188 DQS0 = 59, DQS1 = 59
6562 06:48:23.821290 DQM Delay:
6563 06:48:23.824469 DQM0 = 16, DQM1 = 10
6564 06:48:23.824570 DQ Delay:
6565 06:48:23.827817 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6566 06:48:23.831116 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6567 06:48:23.834468 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6568 06:48:23.837852 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6569 06:48:23.837930
6570 06:48:23.837992
6571 06:48:23.838051 ==
6572 06:48:23.841213 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 06:48:23.844154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 06:48:23.844229 ==
6575 06:48:23.844291
6576 06:48:23.844349
6577 06:48:23.847459 TX Vref Scan disable
6578 06:48:23.847531 == TX Byte 0 ==
6579 06:48:23.854065 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6580 06:48:23.857726 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6581 06:48:23.857796 == TX Byte 1 ==
6582 06:48:23.864032 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6583 06:48:23.867705 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6584 06:48:23.867775 ==
6585 06:48:23.870857 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 06:48:23.874031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 06:48:23.874109 ==
6588 06:48:23.874170
6589 06:48:23.874227
6590 06:48:23.877281 TX Vref Scan disable
6591 06:48:23.880556 == TX Byte 0 ==
6592 06:48:23.883925 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6593 06:48:23.887604 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6594 06:48:23.887682 == TX Byte 1 ==
6595 06:48:23.894142 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6596 06:48:23.897380 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6597 06:48:23.897487
6598 06:48:23.897551 [DATLAT]
6599 06:48:23.900481 Freq=400, CH0 RK1
6600 06:48:23.900579
6601 06:48:23.900677 DATLAT Default: 0xe
6602 06:48:23.903955 0, 0xFFFF, sum = 0
6603 06:48:23.904059 1, 0xFFFF, sum = 0
6604 06:48:23.907359 2, 0xFFFF, sum = 0
6605 06:48:23.907437 3, 0xFFFF, sum = 0
6606 06:48:23.910665 4, 0xFFFF, sum = 0
6607 06:48:23.913778 5, 0xFFFF, sum = 0
6608 06:48:23.913851 6, 0xFFFF, sum = 0
6609 06:48:23.917325 7, 0xFFFF, sum = 0
6610 06:48:23.917431 8, 0xFFFF, sum = 0
6611 06:48:23.920339 9, 0xFFFF, sum = 0
6612 06:48:23.920425 10, 0xFFFF, sum = 0
6613 06:48:23.923945 11, 0xFFFF, sum = 0
6614 06:48:23.924033 12, 0xFFFF, sum = 0
6615 06:48:23.927268 13, 0x0, sum = 1
6616 06:48:23.927353 14, 0x0, sum = 2
6617 06:48:23.930687 15, 0x0, sum = 3
6618 06:48:23.930772 16, 0x0, sum = 4
6619 06:48:23.930840 best_step = 14
6620 06:48:23.933762
6621 06:48:23.933846 ==
6622 06:48:23.936947 Dram Type= 6, Freq= 0, CH_0, rank 1
6623 06:48:23.940554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 06:48:23.940663 ==
6625 06:48:23.940759 RX Vref Scan: 0
6626 06:48:23.940853
6627 06:48:23.943792 RX Vref 0 -> 0, step: 1
6628 06:48:23.943888
6629 06:48:23.947031 RX Delay -359 -> 252, step: 8
6630 06:48:23.954470 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6631 06:48:23.957732 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6632 06:48:23.961031 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6633 06:48:23.964284 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6634 06:48:23.970833 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6635 06:48:23.974282 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6636 06:48:23.977847 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6637 06:48:23.980987 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6638 06:48:23.987373 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6639 06:48:23.990702 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488
6640 06:48:23.993978 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6641 06:48:24.000463 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6642 06:48:24.003764 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6643 06:48:24.007266 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6644 06:48:24.010534 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6645 06:48:24.017113 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6646 06:48:24.017222 ==
6647 06:48:24.020755 Dram Type= 6, Freq= 0, CH_0, rank 1
6648 06:48:24.023929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 06:48:24.024015 ==
6650 06:48:24.024083 DQS Delay:
6651 06:48:24.027457 DQS0 = 60, DQS1 = 68
6652 06:48:24.027536 DQM Delay:
6653 06:48:24.030681 DQM0 = 11, DQM1 = 13
6654 06:48:24.030753 DQ Delay:
6655 06:48:24.033953 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6656 06:48:24.037181 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6657 06:48:24.040420 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6658 06:48:24.043998 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6659 06:48:24.044105
6660 06:48:24.044199
6661 06:48:24.050625 [DQSOSCAuto] RK1, (LSB)MR18= 0xcc82, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6662 06:48:24.053702 CH0 RK1: MR19=C0C, MR18=CC82
6663 06:48:24.060497 CH0_RK1: MR19=0xC0C, MR18=0xCC82, DQSOSC=384, MR23=63, INC=400, DEC=267
6664 06:48:24.063895 [RxdqsGatingPostProcess] freq 400
6665 06:48:24.070167 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6666 06:48:24.073454 best DQS0 dly(2T, 0.5T) = (0, 10)
6667 06:48:24.073540 best DQS1 dly(2T, 0.5T) = (0, 10)
6668 06:48:24.076793 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6669 06:48:24.079960 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6670 06:48:24.083335 best DQS0 dly(2T, 0.5T) = (0, 10)
6671 06:48:24.086928 best DQS1 dly(2T, 0.5T) = (0, 10)
6672 06:48:24.090210 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6673 06:48:24.093465 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6674 06:48:24.096658 Pre-setting of DQS Precalculation
6675 06:48:24.103275 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6676 06:48:24.103381 ==
6677 06:48:24.106520 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 06:48:24.109823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 06:48:24.109905 ==
6680 06:48:24.116680 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6681 06:48:24.119899 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6682 06:48:24.123156 [CA 0] Center 36 (8~64) winsize 57
6683 06:48:24.126398 [CA 1] Center 36 (8~64) winsize 57
6684 06:48:24.129732 [CA 2] Center 36 (8~64) winsize 57
6685 06:48:24.133296 [CA 3] Center 36 (8~64) winsize 57
6686 06:48:24.136560 [CA 4] Center 36 (8~64) winsize 57
6687 06:48:24.139893 [CA 5] Center 36 (8~64) winsize 57
6688 06:48:24.139969
6689 06:48:24.143233 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6690 06:48:24.143308
6691 06:48:24.146405 [CATrainingPosCal] consider 1 rank data
6692 06:48:24.149704 u2DelayCellTimex100 = 270/100 ps
6693 06:48:24.152948 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 06:48:24.156500 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 06:48:24.159679 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 06:48:24.166420 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 06:48:24.169703 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 06:48:24.173171 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 06:48:24.173277
6700 06:48:24.176491 CA PerBit enable=1, Macro0, CA PI delay=36
6701 06:48:24.176567
6702 06:48:24.179454 [CBTSetCACLKResult] CA Dly = 36
6703 06:48:24.179533 CS Dly: 1 (0~32)
6704 06:48:24.179596 ==
6705 06:48:24.182750 Dram Type= 6, Freq= 0, CH_1, rank 1
6706 06:48:24.189736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 06:48:24.189813 ==
6708 06:48:24.192974 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6709 06:48:24.199476 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6710 06:48:24.202870 [CA 0] Center 36 (8~64) winsize 57
6711 06:48:24.206114 [CA 1] Center 36 (8~64) winsize 57
6712 06:48:24.209523 [CA 2] Center 36 (8~64) winsize 57
6713 06:48:24.213077 [CA 3] Center 36 (8~64) winsize 57
6714 06:48:24.216073 [CA 4] Center 36 (8~64) winsize 57
6715 06:48:24.219589 [CA 5] Center 36 (8~64) winsize 57
6716 06:48:24.219662
6717 06:48:24.222736 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6718 06:48:24.222816
6719 06:48:24.225946 [CATrainingPosCal] consider 2 rank data
6720 06:48:24.229423 u2DelayCellTimex100 = 270/100 ps
6721 06:48:24.232760 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 06:48:24.236072 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 06:48:24.239361 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 06:48:24.242626 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 06:48:24.245865 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 06:48:24.252700 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 06:48:24.252777
6728 06:48:24.256173 CA PerBit enable=1, Macro0, CA PI delay=36
6729 06:48:24.256274
6730 06:48:24.259385 [CBTSetCACLKResult] CA Dly = 36
6731 06:48:24.259459 CS Dly: 1 (0~32)
6732 06:48:24.259521
6733 06:48:24.262719 ----->DramcWriteLeveling(PI) begin...
6734 06:48:24.262800 ==
6735 06:48:24.265710 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 06:48:24.269057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 06:48:24.272676 ==
6738 06:48:24.272753 Write leveling (Byte 0): 40 => 8
6739 06:48:24.275671 Write leveling (Byte 1): 40 => 8
6740 06:48:24.278973 DramcWriteLeveling(PI) end<-----
6741 06:48:24.279046
6742 06:48:24.279106 ==
6743 06:48:24.282429 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 06:48:24.289097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 06:48:24.289207 ==
6746 06:48:24.289307 [Gating] SW mode calibration
6747 06:48:24.298988 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6748 06:48:24.302223 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6749 06:48:24.308741 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6750 06:48:24.311982 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6751 06:48:24.315421 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6752 06:48:24.322052 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6753 06:48:24.325459 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6754 06:48:24.328895 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6755 06:48:24.331913 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6756 06:48:24.338719 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6757 06:48:24.341891 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6758 06:48:24.345103 Total UI for P1: 0, mck2ui 16
6759 06:48:24.348431 best dqsien dly found for B0: ( 0, 14, 24)
6760 06:48:24.351787 Total UI for P1: 0, mck2ui 16
6761 06:48:24.355000 best dqsien dly found for B1: ( 0, 14, 24)
6762 06:48:24.358545 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6763 06:48:24.361806 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6764 06:48:24.361885
6765 06:48:24.365144 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6766 06:48:24.371704 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6767 06:48:24.371782 [Gating] SW calibration Done
6768 06:48:24.371851 ==
6769 06:48:24.374930 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 06:48:24.381775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 06:48:24.381855 ==
6772 06:48:24.381923 RX Vref Scan: 0
6773 06:48:24.381986
6774 06:48:24.385070 RX Vref 0 -> 0, step: 1
6775 06:48:24.385166
6776 06:48:24.388341 RX Delay -410 -> 252, step: 16
6777 06:48:24.391821 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6778 06:48:24.394845 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6779 06:48:24.401525 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6780 06:48:24.404952 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6781 06:48:24.408094 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6782 06:48:24.411432 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6783 06:48:24.418226 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6784 06:48:24.421470 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6785 06:48:24.424757 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6786 06:48:24.428100 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6787 06:48:24.434798 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6788 06:48:24.437783 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6789 06:48:24.441346 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6790 06:48:24.447967 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6791 06:48:24.451269 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6792 06:48:24.454398 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6793 06:48:24.454520 ==
6794 06:48:24.457701 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 06:48:24.460996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 06:48:24.461113 ==
6797 06:48:24.464645 DQS Delay:
6798 06:48:24.464745 DQS0 = 51, DQS1 = 67
6799 06:48:24.467652 DQM Delay:
6800 06:48:24.467771 DQM0 = 13, DQM1 = 17
6801 06:48:24.471005 DQ Delay:
6802 06:48:24.471117 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6803 06:48:24.474332 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6804 06:48:24.477629 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6805 06:48:24.480915 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6806 06:48:24.481016
6807 06:48:24.481114
6808 06:48:24.481201 ==
6809 06:48:24.484229 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 06:48:24.490763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 06:48:24.490873 ==
6812 06:48:24.490943
6813 06:48:24.491003
6814 06:48:24.491060 TX Vref Scan disable
6815 06:48:24.494424 == TX Byte 0 ==
6816 06:48:24.497682 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6817 06:48:24.500609 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6818 06:48:24.504256 == TX Byte 1 ==
6819 06:48:24.507319 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6820 06:48:24.510855 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6821 06:48:24.514225 ==
6822 06:48:24.517345 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 06:48:24.520686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 06:48:24.520761 ==
6825 06:48:24.520824
6826 06:48:24.520894
6827 06:48:24.524231 TX Vref Scan disable
6828 06:48:24.524311 == TX Byte 0 ==
6829 06:48:24.527282 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6830 06:48:24.533796 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6831 06:48:24.533876 == TX Byte 1 ==
6832 06:48:24.537093 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6833 06:48:24.544004 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6834 06:48:24.544084
6835 06:48:24.544152 [DATLAT]
6836 06:48:24.544213 Freq=400, CH1 RK0
6837 06:48:24.544272
6838 06:48:24.547273 DATLAT Default: 0xf
6839 06:48:24.547343 0, 0xFFFF, sum = 0
6840 06:48:24.550252 1, 0xFFFF, sum = 0
6841 06:48:24.553902 2, 0xFFFF, sum = 0
6842 06:48:24.553982 3, 0xFFFF, sum = 0
6843 06:48:24.557006 4, 0xFFFF, sum = 0
6844 06:48:24.557088 5, 0xFFFF, sum = 0
6845 06:48:24.560467 6, 0xFFFF, sum = 0
6846 06:48:24.560539 7, 0xFFFF, sum = 0
6847 06:48:24.563637 8, 0xFFFF, sum = 0
6848 06:48:24.563723 9, 0xFFFF, sum = 0
6849 06:48:24.567078 10, 0xFFFF, sum = 0
6850 06:48:24.567161 11, 0xFFFF, sum = 0
6851 06:48:24.570369 12, 0xFFFF, sum = 0
6852 06:48:24.570452 13, 0x0, sum = 1
6853 06:48:24.573594 14, 0x0, sum = 2
6854 06:48:24.573670 15, 0x0, sum = 3
6855 06:48:24.576834 16, 0x0, sum = 4
6856 06:48:24.576910 best_step = 14
6857 06:48:24.576975
6858 06:48:24.577033 ==
6859 06:48:24.579991 Dram Type= 6, Freq= 0, CH_1, rank 0
6860 06:48:24.583384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 06:48:24.586882 ==
6862 06:48:24.586964 RX Vref Scan: 1
6863 06:48:24.587027
6864 06:48:24.590135 RX Vref 0 -> 0, step: 1
6865 06:48:24.590238
6866 06:48:24.593445 RX Delay -375 -> 252, step: 8
6867 06:48:24.593533
6868 06:48:24.596822 Set Vref, RX VrefLevel [Byte0]: 54
6869 06:48:24.599765 [Byte1]: 52
6870 06:48:24.599876
6871 06:48:24.603363 Final RX Vref Byte 0 = 54 to rank0
6872 06:48:24.606217 Final RX Vref Byte 1 = 52 to rank0
6873 06:48:24.609538 Final RX Vref Byte 0 = 54 to rank1
6874 06:48:24.613136 Final RX Vref Byte 1 = 52 to rank1==
6875 06:48:24.616344 Dram Type= 6, Freq= 0, CH_1, rank 0
6876 06:48:24.619718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 06:48:24.622803 ==
6878 06:48:24.622885 DQS Delay:
6879 06:48:24.622964 DQS0 = 52, DQS1 = 64
6880 06:48:24.626229 DQM Delay:
6881 06:48:24.626310 DQM0 = 9, DQM1 = 10
6882 06:48:24.629412 DQ Delay:
6883 06:48:24.629517 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6884 06:48:24.633022 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6885 06:48:24.636077 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6886 06:48:24.639605 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6887 06:48:24.639702
6888 06:48:24.639809
6889 06:48:24.649491 [DQSOSCAuto] RK0, (LSB)MR18= 0x576a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6890 06:48:24.652818 CH1 RK0: MR19=C0C, MR18=576A
6891 06:48:24.659395 CH1_RK0: MR19=0xC0C, MR18=0x576A, DQSOSC=396, MR23=63, INC=376, DEC=251
6892 06:48:24.659479 ==
6893 06:48:24.662801 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 06:48:24.666124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 06:48:24.666208 ==
6896 06:48:24.669438 [Gating] SW mode calibration
6897 06:48:24.675876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6898 06:48:24.679277 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6899 06:48:24.685998 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6900 06:48:24.689043 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6901 06:48:24.692730 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6902 06:48:24.699366 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6903 06:48:24.702741 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6904 06:48:24.706102 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6905 06:48:24.712682 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6906 06:48:24.715925 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6907 06:48:24.719149 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6908 06:48:24.722538 Total UI for P1: 0, mck2ui 16
6909 06:48:24.725749 best dqsien dly found for B0: ( 0, 14, 24)
6910 06:48:24.729020 Total UI for P1: 0, mck2ui 16
6911 06:48:24.732622 best dqsien dly found for B1: ( 0, 14, 24)
6912 06:48:24.735866 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6913 06:48:24.739125 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6914 06:48:24.739228
6915 06:48:24.745880 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6916 06:48:24.749145 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6917 06:48:24.749224 [Gating] SW calibration Done
6918 06:48:24.752389 ==
6919 06:48:24.755754 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 06:48:24.759185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 06:48:24.759264 ==
6922 06:48:24.759352 RX Vref Scan: 0
6923 06:48:24.759413
6924 06:48:24.762569 RX Vref 0 -> 0, step: 1
6925 06:48:24.762645
6926 06:48:24.765803 RX Delay -410 -> 252, step: 16
6927 06:48:24.769088 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6928 06:48:24.775899 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6929 06:48:24.779130 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6930 06:48:24.782492 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6931 06:48:24.785969 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6932 06:48:24.789175 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6933 06:48:24.795490 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6934 06:48:24.798841 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6935 06:48:24.802172 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6936 06:48:24.805498 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6937 06:48:24.812252 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6938 06:48:24.815726 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6939 06:48:24.818825 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6940 06:48:24.825743 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6941 06:48:24.828998 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6942 06:48:24.832274 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6943 06:48:24.832356 ==
6944 06:48:24.835556 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 06:48:24.838716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 06:48:24.838787 ==
6947 06:48:24.842162 DQS Delay:
6948 06:48:24.842231 DQS0 = 59, DQS1 = 59
6949 06:48:24.845325 DQM Delay:
6950 06:48:24.845398 DQM0 = 19, DQM1 = 13
6951 06:48:24.848670 DQ Delay:
6952 06:48:24.848737 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6953 06:48:24.851963 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6954 06:48:24.855680 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6955 06:48:24.858843 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6956 06:48:24.858932
6957 06:48:24.859023
6958 06:48:24.862130 ==
6959 06:48:24.862199 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 06:48:24.868723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 06:48:24.868828 ==
6962 06:48:24.868918
6963 06:48:24.869007
6964 06:48:24.871769 TX Vref Scan disable
6965 06:48:24.871837 == TX Byte 0 ==
6966 06:48:24.875373 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6967 06:48:24.882005 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6968 06:48:24.882101 == TX Byte 1 ==
6969 06:48:24.885310 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6970 06:48:24.888546 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6971 06:48:24.891894 ==
6972 06:48:24.895130 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 06:48:24.898810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 06:48:24.898882 ==
6975 06:48:24.898943
6976 06:48:24.898999
6977 06:48:24.902132 TX Vref Scan disable
6978 06:48:24.902196 == TX Byte 0 ==
6979 06:48:24.905347 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6980 06:48:24.912121 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6981 06:48:24.912190 == TX Byte 1 ==
6982 06:48:24.915255 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6983 06:48:24.918439 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6984 06:48:24.921804
6985 06:48:24.921875 [DATLAT]
6986 06:48:24.921935 Freq=400, CH1 RK1
6987 06:48:24.921993
6988 06:48:24.924984 DATLAT Default: 0xe
6989 06:48:24.925059 0, 0xFFFF, sum = 0
6990 06:48:24.928562 1, 0xFFFF, sum = 0
6991 06:48:24.928665 2, 0xFFFF, sum = 0
6992 06:48:24.931896 3, 0xFFFF, sum = 0
6993 06:48:24.931964 4, 0xFFFF, sum = 0
6994 06:48:24.935181 5, 0xFFFF, sum = 0
6995 06:48:24.938716 6, 0xFFFF, sum = 0
6996 06:48:24.938784 7, 0xFFFF, sum = 0
6997 06:48:24.941697 8, 0xFFFF, sum = 0
6998 06:48:24.941794 9, 0xFFFF, sum = 0
6999 06:48:24.944935 10, 0xFFFF, sum = 0
7000 06:48:24.945003 11, 0xFFFF, sum = 0
7001 06:48:24.948503 12, 0xFFFF, sum = 0
7002 06:48:24.948571 13, 0x0, sum = 1
7003 06:48:24.952186 14, 0x0, sum = 2
7004 06:48:24.952298 15, 0x0, sum = 3
7005 06:48:24.954900 16, 0x0, sum = 4
7006 06:48:24.954974 best_step = 14
7007 06:48:24.955034
7008 06:48:24.955090 ==
7009 06:48:24.958097 Dram Type= 6, Freq= 0, CH_1, rank 1
7010 06:48:24.961394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7011 06:48:24.961534 ==
7012 06:48:24.964772 RX Vref Scan: 0
7013 06:48:24.964853
7014 06:48:24.968346 RX Vref 0 -> 0, step: 1
7015 06:48:24.968426
7016 06:48:24.968490 RX Delay -359 -> 252, step: 8
7017 06:48:24.977010 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7018 06:48:24.980412 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7019 06:48:24.983803 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7020 06:48:24.987141 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7021 06:48:24.993744 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7022 06:48:24.996953 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7023 06:48:25.000641 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7024 06:48:25.003871 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7025 06:48:25.010197 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7026 06:48:25.013926 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7027 06:48:25.016853 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7028 06:48:25.023676 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7029 06:48:25.026752 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7030 06:48:25.030180 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7031 06:48:25.033683 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7032 06:48:25.040306 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7033 06:48:25.040387 ==
7034 06:48:25.043645 Dram Type= 6, Freq= 0, CH_1, rank 1
7035 06:48:25.046825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7036 06:48:25.046907 ==
7037 06:48:25.046971 DQS Delay:
7038 06:48:25.050124 DQS0 = 60, DQS1 = 64
7039 06:48:25.050206 DQM Delay:
7040 06:48:25.053419 DQM0 = 12, DQM1 = 10
7041 06:48:25.053524 DQ Delay:
7042 06:48:25.056932 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7043 06:48:25.060208 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7044 06:48:25.063397 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7045 06:48:25.066649 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7046 06:48:25.066740
7047 06:48:25.066804
7048 06:48:25.073448 [DQSOSCAuto] RK1, (LSB)MR18= 0x7fb0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
7049 06:48:25.076701 CH1 RK1: MR19=C0C, MR18=7FB0
7050 06:48:25.083443 CH1_RK1: MR19=0xC0C, MR18=0x7FB0, DQSOSC=387, MR23=63, INC=394, DEC=262
7051 06:48:25.086595 [RxdqsGatingPostProcess] freq 400
7052 06:48:25.093390 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7053 06:48:25.093471 best DQS0 dly(2T, 0.5T) = (0, 10)
7054 06:48:25.096834 best DQS1 dly(2T, 0.5T) = (0, 10)
7055 06:48:25.099898 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7056 06:48:25.103499 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7057 06:48:25.106550 best DQS0 dly(2T, 0.5T) = (0, 10)
7058 06:48:25.109932 best DQS1 dly(2T, 0.5T) = (0, 10)
7059 06:48:25.113248 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7060 06:48:25.116499 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7061 06:48:25.119813 Pre-setting of DQS Precalculation
7062 06:48:25.126774 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7063 06:48:25.133403 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7064 06:48:25.139969 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7065 06:48:25.140052
7066 06:48:25.140115
7067 06:48:25.143106 [Calibration Summary] 800 Mbps
7068 06:48:25.143186 CH 0, Rank 0
7069 06:48:25.146380 SW Impedance : PASS
7070 06:48:25.146461 DUTY Scan : NO K
7071 06:48:25.149952 ZQ Calibration : PASS
7072 06:48:25.153125 Jitter Meter : NO K
7073 06:48:25.153206 CBT Training : PASS
7074 06:48:25.156458 Write leveling : PASS
7075 06:48:25.159820 RX DQS gating : PASS
7076 06:48:25.159911 RX DQ/DQS(RDDQC) : PASS
7077 06:48:25.163141 TX DQ/DQS : PASS
7078 06:48:25.166420 RX DATLAT : PASS
7079 06:48:25.166500 RX DQ/DQS(Engine): PASS
7080 06:48:25.169722 TX OE : NO K
7081 06:48:25.169802 All Pass.
7082 06:48:25.169878
7083 06:48:25.172908 CH 0, Rank 1
7084 06:48:25.172989 SW Impedance : PASS
7085 06:48:25.176062 DUTY Scan : NO K
7086 06:48:25.179735 ZQ Calibration : PASS
7087 06:48:25.179841 Jitter Meter : NO K
7088 06:48:25.182722 CBT Training : PASS
7089 06:48:25.186367 Write leveling : NO K
7090 06:48:25.186448 RX DQS gating : PASS
7091 06:48:25.189422 RX DQ/DQS(RDDQC) : PASS
7092 06:48:25.192945 TX DQ/DQS : PASS
7093 06:48:25.193026 RX DATLAT : PASS
7094 06:48:25.196116 RX DQ/DQS(Engine): PASS
7095 06:48:25.199578 TX OE : NO K
7096 06:48:25.199658 All Pass.
7097 06:48:25.199722
7098 06:48:25.199794 CH 1, Rank 0
7099 06:48:25.203052 SW Impedance : PASS
7100 06:48:25.203132 DUTY Scan : NO K
7101 06:48:25.206243 ZQ Calibration : PASS
7102 06:48:25.209550 Jitter Meter : NO K
7103 06:48:25.209631 CBT Training : PASS
7104 06:48:25.212969 Write leveling : PASS
7105 06:48:25.216179 RX DQS gating : PASS
7106 06:48:25.216259 RX DQ/DQS(RDDQC) : PASS
7107 06:48:25.219440 TX DQ/DQS : PASS
7108 06:48:25.222832 RX DATLAT : PASS
7109 06:48:25.222920 RX DQ/DQS(Engine): PASS
7110 06:48:25.225917 TX OE : NO K
7111 06:48:25.225999 All Pass.
7112 06:48:25.226063
7113 06:48:25.229344 CH 1, Rank 1
7114 06:48:25.229440 SW Impedance : PASS
7115 06:48:25.232598 DUTY Scan : NO K
7116 06:48:25.236074 ZQ Calibration : PASS
7117 06:48:25.236149 Jitter Meter : NO K
7118 06:48:25.239235 CBT Training : PASS
7119 06:48:25.242806 Write leveling : NO K
7120 06:48:25.242906 RX DQS gating : PASS
7121 06:48:25.245911 RX DQ/DQS(RDDQC) : PASS
7122 06:48:25.249173 TX DQ/DQS : PASS
7123 06:48:25.249274 RX DATLAT : PASS
7124 06:48:25.252436 RX DQ/DQS(Engine): PASS
7125 06:48:25.256091 TX OE : NO K
7126 06:48:25.256197 All Pass.
7127 06:48:25.256287
7128 06:48:25.256381 DramC Write-DBI off
7129 06:48:25.259292 PER_BANK_REFRESH: Hybrid Mode
7130 06:48:25.262561 TX_TRACKING: ON
7131 06:48:25.269252 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7132 06:48:25.272230 [FAST_K] Save calibration result to emmc
7133 06:48:25.278822 dramc_set_vcore_voltage set vcore to 725000
7134 06:48:25.278893 Read voltage for 1600, 0
7135 06:48:25.282489 Vio18 = 0
7136 06:48:25.282585 Vcore = 725000
7137 06:48:25.282673 Vdram = 0
7138 06:48:25.285759 Vddq = 0
7139 06:48:25.285846 Vmddr = 0
7140 06:48:25.288882 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7141 06:48:25.295554 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7142 06:48:25.298780 MEM_TYPE=3, freq_sel=13
7143 06:48:25.302256 sv_algorithm_assistance_LP4_3733
7144 06:48:25.305334 ============ PULL DRAM RESETB DOWN ============
7145 06:48:25.308717 ========== PULL DRAM RESETB DOWN end =========
7146 06:48:25.312149 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7147 06:48:25.315280 ===================================
7148 06:48:25.318569 LPDDR4 DRAM CONFIGURATION
7149 06:48:25.322008 ===================================
7150 06:48:25.325209 EX_ROW_EN[0] = 0x0
7151 06:48:25.325317 EX_ROW_EN[1] = 0x0
7152 06:48:25.328481 LP4Y_EN = 0x0
7153 06:48:25.328583 WORK_FSP = 0x1
7154 06:48:25.331930 WL = 0x5
7155 06:48:25.332006 RL = 0x5
7156 06:48:25.335187 BL = 0x2
7157 06:48:25.335266 RPST = 0x0
7158 06:48:25.338338 RD_PRE = 0x0
7159 06:48:25.341636 WR_PRE = 0x1
7160 06:48:25.341711 WR_PST = 0x1
7161 06:48:25.345232 DBI_WR = 0x0
7162 06:48:25.345334 DBI_RD = 0x0
7163 06:48:25.348325 OTF = 0x1
7164 06:48:25.351702 ===================================
7165 06:48:25.354947 ===================================
7166 06:48:25.355032 ANA top config
7167 06:48:25.358472 ===================================
7168 06:48:25.361393 DLL_ASYNC_EN = 0
7169 06:48:25.364770 ALL_SLAVE_EN = 0
7170 06:48:25.364847 NEW_RANK_MODE = 1
7171 06:48:25.368420 DLL_IDLE_MODE = 1
7172 06:48:25.371780 LP45_APHY_COMB_EN = 1
7173 06:48:25.374897 TX_ODT_DIS = 0
7174 06:48:25.374966 NEW_8X_MODE = 1
7175 06:48:25.378295 ===================================
7176 06:48:25.381583 ===================================
7177 06:48:25.384823 data_rate = 3200
7178 06:48:25.388001 CKR = 1
7179 06:48:25.391649 DQ_P2S_RATIO = 8
7180 06:48:25.394780 ===================================
7181 06:48:25.398344 CA_P2S_RATIO = 8
7182 06:48:25.401756 DQ_CA_OPEN = 0
7183 06:48:25.401823 DQ_SEMI_OPEN = 0
7184 06:48:25.405072 CA_SEMI_OPEN = 0
7185 06:48:25.408310 CA_FULL_RATE = 0
7186 06:48:25.411550 DQ_CKDIV4_EN = 0
7187 06:48:25.414932 CA_CKDIV4_EN = 0
7188 06:48:25.418083 CA_PREDIV_EN = 0
7189 06:48:25.418155 PH8_DLY = 12
7190 06:48:25.421589 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7191 06:48:25.424898 DQ_AAMCK_DIV = 4
7192 06:48:25.428376 CA_AAMCK_DIV = 4
7193 06:48:25.431513 CA_ADMCK_DIV = 4
7194 06:48:25.434858 DQ_TRACK_CA_EN = 0
7195 06:48:25.434930 CA_PICK = 1600
7196 06:48:25.438047 CA_MCKIO = 1600
7197 06:48:25.441240 MCKIO_SEMI = 0
7198 06:48:25.444686 PLL_FREQ = 3068
7199 06:48:25.447956 DQ_UI_PI_RATIO = 32
7200 06:48:25.451341 CA_UI_PI_RATIO = 0
7201 06:48:25.454737 ===================================
7202 06:48:25.457919 ===================================
7203 06:48:25.461370 memory_type:LPDDR4
7204 06:48:25.461469 GP_NUM : 10
7205 06:48:25.464641 SRAM_EN : 1
7206 06:48:25.464745 MD32_EN : 0
7207 06:48:25.467974 ===================================
7208 06:48:25.471172 [ANA_INIT] >>>>>>>>>>>>>>
7209 06:48:25.474450 <<<<<< [CONFIGURE PHASE]: ANA_TX
7210 06:48:25.477754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7211 06:48:25.481059 ===================================
7212 06:48:25.484347 data_rate = 3200,PCW = 0X7600
7213 06:48:25.487792 ===================================
7214 06:48:25.491069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7215 06:48:25.497576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7216 06:48:25.500755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7217 06:48:25.507393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7218 06:48:25.510783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7219 06:48:25.514139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7220 06:48:25.514211 [ANA_INIT] flow start
7221 06:48:25.517354 [ANA_INIT] PLL >>>>>>>>
7222 06:48:25.520698 [ANA_INIT] PLL <<<<<<<<
7223 06:48:25.520768 [ANA_INIT] MIDPI >>>>>>>>
7224 06:48:25.523989 [ANA_INIT] MIDPI <<<<<<<<
7225 06:48:25.527217 [ANA_INIT] DLL >>>>>>>>
7226 06:48:25.527290 [ANA_INIT] DLL <<<<<<<<
7227 06:48:25.530689 [ANA_INIT] flow end
7228 06:48:25.533719 ============ LP4 DIFF to SE enter ============
7229 06:48:25.540644 ============ LP4 DIFF to SE exit ============
7230 06:48:25.540744 [ANA_INIT] <<<<<<<<<<<<<
7231 06:48:25.543613 [Flow] Enable top DCM control >>>>>
7232 06:48:25.547302 [Flow] Enable top DCM control <<<<<
7233 06:48:25.550548 Enable DLL master slave shuffle
7234 06:48:25.557039 ==============================================================
7235 06:48:25.557147 Gating Mode config
7236 06:48:25.563677 ==============================================================
7237 06:48:25.567060 Config description:
7238 06:48:25.573868 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7239 06:48:25.580338 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7240 06:48:25.587003 SELPH_MODE 0: By rank 1: By Phase
7241 06:48:25.593716 ==============================================================
7242 06:48:25.596971 GAT_TRACK_EN = 1
7243 06:48:25.597055 RX_GATING_MODE = 2
7244 06:48:25.600198 RX_GATING_TRACK_MODE = 2
7245 06:48:25.603460 SELPH_MODE = 1
7246 06:48:25.606760 PICG_EARLY_EN = 1
7247 06:48:25.609975 VALID_LAT_VALUE = 1
7248 06:48:25.616673 ==============================================================
7249 06:48:25.619912 Enter into Gating configuration >>>>
7250 06:48:25.623287 Exit from Gating configuration <<<<
7251 06:48:25.626579 Enter into DVFS_PRE_config >>>>>
7252 06:48:25.636472 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7253 06:48:25.639941 Exit from DVFS_PRE_config <<<<<
7254 06:48:25.643041 Enter into PICG configuration >>>>
7255 06:48:25.646559 Exit from PICG configuration <<<<
7256 06:48:25.649815 [RX_INPUT] configuration >>>>>
7257 06:48:25.653158 [RX_INPUT] configuration <<<<<
7258 06:48:25.656463 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7259 06:48:25.662902 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7260 06:48:25.669434 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7261 06:48:25.676121 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7262 06:48:25.679452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7263 06:48:25.686232 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7264 06:48:25.689712 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7265 06:48:25.696373 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7266 06:48:25.699533 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7267 06:48:25.702887 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7268 06:48:25.706009 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7269 06:48:25.712619 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7270 06:48:25.715935 ===================================
7271 06:48:25.716018 LPDDR4 DRAM CONFIGURATION
7272 06:48:25.719488 ===================================
7273 06:48:25.722832 EX_ROW_EN[0] = 0x0
7274 06:48:25.725999 EX_ROW_EN[1] = 0x0
7275 06:48:25.726080 LP4Y_EN = 0x0
7276 06:48:25.729339 WORK_FSP = 0x1
7277 06:48:25.729451 WL = 0x5
7278 06:48:25.732701 RL = 0x5
7279 06:48:25.732782 BL = 0x2
7280 06:48:25.735904 RPST = 0x0
7281 06:48:25.735984 RD_PRE = 0x0
7282 06:48:25.739552 WR_PRE = 0x1
7283 06:48:25.739633 WR_PST = 0x1
7284 06:48:25.742750 DBI_WR = 0x0
7285 06:48:25.742831 DBI_RD = 0x0
7286 06:48:25.746155 OTF = 0x1
7287 06:48:25.749353 ===================================
7288 06:48:25.752772 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7289 06:48:25.755884 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7290 06:48:25.762645 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7291 06:48:25.765779 ===================================
7292 06:48:25.765861 LPDDR4 DRAM CONFIGURATION
7293 06:48:25.769590 ===================================
7294 06:48:25.772864 EX_ROW_EN[0] = 0x10
7295 06:48:25.776163 EX_ROW_EN[1] = 0x0
7296 06:48:25.776244 LP4Y_EN = 0x0
7297 06:48:25.779184 WORK_FSP = 0x1
7298 06:48:25.779265 WL = 0x5
7299 06:48:25.782459 RL = 0x5
7300 06:48:25.782540 BL = 0x2
7301 06:48:25.786124 RPST = 0x0
7302 06:48:25.786205 RD_PRE = 0x0
7303 06:48:25.789094 WR_PRE = 0x1
7304 06:48:25.789175 WR_PST = 0x1
7305 06:48:25.792360 DBI_WR = 0x0
7306 06:48:25.792440 DBI_RD = 0x0
7307 06:48:25.795943 OTF = 0x1
7308 06:48:25.799141 ===================================
7309 06:48:25.805758 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7310 06:48:25.805840 ==
7311 06:48:25.809176 Dram Type= 6, Freq= 0, CH_0, rank 0
7312 06:48:25.812452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7313 06:48:25.812536 ==
7314 06:48:25.815887 [Duty_Offset_Calibration]
7315 06:48:25.815968 B0:2 B1:0 CA:3
7316 06:48:25.816032
7317 06:48:25.819376 [DutyScan_Calibration_Flow] k_type=0
7318 06:48:25.829515
7319 06:48:25.829598 ==CLK 0==
7320 06:48:25.832914 Final CLK duty delay cell = 0
7321 06:48:25.836009 [0] MAX Duty = 5031%(X100), DQS PI = 12
7322 06:48:25.839297 [0] MIN Duty = 4875%(X100), DQS PI = 52
7323 06:48:25.842542 [0] AVG Duty = 4953%(X100)
7324 06:48:25.842623
7325 06:48:25.845780 CH0 CLK Duty spec in!! Max-Min= 156%
7326 06:48:25.849270 [DutyScan_Calibration_Flow] ====Done====
7327 06:48:25.849352
7328 06:48:25.852569 [DutyScan_Calibration_Flow] k_type=1
7329 06:48:25.869496
7330 06:48:25.869592 ==DQS 0 ==
7331 06:48:25.872847 Final DQS duty delay cell = 0
7332 06:48:25.876137 [0] MAX Duty = 5125%(X100), DQS PI = 30
7333 06:48:25.879423 [0] MIN Duty = 4875%(X100), DQS PI = 48
7334 06:48:25.879504 [0] AVG Duty = 5000%(X100)
7335 06:48:25.882625
7336 06:48:25.882706 ==DQS 1 ==
7337 06:48:25.886162 Final DQS duty delay cell = 0
7338 06:48:25.889405 [0] MAX Duty = 5156%(X100), DQS PI = 32
7339 06:48:25.892677 [0] MIN Duty = 5031%(X100), DQS PI = 12
7340 06:48:25.895935 [0] AVG Duty = 5093%(X100)
7341 06:48:25.896017
7342 06:48:25.899234 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7343 06:48:25.899316
7344 06:48:25.902477 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7345 06:48:25.905739 [DutyScan_Calibration_Flow] ====Done====
7346 06:48:25.905820
7347 06:48:25.909291 [DutyScan_Calibration_Flow] k_type=3
7348 06:48:25.926810
7349 06:48:25.926891 ==DQM 0 ==
7350 06:48:25.929904 Final DQM duty delay cell = 0
7351 06:48:25.933538 [0] MAX Duty = 5187%(X100), DQS PI = 30
7352 06:48:25.936814 [0] MIN Duty = 4875%(X100), DQS PI = 0
7353 06:48:25.936895 [0] AVG Duty = 5031%(X100)
7354 06:48:25.939922
7355 06:48:25.940003 ==DQM 1 ==
7356 06:48:25.943283 Final DQM duty delay cell = 0
7357 06:48:25.946522 [0] MAX Duty = 4969%(X100), DQS PI = 62
7358 06:48:25.949879 [0] MIN Duty = 4813%(X100), DQS PI = 20
7359 06:48:25.953118 [0] AVG Duty = 4891%(X100)
7360 06:48:25.953198
7361 06:48:25.956352 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7362 06:48:25.956433
7363 06:48:25.959716 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7364 06:48:25.963178 [DutyScan_Calibration_Flow] ====Done====
7365 06:48:25.963260
7366 06:48:25.966492 [DutyScan_Calibration_Flow] k_type=2
7367 06:48:25.983157
7368 06:48:25.983238 ==DQ 0 ==
7369 06:48:25.986427 Final DQ duty delay cell = -4
7370 06:48:25.989508 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7371 06:48:25.992866 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7372 06:48:25.996158 [-4] AVG Duty = 4938%(X100)
7373 06:48:25.996239
7374 06:48:25.996302 ==DQ 1 ==
7375 06:48:25.999456 Final DQ duty delay cell = 0
7376 06:48:26.002806 [0] MAX Duty = 5156%(X100), DQS PI = 58
7377 06:48:26.006064 [0] MIN Duty = 5000%(X100), DQS PI = 16
7378 06:48:26.009591 [0] AVG Duty = 5078%(X100)
7379 06:48:26.009669
7380 06:48:26.012877 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7381 06:48:26.012952
7382 06:48:26.016185 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7383 06:48:26.019649 [DutyScan_Calibration_Flow] ====Done====
7384 06:48:26.019722 ==
7385 06:48:26.022900 Dram Type= 6, Freq= 0, CH_1, rank 0
7386 06:48:26.026125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7387 06:48:26.026202 ==
7388 06:48:26.029359 [Duty_Offset_Calibration]
7389 06:48:26.029435 B0:1 B1:-2 CA:1
7390 06:48:26.029537
7391 06:48:26.032425 [DutyScan_Calibration_Flow] k_type=0
7392 06:48:26.043644
7393 06:48:26.043724 ==CLK 0==
7394 06:48:26.046944 Final CLK duty delay cell = 0
7395 06:48:26.050160 [0] MAX Duty = 5062%(X100), DQS PI = 20
7396 06:48:26.053654 [0] MIN Duty = 4844%(X100), DQS PI = 4
7397 06:48:26.053729 [0] AVG Duty = 4953%(X100)
7398 06:48:26.056633
7399 06:48:26.060217 CH1 CLK Duty spec in!! Max-Min= 218%
7400 06:48:26.063331 [DutyScan_Calibration_Flow] ====Done====
7401 06:48:26.063412
7402 06:48:26.066748 [DutyScan_Calibration_Flow] k_type=1
7403 06:48:26.082404
7404 06:48:26.082524 ==DQS 0 ==
7405 06:48:26.085857 Final DQS duty delay cell = -4
7406 06:48:26.088946 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7407 06:48:26.092113 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7408 06:48:26.095641 [-4] AVG Duty = 4922%(X100)
7409 06:48:26.095722
7410 06:48:26.095790 ==DQS 1 ==
7411 06:48:26.098981 Final DQS duty delay cell = 0
7412 06:48:26.102255 [0] MAX Duty = 5093%(X100), DQS PI = 60
7413 06:48:26.105444 [0] MIN Duty = 4844%(X100), DQS PI = 26
7414 06:48:26.108778 [0] AVG Duty = 4968%(X100)
7415 06:48:26.108851
7416 06:48:26.112097 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7417 06:48:26.112193
7418 06:48:26.115407 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7419 06:48:26.118722 [DutyScan_Calibration_Flow] ====Done====
7420 06:48:26.118817
7421 06:48:26.122081 [DutyScan_Calibration_Flow] k_type=3
7422 06:48:26.139757
7423 06:48:26.139850 ==DQM 0 ==
7424 06:48:26.142911 Final DQM duty delay cell = 0
7425 06:48:26.146260 [0] MAX Duty = 5031%(X100), DQS PI = 24
7426 06:48:26.149629 [0] MIN Duty = 4813%(X100), DQS PI = 56
7427 06:48:26.153025 [0] AVG Duty = 4922%(X100)
7428 06:48:26.153097
7429 06:48:26.153158 ==DQM 1 ==
7430 06:48:26.156121 Final DQM duty delay cell = 0
7431 06:48:26.159694 [0] MAX Duty = 5062%(X100), DQS PI = 34
7432 06:48:26.162923 [0] MIN Duty = 4875%(X100), DQS PI = 24
7433 06:48:26.166194 [0] AVG Duty = 4968%(X100)
7434 06:48:26.166272
7435 06:48:26.169416 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7436 06:48:26.169549
7437 06:48:26.172755 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7438 06:48:26.175897 [DutyScan_Calibration_Flow] ====Done====
7439 06:48:26.175972
7440 06:48:26.179180 [DutyScan_Calibration_Flow] k_type=2
7441 06:48:26.196409
7442 06:48:26.196495 ==DQ 0 ==
7443 06:48:26.200091 Final DQ duty delay cell = 0
7444 06:48:26.203143 [0] MAX Duty = 5093%(X100), DQS PI = 20
7445 06:48:26.206695 [0] MIN Duty = 4907%(X100), DQS PI = 60
7446 06:48:26.206792 [0] AVG Duty = 5000%(X100)
7447 06:48:26.210035
7448 06:48:26.210116 ==DQ 1 ==
7449 06:48:26.213150 Final DQ duty delay cell = 0
7450 06:48:26.216381 [0] MAX Duty = 5156%(X100), DQS PI = 36
7451 06:48:26.219656 [0] MIN Duty = 4969%(X100), DQS PI = 24
7452 06:48:26.219793 [0] AVG Duty = 5062%(X100)
7453 06:48:26.223059
7454 06:48:26.226703 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7455 06:48:26.226792
7456 06:48:26.229976 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7457 06:48:26.233222 [DutyScan_Calibration_Flow] ====Done====
7458 06:48:26.236537 nWR fixed to 30
7459 06:48:26.236619 [ModeRegInit_LP4] CH0 RK0
7460 06:48:26.239757 [ModeRegInit_LP4] CH0 RK1
7461 06:48:26.242865 [ModeRegInit_LP4] CH1 RK0
7462 06:48:26.246472 [ModeRegInit_LP4] CH1 RK1
7463 06:48:26.246554 match AC timing 5
7464 06:48:26.252796 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7465 06:48:26.256126 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7466 06:48:26.259399 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7467 06:48:26.266214 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7468 06:48:26.269636 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7469 06:48:26.269739 [MiockJmeterHQA]
7470 06:48:26.269830
7471 06:48:26.272868 [DramcMiockJmeter] u1RxGatingPI = 0
7472 06:48:26.276175 0 : 4255, 4029
7473 06:48:26.276260 4 : 4253, 4026
7474 06:48:26.279530 8 : 4252, 4027
7475 06:48:26.279616 12 : 4255, 4029
7476 06:48:26.279705 16 : 4363, 4138
7477 06:48:26.282783 20 : 4253, 4026
7478 06:48:26.282868 24 : 4252, 4027
7479 06:48:26.286251 28 : 4252, 4027
7480 06:48:26.286336 32 : 4255, 4029
7481 06:48:26.289683 36 : 4252, 4027
7482 06:48:26.289767 40 : 4250, 4026
7483 06:48:26.289834 44 : 4366, 4140
7484 06:48:26.292939 48 : 4250, 4027
7485 06:48:26.293027 52 : 4255, 4029
7486 06:48:26.296330 56 : 4250, 4027
7487 06:48:26.296414 60 : 4360, 4137
7488 06:48:26.299571 64 : 4250, 4026
7489 06:48:26.299655 68 : 4361, 4138
7490 06:48:26.302905 72 : 4250, 4026
7491 06:48:26.302989 76 : 4250, 4027
7492 06:48:26.303055 80 : 4250, 4027
7493 06:48:26.306178 84 : 4252, 4029
7494 06:48:26.306262 88 : 4361, 4137
7495 06:48:26.309542 92 : 4250, 4026
7496 06:48:26.309626 96 : 4360, 4138
7497 06:48:26.312938 100 : 4250, 4027
7498 06:48:26.313022 104 : 4250, 3571
7499 06:48:26.315971 108 : 4253, 2
7500 06:48:26.316047 112 : 4250, 0
7501 06:48:26.316114 116 : 4250, 0
7502 06:48:26.319217 120 : 4250, 0
7503 06:48:26.319317 124 : 4250, 0
7504 06:48:26.319410 128 : 4361, 0
7505 06:48:26.322551 132 : 4361, 0
7506 06:48:26.322628 136 : 4250, 0
7507 06:48:26.325973 140 : 4252, 0
7508 06:48:26.326054 144 : 4363, 0
7509 06:48:26.326119 148 : 4250, 0
7510 06:48:26.329206 152 : 4250, 0
7511 06:48:26.329285 156 : 4250, 0
7512 06:48:26.332800 160 : 4253, 0
7513 06:48:26.332877 164 : 4360, 0
7514 06:48:26.332941 168 : 4250, 0
7515 06:48:26.336063 172 : 4250, 0
7516 06:48:26.336165 176 : 4250, 0
7517 06:48:26.339337 180 : 4361, 0
7518 06:48:26.339428 184 : 4361, 0
7519 06:48:26.339492 188 : 4250, 0
7520 06:48:26.342611 192 : 4250, 0
7521 06:48:26.342690 196 : 4250, 0
7522 06:48:26.345828 200 : 4253, 0
7523 06:48:26.345903 204 : 4250, 0
7524 06:48:26.345974 208 : 4250, 0
7525 06:48:26.348940 212 : 4253, 0
7526 06:48:26.349024 216 : 4360, 0
7527 06:48:26.349095 220 : 4250, 0
7528 06:48:26.352422 224 : 4250, 0
7529 06:48:26.352499 228 : 4250, 0
7530 06:48:26.355770 232 : 4361, 0
7531 06:48:26.355857 236 : 4361, 1060
7532 06:48:26.359162 240 : 4361, 4137
7533 06:48:26.359237 244 : 4249, 4027
7534 06:48:26.362423 248 : 4250, 4027
7535 06:48:26.362514 252 : 4250, 4026
7536 06:48:26.362579 256 : 4250, 4027
7537 06:48:26.365635 260 : 4249, 4027
7538 06:48:26.365711 264 : 4250, 4026
7539 06:48:26.368939 268 : 4253, 4029
7540 06:48:26.369010 272 : 4250, 4027
7541 06:48:26.372218 276 : 4361, 4138
7542 06:48:26.372291 280 : 4360, 4137
7543 06:48:26.375838 284 : 4250, 4027
7544 06:48:26.375911 288 : 4363, 4140
7545 06:48:26.379141 292 : 4250, 4027
7546 06:48:26.379216 296 : 4250, 4027
7547 06:48:26.382474 300 : 4250, 4026
7548 06:48:26.382548 304 : 4253, 4029
7549 06:48:26.385767 308 : 4250, 4027
7550 06:48:26.385844 312 : 4250, 4027
7551 06:48:26.385907 316 : 4250, 4026
7552 06:48:26.388890 320 : 4253, 4029
7553 06:48:26.388965 324 : 4250, 4027
7554 06:48:26.392047 328 : 4361, 4138
7555 06:48:26.392130 332 : 4360, 4137
7556 06:48:26.395543 336 : 4250, 4026
7557 06:48:26.395626 340 : 4361, 4137
7558 06:48:26.398718 344 : 4250, 4027
7559 06:48:26.398800 348 : 4250, 4027
7560 06:48:26.401980 352 : 4253, 4017
7561 06:48:26.402079 356 : 4253, 2777
7562 06:48:26.405706 360 : 4250, 2
7563 06:48:26.405805
7564 06:48:26.405902 MIOCK jitter meter ch=0
7565 06:48:26.405995
7566 06:48:26.408964 1T = (360-108) = 252 dly cells
7567 06:48:26.415263 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7568 06:48:26.415347 ==
7569 06:48:26.418622 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 06:48:26.421872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 06:48:26.421957 ==
7572 06:48:26.428435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7573 06:48:26.431707 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7574 06:48:26.435217 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7575 06:48:26.441757 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7576 06:48:26.451698 [CA 0] Center 44 (14~75) winsize 62
7577 06:48:26.454743 [CA 1] Center 43 (13~74) winsize 62
7578 06:48:26.457969 [CA 2] Center 40 (11~69) winsize 59
7579 06:48:26.461652 [CA 3] Center 39 (10~68) winsize 59
7580 06:48:26.464885 [CA 4] Center 37 (8~67) winsize 60
7581 06:48:26.468129 [CA 5] Center 37 (7~67) winsize 61
7582 06:48:26.468204
7583 06:48:26.471642 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7584 06:48:26.471717
7585 06:48:26.478104 [CATrainingPosCal] consider 1 rank data
7586 06:48:26.478187 u2DelayCellTimex100 = 258/100 ps
7587 06:48:26.484764 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7588 06:48:26.488174 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7589 06:48:26.491608 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7590 06:48:26.494691 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7591 06:48:26.498229 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7592 06:48:26.501134 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7593 06:48:26.501211
7594 06:48:26.504782 CA PerBit enable=1, Macro0, CA PI delay=37
7595 06:48:26.504859
7596 06:48:26.507745 [CBTSetCACLKResult] CA Dly = 37
7597 06:48:26.511268 CS Dly: 11 (0~42)
7598 06:48:26.514750 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7599 06:48:26.518005 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7600 06:48:26.518083 ==
7601 06:48:26.521203 Dram Type= 6, Freq= 0, CH_0, rank 1
7602 06:48:26.527941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 06:48:26.528026 ==
7604 06:48:26.531315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7605 06:48:26.537852 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7606 06:48:26.541187 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7607 06:48:26.547511 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7608 06:48:26.555640 [CA 0] Center 44 (13~75) winsize 63
7609 06:48:26.558659 [CA 1] Center 43 (13~74) winsize 62
7610 06:48:26.561889 [CA 2] Center 39 (10~69) winsize 60
7611 06:48:26.565466 [CA 3] Center 39 (10~68) winsize 59
7612 06:48:26.568412 [CA 4] Center 37 (8~67) winsize 60
7613 06:48:26.571935 [CA 5] Center 36 (7~66) winsize 60
7614 06:48:26.572013
7615 06:48:26.575377 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7616 06:48:26.575455
7617 06:48:26.581874 [CATrainingPosCal] consider 2 rank data
7618 06:48:26.581953 u2DelayCellTimex100 = 258/100 ps
7619 06:48:26.588411 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7620 06:48:26.591735 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7621 06:48:26.595053 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7622 06:48:26.598369 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7623 06:48:26.601618 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7624 06:48:26.604860 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7625 06:48:26.604940
7626 06:48:26.608462 CA PerBit enable=1, Macro0, CA PI delay=36
7627 06:48:26.608538
7628 06:48:26.611706 [CBTSetCACLKResult] CA Dly = 36
7629 06:48:26.614894 CS Dly: 11 (0~42)
7630 06:48:26.618380 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7631 06:48:26.621771 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7632 06:48:26.621853
7633 06:48:26.624973 ----->DramcWriteLeveling(PI) begin...
7634 06:48:26.628194 ==
7635 06:48:26.628277 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 06:48:26.634753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 06:48:26.634835 ==
7638 06:48:26.638090 Write leveling (Byte 0): 36 => 36
7639 06:48:26.641345 Write leveling (Byte 1): 29 => 29
7640 06:48:26.644717 DramcWriteLeveling(PI) end<-----
7641 06:48:26.644798
7642 06:48:26.644861 ==
7643 06:48:26.648085 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 06:48:26.651361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 06:48:26.651492 ==
7646 06:48:26.654691 [Gating] SW mode calibration
7647 06:48:26.661287 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7648 06:48:26.664980 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7649 06:48:26.671372 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 06:48:26.674865 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 06:48:26.678114 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 06:48:26.684791 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7653 06:48:26.687967 1 4 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7654 06:48:26.691106 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7655 06:48:26.697793 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7656 06:48:26.701359 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7657 06:48:26.704498 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7658 06:48:26.711058 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 06:48:26.714456 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7660 06:48:26.717722 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7661 06:48:26.724212 1 5 16 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7662 06:48:26.727880 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7663 06:48:26.731219 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7664 06:48:26.737851 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 06:48:26.741139 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 06:48:26.744430 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 06:48:26.751121 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 06:48:26.754451 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7669 06:48:26.757816 1 6 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7670 06:48:26.764369 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7671 06:48:26.767716 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 06:48:26.771069 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 06:48:26.777724 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 06:48:26.780682 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 06:48:26.784316 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 06:48:26.790741 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7677 06:48:26.793856 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7678 06:48:26.797431 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7679 06:48:26.804052 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7680 06:48:26.807172 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 06:48:26.810591 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 06:48:26.817289 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 06:48:26.820579 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 06:48:26.823937 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 06:48:26.830569 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 06:48:26.833973 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 06:48:26.837186 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 06:48:26.843897 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 06:48:26.846847 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 06:48:26.850424 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 06:48:26.853657 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7692 06:48:26.860184 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7693 06:48:26.863599 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7694 06:48:26.866789 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7695 06:48:26.870121 Total UI for P1: 0, mck2ui 16
7696 06:48:26.873677 best dqsien dly found for B0: ( 1, 9, 12)
7697 06:48:26.880215 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7698 06:48:26.883488 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7699 06:48:26.886765 Total UI for P1: 0, mck2ui 16
7700 06:48:26.890346 best dqsien dly found for B1: ( 1, 9, 24)
7701 06:48:26.893629 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7702 06:48:26.896885 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7703 06:48:26.896960
7704 06:48:26.900165 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7705 06:48:26.903466 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7706 06:48:26.906793 [Gating] SW calibration Done
7707 06:48:26.906865 ==
7708 06:48:26.910315 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 06:48:26.916781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 06:48:26.916862 ==
7711 06:48:26.916926 RX Vref Scan: 0
7712 06:48:26.916992
7713 06:48:26.920153 RX Vref 0 -> 0, step: 1
7714 06:48:26.920230
7715 06:48:26.923288 RX Delay 0 -> 252, step: 8
7716 06:48:26.926742 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7717 06:48:26.929788 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7718 06:48:26.933406 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7719 06:48:26.936791 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7720 06:48:26.942976 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7721 06:48:26.946475 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7722 06:48:26.949692 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7723 06:48:26.953183 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7724 06:48:26.956495 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7725 06:48:26.963117 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7726 06:48:26.966130 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7727 06:48:26.969665 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7728 06:48:26.973000 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7729 06:48:26.979378 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7730 06:48:26.982744 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7731 06:48:26.986151 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7732 06:48:26.986232 ==
7733 06:48:26.989449 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 06:48:26.992729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 06:48:26.992810 ==
7736 06:48:26.995975 DQS Delay:
7737 06:48:26.996056 DQS0 = 0, DQS1 = 0
7738 06:48:26.999565 DQM Delay:
7739 06:48:26.999645 DQM0 = 129, DQM1 = 124
7740 06:48:26.999708 DQ Delay:
7741 06:48:27.005848 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =123
7742 06:48:27.009454 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7743 06:48:27.012642 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7744 06:48:27.015895 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7745 06:48:27.015972
7746 06:48:27.016033
7747 06:48:27.016090 ==
7748 06:48:27.019118 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 06:48:27.022432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 06:48:27.022509 ==
7751 06:48:27.022570
7752 06:48:27.022627
7753 06:48:27.025755 TX Vref Scan disable
7754 06:48:27.029064 == TX Byte 0 ==
7755 06:48:27.032341 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7756 06:48:27.035831 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7757 06:48:27.038827 == TX Byte 1 ==
7758 06:48:27.042122 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7759 06:48:27.045488 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7760 06:48:27.045583 ==
7761 06:48:27.048814 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 06:48:27.055698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 06:48:27.055779 ==
7764 06:48:27.067814
7765 06:48:27.070883 TX Vref early break, caculate TX vref
7766 06:48:27.074535 TX Vref=16, minBit 8, minWin=21, winSum=365
7767 06:48:27.077700 TX Vref=18, minBit 8, minWin=22, winSum=374
7768 06:48:27.081042 TX Vref=20, minBit 8, minWin=22, winSum=387
7769 06:48:27.084238 TX Vref=22, minBit 8, minWin=23, winSum=393
7770 06:48:27.087532 TX Vref=24, minBit 4, minWin=24, winSum=405
7771 06:48:27.094181 TX Vref=26, minBit 5, minWin=25, winSum=412
7772 06:48:27.097822 TX Vref=28, minBit 10, minWin=24, winSum=409
7773 06:48:27.100966 TX Vref=30, minBit 8, minWin=23, winSum=404
7774 06:48:27.104165 TX Vref=32, minBit 8, minWin=23, winSum=392
7775 06:48:27.107512 TX Vref=34, minBit 8, minWin=22, winSum=386
7776 06:48:27.114131 [TxChooseVref] Worse bit 5, Min win 25, Win sum 412, Final Vref 26
7777 06:48:27.114211
7778 06:48:27.117359 Final TX Range 0 Vref 26
7779 06:48:27.117440
7780 06:48:27.117543 ==
7781 06:48:27.120601 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 06:48:27.123928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 06:48:27.124014 ==
7784 06:48:27.124078
7785 06:48:27.124136
7786 06:48:27.127190 TX Vref Scan disable
7787 06:48:27.133960 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7788 06:48:27.134074 == TX Byte 0 ==
7789 06:48:27.137272 u2DelayCellOfst[0]=15 cells (4 PI)
7790 06:48:27.140532 u2DelayCellOfst[1]=18 cells (5 PI)
7791 06:48:27.143831 u2DelayCellOfst[2]=11 cells (3 PI)
7792 06:48:27.147443 u2DelayCellOfst[3]=11 cells (3 PI)
7793 06:48:27.150735 u2DelayCellOfst[4]=7 cells (2 PI)
7794 06:48:27.153739 u2DelayCellOfst[5]=0 cells (0 PI)
7795 06:48:27.157074 u2DelayCellOfst[6]=22 cells (6 PI)
7796 06:48:27.160319 u2DelayCellOfst[7]=18 cells (5 PI)
7797 06:48:27.163648 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7798 06:48:27.166975 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7799 06:48:27.170266 == TX Byte 1 ==
7800 06:48:27.173648 u2DelayCellOfst[8]=0 cells (0 PI)
7801 06:48:27.173724 u2DelayCellOfst[9]=3 cells (1 PI)
7802 06:48:27.177107 u2DelayCellOfst[10]=7 cells (2 PI)
7803 06:48:27.180117 u2DelayCellOfst[11]=7 cells (2 PI)
7804 06:48:27.183756 u2DelayCellOfst[12]=11 cells (3 PI)
7805 06:48:27.186982 u2DelayCellOfst[13]=11 cells (3 PI)
7806 06:48:27.190093 u2DelayCellOfst[14]=15 cells (4 PI)
7807 06:48:27.193415 u2DelayCellOfst[15]=11 cells (3 PI)
7808 06:48:27.196874 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7809 06:48:27.203696 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7810 06:48:27.203778 DramC Write-DBI on
7811 06:48:27.203842 ==
7812 06:48:27.206925 Dram Type= 6, Freq= 0, CH_0, rank 0
7813 06:48:27.213275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7814 06:48:27.213378 ==
7815 06:48:27.213481
7816 06:48:27.213602
7817 06:48:27.213670 TX Vref Scan disable
7818 06:48:27.217361 == TX Byte 0 ==
7819 06:48:27.220648 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7820 06:48:27.224223 == TX Byte 1 ==
7821 06:48:27.227229 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7822 06:48:27.230451 DramC Write-DBI off
7823 06:48:27.230589
7824 06:48:27.230692 [DATLAT]
7825 06:48:27.230766 Freq=1600, CH0 RK0
7826 06:48:27.230831
7827 06:48:27.233785 DATLAT Default: 0xf
7828 06:48:27.233859 0, 0xFFFF, sum = 0
7829 06:48:27.237317 1, 0xFFFF, sum = 0
7830 06:48:27.240506 2, 0xFFFF, sum = 0
7831 06:48:27.240579 3, 0xFFFF, sum = 0
7832 06:48:27.243939 4, 0xFFFF, sum = 0
7833 06:48:27.244015 5, 0xFFFF, sum = 0
7834 06:48:27.246901 6, 0xFFFF, sum = 0
7835 06:48:27.246972 7, 0xFFFF, sum = 0
7836 06:48:27.250013 8, 0xFFFF, sum = 0
7837 06:48:27.250091 9, 0xFFFF, sum = 0
7838 06:48:27.253687 10, 0xFFFF, sum = 0
7839 06:48:27.253764 11, 0xFFFF, sum = 0
7840 06:48:27.256886 12, 0xFFFF, sum = 0
7841 06:48:27.256960 13, 0xCFFF, sum = 0
7842 06:48:27.259908 14, 0x0, sum = 1
7843 06:48:27.260017 15, 0x0, sum = 2
7844 06:48:27.263192 16, 0x0, sum = 3
7845 06:48:27.263265 17, 0x0, sum = 4
7846 06:48:27.266546 best_step = 15
7847 06:48:27.266646
7848 06:48:27.266723 ==
7849 06:48:27.270105 Dram Type= 6, Freq= 0, CH_0, rank 0
7850 06:48:27.273258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7851 06:48:27.273339 ==
7852 06:48:27.276637 RX Vref Scan: 1
7853 06:48:27.276734
7854 06:48:27.276822 Set Vref Range= 24 -> 127
7855 06:48:27.276882
7856 06:48:27.280102 RX Vref 24 -> 127, step: 1
7857 06:48:27.280199
7858 06:48:27.283191 RX Delay 11 -> 252, step: 4
7859 06:48:27.283272
7860 06:48:27.286431 Set Vref, RX VrefLevel [Byte0]: 24
7861 06:48:27.289723 [Byte1]: 24
7862 06:48:27.289829
7863 06:48:27.293412 Set Vref, RX VrefLevel [Byte0]: 25
7864 06:48:27.296667 [Byte1]: 25
7865 06:48:27.300353
7866 06:48:27.300460 Set Vref, RX VrefLevel [Byte0]: 26
7867 06:48:27.303374 [Byte1]: 26
7868 06:48:27.307936
7869 06:48:27.308033 Set Vref, RX VrefLevel [Byte0]: 27
7870 06:48:27.311113 [Byte1]: 27
7871 06:48:27.315359
7872 06:48:27.315440 Set Vref, RX VrefLevel [Byte0]: 28
7873 06:48:27.318654 [Byte1]: 28
7874 06:48:27.323134
7875 06:48:27.323213 Set Vref, RX VrefLevel [Byte0]: 29
7876 06:48:27.326350 [Byte1]: 29
7877 06:48:27.330478
7878 06:48:27.330588 Set Vref, RX VrefLevel [Byte0]: 30
7879 06:48:27.333848 [Byte1]: 30
7880 06:48:27.338364
7881 06:48:27.338445 Set Vref, RX VrefLevel [Byte0]: 31
7882 06:48:27.341694 [Byte1]: 31
7883 06:48:27.345830
7884 06:48:27.345942 Set Vref, RX VrefLevel [Byte0]: 32
7885 06:48:27.348980 [Byte1]: 32
7886 06:48:27.353431
7887 06:48:27.353545 Set Vref, RX VrefLevel [Byte0]: 33
7888 06:48:27.356724 [Byte1]: 33
7889 06:48:27.360894
7890 06:48:27.360989 Set Vref, RX VrefLevel [Byte0]: 34
7891 06:48:27.364607 [Byte1]: 34
7892 06:48:27.368737
7893 06:48:27.368817 Set Vref, RX VrefLevel [Byte0]: 35
7894 06:48:27.372092 [Byte1]: 35
7895 06:48:27.376175
7896 06:48:27.376254 Set Vref, RX VrefLevel [Byte0]: 36
7897 06:48:27.379494 [Byte1]: 36
7898 06:48:27.383889
7899 06:48:27.383969 Set Vref, RX VrefLevel [Byte0]: 37
7900 06:48:27.387248 [Byte1]: 37
7901 06:48:27.391644
7902 06:48:27.391724 Set Vref, RX VrefLevel [Byte0]: 38
7903 06:48:27.394832 [Byte1]: 38
7904 06:48:27.399000
7905 06:48:27.399080 Set Vref, RX VrefLevel [Byte0]: 39
7906 06:48:27.402318 [Byte1]: 39
7907 06:48:27.406643
7908 06:48:27.406759 Set Vref, RX VrefLevel [Byte0]: 40
7909 06:48:27.410024 [Byte1]: 40
7910 06:48:27.414421
7911 06:48:27.414501 Set Vref, RX VrefLevel [Byte0]: 41
7912 06:48:27.417813 [Byte1]: 41
7913 06:48:27.422050
7914 06:48:27.422130 Set Vref, RX VrefLevel [Byte0]: 42
7915 06:48:27.425321 [Byte1]: 42
7916 06:48:27.429516
7917 06:48:27.429596 Set Vref, RX VrefLevel [Byte0]: 43
7918 06:48:27.432786 [Byte1]: 43
7919 06:48:27.437195
7920 06:48:27.437275 Set Vref, RX VrefLevel [Byte0]: 44
7921 06:48:27.440660 [Byte1]: 44
7922 06:48:27.444830
7923 06:48:27.444910 Set Vref, RX VrefLevel [Byte0]: 45
7924 06:48:27.448214 [Byte1]: 45
7925 06:48:27.452301
7926 06:48:27.452398 Set Vref, RX VrefLevel [Byte0]: 46
7927 06:48:27.455853 [Byte1]: 46
7928 06:48:27.460068
7929 06:48:27.460148 Set Vref, RX VrefLevel [Byte0]: 47
7930 06:48:27.463195 [Byte1]: 47
7931 06:48:27.467857
7932 06:48:27.467935 Set Vref, RX VrefLevel [Byte0]: 48
7933 06:48:27.471113 [Byte1]: 48
7934 06:48:27.475289
7935 06:48:27.475364 Set Vref, RX VrefLevel [Byte0]: 49
7936 06:48:27.478546 [Byte1]: 49
7937 06:48:27.482704
7938 06:48:27.482810 Set Vref, RX VrefLevel [Byte0]: 50
7939 06:48:27.486074 [Byte1]: 50
7940 06:48:27.490323
7941 06:48:27.490401 Set Vref, RX VrefLevel [Byte0]: 51
7942 06:48:27.493838 [Byte1]: 51
7943 06:48:27.498092
7944 06:48:27.498198 Set Vref, RX VrefLevel [Byte0]: 52
7945 06:48:27.501425 [Byte1]: 52
7946 06:48:27.505769
7947 06:48:27.505857 Set Vref, RX VrefLevel [Byte0]: 53
7948 06:48:27.509020 [Byte1]: 53
7949 06:48:27.513292
7950 06:48:27.513391 Set Vref, RX VrefLevel [Byte0]: 54
7951 06:48:27.516669 [Byte1]: 54
7952 06:48:27.520641
7953 06:48:27.520714 Set Vref, RX VrefLevel [Byte0]: 55
7954 06:48:27.524357 [Byte1]: 55
7955 06:48:27.528544
7956 06:48:27.528641 Set Vref, RX VrefLevel [Byte0]: 56
7957 06:48:27.531678 [Byte1]: 56
7958 06:48:27.536016
7959 06:48:27.536124 Set Vref, RX VrefLevel [Byte0]: 57
7960 06:48:27.539285 [Byte1]: 57
7961 06:48:27.543790
7962 06:48:27.543867 Set Vref, RX VrefLevel [Byte0]: 58
7963 06:48:27.546869 [Byte1]: 58
7964 06:48:27.551466
7965 06:48:27.551544 Set Vref, RX VrefLevel [Byte0]: 59
7966 06:48:27.554781 [Byte1]: 59
7967 06:48:27.559061
7968 06:48:27.559144 Set Vref, RX VrefLevel [Byte0]: 60
7969 06:48:27.562035 [Byte1]: 60
7970 06:48:27.566663
7971 06:48:27.566744 Set Vref, RX VrefLevel [Byte0]: 61
7972 06:48:27.570003 [Byte1]: 61
7973 06:48:27.574264
7974 06:48:27.574346 Set Vref, RX VrefLevel [Byte0]: 62
7975 06:48:27.577283 [Byte1]: 62
7976 06:48:27.581934
7977 06:48:27.582017 Set Vref, RX VrefLevel [Byte0]: 63
7978 06:48:27.584884 [Byte1]: 63
7979 06:48:27.589403
7980 06:48:27.589492 Set Vref, RX VrefLevel [Byte0]: 64
7981 06:48:27.592805 [Byte1]: 64
7982 06:48:27.597230
7983 06:48:27.597311 Set Vref, RX VrefLevel [Byte0]: 65
7984 06:48:27.600340 [Byte1]: 65
7985 06:48:27.604942
7986 06:48:27.605035 Set Vref, RX VrefLevel [Byte0]: 66
7987 06:48:27.608183 [Byte1]: 66
7988 06:48:27.612272
7989 06:48:27.612374 Set Vref, RX VrefLevel [Byte0]: 67
7990 06:48:27.615673 [Byte1]: 67
7991 06:48:27.620169
7992 06:48:27.620295 Set Vref, RX VrefLevel [Byte0]: 68
7993 06:48:27.623439 [Byte1]: 68
7994 06:48:27.627555
7995 06:48:27.627727 Set Vref, RX VrefLevel [Byte0]: 69
7996 06:48:27.630934 [Byte1]: 69
7997 06:48:27.635242
7998 06:48:27.635419 Set Vref, RX VrefLevel [Byte0]: 70
7999 06:48:27.638467 [Byte1]: 70
8000 06:48:27.643079
8001 06:48:27.643331 Set Vref, RX VrefLevel [Byte0]: 71
8002 06:48:27.646252 [Byte1]: 71
8003 06:48:27.650307
8004 06:48:27.650626 Set Vref, RX VrefLevel [Byte0]: 72
8005 06:48:27.653933 [Byte1]: 72
8006 06:48:27.658184
8007 06:48:27.658638 Set Vref, RX VrefLevel [Byte0]: 73
8008 06:48:27.661618 [Byte1]: 73
8009 06:48:27.666045
8010 06:48:27.666536 Set Vref, RX VrefLevel [Byte0]: 74
8011 06:48:27.669100 [Byte1]: 74
8012 06:48:27.673545
8013 06:48:27.674143 Set Vref, RX VrefLevel [Byte0]: 75
8014 06:48:27.676891 [Byte1]: 75
8015 06:48:27.680980
8016 06:48:27.681437 Set Vref, RX VrefLevel [Byte0]: 76
8017 06:48:27.684361 [Byte1]: 76
8018 06:48:27.689035
8019 06:48:27.689551 Set Vref, RX VrefLevel [Byte0]: 77
8020 06:48:27.691859 [Byte1]: 77
8021 06:48:27.696631
8022 06:48:27.697081 Set Vref, RX VrefLevel [Byte0]: 78
8023 06:48:27.699931 [Byte1]: 78
8024 06:48:27.704005
8025 06:48:27.704461 Final RX Vref Byte 0 = 62 to rank0
8026 06:48:27.707164 Final RX Vref Byte 1 = 61 to rank0
8027 06:48:27.710644 Final RX Vref Byte 0 = 62 to rank1
8028 06:48:27.713913 Final RX Vref Byte 1 = 61 to rank1==
8029 06:48:27.717276 Dram Type= 6, Freq= 0, CH_0, rank 0
8030 06:48:27.723794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 06:48:27.724286 ==
8032 06:48:27.724672 DQS Delay:
8033 06:48:27.727247 DQS0 = 0, DQS1 = 0
8034 06:48:27.727929 DQM Delay:
8035 06:48:27.728435 DQM0 = 126, DQM1 = 120
8036 06:48:27.730679 DQ Delay:
8037 06:48:27.733579 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8038 06:48:27.737189 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
8039 06:48:27.740274 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8040 06:48:27.743790 DQ12 =124, DQ13 =124, DQ14 =132, DQ15 =128
8041 06:48:27.744248
8042 06:48:27.744605
8043 06:48:27.744937
8044 06:48:27.747135 [DramC_TX_OE_Calibration] TA2
8045 06:48:27.750627 Original DQ_B0 (3 6) =30, OEN = 27
8046 06:48:27.753902 Original DQ_B1 (3 6) =30, OEN = 27
8047 06:48:27.757019 24, 0x0, End_B0=24 End_B1=24
8048 06:48:27.757560 25, 0x0, End_B0=25 End_B1=25
8049 06:48:27.760187 26, 0x0, End_B0=26 End_B1=26
8050 06:48:27.763350 27, 0x0, End_B0=27 End_B1=27
8051 06:48:27.767003 28, 0x0, End_B0=28 End_B1=28
8052 06:48:27.770223 29, 0x0, End_B0=29 End_B1=29
8053 06:48:27.770706 30, 0x0, End_B0=30 End_B1=30
8054 06:48:27.773439 31, 0x4141, End_B0=30 End_B1=30
8055 06:48:27.776973 Byte0 end_step=30 best_step=27
8056 06:48:27.780312 Byte1 end_step=30 best_step=27
8057 06:48:27.783582 Byte0 TX OE(2T, 0.5T) = (3, 3)
8058 06:48:27.786940 Byte1 TX OE(2T, 0.5T) = (3, 3)
8059 06:48:27.787427
8060 06:48:27.787815
8061 06:48:27.793326 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8062 06:48:27.796717 CH0 RK0: MR19=303, MR18=1414
8063 06:48:27.803472 CH0_RK0: MR19=0x303, MR18=0x1414, DQSOSC=399, MR23=63, INC=23, DEC=15
8064 06:48:27.803962
8065 06:48:27.806543 ----->DramcWriteLeveling(PI) begin...
8066 06:48:27.807023 ==
8067 06:48:27.809818 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 06:48:27.813400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 06:48:27.814000 ==
8070 06:48:27.816657 Write leveling (Byte 0): 34 => 34
8071 06:48:27.820016 Write leveling (Byte 1): 26 => 26
8072 06:48:27.823161 DramcWriteLeveling(PI) end<-----
8073 06:48:27.823640
8074 06:48:27.824120 ==
8075 06:48:27.826556 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 06:48:27.829766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 06:48:27.830269 ==
8078 06:48:27.833258 [Gating] SW mode calibration
8079 06:48:27.840030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8080 06:48:27.846463 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8081 06:48:27.849609 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 06:48:27.856319 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 06:48:27.859617 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8084 06:48:27.862884 1 4 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8085 06:48:27.869750 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8086 06:48:27.872833 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8087 06:48:27.876250 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8088 06:48:27.882624 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8089 06:48:27.885970 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8090 06:48:27.889207 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8091 06:48:27.895902 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8092 06:48:27.899418 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
8093 06:48:27.902578 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8094 06:48:27.909287 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8095 06:48:27.912654 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 06:48:27.915742 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 06:48:27.922260 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 06:48:27.925767 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 06:48:27.929274 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
8100 06:48:27.935646 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8101 06:48:27.938937 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8102 06:48:27.942279 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8103 06:48:27.948789 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 06:48:27.952014 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 06:48:27.955462 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 06:48:27.962073 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 06:48:27.965564 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 06:48:27.968710 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8109 06:48:27.975241 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8110 06:48:27.978439 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8111 06:48:27.982128 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 06:48:27.985119 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 06:48:27.992055 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 06:48:27.995499 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 06:48:27.998482 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 06:48:28.005073 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 06:48:28.008458 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 06:48:28.011799 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 06:48:28.018265 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 06:48:28.021619 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 06:48:28.024802 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 06:48:28.031649 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 06:48:28.034898 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8124 06:48:28.038220 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8125 06:48:28.041517 Total UI for P1: 0, mck2ui 16
8126 06:48:28.045093 best dqsien dly found for B0: ( 1, 9, 8)
8127 06:48:28.051807 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8128 06:48:28.055114 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8129 06:48:28.058279 Total UI for P1: 0, mck2ui 16
8130 06:48:28.061594 best dqsien dly found for B1: ( 1, 9, 16)
8131 06:48:28.064885 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8132 06:48:28.068196 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8133 06:48:28.068662
8134 06:48:28.071407 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8135 06:48:28.074645 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8136 06:48:28.077847 [Gating] SW calibration Done
8137 06:48:28.078299 ==
8138 06:48:28.081703 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 06:48:28.084679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 06:48:28.087981 ==
8141 06:48:28.088548 RX Vref Scan: 0
8142 06:48:28.089089
8143 06:48:28.091335 RX Vref 0 -> 0, step: 1
8144 06:48:28.091996
8145 06:48:28.092553 RX Delay 0 -> 252, step: 8
8146 06:48:28.097996 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8147 06:48:28.101251 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8148 06:48:28.104755 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8149 06:48:28.108206 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8150 06:48:28.111512 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8151 06:48:28.118244 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8152 06:48:28.121116 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8153 06:48:28.124687 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8154 06:48:28.127959 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8155 06:48:28.131299 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8156 06:48:28.137970 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8157 06:48:28.141207 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8158 06:48:28.144700 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8159 06:48:28.147698 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8160 06:48:28.154715 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8161 06:48:28.157979 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8162 06:48:28.158509 ==
8163 06:48:28.161089 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 06:48:28.164421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 06:48:28.164975 ==
8166 06:48:28.165325 DQS Delay:
8167 06:48:28.167680 DQS0 = 0, DQS1 = 0
8168 06:48:28.168102 DQM Delay:
8169 06:48:28.170917 DQM0 = 128, DQM1 = 121
8170 06:48:28.171459 DQ Delay:
8171 06:48:28.174413 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8172 06:48:28.177840 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8173 06:48:28.181051 DQ8 =115, DQ9 =107, DQ10 =119, DQ11 =115
8174 06:48:28.187633 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8175 06:48:28.188055
8176 06:48:28.188386
8177 06:48:28.188692 ==
8178 06:48:28.190930 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 06:48:28.194170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 06:48:28.194590 ==
8181 06:48:28.194924
8182 06:48:28.195232
8183 06:48:28.197330 TX Vref Scan disable
8184 06:48:28.197797 == TX Byte 0 ==
8185 06:48:28.204093 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8186 06:48:28.207365 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8187 06:48:28.207784 == TX Byte 1 ==
8188 06:48:28.214256 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8189 06:48:28.217288 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8190 06:48:28.217766 ==
8191 06:48:28.220750 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 06:48:28.224066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 06:48:28.224485 ==
8194 06:48:28.238780
8195 06:48:28.241917 TX Vref early break, caculate TX vref
8196 06:48:28.245286 TX Vref=16, minBit 8, minWin=21, winSum=363
8197 06:48:28.248585 TX Vref=18, minBit 1, minWin=22, winSum=370
8198 06:48:28.251890 TX Vref=20, minBit 1, minWin=23, winSum=384
8199 06:48:28.255305 TX Vref=22, minBit 0, minWin=24, winSum=392
8200 06:48:28.258492 TX Vref=24, minBit 0, minWin=24, winSum=403
8201 06:48:28.265160 TX Vref=26, minBit 8, minWin=24, winSum=406
8202 06:48:28.268486 TX Vref=28, minBit 10, minWin=24, winSum=409
8203 06:48:28.271626 TX Vref=30, minBit 8, minWin=23, winSum=404
8204 06:48:28.275111 TX Vref=32, minBit 8, minWin=23, winSum=397
8205 06:48:28.278308 TX Vref=34, minBit 8, minWin=22, winSum=384
8206 06:48:28.285239 [TxChooseVref] Worse bit 10, Min win 24, Win sum 409, Final Vref 28
8207 06:48:28.285862
8208 06:48:28.288363 Final TX Range 0 Vref 28
8209 06:48:28.288881
8210 06:48:28.289213 ==
8211 06:48:28.291707 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 06:48:28.295161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 06:48:28.295728 ==
8214 06:48:28.296081
8215 06:48:28.296391
8216 06:48:28.298488 TX Vref Scan disable
8217 06:48:28.304848 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8218 06:48:28.305424 == TX Byte 0 ==
8219 06:48:28.308409 u2DelayCellOfst[0]=11 cells (3 PI)
8220 06:48:28.311517 u2DelayCellOfst[1]=15 cells (4 PI)
8221 06:48:28.314703 u2DelayCellOfst[2]=7 cells (2 PI)
8222 06:48:28.317931 u2DelayCellOfst[3]=11 cells (3 PI)
8223 06:48:28.321645 u2DelayCellOfst[4]=7 cells (2 PI)
8224 06:48:28.324883 u2DelayCellOfst[5]=0 cells (0 PI)
8225 06:48:28.328098 u2DelayCellOfst[6]=15 cells (4 PI)
8226 06:48:28.331576 u2DelayCellOfst[7]=18 cells (5 PI)
8227 06:48:28.334877 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8228 06:48:28.338137 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8229 06:48:28.341457 == TX Byte 1 ==
8230 06:48:28.341923 u2DelayCellOfst[8]=0 cells (0 PI)
8231 06:48:28.345131 u2DelayCellOfst[9]=0 cells (0 PI)
8232 06:48:28.348478 u2DelayCellOfst[10]=7 cells (2 PI)
8233 06:48:28.351660 u2DelayCellOfst[11]=3 cells (1 PI)
8234 06:48:28.354923 u2DelayCellOfst[12]=11 cells (3 PI)
8235 06:48:28.358268 u2DelayCellOfst[13]=11 cells (3 PI)
8236 06:48:28.361524 u2DelayCellOfst[14]=15 cells (4 PI)
8237 06:48:28.364805 u2DelayCellOfst[15]=11 cells (3 PI)
8238 06:48:28.368187 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8239 06:48:28.374765 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8240 06:48:28.375206 DramC Write-DBI on
8241 06:48:28.375534 ==
8242 06:48:28.378158 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 06:48:28.384659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 06:48:28.385080 ==
8245 06:48:28.385411
8246 06:48:28.385779
8247 06:48:28.386078 TX Vref Scan disable
8248 06:48:28.388209 == TX Byte 0 ==
8249 06:48:28.391620 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8250 06:48:28.395005 == TX Byte 1 ==
8251 06:48:28.398165 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8252 06:48:28.401585 DramC Write-DBI off
8253 06:48:28.401998
8254 06:48:28.402327 [DATLAT]
8255 06:48:28.402783 Freq=1600, CH0 RK1
8256 06:48:28.403111
8257 06:48:28.404974 DATLAT Default: 0xf
8258 06:48:28.405392 0, 0xFFFF, sum = 0
8259 06:48:28.408203 1, 0xFFFF, sum = 0
8260 06:48:28.411624 2, 0xFFFF, sum = 0
8261 06:48:28.412042 3, 0xFFFF, sum = 0
8262 06:48:28.414557 4, 0xFFFF, sum = 0
8263 06:48:28.414977 5, 0xFFFF, sum = 0
8264 06:48:28.418089 6, 0xFFFF, sum = 0
8265 06:48:28.418594 7, 0xFFFF, sum = 0
8266 06:48:28.421264 8, 0xFFFF, sum = 0
8267 06:48:28.421779 9, 0xFFFF, sum = 0
8268 06:48:28.424612 10, 0xFFFF, sum = 0
8269 06:48:28.425042 11, 0xFFFF, sum = 0
8270 06:48:28.428250 12, 0xFFFF, sum = 0
8271 06:48:28.428673 13, 0xCFFF, sum = 0
8272 06:48:28.431568 14, 0x0, sum = 1
8273 06:48:28.432048 15, 0x0, sum = 2
8274 06:48:28.434847 16, 0x0, sum = 3
8275 06:48:28.435348 17, 0x0, sum = 4
8276 06:48:28.437949 best_step = 15
8277 06:48:28.438363
8278 06:48:28.438692 ==
8279 06:48:28.441567 Dram Type= 6, Freq= 0, CH_0, rank 1
8280 06:48:28.444800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 06:48:28.445258 ==
8282 06:48:28.447949 RX Vref Scan: 0
8283 06:48:28.448455
8284 06:48:28.448790 RX Vref 0 -> 0, step: 1
8285 06:48:28.449099
8286 06:48:28.451322 RX Delay 3 -> 252, step: 4
8287 06:48:28.454663 iDelay=191, Bit 0, Center 122 (67 ~ 178) 112
8288 06:48:28.461579 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8289 06:48:28.464554 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8290 06:48:28.467754 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8291 06:48:28.471004 iDelay=191, Bit 4, Center 122 (67 ~ 178) 112
8292 06:48:28.474374 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8293 06:48:28.481269 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8294 06:48:28.484589 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8295 06:48:28.487846 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8296 06:48:28.490947 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8297 06:48:28.494277 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8298 06:48:28.500916 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8299 06:48:28.504343 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8300 06:48:28.507682 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8301 06:48:28.510748 iDelay=191, Bit 14, Center 126 (67 ~ 186) 120
8302 06:48:28.517517 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8303 06:48:28.517940 ==
8304 06:48:28.520588 Dram Type= 6, Freq= 0, CH_0, rank 1
8305 06:48:28.524166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 06:48:28.524587 ==
8307 06:48:28.524921 DQS Delay:
8308 06:48:28.527396 DQS0 = 0, DQS1 = 0
8309 06:48:28.527814 DQM Delay:
8310 06:48:28.530825 DQM0 = 124, DQM1 = 117
8311 06:48:28.531242 DQ Delay:
8312 06:48:28.534068 DQ0 =122, DQ1 =126, DQ2 =120, DQ3 =122
8313 06:48:28.537264 DQ4 =122, DQ5 =112, DQ6 =134, DQ7 =134
8314 06:48:28.540409 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8315 06:48:28.543909 DQ12 =124, DQ13 =122, DQ14 =126, DQ15 =124
8316 06:48:28.544331
8317 06:48:28.544659
8318 06:48:28.547284
8319 06:48:28.547705 [DramC_TX_OE_Calibration] TA2
8320 06:48:28.550526 Original DQ_B0 (3 6) =30, OEN = 27
8321 06:48:28.554054 Original DQ_B1 (3 6) =30, OEN = 27
8322 06:48:28.557057 24, 0x0, End_B0=24 End_B1=24
8323 06:48:28.560391 25, 0x0, End_B0=25 End_B1=25
8324 06:48:28.563398 26, 0x0, End_B0=26 End_B1=26
8325 06:48:28.563483 27, 0x0, End_B0=27 End_B1=27
8326 06:48:28.566726 28, 0x0, End_B0=28 End_B1=28
8327 06:48:28.570004 29, 0x0, End_B0=29 End_B1=29
8328 06:48:28.573304 30, 0x0, End_B0=30 End_B1=30
8329 06:48:28.576239 31, 0x4141, End_B0=30 End_B1=30
8330 06:48:28.576323 Byte0 end_step=30 best_step=27
8331 06:48:28.579543 Byte1 end_step=30 best_step=27
8332 06:48:28.582921 Byte0 TX OE(2T, 0.5T) = (3, 3)
8333 06:48:28.586145 Byte1 TX OE(2T, 0.5T) = (3, 3)
8334 06:48:28.586228
8335 06:48:28.586312
8336 06:48:28.596195 [DQSOSCAuto] RK1, (LSB)MR18= 0x2715, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
8337 06:48:28.596280 CH0 RK1: MR19=303, MR18=2715
8338 06:48:28.602771 CH0_RK1: MR19=0x303, MR18=0x2715, DQSOSC=390, MR23=63, INC=24, DEC=16
8339 06:48:28.606295 [RxdqsGatingPostProcess] freq 1600
8340 06:48:28.613095 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8341 06:48:28.616203 best DQS0 dly(2T, 0.5T) = (1, 1)
8342 06:48:28.619666 best DQS1 dly(2T, 0.5T) = (1, 1)
8343 06:48:28.619749 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8344 06:48:28.622743 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8345 06:48:28.626118 best DQS0 dly(2T, 0.5T) = (1, 1)
8346 06:48:28.629396 best DQS1 dly(2T, 0.5T) = (1, 1)
8347 06:48:28.632820 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8348 06:48:28.636119 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8349 06:48:28.639543 Pre-setting of DQS Precalculation
8350 06:48:28.646005 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8351 06:48:28.646089 ==
8352 06:48:28.649333 Dram Type= 6, Freq= 0, CH_1, rank 0
8353 06:48:28.652759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8354 06:48:28.652849 ==
8355 06:48:28.659511 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8356 06:48:28.662555 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8357 06:48:28.666176 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8358 06:48:28.672541 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8359 06:48:28.680947 [CA 0] Center 41 (12~71) winsize 60
8360 06:48:28.684323 [CA 1] Center 42 (13~72) winsize 60
8361 06:48:28.687670 [CA 2] Center 37 (9~66) winsize 58
8362 06:48:28.690950 [CA 3] Center 36 (7~66) winsize 60
8363 06:48:28.694265 [CA 4] Center 37 (8~66) winsize 59
8364 06:48:28.697998 [CA 5] Center 36 (7~66) winsize 60
8365 06:48:28.698235
8366 06:48:28.700886 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8367 06:48:28.701120
8368 06:48:28.704316 [CATrainingPosCal] consider 1 rank data
8369 06:48:28.707737 u2DelayCellTimex100 = 258/100 ps
8370 06:48:28.711208 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8371 06:48:28.717749 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8372 06:48:28.720854 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8373 06:48:28.724322 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8374 06:48:28.727721 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8375 06:48:28.731197 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8376 06:48:28.731607
8377 06:48:28.734281 CA PerBit enable=1, Macro0, CA PI delay=36
8378 06:48:28.734693
8379 06:48:28.737647 [CBTSetCACLKResult] CA Dly = 36
8380 06:48:28.741146 CS Dly: 9 (0~40)
8381 06:48:28.744286 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8382 06:48:28.747675 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8383 06:48:28.748086 ==
8384 06:48:28.750958 Dram Type= 6, Freq= 0, CH_1, rank 1
8385 06:48:28.754132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8386 06:48:28.757454 ==
8387 06:48:28.761056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8388 06:48:28.764254 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8389 06:48:28.770958 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8390 06:48:28.773984 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8391 06:48:28.784476 [CA 0] Center 42 (13~72) winsize 60
8392 06:48:28.787748 [CA 1] Center 42 (12~72) winsize 61
8393 06:48:28.790961 [CA 2] Center 37 (8~67) winsize 60
8394 06:48:28.794247 [CA 3] Center 36 (7~66) winsize 60
8395 06:48:28.797938 [CA 4] Center 37 (8~67) winsize 60
8396 06:48:28.801127 [CA 5] Center 36 (6~66) winsize 61
8397 06:48:28.801583
8398 06:48:28.804341 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8399 06:48:28.804766
8400 06:48:28.807547 [CATrainingPosCal] consider 2 rank data
8401 06:48:28.810897 u2DelayCellTimex100 = 258/100 ps
8402 06:48:28.814406 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8403 06:48:28.820903 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8404 06:48:28.824175 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8405 06:48:28.827558 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8406 06:48:28.830844 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8407 06:48:28.834006 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8408 06:48:28.834418
8409 06:48:28.837520 CA PerBit enable=1, Macro0, CA PI delay=36
8410 06:48:28.837935
8411 06:48:28.840677 [CBTSetCACLKResult] CA Dly = 36
8412 06:48:28.844329 CS Dly: 11 (0~44)
8413 06:48:28.847216 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8414 06:48:28.850603 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8415 06:48:28.851013
8416 06:48:28.854029 ----->DramcWriteLeveling(PI) begin...
8417 06:48:28.854443 ==
8418 06:48:28.857434 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 06:48:28.864201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 06:48:28.864612 ==
8421 06:48:28.867293 Write leveling (Byte 0): 24 => 24
8422 06:48:28.867708 Write leveling (Byte 1): 28 => 28
8423 06:48:28.870701 DramcWriteLeveling(PI) end<-----
8424 06:48:28.871111
8425 06:48:28.871435 ==
8426 06:48:28.874032 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 06:48:28.880550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 06:48:28.880964 ==
8429 06:48:28.883892 [Gating] SW mode calibration
8430 06:48:28.890531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8431 06:48:28.893881 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8432 06:48:28.900584 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 06:48:28.903874 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 06:48:28.907126 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 06:48:28.913670 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 06:48:28.917127 1 4 16 | B1->B0 | 3232 3232 | 0 1 | (0 0) (1 1)
8437 06:48:28.920514 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8438 06:48:28.927174 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8439 06:48:28.930305 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 06:48:28.933621 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 06:48:28.940267 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 06:48:28.943547 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 06:48:28.946672 1 5 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
8444 06:48:28.953570 1 5 16 | B1->B0 | 2828 2525 | 0 0 | (1 0) (1 0)
8445 06:48:28.956682 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8446 06:48:28.959940 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 06:48:28.966802 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 06:48:28.969836 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 06:48:28.973140 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 06:48:28.979999 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 06:48:28.983085 1 6 12 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
8452 06:48:28.986493 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8453 06:48:28.992956 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 06:48:28.996378 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 06:48:28.999457 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 06:48:29.006415 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 06:48:29.009533 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 06:48:29.012960 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 06:48:29.019438 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 06:48:29.023010 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8461 06:48:29.026290 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8462 06:48:29.032765 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 06:48:29.036114 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 06:48:29.039389 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 06:48:29.042690 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 06:48:29.049137 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 06:48:29.052326 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 06:48:29.055782 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 06:48:29.062382 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 06:48:29.065753 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 06:48:29.068931 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 06:48:29.075601 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 06:48:29.078984 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 06:48:29.085614 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 06:48:29.088681 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 06:48:29.091984 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8477 06:48:29.095230 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8478 06:48:29.098479 Total UI for P1: 0, mck2ui 16
8479 06:48:29.101809 best dqsien dly found for B0: ( 1, 9, 16)
8480 06:48:29.108445 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8481 06:48:29.111951 Total UI for P1: 0, mck2ui 16
8482 06:48:29.115252 best dqsien dly found for B1: ( 1, 9, 20)
8483 06:48:29.118539 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8484 06:48:29.121760 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8485 06:48:29.122205
8486 06:48:29.125181 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8487 06:48:29.128479 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8488 06:48:29.131859 [Gating] SW calibration Done
8489 06:48:29.132270 ==
8490 06:48:29.135350 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 06:48:29.138392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 06:48:29.138825 ==
8493 06:48:29.142005 RX Vref Scan: 0
8494 06:48:29.142422
8495 06:48:29.145300 RX Vref 0 -> 0, step: 1
8496 06:48:29.145750
8497 06:48:29.146086 RX Delay 0 -> 252, step: 8
8498 06:48:29.151755 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8499 06:48:29.155178 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8500 06:48:29.158387 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8501 06:48:29.161383 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8502 06:48:29.164764 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8503 06:48:29.171228 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8504 06:48:29.174521 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8505 06:48:29.178229 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8506 06:48:29.181393 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8507 06:48:29.184518 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8508 06:48:29.191109 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8509 06:48:29.194566 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8510 06:48:29.197951 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8511 06:48:29.201311 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8512 06:48:29.207746 iDelay=208, Bit 14, Center 131 (80 ~ 183) 104
8513 06:48:29.210983 iDelay=208, Bit 15, Center 131 (72 ~ 191) 120
8514 06:48:29.211423 ==
8515 06:48:29.214507 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 06:48:29.217222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 06:48:29.217303 ==
8518 06:48:29.217367 DQS Delay:
8519 06:48:29.220889 DQS0 = 0, DQS1 = 0
8520 06:48:29.220970 DQM Delay:
8521 06:48:29.224018 DQM0 = 133, DQM1 = 124
8522 06:48:29.224099 DQ Delay:
8523 06:48:29.227313 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8524 06:48:29.230491 DQ4 =127, DQ5 =147, DQ6 =147, DQ7 =131
8525 06:48:29.233800 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8526 06:48:29.240571 DQ12 =135, DQ13 =131, DQ14 =131, DQ15 =131
8527 06:48:29.240653
8528 06:48:29.240718
8529 06:48:29.240776 ==
8530 06:48:29.243759 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 06:48:29.246944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 06:48:29.247026 ==
8533 06:48:29.247091
8534 06:48:29.247151
8535 06:48:29.250515 TX Vref Scan disable
8536 06:48:29.250596 == TX Byte 0 ==
8537 06:48:29.257115 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8538 06:48:29.260403 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8539 06:48:29.260484 == TX Byte 1 ==
8540 06:48:29.267126 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8541 06:48:29.270365 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8542 06:48:29.270445 ==
8543 06:48:29.273588 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 06:48:29.276890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 06:48:29.276972 ==
8546 06:48:29.291723
8547 06:48:29.295550 TX Vref early break, caculate TX vref
8548 06:48:29.298854 TX Vref=16, minBit 5, minWin=21, winSum=354
8549 06:48:29.301962 TX Vref=18, minBit 3, minWin=22, winSum=364
8550 06:48:29.305096 TX Vref=20, minBit 0, minWin=23, winSum=377
8551 06:48:29.308578 TX Vref=22, minBit 4, minWin=23, winSum=390
8552 06:48:29.312037 TX Vref=24, minBit 0, minWin=24, winSum=399
8553 06:48:29.318452 TX Vref=26, minBit 14, minWin=24, winSum=410
8554 06:48:29.321753 TX Vref=28, minBit 1, minWin=24, winSum=415
8555 06:48:29.324969 TX Vref=30, minBit 0, minWin=24, winSum=411
8556 06:48:29.328488 TX Vref=32, minBit 1, minWin=24, winSum=407
8557 06:48:29.331657 TX Vref=34, minBit 0, minWin=23, winSum=399
8558 06:48:29.334910 TX Vref=36, minBit 0, minWin=23, winSum=389
8559 06:48:29.341822 [TxChooseVref] Worse bit 1, Min win 24, Win sum 415, Final Vref 28
8560 06:48:29.341906
8561 06:48:29.345014 Final TX Range 0 Vref 28
8562 06:48:29.345096
8563 06:48:29.345160 ==
8564 06:48:29.348428 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 06:48:29.351589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 06:48:29.351670 ==
8567 06:48:29.351735
8568 06:48:29.354673
8569 06:48:29.354754 TX Vref Scan disable
8570 06:48:29.361615 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8571 06:48:29.361696 == TX Byte 0 ==
8572 06:48:29.364956 u2DelayCellOfst[0]=22 cells (6 PI)
8573 06:48:29.368223 u2DelayCellOfst[1]=18 cells (5 PI)
8574 06:48:29.371771 u2DelayCellOfst[2]=0 cells (0 PI)
8575 06:48:29.375068 u2DelayCellOfst[3]=7 cells (2 PI)
8576 06:48:29.378260 u2DelayCellOfst[4]=7 cells (2 PI)
8577 06:48:29.381499 u2DelayCellOfst[5]=22 cells (6 PI)
8578 06:48:29.384857 u2DelayCellOfst[6]=22 cells (6 PI)
8579 06:48:29.388120 u2DelayCellOfst[7]=7 cells (2 PI)
8580 06:48:29.391609 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8581 06:48:29.394893 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8582 06:48:29.398242 == TX Byte 1 ==
8583 06:48:29.401401 u2DelayCellOfst[8]=0 cells (0 PI)
8584 06:48:29.401532 u2DelayCellOfst[9]=7 cells (2 PI)
8585 06:48:29.404772 u2DelayCellOfst[10]=15 cells (4 PI)
8586 06:48:29.408161 u2DelayCellOfst[11]=7 cells (2 PI)
8587 06:48:29.411198 u2DelayCellOfst[12]=18 cells (5 PI)
8588 06:48:29.414869 u2DelayCellOfst[13]=22 cells (6 PI)
8589 06:48:29.417943 u2DelayCellOfst[14]=22 cells (6 PI)
8590 06:48:29.421589 u2DelayCellOfst[15]=22 cells (6 PI)
8591 06:48:29.424735 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8592 06:48:29.431461 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8593 06:48:29.431544 DramC Write-DBI on
8594 06:48:29.431609 ==
8595 06:48:29.434863 Dram Type= 6, Freq= 0, CH_1, rank 0
8596 06:48:29.441295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8597 06:48:29.441383 ==
8598 06:48:29.441501
8599 06:48:29.441578
8600 06:48:29.441636 TX Vref Scan disable
8601 06:48:29.445174 == TX Byte 0 ==
8602 06:48:29.448469 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8603 06:48:29.451616 == TX Byte 1 ==
8604 06:48:29.455090 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8605 06:48:29.458226 DramC Write-DBI off
8606 06:48:29.458307
8607 06:48:29.458371 [DATLAT]
8608 06:48:29.458430 Freq=1600, CH1 RK0
8609 06:48:29.458488
8610 06:48:29.461424 DATLAT Default: 0xf
8611 06:48:29.464714 0, 0xFFFF, sum = 0
8612 06:48:29.464797 1, 0xFFFF, sum = 0
8613 06:48:29.468140 2, 0xFFFF, sum = 0
8614 06:48:29.468228 3, 0xFFFF, sum = 0
8615 06:48:29.471275 4, 0xFFFF, sum = 0
8616 06:48:29.471364 5, 0xFFFF, sum = 0
8617 06:48:29.474624 6, 0xFFFF, sum = 0
8618 06:48:29.474718 7, 0xFFFF, sum = 0
8619 06:48:29.478239 8, 0xFFFF, sum = 0
8620 06:48:29.478341 9, 0xFFFF, sum = 0
8621 06:48:29.481366 10, 0xFFFF, sum = 0
8622 06:48:29.481468 11, 0xFFFF, sum = 0
8623 06:48:29.484945 12, 0xFFFF, sum = 0
8624 06:48:29.485057 13, 0x8FFF, sum = 0
8625 06:48:29.487767 14, 0x0, sum = 1
8626 06:48:29.487932 15, 0x0, sum = 2
8627 06:48:29.490952 16, 0x0, sum = 3
8628 06:48:29.491074 17, 0x0, sum = 4
8629 06:48:29.494502 best_step = 15
8630 06:48:29.494636
8631 06:48:29.494743 ==
8632 06:48:29.497848 Dram Type= 6, Freq= 0, CH_1, rank 0
8633 06:48:29.501056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8634 06:48:29.501208 ==
8635 06:48:29.504362 RX Vref Scan: 1
8636 06:48:29.504533
8637 06:48:29.504670 Set Vref Range= 24 -> 127
8638 06:48:29.504797
8639 06:48:29.507784 RX Vref 24 -> 127, step: 1
8640 06:48:29.507983
8641 06:48:29.511043 RX Delay 11 -> 252, step: 4
8642 06:48:29.511242
8643 06:48:29.514331 Set Vref, RX VrefLevel [Byte0]: 24
8644 06:48:29.518038 [Byte1]: 24
8645 06:48:29.518339
8646 06:48:29.521290 Set Vref, RX VrefLevel [Byte0]: 25
8647 06:48:29.524640 [Byte1]: 25
8648 06:48:29.528323
8649 06:48:29.528868 Set Vref, RX VrefLevel [Byte0]: 26
8650 06:48:29.531727 [Byte1]: 26
8651 06:48:29.536176
8652 06:48:29.536869 Set Vref, RX VrefLevel [Byte0]: 27
8653 06:48:29.539415 [Byte1]: 27
8654 06:48:29.543709
8655 06:48:29.544194 Set Vref, RX VrefLevel [Byte0]: 28
8656 06:48:29.547008 [Byte1]: 28
8657 06:48:29.551187
8658 06:48:29.551766 Set Vref, RX VrefLevel [Byte0]: 29
8659 06:48:29.554444 [Byte1]: 29
8660 06:48:29.558794
8661 06:48:29.559247 Set Vref, RX VrefLevel [Byte0]: 30
8662 06:48:29.562060 [Byte1]: 30
8663 06:48:29.566325
8664 06:48:29.566821 Set Vref, RX VrefLevel [Byte0]: 31
8665 06:48:29.569884 [Byte1]: 31
8666 06:48:29.574208
8667 06:48:29.574701 Set Vref, RX VrefLevel [Byte0]: 32
8668 06:48:29.577415 [Byte1]: 32
8669 06:48:29.581544
8670 06:48:29.581999 Set Vref, RX VrefLevel [Byte0]: 33
8671 06:48:29.584802 [Byte1]: 33
8672 06:48:29.589303
8673 06:48:29.589882 Set Vref, RX VrefLevel [Byte0]: 34
8674 06:48:29.592512 [Byte1]: 34
8675 06:48:29.596742
8676 06:48:29.597152 Set Vref, RX VrefLevel [Byte0]: 35
8677 06:48:29.600225 [Byte1]: 35
8678 06:48:29.604485
8679 06:48:29.604894 Set Vref, RX VrefLevel [Byte0]: 36
8680 06:48:29.607765 [Byte1]: 36
8681 06:48:29.612257
8682 06:48:29.612666 Set Vref, RX VrefLevel [Byte0]: 37
8683 06:48:29.615639 [Byte1]: 37
8684 06:48:29.619557
8685 06:48:29.619966 Set Vref, RX VrefLevel [Byte0]: 38
8686 06:48:29.622896 [Byte1]: 38
8687 06:48:29.627130
8688 06:48:29.627539 Set Vref, RX VrefLevel [Byte0]: 39
8689 06:48:29.630532 [Byte1]: 39
8690 06:48:29.634943
8691 06:48:29.635406 Set Vref, RX VrefLevel [Byte0]: 40
8692 06:48:29.638175 [Byte1]: 40
8693 06:48:29.642628
8694 06:48:29.643078 Set Vref, RX VrefLevel [Byte0]: 41
8695 06:48:29.645816 [Byte1]: 41
8696 06:48:29.650006
8697 06:48:29.650416 Set Vref, RX VrefLevel [Byte0]: 42
8698 06:48:29.653274 [Byte1]: 42
8699 06:48:29.657718
8700 06:48:29.658169 Set Vref, RX VrefLevel [Byte0]: 43
8701 06:48:29.661180 [Byte1]: 43
8702 06:48:29.665363
8703 06:48:29.665855 Set Vref, RX VrefLevel [Byte0]: 44
8704 06:48:29.668483 [Byte1]: 44
8705 06:48:29.672938
8706 06:48:29.673348 Set Vref, RX VrefLevel [Byte0]: 45
8707 06:48:29.676141 [Byte1]: 45
8708 06:48:29.680351
8709 06:48:29.680801 Set Vref, RX VrefLevel [Byte0]: 46
8710 06:48:29.683609 [Byte1]: 46
8711 06:48:29.688504
8712 06:48:29.689050 Set Vref, RX VrefLevel [Byte0]: 47
8713 06:48:29.691403 [Byte1]: 47
8714 06:48:29.695786
8715 06:48:29.696222 Set Vref, RX VrefLevel [Byte0]: 48
8716 06:48:29.698926 [Byte1]: 48
8717 06:48:29.703411
8718 06:48:29.703817 Set Vref, RX VrefLevel [Byte0]: 49
8719 06:48:29.706528 [Byte1]: 49
8720 06:48:29.710910
8721 06:48:29.711345 Set Vref, RX VrefLevel [Byte0]: 50
8722 06:48:29.714318 [Byte1]: 50
8723 06:48:29.718686
8724 06:48:29.719101 Set Vref, RX VrefLevel [Byte0]: 51
8725 06:48:29.721907 [Byte1]: 51
8726 06:48:29.725989
8727 06:48:29.726404 Set Vref, RX VrefLevel [Byte0]: 52
8728 06:48:29.729335 [Byte1]: 52
8729 06:48:29.733809
8730 06:48:29.734289 Set Vref, RX VrefLevel [Byte0]: 53
8731 06:48:29.736909 [Byte1]: 53
8732 06:48:29.741422
8733 06:48:29.742035 Set Vref, RX VrefLevel [Byte0]: 54
8734 06:48:29.744639 [Byte1]: 54
8735 06:48:29.749149
8736 06:48:29.749776 Set Vref, RX VrefLevel [Byte0]: 55
8737 06:48:29.751991 [Byte1]: 55
8738 06:48:29.756630
8739 06:48:29.757166 Set Vref, RX VrefLevel [Byte0]: 56
8740 06:48:29.759566 [Byte1]: 56
8741 06:48:29.764092
8742 06:48:29.764605 Set Vref, RX VrefLevel [Byte0]: 57
8743 06:48:29.767338 [Byte1]: 57
8744 06:48:29.771713
8745 06:48:29.772149 Set Vref, RX VrefLevel [Byte0]: 58
8746 06:48:29.774920 [Byte1]: 58
8747 06:48:29.779525
8748 06:48:29.779943 Set Vref, RX VrefLevel [Byte0]: 59
8749 06:48:29.782882 [Byte1]: 59
8750 06:48:29.787067
8751 06:48:29.787514 Set Vref, RX VrefLevel [Byte0]: 60
8752 06:48:29.790355 [Byte1]: 60
8753 06:48:29.794556
8754 06:48:29.795133 Set Vref, RX VrefLevel [Byte0]: 61
8755 06:48:29.797804 [Byte1]: 61
8756 06:48:29.802141
8757 06:48:29.802567 Set Vref, RX VrefLevel [Byte0]: 62
8758 06:48:29.805306 [Byte1]: 62
8759 06:48:29.809750
8760 06:48:29.810183 Set Vref, RX VrefLevel [Byte0]: 63
8761 06:48:29.813270 [Byte1]: 63
8762 06:48:29.817533
8763 06:48:29.817959 Set Vref, RX VrefLevel [Byte0]: 64
8764 06:48:29.820592 [Byte1]: 64
8765 06:48:29.824868
8766 06:48:29.825283 Set Vref, RX VrefLevel [Byte0]: 65
8767 06:48:29.828321 [Byte1]: 65
8768 06:48:29.832763
8769 06:48:29.833226 Set Vref, RX VrefLevel [Byte0]: 66
8770 06:48:29.835773 [Byte1]: 66
8771 06:48:29.839937
8772 06:48:29.840019 Set Vref, RX VrefLevel [Byte0]: 67
8773 06:48:29.843226 [Byte1]: 67
8774 06:48:29.847759
8775 06:48:29.847840 Set Vref, RX VrefLevel [Byte0]: 68
8776 06:48:29.850965 [Byte1]: 68
8777 06:48:29.855149
8778 06:48:29.855230 Set Vref, RX VrefLevel [Byte0]: 69
8779 06:48:29.858513 [Byte1]: 69
8780 06:48:29.862911
8781 06:48:29.862991 Set Vref, RX VrefLevel [Byte0]: 70
8782 06:48:29.866305 [Byte1]: 70
8783 06:48:29.870400
8784 06:48:29.870482 Set Vref, RX VrefLevel [Byte0]: 71
8785 06:48:29.873605 [Byte1]: 71
8786 06:48:29.878180
8787 06:48:29.878263 Final RX Vref Byte 0 = 56 to rank0
8788 06:48:29.881486 Final RX Vref Byte 1 = 55 to rank0
8789 06:48:29.884971 Final RX Vref Byte 0 = 56 to rank1
8790 06:48:29.887770 Final RX Vref Byte 1 = 55 to rank1==
8791 06:48:29.891022 Dram Type= 6, Freq= 0, CH_1, rank 0
8792 06:48:29.897712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 06:48:29.897794 ==
8794 06:48:29.897859 DQS Delay:
8795 06:48:29.900927 DQS0 = 0, DQS1 = 0
8796 06:48:29.901010 DQM Delay:
8797 06:48:29.901082 DQM0 = 131, DQM1 = 122
8798 06:48:29.904391 DQ Delay:
8799 06:48:29.907501 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8800 06:48:29.910894 DQ4 =130, DQ5 =140, DQ6 =142, DQ7 =128
8801 06:48:29.914133 DQ8 =108, DQ9 =112, DQ10 =120, DQ11 =114
8802 06:48:29.917376 DQ12 =132, DQ13 =130, DQ14 =130, DQ15 =130
8803 06:48:29.917496
8804 06:48:29.917564
8805 06:48:29.917628
8806 06:48:29.920996 [DramC_TX_OE_Calibration] TA2
8807 06:48:29.924170 Original DQ_B0 (3 6) =30, OEN = 27
8808 06:48:29.927655 Original DQ_B1 (3 6) =30, OEN = 27
8809 06:48:29.930873 24, 0x0, End_B0=24 End_B1=24
8810 06:48:29.930955 25, 0x0, End_B0=25 End_B1=25
8811 06:48:29.934094 26, 0x0, End_B0=26 End_B1=26
8812 06:48:29.937315 27, 0x0, End_B0=27 End_B1=27
8813 06:48:29.940580 28, 0x0, End_B0=28 End_B1=28
8814 06:48:29.943978 29, 0x0, End_B0=29 End_B1=29
8815 06:48:29.944061 30, 0x0, End_B0=30 End_B1=30
8816 06:48:29.947328 31, 0x4141, End_B0=30 End_B1=30
8817 06:48:29.950691 Byte0 end_step=30 best_step=27
8818 06:48:29.953962 Byte1 end_step=30 best_step=27
8819 06:48:29.957344 Byte0 TX OE(2T, 0.5T) = (3, 3)
8820 06:48:29.960774 Byte1 TX OE(2T, 0.5T) = (3, 3)
8821 06:48:29.960848
8822 06:48:29.960911
8823 06:48:29.967464 [DQSOSCAuto] RK0, (LSB)MR18= 0xc10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
8824 06:48:29.970446 CH1 RK0: MR19=303, MR18=C10
8825 06:48:29.977021 CH1_RK0: MR19=0x303, MR18=0xC10, DQSOSC=401, MR23=63, INC=22, DEC=15
8826 06:48:29.977100
8827 06:48:29.980701 ----->DramcWriteLeveling(PI) begin...
8828 06:48:29.980774 ==
8829 06:48:29.983967 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 06:48:29.987237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 06:48:29.987311 ==
8832 06:48:29.990366 Write leveling (Byte 0): 23 => 23
8833 06:48:29.993666 Write leveling (Byte 1): 26 => 26
8834 06:48:29.996933 DramcWriteLeveling(PI) end<-----
8835 06:48:29.997007
8836 06:48:29.997068 ==
8837 06:48:30.000260 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 06:48:30.003843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 06:48:30.003921 ==
8840 06:48:30.007193 [Gating] SW mode calibration
8841 06:48:30.013872 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8842 06:48:30.020521 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8843 06:48:30.023601 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 06:48:30.026989 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8845 06:48:30.033821 1 4 8 | B1->B0 | 2322 3434 | 1 1 | (1 0) (1 1)
8846 06:48:30.037143 1 4 12 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
8847 06:48:30.040457 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8848 06:48:30.046996 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8849 06:48:30.050339 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 06:48:30.053426 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 06:48:30.060364 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 06:48:30.063695 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 06:48:30.067293 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8854 06:48:30.073785 1 5 12 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (1 0)
8855 06:48:30.077100 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 06:48:30.080489 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 06:48:30.086945 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 06:48:30.090279 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 06:48:30.093738 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 06:48:30.100128 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8861 06:48:30.103499 1 6 8 | B1->B0 | 2323 4343 | 0 1 | (0 0) (1 1)
8862 06:48:30.106644 1 6 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8863 06:48:30.113586 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 06:48:30.117023 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 06:48:30.120331 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 06:48:30.126695 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 06:48:30.129989 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 06:48:30.133550 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 06:48:30.139948 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8870 06:48:30.143427 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8871 06:48:30.146535 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 06:48:30.153266 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 06:48:30.156551 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 06:48:30.160070 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 06:48:30.163037 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 06:48:30.169752 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 06:48:30.173163 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 06:48:30.176412 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 06:48:30.183420 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 06:48:30.186702 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 06:48:30.189984 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 06:48:30.196561 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 06:48:30.200096 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 06:48:30.203028 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 06:48:30.209791 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8886 06:48:30.213266 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8887 06:48:30.216320 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8888 06:48:30.219629 Total UI for P1: 0, mck2ui 16
8889 06:48:30.223073 best dqsien dly found for B0: ( 1, 9, 10)
8890 06:48:30.226501 Total UI for P1: 0, mck2ui 16
8891 06:48:30.229887 best dqsien dly found for B1: ( 1, 9, 10)
8892 06:48:30.233121 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8893 06:48:30.236501 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8894 06:48:30.236602
8895 06:48:30.243149 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8896 06:48:30.246530 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8897 06:48:30.246690 [Gating] SW calibration Done
8898 06:48:30.249833 ==
8899 06:48:30.253064 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 06:48:30.256361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 06:48:30.256441 ==
8902 06:48:30.256505 RX Vref Scan: 0
8903 06:48:30.256564
8904 06:48:30.259790 RX Vref 0 -> 0, step: 1
8905 06:48:30.259870
8906 06:48:30.263180 RX Delay 0 -> 252, step: 8
8907 06:48:30.266134 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8908 06:48:30.269418 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8909 06:48:30.272790 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8910 06:48:30.279456 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8911 06:48:30.282828 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8912 06:48:30.286186 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8913 06:48:30.289324 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8914 06:48:30.292819 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8915 06:48:30.299409 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8916 06:48:30.302763 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8917 06:48:30.306034 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8918 06:48:30.309627 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8919 06:48:30.312753 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8920 06:48:30.319346 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8921 06:48:30.322397 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8922 06:48:30.326021 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8923 06:48:30.326127 ==
8924 06:48:30.329018 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 06:48:30.335775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 06:48:30.335871 ==
8927 06:48:30.335959 DQS Delay:
8928 06:48:30.336050 DQS0 = 0, DQS1 = 0
8929 06:48:30.339119 DQM Delay:
8930 06:48:30.339199 DQM0 = 129, DQM1 = 128
8931 06:48:30.342520 DQ Delay:
8932 06:48:30.345881 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8933 06:48:30.348854 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8934 06:48:30.352265 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8935 06:48:30.355516 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8936 06:48:30.355586
8937 06:48:30.355646
8938 06:48:30.355701 ==
8939 06:48:30.358781 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 06:48:30.362256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 06:48:30.365571 ==
8942 06:48:30.365644
8943 06:48:30.365707
8944 06:48:30.365764 TX Vref Scan disable
8945 06:48:30.368925 == TX Byte 0 ==
8946 06:48:30.372184 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8947 06:48:30.375361 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8948 06:48:30.378654 == TX Byte 1 ==
8949 06:48:30.381983 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8950 06:48:30.385377 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8951 06:48:30.388737 ==
8952 06:48:30.392047 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 06:48:30.395022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 06:48:30.395096 ==
8955 06:48:30.407155
8956 06:48:30.410861 TX Vref early break, caculate TX vref
8957 06:48:30.413843 TX Vref=16, minBit 0, minWin=21, winSum=375
8958 06:48:30.417165 TX Vref=18, minBit 0, minWin=22, winSum=388
8959 06:48:30.420460 TX Vref=20, minBit 0, minWin=23, winSum=395
8960 06:48:30.424114 TX Vref=22, minBit 0, minWin=24, winSum=407
8961 06:48:30.427099 TX Vref=24, minBit 0, minWin=24, winSum=415
8962 06:48:30.433979 TX Vref=26, minBit 0, minWin=23, winSum=417
8963 06:48:30.437268 TX Vref=28, minBit 0, minWin=24, winSum=420
8964 06:48:30.440669 TX Vref=30, minBit 0, minWin=24, winSum=413
8965 06:48:30.443966 TX Vref=32, minBit 1, minWin=24, winSum=412
8966 06:48:30.447306 TX Vref=34, minBit 0, minWin=23, winSum=397
8967 06:48:30.454072 [TxChooseVref] Worse bit 0, Min win 24, Win sum 420, Final Vref 28
8968 06:48:30.454152
8969 06:48:30.457366 Final TX Range 0 Vref 28
8970 06:48:30.457514
8971 06:48:30.457647 ==
8972 06:48:30.460456 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 06:48:30.463948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 06:48:30.464028 ==
8975 06:48:30.464101
8976 06:48:30.464159
8977 06:48:30.466917 TX Vref Scan disable
8978 06:48:30.473706 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8979 06:48:30.473788 == TX Byte 0 ==
8980 06:48:30.477048 u2DelayCellOfst[0]=18 cells (5 PI)
8981 06:48:30.480323 u2DelayCellOfst[1]=15 cells (4 PI)
8982 06:48:30.483813 u2DelayCellOfst[2]=0 cells (0 PI)
8983 06:48:30.487046 u2DelayCellOfst[3]=7 cells (2 PI)
8984 06:48:30.490492 u2DelayCellOfst[4]=7 cells (2 PI)
8985 06:48:30.493887 u2DelayCellOfst[5]=26 cells (7 PI)
8986 06:48:30.497208 u2DelayCellOfst[6]=22 cells (6 PI)
8987 06:48:30.497289 u2DelayCellOfst[7]=7 cells (2 PI)
8988 06:48:30.503761 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8989 06:48:30.507082 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8990 06:48:30.507164 == TX Byte 1 ==
8991 06:48:30.510408 u2DelayCellOfst[8]=0 cells (0 PI)
8992 06:48:30.513879 u2DelayCellOfst[9]=3 cells (1 PI)
8993 06:48:30.517100 u2DelayCellOfst[10]=15 cells (4 PI)
8994 06:48:30.520356 u2DelayCellOfst[11]=7 cells (2 PI)
8995 06:48:30.523712 u2DelayCellOfst[12]=18 cells (5 PI)
8996 06:48:30.526727 u2DelayCellOfst[13]=18 cells (5 PI)
8997 06:48:30.530007 u2DelayCellOfst[14]=22 cells (6 PI)
8998 06:48:30.533279 u2DelayCellOfst[15]=18 cells (5 PI)
8999 06:48:30.536882 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9000 06:48:30.543294 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9001 06:48:30.543379 DramC Write-DBI on
9002 06:48:30.543443 ==
9003 06:48:30.546657 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 06:48:30.550013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 06:48:30.553202 ==
9006 06:48:30.553276
9007 06:48:30.553345
9008 06:48:30.553403 TX Vref Scan disable
9009 06:48:30.556634 == TX Byte 0 ==
9010 06:48:30.560081 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9011 06:48:30.563531 == TX Byte 1 ==
9012 06:48:30.566436 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9013 06:48:30.569925 DramC Write-DBI off
9014 06:48:30.570005
9015 06:48:30.570069 [DATLAT]
9016 06:48:30.570127 Freq=1600, CH1 RK1
9017 06:48:30.570215
9018 06:48:30.573032 DATLAT Default: 0xf
9019 06:48:30.573114 0, 0xFFFF, sum = 0
9020 06:48:30.576525 1, 0xFFFF, sum = 0
9021 06:48:30.579883 2, 0xFFFF, sum = 0
9022 06:48:30.579964 3, 0xFFFF, sum = 0
9023 06:48:30.582945 4, 0xFFFF, sum = 0
9024 06:48:30.583026 5, 0xFFFF, sum = 0
9025 06:48:30.586275 6, 0xFFFF, sum = 0
9026 06:48:30.586356 7, 0xFFFF, sum = 0
9027 06:48:30.589721 8, 0xFFFF, sum = 0
9028 06:48:30.589802 9, 0xFFFF, sum = 0
9029 06:48:30.593024 10, 0xFFFF, sum = 0
9030 06:48:30.593106 11, 0xFFFF, sum = 0
9031 06:48:30.596036 12, 0xFFFF, sum = 0
9032 06:48:30.596118 13, 0x8FFF, sum = 0
9033 06:48:30.599416 14, 0x0, sum = 1
9034 06:48:30.599497 15, 0x0, sum = 2
9035 06:48:30.602843 16, 0x0, sum = 3
9036 06:48:30.602924 17, 0x0, sum = 4
9037 06:48:30.606071 best_step = 15
9038 06:48:30.606176
9039 06:48:30.606267 ==
9040 06:48:30.609338 Dram Type= 6, Freq= 0, CH_1, rank 1
9041 06:48:30.612560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9042 06:48:30.612641 ==
9043 06:48:30.615898 RX Vref Scan: 0
9044 06:48:30.615978
9045 06:48:30.616041 RX Vref 0 -> 0, step: 1
9046 06:48:30.616100
9047 06:48:30.619476 RX Delay 11 -> 252, step: 4
9048 06:48:30.626122 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9049 06:48:30.629259 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9050 06:48:30.632544 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9051 06:48:30.635978 iDelay=195, Bit 3, Center 124 (67 ~ 182) 116
9052 06:48:30.639073 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9053 06:48:30.645866 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9054 06:48:30.648855 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9055 06:48:30.652382 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9056 06:48:30.655817 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
9057 06:48:30.659080 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9058 06:48:30.665669 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
9059 06:48:30.668939 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9060 06:48:30.672301 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9061 06:48:30.675500 iDelay=195, Bit 13, Center 130 (75 ~ 186) 112
9062 06:48:30.682082 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9063 06:48:30.685304 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9064 06:48:30.685384 ==
9065 06:48:30.688690 Dram Type= 6, Freq= 0, CH_1, rank 1
9066 06:48:30.691756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9067 06:48:30.691833 ==
9068 06:48:30.691896 DQS Delay:
9069 06:48:30.695205 DQS0 = 0, DQS1 = 0
9070 06:48:30.695277 DQM Delay:
9071 06:48:30.698506 DQM0 = 127, DQM1 = 124
9072 06:48:30.698582 DQ Delay:
9073 06:48:30.701882 DQ0 =132, DQ1 =124, DQ2 =114, DQ3 =124
9074 06:48:30.705349 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9075 06:48:30.708721 DQ8 =108, DQ9 =112, DQ10 =126, DQ11 =120
9076 06:48:30.714842 DQ12 =132, DQ13 =130, DQ14 =130, DQ15 =134
9077 06:48:30.714919
9078 06:48:30.714980
9079 06:48:30.715037
9080 06:48:30.718615 [DramC_TX_OE_Calibration] TA2
9081 06:48:30.718683 Original DQ_B0 (3 6) =30, OEN = 27
9082 06:48:30.721588 Original DQ_B1 (3 6) =30, OEN = 27
9083 06:48:30.725051 24, 0x0, End_B0=24 End_B1=24
9084 06:48:30.728528 25, 0x0, End_B0=25 End_B1=25
9085 06:48:30.731937 26, 0x0, End_B0=26 End_B1=26
9086 06:48:30.734865 27, 0x0, End_B0=27 End_B1=27
9087 06:48:30.734936 28, 0x0, End_B0=28 End_B1=28
9088 06:48:30.738186 29, 0x0, End_B0=29 End_B1=29
9089 06:48:30.741452 30, 0x0, End_B0=30 End_B1=30
9090 06:48:30.744908 31, 0x4141, End_B0=30 End_B1=30
9091 06:48:30.747881 Byte0 end_step=30 best_step=27
9092 06:48:30.747961 Byte1 end_step=30 best_step=27
9093 06:48:30.751101 Byte0 TX OE(2T, 0.5T) = (3, 3)
9094 06:48:30.754528 Byte1 TX OE(2T, 0.5T) = (3, 3)
9095 06:48:30.754607
9096 06:48:30.754714
9097 06:48:30.764757 [DQSOSCAuto] RK1, (LSB)MR18= 0x1420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
9098 06:48:30.764835 CH1 RK1: MR19=303, MR18=1420
9099 06:48:30.770891 CH1_RK1: MR19=0x303, MR18=0x1420, DQSOSC=393, MR23=63, INC=23, DEC=15
9100 06:48:30.774215 [RxdqsGatingPostProcess] freq 1600
9101 06:48:30.780857 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9102 06:48:30.784410 best DQS0 dly(2T, 0.5T) = (1, 1)
9103 06:48:30.787679 best DQS1 dly(2T, 0.5T) = (1, 1)
9104 06:48:30.791214 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9105 06:48:30.794394 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9106 06:48:30.797413 best DQS0 dly(2T, 0.5T) = (1, 1)
9107 06:48:30.797554 best DQS1 dly(2T, 0.5T) = (1, 1)
9108 06:48:30.800832 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9109 06:48:30.804078 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9110 06:48:30.807478 Pre-setting of DQS Precalculation
9111 06:48:30.814174 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9112 06:48:30.820626 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9113 06:48:30.827460 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9114 06:48:30.827541
9115 06:48:30.827605
9116 06:48:30.830952 [Calibration Summary] 3200 Mbps
9117 06:48:30.831022 CH 0, Rank 0
9118 06:48:30.834044 SW Impedance : PASS
9119 06:48:30.837390 DUTY Scan : NO K
9120 06:48:30.837520 ZQ Calibration : PASS
9121 06:48:30.840860 Jitter Meter : NO K
9122 06:48:30.843802 CBT Training : PASS
9123 06:48:30.843911 Write leveling : PASS
9124 06:48:30.847197 RX DQS gating : PASS
9125 06:48:30.850533 RX DQ/DQS(RDDQC) : PASS
9126 06:48:30.850640 TX DQ/DQS : PASS
9127 06:48:30.853823 RX DATLAT : PASS
9128 06:48:30.857016 RX DQ/DQS(Engine): PASS
9129 06:48:30.857098 TX OE : PASS
9130 06:48:30.860559 All Pass.
9131 06:48:30.860665
9132 06:48:30.860757 CH 0, Rank 1
9133 06:48:30.863773 SW Impedance : PASS
9134 06:48:30.863844 DUTY Scan : NO K
9135 06:48:30.867257 ZQ Calibration : PASS
9136 06:48:30.870627 Jitter Meter : NO K
9137 06:48:30.870706 CBT Training : PASS
9138 06:48:30.873694 Write leveling : PASS
9139 06:48:30.877031 RX DQS gating : PASS
9140 06:48:30.877104 RX DQ/DQS(RDDQC) : PASS
9141 06:48:30.880259 TX DQ/DQS : PASS
9142 06:48:30.883554 RX DATLAT : PASS
9143 06:48:30.883626 RX DQ/DQS(Engine): PASS
9144 06:48:30.886911 TX OE : PASS
9145 06:48:30.886983 All Pass.
9146 06:48:30.887043
9147 06:48:30.890164 CH 1, Rank 0
9148 06:48:30.890260 SW Impedance : PASS
9149 06:48:30.893774 DUTY Scan : NO K
9150 06:48:30.896723 ZQ Calibration : PASS
9151 06:48:30.896805 Jitter Meter : NO K
9152 06:48:30.899963 CBT Training : PASS
9153 06:48:30.900060 Write leveling : PASS
9154 06:48:30.903422 RX DQS gating : PASS
9155 06:48:30.906488 RX DQ/DQS(RDDQC) : PASS
9156 06:48:30.906587 TX DQ/DQS : PASS
9157 06:48:30.909893 RX DATLAT : PASS
9158 06:48:30.913309 RX DQ/DQS(Engine): PASS
9159 06:48:30.913416 TX OE : PASS
9160 06:48:30.916783 All Pass.
9161 06:48:30.916864
9162 06:48:30.916928 CH 1, Rank 1
9163 06:48:30.920032 SW Impedance : PASS
9164 06:48:30.920111 DUTY Scan : NO K
9165 06:48:30.923333 ZQ Calibration : PASS
9166 06:48:30.926793 Jitter Meter : NO K
9167 06:48:30.926869 CBT Training : PASS
9168 06:48:30.929788 Write leveling : PASS
9169 06:48:30.933102 RX DQS gating : PASS
9170 06:48:30.933172 RX DQ/DQS(RDDQC) : PASS
9171 06:48:30.936464 TX DQ/DQS : PASS
9172 06:48:30.939829 RX DATLAT : PASS
9173 06:48:30.939904 RX DQ/DQS(Engine): PASS
9174 06:48:30.943101 TX OE : PASS
9175 06:48:30.943170 All Pass.
9176 06:48:30.943230
9177 06:48:30.946643 DramC Write-DBI on
9178 06:48:30.949900 PER_BANK_REFRESH: Hybrid Mode
9179 06:48:30.949980 TX_TRACKING: ON
9180 06:48:30.959865 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9181 06:48:30.966098 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9182 06:48:30.972738 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9183 06:48:30.976231 [FAST_K] Save calibration result to emmc
9184 06:48:30.979352 sync common calibartion params.
9185 06:48:30.982815 sync cbt_mode0:1, 1:1
9186 06:48:30.986022 dram_init: ddr_geometry: 2
9187 06:48:30.986095 dram_init: ddr_geometry: 2
9188 06:48:30.989381 dram_init: ddr_geometry: 2
9189 06:48:30.992722 0:dram_rank_size:100000000
9190 06:48:30.996096 1:dram_rank_size:100000000
9191 06:48:30.999464 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9192 06:48:31.002708 DFS_SHUFFLE_HW_MODE: ON
9193 06:48:31.005842 dramc_set_vcore_voltage set vcore to 725000
9194 06:48:31.008975 Read voltage for 1600, 0
9195 06:48:31.009080 Vio18 = 0
9196 06:48:31.009170 Vcore = 725000
9197 06:48:31.012312 Vdram = 0
9198 06:48:31.012419 Vddq = 0
9199 06:48:31.012510 Vmddr = 0
9200 06:48:31.015590 switch to 3200 Mbps bootup
9201 06:48:31.019019 [DramcRunTimeConfig]
9202 06:48:31.019098 PHYPLL
9203 06:48:31.019162 DPM_CONTROL_AFTERK: ON
9204 06:48:31.022457 PER_BANK_REFRESH: ON
9205 06:48:31.025658 REFRESH_OVERHEAD_REDUCTION: ON
9206 06:48:31.025732 CMD_PICG_NEW_MODE: OFF
9207 06:48:31.029021 XRTWTW_NEW_MODE: ON
9208 06:48:31.032319 XRTRTR_NEW_MODE: ON
9209 06:48:31.032387 TX_TRACKING: ON
9210 06:48:31.035568 RDSEL_TRACKING: OFF
9211 06:48:31.035678 DQS Precalculation for DVFS: ON
9212 06:48:31.039011 RX_TRACKING: OFF
9213 06:48:31.039122 HW_GATING DBG: ON
9214 06:48:31.042179 ZQCS_ENABLE_LP4: ON
9215 06:48:31.042260 RX_PICG_NEW_MODE: ON
9216 06:48:31.045661 TX_PICG_NEW_MODE: ON
9217 06:48:31.048909 ENABLE_RX_DCM_DPHY: ON
9218 06:48:31.052430 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9219 06:48:31.052516 DUMMY_READ_FOR_TRACKING: OFF
9220 06:48:31.055669 !!! SPM_CONTROL_AFTERK: OFF
9221 06:48:31.059020 !!! SPM could not control APHY
9222 06:48:31.062409 IMPEDANCE_TRACKING: ON
9223 06:48:31.062576 TEMP_SENSOR: ON
9224 06:48:31.065552 HW_SAVE_FOR_SR: OFF
9225 06:48:31.065744 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9226 06:48:31.072036 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9227 06:48:31.072156 Read ODT Tracking: ON
9228 06:48:31.075408 Refresh Rate DeBounce: ON
9229 06:48:31.078990 DFS_NO_QUEUE_FLUSH: ON
9230 06:48:31.079138 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9231 06:48:31.081999 ENABLE_DFS_RUNTIME_MRW: OFF
9232 06:48:31.085451 DDR_RESERVE_NEW_MODE: ON
9233 06:48:31.088749 MR_CBT_SWITCH_FREQ: ON
9234 06:48:31.088829 =========================
9235 06:48:31.108246 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9236 06:48:31.111544 dram_init: ddr_geometry: 2
9237 06:48:31.129845 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9238 06:48:31.133019 dram_init: dram init end (result: 0)
9239 06:48:31.139702 DRAM-K: Full calibration passed in 24591 msecs
9240 06:48:31.142978 MRC: failed to locate region type 0.
9241 06:48:31.143111 DRAM rank0 size:0x100000000,
9242 06:48:31.146363 DRAM rank1 size=0x100000000
9243 06:48:31.156416 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9244 06:48:31.162993 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9245 06:48:31.169586 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9246 06:48:31.176230 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9247 06:48:31.179509 DRAM rank0 size:0x100000000,
9248 06:48:31.182770 DRAM rank1 size=0x100000000
9249 06:48:31.183092 CBMEM:
9250 06:48:31.186181 IMD: root @ 0xfffff000 254 entries.
9251 06:48:31.189550 IMD: root @ 0xffffec00 62 entries.
9252 06:48:31.193026 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9253 06:48:31.199528 WARNING: RO_VPD is uninitialized or empty.
9254 06:48:31.202853 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9255 06:48:31.210018 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9256 06:48:31.222373 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9257 06:48:31.234114 BS: romstage times (exec / console): total (unknown) / 24052 ms
9258 06:48:31.234196
9259 06:48:31.234261
9260 06:48:31.243855 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9261 06:48:31.247211 ARM64: Exception handlers installed.
9262 06:48:31.250418 ARM64: Testing exception
9263 06:48:31.253792 ARM64: Done test exception
9264 06:48:31.253893 Enumerating buses...
9265 06:48:31.256858 Show all devs... Before device enumeration.
9266 06:48:31.260506 Root Device: enabled 1
9267 06:48:31.263549 CPU_CLUSTER: 0: enabled 1
9268 06:48:31.263624 CPU: 00: enabled 1
9269 06:48:31.267027 Compare with tree...
9270 06:48:31.267102 Root Device: enabled 1
9271 06:48:31.270415 CPU_CLUSTER: 0: enabled 1
9272 06:48:31.273644 CPU: 00: enabled 1
9273 06:48:31.273725 Root Device scanning...
9274 06:48:31.276811 scan_static_bus for Root Device
9275 06:48:31.279966 CPU_CLUSTER: 0 enabled
9276 06:48:31.283695 scan_static_bus for Root Device done
9277 06:48:31.286633 scan_bus: bus Root Device finished in 8 msecs
9278 06:48:31.286715 done
9279 06:48:31.293245 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9280 06:48:31.296742 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9281 06:48:31.303133 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9282 06:48:31.306490 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9283 06:48:31.309904 Allocating resources...
9284 06:48:31.313257 Reading resources...
9285 06:48:31.316606 Root Device read_resources bus 0 link: 0
9286 06:48:31.316687 DRAM rank0 size:0x100000000,
9287 06:48:31.320023 DRAM rank1 size=0x100000000
9288 06:48:31.323307 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9289 06:48:31.326581 CPU: 00 missing read_resources
9290 06:48:31.333340 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9291 06:48:31.336640 Root Device read_resources bus 0 link: 0 done
9292 06:48:31.336734 Done reading resources.
9293 06:48:31.343404 Show resources in subtree (Root Device)...After reading.
9294 06:48:31.346917 Root Device child on link 0 CPU_CLUSTER: 0
9295 06:48:31.349859 CPU_CLUSTER: 0 child on link 0 CPU: 00
9296 06:48:31.360092 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9297 06:48:31.360245 CPU: 00
9298 06:48:31.363516 Root Device assign_resources, bus 0 link: 0
9299 06:48:31.366794 CPU_CLUSTER: 0 missing set_resources
9300 06:48:31.373330 Root Device assign_resources, bus 0 link: 0 done
9301 06:48:31.373593 Done setting resources.
9302 06:48:31.380325 Show resources in subtree (Root Device)...After assigning values.
9303 06:48:31.383247 Root Device child on link 0 CPU_CLUSTER: 0
9304 06:48:31.386816 CPU_CLUSTER: 0 child on link 0 CPU: 00
9305 06:48:31.396749 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9306 06:48:31.397216 CPU: 00
9307 06:48:31.400004 Done allocating resources.
9308 06:48:31.406617 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9309 06:48:31.407118 Enabling resources...
9310 06:48:31.407516 done.
9311 06:48:31.413386 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9312 06:48:31.414045 Initializing devices...
9313 06:48:31.416563 Root Device init
9314 06:48:31.417018 init hardware done!
9315 06:48:31.420051 0x00000018: ctrlr->caps
9316 06:48:31.423335 52.000 MHz: ctrlr->f_max
9317 06:48:31.423804 0.400 MHz: ctrlr->f_min
9318 06:48:31.426674 0x40ff8080: ctrlr->voltages
9319 06:48:31.429839 sclk: 390625
9320 06:48:31.430286 Bus Width = 1
9321 06:48:31.430619 sclk: 390625
9322 06:48:31.433058 Bus Width = 1
9323 06:48:31.433510 Early init status = 3
9324 06:48:31.439955 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9325 06:48:31.443237 in-header: 03 fc 00 00 01 00 00 00
9326 06:48:31.443700 in-data: 00
9327 06:48:31.449855 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9328 06:48:31.453072 in-header: 03 fd 00 00 00 00 00 00
9329 06:48:31.456592 in-data:
9330 06:48:31.459564 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9331 06:48:31.463298 in-header: 03 fc 00 00 01 00 00 00
9332 06:48:31.466677 in-data: 00
9333 06:48:31.469914 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9334 06:48:31.474910 in-header: 03 fd 00 00 00 00 00 00
9335 06:48:31.478047 in-data:
9336 06:48:31.481380 [SSUSB] Setting up USB HOST controller...
9337 06:48:31.484793 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9338 06:48:31.488206 [SSUSB] phy power-on done.
9339 06:48:31.491189 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9340 06:48:31.497798 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9341 06:48:31.501365 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9342 06:48:31.507911 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9343 06:48:31.514541 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9344 06:48:31.521134 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9345 06:48:31.527578 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9346 06:48:31.534180 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9347 06:48:31.537759 SPM: binary array size = 0x9dc
9348 06:48:31.540997 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9349 06:48:31.547552 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9350 06:48:31.554152 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9351 06:48:31.560496 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9352 06:48:31.563757 configure_display: Starting display init
9353 06:48:31.597531 anx7625_power_on_init: Init interface.
9354 06:48:31.600854 anx7625_disable_pd_protocol: Disabled PD feature.
9355 06:48:31.604043 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9356 06:48:31.631990 anx7625_start_dp_work: Secure OCM version=00
9357 06:48:31.635273 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9358 06:48:31.650281 sp_tx_get_edid_block: EDID Block = 1
9359 06:48:31.753112 Extracted contents:
9360 06:48:31.756377 header: 00 ff ff ff ff ff ff 00
9361 06:48:31.759793 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9362 06:48:31.763097 version: 01 04
9363 06:48:31.766183 basic params: 95 1f 11 78 0a
9364 06:48:31.769807 chroma info: 76 90 94 55 54 90 27 21 50 54
9365 06:48:31.772783 established: 00 00 00
9366 06:48:31.779546 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9367 06:48:31.782673 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9368 06:48:31.789592 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9369 06:48:31.796335 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9370 06:48:31.802681 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9371 06:48:31.805937 extensions: 00
9372 06:48:31.806353 checksum: fb
9373 06:48:31.806681
9374 06:48:31.809284 Manufacturer: IVO Model 57d Serial Number 0
9375 06:48:31.812559 Made week 0 of 2020
9376 06:48:31.812975 EDID version: 1.4
9377 06:48:31.816178 Digital display
9378 06:48:31.819272 6 bits per primary color channel
9379 06:48:31.819575 DisplayPort interface
9380 06:48:31.822635 Maximum image size: 31 cm x 17 cm
9381 06:48:31.825774 Gamma: 220%
9382 06:48:31.825855 Check DPMS levels
9383 06:48:31.828852 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9384 06:48:31.835308 First detailed timing is preferred timing
9385 06:48:31.835390 Established timings supported:
9386 06:48:31.838652 Standard timings supported:
9387 06:48:31.842090 Detailed timings
9388 06:48:31.845326 Hex of detail: 383680a07038204018303c0035ae10000019
9389 06:48:31.848769 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9390 06:48:31.855276 0780 0798 07c8 0820 hborder 0
9391 06:48:31.858676 0438 043b 0447 0458 vborder 0
9392 06:48:31.862131 -hsync -vsync
9393 06:48:31.862212 Did detailed timing
9394 06:48:31.868494 Hex of detail: 000000000000000000000000000000000000
9395 06:48:31.868576 Manufacturer-specified data, tag 0
9396 06:48:31.875410 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9397 06:48:31.878427 ASCII string: InfoVision
9398 06:48:31.881913 Hex of detail: 000000fe00523134304e574635205248200a
9399 06:48:31.885167 ASCII string: R140NWF5 RH
9400 06:48:31.885284 Checksum
9401 06:48:31.888536 Checksum: 0xfb (valid)
9402 06:48:31.891550 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9403 06:48:31.894876 DSI data_rate: 832800000 bps
9404 06:48:31.901494 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9405 06:48:31.904803 anx7625_parse_edid: pixelclock(138800).
9406 06:48:31.908358 hactive(1920), hsync(48), hfp(24), hbp(88)
9407 06:48:31.911750 vactive(1080), vsync(12), vfp(3), vbp(17)
9408 06:48:31.914938 anx7625_dsi_config: config dsi.
9409 06:48:31.921704 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9410 06:48:31.934742 anx7625_dsi_config: success to config DSI
9411 06:48:31.938082 anx7625_dp_start: MIPI phy setup OK.
9412 06:48:31.941376 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9413 06:48:31.944571 mtk_ddp_mode_set invalid vrefresh 60
9414 06:48:31.947906 main_disp_path_setup
9415 06:48:31.947988 ovl_layer_smi_id_en
9416 06:48:31.951134 ovl_layer_smi_id_en
9417 06:48:31.951216 ccorr_config
9418 06:48:31.951279 aal_config
9419 06:48:31.954658 gamma_config
9420 06:48:31.954748 postmask_config
9421 06:48:31.957974 dither_config
9422 06:48:31.961393 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9423 06:48:31.967999 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9424 06:48:31.971486 Root Device init finished in 551 msecs
9425 06:48:31.974605 CPU_CLUSTER: 0 init
9426 06:48:31.981205 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9427 06:48:31.984425 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9428 06:48:31.988026 APU_MBOX 0x190000b0 = 0x10001
9429 06:48:31.990993 APU_MBOX 0x190001b0 = 0x10001
9430 06:48:31.994450 APU_MBOX 0x190005b0 = 0x10001
9431 06:48:31.997803 APU_MBOX 0x190006b0 = 0x10001
9432 06:48:32.001062 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9433 06:48:32.013715 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9434 06:48:32.026481 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9435 06:48:32.032688 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9436 06:48:32.044330 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9437 06:48:32.053335 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9438 06:48:32.056834 CPU_CLUSTER: 0 init finished in 81 msecs
9439 06:48:32.060125 Devices initialized
9440 06:48:32.063502 Show all devs... After init.
9441 06:48:32.063583 Root Device: enabled 1
9442 06:48:32.066782 CPU_CLUSTER: 0: enabled 1
9443 06:48:32.070088 CPU: 00: enabled 1
9444 06:48:32.073337 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9445 06:48:32.076893 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9446 06:48:32.080235 ELOG: NV offset 0x57f000 size 0x1000
9447 06:48:32.086552 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9448 06:48:32.093398 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9449 06:48:32.096485 ELOG: Event(17) added with size 13 at 2024-02-03 06:48:36 UTC
9450 06:48:32.099871 out: cmd=0x121: 03 db 21 01 00 00 00 00
9451 06:48:32.103803 in-header: 03 4b 00 00 2c 00 00 00
9452 06:48:32.117006 in-data: 13 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9453 06:48:32.123508 ELOG: Event(A1) added with size 10 at 2024-02-03 06:48:36 UTC
9454 06:48:32.130438 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9455 06:48:32.137133 ELOG: Event(A0) added with size 9 at 2024-02-03 06:48:36 UTC
9456 06:48:32.140399 elog_add_boot_reason: Logged dev mode boot
9457 06:48:32.143638 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9458 06:48:32.146995 Finalize devices...
9459 06:48:32.147166 Devices finalized
9460 06:48:32.153711 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9461 06:48:32.157031 Writing coreboot table at 0xffe64000
9462 06:48:32.160256 0. 000000000010a000-0000000000113fff: RAMSTAGE
9463 06:48:32.163774 1. 0000000040000000-00000000400fffff: RAM
9464 06:48:32.170240 2. 0000000040100000-000000004032afff: RAMSTAGE
9465 06:48:32.173502 3. 000000004032b000-00000000545fffff: RAM
9466 06:48:32.176704 4. 0000000054600000-000000005465ffff: BL31
9467 06:48:32.180376 5. 0000000054660000-00000000ffe63fff: RAM
9468 06:48:32.187004 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9469 06:48:32.190351 7. 0000000100000000-000000023fffffff: RAM
9470 06:48:32.193589 Passing 5 GPIOs to payload:
9471 06:48:32.196769 NAME | PORT | POLARITY | VALUE
9472 06:48:32.200049 EC in RW | 0x000000aa | low | undefined
9473 06:48:32.206790 EC interrupt | 0x00000005 | low | undefined
9474 06:48:32.210102 TPM interrupt | 0x000000ab | high | undefined
9475 06:48:32.216825 SD card detect | 0x00000011 | high | undefined
9476 06:48:32.220147 speaker enable | 0x00000093 | high | undefined
9477 06:48:32.223456 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9478 06:48:32.226744 in-header: 03 f9 00 00 02 00 00 00
9479 06:48:32.227160 in-data: 02 00
9480 06:48:32.230106 ADC[4]: Raw value=894821 ID=7
9481 06:48:32.233584 ADC[3]: Raw value=212330 ID=1
9482 06:48:32.236633 RAM Code: 0x71
9483 06:48:32.237046 ADC[6]: Raw value=74352 ID=0
9484 06:48:32.239816 ADC[5]: Raw value=212330 ID=1
9485 06:48:32.243390 SKU Code: 0x1
9486 06:48:32.246526 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1c2
9487 06:48:32.249705 coreboot table: 964 bytes.
9488 06:48:32.253164 IMD ROOT 0. 0xfffff000 0x00001000
9489 06:48:32.256564 IMD SMALL 1. 0xffffe000 0x00001000
9490 06:48:32.259763 RO MCACHE 2. 0xffffc000 0x00001104
9491 06:48:32.263150 CONSOLE 3. 0xfff7c000 0x00080000
9492 06:48:32.266819 FMAP 4. 0xfff7b000 0x00000452
9493 06:48:32.269928 TIME STAMP 5. 0xfff7a000 0x00000910
9494 06:48:32.273107 VBOOT WORK 6. 0xfff66000 0x00014000
9495 06:48:32.276514 RAMOOPS 7. 0xffe66000 0x00100000
9496 06:48:32.279891 COREBOOT 8. 0xffe64000 0x00002000
9497 06:48:32.280306 IMD small region:
9498 06:48:32.283170 IMD ROOT 0. 0xffffec00 0x00000400
9499 06:48:32.286582 VPD 1. 0xffffeb80 0x0000006c
9500 06:48:32.289910 MMC STATUS 2. 0xffffeb60 0x00000004
9501 06:48:32.296467 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9502 06:48:32.299645 Probing TPM: done!
9503 06:48:32.302927 Connected to device vid:did:rid of 1ae0:0028:00
9504 06:48:32.313028 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9505 06:48:32.316124 Initialized TPM device CR50 revision 0
9506 06:48:32.320268 Checking cr50 for pending updates
9507 06:48:32.323605 Reading cr50 TPM mode
9508 06:48:32.332062 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9509 06:48:32.338634 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9510 06:48:32.379256 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9511 06:48:32.382140 Checking segment from ROM address 0x40100000
9512 06:48:32.385872 Checking segment from ROM address 0x4010001c
9513 06:48:32.392433 Loading segment from ROM address 0x40100000
9514 06:48:32.392993 code (compression=0)
9515 06:48:32.399241 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9516 06:48:32.409100 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9517 06:48:32.409630 it's not compressed!
9518 06:48:32.415568 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9519 06:48:32.419144 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9520 06:48:32.439148 Loading segment from ROM address 0x4010001c
9521 06:48:32.439628 Entry Point 0x80000000
9522 06:48:32.442490 Loaded segments
9523 06:48:32.446096 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9524 06:48:32.452407 Jumping to boot code at 0x80000000(0xffe64000)
9525 06:48:32.459375 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9526 06:48:32.465916 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9527 06:48:32.473582 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9528 06:48:32.477335 Checking segment from ROM address 0x40100000
9529 06:48:32.480629 Checking segment from ROM address 0x4010001c
9530 06:48:32.487201 Loading segment from ROM address 0x40100000
9531 06:48:32.487621 code (compression=1)
9532 06:48:32.493933 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9533 06:48:32.503708 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9534 06:48:32.504240 using LZMA
9535 06:48:32.512067 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9536 06:48:32.518797 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9537 06:48:32.521742 Loading segment from ROM address 0x4010001c
9538 06:48:32.521968 Entry Point 0x54601000
9539 06:48:32.525380 Loaded segments
9540 06:48:32.528315 NOTICE: MT8192 bl31_setup
9541 06:48:32.535186 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9542 06:48:32.538722 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9543 06:48:32.541922 WARNING: region 0:
9544 06:48:32.545487 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 06:48:32.545586 WARNING: region 1:
9546 06:48:32.551969 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9547 06:48:32.555254 WARNING: region 2:
9548 06:48:32.558481 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9549 06:48:32.561749 WARNING: region 3:
9550 06:48:32.565417 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9551 06:48:32.568693 WARNING: region 4:
9552 06:48:32.575429 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9553 06:48:32.575524 WARNING: region 5:
9554 06:48:32.578432 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9555 06:48:32.581888 WARNING: region 6:
9556 06:48:32.585618 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9557 06:48:32.585698 WARNING: region 7:
9558 06:48:32.591826 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9559 06:48:32.598735 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9560 06:48:32.601964 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9561 06:48:32.605196 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9562 06:48:32.612069 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9563 06:48:32.615540 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9564 06:48:32.618817 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9565 06:48:32.625632 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9566 06:48:32.628609 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9567 06:48:32.635548 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9568 06:48:32.638931 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9569 06:48:32.642156 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9570 06:48:32.648778 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9571 06:48:32.652056 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9572 06:48:32.655486 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9573 06:48:32.662109 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9574 06:48:32.665318 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9575 06:48:32.668746 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9576 06:48:32.675485 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9577 06:48:32.678749 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9578 06:48:32.682073 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9579 06:48:32.688879 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9580 06:48:32.691807 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9581 06:48:32.698574 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9582 06:48:32.701844 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9583 06:48:32.708578 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9584 06:48:32.712053 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9585 06:48:32.715311 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9586 06:48:32.722183 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9587 06:48:32.725305 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9588 06:48:32.731959 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9589 06:48:32.735432 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9590 06:48:32.738781 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9591 06:48:32.745505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9592 06:48:32.748861 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9593 06:48:32.752176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9594 06:48:32.755510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9595 06:48:32.758964 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9596 06:48:32.765797 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9597 06:48:32.768928 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9598 06:48:32.772229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9599 06:48:32.775615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9600 06:48:32.782341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9601 06:48:32.785403 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9602 06:48:32.788869 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9603 06:48:32.795576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9604 06:48:32.798736 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9605 06:48:32.801892 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9606 06:48:32.805105 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9607 06:48:32.811783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9608 06:48:32.815197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9609 06:48:32.822000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9610 06:48:32.825273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9611 06:48:32.828629 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9612 06:48:32.835386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9613 06:48:32.838486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9614 06:48:32.845303 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9615 06:48:32.848814 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9616 06:48:32.855237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9617 06:48:32.858508 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9618 06:48:32.861944 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9619 06:48:32.868573 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9620 06:48:32.872066 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9621 06:48:32.878564 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9622 06:48:32.881791 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9623 06:48:32.888567 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9624 06:48:32.892104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9625 06:48:32.895371 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9626 06:48:32.902008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9627 06:48:32.905326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9628 06:48:32.912078 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9629 06:48:32.915399 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9630 06:48:32.921728 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9631 06:48:32.925304 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9632 06:48:32.928649 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9633 06:48:32.935314 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9634 06:48:32.938693 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9635 06:48:32.945408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9636 06:48:32.948810 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9637 06:48:32.955210 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9638 06:48:32.958344 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9639 06:48:32.965285 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9640 06:48:32.968403 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9641 06:48:32.972036 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9642 06:48:32.978509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9643 06:48:32.981798 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9644 06:48:32.988507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9645 06:48:32.991896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9646 06:48:32.995383 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9647 06:48:33.002030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9648 06:48:33.005314 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9649 06:48:33.012280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9650 06:48:33.015619 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9651 06:48:33.022125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9652 06:48:33.025326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9653 06:48:33.032477 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9654 06:48:33.035634 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9655 06:48:33.038983 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9656 06:48:33.045320 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9657 06:48:33.048731 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9658 06:48:33.051961 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9659 06:48:33.055688 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9660 06:48:33.062457 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9661 06:48:33.065961 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9662 06:48:33.069034 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9663 06:48:33.075909 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9664 06:48:33.079147 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9665 06:48:33.085758 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9666 06:48:33.088965 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9667 06:48:33.095497 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9668 06:48:33.098983 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9669 06:48:33.101951 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9670 06:48:33.108752 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9671 06:48:33.112382 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9672 06:48:33.115546 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9673 06:48:33.122186 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9674 06:48:33.125443 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9675 06:48:33.128894 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9676 06:48:33.135452 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9677 06:48:33.138954 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9678 06:48:33.142572 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9679 06:48:33.149225 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9680 06:48:33.152201 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9681 06:48:33.155596 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9682 06:48:33.159043 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9683 06:48:33.165566 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9684 06:48:33.169256 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9685 06:48:33.172532 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9686 06:48:33.179157 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9687 06:48:33.182410 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9688 06:48:33.189068 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9689 06:48:33.192676 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9690 06:48:33.195667 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9691 06:48:33.202329 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9692 06:48:33.205857 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9693 06:48:33.212305 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9694 06:48:33.215775 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9695 06:48:33.218808 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9696 06:48:33.225663 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9697 06:48:33.229032 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9698 06:48:33.232599 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9699 06:48:33.239146 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9700 06:48:33.242728 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9701 06:48:33.249367 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9702 06:48:33.252739 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9703 06:48:33.255987 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9704 06:48:33.262264 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9705 06:48:33.265549 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9706 06:48:33.272560 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9707 06:48:33.275677 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9708 06:48:33.279193 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9709 06:48:33.285895 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9710 06:48:33.289142 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9711 06:48:33.292453 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9712 06:48:33.299422 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9713 06:48:33.302339 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9714 06:48:33.309342 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9715 06:48:33.312094 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9716 06:48:33.315874 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9717 06:48:33.322258 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9718 06:48:33.325712 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9719 06:48:33.332335 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9720 06:48:33.335856 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9721 06:48:33.338834 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9722 06:48:33.345701 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9723 06:48:33.348697 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9724 06:48:33.351998 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9725 06:48:33.358736 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9726 06:48:33.362283 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9727 06:48:33.368940 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9728 06:48:33.372474 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9729 06:48:33.375657 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9730 06:48:33.382287 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9731 06:48:33.385543 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9732 06:48:33.392071 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9733 06:48:33.395239 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9734 06:48:33.398953 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9735 06:48:33.405427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9736 06:48:33.408733 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9737 06:48:33.415383 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9738 06:48:33.418707 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9739 06:48:33.422031 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9740 06:48:33.428780 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9741 06:48:33.431829 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9742 06:48:33.438569 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9743 06:48:33.441796 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9744 06:48:33.445278 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9745 06:48:33.451663 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9746 06:48:33.455223 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9747 06:48:33.461444 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9748 06:48:33.465162 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9749 06:48:33.468090 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9750 06:48:33.474747 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9751 06:48:33.478114 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9752 06:48:33.484733 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9753 06:48:33.488434 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9754 06:48:33.491739 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9755 06:48:33.498236 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9756 06:48:33.501501 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9757 06:48:33.507942 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9758 06:48:33.511287 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9759 06:48:33.517878 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9760 06:48:33.521089 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9761 06:48:33.524559 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9762 06:48:33.531123 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9763 06:48:33.534276 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9764 06:48:33.541165 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9765 06:48:33.544748 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9766 06:48:33.547756 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9767 06:48:33.554428 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9768 06:48:33.558003 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9769 06:48:33.564568 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9770 06:48:33.567773 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9771 06:48:33.574257 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9772 06:48:33.577451 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9773 06:48:33.581101 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9774 06:48:33.587572 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9775 06:48:33.590914 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9776 06:48:33.597387 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9777 06:48:33.600664 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9778 06:48:33.607387 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9779 06:48:33.610656 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9780 06:48:33.613940 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9781 06:48:33.620583 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9782 06:48:33.623938 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9783 06:48:33.630494 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9784 06:48:33.634222 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9785 06:48:33.640571 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9786 06:48:33.643840 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9787 06:48:33.647365 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9788 06:48:33.653527 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9789 06:48:33.656929 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9790 06:48:33.660192 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9791 06:48:33.663619 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9792 06:48:33.667085 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9793 06:48:33.673755 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9794 06:48:33.676788 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9795 06:48:33.683464 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9796 06:48:33.686915 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9797 06:48:33.689962 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9798 06:48:33.696909 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9799 06:48:33.699981 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9800 06:48:33.706616 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9801 06:48:33.710103 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9802 06:48:33.713409 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9803 06:48:33.719618 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9804 06:48:33.722816 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9805 06:48:33.726261 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9806 06:48:33.733065 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9807 06:48:33.736310 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9808 06:48:33.739672 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9809 06:48:33.746069 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9810 06:48:33.749710 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9811 06:48:33.756017 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9812 06:48:33.759660 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9813 06:48:33.762946 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9814 06:48:33.769597 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9815 06:48:33.773015 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9816 06:48:33.776143 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9817 06:48:33.782422 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9818 06:48:33.786018 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9819 06:48:33.792490 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9820 06:48:33.795643 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9821 06:48:33.798910 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9822 06:48:33.805666 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9823 06:48:33.808879 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9824 06:48:33.812347 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9825 06:48:33.818687 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9826 06:48:33.821971 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9827 06:48:33.825540 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9828 06:48:33.831977 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9829 06:48:33.835218 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9830 06:48:33.838675 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9831 06:48:33.842041 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9832 06:48:33.845372 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9833 06:48:33.851850 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9834 06:48:33.855052 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9835 06:48:33.858345 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9836 06:48:33.864985 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9837 06:48:33.868258 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9838 06:48:33.871584 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9839 06:48:33.878225 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9840 06:48:33.881676 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9841 06:48:33.885058 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9842 06:48:33.891781 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9843 06:48:33.895273 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9844 06:48:33.898346 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9845 06:48:33.905192 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9846 06:48:33.908255 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9847 06:48:33.914824 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9848 06:48:33.918130 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9849 06:48:33.921377 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9850 06:48:33.927907 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9851 06:48:33.931365 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9852 06:48:33.938096 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9853 06:48:33.941347 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9854 06:48:33.947857 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9855 06:48:33.951285 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9856 06:48:33.954572 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9857 06:48:33.961308 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9858 06:48:33.964873 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9859 06:48:33.971196 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9860 06:48:33.974610 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9861 06:48:33.978016 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9862 06:48:33.984438 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9863 06:48:33.987993 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9864 06:48:33.994548 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9865 06:48:33.997954 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9866 06:48:34.000923 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9867 06:48:34.007570 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9868 06:48:34.011139 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9869 06:48:34.017585 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9870 06:48:34.020942 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9871 06:48:34.027696 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9872 06:48:34.031120 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9873 06:48:34.034327 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9874 06:48:34.041100 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9875 06:48:34.044337 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9876 06:48:34.051123 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9877 06:48:34.054368 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9878 06:48:34.057425 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9879 06:48:34.064160 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9880 06:48:34.067693 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9881 06:48:34.070952 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9882 06:48:34.077670 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9883 06:48:34.080956 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9884 06:48:34.087438 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9885 06:48:34.090891 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9886 06:48:34.097508 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9887 06:48:34.100731 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9888 06:48:34.103958 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9889 06:48:34.110931 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9890 06:48:34.114026 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9891 06:48:34.120899 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9892 06:48:34.123907 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9893 06:48:34.127278 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9894 06:48:34.134300 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9895 06:48:34.137632 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9896 06:48:34.144070 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9897 06:48:34.147413 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9898 06:48:34.150268 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9899 06:48:34.157451 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9900 06:48:34.160550 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9901 06:48:34.167012 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9902 06:48:34.170336 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9903 06:48:34.177249 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9904 06:48:34.180309 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9905 06:48:34.183807 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9906 06:48:34.190396 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9907 06:48:34.193866 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9908 06:48:34.200203 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9909 06:48:34.203570 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9910 06:48:34.207120 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9911 06:48:34.213455 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9912 06:48:34.217184 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9913 06:48:34.223424 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9914 06:48:34.226984 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9915 06:48:34.230185 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9916 06:48:34.236831 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9917 06:48:34.240259 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9918 06:48:34.246771 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9919 06:48:34.249879 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9920 06:48:34.256761 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9921 06:48:34.259980 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9922 06:48:34.266515 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9923 06:48:34.269880 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9924 06:48:34.273128 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9925 06:48:34.279910 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9926 06:48:34.283303 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9927 06:48:34.290028 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9928 06:48:34.293031 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9929 06:48:34.299885 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9930 06:48:34.303081 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9931 06:48:34.306260 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9932 06:48:34.312974 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9933 06:48:34.316214 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9934 06:48:34.322919 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9935 06:48:34.326334 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9936 06:48:34.333153 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9937 06:48:34.336312 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9938 06:48:34.342814 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9939 06:48:34.346245 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9940 06:48:34.349576 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9941 06:48:34.355940 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9942 06:48:34.359265 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9943 06:48:34.366120 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9944 06:48:34.369464 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9945 06:48:34.375994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9946 06:48:34.379440 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9947 06:48:34.382677 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9948 06:48:34.389424 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9949 06:48:34.392716 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9950 06:48:34.399444 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9951 06:48:34.402549 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9952 06:48:34.408908 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9953 06:48:34.412177 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9954 06:48:34.419114 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9955 06:48:34.422264 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9956 06:48:34.425457 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9957 06:48:34.432122 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9958 06:48:34.435484 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9959 06:48:34.442138 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9960 06:48:34.445619 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9961 06:48:34.448612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9962 06:48:34.455444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9963 06:48:34.458850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9964 06:48:34.465253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9965 06:48:34.468992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9966 06:48:34.475716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9967 06:48:34.478607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9968 06:48:34.485400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9969 06:48:34.488718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9970 06:48:34.495403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9971 06:48:34.498417 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9972 06:48:34.505260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9973 06:48:34.508685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9974 06:48:34.515221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9975 06:48:34.518603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9976 06:48:34.522278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9977 06:48:34.528888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9978 06:48:34.532136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9979 06:48:34.538669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9980 06:48:34.541949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9981 06:48:34.548406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9982 06:48:34.551703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9983 06:48:34.558396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9984 06:48:34.561765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9985 06:48:34.568356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9986 06:48:34.571955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9987 06:48:34.578441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9988 06:48:34.584970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9989 06:48:34.588313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9990 06:48:34.594944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9991 06:48:34.598604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9992 06:48:34.605014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9993 06:48:34.608276 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9994 06:48:34.608689 INFO: [APUAPC] vio 0
9995 06:48:34.615747 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9996 06:48:34.618702 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9997 06:48:34.621962 INFO: [APUAPC] D0_APC_0: 0x400510
9998 06:48:34.625180 INFO: [APUAPC] D0_APC_1: 0x0
9999 06:48:34.628982 INFO: [APUAPC] D0_APC_2: 0x1540
10000 06:48:34.632259 INFO: [APUAPC] D0_APC_3: 0x0
10001 06:48:34.635288 INFO: [APUAPC] D1_APC_0: 0xffffffff
10002 06:48:34.638635 INFO: [APUAPC] D1_APC_1: 0xffffffff
10003 06:48:34.641877 INFO: [APUAPC] D1_APC_2: 0x3fffff
10004 06:48:34.645591 INFO: [APUAPC] D1_APC_3: 0x0
10005 06:48:34.648677 INFO: [APUAPC] D2_APC_0: 0xffffffff
10006 06:48:34.652184 INFO: [APUAPC] D2_APC_1: 0xffffffff
10007 06:48:34.655318 INFO: [APUAPC] D2_APC_2: 0x3fffff
10008 06:48:34.658671 INFO: [APUAPC] D2_APC_3: 0x0
10009 06:48:34.661779 INFO: [APUAPC] D3_APC_0: 0xffffffff
10010 06:48:34.665369 INFO: [APUAPC] D3_APC_1: 0xffffffff
10011 06:48:34.668617 INFO: [APUAPC] D3_APC_2: 0x3fffff
10012 06:48:34.671951 INFO: [APUAPC] D3_APC_3: 0x0
10013 06:48:34.675233 INFO: [APUAPC] D4_APC_0: 0xffffffff
10014 06:48:34.678580 INFO: [APUAPC] D4_APC_1: 0xffffffff
10015 06:48:34.681821 INFO: [APUAPC] D4_APC_2: 0x3fffff
10016 06:48:34.682242 INFO: [APUAPC] D4_APC_3: 0x0
10017 06:48:34.688514 INFO: [APUAPC] D5_APC_0: 0xffffffff
10018 06:48:34.691590 INFO: [APUAPC] D5_APC_1: 0xffffffff
10019 06:48:34.694811 INFO: [APUAPC] D5_APC_2: 0x3fffff
10020 06:48:34.695245 INFO: [APUAPC] D5_APC_3: 0x0
10021 06:48:34.698249 INFO: [APUAPC] D6_APC_0: 0xffffffff
10022 06:48:34.701559 INFO: [APUAPC] D6_APC_1: 0xffffffff
10023 06:48:34.704914 INFO: [APUAPC] D6_APC_2: 0x3fffff
10024 06:48:34.708021 INFO: [APUAPC] D6_APC_3: 0x0
10025 06:48:34.711527 INFO: [APUAPC] D7_APC_0: 0xffffffff
10026 06:48:34.714909 INFO: [APUAPC] D7_APC_1: 0xffffffff
10027 06:48:34.718136 INFO: [APUAPC] D7_APC_2: 0x3fffff
10028 06:48:34.721697 INFO: [APUAPC] D7_APC_3: 0x0
10029 06:48:34.724763 INFO: [APUAPC] D8_APC_0: 0xffffffff
10030 06:48:34.728011 INFO: [APUAPC] D8_APC_1: 0xffffffff
10031 06:48:34.731343 INFO: [APUAPC] D8_APC_2: 0x3fffff
10032 06:48:34.734627 INFO: [APUAPC] D8_APC_3: 0x0
10033 06:48:34.738123 INFO: [APUAPC] D9_APC_0: 0xffffffff
10034 06:48:34.741410 INFO: [APUAPC] D9_APC_1: 0xffffffff
10035 06:48:34.744574 INFO: [APUAPC] D9_APC_2: 0x3fffff
10036 06:48:34.748067 INFO: [APUAPC] D9_APC_3: 0x0
10037 06:48:34.751251 INFO: [APUAPC] D10_APC_0: 0xffffffff
10038 06:48:34.754562 INFO: [APUAPC] D10_APC_1: 0xffffffff
10039 06:48:34.757840 INFO: [APUAPC] D10_APC_2: 0x3fffff
10040 06:48:34.761375 INFO: [APUAPC] D10_APC_3: 0x0
10041 06:48:34.764362 INFO: [APUAPC] D11_APC_0: 0xffffffff
10042 06:48:34.767835 INFO: [APUAPC] D11_APC_1: 0xffffffff
10043 06:48:34.771158 INFO: [APUAPC] D11_APC_2: 0x3fffff
10044 06:48:34.774572 INFO: [APUAPC] D11_APC_3: 0x0
10045 06:48:34.777618 INFO: [APUAPC] D12_APC_0: 0xffffffff
10046 06:48:34.781006 INFO: [APUAPC] D12_APC_1: 0xffffffff
10047 06:48:34.784318 INFO: [APUAPC] D12_APC_2: 0x3fffff
10048 06:48:34.787612 INFO: [APUAPC] D12_APC_3: 0x0
10049 06:48:34.790836 INFO: [APUAPC] D13_APC_0: 0xffffffff
10050 06:48:34.794219 INFO: [APUAPC] D13_APC_1: 0xffffffff
10051 06:48:34.797603 INFO: [APUAPC] D13_APC_2: 0x3fffff
10052 06:48:34.800930 INFO: [APUAPC] D13_APC_3: 0x0
10053 06:48:34.804154 INFO: [APUAPC] D14_APC_0: 0xffffffff
10054 06:48:34.807380 INFO: [APUAPC] D14_APC_1: 0xffffffff
10055 06:48:34.810899 INFO: [APUAPC] D14_APC_2: 0x3fffff
10056 06:48:34.814037 INFO: [APUAPC] D14_APC_3: 0x0
10057 06:48:34.817444 INFO: [APUAPC] D15_APC_0: 0xffffffff
10058 06:48:34.820717 INFO: [APUAPC] D15_APC_1: 0xffffffff
10059 06:48:34.824190 INFO: [APUAPC] D15_APC_2: 0x3fffff
10060 06:48:34.827357 INFO: [APUAPC] D15_APC_3: 0x0
10061 06:48:34.830666 INFO: [APUAPC] APC_CON: 0x4
10062 06:48:34.833826 INFO: [NOCDAPC] D0_APC_0: 0x0
10063 06:48:34.837020 INFO: [NOCDAPC] D0_APC_1: 0x0
10064 06:48:34.840360 INFO: [NOCDAPC] D1_APC_0: 0x0
10065 06:48:34.843913 INFO: [NOCDAPC] D1_APC_1: 0xfff
10066 06:48:34.847082 INFO: [NOCDAPC] D2_APC_0: 0x0
10067 06:48:34.850344 INFO: [NOCDAPC] D2_APC_1: 0xfff
10068 06:48:34.850867 INFO: [NOCDAPC] D3_APC_0: 0x0
10069 06:48:34.853769 INFO: [NOCDAPC] D3_APC_1: 0xfff
10070 06:48:34.857202 INFO: [NOCDAPC] D4_APC_0: 0x0
10071 06:48:34.860394 INFO: [NOCDAPC] D4_APC_1: 0xfff
10072 06:48:34.863891 INFO: [NOCDAPC] D5_APC_0: 0x0
10073 06:48:34.866850 INFO: [NOCDAPC] D5_APC_1: 0xfff
10074 06:48:34.870421 INFO: [NOCDAPC] D6_APC_0: 0x0
10075 06:48:34.873625 INFO: [NOCDAPC] D6_APC_1: 0xfff
10076 06:48:34.876790 INFO: [NOCDAPC] D7_APC_0: 0x0
10077 06:48:34.880112 INFO: [NOCDAPC] D7_APC_1: 0xfff
10078 06:48:34.883497 INFO: [NOCDAPC] D8_APC_0: 0x0
10079 06:48:34.886798 INFO: [NOCDAPC] D8_APC_1: 0xfff
10080 06:48:34.887104 INFO: [NOCDAPC] D9_APC_0: 0x0
10081 06:48:34.890145 INFO: [NOCDAPC] D9_APC_1: 0xfff
10082 06:48:34.893426 INFO: [NOCDAPC] D10_APC_0: 0x0
10083 06:48:34.896902 INFO: [NOCDAPC] D10_APC_1: 0xfff
10084 06:48:34.900264 INFO: [NOCDAPC] D11_APC_0: 0x0
10085 06:48:34.903537 INFO: [NOCDAPC] D11_APC_1: 0xfff
10086 06:48:34.906842 INFO: [NOCDAPC] D12_APC_0: 0x0
10087 06:48:34.910139 INFO: [NOCDAPC] D12_APC_1: 0xfff
10088 06:48:34.913392 INFO: [NOCDAPC] D13_APC_0: 0x0
10089 06:48:34.916879 INFO: [NOCDAPC] D13_APC_1: 0xfff
10090 06:48:34.919735 INFO: [NOCDAPC] D14_APC_0: 0x0
10091 06:48:34.922960 INFO: [NOCDAPC] D14_APC_1: 0xfff
10092 06:48:34.926630 INFO: [NOCDAPC] D15_APC_0: 0x0
10093 06:48:34.929982 INFO: [NOCDAPC] D15_APC_1: 0xfff
10094 06:48:34.930062 INFO: [NOCDAPC] APC_CON: 0x4
10095 06:48:34.933161 INFO: [APUAPC] set_apusys_apc done
10096 06:48:34.936452 INFO: [DEVAPC] devapc_init done
10097 06:48:34.943327 INFO: GICv3 without legacy support detected.
10098 06:48:34.946436 INFO: ARM GICv3 driver initialized in EL3
10099 06:48:34.949745 INFO: Maximum SPI INTID supported: 639
10100 06:48:34.953219 INFO: BL31: Initializing runtime services
10101 06:48:34.959502 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10102 06:48:34.962969 INFO: SPM: enable CPC mode
10103 06:48:34.966363 INFO: mcdi ready for mcusys-off-idle and system suspend
10104 06:48:34.972987 INFO: BL31: Preparing for EL3 exit to normal world
10105 06:48:34.976172 INFO: Entry point address = 0x80000000
10106 06:48:34.976249 INFO: SPSR = 0x8
10107 06:48:34.983074
10108 06:48:34.983153
10109 06:48:34.983217
10110 06:48:34.986480 Starting depthcharge on Spherion...
10111 06:48:34.986555
10112 06:48:34.986616 Wipe memory regions:
10113 06:48:34.986676
10114 06:48:34.987345 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10115 06:48:34.987463 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10116 06:48:34.987549 Setting prompt string to ['asurada:']
10117 06:48:34.987631 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10118 06:48:34.989841 [0x00000040000000, 0x00000054600000)
10119 06:48:35.111917
10120 06:48:35.112071 [0x00000054660000, 0x00000080000000)
10121 06:48:35.372552
10122 06:48:35.372700 [0x000000821a7280, 0x000000ffe64000)
10123 06:48:36.117324
10124 06:48:36.117516 [0x00000100000000, 0x00000240000000)
10125 06:48:38.007309
10126 06:48:38.010337 Initializing XHCI USB controller at 0x11200000.
10127 06:48:39.049276
10128 06:48:39.052609 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10129 06:48:39.052703
10130 06:48:39.052803
10131 06:48:39.052903
10132 06:48:39.053228 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10134 06:48:39.153595 asurada: tftpboot 192.168.201.1 12694808/tftp-deploy-e5jug5ya/kernel/image.itb 12694808/tftp-deploy-e5jug5ya/kernel/cmdline
10135 06:48:39.153741 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10136 06:48:39.153846 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10137 06:48:39.158145 tftpboot 192.168.201.1 12694808/tftp-deploy-e5jug5ya/kernel/image.itp-deploy-e5jug5ya/kernel/cmdline
10138 06:48:39.158241
10139 06:48:39.158340 Waiting for link
10140 06:48:39.319085
10141 06:48:39.319222 R8152: Initializing
10142 06:48:39.319325
10143 06:48:39.321836 Version 6 (ocp_data = 5c30)
10144 06:48:39.321920
10145 06:48:39.325097 R8152: Done initializing
10146 06:48:39.325209
10147 06:48:39.325304 Adding net device
10148 06:48:41.276180
10149 06:48:41.276683 done.
10150 06:48:41.277025
10151 06:48:41.277333 MAC: 00:24:32:30:78:ff
10152 06:48:41.277672
10153 06:48:41.279462 Sending DHCP discover... done.
10154 06:48:41.279876
10155 06:48:45.094508 Waiting for reply... done.
10156 06:48:45.094647
10157 06:48:45.094716 Sending DHCP request... done.
10158 06:48:45.097668
10159 06:48:45.102505 Waiting for reply... done.
10160 06:48:45.102585
10161 06:48:45.102647 My ip is 192.168.201.21
10162 06:48:45.102706
10163 06:48:45.105775 The DHCP server ip is 192.168.201.1
10164 06:48:45.105878
10165 06:48:45.112331 TFTP server IP predefined by user: 192.168.201.1
10166 06:48:45.112422
10167 06:48:45.119242 Bootfile predefined by user: 12694808/tftp-deploy-e5jug5ya/kernel/image.itb
10168 06:48:45.119327
10169 06:48:45.122340 Sending tftp read request... done.
10170 06:48:45.122426
10171 06:48:45.126048 Waiting for the transfer...
10172 06:48:45.126139
10173 06:48:45.675661 00000000 ################################################################
10174 06:48:45.675796
10175 06:48:46.221001 00080000 ################################################################
10176 06:48:46.221142
10177 06:48:46.811860 00100000 ################################################################
10178 06:48:46.812008
10179 06:48:47.379903 00180000 ################################################################
10180 06:48:47.380057
10181 06:48:48.058501 00200000 ################################################################
10182 06:48:48.059075
10183 06:48:48.651764 00280000 ################################################################
10184 06:48:48.651902
10185 06:48:49.297186 00300000 ################################################################
10186 06:48:49.297350
10187 06:48:49.885415 00380000 ################################################################
10188 06:48:49.885589
10189 06:48:50.454410 00400000 ################################################################
10190 06:48:50.454546
10191 06:48:51.006476 00480000 ################################################################
10192 06:48:51.006654
10193 06:48:51.622796 00500000 ################################################################
10194 06:48:51.623289
10195 06:48:52.257241 00580000 ################################################################
10196 06:48:52.257419
10197 06:48:52.874002 00600000 ################################################################
10198 06:48:52.874138
10199 06:48:53.484733 00680000 ################################################################
10200 06:48:53.484891
10201 06:48:54.067590 00700000 ################################################################
10202 06:48:54.067736
10203 06:48:54.631108 00780000 ################################################################
10204 06:48:54.631248
10205 06:48:55.265835 00800000 ################################################################
10206 06:48:55.265986
10207 06:48:55.839686 00880000 ################################################################
10208 06:48:55.839841
10209 06:48:56.426610 00900000 ################################################################
10210 06:48:56.426752
10211 06:48:57.052951 00980000 ################################################################
10212 06:48:57.053082
10213 06:48:57.645963 00a00000 ################################################################
10214 06:48:57.646093
10215 06:48:58.248570 00a80000 ################################################################
10216 06:48:58.248716
10217 06:48:58.853767 00b00000 ################################################################
10218 06:48:58.854029
10219 06:48:59.596708 00b80000 ################################################################
10220 06:48:59.597505
10221 06:49:00.257029 00c00000 ################################################################
10222 06:49:00.257569
10223 06:49:00.987507 00c80000 ################################################################
10224 06:49:00.988062
10225 06:49:01.702977 00d00000 ################################################################
10226 06:49:01.703339
10227 06:49:02.330707 00d80000 ################################################################
10228 06:49:02.331213
10229 06:49:02.934995 00e00000 ################################################################
10230 06:49:02.935134
10231 06:49:03.549054 00e80000 ################################################################
10232 06:49:03.549229
10233 06:49:04.124501 00f00000 ################################################################
10234 06:49:04.124630
10235 06:49:04.691487 00f80000 ################################################################
10236 06:49:04.691639
10237 06:49:05.285180 01000000 ################################################################
10238 06:49:05.285750
10239 06:49:05.904064 01080000 ################################################################
10240 06:49:05.904207
10241 06:49:06.488755 01100000 ################################################################
10242 06:49:06.488898
10243 06:49:07.039576 01180000 ################################################################
10244 06:49:07.039706
10245 06:49:07.625301 01200000 ################################################################
10246 06:49:07.625481
10247 06:49:08.213682 01280000 ################################################################
10248 06:49:08.213817
10249 06:49:08.786093 01300000 ################################################################
10250 06:49:08.786236
10251 06:49:09.346985 01380000 ################################################################
10252 06:49:09.347122
10253 06:49:09.905151 01400000 ################################################################
10254 06:49:09.905364
10255 06:49:10.487417 01480000 ################################################################
10256 06:49:10.487553
10257 06:49:11.094835 01500000 ################################################################
10258 06:49:11.094975
10259 06:49:11.617939 01580000 ################################################################
10260 06:49:11.618070
10261 06:49:12.139082 01600000 ################################################################
10262 06:49:12.139222
10263 06:49:12.737209 01680000 ################################################################
10264 06:49:12.737763
10265 06:49:13.398679 01700000 ################################################################
10266 06:49:13.398830
10267 06:49:13.954697 01780000 ################################################################
10268 06:49:13.954840
10269 06:49:14.528561 01800000 ################################################################
10270 06:49:14.528704
10271 06:49:15.090243 01880000 ################################################################
10272 06:49:15.090391
10273 06:49:15.641888 01900000 ################################################################
10274 06:49:15.642022
10275 06:49:16.264549 01980000 ################################################################
10276 06:49:16.265049
10277 06:49:16.956755 01a00000 ################################################################
10278 06:49:16.957362
10279 06:49:17.649888 01a80000 ################################################################
10280 06:49:17.650430
10281 06:49:18.352254 01b00000 ################################################################
10282 06:49:18.352861
10283 06:49:19.059333 01b80000 ################################################################
10284 06:49:19.059863
10285 06:49:19.771159 01c00000 ################################################################
10286 06:49:19.771701
10287 06:49:20.506170 01c80000 ################################################################
10288 06:49:20.506732
10289 06:49:21.151328 01d00000 ######################################################### done.
10290 06:49:21.151474
10291 06:49:21.154521 The bootfile was 30869398 bytes long.
10292 06:49:21.154616
10293 06:49:21.157831 Sending tftp read request... done.
10294 06:49:21.157913
10295 06:49:21.160841 Waiting for the transfer...
10296 06:49:21.160922
10297 06:49:21.160986 00000000 # done.
10298 06:49:21.161046
10299 06:49:21.170961 Command line loaded dynamically from TFTP file: 12694808/tftp-deploy-e5jug5ya/kernel/cmdline
10300 06:49:21.171043
10301 06:49:21.191234 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694808/extract-nfsrootfs-jye3qfhu,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10302 06:49:21.194548
10303 06:49:21.194642 Loading FIT.
10304 06:49:21.194714
10305 06:49:21.197686 Image ramdisk-1 has 18769502 bytes.
10306 06:49:21.197786
10307 06:49:21.200979 Image fdt-1 has 47278 bytes.
10308 06:49:21.201158
10309 06:49:21.204646 Image kernel-1 has 12050581 bytes.
10310 06:49:21.204834
10311 06:49:21.211223 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10312 06:49:21.211424
10313 06:49:21.230924 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10314 06:49:21.231221
10315 06:49:21.234143 Choosing best match conf-1 for compat google,spherion-rev2.
10316 06:49:21.238743
10317 06:49:21.243564 Connected to device vid:did:rid of 1ae0:0028:00
10318 06:49:21.250808
10319 06:49:21.254352 tpm_get_response: command 0x17b, return code 0x0
10320 06:49:21.254866
10321 06:49:21.257059 ec_init: CrosEC protocol v3 supported (256, 248)
10322 06:49:21.261039
10323 06:49:21.264508 tpm_cleanup: add release locality here.
10324 06:49:21.265017
10325 06:49:21.265349 Shutting down all USB controllers.
10326 06:49:21.267846
10327 06:49:21.268376 Removing current net device
10328 06:49:21.268713
10329 06:49:21.274326 Exiting depthcharge with code 4 at timestamp: 75617086
10330 06:49:21.274801
10331 06:49:21.277519 LZMA decompressing kernel-1 to 0x821a6718
10332 06:49:21.277906
10333 06:49:21.280807 LZMA decompressing kernel-1 to 0x40000000
10334 06:49:22.779495
10335 06:49:22.780022 jumping to kernel
10336 06:49:22.781615 end: 2.2.4 bootloader-commands (duration 00:00:48) [common]
10337 06:49:22.782090 start: 2.2.5 auto-login-action (timeout 00:03:37) [common]
10338 06:49:22.782449 Setting prompt string to ['Linux version [0-9]']
10339 06:49:22.782781 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10340 06:49:22.783117 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10341 06:49:22.861694
10342 06:49:22.864944 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10343 06:49:22.868979 start: 2.2.5.1 login-action (timeout 00:03:37) [common]
10344 06:49:22.869434 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10345 06:49:22.869809 Setting prompt string to []
10346 06:49:22.870171 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10347 06:49:22.870535 Using line separator: #'\n'#
10348 06:49:22.870835 No login prompt set.
10349 06:49:22.871202 Parsing kernel messages
10350 06:49:22.871490 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10351 06:49:22.871991 [login-action] Waiting for messages, (timeout 00:03:37)
10352 06:49:22.888011 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10353 06:49:22.891428 [ 0.000000] random: crng init done
10354 06:49:22.898079 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10355 06:49:22.901361 [ 0.000000] efi: UEFI not found.
10356 06:49:22.907993 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10357 06:49:22.914534 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10358 06:49:22.924611 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10359 06:49:22.934509 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10360 06:49:22.941167 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10361 06:49:22.947383 [ 0.000000] printk: bootconsole [mtk8250] enabled
10362 06:49:22.953930 [ 0.000000] NUMA: No NUMA configuration found
10363 06:49:22.960555 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10364 06:49:22.963967 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10365 06:49:22.967363 [ 0.000000] Zone ranges:
10366 06:49:22.973908 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10367 06:49:22.977277 [ 0.000000] DMA32 empty
10368 06:49:22.983674 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10369 06:49:22.987093 [ 0.000000] Movable zone start for each node
10370 06:49:22.990403 [ 0.000000] Early memory node ranges
10371 06:49:22.997109 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10372 06:49:23.003742 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10373 06:49:23.010049 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10374 06:49:23.016706 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10375 06:49:23.023269 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10376 06:49:23.030080 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10377 06:49:23.086017 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10378 06:49:23.092525 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10379 06:49:23.099248 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10380 06:49:23.102612 [ 0.000000] psci: probing for conduit method from DT.
10381 06:49:23.109096 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10382 06:49:23.112505 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10383 06:49:23.119065 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10384 06:49:23.122475 [ 0.000000] psci: SMC Calling Convention v1.2
10385 06:49:23.129115 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10386 06:49:23.132325 [ 0.000000] Detected VIPT I-cache on CPU0
10387 06:49:23.139069 [ 0.000000] CPU features: detected: GIC system register CPU interface
10388 06:49:23.145742 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10389 06:49:23.152309 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10390 06:49:23.159074 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10391 06:49:23.168950 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10392 06:49:23.175451 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10393 06:49:23.178898 [ 0.000000] alternatives: applying boot alternatives
10394 06:49:23.185352 [ 0.000000] Fallback order for Node 0: 0
10395 06:49:23.192198 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10396 06:49:23.195256 [ 0.000000] Policy zone: Normal
10397 06:49:23.218398 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694808/extract-nfsrootfs-jye3qfhu,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10398 06:49:23.228324 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10399 06:49:23.238886 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10400 06:49:23.248970 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10401 06:49:23.255637 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10402 06:49:23.258830 <6>[ 0.000000] software IO TLB: area num 8.
10403 06:49:23.315350 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10404 06:49:23.464884 <6>[ 0.000000] Memory: 7948924K/8385536K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 403844K reserved, 32768K cma-reserved)
10405 06:49:23.471112 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10406 06:49:23.477891 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10407 06:49:23.481224 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10408 06:49:23.487918 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10409 06:49:23.494715 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10410 06:49:23.497812 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10411 06:49:23.507966 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10412 06:49:23.514679 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10413 06:49:23.517820 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10414 06:49:23.525591 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10415 06:49:23.529265 <6>[ 0.000000] GICv3: 608 SPIs implemented
10416 06:49:23.535824 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10417 06:49:23.539263 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10418 06:49:23.542278 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10419 06:49:23.552152 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10420 06:49:23.562163 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10421 06:49:23.575348 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10422 06:49:23.581675 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10423 06:49:23.591118 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10424 06:49:23.604425 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10425 06:49:23.611002 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10426 06:49:23.617592 <6>[ 0.009234] Console: colour dummy device 80x25
10427 06:49:23.627807 <6>[ 0.013960] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10428 06:49:23.634257 <6>[ 0.024467] pid_max: default: 32768 minimum: 301
10429 06:49:23.637593 <6>[ 0.029338] LSM: Security Framework initializing
10430 06:49:23.644292 <6>[ 0.034278] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10431 06:49:23.654057 <6>[ 0.042093] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10432 06:49:23.664122 <6>[ 0.051508] cblist_init_generic: Setting adjustable number of callback queues.
10433 06:49:23.667288 <6>[ 0.058950] cblist_init_generic: Setting shift to 3 and lim to 1.
10434 06:49:23.677326 <6>[ 0.065289] cblist_init_generic: Setting adjustable number of callback queues.
10435 06:49:23.683874 <6>[ 0.072762] cblist_init_generic: Setting shift to 3 and lim to 1.
10436 06:49:23.687341 <6>[ 0.079201] rcu: Hierarchical SRCU implementation.
10437 06:49:23.693807 <6>[ 0.084217] rcu: Max phase no-delay instances is 1000.
10438 06:49:23.700360 <6>[ 0.091242] EFI services will not be available.
10439 06:49:23.703720 <6>[ 0.096199] smp: Bringing up secondary CPUs ...
10440 06:49:23.712315 <6>[ 0.101245] Detected VIPT I-cache on CPU1
10441 06:49:23.718612 <6>[ 0.101314] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10442 06:49:23.725267 <6>[ 0.101344] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10443 06:49:23.728610 <6>[ 0.101684] Detected VIPT I-cache on CPU2
10444 06:49:23.735257 <6>[ 0.101738] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10445 06:49:23.745125 <6>[ 0.101757] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10446 06:49:23.748343 <6>[ 0.102016] Detected VIPT I-cache on CPU3
10447 06:49:23.755157 <6>[ 0.102062] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10448 06:49:23.761672 <6>[ 0.102076] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10449 06:49:23.765143 <6>[ 0.102381] CPU features: detected: Spectre-v4
10450 06:49:23.772021 <6>[ 0.102388] CPU features: detected: Spectre-BHB
10451 06:49:23.774897 <6>[ 0.102392] Detected PIPT I-cache on CPU4
10452 06:49:23.781461 <6>[ 0.102450] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10453 06:49:23.787932 <6>[ 0.102467] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10454 06:49:23.794854 <6>[ 0.102759] Detected PIPT I-cache on CPU5
10455 06:49:23.801586 <6>[ 0.102821] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10456 06:49:23.808044 <6>[ 0.102837] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10457 06:49:23.811286 <6>[ 0.103121] Detected PIPT I-cache on CPU6
10458 06:49:23.818127 <6>[ 0.103183] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10459 06:49:23.824638 <6>[ 0.103200] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10460 06:49:23.831516 <6>[ 0.103498] Detected PIPT I-cache on CPU7
10461 06:49:23.838070 <6>[ 0.103562] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10462 06:49:23.844443 <6>[ 0.103578] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10463 06:49:23.847727 <6>[ 0.103625] smp: Brought up 1 node, 8 CPUs
10464 06:49:23.854255 <6>[ 0.244793] SMP: Total of 8 processors activated.
10465 06:49:23.857814 <6>[ 0.249714] CPU features: detected: 32-bit EL0 Support
10466 06:49:23.867653 <6>[ 0.255076] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10467 06:49:23.874127 <6>[ 0.263877] CPU features: detected: Common not Private translations
10468 06:49:23.880650 <6>[ 0.270352] CPU features: detected: CRC32 instructions
10469 06:49:23.883990 <6>[ 0.275704] CPU features: detected: RCpc load-acquire (LDAPR)
10470 06:49:23.890598 <6>[ 0.281664] CPU features: detected: LSE atomic instructions
10471 06:49:23.897251 <6>[ 0.287445] CPU features: detected: Privileged Access Never
10472 06:49:23.903823 <6>[ 0.293261] CPU features: detected: RAS Extension Support
10473 06:49:23.910551 <6>[ 0.298870] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10474 06:49:23.914176 <6>[ 0.306091] CPU: All CPU(s) started at EL2
10475 06:49:23.920167 <6>[ 0.310408] alternatives: applying system-wide alternatives
10476 06:49:23.929416 <6>[ 0.321118] devtmpfs: initialized
10477 06:49:23.941978 <6>[ 0.330007] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10478 06:49:23.951720 <6>[ 0.339968] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10479 06:49:23.958602 <6>[ 0.348205] pinctrl core: initialized pinctrl subsystem
10480 06:49:23.961575 <6>[ 0.354867] DMI not present or invalid.
10481 06:49:23.968324 <6>[ 0.359279] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10482 06:49:23.978034 <6>[ 0.366150] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10483 06:49:23.984653 <6>[ 0.373736] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10484 06:49:23.994833 <6>[ 0.381962] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10485 06:49:23.997960 <6>[ 0.390202] audit: initializing netlink subsys (disabled)
10486 06:49:24.007880 <5>[ 0.395894] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10487 06:49:24.014529 <6>[ 0.396588] thermal_sys: Registered thermal governor 'step_wise'
10488 06:49:24.021179 <6>[ 0.403860] thermal_sys: Registered thermal governor 'power_allocator'
10489 06:49:24.024161 <6>[ 0.410115] cpuidle: using governor menu
10490 06:49:24.030677 <6>[ 0.421073] NET: Registered PF_QIPCRTR protocol family
10491 06:49:24.037439 <6>[ 0.426560] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10492 06:49:24.044088 <6>[ 0.433660] ASID allocator initialised with 32768 entries
10493 06:49:24.047229 <6>[ 0.440190] Serial: AMBA PL011 UART driver
10494 06:49:24.057090 <4>[ 0.448979] Trying to register duplicate clock ID: 134
10495 06:49:24.111004 <6>[ 0.505853] KASLR enabled
10496 06:49:24.125179 <6>[ 0.513532] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10497 06:49:24.131918 <6>[ 0.520545] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10498 06:49:24.138291 <6>[ 0.527034] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10499 06:49:24.144976 <6>[ 0.534036] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10500 06:49:24.151526 <6>[ 0.540522] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10501 06:49:24.158101 <6>[ 0.547527] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10502 06:49:24.165007 <6>[ 0.554012] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10503 06:49:24.171506 <6>[ 0.561016] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10504 06:49:24.174582 <6>[ 0.568520] ACPI: Interpreter disabled.
10505 06:49:24.183417 <6>[ 0.574935] iommu: Default domain type: Translated
10506 06:49:24.189910 <6>[ 0.580046] iommu: DMA domain TLB invalidation policy: strict mode
10507 06:49:24.193538 <5>[ 0.586703] SCSI subsystem initialized
10508 06:49:24.199900 <6>[ 0.590865] usbcore: registered new interface driver usbfs
10509 06:49:24.206850 <6>[ 0.596598] usbcore: registered new interface driver hub
10510 06:49:24.209897 <6>[ 0.602152] usbcore: registered new device driver usb
10511 06:49:24.216585 <6>[ 0.608250] pps_core: LinuxPPS API ver. 1 registered
10512 06:49:24.226725 <6>[ 0.613443] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10513 06:49:24.229827 <6>[ 0.622792] PTP clock support registered
10514 06:49:24.232919 <6>[ 0.627033] EDAC MC: Ver: 3.0.0
10515 06:49:24.240672 <6>[ 0.632175] FPGA manager framework
10516 06:49:24.247088 <6>[ 0.635854] Advanced Linux Sound Architecture Driver Initialized.
10517 06:49:24.250315 <6>[ 0.642630] vgaarb: loaded
10518 06:49:24.256862 <6>[ 0.645781] clocksource: Switched to clocksource arch_sys_counter
10519 06:49:24.260558 <5>[ 0.652222] VFS: Disk quotas dquot_6.6.0
10520 06:49:24.267101 <6>[ 0.656408] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10521 06:49:24.270114 <6>[ 0.663595] pnp: PnP ACPI: disabled
10522 06:49:24.278631 <6>[ 0.670276] NET: Registered PF_INET protocol family
10523 06:49:24.288643 <6>[ 0.675872] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10524 06:49:24.299824 <6>[ 0.688209] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10525 06:49:24.309921 <6>[ 0.697021] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10526 06:49:24.316576 <6>[ 0.704994] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10527 06:49:24.323273 <6>[ 0.713696] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10528 06:49:24.335043 <6>[ 0.723448] TCP: Hash tables configured (established 65536 bind 65536)
10529 06:49:24.341610 <6>[ 0.730306] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10530 06:49:24.348359 <6>[ 0.737504] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10531 06:49:24.354908 <6>[ 0.745206] NET: Registered PF_UNIX/PF_LOCAL protocol family
10532 06:49:24.361677 <6>[ 0.751359] RPC: Registered named UNIX socket transport module.
10533 06:49:24.365103 <6>[ 0.757513] RPC: Registered udp transport module.
10534 06:49:24.371495 <6>[ 0.762444] RPC: Registered tcp transport module.
10535 06:49:24.378285 <6>[ 0.767375] RPC: Registered tcp NFSv4.1 backchannel transport module.
10536 06:49:24.381518 <6>[ 0.774041] PCI: CLS 0 bytes, default 64
10537 06:49:24.384978 <6>[ 0.778378] Unpacking initramfs...
10538 06:49:24.409628 <6>[ 0.797888] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10539 06:49:24.419442 <6>[ 0.806534] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10540 06:49:24.422731 <6>[ 0.815382] kvm [1]: IPA Size Limit: 40 bits
10541 06:49:24.429250 <6>[ 0.819906] kvm [1]: GICv3: no GICV resource entry
10542 06:49:24.432527 <6>[ 0.824925] kvm [1]: disabling GICv2 emulation
10543 06:49:24.439193 <6>[ 0.829612] kvm [1]: GIC system register CPU interface enabled
10544 06:49:24.442686 <6>[ 0.835773] kvm [1]: vgic interrupt IRQ18
10545 06:49:24.449150 <6>[ 0.840149] kvm [1]: VHE mode initialized successfully
10546 06:49:24.455901 <5>[ 0.846630] Initialise system trusted keyrings
10547 06:49:24.462142 <6>[ 0.851496] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10548 06:49:24.469842 <6>[ 0.861442] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10549 06:49:24.476702 <5>[ 0.867826] NFS: Registering the id_resolver key type
10550 06:49:24.479849 <5>[ 0.873124] Key type id_resolver registered
10551 06:49:24.486375 <5>[ 0.877537] Key type id_legacy registered
10552 06:49:24.493205 <6>[ 0.881819] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10553 06:49:24.499749 <6>[ 0.888740] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10554 06:49:24.506368 <6>[ 0.896474] 9p: Installing v9fs 9p2000 file system support
10555 06:49:24.542612 <5>[ 0.934274] Key type asymmetric registered
10556 06:49:24.546024 <5>[ 0.938605] Asymmetric key parser 'x509' registered
10557 06:49:24.555862 <6>[ 0.943747] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10558 06:49:24.559410 <6>[ 0.951362] io scheduler mq-deadline registered
10559 06:49:24.562648 <6>[ 0.956137] io scheduler kyber registered
10560 06:49:24.581612 <6>[ 0.973231] EINJ: ACPI disabled.
10561 06:49:24.613968 <4>[ 0.998850] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10562 06:49:24.623900 <4>[ 1.009461] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10563 06:49:24.638585 <6>[ 1.030236] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10564 06:49:24.646528 <6>[ 1.038286] printk: console [ttyS0] disabled
10565 06:49:24.674639 <6>[ 1.062908] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10566 06:49:24.681383 <6>[ 1.072395] printk: console [ttyS0] enabled
10567 06:49:24.684442 <6>[ 1.072395] printk: console [ttyS0] enabled
10568 06:49:24.691138 <6>[ 1.081290] printk: bootconsole [mtk8250] disabled
10569 06:49:24.694534 <6>[ 1.081290] printk: bootconsole [mtk8250] disabled
10570 06:49:24.701063 <6>[ 1.092545] SuperH (H)SCI(F) driver initialized
10571 06:49:24.704486 <6>[ 1.097836] msm_serial: driver initialized
10572 06:49:24.718714 <6>[ 1.106854] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10573 06:49:24.728568 <6>[ 1.115401] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10574 06:49:24.735193 <6>[ 1.123943] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10575 06:49:24.744907 <6>[ 1.132571] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10576 06:49:24.751652 <6>[ 1.141282] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10577 06:49:24.761930 <6>[ 1.150003] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10578 06:49:24.771673 <6>[ 1.158543] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10579 06:49:24.778469 <6>[ 1.167346] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10580 06:49:24.787952 <6>[ 1.175891] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10581 06:49:24.800276 <6>[ 1.191665] loop: module loaded
10582 06:49:24.806519 <6>[ 1.197681] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10583 06:49:24.829211 <4>[ 1.221024] mtk-pmic-keys: Failed to locate of_node [id: -1]
10584 06:49:24.836044 <6>[ 1.227768] megasas: 07.719.03.00-rc1
10585 06:49:24.845776 <6>[ 1.237436] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10586 06:49:24.853472 <6>[ 1.245175] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10587 06:49:24.870404 <6>[ 1.261862] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10588 06:49:24.926838 <6>[ 1.311979] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10589 06:49:25.179123 <6>[ 1.571113] Freeing initrd memory: 18328K
10590 06:49:25.191003 <6>[ 1.582956] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10591 06:49:25.201955 <6>[ 1.594020] tun: Universal TUN/TAP device driver, 1.6
10592 06:49:25.205346 <6>[ 1.600094] thunder_xcv, ver 1.0
10593 06:49:25.208543 <6>[ 1.603598] thunder_bgx, ver 1.0
10594 06:49:25.211947 <6>[ 1.607094] nicpf, ver 1.0
10595 06:49:25.222619 <6>[ 1.611112] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10596 06:49:25.225925 <6>[ 1.618588] hns3: Copyright (c) 2017 Huawei Corporation.
10597 06:49:25.232261 <6>[ 1.624176] hclge is initializing
10598 06:49:25.235461 <6>[ 1.627757] e1000: Intel(R) PRO/1000 Network Driver
10599 06:49:25.242178 <6>[ 1.632885] e1000: Copyright (c) 1999-2006 Intel Corporation.
10600 06:49:25.245591 <6>[ 1.638899] e1000e: Intel(R) PRO/1000 Network Driver
10601 06:49:25.252319 <6>[ 1.644115] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10602 06:49:25.259074 <6>[ 1.650299] igb: Intel(R) Gigabit Ethernet Network Driver
10603 06:49:25.265559 <6>[ 1.655948] igb: Copyright (c) 2007-2014 Intel Corporation.
10604 06:49:25.272236 <6>[ 1.661787] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10605 06:49:25.278855 <6>[ 1.668304] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10606 06:49:25.281840 <6>[ 1.674773] sky2: driver version 1.30
10607 06:49:25.288458 <6>[ 1.679754] VFIO - User Level meta-driver version: 0.3
10608 06:49:25.296024 <6>[ 1.687995] usbcore: registered new interface driver usb-storage
10609 06:49:25.302950 <6>[ 1.694444] usbcore: registered new device driver onboard-usb-hub
10610 06:49:25.311674 <6>[ 1.703611] mt6397-rtc mt6359-rtc: registered as rtc0
10611 06:49:25.321471 <6>[ 1.709074] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:49:29 UTC (1706942969)
10612 06:49:25.324654 <6>[ 1.718636] i2c_dev: i2c /dev entries driver
10613 06:49:25.341737 <6>[ 1.730349] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10614 06:49:25.362265 <6>[ 1.754333] cpu cpu0: EM: created perf domain
10615 06:49:25.365746 <6>[ 1.759261] cpu cpu4: EM: created perf domain
10616 06:49:25.372697 <6>[ 1.764887] sdhci: Secure Digital Host Controller Interface driver
10617 06:49:25.379735 <6>[ 1.771319] sdhci: Copyright(c) Pierre Ossman
10618 06:49:25.386287 <6>[ 1.776275] Synopsys Designware Multimedia Card Interface Driver
10619 06:49:25.393099 <6>[ 1.782913] sdhci-pltfm: SDHCI platform and OF driver helper
10620 06:49:25.395970 <6>[ 1.782980] mmc0: CQHCI version 5.10
10621 06:49:25.402950 <6>[ 1.792991] ledtrig-cpu: registered to indicate activity on CPUs
10622 06:49:25.409603 <6>[ 1.800104] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10623 06:49:25.416062 <6>[ 1.807159] usbcore: registered new interface driver usbhid
10624 06:49:25.419639 <6>[ 1.812980] usbhid: USB HID core driver
10625 06:49:25.425934 <6>[ 1.817176] spi_master spi0: will run message pump with realtime priority
10626 06:49:25.469366 <6>[ 1.854294] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10627 06:49:25.487648 <6>[ 1.869247] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10628 06:49:25.491048 <6>[ 1.882843] mmc0: Command Queue Engine enabled
10629 06:49:25.497941 <6>[ 1.887608] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10630 06:49:25.504310 <6>[ 1.894541] cros-ec-spi spi0.0: Chrome EC device registered
10631 06:49:25.507590 <6>[ 1.894875] mmcblk0: mmc0:0001 DA4128 116 GiB
10632 06:49:25.520957 <6>[ 1.912887] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10633 06:49:25.528985 <6>[ 1.920450] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10634 06:49:25.538850 <6>[ 1.923966] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10635 06:49:25.541957 <6>[ 1.926381] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10636 06:49:25.548852 <6>[ 1.936216] NET: Registered PF_PACKET protocol family
10637 06:49:25.555750 <6>[ 1.940859] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10638 06:49:25.559245 <6>[ 1.945582] 9pnet: Installing 9P2000 support
10639 06:49:25.565560 <5>[ 1.956604] Key type dns_resolver registered
10640 06:49:25.568774 <6>[ 1.961549] registered taskstats version 1
10641 06:49:25.575577 <5>[ 1.965929] Loading compiled-in X.509 certificates
10642 06:49:25.604525 <4>[ 1.989711] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 06:49:25.614562 <4>[ 2.000494] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 06:49:25.621148 <3>[ 2.011038] debugfs: File 'uA_load' in directory '/' already present!
10645 06:49:25.627564 <3>[ 2.017862] debugfs: File 'min_uV' in directory '/' already present!
10646 06:49:25.634375 <3>[ 2.024477] debugfs: File 'max_uV' in directory '/' already present!
10647 06:49:25.641042 <3>[ 2.031089] debugfs: File 'constraint_flags' in directory '/' already present!
10648 06:49:25.652185 <3>[ 2.040790] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10649 06:49:25.662021 <6>[ 2.053591] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10650 06:49:25.668769 <6>[ 2.060344] xhci-mtk 11200000.usb: xHCI Host Controller
10651 06:49:25.675376 <6>[ 2.065885] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10652 06:49:25.685341 <6>[ 2.073721] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10653 06:49:25.692159 <6>[ 2.083145] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10654 06:49:25.698690 <6>[ 2.089213] xhci-mtk 11200000.usb: xHCI Host Controller
10655 06:49:25.705406 <6>[ 2.094687] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10656 06:49:25.711970 <6>[ 2.102333] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10657 06:49:25.718515 <6>[ 2.110079] hub 1-0:1.0: USB hub found
10658 06:49:25.722020 <6>[ 2.114095] hub 1-0:1.0: 1 port detected
10659 06:49:25.728644 <6>[ 2.118356] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10660 06:49:25.735306 <6>[ 2.127076] hub 2-0:1.0: USB hub found
10661 06:49:25.738770 <6>[ 2.131098] hub 2-0:1.0: 1 port detected
10662 06:49:25.747448 <6>[ 2.139125] mtk-msdc 11f70000.mmc: Got CD GPIO
10663 06:49:25.759228 <6>[ 2.147577] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10664 06:49:25.766022 <6>[ 2.155623] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10665 06:49:25.776389 <4>[ 2.163538] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10666 06:49:25.786012 <6>[ 2.173065] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10667 06:49:25.792515 <6>[ 2.181143] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10668 06:49:25.799920 <6>[ 2.189238] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10669 06:49:25.809289 <6>[ 2.197161] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10670 06:49:25.815880 <6>[ 2.204978] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10671 06:49:25.825902 <6>[ 2.212794] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10672 06:49:25.835693 <6>[ 2.223235] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10673 06:49:25.842413 <6>[ 2.231617] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10674 06:49:25.852419 <6>[ 2.239958] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10675 06:49:25.858894 <6>[ 2.248297] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10676 06:49:25.868817 <6>[ 2.256638] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10677 06:49:25.875739 <6>[ 2.264980] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10678 06:49:25.885331 <6>[ 2.273319] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10679 06:49:25.892024 <6>[ 2.281658] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10680 06:49:25.902381 <6>[ 2.289996] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10681 06:49:25.909100 <6>[ 2.298335] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10682 06:49:25.918503 <6>[ 2.306673] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10683 06:49:25.925099 <6>[ 2.315012] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10684 06:49:25.935029 <6>[ 2.323351] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10685 06:49:25.941657 <6>[ 2.331690] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10686 06:49:25.951660 <6>[ 2.340029] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10687 06:49:25.958141 <6>[ 2.348788] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10688 06:49:25.965045 <6>[ 2.355988] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10689 06:49:25.971396 <6>[ 2.362749] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10690 06:49:25.978280 <6>[ 2.369524] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10691 06:49:25.988100 <6>[ 2.376452] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10692 06:49:25.994732 <6>[ 2.383292] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10693 06:49:26.004481 <6>[ 2.392419] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10694 06:49:26.014607 <6>[ 2.401542] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10695 06:49:26.024360 <6>[ 2.410837] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10696 06:49:26.034197 <6>[ 2.420305] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10697 06:49:26.040879 <6>[ 2.429772] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10698 06:49:26.050818 <6>[ 2.438892] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10699 06:49:26.060689 <6>[ 2.448358] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10700 06:49:26.070826 <6>[ 2.457476] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10701 06:49:26.080970 <6>[ 2.466770] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10702 06:49:26.090685 <6>[ 2.476931] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10703 06:49:26.100665 <6>[ 2.488782] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10704 06:49:26.107042 <6>[ 2.498190] Trying to probe devices needed for running init ...
10705 06:49:26.130118 <6>[ 2.518306] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10706 06:49:26.158055 <6>[ 2.549562] hub 2-1:1.0: USB hub found
10707 06:49:26.161381 <6>[ 2.554049] hub 2-1:1.0: 3 ports detected
10708 06:49:26.169952 <6>[ 2.561428] hub 2-1:1.0: USB hub found
10709 06:49:26.173400 <6>[ 2.565739] hub 2-1:1.0: 3 ports detected
10710 06:49:26.281273 <6>[ 2.670070] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10711 06:49:26.435712 <6>[ 2.828175] hub 1-1:1.0: USB hub found
10712 06:49:26.439144 <6>[ 2.832668] hub 1-1:1.0: 4 ports detected
10713 06:49:26.448962 <6>[ 2.841229] hub 1-1:1.0: USB hub found
10714 06:49:26.452281 <6>[ 2.845733] hub 1-1:1.0: 4 ports detected
10715 06:49:26.521302 <6>[ 2.910259] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10716 06:49:26.773119 <6>[ 3.162084] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10717 06:49:26.905383 <6>[ 3.297824] hub 1-1.4:1.0: USB hub found
10718 06:49:26.908906 <6>[ 3.302462] hub 1-1.4:1.0: 2 ports detected
10719 06:49:26.917986 <6>[ 3.310179] hub 1-1.4:1.0: USB hub found
10720 06:49:26.921403 <6>[ 3.314728] hub 1-1.4:1.0: 2 ports detected
10721 06:49:27.216941 <6>[ 3.606050] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10722 06:49:27.408887 <6>[ 3.798077] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10723 06:49:38.402275 <6>[ 14.799104] ALSA device list:
10724 06:49:38.408769 <6>[ 14.802400] No soundcards found.
10725 06:49:38.416851 <6>[ 14.810399] Freeing unused kernel memory: 8448K
10726 06:49:38.420176 <6>[ 14.815386] Run /init as init process
10727 06:49:38.431564 Loading, please wait...
10728 06:49:38.457841 Starting systemd-udevd version 252.19-1~deb12u1
10729 06:49:38.713649 <6>[ 15.103853] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10730 06:49:38.731340 <6>[ 15.124958] remoteproc remoteproc0: scp is available
10731 06:49:38.737975 <6>[ 15.130735] remoteproc remoteproc0: powering up scp
10732 06:49:38.744690 <6>[ 15.135904] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10733 06:49:38.751114 <6>[ 15.144352] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10734 06:49:38.761247 <3>[ 15.151014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 06:49:38.767750 <3>[ 15.159417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 06:49:38.777945 <6>[ 15.171412] mc: Linux media interface: v0.10
10737 06:49:38.784594 <6>[ 15.171590] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10738 06:49:38.794282 <3>[ 15.171668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 06:49:38.801189 <6>[ 15.172497] usbcore: registered new device driver r8152-cfgselector
10740 06:49:38.807783 <3>[ 15.172657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 06:49:38.817485 <3>[ 15.172674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 06:49:38.824215 <3>[ 15.172683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 06:49:38.830926 <3>[ 15.172695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 06:49:38.840978 <3>[ 15.172703] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 06:49:38.847675 <3>[ 15.172838] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 06:49:38.857400 <3>[ 15.172905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 06:49:38.864318 <3>[ 15.172913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 06:49:38.874017 <3>[ 15.172919] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 06:49:38.880993 <6>[ 15.172993] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10750 06:49:38.887543 <3>[ 15.173009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 06:49:38.897818 <3>[ 15.173019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 06:49:38.904568 <3>[ 15.173027] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 06:49:38.914596 <3>[ 15.173039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 06:49:38.921021 <3>[ 15.173050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 06:49:38.927718 <3>[ 15.173092] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 06:49:38.937684 <4>[ 15.184179] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10757 06:49:38.944458 <6>[ 15.191718] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10758 06:49:38.951070 <4>[ 15.198557] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10759 06:49:38.957599 <6>[ 15.200112] videodev: Linux video capture interface: v2.00
10760 06:49:38.967412 <6>[ 15.206344] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10761 06:49:38.974161 <4>[ 15.216321] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10762 06:49:38.980642 <4>[ 15.216321] Fallback method does not support PEC.
10763 06:49:38.987219 <6>[ 15.262371] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10764 06:49:38.997676 <6>[ 15.275868] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10765 06:49:39.004399 <6>[ 15.275924] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10766 06:49:39.010956 <6>[ 15.275932] remoteproc remoteproc0: remote processor scp is now up
10767 06:49:39.017515 <6>[ 15.331271] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10768 06:49:39.028054 <3>[ 15.336162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10769 06:49:39.037994 <6>[ 15.337335] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10770 06:49:39.044411 <6>[ 15.337613] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10771 06:49:39.054412 <6>[ 15.339416] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10772 06:49:39.064210 <4>[ 15.346257] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10773 06:49:39.071059 <6>[ 15.352826] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10774 06:49:39.080883 <4>[ 15.357094] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10775 06:49:39.084117 <6>[ 15.357819] Bluetooth: Core ver 2.22
10776 06:49:39.090758 <6>[ 15.357946] NET: Registered PF_BLUETOOTH protocol family
10777 06:49:39.097401 <6>[ 15.357950] Bluetooth: HCI device and connection manager initialized
10778 06:49:39.100528 <6>[ 15.357984] Bluetooth: HCI socket layer initialized
10779 06:49:39.107045 <6>[ 15.357990] Bluetooth: L2CAP socket layer initialized
10780 06:49:39.110649 <6>[ 15.357999] Bluetooth: SCO socket layer initialized
10781 06:49:39.117170 <6>[ 15.365680] pci_bus 0000:00: root bus resource [bus 00-ff]
10782 06:49:39.123690 <6>[ 15.409747] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10783 06:49:39.130226 <6>[ 15.410588] usbcore: registered new interface driver btusb
10784 06:49:39.136906 <6>[ 15.416641] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10785 06:49:39.147084 <4>[ 15.416940] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10786 06:49:39.153397 <3>[ 15.416950] Bluetooth: hci0: Failed to load firmware file (-2)
10787 06:49:39.160233 <3>[ 15.416954] Bluetooth: hci0: Failed to set up firmware (-2)
10788 06:49:39.169900 <4>[ 15.416957] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10789 06:49:39.179917 <6>[ 15.418049] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10790 06:49:39.186486 <6>[ 15.426024] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10791 06:49:39.196243 <6>[ 15.426732] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10792 06:49:39.203104 <6>[ 15.426846] usbcore: registered new interface driver uvcvideo
10793 06:49:39.213500 <3>[ 15.427891] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10794 06:49:39.222778 <6>[ 15.435381] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10795 06:49:39.225799 <6>[ 15.466080] r8152 2-1.3:1.0 eth0: v1.12.13
10796 06:49:39.232647 <6>[ 15.471018] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10797 06:49:39.239062 <6>[ 15.479308] usbcore: registered new interface driver r8152
10798 06:49:39.245667 <6>[ 15.482927] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10799 06:49:39.249199 <6>[ 15.482989] pci 0000:00:00.0: supports D1 D2
10800 06:49:39.255720 <6>[ 15.510951] usbcore: registered new interface driver cdc_ether
10801 06:49:39.262440 <6>[ 15.516378] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10802 06:49:39.272283 <6>[ 15.517294] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10803 06:49:39.278600 <6>[ 15.536426] usbcore: registered new interface driver r8153_ecm
10804 06:49:39.285698 <6>[ 15.546876] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10805 06:49:39.288500 <6>[ 15.569008] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10806 06:49:39.298723 <6>[ 15.569158] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10807 06:49:39.305645 <6>[ 15.696386] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10808 06:49:39.311882 <6>[ 15.703869] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10809 06:49:39.318480 <6>[ 15.711444] pci 0000:01:00.0: supports D1 D2
10810 06:49:39.325004 <6>[ 15.715962] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10811 06:49:39.343816 <6>[ 15.734004] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10812 06:49:39.350215 <6>[ 15.740903] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10813 06:49:39.356757 <6>[ 15.748982] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10814 06:49:39.366854 <6>[ 15.756981] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10815 06:49:39.373621 <6>[ 15.764982] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10816 06:49:39.383404 <6>[ 15.772982] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10817 06:49:39.386573 <6>[ 15.780982] pci 0000:00:00.0: PCI bridge to [bus 01]
10818 06:49:39.396683 <6>[ 15.786197] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10819 06:49:39.403285 <6>[ 15.794322] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10820 06:49:39.409899 <6>[ 15.801167] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10821 06:49:39.416286 <6>[ 15.807913] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10822 06:49:39.438988 <5>[ 15.829515] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10823 06:49:39.458913 <5>[ 15.849430] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10824 06:49:39.465679 <5>[ 15.856908] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10825 06:49:39.475550 <4>[ 15.865401] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10826 06:49:39.482157 <6>[ 15.874318] cfg80211: failed to load regulatory.db
10827 06:49:39.534668 <6>[ 15.925228] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10828 06:49:39.541704 <6>[ 15.932851] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10829 06:49:39.566143 <6>[ 15.959720] mt7921e 0000:01:00.0: ASIC revision: 79610010
10830 06:49:39.668423 <6>[ 16.058816] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10831 06:49:39.671612 <6>[ 16.058816]
10832 06:49:39.679663 Begin: Loading essential drivers ... done.
10833 06:49:39.683048 Begin: Running /scripts/init-premount ... done.
10834 06:49:39.689596 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10835 06:49:39.699461 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10836 06:49:39.702593 Device /sys/class/net/enx0024323078ff found
10837 06:49:39.702694 done.
10838 06:49:39.709256 Begin: Waiting up to 180 secs for any network device to become available ... done.
10839 06:49:39.759624 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10840 06:49:39.936337 <6>[ 16.326893] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10841 06:49:40.663441 <6>[ 17.056945] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10842 06:49:40.804304 <6>[ 17.197987] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10843 06:49:40.815416 IP-Config: no response after 2 secs - giving up
10844 06:49:40.821976 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10845 06:49:40.856379 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10846 06:49:41.507005 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10847 06:49:41.513695 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10848 06:49:41.520320 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10849 06:49:41.526906 host : mt8192-asurada-spherion-r0-cbg-8
10850 06:49:41.533388 domain : lava-rack
10851 06:49:41.539991 rootserver: 192.168.201.1 rootpath:
10852 06:49:41.540107 filename :
10853 06:49:41.676760 done.
10854 06:49:41.684964 Begin: Running /scripts/nfs-bottom ... done.
10855 06:49:41.703245 Begin: Running /scripts/init-bottom ... done.
10856 06:49:43.076545 <6>[ 19.470823] NET: Registered PF_INET6 protocol family
10857 06:49:43.084210 <6>[ 19.478440] Segment Routing with IPv6
10858 06:49:43.087671 <6>[ 19.482460] In-situ OAM (IOAM) with IPv6
10859 06:49:43.294068 <30>[ 19.658511] systemd[1]: systemd 252.19-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10860 06:49:43.297084 <30>[ 19.691625] systemd[1]: Detected architecture arm64.
10861 06:49:43.314290
10862 06:49:43.317892 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10863 06:49:43.317998
10864 06:49:43.345888 <30>[ 19.740003] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10865 06:49:44.449934 <30>[ 20.841040] systemd[1]: Queued start job for default target graphical.target.
10866 06:49:44.495940 <30>[ 20.886906] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10867 06:49:44.502386 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10868 06:49:44.524888 <30>[ 20.915892] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10869 06:49:44.534717 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10870 06:49:44.552758 <30>[ 20.943793] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10871 06:49:44.562701 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10872 06:49:44.580757 <30>[ 20.971399] systemd[1]: Created slice user.slice - User and Session Slice.
10873 06:49:44.586937 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10874 06:49:44.610747 <30>[ 20.998394] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10875 06:49:44.617312 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10876 06:49:44.638604 <30>[ 21.026301] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10877 06:49:44.645342 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10878 06:49:44.673823 <30>[ 21.054741] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10879 06:49:44.683820 <30>[ 21.074788] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10880 06:49:44.690482 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10881 06:49:44.711728 <30>[ 21.102593] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10882 06:49:44.721712 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10883 06:49:44.735799 <30>[ 21.130276] systemd[1]: Reached target paths.target - Path Units.
10884 06:49:44.742648 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10885 06:49:44.763599 <30>[ 21.154467] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10886 06:49:44.770302 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10887 06:49:44.783699 <30>[ 21.178088] systemd[1]: Reached target slices.target - Slice Units.
10888 06:49:44.793895 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10889 06:49:44.808563 <30>[ 21.202570] systemd[1]: Reached target swap.target - Swaps.
10890 06:49:44.815147 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10891 06:49:44.835532 <30>[ 21.226572] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10892 06:49:44.845354 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10893 06:49:44.864107 <30>[ 21.255059] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10894 06:49:44.874016 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10895 06:49:44.894444 <30>[ 21.285313] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10896 06:49:44.904366 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10897 06:49:44.920608 <30>[ 21.311617] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10898 06:49:44.930496 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10899 06:49:44.948040 <30>[ 21.338797] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10900 06:49:44.954264 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10901 06:49:44.973009 <30>[ 21.363817] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10902 06:49:44.982878 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10903 06:49:45.003599 <30>[ 21.394313] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10904 06:49:45.013289 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10905 06:49:45.031649 <30>[ 21.422612] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10906 06:49:45.041398 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10907 06:49:45.091253 <30>[ 21.482254] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10908 06:49:45.097765 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10909 06:49:45.119598 <30>[ 21.510657] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10910 06:49:45.126355 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10911 06:49:45.151609 <30>[ 21.542761] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10912 06:49:45.158142 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10913 06:49:45.186078 <30>[ 21.570430] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10914 06:49:45.202059 <30>[ 21.593184] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10915 06:49:45.212075 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10916 06:49:45.283972 <30>[ 21.674875] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10917 06:49:45.290480 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10918 06:49:45.315303 <30>[ 21.706119] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10919 06:49:45.321443 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10920 06:49:45.354777 <30>[ 21.745284] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10921 06:49:45.367679 Starting [0;1;39mmodprobe@drm.service<6>[ 21.757757] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10922 06:49:45.371066 [0m - Load Kernel Module drm...
10923 06:49:45.428025 <30>[ 21.818795] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10924 06:49:45.437432 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10925 06:49:45.457963 <30>[ 21.849097] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10926 06:49:45.464787 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10927 06:49:45.490257 <30>[ 21.881292] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10928 06:49:45.496891 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10929 06:49:45.505387 <6>[ 21.899703] fuse: init (API version 7.37)
10930 06:49:45.525006 <30>[ 21.916053] systemd[1]: Starting systemd-journald.service - Journal Service...
10931 06:49:45.531712 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10932 06:49:45.564833 <30>[ 21.955819] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10933 06:49:45.571240 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10934 06:49:45.599321 <30>[ 21.986933] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10935 06:49:45.605882 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10936 06:49:45.632452 <30>[ 22.023412] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10937 06:49:45.642304 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10938 06:49:45.700608 <30>[ 22.091193] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10939 06:49:45.714199 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug Al<3>[ 22.105479] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 06:49:45.717266 l udev Devices...
10941 06:49:45.740097 <30>[ 22.130454] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10942 06:49:45.750084 [[0;32m OK [0m] Mounted [0;<3>[ 22.139974] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 06:49:45.756684 1;39mdev-hugepages.mount[0m - Huge Pages File System.
10944 06:49:45.776153 <30>[ 22.167124] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10945 06:49:45.783025 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10946 06:49:45.794588 <3>[ 22.185408] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 06:49:45.807197 <30>[ 22.198285] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10948 06:49:45.814439 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10949 06:49:45.824629 <3>[ 22.214663] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 06:49:45.835383 <30>[ 22.226596] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10951 06:49:45.846251 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10952 06:49:45.852935 <3>[ 22.245089] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 06:49:45.864634 <30>[ 22.255894] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10954 06:49:45.875279 <30>[ 22.264615] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10955 06:49:45.888792 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 22.278244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 06:49:45.891892 Load Kernel Module configfs.
10957 06:49:45.908463 <30>[ 22.298915] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10958 06:49:45.915268 <30>[ 22.306641] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10959 06:49:45.925402 <3>[ 22.308688] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 06:49:45.931993 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10961 06:49:45.954238 <3>[ 22.344962] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 06:49:45.964064 <30>[ 22.355249] systemd[1]: modprobe@drm.service: Deactivated successfully.
10963 06:49:45.970789 <30>[ 22.362987] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10964 06:49:45.980589 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10965 06:49:45.994254 <3>[ 22.384848] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 06:49:46.004840 <30>[ 22.395829] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10967 06:49:46.015378 <30>[ 22.404177] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10968 06:49:46.022750 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10969 06:49:46.029177 <3>[ 22.420181] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 06:49:46.040958 <30>[ 22.432155] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10971 06:49:46.048164 <30>[ 22.440290] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10972 06:49:46.058230 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10973 06:49:46.076479 <30>[ 22.467121] systemd[1]: modprobe@loop.service: Deactivated successfully.
10974 06:49:46.083236 <30>[ 22.474915] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10975 06:49:46.092834 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10976 06:49:46.116506 <30>[ 22.507760] systemd[1]: Started systemd-journald.service - Journal Service.
10977 06:49:46.122998 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10978 06:49:46.149899 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10979 06:49:46.172004 <4>[ 22.556426] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10980 06:49:46.181651 <3>[ 22.572086] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10981 06:49:46.188196 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10982 06:49:46.212454 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10983 06:49:46.232658 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10984 06:49:46.254045 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10985 06:49:46.295072 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10986 06:49:46.313419 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10987 06:49:46.334557 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10988 06:49:46.355577 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10989 06:49:46.386400 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10990 06:49:46.396250 <46>[ 22.786985] systemd-journald[308]: Received client request to flush runtime journal.
10991 06:49:46.409079 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10992 06:49:46.438868 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10993 06:49:46.455959 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10994 06:49:46.476623 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10995 06:49:47.159933 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10996 06:49:47.782120 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10997 06:49:47.800221 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10998 06:49:47.839455 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10999 06:49:47.938188 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11000 06:49:47.959262 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11001 06:49:47.979034 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11002 06:49:48.031503 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
11003 06:49:48.053735 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11004 06:49:48.076336 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11005 06:49:48.110504 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11006 06:49:48.123345 See 'systemctl status systemd-binfmt.service' for details.
11007 06:49:48.341353 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11008 06:49:48.405397 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11009 06:49:48.454099 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11010 06:49:48.785423 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11011 06:49:48.824566 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11012 06:49:48.845922 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11013 06:49:48.901263 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11014 06:49:48.983015 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11015 06:49:49.003062 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11016 06:49:49.024065 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11017 06:49:49.044860 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11018 06:49:49.112432 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11019 06:49:49.135803 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11020 06:49:49.216219 <46>[ 25.610953] systemd-journald[308]: Time jumped backwards, rotating.
11021 06:49:49.226861 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11022 06:49:49.247244 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11023 06:49:49.269043 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11024 06:49:49.295115 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11025 06:49:49.311063 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11026 06:49:49.326966 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11027 06:49:50.012752 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11028 06:49:50.340720 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11029 06:49:50.358783 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11030 06:49:50.711113 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11031 06:49:50.734207 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11032 06:49:50.750774 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11033 06:49:50.768869 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11034 06:49:50.786653 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11035 06:49:50.802700 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11036 06:49:50.847848 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11037 06:49:50.883652 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11038 06:49:50.970200 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11039 06:49:50.995450 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11040 06:49:51.014979 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11041 06:49:51.190588 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11042 06:49:51.239668 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11043 06:49:51.262931 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11044 06:49:51.281385 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11045 06:49:51.300277 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11046 06:49:51.323131 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11047 06:49:51.354693 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11048 06:49:51.382090 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11049 06:49:51.403682 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11050 06:49:51.472501 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11051 06:49:51.498002 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11052 06:49:51.552094 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11053 06:49:51.584490 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11054 06:49:51.665908
11055 06:49:51.666056
11056 06:49:51.669635 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11057 06:49:51.669718
11058 06:49:51.672346 debian-bookworm-arm64 login: root (automatic login)
11059 06:49:51.672428
11060 06:49:51.672492
11061 06:49:51.977897 Linux debian-bookworm-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
11062 06:49:51.978060
11063 06:49:51.984565 The programs included with the Debian GNU/Linux system are free software;
11064 06:49:51.991181 the exact distribution terms for each program are described in the
11065 06:49:51.994629 individual files in /usr/share/doc/*/copyright.
11066 06:49:51.994725
11067 06:49:52.001197 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11068 06:49:52.004186 permitted by applicable law.
11069 06:49:53.022778 Matched prompt #10: / #
11071 06:49:53.023064 Setting prompt string to ['/ #']
11072 06:49:53.023159 end: 2.2.5.1 login-action (duration 00:00:30) [common]
11074 06:49:53.023354 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11075 06:49:53.023441 start: 2.2.6 expect-shell-connection (timeout 00:03:07) [common]
11076 06:49:53.023511 Setting prompt string to ['/ #']
11077 06:49:53.023570 Forcing a shell prompt, looking for ['/ #']
11079 06:49:53.073792 / #
11080 06:49:53.073952 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11081 06:49:53.074039 Waiting using forced prompt support (timeout 00:02:30)
11082 06:49:53.078861
11083 06:49:53.079170 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11084 06:49:53.079282 start: 2.2.7 export-device-env (timeout 00:03:07) [common]
11086 06:49:53.179653 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694808/extract-nfsrootfs-jye3qfhu'
11087 06:49:53.184654 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694808/extract-nfsrootfs-jye3qfhu'
11089 06:49:53.285203 / # export NFS_SERVER_IP='192.168.201.1'
11090 06:49:53.290374 export NFS_SERVER_IP='192.168.201.1'
11091 06:49:53.290664 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11092 06:49:53.290766 end: 2.2 depthcharge-retry (duration 00:01:53) [common]
11093 06:49:53.290856 end: 2 depthcharge-action (duration 00:01:53) [common]
11094 06:49:53.290949 start: 3 lava-test-retry (timeout 00:07:23) [common]
11095 06:49:53.291034 start: 3.1 lava-test-shell (timeout 00:07:23) [common]
11096 06:49:53.291107 Using namespace: common
11098 06:49:53.391467 / # #
11099 06:49:53.391646 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11100 06:49:53.396902 #
11101 06:49:53.397166 Using /lava-12694808
11103 06:49:53.497550 / # export SHELL=/bin/bash
11104 06:49:53.502844 export SHELL=/bin/bash
11106 06:49:53.603405 / # . /lava-12694808/environment
11107 06:49:53.608779 . /lava-12694808/environment
11109 06:49:53.715463 / # /lava-12694808/bin/lava-test-runner /lava-12694808/0
11110 06:49:53.715633 Test shell timeout: 10s (minimum of the action and connection timeout)
11111 06:49:53.720674 /lava-12694808/bin/lava-test-runner /lava-12694808/0
11112 06:49:53.996736 + export TESTRUN_ID=0_timesync-off
11113 06:49:53.999967 + TESTRUN_ID=0_timesync-off
11114 06:49:54.002902 + cd /lava-12694808/0/tests/0_timesync-off
11115 06:49:54.006303 ++ cat uuid
11116 06:49:54.012646 + UUID=12694808_1.6.2.3.1
11117 06:49:54.012732 + set +x
11118 06:49:54.019367 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12694808_1.6.2.3.1>
11119 06:49:54.019635 Received signal: <STARTRUN> 0_timesync-off 12694808_1.6.2.3.1
11120 06:49:54.019711 Starting test lava.0_timesync-off (12694808_1.6.2.3.1)
11121 06:49:54.019798 Skipping test definition patterns.
11122 06:49:54.022368 + systemctl stop systemd-timesyncd
11123 06:49:54.100077 + set +x
11124 06:49:54.103438 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12694808_1.6.2.3.1>
11125 06:49:54.103707 Received signal: <ENDRUN> 0_timesync-off 12694808_1.6.2.3.1
11126 06:49:54.103791 Ending use of test pattern.
11127 06:49:54.103852 Ending test lava.0_timesync-off (12694808_1.6.2.3.1), duration 0.08
11129 06:49:54.184688 + export TESTRUN_ID=1_kselftest-alsa
11130 06:49:54.188066 + TESTRUN_ID=1_kselftest-alsa
11131 06:49:54.194815 + cd /lava-12694808/0/tests/1_kselftest-alsa
11132 06:49:54.194907 ++ cat uuid
11133 06:49:54.199467 + UUID=12694808_1.6.2.3.5
11134 06:49:54.199549 + set +x
11135 06:49:54.206205 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12694808_1.6.2.3.5>
11136 06:49:54.206469 Received signal: <STARTRUN> 1_kselftest-alsa 12694808_1.6.2.3.5
11137 06:49:54.206538 Starting test lava.1_kselftest-alsa (12694808_1.6.2.3.5)
11138 06:49:54.206621 Skipping test definition patterns.
11139 06:49:54.209398 + cd ./automated/linux/kselftest/
11140 06:49:54.235761 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11141 06:49:54.281839 INFO: install_deps skipped
11142 06:49:54.784160 --2024-02-03 06:49:54-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11143 06:49:54.790448 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11144 06:49:54.921523 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11145 06:49:55.055009 HTTP request sent, awaiting response... 200 OK
11146 06:49:55.058466 Length: 2965368 (2.8M) [application/octet-stream]
11147 06:49:55.061738 Saving to: 'kselftest.tar.xz'
11148 06:49:55.061851
11149 06:49:55.061922
11150 06:49:55.321791 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11151 06:49:55.588416 kselftest.tar.xz 1%[ ] 47.81K 180KB/s
11152 06:49:55.855269 kselftest.tar.xz 7%[> ] 219.84K 414KB/s
11153 06:49:56.054948 kselftest.tar.xz 30%[=====> ] 896.25K 1.10MB/s
11154 06:49:56.313239 kselftest.tar.xz 49%[========> ] 1.40M 1.40MB/s
11155 06:49:56.319589 kselftest.tar.xz 87%[================> ] 2.48M 1.98MB/s
11156 06:49:56.326414 kselftest.tar.xz 100%[===================>] 2.83M 2.24MB/s in 1.3s
11157 06:49:56.326502
11158 06:49:56.583599 2024-02-03 06:49:56 (2.24 MB/s) - 'kselftest.tar.xz' saved [2965368/2965368]
11159 06:49:56.583755
11160 06:50:02.623476 skiplist:
11161 06:50:02.626890 ========================================
11162 06:50:02.630175 ========================================
11163 06:50:02.680731 alsa:mixer-test
11164 06:50:02.703382 ============== Tests to run ===============
11165 06:50:02.703538 alsa:mixer-test
11166 06:50:02.710025 ===========End Tests to run ===============
11167 06:50:02.713364 shardfile-alsa pass
11168 06:50:02.822816 <12>[ 39.219168] kselftest: Running tests in alsa
11169 06:50:02.832912 TAP version 13
11170 06:50:02.849060 1..1
11171 06:50:02.867971 # selftests: alsa: mixer-test
11172 06:50:03.377817 # TAP version 13
11173 06:50:03.377964 # 1..0
11174 06:50:03.384487 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11175 06:50:03.387524 ok 1 selftests: alsa: mixer-test
11176 06:50:04.115646 alsa_mixer-test pass
11177 06:50:04.159752 + ../../utils/send-to-lava.sh ./output/result.txt
11178 06:50:04.230512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11179 06:50:04.230827 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11181 06:50:04.288119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11182 06:50:04.288233 + set +x
11183 06:50:04.288475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11185 06:50:04.294744 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12694808_1.6.2.3.5>
11186 06:50:04.294996 Received signal: <ENDRUN> 1_kselftest-alsa 12694808_1.6.2.3.5
11187 06:50:04.295072 Ending use of test pattern.
11188 06:50:04.295134 Ending test lava.1_kselftest-alsa (12694808_1.6.2.3.5), duration 10.09
11190 06:50:04.297757 <LAVA_TEST_RUNNER EXIT>
11191 06:50:04.298008 ok: lava_test_shell seems to have completed
11192 06:50:04.298106 alsa_mixer-test: pass
shardfile-alsa: pass
11193 06:50:04.298196 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11194 06:50:04.298278 end: 3 lava-test-retry (duration 00:00:11) [common]
11195 06:50:04.298361 start: 4 finalize (timeout 00:07:12) [common]
11196 06:50:04.298447 start: 4.1 power-off (timeout 00:00:30) [common]
11197 06:50:04.298599 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11198 06:50:04.378592 >> Command sent successfully.
11199 06:50:04.380925 Returned 0 in 0 seconds
11200 06:50:04.481328 end: 4.1 power-off (duration 00:00:00) [common]
11202 06:50:04.481694 start: 4.2 read-feedback (timeout 00:07:12) [common]
11203 06:50:04.481961 Listened to connection for namespace 'common' for up to 1s
11204 06:50:05.482915 Finalising connection for namespace 'common'
11205 06:50:05.483089 Disconnecting from shell: Finalise
11206 06:50:05.483173 / #
11207 06:50:05.583495 end: 4.2 read-feedback (duration 00:00:01) [common]
11208 06:50:05.583656 end: 4 finalize (duration 00:00:01) [common]
11209 06:50:05.583770 Cleaning after the job
11210 06:50:05.583868 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/ramdisk
11211 06:50:05.586861 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/kernel
11212 06:50:05.600316 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/dtb
11213 06:50:05.600489 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/nfsrootfs
11214 06:50:05.702288 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694808/tftp-deploy-e5jug5ya/modules
11215 06:50:05.709412 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694808
11216 06:50:06.369876 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694808
11217 06:50:06.370051 Job finished correctly