Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 35
1 06:54:25.494322 lava-dispatcher, installed at version: 2023.10
2 06:54:25.494535 start: 0 validate
3 06:54:25.494677 Start time: 2024-02-03 06:54:25.494669+00:00 (UTC)
4 06:54:25.494794 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:54:25.494927 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 06:54:25.765738 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:54:25.766456 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:54:26.037413 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:54:26.038154 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:54:26.307472 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:54:26.308205 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:54:26.578879 Using caching service: 'http://localhost/cache/?uri=%s'
13 06:54:26.579629 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 06:54:26.856650 validate duration: 1.36
16 06:54:26.857883 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:54:26.858404 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:54:26.858854 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:54:26.859412 Not decompressing ramdisk as can be used compressed.
20 06:54:26.859838 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 06:54:26.860162 saving as /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/ramdisk/initrd.cpio.gz
22 06:54:26.860495 total size: 4665395 (4 MB)
23 06:54:26.865344 progress 0 % (0 MB)
24 06:54:26.872988 progress 5 % (0 MB)
25 06:54:26.879495 progress 10 % (0 MB)
26 06:54:26.884404 progress 15 % (0 MB)
27 06:54:26.888160 progress 20 % (0 MB)
28 06:54:26.891389 progress 25 % (1 MB)
29 06:54:26.894228 progress 30 % (1 MB)
30 06:54:26.896761 progress 35 % (1 MB)
31 06:54:26.899028 progress 40 % (1 MB)
32 06:54:26.901493 progress 45 % (2 MB)
33 06:54:26.903436 progress 50 % (2 MB)
34 06:54:26.905424 progress 55 % (2 MB)
35 06:54:26.907214 progress 60 % (2 MB)
36 06:54:26.908915 progress 65 % (2 MB)
37 06:54:26.910627 progress 70 % (3 MB)
38 06:54:26.912177 progress 75 % (3 MB)
39 06:54:26.913704 progress 80 % (3 MB)
40 06:54:26.915433 progress 85 % (3 MB)
41 06:54:26.916848 progress 90 % (4 MB)
42 06:54:26.918226 progress 95 % (4 MB)
43 06:54:26.919616 progress 100 % (4 MB)
44 06:54:26.919784 4 MB downloaded in 0.06 s (75.02 MB/s)
45 06:54:26.919950 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:54:26.920214 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:54:26.920309 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:54:26.920401 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:54:26.920560 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 06:54:26.920638 saving as /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/kernel/Image
52 06:54:26.920707 total size: 51532288 (49 MB)
53 06:54:26.920776 No compression specified
54 06:54:26.921879 progress 0 % (0 MB)
55 06:54:26.935285 progress 5 % (2 MB)
56 06:54:26.948615 progress 10 % (4 MB)
57 06:54:26.962129 progress 15 % (7 MB)
58 06:54:26.975592 progress 20 % (9 MB)
59 06:54:26.988895 progress 25 % (12 MB)
60 06:54:27.002249 progress 30 % (14 MB)
61 06:54:27.015656 progress 35 % (17 MB)
62 06:54:27.028940 progress 40 % (19 MB)
63 06:54:27.042105 progress 45 % (22 MB)
64 06:54:27.055627 progress 50 % (24 MB)
65 06:54:27.068828 progress 55 % (27 MB)
66 06:54:27.082209 progress 60 % (29 MB)
67 06:54:27.095529 progress 65 % (31 MB)
68 06:54:27.108663 progress 70 % (34 MB)
69 06:54:27.121953 progress 75 % (36 MB)
70 06:54:27.135043 progress 80 % (39 MB)
71 06:54:27.147947 progress 85 % (41 MB)
72 06:54:27.161289 progress 90 % (44 MB)
73 06:54:27.174605 progress 95 % (46 MB)
74 06:54:27.187595 progress 100 % (49 MB)
75 06:54:27.187799 49 MB downloaded in 0.27 s (184.00 MB/s)
76 06:54:27.187948 end: 1.2.1 http-download (duration 00:00:00) [common]
78 06:54:27.188180 end: 1.2 download-retry (duration 00:00:00) [common]
79 06:54:27.188265 start: 1.3 download-retry (timeout 00:10:00) [common]
80 06:54:27.188352 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 06:54:27.188490 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 06:54:27.188588 saving as /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/dtb/mt8192-asurada-spherion-r0.dtb
83 06:54:27.188654 total size: 47278 (0 MB)
84 06:54:27.188715 No compression specified
85 06:54:27.189839 progress 69 % (0 MB)
86 06:54:27.190108 progress 100 % (0 MB)
87 06:54:27.190309 0 MB downloaded in 0.00 s (27.28 MB/s)
88 06:54:27.190446 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:54:27.190665 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:54:27.190751 start: 1.4 download-retry (timeout 00:10:00) [common]
92 06:54:27.190832 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 06:54:27.190941 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 06:54:27.191007 saving as /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/nfsrootfs/full.rootfs.tar
95 06:54:27.191067 total size: 200813988 (191 MB)
96 06:54:27.191127 Using unxz to decompress xz
97 06:54:27.195374 progress 0 % (0 MB)
98 06:54:27.719157 progress 5 % (9 MB)
99 06:54:28.226909 progress 10 % (19 MB)
100 06:54:28.805050 progress 15 % (28 MB)
101 06:54:29.177543 progress 20 % (38 MB)
102 06:54:29.496265 progress 25 % (47 MB)
103 06:54:30.080076 progress 30 % (57 MB)
104 06:54:30.619054 progress 35 % (67 MB)
105 06:54:31.205801 progress 40 % (76 MB)
106 06:54:31.755543 progress 45 % (86 MB)
107 06:54:32.333135 progress 50 % (95 MB)
108 06:54:32.951734 progress 55 % (105 MB)
109 06:54:33.603636 progress 60 % (114 MB)
110 06:54:33.720466 progress 65 % (124 MB)
111 06:54:33.858253 progress 70 % (134 MB)
112 06:54:33.953488 progress 75 % (143 MB)
113 06:54:34.024485 progress 80 % (153 MB)
114 06:54:34.092453 progress 85 % (162 MB)
115 06:54:34.192624 progress 90 % (172 MB)
116 06:54:34.472167 progress 95 % (181 MB)
117 06:54:35.051787 progress 100 % (191 MB)
118 06:54:35.057004 191 MB downloaded in 7.87 s (24.35 MB/s)
119 06:54:35.057303 end: 1.4.1 http-download (duration 00:00:08) [common]
121 06:54:35.057753 end: 1.4 download-retry (duration 00:00:08) [common]
122 06:54:35.057871 start: 1.5 download-retry (timeout 00:09:52) [common]
123 06:54:35.057986 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 06:54:35.058173 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 06:54:35.058267 saving as /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/modules/modules.tar
126 06:54:35.058356 total size: 8624064 (8 MB)
127 06:54:35.058449 Using unxz to decompress xz
128 06:54:35.063116 progress 0 % (0 MB)
129 06:54:35.083880 progress 5 % (0 MB)
130 06:54:35.106872 progress 10 % (0 MB)
131 06:54:35.130017 progress 15 % (1 MB)
132 06:54:35.153064 progress 20 % (1 MB)
133 06:54:35.177055 progress 25 % (2 MB)
134 06:54:35.202579 progress 30 % (2 MB)
135 06:54:35.228920 progress 35 % (2 MB)
136 06:54:35.252295 progress 40 % (3 MB)
137 06:54:35.276185 progress 45 % (3 MB)
138 06:54:35.300888 progress 50 % (4 MB)
139 06:54:35.325124 progress 55 % (4 MB)
140 06:54:35.349659 progress 60 % (4 MB)
141 06:54:35.376765 progress 65 % (5 MB)
142 06:54:35.401178 progress 70 % (5 MB)
143 06:54:35.424418 progress 75 % (6 MB)
144 06:54:35.451146 progress 80 % (6 MB)
145 06:54:35.476310 progress 85 % (7 MB)
146 06:54:35.500847 progress 90 % (7 MB)
147 06:54:35.531744 progress 95 % (7 MB)
148 06:54:35.559091 progress 100 % (8 MB)
149 06:54:35.563900 8 MB downloaded in 0.51 s (16.27 MB/s)
150 06:54:35.564196 end: 1.5.1 http-download (duration 00:00:01) [common]
152 06:54:35.564464 end: 1.5 download-retry (duration 00:00:01) [common]
153 06:54:35.564557 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 06:54:35.564656 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 06:54:39.033033 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12694862/extract-nfsrootfs-9tq3hp0n
156 06:54:39.033231 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 06:54:39.033341 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 06:54:39.033559 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww
159 06:54:39.033690 makedir: /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin
160 06:54:39.033791 makedir: /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/tests
161 06:54:39.033889 makedir: /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/results
162 06:54:39.033988 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-add-keys
163 06:54:39.034134 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-add-sources
164 06:54:39.034263 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-background-process-start
165 06:54:39.034389 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-background-process-stop
166 06:54:39.034514 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-common-functions
167 06:54:39.034637 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-echo-ipv4
168 06:54:39.034761 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-install-packages
169 06:54:39.034883 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-installed-packages
170 06:54:39.035005 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-os-build
171 06:54:39.035128 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-probe-channel
172 06:54:39.035250 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-probe-ip
173 06:54:39.035372 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-target-ip
174 06:54:39.035497 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-target-mac
175 06:54:39.035619 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-target-storage
176 06:54:39.035746 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-test-case
177 06:54:39.035872 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-test-event
178 06:54:39.035995 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-test-feedback
179 06:54:39.036119 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-test-raise
180 06:54:39.036242 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-test-reference
181 06:54:39.036366 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-test-runner
182 06:54:39.036489 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-test-set
183 06:54:39.036611 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-test-shell
184 06:54:39.036736 Updating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-add-keys (debian)
185 06:54:39.036886 Updating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-add-sources (debian)
186 06:54:39.037024 Updating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-install-packages (debian)
187 06:54:39.037161 Updating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-installed-packages (debian)
188 06:54:39.037297 Updating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/bin/lava-os-build (debian)
189 06:54:39.037417 Creating /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/environment
190 06:54:39.037628 LAVA metadata
191 06:54:39.037700 - LAVA_JOB_ID=12694862
192 06:54:39.037763 - LAVA_DISPATCHER_IP=192.168.201.1
193 06:54:39.037862 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 06:54:39.037926 skipped lava-vland-overlay
195 06:54:39.037998 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 06:54:39.038075 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 06:54:39.038147 skipped lava-multinode-overlay
198 06:54:39.038219 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 06:54:39.038297 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 06:54:39.038367 Loading test definitions
201 06:54:39.038455 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 06:54:39.038529 Using /lava-12694862 at stage 0
203 06:54:39.038809 uuid=12694862_1.6.2.3.1 testdef=None
204 06:54:39.038894 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 06:54:39.038977 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 06:54:39.039424 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 06:54:39.039639 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 06:54:39.040189 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 06:54:39.040416 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 06:54:39.041030 runner path: /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/0/tests/0_timesync-off test_uuid 12694862_1.6.2.3.1
213 06:54:39.041182 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 06:54:39.041404 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 06:54:39.041483 Using /lava-12694862 at stage 0
217 06:54:39.041633 Fetching tests from https://github.com/kernelci/test-definitions.git
218 06:54:39.041711 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/0/tests/1_kselftest-arm64'
219 06:54:45.776775 Running '/usr/bin/git checkout kernelci.org
220 06:54:45.926535 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 06:54:45.927294 uuid=12694862_1.6.2.3.5 testdef=None
222 06:54:45.927464 end: 1.6.2.3.5 git-repo-action (duration 00:00:07) [common]
224 06:54:45.927751 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 06:54:45.928527 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 06:54:45.928796 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 06:54:45.929924 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 06:54:45.930188 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 06:54:45.931142 runner path: /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/0/tests/1_kselftest-arm64 test_uuid 12694862_1.6.2.3.5
232 06:54:45.931244 BOARD='mt8192-asurada-spherion-r0'
233 06:54:45.931322 BRANCH='cip'
234 06:54:45.931403 SKIPFILE='/dev/null'
235 06:54:45.931481 SKIP_INSTALL='True'
236 06:54:45.931558 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 06:54:45.931659 TST_CASENAME=''
238 06:54:45.931755 TST_CMDFILES='arm64'
239 06:54:45.931955 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 06:54:45.932314 Creating lava-test-runner.conf files
242 06:54:45.932417 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694862/lava-overlay-_kw1asww/lava-12694862/0 for stage 0
243 06:54:45.932558 - 0_timesync-off
244 06:54:45.932663 - 1_kselftest-arm64
245 06:54:45.932806 end: 1.6.2.3 test-definition (duration 00:00:07) [common]
246 06:54:45.932933 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 06:54:53.638337 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 06:54:53.638487 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 06:54:53.638585 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 06:54:53.638688 end: 1.6.2 lava-overlay (duration 00:00:15) [common]
251 06:54:53.638811 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 06:54:53.766821 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 06:54:53.767198 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
254 06:54:53.767361 extracting modules file /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694862/extract-nfsrootfs-9tq3hp0n
255 06:54:53.992499 extracting modules file /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694862/extract-overlay-ramdisk-8452abxf/ramdisk
256 06:54:54.219889 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 06:54:54.220045 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 06:54:54.220137 [common] Applying overlay to NFS
259 06:54:54.220208 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694862/compress-overlay-sjsewf0r/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694862/extract-nfsrootfs-9tq3hp0n
260 06:54:55.144499 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 06:54:55.144660 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 06:54:55.144755 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 06:54:55.144849 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 06:54:55.144932 Building ramdisk /var/lib/lava/dispatcher/tmp/12694862/extract-overlay-ramdisk-8452abxf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694862/extract-overlay-ramdisk-8452abxf/ramdisk
265 06:54:55.475250 >> 119430 blocks
266 06:54:57.448452 rename /var/lib/lava/dispatcher/tmp/12694862/extract-overlay-ramdisk-8452abxf/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/ramdisk/ramdisk.cpio.gz
267 06:54:57.448901 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 06:54:57.449037 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 06:54:57.449143 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 06:54:57.449251 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/kernel/Image'
271 06:55:10.300789 Returned 0 in 12 seconds
272 06:55:10.401409 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/kernel/image.itb
273 06:55:10.785008 output: FIT description: Kernel Image image with one or more FDT blobs
274 06:55:10.785413 output: Created: Sat Feb 3 06:55:10 2024
275 06:55:10.785562 output: Image 0 (kernel-1)
276 06:55:10.785667 output: Description:
277 06:55:10.785762 output: Created: Sat Feb 3 06:55:10 2024
278 06:55:10.785854 output: Type: Kernel Image
279 06:55:10.785949 output: Compression: lzma compressed
280 06:55:10.786045 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
281 06:55:10.786136 output: Architecture: AArch64
282 06:55:10.786223 output: OS: Linux
283 06:55:10.786310 output: Load Address: 0x00000000
284 06:55:10.786396 output: Entry Point: 0x00000000
285 06:55:10.786481 output: Hash algo: crc32
286 06:55:10.786569 output: Hash value: 380e7c3c
287 06:55:10.786656 output: Image 1 (fdt-1)
288 06:55:10.786774 output: Description: mt8192-asurada-spherion-r0
289 06:55:10.786856 output: Created: Sat Feb 3 06:55:10 2024
290 06:55:10.786939 output: Type: Flat Device Tree
291 06:55:10.787021 output: Compression: uncompressed
292 06:55:10.787103 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 06:55:10.787185 output: Architecture: AArch64
294 06:55:10.787266 output: Hash algo: crc32
295 06:55:10.787347 output: Hash value: cc4352de
296 06:55:10.787429 output: Image 2 (ramdisk-1)
297 06:55:10.787510 output: Description: unavailable
298 06:55:10.787595 output: Created: Sat Feb 3 06:55:10 2024
299 06:55:10.787677 output: Type: RAMDisk Image
300 06:55:10.787759 output: Compression: Unknown Compression
301 06:55:10.787840 output: Data Size: 17801501 Bytes = 17384.28 KiB = 16.98 MiB
302 06:55:10.787922 output: Architecture: AArch64
303 06:55:10.788007 output: OS: Linux
304 06:55:10.788088 output: Load Address: unavailable
305 06:55:10.788169 output: Entry Point: unavailable
306 06:55:10.788250 output: Hash algo: crc32
307 06:55:10.788331 output: Hash value: 18aa6650
308 06:55:10.788412 output: Default Configuration: 'conf-1'
309 06:55:10.788496 output: Configuration 0 (conf-1)
310 06:55:10.788552 output: Description: mt8192-asurada-spherion-r0
311 06:55:10.788605 output: Kernel: kernel-1
312 06:55:10.788658 output: Init Ramdisk: ramdisk-1
313 06:55:10.788710 output: FDT: fdt-1
314 06:55:10.788761 output: Loadables: kernel-1
315 06:55:10.788813 output:
316 06:55:10.789020 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 06:55:10.789142 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 06:55:10.789288 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 06:55:10.789411 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 06:55:10.789568 No LXC device requested
321 06:55:10.789750 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 06:55:10.789939 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 06:55:10.790085 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 06:55:10.790214 Checking files for TFTP limit of 4294967296 bytes.
325 06:55:10.791091 end: 1 tftp-deploy (duration 00:00:44) [common]
326 06:55:10.791270 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 06:55:10.791429 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 06:55:10.791642 substitutions:
329 06:55:10.791767 - {DTB}: 12694862/tftp-deploy-b_wrejdt/dtb/mt8192-asurada-spherion-r0.dtb
330 06:55:10.791890 - {INITRD}: 12694862/tftp-deploy-b_wrejdt/ramdisk/ramdisk.cpio.gz
331 06:55:10.792003 - {KERNEL}: 12694862/tftp-deploy-b_wrejdt/kernel/Image
332 06:55:10.792120 - {LAVA_MAC}: None
333 06:55:10.792235 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12694862/extract-nfsrootfs-9tq3hp0n
334 06:55:10.792344 - {NFS_SERVER_IP}: 192.168.201.1
335 06:55:10.792458 - {PRESEED_CONFIG}: None
336 06:55:10.792575 - {PRESEED_LOCAL}: None
337 06:55:10.792697 - {RAMDISK}: 12694862/tftp-deploy-b_wrejdt/ramdisk/ramdisk.cpio.gz
338 06:55:10.792816 - {ROOT_PART}: None
339 06:55:10.792936 - {ROOT}: None
340 06:55:10.793058 - {SERVER_IP}: 192.168.201.1
341 06:55:10.793179 - {TEE}: None
342 06:55:10.793299 Parsed boot commands:
343 06:55:10.793417 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 06:55:10.793764 Parsed boot commands: tftpboot 192.168.201.1 12694862/tftp-deploy-b_wrejdt/kernel/image.itb 12694862/tftp-deploy-b_wrejdt/kernel/cmdline
345 06:55:10.793926 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 06:55:10.794084 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 06:55:10.794251 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 06:55:10.794417 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 06:55:10.794561 Not connected, no need to disconnect.
350 06:55:10.794712 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 06:55:10.794869 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 06:55:10.795005 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 06:55:10.800370 Setting prompt string to ['lava-test: # ']
354 06:55:10.800941 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 06:55:10.801139 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 06:55:10.801324 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 06:55:10.801523 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 06:55:10.801953 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 06:55:15.948128 >> Command sent successfully.
360 06:55:15.959685 Returned 0 in 5 seconds
361 06:55:16.060679 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 06:55:16.061129 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 06:55:16.061277 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 06:55:16.061410 Setting prompt string to 'Starting depthcharge on Spherion...'
366 06:55:16.061541 Changing prompt to 'Starting depthcharge on Spherion...'
367 06:55:16.061644 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 06:55:16.062032 [Enter `^Ec?' for help]
369 06:55:16.225502
370 06:55:16.226129
371 06:55:16.226535 F0: 102B 0000
372 06:55:16.226892
373 06:55:16.227356 F3: 1001 0000 [0200]
374 06:55:16.227708
375 06:55:16.229028 F3: 1001 0000
376 06:55:16.229550
377 06:55:16.229938 F7: 102D 0000
378 06:55:16.230359
379 06:55:16.230717 F1: 0000 0000
380 06:55:16.231172
381 06:55:16.232933 V0: 0000 0000 [0001]
382 06:55:16.233613
383 06:55:16.234163 00: 0007 8000
384 06:55:16.234617
385 06:55:16.237157 01: 0000 0000
386 06:55:16.237728
387 06:55:16.238079 BP: 0C00 0209 [0000]
388 06:55:16.238403
389 06:55:16.238707 G0: 1182 0000
390 06:55:16.239009
391 06:55:16.240377 EC: 0000 0021 [4000]
392 06:55:16.240824
393 06:55:16.241218 S7: 0000 0000 [0000]
394 06:55:16.244106
395 06:55:16.244619 CC: 0000 0000 [0001]
396 06:55:16.244972
397 06:55:16.247460 T0: 0000 0040 [010F]
398 06:55:16.248054
399 06:55:16.248412 Jump to BL
400 06:55:16.248734
401 06:55:16.271908
402 06:55:16.272436
403 06:55:16.272775
404 06:55:16.278937 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 06:55:16.282260 ARM64: Exception handlers installed.
406 06:55:16.285826 ARM64: Testing exception
407 06:55:16.289273 ARM64: Done test exception
408 06:55:16.296760 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 06:55:16.307892 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 06:55:16.314209 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 06:55:16.324634 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 06:55:16.331069 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 06:55:16.337750 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 06:55:16.349143 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 06:55:16.356041 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 06:55:16.374795 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 06:55:16.378209 WDT: Last reset was cold boot
418 06:55:16.381862 SPI1(PAD0) initialized at 2873684 Hz
419 06:55:16.384774 SPI5(PAD0) initialized at 992727 Hz
420 06:55:16.388755 VBOOT: Loading verstage.
421 06:55:16.394460 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 06:55:16.398286 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 06:55:16.401314 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 06:55:16.404446 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 06:55:16.412465 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 06:55:16.418836 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 06:55:16.430091 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 06:55:16.430678
429 06:55:16.431056
430 06:55:16.439955 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 06:55:16.443725 ARM64: Exception handlers installed.
432 06:55:16.446430 ARM64: Testing exception
433 06:55:16.447044 ARM64: Done test exception
434 06:55:16.453209 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 06:55:16.456740 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 06:55:16.471187 Probing TPM: . done!
437 06:55:16.471771 TPM ready after 0 ms
438 06:55:16.477742 Connected to device vid:did:rid of 1ae0:0028:00
439 06:55:16.525080 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 06:55:16.525965 Initialized TPM device CR50 revision 0
441 06:55:16.536504 tlcl_send_startup: Startup return code is 0
442 06:55:16.537087 TPM: setup succeeded
443 06:55:16.548047 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 06:55:16.556846 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 06:55:16.569683 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 06:55:16.578026 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 06:55:16.581595 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 06:55:16.584887 in-header: 03 07 00 00 08 00 00 00
449 06:55:16.589159 in-data: aa e4 47 04 13 02 00 00
450 06:55:16.592494 Chrome EC: UHEPI supported
451 06:55:16.599759 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 06:55:16.603203 in-header: 03 9d 00 00 08 00 00 00
453 06:55:16.606637 in-data: 10 20 20 08 00 00 00 00
454 06:55:16.607072 Phase 1
455 06:55:16.610383 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 06:55:16.617581 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 06:55:16.621367 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 06:55:16.624834 Recovery requested (1009000e)
459 06:55:16.633576 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 06:55:16.638738 tlcl_extend: response is 0
461 06:55:16.646417 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 06:55:16.652194 tlcl_extend: response is 0
463 06:55:16.658442 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 06:55:16.679639 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 06:55:16.687145 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 06:55:16.687670
467 06:55:16.688016
468 06:55:16.694463 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 06:55:16.698435 ARM64: Exception handlers installed.
470 06:55:16.702366 ARM64: Testing exception
471 06:55:16.705363 ARM64: Done test exception
472 06:55:16.724804 pmic_efuse_setting: Set efuses in 11 msecs
473 06:55:16.728565 pmwrap_interface_init: Select PMIF_VLD_RDY
474 06:55:16.731889 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 06:55:16.739574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 06:55:16.743431 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 06:55:16.747175 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 06:55:16.754201 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 06:55:16.757850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 06:55:16.761705 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 06:55:16.768964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 06:55:16.772502 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 06:55:16.775466 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 06:55:16.782027 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 06:55:16.785734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 06:55:16.789079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 06:55:16.796638 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 06:55:16.803205 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 06:55:16.809664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 06:55:16.813194 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 06:55:16.820083 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 06:55:16.827174 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 06:55:16.830562 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 06:55:16.837471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 06:55:16.841567 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 06:55:16.848092 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 06:55:16.851632 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 06:55:16.858429 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 06:55:16.865070 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 06:55:16.868121 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 06:55:16.874470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 06:55:16.878029 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 06:55:16.885157 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 06:55:16.888802 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 06:55:16.892109 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 06:55:16.899541 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 06:55:16.902983 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 06:55:16.906772 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 06:55:16.913835 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 06:55:16.917507 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 06:55:16.924231 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 06:55:16.927785 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 06:55:16.931092 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 06:55:16.937865 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 06:55:16.940855 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 06:55:16.944381 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 06:55:16.951025 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 06:55:16.954290 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 06:55:16.957487 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 06:55:16.961009 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 06:55:16.968026 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 06:55:16.971146 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 06:55:16.974618 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 06:55:16.977894 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 06:55:16.987584 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 06:55:16.994435 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 06:55:17.000846 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 06:55:17.007495 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 06:55:17.017597 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 06:55:17.020912 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 06:55:17.024126 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 06:55:17.030778 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 06:55:17.037581 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2a
534 06:55:17.044077 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 06:55:17.047430 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 06:55:17.050887 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 06:55:17.062020 [RTC]rtc_get_frequency_meter,154: input=15, output=795
538 06:55:17.065386 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 06:55:17.071973 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 06:55:17.075090 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 06:55:17.078574 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 06:55:17.081469 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 06:55:17.085125 ADC[4]: Raw value=898890 ID=7
544 06:55:17.088807 ADC[3]: Raw value=212700 ID=1
545 06:55:17.091842 RAM Code: 0x71
546 06:55:17.095019 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 06:55:17.098143 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 06:55:17.108616 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 06:55:17.115407 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 06:55:17.118704 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 06:55:17.122522 in-header: 03 07 00 00 08 00 00 00
552 06:55:17.125437 in-data: aa e4 47 04 13 02 00 00
553 06:55:17.128767 Chrome EC: UHEPI supported
554 06:55:17.132678 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 06:55:17.136499 in-header: 03 d5 00 00 08 00 00 00
556 06:55:17.140254 in-data: 98 20 60 08 00 00 00 00
557 06:55:17.144312 MRC: failed to locate region type 0.
558 06:55:17.151728 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 06:55:17.155264 DRAM-K: Running full calibration
560 06:55:17.158918 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 06:55:17.162045 header.status = 0x0
562 06:55:17.165581 header.version = 0x6 (expected: 0x6)
563 06:55:17.168910 header.size = 0xd00 (expected: 0xd00)
564 06:55:17.169343 header.flags = 0x0
565 06:55:17.176027 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 06:55:17.194001 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
567 06:55:17.201097 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 06:55:17.204234 dram_init: ddr_geometry: 2
569 06:55:17.207597 [EMI] MDL number = 2
570 06:55:17.208152 [EMI] Get MDL freq = 0
571 06:55:17.210694 dram_init: ddr_type: 0
572 06:55:17.211136 is_discrete_lpddr4: 1
573 06:55:17.214106 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 06:55:17.214548
575 06:55:17.214892
576 06:55:17.217281 [Bian_co] ETT version 0.0.0.1
577 06:55:17.224241 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 06:55:17.224716
579 06:55:17.227610 dramc_set_vcore_voltage set vcore to 650000
580 06:55:17.228089 Read voltage for 800, 4
581 06:55:17.230671 Vio18 = 0
582 06:55:17.231108 Vcore = 650000
583 06:55:17.231589 Vdram = 0
584 06:55:17.234269 Vddq = 0
585 06:55:17.234708 Vmddr = 0
586 06:55:17.237739 dram_init: config_dvfs: 1
587 06:55:17.241084 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 06:55:17.247499 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 06:55:17.251375 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 06:55:17.254188 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 06:55:17.257902 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 06:55:17.260813 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 06:55:17.264319 MEM_TYPE=3, freq_sel=18
594 06:55:17.267524 sv_algorithm_assistance_LP4_1600
595 06:55:17.270942 ============ PULL DRAM RESETB DOWN ============
596 06:55:17.274198 ========== PULL DRAM RESETB DOWN end =========
597 06:55:17.280759 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 06:55:17.284895 ===================================
599 06:55:17.285435 LPDDR4 DRAM CONFIGURATION
600 06:55:17.287724 ===================================
601 06:55:17.290963 EX_ROW_EN[0] = 0x0
602 06:55:17.294338 EX_ROW_EN[1] = 0x0
603 06:55:17.294874 LP4Y_EN = 0x0
604 06:55:17.297889 WORK_FSP = 0x0
605 06:55:17.298442 WL = 0x2
606 06:55:17.302112 RL = 0x2
607 06:55:17.302659 BL = 0x2
608 06:55:17.305194 RPST = 0x0
609 06:55:17.305663 RD_PRE = 0x0
610 06:55:17.306020 WR_PRE = 0x1
611 06:55:17.309087 WR_PST = 0x0
612 06:55:17.309915 DBI_WR = 0x0
613 06:55:17.312658 DBI_RD = 0x0
614 06:55:17.313096 OTF = 0x1
615 06:55:17.316844 ===================================
616 06:55:17.320652 ===================================
617 06:55:17.321202 ANA top config
618 06:55:17.324488 ===================================
619 06:55:17.328030 DLL_ASYNC_EN = 0
620 06:55:17.331617 ALL_SLAVE_EN = 1
621 06:55:17.332060 NEW_RANK_MODE = 1
622 06:55:17.335092 DLL_IDLE_MODE = 1
623 06:55:17.338916 LP45_APHY_COMB_EN = 1
624 06:55:17.339360 TX_ODT_DIS = 1
625 06:55:17.342481 NEW_8X_MODE = 1
626 06:55:17.346472 ===================================
627 06:55:17.349965 ===================================
628 06:55:17.354184 data_rate = 1600
629 06:55:17.354635 CKR = 1
630 06:55:17.357856 DQ_P2S_RATIO = 8
631 06:55:17.361347 ===================================
632 06:55:17.365074 CA_P2S_RATIO = 8
633 06:55:17.368685 DQ_CA_OPEN = 0
634 06:55:17.368962 DQ_SEMI_OPEN = 0
635 06:55:17.372203 CA_SEMI_OPEN = 0
636 06:55:17.375679 CA_FULL_RATE = 0
637 06:55:17.379377 DQ_CKDIV4_EN = 1
638 06:55:17.379562 CA_CKDIV4_EN = 1
639 06:55:17.383516 CA_PREDIV_EN = 0
640 06:55:17.386888 PH8_DLY = 0
641 06:55:17.389938 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 06:55:17.390095 DQ_AAMCK_DIV = 4
643 06:55:17.393487 CA_AAMCK_DIV = 4
644 06:55:17.396929 CA_ADMCK_DIV = 4
645 06:55:17.400437 DQ_TRACK_CA_EN = 0
646 06:55:17.404023 CA_PICK = 800
647 06:55:17.406986 CA_MCKIO = 800
648 06:55:17.407156 MCKIO_SEMI = 0
649 06:55:17.410021 PLL_FREQ = 3068
650 06:55:17.414011 DQ_UI_PI_RATIO = 32
651 06:55:17.417113 CA_UI_PI_RATIO = 0
652 06:55:17.420510 ===================================
653 06:55:17.423834 ===================================
654 06:55:17.426946 memory_type:LPDDR4
655 06:55:17.427116 GP_NUM : 10
656 06:55:17.430562 SRAM_EN : 1
657 06:55:17.433699 MD32_EN : 0
658 06:55:17.437231 ===================================
659 06:55:17.437406 [ANA_INIT] >>>>>>>>>>>>>>
660 06:55:17.440371 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 06:55:17.443598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 06:55:17.446727 ===================================
663 06:55:17.450155 data_rate = 1600,PCW = 0X7600
664 06:55:17.453734 ===================================
665 06:55:17.456592 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 06:55:17.463728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 06:55:17.467111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 06:55:17.473708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 06:55:17.476833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 06:55:17.480516 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 06:55:17.480742 [ANA_INIT] flow start
672 06:55:17.484675 [ANA_INIT] PLL >>>>>>>>
673 06:55:17.485044 [ANA_INIT] PLL <<<<<<<<
674 06:55:17.487856 [ANA_INIT] MIDPI >>>>>>>>
675 06:55:17.492230 [ANA_INIT] MIDPI <<<<<<<<
676 06:55:17.492681 [ANA_INIT] DLL >>>>>>>>
677 06:55:17.495484 [ANA_INIT] flow end
678 06:55:17.499275 ============ LP4 DIFF to SE enter ============
679 06:55:17.503260 ============ LP4 DIFF to SE exit ============
680 06:55:17.506899 [ANA_INIT] <<<<<<<<<<<<<
681 06:55:17.510528 [Flow] Enable top DCM control >>>>>
682 06:55:17.511068 [Flow] Enable top DCM control <<<<<
683 06:55:17.514150 Enable DLL master slave shuffle
684 06:55:17.521926 ==============================================================
685 06:55:17.522370 Gating Mode config
686 06:55:17.528684 ==============================================================
687 06:55:17.529242 Config description:
688 06:55:17.538549 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 06:55:17.545258 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 06:55:17.552063 SELPH_MODE 0: By rank 1: By Phase
691 06:55:17.555471 ==============================================================
692 06:55:17.558614 GAT_TRACK_EN = 1
693 06:55:17.561775 RX_GATING_MODE = 2
694 06:55:17.565332 RX_GATING_TRACK_MODE = 2
695 06:55:17.568342 SELPH_MODE = 1
696 06:55:17.571600 PICG_EARLY_EN = 1
697 06:55:17.575243 VALID_LAT_VALUE = 1
698 06:55:17.581536 ==============================================================
699 06:55:17.585567 Enter into Gating configuration >>>>
700 06:55:17.586108 Exit from Gating configuration <<<<
701 06:55:17.588635 Enter into DVFS_PRE_config >>>>>
702 06:55:17.602024 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 06:55:17.605215 Exit from DVFS_PRE_config <<<<<
704 06:55:17.608473 Enter into PICG configuration >>>>
705 06:55:17.611975 Exit from PICG configuration <<<<
706 06:55:17.612419 [RX_INPUT] configuration >>>>>
707 06:55:17.615069 [RX_INPUT] configuration <<<<<
708 06:55:17.622032 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 06:55:17.624991 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 06:55:17.632707 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 06:55:17.639847 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 06:55:17.646627 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 06:55:17.650385 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 06:55:17.653955 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 06:55:17.658049 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 06:55:17.661518 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 06:55:17.668521 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 06:55:17.672355 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 06:55:17.675991 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 06:55:17.679648 ===================================
721 06:55:17.683194 LPDDR4 DRAM CONFIGURATION
722 06:55:17.687163 ===================================
723 06:55:17.687749 EX_ROW_EN[0] = 0x0
724 06:55:17.690550 EX_ROW_EN[1] = 0x0
725 06:55:17.690985 LP4Y_EN = 0x0
726 06:55:17.694209 WORK_FSP = 0x0
727 06:55:17.694746 WL = 0x2
728 06:55:17.697878 RL = 0x2
729 06:55:17.698416 BL = 0x2
730 06:55:17.698763 RPST = 0x0
731 06:55:17.701698 RD_PRE = 0x0
732 06:55:17.702232 WR_PRE = 0x1
733 06:55:17.705194 WR_PST = 0x0
734 06:55:17.705762 DBI_WR = 0x0
735 06:55:17.709007 DBI_RD = 0x0
736 06:55:17.709581 OTF = 0x1
737 06:55:17.712722 ===================================
738 06:55:17.716371 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 06:55:17.720026 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 06:55:17.727441 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 06:55:17.728076 ===================================
742 06:55:17.730942 LPDDR4 DRAM CONFIGURATION
743 06:55:17.735081 ===================================
744 06:55:17.735521 EX_ROW_EN[0] = 0x10
745 06:55:17.738565 EX_ROW_EN[1] = 0x0
746 06:55:17.742285 LP4Y_EN = 0x0
747 06:55:17.742725 WORK_FSP = 0x0
748 06:55:17.743073 WL = 0x2
749 06:55:17.745451 RL = 0x2
750 06:55:17.745922 BL = 0x2
751 06:55:17.749213 RPST = 0x0
752 06:55:17.749690 RD_PRE = 0x0
753 06:55:17.753090 WR_PRE = 0x1
754 06:55:17.753669 WR_PST = 0x0
755 06:55:17.756876 DBI_WR = 0x0
756 06:55:17.757439 DBI_RD = 0x0
757 06:55:17.760185 OTF = 0x1
758 06:55:17.764169 ===================================
759 06:55:17.767382 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 06:55:17.772607 nWR fixed to 40
761 06:55:17.776101 [ModeRegInit_LP4] CH0 RK0
762 06:55:17.776602 [ModeRegInit_LP4] CH0 RK1
763 06:55:17.779961 [ModeRegInit_LP4] CH1 RK0
764 06:55:17.780442 [ModeRegInit_LP4] CH1 RK1
765 06:55:17.783562 match AC timing 13
766 06:55:17.787563 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 06:55:17.791326 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 06:55:17.794792 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 06:55:17.802756 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 06:55:17.806422 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 06:55:17.806901 [EMI DOE] emi_dcm 0
772 06:55:17.810279 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 06:55:17.813965 ==
774 06:55:17.814465 Dram Type= 6, Freq= 0, CH_0, rank 0
775 06:55:17.820912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 06:55:17.821354 ==
777 06:55:17.824849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 06:55:17.832039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 06:55:17.840136 [CA 0] Center 38 (7~69) winsize 63
780 06:55:17.844119 [CA 1] Center 37 (7~68) winsize 62
781 06:55:17.847997 [CA 2] Center 35 (5~66) winsize 62
782 06:55:17.852205 [CA 3] Center 35 (5~66) winsize 62
783 06:55:17.856009 [CA 4] Center 34 (4~65) winsize 62
784 06:55:17.856707 [CA 5] Center 34 (3~65) winsize 63
785 06:55:17.857080
786 06:55:17.859298 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 06:55:17.859739
788 06:55:17.863376 [CATrainingPosCal] consider 1 rank data
789 06:55:17.866995 u2DelayCellTimex100 = 270/100 ps
790 06:55:17.870455 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 06:55:17.874515 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 06:55:17.877923 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 06:55:17.881520 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 06:55:17.885397 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 06:55:17.889022 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
796 06:55:17.889716
797 06:55:17.892556 CA PerBit enable=1, Macro0, CA PI delay=34
798 06:55:17.892999
799 06:55:17.896717 [CBTSetCACLKResult] CA Dly = 34
800 06:55:17.899772 CS Dly: 6 (0~37)
801 06:55:17.900385 ==
802 06:55:17.900792 Dram Type= 6, Freq= 0, CH_0, rank 1
803 06:55:17.904323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 06:55:17.907584 ==
805 06:55:17.911336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 06:55:17.918469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 06:55:17.926491 [CA 0] Center 38 (7~69) winsize 63
808 06:55:17.929523 [CA 1] Center 37 (7~68) winsize 62
809 06:55:17.932981 [CA 2] Center 35 (5~66) winsize 62
810 06:55:17.936707 [CA 3] Center 35 (5~66) winsize 62
811 06:55:17.939703 [CA 4] Center 34 (4~65) winsize 62
812 06:55:17.942795 [CA 5] Center 34 (4~64) winsize 61
813 06:55:17.943327
814 06:55:17.946380 [CmdBusTrainingLP45] Vref(ca) range 1: 32
815 06:55:17.946916
816 06:55:17.949910 [CATrainingPosCal] consider 2 rank data
817 06:55:17.953272 u2DelayCellTimex100 = 270/100 ps
818 06:55:17.956345 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 06:55:17.959806 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 06:55:17.966458 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 06:55:17.969521 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 06:55:17.972963 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 06:55:17.976304 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
824 06:55:17.976844
825 06:55:17.979405 CA PerBit enable=1, Macro0, CA PI delay=34
826 06:55:17.979843
827 06:55:17.983157 [CBTSetCACLKResult] CA Dly = 34
828 06:55:17.983648 CS Dly: 6 (0~38)
829 06:55:17.984002
830 06:55:17.986124 ----->DramcWriteLeveling(PI) begin...
831 06:55:17.989684 ==
832 06:55:17.990229 Dram Type= 6, Freq= 0, CH_0, rank 0
833 06:55:17.996431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 06:55:17.996971 ==
835 06:55:17.999623 Write leveling (Byte 0): 34 => 34
836 06:55:18.003046 Write leveling (Byte 1): 29 => 29
837 06:55:18.006246 DramcWriteLeveling(PI) end<-----
838 06:55:18.006678
839 06:55:18.007015 ==
840 06:55:18.009607 Dram Type= 6, Freq= 0, CH_0, rank 0
841 06:55:18.012700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 06:55:18.013259 ==
843 06:55:18.016524 [Gating] SW mode calibration
844 06:55:18.023049 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 06:55:18.026022 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 06:55:18.033309 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 06:55:18.036576 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 06:55:18.039451 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
849 06:55:18.046346 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 06:55:18.049852 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 06:55:18.052999 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 06:55:18.059923 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 06:55:18.063265 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 06:55:18.066849 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 06:55:18.070215 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 06:55:18.078130 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 06:55:18.081522 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 06:55:18.085046 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 06:55:18.088122 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 06:55:18.095878 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 06:55:18.098780 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 06:55:18.102387 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 06:55:18.105883 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
864 06:55:18.112379 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
865 06:55:18.115288 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 06:55:18.118596 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 06:55:18.125555 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 06:55:18.129152 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 06:55:18.132477 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 06:55:18.138900 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 06:55:18.142002 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 06:55:18.146051 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 06:55:18.152733 0 9 12 | B1->B0 | 2929 3333 | 0 1 | (0 0) (1 1)
874 06:55:18.156030 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 06:55:18.159351 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 06:55:18.162404 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 06:55:18.169179 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 06:55:18.172181 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 06:55:18.175809 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 06:55:18.181800 0 10 8 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 0)
881 06:55:18.185226 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
882 06:55:18.188739 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 06:55:18.195513 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 06:55:18.198734 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 06:55:18.202144 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 06:55:18.209197 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 06:55:18.212567 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 06:55:18.215317 0 11 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
889 06:55:18.221977 0 11 12 | B1->B0 | 3030 4545 | 0 0 | (1 1) (0 0)
890 06:55:18.225566 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
891 06:55:18.228495 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 06:55:18.235254 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 06:55:18.238507 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 06:55:18.241964 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 06:55:18.248428 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 06:55:18.252025 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 06:55:18.254913 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 06:55:18.261821 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 06:55:18.265221 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 06:55:18.269173 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 06:55:18.275619 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 06:55:18.278349 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 06:55:18.281419 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 06:55:18.288605 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 06:55:18.291951 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 06:55:18.295042 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 06:55:18.301984 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 06:55:18.304864 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 06:55:18.308684 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 06:55:18.311744 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 06:55:18.318369 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 06:55:18.321766 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
913 06:55:18.324871 Total UI for P1: 0, mck2ui 16
914 06:55:18.328660 best dqsien dly found for B0: ( 0, 14, 6)
915 06:55:18.331883 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
916 06:55:18.335078 Total UI for P1: 0, mck2ui 16
917 06:55:18.338403 best dqsien dly found for B1: ( 0, 14, 10)
918 06:55:18.341588 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
919 06:55:18.345258 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
920 06:55:18.345754
921 06:55:18.351819 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
922 06:55:18.355494 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
923 06:55:18.358726 [Gating] SW calibration Done
924 06:55:18.359262 ==
925 06:55:18.362175 Dram Type= 6, Freq= 0, CH_0, rank 0
926 06:55:18.365291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 06:55:18.365855 ==
928 06:55:18.366207 RX Vref Scan: 0
929 06:55:18.366529
930 06:55:18.368329 RX Vref 0 -> 0, step: 1
931 06:55:18.368761
932 06:55:18.371587 RX Delay -130 -> 252, step: 16
933 06:55:18.375141 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
934 06:55:18.378228 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
935 06:55:18.384851 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
936 06:55:18.388540 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
937 06:55:18.392015 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
938 06:55:18.395351 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
939 06:55:18.398537 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
940 06:55:18.401991 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
941 06:55:18.408274 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
942 06:55:18.411742 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
943 06:55:18.414997 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
944 06:55:18.418327 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
945 06:55:18.425262 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
946 06:55:18.428671 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
947 06:55:18.432017 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
948 06:55:18.435056 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
949 06:55:18.435491 ==
950 06:55:18.438267 Dram Type= 6, Freq= 0, CH_0, rank 0
951 06:55:18.441817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
952 06:55:18.444964 ==
953 06:55:18.445392 DQS Delay:
954 06:55:18.445787 DQS0 = 0, DQS1 = 0
955 06:55:18.448143 DQM Delay:
956 06:55:18.448574 DQM0 = 84, DQM1 = 70
957 06:55:18.451835 DQ Delay:
958 06:55:18.455367 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
959 06:55:18.455901 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
960 06:55:18.458085 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
961 06:55:18.462022 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
962 06:55:18.465206
963 06:55:18.465769
964 06:55:18.466121 ==
965 06:55:18.468537 Dram Type= 6, Freq= 0, CH_0, rank 0
966 06:55:18.471541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 06:55:18.471979 ==
968 06:55:18.472320
969 06:55:18.472636
970 06:55:18.475557 TX Vref Scan disable
971 06:55:18.476202 == TX Byte 0 ==
972 06:55:18.479059 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
973 06:55:18.485623 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
974 06:55:18.486155 == TX Byte 1 ==
975 06:55:18.489184 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
976 06:55:18.495608 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
977 06:55:18.496141 ==
978 06:55:18.498974 Dram Type= 6, Freq= 0, CH_0, rank 0
979 06:55:18.502402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 06:55:18.502937 ==
981 06:55:18.515424 TX Vref=22, minBit 1, minWin=27, winSum=438
982 06:55:18.518734 TX Vref=24, minBit 5, minWin=27, winSum=439
983 06:55:18.522246 TX Vref=26, minBit 5, minWin=27, winSum=444
984 06:55:18.525859 TX Vref=28, minBit 10, minWin=27, winSum=445
985 06:55:18.529281 TX Vref=30, minBit 10, minWin=27, winSum=443
986 06:55:18.535610 TX Vref=32, minBit 4, minWin=27, winSum=441
987 06:55:18.539217 [TxChooseVref] Worse bit 10, Min win 27, Win sum 445, Final Vref 28
988 06:55:18.539651
989 06:55:18.542264 Final TX Range 1 Vref 28
990 06:55:18.542696
991 06:55:18.543035 ==
992 06:55:18.545286 Dram Type= 6, Freq= 0, CH_0, rank 0
993 06:55:18.549037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
994 06:55:18.552095 ==
995 06:55:18.552631
996 06:55:18.552973
997 06:55:18.553296 TX Vref Scan disable
998 06:55:18.556023 == TX Byte 0 ==
999 06:55:18.559104 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1000 06:55:18.562666 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1001 06:55:18.566378 == TX Byte 1 ==
1002 06:55:18.569379 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1003 06:55:18.576099 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1004 06:55:18.576653
1005 06:55:18.577004 [DATLAT]
1006 06:55:18.577325 Freq=800, CH0 RK0
1007 06:55:18.577673
1008 06:55:18.579083 DATLAT Default: 0xa
1009 06:55:18.579541 0, 0xFFFF, sum = 0
1010 06:55:18.582507 1, 0xFFFF, sum = 0
1011 06:55:18.582948 2, 0xFFFF, sum = 0
1012 06:55:18.586225 3, 0xFFFF, sum = 0
1013 06:55:18.586762 4, 0xFFFF, sum = 0
1014 06:55:18.589319 5, 0xFFFF, sum = 0
1015 06:55:18.592799 6, 0xFFFF, sum = 0
1016 06:55:18.593335 7, 0xFFFF, sum = 0
1017 06:55:18.596128 8, 0xFFFF, sum = 0
1018 06:55:18.596670 9, 0x0, sum = 1
1019 06:55:18.597024 10, 0x0, sum = 2
1020 06:55:18.599526 11, 0x0, sum = 3
1021 06:55:18.600066 12, 0x0, sum = 4
1022 06:55:18.602730 best_step = 10
1023 06:55:18.603261
1024 06:55:18.603608 ==
1025 06:55:18.606150 Dram Type= 6, Freq= 0, CH_0, rank 0
1026 06:55:18.609506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1027 06:55:18.610041 ==
1028 06:55:18.612194 RX Vref Scan: 1
1029 06:55:18.612616
1030 06:55:18.612995 Set Vref Range= 32 -> 127
1031 06:55:18.615798
1032 06:55:18.616221 RX Vref 32 -> 127, step: 1
1033 06:55:18.616684
1034 06:55:18.618991 RX Delay -111 -> 252, step: 8
1035 06:55:18.619425
1036 06:55:18.622230 Set Vref, RX VrefLevel [Byte0]: 32
1037 06:55:18.625636 [Byte1]: 32
1038 06:55:18.626132
1039 06:55:18.629099 Set Vref, RX VrefLevel [Byte0]: 33
1040 06:55:18.632408 [Byte1]: 33
1041 06:55:18.636394
1042 06:55:18.636815 Set Vref, RX VrefLevel [Byte0]: 34
1043 06:55:18.639709 [Byte1]: 34
1044 06:55:18.644060
1045 06:55:18.644579 Set Vref, RX VrefLevel [Byte0]: 35
1046 06:55:18.647855 [Byte1]: 35
1047 06:55:18.652110
1048 06:55:18.652629 Set Vref, RX VrefLevel [Byte0]: 36
1049 06:55:18.655318 [Byte1]: 36
1050 06:55:18.659718
1051 06:55:18.660247 Set Vref, RX VrefLevel [Byte0]: 37
1052 06:55:18.662691 [Byte1]: 37
1053 06:55:18.667147
1054 06:55:18.667668 Set Vref, RX VrefLevel [Byte0]: 38
1055 06:55:18.670392 [Byte1]: 38
1056 06:55:18.674853
1057 06:55:18.675276 Set Vref, RX VrefLevel [Byte0]: 39
1058 06:55:18.677783 [Byte1]: 39
1059 06:55:18.682420
1060 06:55:18.682955 Set Vref, RX VrefLevel [Byte0]: 40
1061 06:55:18.685675 [Byte1]: 40
1062 06:55:18.689920
1063 06:55:18.690445 Set Vref, RX VrefLevel [Byte0]: 41
1064 06:55:18.693048 [Byte1]: 41
1065 06:55:18.697438
1066 06:55:18.697902 Set Vref, RX VrefLevel [Byte0]: 42
1067 06:55:18.701166 [Byte1]: 42
1068 06:55:18.705635
1069 06:55:18.706151 Set Vref, RX VrefLevel [Byte0]: 43
1070 06:55:18.708315 [Byte1]: 43
1071 06:55:18.712942
1072 06:55:18.713463 Set Vref, RX VrefLevel [Byte0]: 44
1073 06:55:18.716345 [Byte1]: 44
1074 06:55:18.720597
1075 06:55:18.721162 Set Vref, RX VrefLevel [Byte0]: 45
1076 06:55:18.724159 [Byte1]: 45
1077 06:55:18.728674
1078 06:55:18.729196 Set Vref, RX VrefLevel [Byte0]: 46
1079 06:55:18.731670 [Byte1]: 46
1080 06:55:18.736293
1081 06:55:18.736721 Set Vref, RX VrefLevel [Byte0]: 47
1082 06:55:18.739347 [Byte1]: 47
1083 06:55:18.743665
1084 06:55:18.744145 Set Vref, RX VrefLevel [Byte0]: 48
1085 06:55:18.746568 [Byte1]: 48
1086 06:55:18.751202
1087 06:55:18.751623 Set Vref, RX VrefLevel [Byte0]: 49
1088 06:55:18.754717 [Byte1]: 49
1089 06:55:18.758794
1090 06:55:18.759215 Set Vref, RX VrefLevel [Byte0]: 50
1091 06:55:18.762305 [Byte1]: 50
1092 06:55:18.766294
1093 06:55:18.766714 Set Vref, RX VrefLevel [Byte0]: 51
1094 06:55:18.769567 [Byte1]: 51
1095 06:55:18.773817
1096 06:55:18.774335 Set Vref, RX VrefLevel [Byte0]: 52
1097 06:55:18.777469 [Byte1]: 52
1098 06:55:18.781847
1099 06:55:18.782375 Set Vref, RX VrefLevel [Byte0]: 53
1100 06:55:18.785022 [Byte1]: 53
1101 06:55:18.789399
1102 06:55:18.789955 Set Vref, RX VrefLevel [Byte0]: 54
1103 06:55:18.792399 [Byte1]: 54
1104 06:55:18.796850
1105 06:55:18.797405 Set Vref, RX VrefLevel [Byte0]: 55
1106 06:55:18.800323 [Byte1]: 55
1107 06:55:18.804823
1108 06:55:18.805345 Set Vref, RX VrefLevel [Byte0]: 56
1109 06:55:18.808198 [Byte1]: 56
1110 06:55:18.812585
1111 06:55:18.813109 Set Vref, RX VrefLevel [Byte0]: 57
1112 06:55:18.816121 [Byte1]: 57
1113 06:55:18.819804
1114 06:55:18.820230 Set Vref, RX VrefLevel [Byte0]: 58
1115 06:55:18.823637 [Byte1]: 58
1116 06:55:18.827874
1117 06:55:18.828396 Set Vref, RX VrefLevel [Byte0]: 59
1118 06:55:18.831154 [Byte1]: 59
1119 06:55:18.834993
1120 06:55:18.835522 Set Vref, RX VrefLevel [Byte0]: 60
1121 06:55:18.838556 [Byte1]: 60
1122 06:55:18.842970
1123 06:55:18.846042 Set Vref, RX VrefLevel [Byte0]: 61
1124 06:55:18.849097 [Byte1]: 61
1125 06:55:18.849566
1126 06:55:18.853065 Set Vref, RX VrefLevel [Byte0]: 62
1127 06:55:18.856197 [Byte1]: 62
1128 06:55:18.856724
1129 06:55:18.859105 Set Vref, RX VrefLevel [Byte0]: 63
1130 06:55:18.862528 [Byte1]: 63
1131 06:55:18.862954
1132 06:55:18.865671 Set Vref, RX VrefLevel [Byte0]: 64
1133 06:55:18.869424 [Byte1]: 64
1134 06:55:18.873270
1135 06:55:18.873750 Set Vref, RX VrefLevel [Byte0]: 65
1136 06:55:18.876854 [Byte1]: 65
1137 06:55:18.881088
1138 06:55:18.881545 Set Vref, RX VrefLevel [Byte0]: 66
1139 06:55:18.884453 [Byte1]: 66
1140 06:55:18.888798
1141 06:55:18.889321 Set Vref, RX VrefLevel [Byte0]: 67
1142 06:55:18.891970 [Byte1]: 67
1143 06:55:18.896208
1144 06:55:18.896632 Set Vref, RX VrefLevel [Byte0]: 68
1145 06:55:18.899727 [Byte1]: 68
1146 06:55:18.904365
1147 06:55:18.904885 Set Vref, RX VrefLevel [Byte0]: 69
1148 06:55:18.907656 [Byte1]: 69
1149 06:55:18.911793
1150 06:55:18.912319 Set Vref, RX VrefLevel [Byte0]: 70
1151 06:55:18.914701 [Byte1]: 70
1152 06:55:18.919212
1153 06:55:18.919787 Set Vref, RX VrefLevel [Byte0]: 71
1154 06:55:18.922399 [Byte1]: 71
1155 06:55:18.927157
1156 06:55:18.927693 Set Vref, RX VrefLevel [Byte0]: 72
1157 06:55:18.930001 [Byte1]: 72
1158 06:55:18.934695
1159 06:55:18.935227 Set Vref, RX VrefLevel [Byte0]: 73
1160 06:55:18.937603 [Byte1]: 73
1161 06:55:18.942790
1162 06:55:18.943328 Set Vref, RX VrefLevel [Byte0]: 74
1163 06:55:18.945318 [Byte1]: 74
1164 06:55:18.950120
1165 06:55:18.950651 Set Vref, RX VrefLevel [Byte0]: 75
1166 06:55:18.953254 [Byte1]: 75
1167 06:55:18.957673
1168 06:55:18.958204 Set Vref, RX VrefLevel [Byte0]: 76
1169 06:55:18.960874 [Byte1]: 76
1170 06:55:18.965155
1171 06:55:18.965618 Set Vref, RX VrefLevel [Byte0]: 77
1172 06:55:18.968605 [Byte1]: 77
1173 06:55:18.972888
1174 06:55:18.973376 Set Vref, RX VrefLevel [Byte0]: 78
1175 06:55:18.976124 [Byte1]: 78
1176 06:55:18.980039
1177 06:55:18.980471 Set Vref, RX VrefLevel [Byte0]: 79
1178 06:55:18.984092 [Byte1]: 79
1179 06:55:18.988481
1180 06:55:18.989015 Set Vref, RX VrefLevel [Byte0]: 80
1181 06:55:18.991737 [Byte1]: 80
1182 06:55:18.995635
1183 06:55:18.996173 Final RX Vref Byte 0 = 53 to rank0
1184 06:55:18.999320 Final RX Vref Byte 1 = 58 to rank0
1185 06:55:19.002047 Final RX Vref Byte 0 = 53 to rank1
1186 06:55:19.006131 Final RX Vref Byte 1 = 58 to rank1==
1187 06:55:19.008944 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 06:55:19.015813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 06:55:19.016354 ==
1190 06:55:19.016809 DQS Delay:
1191 06:55:19.017251 DQS0 = 0, DQS1 = 0
1192 06:55:19.019046 DQM Delay:
1193 06:55:19.019526 DQM0 = 82, DQM1 = 68
1194 06:55:19.022327 DQ Delay:
1195 06:55:19.025449 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1196 06:55:19.025929 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1197 06:55:19.029446 DQ8 =64, DQ9 =56, DQ10 =68, DQ11 =60
1198 06:55:19.032730 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1199 06:55:19.035504
1200 06:55:19.036037
1201 06:55:19.042247 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1202 06:55:19.045847 CH0 RK0: MR19=606, MR18=2323
1203 06:55:19.052525 CH0_RK0: MR19=0x606, MR18=0x2323, DQSOSC=401, MR23=63, INC=91, DEC=61
1204 06:55:19.053049
1205 06:55:19.055814 ----->DramcWriteLeveling(PI) begin...
1206 06:55:19.056344 ==
1207 06:55:19.059101 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 06:55:19.062314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 06:55:19.062746 ==
1210 06:55:19.066074 Write leveling (Byte 0): 32 => 32
1211 06:55:19.069133 Write leveling (Byte 1): 31 => 31
1212 06:55:19.072412 DramcWriteLeveling(PI) end<-----
1213 06:55:19.072838
1214 06:55:19.073167 ==
1215 06:55:19.075962 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 06:55:19.078882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 06:55:19.079312 ==
1218 06:55:19.082240 [Gating] SW mode calibration
1219 06:55:19.088978 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 06:55:19.096354 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 06:55:19.099406 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 06:55:19.102506 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 06:55:19.109079 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1224 06:55:19.112889 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 06:55:19.116286 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 06:55:19.122291 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 06:55:19.125614 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 06:55:19.129090 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 06:55:19.135527 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 06:55:19.139537 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 06:55:19.142339 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 06:55:19.146390 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 06:55:19.190083 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 06:55:19.190652 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 06:55:19.191397 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 06:55:19.191750 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 06:55:19.192071 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1238 06:55:19.192376 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1239 06:55:19.192675 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1240 06:55:19.193058 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1241 06:55:19.193359 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 06:55:19.193686 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 06:55:19.212753 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 06:55:19.213299 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 06:55:19.213711 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 06:55:19.214043 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 06:55:19.214357 0 9 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
1248 06:55:19.216100 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 06:55:19.222691 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 06:55:19.226484 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 06:55:19.229299 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 06:55:19.236217 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 06:55:19.239772 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 06:55:19.242672 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
1255 06:55:19.249722 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (0 0) (1 0)
1256 06:55:19.253157 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1257 06:55:19.256453 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 06:55:19.263043 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 06:55:19.266475 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 06:55:19.269629 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 06:55:19.276699 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 06:55:19.279380 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1263 06:55:19.282839 0 11 8 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)
1264 06:55:19.289780 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1265 06:55:19.293419 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 06:55:19.296392 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 06:55:19.299904 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 06:55:19.306890 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 06:55:19.310292 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 06:55:19.313931 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1271 06:55:19.317640 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1272 06:55:19.324458 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1273 06:55:19.327511 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 06:55:19.331580 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 06:55:19.334812 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 06:55:19.341541 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 06:55:19.344966 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 06:55:19.347980 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 06:55:19.354772 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 06:55:19.358320 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 06:55:19.361693 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 06:55:19.368326 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 06:55:19.371573 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 06:55:19.374816 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 06:55:19.381525 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 06:55:19.385100 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 06:55:19.388719 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1288 06:55:19.395039 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 06:55:19.395570 Total UI for P1: 0, mck2ui 16
1290 06:55:19.398453 best dqsien dly found for B0: ( 0, 14, 8)
1291 06:55:19.401803 Total UI for P1: 0, mck2ui 16
1292 06:55:19.405590 best dqsien dly found for B1: ( 0, 14, 8)
1293 06:55:19.408570 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1294 06:55:19.411573 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1295 06:55:19.415234
1296 06:55:19.418206 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1297 06:55:19.421875 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1298 06:55:19.425047 [Gating] SW calibration Done
1299 06:55:19.425502 ==
1300 06:55:19.428550 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 06:55:19.432339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 06:55:19.432867 ==
1303 06:55:19.433210 RX Vref Scan: 0
1304 06:55:19.433574
1305 06:55:19.434975 RX Vref 0 -> 0, step: 1
1306 06:55:19.435400
1307 06:55:19.438194 RX Delay -130 -> 252, step: 16
1308 06:55:19.441781 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1309 06:55:19.445099 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1310 06:55:19.451801 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
1311 06:55:19.454891 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1312 06:55:19.458252 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1313 06:55:19.461923 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1314 06:55:19.465013 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1315 06:55:19.471978 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1316 06:55:19.475194 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1317 06:55:19.478086 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1318 06:55:19.481383 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1319 06:55:19.484834 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1320 06:55:19.491871 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1321 06:55:19.495093 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1322 06:55:19.498337 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1323 06:55:19.501563 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1324 06:55:19.502096 ==
1325 06:55:19.505269 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 06:55:19.511633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 06:55:19.512170 ==
1328 06:55:19.512508 DQS Delay:
1329 06:55:19.512823 DQS0 = 0, DQS1 = 0
1330 06:55:19.514839 DQM Delay:
1331 06:55:19.515302 DQM0 = 77, DQM1 = 69
1332 06:55:19.518218 DQ Delay:
1333 06:55:19.521391 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =69
1334 06:55:19.524849 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =85
1335 06:55:19.525383 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1336 06:55:19.531672 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1337 06:55:19.532201
1338 06:55:19.532540
1339 06:55:19.532931 ==
1340 06:55:19.534864 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 06:55:19.537965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 06:55:19.538404 ==
1343 06:55:19.538743
1344 06:55:19.539056
1345 06:55:19.541367 TX Vref Scan disable
1346 06:55:19.541838 == TX Byte 0 ==
1347 06:55:19.548460 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1348 06:55:19.551240 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1349 06:55:19.551664 == TX Byte 1 ==
1350 06:55:19.557907 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1351 06:55:19.561287 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1352 06:55:19.561751 ==
1353 06:55:19.565158 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 06:55:19.568112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 06:55:19.568647 ==
1356 06:55:19.581802 TX Vref=22, minBit 11, minWin=26, winSum=432
1357 06:55:19.584901 TX Vref=24, minBit 1, minWin=27, winSum=437
1358 06:55:19.589028 TX Vref=26, minBit 1, minWin=27, winSum=441
1359 06:55:19.591638 TX Vref=28, minBit 1, minWin=27, winSum=440
1360 06:55:19.595215 TX Vref=30, minBit 1, minWin=27, winSum=442
1361 06:55:19.601668 TX Vref=32, minBit 8, minWin=27, winSum=442
1362 06:55:19.604832 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 30
1363 06:55:19.605383
1364 06:55:19.608091 Final TX Range 1 Vref 30
1365 06:55:19.608625
1366 06:55:19.609095 ==
1367 06:55:19.611767 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 06:55:19.614815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 06:55:19.615347 ==
1370 06:55:19.615747
1371 06:55:19.618143
1372 06:55:19.618515 TX Vref Scan disable
1373 06:55:19.621391 == TX Byte 0 ==
1374 06:55:19.624596 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1375 06:55:19.631277 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1376 06:55:19.631461 == TX Byte 1 ==
1377 06:55:19.634898 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1378 06:55:19.641465 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1379 06:55:19.641757
1380 06:55:19.641909 [DATLAT]
1381 06:55:19.642045 Freq=800, CH0 RK1
1382 06:55:19.642175
1383 06:55:19.645359 DATLAT Default: 0xa
1384 06:55:19.645663 0, 0xFFFF, sum = 0
1385 06:55:19.648783 1, 0xFFFF, sum = 0
1386 06:55:19.649055 2, 0xFFFF, sum = 0
1387 06:55:19.651772 3, 0xFFFF, sum = 0
1388 06:55:19.652046 4, 0xFFFF, sum = 0
1389 06:55:19.655015 5, 0xFFFF, sum = 0
1390 06:55:19.655294 6, 0xFFFF, sum = 0
1391 06:55:19.658115 7, 0xFFFF, sum = 0
1392 06:55:19.661712 8, 0xFFFF, sum = 0
1393 06:55:19.662146 9, 0x0, sum = 1
1394 06:55:19.662485 10, 0x0, sum = 2
1395 06:55:19.664898 11, 0x0, sum = 3
1396 06:55:19.665322 12, 0x0, sum = 4
1397 06:55:19.668649 best_step = 10
1398 06:55:19.669177
1399 06:55:19.669563 ==
1400 06:55:19.672007 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 06:55:19.675000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 06:55:19.675446 ==
1403 06:55:19.678517 RX Vref Scan: 0
1404 06:55:19.679050
1405 06:55:19.679387 RX Vref 0 -> 0, step: 1
1406 06:55:19.679694
1407 06:55:19.681871 RX Delay -111 -> 252, step: 8
1408 06:55:19.688607 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1409 06:55:19.692133 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1410 06:55:19.694870 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1411 06:55:19.698415 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1412 06:55:19.702265 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1413 06:55:19.708600 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1414 06:55:19.712072 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1415 06:55:19.714984 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1416 06:55:19.718183 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1417 06:55:19.721902 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1418 06:55:19.728445 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1419 06:55:19.732104 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1420 06:55:19.735044 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1421 06:55:19.738408 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1422 06:55:19.745206 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1423 06:55:19.748448 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1424 06:55:19.748979 ==
1425 06:55:19.751595 Dram Type= 6, Freq= 0, CH_0, rank 1
1426 06:55:19.755435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 06:55:19.755977 ==
1428 06:55:19.756314 DQS Delay:
1429 06:55:19.758234 DQS0 = 0, DQS1 = 0
1430 06:55:19.758656 DQM Delay:
1431 06:55:19.762201 DQM0 = 79, DQM1 = 70
1432 06:55:19.762730 DQ Delay:
1433 06:55:19.765128 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1434 06:55:19.768744 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1435 06:55:19.771854 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1436 06:55:19.775354 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1437 06:55:19.775892
1438 06:55:19.776231
1439 06:55:19.785421 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
1440 06:55:19.786000 CH0 RK1: MR19=606, MR18=4E29
1441 06:55:19.791676 CH0_RK1: MR19=0x606, MR18=0x4E29, DQSOSC=390, MR23=63, INC=97, DEC=64
1442 06:55:19.795410 [RxdqsGatingPostProcess] freq 800
1443 06:55:19.802122 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1444 06:55:19.804900 Pre-setting of DQS Precalculation
1445 06:55:19.808056 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1446 06:55:19.808570 ==
1447 06:55:19.811642 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 06:55:19.815165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 06:55:19.815721 ==
1450 06:55:19.821528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 06:55:19.828503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 06:55:19.836992 [CA 0] Center 36 (6~66) winsize 61
1453 06:55:19.840464 [CA 1] Center 36 (6~67) winsize 62
1454 06:55:19.843218 [CA 2] Center 34 (4~64) winsize 61
1455 06:55:19.847077 [CA 3] Center 34 (4~64) winsize 61
1456 06:55:19.850290 [CA 4] Center 34 (4~64) winsize 61
1457 06:55:19.853406 [CA 5] Center 33 (3~64) winsize 62
1458 06:55:19.854012
1459 06:55:19.856780 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1460 06:55:19.857228
1461 06:55:19.859959 [CATrainingPosCal] consider 1 rank data
1462 06:55:19.863823 u2DelayCellTimex100 = 270/100 ps
1463 06:55:19.867104 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1464 06:55:19.870463 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1465 06:55:19.876931 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1466 06:55:19.880280 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1467 06:55:19.883680 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1468 06:55:19.886798 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1469 06:55:19.887247
1470 06:55:19.890407 CA PerBit enable=1, Macro0, CA PI delay=33
1471 06:55:19.890962
1472 06:55:19.893930 [CBTSetCACLKResult] CA Dly = 33
1473 06:55:19.894483 CS Dly: 5 (0~36)
1474 06:55:19.894946 ==
1475 06:55:19.897064 Dram Type= 6, Freq= 0, CH_1, rank 1
1476 06:55:19.903798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 06:55:19.904352 ==
1478 06:55:19.906633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 06:55:19.913418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 06:55:19.922840 [CA 0] Center 36 (7~66) winsize 60
1481 06:55:19.926290 [CA 1] Center 36 (6~67) winsize 62
1482 06:55:19.929852 [CA 2] Center 34 (4~65) winsize 62
1483 06:55:19.933244 [CA 3] Center 33 (3~64) winsize 62
1484 06:55:19.936180 [CA 4] Center 34 (4~65) winsize 62
1485 06:55:19.939398 [CA 5] Center 33 (3~64) winsize 62
1486 06:55:19.939827
1487 06:55:19.942863 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1488 06:55:19.943293
1489 06:55:19.946077 [CATrainingPosCal] consider 2 rank data
1490 06:55:19.949670 u2DelayCellTimex100 = 270/100 ps
1491 06:55:19.952728 CA0 delay=36 (7~66),Diff = 3 PI (21 cell)
1492 06:55:19.959566 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1493 06:55:19.962615 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1494 06:55:19.966299 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1495 06:55:19.970186 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1496 06:55:19.973646 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1497 06:55:19.974198
1498 06:55:19.976957 CA PerBit enable=1, Macro0, CA PI delay=33
1499 06:55:19.977381
1500 06:55:19.980919 [CBTSetCACLKResult] CA Dly = 33
1501 06:55:19.981346 CS Dly: 6 (0~38)
1502 06:55:19.981767
1503 06:55:19.984737 ----->DramcWriteLeveling(PI) begin...
1504 06:55:19.985165 ==
1505 06:55:19.988778 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 06:55:19.992619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 06:55:19.993240 ==
1508 06:55:19.996261 Write leveling (Byte 0): 29 => 29
1509 06:55:19.999567 Write leveling (Byte 1): 31 => 31
1510 06:55:20.000005 DramcWriteLeveling(PI) end<-----
1511 06:55:20.003497
1512 06:55:20.004077 ==
1513 06:55:20.006886 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 06:55:20.010195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 06:55:20.010632 ==
1516 06:55:20.013631 [Gating] SW mode calibration
1517 06:55:20.020214 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1518 06:55:20.023257 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1519 06:55:20.030456 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1520 06:55:20.033558 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1521 06:55:20.037029 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 06:55:20.043659 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 06:55:20.046278 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 06:55:20.050420 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 06:55:20.056945 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 06:55:20.060206 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 06:55:20.063302 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 06:55:20.066514 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 06:55:20.073354 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 06:55:20.076401 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 06:55:20.080078 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 06:55:20.086465 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 06:55:20.089857 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 06:55:20.093253 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 06:55:20.100131 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 06:55:20.103146 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1537 06:55:20.106648 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 06:55:20.113025 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 06:55:20.116347 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 06:55:20.120125 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 06:55:20.126296 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 06:55:20.129965 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 06:55:20.133409 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 06:55:20.140045 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 06:55:20.143047 0 9 8 | B1->B0 | 2c2c 2424 | 1 1 | (1 1) (0 0)
1546 06:55:20.146594 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 06:55:20.153096 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 06:55:20.156259 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 06:55:20.159915 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 06:55:20.166389 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 06:55:20.169892 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 06:55:20.173208 0 10 4 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 1)
1553 06:55:20.179888 0 10 8 | B1->B0 | 2a2a 2c2c | 0 0 | (0 0) (0 0)
1554 06:55:20.182918 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 06:55:20.186372 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 06:55:20.189875 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 06:55:20.196214 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 06:55:20.199611 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 06:55:20.203573 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 06:55:20.210007 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1561 06:55:20.213263 0 11 8 | B1->B0 | 3d3d 3838 | 1 1 | (0 0) (0 0)
1562 06:55:20.216822 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 06:55:20.223435 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 06:55:20.226209 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 06:55:20.229753 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 06:55:20.236401 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 06:55:20.239766 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 06:55:20.242998 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 06:55:20.249887 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1570 06:55:20.253164 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 06:55:20.256334 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 06:55:20.263170 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 06:55:20.266454 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 06:55:20.269662 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 06:55:20.276335 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 06:55:20.279554 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 06:55:20.283078 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 06:55:20.286044 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 06:55:20.293196 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 06:55:20.296453 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 06:55:20.299762 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 06:55:20.306649 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 06:55:20.310217 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 06:55:20.313224 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1585 06:55:20.319343 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 06:55:20.322835 Total UI for P1: 0, mck2ui 16
1587 06:55:20.326003 best dqsien dly found for B0: ( 0, 14, 4)
1588 06:55:20.326436 Total UI for P1: 0, mck2ui 16
1589 06:55:20.333518 best dqsien dly found for B1: ( 0, 14, 4)
1590 06:55:20.336764 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1591 06:55:20.339593 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1592 06:55:20.340022
1593 06:55:20.343149 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1594 06:55:20.346345 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1595 06:55:20.349742 [Gating] SW calibration Done
1596 06:55:20.350277 ==
1597 06:55:20.353232 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 06:55:20.356536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 06:55:20.357072 ==
1600 06:55:20.359900 RX Vref Scan: 0
1601 06:55:20.360430
1602 06:55:20.360765 RX Vref 0 -> 0, step: 1
1603 06:55:20.361076
1604 06:55:20.362900 RX Delay -130 -> 252, step: 16
1605 06:55:20.366229 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1606 06:55:20.373229 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1607 06:55:20.376667 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1608 06:55:20.379787 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1609 06:55:20.382886 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1610 06:55:20.386352 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1611 06:55:20.393291 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1612 06:55:20.396536 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1613 06:55:20.399699 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1614 06:55:20.403055 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1615 06:55:20.406372 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1616 06:55:20.413250 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1617 06:55:20.416229 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1618 06:55:20.419511 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1619 06:55:20.422989 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1620 06:55:20.426180 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1621 06:55:20.426614 ==
1622 06:55:20.429428 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 06:55:20.436426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 06:55:20.437204 ==
1625 06:55:20.437620 DQS Delay:
1626 06:55:20.439559 DQS0 = 0, DQS1 = 0
1627 06:55:20.440243 DQM Delay:
1628 06:55:20.440783 DQM0 = 81, DQM1 = 71
1629 06:55:20.442948 DQ Delay:
1630 06:55:20.446542 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1631 06:55:20.449588 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1632 06:55:20.453269 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1633 06:55:20.456439 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1634 06:55:20.456861
1635 06:55:20.457192
1636 06:55:20.457543 ==
1637 06:55:20.460243 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 06:55:20.463280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 06:55:20.463726 ==
1640 06:55:20.464066
1641 06:55:20.464380
1642 06:55:20.466599 TX Vref Scan disable
1643 06:55:20.467025 == TX Byte 0 ==
1644 06:55:20.473159 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1645 06:55:20.476283 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1646 06:55:20.476710 == TX Byte 1 ==
1647 06:55:20.483195 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1648 06:55:20.486525 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1649 06:55:20.486960 ==
1650 06:55:20.489776 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 06:55:20.493163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 06:55:20.493668 ==
1653 06:55:20.507041 TX Vref=22, minBit 8, minWin=27, winSum=445
1654 06:55:20.510245 TX Vref=24, minBit 8, minWin=27, winSum=445
1655 06:55:20.513644 TX Vref=26, minBit 8, minWin=27, winSum=448
1656 06:55:20.517188 TX Vref=28, minBit 11, minWin=27, winSum=449
1657 06:55:20.520532 TX Vref=30, minBit 3, minWin=28, winSum=456
1658 06:55:20.527086 TX Vref=32, minBit 9, minWin=27, winSum=455
1659 06:55:20.530278 [TxChooseVref] Worse bit 3, Min win 28, Win sum 456, Final Vref 30
1660 06:55:20.530718
1661 06:55:20.536869 Final TX Range 1 Vref 30
1662 06:55:20.537313
1663 06:55:20.537775 ==
1664 06:55:20.538516 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 06:55:20.540922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 06:55:20.541360 ==
1667 06:55:20.543562
1668 06:55:20.543990
1669 06:55:20.544427 TX Vref Scan disable
1670 06:55:20.547517 == TX Byte 0 ==
1671 06:55:20.550680 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1672 06:55:20.554462 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1673 06:55:20.557587 == TX Byte 1 ==
1674 06:55:20.560938 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1675 06:55:20.564306 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1676 06:55:20.564738
1677 06:55:20.567767 [DATLAT]
1678 06:55:20.568301 Freq=800, CH1 RK0
1679 06:55:20.568641
1680 06:55:20.570922 DATLAT Default: 0xa
1681 06:55:20.571459 0, 0xFFFF, sum = 0
1682 06:55:20.574033 1, 0xFFFF, sum = 0
1683 06:55:20.574472 2, 0xFFFF, sum = 0
1684 06:55:20.577347 3, 0xFFFF, sum = 0
1685 06:55:20.577816 4, 0xFFFF, sum = 0
1686 06:55:20.580653 5, 0xFFFF, sum = 0
1687 06:55:20.581088 6, 0xFFFF, sum = 0
1688 06:55:20.584201 7, 0xFFFF, sum = 0
1689 06:55:20.584638 8, 0xFFFF, sum = 0
1690 06:55:20.587400 9, 0x0, sum = 1
1691 06:55:20.587834 10, 0x0, sum = 2
1692 06:55:20.591191 11, 0x0, sum = 3
1693 06:55:20.591730 12, 0x0, sum = 4
1694 06:55:20.594082 best_step = 10
1695 06:55:20.594513
1696 06:55:20.594852 ==
1697 06:55:20.597695 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 06:55:20.601073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1699 06:55:20.601659 ==
1700 06:55:20.604615 RX Vref Scan: 1
1701 06:55:20.605145
1702 06:55:20.605534 Set Vref Range= 32 -> 127
1703 06:55:20.605869
1704 06:55:20.607846 RX Vref 32 -> 127, step: 1
1705 06:55:20.608377
1706 06:55:20.611064 RX Delay -111 -> 252, step: 8
1707 06:55:20.611602
1708 06:55:20.614121 Set Vref, RX VrefLevel [Byte0]: 32
1709 06:55:20.617815 [Byte1]: 32
1710 06:55:20.618348
1711 06:55:20.621171 Set Vref, RX VrefLevel [Byte0]: 33
1712 06:55:20.624100 [Byte1]: 33
1713 06:55:20.627649
1714 06:55:20.628101 Set Vref, RX VrefLevel [Byte0]: 34
1715 06:55:20.630711 [Byte1]: 34
1716 06:55:20.635218
1717 06:55:20.635648 Set Vref, RX VrefLevel [Byte0]: 35
1718 06:55:20.638468 [Byte1]: 35
1719 06:55:20.642939
1720 06:55:20.643375 Set Vref, RX VrefLevel [Byte0]: 36
1721 06:55:20.646108 [Byte1]: 36
1722 06:55:20.650930
1723 06:55:20.651473 Set Vref, RX VrefLevel [Byte0]: 37
1724 06:55:20.653724 [Byte1]: 37
1725 06:55:20.658453
1726 06:55:20.658986 Set Vref, RX VrefLevel [Byte0]: 38
1727 06:55:20.661617 [Byte1]: 38
1728 06:55:20.666022
1729 06:55:20.669147 Set Vref, RX VrefLevel [Byte0]: 39
1730 06:55:20.672611 [Byte1]: 39
1731 06:55:20.673145
1732 06:55:20.675576 Set Vref, RX VrefLevel [Byte0]: 40
1733 06:55:20.678738 [Byte1]: 40
1734 06:55:20.679170
1735 06:55:20.682779 Set Vref, RX VrefLevel [Byte0]: 41
1736 06:55:20.685591 [Byte1]: 41
1737 06:55:20.686021
1738 06:55:20.689089 Set Vref, RX VrefLevel [Byte0]: 42
1739 06:55:20.692314 [Byte1]: 42
1740 06:55:20.696615
1741 06:55:20.697154 Set Vref, RX VrefLevel [Byte0]: 43
1742 06:55:20.700000 [Byte1]: 43
1743 06:55:20.704295
1744 06:55:20.704830 Set Vref, RX VrefLevel [Byte0]: 44
1745 06:55:20.707359 [Byte1]: 44
1746 06:55:20.711904
1747 06:55:20.712456 Set Vref, RX VrefLevel [Byte0]: 45
1748 06:55:20.715270 [Byte1]: 45
1749 06:55:20.719800
1750 06:55:20.720340 Set Vref, RX VrefLevel [Byte0]: 46
1751 06:55:20.722708 [Byte1]: 46
1752 06:55:20.727195
1753 06:55:20.727767 Set Vref, RX VrefLevel [Byte0]: 47
1754 06:55:20.730592 [Byte1]: 47
1755 06:55:20.734924
1756 06:55:20.735465 Set Vref, RX VrefLevel [Byte0]: 48
1757 06:55:20.738225 [Byte1]: 48
1758 06:55:20.742384
1759 06:55:20.742809 Set Vref, RX VrefLevel [Byte0]: 49
1760 06:55:20.745714 [Byte1]: 49
1761 06:55:20.750190
1762 06:55:20.750723 Set Vref, RX VrefLevel [Byte0]: 50
1763 06:55:20.753577 [Byte1]: 50
1764 06:55:20.757775
1765 06:55:20.758305 Set Vref, RX VrefLevel [Byte0]: 51
1766 06:55:20.761211 [Byte1]: 51
1767 06:55:20.765159
1768 06:55:20.768625 Set Vref, RX VrefLevel [Byte0]: 52
1769 06:55:20.771991 [Byte1]: 52
1770 06:55:20.772531
1771 06:55:20.775104 Set Vref, RX VrefLevel [Byte0]: 53
1772 06:55:20.778465 [Byte1]: 53
1773 06:55:20.779006
1774 06:55:20.782159 Set Vref, RX VrefLevel [Byte0]: 54
1775 06:55:20.785101 [Byte1]: 54
1776 06:55:20.788649
1777 06:55:20.789187 Set Vref, RX VrefLevel [Byte0]: 55
1778 06:55:20.791735 [Byte1]: 55
1779 06:55:20.795852
1780 06:55:20.796393 Set Vref, RX VrefLevel [Byte0]: 56
1781 06:55:20.799572 [Byte1]: 56
1782 06:55:20.803580
1783 06:55:20.804010 Set Vref, RX VrefLevel [Byte0]: 57
1784 06:55:20.806878 [Byte1]: 57
1785 06:55:20.811555
1786 06:55:20.812100 Set Vref, RX VrefLevel [Byte0]: 58
1787 06:55:20.814265 [Byte1]: 58
1788 06:55:20.818810
1789 06:55:20.819347 Set Vref, RX VrefLevel [Byte0]: 59
1790 06:55:20.822443 [Byte1]: 59
1791 06:55:20.826330
1792 06:55:20.826760 Set Vref, RX VrefLevel [Byte0]: 60
1793 06:55:20.829929 [Byte1]: 60
1794 06:55:20.834430
1795 06:55:20.834962 Set Vref, RX VrefLevel [Byte0]: 61
1796 06:55:20.837645 [Byte1]: 61
1797 06:55:20.841937
1798 06:55:20.842472 Set Vref, RX VrefLevel [Byte0]: 62
1799 06:55:20.845061 [Byte1]: 62
1800 06:55:20.849637
1801 06:55:20.850175 Set Vref, RX VrefLevel [Byte0]: 63
1802 06:55:20.852906 [Byte1]: 63
1803 06:55:20.857374
1804 06:55:20.857966 Set Vref, RX VrefLevel [Byte0]: 64
1805 06:55:20.860496 [Byte1]: 64
1806 06:55:20.864985
1807 06:55:20.865567 Set Vref, RX VrefLevel [Byte0]: 65
1808 06:55:20.868036 [Byte1]: 65
1809 06:55:20.872557
1810 06:55:20.873096 Set Vref, RX VrefLevel [Byte0]: 66
1811 06:55:20.875538 [Byte1]: 66
1812 06:55:20.880171
1813 06:55:20.880724 Set Vref, RX VrefLevel [Byte0]: 67
1814 06:55:20.883182 [Byte1]: 67
1815 06:55:20.887890
1816 06:55:20.888431 Set Vref, RX VrefLevel [Byte0]: 68
1817 06:55:20.890907 [Byte1]: 68
1818 06:55:20.895448
1819 06:55:20.895986 Set Vref, RX VrefLevel [Byte0]: 69
1820 06:55:20.898970 [Byte1]: 69
1821 06:55:20.902718
1822 06:55:20.903145 Set Vref, RX VrefLevel [Byte0]: 70
1823 06:55:20.906208 [Byte1]: 70
1824 06:55:20.911014
1825 06:55:20.911548 Set Vref, RX VrefLevel [Byte0]: 71
1826 06:55:20.913947 [Byte1]: 71
1827 06:55:20.918419
1828 06:55:20.918951 Set Vref, RX VrefLevel [Byte0]: 72
1829 06:55:20.921227 [Byte1]: 72
1830 06:55:20.926167
1831 06:55:20.926600 Set Vref, RX VrefLevel [Byte0]: 73
1832 06:55:20.929290 [Byte1]: 73
1833 06:55:20.934057
1834 06:55:20.934597 Set Vref, RX VrefLevel [Byte0]: 74
1835 06:55:20.937163 [Byte1]: 74
1836 06:55:20.941468
1837 06:55:20.942056 Set Vref, RX VrefLevel [Byte0]: 75
1838 06:55:20.944229 [Byte1]: 75
1839 06:55:20.949108
1840 06:55:20.949705 Final RX Vref Byte 0 = 55 to rank0
1841 06:55:20.952374 Final RX Vref Byte 1 = 53 to rank0
1842 06:55:20.955738 Final RX Vref Byte 0 = 55 to rank1
1843 06:55:20.958860 Final RX Vref Byte 1 = 53 to rank1==
1844 06:55:20.962421 Dram Type= 6, Freq= 0, CH_1, rank 0
1845 06:55:20.969100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 06:55:20.969678 ==
1847 06:55:20.970030 DQS Delay:
1848 06:55:20.970349 DQS0 = 0, DQS1 = 0
1849 06:55:20.972590 DQM Delay:
1850 06:55:20.973111 DQM0 = 80, DQM1 = 71
1851 06:55:20.975384 DQ Delay:
1852 06:55:20.979109 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1853 06:55:20.979632 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1854 06:55:20.982232 DQ8 =64, DQ9 =64, DQ10 =72, DQ11 =64
1855 06:55:20.985677 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1856 06:55:20.988823
1857 06:55:20.989247
1858 06:55:20.995749 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1859 06:55:20.999312 CH1 RK0: MR19=606, MR18=E18
1860 06:55:21.005759 CH1_RK0: MR19=0x606, MR18=0xE18, DQSOSC=403, MR23=63, INC=90, DEC=60
1861 06:55:21.006283
1862 06:55:21.009047 ----->DramcWriteLeveling(PI) begin...
1863 06:55:21.009627 ==
1864 06:55:21.012785 Dram Type= 6, Freq= 0, CH_1, rank 1
1865 06:55:21.015691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1866 06:55:21.016241 ==
1867 06:55:21.019097 Write leveling (Byte 0): 26 => 26
1868 06:55:21.022052 Write leveling (Byte 1): 31 => 31
1869 06:55:21.025651 DramcWriteLeveling(PI) end<-----
1870 06:55:21.026083
1871 06:55:21.026421 ==
1872 06:55:21.028833 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 06:55:21.032427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 06:55:21.032955 ==
1875 06:55:21.035648 [Gating] SW mode calibration
1876 06:55:21.042068 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1877 06:55:21.049068 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1878 06:55:21.051959 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1879 06:55:21.055681 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1880 06:55:21.062440 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 06:55:21.065434 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 06:55:21.068658 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 06:55:21.075276 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 06:55:21.078580 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 06:55:21.082355 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 06:55:21.088763 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 06:55:21.092037 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 06:55:21.095464 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 06:55:21.098573 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 06:55:21.105720 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 06:55:21.108964 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 06:55:21.112326 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 06:55:21.118635 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 06:55:21.121840 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 06:55:21.125076 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1896 06:55:21.131871 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 06:55:21.134902 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 06:55:21.138562 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 06:55:21.145183 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 06:55:21.148279 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 06:55:21.152165 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 06:55:21.158629 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 06:55:21.162053 0 9 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1904 06:55:21.165060 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
1905 06:55:21.171787 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 06:55:21.175294 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 06:55:21.178433 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 06:55:21.185217 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 06:55:21.188715 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 06:55:21.191848 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1911 06:55:21.198501 0 10 4 | B1->B0 | 3030 2929 | 0 0 | (0 1) (0 0)
1912 06:55:21.202058 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1913 06:55:21.205354 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 06:55:21.211674 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 06:55:21.214855 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 06:55:21.218176 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 06:55:21.224922 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 06:55:21.228430 0 11 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1919 06:55:21.231382 0 11 4 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)
1920 06:55:21.235089 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1921 06:55:21.241597 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 06:55:21.244746 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 06:55:21.248172 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 06:55:21.254960 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 06:55:21.258321 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 06:55:21.261970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 06:55:21.268346 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 06:55:21.271753 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1929 06:55:21.274975 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 06:55:21.281789 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 06:55:21.284840 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 06:55:21.288082 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 06:55:21.294921 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 06:55:21.298393 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 06:55:21.301636 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 06:55:21.308718 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 06:55:21.311873 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 06:55:21.315121 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 06:55:21.321848 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 06:55:21.324939 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 06:55:21.328574 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 06:55:21.331555 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 06:55:21.338112 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1944 06:55:21.341550 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1945 06:55:21.345072 Total UI for P1: 0, mck2ui 16
1946 06:55:21.348744 best dqsien dly found for B0: ( 0, 14, 4)
1947 06:55:21.351607 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 06:55:21.355184 Total UI for P1: 0, mck2ui 16
1949 06:55:21.358256 best dqsien dly found for B1: ( 0, 14, 8)
1950 06:55:21.361670 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1951 06:55:21.365307 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1952 06:55:21.365887
1953 06:55:21.371939 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1954 06:55:21.375241 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1955 06:55:21.375782 [Gating] SW calibration Done
1956 06:55:21.378205 ==
1957 06:55:21.381601 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 06:55:21.384756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 06:55:21.385315 ==
1960 06:55:21.385791 RX Vref Scan: 0
1961 06:55:21.386117
1962 06:55:21.388339 RX Vref 0 -> 0, step: 1
1963 06:55:21.388757
1964 06:55:21.391993 RX Delay -130 -> 252, step: 16
1965 06:55:21.395466 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1966 06:55:21.398403 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1967 06:55:21.402048 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1968 06:55:21.408779 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1969 06:55:21.412186 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1970 06:55:21.415120 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1971 06:55:21.418206 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1972 06:55:21.421678 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1973 06:55:21.428783 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1974 06:55:21.431588 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1975 06:55:21.435218 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1976 06:55:21.438761 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1977 06:55:21.441629 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1978 06:55:21.448425 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1979 06:55:21.451778 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1980 06:55:21.454985 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1981 06:55:21.455418 ==
1982 06:55:21.458187 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 06:55:21.461720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 06:55:21.465287 ==
1985 06:55:21.465901 DQS Delay:
1986 06:55:21.466251 DQS0 = 0, DQS1 = 0
1987 06:55:21.467950 DQM Delay:
1988 06:55:21.468377 DQM0 = 79, DQM1 = 74
1989 06:55:21.471883 DQ Delay:
1990 06:55:21.472410 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1991 06:55:21.474753 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1992 06:55:21.478062 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1993 06:55:21.481597 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1994 06:55:21.482128
1995 06:55:21.484748
1996 06:55:21.485272 ==
1997 06:55:21.488195 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 06:55:21.491421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 06:55:21.491956 ==
2000 06:55:21.492303
2001 06:55:21.492622
2002 06:55:21.495024 TX Vref Scan disable
2003 06:55:21.495549 == TX Byte 0 ==
2004 06:55:21.501238 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2005 06:55:21.504742 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2006 06:55:21.505175 == TX Byte 1 ==
2007 06:55:21.511695 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2008 06:55:21.515009 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2009 06:55:21.515535 ==
2010 06:55:21.518418 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 06:55:21.521512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 06:55:21.522059 ==
2013 06:55:21.535419 TX Vref=22, minBit 9, minWin=27, winSum=449
2014 06:55:21.538664 TX Vref=24, minBit 0, minWin=28, winSum=453
2015 06:55:21.541988 TX Vref=26, minBit 3, minWin=28, winSum=457
2016 06:55:21.545437 TX Vref=28, minBit 6, minWin=28, winSum=459
2017 06:55:21.548590 TX Vref=30, minBit 3, minWin=28, winSum=458
2018 06:55:21.551888 TX Vref=32, minBit 2, minWin=28, winSum=454
2019 06:55:21.558682 [TxChooseVref] Worse bit 6, Min win 28, Win sum 459, Final Vref 28
2020 06:55:21.559203
2021 06:55:21.562017 Final TX Range 1 Vref 28
2022 06:55:21.562526
2023 06:55:21.562861 ==
2024 06:55:21.564944 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 06:55:21.568468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 06:55:21.568999 ==
2027 06:55:21.569348
2028 06:55:21.571783
2029 06:55:21.572198 TX Vref Scan disable
2030 06:55:21.575795 == TX Byte 0 ==
2031 06:55:21.578313 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2032 06:55:21.581969 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2033 06:55:21.585267 == TX Byte 1 ==
2034 06:55:21.588330 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2035 06:55:21.592356 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2036 06:55:21.595175
2037 06:55:21.595594 [DATLAT]
2038 06:55:21.595926 Freq=800, CH1 RK1
2039 06:55:21.596236
2040 06:55:21.598686 DATLAT Default: 0xa
2041 06:55:21.599107 0, 0xFFFF, sum = 0
2042 06:55:21.602027 1, 0xFFFF, sum = 0
2043 06:55:21.602467 2, 0xFFFF, sum = 0
2044 06:55:21.605230 3, 0xFFFF, sum = 0
2045 06:55:21.605712 4, 0xFFFF, sum = 0
2046 06:55:21.608608 5, 0xFFFF, sum = 0
2047 06:55:21.609036 6, 0xFFFF, sum = 0
2048 06:55:21.611785 7, 0xFFFF, sum = 0
2049 06:55:21.615240 8, 0xFFFF, sum = 0
2050 06:55:21.615773 9, 0x0, sum = 1
2051 06:55:21.616116 10, 0x0, sum = 2
2052 06:55:21.618554 11, 0x0, sum = 3
2053 06:55:21.618994 12, 0x0, sum = 4
2054 06:55:21.622002 best_step = 10
2055 06:55:21.622438
2056 06:55:21.622776 ==
2057 06:55:21.625073 Dram Type= 6, Freq= 0, CH_1, rank 1
2058 06:55:21.628392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2059 06:55:21.628911 ==
2060 06:55:21.631752 RX Vref Scan: 0
2061 06:55:21.632171
2062 06:55:21.632639 RX Vref 0 -> 0, step: 1
2063 06:55:21.633302
2064 06:55:21.635201 RX Delay -111 -> 252, step: 8
2065 06:55:21.642098 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2066 06:55:21.645324 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2067 06:55:21.648875 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2068 06:55:21.652232 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2069 06:55:21.655764 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2070 06:55:21.662460 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2071 06:55:21.665192 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2072 06:55:21.668785 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2073 06:55:21.672098 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2074 06:55:21.675461 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2075 06:55:21.682214 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2076 06:55:21.685585 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2077 06:55:21.689166 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2078 06:55:21.692567 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2079 06:55:21.695241 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2080 06:55:21.702453 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2081 06:55:21.702985 ==
2082 06:55:21.705650 Dram Type= 6, Freq= 0, CH_1, rank 1
2083 06:55:21.709022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2084 06:55:21.709586 ==
2085 06:55:21.709926 DQS Delay:
2086 06:55:21.712555 DQS0 = 0, DQS1 = 0
2087 06:55:21.713078 DQM Delay:
2088 06:55:21.715682 DQM0 = 77, DQM1 = 72
2089 06:55:21.716210 DQ Delay:
2090 06:55:21.719077 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2091 06:55:21.722091 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2092 06:55:21.725723 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
2093 06:55:21.728688 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
2094 06:55:21.729223
2095 06:55:21.729615
2096 06:55:21.735114 [DQSOSCAuto] RK1, (LSB)MR18= 0x263e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2097 06:55:21.738626 CH1 RK1: MR19=606, MR18=263E
2098 06:55:21.745370 CH1_RK1: MR19=0x606, MR18=0x263E, DQSOSC=394, MR23=63, INC=95, DEC=63
2099 06:55:21.748781 [RxdqsGatingPostProcess] freq 800
2100 06:55:21.755467 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2101 06:55:21.758673 Pre-setting of DQS Precalculation
2102 06:55:21.762365 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2103 06:55:21.768936 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2104 06:55:21.775613 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2105 06:55:21.776140
2106 06:55:21.776473
2107 06:55:21.779028 [Calibration Summary] 1600 Mbps
2108 06:55:21.782123 CH 0, Rank 0
2109 06:55:21.782646 SW Impedance : PASS
2110 06:55:21.785713 DUTY Scan : NO K
2111 06:55:21.789062 ZQ Calibration : PASS
2112 06:55:21.789646 Jitter Meter : NO K
2113 06:55:21.792092 CBT Training : PASS
2114 06:55:21.795121 Write leveling : PASS
2115 06:55:21.795542 RX DQS gating : PASS
2116 06:55:21.799096 RX DQ/DQS(RDDQC) : PASS
2117 06:55:21.801817 TX DQ/DQS : PASS
2118 06:55:21.802344 RX DATLAT : PASS
2119 06:55:21.805102 RX DQ/DQS(Engine): PASS
2120 06:55:21.805559 TX OE : NO K
2121 06:55:21.808558 All Pass.
2122 06:55:21.809092
2123 06:55:21.809670 CH 0, Rank 1
2124 06:55:21.812000 SW Impedance : PASS
2125 06:55:21.812418 DUTY Scan : NO K
2126 06:55:21.815542 ZQ Calibration : PASS
2127 06:55:21.818458 Jitter Meter : NO K
2128 06:55:21.818877 CBT Training : PASS
2129 06:55:21.821774 Write leveling : PASS
2130 06:55:21.825401 RX DQS gating : PASS
2131 06:55:21.825966 RX DQ/DQS(RDDQC) : PASS
2132 06:55:21.828928 TX DQ/DQS : PASS
2133 06:55:21.832052 RX DATLAT : PASS
2134 06:55:21.832575 RX DQ/DQS(Engine): PASS
2135 06:55:21.835244 TX OE : NO K
2136 06:55:21.835667 All Pass.
2137 06:55:21.835999
2138 06:55:21.838616 CH 1, Rank 0
2139 06:55:21.839138 SW Impedance : PASS
2140 06:55:21.841735 DUTY Scan : NO K
2141 06:55:21.845327 ZQ Calibration : PASS
2142 06:55:21.845884 Jitter Meter : NO K
2143 06:55:21.848675 CBT Training : PASS
2144 06:55:21.849201 Write leveling : PASS
2145 06:55:21.852221 RX DQS gating : PASS
2146 06:55:21.855378 RX DQ/DQS(RDDQC) : PASS
2147 06:55:21.855962 TX DQ/DQS : PASS
2148 06:55:21.858656 RX DATLAT : PASS
2149 06:55:21.862094 RX DQ/DQS(Engine): PASS
2150 06:55:21.862637 TX OE : NO K
2151 06:55:21.865325 All Pass.
2152 06:55:21.865899
2153 06:55:21.866278 CH 1, Rank 1
2154 06:55:21.868852 SW Impedance : PASS
2155 06:55:21.869378 DUTY Scan : NO K
2156 06:55:21.871891 ZQ Calibration : PASS
2157 06:55:21.875178 Jitter Meter : NO K
2158 06:55:21.875703 CBT Training : PASS
2159 06:55:21.878545 Write leveling : PASS
2160 06:55:21.882066 RX DQS gating : PASS
2161 06:55:21.882592 RX DQ/DQS(RDDQC) : PASS
2162 06:55:21.885333 TX DQ/DQS : PASS
2163 06:55:21.888595 RX DATLAT : PASS
2164 06:55:21.889013 RX DQ/DQS(Engine): PASS
2165 06:55:21.892127 TX OE : NO K
2166 06:55:21.892656 All Pass.
2167 06:55:21.892989
2168 06:55:21.895599 DramC Write-DBI off
2169 06:55:21.898804 PER_BANK_REFRESH: Hybrid Mode
2170 06:55:21.899331 TX_TRACKING: ON
2171 06:55:21.902084 [GetDramInforAfterCalByMRR] Vendor 6.
2172 06:55:21.905110 [GetDramInforAfterCalByMRR] Revision 606.
2173 06:55:21.908378 [GetDramInforAfterCalByMRR] Revision 2 0.
2174 06:55:21.912264 MR0 0x3b3b
2175 06:55:21.912782 MR8 0x5151
2176 06:55:21.915675 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2177 06:55:21.916221
2178 06:55:21.916557 MR0 0x3b3b
2179 06:55:21.918557 MR8 0x5151
2180 06:55:21.921920 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2181 06:55:21.922338
2182 06:55:21.928752 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2183 06:55:21.932081 [FAST_K] Save calibration result to emmc
2184 06:55:21.938636 [FAST_K] Save calibration result to emmc
2185 06:55:21.939155 dram_init: config_dvfs: 1
2186 06:55:21.942124 dramc_set_vcore_voltage set vcore to 662500
2187 06:55:21.945190 Read voltage for 1200, 2
2188 06:55:21.945690 Vio18 = 0
2189 06:55:21.948746 Vcore = 662500
2190 06:55:21.949284 Vdram = 0
2191 06:55:21.949669 Vddq = 0
2192 06:55:21.951997 Vmddr = 0
2193 06:55:21.955319 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2194 06:55:21.962223 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2195 06:55:21.962750 MEM_TYPE=3, freq_sel=15
2196 06:55:21.965533 sv_algorithm_assistance_LP4_1600
2197 06:55:21.972171 ============ PULL DRAM RESETB DOWN ============
2198 06:55:21.975260 ========== PULL DRAM RESETB DOWN end =========
2199 06:55:21.978808 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2200 06:55:21.982227 ===================================
2201 06:55:21.985152 LPDDR4 DRAM CONFIGURATION
2202 06:55:21.988618 ===================================
2203 06:55:21.989039 EX_ROW_EN[0] = 0x0
2204 06:55:21.991827 EX_ROW_EN[1] = 0x0
2205 06:55:21.995255 LP4Y_EN = 0x0
2206 06:55:21.995675 WORK_FSP = 0x0
2207 06:55:21.998626 WL = 0x4
2208 06:55:21.999165 RL = 0x4
2209 06:55:22.002053 BL = 0x2
2210 06:55:22.002580 RPST = 0x0
2211 06:55:22.005118 RD_PRE = 0x0
2212 06:55:22.005579 WR_PRE = 0x1
2213 06:55:22.008702 WR_PST = 0x0
2214 06:55:22.009231 DBI_WR = 0x0
2215 06:55:22.012205 DBI_RD = 0x0
2216 06:55:22.012738 OTF = 0x1
2217 06:55:22.015321 ===================================
2218 06:55:22.018430 ===================================
2219 06:55:22.022193 ANA top config
2220 06:55:22.025410 ===================================
2221 06:55:22.025992 DLL_ASYNC_EN = 0
2222 06:55:22.028948 ALL_SLAVE_EN = 0
2223 06:55:22.032299 NEW_RANK_MODE = 1
2224 06:55:22.035284 DLL_IDLE_MODE = 1
2225 06:55:22.035751 LP45_APHY_COMB_EN = 1
2226 06:55:22.038674 TX_ODT_DIS = 1
2227 06:55:22.042050 NEW_8X_MODE = 1
2228 06:55:22.045369 ===================================
2229 06:55:22.048606 ===================================
2230 06:55:22.052458 data_rate = 2400
2231 06:55:22.055532 CKR = 1
2232 06:55:22.059082 DQ_P2S_RATIO = 8
2233 06:55:22.062431 ===================================
2234 06:55:22.062957 CA_P2S_RATIO = 8
2235 06:55:22.065714 DQ_CA_OPEN = 0
2236 06:55:22.068940 DQ_SEMI_OPEN = 0
2237 06:55:22.072234 CA_SEMI_OPEN = 0
2238 06:55:22.075716 CA_FULL_RATE = 0
2239 06:55:22.078848 DQ_CKDIV4_EN = 0
2240 06:55:22.079430 CA_CKDIV4_EN = 0
2241 06:55:22.081870 CA_PREDIV_EN = 0
2242 06:55:22.085107 PH8_DLY = 17
2243 06:55:22.088394 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2244 06:55:22.091959 DQ_AAMCK_DIV = 4
2245 06:55:22.094919 CA_AAMCK_DIV = 4
2246 06:55:22.095340 CA_ADMCK_DIV = 4
2247 06:55:22.098455 DQ_TRACK_CA_EN = 0
2248 06:55:22.101959 CA_PICK = 1200
2249 06:55:22.105391 CA_MCKIO = 1200
2250 06:55:22.108644 MCKIO_SEMI = 0
2251 06:55:22.112110 PLL_FREQ = 2366
2252 06:55:22.114818 DQ_UI_PI_RATIO = 32
2253 06:55:22.115251 CA_UI_PI_RATIO = 0
2254 06:55:22.118200 ===================================
2255 06:55:22.121925 ===================================
2256 06:55:22.125257 memory_type:LPDDR4
2257 06:55:22.128163 GP_NUM : 10
2258 06:55:22.128589 SRAM_EN : 1
2259 06:55:22.131453 MD32_EN : 0
2260 06:55:22.135011 ===================================
2261 06:55:22.138062 [ANA_INIT] >>>>>>>>>>>>>>
2262 06:55:22.141668 <<<<<< [CONFIGURE PHASE]: ANA_TX
2263 06:55:22.144958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2264 06:55:22.148610 ===================================
2265 06:55:22.149145 data_rate = 2400,PCW = 0X5b00
2266 06:55:22.151748 ===================================
2267 06:55:22.154788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2268 06:55:22.161565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2269 06:55:22.168758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2270 06:55:22.171800 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2271 06:55:22.175155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2272 06:55:22.178286 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2273 06:55:22.181565 [ANA_INIT] flow start
2274 06:55:22.182099 [ANA_INIT] PLL >>>>>>>>
2275 06:55:22.185119 [ANA_INIT] PLL <<<<<<<<
2276 06:55:22.188169 [ANA_INIT] MIDPI >>>>>>>>
2277 06:55:22.191414 [ANA_INIT] MIDPI <<<<<<<<
2278 06:55:22.191840 [ANA_INIT] DLL >>>>>>>>
2279 06:55:22.195026 [ANA_INIT] DLL <<<<<<<<
2280 06:55:22.195565 [ANA_INIT] flow end
2281 06:55:22.202035 ============ LP4 DIFF to SE enter ============
2282 06:55:22.205188 ============ LP4 DIFF to SE exit ============
2283 06:55:22.208438 [ANA_INIT] <<<<<<<<<<<<<
2284 06:55:22.212106 [Flow] Enable top DCM control >>>>>
2285 06:55:22.215141 [Flow] Enable top DCM control <<<<<
2286 06:55:22.215709 Enable DLL master slave shuffle
2287 06:55:22.221946 ==============================================================
2288 06:55:22.225050 Gating Mode config
2289 06:55:22.228492 ==============================================================
2290 06:55:22.231822 Config description:
2291 06:55:22.241764 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2292 06:55:22.248658 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2293 06:55:22.251806 SELPH_MODE 0: By rank 1: By Phase
2294 06:55:22.258217 ==============================================================
2295 06:55:22.261668 GAT_TRACK_EN = 1
2296 06:55:22.264920 RX_GATING_MODE = 2
2297 06:55:22.268132 RX_GATING_TRACK_MODE = 2
2298 06:55:22.268559 SELPH_MODE = 1
2299 06:55:22.271640 PICG_EARLY_EN = 1
2300 06:55:22.275277 VALID_LAT_VALUE = 1
2301 06:55:22.281932 ==============================================================
2302 06:55:22.285314 Enter into Gating configuration >>>>
2303 06:55:22.288160 Exit from Gating configuration <<<<
2304 06:55:22.291564 Enter into DVFS_PRE_config >>>>>
2305 06:55:22.301627 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2306 06:55:22.304956 Exit from DVFS_PRE_config <<<<<
2307 06:55:22.308348 Enter into PICG configuration >>>>
2308 06:55:22.311882 Exit from PICG configuration <<<<
2309 06:55:22.315154 [RX_INPUT] configuration >>>>>
2310 06:55:22.318299 [RX_INPUT] configuration <<<<<
2311 06:55:22.321437 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2312 06:55:22.328025 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2313 06:55:22.334948 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2314 06:55:22.341682 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2315 06:55:22.344722 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 06:55:22.351949 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 06:55:22.355320 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2318 06:55:22.361527 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2319 06:55:22.365215 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2320 06:55:22.368185 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2321 06:55:22.371427 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2322 06:55:22.378332 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2323 06:55:22.382029 ===================================
2324 06:55:22.382563 LPDDR4 DRAM CONFIGURATION
2325 06:55:22.385217 ===================================
2326 06:55:22.388063 EX_ROW_EN[0] = 0x0
2327 06:55:22.391496 EX_ROW_EN[1] = 0x0
2328 06:55:22.391927 LP4Y_EN = 0x0
2329 06:55:22.395083 WORK_FSP = 0x0
2330 06:55:22.395615 WL = 0x4
2331 06:55:22.398454 RL = 0x4
2332 06:55:22.398984 BL = 0x2
2333 06:55:22.401559 RPST = 0x0
2334 06:55:22.401989 RD_PRE = 0x0
2335 06:55:22.405162 WR_PRE = 0x1
2336 06:55:22.405740 WR_PST = 0x0
2337 06:55:22.408647 DBI_WR = 0x0
2338 06:55:22.409173 DBI_RD = 0x0
2339 06:55:22.411957 OTF = 0x1
2340 06:55:22.415321 ===================================
2341 06:55:22.418259 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2342 06:55:22.422087 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2343 06:55:22.428374 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2344 06:55:22.432012 ===================================
2345 06:55:22.432548 LPDDR4 DRAM CONFIGURATION
2346 06:55:22.435150 ===================================
2347 06:55:22.438187 EX_ROW_EN[0] = 0x10
2348 06:55:22.438613 EX_ROW_EN[1] = 0x0
2349 06:55:22.441779 LP4Y_EN = 0x0
2350 06:55:22.445115 WORK_FSP = 0x0
2351 06:55:22.445699 WL = 0x4
2352 06:55:22.448902 RL = 0x4
2353 06:55:22.449444 BL = 0x2
2354 06:55:22.451733 RPST = 0x0
2355 06:55:22.452159 RD_PRE = 0x0
2356 06:55:22.455225 WR_PRE = 0x1
2357 06:55:22.455653 WR_PST = 0x0
2358 06:55:22.458309 DBI_WR = 0x0
2359 06:55:22.458734 DBI_RD = 0x0
2360 06:55:22.462123 OTF = 0x1
2361 06:55:22.465257 ===================================
2362 06:55:22.468428 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2363 06:55:22.471531 ==
2364 06:55:22.475131 Dram Type= 6, Freq= 0, CH_0, rank 0
2365 06:55:22.478323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2366 06:55:22.478753 ==
2367 06:55:22.481587 [Duty_Offset_Calibration]
2368 06:55:22.482008 B0:2 B1:0 CA:4
2369 06:55:22.482339
2370 06:55:22.484743 [DutyScan_Calibration_Flow] k_type=0
2371 06:55:22.495085
2372 06:55:22.495606 ==CLK 0==
2373 06:55:22.498193 Final CLK duty delay cell = 0
2374 06:55:22.501917 [0] MAX Duty = 5031%(X100), DQS PI = 12
2375 06:55:22.504774 [0] MIN Duty = 4907%(X100), DQS PI = 8
2376 06:55:22.505302 [0] AVG Duty = 4969%(X100)
2377 06:55:22.505695
2378 06:55:22.508126 CH0 CLK Duty spec in!! Max-Min= 124%
2379 06:55:22.514784 [DutyScan_Calibration_Flow] ====Done====
2380 06:55:22.515333
2381 06:55:22.517716 [DutyScan_Calibration_Flow] k_type=1
2382 06:55:22.533186
2383 06:55:22.533752 ==DQS 0 ==
2384 06:55:22.536308 Final DQS duty delay cell = 0
2385 06:55:22.539702 [0] MAX Duty = 5062%(X100), DQS PI = 12
2386 06:55:22.542960 [0] MIN Duty = 4907%(X100), DQS PI = 46
2387 06:55:22.546217 [0] AVG Duty = 4984%(X100)
2388 06:55:22.546638
2389 06:55:22.547006 ==DQS 1 ==
2390 06:55:22.549997 Final DQS duty delay cell = -4
2391 06:55:22.552950 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2392 06:55:22.556658 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2393 06:55:22.559597 [-4] AVG Duty = 4937%(X100)
2394 06:55:22.560128
2395 06:55:22.563155 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2396 06:55:22.563574
2397 06:55:22.566826 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2398 06:55:22.570363 [DutyScan_Calibration_Flow] ====Done====
2399 06:55:22.570891
2400 06:55:22.573225 [DutyScan_Calibration_Flow] k_type=3
2401 06:55:22.589744
2402 06:55:22.590278 ==DQM 0 ==
2403 06:55:22.593308 Final DQM duty delay cell = 0
2404 06:55:22.596380 [0] MAX Duty = 5124%(X100), DQS PI = 28
2405 06:55:22.600161 [0] MIN Duty = 4876%(X100), DQS PI = 48
2406 06:55:22.603241 [0] AVG Duty = 5000%(X100)
2407 06:55:22.603769
2408 06:55:22.604106 ==DQM 1 ==
2409 06:55:22.606514 Final DQM duty delay cell = 0
2410 06:55:22.610076 [0] MAX Duty = 4969%(X100), DQS PI = 50
2411 06:55:22.613537 [0] MIN Duty = 4876%(X100), DQS PI = 8
2412 06:55:22.616768 [0] AVG Duty = 4922%(X100)
2413 06:55:22.617292
2414 06:55:22.620325 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2415 06:55:22.620859
2416 06:55:22.623533 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2417 06:55:22.626623 [DutyScan_Calibration_Flow] ====Done====
2418 06:55:22.627164
2419 06:55:22.629712 [DutyScan_Calibration_Flow] k_type=2
2420 06:55:22.644589
2421 06:55:22.645111 ==DQ 0 ==
2422 06:55:22.647935 Final DQ duty delay cell = -4
2423 06:55:22.651693 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2424 06:55:22.654393 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2425 06:55:22.657904 [-4] AVG Duty = 4969%(X100)
2426 06:55:22.658429
2427 06:55:22.658766 ==DQ 1 ==
2428 06:55:22.661298 Final DQ duty delay cell = -4
2429 06:55:22.664632 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2430 06:55:22.667788 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2431 06:55:22.671564 [-4] AVG Duty = 4938%(X100)
2432 06:55:22.672092
2433 06:55:22.674443 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2434 06:55:22.674866
2435 06:55:22.677938 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2436 06:55:22.681613 [DutyScan_Calibration_Flow] ====Done====
2437 06:55:22.682138 ==
2438 06:55:22.684628 Dram Type= 6, Freq= 0, CH_1, rank 0
2439 06:55:22.687908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2440 06:55:22.688336 ==
2441 06:55:22.691453 [Duty_Offset_Calibration]
2442 06:55:22.691913 B0:1 B1:-2 CA:0
2443 06:55:22.692254
2444 06:55:22.694619 [DutyScan_Calibration_Flow] k_type=0
2445 06:55:22.705929
2446 06:55:22.706357 ==CLK 0==
2447 06:55:22.709377 Final CLK duty delay cell = 4
2448 06:55:22.712751 [4] MAX Duty = 5156%(X100), DQS PI = 0
2449 06:55:22.715947 [4] MIN Duty = 5031%(X100), DQS PI = 18
2450 06:55:22.716381 [4] AVG Duty = 5093%(X100)
2451 06:55:22.716719
2452 06:55:22.719304 CH1 CLK Duty spec in!! Max-Min= 125%
2453 06:55:22.726422 [DutyScan_Calibration_Flow] ====Done====
2454 06:55:22.726946
2455 06:55:22.728977 [DutyScan_Calibration_Flow] k_type=1
2456 06:55:22.744272
2457 06:55:22.744704 ==DQS 0 ==
2458 06:55:22.747605 Final DQS duty delay cell = -4
2459 06:55:22.750866 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2460 06:55:22.754236 [-4] MIN Duty = 4907%(X100), DQS PI = 4
2461 06:55:22.757556 [-4] AVG Duty = 4953%(X100)
2462 06:55:22.757985
2463 06:55:22.758324 ==DQS 1 ==
2464 06:55:22.761072 Final DQS duty delay cell = 0
2465 06:55:22.764321 [0] MAX Duty = 5093%(X100), DQS PI = 32
2466 06:55:22.767576 [0] MIN Duty = 4844%(X100), DQS PI = 58
2467 06:55:22.770908 [0] AVG Duty = 4968%(X100)
2468 06:55:22.771343
2469 06:55:22.774214 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2470 06:55:22.774643
2471 06:55:22.777588 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2472 06:55:22.781334 [DutyScan_Calibration_Flow] ====Done====
2473 06:55:22.781970
2474 06:55:22.784229 [DutyScan_Calibration_Flow] k_type=3
2475 06:55:22.801215
2476 06:55:22.801779 ==DQM 0 ==
2477 06:55:22.804685 Final DQM duty delay cell = 0
2478 06:55:22.807578 [0] MAX Duty = 5000%(X100), DQS PI = 56
2479 06:55:22.811292 [0] MIN Duty = 4876%(X100), DQS PI = 20
2480 06:55:22.814741 [0] AVG Duty = 4938%(X100)
2481 06:55:22.815280
2482 06:55:22.815625 ==DQM 1 ==
2483 06:55:22.817637 Final DQM duty delay cell = 0
2484 06:55:22.820997 [0] MAX Duty = 5031%(X100), DQS PI = 4
2485 06:55:22.824656 [0] MIN Duty = 4907%(X100), DQS PI = 46
2486 06:55:22.825195 [0] AVG Duty = 4969%(X100)
2487 06:55:22.827947
2488 06:55:22.831066 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2489 06:55:22.831498
2490 06:55:22.834292 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2491 06:55:22.837690 [DutyScan_Calibration_Flow] ====Done====
2492 06:55:22.838230
2493 06:55:22.840924 [DutyScan_Calibration_Flow] k_type=2
2494 06:55:22.857254
2495 06:55:22.857835 ==DQ 0 ==
2496 06:55:22.860694 Final DQ duty delay cell = 0
2497 06:55:22.864264 [0] MAX Duty = 5062%(X100), DQS PI = 0
2498 06:55:22.867708 [0] MIN Duty = 4938%(X100), DQS PI = 22
2499 06:55:22.868245 [0] AVG Duty = 5000%(X100)
2500 06:55:22.868592
2501 06:55:22.870754 ==DQ 1 ==
2502 06:55:22.874455 Final DQ duty delay cell = 0
2503 06:55:22.877702 [0] MAX Duty = 5093%(X100), DQS PI = 2
2504 06:55:22.880655 [0] MIN Duty = 4938%(X100), DQS PI = 58
2505 06:55:22.881084 [0] AVG Duty = 5015%(X100)
2506 06:55:22.881422
2507 06:55:22.884137 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2508 06:55:22.884584
2509 06:55:22.887346 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2510 06:55:22.893977 [DutyScan_Calibration_Flow] ====Done====
2511 06:55:22.897560 nWR fixed to 30
2512 06:55:22.898107 [ModeRegInit_LP4] CH0 RK0
2513 06:55:22.900722 [ModeRegInit_LP4] CH0 RK1
2514 06:55:22.904226 [ModeRegInit_LP4] CH1 RK0
2515 06:55:22.904762 [ModeRegInit_LP4] CH1 RK1
2516 06:55:22.907832 match AC timing 7
2517 06:55:22.910919 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2518 06:55:22.914262 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2519 06:55:22.921071 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2520 06:55:22.924433 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2521 06:55:22.930756 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2522 06:55:22.931278 ==
2523 06:55:22.933880 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 06:55:22.937305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 06:55:22.937935 ==
2526 06:55:22.944445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2527 06:55:22.947362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2528 06:55:22.957321 [CA 0] Center 40 (10~71) winsize 62
2529 06:55:22.960910 [CA 1] Center 39 (9~70) winsize 62
2530 06:55:22.964067 [CA 2] Center 36 (6~66) winsize 61
2531 06:55:22.967443 [CA 3] Center 35 (5~66) winsize 62
2532 06:55:22.970896 [CA 4] Center 34 (4~65) winsize 62
2533 06:55:22.974112 [CA 5] Center 33 (3~64) winsize 62
2534 06:55:22.974638
2535 06:55:22.977465 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2536 06:55:22.978017
2537 06:55:22.980591 [CATrainingPosCal] consider 1 rank data
2538 06:55:22.983746 u2DelayCellTimex100 = 270/100 ps
2539 06:55:22.987535 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2540 06:55:22.993650 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2541 06:55:22.997717 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2542 06:55:23.000907 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2543 06:55:23.004176 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2544 06:55:23.007394 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2545 06:55:23.007825
2546 06:55:23.010711 CA PerBit enable=1, Macro0, CA PI delay=33
2547 06:55:23.011238
2548 06:55:23.014376 [CBTSetCACLKResult] CA Dly = 33
2549 06:55:23.014902 CS Dly: 7 (0~38)
2550 06:55:23.017558 ==
2551 06:55:23.020830 Dram Type= 6, Freq= 0, CH_0, rank 1
2552 06:55:23.024048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2553 06:55:23.024477 ==
2554 06:55:23.027710 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2555 06:55:23.034350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2556 06:55:23.043786 [CA 0] Center 40 (10~71) winsize 62
2557 06:55:23.046670 [CA 1] Center 40 (10~70) winsize 61
2558 06:55:23.050028 [CA 2] Center 35 (5~66) winsize 62
2559 06:55:23.053460 [CA 3] Center 35 (5~66) winsize 62
2560 06:55:23.057037 [CA 4] Center 34 (4~65) winsize 62
2561 06:55:23.060334 [CA 5] Center 33 (3~63) winsize 61
2562 06:55:23.060933
2563 06:55:23.063567 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2564 06:55:23.064091
2565 06:55:23.066999 [CATrainingPosCal] consider 2 rank data
2566 06:55:23.069955 u2DelayCellTimex100 = 270/100 ps
2567 06:55:23.073428 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2568 06:55:23.080292 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2569 06:55:23.083292 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2570 06:55:23.086904 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2571 06:55:23.090057 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2572 06:55:23.093601 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2573 06:55:23.094127
2574 06:55:23.096535 CA PerBit enable=1, Macro0, CA PI delay=33
2575 06:55:23.097064
2576 06:55:23.100065 [CBTSetCACLKResult] CA Dly = 33
2577 06:55:23.103428 CS Dly: 8 (0~40)
2578 06:55:23.103860
2579 06:55:23.106514 ----->DramcWriteLeveling(PI) begin...
2580 06:55:23.106950 ==
2581 06:55:23.110019 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 06:55:23.113522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 06:55:23.114060 ==
2584 06:55:23.116824 Write leveling (Byte 0): 34 => 34
2585 06:55:23.120046 Write leveling (Byte 1): 29 => 29
2586 06:55:23.123353 DramcWriteLeveling(PI) end<-----
2587 06:55:23.123776
2588 06:55:23.124112 ==
2589 06:55:23.126997 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 06:55:23.130058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 06:55:23.130666 ==
2592 06:55:23.133594 [Gating] SW mode calibration
2593 06:55:23.140404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2594 06:55:23.146928 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2595 06:55:23.150086 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 06:55:23.153646 0 15 4 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
2597 06:55:23.159981 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 06:55:23.163824 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 06:55:23.167308 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 06:55:23.170030 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 06:55:23.177019 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 06:55:23.180173 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2603 06:55:23.183190 1 0 0 | B1->B0 | 3232 2b2b | 0 0 | (0 1) (0 0)
2604 06:55:23.190211 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
2605 06:55:23.193255 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 06:55:23.196968 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 06:55:23.203670 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 06:55:23.206703 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 06:55:23.210298 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 06:55:23.217454 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 06:55:23.220778 1 1 0 | B1->B0 | 2727 3534 | 0 1 | (0 0) (0 0)
2612 06:55:23.223755 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2613 06:55:23.230357 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 06:55:23.233381 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 06:55:23.237132 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 06:55:23.243478 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 06:55:23.247120 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 06:55:23.250544 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2619 06:55:23.253817 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2620 06:55:23.260163 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2621 06:55:23.263724 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 06:55:23.267184 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 06:55:23.273668 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 06:55:23.277369 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 06:55:23.280255 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 06:55:23.286950 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 06:55:23.290337 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 06:55:23.293622 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 06:55:23.300353 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 06:55:23.303327 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 06:55:23.307201 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 06:55:23.313815 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 06:55:23.317068 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 06:55:23.320341 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2635 06:55:23.326495 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2636 06:55:23.330344 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2637 06:55:23.333521 Total UI for P1: 0, mck2ui 16
2638 06:55:23.337160 best dqsien dly found for B0: ( 1, 3, 30)
2639 06:55:23.340001 Total UI for P1: 0, mck2ui 16
2640 06:55:23.343216 best dqsien dly found for B1: ( 1, 4, 0)
2641 06:55:23.346426 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2642 06:55:23.349799 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2643 06:55:23.350224
2644 06:55:23.353542 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2645 06:55:23.356751 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2646 06:55:23.360310 [Gating] SW calibration Done
2647 06:55:23.360833 ==
2648 06:55:23.363381 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 06:55:23.366540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 06:55:23.367191 ==
2651 06:55:23.369731 RX Vref Scan: 0
2652 06:55:23.370155
2653 06:55:23.373247 RX Vref 0 -> 0, step: 1
2654 06:55:23.373826
2655 06:55:23.374173 RX Delay -40 -> 252, step: 8
2656 06:55:23.379686 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2657 06:55:23.383469 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2658 06:55:23.386610 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2659 06:55:23.390418 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2660 06:55:23.393688 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2661 06:55:23.400090 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2662 06:55:23.403156 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2663 06:55:23.406263 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2664 06:55:23.409533 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2665 06:55:23.413083 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2666 06:55:23.419892 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2667 06:55:23.422868 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2668 06:55:23.426226 iDelay=200, Bit 12, Center 103 (32 ~ 175) 144
2669 06:55:23.429294 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2670 06:55:23.432898 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2671 06:55:23.439771 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2672 06:55:23.440302 ==
2673 06:55:23.442998 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 06:55:23.446445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 06:55:23.446878 ==
2676 06:55:23.447224 DQS Delay:
2677 06:55:23.449515 DQS0 = 0, DQS1 = 0
2678 06:55:23.449947 DQM Delay:
2679 06:55:23.453056 DQM0 = 111, DQM1 = 101
2680 06:55:23.453520 DQ Delay:
2681 06:55:23.456630 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2682 06:55:23.459867 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2683 06:55:23.463407 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2684 06:55:23.466525 DQ12 =103, DQ13 =107, DQ14 =115, DQ15 =111
2685 06:55:23.467080
2686 06:55:23.467429
2687 06:55:23.467741 ==
2688 06:55:23.469731 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 06:55:23.476330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 06:55:23.476855 ==
2691 06:55:23.477195
2692 06:55:23.477599
2693 06:55:23.477909 TX Vref Scan disable
2694 06:55:23.479706 == TX Byte 0 ==
2695 06:55:23.483277 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2696 06:55:23.489861 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2697 06:55:23.490400 == TX Byte 1 ==
2698 06:55:23.493356 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2699 06:55:23.500082 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2700 06:55:23.500602 ==
2701 06:55:23.503306 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 06:55:23.506403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 06:55:23.506833 ==
2704 06:55:23.518203 TX Vref=22, minBit 1, minWin=25, winSum=413
2705 06:55:23.521354 TX Vref=24, minBit 7, minWin=25, winSum=421
2706 06:55:23.524760 TX Vref=26, minBit 2, minWin=26, winSum=427
2707 06:55:23.528166 TX Vref=28, minBit 4, minWin=26, winSum=429
2708 06:55:23.531801 TX Vref=30, minBit 8, minWin=26, winSum=428
2709 06:55:23.534497 TX Vref=32, minBit 2, minWin=26, winSum=426
2710 06:55:23.540958 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 28
2711 06:55:23.541384
2712 06:55:23.544446 Final TX Range 1 Vref 28
2713 06:55:23.544877
2714 06:55:23.545268 ==
2715 06:55:23.547945 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 06:55:23.551212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 06:55:23.551641 ==
2718 06:55:23.554276
2719 06:55:23.554704
2720 06:55:23.555041 TX Vref Scan disable
2721 06:55:23.557852 == TX Byte 0 ==
2722 06:55:23.560992 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2723 06:55:23.567910 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2724 06:55:23.568450 == TX Byte 1 ==
2725 06:55:23.570906 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2726 06:55:23.577982 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2727 06:55:23.578517
2728 06:55:23.578863 [DATLAT]
2729 06:55:23.579178 Freq=1200, CH0 RK0
2730 06:55:23.579485
2731 06:55:23.580923 DATLAT Default: 0xd
2732 06:55:23.581343 0, 0xFFFF, sum = 0
2733 06:55:23.584247 1, 0xFFFF, sum = 0
2734 06:55:23.587930 2, 0xFFFF, sum = 0
2735 06:55:23.588367 3, 0xFFFF, sum = 0
2736 06:55:23.591044 4, 0xFFFF, sum = 0
2737 06:55:23.591477 5, 0xFFFF, sum = 0
2738 06:55:23.594461 6, 0xFFFF, sum = 0
2739 06:55:23.595024 7, 0xFFFF, sum = 0
2740 06:55:23.598191 8, 0xFFFF, sum = 0
2741 06:55:23.598722 9, 0xFFFF, sum = 0
2742 06:55:23.601144 10, 0xFFFF, sum = 0
2743 06:55:23.601718 11, 0xFFFF, sum = 0
2744 06:55:23.604718 12, 0x0, sum = 1
2745 06:55:23.605247 13, 0x0, sum = 2
2746 06:55:23.608115 14, 0x0, sum = 3
2747 06:55:23.608642 15, 0x0, sum = 4
2748 06:55:23.608986 best_step = 13
2749 06:55:23.610973
2750 06:55:23.611394 ==
2751 06:55:23.614414 Dram Type= 6, Freq= 0, CH_0, rank 0
2752 06:55:23.617763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2753 06:55:23.618289 ==
2754 06:55:23.618630 RX Vref Scan: 1
2755 06:55:23.618944
2756 06:55:23.620844 Set Vref Range= 32 -> 127
2757 06:55:23.621284
2758 06:55:23.624442 RX Vref 32 -> 127, step: 1
2759 06:55:23.624865
2760 06:55:23.628086 RX Delay -37 -> 252, step: 4
2761 06:55:23.628606
2762 06:55:23.630792 Set Vref, RX VrefLevel [Byte0]: 32
2763 06:55:23.634168 [Byte1]: 32
2764 06:55:23.634693
2765 06:55:23.637971 Set Vref, RX VrefLevel [Byte0]: 33
2766 06:55:23.641088 [Byte1]: 33
2767 06:55:23.644409
2768 06:55:23.645044 Set Vref, RX VrefLevel [Byte0]: 34
2769 06:55:23.647526 [Byte1]: 34
2770 06:55:23.652632
2771 06:55:23.653149 Set Vref, RX VrefLevel [Byte0]: 35
2772 06:55:23.656071 [Byte1]: 35
2773 06:55:23.660327
2774 06:55:23.660792 Set Vref, RX VrefLevel [Byte0]: 36
2775 06:55:23.664008 [Byte1]: 36
2776 06:55:23.668399
2777 06:55:23.668917 Set Vref, RX VrefLevel [Byte0]: 37
2778 06:55:23.671909 [Byte1]: 37
2779 06:55:23.676614
2780 06:55:23.677131 Set Vref, RX VrefLevel [Byte0]: 38
2781 06:55:23.679936 [Byte1]: 38
2782 06:55:23.684487
2783 06:55:23.684916 Set Vref, RX VrefLevel [Byte0]: 39
2784 06:55:23.687905 [Byte1]: 39
2785 06:55:23.692551
2786 06:55:23.692975 Set Vref, RX VrefLevel [Byte0]: 40
2787 06:55:23.695854 [Byte1]: 40
2788 06:55:23.700680
2789 06:55:23.701204 Set Vref, RX VrefLevel [Byte0]: 41
2790 06:55:23.703966 [Byte1]: 41
2791 06:55:23.708668
2792 06:55:23.709190 Set Vref, RX VrefLevel [Byte0]: 42
2793 06:55:23.712022 [Byte1]: 42
2794 06:55:23.716818
2795 06:55:23.717340 Set Vref, RX VrefLevel [Byte0]: 43
2796 06:55:23.719742 [Byte1]: 43
2797 06:55:23.724612
2798 06:55:23.725035 Set Vref, RX VrefLevel [Byte0]: 44
2799 06:55:23.727788 [Byte1]: 44
2800 06:55:23.732602
2801 06:55:23.733122 Set Vref, RX VrefLevel [Byte0]: 45
2802 06:55:23.736042 [Byte1]: 45
2803 06:55:23.740940
2804 06:55:23.741463 Set Vref, RX VrefLevel [Byte0]: 46
2805 06:55:23.743877 [Byte1]: 46
2806 06:55:23.748737
2807 06:55:23.749261 Set Vref, RX VrefLevel [Byte0]: 47
2808 06:55:23.751587 [Byte1]: 47
2809 06:55:23.756673
2810 06:55:23.757210 Set Vref, RX VrefLevel [Byte0]: 48
2811 06:55:23.759757 [Byte1]: 48
2812 06:55:23.764763
2813 06:55:23.765337 Set Vref, RX VrefLevel [Byte0]: 49
2814 06:55:23.768159 [Byte1]: 49
2815 06:55:23.772402
2816 06:55:23.772919 Set Vref, RX VrefLevel [Byte0]: 50
2817 06:55:23.775759 [Byte1]: 50
2818 06:55:23.780509
2819 06:55:23.781025 Set Vref, RX VrefLevel [Byte0]: 51
2820 06:55:23.783804 [Byte1]: 51
2821 06:55:23.788529
2822 06:55:23.788990 Set Vref, RX VrefLevel [Byte0]: 52
2823 06:55:23.791594 [Byte1]: 52
2824 06:55:23.796414
2825 06:55:23.796839 Set Vref, RX VrefLevel [Byte0]: 53
2826 06:55:23.799854 [Byte1]: 53
2827 06:55:23.804423
2828 06:55:23.804948 Set Vref, RX VrefLevel [Byte0]: 54
2829 06:55:23.808213 [Byte1]: 54
2830 06:55:23.812730
2831 06:55:23.813258 Set Vref, RX VrefLevel [Byte0]: 55
2832 06:55:23.815918 [Byte1]: 55
2833 06:55:23.820544
2834 06:55:23.821059 Set Vref, RX VrefLevel [Byte0]: 56
2835 06:55:23.823839 [Byte1]: 56
2836 06:55:23.828876
2837 06:55:23.829393 Set Vref, RX VrefLevel [Byte0]: 57
2838 06:55:23.832191 [Byte1]: 57
2839 06:55:23.836802
2840 06:55:23.837325 Set Vref, RX VrefLevel [Byte0]: 58
2841 06:55:23.839962 [Byte1]: 58
2842 06:55:23.844629
2843 06:55:23.845135 Set Vref, RX VrefLevel [Byte0]: 59
2844 06:55:23.848222 [Byte1]: 59
2845 06:55:23.852564
2846 06:55:23.853140 Set Vref, RX VrefLevel [Byte0]: 60
2847 06:55:23.855949 [Byte1]: 60
2848 06:55:23.860378
2849 06:55:23.860806 Set Vref, RX VrefLevel [Byte0]: 61
2850 06:55:23.863401 [Byte1]: 61
2851 06:55:23.868436
2852 06:55:23.871900 Set Vref, RX VrefLevel [Byte0]: 62
2853 06:55:23.872397 [Byte1]: 62
2854 06:55:23.876431
2855 06:55:23.876870 Set Vref, RX VrefLevel [Byte0]: 63
2856 06:55:23.879562 [Byte1]: 63
2857 06:55:23.884767
2858 06:55:23.885290 Set Vref, RX VrefLevel [Byte0]: 64
2859 06:55:23.887709 [Byte1]: 64
2860 06:55:23.892463
2861 06:55:23.892883 Set Vref, RX VrefLevel [Byte0]: 65
2862 06:55:23.895860 [Byte1]: 65
2863 06:55:23.900656
2864 06:55:23.901175 Set Vref, RX VrefLevel [Byte0]: 66
2865 06:55:23.903925 [Byte1]: 66
2866 06:55:23.908693
2867 06:55:23.909214 Set Vref, RX VrefLevel [Byte0]: 67
2868 06:55:23.911956 [Byte1]: 67
2869 06:55:23.916562
2870 06:55:23.917078 Set Vref, RX VrefLevel [Byte0]: 68
2871 06:55:23.919888 [Byte1]: 68
2872 06:55:23.924554
2873 06:55:23.925122 Set Vref, RX VrefLevel [Byte0]: 69
2874 06:55:23.928132 [Byte1]: 69
2875 06:55:23.932789
2876 06:55:23.933305 Set Vref, RX VrefLevel [Byte0]: 70
2877 06:55:23.936021 [Byte1]: 70
2878 06:55:23.940717
2879 06:55:23.941242 Set Vref, RX VrefLevel [Byte0]: 71
2880 06:55:23.944057 [Byte1]: 71
2881 06:55:23.948983
2882 06:55:23.949559 Set Vref, RX VrefLevel [Byte0]: 72
2883 06:55:23.952034 [Byte1]: 72
2884 06:55:23.956381
2885 06:55:23.956803 Set Vref, RX VrefLevel [Byte0]: 73
2886 06:55:23.960262 [Byte1]: 73
2887 06:55:23.964697
2888 06:55:23.965225 Set Vref, RX VrefLevel [Byte0]: 74
2889 06:55:23.968105 [Byte1]: 74
2890 06:55:23.972812
2891 06:55:23.973333 Final RX Vref Byte 0 = 61 to rank0
2892 06:55:23.975827 Final RX Vref Byte 1 = 57 to rank0
2893 06:55:23.979520 Final RX Vref Byte 0 = 61 to rank1
2894 06:55:23.983020 Final RX Vref Byte 1 = 57 to rank1==
2895 06:55:23.985852 Dram Type= 6, Freq= 0, CH_0, rank 0
2896 06:55:23.992313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 06:55:23.992840 ==
2898 06:55:23.993182 DQS Delay:
2899 06:55:23.993551 DQS0 = 0, DQS1 = 0
2900 06:55:23.995551 DQM Delay:
2901 06:55:23.995981 DQM0 = 112, DQM1 = 102
2902 06:55:23.999058 DQ Delay:
2903 06:55:24.002508 DQ0 =112, DQ1 =112, DQ2 =110, DQ3 =108
2904 06:55:24.005853 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2905 06:55:24.009101 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2906 06:55:24.012885 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =108
2907 06:55:24.013435
2908 06:55:24.013830
2909 06:55:24.019386 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2910 06:55:24.022656 CH0 RK0: MR19=303, MR18=FDFD
2911 06:55:24.029231 CH0_RK0: MR19=0x303, MR18=0xFDFD, DQSOSC=411, MR23=63, INC=38, DEC=25
2912 06:55:24.029830
2913 06:55:24.032598 ----->DramcWriteLeveling(PI) begin...
2914 06:55:24.033070 ==
2915 06:55:24.035708 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 06:55:24.039384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 06:55:24.042245 ==
2918 06:55:24.042666 Write leveling (Byte 0): 32 => 32
2919 06:55:24.045641 Write leveling (Byte 1): 28 => 28
2920 06:55:24.048914 DramcWriteLeveling(PI) end<-----
2921 06:55:24.049333
2922 06:55:24.049713 ==
2923 06:55:24.052542 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 06:55:24.059266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 06:55:24.059778 ==
2926 06:55:24.060127 [Gating] SW mode calibration
2927 06:55:24.069404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2928 06:55:24.072673 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2929 06:55:24.076124 0 15 0 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
2930 06:55:24.082473 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 06:55:24.085742 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 06:55:24.089433 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2933 06:55:24.095883 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 06:55:24.099420 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2935 06:55:24.102472 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2936 06:55:24.109373 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2937 06:55:24.112719 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2938 06:55:24.115950 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 06:55:24.122534 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 06:55:24.125959 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 06:55:24.129278 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 06:55:24.135675 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 06:55:24.139328 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2944 06:55:24.142567 1 0 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2945 06:55:24.145831 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2946 06:55:24.152285 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 06:55:24.156201 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 06:55:24.159384 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 06:55:24.166114 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 06:55:24.169533 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 06:55:24.172801 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 06:55:24.179564 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2953 06:55:24.182701 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 06:55:24.185884 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 06:55:24.192774 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 06:55:24.196007 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 06:55:24.199716 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 06:55:24.206415 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 06:55:24.209711 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 06:55:24.212635 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 06:55:24.219529 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 06:55:24.222678 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 06:55:24.225778 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 06:55:24.232512 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 06:55:24.236230 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 06:55:24.239321 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 06:55:24.242578 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 06:55:24.248878 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2969 06:55:24.252233 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2970 06:55:24.255650 Total UI for P1: 0, mck2ui 16
2971 06:55:24.259076 best dqsien dly found for B0: ( 1, 3, 28)
2972 06:55:24.262638 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 06:55:24.265969 Total UI for P1: 0, mck2ui 16
2974 06:55:24.269535 best dqsien dly found for B1: ( 1, 4, 0)
2975 06:55:24.272840 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2976 06:55:24.275560 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2977 06:55:24.276006
2978 06:55:24.282506 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2979 06:55:24.286049 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2980 06:55:24.286571 [Gating] SW calibration Done
2981 06:55:24.289526 ==
2982 06:55:24.292754 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 06:55:24.296166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 06:55:24.296776 ==
2985 06:55:24.297124 RX Vref Scan: 0
2986 06:55:24.297439
2987 06:55:24.299091 RX Vref 0 -> 0, step: 1
2988 06:55:24.299511
2989 06:55:24.302792 RX Delay -40 -> 252, step: 8
2990 06:55:24.306090 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2991 06:55:24.309211 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2992 06:55:24.312851 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2993 06:55:24.319552 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2994 06:55:24.322367 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2995 06:55:24.326154 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2996 06:55:24.329235 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2997 06:55:24.332340 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2998 06:55:24.339256 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2999 06:55:24.342726 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
3000 06:55:24.345551 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3001 06:55:24.348918 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3002 06:55:24.352365 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3003 06:55:24.358914 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3004 06:55:24.362257 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3005 06:55:24.365949 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3006 06:55:24.366477 ==
3007 06:55:24.369148 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 06:55:24.372531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 06:55:24.373054 ==
3010 06:55:24.375733 DQS Delay:
3011 06:55:24.376157 DQS0 = 0, DQS1 = 0
3012 06:55:24.379481 DQM Delay:
3013 06:55:24.380001 DQM0 = 112, DQM1 = 102
3014 06:55:24.380339 DQ Delay:
3015 06:55:24.382597 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3016 06:55:24.389443 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
3017 06:55:24.392546 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
3018 06:55:24.396188 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3019 06:55:24.396851
3020 06:55:24.397194
3021 06:55:24.397538 ==
3022 06:55:24.399492 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 06:55:24.402583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 06:55:24.403104 ==
3025 06:55:24.403441
3026 06:55:24.403750
3027 06:55:24.405935 TX Vref Scan disable
3028 06:55:24.406458 == TX Byte 0 ==
3029 06:55:24.412878 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3030 06:55:24.415788 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3031 06:55:24.416172 == TX Byte 1 ==
3032 06:55:24.422694 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3033 06:55:24.426349 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3034 06:55:24.426877 ==
3035 06:55:24.429471 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 06:55:24.432467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 06:55:24.432919 ==
3038 06:55:24.445981 TX Vref=22, minBit 8, minWin=25, winSum=426
3039 06:55:24.449021 TX Vref=24, minBit 9, minWin=25, winSum=430
3040 06:55:24.452629 TX Vref=26, minBit 8, minWin=26, winSum=432
3041 06:55:24.456089 TX Vref=28, minBit 8, minWin=26, winSum=435
3042 06:55:24.459183 TX Vref=30, minBit 8, minWin=25, winSum=433
3043 06:55:24.465614 TX Vref=32, minBit 8, minWin=26, winSum=434
3044 06:55:24.468849 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 28
3045 06:55:24.469274
3046 06:55:24.472157 Final TX Range 1 Vref 28
3047 06:55:24.472685
3048 06:55:24.473021 ==
3049 06:55:24.475864 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 06:55:24.479009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 06:55:24.481983 ==
3052 06:55:24.482416
3053 06:55:24.482752
3054 06:55:24.483060 TX Vref Scan disable
3055 06:55:24.485315 == TX Byte 0 ==
3056 06:55:24.488848 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3057 06:55:24.492181 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3058 06:55:24.495812 == TX Byte 1 ==
3059 06:55:24.498603 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3060 06:55:24.502354 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3061 06:55:24.505637
3062 06:55:24.506057 [DATLAT]
3063 06:55:24.506392 Freq=1200, CH0 RK1
3064 06:55:24.506712
3065 06:55:24.509518 DATLAT Default: 0xd
3066 06:55:24.510049 0, 0xFFFF, sum = 0
3067 06:55:24.512277 1, 0xFFFF, sum = 0
3068 06:55:24.512707 2, 0xFFFF, sum = 0
3069 06:55:24.515727 3, 0xFFFF, sum = 0
3070 06:55:24.516259 4, 0xFFFF, sum = 0
3071 06:55:24.518684 5, 0xFFFF, sum = 0
3072 06:55:24.522452 6, 0xFFFF, sum = 0
3073 06:55:24.522979 7, 0xFFFF, sum = 0
3074 06:55:24.525851 8, 0xFFFF, sum = 0
3075 06:55:24.526378 9, 0xFFFF, sum = 0
3076 06:55:24.529310 10, 0xFFFF, sum = 0
3077 06:55:24.529893 11, 0xFFFF, sum = 0
3078 06:55:24.532398 12, 0x0, sum = 1
3079 06:55:24.532924 13, 0x0, sum = 2
3080 06:55:24.535917 14, 0x0, sum = 3
3081 06:55:24.536449 15, 0x0, sum = 4
3082 06:55:24.536797 best_step = 13
3083 06:55:24.537111
3084 06:55:24.538913 ==
3085 06:55:24.542442 Dram Type= 6, Freq= 0, CH_0, rank 1
3086 06:55:24.545726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 06:55:24.546287 ==
3088 06:55:24.546801 RX Vref Scan: 0
3089 06:55:24.547142
3090 06:55:24.548919 RX Vref 0 -> 0, step: 1
3091 06:55:24.549580
3092 06:55:24.552409 RX Delay -29 -> 252, step: 4
3093 06:55:24.555956 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3094 06:55:24.562473 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3095 06:55:24.566041 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3096 06:55:24.568745 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3097 06:55:24.572473 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3098 06:55:24.575809 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3099 06:55:24.579147 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3100 06:55:24.585381 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3101 06:55:24.588666 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3102 06:55:24.592373 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3103 06:55:24.595762 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3104 06:55:24.598727 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3105 06:55:24.605752 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3106 06:55:24.609163 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3107 06:55:24.612319 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3108 06:55:24.615834 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3109 06:55:24.616385 ==
3110 06:55:24.618998 Dram Type= 6, Freq= 0, CH_0, rank 1
3111 06:55:24.625366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 06:55:24.625946 ==
3113 06:55:24.626285 DQS Delay:
3114 06:55:24.628781 DQS0 = 0, DQS1 = 0
3115 06:55:24.629316 DQM Delay:
3116 06:55:24.629721 DQM0 = 110, DQM1 = 101
3117 06:55:24.632099 DQ Delay:
3118 06:55:24.635321 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3119 06:55:24.638930 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3120 06:55:24.642384 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3121 06:55:24.645681 DQ12 =110, DQ13 =108, DQ14 =114, DQ15 =110
3122 06:55:24.646102
3123 06:55:24.646434
3124 06:55:24.655613 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3125 06:55:24.656141 CH0 RK1: MR19=403, MR18=11F8
3126 06:55:24.661978 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3127 06:55:24.665302 [RxdqsGatingPostProcess] freq 1200
3128 06:55:24.672337 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3129 06:55:24.675502 best DQS0 dly(2T, 0.5T) = (0, 11)
3130 06:55:24.678603 best DQS1 dly(2T, 0.5T) = (0, 12)
3131 06:55:24.682083 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3132 06:55:24.685676 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3133 06:55:24.686201 best DQS0 dly(2T, 0.5T) = (0, 11)
3134 06:55:24.688834 best DQS1 dly(2T, 0.5T) = (0, 12)
3135 06:55:24.691953 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3136 06:55:24.695639 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3137 06:55:24.698688 Pre-setting of DQS Precalculation
3138 06:55:24.705696 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3139 06:55:24.706221 ==
3140 06:55:24.709011 Dram Type= 6, Freq= 0, CH_1, rank 0
3141 06:55:24.711985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 06:55:24.712413 ==
3143 06:55:24.719046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3144 06:55:24.722244 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3145 06:55:24.731839 [CA 0] Center 38 (8~68) winsize 61
3146 06:55:24.735189 [CA 1] Center 38 (8~69) winsize 62
3147 06:55:24.738269 [CA 2] Center 35 (5~65) winsize 61
3148 06:55:24.741896 [CA 3] Center 34 (4~65) winsize 62
3149 06:55:24.745347 [CA 4] Center 35 (5~65) winsize 61
3150 06:55:24.748964 [CA 5] Center 34 (4~64) winsize 61
3151 06:55:24.749559
3152 06:55:24.751646 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3153 06:55:24.752073
3154 06:55:24.755239 [CATrainingPosCal] consider 1 rank data
3155 06:55:24.758781 u2DelayCellTimex100 = 270/100 ps
3156 06:55:24.761765 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3157 06:55:24.765083 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
3158 06:55:24.772089 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3159 06:55:24.775358 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3160 06:55:24.778242 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3161 06:55:24.781935 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3162 06:55:24.782457
3163 06:55:24.785352 CA PerBit enable=1, Macro0, CA PI delay=34
3164 06:55:24.785918
3165 06:55:24.788554 [CBTSetCACLKResult] CA Dly = 34
3166 06:55:24.789085 CS Dly: 7 (0~38)
3167 06:55:24.789429 ==
3168 06:55:24.792039 Dram Type= 6, Freq= 0, CH_1, rank 1
3169 06:55:24.798602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 06:55:24.799132 ==
3171 06:55:24.802244 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3172 06:55:24.808868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3173 06:55:24.817623 [CA 0] Center 38 (8~68) winsize 61
3174 06:55:24.821025 [CA 1] Center 38 (8~69) winsize 62
3175 06:55:24.824203 [CA 2] Center 35 (5~66) winsize 62
3176 06:55:24.827337 [CA 3] Center 34 (4~65) winsize 62
3177 06:55:24.830511 [CA 4] Center 35 (5~66) winsize 62
3178 06:55:24.833928 [CA 5] Center 33 (3~64) winsize 62
3179 06:55:24.834387
3180 06:55:24.837264 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3181 06:55:24.837722
3182 06:55:24.840828 [CATrainingPosCal] consider 2 rank data
3183 06:55:24.844275 u2DelayCellTimex100 = 270/100 ps
3184 06:55:24.847700 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3185 06:55:24.850660 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
3186 06:55:24.857545 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3187 06:55:24.860800 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3188 06:55:24.864120 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3189 06:55:24.867226 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3190 06:55:24.867651
3191 06:55:24.870956 CA PerBit enable=1, Macro0, CA PI delay=34
3192 06:55:24.871482
3193 06:55:24.874071 [CBTSetCACLKResult] CA Dly = 34
3194 06:55:24.874530 CS Dly: 8 (0~41)
3195 06:55:24.874870
3196 06:55:24.877101 ----->DramcWriteLeveling(PI) begin...
3197 06:55:24.880835 ==
3198 06:55:24.883953 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 06:55:24.887182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 06:55:24.887613 ==
3201 06:55:24.890815 Write leveling (Byte 0): 25 => 25
3202 06:55:24.893975 Write leveling (Byte 1): 29 => 29
3203 06:55:24.897395 DramcWriteLeveling(PI) end<-----
3204 06:55:24.897999
3205 06:55:24.898351 ==
3206 06:55:24.900620 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 06:55:24.904072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 06:55:24.904498 ==
3209 06:55:24.907729 [Gating] SW mode calibration
3210 06:55:24.913880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3211 06:55:24.917387 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3212 06:55:24.924017 0 15 0 | B1->B0 | 2929 2a2a | 1 0 | (0 0) (0 0)
3213 06:55:24.927234 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 06:55:24.930731 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3215 06:55:24.937118 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 06:55:24.940433 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 06:55:24.944242 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3218 06:55:24.950448 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3219 06:55:24.953951 0 15 28 | B1->B0 | 3333 3434 | 0 0 | (0 1) (0 1)
3220 06:55:24.957008 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 06:55:24.963925 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 06:55:24.967265 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 06:55:24.971351 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 06:55:24.977300 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3225 06:55:24.980981 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3226 06:55:24.983810 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3227 06:55:24.990723 1 0 28 | B1->B0 | 3333 2a29 | 1 1 | (0 0) (0 0)
3228 06:55:24.993807 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 06:55:24.997201 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 06:55:25.004250 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 06:55:25.007302 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 06:55:25.010970 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 06:55:25.013982 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 06:55:25.020966 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 06:55:25.024478 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3236 06:55:25.027664 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 06:55:25.033848 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 06:55:25.037444 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 06:55:25.040861 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 06:55:25.047382 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 06:55:25.050643 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 06:55:25.053855 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 06:55:25.061014 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 06:55:25.064496 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 06:55:25.068014 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 06:55:25.073927 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 06:55:25.077426 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 06:55:25.081044 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 06:55:25.087831 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 06:55:25.090697 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 06:55:25.094178 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3252 06:55:25.097615 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3253 06:55:25.100955 Total UI for P1: 0, mck2ui 16
3254 06:55:25.104082 best dqsien dly found for B0: ( 1, 3, 28)
3255 06:55:25.111029 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 06:55:25.114259 Total UI for P1: 0, mck2ui 16
3257 06:55:25.117803 best dqsien dly found for B1: ( 1, 3, 30)
3258 06:55:25.120879 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3259 06:55:25.124494 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3260 06:55:25.125080
3261 06:55:25.127447 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3262 06:55:25.130800 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3263 06:55:25.133844 [Gating] SW calibration Done
3264 06:55:25.134266 ==
3265 06:55:25.137619 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 06:55:25.140937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 06:55:25.141463 ==
3268 06:55:25.144410 RX Vref Scan: 0
3269 06:55:25.144928
3270 06:55:25.145268 RX Vref 0 -> 0, step: 1
3271 06:55:25.147578
3272 06:55:25.148104 RX Delay -40 -> 252, step: 8
3273 06:55:25.154014 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3274 06:55:25.157005 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3275 06:55:25.160744 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3276 06:55:25.164188 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3277 06:55:25.167327 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3278 06:55:25.170688 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3279 06:55:25.177127 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3280 06:55:25.180746 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3281 06:55:25.183816 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3282 06:55:25.187550 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3283 06:55:25.190590 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3284 06:55:25.197381 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3285 06:55:25.200835 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3286 06:55:25.204282 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3287 06:55:25.207222 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3288 06:55:25.214069 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3289 06:55:25.214593 ==
3290 06:55:25.217376 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 06:55:25.220733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 06:55:25.221260 ==
3293 06:55:25.221648 DQS Delay:
3294 06:55:25.224143 DQS0 = 0, DQS1 = 0
3295 06:55:25.224671 DQM Delay:
3296 06:55:25.227446 DQM0 = 117, DQM1 = 108
3297 06:55:25.227970 DQ Delay:
3298 06:55:25.230388 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3299 06:55:25.233533 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3300 06:55:25.237026 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =103
3301 06:55:25.240592 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =111
3302 06:55:25.241155
3303 06:55:25.241680
3304 06:55:25.242146 ==
3305 06:55:25.243840 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 06:55:25.250416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 06:55:25.250943 ==
3308 06:55:25.251316
3309 06:55:25.251671
3310 06:55:25.251975 TX Vref Scan disable
3311 06:55:25.253772 == TX Byte 0 ==
3312 06:55:25.257029 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3313 06:55:25.264057 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3314 06:55:25.264589 == TX Byte 1 ==
3315 06:55:25.267674 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3316 06:55:25.274164 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3317 06:55:25.274690 ==
3318 06:55:25.277423 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 06:55:25.280627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 06:55:25.281152 ==
3321 06:55:25.292015 TX Vref=22, minBit 1, minWin=24, winSum=407
3322 06:55:25.295295 TX Vref=24, minBit 1, minWin=24, winSum=411
3323 06:55:25.298827 TX Vref=26, minBit 1, minWin=25, winSum=414
3324 06:55:25.302289 TX Vref=28, minBit 1, minWin=25, winSum=416
3325 06:55:25.305872 TX Vref=30, minBit 1, minWin=25, winSum=418
3326 06:55:25.309106 TX Vref=32, minBit 3, minWin=24, winSum=416
3327 06:55:25.315796 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 30
3328 06:55:25.316318
3329 06:55:25.319192 Final TX Range 1 Vref 30
3330 06:55:25.319720
3331 06:55:25.320058 ==
3332 06:55:25.322338 Dram Type= 6, Freq= 0, CH_1, rank 0
3333 06:55:25.325756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3334 06:55:25.326276 ==
3335 06:55:25.326618
3336 06:55:25.329012
3337 06:55:25.329556 TX Vref Scan disable
3338 06:55:25.331929 == TX Byte 0 ==
3339 06:55:25.335503 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3340 06:55:25.338905 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3341 06:55:25.342141 == TX Byte 1 ==
3342 06:55:25.345626 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3343 06:55:25.348974 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3344 06:55:25.349555
3345 06:55:25.352550 [DATLAT]
3346 06:55:25.353083 Freq=1200, CH1 RK0
3347 06:55:25.353423
3348 06:55:25.355806 DATLAT Default: 0xd
3349 06:55:25.356326 0, 0xFFFF, sum = 0
3350 06:55:25.358594 1, 0xFFFF, sum = 0
3351 06:55:25.359055 2, 0xFFFF, sum = 0
3352 06:55:25.362420 3, 0xFFFF, sum = 0
3353 06:55:25.362850 4, 0xFFFF, sum = 0
3354 06:55:25.365459 5, 0xFFFF, sum = 0
3355 06:55:25.365927 6, 0xFFFF, sum = 0
3356 06:55:25.369072 7, 0xFFFF, sum = 0
3357 06:55:25.369657 8, 0xFFFF, sum = 0
3358 06:55:25.371960 9, 0xFFFF, sum = 0
3359 06:55:25.375285 10, 0xFFFF, sum = 0
3360 06:55:25.375712 11, 0xFFFF, sum = 0
3361 06:55:25.378439 12, 0x0, sum = 1
3362 06:55:25.378863 13, 0x0, sum = 2
3363 06:55:25.379202 14, 0x0, sum = 3
3364 06:55:25.382037 15, 0x0, sum = 4
3365 06:55:25.382464 best_step = 13
3366 06:55:25.382797
3367 06:55:25.383105 ==
3368 06:55:25.385382 Dram Type= 6, Freq= 0, CH_1, rank 0
3369 06:55:25.391685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3370 06:55:25.392110 ==
3371 06:55:25.392444 RX Vref Scan: 1
3372 06:55:25.392754
3373 06:55:25.395283 Set Vref Range= 32 -> 127
3374 06:55:25.395705
3375 06:55:25.398694 RX Vref 32 -> 127, step: 1
3376 06:55:25.399296
3377 06:55:25.402034 RX Delay -21 -> 252, step: 4
3378 06:55:25.402552
3379 06:55:25.405212 Set Vref, RX VrefLevel [Byte0]: 32
3380 06:55:25.408471 [Byte1]: 32
3381 06:55:25.408995
3382 06:55:25.411956 Set Vref, RX VrefLevel [Byte0]: 33
3383 06:55:25.415528 [Byte1]: 33
3384 06:55:25.416049
3385 06:55:25.418461 Set Vref, RX VrefLevel [Byte0]: 34
3386 06:55:25.422100 [Byte1]: 34
3387 06:55:25.426420
3388 06:55:25.426940 Set Vref, RX VrefLevel [Byte0]: 35
3389 06:55:25.429756 [Byte1]: 35
3390 06:55:25.433939
3391 06:55:25.434466 Set Vref, RX VrefLevel [Byte0]: 36
3392 06:55:25.437178 [Byte1]: 36
3393 06:55:25.442162
3394 06:55:25.442891 Set Vref, RX VrefLevel [Byte0]: 37
3395 06:55:25.445243 [Byte1]: 37
3396 06:55:25.450080
3397 06:55:25.450578 Set Vref, RX VrefLevel [Byte0]: 38
3398 06:55:25.453083 [Byte1]: 38
3399 06:55:25.457980
3400 06:55:25.458658 Set Vref, RX VrefLevel [Byte0]: 39
3401 06:55:25.461067 [Byte1]: 39
3402 06:55:25.465894
3403 06:55:25.466408 Set Vref, RX VrefLevel [Byte0]: 40
3404 06:55:25.468897 [Byte1]: 40
3405 06:55:25.473418
3406 06:55:25.473989 Set Vref, RX VrefLevel [Byte0]: 41
3407 06:55:25.477100 [Byte1]: 41
3408 06:55:25.481814
3409 06:55:25.482331 Set Vref, RX VrefLevel [Byte0]: 42
3410 06:55:25.485165 [Byte1]: 42
3411 06:55:25.489749
3412 06:55:25.490266 Set Vref, RX VrefLevel [Byte0]: 43
3413 06:55:25.493180 [Byte1]: 43
3414 06:55:25.497615
3415 06:55:25.498128 Set Vref, RX VrefLevel [Byte0]: 44
3416 06:55:25.500717 [Byte1]: 44
3417 06:55:25.505562
3418 06:55:25.506071 Set Vref, RX VrefLevel [Byte0]: 45
3419 06:55:25.508888 [Byte1]: 45
3420 06:55:25.513354
3421 06:55:25.513990 Set Vref, RX VrefLevel [Byte0]: 46
3422 06:55:25.516437 [Byte1]: 46
3423 06:55:25.521454
3424 06:55:25.522024 Set Vref, RX VrefLevel [Byte0]: 47
3425 06:55:25.524453 [Byte1]: 47
3426 06:55:25.529672
3427 06:55:25.530214 Set Vref, RX VrefLevel [Byte0]: 48
3428 06:55:25.532527 [Byte1]: 48
3429 06:55:25.537064
3430 06:55:25.537626 Set Vref, RX VrefLevel [Byte0]: 49
3431 06:55:25.540649 [Byte1]: 49
3432 06:55:25.544914
3433 06:55:25.545433 Set Vref, RX VrefLevel [Byte0]: 50
3434 06:55:25.548336 [Byte1]: 50
3435 06:55:25.552854
3436 06:55:25.553578 Set Vref, RX VrefLevel [Byte0]: 51
3437 06:55:25.555946 [Byte1]: 51
3438 06:55:25.560966
3439 06:55:25.561539 Set Vref, RX VrefLevel [Byte0]: 52
3440 06:55:25.563876 [Byte1]: 52
3441 06:55:25.568743
3442 06:55:25.569277 Set Vref, RX VrefLevel [Byte0]: 53
3443 06:55:25.572276 [Byte1]: 53
3444 06:55:25.577093
3445 06:55:25.577715 Set Vref, RX VrefLevel [Byte0]: 54
3446 06:55:25.579858 [Byte1]: 54
3447 06:55:25.584498
3448 06:55:25.585153 Set Vref, RX VrefLevel [Byte0]: 55
3449 06:55:25.587609 [Byte1]: 55
3450 06:55:25.592403
3451 06:55:25.592841 Set Vref, RX VrefLevel [Byte0]: 56
3452 06:55:25.595644 [Byte1]: 56
3453 06:55:25.600721
3454 06:55:25.601257 Set Vref, RX VrefLevel [Byte0]: 57
3455 06:55:25.604057 [Byte1]: 57
3456 06:55:25.608447
3457 06:55:25.608987 Set Vref, RX VrefLevel [Byte0]: 58
3458 06:55:25.611691 [Byte1]: 58
3459 06:55:25.616460
3460 06:55:25.617004 Set Vref, RX VrefLevel [Byte0]: 59
3461 06:55:25.620068 [Byte1]: 59
3462 06:55:25.624241
3463 06:55:25.624778 Set Vref, RX VrefLevel [Byte0]: 60
3464 06:55:25.627218 [Byte1]: 60
3465 06:55:25.632220
3466 06:55:25.632760 Set Vref, RX VrefLevel [Byte0]: 61
3467 06:55:25.635562 [Byte1]: 61
3468 06:55:25.640269
3469 06:55:25.640816 Set Vref, RX VrefLevel [Byte0]: 62
3470 06:55:25.643726 [Byte1]: 62
3471 06:55:25.647870
3472 06:55:25.648407 Set Vref, RX VrefLevel [Byte0]: 63
3473 06:55:25.651098 [Byte1]: 63
3474 06:55:25.655546
3475 06:55:25.656101 Set Vref, RX VrefLevel [Byte0]: 64
3476 06:55:25.659288 [Byte1]: 64
3477 06:55:25.663799
3478 06:55:25.664225 Set Vref, RX VrefLevel [Byte0]: 65
3479 06:55:25.667424 [Byte1]: 65
3480 06:55:25.671729
3481 06:55:25.672252 Set Vref, RX VrefLevel [Byte0]: 66
3482 06:55:25.674987 [Byte1]: 66
3483 06:55:25.679613
3484 06:55:25.680133 Final RX Vref Byte 0 = 55 to rank0
3485 06:55:25.683298 Final RX Vref Byte 1 = 55 to rank0
3486 06:55:25.686079 Final RX Vref Byte 0 = 55 to rank1
3487 06:55:25.689674 Final RX Vref Byte 1 = 55 to rank1==
3488 06:55:25.692936 Dram Type= 6, Freq= 0, CH_1, rank 0
3489 06:55:25.699551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 06:55:25.700071 ==
3491 06:55:25.700410 DQS Delay:
3492 06:55:25.700727 DQS0 = 0, DQS1 = 0
3493 06:55:25.702637 DQM Delay:
3494 06:55:25.703061 DQM0 = 116, DQM1 = 111
3495 06:55:25.706061 DQ Delay:
3496 06:55:25.709400 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =116
3497 06:55:25.713185 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =114
3498 06:55:25.716109 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3499 06:55:25.719609 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3500 06:55:25.720139
3501 06:55:25.720474
3502 06:55:25.729563 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3503 06:55:25.730108 CH1 RK0: MR19=303, MR18=F0F7
3504 06:55:25.736107 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3505 06:55:25.736615
3506 06:55:25.739291 ----->DramcWriteLeveling(PI) begin...
3507 06:55:25.739718 ==
3508 06:55:25.743154 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 06:55:25.745919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 06:55:25.749451 ==
3511 06:55:25.750008 Write leveling (Byte 0): 23 => 23
3512 06:55:25.753209 Write leveling (Byte 1): 28 => 28
3513 06:55:25.756310 DramcWriteLeveling(PI) end<-----
3514 06:55:25.756758
3515 06:55:25.757178 ==
3516 06:55:25.759821 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 06:55:25.765996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 06:55:25.766523 ==
3519 06:55:25.769232 [Gating] SW mode calibration
3520 06:55:25.776004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3521 06:55:25.779397 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3522 06:55:25.786067 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3523 06:55:25.789510 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 06:55:25.792845 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 06:55:25.796515 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 06:55:25.802940 0 15 16 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
3527 06:55:25.806452 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3528 06:55:25.809527 0 15 24 | B1->B0 | 3434 2929 | 1 1 | (1 0) (1 0)
3529 06:55:25.816031 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
3530 06:55:25.819689 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 06:55:25.823131 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 06:55:25.829861 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 06:55:25.833183 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 06:55:25.836105 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 06:55:25.842938 1 0 20 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
3536 06:55:25.846194 1 0 24 | B1->B0 | 2727 4343 | 0 0 | (0 0) (0 0)
3537 06:55:25.849593 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3538 06:55:25.855914 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 06:55:25.859627 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 06:55:25.862749 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 06:55:25.869580 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 06:55:25.873199 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 06:55:25.876207 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 06:55:25.882856 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3545 06:55:25.885663 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3546 06:55:25.889132 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 06:55:25.895564 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 06:55:25.899128 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 06:55:25.902425 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 06:55:25.908848 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 06:55:25.912363 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 06:55:25.915486 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 06:55:25.919362 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 06:55:25.925874 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 06:55:25.929579 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 06:55:25.932196 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 06:55:25.939113 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 06:55:25.942245 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 06:55:25.945726 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 06:55:25.952611 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3561 06:55:25.955792 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3562 06:55:25.959110 Total UI for P1: 0, mck2ui 16
3563 06:55:25.962133 best dqsien dly found for B0: ( 1, 3, 24)
3564 06:55:25.965636 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3565 06:55:25.969334 Total UI for P1: 0, mck2ui 16
3566 06:55:25.972309 best dqsien dly found for B1: ( 1, 3, 26)
3567 06:55:25.975444 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3568 06:55:25.978778 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3569 06:55:25.979285
3570 06:55:25.985524 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3571 06:55:25.988707 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3572 06:55:25.992390 [Gating] SW calibration Done
3573 06:55:25.992932 ==
3574 06:55:25.995366 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 06:55:25.998282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 06:55:25.998738 ==
3577 06:55:25.999210 RX Vref Scan: 0
3578 06:55:25.999651
3579 06:55:26.002076 RX Vref 0 -> 0, step: 1
3580 06:55:26.002516
3581 06:55:26.005581 RX Delay -40 -> 252, step: 8
3582 06:55:26.008641 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3583 06:55:26.012197 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3584 06:55:26.018200 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3585 06:55:26.021933 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3586 06:55:26.024786 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3587 06:55:26.028447 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3588 06:55:26.032063 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3589 06:55:26.038329 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3590 06:55:26.041814 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3591 06:55:26.045224 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3592 06:55:26.048613 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3593 06:55:26.051963 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3594 06:55:26.058179 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3595 06:55:26.061776 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3596 06:55:26.065268 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3597 06:55:26.068613 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3598 06:55:26.069139 ==
3599 06:55:26.071559 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 06:55:26.078474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 06:55:26.079003 ==
3602 06:55:26.079343 DQS Delay:
3603 06:55:26.079661 DQS0 = 0, DQS1 = 0
3604 06:55:26.081556 DQM Delay:
3605 06:55:26.082011 DQM0 = 114, DQM1 = 112
3606 06:55:26.085099 DQ Delay:
3607 06:55:26.088088 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3608 06:55:26.091252 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3609 06:55:26.094583 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3610 06:55:26.098164 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3611 06:55:26.098606
3612 06:55:26.099161
3613 06:55:26.099519 ==
3614 06:55:26.101661 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 06:55:26.104600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 06:55:26.105029 ==
3617 06:55:26.108088
3618 06:55:26.108506
3619 06:55:26.108842 TX Vref Scan disable
3620 06:55:26.111520 == TX Byte 0 ==
3621 06:55:26.114771 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3622 06:55:26.118078 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3623 06:55:26.121369 == TX Byte 1 ==
3624 06:55:26.124449 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3625 06:55:26.127942 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3626 06:55:26.128478 ==
3627 06:55:26.131812 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 06:55:26.138116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 06:55:26.138640 ==
3630 06:55:26.148864 TX Vref=22, minBit 1, minWin=24, winSum=404
3631 06:55:26.152008 TX Vref=24, minBit 1, minWin=25, winSum=415
3632 06:55:26.155349 TX Vref=26, minBit 1, minWin=25, winSum=417
3633 06:55:26.158799 TX Vref=28, minBit 1, minWin=25, winSum=421
3634 06:55:26.162002 TX Vref=30, minBit 1, minWin=25, winSum=421
3635 06:55:26.165986 TX Vref=32, minBit 3, minWin=25, winSum=418
3636 06:55:26.172193 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
3637 06:55:26.172715
3638 06:55:26.175765 Final TX Range 1 Vref 28
3639 06:55:26.176290
3640 06:55:26.176627 ==
3641 06:55:26.178438 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 06:55:26.181685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 06:55:26.185456 ==
3644 06:55:26.186112
3645 06:55:26.186456
3646 06:55:26.186769 TX Vref Scan disable
3647 06:55:26.188681 == TX Byte 0 ==
3648 06:55:26.192137 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3649 06:55:26.195841 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3650 06:55:26.198623 == TX Byte 1 ==
3651 06:55:26.201985 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3652 06:55:26.208652 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3653 06:55:26.209177
3654 06:55:26.209562 [DATLAT]
3655 06:55:26.209889 Freq=1200, CH1 RK1
3656 06:55:26.210191
3657 06:55:26.211914 DATLAT Default: 0xd
3658 06:55:26.212440 0, 0xFFFF, sum = 0
3659 06:55:26.215429 1, 0xFFFF, sum = 0
3660 06:55:26.215962 2, 0xFFFF, sum = 0
3661 06:55:26.218459 3, 0xFFFF, sum = 0
3662 06:55:26.222054 4, 0xFFFF, sum = 0
3663 06:55:26.222583 5, 0xFFFF, sum = 0
3664 06:55:26.225680 6, 0xFFFF, sum = 0
3665 06:55:26.226207 7, 0xFFFF, sum = 0
3666 06:55:26.228683 8, 0xFFFF, sum = 0
3667 06:55:26.229208 9, 0xFFFF, sum = 0
3668 06:55:26.232004 10, 0xFFFF, sum = 0
3669 06:55:26.232545 11, 0xFFFF, sum = 0
3670 06:55:26.235012 12, 0x0, sum = 1
3671 06:55:26.235439 13, 0x0, sum = 2
3672 06:55:26.238375 14, 0x0, sum = 3
3673 06:55:26.238801 15, 0x0, sum = 4
3674 06:55:26.241789 best_step = 13
3675 06:55:26.242211
3676 06:55:26.242541 ==
3677 06:55:26.245134 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 06:55:26.248210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 06:55:26.248634 ==
3680 06:55:26.248970 RX Vref Scan: 0
3681 06:55:26.249299
3682 06:55:26.251272 RX Vref 0 -> 0, step: 1
3683 06:55:26.251783
3684 06:55:26.254707 RX Delay -21 -> 252, step: 4
3685 06:55:26.257927 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3686 06:55:26.264662 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3687 06:55:26.267882 iDelay=195, Bit 2, Center 104 (39 ~ 170) 132
3688 06:55:26.271402 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3689 06:55:26.274209 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3690 06:55:26.277441 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3691 06:55:26.284633 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3692 06:55:26.287523 iDelay=195, Bit 7, Center 112 (47 ~ 178) 132
3693 06:55:26.291070 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3694 06:55:26.294215 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3695 06:55:26.300797 iDelay=195, Bit 10, Center 116 (51 ~ 182) 132
3696 06:55:26.304191 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3697 06:55:26.307248 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3698 06:55:26.310736 iDelay=195, Bit 13, Center 122 (59 ~ 186) 128
3699 06:55:26.313810 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3700 06:55:26.320422 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3701 06:55:26.320505 ==
3702 06:55:26.323730 Dram Type= 6, Freq= 0, CH_1, rank 1
3703 06:55:26.327139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3704 06:55:26.327222 ==
3705 06:55:26.327287 DQS Delay:
3706 06:55:26.330494 DQS0 = 0, DQS1 = 0
3707 06:55:26.330576 DQM Delay:
3708 06:55:26.333838 DQM0 = 113, DQM1 = 114
3709 06:55:26.333921 DQ Delay:
3710 06:55:26.337017 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =110
3711 06:55:26.340509 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =112
3712 06:55:26.343820 DQ8 =100, DQ9 =104, DQ10 =116, DQ11 =106
3713 06:55:26.347647 DQ12 =122, DQ13 =122, DQ14 =120, DQ15 =124
3714 06:55:26.348085
3715 06:55:26.350706
3716 06:55:26.357418 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3717 06:55:26.361043 CH1 RK1: MR19=304, MR18=FB0B
3718 06:55:26.367219 CH1_RK1: MR19=0x304, MR18=0xFB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3719 06:55:26.370473 [RxdqsGatingPostProcess] freq 1200
3720 06:55:26.373776 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3721 06:55:26.377276 best DQS0 dly(2T, 0.5T) = (0, 11)
3722 06:55:26.380333 best DQS1 dly(2T, 0.5T) = (0, 11)
3723 06:55:26.383525 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3724 06:55:26.387028 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3725 06:55:26.390364 best DQS0 dly(2T, 0.5T) = (0, 11)
3726 06:55:26.393523 best DQS1 dly(2T, 0.5T) = (0, 11)
3727 06:55:26.396845 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3728 06:55:26.400459 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3729 06:55:26.403746 Pre-setting of DQS Precalculation
3730 06:55:26.406781 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3731 06:55:26.413663 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3732 06:55:26.423531 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3733 06:55:26.423732
3734 06:55:26.423833
3735 06:55:26.426691 [Calibration Summary] 2400 Mbps
3736 06:55:26.426891 CH 0, Rank 0
3737 06:55:26.430131 SW Impedance : PASS
3738 06:55:26.430342 DUTY Scan : NO K
3739 06:55:26.433196 ZQ Calibration : PASS
3740 06:55:26.436713 Jitter Meter : NO K
3741 06:55:26.436911 CBT Training : PASS
3742 06:55:26.440059 Write leveling : PASS
3743 06:55:26.443620 RX DQS gating : PASS
3744 06:55:26.443894 RX DQ/DQS(RDDQC) : PASS
3745 06:55:26.446528 TX DQ/DQS : PASS
3746 06:55:26.446805 RX DATLAT : PASS
3747 06:55:26.449914 RX DQ/DQS(Engine): PASS
3748 06:55:26.453367 TX OE : NO K
3749 06:55:26.453757 All Pass.
3750 06:55:26.453984
3751 06:55:26.454180 CH 0, Rank 1
3752 06:55:26.456748 SW Impedance : PASS
3753 06:55:26.460063 DUTY Scan : NO K
3754 06:55:26.460571 ZQ Calibration : PASS
3755 06:55:26.463286 Jitter Meter : NO K
3756 06:55:26.466614 CBT Training : PASS
3757 06:55:26.467045 Write leveling : PASS
3758 06:55:26.470188 RX DQS gating : PASS
3759 06:55:26.473788 RX DQ/DQS(RDDQC) : PASS
3760 06:55:26.474337 TX DQ/DQS : PASS
3761 06:55:26.476936 RX DATLAT : PASS
3762 06:55:26.479700 RX DQ/DQS(Engine): PASS
3763 06:55:26.480132 TX OE : NO K
3764 06:55:26.483414 All Pass.
3765 06:55:26.483949
3766 06:55:26.484291 CH 1, Rank 0
3767 06:55:26.486407 SW Impedance : PASS
3768 06:55:26.486836 DUTY Scan : NO K
3769 06:55:26.489605 ZQ Calibration : PASS
3770 06:55:26.493204 Jitter Meter : NO K
3771 06:55:26.493790 CBT Training : PASS
3772 06:55:26.496673 Write leveling : PASS
3773 06:55:26.499721 RX DQS gating : PASS
3774 06:55:26.500157 RX DQ/DQS(RDDQC) : PASS
3775 06:55:26.503069 TX DQ/DQS : PASS
3776 06:55:26.506190 RX DATLAT : PASS
3777 06:55:26.506621 RX DQ/DQS(Engine): PASS
3778 06:55:26.509531 TX OE : NO K
3779 06:55:26.510067 All Pass.
3780 06:55:26.510408
3781 06:55:26.513107 CH 1, Rank 1
3782 06:55:26.513779 SW Impedance : PASS
3783 06:55:26.516614 DUTY Scan : NO K
3784 06:55:26.517042 ZQ Calibration : PASS
3785 06:55:26.519890 Jitter Meter : NO K
3786 06:55:26.523035 CBT Training : PASS
3787 06:55:26.523471 Write leveling : PASS
3788 06:55:26.526179 RX DQS gating : PASS
3789 06:55:26.529257 RX DQ/DQS(RDDQC) : PASS
3790 06:55:26.529737 TX DQ/DQS : PASS
3791 06:55:26.532624 RX DATLAT : PASS
3792 06:55:26.535877 RX DQ/DQS(Engine): PASS
3793 06:55:26.536307 TX OE : NO K
3794 06:55:26.539878 All Pass.
3795 06:55:26.540406
3796 06:55:26.540746 DramC Write-DBI off
3797 06:55:26.543141 PER_BANK_REFRESH: Hybrid Mode
3798 06:55:26.543732 TX_TRACKING: ON
3799 06:55:26.552771 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3800 06:55:26.556129 [FAST_K] Save calibration result to emmc
3801 06:55:26.559301 dramc_set_vcore_voltage set vcore to 650000
3802 06:55:26.562497 Read voltage for 600, 5
3803 06:55:26.562925 Vio18 = 0
3804 06:55:26.565778 Vcore = 650000
3805 06:55:26.566205 Vdram = 0
3806 06:55:26.566541 Vddq = 0
3807 06:55:26.569703 Vmddr = 0
3808 06:55:26.572753 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3809 06:55:26.579166 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3810 06:55:26.579704 MEM_TYPE=3, freq_sel=19
3811 06:55:26.582413 sv_algorithm_assistance_LP4_1600
3812 06:55:26.589587 ============ PULL DRAM RESETB DOWN ============
3813 06:55:26.592095 ========== PULL DRAM RESETB DOWN end =========
3814 06:55:26.596056 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3815 06:55:26.598988 ===================================
3816 06:55:26.602082 LPDDR4 DRAM CONFIGURATION
3817 06:55:26.605459 ===================================
3818 06:55:26.609214 EX_ROW_EN[0] = 0x0
3819 06:55:26.609957 EX_ROW_EN[1] = 0x0
3820 06:55:26.612095 LP4Y_EN = 0x0
3821 06:55:26.612523 WORK_FSP = 0x0
3822 06:55:26.616018 WL = 0x2
3823 06:55:26.616612 RL = 0x2
3824 06:55:26.618917 BL = 0x2
3825 06:55:26.619348 RPST = 0x0
3826 06:55:26.622246 RD_PRE = 0x0
3827 06:55:26.622674 WR_PRE = 0x1
3828 06:55:26.625695 WR_PST = 0x0
3829 06:55:26.626215 DBI_WR = 0x0
3830 06:55:26.628868 DBI_RD = 0x0
3831 06:55:26.629404 OTF = 0x1
3832 06:55:26.632140 ===================================
3833 06:55:26.635213 ===================================
3834 06:55:26.638666 ANA top config
3835 06:55:26.642286 ===================================
3836 06:55:26.645307 DLL_ASYNC_EN = 0
3837 06:55:26.645883 ALL_SLAVE_EN = 1
3838 06:55:26.648582 NEW_RANK_MODE = 1
3839 06:55:26.651818 DLL_IDLE_MODE = 1
3840 06:55:26.655247 LP45_APHY_COMB_EN = 1
3841 06:55:26.655773 TX_ODT_DIS = 1
3842 06:55:26.658429 NEW_8X_MODE = 1
3843 06:55:26.661950 ===================================
3844 06:55:26.665137 ===================================
3845 06:55:26.668476 data_rate = 1200
3846 06:55:26.672104 CKR = 1
3847 06:55:26.675463 DQ_P2S_RATIO = 8
3848 06:55:26.678955 ===================================
3849 06:55:26.681589 CA_P2S_RATIO = 8
3850 06:55:26.682020 DQ_CA_OPEN = 0
3851 06:55:26.685331 DQ_SEMI_OPEN = 0
3852 06:55:26.688673 CA_SEMI_OPEN = 0
3853 06:55:26.691696 CA_FULL_RATE = 0
3854 06:55:26.694959 DQ_CKDIV4_EN = 1
3855 06:55:26.698461 CA_CKDIV4_EN = 1
3856 06:55:26.698999 CA_PREDIV_EN = 0
3857 06:55:26.701991 PH8_DLY = 0
3858 06:55:26.705145 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3859 06:55:26.708526 DQ_AAMCK_DIV = 4
3860 06:55:26.711713 CA_AAMCK_DIV = 4
3861 06:55:26.714740 CA_ADMCK_DIV = 4
3862 06:55:26.715259 DQ_TRACK_CA_EN = 0
3863 06:55:26.718041 CA_PICK = 600
3864 06:55:26.721195 CA_MCKIO = 600
3865 06:55:26.724937 MCKIO_SEMI = 0
3866 06:55:26.728160 PLL_FREQ = 2288
3867 06:55:26.731103 DQ_UI_PI_RATIO = 32
3868 06:55:26.734591 CA_UI_PI_RATIO = 0
3869 06:55:26.738038 ===================================
3870 06:55:26.741165 ===================================
3871 06:55:26.741717 memory_type:LPDDR4
3872 06:55:26.744975 GP_NUM : 10
3873 06:55:26.747748 SRAM_EN : 1
3874 06:55:26.748181 MD32_EN : 0
3875 06:55:26.751412 ===================================
3876 06:55:26.754640 [ANA_INIT] >>>>>>>>>>>>>>
3877 06:55:26.757702 <<<<<< [CONFIGURE PHASE]: ANA_TX
3878 06:55:26.761848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3879 06:55:26.764831 ===================================
3880 06:55:26.767927 data_rate = 1200,PCW = 0X5800
3881 06:55:26.771284 ===================================
3882 06:55:26.774947 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3883 06:55:26.777660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3884 06:55:26.784668 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3885 06:55:26.787755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3886 06:55:26.791149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3887 06:55:26.794488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3888 06:55:26.797796 [ANA_INIT] flow start
3889 06:55:26.801569 [ANA_INIT] PLL >>>>>>>>
3890 06:55:26.802267 [ANA_INIT] PLL <<<<<<<<
3891 06:55:26.804176 [ANA_INIT] MIDPI >>>>>>>>
3892 06:55:26.808173 [ANA_INIT] MIDPI <<<<<<<<
3893 06:55:26.808696 [ANA_INIT] DLL >>>>>>>>
3894 06:55:26.811130 [ANA_INIT] flow end
3895 06:55:26.814519 ============ LP4 DIFF to SE enter ============
3896 06:55:26.821149 ============ LP4 DIFF to SE exit ============
3897 06:55:26.821712 [ANA_INIT] <<<<<<<<<<<<<
3898 06:55:26.824735 [Flow] Enable top DCM control >>>>>
3899 06:55:26.827922 [Flow] Enable top DCM control <<<<<
3900 06:55:26.830959 Enable DLL master slave shuffle
3901 06:55:26.837883 ==============================================================
3902 06:55:26.838412 Gating Mode config
3903 06:55:26.844598 ==============================================================
3904 06:55:26.847314 Config description:
3905 06:55:26.854209 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3906 06:55:26.860727 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3907 06:55:26.867783 SELPH_MODE 0: By rank 1: By Phase
3908 06:55:26.874253 ==============================================================
3909 06:55:26.874767 GAT_TRACK_EN = 1
3910 06:55:26.877390 RX_GATING_MODE = 2
3911 06:55:26.880661 RX_GATING_TRACK_MODE = 2
3912 06:55:26.884108 SELPH_MODE = 1
3913 06:55:26.887315 PICG_EARLY_EN = 1
3914 06:55:26.890537 VALID_LAT_VALUE = 1
3915 06:55:26.897557 ==============================================================
3916 06:55:26.900318 Enter into Gating configuration >>>>
3917 06:55:26.904380 Exit from Gating configuration <<<<
3918 06:55:26.907412 Enter into DVFS_PRE_config >>>>>
3919 06:55:26.917205 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3920 06:55:26.920775 Exit from DVFS_PRE_config <<<<<
3921 06:55:26.924046 Enter into PICG configuration >>>>
3922 06:55:26.927233 Exit from PICG configuration <<<<
3923 06:55:26.930536 [RX_INPUT] configuration >>>>>
3924 06:55:26.933800 [RX_INPUT] configuration <<<<<
3925 06:55:26.936865 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3926 06:55:26.943917 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3927 06:55:26.950109 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3928 06:55:26.953673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3929 06:55:26.959955 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3930 06:55:26.966840 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3931 06:55:26.969975 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3932 06:55:26.976880 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3933 06:55:26.980380 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3934 06:55:26.983537 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3935 06:55:26.987020 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3936 06:55:26.993857 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3937 06:55:26.996865 ===================================
3938 06:55:26.997389 LPDDR4 DRAM CONFIGURATION
3939 06:55:27.000046 ===================================
3940 06:55:27.002967 EX_ROW_EN[0] = 0x0
3941 06:55:27.006263 EX_ROW_EN[1] = 0x0
3942 06:55:27.006709 LP4Y_EN = 0x0
3943 06:55:27.009696 WORK_FSP = 0x0
3944 06:55:27.010111 WL = 0x2
3945 06:55:27.013338 RL = 0x2
3946 06:55:27.013906 BL = 0x2
3947 06:55:27.016578 RPST = 0x0
3948 06:55:27.017108 RD_PRE = 0x0
3949 06:55:27.019734 WR_PRE = 0x1
3950 06:55:27.020258 WR_PST = 0x0
3951 06:55:27.023623 DBI_WR = 0x0
3952 06:55:27.024147 DBI_RD = 0x0
3953 06:55:27.026260 OTF = 0x1
3954 06:55:27.030234 ===================================
3955 06:55:27.033200 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3956 06:55:27.036207 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3957 06:55:27.043155 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3958 06:55:27.046227 ===================================
3959 06:55:27.046778 LPDDR4 DRAM CONFIGURATION
3960 06:55:27.049559 ===================================
3961 06:55:27.052731 EX_ROW_EN[0] = 0x10
3962 06:55:27.056066 EX_ROW_EN[1] = 0x0
3963 06:55:27.056483 LP4Y_EN = 0x0
3964 06:55:27.059404 WORK_FSP = 0x0
3965 06:55:27.059825 WL = 0x2
3966 06:55:27.062721 RL = 0x2
3967 06:55:27.063244 BL = 0x2
3968 06:55:27.065804 RPST = 0x0
3969 06:55:27.066221 RD_PRE = 0x0
3970 06:55:27.069352 WR_PRE = 0x1
3971 06:55:27.069914 WR_PST = 0x0
3972 06:55:27.072796 DBI_WR = 0x0
3973 06:55:27.073317 DBI_RD = 0x0
3974 06:55:27.075947 OTF = 0x1
3975 06:55:27.079378 ===================================
3976 06:55:27.085860 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3977 06:55:27.089268 nWR fixed to 30
3978 06:55:27.092614 [ModeRegInit_LP4] CH0 RK0
3979 06:55:27.093171 [ModeRegInit_LP4] CH0 RK1
3980 06:55:27.095775 [ModeRegInit_LP4] CH1 RK0
3981 06:55:27.099073 [ModeRegInit_LP4] CH1 RK1
3982 06:55:27.099493 match AC timing 17
3983 06:55:27.105846 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3984 06:55:27.108956 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3985 06:55:27.112273 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3986 06:55:27.119059 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3987 06:55:27.122433 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3988 06:55:27.122999 ==
3989 06:55:27.126033 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 06:55:27.129359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 06:55:27.129937 ==
3992 06:55:27.135803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3993 06:55:27.142300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3994 06:55:27.145632 [CA 0] Center 37 (7~67) winsize 61
3995 06:55:27.149150 [CA 1] Center 36 (6~67) winsize 62
3996 06:55:27.152119 [CA 2] Center 35 (5~65) winsize 61
3997 06:55:27.155366 [CA 3] Center 35 (5~65) winsize 61
3998 06:55:27.159155 [CA 4] Center 34 (4~65) winsize 62
3999 06:55:27.162374 [CA 5] Center 34 (4~64) winsize 61
4000 06:55:27.162900
4001 06:55:27.165394 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4002 06:55:27.165878
4003 06:55:27.169228 [CATrainingPosCal] consider 1 rank data
4004 06:55:27.172199 u2DelayCellTimex100 = 270/100 ps
4005 06:55:27.175694 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4006 06:55:27.178650 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4007 06:55:27.182005 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4008 06:55:27.185387 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4009 06:55:27.188737 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4010 06:55:27.191689 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4011 06:55:27.192109
4012 06:55:27.198364 CA PerBit enable=1, Macro0, CA PI delay=34
4013 06:55:27.198876
4014 06:55:27.201950 [CBTSetCACLKResult] CA Dly = 34
4015 06:55:27.202377 CS Dly: 7 (0~38)
4016 06:55:27.202720 ==
4017 06:55:27.205140 Dram Type= 6, Freq= 0, CH_0, rank 1
4018 06:55:27.208322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 06:55:27.208755 ==
4020 06:55:27.215474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4021 06:55:27.221728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4022 06:55:27.225399 [CA 0] Center 37 (7~67) winsize 61
4023 06:55:27.228349 [CA 1] Center 37 (7~67) winsize 61
4024 06:55:27.231846 [CA 2] Center 35 (5~65) winsize 61
4025 06:55:27.234918 [CA 3] Center 35 (5~65) winsize 61
4026 06:55:27.238483 [CA 4] Center 34 (4~65) winsize 62
4027 06:55:27.242062 [CA 5] Center 34 (3~65) winsize 63
4028 06:55:27.242588
4029 06:55:27.245330 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4030 06:55:27.245910
4031 06:55:27.248614 [CATrainingPosCal] consider 2 rank data
4032 06:55:27.251821 u2DelayCellTimex100 = 270/100 ps
4033 06:55:27.255028 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4034 06:55:27.258280 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4035 06:55:27.261627 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4036 06:55:27.264903 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4037 06:55:27.268587 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4038 06:55:27.275046 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4039 06:55:27.275476
4040 06:55:27.278311 CA PerBit enable=1, Macro0, CA PI delay=34
4041 06:55:27.278740
4042 06:55:27.281340 [CBTSetCACLKResult] CA Dly = 34
4043 06:55:27.281812 CS Dly: 7 (0~38)
4044 06:55:27.282173
4045 06:55:27.284686 ----->DramcWriteLeveling(PI) begin...
4046 06:55:27.285120 ==
4047 06:55:27.288317 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 06:55:27.291750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 06:55:27.294580 ==
4050 06:55:27.298213 Write leveling (Byte 0): 35 => 35
4051 06:55:27.298644 Write leveling (Byte 1): 31 => 31
4052 06:55:27.301616 DramcWriteLeveling(PI) end<-----
4053 06:55:27.302047
4054 06:55:27.302386 ==
4055 06:55:27.304679 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 06:55:27.311382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 06:55:27.311907 ==
4058 06:55:27.315028 [Gating] SW mode calibration
4059 06:55:27.321637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4060 06:55:27.325004 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4061 06:55:27.331275 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4062 06:55:27.334359 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4063 06:55:27.337631 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4064 06:55:27.345371 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4065 06:55:27.347740 0 9 16 | B1->B0 | 3131 2626 | 0 1 | (0 0) (1 0)
4066 06:55:27.351504 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 06:55:27.357565 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 06:55:27.361283 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 06:55:27.364710 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 06:55:27.367804 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 06:55:27.374268 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 06:55:27.377751 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4073 06:55:27.380954 0 10 16 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
4074 06:55:27.387922 0 10 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4075 06:55:27.391259 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 06:55:27.393994 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 06:55:27.401119 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 06:55:27.404550 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 06:55:27.407527 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 06:55:27.414292 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 06:55:27.417843 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 06:55:27.420776 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 06:55:27.427838 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 06:55:27.430559 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 06:55:27.434357 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 06:55:27.440754 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 06:55:27.444122 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 06:55:27.447354 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 06:55:27.453928 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 06:55:27.457100 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 06:55:27.460641 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 06:55:27.467146 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 06:55:27.470525 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 06:55:27.473756 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 06:55:27.480482 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 06:55:27.483499 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4097 06:55:27.487141 Total UI for P1: 0, mck2ui 16
4098 06:55:27.490241 best dqsien dly found for B0: ( 0, 13, 10)
4099 06:55:27.493366 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 06:55:27.496764 Total UI for P1: 0, mck2ui 16
4101 06:55:27.500002 best dqsien dly found for B1: ( 0, 13, 12)
4102 06:55:27.503721 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4103 06:55:27.506926 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4104 06:55:27.507449
4105 06:55:27.513403 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4106 06:55:27.516859 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4107 06:55:27.520080 [Gating] SW calibration Done
4108 06:55:27.520510 ==
4109 06:55:27.523075 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 06:55:27.526455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 06:55:27.526982 ==
4112 06:55:27.527325 RX Vref Scan: 0
4113 06:55:27.527642
4114 06:55:27.530061 RX Vref 0 -> 0, step: 1
4115 06:55:27.530592
4116 06:55:27.533138 RX Delay -230 -> 252, step: 16
4117 06:55:27.536763 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4118 06:55:27.542958 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4119 06:55:27.546428 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4120 06:55:27.550204 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4121 06:55:27.553219 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4122 06:55:27.556355 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4123 06:55:27.563115 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4124 06:55:27.566216 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4125 06:55:27.569555 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4126 06:55:27.572984 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4127 06:55:27.579856 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4128 06:55:27.582863 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4129 06:55:27.586210 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4130 06:55:27.589422 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4131 06:55:27.596020 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4132 06:55:27.599311 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4133 06:55:27.599742 ==
4134 06:55:27.602714 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 06:55:27.605922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 06:55:27.606353 ==
4137 06:55:27.609617 DQS Delay:
4138 06:55:27.610189 DQS0 = 0, DQS1 = 0
4139 06:55:27.610538 DQM Delay:
4140 06:55:27.612379 DQM0 = 35, DQM1 = 30
4141 06:55:27.612807 DQ Delay:
4142 06:55:27.615707 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4143 06:55:27.619306 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =49
4144 06:55:27.622726 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4145 06:55:27.625928 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4146 06:55:27.626456
4147 06:55:27.626796
4148 06:55:27.627110 ==
4149 06:55:27.629274 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 06:55:27.635667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 06:55:27.636181 ==
4152 06:55:27.636521
4153 06:55:27.636834
4154 06:55:27.637134 TX Vref Scan disable
4155 06:55:27.639436 == TX Byte 0 ==
4156 06:55:27.642947 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4157 06:55:27.649390 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4158 06:55:27.649958 == TX Byte 1 ==
4159 06:55:27.652328 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4160 06:55:27.659425 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4161 06:55:27.659949 ==
4162 06:55:27.663009 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 06:55:27.666143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 06:55:27.666671 ==
4165 06:55:27.667015
4166 06:55:27.667330
4167 06:55:27.669091 TX Vref Scan disable
4168 06:55:27.672908 == TX Byte 0 ==
4169 06:55:27.675889 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4170 06:55:27.679328 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4171 06:55:27.682640 == TX Byte 1 ==
4172 06:55:27.685842 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4173 06:55:27.689234 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4174 06:55:27.689724
4175 06:55:27.690064 [DATLAT]
4176 06:55:27.692541 Freq=600, CH0 RK0
4177 06:55:27.693067
4178 06:55:27.695571 DATLAT Default: 0x9
4179 06:55:27.695996 0, 0xFFFF, sum = 0
4180 06:55:27.698798 1, 0xFFFF, sum = 0
4181 06:55:27.699232 2, 0xFFFF, sum = 0
4182 06:55:27.702206 3, 0xFFFF, sum = 0
4183 06:55:27.702642 4, 0xFFFF, sum = 0
4184 06:55:27.705695 5, 0xFFFF, sum = 0
4185 06:55:27.706222 6, 0xFFFF, sum = 0
4186 06:55:27.708991 7, 0xFFFF, sum = 0
4187 06:55:27.709433 8, 0x0, sum = 1
4188 06:55:27.712395 9, 0x0, sum = 2
4189 06:55:27.712920 10, 0x0, sum = 3
4190 06:55:27.715646 11, 0x0, sum = 4
4191 06:55:27.716177 best_step = 9
4192 06:55:27.716520
4193 06:55:27.716837 ==
4194 06:55:27.718620 Dram Type= 6, Freq= 0, CH_0, rank 0
4195 06:55:27.722355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 06:55:27.722886 ==
4197 06:55:27.725594 RX Vref Scan: 1
4198 06:55:27.726115
4199 06:55:27.728997 RX Vref 0 -> 0, step: 1
4200 06:55:27.729582
4201 06:55:27.729942 RX Delay -195 -> 252, step: 8
4202 06:55:27.730265
4203 06:55:27.732073 Set Vref, RX VrefLevel [Byte0]: 61
4204 06:55:27.735174 [Byte1]: 57
4205 06:55:27.739709
4206 06:55:27.740134 Final RX Vref Byte 0 = 61 to rank0
4207 06:55:27.743323 Final RX Vref Byte 1 = 57 to rank0
4208 06:55:27.746886 Final RX Vref Byte 0 = 61 to rank1
4209 06:55:27.750025 Final RX Vref Byte 1 = 57 to rank1==
4210 06:55:27.753239 Dram Type= 6, Freq= 0, CH_0, rank 0
4211 06:55:27.759819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 06:55:27.760347 ==
4213 06:55:27.760690 DQS Delay:
4214 06:55:27.761004 DQS0 = 0, DQS1 = 0
4215 06:55:27.763373 DQM Delay:
4216 06:55:27.763909 DQM0 = 35, DQM1 = 29
4217 06:55:27.766313 DQ Delay:
4218 06:55:27.769614 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4219 06:55:27.772983 DQ4 =36, DQ5 =24, DQ6 =40, DQ7 =44
4220 06:55:27.776694 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4221 06:55:27.779840 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4222 06:55:27.780368
4223 06:55:27.780708
4224 06:55:27.786238 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4225 06:55:27.789542 CH0 RK0: MR19=808, MR18=3C3A
4226 06:55:27.796012 CH0_RK0: MR19=0x808, MR18=0x3C3A, DQSOSC=398, MR23=63, INC=165, DEC=110
4227 06:55:27.796440
4228 06:55:27.799512 ----->DramcWriteLeveling(PI) begin...
4229 06:55:27.800046 ==
4230 06:55:27.802977 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 06:55:27.806001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 06:55:27.806438 ==
4233 06:55:27.809290 Write leveling (Byte 0): 36 => 36
4234 06:55:27.812930 Write leveling (Byte 1): 30 => 30
4235 06:55:27.815839 DramcWriteLeveling(PI) end<-----
4236 06:55:27.816373
4237 06:55:27.816716 ==
4238 06:55:27.819342 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 06:55:27.823107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 06:55:27.825850 ==
4241 06:55:27.826280 [Gating] SW mode calibration
4242 06:55:27.832442 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4243 06:55:27.838889 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4244 06:55:27.842542 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 06:55:27.849163 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4246 06:55:27.852563 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4247 06:55:27.855815 0 9 12 | B1->B0 | 3333 3232 | 0 0 | (0 0) (1 1)
4248 06:55:27.862429 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4249 06:55:27.865730 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 06:55:27.869077 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 06:55:27.875988 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 06:55:27.879003 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 06:55:27.882313 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 06:55:27.889062 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 06:55:27.892618 0 10 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (0 0)
4256 06:55:27.895474 0 10 16 | B1->B0 | 3b3b 4444 | 1 0 | (0 0) (0 0)
4257 06:55:27.902206 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 06:55:27.905684 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 06:55:27.908886 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 06:55:27.912716 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 06:55:27.918858 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 06:55:27.922025 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 06:55:27.925397 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4264 06:55:27.932231 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4265 06:55:27.935147 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 06:55:27.938658 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 06:55:27.944977 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 06:55:27.948304 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 06:55:27.951619 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 06:55:27.958643 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 06:55:27.962151 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 06:55:27.965423 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 06:55:27.971911 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 06:55:27.975489 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 06:55:27.978314 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 06:55:27.985432 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 06:55:27.988761 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 06:55:27.992227 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 06:55:27.998638 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4280 06:55:28.001837 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 06:55:28.005570 Total UI for P1: 0, mck2ui 16
4282 06:55:28.008580 best dqsien dly found for B0: ( 0, 13, 12)
4283 06:55:28.011878 Total UI for P1: 0, mck2ui 16
4284 06:55:28.015276 best dqsien dly found for B1: ( 0, 13, 14)
4285 06:55:28.018622 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4286 06:55:28.021370 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4287 06:55:28.021824
4288 06:55:28.025019 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4289 06:55:28.028366 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4290 06:55:28.032226 [Gating] SW calibration Done
4291 06:55:28.032751 ==
4292 06:55:28.034692 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 06:55:28.038370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 06:55:28.041417 ==
4295 06:55:28.041887 RX Vref Scan: 0
4296 06:55:28.042230
4297 06:55:28.045157 RX Vref 0 -> 0, step: 1
4298 06:55:28.045752
4299 06:55:28.048618 RX Delay -230 -> 252, step: 16
4300 06:55:28.051417 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4301 06:55:28.054686 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4302 06:55:28.058310 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4303 06:55:28.064830 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4304 06:55:28.068198 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4305 06:55:28.071105 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4306 06:55:28.074782 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4307 06:55:28.077952 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4308 06:55:28.084639 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4309 06:55:28.087913 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4310 06:55:28.091436 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4311 06:55:28.094407 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4312 06:55:28.101108 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4313 06:55:28.104540 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4314 06:55:28.107525 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4315 06:55:28.111209 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4316 06:55:28.111738 ==
4317 06:55:28.114422 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 06:55:28.120860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 06:55:28.121435 ==
4320 06:55:28.121823 DQS Delay:
4321 06:55:28.124606 DQS0 = 0, DQS1 = 0
4322 06:55:28.125129 DQM Delay:
4323 06:55:28.127920 DQM0 = 40, DQM1 = 28
4324 06:55:28.128454 DQ Delay:
4325 06:55:28.131105 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4326 06:55:28.134418 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4327 06:55:28.137735 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4328 06:55:28.141111 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4329 06:55:28.141686
4330 06:55:28.142038
4331 06:55:28.142352 ==
4332 06:55:28.144485 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 06:55:28.148030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 06:55:28.148554 ==
4335 06:55:28.148891
4336 06:55:28.149204
4337 06:55:28.150999 TX Vref Scan disable
4338 06:55:28.154416 == TX Byte 0 ==
4339 06:55:28.158217 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4340 06:55:28.160742 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4341 06:55:28.164315 == TX Byte 1 ==
4342 06:55:28.168048 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4343 06:55:28.170616 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4344 06:55:28.171263 ==
4345 06:55:28.174085 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 06:55:28.177460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 06:55:28.180666 ==
4348 06:55:28.181091
4349 06:55:28.181425
4350 06:55:28.181797 TX Vref Scan disable
4351 06:55:28.184710 == TX Byte 0 ==
4352 06:55:28.188581 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4353 06:55:28.194933 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4354 06:55:28.195461 == TX Byte 1 ==
4355 06:55:28.197967 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4356 06:55:28.204827 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4357 06:55:28.205253
4358 06:55:28.205634 [DATLAT]
4359 06:55:28.205959 Freq=600, CH0 RK1
4360 06:55:28.206268
4361 06:55:28.207622 DATLAT Default: 0x9
4362 06:55:28.208046 0, 0xFFFF, sum = 0
4363 06:55:28.210914 1, 0xFFFF, sum = 0
4364 06:55:28.214453 2, 0xFFFF, sum = 0
4365 06:55:28.214882 3, 0xFFFF, sum = 0
4366 06:55:28.217598 4, 0xFFFF, sum = 0
4367 06:55:28.218027 5, 0xFFFF, sum = 0
4368 06:55:28.221011 6, 0xFFFF, sum = 0
4369 06:55:28.221571 7, 0xFFFF, sum = 0
4370 06:55:28.224489 8, 0x0, sum = 1
4371 06:55:28.224919 9, 0x0, sum = 2
4372 06:55:28.227216 10, 0x0, sum = 3
4373 06:55:28.227644 11, 0x0, sum = 4
4374 06:55:28.227982 best_step = 9
4375 06:55:28.228293
4376 06:55:28.231182 ==
4377 06:55:28.234294 Dram Type= 6, Freq= 0, CH_0, rank 1
4378 06:55:28.238109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 06:55:28.238964 ==
4380 06:55:28.239318 RX Vref Scan: 0
4381 06:55:28.239635
4382 06:55:28.240820 RX Vref 0 -> 0, step: 1
4383 06:55:28.241258
4384 06:55:28.244339 RX Delay -195 -> 252, step: 8
4385 06:55:28.251010 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4386 06:55:28.254012 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4387 06:55:28.257270 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4388 06:55:28.260779 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4389 06:55:28.264630 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4390 06:55:28.271054 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4391 06:55:28.273863 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4392 06:55:28.277268 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4393 06:55:28.280516 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4394 06:55:28.287318 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4395 06:55:28.290424 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4396 06:55:28.293796 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4397 06:55:28.297225 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4398 06:55:28.303667 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4399 06:55:28.307202 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4400 06:55:28.310596 iDelay=205, Bit 15, Center 32 (-131 ~ 196) 328
4401 06:55:28.311212 ==
4402 06:55:28.313840 Dram Type= 6, Freq= 0, CH_0, rank 1
4403 06:55:28.317061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 06:55:28.317524 ==
4405 06:55:28.320241 DQS Delay:
4406 06:55:28.320764 DQS0 = 0, DQS1 = 0
4407 06:55:28.323666 DQM Delay:
4408 06:55:28.324197 DQM0 = 34, DQM1 = 27
4409 06:55:28.326533 DQ Delay:
4410 06:55:28.326951 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4411 06:55:28.330196 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4412 06:55:28.333452 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4413 06:55:28.336632 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =32
4414 06:55:28.340103
4415 06:55:28.340614
4416 06:55:28.346984 [DQSOSCAuto] RK1, (LSB)MR18= 0x703f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4417 06:55:28.349728 CH0 RK1: MR19=808, MR18=703F
4418 06:55:28.356500 CH0_RK1: MR19=0x808, MR18=0x703F, DQSOSC=388, MR23=63, INC=174, DEC=116
4419 06:55:28.359662 [RxdqsGatingPostProcess] freq 600
4420 06:55:28.363029 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4421 06:55:28.366326 Pre-setting of DQS Precalculation
4422 06:55:28.373202 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4423 06:55:28.373670 ==
4424 06:55:28.376493 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 06:55:28.379209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 06:55:28.379596 ==
4427 06:55:28.386165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4428 06:55:28.389373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4429 06:55:28.394344 [CA 0] Center 36 (6~66) winsize 61
4430 06:55:28.397333 [CA 1] Center 36 (6~67) winsize 62
4431 06:55:28.400585 [CA 2] Center 35 (5~65) winsize 61
4432 06:55:28.404224 [CA 3] Center 34 (4~65) winsize 62
4433 06:55:28.406842 [CA 4] Center 35 (5~65) winsize 61
4434 06:55:28.410415 [CA 5] Center 34 (4~65) winsize 62
4435 06:55:28.410953
4436 06:55:28.413557 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4437 06:55:28.413982
4438 06:55:28.417270 [CATrainingPosCal] consider 1 rank data
4439 06:55:28.420504 u2DelayCellTimex100 = 270/100 ps
4440 06:55:28.423827 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4441 06:55:28.430121 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4442 06:55:28.433640 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4443 06:55:28.436876 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4444 06:55:28.439965 CA4 delay=35 (5~65),Diff = 1 PI (9 cell)
4445 06:55:28.443511 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4446 06:55:28.444053
4447 06:55:28.446903 CA PerBit enable=1, Macro0, CA PI delay=34
4448 06:55:28.447429
4449 06:55:28.449926 [CBTSetCACLKResult] CA Dly = 34
4450 06:55:28.453421 CS Dly: 5 (0~36)
4451 06:55:28.453872 ==
4452 06:55:28.456929 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 06:55:28.459810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 06:55:28.460241 ==
4455 06:55:28.467044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4456 06:55:28.469681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4457 06:55:28.474238 [CA 0] Center 36 (6~66) winsize 61
4458 06:55:28.477363 [CA 1] Center 36 (6~67) winsize 62
4459 06:55:28.480764 [CA 2] Center 35 (5~65) winsize 61
4460 06:55:28.483776 [CA 3] Center 34 (4~65) winsize 62
4461 06:55:28.487597 [CA 4] Center 34 (4~65) winsize 62
4462 06:55:28.490503 [CA 5] Center 34 (4~65) winsize 62
4463 06:55:28.490925
4464 06:55:28.493931 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4465 06:55:28.494461
4466 06:55:28.497407 [CATrainingPosCal] consider 2 rank data
4467 06:55:28.500802 u2DelayCellTimex100 = 270/100 ps
4468 06:55:28.504142 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4469 06:55:28.510452 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4470 06:55:28.513921 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4471 06:55:28.517401 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4472 06:55:28.520611 CA4 delay=35 (5~65),Diff = 1 PI (9 cell)
4473 06:55:28.523796 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4474 06:55:28.524337
4475 06:55:28.526651 CA PerBit enable=1, Macro0, CA PI delay=34
4476 06:55:28.527074
4477 06:55:28.530240 [CBTSetCACLKResult] CA Dly = 34
4478 06:55:28.534090 CS Dly: 6 (0~38)
4479 06:55:28.534611
4480 06:55:28.537087 ----->DramcWriteLeveling(PI) begin...
4481 06:55:28.537657 ==
4482 06:55:28.540255 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 06:55:28.543691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 06:55:28.544219 ==
4485 06:55:28.546839 Write leveling (Byte 0): 30 => 30
4486 06:55:28.550171 Write leveling (Byte 1): 29 => 29
4487 06:55:28.553116 DramcWriteLeveling(PI) end<-----
4488 06:55:28.553667
4489 06:55:28.554009 ==
4490 06:55:28.556848 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 06:55:28.559796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 06:55:28.560223 ==
4493 06:55:28.563391 [Gating] SW mode calibration
4494 06:55:28.570055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4495 06:55:28.576567 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4496 06:55:28.580074 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4497 06:55:28.583340 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4498 06:55:28.590127 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4499 06:55:28.593516 0 9 12 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 0)
4500 06:55:28.596844 0 9 16 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
4501 06:55:28.603039 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 06:55:28.606503 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 06:55:28.609945 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 06:55:28.616410 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 06:55:28.619930 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 06:55:28.623057 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 06:55:28.629968 0 10 12 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (0 0)
4508 06:55:28.633247 0 10 16 | B1->B0 | 4141 3f3f | 0 0 | (0 0) (0 0)
4509 06:55:28.636419 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 06:55:28.642823 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 06:55:28.646386 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 06:55:28.649890 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 06:55:28.653243 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 06:55:28.659413 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 06:55:28.663027 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 06:55:28.666089 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 06:55:28.672660 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 06:55:28.676042 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 06:55:28.679795 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 06:55:28.686046 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 06:55:28.689355 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 06:55:28.692691 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 06:55:28.699447 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 06:55:28.702795 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 06:55:28.706042 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 06:55:28.712658 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 06:55:28.716225 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 06:55:28.719528 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 06:55:28.725979 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 06:55:28.729320 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 06:55:28.732844 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4532 06:55:28.738942 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 06:55:28.742394 Total UI for P1: 0, mck2ui 16
4534 06:55:28.745852 best dqsien dly found for B0: ( 0, 13, 12)
4535 06:55:28.746374 Total UI for P1: 0, mck2ui 16
4536 06:55:28.752354 best dqsien dly found for B1: ( 0, 13, 14)
4537 06:55:28.755564 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4538 06:55:28.758776 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4539 06:55:28.759301
4540 06:55:28.762310 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4541 06:55:28.765284 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4542 06:55:28.768940 [Gating] SW calibration Done
4543 06:55:28.769465 ==
4544 06:55:28.772354 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 06:55:28.775056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 06:55:28.775487 ==
4547 06:55:28.778597 RX Vref Scan: 0
4548 06:55:28.779022
4549 06:55:28.779358 RX Vref 0 -> 0, step: 1
4550 06:55:28.782034
4551 06:55:28.782455 RX Delay -230 -> 252, step: 16
4552 06:55:28.788575 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4553 06:55:28.791624 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4554 06:55:28.795055 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4555 06:55:28.798544 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4556 06:55:28.805067 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4557 06:55:28.808415 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4558 06:55:28.811954 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4559 06:55:28.815197 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4560 06:55:28.818196 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4561 06:55:28.825106 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4562 06:55:28.828512 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4563 06:55:28.831814 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4564 06:55:28.835036 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4565 06:55:28.841873 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4566 06:55:28.845132 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4567 06:55:28.848520 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4568 06:55:28.849044 ==
4569 06:55:28.851457 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 06:55:28.857847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 06:55:28.858277 ==
4572 06:55:28.858613 DQS Delay:
4573 06:55:28.858928 DQS0 = 0, DQS1 = 0
4574 06:55:28.861091 DQM Delay:
4575 06:55:28.861580 DQM0 = 40, DQM1 = 32
4576 06:55:28.864673 DQ Delay:
4577 06:55:28.868090 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4578 06:55:28.870959 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4579 06:55:28.874360 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4580 06:55:28.877647 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =33
4581 06:55:28.878075
4582 06:55:28.878411
4583 06:55:28.878724 ==
4584 06:55:28.880972 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 06:55:28.884702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 06:55:28.885245 ==
4587 06:55:28.885643
4588 06:55:28.885966
4589 06:55:28.887554 TX Vref Scan disable
4590 06:55:28.887985 == TX Byte 0 ==
4591 06:55:28.894393 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4592 06:55:28.897349 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4593 06:55:28.897845 == TX Byte 1 ==
4594 06:55:28.904136 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4595 06:55:28.907670 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4596 06:55:28.908204 ==
4597 06:55:28.910780 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 06:55:28.914446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 06:55:28.914878 ==
4600 06:55:28.917177
4601 06:55:28.917635
4602 06:55:28.917982 TX Vref Scan disable
4603 06:55:28.920950 == TX Byte 0 ==
4604 06:55:28.924179 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4605 06:55:28.930993 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4606 06:55:28.931522 == TX Byte 1 ==
4607 06:55:28.934258 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4608 06:55:28.941087 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4609 06:55:28.941670
4610 06:55:28.942023 [DATLAT]
4611 06:55:28.942437 Freq=600, CH1 RK0
4612 06:55:28.942756
4613 06:55:28.944387 DATLAT Default: 0x9
4614 06:55:28.944813 0, 0xFFFF, sum = 0
4615 06:55:28.947845 1, 0xFFFF, sum = 0
4616 06:55:28.948377 2, 0xFFFF, sum = 0
4617 06:55:28.950662 3, 0xFFFF, sum = 0
4618 06:55:28.953765 4, 0xFFFF, sum = 0
4619 06:55:28.954200 5, 0xFFFF, sum = 0
4620 06:55:28.957627 6, 0xFFFF, sum = 0
4621 06:55:28.958151 7, 0xFFFF, sum = 0
4622 06:55:28.960511 8, 0x0, sum = 1
4623 06:55:28.960943 9, 0x0, sum = 2
4624 06:55:28.964174 10, 0x0, sum = 3
4625 06:55:28.964707 11, 0x0, sum = 4
4626 06:55:28.965055 best_step = 9
4627 06:55:28.965372
4628 06:55:28.965726 ==
4629 06:55:28.967108 Dram Type= 6, Freq= 0, CH_1, rank 0
4630 06:55:28.973749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 06:55:28.974183 ==
4632 06:55:28.974523 RX Vref Scan: 1
4633 06:55:28.974965
4634 06:55:28.977169 RX Vref 0 -> 0, step: 1
4635 06:55:28.977645
4636 06:55:28.980415 RX Delay -195 -> 252, step: 8
4637 06:55:28.980841
4638 06:55:28.983953 Set Vref, RX VrefLevel [Byte0]: 55
4639 06:55:28.986974 [Byte1]: 55
4640 06:55:28.987411
4641 06:55:28.990361 Final RX Vref Byte 0 = 55 to rank0
4642 06:55:28.993464 Final RX Vref Byte 1 = 55 to rank0
4643 06:55:28.997104 Final RX Vref Byte 0 = 55 to rank1
4644 06:55:29.000279 Final RX Vref Byte 1 = 55 to rank1==
4645 06:55:29.003866 Dram Type= 6, Freq= 0, CH_1, rank 0
4646 06:55:29.007130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 06:55:29.007658 ==
4648 06:55:29.010288 DQS Delay:
4649 06:55:29.010718 DQS0 = 0, DQS1 = 0
4650 06:55:29.013869 DQM Delay:
4651 06:55:29.014398 DQM0 = 39, DQM1 = 29
4652 06:55:29.014739 DQ Delay:
4653 06:55:29.016850 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4654 06:55:29.020641 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4655 06:55:29.023624 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4656 06:55:29.027221 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4657 06:55:29.027751
4658 06:55:29.028092
4659 06:55:29.036878 [DQSOSCAuto] RK0, (LSB)MR18= 0x2330, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4660 06:55:29.040075 CH1 RK0: MR19=808, MR18=2330
4661 06:55:29.047278 CH1_RK0: MR19=0x808, MR18=0x2330, DQSOSC=400, MR23=63, INC=163, DEC=109
4662 06:55:29.047802
4663 06:55:29.050458 ----->DramcWriteLeveling(PI) begin...
4664 06:55:29.050996 ==
4665 06:55:29.053472 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 06:55:29.056712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 06:55:29.057150 ==
4668 06:55:29.060319 Write leveling (Byte 0): 30 => 30
4669 06:55:29.063598 Write leveling (Byte 1): 29 => 29
4670 06:55:29.066958 DramcWriteLeveling(PI) end<-----
4671 06:55:29.067485
4672 06:55:29.067825 ==
4673 06:55:29.070232 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 06:55:29.073360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 06:55:29.073926 ==
4676 06:55:29.076367 [Gating] SW mode calibration
4677 06:55:29.083404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4678 06:55:29.090031 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4679 06:55:29.093051 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4680 06:55:29.096763 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4681 06:55:29.103105 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
4682 06:55:29.106307 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4683 06:55:29.109642 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4684 06:55:29.116571 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 06:55:29.119760 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 06:55:29.122784 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 06:55:29.129639 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 06:55:29.133063 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 06:55:29.136438 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4690 06:55:29.142815 0 10 12 | B1->B0 | 3030 3939 | 1 0 | (0 0) (1 1)
4691 06:55:29.146015 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4692 06:55:29.149403 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 06:55:29.155858 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 06:55:29.159773 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 06:55:29.162519 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 06:55:29.169382 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 06:55:29.172431 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 06:55:29.175747 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4699 06:55:29.182459 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 06:55:29.185813 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 06:55:29.189414 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 06:55:29.196087 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 06:55:29.198915 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 06:55:29.202195 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 06:55:29.209016 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 06:55:29.212801 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 06:55:29.215969 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 06:55:29.222472 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 06:55:29.225862 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 06:55:29.228933 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 06:55:29.235415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 06:55:29.238719 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 06:55:29.242042 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 06:55:29.248778 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4715 06:55:29.252274 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 06:55:29.255406 Total UI for P1: 0, mck2ui 16
4717 06:55:29.258810 best dqsien dly found for B0: ( 0, 13, 12)
4718 06:55:29.262163 Total UI for P1: 0, mck2ui 16
4719 06:55:29.265625 best dqsien dly found for B1: ( 0, 13, 12)
4720 06:55:29.268553 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4721 06:55:29.271970 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4722 06:55:29.272391
4723 06:55:29.275241 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4724 06:55:29.278310 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4725 06:55:29.281659 [Gating] SW calibration Done
4726 06:55:29.282217 ==
4727 06:55:29.284916 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 06:55:29.288648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 06:55:29.289176 ==
4730 06:55:29.292104 RX Vref Scan: 0
4731 06:55:29.292626
4732 06:55:29.295302 RX Vref 0 -> 0, step: 1
4733 06:55:29.295832
4734 06:55:29.296173 RX Delay -230 -> 252, step: 16
4735 06:55:29.301815 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4736 06:55:29.305290 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4737 06:55:29.308658 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4738 06:55:29.312012 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4739 06:55:29.318466 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4740 06:55:29.321930 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4741 06:55:29.325047 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4742 06:55:29.328835 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4743 06:55:29.335105 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4744 06:55:29.338468 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4745 06:55:29.341331 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4746 06:55:29.344589 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4747 06:55:29.351437 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4748 06:55:29.354708 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4749 06:55:29.358089 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4750 06:55:29.361134 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4751 06:55:29.361683 ==
4752 06:55:29.364852 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 06:55:29.371505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 06:55:29.372032 ==
4755 06:55:29.372389 DQS Delay:
4756 06:55:29.374380 DQS0 = 0, DQS1 = 0
4757 06:55:29.374802 DQM Delay:
4758 06:55:29.375137 DQM0 = 37, DQM1 = 30
4759 06:55:29.377563 DQ Delay:
4760 06:55:29.381060 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4761 06:55:29.384279 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4762 06:55:29.388025 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4763 06:55:29.391193 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =33
4764 06:55:29.391620
4765 06:55:29.391956
4766 06:55:29.392336 ==
4767 06:55:29.394233 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 06:55:29.397667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 06:55:29.398131 ==
4770 06:55:29.398475
4771 06:55:29.398802
4772 06:55:29.401006 TX Vref Scan disable
4773 06:55:29.401427 == TX Byte 0 ==
4774 06:55:29.407974 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4775 06:55:29.410900 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4776 06:55:29.411362 == TX Byte 1 ==
4777 06:55:29.417618 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4778 06:55:29.421149 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4779 06:55:29.421728 ==
4780 06:55:29.424002 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 06:55:29.427671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 06:55:29.428207 ==
4783 06:55:29.431112
4784 06:55:29.431634
4785 06:55:29.431976 TX Vref Scan disable
4786 06:55:29.434261 == TX Byte 0 ==
4787 06:55:29.437921 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4788 06:55:29.444333 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4789 06:55:29.444762 == TX Byte 1 ==
4790 06:55:29.448211 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4791 06:55:29.454523 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4792 06:55:29.455062
4793 06:55:29.455409 [DATLAT]
4794 06:55:29.455724 Freq=600, CH1 RK1
4795 06:55:29.456029
4796 06:55:29.457538 DATLAT Default: 0x9
4797 06:55:29.457967 0, 0xFFFF, sum = 0
4798 06:55:29.460575 1, 0xFFFF, sum = 0
4799 06:55:29.461007 2, 0xFFFF, sum = 0
4800 06:55:29.464054 3, 0xFFFF, sum = 0
4801 06:55:29.467690 4, 0xFFFF, sum = 0
4802 06:55:29.468121 5, 0xFFFF, sum = 0
4803 06:55:29.471174 6, 0xFFFF, sum = 0
4804 06:55:29.471604 7, 0xFFFF, sum = 0
4805 06:55:29.474393 8, 0x0, sum = 1
4806 06:55:29.474825 9, 0x0, sum = 2
4807 06:55:29.475165 10, 0x0, sum = 3
4808 06:55:29.477536 11, 0x0, sum = 4
4809 06:55:29.478169 best_step = 9
4810 06:55:29.478583
4811 06:55:29.478905 ==
4812 06:55:29.480685 Dram Type= 6, Freq= 0, CH_1, rank 1
4813 06:55:29.487237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4814 06:55:29.487682 ==
4815 06:55:29.488018 RX Vref Scan: 0
4816 06:55:29.488331
4817 06:55:29.490738 RX Vref 0 -> 0, step: 1
4818 06:55:29.491163
4819 06:55:29.494024 RX Delay -195 -> 252, step: 8
4820 06:55:29.497659 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4821 06:55:29.504059 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4822 06:55:29.507645 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4823 06:55:29.510745 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4824 06:55:29.514201 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4825 06:55:29.520820 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4826 06:55:29.523679 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4827 06:55:29.527327 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4828 06:55:29.530531 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4829 06:55:29.533943 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4830 06:55:29.540567 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4831 06:55:29.543873 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4832 06:55:29.547169 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4833 06:55:29.550603 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4834 06:55:29.557103 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4835 06:55:29.560166 iDelay=205, Bit 15, Center 40 (-123 ~ 204) 328
4836 06:55:29.560594 ==
4837 06:55:29.564167 Dram Type= 6, Freq= 0, CH_1, rank 1
4838 06:55:29.567141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4839 06:55:29.567672 ==
4840 06:55:29.570070 DQS Delay:
4841 06:55:29.570494 DQS0 = 0, DQS1 = 0
4842 06:55:29.573373 DQM Delay:
4843 06:55:29.573940 DQM0 = 36, DQM1 = 31
4844 06:55:29.574283 DQ Delay:
4845 06:55:29.576617 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4846 06:55:29.579563 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4847 06:55:29.583223 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4848 06:55:29.586617 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =40
4849 06:55:29.587058
4850 06:55:29.587397
4851 06:55:29.596709 [DQSOSCAuto] RK1, (LSB)MR18= 0x3555, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4852 06:55:29.600006 CH1 RK1: MR19=808, MR18=3555
4853 06:55:29.606512 CH1_RK1: MR19=0x808, MR18=0x3555, DQSOSC=393, MR23=63, INC=169, DEC=113
4854 06:55:29.607035 [RxdqsGatingPostProcess] freq 600
4855 06:55:29.613300 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4856 06:55:29.616627 Pre-setting of DQS Precalculation
4857 06:55:29.619763 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4858 06:55:29.629994 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4859 06:55:29.636514 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4860 06:55:29.637043
4861 06:55:29.637381
4862 06:55:29.639931 [Calibration Summary] 1200 Mbps
4863 06:55:29.640453 CH 0, Rank 0
4864 06:55:29.643040 SW Impedance : PASS
4865 06:55:29.643467 DUTY Scan : NO K
4866 06:55:29.646599 ZQ Calibration : PASS
4867 06:55:29.649679 Jitter Meter : NO K
4868 06:55:29.650105 CBT Training : PASS
4869 06:55:29.653143 Write leveling : PASS
4870 06:55:29.656069 RX DQS gating : PASS
4871 06:55:29.656496 RX DQ/DQS(RDDQC) : PASS
4872 06:55:29.659484 TX DQ/DQS : PASS
4873 06:55:29.663062 RX DATLAT : PASS
4874 06:55:29.663583 RX DQ/DQS(Engine): PASS
4875 06:55:29.666155 TX OE : NO K
4876 06:55:29.666581 All Pass.
4877 06:55:29.666917
4878 06:55:29.669791 CH 0, Rank 1
4879 06:55:29.670316 SW Impedance : PASS
4880 06:55:29.672643 DUTY Scan : NO K
4881 06:55:29.675969 ZQ Calibration : PASS
4882 06:55:29.676392 Jitter Meter : NO K
4883 06:55:29.679251 CBT Training : PASS
4884 06:55:29.683052 Write leveling : PASS
4885 06:55:29.683478 RX DQS gating : PASS
4886 06:55:29.686133 RX DQ/DQS(RDDQC) : PASS
4887 06:55:29.686558 TX DQ/DQS : PASS
4888 06:55:29.689381 RX DATLAT : PASS
4889 06:55:29.692728 RX DQ/DQS(Engine): PASS
4890 06:55:29.693247 TX OE : NO K
4891 06:55:29.696059 All Pass.
4892 06:55:29.696609
4893 06:55:29.697050 CH 1, Rank 0
4894 06:55:29.699092 SW Impedance : PASS
4895 06:55:29.699538 DUTY Scan : NO K
4896 06:55:29.702475 ZQ Calibration : PASS
4897 06:55:29.705690 Jitter Meter : NO K
4898 06:55:29.706217 CBT Training : PASS
4899 06:55:29.709262 Write leveling : PASS
4900 06:55:29.712599 RX DQS gating : PASS
4901 06:55:29.713146 RX DQ/DQS(RDDQC) : PASS
4902 06:55:29.715829 TX DQ/DQS : PASS
4903 06:55:29.719163 RX DATLAT : PASS
4904 06:55:29.719695 RX DQ/DQS(Engine): PASS
4905 06:55:29.722751 TX OE : NO K
4906 06:55:29.723292 All Pass.
4907 06:55:29.723768
4908 06:55:29.726086 CH 1, Rank 1
4909 06:55:29.726640 SW Impedance : PASS
4910 06:55:29.729395 DUTY Scan : NO K
4911 06:55:29.732504 ZQ Calibration : PASS
4912 06:55:29.733043 Jitter Meter : NO K
4913 06:55:29.735557 CBT Training : PASS
4914 06:55:29.739170 Write leveling : PASS
4915 06:55:29.739712 RX DQS gating : PASS
4916 06:55:29.742254 RX DQ/DQS(RDDQC) : PASS
4917 06:55:29.742694 TX DQ/DQS : PASS
4918 06:55:29.746107 RX DATLAT : PASS
4919 06:55:29.749511 RX DQ/DQS(Engine): PASS
4920 06:55:29.750060 TX OE : NO K
4921 06:55:29.752687 All Pass.
4922 06:55:29.753120
4923 06:55:29.753668 DramC Write-DBI off
4924 06:55:29.755964 PER_BANK_REFRESH: Hybrid Mode
4925 06:55:29.759564 TX_TRACKING: ON
4926 06:55:29.765820 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4927 06:55:29.768722 [FAST_K] Save calibration result to emmc
4928 06:55:29.772518 dramc_set_vcore_voltage set vcore to 662500
4929 06:55:29.775697 Read voltage for 933, 3
4930 06:55:29.776236 Vio18 = 0
4931 06:55:29.778454 Vcore = 662500
4932 06:55:29.778891 Vdram = 0
4933 06:55:29.779424 Vddq = 0
4934 06:55:29.781848 Vmddr = 0
4935 06:55:29.785592 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4936 06:55:29.792259 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4937 06:55:29.792810 MEM_TYPE=3, freq_sel=17
4938 06:55:29.795465 sv_algorithm_assistance_LP4_1600
4939 06:55:29.802244 ============ PULL DRAM RESETB DOWN ============
4940 06:55:29.805208 ========== PULL DRAM RESETB DOWN end =========
4941 06:55:29.808784 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4942 06:55:29.812134 ===================================
4943 06:55:29.815106 LPDDR4 DRAM CONFIGURATION
4944 06:55:29.818539 ===================================
4945 06:55:29.821696 EX_ROW_EN[0] = 0x0
4946 06:55:29.822217 EX_ROW_EN[1] = 0x0
4947 06:55:29.824920 LP4Y_EN = 0x0
4948 06:55:29.825355 WORK_FSP = 0x0
4949 06:55:29.828597 WL = 0x3
4950 06:55:29.829182 RL = 0x3
4951 06:55:29.831630 BL = 0x2
4952 06:55:29.832069 RPST = 0x0
4953 06:55:29.835114 RD_PRE = 0x0
4954 06:55:29.835630 WR_PRE = 0x1
4955 06:55:29.838433 WR_PST = 0x0
4956 06:55:29.838976 DBI_WR = 0x0
4957 06:55:29.841446 DBI_RD = 0x0
4958 06:55:29.841921 OTF = 0x1
4959 06:55:29.844992 ===================================
4960 06:55:29.848339 ===================================
4961 06:55:29.851770 ANA top config
4962 06:55:29.854858 ===================================
4963 06:55:29.858245 DLL_ASYNC_EN = 0
4964 06:55:29.858785 ALL_SLAVE_EN = 1
4965 06:55:29.861364 NEW_RANK_MODE = 1
4966 06:55:29.864666 DLL_IDLE_MODE = 1
4967 06:55:29.868260 LP45_APHY_COMB_EN = 1
4968 06:55:29.871115 TX_ODT_DIS = 1
4969 06:55:29.871551 NEW_8X_MODE = 1
4970 06:55:29.874726 ===================================
4971 06:55:29.877992 ===================================
4972 06:55:29.880850 data_rate = 1866
4973 06:55:29.884526 CKR = 1
4974 06:55:29.888165 DQ_P2S_RATIO = 8
4975 06:55:29.891293 ===================================
4976 06:55:29.894349 CA_P2S_RATIO = 8
4977 06:55:29.897682 DQ_CA_OPEN = 0
4978 06:55:29.898127 DQ_SEMI_OPEN = 0
4979 06:55:29.900611 CA_SEMI_OPEN = 0
4980 06:55:29.904576 CA_FULL_RATE = 0
4981 06:55:29.907769 DQ_CKDIV4_EN = 1
4982 06:55:29.910907 CA_CKDIV4_EN = 1
4983 06:55:29.914641 CA_PREDIV_EN = 0
4984 06:55:29.915222 PH8_DLY = 0
4985 06:55:29.917688 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4986 06:55:29.921068 DQ_AAMCK_DIV = 4
4987 06:55:29.924084 CA_AAMCK_DIV = 4
4988 06:55:29.927675 CA_ADMCK_DIV = 4
4989 06:55:29.931327 DQ_TRACK_CA_EN = 0
4990 06:55:29.931897 CA_PICK = 933
4991 06:55:29.934207 CA_MCKIO = 933
4992 06:55:29.937433 MCKIO_SEMI = 0
4993 06:55:29.940893 PLL_FREQ = 3732
4994 06:55:29.944471 DQ_UI_PI_RATIO = 32
4995 06:55:29.947326 CA_UI_PI_RATIO = 0
4996 06:55:29.951145 ===================================
4997 06:55:29.953969 ===================================
4998 06:55:29.954506 memory_type:LPDDR4
4999 06:55:29.957768 GP_NUM : 10
5000 06:55:29.960522 SRAM_EN : 1
5001 06:55:29.960961 MD32_EN : 0
5002 06:55:29.964322 ===================================
5003 06:55:29.967009 [ANA_INIT] >>>>>>>>>>>>>>
5004 06:55:29.970893 <<<<<< [CONFIGURE PHASE]: ANA_TX
5005 06:55:29.974005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5006 06:55:29.977621 ===================================
5007 06:55:29.980508 data_rate = 1866,PCW = 0X8f00
5008 06:55:29.983942 ===================================
5009 06:55:29.987554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5010 06:55:29.990990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5011 06:55:29.997436 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5012 06:55:30.000499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5013 06:55:30.007103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5014 06:55:30.010131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5015 06:55:30.010573 [ANA_INIT] flow start
5016 06:55:30.014007 [ANA_INIT] PLL >>>>>>>>
5017 06:55:30.017176 [ANA_INIT] PLL <<<<<<<<
5018 06:55:30.017756 [ANA_INIT] MIDPI >>>>>>>>
5019 06:55:30.020622 [ANA_INIT] MIDPI <<<<<<<<
5020 06:55:30.024059 [ANA_INIT] DLL >>>>>>>>
5021 06:55:30.024602 [ANA_INIT] flow end
5022 06:55:30.030381 ============ LP4 DIFF to SE enter ============
5023 06:55:30.033910 ============ LP4 DIFF to SE exit ============
5024 06:55:30.034446 [ANA_INIT] <<<<<<<<<<<<<
5025 06:55:30.036771 [Flow] Enable top DCM control >>>>>
5026 06:55:30.040095 [Flow] Enable top DCM control <<<<<
5027 06:55:30.043626 Enable DLL master slave shuffle
5028 06:55:30.050513 ==============================================================
5029 06:55:30.053639 Gating Mode config
5030 06:55:30.056713 ==============================================================
5031 06:55:30.060099 Config description:
5032 06:55:30.070108 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5033 06:55:30.076630 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5034 06:55:30.079335 SELPH_MODE 0: By rank 1: By Phase
5035 06:55:30.085989 ==============================================================
5036 06:55:30.089652 GAT_TRACK_EN = 1
5037 06:55:30.093243 RX_GATING_MODE = 2
5038 06:55:30.096441 RX_GATING_TRACK_MODE = 2
5039 06:55:30.096969 SELPH_MODE = 1
5040 06:55:30.099776 PICG_EARLY_EN = 1
5041 06:55:30.102998 VALID_LAT_VALUE = 1
5042 06:55:30.109960 ==============================================================
5043 06:55:30.112516 Enter into Gating configuration >>>>
5044 06:55:30.116581 Exit from Gating configuration <<<<
5045 06:55:30.119935 Enter into DVFS_PRE_config >>>>>
5046 06:55:30.129739 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5047 06:55:30.133084 Exit from DVFS_PRE_config <<<<<
5048 06:55:30.136464 Enter into PICG configuration >>>>
5049 06:55:30.139393 Exit from PICG configuration <<<<
5050 06:55:30.142778 [RX_INPUT] configuration >>>>>
5051 06:55:30.145923 [RX_INPUT] configuration <<<<<
5052 06:55:30.149333 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5053 06:55:30.155938 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5054 06:55:30.162415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5055 06:55:30.169084 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5056 06:55:30.175820 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5057 06:55:30.179039 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5058 06:55:30.185801 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5059 06:55:30.189021 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5060 06:55:30.192524 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5061 06:55:30.195669 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5062 06:55:30.202154 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5063 06:55:30.205820 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5064 06:55:30.208775 ===================================
5065 06:55:30.212231 LPDDR4 DRAM CONFIGURATION
5066 06:55:30.215779 ===================================
5067 06:55:30.216204 EX_ROW_EN[0] = 0x0
5068 06:55:30.219335 EX_ROW_EN[1] = 0x0
5069 06:55:30.219867 LP4Y_EN = 0x0
5070 06:55:30.222421 WORK_FSP = 0x0
5071 06:55:30.222946 WL = 0x3
5072 06:55:30.225766 RL = 0x3
5073 06:55:30.226353 BL = 0x2
5074 06:55:30.229290 RPST = 0x0
5075 06:55:30.229868 RD_PRE = 0x0
5076 06:55:30.232457 WR_PRE = 0x1
5077 06:55:30.232878 WR_PST = 0x0
5078 06:55:30.235613 DBI_WR = 0x0
5079 06:55:30.238919 DBI_RD = 0x0
5080 06:55:30.239447 OTF = 0x1
5081 06:55:30.242163 ===================================
5082 06:55:30.245700 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5083 06:55:30.248835 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5084 06:55:30.255737 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5085 06:55:30.258705 ===================================
5086 06:55:30.262269 LPDDR4 DRAM CONFIGURATION
5087 06:55:30.262795 ===================================
5088 06:55:30.265774 EX_ROW_EN[0] = 0x10
5089 06:55:30.268990 EX_ROW_EN[1] = 0x0
5090 06:55:30.269418 LP4Y_EN = 0x0
5091 06:55:30.272177 WORK_FSP = 0x0
5092 06:55:30.272599 WL = 0x3
5093 06:55:30.275227 RL = 0x3
5094 06:55:30.275651 BL = 0x2
5095 06:55:30.278816 RPST = 0x0
5096 06:55:30.279341 RD_PRE = 0x0
5097 06:55:30.281928 WR_PRE = 0x1
5098 06:55:30.282596 WR_PST = 0x0
5099 06:55:30.285320 DBI_WR = 0x0
5100 06:55:30.285777 DBI_RD = 0x0
5101 06:55:30.288639 OTF = 0x1
5102 06:55:30.292195 ===================================
5103 06:55:30.298652 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5104 06:55:30.301709 nWR fixed to 30
5105 06:55:30.305010 [ModeRegInit_LP4] CH0 RK0
5106 06:55:30.305433 [ModeRegInit_LP4] CH0 RK1
5107 06:55:30.308335 [ModeRegInit_LP4] CH1 RK0
5108 06:55:30.311781 [ModeRegInit_LP4] CH1 RK1
5109 06:55:30.312209 match AC timing 9
5110 06:55:30.318124 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5111 06:55:30.321529 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5112 06:55:30.325329 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5113 06:55:30.331724 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5114 06:55:30.335121 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5115 06:55:30.335645 ==
5116 06:55:30.338279 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 06:55:30.341682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 06:55:30.342201 ==
5119 06:55:30.348483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5120 06:55:30.355097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5121 06:55:30.358097 [CA 0] Center 38 (8~69) winsize 62
5122 06:55:30.361686 [CA 1] Center 38 (7~69) winsize 63
5123 06:55:30.365197 [CA 2] Center 35 (5~65) winsize 61
5124 06:55:30.368600 [CA 3] Center 35 (5~65) winsize 61
5125 06:55:30.371121 [CA 4] Center 34 (4~65) winsize 62
5126 06:55:30.375192 [CA 5] Center 33 (3~64) winsize 62
5127 06:55:30.375717
5128 06:55:30.377724 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5129 06:55:30.378147
5130 06:55:30.381280 [CATrainingPosCal] consider 1 rank data
5131 06:55:30.384399 u2DelayCellTimex100 = 270/100 ps
5132 06:55:30.387978 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5133 06:55:30.391327 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5134 06:55:30.394472 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5135 06:55:30.397526 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5136 06:55:30.404461 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5137 06:55:30.407843 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5138 06:55:30.408471
5139 06:55:30.411000 CA PerBit enable=1, Macro0, CA PI delay=33
5140 06:55:30.411425
5141 06:55:30.414224 [CBTSetCACLKResult] CA Dly = 33
5142 06:55:30.414743 CS Dly: 7 (0~38)
5143 06:55:30.415083 ==
5144 06:55:30.417744 Dram Type= 6, Freq= 0, CH_0, rank 1
5145 06:55:30.424395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 06:55:30.424917 ==
5147 06:55:30.428054 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5148 06:55:30.434336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5149 06:55:30.437467 [CA 0] Center 38 (8~69) winsize 62
5150 06:55:30.440962 [CA 1] Center 38 (8~69) winsize 62
5151 06:55:30.443992 [CA 2] Center 35 (5~66) winsize 62
5152 06:55:30.447890 [CA 3] Center 35 (5~66) winsize 62
5153 06:55:30.450874 [CA 4] Center 34 (4~65) winsize 62
5154 06:55:30.454186 [CA 5] Center 34 (4~64) winsize 61
5155 06:55:30.454709
5156 06:55:30.457069 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5157 06:55:30.457518
5158 06:55:30.460723 [CATrainingPosCal] consider 2 rank data
5159 06:55:30.463740 u2DelayCellTimex100 = 270/100 ps
5160 06:55:30.467660 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5161 06:55:30.470766 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5162 06:55:30.474066 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5163 06:55:30.480692 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5164 06:55:30.483655 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5165 06:55:30.487337 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5166 06:55:30.487874
5167 06:55:30.490644 CA PerBit enable=1, Macro0, CA PI delay=34
5168 06:55:30.491177
5169 06:55:30.493873 [CBTSetCACLKResult] CA Dly = 34
5170 06:55:30.494333 CS Dly: 7 (0~38)
5171 06:55:30.494682
5172 06:55:30.497408 ----->DramcWriteLeveling(PI) begin...
5173 06:55:30.500406 ==
5174 06:55:30.500830 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 06:55:30.506819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 06:55:30.507338 ==
5177 06:55:30.510273 Write leveling (Byte 0): 32 => 32
5178 06:55:30.514061 Write leveling (Byte 1): 28 => 28
5179 06:55:30.517227 DramcWriteLeveling(PI) end<-----
5180 06:55:30.517716
5181 06:55:30.518121 ==
5182 06:55:30.520200 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 06:55:30.523597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 06:55:30.524025 ==
5185 06:55:30.526826 [Gating] SW mode calibration
5186 06:55:30.533256 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5187 06:55:30.536811 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5188 06:55:30.543433 0 14 0 | B1->B0 | 2322 2b2b | 1 1 | (0 0) (1 1)
5189 06:55:30.546473 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5190 06:55:30.549866 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 06:55:30.556968 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 06:55:30.559999 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 06:55:30.563297 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 06:55:30.570244 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 06:55:30.573443 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5196 06:55:30.576713 0 15 0 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
5197 06:55:30.583244 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5198 06:55:30.586611 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 06:55:30.589661 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 06:55:30.596678 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 06:55:30.600252 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 06:55:30.603031 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 06:55:30.609637 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 06:55:30.613210 1 0 0 | B1->B0 | 2828 3a3a | 0 1 | (0 0) (0 0)
5205 06:55:30.616661 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5206 06:55:30.622895 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 06:55:30.626445 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 06:55:30.629407 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 06:55:30.636930 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 06:55:30.639511 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 06:55:30.642739 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 06:55:30.649790 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5213 06:55:30.652778 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5214 06:55:30.656209 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 06:55:30.662617 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 06:55:30.666231 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 06:55:30.669146 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 06:55:30.676324 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 06:55:30.679754 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 06:55:30.682952 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 06:55:30.689264 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 06:55:30.692904 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 06:55:30.696478 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 06:55:30.702301 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 06:55:30.705641 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 06:55:30.709067 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 06:55:30.716174 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5228 06:55:30.719578 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5229 06:55:30.722463 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5230 06:55:30.726139 Total UI for P1: 0, mck2ui 16
5231 06:55:30.729305 best dqsien dly found for B0: ( 1, 2, 30)
5232 06:55:30.732314 Total UI for P1: 0, mck2ui 16
5233 06:55:30.735694 best dqsien dly found for B1: ( 1, 3, 2)
5234 06:55:30.739407 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5235 06:55:30.742422 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5236 06:55:30.742957
5237 06:55:30.745773 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5238 06:55:30.752501 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5239 06:55:30.753039 [Gating] SW calibration Done
5240 06:55:30.753382 ==
5241 06:55:30.755815 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 06:55:30.762310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 06:55:30.762742 ==
5244 06:55:30.763076 RX Vref Scan: 0
5245 06:55:30.763390
5246 06:55:30.765240 RX Vref 0 -> 0, step: 1
5247 06:55:30.765708
5248 06:55:30.768684 RX Delay -80 -> 252, step: 8
5249 06:55:30.772235 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5250 06:55:30.775288 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5251 06:55:30.778582 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5252 06:55:30.782213 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5253 06:55:30.788700 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5254 06:55:30.792084 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5255 06:55:30.795097 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5256 06:55:30.798491 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5257 06:55:30.801765 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5258 06:55:30.808585 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5259 06:55:30.811907 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5260 06:55:30.815044 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5261 06:55:30.818418 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5262 06:55:30.821724 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5263 06:55:30.828630 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5264 06:55:30.831886 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5265 06:55:30.832420 ==
5266 06:55:30.834764 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 06:55:30.838163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 06:55:30.838697 ==
5269 06:55:30.841706 DQS Delay:
5270 06:55:30.842238 DQS0 = 0, DQS1 = 0
5271 06:55:30.842584 DQM Delay:
5272 06:55:30.844634 DQM0 = 94, DQM1 = 83
5273 06:55:30.845058 DQ Delay:
5274 06:55:30.848012 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5275 06:55:30.851161 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =111
5276 06:55:30.854955 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5277 06:55:30.857879 DQ12 =83, DQ13 =91, DQ14 =91, DQ15 =91
5278 06:55:30.858306
5279 06:55:30.858639
5280 06:55:30.858952 ==
5281 06:55:30.861172 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 06:55:30.868058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 06:55:30.868593 ==
5284 06:55:30.868936
5285 06:55:30.869247
5286 06:55:30.871450 TX Vref Scan disable
5287 06:55:30.871984 == TX Byte 0 ==
5288 06:55:30.874264 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5289 06:55:30.881352 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5290 06:55:30.881950 == TX Byte 1 ==
5291 06:55:30.884253 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5292 06:55:30.891410 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5293 06:55:30.891960 ==
5294 06:55:30.894564 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 06:55:30.897350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 06:55:30.897812 ==
5297 06:55:30.898151
5298 06:55:30.898461
5299 06:55:30.900595 TX Vref Scan disable
5300 06:55:30.904100 == TX Byte 0 ==
5301 06:55:30.907870 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5302 06:55:30.910704 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5303 06:55:30.913916 == TX Byte 1 ==
5304 06:55:30.917551 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5305 06:55:30.921125 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5306 06:55:30.921701
5307 06:55:30.923985 [DATLAT]
5308 06:55:30.924406 Freq=933, CH0 RK0
5309 06:55:30.924746
5310 06:55:30.927214 DATLAT Default: 0xd
5311 06:55:30.927638 0, 0xFFFF, sum = 0
5312 06:55:30.930265 1, 0xFFFF, sum = 0
5313 06:55:30.930700 2, 0xFFFF, sum = 0
5314 06:55:30.933622 3, 0xFFFF, sum = 0
5315 06:55:30.934057 4, 0xFFFF, sum = 0
5316 06:55:30.937338 5, 0xFFFF, sum = 0
5317 06:55:30.937921 6, 0xFFFF, sum = 0
5318 06:55:30.940541 7, 0xFFFF, sum = 0
5319 06:55:30.941078 8, 0xFFFF, sum = 0
5320 06:55:30.943758 9, 0xFFFF, sum = 0
5321 06:55:30.944206 10, 0x0, sum = 1
5322 06:55:30.947056 11, 0x0, sum = 2
5323 06:55:30.947487 12, 0x0, sum = 3
5324 06:55:30.950165 13, 0x0, sum = 4
5325 06:55:30.950599 best_step = 11
5326 06:55:30.950939
5327 06:55:30.951253 ==
5328 06:55:30.953713 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 06:55:30.960462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 06:55:30.960994 ==
5331 06:55:30.961337 RX Vref Scan: 1
5332 06:55:30.961693
5333 06:55:30.963273 RX Vref 0 -> 0, step: 1
5334 06:55:30.963699
5335 06:55:30.966936 RX Delay -69 -> 252, step: 4
5336 06:55:30.967463
5337 06:55:30.970425 Set Vref, RX VrefLevel [Byte0]: 61
5338 06:55:30.973373 [Byte1]: 57
5339 06:55:30.973935
5340 06:55:30.977109 Final RX Vref Byte 0 = 61 to rank0
5341 06:55:30.979874 Final RX Vref Byte 1 = 57 to rank0
5342 06:55:30.983508 Final RX Vref Byte 0 = 61 to rank1
5343 06:55:30.986849 Final RX Vref Byte 1 = 57 to rank1==
5344 06:55:30.989932 Dram Type= 6, Freq= 0, CH_0, rank 0
5345 06:55:30.993340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 06:55:30.993813 ==
5347 06:55:30.996714 DQS Delay:
5348 06:55:30.997135 DQS0 = 0, DQS1 = 0
5349 06:55:30.997471 DQM Delay:
5350 06:55:31.000087 DQM0 = 95, DQM1 = 84
5351 06:55:31.000512 DQ Delay:
5352 06:55:31.003194 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5353 06:55:31.006445 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5354 06:55:31.009973 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =80
5355 06:55:31.013396 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5356 06:55:31.013964
5357 06:55:31.014304
5358 06:55:31.022985 [DQSOSCAuto] RK0, (LSB)MR18= 0x1716, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5359 06:55:31.026285 CH0 RK0: MR19=505, MR18=1716
5360 06:55:31.032648 CH0_RK0: MR19=0x505, MR18=0x1716, DQSOSC=414, MR23=63, INC=63, DEC=42
5361 06:55:31.033070
5362 06:55:31.036322 ----->DramcWriteLeveling(PI) begin...
5363 06:55:31.036747 ==
5364 06:55:31.039218 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 06:55:31.042601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 06:55:31.043060 ==
5367 06:55:31.046016 Write leveling (Byte 0): 29 => 29
5368 06:55:31.049598 Write leveling (Byte 1): 29 => 29
5369 06:55:31.053193 DramcWriteLeveling(PI) end<-----
5370 06:55:31.053756
5371 06:55:31.054093 ==
5372 06:55:31.056238 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 06:55:31.059558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 06:55:31.060141 ==
5375 06:55:31.062518 [Gating] SW mode calibration
5376 06:55:31.069362 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5377 06:55:31.076077 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5378 06:55:31.079145 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
5379 06:55:31.082324 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 06:55:31.088647 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 06:55:31.092266 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 06:55:31.095353 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 06:55:31.102110 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 06:55:31.105429 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 06:55:31.108770 0 14 28 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
5386 06:55:31.115683 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5387 06:55:31.119227 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 06:55:31.122354 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 06:55:31.128944 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 06:55:31.132062 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 06:55:31.135360 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 06:55:31.141991 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 06:55:31.145015 0 15 28 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
5394 06:55:31.148308 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5395 06:55:31.155180 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 06:55:31.158495 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 06:55:31.161523 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 06:55:31.168204 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 06:55:31.171727 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 06:55:31.174892 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 06:55:31.181571 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5402 06:55:31.184939 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5403 06:55:31.188250 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 06:55:31.194566 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 06:55:31.197951 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 06:55:31.201609 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 06:55:31.207921 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 06:55:31.211357 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 06:55:31.214468 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 06:55:31.221696 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 06:55:31.225170 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 06:55:31.227802 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 06:55:31.234003 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 06:55:31.237688 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 06:55:31.240922 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 06:55:31.247449 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 06:55:31.250741 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5418 06:55:31.254346 Total UI for P1: 0, mck2ui 16
5419 06:55:31.257257 best dqsien dly found for B0: ( 1, 2, 26)
5420 06:55:31.260944 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5421 06:55:31.267531 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 06:55:31.268061 Total UI for P1: 0, mck2ui 16
5423 06:55:31.273672 best dqsien dly found for B1: ( 1, 2, 30)
5424 06:55:31.277248 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5425 06:55:31.280443 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5426 06:55:31.280966
5427 06:55:31.283792 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5428 06:55:31.287206 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5429 06:55:31.290375 [Gating] SW calibration Done
5430 06:55:31.290799 ==
5431 06:55:31.293703 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 06:55:31.296869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 06:55:31.297298 ==
5434 06:55:31.300451 RX Vref Scan: 0
5435 06:55:31.300973
5436 06:55:31.301314 RX Vref 0 -> 0, step: 1
5437 06:55:31.301698
5438 06:55:31.303991 RX Delay -80 -> 252, step: 8
5439 06:55:31.307139 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5440 06:55:31.313894 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5441 06:55:31.316889 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5442 06:55:31.320764 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5443 06:55:31.323975 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5444 06:55:31.326676 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5445 06:55:31.333888 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5446 06:55:31.336912 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5447 06:55:31.340177 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5448 06:55:31.343714 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5449 06:55:31.346622 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5450 06:55:31.353170 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5451 06:55:31.356510 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5452 06:55:31.360180 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5453 06:55:31.363251 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5454 06:55:31.366493 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5455 06:55:31.366919 ==
5456 06:55:31.369854 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 06:55:31.376754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 06:55:31.377281 ==
5459 06:55:31.377679 DQS Delay:
5460 06:55:31.380093 DQS0 = 0, DQS1 = 0
5461 06:55:31.380618 DQM Delay:
5462 06:55:31.380960 DQM0 = 93, DQM1 = 83
5463 06:55:31.383013 DQ Delay:
5464 06:55:31.386168 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =87
5465 06:55:31.389598 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5466 06:55:31.392936 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5467 06:55:31.395969 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5468 06:55:31.396406
5469 06:55:31.396739
5470 06:55:31.397048 ==
5471 06:55:31.399235 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 06:55:31.402937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 06:55:31.403468 ==
5474 06:55:31.403815
5475 06:55:31.404329
5476 06:55:31.406209 TX Vref Scan disable
5477 06:55:31.409833 == TX Byte 0 ==
5478 06:55:31.413285 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5479 06:55:31.416248 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5480 06:55:31.419770 == TX Byte 1 ==
5481 06:55:31.422859 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5482 06:55:31.426385 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5483 06:55:31.426912 ==
5484 06:55:31.429931 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 06:55:31.433111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 06:55:31.435837 ==
5487 06:55:31.436259
5488 06:55:31.436594
5489 06:55:31.436901 TX Vref Scan disable
5490 06:55:31.439531 == TX Byte 0 ==
5491 06:55:31.442827 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5492 06:55:31.449592 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5493 06:55:31.450110 == TX Byte 1 ==
5494 06:55:31.453092 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5495 06:55:31.459128 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5496 06:55:31.459640
5497 06:55:31.459977 [DATLAT]
5498 06:55:31.460289 Freq=933, CH0 RK1
5499 06:55:31.460593
5500 06:55:31.462667 DATLAT Default: 0xb
5501 06:55:31.463212 0, 0xFFFF, sum = 0
5502 06:55:31.465756 1, 0xFFFF, sum = 0
5503 06:55:31.469217 2, 0xFFFF, sum = 0
5504 06:55:31.469690 3, 0xFFFF, sum = 0
5505 06:55:31.472655 4, 0xFFFF, sum = 0
5506 06:55:31.473184 5, 0xFFFF, sum = 0
5507 06:55:31.475720 6, 0xFFFF, sum = 0
5508 06:55:31.476249 7, 0xFFFF, sum = 0
5509 06:55:31.479470 8, 0xFFFF, sum = 0
5510 06:55:31.480007 9, 0xFFFF, sum = 0
5511 06:55:31.482640 10, 0x0, sum = 1
5512 06:55:31.483171 11, 0x0, sum = 2
5513 06:55:31.486174 12, 0x0, sum = 3
5514 06:55:31.486709 13, 0x0, sum = 4
5515 06:55:31.487057 best_step = 11
5516 06:55:31.487371
5517 06:55:31.489075 ==
5518 06:55:31.492486 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 06:55:31.495805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 06:55:31.496236 ==
5521 06:55:31.496573 RX Vref Scan: 0
5522 06:55:31.496884
5523 06:55:31.498958 RX Vref 0 -> 0, step: 1
5524 06:55:31.499382
5525 06:55:31.502986 RX Delay -77 -> 252, step: 4
5526 06:55:31.505872 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5527 06:55:31.512591 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5528 06:55:31.515579 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5529 06:55:31.519547 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5530 06:55:31.522233 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5531 06:55:31.525797 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5532 06:55:31.528987 iDelay=199, Bit 6, Center 102 (7 ~ 198) 192
5533 06:55:31.536125 iDelay=199, Bit 7, Center 100 (7 ~ 194) 188
5534 06:55:31.539340 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5535 06:55:31.542580 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5536 06:55:31.545599 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5537 06:55:31.548639 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5538 06:55:31.555753 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5539 06:55:31.558739 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5540 06:55:31.562232 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5541 06:55:31.565817 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5542 06:55:31.566340 ==
5543 06:55:31.568461 Dram Type= 6, Freq= 0, CH_0, rank 1
5544 06:55:31.572173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 06:55:31.575746 ==
5546 06:55:31.576267 DQS Delay:
5547 06:55:31.576607 DQS0 = 0, DQS1 = 0
5548 06:55:31.578649 DQM Delay:
5549 06:55:31.579072 DQM0 = 92, DQM1 = 85
5550 06:55:31.582123 DQ Delay:
5551 06:55:31.585516 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5552 06:55:31.588218 DQ4 =92, DQ5 =82, DQ6 =102, DQ7 =100
5553 06:55:31.591567 DQ8 =80, DQ9 =70, DQ10 =84, DQ11 =80
5554 06:55:31.595241 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5555 06:55:31.595761
5556 06:55:31.596097
5557 06:55:31.601586 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5558 06:55:31.604757 CH0 RK1: MR19=505, MR18=2C0D
5559 06:55:31.611343 CH0_RK1: MR19=0x505, MR18=0x2C0D, DQSOSC=408, MR23=63, INC=65, DEC=43
5560 06:55:31.614820 [RxdqsGatingPostProcess] freq 933
5561 06:55:31.618061 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5562 06:55:31.621370 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 06:55:31.624647 best DQS1 dly(2T, 0.5T) = (0, 11)
5564 06:55:31.628356 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 06:55:31.631673 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5566 06:55:31.634722 best DQS0 dly(2T, 0.5T) = (0, 10)
5567 06:55:31.637960 best DQS1 dly(2T, 0.5T) = (0, 10)
5568 06:55:31.641160 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5569 06:55:31.644712 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5570 06:55:31.648212 Pre-setting of DQS Precalculation
5571 06:55:31.651381 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5572 06:55:31.651806 ==
5573 06:55:31.654864 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 06:55:31.661448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 06:55:31.662014 ==
5576 06:55:31.664994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5577 06:55:31.671370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5578 06:55:31.674592 [CA 0] Center 38 (8~68) winsize 61
5579 06:55:31.678110 [CA 1] Center 38 (8~69) winsize 62
5580 06:55:31.681102 [CA 2] Center 35 (6~65) winsize 60
5581 06:55:31.684761 [CA 3] Center 35 (5~65) winsize 61
5582 06:55:31.688322 [CA 4] Center 35 (5~65) winsize 61
5583 06:55:31.691444 [CA 5] Center 34 (5~64) winsize 60
5584 06:55:31.691912
5585 06:55:31.694436 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5586 06:55:31.694863
5587 06:55:31.697973 [CATrainingPosCal] consider 1 rank data
5588 06:55:31.701565 u2DelayCellTimex100 = 270/100 ps
5589 06:55:31.704738 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5590 06:55:31.707976 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5591 06:55:31.714520 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5592 06:55:31.717893 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5593 06:55:31.721371 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5594 06:55:31.724380 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5595 06:55:31.724906
5596 06:55:31.727748 CA PerBit enable=1, Macro0, CA PI delay=34
5597 06:55:31.728275
5598 06:55:31.730776 [CBTSetCACLKResult] CA Dly = 34
5599 06:55:31.731298 CS Dly: 6 (0~37)
5600 06:55:31.734103 ==
5601 06:55:31.737705 Dram Type= 6, Freq= 0, CH_1, rank 1
5602 06:55:31.740720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 06:55:31.741243 ==
5604 06:55:31.747616 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5605 06:55:31.750756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5606 06:55:31.754487 [CA 0] Center 38 (8~69) winsize 62
5607 06:55:31.758091 [CA 1] Center 38 (8~69) winsize 62
5608 06:55:31.761171 [CA 2] Center 36 (6~66) winsize 61
5609 06:55:31.764563 [CA 3] Center 35 (5~65) winsize 61
5610 06:55:31.767978 [CA 4] Center 36 (6~66) winsize 61
5611 06:55:31.771335 [CA 5] Center 34 (4~64) winsize 61
5612 06:55:31.771858
5613 06:55:31.774327 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5614 06:55:31.774755
5615 06:55:31.778002 [CATrainingPosCal] consider 2 rank data
5616 06:55:31.781054 u2DelayCellTimex100 = 270/100 ps
5617 06:55:31.784404 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5618 06:55:31.790833 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5619 06:55:31.794000 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5620 06:55:31.797897 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5621 06:55:31.800959 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5622 06:55:31.804630 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5623 06:55:31.805166
5624 06:55:31.807613 CA PerBit enable=1, Macro0, CA PI delay=34
5625 06:55:31.808141
5626 06:55:31.810744 [CBTSetCACLKResult] CA Dly = 34
5627 06:55:31.814264 CS Dly: 7 (0~39)
5628 06:55:31.814833
5629 06:55:31.817533 ----->DramcWriteLeveling(PI) begin...
5630 06:55:31.818070 ==
5631 06:55:31.820922 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 06:55:31.823812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 06:55:31.824245 ==
5634 06:55:31.827614 Write leveling (Byte 0): 24 => 24
5635 06:55:31.830664 Write leveling (Byte 1): 27 => 27
5636 06:55:31.833950 DramcWriteLeveling(PI) end<-----
5637 06:55:31.834374
5638 06:55:31.834708 ==
5639 06:55:31.837513 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 06:55:31.840494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 06:55:31.840925 ==
5642 06:55:31.844208 [Gating] SW mode calibration
5643 06:55:31.850651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5644 06:55:31.857032 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5645 06:55:31.860754 0 14 0 | B1->B0 | 2c2c 2d2d | 0 0 | (0 0) (0 0)
5646 06:55:31.863885 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 06:55:31.870441 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 06:55:31.873758 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 06:55:31.876874 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 06:55:31.883570 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 06:55:31.886598 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 06:55:31.890055 0 14 28 | B1->B0 | 2f2f 3030 | 1 1 | (1 1) (1 1)
5653 06:55:31.896964 0 15 0 | B1->B0 | 2a2a 2929 | 1 1 | (1 0) (1 0)
5654 06:55:31.900104 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 06:55:31.903501 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 06:55:31.910127 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 06:55:31.913295 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 06:55:31.916685 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 06:55:31.923402 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 06:55:31.926842 0 15 28 | B1->B0 | 3030 3131 | 0 0 | (1 1) (1 1)
5661 06:55:31.930007 1 0 0 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
5662 06:55:31.936311 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 06:55:31.939758 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 06:55:31.942589 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 06:55:31.949956 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 06:55:31.952729 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 06:55:31.956308 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 06:55:31.963077 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5669 06:55:31.966090 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5670 06:55:31.969336 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 06:55:31.975737 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 06:55:31.979646 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 06:55:31.982750 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 06:55:31.989638 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 06:55:31.992706 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 06:55:31.996256 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 06:55:32.002931 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 06:55:32.005798 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 06:55:32.009535 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 06:55:32.015841 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 06:55:32.019377 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 06:55:32.022408 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 06:55:32.025995 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 06:55:32.032422 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5685 06:55:32.035789 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5686 06:55:32.039098 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5687 06:55:32.042658 Total UI for P1: 0, mck2ui 16
5688 06:55:32.045898 best dqsien dly found for B0: ( 1, 2, 30)
5689 06:55:32.048845 Total UI for P1: 0, mck2ui 16
5690 06:55:32.052490 best dqsien dly found for B1: ( 1, 2, 30)
5691 06:55:32.055718 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5692 06:55:32.062175 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5693 06:55:32.062681
5694 06:55:32.065360 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5695 06:55:32.068677 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5696 06:55:32.072248 [Gating] SW calibration Done
5697 06:55:32.072769 ==
5698 06:55:32.075328 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 06:55:32.079000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 06:55:32.079565 ==
5701 06:55:32.080124 RX Vref Scan: 0
5702 06:55:32.081921
5703 06:55:32.082344 RX Vref 0 -> 0, step: 1
5704 06:55:32.082681
5705 06:55:32.085339 RX Delay -80 -> 252, step: 8
5706 06:55:32.088831 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5707 06:55:32.092232 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5708 06:55:32.098552 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5709 06:55:32.101916 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5710 06:55:32.105378 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5711 06:55:32.108619 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5712 06:55:32.112156 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5713 06:55:32.115066 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5714 06:55:32.121835 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5715 06:55:32.125556 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5716 06:55:32.128556 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5717 06:55:32.132118 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5718 06:55:32.135203 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5719 06:55:32.138575 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5720 06:55:32.145162 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5721 06:55:32.148298 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5722 06:55:32.148822 ==
5723 06:55:32.152008 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 06:55:32.154761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 06:55:32.155188 ==
5726 06:55:32.158329 DQS Delay:
5727 06:55:32.158752 DQS0 = 0, DQS1 = 0
5728 06:55:32.159084 DQM Delay:
5729 06:55:32.161447 DQM0 = 97, DQM1 = 89
5730 06:55:32.161915 DQ Delay:
5731 06:55:32.165181 DQ0 =99, DQ1 =95, DQ2 =87, DQ3 =95
5732 06:55:32.168143 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5733 06:55:32.171316 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5734 06:55:32.174980 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5735 06:55:32.175504
5736 06:55:32.175844
5737 06:55:32.176154 ==
5738 06:55:32.177954 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 06:55:32.184560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 06:55:32.185082 ==
5741 06:55:32.185424
5742 06:55:32.185769
5743 06:55:32.186070 TX Vref Scan disable
5744 06:55:32.188233 == TX Byte 0 ==
5745 06:55:32.191653 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5746 06:55:32.197914 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5747 06:55:32.198402 == TX Byte 1 ==
5748 06:55:32.201326 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5749 06:55:32.208525 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5750 06:55:32.209074 ==
5751 06:55:32.211579 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 06:55:32.215029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 06:55:32.215583 ==
5754 06:55:32.215931
5755 06:55:32.216248
5756 06:55:32.217927 TX Vref Scan disable
5757 06:55:32.218352 == TX Byte 0 ==
5758 06:55:32.224627 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5759 06:55:32.228452 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5760 06:55:32.228977 == TX Byte 1 ==
5761 06:55:32.234823 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5762 06:55:32.238362 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5763 06:55:32.238886
5764 06:55:32.239224 [DATLAT]
5765 06:55:32.241537 Freq=933, CH1 RK0
5766 06:55:32.242069
5767 06:55:32.242408 DATLAT Default: 0xd
5768 06:55:32.244788 0, 0xFFFF, sum = 0
5769 06:55:32.245319 1, 0xFFFF, sum = 0
5770 06:55:32.247824 2, 0xFFFF, sum = 0
5771 06:55:32.251384 3, 0xFFFF, sum = 0
5772 06:55:32.251913 4, 0xFFFF, sum = 0
5773 06:55:32.254732 5, 0xFFFF, sum = 0
5774 06:55:32.255267 6, 0xFFFF, sum = 0
5775 06:55:32.258003 7, 0xFFFF, sum = 0
5776 06:55:32.258533 8, 0xFFFF, sum = 0
5777 06:55:32.260926 9, 0xFFFF, sum = 0
5778 06:55:32.261356 10, 0x0, sum = 1
5779 06:55:32.264750 11, 0x0, sum = 2
5780 06:55:32.265349 12, 0x0, sum = 3
5781 06:55:32.265758 13, 0x0, sum = 4
5782 06:55:32.267668 best_step = 11
5783 06:55:32.268091
5784 06:55:32.268426 ==
5785 06:55:32.271540 Dram Type= 6, Freq= 0, CH_1, rank 0
5786 06:55:32.274318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 06:55:32.274747 ==
5788 06:55:32.277558 RX Vref Scan: 1
5789 06:55:32.277986
5790 06:55:32.281077 RX Vref 0 -> 0, step: 1
5791 06:55:32.281663
5792 06:55:32.282013 RX Delay -69 -> 252, step: 4
5793 06:55:32.282332
5794 06:55:32.284883 Set Vref, RX VrefLevel [Byte0]: 55
5795 06:55:32.287530 [Byte1]: 55
5796 06:55:32.292401
5797 06:55:32.292929 Final RX Vref Byte 0 = 55 to rank0
5798 06:55:32.295232 Final RX Vref Byte 1 = 55 to rank0
5799 06:55:32.299176 Final RX Vref Byte 0 = 55 to rank1
5800 06:55:32.301779 Final RX Vref Byte 1 = 55 to rank1==
5801 06:55:32.305590 Dram Type= 6, Freq= 0, CH_1, rank 0
5802 06:55:32.312351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 06:55:32.312893 ==
5804 06:55:32.313239 DQS Delay:
5805 06:55:32.315869 DQS0 = 0, DQS1 = 0
5806 06:55:32.316452 DQM Delay:
5807 06:55:32.316801 DQM0 = 99, DQM1 = 92
5808 06:55:32.318884 DQ Delay:
5809 06:55:32.321951 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =96
5810 06:55:32.325635 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =98
5811 06:55:32.328932 DQ8 =82, DQ9 =86, DQ10 =92, DQ11 =86
5812 06:55:32.332172 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =98
5813 06:55:32.332709
5814 06:55:32.333052
5815 06:55:32.338609 [DQSOSCAuto] RK0, (LSB)MR18= 0xff07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5816 06:55:32.342106 CH1 RK0: MR19=405, MR18=FF07
5817 06:55:32.348337 CH1_RK0: MR19=0x405, MR18=0xFF07, DQSOSC=419, MR23=63, INC=61, DEC=41
5818 06:55:32.348859
5819 06:55:32.351986 ----->DramcWriteLeveling(PI) begin...
5820 06:55:32.352546 ==
5821 06:55:32.355361 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 06:55:32.358781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 06:55:32.359324 ==
5824 06:55:32.361894 Write leveling (Byte 0): 27 => 27
5825 06:55:32.365388 Write leveling (Byte 1): 29 => 29
5826 06:55:32.369195 DramcWriteLeveling(PI) end<-----
5827 06:55:32.369777
5828 06:55:32.370120 ==
5829 06:55:32.372148 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 06:55:32.375339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 06:55:32.378556 ==
5832 06:55:32.379084 [Gating] SW mode calibration
5833 06:55:32.384997 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5834 06:55:32.391899 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5835 06:55:32.394918 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5836 06:55:32.401435 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 06:55:32.404951 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 06:55:32.408200 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 06:55:32.415087 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5840 06:55:32.418163 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5841 06:55:32.421680 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5842 06:55:32.428165 0 14 28 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)
5843 06:55:32.431773 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 06:55:32.434692 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 06:55:32.441656 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 06:55:32.445008 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 06:55:32.447963 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 06:55:32.454651 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5849 06:55:32.458093 0 15 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5850 06:55:32.461462 0 15 28 | B1->B0 | 3434 4444 | 1 0 | (1 1) (0 0)
5851 06:55:32.468226 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 06:55:32.471124 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 06:55:32.474914 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 06:55:32.481630 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 06:55:32.484561 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 06:55:32.487665 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5857 06:55:32.494216 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5858 06:55:32.497735 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5859 06:55:32.501245 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 06:55:32.504391 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 06:55:32.511109 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 06:55:32.514242 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 06:55:32.517916 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 06:55:32.524748 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 06:55:32.527835 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 06:55:32.530810 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 06:55:32.537927 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 06:55:32.541167 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 06:55:32.544447 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 06:55:32.550726 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 06:55:32.554298 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 06:55:32.557753 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 06:55:32.564456 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5874 06:55:32.567272 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5875 06:55:32.570814 Total UI for P1: 0, mck2ui 16
5876 06:55:32.574184 best dqsien dly found for B0: ( 1, 2, 24)
5877 06:55:32.578024 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5878 06:55:32.580972 Total UI for P1: 0, mck2ui 16
5879 06:55:32.583908 best dqsien dly found for B1: ( 1, 2, 26)
5880 06:55:32.587437 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5881 06:55:32.590706 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5882 06:55:32.591243
5883 06:55:32.597083 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5884 06:55:32.600556 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5885 06:55:32.604285 [Gating] SW calibration Done
5886 06:55:32.604825 ==
5887 06:55:32.607073 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 06:55:32.610192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 06:55:32.610626 ==
5890 06:55:32.610967 RX Vref Scan: 0
5891 06:55:32.611286
5892 06:55:32.613805 RX Vref 0 -> 0, step: 1
5893 06:55:32.614235
5894 06:55:32.617300 RX Delay -80 -> 252, step: 8
5895 06:55:32.620997 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5896 06:55:32.623978 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5897 06:55:32.627569 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5898 06:55:32.634149 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5899 06:55:32.636932 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5900 06:55:32.640599 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5901 06:55:32.643974 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5902 06:55:32.646999 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5903 06:55:32.653787 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5904 06:55:32.657038 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5905 06:55:32.660512 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5906 06:55:32.663499 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5907 06:55:32.666982 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5908 06:55:32.670043 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5909 06:55:32.677033 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5910 06:55:32.680179 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5911 06:55:32.680726 ==
5912 06:55:32.683686 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 06:55:32.686871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 06:55:32.687414 ==
5915 06:55:32.689984 DQS Delay:
5916 06:55:32.690413 DQS0 = 0, DQS1 = 0
5917 06:55:32.690749 DQM Delay:
5918 06:55:32.693335 DQM0 = 94, DQM1 = 91
5919 06:55:32.693933 DQ Delay:
5920 06:55:32.696616 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5921 06:55:32.699779 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5922 06:55:32.703394 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =83
5923 06:55:32.706776 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5924 06:55:32.707204
5925 06:55:32.707542
5926 06:55:32.707854 ==
5927 06:55:32.709816 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 06:55:32.716412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 06:55:32.716843 ==
5930 06:55:32.717188
5931 06:55:32.717679
5932 06:55:32.718027 TX Vref Scan disable
5933 06:55:32.719745 == TX Byte 0 ==
5934 06:55:32.723077 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5935 06:55:32.729553 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5936 06:55:32.729989 == TX Byte 1 ==
5937 06:55:32.733154 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5938 06:55:32.739801 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5939 06:55:32.740342 ==
5940 06:55:32.743293 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 06:55:32.746190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 06:55:32.746619 ==
5943 06:55:32.746960
5944 06:55:32.747277
5945 06:55:32.749388 TX Vref Scan disable
5946 06:55:32.749844 == TX Byte 0 ==
5947 06:55:32.756733 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5948 06:55:32.759572 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5949 06:55:32.760003 == TX Byte 1 ==
5950 06:55:32.766248 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5951 06:55:32.769347 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5952 06:55:32.769807
5953 06:55:32.770147 [DATLAT]
5954 06:55:32.772794 Freq=933, CH1 RK1
5955 06:55:32.773224
5956 06:55:32.773594 DATLAT Default: 0xb
5957 06:55:32.776060 0, 0xFFFF, sum = 0
5958 06:55:32.776496 1, 0xFFFF, sum = 0
5959 06:55:32.779504 2, 0xFFFF, sum = 0
5960 06:55:32.782856 3, 0xFFFF, sum = 0
5961 06:55:32.783413 4, 0xFFFF, sum = 0
5962 06:55:32.785662 5, 0xFFFF, sum = 0
5963 06:55:32.786104 6, 0xFFFF, sum = 0
5964 06:55:32.789309 7, 0xFFFF, sum = 0
5965 06:55:32.789784 8, 0xFFFF, sum = 0
5966 06:55:32.792588 9, 0xFFFF, sum = 0
5967 06:55:32.793030 10, 0x0, sum = 1
5968 06:55:32.796026 11, 0x0, sum = 2
5969 06:55:32.796466 12, 0x0, sum = 3
5970 06:55:32.799230 13, 0x0, sum = 4
5971 06:55:32.799668 best_step = 11
5972 06:55:32.800100
5973 06:55:32.800509 ==
5974 06:55:32.802431 Dram Type= 6, Freq= 0, CH_1, rank 1
5975 06:55:32.805863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5976 06:55:32.806313 ==
5977 06:55:32.808968 RX Vref Scan: 0
5978 06:55:32.809398
5979 06:55:32.812583 RX Vref 0 -> 0, step: 1
5980 06:55:32.813123
5981 06:55:32.813662 RX Delay -61 -> 252, step: 4
5982 06:55:32.820685 iDelay=203, Bit 0, Center 100 (7 ~ 194) 188
5983 06:55:32.823360 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5984 06:55:32.827173 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5985 06:55:32.830302 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5986 06:55:32.833694 iDelay=203, Bit 4, Center 92 (-1 ~ 186) 188
5987 06:55:32.840104 iDelay=203, Bit 5, Center 106 (15 ~ 198) 184
5988 06:55:32.843765 iDelay=203, Bit 6, Center 108 (15 ~ 202) 188
5989 06:55:32.846841 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5990 06:55:32.850098 iDelay=203, Bit 8, Center 84 (-5 ~ 174) 180
5991 06:55:32.853631 iDelay=203, Bit 9, Center 86 (-1 ~ 174) 176
5992 06:55:32.856752 iDelay=203, Bit 10, Center 98 (7 ~ 190) 184
5993 06:55:32.863594 iDelay=203, Bit 11, Center 88 (-1 ~ 178) 180
5994 06:55:32.866606 iDelay=203, Bit 12, Center 104 (15 ~ 194) 180
5995 06:55:32.870351 iDelay=203, Bit 13, Center 102 (15 ~ 190) 176
5996 06:55:32.873871 iDelay=203, Bit 14, Center 102 (15 ~ 190) 176
5997 06:55:32.880609 iDelay=203, Bit 15, Center 100 (11 ~ 190) 180
5998 06:55:32.881151 ==
5999 06:55:32.883556 Dram Type= 6, Freq= 0, CH_1, rank 1
6000 06:55:32.886600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6001 06:55:32.887066 ==
6002 06:55:32.887506 DQS Delay:
6003 06:55:32.889717 DQS0 = 0, DQS1 = 0
6004 06:55:32.890151 DQM Delay:
6005 06:55:32.893195 DQM0 = 95, DQM1 = 95
6006 06:55:32.893659 DQ Delay:
6007 06:55:32.896579 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =92
6008 06:55:32.899589 DQ4 =92, DQ5 =106, DQ6 =108, DQ7 =92
6009 06:55:32.903254 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =88
6010 06:55:32.906323 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =100
6011 06:55:32.906762
6012 06:55:32.907196
6013 06:55:32.916737 [DQSOSCAuto] RK1, (LSB)MR18= 0xe22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
6014 06:55:32.917283 CH1 RK1: MR19=505, MR18=E22
6015 06:55:32.923056 CH1_RK1: MR19=0x505, MR18=0xE22, DQSOSC=411, MR23=63, INC=64, DEC=42
6016 06:55:32.926085 [RxdqsGatingPostProcess] freq 933
6017 06:55:32.932931 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6018 06:55:32.936464 best DQS0 dly(2T, 0.5T) = (0, 10)
6019 06:55:32.939713 best DQS1 dly(2T, 0.5T) = (0, 10)
6020 06:55:32.943200 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6021 06:55:32.946027 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6022 06:55:32.946571 best DQS0 dly(2T, 0.5T) = (0, 10)
6023 06:55:32.949380 best DQS1 dly(2T, 0.5T) = (0, 10)
6024 06:55:32.952909 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6025 06:55:32.956195 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6026 06:55:32.959575 Pre-setting of DQS Precalculation
6027 06:55:32.966417 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6028 06:55:32.972872 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6029 06:55:32.979348 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6030 06:55:32.979874
6031 06:55:32.980211
6032 06:55:32.982772 [Calibration Summary] 1866 Mbps
6033 06:55:32.983320 CH 0, Rank 0
6034 06:55:32.986176 SW Impedance : PASS
6035 06:55:32.989233 DUTY Scan : NO K
6036 06:55:32.989829 ZQ Calibration : PASS
6037 06:55:32.992433 Jitter Meter : NO K
6038 06:55:32.996020 CBT Training : PASS
6039 06:55:32.996608 Write leveling : PASS
6040 06:55:32.999096 RX DQS gating : PASS
6041 06:55:33.002313 RX DQ/DQS(RDDQC) : PASS
6042 06:55:33.002749 TX DQ/DQS : PASS
6043 06:55:33.006017 RX DATLAT : PASS
6044 06:55:33.009230 RX DQ/DQS(Engine): PASS
6045 06:55:33.009891 TX OE : NO K
6046 06:55:33.010343 All Pass.
6047 06:55:33.012896
6048 06:55:33.013429 CH 0, Rank 1
6049 06:55:33.016019 SW Impedance : PASS
6050 06:55:33.016559 DUTY Scan : NO K
6051 06:55:33.019339 ZQ Calibration : PASS
6052 06:55:33.019881 Jitter Meter : NO K
6053 06:55:33.022596 CBT Training : PASS
6054 06:55:33.025889 Write leveling : PASS
6055 06:55:33.026429 RX DQS gating : PASS
6056 06:55:33.029519 RX DQ/DQS(RDDQC) : PASS
6057 06:55:33.032940 TX DQ/DQS : PASS
6058 06:55:33.033522 RX DATLAT : PASS
6059 06:55:33.035780 RX DQ/DQS(Engine): PASS
6060 06:55:33.039355 TX OE : NO K
6061 06:55:33.039903 All Pass.
6062 06:55:33.040352
6063 06:55:33.040767 CH 1, Rank 0
6064 06:55:33.042279 SW Impedance : PASS
6065 06:55:33.045744 DUTY Scan : NO K
6066 06:55:33.046291 ZQ Calibration : PASS
6067 06:55:33.048808 Jitter Meter : NO K
6068 06:55:33.052066 CBT Training : PASS
6069 06:55:33.052502 Write leveling : PASS
6070 06:55:33.055580 RX DQS gating : PASS
6071 06:55:33.058940 RX DQ/DQS(RDDQC) : PASS
6072 06:55:33.059480 TX DQ/DQS : PASS
6073 06:55:33.062323 RX DATLAT : PASS
6074 06:55:33.065519 RX DQ/DQS(Engine): PASS
6075 06:55:33.065959 TX OE : NO K
6076 06:55:33.068770 All Pass.
6077 06:55:33.069309
6078 06:55:33.069795 CH 1, Rank 1
6079 06:55:33.072217 SW Impedance : PASS
6080 06:55:33.072766 DUTY Scan : NO K
6081 06:55:33.075539 ZQ Calibration : PASS
6082 06:55:33.078883 Jitter Meter : NO K
6083 06:55:33.079424 CBT Training : PASS
6084 06:55:33.081915 Write leveling : PASS
6085 06:55:33.082452 RX DQS gating : PASS
6086 06:55:33.085216 RX DQ/DQS(RDDQC) : PASS
6087 06:55:33.088850 TX DQ/DQS : PASS
6088 06:55:33.089406 RX DATLAT : PASS
6089 06:55:33.091961 RX DQ/DQS(Engine): PASS
6090 06:55:33.095176 TX OE : NO K
6091 06:55:33.095719 All Pass.
6092 06:55:33.096168
6093 06:55:33.098307 DramC Write-DBI off
6094 06:55:33.098742 PER_BANK_REFRESH: Hybrid Mode
6095 06:55:33.101619 TX_TRACKING: ON
6096 06:55:33.111883 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6097 06:55:33.114803 [FAST_K] Save calibration result to emmc
6098 06:55:33.118230 dramc_set_vcore_voltage set vcore to 650000
6099 06:55:33.121420 Read voltage for 400, 6
6100 06:55:33.121885 Vio18 = 0
6101 06:55:33.122226 Vcore = 650000
6102 06:55:33.124772 Vdram = 0
6103 06:55:33.125294 Vddq = 0
6104 06:55:33.125691 Vmddr = 0
6105 06:55:33.131934 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6106 06:55:33.134902 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6107 06:55:33.138283 MEM_TYPE=3, freq_sel=20
6108 06:55:33.141472 sv_algorithm_assistance_LP4_800
6109 06:55:33.144975 ============ PULL DRAM RESETB DOWN ============
6110 06:55:33.148241 ========== PULL DRAM RESETB DOWN end =========
6111 06:55:33.154647 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6112 06:55:33.158067 ===================================
6113 06:55:33.158620 LPDDR4 DRAM CONFIGURATION
6114 06:55:33.161438 ===================================
6115 06:55:33.164909 EX_ROW_EN[0] = 0x0
6116 06:55:33.168158 EX_ROW_EN[1] = 0x0
6117 06:55:33.168703 LP4Y_EN = 0x0
6118 06:55:33.171339 WORK_FSP = 0x0
6119 06:55:33.171775 WL = 0x2
6120 06:55:33.174380 RL = 0x2
6121 06:55:33.174925 BL = 0x2
6122 06:55:33.177951 RPST = 0x0
6123 06:55:33.178492 RD_PRE = 0x0
6124 06:55:33.180733 WR_PRE = 0x1
6125 06:55:33.181163 WR_PST = 0x0
6126 06:55:33.184366 DBI_WR = 0x0
6127 06:55:33.184918 DBI_RD = 0x0
6128 06:55:33.187687 OTF = 0x1
6129 06:55:33.191230 ===================================
6130 06:55:33.194279 ===================================
6131 06:55:33.194818 ANA top config
6132 06:55:33.197576 ===================================
6133 06:55:33.200807 DLL_ASYNC_EN = 0
6134 06:55:33.204446 ALL_SLAVE_EN = 1
6135 06:55:33.207152 NEW_RANK_MODE = 1
6136 06:55:33.207607 DLL_IDLE_MODE = 1
6137 06:55:33.210562 LP45_APHY_COMB_EN = 1
6138 06:55:33.213879 TX_ODT_DIS = 1
6139 06:55:33.217413 NEW_8X_MODE = 1
6140 06:55:33.220809 ===================================
6141 06:55:33.224277 ===================================
6142 06:55:33.227537 data_rate = 800
6143 06:55:33.228081 CKR = 1
6144 06:55:33.230925 DQ_P2S_RATIO = 4
6145 06:55:33.234124 ===================================
6146 06:55:33.237225 CA_P2S_RATIO = 4
6147 06:55:33.240668 DQ_CA_OPEN = 0
6148 06:55:33.244196 DQ_SEMI_OPEN = 1
6149 06:55:33.247237 CA_SEMI_OPEN = 1
6150 06:55:33.247777 CA_FULL_RATE = 0
6151 06:55:33.250265 DQ_CKDIV4_EN = 0
6152 06:55:33.254064 CA_CKDIV4_EN = 1
6153 06:55:33.257058 CA_PREDIV_EN = 0
6154 06:55:33.260190 PH8_DLY = 0
6155 06:55:33.263753 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6156 06:55:33.264296 DQ_AAMCK_DIV = 0
6157 06:55:33.266978 CA_AAMCK_DIV = 0
6158 06:55:33.270138 CA_ADMCK_DIV = 4
6159 06:55:33.273596 DQ_TRACK_CA_EN = 0
6160 06:55:33.276982 CA_PICK = 800
6161 06:55:33.280243 CA_MCKIO = 400
6162 06:55:33.283823 MCKIO_SEMI = 400
6163 06:55:33.286887 PLL_FREQ = 3016
6164 06:55:33.287431 DQ_UI_PI_RATIO = 32
6165 06:55:33.290218 CA_UI_PI_RATIO = 32
6166 06:55:33.293584 ===================================
6167 06:55:33.297223 ===================================
6168 06:55:33.300043 memory_type:LPDDR4
6169 06:55:33.303232 GP_NUM : 10
6170 06:55:33.303672 SRAM_EN : 1
6171 06:55:33.306463 MD32_EN : 0
6172 06:55:33.309596 ===================================
6173 06:55:33.313272 [ANA_INIT] >>>>>>>>>>>>>>
6174 06:55:33.313854 <<<<<< [CONFIGURE PHASE]: ANA_TX
6175 06:55:33.316209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6176 06:55:33.319405 ===================================
6177 06:55:33.323200 data_rate = 800,PCW = 0X7400
6178 06:55:33.326251 ===================================
6179 06:55:33.329761 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6180 06:55:33.336263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6181 06:55:33.346352 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6182 06:55:33.352848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6183 06:55:33.356447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6184 06:55:33.359793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6185 06:55:33.360339 [ANA_INIT] flow start
6186 06:55:33.362815 [ANA_INIT] PLL >>>>>>>>
6187 06:55:33.366188 [ANA_INIT] PLL <<<<<<<<
6188 06:55:33.369770 [ANA_INIT] MIDPI >>>>>>>>
6189 06:55:33.370308 [ANA_INIT] MIDPI <<<<<<<<
6190 06:55:33.372919 [ANA_INIT] DLL >>>>>>>>
6191 06:55:33.373536 [ANA_INIT] flow end
6192 06:55:33.379784 ============ LP4 DIFF to SE enter ============
6193 06:55:33.382972 ============ LP4 DIFF to SE exit ============
6194 06:55:33.386283 [ANA_INIT] <<<<<<<<<<<<<
6195 06:55:33.389638 [Flow] Enable top DCM control >>>>>
6196 06:55:33.393188 [Flow] Enable top DCM control <<<<<
6197 06:55:33.396299 Enable DLL master slave shuffle
6198 06:55:33.399643 ==============================================================
6199 06:55:33.402613 Gating Mode config
6200 06:55:33.405765 ==============================================================
6201 06:55:33.409315 Config description:
6202 06:55:33.419127 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6203 06:55:33.425713 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6204 06:55:33.429423 SELPH_MODE 0: By rank 1: By Phase
6205 06:55:33.435460 ==============================================================
6206 06:55:33.439031 GAT_TRACK_EN = 0
6207 06:55:33.442152 RX_GATING_MODE = 2
6208 06:55:33.445576 RX_GATING_TRACK_MODE = 2
6209 06:55:33.448963 SELPH_MODE = 1
6210 06:55:33.452082 PICG_EARLY_EN = 1
6211 06:55:33.455112 VALID_LAT_VALUE = 1
6212 06:55:33.458927 ==============================================================
6213 06:55:33.462076 Enter into Gating configuration >>>>
6214 06:55:33.465302 Exit from Gating configuration <<<<
6215 06:55:33.468840 Enter into DVFS_PRE_config >>>>>
6216 06:55:33.481834 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6217 06:55:33.482423 Exit from DVFS_PRE_config <<<<<
6218 06:55:33.485283 Enter into PICG configuration >>>>
6219 06:55:33.488502 Exit from PICG configuration <<<<
6220 06:55:33.491608 [RX_INPUT] configuration >>>>>
6221 06:55:33.495218 [RX_INPUT] configuration <<<<<
6222 06:55:33.501545 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6223 06:55:33.504945 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6224 06:55:33.511993 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6225 06:55:33.517977 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6226 06:55:33.524999 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6227 06:55:33.531318 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6228 06:55:33.534908 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6229 06:55:33.537653 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6230 06:55:33.541142 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6231 06:55:33.547991 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6232 06:55:33.551217 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6233 06:55:33.554354 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6234 06:55:33.558231 ===================================
6235 06:55:33.561228 LPDDR4 DRAM CONFIGURATION
6236 06:55:33.564612 ===================================
6237 06:55:33.567884 EX_ROW_EN[0] = 0x0
6238 06:55:33.568424 EX_ROW_EN[1] = 0x0
6239 06:55:33.571035 LP4Y_EN = 0x0
6240 06:55:33.571474 WORK_FSP = 0x0
6241 06:55:33.574354 WL = 0x2
6242 06:55:33.574835 RL = 0x2
6243 06:55:33.577724 BL = 0x2
6244 06:55:33.578256 RPST = 0x0
6245 06:55:33.581165 RD_PRE = 0x0
6246 06:55:33.581753 WR_PRE = 0x1
6247 06:55:33.584279 WR_PST = 0x0
6248 06:55:33.584819 DBI_WR = 0x0
6249 06:55:33.587425 DBI_RD = 0x0
6250 06:55:33.587940 OTF = 0x1
6251 06:55:33.590851 ===================================
6252 06:55:33.597418 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6253 06:55:33.600686 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6254 06:55:33.604052 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6255 06:55:33.607667 ===================================
6256 06:55:33.610765 LPDDR4 DRAM CONFIGURATION
6257 06:55:33.614045 ===================================
6258 06:55:33.617295 EX_ROW_EN[0] = 0x10
6259 06:55:33.617768 EX_ROW_EN[1] = 0x0
6260 06:55:33.620849 LP4Y_EN = 0x0
6261 06:55:33.621387 WORK_FSP = 0x0
6262 06:55:33.624323 WL = 0x2
6263 06:55:33.624861 RL = 0x2
6264 06:55:33.627700 BL = 0x2
6265 06:55:33.628237 RPST = 0x0
6266 06:55:33.630785 RD_PRE = 0x0
6267 06:55:33.631227 WR_PRE = 0x1
6268 06:55:33.633876 WR_PST = 0x0
6269 06:55:33.634418 DBI_WR = 0x0
6270 06:55:33.637579 DBI_RD = 0x0
6271 06:55:33.638114 OTF = 0x1
6272 06:55:33.640561 ===================================
6273 06:55:33.646732 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6274 06:55:33.651841 nWR fixed to 30
6275 06:55:33.655054 [ModeRegInit_LP4] CH0 RK0
6276 06:55:33.655489 [ModeRegInit_LP4] CH0 RK1
6277 06:55:33.658860 [ModeRegInit_LP4] CH1 RK0
6278 06:55:33.661852 [ModeRegInit_LP4] CH1 RK1
6279 06:55:33.662386 match AC timing 19
6280 06:55:33.668601 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6281 06:55:33.671986 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6282 06:55:33.675028 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6283 06:55:33.681608 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6284 06:55:33.685123 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6285 06:55:33.685695 ==
6286 06:55:33.688238 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 06:55:33.691474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 06:55:33.691917 ==
6289 06:55:33.698264 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6290 06:55:33.704781 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6291 06:55:33.708110 [CA 0] Center 36 (8~64) winsize 57
6292 06:55:33.711386 [CA 1] Center 36 (8~64) winsize 57
6293 06:55:33.715352 [CA 2] Center 36 (8~64) winsize 57
6294 06:55:33.718102 [CA 3] Center 36 (8~64) winsize 57
6295 06:55:33.718543 [CA 4] Center 36 (8~64) winsize 57
6296 06:55:33.721539 [CA 5] Center 36 (8~64) winsize 57
6297 06:55:33.721982
6298 06:55:33.727935 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6299 06:55:33.728454
6300 06:55:33.731799 [CATrainingPosCal] consider 1 rank data
6301 06:55:33.734802 u2DelayCellTimex100 = 270/100 ps
6302 06:55:33.738180 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 06:55:33.741643 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 06:55:33.744985 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 06:55:33.748287 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 06:55:33.751526 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 06:55:33.754348 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 06:55:33.754788
6309 06:55:33.758061 CA PerBit enable=1, Macro0, CA PI delay=36
6310 06:55:33.758600
6311 06:55:33.761404 [CBTSetCACLKResult] CA Dly = 36
6312 06:55:33.764505 CS Dly: 1 (0~32)
6313 06:55:33.765040 ==
6314 06:55:33.768197 Dram Type= 6, Freq= 0, CH_0, rank 1
6315 06:55:33.770915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 06:55:33.771358 ==
6317 06:55:33.777779 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6318 06:55:33.784288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6319 06:55:33.788082 [CA 0] Center 36 (8~64) winsize 57
6320 06:55:33.788622 [CA 1] Center 36 (8~64) winsize 57
6321 06:55:33.791175 [CA 2] Center 36 (8~64) winsize 57
6322 06:55:33.794458 [CA 3] Center 36 (8~64) winsize 57
6323 06:55:33.797581 [CA 4] Center 36 (8~64) winsize 57
6324 06:55:33.800910 [CA 5] Center 36 (8~64) winsize 57
6325 06:55:33.801683
6326 06:55:33.804576 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6327 06:55:33.805013
6328 06:55:33.807477 [CATrainingPosCal] consider 2 rank data
6329 06:55:33.810933 u2DelayCellTimex100 = 270/100 ps
6330 06:55:33.814130 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 06:55:33.817594 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 06:55:33.824179 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 06:55:33.827577 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 06:55:33.830669 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 06:55:33.834167 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 06:55:33.834595
6337 06:55:33.837783 CA PerBit enable=1, Macro0, CA PI delay=36
6338 06:55:33.838207
6339 06:55:33.841059 [CBTSetCACLKResult] CA Dly = 36
6340 06:55:33.841520 CS Dly: 1 (0~32)
6341 06:55:33.841872
6342 06:55:33.847441 ----->DramcWriteLeveling(PI) begin...
6343 06:55:33.847873 ==
6344 06:55:33.850750 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 06:55:33.854036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 06:55:33.854464 ==
6347 06:55:33.857362 Write leveling (Byte 0): 40 => 8
6348 06:55:33.860935 Write leveling (Byte 1): 40 => 8
6349 06:55:33.863932 DramcWriteLeveling(PI) end<-----
6350 06:55:33.864404
6351 06:55:33.864836 ==
6352 06:55:33.867331 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 06:55:33.870790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 06:55:33.871223 ==
6355 06:55:33.874276 [Gating] SW mode calibration
6356 06:55:33.880766 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6357 06:55:33.883840 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6358 06:55:33.890766 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6359 06:55:33.893900 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6360 06:55:33.897094 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 06:55:33.903832 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6362 06:55:33.907219 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 06:55:33.910426 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 06:55:33.916874 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6365 06:55:33.920024 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6366 06:55:33.923661 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6367 06:55:33.926644 Total UI for P1: 0, mck2ui 16
6368 06:55:33.929925 best dqsien dly found for B0: ( 0, 14, 24)
6369 06:55:33.933265 Total UI for P1: 0, mck2ui 16
6370 06:55:33.936529 best dqsien dly found for B1: ( 0, 14, 24)
6371 06:55:33.940291 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6372 06:55:33.946694 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6373 06:55:33.946996
6374 06:55:33.950079 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6375 06:55:33.953251 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6376 06:55:33.956973 [Gating] SW calibration Done
6377 06:55:33.957291 ==
6378 06:55:33.960277 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 06:55:33.963056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 06:55:33.963335 ==
6381 06:55:33.966839 RX Vref Scan: 0
6382 06:55:33.967216
6383 06:55:33.967445 RX Vref 0 -> 0, step: 1
6384 06:55:33.967645
6385 06:55:33.969749 RX Delay -410 -> 252, step: 16
6386 06:55:33.973438 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6387 06:55:33.979688 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6388 06:55:33.983335 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6389 06:55:33.986229 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6390 06:55:33.989996 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6391 06:55:33.996768 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6392 06:55:33.999766 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6393 06:55:34.003142 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6394 06:55:34.006633 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6395 06:55:34.013277 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6396 06:55:34.016429 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6397 06:55:34.019771 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6398 06:55:34.026434 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6399 06:55:34.029459 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6400 06:55:34.033064 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6401 06:55:34.036493 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6402 06:55:34.037018 ==
6403 06:55:34.039692 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 06:55:34.046365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 06:55:34.046891 ==
6406 06:55:34.047225 DQS Delay:
6407 06:55:34.049643 DQS0 = 59, DQS1 = 59
6408 06:55:34.050178 DQM Delay:
6409 06:55:34.052738 DQM0 = 18, DQM1 = 10
6410 06:55:34.053155 DQ Delay:
6411 06:55:34.056236 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6412 06:55:34.059608 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6413 06:55:34.062885 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6414 06:55:34.066305 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6415 06:55:34.066827
6416 06:55:34.067158
6417 06:55:34.067462 ==
6418 06:55:34.069411 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 06:55:34.073015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 06:55:34.073586 ==
6421 06:55:34.073931
6422 06:55:34.074241
6423 06:55:34.076046 TX Vref Scan disable
6424 06:55:34.076569 == TX Byte 0 ==
6425 06:55:34.082471 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6426 06:55:34.085613 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6427 06:55:34.086240 == TX Byte 1 ==
6428 06:55:34.092874 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6429 06:55:34.096019 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6430 06:55:34.096564 ==
6431 06:55:34.099371 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 06:55:34.102379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 06:55:34.102818 ==
6434 06:55:34.103260
6435 06:55:34.103669
6436 06:55:34.105938 TX Vref Scan disable
6437 06:55:34.106361 == TX Byte 0 ==
6438 06:55:34.112480 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6439 06:55:34.116252 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6440 06:55:34.116781 == TX Byte 1 ==
6441 06:55:34.122289 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6442 06:55:34.125721 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6443 06:55:34.126262
6444 06:55:34.126707 [DATLAT]
6445 06:55:34.129167 Freq=400, CH0 RK0
6446 06:55:34.129764
6447 06:55:34.130210 DATLAT Default: 0xf
6448 06:55:34.132968 0, 0xFFFF, sum = 0
6449 06:55:34.133577 1, 0xFFFF, sum = 0
6450 06:55:34.135841 2, 0xFFFF, sum = 0
6451 06:55:34.136385 3, 0xFFFF, sum = 0
6452 06:55:34.139330 4, 0xFFFF, sum = 0
6453 06:55:34.139875 5, 0xFFFF, sum = 0
6454 06:55:34.142359 6, 0xFFFF, sum = 0
6455 06:55:34.142800 7, 0xFFFF, sum = 0
6456 06:55:34.145962 8, 0xFFFF, sum = 0
6457 06:55:34.146514 9, 0xFFFF, sum = 0
6458 06:55:34.149325 10, 0xFFFF, sum = 0
6459 06:55:34.149928 11, 0xFFFF, sum = 0
6460 06:55:34.152316 12, 0xFFFF, sum = 0
6461 06:55:34.155870 13, 0x0, sum = 1
6462 06:55:34.156417 14, 0x0, sum = 2
6463 06:55:34.156871 15, 0x0, sum = 3
6464 06:55:34.159271 16, 0x0, sum = 4
6465 06:55:34.159833 best_step = 14
6466 06:55:34.160286
6467 06:55:34.162303 ==
6468 06:55:34.162738 Dram Type= 6, Freq= 0, CH_0, rank 0
6469 06:55:34.169454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 06:55:34.170042 ==
6471 06:55:34.170491 RX Vref Scan: 1
6472 06:55:34.170905
6473 06:55:34.172328 RX Vref 0 -> 0, step: 1
6474 06:55:34.172762
6475 06:55:34.175980 RX Delay -359 -> 252, step: 8
6476 06:55:34.176527
6477 06:55:34.179262 Set Vref, RX VrefLevel [Byte0]: 61
6478 06:55:34.182361 [Byte1]: 57
6479 06:55:34.185691
6480 06:55:34.186233 Final RX Vref Byte 0 = 61 to rank0
6481 06:55:34.189207 Final RX Vref Byte 1 = 57 to rank0
6482 06:55:34.192518 Final RX Vref Byte 0 = 61 to rank1
6483 06:55:34.195758 Final RX Vref Byte 1 = 57 to rank1==
6484 06:55:34.198986 Dram Type= 6, Freq= 0, CH_0, rank 0
6485 06:55:34.205612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 06:55:34.206342 ==
6487 06:55:34.206774 DQS Delay:
6488 06:55:34.209029 DQS0 = 60, DQS1 = 68
6489 06:55:34.209610 DQM Delay:
6490 06:55:34.209956 DQM0 = 14, DQM1 = 14
6491 06:55:34.211821 DQ Delay:
6492 06:55:34.215566 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6493 06:55:34.218601 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6494 06:55:34.219027 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6495 06:55:34.222050 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6496 06:55:34.225323
6497 06:55:34.225771
6498 06:55:34.231926 [DQSOSCAuto] RK0, (LSB)MR18= 0x817f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6499 06:55:34.235610 CH0 RK0: MR19=C0C, MR18=817F
6500 06:55:34.242179 CH0_RK0: MR19=0xC0C, MR18=0x817F, DQSOSC=393, MR23=63, INC=382, DEC=254
6501 06:55:34.242740 ==
6502 06:55:34.245684 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 06:55:34.248615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 06:55:34.249142 ==
6505 06:55:34.251977 [Gating] SW mode calibration
6506 06:55:34.258604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6507 06:55:34.265065 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6508 06:55:34.268832 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6509 06:55:34.271567 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6510 06:55:34.278353 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 06:55:34.281913 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6512 06:55:34.285285 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 06:55:34.291768 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 06:55:34.295550 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 06:55:34.298411 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6516 06:55:34.304967 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6517 06:55:34.305539 Total UI for P1: 0, mck2ui 16
6518 06:55:34.311362 best dqsien dly found for B0: ( 0, 14, 24)
6519 06:55:34.311962 Total UI for P1: 0, mck2ui 16
6520 06:55:34.317962 best dqsien dly found for B1: ( 0, 14, 24)
6521 06:55:34.321469 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6522 06:55:34.324777 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6523 06:55:34.325205
6524 06:55:34.327970 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6525 06:55:34.331650 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6526 06:55:34.335082 [Gating] SW calibration Done
6527 06:55:34.335607 ==
6528 06:55:34.337964 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 06:55:34.341391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 06:55:34.341954 ==
6531 06:55:34.344506 RX Vref Scan: 0
6532 06:55:34.344928
6533 06:55:34.345259 RX Vref 0 -> 0, step: 1
6534 06:55:34.345614
6535 06:55:34.348133 RX Delay -410 -> 252, step: 16
6536 06:55:34.354357 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6537 06:55:34.357524 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6538 06:55:34.361017 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6539 06:55:34.364313 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6540 06:55:34.370978 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6541 06:55:34.374136 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6542 06:55:34.377693 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6543 06:55:34.380880 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6544 06:55:34.387890 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6545 06:55:34.391201 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6546 06:55:34.394216 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6547 06:55:34.397773 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6548 06:55:34.404378 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6549 06:55:34.407268 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6550 06:55:34.410809 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6551 06:55:34.413927 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6552 06:55:34.417722 ==
6553 06:55:34.420970 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 06:55:34.423864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 06:55:34.424394 ==
6556 06:55:34.424730 DQS Delay:
6557 06:55:34.427077 DQS0 = 59, DQS1 = 59
6558 06:55:34.427497 DQM Delay:
6559 06:55:34.430940 DQM0 = 18, DQM1 = 10
6560 06:55:34.431467 DQ Delay:
6561 06:55:34.434025 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6562 06:55:34.437370 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6563 06:55:34.440684 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6564 06:55:34.444125 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6565 06:55:34.444650
6566 06:55:34.444985
6567 06:55:34.445291 ==
6568 06:55:34.447150 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 06:55:34.450419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 06:55:34.450845 ==
6571 06:55:34.451178
6572 06:55:34.451612
6573 06:55:34.453683 TX Vref Scan disable
6574 06:55:34.454104 == TX Byte 0 ==
6575 06:55:34.460678 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6576 06:55:34.464066 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6577 06:55:34.464593 == TX Byte 1 ==
6578 06:55:34.470436 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6579 06:55:34.473935 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6580 06:55:34.474465 ==
6581 06:55:34.477397 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 06:55:34.480611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 06:55:34.481145 ==
6584 06:55:34.481511
6585 06:55:34.481831
6586 06:55:34.484094 TX Vref Scan disable
6587 06:55:34.487043 == TX Byte 0 ==
6588 06:55:34.490310 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6589 06:55:34.493615 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6590 06:55:34.494149 == TX Byte 1 ==
6591 06:55:34.500112 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6592 06:55:34.503687 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6593 06:55:34.504218
6594 06:55:34.504552 [DATLAT]
6595 06:55:34.506961 Freq=400, CH0 RK1
6596 06:55:34.507388
6597 06:55:34.507845 DATLAT Default: 0xe
6598 06:55:34.510079 0, 0xFFFF, sum = 0
6599 06:55:34.510509 1, 0xFFFF, sum = 0
6600 06:55:34.513353 2, 0xFFFF, sum = 0
6601 06:55:34.513844 3, 0xFFFF, sum = 0
6602 06:55:34.517113 4, 0xFFFF, sum = 0
6603 06:55:34.520242 5, 0xFFFF, sum = 0
6604 06:55:34.520768 6, 0xFFFF, sum = 0
6605 06:55:34.523247 7, 0xFFFF, sum = 0
6606 06:55:34.523674 8, 0xFFFF, sum = 0
6607 06:55:34.526767 9, 0xFFFF, sum = 0
6608 06:55:34.527295 10, 0xFFFF, sum = 0
6609 06:55:34.529973 11, 0xFFFF, sum = 0
6610 06:55:34.530402 12, 0xFFFF, sum = 0
6611 06:55:34.533246 13, 0x0, sum = 1
6612 06:55:34.533774 14, 0x0, sum = 2
6613 06:55:34.536286 15, 0x0, sum = 3
6614 06:55:34.536711 16, 0x0, sum = 4
6615 06:55:34.539975 best_step = 14
6616 06:55:34.540397
6617 06:55:34.540729 ==
6618 06:55:34.543366 Dram Type= 6, Freq= 0, CH_0, rank 1
6619 06:55:34.546253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 06:55:34.546685 ==
6621 06:55:34.547021 RX Vref Scan: 0
6622 06:55:34.547333
6623 06:55:34.549977 RX Vref 0 -> 0, step: 1
6624 06:55:34.550535
6625 06:55:34.553621 RX Delay -359 -> 252, step: 8
6626 06:55:34.560717 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6627 06:55:34.564087 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6628 06:55:34.567111 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6629 06:55:34.570987 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6630 06:55:34.577639 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6631 06:55:34.580472 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6632 06:55:34.584165 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6633 06:55:34.587601 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6634 06:55:34.593853 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6635 06:55:34.596820 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6636 06:55:34.600570 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6637 06:55:34.603672 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6638 06:55:34.610214 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6639 06:55:34.613582 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6640 06:55:34.617093 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6641 06:55:34.623762 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6642 06:55:34.624299 ==
6643 06:55:34.626968 Dram Type= 6, Freq= 0, CH_0, rank 1
6644 06:55:34.630486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 06:55:34.631021 ==
6646 06:55:34.631360 DQS Delay:
6647 06:55:34.633461 DQS0 = 60, DQS1 = 68
6648 06:55:34.633924 DQM Delay:
6649 06:55:34.637148 DQM0 = 12, DQM1 = 14
6650 06:55:34.637718 DQ Delay:
6651 06:55:34.640158 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6652 06:55:34.643694 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6653 06:55:34.646817 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6654 06:55:34.650208 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6655 06:55:34.650632
6656 06:55:34.650962
6657 06:55:34.656377 [DQSOSCAuto] RK1, (LSB)MR18= 0xc87e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6658 06:55:34.660520 CH0 RK1: MR19=C0C, MR18=C87E
6659 06:55:34.666716 CH0_RK1: MR19=0xC0C, MR18=0xC87E, DQSOSC=385, MR23=63, INC=398, DEC=265
6660 06:55:34.670398 [RxdqsGatingPostProcess] freq 400
6661 06:55:34.676660 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6662 06:55:34.680018 best DQS0 dly(2T, 0.5T) = (0, 10)
6663 06:55:34.680549 best DQS1 dly(2T, 0.5T) = (0, 10)
6664 06:55:34.683306 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6665 06:55:34.686485 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6666 06:55:34.690105 best DQS0 dly(2T, 0.5T) = (0, 10)
6667 06:55:34.693257 best DQS1 dly(2T, 0.5T) = (0, 10)
6668 06:55:34.696269 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6669 06:55:34.699943 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6670 06:55:34.702979 Pre-setting of DQS Precalculation
6671 06:55:34.709352 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6672 06:55:34.709917 ==
6673 06:55:34.713081 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 06:55:34.716202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 06:55:34.716728 ==
6676 06:55:34.722685 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6677 06:55:34.726297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6678 06:55:34.729558 [CA 0] Center 36 (8~64) winsize 57
6679 06:55:34.732937 [CA 1] Center 36 (8~64) winsize 57
6680 06:55:34.736078 [CA 2] Center 36 (8~64) winsize 57
6681 06:55:34.739070 [CA 3] Center 36 (8~64) winsize 57
6682 06:55:34.742723 [CA 4] Center 36 (8~64) winsize 57
6683 06:55:34.746286 [CA 5] Center 36 (8~64) winsize 57
6684 06:55:34.746832
6685 06:55:34.749174 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6686 06:55:34.749641
6687 06:55:34.752363 [CATrainingPosCal] consider 1 rank data
6688 06:55:34.755893 u2DelayCellTimex100 = 270/100 ps
6689 06:55:34.759196 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 06:55:34.762451 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 06:55:34.768887 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 06:55:34.772274 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 06:55:34.776273 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 06:55:34.779417 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 06:55:34.779949
6696 06:55:34.782774 CA PerBit enable=1, Macro0, CA PI delay=36
6697 06:55:34.783336
6698 06:55:34.785755 [CBTSetCACLKResult] CA Dly = 36
6699 06:55:34.786185 CS Dly: 1 (0~32)
6700 06:55:34.788839 ==
6701 06:55:34.789268 Dram Type= 6, Freq= 0, CH_1, rank 1
6702 06:55:34.795506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 06:55:34.796022 ==
6704 06:55:34.798999 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6705 06:55:34.805702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6706 06:55:34.809143 [CA 0] Center 36 (8~64) winsize 57
6707 06:55:34.812060 [CA 1] Center 36 (8~64) winsize 57
6708 06:55:34.815225 [CA 2] Center 36 (8~64) winsize 57
6709 06:55:34.818474 [CA 3] Center 36 (8~64) winsize 57
6710 06:55:34.822173 [CA 4] Center 36 (8~64) winsize 57
6711 06:55:34.825593 [CA 5] Center 36 (8~64) winsize 57
6712 06:55:34.826114
6713 06:55:34.828733 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6714 06:55:34.829264
6715 06:55:34.832039 [CATrainingPosCal] consider 2 rank data
6716 06:55:34.835600 u2DelayCellTimex100 = 270/100 ps
6717 06:55:34.838634 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 06:55:34.842075 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 06:55:34.845378 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 06:55:34.848928 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 06:55:34.855175 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 06:55:34.858302 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 06:55:34.858732
6724 06:55:34.862135 CA PerBit enable=1, Macro0, CA PI delay=36
6725 06:55:34.862666
6726 06:55:34.865102 [CBTSetCACLKResult] CA Dly = 36
6727 06:55:34.865565 CS Dly: 1 (0~32)
6728 06:55:34.865909
6729 06:55:34.868364 ----->DramcWriteLeveling(PI) begin...
6730 06:55:34.868800 ==
6731 06:55:34.871794 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 06:55:34.878490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 06:55:34.879019 ==
6734 06:55:34.881850 Write leveling (Byte 0): 40 => 8
6735 06:55:34.882406 Write leveling (Byte 1): 40 => 8
6736 06:55:34.884901 DramcWriteLeveling(PI) end<-----
6737 06:55:34.885330
6738 06:55:34.888224 ==
6739 06:55:34.888748 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 06:55:34.895205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 06:55:34.895734 ==
6742 06:55:34.898312 [Gating] SW mode calibration
6743 06:55:34.904814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6744 06:55:34.908133 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6745 06:55:34.914566 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6746 06:55:34.918246 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6747 06:55:34.921440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 06:55:34.928405 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6749 06:55:34.931505 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 06:55:34.935195 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 06:55:34.941356 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6752 06:55:34.944857 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6753 06:55:34.948105 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6754 06:55:34.951286 Total UI for P1: 0, mck2ui 16
6755 06:55:34.954722 best dqsien dly found for B0: ( 0, 14, 24)
6756 06:55:34.957875 Total UI for P1: 0, mck2ui 16
6757 06:55:34.961445 best dqsien dly found for B1: ( 0, 14, 24)
6758 06:55:34.964114 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6759 06:55:34.967637 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6760 06:55:34.968116
6761 06:55:34.974365 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6762 06:55:34.977614 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6763 06:55:34.978211 [Gating] SW calibration Done
6764 06:55:34.980778 ==
6765 06:55:34.984263 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 06:55:34.987482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 06:55:34.987927 ==
6768 06:55:34.988276 RX Vref Scan: 0
6769 06:55:34.988585
6770 06:55:34.991024 RX Vref 0 -> 0, step: 1
6771 06:55:34.991449
6772 06:55:34.994064 RX Delay -410 -> 252, step: 16
6773 06:55:34.997197 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6774 06:55:35.003958 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6775 06:55:35.007297 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6776 06:55:35.010731 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6777 06:55:35.014037 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6778 06:55:35.020727 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6779 06:55:35.024363 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6780 06:55:35.027603 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6781 06:55:35.030908 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6782 06:55:35.037225 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6783 06:55:35.040590 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6784 06:55:35.044429 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6785 06:55:35.047071 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6786 06:55:35.053619 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6787 06:55:35.056913 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6788 06:55:35.060421 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6789 06:55:35.060856 ==
6790 06:55:35.063982 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 06:55:35.066913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 06:55:35.070423 ==
6793 06:55:35.070949 DQS Delay:
6794 06:55:35.071291 DQS0 = 51, DQS1 = 67
6795 06:55:35.073454 DQM Delay:
6796 06:55:35.073951 DQM0 = 13, DQM1 = 17
6797 06:55:35.077412 DQ Delay:
6798 06:55:35.077982 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6799 06:55:35.080452 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6800 06:55:35.084013 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6801 06:55:35.086877 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6802 06:55:35.087310
6803 06:55:35.087646
6804 06:55:35.090451 ==
6805 06:55:35.093928 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 06:55:35.097226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 06:55:35.097796 ==
6808 06:55:35.098144
6809 06:55:35.098466
6810 06:55:35.100133 TX Vref Scan disable
6811 06:55:35.100564 == TX Byte 0 ==
6812 06:55:35.103507 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6813 06:55:35.110122 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6814 06:55:35.110633 == TX Byte 1 ==
6815 06:55:35.113363 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6816 06:55:35.119926 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6817 06:55:35.120440 ==
6818 06:55:35.123150 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 06:55:35.126988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 06:55:35.127578 ==
6821 06:55:35.128086
6822 06:55:35.128427
6823 06:55:35.130034 TX Vref Scan disable
6824 06:55:35.130466 == TX Byte 0 ==
6825 06:55:35.133468 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6826 06:55:35.139880 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6827 06:55:35.140388 == TX Byte 1 ==
6828 06:55:35.143591 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6829 06:55:35.150098 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6830 06:55:35.150667
6831 06:55:35.151009 [DATLAT]
6832 06:55:35.151318 Freq=400, CH1 RK0
6833 06:55:35.151617
6834 06:55:35.153230 DATLAT Default: 0xf
6835 06:55:35.156552 0, 0xFFFF, sum = 0
6836 06:55:35.157083 1, 0xFFFF, sum = 0
6837 06:55:35.160217 2, 0xFFFF, sum = 0
6838 06:55:35.160744 3, 0xFFFF, sum = 0
6839 06:55:35.163705 4, 0xFFFF, sum = 0
6840 06:55:35.164238 5, 0xFFFF, sum = 0
6841 06:55:35.166270 6, 0xFFFF, sum = 0
6842 06:55:35.166736 7, 0xFFFF, sum = 0
6843 06:55:35.170024 8, 0xFFFF, sum = 0
6844 06:55:35.170558 9, 0xFFFF, sum = 0
6845 06:55:35.173003 10, 0xFFFF, sum = 0
6846 06:55:35.173432 11, 0xFFFF, sum = 0
6847 06:55:35.176372 12, 0xFFFF, sum = 0
6848 06:55:35.176840 13, 0x0, sum = 1
6849 06:55:35.180150 14, 0x0, sum = 2
6850 06:55:35.180684 15, 0x0, sum = 3
6851 06:55:35.183306 16, 0x0, sum = 4
6852 06:55:35.183835 best_step = 14
6853 06:55:35.184169
6854 06:55:35.184478 ==
6855 06:55:35.186282 Dram Type= 6, Freq= 0, CH_1, rank 0
6856 06:55:35.189909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 06:55:35.192982 ==
6858 06:55:35.193549 RX Vref Scan: 1
6859 06:55:35.193897
6860 06:55:35.196105 RX Vref 0 -> 0, step: 1
6861 06:55:35.196525
6862 06:55:35.199741 RX Delay -375 -> 252, step: 8
6863 06:55:35.200267
6864 06:55:35.203054 Set Vref, RX VrefLevel [Byte0]: 55
6865 06:55:35.206417 [Byte1]: 55
6866 06:55:35.206941
6867 06:55:35.209642 Final RX Vref Byte 0 = 55 to rank0
6868 06:55:35.212447 Final RX Vref Byte 1 = 55 to rank0
6869 06:55:35.216544 Final RX Vref Byte 0 = 55 to rank1
6870 06:55:35.219816 Final RX Vref Byte 1 = 55 to rank1==
6871 06:55:35.222928 Dram Type= 6, Freq= 0, CH_1, rank 0
6872 06:55:35.225762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 06:55:35.229511 ==
6874 06:55:35.230049 DQS Delay:
6875 06:55:35.230410 DQS0 = 52, DQS1 = 64
6876 06:55:35.232682 DQM Delay:
6877 06:55:35.233205 DQM0 = 9, DQM1 = 10
6878 06:55:35.236023 DQ Delay:
6879 06:55:35.236451 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6880 06:55:35.239575 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6881 06:55:35.242694 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6882 06:55:35.246170 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6883 06:55:35.246700
6884 06:55:35.247039
6885 06:55:35.255622 [DQSOSCAuto] RK0, (LSB)MR18= 0x5467, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6886 06:55:35.259098 CH1 RK0: MR19=C0C, MR18=5467
6887 06:55:35.262431 CH1_RK0: MR19=0xC0C, MR18=0x5467, DQSOSC=396, MR23=63, INC=376, DEC=251
6888 06:55:35.265699 ==
6889 06:55:35.269007 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 06:55:35.272620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 06:55:35.273149 ==
6892 06:55:35.275529 [Gating] SW mode calibration
6893 06:55:35.282582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6894 06:55:35.286022 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6895 06:55:35.292586 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6896 06:55:35.295588 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6897 06:55:35.299173 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 06:55:35.305782 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6899 06:55:35.309013 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 06:55:35.311913 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 06:55:35.318947 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6902 06:55:35.322053 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6903 06:55:35.325640 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6904 06:55:35.329110 Total UI for P1: 0, mck2ui 16
6905 06:55:35.332226 best dqsien dly found for B0: ( 0, 14, 24)
6906 06:55:35.335621 Total UI for P1: 0, mck2ui 16
6907 06:55:35.338951 best dqsien dly found for B1: ( 0, 14, 24)
6908 06:55:35.342184 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6909 06:55:35.345679 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6910 06:55:35.346204
6911 06:55:35.352029 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6912 06:55:35.355537 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6913 06:55:35.358752 [Gating] SW calibration Done
6914 06:55:35.359292 ==
6915 06:55:35.361866 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 06:55:35.365899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 06:55:35.366426 ==
6918 06:55:35.366767 RX Vref Scan: 0
6919 06:55:35.367082
6920 06:55:35.368350 RX Vref 0 -> 0, step: 1
6921 06:55:35.368775
6922 06:55:35.372081 RX Delay -410 -> 252, step: 16
6923 06:55:35.375110 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6924 06:55:35.381709 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6925 06:55:35.385581 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6926 06:55:35.388769 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6927 06:55:35.391889 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6928 06:55:35.398372 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6929 06:55:35.401754 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6930 06:55:35.404905 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6931 06:55:35.408229 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6932 06:55:35.411491 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6933 06:55:35.418077 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6934 06:55:35.421744 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6935 06:55:35.425224 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6936 06:55:35.431859 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6937 06:55:35.434635 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6938 06:55:35.438455 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6939 06:55:35.439002 ==
6940 06:55:35.441638 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 06:55:35.444987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 06:55:35.448413 ==
6943 06:55:35.448951 DQS Delay:
6944 06:55:35.449470 DQS0 = 59, DQS1 = 59
6945 06:55:35.451384 DQM Delay:
6946 06:55:35.451818 DQM0 = 19, DQM1 = 13
6947 06:55:35.454875 DQ Delay:
6948 06:55:35.458406 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6949 06:55:35.458977 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6950 06:55:35.461338 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6951 06:55:35.464826 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6952 06:55:35.465365
6953 06:55:35.467843
6954 06:55:35.468276 ==
6955 06:55:35.471571 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 06:55:35.474410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 06:55:35.474853 ==
6958 06:55:35.475300
6959 06:55:35.475719
6960 06:55:35.477804 TX Vref Scan disable
6961 06:55:35.478243 == TX Byte 0 ==
6962 06:55:35.481570 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6963 06:55:35.487857 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6964 06:55:35.488401 == TX Byte 1 ==
6965 06:55:35.490849 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6966 06:55:35.497999 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6967 06:55:35.498543 ==
6968 06:55:35.501359 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 06:55:35.504737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 06:55:35.505277 ==
6971 06:55:35.505790
6972 06:55:35.506209
6973 06:55:35.507797 TX Vref Scan disable
6974 06:55:35.508236 == TX Byte 0 ==
6975 06:55:35.511059 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6976 06:55:35.517450 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6977 06:55:35.517926 == TX Byte 1 ==
6978 06:55:35.520830 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6979 06:55:35.527206 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6980 06:55:35.527726
6981 06:55:35.528171 [DATLAT]
6982 06:55:35.528587 Freq=400, CH1 RK1
6983 06:55:35.530695
6984 06:55:35.531130 DATLAT Default: 0xe
6985 06:55:35.533942 0, 0xFFFF, sum = 0
6986 06:55:35.534390 1, 0xFFFF, sum = 0
6987 06:55:35.537222 2, 0xFFFF, sum = 0
6988 06:55:35.537774 3, 0xFFFF, sum = 0
6989 06:55:35.540747 4, 0xFFFF, sum = 0
6990 06:55:35.541321 5, 0xFFFF, sum = 0
6991 06:55:35.544148 6, 0xFFFF, sum = 0
6992 06:55:35.544689 7, 0xFFFF, sum = 0
6993 06:55:35.547569 8, 0xFFFF, sum = 0
6994 06:55:35.548115 9, 0xFFFF, sum = 0
6995 06:55:35.550832 10, 0xFFFF, sum = 0
6996 06:55:35.551279 11, 0xFFFF, sum = 0
6997 06:55:35.553809 12, 0xFFFF, sum = 0
6998 06:55:35.554252 13, 0x0, sum = 1
6999 06:55:35.557375 14, 0x0, sum = 2
7000 06:55:35.557865 15, 0x0, sum = 3
7001 06:55:35.561033 16, 0x0, sum = 4
7002 06:55:35.561639 best_step = 14
7003 06:55:35.562090
7004 06:55:35.562509 ==
7005 06:55:35.564096 Dram Type= 6, Freq= 0, CH_1, rank 1
7006 06:55:35.570991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7007 06:55:35.571534 ==
7008 06:55:35.571988 RX Vref Scan: 0
7009 06:55:35.572407
7010 06:55:35.574183 RX Vref 0 -> 0, step: 1
7011 06:55:35.574623
7012 06:55:35.577170 RX Delay -359 -> 252, step: 8
7013 06:55:35.584219 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7014 06:55:35.587146 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7015 06:55:35.590664 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7016 06:55:35.593912 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7017 06:55:35.600997 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7018 06:55:35.604187 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7019 06:55:35.607038 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7020 06:55:35.610876 iDelay=217, Bit 7, Center -48 (-295 ~ 200) 496
7021 06:55:35.616906 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7022 06:55:35.620726 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7023 06:55:35.623746 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7024 06:55:35.626988 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
7025 06:55:35.633934 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7026 06:55:35.636981 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7027 06:55:35.640349 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7028 06:55:35.646795 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7029 06:55:35.647340 ==
7030 06:55:35.650129 Dram Type= 6, Freq= 0, CH_1, rank 1
7031 06:55:35.653849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7032 06:55:35.654435 ==
7033 06:55:35.654891 DQS Delay:
7034 06:55:35.656665 DQS0 = 60, DQS1 = 64
7035 06:55:35.657103 DQM Delay:
7036 06:55:35.659782 DQM0 = 13, DQM1 = 10
7037 06:55:35.660222 DQ Delay:
7038 06:55:35.663348 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7039 06:55:35.666519 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7040 06:55:35.669967 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7041 06:55:35.673058 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7042 06:55:35.673519
7043 06:55:35.674066
7044 06:55:35.679999 [DQSOSCAuto] RK1, (LSB)MR18= 0x75a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7045 06:55:35.683065 CH1 RK1: MR19=C0C, MR18=75A5
7046 06:55:35.690086 CH1_RK1: MR19=0xC0C, MR18=0x75A5, DQSOSC=389, MR23=63, INC=390, DEC=260
7047 06:55:35.693730 [RxdqsGatingPostProcess] freq 400
7048 06:55:35.699792 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7049 06:55:35.700328 best DQS0 dly(2T, 0.5T) = (0, 10)
7050 06:55:35.702839 best DQS1 dly(2T, 0.5T) = (0, 10)
7051 06:55:35.706027 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7052 06:55:35.709807 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7053 06:55:35.712920 best DQS0 dly(2T, 0.5T) = (0, 10)
7054 06:55:35.716086 best DQS1 dly(2T, 0.5T) = (0, 10)
7055 06:55:35.719842 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7056 06:55:35.723034 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7057 06:55:35.726064 Pre-setting of DQS Precalculation
7058 06:55:35.733087 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7059 06:55:35.739611 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7060 06:55:35.746139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7061 06:55:35.746680
7062 06:55:35.747130
7063 06:55:35.749304 [Calibration Summary] 800 Mbps
7064 06:55:35.749794 CH 0, Rank 0
7065 06:55:35.752774 SW Impedance : PASS
7066 06:55:35.755980 DUTY Scan : NO K
7067 06:55:35.756574 ZQ Calibration : PASS
7068 06:55:35.759347 Jitter Meter : NO K
7069 06:55:35.762445 CBT Training : PASS
7070 06:55:35.762993 Write leveling : PASS
7071 06:55:35.765743 RX DQS gating : PASS
7072 06:55:35.766182 RX DQ/DQS(RDDQC) : PASS
7073 06:55:35.769138 TX DQ/DQS : PASS
7074 06:55:35.772432 RX DATLAT : PASS
7075 06:55:35.772968 RX DQ/DQS(Engine): PASS
7076 06:55:35.775678 TX OE : NO K
7077 06:55:35.776221 All Pass.
7078 06:55:35.776672
7079 06:55:35.779327 CH 0, Rank 1
7080 06:55:35.779865 SW Impedance : PASS
7081 06:55:35.782014 DUTY Scan : NO K
7082 06:55:35.785641 ZQ Calibration : PASS
7083 06:55:35.786174 Jitter Meter : NO K
7084 06:55:35.788966 CBT Training : PASS
7085 06:55:35.791920 Write leveling : NO K
7086 06:55:35.792482 RX DQS gating : PASS
7087 06:55:35.795627 RX DQ/DQS(RDDQC) : PASS
7088 06:55:35.798871 TX DQ/DQS : PASS
7089 06:55:35.799413 RX DATLAT : PASS
7090 06:55:35.802221 RX DQ/DQS(Engine): PASS
7091 06:55:35.805548 TX OE : NO K
7092 06:55:35.806119 All Pass.
7093 06:55:35.806569
7094 06:55:35.806984 CH 1, Rank 0
7095 06:55:35.808491 SW Impedance : PASS
7096 06:55:35.811770 DUTY Scan : NO K
7097 06:55:35.812213 ZQ Calibration : PASS
7098 06:55:35.815431 Jitter Meter : NO K
7099 06:55:35.818727 CBT Training : PASS
7100 06:55:35.819156 Write leveling : PASS
7101 06:55:35.821964 RX DQS gating : PASS
7102 06:55:35.825231 RX DQ/DQS(RDDQC) : PASS
7103 06:55:35.825804 TX DQ/DQS : PASS
7104 06:55:35.828549 RX DATLAT : PASS
7105 06:55:35.828979 RX DQ/DQS(Engine): PASS
7106 06:55:35.832101 TX OE : NO K
7107 06:55:35.832823 All Pass.
7108 06:55:35.833195
7109 06:55:35.835142 CH 1, Rank 1
7110 06:55:35.835543 SW Impedance : PASS
7111 06:55:35.838688 DUTY Scan : NO K
7112 06:55:35.841994 ZQ Calibration : PASS
7113 06:55:35.842531 Jitter Meter : NO K
7114 06:55:35.845285 CBT Training : PASS
7115 06:55:35.848363 Write leveling : NO K
7116 06:55:35.848795 RX DQS gating : PASS
7117 06:55:35.851767 RX DQ/DQS(RDDQC) : PASS
7118 06:55:35.855083 TX DQ/DQS : PASS
7119 06:55:35.855516 RX DATLAT : PASS
7120 06:55:35.858052 RX DQ/DQS(Engine): PASS
7121 06:55:35.861832 TX OE : NO K
7122 06:55:35.862365 All Pass.
7123 06:55:35.862812
7124 06:55:35.865062 DramC Write-DBI off
7125 06:55:35.865642 PER_BANK_REFRESH: Hybrid Mode
7126 06:55:35.867991 TX_TRACKING: ON
7127 06:55:35.874751 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7128 06:55:35.881605 [FAST_K] Save calibration result to emmc
7129 06:55:35.884888 dramc_set_vcore_voltage set vcore to 725000
7130 06:55:35.885424 Read voltage for 1600, 0
7131 06:55:35.888116 Vio18 = 0
7132 06:55:35.888649 Vcore = 725000
7133 06:55:35.889095 Vdram = 0
7134 06:55:35.891182 Vddq = 0
7135 06:55:35.891647 Vmddr = 0
7136 06:55:35.898185 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7137 06:55:35.901555 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7138 06:55:35.904551 MEM_TYPE=3, freq_sel=13
7139 06:55:35.907751 sv_algorithm_assistance_LP4_3733
7140 06:55:35.911006 ============ PULL DRAM RESETB DOWN ============
7141 06:55:35.914262 ========== PULL DRAM RESETB DOWN end =========
7142 06:55:35.921240 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7143 06:55:35.924044 ===================================
7144 06:55:35.924482 LPDDR4 DRAM CONFIGURATION
7145 06:55:35.927758 ===================================
7146 06:55:35.931010 EX_ROW_EN[0] = 0x0
7147 06:55:35.934281 EX_ROW_EN[1] = 0x0
7148 06:55:35.934721 LP4Y_EN = 0x0
7149 06:55:35.937678 WORK_FSP = 0x1
7150 06:55:35.938214 WL = 0x5
7151 06:55:35.940815 RL = 0x5
7152 06:55:35.941256 BL = 0x2
7153 06:55:35.944376 RPST = 0x0
7154 06:55:35.944918 RD_PRE = 0x0
7155 06:55:35.947725 WR_PRE = 0x1
7156 06:55:35.948281 WR_PST = 0x1
7157 06:55:35.951091 DBI_WR = 0x0
7158 06:55:35.951625 DBI_RD = 0x0
7159 06:55:35.954130 OTF = 0x1
7160 06:55:35.957233 ===================================
7161 06:55:35.960422 ===================================
7162 06:55:35.960862 ANA top config
7163 06:55:35.964229 ===================================
7164 06:55:35.967374 DLL_ASYNC_EN = 0
7165 06:55:35.970394 ALL_SLAVE_EN = 0
7166 06:55:35.974193 NEW_RANK_MODE = 1
7167 06:55:35.974786 DLL_IDLE_MODE = 1
7168 06:55:35.977390 LP45_APHY_COMB_EN = 1
7169 06:55:35.980672 TX_ODT_DIS = 0
7170 06:55:35.983783 NEW_8X_MODE = 1
7171 06:55:35.987256 ===================================
7172 06:55:35.990230 ===================================
7173 06:55:35.993923 data_rate = 3200
7174 06:55:35.994463 CKR = 1
7175 06:55:35.996843 DQ_P2S_RATIO = 8
7176 06:55:36.000641 ===================================
7177 06:55:36.003624 CA_P2S_RATIO = 8
7178 06:55:36.006943 DQ_CA_OPEN = 0
7179 06:55:36.010034 DQ_SEMI_OPEN = 0
7180 06:55:36.013210 CA_SEMI_OPEN = 0
7181 06:55:36.013689 CA_FULL_RATE = 0
7182 06:55:36.017026 DQ_CKDIV4_EN = 0
7183 06:55:36.019858 CA_CKDIV4_EN = 0
7184 06:55:36.023421 CA_PREDIV_EN = 0
7185 06:55:36.026533 PH8_DLY = 12
7186 06:55:36.030110 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7187 06:55:36.030550 DQ_AAMCK_DIV = 4
7188 06:55:36.033402 CA_AAMCK_DIV = 4
7189 06:55:36.036624 CA_ADMCK_DIV = 4
7190 06:55:36.039819 DQ_TRACK_CA_EN = 0
7191 06:55:36.043556 CA_PICK = 1600
7192 06:55:36.046535 CA_MCKIO = 1600
7193 06:55:36.049613 MCKIO_SEMI = 0
7194 06:55:36.053148 PLL_FREQ = 3068
7195 06:55:36.053617 DQ_UI_PI_RATIO = 32
7196 06:55:36.056386 CA_UI_PI_RATIO = 0
7197 06:55:36.059694 ===================================
7198 06:55:36.062769 ===================================
7199 06:55:36.066423 memory_type:LPDDR4
7200 06:55:36.069711 GP_NUM : 10
7201 06:55:36.070169 SRAM_EN : 1
7202 06:55:36.073273 MD32_EN : 0
7203 06:55:36.076600 ===================================
7204 06:55:36.077280 [ANA_INIT] >>>>>>>>>>>>>>
7205 06:55:36.079563 <<<<<< [CONFIGURE PHASE]: ANA_TX
7206 06:55:36.082825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7207 06:55:36.086227 ===================================
7208 06:55:36.089079 data_rate = 3200,PCW = 0X7600
7209 06:55:36.092704 ===================================
7210 06:55:36.096151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7211 06:55:36.102407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7212 06:55:36.109590 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7213 06:55:36.112564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7214 06:55:36.115854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7215 06:55:36.119305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7216 06:55:36.122288 [ANA_INIT] flow start
7217 06:55:36.122726 [ANA_INIT] PLL >>>>>>>>
7218 06:55:36.125763 [ANA_INIT] PLL <<<<<<<<
7219 06:55:36.128992 [ANA_INIT] MIDPI >>>>>>>>
7220 06:55:36.132167 [ANA_INIT] MIDPI <<<<<<<<
7221 06:55:36.132605 [ANA_INIT] DLL >>>>>>>>
7222 06:55:36.135965 [ANA_INIT] DLL <<<<<<<<
7223 06:55:36.136404 [ANA_INIT] flow end
7224 06:55:36.142800 ============ LP4 DIFF to SE enter ============
7225 06:55:36.145352 ============ LP4 DIFF to SE exit ============
7226 06:55:36.149068 [ANA_INIT] <<<<<<<<<<<<<
7227 06:55:36.152231 [Flow] Enable top DCM control >>>>>
7228 06:55:36.155463 [Flow] Enable top DCM control <<<<<
7229 06:55:36.158673 Enable DLL master slave shuffle
7230 06:55:36.161827 ==============================================================
7231 06:55:36.165326 Gating Mode config
7232 06:55:36.168688 ==============================================================
7233 06:55:36.171944 Config description:
7234 06:55:36.181686 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7235 06:55:36.188649 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7236 06:55:36.191992 SELPH_MODE 0: By rank 1: By Phase
7237 06:55:36.198410 ==============================================================
7238 06:55:36.201960 GAT_TRACK_EN = 1
7239 06:55:36.205433 RX_GATING_MODE = 2
7240 06:55:36.208624 RX_GATING_TRACK_MODE = 2
7241 06:55:36.211573 SELPH_MODE = 1
7242 06:55:36.214972 PICG_EARLY_EN = 1
7243 06:55:36.218025 VALID_LAT_VALUE = 1
7244 06:55:36.221695 ==============================================================
7245 06:55:36.225147 Enter into Gating configuration >>>>
7246 06:55:36.228543 Exit from Gating configuration <<<<
7247 06:55:36.231529 Enter into DVFS_PRE_config >>>>>
7248 06:55:36.244799 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7249 06:55:36.245348 Exit from DVFS_PRE_config <<<<<
7250 06:55:36.248202 Enter into PICG configuration >>>>
7251 06:55:36.251621 Exit from PICG configuration <<<<
7252 06:55:36.254652 [RX_INPUT] configuration >>>>>
7253 06:55:36.258180 [RX_INPUT] configuration <<<<<
7254 06:55:36.265151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7255 06:55:36.268119 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7256 06:55:36.274889 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7257 06:55:36.281345 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7258 06:55:36.287661 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7259 06:55:36.294080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7260 06:55:36.297429 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7261 06:55:36.301390 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7262 06:55:36.304440 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7263 06:55:36.310791 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7264 06:55:36.314048 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7265 06:55:36.317434 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7266 06:55:36.320850 ===================================
7267 06:55:36.323888 LPDDR4 DRAM CONFIGURATION
7268 06:55:36.327319 ===================================
7269 06:55:36.330843 EX_ROW_EN[0] = 0x0
7270 06:55:36.331372 EX_ROW_EN[1] = 0x0
7271 06:55:36.333838 LP4Y_EN = 0x0
7272 06:55:36.334406 WORK_FSP = 0x1
7273 06:55:36.337229 WL = 0x5
7274 06:55:36.337787 RL = 0x5
7275 06:55:36.340675 BL = 0x2
7276 06:55:36.341202 RPST = 0x0
7277 06:55:36.343687 RD_PRE = 0x0
7278 06:55:36.344207 WR_PRE = 0x1
7279 06:55:36.347360 WR_PST = 0x1
7280 06:55:36.347890 DBI_WR = 0x0
7281 06:55:36.350471 DBI_RD = 0x0
7282 06:55:36.350997 OTF = 0x1
7283 06:55:36.353861 ===================================
7284 06:55:36.360218 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7285 06:55:36.363439 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7286 06:55:36.367119 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7287 06:55:36.369918 ===================================
7288 06:55:36.373397 LPDDR4 DRAM CONFIGURATION
7289 06:55:36.376690 ===================================
7290 06:55:36.380217 EX_ROW_EN[0] = 0x10
7291 06:55:36.380743 EX_ROW_EN[1] = 0x0
7292 06:55:36.383707 LP4Y_EN = 0x0
7293 06:55:36.384229 WORK_FSP = 0x1
7294 06:55:36.386456 WL = 0x5
7295 06:55:36.386881 RL = 0x5
7296 06:55:36.390025 BL = 0x2
7297 06:55:36.390546 RPST = 0x0
7298 06:55:36.393258 RD_PRE = 0x0
7299 06:55:36.393715 WR_PRE = 0x1
7300 06:55:36.396349 WR_PST = 0x1
7301 06:55:36.396808 DBI_WR = 0x0
7302 06:55:36.400202 DBI_RD = 0x0
7303 06:55:36.400727 OTF = 0x1
7304 06:55:36.403078 ===================================
7305 06:55:36.409940 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7306 06:55:36.410474 ==
7307 06:55:36.413110 Dram Type= 6, Freq= 0, CH_0, rank 0
7308 06:55:36.419656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7309 06:55:36.420172 ==
7310 06:55:36.420510 [Duty_Offset_Calibration]
7311 06:55:36.422825 B0:2 B1:0 CA:3
7312 06:55:36.423246
7313 06:55:36.425992 [DutyScan_Calibration_Flow] k_type=0
7314 06:55:36.435799
7315 06:55:36.436321 ==CLK 0==
7316 06:55:36.439119 Final CLK duty delay cell = 0
7317 06:55:36.442419 [0] MAX Duty = 5031%(X100), DQS PI = 12
7318 06:55:36.446042 [0] MIN Duty = 4875%(X100), DQS PI = 54
7319 06:55:36.446569 [0] AVG Duty = 4953%(X100)
7320 06:55:36.449036
7321 06:55:36.449452 CH0 CLK Duty spec in!! Max-Min= 156%
7322 06:55:36.455860 [DutyScan_Calibration_Flow] ====Done====
7323 06:55:36.456413
7324 06:55:36.459046 [DutyScan_Calibration_Flow] k_type=1
7325 06:55:36.475774
7326 06:55:36.476327 ==DQS 0 ==
7327 06:55:36.479130 Final DQS duty delay cell = 0
7328 06:55:36.482583 [0] MAX Duty = 5125%(X100), DQS PI = 30
7329 06:55:36.485919 [0] MIN Duty = 4875%(X100), DQS PI = 48
7330 06:55:36.489242 [0] AVG Duty = 5000%(X100)
7331 06:55:36.489820
7332 06:55:36.490290 ==DQS 1 ==
7333 06:55:36.491942 Final DQS duty delay cell = 0
7334 06:55:36.495480 [0] MAX Duty = 5156%(X100), DQS PI = 32
7335 06:55:36.498884 [0] MIN Duty = 5031%(X100), DQS PI = 12
7336 06:55:36.502423 [0] AVG Duty = 5093%(X100)
7337 06:55:36.502956
7338 06:55:36.505316 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7339 06:55:36.505779
7340 06:55:36.508502 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7341 06:55:36.511764 [DutyScan_Calibration_Flow] ====Done====
7342 06:55:36.512252
7343 06:55:36.515186 [DutyScan_Calibration_Flow] k_type=3
7344 06:55:36.533038
7345 06:55:36.533615 ==DQM 0 ==
7346 06:55:36.536363 Final DQM duty delay cell = 0
7347 06:55:36.540105 [0] MAX Duty = 5156%(X100), DQS PI = 30
7348 06:55:36.542743 [0] MIN Duty = 4844%(X100), DQS PI = 52
7349 06:55:36.546493 [0] AVG Duty = 5000%(X100)
7350 06:55:36.547032
7351 06:55:36.547481 ==DQM 1 ==
7352 06:55:36.549467 Final DQM duty delay cell = 0
7353 06:55:36.553097 [0] MAX Duty = 4938%(X100), DQS PI = 0
7354 06:55:36.556175 [0] MIN Duty = 4813%(X100), DQS PI = 10
7355 06:55:36.559711 [0] AVG Duty = 4875%(X100)
7356 06:55:36.560249
7357 06:55:36.562914 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7358 06:55:36.563457
7359 06:55:36.565974 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7360 06:55:36.569063 [DutyScan_Calibration_Flow] ====Done====
7361 06:55:36.569609
7362 06:55:36.572433 [DutyScan_Calibration_Flow] k_type=2
7363 06:55:36.589667
7364 06:55:36.590056 ==DQ 0 ==
7365 06:55:36.592870 Final DQ duty delay cell = -4
7366 06:55:36.595931 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7367 06:55:36.599023 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7368 06:55:36.602311 [-4] AVG Duty = 4938%(X100)
7369 06:55:36.602612
7370 06:55:36.602849 ==DQ 1 ==
7371 06:55:36.605996 Final DQ duty delay cell = 0
7372 06:55:36.609082 [0] MAX Duty = 5156%(X100), DQS PI = 60
7373 06:55:36.612324 [0] MIN Duty = 5000%(X100), DQS PI = 16
7374 06:55:36.615634 [0] AVG Duty = 5078%(X100)
7375 06:55:36.615936
7376 06:55:36.618770 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7377 06:55:36.619069
7378 06:55:36.622045 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7379 06:55:36.625346 [DutyScan_Calibration_Flow] ====Done====
7380 06:55:36.625678 ==
7381 06:55:36.629086 Dram Type= 6, Freq= 0, CH_1, rank 0
7382 06:55:36.632093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7383 06:55:36.632514 ==
7384 06:55:36.635659 [Duty_Offset_Calibration]
7385 06:55:36.636080 B0:1 B1:-2 CA:1
7386 06:55:36.636407
7387 06:55:36.639132 [DutyScan_Calibration_Flow] k_type=0
7388 06:55:36.650071
7389 06:55:36.650585 ==CLK 0==
7390 06:55:36.653050 Final CLK duty delay cell = 0
7391 06:55:36.656370 [0] MAX Duty = 5062%(X100), DQS PI = 22
7392 06:55:36.660208 [0] MIN Duty = 4844%(X100), DQS PI = 4
7393 06:55:36.660732 [0] AVG Duty = 4953%(X100)
7394 06:55:36.663442
7395 06:55:36.666427 CH1 CLK Duty spec in!! Max-Min= 218%
7396 06:55:36.669799 [DutyScan_Calibration_Flow] ====Done====
7397 06:55:36.670327
7398 06:55:36.672865 [DutyScan_Calibration_Flow] k_type=1
7399 06:55:36.688948
7400 06:55:36.689605 ==DQS 0 ==
7401 06:55:36.692450 Final DQS duty delay cell = -4
7402 06:55:36.695262 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7403 06:55:36.698760 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7404 06:55:36.702069 [-4] AVG Duty = 4906%(X100)
7405 06:55:36.702588
7406 06:55:36.702920 ==DQS 1 ==
7407 06:55:36.705095 Final DQS duty delay cell = 0
7408 06:55:36.708233 [0] MAX Duty = 5093%(X100), DQS PI = 62
7409 06:55:36.711855 [0] MIN Duty = 4844%(X100), DQS PI = 24
7410 06:55:36.714916 [0] AVG Duty = 4968%(X100)
7411 06:55:36.715337
7412 06:55:36.718602 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7413 06:55:36.719124
7414 06:55:36.721751 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7415 06:55:36.725151 [DutyScan_Calibration_Flow] ====Done====
7416 06:55:36.725613
7417 06:55:36.728305 [DutyScan_Calibration_Flow] k_type=3
7418 06:55:36.746104
7419 06:55:36.746620 ==DQM 0 ==
7420 06:55:36.749344 Final DQM duty delay cell = 0
7421 06:55:36.752513 [0] MAX Duty = 5031%(X100), DQS PI = 24
7422 06:55:36.755831 [0] MIN Duty = 4813%(X100), DQS PI = 56
7423 06:55:36.758997 [0] AVG Duty = 4922%(X100)
7424 06:55:36.759417
7425 06:55:36.759748 ==DQM 1 ==
7426 06:55:36.762664 Final DQM duty delay cell = 0
7427 06:55:36.766092 [0] MAX Duty = 5062%(X100), DQS PI = 34
7428 06:55:36.769320 [0] MIN Duty = 4875%(X100), DQS PI = 26
7429 06:55:36.772754 [0] AVG Duty = 4968%(X100)
7430 06:55:36.773275
7431 06:55:36.775803 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7432 06:55:36.776342
7433 06:55:36.779385 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7434 06:55:36.782536 [DutyScan_Calibration_Flow] ====Done====
7435 06:55:36.783061
7436 06:55:36.785611 [DutyScan_Calibration_Flow] k_type=2
7437 06:55:36.803156
7438 06:55:36.803672 ==DQ 0 ==
7439 06:55:36.806438 Final DQ duty delay cell = 0
7440 06:55:36.809727 [0] MAX Duty = 5093%(X100), DQS PI = 22
7441 06:55:36.813295 [0] MIN Duty = 4907%(X100), DQS PI = 62
7442 06:55:36.813877 [0] AVG Duty = 5000%(X100)
7443 06:55:36.816533
7444 06:55:36.817050 ==DQ 1 ==
7445 06:55:36.819894 Final DQ duty delay cell = 0
7446 06:55:36.823173 [0] MAX Duty = 5156%(X100), DQS PI = 36
7447 06:55:36.826422 [0] MIN Duty = 4938%(X100), DQS PI = 26
7448 06:55:36.826948 [0] AVG Duty = 5047%(X100)
7449 06:55:36.827283
7450 06:55:36.833082 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7451 06:55:36.833719
7452 06:55:36.836388 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7453 06:55:36.838945 [DutyScan_Calibration_Flow] ====Done====
7454 06:55:36.842842 nWR fixed to 30
7455 06:55:36.843261 [ModeRegInit_LP4] CH0 RK0
7456 06:55:36.845906 [ModeRegInit_LP4] CH0 RK1
7457 06:55:36.848869 [ModeRegInit_LP4] CH1 RK0
7458 06:55:36.852510 [ModeRegInit_LP4] CH1 RK1
7459 06:55:36.853031 match AC timing 5
7460 06:55:36.858948 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7461 06:55:36.862201 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7462 06:55:36.865429 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7463 06:55:36.872356 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7464 06:55:36.875724 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7465 06:55:36.876281 [MiockJmeterHQA]
7466 06:55:36.876624
7467 06:55:36.878582 [DramcMiockJmeter] u1RxGatingPI = 0
7468 06:55:36.881986 0 : 4363, 4137
7469 06:55:36.882439 4 : 4363, 4137
7470 06:55:36.884966 8 : 4363, 4137
7471 06:55:36.885611 12 : 4362, 4137
7472 06:55:36.888359 16 : 4365, 4140
7473 06:55:36.888784 20 : 4253, 4027
7474 06:55:36.889123 24 : 4253, 4026
7475 06:55:36.891885 28 : 4252, 4027
7476 06:55:36.892450 32 : 4363, 4137
7477 06:55:36.895104 36 : 4253, 4027
7478 06:55:36.895531 40 : 4363, 4138
7479 06:55:36.898346 44 : 4253, 4026
7480 06:55:36.898808 48 : 4252, 4027
7481 06:55:36.901658 52 : 4249, 4027
7482 06:55:36.902087 56 : 4255, 4029
7483 06:55:36.902421 60 : 4360, 4137
7484 06:55:36.905520 64 : 4250, 4026
7485 06:55:36.906113 68 : 4360, 4138
7486 06:55:36.908278 72 : 4250, 4027
7487 06:55:36.908710 76 : 4250, 4027
7488 06:55:36.911928 80 : 4250, 4027
7489 06:55:36.912463 84 : 4360, 4137
7490 06:55:36.915119 88 : 4250, 4027
7491 06:55:36.915567 92 : 4360, 4137
7492 06:55:36.915908 96 : 4250, 4026
7493 06:55:36.918105 100 : 4249, 4027
7494 06:55:36.918538 104 : 4361, 3821
7495 06:55:36.921807 108 : 4360, 3
7496 06:55:36.922239 112 : 4250, 0
7497 06:55:36.925136 116 : 4250, 0
7498 06:55:36.925603 120 : 4361, 0
7499 06:55:36.925951 124 : 4361, 0
7500 06:55:36.928256 128 : 4247, 0
7501 06:55:36.928685 132 : 4250, 0
7502 06:55:36.929023 136 : 4249, 0
7503 06:55:36.932012 140 : 4250, 0
7504 06:55:36.932553 144 : 4253, 0
7505 06:55:36.935220 148 : 4249, 0
7506 06:55:36.935757 152 : 4250, 0
7507 06:55:36.936098 156 : 4253, 0
7508 06:55:36.938301 160 : 4360, 0
7509 06:55:36.938730 164 : 4250, 0
7510 06:55:36.941254 168 : 4250, 0
7511 06:55:36.941742 172 : 4250, 0
7512 06:55:36.942085 176 : 4361, 0
7513 06:55:36.945152 180 : 4361, 0
7514 06:55:36.945754 184 : 4253, 0
7515 06:55:36.948375 188 : 4360, 0
7516 06:55:36.948818 192 : 4250, 0
7517 06:55:36.949273 196 : 4250, 0
7518 06:55:36.952008 200 : 4250, 0
7519 06:55:36.952560 204 : 4250, 0
7520 06:55:36.953019 208 : 4252, 0
7521 06:55:36.954692 212 : 4360, 0
7522 06:55:36.955148 216 : 4250, 0
7523 06:55:36.957954 220 : 4250, 0
7524 06:55:36.958398 224 : 4250, 0
7525 06:55:36.958846 228 : 4361, 0
7526 06:55:36.961585 232 : 4250, 0
7527 06:55:36.962132 236 : 4250, 1007
7528 06:55:36.964920 240 : 4253, 4029
7529 06:55:36.965472 244 : 4250, 4027
7530 06:55:36.968381 248 : 4249, 4027
7531 06:55:36.968929 252 : 4361, 4137
7532 06:55:36.971574 256 : 4250, 4027
7533 06:55:36.972029 260 : 4250, 4027
7534 06:55:36.974619 264 : 4360, 4138
7535 06:55:36.975060 268 : 4360, 4137
7536 06:55:36.978017 272 : 4250, 4027
7537 06:55:36.978458 276 : 4363, 4140
7538 06:55:36.978905 280 : 4250, 4027
7539 06:55:36.980930 284 : 4249, 4027
7540 06:55:36.981391 288 : 4250, 4026
7541 06:55:36.984709 292 : 4253, 4029
7542 06:55:36.985274 296 : 4250, 4027
7543 06:55:36.987629 300 : 4250, 4027
7544 06:55:36.988072 304 : 4250, 4026
7545 06:55:36.991241 308 : 4253, 4029
7546 06:55:36.991797 312 : 4250, 4027
7547 06:55:36.994311 316 : 4360, 4138
7548 06:55:36.994863 320 : 4360, 4137
7549 06:55:36.997758 324 : 4250, 4027
7550 06:55:36.998224 328 : 4363, 4140
7551 06:55:37.001148 332 : 4250, 4027
7552 06:55:37.001619 336 : 4249, 4027
7553 06:55:37.004600 340 : 4250, 4026
7554 06:55:37.005189 344 : 4253, 4029
7555 06:55:37.005600 348 : 4250, 4027
7556 06:55:37.007638 352 : 4250, 4026
7557 06:55:37.008067 356 : 4250, 2946
7558 06:55:37.011118 360 : 4253, 0
7559 06:55:37.011548
7560 06:55:37.011882 MIOCK jitter meter ch=0
7561 06:55:37.014386
7562 06:55:37.014909 1T = (360-108) = 252 dly cells
7563 06:55:37.021309 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7564 06:55:37.022089 ==
7565 06:55:37.024327 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 06:55:37.028118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 06:55:37.028729 ==
7568 06:55:37.034249 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7569 06:55:37.038149 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7570 06:55:37.044393 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7571 06:55:37.047619 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7572 06:55:37.057989 [CA 0] Center 43 (13~74) winsize 62
7573 06:55:37.061283 [CA 1] Center 43 (13~74) winsize 62
7574 06:55:37.064757 [CA 2] Center 38 (10~67) winsize 58
7575 06:55:37.067968 [CA 3] Center 38 (9~68) winsize 60
7576 06:55:37.071019 [CA 4] Center 36 (7~66) winsize 60
7577 06:55:37.074235 [CA 5] Center 36 (7~66) winsize 60
7578 06:55:37.074670
7579 06:55:37.077637 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7580 06:55:37.078076
7581 06:55:37.084583 [CATrainingPosCal] consider 1 rank data
7582 06:55:37.085119 u2DelayCellTimex100 = 258/100 ps
7583 06:55:37.091033 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7584 06:55:37.094096 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7585 06:55:37.097838 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7586 06:55:37.100899 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7587 06:55:37.104421 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7588 06:55:37.107343 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7589 06:55:37.107808
7590 06:55:37.110870 CA PerBit enable=1, Macro0, CA PI delay=36
7591 06:55:37.111411
7592 06:55:37.114445 [CBTSetCACLKResult] CA Dly = 36
7593 06:55:37.117693 CS Dly: 11 (0~42)
7594 06:55:37.121012 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7595 06:55:37.124246 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7596 06:55:37.124683 ==
7597 06:55:37.127709 Dram Type= 6, Freq= 0, CH_0, rank 1
7598 06:55:37.134221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 06:55:37.134662 ==
7600 06:55:37.137203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7601 06:55:37.141023 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7602 06:55:37.147368 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7603 06:55:37.154032 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7604 06:55:37.161668 [CA 0] Center 43 (13~74) winsize 62
7605 06:55:37.164739 [CA 1] Center 43 (13~74) winsize 62
7606 06:55:37.168136 [CA 2] Center 38 (9~68) winsize 60
7607 06:55:37.171426 [CA 3] Center 39 (10~68) winsize 59
7608 06:55:37.174918 [CA 4] Center 36 (6~66) winsize 61
7609 06:55:37.178109 [CA 5] Center 36 (6~66) winsize 61
7610 06:55:37.178653
7611 06:55:37.181654 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7612 06:55:37.182204
7613 06:55:37.185197 [CATrainingPosCal] consider 2 rank data
7614 06:55:37.188706 u2DelayCellTimex100 = 258/100 ps
7615 06:55:37.191274 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7616 06:55:37.198471 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7617 06:55:37.201624 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7618 06:55:37.204707 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7619 06:55:37.207819 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7620 06:55:37.211265 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7621 06:55:37.211692
7622 06:55:37.214374 CA PerBit enable=1, Macro0, CA PI delay=36
7623 06:55:37.214796
7624 06:55:37.217785 [CBTSetCACLKResult] CA Dly = 36
7625 06:55:37.221022 CS Dly: 11 (0~43)
7626 06:55:37.224464 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7627 06:55:37.227756 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7628 06:55:37.228319
7629 06:55:37.231051 ----->DramcWriteLeveling(PI) begin...
7630 06:55:37.231483 ==
7631 06:55:37.234205 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 06:55:37.240984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 06:55:37.241408 ==
7634 06:55:37.244291 Write leveling (Byte 0): 34 => 34
7635 06:55:37.247417 Write leveling (Byte 1): 29 => 29
7636 06:55:37.247839 DramcWriteLeveling(PI) end<-----
7637 06:55:37.248174
7638 06:55:37.250844 ==
7639 06:55:37.254635 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 06:55:37.257600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 06:55:37.258179 ==
7642 06:55:37.261014 [Gating] SW mode calibration
7643 06:55:37.267211 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7644 06:55:37.270879 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7645 06:55:37.277523 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 06:55:37.280658 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 06:55:37.284239 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 06:55:37.290741 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 06:55:37.294395 1 4 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7650 06:55:37.297596 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7651 06:55:37.304256 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7652 06:55:37.307254 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7653 06:55:37.310869 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7654 06:55:37.317253 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7655 06:55:37.320496 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7656 06:55:37.323522 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7657 06:55:37.330235 1 5 16 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
7658 06:55:37.333366 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7659 06:55:37.337158 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
7660 06:55:37.343854 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 06:55:37.346824 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 06:55:37.349982 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 06:55:37.356858 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 06:55:37.360459 1 6 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7665 06:55:37.363298 1 6 16 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
7666 06:55:37.369992 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7667 06:55:37.373170 1 6 24 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
7668 06:55:37.376778 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 06:55:37.383160 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 06:55:37.386458 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7671 06:55:37.389897 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 06:55:37.396448 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 06:55:37.399575 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7674 06:55:37.403167 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7675 06:55:37.409982 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7676 06:55:37.413221 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7677 06:55:37.416435 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 06:55:37.422779 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 06:55:37.425835 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 06:55:37.429529 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 06:55:37.435972 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 06:55:37.439605 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 06:55:37.442380 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 06:55:37.449422 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 06:55:37.452380 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 06:55:37.456192 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 06:55:37.462572 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 06:55:37.466101 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 06:55:37.469535 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7690 06:55:37.475597 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7691 06:55:37.476126 Total UI for P1: 0, mck2ui 16
7692 06:55:37.479151 best dqsien dly found for B0: ( 1, 9, 16)
7693 06:55:37.485547 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7694 06:55:37.489105 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7695 06:55:37.492043 Total UI for P1: 0, mck2ui 16
7696 06:55:37.495827 best dqsien dly found for B1: ( 1, 9, 22)
7697 06:55:37.499098 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7698 06:55:37.502165 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7699 06:55:37.502588
7700 06:55:37.505552 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7701 06:55:37.512331 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7702 06:55:37.512864 [Gating] SW calibration Done
7703 06:55:37.515712 ==
7704 06:55:37.516285 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 06:55:37.522075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 06:55:37.522589 ==
7707 06:55:37.522930 RX Vref Scan: 0
7708 06:55:37.523245
7709 06:55:37.525263 RX Vref 0 -> 0, step: 1
7710 06:55:37.525736
7711 06:55:37.528929 RX Delay 0 -> 252, step: 8
7712 06:55:37.532497 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7713 06:55:37.535730 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7714 06:55:37.539397 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7715 06:55:37.546118 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7716 06:55:37.548873 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7717 06:55:37.552503 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7718 06:55:37.555422 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7719 06:55:37.558823 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7720 06:55:37.562274 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7721 06:55:37.568833 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7722 06:55:37.572096 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7723 06:55:37.575430 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7724 06:55:37.578648 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7725 06:55:37.585616 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7726 06:55:37.589105 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7727 06:55:37.592004 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7728 06:55:37.592429 ==
7729 06:55:37.595154 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 06:55:37.598721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 06:55:37.599149 ==
7732 06:55:37.601850 DQS Delay:
7733 06:55:37.602288 DQS0 = 0, DQS1 = 0
7734 06:55:37.605159 DQM Delay:
7735 06:55:37.605603 DQM0 = 128, DQM1 = 123
7736 06:55:37.605942 DQ Delay:
7737 06:55:37.612025 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7738 06:55:37.615558 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7739 06:55:37.618302 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7740 06:55:37.622018 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7741 06:55:37.622548
7742 06:55:37.622891
7743 06:55:37.623209 ==
7744 06:55:37.624961 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 06:55:37.628574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 06:55:37.629021 ==
7747 06:55:37.629363
7748 06:55:37.629793
7749 06:55:37.631861 TX Vref Scan disable
7750 06:55:37.635321 == TX Byte 0 ==
7751 06:55:37.638411 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7752 06:55:37.641844 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7753 06:55:37.645078 == TX Byte 1 ==
7754 06:55:37.648221 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7755 06:55:37.651609 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7756 06:55:37.652139 ==
7757 06:55:37.655094 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 06:55:37.661551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 06:55:37.662079 ==
7760 06:55:37.673415
7761 06:55:37.676689 TX Vref early break, caculate TX vref
7762 06:55:37.680299 TX Vref=16, minBit 4, minWin=21, winSum=360
7763 06:55:37.683153 TX Vref=18, minBit 0, minWin=22, winSum=366
7764 06:55:37.686444 TX Vref=20, minBit 0, minWin=23, winSum=378
7765 06:55:37.689991 TX Vref=22, minBit 0, minWin=23, winSum=385
7766 06:55:37.693342 TX Vref=24, minBit 2, minWin=24, winSum=401
7767 06:55:37.699876 TX Vref=26, minBit 8, minWin=24, winSum=409
7768 06:55:37.702911 TX Vref=28, minBit 4, minWin=24, winSum=403
7769 06:55:37.706328 TX Vref=30, minBit 0, minWin=24, winSum=397
7770 06:55:37.709620 TX Vref=32, minBit 1, minWin=23, winSum=388
7771 06:55:37.712995 TX Vref=34, minBit 3, minWin=22, winSum=379
7772 06:55:37.720099 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 26
7773 06:55:37.720633
7774 06:55:37.722849 Final TX Range 0 Vref 26
7775 06:55:37.723269
7776 06:55:37.723642 ==
7777 06:55:37.726722 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 06:55:37.729599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 06:55:37.730030 ==
7780 06:55:37.730365
7781 06:55:37.730674
7782 06:55:37.732610 TX Vref Scan disable
7783 06:55:37.739315 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7784 06:55:37.739841 == TX Byte 0 ==
7785 06:55:37.742893 u2DelayCellOfst[0]=18 cells (5 PI)
7786 06:55:37.746009 u2DelayCellOfst[1]=22 cells (6 PI)
7787 06:55:37.749534 u2DelayCellOfst[2]=11 cells (3 PI)
7788 06:55:37.753196 u2DelayCellOfst[3]=15 cells (4 PI)
7789 06:55:37.756469 u2DelayCellOfst[4]=11 cells (3 PI)
7790 06:55:37.759223 u2DelayCellOfst[5]=0 cells (0 PI)
7791 06:55:37.762180 u2DelayCellOfst[6]=22 cells (6 PI)
7792 06:55:37.765964 u2DelayCellOfst[7]=22 cells (6 PI)
7793 06:55:37.769459 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7794 06:55:37.772451 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7795 06:55:37.775875 == TX Byte 1 ==
7796 06:55:37.779309 u2DelayCellOfst[8]=0 cells (0 PI)
7797 06:55:37.779836 u2DelayCellOfst[9]=0 cells (0 PI)
7798 06:55:37.782540 u2DelayCellOfst[10]=7 cells (2 PI)
7799 06:55:37.785635 u2DelayCellOfst[11]=3 cells (1 PI)
7800 06:55:37.789352 u2DelayCellOfst[12]=15 cells (4 PI)
7801 06:55:37.792468 u2DelayCellOfst[13]=11 cells (3 PI)
7802 06:55:37.795506 u2DelayCellOfst[14]=18 cells (5 PI)
7803 06:55:37.798823 u2DelayCellOfst[15]=11 cells (3 PI)
7804 06:55:37.805569 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7805 06:55:37.808808 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7806 06:55:37.809398 DramC Write-DBI on
7807 06:55:37.809808 ==
7808 06:55:37.811989 Dram Type= 6, Freq= 0, CH_0, rank 0
7809 06:55:37.819086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7810 06:55:37.819618 ==
7811 06:55:37.820021
7812 06:55:37.820338
7813 06:55:37.820637 TX Vref Scan disable
7814 06:55:37.822678 == TX Byte 0 ==
7815 06:55:37.825899 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7816 06:55:37.829390 == TX Byte 1 ==
7817 06:55:37.832734 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7818 06:55:37.836452 DramC Write-DBI off
7819 06:55:37.837023
7820 06:55:37.837370 [DATLAT]
7821 06:55:37.837745 Freq=1600, CH0 RK0
7822 06:55:37.838081
7823 06:55:37.839320 DATLAT Default: 0xf
7824 06:55:37.839741 0, 0xFFFF, sum = 0
7825 06:55:37.842917 1, 0xFFFF, sum = 0
7826 06:55:37.846085 2, 0xFFFF, sum = 0
7827 06:55:37.846615 3, 0xFFFF, sum = 0
7828 06:55:37.849706 4, 0xFFFF, sum = 0
7829 06:55:37.850346 5, 0xFFFF, sum = 0
7830 06:55:37.853012 6, 0xFFFF, sum = 0
7831 06:55:37.853590 7, 0xFFFF, sum = 0
7832 06:55:37.856170 8, 0xFFFF, sum = 0
7833 06:55:37.856704 9, 0xFFFF, sum = 0
7834 06:55:37.859371 10, 0xFFFF, sum = 0
7835 06:55:37.859801 11, 0xFFFF, sum = 0
7836 06:55:37.863071 12, 0xFFFF, sum = 0
7837 06:55:37.863622 13, 0xEFFF, sum = 0
7838 06:55:37.866165 14, 0x0, sum = 1
7839 06:55:37.866595 15, 0x0, sum = 2
7840 06:55:37.869298 16, 0x0, sum = 3
7841 06:55:37.869795 17, 0x0, sum = 4
7842 06:55:37.872662 best_step = 15
7843 06:55:37.873081
7844 06:55:37.873411 ==
7845 06:55:37.876326 Dram Type= 6, Freq= 0, CH_0, rank 0
7846 06:55:37.879666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7847 06:55:37.880188 ==
7848 06:55:37.880525 RX Vref Scan: 1
7849 06:55:37.882600
7850 06:55:37.883121 Set Vref Range= 24 -> 127
7851 06:55:37.883458
7852 06:55:37.885889 RX Vref 24 -> 127, step: 1
7853 06:55:37.886407
7854 06:55:37.889408 RX Delay 11 -> 252, step: 4
7855 06:55:37.889900
7856 06:55:37.892824 Set Vref, RX VrefLevel [Byte0]: 24
7857 06:55:37.896069 [Byte1]: 24
7858 06:55:37.896595
7859 06:55:37.899089 Set Vref, RX VrefLevel [Byte0]: 25
7860 06:55:37.902401 [Byte1]: 25
7861 06:55:37.902828
7862 06:55:37.905789 Set Vref, RX VrefLevel [Byte0]: 26
7863 06:55:37.909010 [Byte1]: 26
7864 06:55:37.913321
7865 06:55:37.913938 Set Vref, RX VrefLevel [Byte0]: 27
7866 06:55:37.916545 [Byte1]: 27
7867 06:55:37.920981
7868 06:55:37.921549 Set Vref, RX VrefLevel [Byte0]: 28
7869 06:55:37.924271 [Byte1]: 28
7870 06:55:37.928217
7871 06:55:37.928670 Set Vref, RX VrefLevel [Byte0]: 29
7872 06:55:37.931637 [Byte1]: 29
7873 06:55:37.935915
7874 06:55:37.936486 Set Vref, RX VrefLevel [Byte0]: 30
7875 06:55:37.939391 [Byte1]: 30
7876 06:55:37.943703
7877 06:55:37.944216 Set Vref, RX VrefLevel [Byte0]: 31
7878 06:55:37.946820 [Byte1]: 31
7879 06:55:37.951109
7880 06:55:37.951625 Set Vref, RX VrefLevel [Byte0]: 32
7881 06:55:37.954256 [Byte1]: 32
7882 06:55:37.958660
7883 06:55:37.959085 Set Vref, RX VrefLevel [Byte0]: 33
7884 06:55:37.962001 [Byte1]: 33
7885 06:55:37.966812
7886 06:55:37.967333 Set Vref, RX VrefLevel [Byte0]: 34
7887 06:55:37.969968 [Byte1]: 34
7888 06:55:37.974330
7889 06:55:37.974851 Set Vref, RX VrefLevel [Byte0]: 35
7890 06:55:37.977518 [Byte1]: 35
7891 06:55:37.981815
7892 06:55:37.982332 Set Vref, RX VrefLevel [Byte0]: 36
7893 06:55:37.984976 [Byte1]: 36
7894 06:55:37.989585
7895 06:55:37.990108 Set Vref, RX VrefLevel [Byte0]: 37
7896 06:55:37.992932 [Byte1]: 37
7897 06:55:37.997256
7898 06:55:37.997902 Set Vref, RX VrefLevel [Byte0]: 38
7899 06:55:38.000451 [Byte1]: 38
7900 06:55:38.004487
7901 06:55:38.005012 Set Vref, RX VrefLevel [Byte0]: 39
7902 06:55:38.007842 [Byte1]: 39
7903 06:55:38.012161
7904 06:55:38.012585 Set Vref, RX VrefLevel [Byte0]: 40
7905 06:55:38.015682 [Byte1]: 40
7906 06:55:38.019953
7907 06:55:38.020523 Set Vref, RX VrefLevel [Byte0]: 41
7908 06:55:38.023080 [Byte1]: 41
7909 06:55:38.027397
7910 06:55:38.028072 Set Vref, RX VrefLevel [Byte0]: 42
7911 06:55:38.030669 [Byte1]: 42
7912 06:55:38.035337
7913 06:55:38.035860 Set Vref, RX VrefLevel [Byte0]: 43
7914 06:55:38.038089 [Byte1]: 43
7915 06:55:38.042448
7916 06:55:38.042971 Set Vref, RX VrefLevel [Byte0]: 44
7917 06:55:38.045857 [Byte1]: 44
7918 06:55:38.050026
7919 06:55:38.050448 Set Vref, RX VrefLevel [Byte0]: 45
7920 06:55:38.053864 [Byte1]: 45
7921 06:55:38.057699
7922 06:55:38.058161 Set Vref, RX VrefLevel [Byte0]: 46
7923 06:55:38.061068 [Byte1]: 46
7924 06:55:38.065861
7925 06:55:38.066394 Set Vref, RX VrefLevel [Byte0]: 47
7926 06:55:38.068651 [Byte1]: 47
7927 06:55:38.073258
7928 06:55:38.073863 Set Vref, RX VrefLevel [Byte0]: 48
7929 06:55:38.076386 [Byte1]: 48
7930 06:55:38.080834
7931 06:55:38.081360 Set Vref, RX VrefLevel [Byte0]: 49
7932 06:55:38.083871 [Byte1]: 49
7933 06:55:38.088699
7934 06:55:38.089222 Set Vref, RX VrefLevel [Byte0]: 50
7935 06:55:38.091883 [Byte1]: 50
7936 06:55:38.095919
7937 06:55:38.096445 Set Vref, RX VrefLevel [Byte0]: 51
7938 06:55:38.099520 [Byte1]: 51
7939 06:55:38.103905
7940 06:55:38.104432 Set Vref, RX VrefLevel [Byte0]: 52
7941 06:55:38.107103 [Byte1]: 52
7942 06:55:38.111141
7943 06:55:38.111664 Set Vref, RX VrefLevel [Byte0]: 53
7944 06:55:38.114324 [Byte1]: 53
7945 06:55:38.119062
7946 06:55:38.119584 Set Vref, RX VrefLevel [Byte0]: 54
7947 06:55:38.122076 [Byte1]: 54
7948 06:55:38.126327
7949 06:55:38.126752 Set Vref, RX VrefLevel [Byte0]: 55
7950 06:55:38.129658 [Byte1]: 55
7951 06:55:38.133998
7952 06:55:38.134519 Set Vref, RX VrefLevel [Byte0]: 56
7953 06:55:38.137570 [Byte1]: 56
7954 06:55:38.141658
7955 06:55:38.142173 Set Vref, RX VrefLevel [Byte0]: 57
7956 06:55:38.144807 [Byte1]: 57
7957 06:55:38.149031
7958 06:55:38.149588 Set Vref, RX VrefLevel [Byte0]: 58
7959 06:55:38.152883 [Byte1]: 58
7960 06:55:38.156994
7961 06:55:38.157537 Set Vref, RX VrefLevel [Byte0]: 59
7962 06:55:38.160050 [Byte1]: 59
7963 06:55:38.164675
7964 06:55:38.165204 Set Vref, RX VrefLevel [Byte0]: 60
7965 06:55:38.168267 [Byte1]: 60
7966 06:55:38.172187
7967 06:55:38.172707 Set Vref, RX VrefLevel [Byte0]: 61
7968 06:55:38.175240 [Byte1]: 61
7969 06:55:38.179489
7970 06:55:38.179913 Set Vref, RX VrefLevel [Byte0]: 62
7971 06:55:38.182863 [Byte1]: 62
7972 06:55:38.187121
7973 06:55:38.187646 Set Vref, RX VrefLevel [Byte0]: 63
7974 06:55:38.190386 [Byte1]: 63
7975 06:55:38.195081
7976 06:55:38.195614 Set Vref, RX VrefLevel [Byte0]: 64
7977 06:55:38.198046 [Byte1]: 64
7978 06:55:38.202374
7979 06:55:38.202899 Set Vref, RX VrefLevel [Byte0]: 65
7980 06:55:38.206155 [Byte1]: 65
7981 06:55:38.210292
7982 06:55:38.210810 Set Vref, RX VrefLevel [Byte0]: 66
7983 06:55:38.213560 [Byte1]: 66
7984 06:55:38.218108
7985 06:55:38.218633 Set Vref, RX VrefLevel [Byte0]: 67
7986 06:55:38.221230 [Byte1]: 67
7987 06:55:38.225470
7988 06:55:38.226038 Set Vref, RX VrefLevel [Byte0]: 68
7989 06:55:38.228592 [Byte1]: 68
7990 06:55:38.232907
7991 06:55:38.233444 Set Vref, RX VrefLevel [Byte0]: 69
7992 06:55:38.236511 [Byte1]: 69
7993 06:55:38.240703
7994 06:55:38.241227 Set Vref, RX VrefLevel [Byte0]: 70
7995 06:55:38.244149 [Byte1]: 70
7996 06:55:38.248100
7997 06:55:38.248627 Set Vref, RX VrefLevel [Byte0]: 71
7998 06:55:38.251792 [Byte1]: 71
7999 06:55:38.255977
8000 06:55:38.256510 Set Vref, RX VrefLevel [Byte0]: 72
8001 06:55:38.259044 [Byte1]: 72
8002 06:55:38.263581
8003 06:55:38.264104 Set Vref, RX VrefLevel [Byte0]: 73
8004 06:55:38.266931 [Byte1]: 73
8005 06:55:38.271291
8006 06:55:38.271815 Set Vref, RX VrefLevel [Byte0]: 74
8007 06:55:38.274039 [Byte1]: 74
8008 06:55:38.278525
8009 06:55:38.279046 Set Vref, RX VrefLevel [Byte0]: 75
8010 06:55:38.281831 [Byte1]: 75
8011 06:55:38.286378
8012 06:55:38.286899 Set Vref, RX VrefLevel [Byte0]: 76
8013 06:55:38.289836 [Byte1]: 76
8014 06:55:38.293860
8015 06:55:38.294427 Final RX Vref Byte 0 = 64 to rank0
8016 06:55:38.297322 Final RX Vref Byte 1 = 60 to rank0
8017 06:55:38.300559 Final RX Vref Byte 0 = 64 to rank1
8018 06:55:38.303483 Final RX Vref Byte 1 = 60 to rank1==
8019 06:55:38.307225 Dram Type= 6, Freq= 0, CH_0, rank 0
8020 06:55:38.313585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8021 06:55:38.314015 ==
8022 06:55:38.314459 DQS Delay:
8023 06:55:38.314965 DQS0 = 0, DQS1 = 0
8024 06:55:38.316901 DQM Delay:
8025 06:55:38.317467 DQM0 = 126, DQM1 = 119
8026 06:55:38.320000 DQ Delay:
8027 06:55:38.323972 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8028 06:55:38.327004 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8029 06:55:38.330229 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8030 06:55:38.333758 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8031 06:55:38.334185
8032 06:55:38.334548
8033 06:55:38.334901
8034 06:55:38.336667 [DramC_TX_OE_Calibration] TA2
8035 06:55:38.340173 Original DQ_B0 (3 6) =30, OEN = 27
8036 06:55:38.343718 Original DQ_B1 (3 6) =30, OEN = 27
8037 06:55:38.346940 24, 0x0, End_B0=24 End_B1=24
8038 06:55:38.347373 25, 0x0, End_B0=25 End_B1=25
8039 06:55:38.350158 26, 0x0, End_B0=26 End_B1=26
8040 06:55:38.353589 27, 0x0, End_B0=27 End_B1=27
8041 06:55:38.356817 28, 0x0, End_B0=28 End_B1=28
8042 06:55:38.357249 29, 0x0, End_B0=29 End_B1=29
8043 06:55:38.360105 30, 0x0, End_B0=30 End_B1=30
8044 06:55:38.363584 31, 0x4141, End_B0=30 End_B1=30
8045 06:55:38.366841 Byte0 end_step=30 best_step=27
8046 06:55:38.370169 Byte1 end_step=30 best_step=27
8047 06:55:38.373284 Byte0 TX OE(2T, 0.5T) = (3, 3)
8048 06:55:38.373776 Byte1 TX OE(2T, 0.5T) = (3, 3)
8049 06:55:38.376917
8050 06:55:38.377520
8051 06:55:38.383423 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8052 06:55:38.386830 CH0 RK0: MR19=303, MR18=1515
8053 06:55:38.393775 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
8054 06:55:38.394329
8055 06:55:38.396751 ----->DramcWriteLeveling(PI) begin...
8056 06:55:38.397285 ==
8057 06:55:38.400416 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 06:55:38.403765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 06:55:38.404294 ==
8060 06:55:38.406438 Write leveling (Byte 0): 36 => 36
8061 06:55:38.410061 Write leveling (Byte 1): 28 => 28
8062 06:55:38.413369 DramcWriteLeveling(PI) end<-----
8063 06:55:38.413931
8064 06:55:38.414272 ==
8065 06:55:38.417006 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 06:55:38.420021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 06:55:38.420452 ==
8068 06:55:38.423189 [Gating] SW mode calibration
8069 06:55:38.429815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8070 06:55:38.436347 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8071 06:55:38.440200 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 06:55:38.443410 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 06:55:38.449814 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 06:55:38.453649 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8075 06:55:38.456362 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8076 06:55:38.462854 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8077 06:55:38.466150 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8078 06:55:38.469642 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8079 06:55:38.476236 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8080 06:55:38.479381 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 06:55:38.482855 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8082 06:55:38.489523 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8083 06:55:38.492900 1 5 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8084 06:55:38.496194 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8085 06:55:38.502939 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 06:55:38.505968 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 06:55:38.509813 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 06:55:38.516006 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 06:55:38.519002 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8090 06:55:38.522299 1 6 12 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8091 06:55:38.528984 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8092 06:55:38.532042 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 06:55:38.535629 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 06:55:38.542221 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 06:55:38.545665 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 06:55:38.549038 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 06:55:38.555981 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8098 06:55:38.558926 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8099 06:55:38.562524 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8100 06:55:38.569173 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8101 06:55:38.572472 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 06:55:38.575935 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 06:55:38.582115 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 06:55:38.585527 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 06:55:38.589104 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 06:55:38.595425 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 06:55:38.598835 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 06:55:38.602398 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 06:55:38.609078 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 06:55:38.612242 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 06:55:38.615794 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 06:55:38.622441 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 06:55:38.625625 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8114 06:55:38.628908 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8115 06:55:38.635012 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8116 06:55:38.635439 Total UI for P1: 0, mck2ui 16
8117 06:55:38.638488 best dqsien dly found for B0: ( 1, 9, 10)
8118 06:55:38.645298 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8119 06:55:38.648839 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 06:55:38.651838 Total UI for P1: 0, mck2ui 16
8121 06:55:38.655184 best dqsien dly found for B1: ( 1, 9, 18)
8122 06:55:38.658125 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8123 06:55:38.662165 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8124 06:55:38.662692
8125 06:55:38.665370 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8126 06:55:38.671982 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8127 06:55:38.672509 [Gating] SW calibration Done
8128 06:55:38.675343 ==
8129 06:55:38.675873 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 06:55:38.681668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 06:55:38.682208 ==
8132 06:55:38.682554 RX Vref Scan: 0
8133 06:55:38.682873
8134 06:55:38.684721 RX Vref 0 -> 0, step: 1
8135 06:55:38.685148
8136 06:55:38.688082 RX Delay 0 -> 252, step: 8
8137 06:55:38.691383 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8138 06:55:38.694671 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8139 06:55:38.698172 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8140 06:55:38.704782 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8141 06:55:38.707794 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8142 06:55:38.711227 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8143 06:55:38.714289 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8144 06:55:38.717810 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8145 06:55:38.724529 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8146 06:55:38.727990 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8147 06:55:38.731037 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8148 06:55:38.734217 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8149 06:55:38.737947 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8150 06:55:38.744305 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8151 06:55:38.747935 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8152 06:55:38.751168 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8153 06:55:38.751718 ==
8154 06:55:38.754204 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 06:55:38.758043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 06:55:38.760793 ==
8157 06:55:38.761234 DQS Delay:
8158 06:55:38.761713 DQS0 = 0, DQS1 = 0
8159 06:55:38.764427 DQM Delay:
8160 06:55:38.764977 DQM0 = 128, DQM1 = 122
8161 06:55:38.767789 DQ Delay:
8162 06:55:38.771106 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8163 06:55:38.774490 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8164 06:55:38.777375 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8165 06:55:38.781101 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8166 06:55:38.781689
8167 06:55:38.782146
8168 06:55:38.782566 ==
8169 06:55:38.784587 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 06:55:38.787710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 06:55:38.788307 ==
8172 06:55:38.788758
8173 06:55:38.791028
8174 06:55:38.791573 TX Vref Scan disable
8175 06:55:38.794230 == TX Byte 0 ==
8176 06:55:38.797714 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8177 06:55:38.801082 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8178 06:55:38.804523 == TX Byte 1 ==
8179 06:55:38.807726 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8180 06:55:38.810487 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8181 06:55:38.810914 ==
8182 06:55:38.814189 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 06:55:38.820656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 06:55:38.821192 ==
8185 06:55:38.834476
8186 06:55:38.838135 TX Vref early break, caculate TX vref
8187 06:55:38.841092 TX Vref=16, minBit 8, minWin=22, winSum=373
8188 06:55:38.844428 TX Vref=18, minBit 8, minWin=22, winSum=380
8189 06:55:38.847769 TX Vref=20, minBit 8, minWin=22, winSum=387
8190 06:55:38.850632 TX Vref=22, minBit 8, minWin=23, winSum=393
8191 06:55:38.854569 TX Vref=24, minBit 8, minWin=24, winSum=407
8192 06:55:38.860769 TX Vref=26, minBit 8, minWin=24, winSum=413
8193 06:55:38.864257 TX Vref=28, minBit 8, minWin=24, winSum=414
8194 06:55:38.867262 TX Vref=30, minBit 13, minWin=24, winSum=413
8195 06:55:38.870685 TX Vref=32, minBit 8, minWin=22, winSum=398
8196 06:55:38.874105 TX Vref=34, minBit 8, minWin=22, winSum=393
8197 06:55:38.877443 TX Vref=36, minBit 8, minWin=22, winSum=387
8198 06:55:38.884222 [TxChooseVref] Worse bit 8, Min win 24, Win sum 414, Final Vref 28
8199 06:55:38.884750
8200 06:55:38.886936 Final TX Range 0 Vref 28
8201 06:55:38.887399
8202 06:55:38.887740 ==
8203 06:55:38.890560 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 06:55:38.893599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 06:55:38.894024 ==
8206 06:55:38.897452
8207 06:55:38.898023
8208 06:55:38.898363 TX Vref Scan disable
8209 06:55:38.903725 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8210 06:55:38.904255 == TX Byte 0 ==
8211 06:55:38.907420 u2DelayCellOfst[0]=11 cells (3 PI)
8212 06:55:38.910273 u2DelayCellOfst[1]=18 cells (5 PI)
8213 06:55:38.913919 u2DelayCellOfst[2]=11 cells (3 PI)
8214 06:55:38.917131 u2DelayCellOfst[3]=11 cells (3 PI)
8215 06:55:38.920240 u2DelayCellOfst[4]=7 cells (2 PI)
8216 06:55:38.923768 u2DelayCellOfst[5]=0 cells (0 PI)
8217 06:55:38.926886 u2DelayCellOfst[6]=18 cells (5 PI)
8218 06:55:38.929958 u2DelayCellOfst[7]=18 cells (5 PI)
8219 06:55:38.933434 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8220 06:55:38.936578 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8221 06:55:38.940309 == TX Byte 1 ==
8222 06:55:38.943388 u2DelayCellOfst[8]=0 cells (0 PI)
8223 06:55:38.947204 u2DelayCellOfst[9]=3 cells (1 PI)
8224 06:55:38.949723 u2DelayCellOfst[10]=11 cells (3 PI)
8225 06:55:38.953295 u2DelayCellOfst[11]=7 cells (2 PI)
8226 06:55:38.956395 u2DelayCellOfst[12]=15 cells (4 PI)
8227 06:55:38.959756 u2DelayCellOfst[13]=15 cells (4 PI)
8228 06:55:38.960182 u2DelayCellOfst[14]=15 cells (4 PI)
8229 06:55:38.963158 u2DelayCellOfst[15]=15 cells (4 PI)
8230 06:55:38.970162 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8231 06:55:38.973362 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8232 06:55:38.976165 DramC Write-DBI on
8233 06:55:38.976586 ==
8234 06:55:38.979636 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 06:55:38.983003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 06:55:38.983427 ==
8237 06:55:38.983759
8238 06:55:38.984066
8239 06:55:38.986295 TX Vref Scan disable
8240 06:55:38.986718 == TX Byte 0 ==
8241 06:55:38.993182 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8242 06:55:38.993753 == TX Byte 1 ==
8243 06:55:38.996606 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8244 06:55:38.999634 DramC Write-DBI off
8245 06:55:39.000163
8246 06:55:39.000500 [DATLAT]
8247 06:55:39.002842 Freq=1600, CH0 RK1
8248 06:55:39.003372
8249 06:55:39.003711 DATLAT Default: 0xf
8250 06:55:39.006061 0, 0xFFFF, sum = 0
8251 06:55:39.006492 1, 0xFFFF, sum = 0
8252 06:55:39.009361 2, 0xFFFF, sum = 0
8253 06:55:39.012828 3, 0xFFFF, sum = 0
8254 06:55:39.013367 4, 0xFFFF, sum = 0
8255 06:55:39.016187 5, 0xFFFF, sum = 0
8256 06:55:39.016721 6, 0xFFFF, sum = 0
8257 06:55:39.019550 7, 0xFFFF, sum = 0
8258 06:55:39.020162 8, 0xFFFF, sum = 0
8259 06:55:39.022640 9, 0xFFFF, sum = 0
8260 06:55:39.023069 10, 0xFFFF, sum = 0
8261 06:55:39.026005 11, 0xFFFF, sum = 0
8262 06:55:39.026434 12, 0xFFFF, sum = 0
8263 06:55:39.029608 13, 0xCFFF, sum = 0
8264 06:55:39.030140 14, 0x0, sum = 1
8265 06:55:39.032492 15, 0x0, sum = 2
8266 06:55:39.033077 16, 0x0, sum = 3
8267 06:55:39.036339 17, 0x0, sum = 4
8268 06:55:39.036875 best_step = 15
8269 06:55:39.037215
8270 06:55:39.037576 ==
8271 06:55:39.039573 Dram Type= 6, Freq= 0, CH_0, rank 1
8272 06:55:39.042873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 06:55:39.046185 ==
8274 06:55:39.046609 RX Vref Scan: 0
8275 06:55:39.046946
8276 06:55:39.049454 RX Vref 0 -> 0, step: 1
8277 06:55:39.049919
8278 06:55:39.050254 RX Delay 3 -> 252, step: 4
8279 06:55:39.057138 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8280 06:55:39.060169 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8281 06:55:39.063293 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8282 06:55:39.066550 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8283 06:55:39.070223 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8284 06:55:39.076781 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8285 06:55:39.080069 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8286 06:55:39.083215 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8287 06:55:39.086617 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8288 06:55:39.090098 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8289 06:55:39.096372 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8290 06:55:39.099760 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8291 06:55:39.103060 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8292 06:55:39.106528 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8293 06:55:39.113010 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8294 06:55:39.116641 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8295 06:55:39.117169 ==
8296 06:55:39.120001 Dram Type= 6, Freq= 0, CH_0, rank 1
8297 06:55:39.123285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 06:55:39.123815 ==
8299 06:55:39.126064 DQS Delay:
8300 06:55:39.126518 DQS0 = 0, DQS1 = 0
8301 06:55:39.126855 DQM Delay:
8302 06:55:39.129549 DQM0 = 124, DQM1 = 118
8303 06:55:39.129975 DQ Delay:
8304 06:55:39.133052 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8305 06:55:39.136310 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8306 06:55:39.139390 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8307 06:55:39.145962 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8308 06:55:39.146466
8309 06:55:39.146799
8310 06:55:39.147107
8311 06:55:39.149298 [DramC_TX_OE_Calibration] TA2
8312 06:55:39.149814 Original DQ_B0 (3 6) =30, OEN = 27
8313 06:55:39.153140 Original DQ_B1 (3 6) =30, OEN = 27
8314 06:55:39.156391 24, 0x0, End_B0=24 End_B1=24
8315 06:55:39.159576 25, 0x0, End_B0=25 End_B1=25
8316 06:55:39.163004 26, 0x0, End_B0=26 End_B1=26
8317 06:55:39.166446 27, 0x0, End_B0=27 End_B1=27
8318 06:55:39.166981 28, 0x0, End_B0=28 End_B1=28
8319 06:55:39.169770 29, 0x0, End_B0=29 End_B1=29
8320 06:55:39.172707 30, 0x0, End_B0=30 End_B1=30
8321 06:55:39.176183 31, 0x4141, End_B0=30 End_B1=30
8322 06:55:39.179413 Byte0 end_step=30 best_step=27
8323 06:55:39.179943 Byte1 end_step=30 best_step=27
8324 06:55:39.182796 Byte0 TX OE(2T, 0.5T) = (3, 3)
8325 06:55:39.186175 Byte1 TX OE(2T, 0.5T) = (3, 3)
8326 06:55:39.186710
8327 06:55:39.187049
8328 06:55:39.196044 [DQSOSCAuto] RK1, (LSB)MR18= 0x2411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
8329 06:55:39.196559 CH0 RK1: MR19=303, MR18=2411
8330 06:55:39.202944 CH0_RK1: MR19=0x303, MR18=0x2411, DQSOSC=391, MR23=63, INC=24, DEC=16
8331 06:55:39.206237 [RxdqsGatingPostProcess] freq 1600
8332 06:55:39.212446 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8333 06:55:39.215950 best DQS0 dly(2T, 0.5T) = (1, 1)
8334 06:55:39.219023 best DQS1 dly(2T, 0.5T) = (1, 1)
8335 06:55:39.222592 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8336 06:55:39.226073 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8337 06:55:39.226679 best DQS0 dly(2T, 0.5T) = (1, 1)
8338 06:55:39.228983 best DQS1 dly(2T, 0.5T) = (1, 1)
8339 06:55:39.232516 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8340 06:55:39.235429 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8341 06:55:39.238836 Pre-setting of DQS Precalculation
8342 06:55:39.245995 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8343 06:55:39.246530 ==
8344 06:55:39.248976 Dram Type= 6, Freq= 0, CH_1, rank 0
8345 06:55:39.252355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 06:55:39.252888 ==
8347 06:55:39.258967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8348 06:55:39.262152 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8349 06:55:39.265764 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8350 06:55:39.272192 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8351 06:55:39.281154 [CA 0] Center 41 (13~70) winsize 58
8352 06:55:39.284801 [CA 1] Center 42 (12~72) winsize 61
8353 06:55:39.287763 [CA 2] Center 37 (8~66) winsize 59
8354 06:55:39.290744 [CA 3] Center 36 (7~66) winsize 60
8355 06:55:39.294283 [CA 4] Center 37 (8~67) winsize 60
8356 06:55:39.297650 [CA 5] Center 35 (6~65) winsize 60
8357 06:55:39.298176
8358 06:55:39.300759 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8359 06:55:39.301181
8360 06:55:39.303912 [CATrainingPosCal] consider 1 rank data
8361 06:55:39.307565 u2DelayCellTimex100 = 258/100 ps
8362 06:55:39.310718 CA0 delay=41 (13~70),Diff = 6 PI (22 cell)
8363 06:55:39.317263 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8364 06:55:39.320690 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8365 06:55:39.323899 CA3 delay=36 (7~66),Diff = 1 PI (3 cell)
8366 06:55:39.327375 CA4 delay=37 (8~67),Diff = 2 PI (7 cell)
8367 06:55:39.330828 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
8368 06:55:39.331355
8369 06:55:39.333914 CA PerBit enable=1, Macro0, CA PI delay=35
8370 06:55:39.334338
8371 06:55:39.337307 [CBTSetCACLKResult] CA Dly = 35
8372 06:55:39.340562 CS Dly: 9 (0~40)
8373 06:55:39.344370 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8374 06:55:39.347339 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8375 06:55:39.347760 ==
8376 06:55:39.350772 Dram Type= 6, Freq= 0, CH_1, rank 1
8377 06:55:39.353960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 06:55:39.357366 ==
8379 06:55:39.360734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8380 06:55:39.363819 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8381 06:55:39.370176 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8382 06:55:39.376913 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8383 06:55:39.384287 [CA 0] Center 41 (12~71) winsize 60
8384 06:55:39.387412 [CA 1] Center 42 (12~72) winsize 61
8385 06:55:39.390747 [CA 2] Center 37 (8~67) winsize 60
8386 06:55:39.394329 [CA 3] Center 36 (7~66) winsize 60
8387 06:55:39.397456 [CA 4] Center 37 (8~67) winsize 60
8388 06:55:39.401199 [CA 5] Center 36 (6~66) winsize 61
8389 06:55:39.401818
8390 06:55:39.404235 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8391 06:55:39.404701
8392 06:55:39.407518 [CATrainingPosCal] consider 2 rank data
8393 06:55:39.410905 u2DelayCellTimex100 = 258/100 ps
8394 06:55:39.413823 CA0 delay=41 (13~70),Diff = 6 PI (22 cell)
8395 06:55:39.420679 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8396 06:55:39.424098 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8397 06:55:39.427348 CA3 delay=36 (7~66),Diff = 1 PI (3 cell)
8398 06:55:39.430486 CA4 delay=37 (8~67),Diff = 2 PI (7 cell)
8399 06:55:39.433734 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
8400 06:55:39.434158
8401 06:55:39.437265 CA PerBit enable=1, Macro0, CA PI delay=35
8402 06:55:39.437736
8403 06:55:39.440373 [CBTSetCACLKResult] CA Dly = 35
8404 06:55:39.443498 CS Dly: 11 (0~44)
8405 06:55:39.447135 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8406 06:55:39.450319 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8407 06:55:39.450995
8408 06:55:39.453606 ----->DramcWriteLeveling(PI) begin...
8409 06:55:39.454041 ==
8410 06:55:39.456911 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 06:55:39.463580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 06:55:39.464116 ==
8413 06:55:39.466814 Write leveling (Byte 0): 26 => 26
8414 06:55:39.467529 Write leveling (Byte 1): 28 => 28
8415 06:55:39.469942 DramcWriteLeveling(PI) end<-----
8416 06:55:39.470366
8417 06:55:39.470700 ==
8418 06:55:39.473539 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 06:55:39.480352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 06:55:39.480886 ==
8421 06:55:39.483273 [Gating] SW mode calibration
8422 06:55:39.489898 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8423 06:55:39.493468 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8424 06:55:39.500615 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 06:55:39.503918 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 06:55:39.506843 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 06:55:39.513528 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 06:55:39.516737 1 4 16 | B1->B0 | 3232 3030 | 1 1 | (1 1) (0 0)
8429 06:55:39.520105 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 06:55:39.526490 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 06:55:39.530175 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 06:55:39.533337 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 06:55:39.540058 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8434 06:55:39.543672 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8435 06:55:39.546209 1 5 12 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
8436 06:55:39.553114 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8437 06:55:39.556680 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 06:55:39.559968 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 06:55:39.566453 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 06:55:39.569445 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 06:55:39.572999 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 06:55:39.576123 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8443 06:55:39.582726 1 6 12 | B1->B0 | 3131 2c2b | 0 1 | (1 1) (0 0)
8444 06:55:39.586479 1 6 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8445 06:55:39.589513 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 06:55:39.596366 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 06:55:39.599842 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 06:55:39.603151 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 06:55:39.609798 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 06:55:39.613223 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 06:55:39.616846 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8452 06:55:39.623276 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8453 06:55:39.626198 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 06:55:39.629890 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 06:55:39.636341 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 06:55:39.639860 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 06:55:39.642839 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 06:55:39.649454 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 06:55:39.652574 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 06:55:39.655968 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 06:55:39.662402 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 06:55:39.665721 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 06:55:39.669028 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 06:55:39.675723 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 06:55:39.678838 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 06:55:39.682370 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 06:55:39.688619 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8468 06:55:39.692158 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8469 06:55:39.695751 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 06:55:39.699041 Total UI for P1: 0, mck2ui 16
8471 06:55:39.702158 best dqsien dly found for B0: ( 1, 9, 14)
8472 06:55:39.705669 Total UI for P1: 0, mck2ui 16
8473 06:55:39.708974 best dqsien dly found for B1: ( 1, 9, 14)
8474 06:55:39.712136 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8475 06:55:39.715353 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8476 06:55:39.715791
8477 06:55:39.722055 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8478 06:55:39.725183 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8479 06:55:39.728294 [Gating] SW calibration Done
8480 06:55:39.728725 ==
8481 06:55:39.731798 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 06:55:39.735530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 06:55:39.735960 ==
8484 06:55:39.736303 RX Vref Scan: 0
8485 06:55:39.736624
8486 06:55:39.738647 RX Vref 0 -> 0, step: 1
8487 06:55:39.739181
8488 06:55:39.742014 RX Delay 0 -> 252, step: 8
8489 06:55:39.745320 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8490 06:55:39.748444 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8491 06:55:39.755193 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8492 06:55:39.758629 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8493 06:55:39.761464 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8494 06:55:39.765546 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8495 06:55:39.768695 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8496 06:55:39.774877 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8497 06:55:39.778087 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8498 06:55:39.781732 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8499 06:55:39.784757 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8500 06:55:39.788618 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8501 06:55:39.794855 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8502 06:55:39.798148 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8503 06:55:39.801768 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8504 06:55:39.805067 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8505 06:55:39.805653 ==
8506 06:55:39.807864 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 06:55:39.814865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 06:55:39.815403 ==
8509 06:55:39.815852 DQS Delay:
8510 06:55:39.816270 DQS0 = 0, DQS1 = 0
8511 06:55:39.817889 DQM Delay:
8512 06:55:39.818323 DQM0 = 132, DQM1 = 126
8513 06:55:39.821654 DQ Delay:
8514 06:55:39.824477 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8515 06:55:39.827961 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8516 06:55:39.831411 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8517 06:55:39.834497 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8518 06:55:39.834930
8519 06:55:39.835269
8520 06:55:39.835589 ==
8521 06:55:39.837546 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 06:55:39.841142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 06:55:39.841619 ==
8524 06:55:39.844376
8525 06:55:39.844829
8526 06:55:39.845173 TX Vref Scan disable
8527 06:55:39.847939 == TX Byte 0 ==
8528 06:55:39.850995 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8529 06:55:39.854254 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8530 06:55:39.857623 == TX Byte 1 ==
8531 06:55:39.860987 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8532 06:55:39.864702 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8533 06:55:39.865242 ==
8534 06:55:39.867908 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 06:55:39.874355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 06:55:39.874883 ==
8537 06:55:39.886806
8538 06:55:39.889297 TX Vref early break, caculate TX vref
8539 06:55:39.892912 TX Vref=16, minBit 11, minWin=21, winSum=362
8540 06:55:39.896124 TX Vref=18, minBit 11, minWin=21, winSum=371
8541 06:55:39.899711 TX Vref=20, minBit 1, minWin=22, winSum=379
8542 06:55:39.902826 TX Vref=22, minBit 13, minWin=23, winSum=392
8543 06:55:39.909353 TX Vref=24, minBit 5, minWin=24, winSum=403
8544 06:55:39.912735 TX Vref=26, minBit 0, minWin=25, winSum=413
8545 06:55:39.915967 TX Vref=28, minBit 6, minWin=25, winSum=415
8546 06:55:39.919508 TX Vref=30, minBit 1, minWin=24, winSum=415
8547 06:55:39.922624 TX Vref=32, minBit 9, minWin=23, winSum=399
8548 06:55:39.925857 TX Vref=34, minBit 0, minWin=23, winSum=393
8549 06:55:39.932441 [TxChooseVref] Worse bit 6, Min win 25, Win sum 415, Final Vref 28
8550 06:55:39.932987
8551 06:55:39.935415 Final TX Range 0 Vref 28
8552 06:55:39.935847
8553 06:55:39.936185 ==
8554 06:55:39.939188 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 06:55:39.942521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 06:55:39.943036 ==
8557 06:55:39.943385
8558 06:55:39.943703
8559 06:55:39.945723 TX Vref Scan disable
8560 06:55:39.952386 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8561 06:55:39.952911 == TX Byte 0 ==
8562 06:55:39.956018 u2DelayCellOfst[0]=22 cells (6 PI)
8563 06:55:39.959833 u2DelayCellOfst[1]=15 cells (4 PI)
8564 06:55:39.962261 u2DelayCellOfst[2]=0 cells (0 PI)
8565 06:55:39.965695 u2DelayCellOfst[3]=7 cells (2 PI)
8566 06:55:39.969006 u2DelayCellOfst[4]=11 cells (3 PI)
8567 06:55:39.972172 u2DelayCellOfst[5]=22 cells (6 PI)
8568 06:55:39.975426 u2DelayCellOfst[6]=22 cells (6 PI)
8569 06:55:39.978934 u2DelayCellOfst[7]=7 cells (2 PI)
8570 06:55:39.982224 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8571 06:55:39.985346 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8572 06:55:39.988760 == TX Byte 1 ==
8573 06:55:39.992320 u2DelayCellOfst[8]=0 cells (0 PI)
8574 06:55:39.992866 u2DelayCellOfst[9]=7 cells (2 PI)
8575 06:55:39.995619 u2DelayCellOfst[10]=15 cells (4 PI)
8576 06:55:39.998858 u2DelayCellOfst[11]=11 cells (3 PI)
8577 06:55:40.002177 u2DelayCellOfst[12]=18 cells (5 PI)
8578 06:55:40.005528 u2DelayCellOfst[13]=22 cells (6 PI)
8579 06:55:40.009106 u2DelayCellOfst[14]=22 cells (6 PI)
8580 06:55:40.012131 u2DelayCellOfst[15]=22 cells (6 PI)
8581 06:55:40.018616 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8582 06:55:40.022180 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8583 06:55:40.022730 DramC Write-DBI on
8584 06:55:40.023074 ==
8585 06:55:40.025258 Dram Type= 6, Freq= 0, CH_1, rank 0
8586 06:55:40.031962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8587 06:55:40.032477 ==
8588 06:55:40.032814
8589 06:55:40.033121
8590 06:55:40.033417 TX Vref Scan disable
8591 06:55:40.035987 == TX Byte 0 ==
8592 06:55:40.038899 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8593 06:55:40.042274 == TX Byte 1 ==
8594 06:55:40.045840 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8595 06:55:40.049247 DramC Write-DBI off
8596 06:55:40.049834
8597 06:55:40.050180 [DATLAT]
8598 06:55:40.050555 Freq=1600, CH1 RK0
8599 06:55:40.050888
8600 06:55:40.052604 DATLAT Default: 0xf
8601 06:55:40.053037 0, 0xFFFF, sum = 0
8602 06:55:40.055620 1, 0xFFFF, sum = 0
8603 06:55:40.059207 2, 0xFFFF, sum = 0
8604 06:55:40.059646 3, 0xFFFF, sum = 0
8605 06:55:40.062484 4, 0xFFFF, sum = 0
8606 06:55:40.062935 5, 0xFFFF, sum = 0
8607 06:55:40.065815 6, 0xFFFF, sum = 0
8608 06:55:40.066349 7, 0xFFFF, sum = 0
8609 06:55:40.069132 8, 0xFFFF, sum = 0
8610 06:55:40.069772 9, 0xFFFF, sum = 0
8611 06:55:40.072775 10, 0xFFFF, sum = 0
8612 06:55:40.073311 11, 0xFFFF, sum = 0
8613 06:55:40.075961 12, 0xFFFF, sum = 0
8614 06:55:40.076492 13, 0x8FFF, sum = 0
8615 06:55:40.079267 14, 0x0, sum = 1
8616 06:55:40.079710 15, 0x0, sum = 2
8617 06:55:40.082534 16, 0x0, sum = 3
8618 06:55:40.082969 17, 0x0, sum = 4
8619 06:55:40.085733 best_step = 15
8620 06:55:40.086166
8621 06:55:40.086505 ==
8622 06:55:40.088809 Dram Type= 6, Freq= 0, CH_1, rank 0
8623 06:55:40.092391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8624 06:55:40.092918 ==
8625 06:55:40.093261 RX Vref Scan: 1
8626 06:55:40.095790
8627 06:55:40.096237 Set Vref Range= 24 -> 127
8628 06:55:40.096576
8629 06:55:40.098961 RX Vref 24 -> 127, step: 1
8630 06:55:40.099392
8631 06:55:40.102563 RX Delay 11 -> 252, step: 4
8632 06:55:40.103085
8633 06:55:40.105533 Set Vref, RX VrefLevel [Byte0]: 24
8634 06:55:40.109163 [Byte1]: 24
8635 06:55:40.109772
8636 06:55:40.112272 Set Vref, RX VrefLevel [Byte0]: 25
8637 06:55:40.115968 [Byte1]: 25
8638 06:55:40.116499
8639 06:55:40.118657 Set Vref, RX VrefLevel [Byte0]: 26
8640 06:55:40.121947 [Byte1]: 26
8641 06:55:40.126512
8642 06:55:40.126985 Set Vref, RX VrefLevel [Byte0]: 27
8643 06:55:40.129338 [Byte1]: 27
8644 06:55:40.133595
8645 06:55:40.134027 Set Vref, RX VrefLevel [Byte0]: 28
8646 06:55:40.137161 [Byte1]: 28
8647 06:55:40.141429
8648 06:55:40.141922 Set Vref, RX VrefLevel [Byte0]: 29
8649 06:55:40.144770 [Byte1]: 29
8650 06:55:40.149435
8651 06:55:40.150010 Set Vref, RX VrefLevel [Byte0]: 30
8652 06:55:40.152470 [Byte1]: 30
8653 06:55:40.156844
8654 06:55:40.157273 Set Vref, RX VrefLevel [Byte0]: 31
8655 06:55:40.159875 [Byte1]: 31
8656 06:55:40.164469
8657 06:55:40.164996 Set Vref, RX VrefLevel [Byte0]: 32
8658 06:55:40.167793 [Byte1]: 32
8659 06:55:40.172282
8660 06:55:40.172811 Set Vref, RX VrefLevel [Byte0]: 33
8661 06:55:40.175314 [Byte1]: 33
8662 06:55:40.179724
8663 06:55:40.180248 Set Vref, RX VrefLevel [Byte0]: 34
8664 06:55:40.182956 [Byte1]: 34
8665 06:55:40.187422
8666 06:55:40.187949 Set Vref, RX VrefLevel [Byte0]: 35
8667 06:55:40.190112 [Byte1]: 35
8668 06:55:40.194765
8669 06:55:40.195335 Set Vref, RX VrefLevel [Byte0]: 36
8670 06:55:40.198362 [Byte1]: 36
8671 06:55:40.202558
8672 06:55:40.203085 Set Vref, RX VrefLevel [Byte0]: 37
8673 06:55:40.205559 [Byte1]: 37
8674 06:55:40.210216
8675 06:55:40.210745 Set Vref, RX VrefLevel [Byte0]: 38
8676 06:55:40.212872 [Byte1]: 38
8677 06:55:40.217383
8678 06:55:40.217866 Set Vref, RX VrefLevel [Byte0]: 39
8679 06:55:40.221126 [Byte1]: 39
8680 06:55:40.225160
8681 06:55:40.225757 Set Vref, RX VrefLevel [Byte0]: 40
8682 06:55:40.228593 [Byte1]: 40
8683 06:55:40.233115
8684 06:55:40.233599 Set Vref, RX VrefLevel [Byte0]: 41
8685 06:55:40.236185 [Byte1]: 41
8686 06:55:40.240211
8687 06:55:40.240644 Set Vref, RX VrefLevel [Byte0]: 42
8688 06:55:40.243918 [Byte1]: 42
8689 06:55:40.248055
8690 06:55:40.248578 Set Vref, RX VrefLevel [Byte0]: 43
8691 06:55:40.251247 [Byte1]: 43
8692 06:55:40.255630
8693 06:55:40.256163 Set Vref, RX VrefLevel [Byte0]: 44
8694 06:55:40.259100 [Byte1]: 44
8695 06:55:40.263036
8696 06:55:40.263467 Set Vref, RX VrefLevel [Byte0]: 45
8697 06:55:40.266374 [Byte1]: 45
8698 06:55:40.271102
8699 06:55:40.271626 Set Vref, RX VrefLevel [Byte0]: 46
8700 06:55:40.274432 [Byte1]: 46
8701 06:55:40.278968
8702 06:55:40.279489 Set Vref, RX VrefLevel [Byte0]: 47
8703 06:55:40.281676 [Byte1]: 47
8704 06:55:40.286284
8705 06:55:40.286809 Set Vref, RX VrefLevel [Byte0]: 48
8706 06:55:40.289462 [Byte1]: 48
8707 06:55:40.293855
8708 06:55:40.294380 Set Vref, RX VrefLevel [Byte0]: 49
8709 06:55:40.297230 [Byte1]: 49
8710 06:55:40.301356
8711 06:55:40.301930 Set Vref, RX VrefLevel [Byte0]: 50
8712 06:55:40.304757 [Byte1]: 50
8713 06:55:40.309126
8714 06:55:40.309816 Set Vref, RX VrefLevel [Byte0]: 51
8715 06:55:40.312286 [Byte1]: 51
8716 06:55:40.316534
8717 06:55:40.316966 Set Vref, RX VrefLevel [Byte0]: 52
8718 06:55:40.320204 [Byte1]: 52
8719 06:55:40.324271
8720 06:55:40.324795 Set Vref, RX VrefLevel [Byte0]: 53
8721 06:55:40.327931 [Byte1]: 53
8722 06:55:40.331628
8723 06:55:40.332057 Set Vref, RX VrefLevel [Byte0]: 54
8724 06:55:40.335033 [Byte1]: 54
8725 06:55:40.339207
8726 06:55:40.339629 Set Vref, RX VrefLevel [Byte0]: 55
8727 06:55:40.342707 [Byte1]: 55
8728 06:55:40.347036
8729 06:55:40.347463 Set Vref, RX VrefLevel [Byte0]: 56
8730 06:55:40.350411 [Byte1]: 56
8731 06:55:40.354922
8732 06:55:40.355489 Set Vref, RX VrefLevel [Byte0]: 57
8733 06:55:40.357869 [Byte1]: 57
8734 06:55:40.362292
8735 06:55:40.362910 Set Vref, RX VrefLevel [Byte0]: 58
8736 06:55:40.365648 [Byte1]: 58
8737 06:55:40.369818
8738 06:55:40.370458 Set Vref, RX VrefLevel [Byte0]: 59
8739 06:55:40.373237 [Byte1]: 59
8740 06:55:40.377698
8741 06:55:40.378219 Set Vref, RX VrefLevel [Byte0]: 60
8742 06:55:40.380825 [Byte1]: 60
8743 06:55:40.385253
8744 06:55:40.385826 Set Vref, RX VrefLevel [Byte0]: 61
8745 06:55:40.388596 [Byte1]: 61
8746 06:55:40.392623
8747 06:55:40.393051 Set Vref, RX VrefLevel [Byte0]: 62
8748 06:55:40.396114 [Byte1]: 62
8749 06:55:40.400549
8750 06:55:40.401072 Set Vref, RX VrefLevel [Byte0]: 63
8751 06:55:40.403868 [Byte1]: 63
8752 06:55:40.408017
8753 06:55:40.408543 Set Vref, RX VrefLevel [Byte0]: 64
8754 06:55:40.411614 [Byte1]: 64
8755 06:55:40.415969
8756 06:55:40.416549 Set Vref, RX VrefLevel [Byte0]: 65
8757 06:55:40.418846 [Byte1]: 65
8758 06:55:40.422996
8759 06:55:40.423524 Set Vref, RX VrefLevel [Byte0]: 66
8760 06:55:40.426568 [Byte1]: 66
8761 06:55:40.431121
8762 06:55:40.431643 Set Vref, RX VrefLevel [Byte0]: 67
8763 06:55:40.433985 [Byte1]: 67
8764 06:55:40.438705
8765 06:55:40.439246 Set Vref, RX VrefLevel [Byte0]: 68
8766 06:55:40.441596 [Byte1]: 68
8767 06:55:40.446195
8768 06:55:40.446723 Set Vref, RX VrefLevel [Byte0]: 69
8769 06:55:40.449240 [Byte1]: 69
8770 06:55:40.453726
8771 06:55:40.454246 Set Vref, RX VrefLevel [Byte0]: 70
8772 06:55:40.457108 [Byte1]: 70
8773 06:55:40.461463
8774 06:55:40.462036 Set Vref, RX VrefLevel [Byte0]: 71
8775 06:55:40.464489 [Byte1]: 71
8776 06:55:40.468965
8777 06:55:40.469522 Final RX Vref Byte 0 = 57 to rank0
8778 06:55:40.472499 Final RX Vref Byte 1 = 55 to rank0
8779 06:55:40.475495 Final RX Vref Byte 0 = 57 to rank1
8780 06:55:40.478773 Final RX Vref Byte 1 = 55 to rank1==
8781 06:55:40.481897 Dram Type= 6, Freq= 0, CH_1, rank 0
8782 06:55:40.488831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 06:55:40.489406 ==
8784 06:55:40.489824 DQS Delay:
8785 06:55:40.491720 DQS0 = 0, DQS1 = 0
8786 06:55:40.492144 DQM Delay:
8787 06:55:40.492482 DQM0 = 131, DQM1 = 123
8788 06:55:40.495297 DQ Delay:
8789 06:55:40.498477 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =130
8790 06:55:40.502006 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8791 06:55:40.504978 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8792 06:55:40.508340 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8793 06:55:40.508765
8794 06:55:40.509153
8795 06:55:40.509466
8796 06:55:40.511564 [DramC_TX_OE_Calibration] TA2
8797 06:55:40.514836 Original DQ_B0 (3 6) =30, OEN = 27
8798 06:55:40.518318 Original DQ_B1 (3 6) =30, OEN = 27
8799 06:55:40.521628 24, 0x0, End_B0=24 End_B1=24
8800 06:55:40.522059 25, 0x0, End_B0=25 End_B1=25
8801 06:55:40.525101 26, 0x0, End_B0=26 End_B1=26
8802 06:55:40.528335 27, 0x0, End_B0=27 End_B1=27
8803 06:55:40.531582 28, 0x0, End_B0=28 End_B1=28
8804 06:55:40.534845 29, 0x0, End_B0=29 End_B1=29
8805 06:55:40.535283 30, 0x0, End_B0=30 End_B1=30
8806 06:55:40.538192 31, 0x4141, End_B0=30 End_B1=30
8807 06:55:40.541554 Byte0 end_step=30 best_step=27
8808 06:55:40.544913 Byte1 end_step=30 best_step=27
8809 06:55:40.548175 Byte0 TX OE(2T, 0.5T) = (3, 3)
8810 06:55:40.551414 Byte1 TX OE(2T, 0.5T) = (3, 3)
8811 06:55:40.551852
8812 06:55:40.552194
8813 06:55:40.557966 [DQSOSCAuto] RK0, (LSB)MR18= 0x70b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8814 06:55:40.561311 CH1 RK0: MR19=303, MR18=70B
8815 06:55:40.568249 CH1_RK0: MR19=0x303, MR18=0x70B, DQSOSC=404, MR23=63, INC=22, DEC=15
8816 06:55:40.568744
8817 06:55:40.571511 ----->DramcWriteLeveling(PI) begin...
8818 06:55:40.571951 ==
8819 06:55:40.574420 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 06:55:40.577802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 06:55:40.578276 ==
8822 06:55:40.580986 Write leveling (Byte 0): 23 => 23
8823 06:55:40.584339 Write leveling (Byte 1): 29 => 29
8824 06:55:40.587632 DramcWriteLeveling(PI) end<-----
8825 06:55:40.588062
8826 06:55:40.588401 ==
8827 06:55:40.591272 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 06:55:40.594309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 06:55:40.594743 ==
8830 06:55:40.598022 [Gating] SW mode calibration
8831 06:55:40.604734 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8832 06:55:40.611034 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8833 06:55:40.614462 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 06:55:40.621198 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 06:55:40.624577 1 4 8 | B1->B0 | 2323 3333 | 1 1 | (1 1) (1 1)
8836 06:55:40.627580 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8837 06:55:40.634326 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 06:55:40.637564 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 06:55:40.641039 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 06:55:40.644559 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 06:55:40.651130 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 06:55:40.654279 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8843 06:55:40.657668 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
8844 06:55:40.664008 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8845 06:55:40.667203 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 06:55:40.670643 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 06:55:40.677451 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 06:55:40.680998 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 06:55:40.684226 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 06:55:40.690913 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 06:55:40.693983 1 6 8 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
8852 06:55:40.697705 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8853 06:55:40.704380 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 06:55:40.707788 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 06:55:40.710719 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 06:55:40.717197 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 06:55:40.721011 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 06:55:40.724487 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8859 06:55:40.731003 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8860 06:55:40.733976 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8861 06:55:40.737375 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 06:55:40.744098 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 06:55:40.747245 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 06:55:40.750695 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 06:55:40.756869 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 06:55:40.760205 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 06:55:40.763452 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 06:55:40.770151 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 06:55:40.773766 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 06:55:40.776990 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 06:55:40.783536 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 06:55:40.786764 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 06:55:40.789993 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 06:55:40.796733 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8875 06:55:40.800308 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8876 06:55:40.803591 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8877 06:55:40.806792 Total UI for P1: 0, mck2ui 16
8878 06:55:40.810198 best dqsien dly found for B0: ( 1, 9, 6)
8879 06:55:40.813570 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8880 06:55:40.816761 Total UI for P1: 0, mck2ui 16
8881 06:55:40.820061 best dqsien dly found for B1: ( 1, 9, 10)
8882 06:55:40.823347 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8883 06:55:40.830365 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8884 06:55:40.830890
8885 06:55:40.833656 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8886 06:55:40.836794 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8887 06:55:40.839722 [Gating] SW calibration Done
8888 06:55:40.840152 ==
8889 06:55:40.843350 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 06:55:40.846428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 06:55:40.846860 ==
8892 06:55:40.847203 RX Vref Scan: 0
8893 06:55:40.849573
8894 06:55:40.849992 RX Vref 0 -> 0, step: 1
8895 06:55:40.850323
8896 06:55:40.853187 RX Delay 0 -> 252, step: 8
8897 06:55:40.856407 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8898 06:55:40.859620 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8899 06:55:40.866195 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8900 06:55:40.869699 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8901 06:55:40.872954 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8902 06:55:40.876547 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8903 06:55:40.879723 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8904 06:55:40.886542 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8905 06:55:40.890042 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8906 06:55:40.893344 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8907 06:55:40.896542 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8908 06:55:40.899661 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8909 06:55:40.906413 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8910 06:55:40.909619 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8911 06:55:40.912952 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8912 06:55:40.916013 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8913 06:55:40.916534 ==
8914 06:55:40.919501 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 06:55:40.926007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 06:55:40.926537 ==
8917 06:55:40.926882 DQS Delay:
8918 06:55:40.929507 DQS0 = 0, DQS1 = 0
8919 06:55:40.930051 DQM Delay:
8920 06:55:40.932500 DQM0 = 129, DQM1 = 127
8921 06:55:40.933023 DQ Delay:
8922 06:55:40.936026 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8923 06:55:40.939507 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8924 06:55:40.942373 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8925 06:55:40.945874 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8926 06:55:40.946334
8927 06:55:40.946676
8928 06:55:40.946988 ==
8929 06:55:40.949003 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 06:55:40.955745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 06:55:40.956274 ==
8932 06:55:40.956616
8933 06:55:40.956928
8934 06:55:40.957230 TX Vref Scan disable
8935 06:55:40.959415 == TX Byte 0 ==
8936 06:55:40.962171 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8937 06:55:40.968939 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8938 06:55:40.969542 == TX Byte 1 ==
8939 06:55:40.972007 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8940 06:55:40.979012 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8941 06:55:40.979536 ==
8942 06:55:40.982302 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 06:55:40.985581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 06:55:40.986129 ==
8945 06:55:40.998613
8946 06:55:41.001967 TX Vref early break, caculate TX vref
8947 06:55:41.005291 TX Vref=16, minBit 0, minWin=22, winSum=374
8948 06:55:41.008519 TX Vref=18, minBit 0, minWin=22, winSum=380
8949 06:55:41.011961 TX Vref=20, minBit 0, minWin=23, winSum=394
8950 06:55:41.015068 TX Vref=22, minBit 8, minWin=23, winSum=399
8951 06:55:41.018643 TX Vref=24, minBit 0, minWin=25, winSum=409
8952 06:55:41.025290 TX Vref=26, minBit 0, minWin=25, winSum=416
8953 06:55:41.028594 TX Vref=28, minBit 0, minWin=24, winSum=417
8954 06:55:41.031563 TX Vref=30, minBit 0, minWin=24, winSum=410
8955 06:55:41.035002 TX Vref=32, minBit 5, minWin=23, winSum=403
8956 06:55:41.038291 TX Vref=34, minBit 1, minWin=23, winSum=394
8957 06:55:41.044743 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
8958 06:55:41.045251
8959 06:55:41.047916 Final TX Range 0 Vref 26
8960 06:55:41.048341
8961 06:55:41.048676 ==
8962 06:55:41.051632 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 06:55:41.054974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 06:55:41.055403 ==
8965 06:55:41.055736
8966 06:55:41.056046
8967 06:55:41.058169 TX Vref Scan disable
8968 06:55:41.064905 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8969 06:55:41.065414 == TX Byte 0 ==
8970 06:55:41.068213 u2DelayCellOfst[0]=18 cells (5 PI)
8971 06:55:41.071592 u2DelayCellOfst[1]=11 cells (3 PI)
8972 06:55:41.074905 u2DelayCellOfst[2]=0 cells (0 PI)
8973 06:55:41.078039 u2DelayCellOfst[3]=7 cells (2 PI)
8974 06:55:41.081541 u2DelayCellOfst[4]=7 cells (2 PI)
8975 06:55:41.084731 u2DelayCellOfst[5]=22 cells (6 PI)
8976 06:55:41.087835 u2DelayCellOfst[6]=22 cells (6 PI)
8977 06:55:41.088270 u2DelayCellOfst[7]=3 cells (1 PI)
8978 06:55:41.094623 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8979 06:55:41.097596 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8980 06:55:41.101559 == TX Byte 1 ==
8981 06:55:41.102118 u2DelayCellOfst[8]=0 cells (0 PI)
8982 06:55:41.104543 u2DelayCellOfst[9]=3 cells (1 PI)
8983 06:55:41.107988 u2DelayCellOfst[10]=11 cells (3 PI)
8984 06:55:41.111007 u2DelayCellOfst[11]=3 cells (1 PI)
8985 06:55:41.114434 u2DelayCellOfst[12]=11 cells (3 PI)
8986 06:55:41.117937 u2DelayCellOfst[13]=15 cells (4 PI)
8987 06:55:41.121049 u2DelayCellOfst[14]=15 cells (4 PI)
8988 06:55:41.123909 u2DelayCellOfst[15]=15 cells (4 PI)
8989 06:55:41.127910 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8990 06:55:41.134395 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8991 06:55:41.134933 DramC Write-DBI on
8992 06:55:41.135285 ==
8993 06:55:41.137582 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 06:55:41.140832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 06:55:41.144204 ==
8996 06:55:41.144870
8997 06:55:41.145522
8998 06:55:41.145959 TX Vref Scan disable
8999 06:55:41.147743 == TX Byte 0 ==
9000 06:55:41.150988 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9001 06:55:41.154439 == TX Byte 1 ==
9002 06:55:41.157998 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9003 06:55:41.161433 DramC Write-DBI off
9004 06:55:41.162005
9005 06:55:41.162350 [DATLAT]
9006 06:55:41.162672 Freq=1600, CH1 RK1
9007 06:55:41.162981
9008 06:55:41.164230 DATLAT Default: 0xf
9009 06:55:41.164602 0, 0xFFFF, sum = 0
9010 06:55:41.167833 1, 0xFFFF, sum = 0
9011 06:55:41.170772 2, 0xFFFF, sum = 0
9012 06:55:41.171210 3, 0xFFFF, sum = 0
9013 06:55:41.174384 4, 0xFFFF, sum = 0
9014 06:55:41.174917 5, 0xFFFF, sum = 0
9015 06:55:41.178098 6, 0xFFFF, sum = 0
9016 06:55:41.178629 7, 0xFFFF, sum = 0
9017 06:55:41.181229 8, 0xFFFF, sum = 0
9018 06:55:41.181812 9, 0xFFFF, sum = 0
9019 06:55:41.184276 10, 0xFFFF, sum = 0
9020 06:55:41.184805 11, 0xFFFF, sum = 0
9021 06:55:41.187672 12, 0xFFFF, sum = 0
9022 06:55:41.188201 13, 0x8FFF, sum = 0
9023 06:55:41.190698 14, 0x0, sum = 1
9024 06:55:41.191135 15, 0x0, sum = 2
9025 06:55:41.194367 16, 0x0, sum = 3
9026 06:55:41.194823 17, 0x0, sum = 4
9027 06:55:41.197620 best_step = 15
9028 06:55:41.198146
9029 06:55:41.198488 ==
9030 06:55:41.200736 Dram Type= 6, Freq= 0, CH_1, rank 1
9031 06:55:41.204054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9032 06:55:41.204597 ==
9033 06:55:41.207224 RX Vref Scan: 0
9034 06:55:41.207652
9035 06:55:41.207992 RX Vref 0 -> 0, step: 1
9036 06:55:41.208313
9037 06:55:41.210498 RX Delay 3 -> 252, step: 4
9038 06:55:41.214046 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9039 06:55:41.220596 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9040 06:55:41.223784 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9041 06:55:41.227236 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9042 06:55:41.230558 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9043 06:55:41.233626 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9044 06:55:41.240180 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9045 06:55:41.244107 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9046 06:55:41.246994 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9047 06:55:41.250431 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9048 06:55:41.253742 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9049 06:55:41.260852 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9050 06:55:41.263884 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
9051 06:55:41.267383 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9052 06:55:41.270392 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9053 06:55:41.277308 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9054 06:55:41.277892 ==
9055 06:55:41.280493 Dram Type= 6, Freq= 0, CH_1, rank 1
9056 06:55:41.283945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9057 06:55:41.284474 ==
9058 06:55:41.284820 DQS Delay:
9059 06:55:41.286873 DQS0 = 0, DQS1 = 0
9060 06:55:41.287304 DQM Delay:
9061 06:55:41.290254 DQM0 = 127, DQM1 = 125
9062 06:55:41.290681 DQ Delay:
9063 06:55:41.294016 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =124
9064 06:55:41.297134 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9065 06:55:41.300184 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9066 06:55:41.303947 DQ12 =130, DQ13 =134, DQ14 =130, DQ15 =134
9067 06:55:41.304477
9068 06:55:41.304817
9069 06:55:41.306894
9070 06:55:41.307321 [DramC_TX_OE_Calibration] TA2
9071 06:55:41.309992 Original DQ_B0 (3 6) =30, OEN = 27
9072 06:55:41.313413 Original DQ_B1 (3 6) =30, OEN = 27
9073 06:55:41.316680 24, 0x0, End_B0=24 End_B1=24
9074 06:55:41.320227 25, 0x0, End_B0=25 End_B1=25
9075 06:55:41.323008 26, 0x0, End_B0=26 End_B1=26
9076 06:55:41.323449 27, 0x0, End_B0=27 End_B1=27
9077 06:55:41.326327 28, 0x0, End_B0=28 End_B1=28
9078 06:55:41.329902 29, 0x0, End_B0=29 End_B1=29
9079 06:55:41.333625 30, 0x0, End_B0=30 End_B1=30
9080 06:55:41.336691 31, 0x4141, End_B0=30 End_B1=30
9081 06:55:41.337130 Byte0 end_step=30 best_step=27
9082 06:55:41.340026 Byte1 end_step=30 best_step=27
9083 06:55:41.343337 Byte0 TX OE(2T, 0.5T) = (3, 3)
9084 06:55:41.346372 Byte1 TX OE(2T, 0.5T) = (3, 3)
9085 06:55:41.346818
9086 06:55:41.347162
9087 06:55:41.353288 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9088 06:55:41.356689 CH1 RK1: MR19=303, MR18=F1B
9089 06:55:41.362904 CH1_RK1: MR19=0x303, MR18=0xF1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9090 06:55:41.366901 [RxdqsGatingPostProcess] freq 1600
9091 06:55:41.373153 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9092 06:55:41.376499 best DQS0 dly(2T, 0.5T) = (1, 1)
9093 06:55:41.377028 best DQS1 dly(2T, 0.5T) = (1, 1)
9094 06:55:41.379428 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9095 06:55:41.382709 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9096 06:55:41.386227 best DQS0 dly(2T, 0.5T) = (1, 1)
9097 06:55:41.389892 best DQS1 dly(2T, 0.5T) = (1, 1)
9098 06:55:41.393246 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9099 06:55:41.396511 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9100 06:55:41.399929 Pre-setting of DQS Precalculation
9101 06:55:41.402965 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9102 06:55:41.413250 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9103 06:55:41.419575 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9104 06:55:41.420103
9105 06:55:41.420448
9106 06:55:41.422794 [Calibration Summary] 3200 Mbps
9107 06:55:41.423225 CH 0, Rank 0
9108 06:55:41.426143 SW Impedance : PASS
9109 06:55:41.426672 DUTY Scan : NO K
9110 06:55:41.429298 ZQ Calibration : PASS
9111 06:55:41.432755 Jitter Meter : NO K
9112 06:55:41.433277 CBT Training : PASS
9113 06:55:41.435773 Write leveling : PASS
9114 06:55:41.439196 RX DQS gating : PASS
9115 06:55:41.439626 RX DQ/DQS(RDDQC) : PASS
9116 06:55:41.442117 TX DQ/DQS : PASS
9117 06:55:41.445818 RX DATLAT : PASS
9118 06:55:41.446259 RX DQ/DQS(Engine): PASS
9119 06:55:41.449047 TX OE : PASS
9120 06:55:41.449515 All Pass.
9121 06:55:41.449934
9122 06:55:41.452551 CH 0, Rank 1
9123 06:55:41.453081 SW Impedance : PASS
9124 06:55:41.455924 DUTY Scan : NO K
9125 06:55:41.459111 ZQ Calibration : PASS
9126 06:55:41.459641 Jitter Meter : NO K
9127 06:55:41.462185 CBT Training : PASS
9128 06:55:41.465861 Write leveling : PASS
9129 06:55:41.466389 RX DQS gating : PASS
9130 06:55:41.468873 RX DQ/DQS(RDDQC) : PASS
9131 06:55:41.472087 TX DQ/DQS : PASS
9132 06:55:41.472523 RX DATLAT : PASS
9133 06:55:41.475414 RX DQ/DQS(Engine): PASS
9134 06:55:41.475847 TX OE : PASS
9135 06:55:41.478848 All Pass.
9136 06:55:41.479376
9137 06:55:41.479754 CH 1, Rank 0
9138 06:55:41.482057 SW Impedance : PASS
9139 06:55:41.482489 DUTY Scan : NO K
9140 06:55:41.485369 ZQ Calibration : PASS
9141 06:55:41.488992 Jitter Meter : NO K
9142 06:55:41.489660 CBT Training : PASS
9143 06:55:41.492226 Write leveling : PASS
9144 06:55:41.495552 RX DQS gating : PASS
9145 06:55:41.495984 RX DQ/DQS(RDDQC) : PASS
9146 06:55:41.498959 TX DQ/DQS : PASS
9147 06:55:41.502458 RX DATLAT : PASS
9148 06:55:41.502987 RX DQ/DQS(Engine): PASS
9149 06:55:41.505877 TX OE : PASS
9150 06:55:41.506432 All Pass.
9151 06:55:41.506774
9152 06:55:41.508851 CH 1, Rank 1
9153 06:55:41.509380 SW Impedance : PASS
9154 06:55:41.511739 DUTY Scan : NO K
9155 06:55:41.515475 ZQ Calibration : PASS
9156 06:55:41.516003 Jitter Meter : NO K
9157 06:55:41.518580 CBT Training : PASS
9158 06:55:41.522138 Write leveling : PASS
9159 06:55:41.522661 RX DQS gating : PASS
9160 06:55:41.525674 RX DQ/DQS(RDDQC) : PASS
9161 06:55:41.528957 TX DQ/DQS : PASS
9162 06:55:41.529527 RX DATLAT : PASS
9163 06:55:41.532211 RX DQ/DQS(Engine): PASS
9164 06:55:41.532742 TX OE : PASS
9165 06:55:41.534908 All Pass.
9166 06:55:41.535339
9167 06:55:41.535681 DramC Write-DBI on
9168 06:55:41.538563 PER_BANK_REFRESH: Hybrid Mode
9169 06:55:41.542240 TX_TRACKING: ON
9170 06:55:41.548395 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9171 06:55:41.558666 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9172 06:55:41.565233 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9173 06:55:41.568529 [FAST_K] Save calibration result to emmc
9174 06:55:41.571368 sync common calibartion params.
9175 06:55:41.571807 sync cbt_mode0:1, 1:1
9176 06:55:41.575015 dram_init: ddr_geometry: 2
9177 06:55:41.578182 dram_init: ddr_geometry: 2
9178 06:55:41.581291 dram_init: ddr_geometry: 2
9179 06:55:41.581753 0:dram_rank_size:100000000
9180 06:55:41.585053 1:dram_rank_size:100000000
9181 06:55:41.591564 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9182 06:55:41.592099 DFS_SHUFFLE_HW_MODE: ON
9183 06:55:41.598353 dramc_set_vcore_voltage set vcore to 725000
9184 06:55:41.598834 Read voltage for 1600, 0
9185 06:55:41.601631 Vio18 = 0
9186 06:55:41.602062 Vcore = 725000
9187 06:55:41.602404 Vdram = 0
9188 06:55:41.604950 Vddq = 0
9189 06:55:41.605377 Vmddr = 0
9190 06:55:41.608140 switch to 3200 Mbps bootup
9191 06:55:41.608606 [DramcRunTimeConfig]
9192 06:55:41.608965 PHYPLL
9193 06:55:41.611567 DPM_CONTROL_AFTERK: ON
9194 06:55:41.614793 PER_BANK_REFRESH: ON
9195 06:55:41.615356 REFRESH_OVERHEAD_REDUCTION: ON
9196 06:55:41.618224 CMD_PICG_NEW_MODE: OFF
9197 06:55:41.621645 XRTWTW_NEW_MODE: ON
9198 06:55:41.622168 XRTRTR_NEW_MODE: ON
9199 06:55:41.624436 TX_TRACKING: ON
9200 06:55:41.625003 RDSEL_TRACKING: OFF
9201 06:55:41.627918 DQS Precalculation for DVFS: ON
9202 06:55:41.628487 RX_TRACKING: OFF
9203 06:55:41.631242 HW_GATING DBG: ON
9204 06:55:41.631978 ZQCS_ENABLE_LP4: ON
9205 06:55:41.634189 RX_PICG_NEW_MODE: ON
9206 06:55:41.637648 TX_PICG_NEW_MODE: ON
9207 06:55:41.638173 ENABLE_RX_DCM_DPHY: ON
9208 06:55:41.641040 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9209 06:55:41.644918 DUMMY_READ_FOR_TRACKING: OFF
9210 06:55:41.647766 !!! SPM_CONTROL_AFTERK: OFF
9211 06:55:41.648428 !!! SPM could not control APHY
9212 06:55:41.651169 IMPEDANCE_TRACKING: ON
9213 06:55:41.654067 TEMP_SENSOR: ON
9214 06:55:41.654684 HW_SAVE_FOR_SR: OFF
9215 06:55:41.657627 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9216 06:55:41.661247 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9217 06:55:41.664525 Read ODT Tracking: ON
9218 06:55:41.665248 Refresh Rate DeBounce: ON
9219 06:55:41.667767 DFS_NO_QUEUE_FLUSH: ON
9220 06:55:41.670927 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9221 06:55:41.674207 ENABLE_DFS_RUNTIME_MRW: OFF
9222 06:55:41.674636 DDR_RESERVE_NEW_MODE: ON
9223 06:55:41.677592 MR_CBT_SWITCH_FREQ: ON
9224 06:55:41.680932 =========================
9225 06:55:41.698884 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9226 06:55:41.702471 dram_init: ddr_geometry: 2
9227 06:55:41.720546 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9228 06:55:41.724079 dram_init: dram init end (result: 0)
9229 06:55:41.730437 DRAM-K: Full calibration passed in 24564 msecs
9230 06:55:41.733607 MRC: failed to locate region type 0.
9231 06:55:41.734141 DRAM rank0 size:0x100000000,
9232 06:55:41.737132 DRAM rank1 size=0x100000000
9233 06:55:41.746789 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9234 06:55:41.753864 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9235 06:55:41.760370 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9236 06:55:41.767126 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9237 06:55:41.770217 DRAM rank0 size:0x100000000,
9238 06:55:41.773437 DRAM rank1 size=0x100000000
9239 06:55:41.774029 CBMEM:
9240 06:55:41.776998 IMD: root @ 0xfffff000 254 entries.
9241 06:55:41.780378 IMD: root @ 0xffffec00 62 entries.
9242 06:55:41.783592 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9243 06:55:41.787077 WARNING: RO_VPD is uninitialized or empty.
9244 06:55:41.793700 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9245 06:55:41.800567 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9246 06:55:41.813439 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9247 06:55:41.824769 BS: romstage times (exec / console): total (unknown) / 24028 ms
9248 06:55:41.825313
9249 06:55:41.825725
9250 06:55:41.834894 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9251 06:55:41.838062 ARM64: Exception handlers installed.
9252 06:55:41.841573 ARM64: Testing exception
9253 06:55:41.844580 ARM64: Done test exception
9254 06:55:41.845011 Enumerating buses...
9255 06:55:41.848003 Show all devs... Before device enumeration.
9256 06:55:41.850813 Root Device: enabled 1
9257 06:55:41.854397 CPU_CLUSTER: 0: enabled 1
9258 06:55:41.854844 CPU: 00: enabled 1
9259 06:55:41.857540 Compare with tree...
9260 06:55:41.858234 Root Device: enabled 1
9261 06:55:41.861049 CPU_CLUSTER: 0: enabled 1
9262 06:55:41.864066 CPU: 00: enabled 1
9263 06:55:41.864732 Root Device scanning...
9264 06:55:41.867410 scan_static_bus for Root Device
9265 06:55:41.870784 CPU_CLUSTER: 0 enabled
9266 06:55:41.873950 scan_static_bus for Root Device done
9267 06:55:41.877588 scan_bus: bus Root Device finished in 8 msecs
9268 06:55:41.878239 done
9269 06:55:41.884321 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9270 06:55:41.887387 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9271 06:55:41.894405 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9272 06:55:41.897644 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9273 06:55:41.901101 Allocating resources...
9274 06:55:41.904112 Reading resources...
9275 06:55:41.907280 Root Device read_resources bus 0 link: 0
9276 06:55:41.907712 DRAM rank0 size:0x100000000,
9277 06:55:41.910902 DRAM rank1 size=0x100000000
9278 06:55:41.913990 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9279 06:55:41.917296 CPU: 00 missing read_resources
9280 06:55:41.923921 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9281 06:55:41.927275 Root Device read_resources bus 0 link: 0 done
9282 06:55:41.927808 Done reading resources.
9283 06:55:41.933953 Show resources in subtree (Root Device)...After reading.
9284 06:55:41.936974 Root Device child on link 0 CPU_CLUSTER: 0
9285 06:55:41.940113 CPU_CLUSTER: 0 child on link 0 CPU: 00
9286 06:55:41.950383 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9287 06:55:41.950913 CPU: 00
9288 06:55:41.953617 Root Device assign_resources, bus 0 link: 0
9289 06:55:41.957234 CPU_CLUSTER: 0 missing set_resources
9290 06:55:41.963404 Root Device assign_resources, bus 0 link: 0 done
9291 06:55:41.963914 Done setting resources.
9292 06:55:41.970006 Show resources in subtree (Root Device)...After assigning values.
9293 06:55:41.973538 Root Device child on link 0 CPU_CLUSTER: 0
9294 06:55:41.977076 CPU_CLUSTER: 0 child on link 0 CPU: 00
9295 06:55:41.987006 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9296 06:55:41.987540 CPU: 00
9297 06:55:41.990748 Done allocating resources.
9298 06:55:41.996971 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9299 06:55:41.997523 Enabling resources...
9300 06:55:41.997874 done.
9301 06:55:42.003538 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9302 06:55:42.004122 Initializing devices...
9303 06:55:42.006834 Root Device init
9304 06:55:42.007365 init hardware done!
9305 06:55:42.010124 0x00000018: ctrlr->caps
9306 06:55:42.013278 52.000 MHz: ctrlr->f_max
9307 06:55:42.013748 0.400 MHz: ctrlr->f_min
9308 06:55:42.016841 0x40ff8080: ctrlr->voltages
9309 06:55:42.020091 sclk: 390625
9310 06:55:42.020616 Bus Width = 1
9311 06:55:42.020958 sclk: 390625
9312 06:55:42.023662 Bus Width = 1
9313 06:55:42.024189 Early init status = 3
9314 06:55:42.029985 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9315 06:55:42.033382 in-header: 03 fc 00 00 01 00 00 00
9316 06:55:42.036391 in-data: 00
9317 06:55:42.039532 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9318 06:55:42.045167 in-header: 03 fd 00 00 00 00 00 00
9319 06:55:42.048467 in-data:
9320 06:55:42.051378 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9321 06:55:42.056449 in-header: 03 fc 00 00 01 00 00 00
9322 06:55:42.059705 in-data: 00
9323 06:55:42.062744 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9324 06:55:42.068394 in-header: 03 fd 00 00 00 00 00 00
9325 06:55:42.071576 in-data:
9326 06:55:42.074648 [SSUSB] Setting up USB HOST controller...
9327 06:55:42.078245 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9328 06:55:42.081266 [SSUSB] phy power-on done.
9329 06:55:42.084908 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9330 06:55:42.091734 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9331 06:55:42.095031 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9332 06:55:42.101582 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9333 06:55:42.108204 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9334 06:55:42.114948 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9335 06:55:42.121637 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9336 06:55:42.128155 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9337 06:55:42.131821 SPM: binary array size = 0x9dc
9338 06:55:42.134246 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9339 06:55:42.141086 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9340 06:55:42.147688 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9341 06:55:42.151073 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9342 06:55:42.157583 configure_display: Starting display init
9343 06:55:42.191818 anx7625_power_on_init: Init interface.
9344 06:55:42.194833 anx7625_disable_pd_protocol: Disabled PD feature.
9345 06:55:42.198159 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9346 06:55:42.226225 anx7625_start_dp_work: Secure OCM version=00
9347 06:55:42.229545 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9348 06:55:42.244075 sp_tx_get_edid_block: EDID Block = 1
9349 06:55:42.346682 Extracted contents:
9350 06:55:42.350380 header: 00 ff ff ff ff ff ff 00
9351 06:55:42.352954 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9352 06:55:42.356486 version: 01 04
9353 06:55:42.359980 basic params: 95 1f 11 78 0a
9354 06:55:42.363371 chroma info: 76 90 94 55 54 90 27 21 50 54
9355 06:55:42.366472 established: 00 00 00
9356 06:55:42.372986 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9357 06:55:42.376565 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9358 06:55:42.383047 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9359 06:55:42.389531 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9360 06:55:42.396027 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9361 06:55:42.399448 extensions: 00
9362 06:55:42.399866 checksum: fb
9363 06:55:42.400199
9364 06:55:42.402491 Manufacturer: IVO Model 57d Serial Number 0
9365 06:55:42.405858 Made week 0 of 2020
9366 06:55:42.406279 EDID version: 1.4
9367 06:55:42.409364 Digital display
9368 06:55:42.413066 6 bits per primary color channel
9369 06:55:42.413634 DisplayPort interface
9370 06:55:42.416498 Maximum image size: 31 cm x 17 cm
9371 06:55:42.419244 Gamma: 220%
9372 06:55:42.419664 Check DPMS levels
9373 06:55:42.422994 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9374 06:55:42.429225 First detailed timing is preferred timing
9375 06:55:42.429778 Established timings supported:
9376 06:55:42.432923 Standard timings supported:
9377 06:55:42.436103 Detailed timings
9378 06:55:42.439458 Hex of detail: 383680a07038204018303c0035ae10000019
9379 06:55:42.442714 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9380 06:55:42.449729 0780 0798 07c8 0820 hborder 0
9381 06:55:42.452772 0438 043b 0447 0458 vborder 0
9382 06:55:42.456359 -hsync -vsync
9383 06:55:42.456884 Did detailed timing
9384 06:55:42.459897 Hex of detail: 000000000000000000000000000000000000
9385 06:55:42.463101 Manufacturer-specified data, tag 0
9386 06:55:42.469591 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9387 06:55:42.470042 ASCII string: InfoVision
9388 06:55:42.476239 Hex of detail: 000000fe00523134304e574635205248200a
9389 06:55:42.479209 ASCII string: R140NWF5 RH
9390 06:55:42.479735 Checksum
9391 06:55:42.482418 Checksum: 0xfb (valid)
9392 06:55:42.485688 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9393 06:55:42.489161 DSI data_rate: 832800000 bps
9394 06:55:42.495763 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9395 06:55:42.498704 anx7625_parse_edid: pixelclock(138800).
9396 06:55:42.502343 hactive(1920), hsync(48), hfp(24), hbp(88)
9397 06:55:42.505646 vactive(1080), vsync(12), vfp(3), vbp(17)
9398 06:55:42.508692 anx7625_dsi_config: config dsi.
9399 06:55:42.515483 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9400 06:55:42.528825 anx7625_dsi_config: success to config DSI
9401 06:55:42.532108 anx7625_dp_start: MIPI phy setup OK.
9402 06:55:42.535511 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9403 06:55:42.538664 mtk_ddp_mode_set invalid vrefresh 60
9404 06:55:42.541759 main_disp_path_setup
9405 06:55:42.542181 ovl_layer_smi_id_en
9406 06:55:42.545212 ovl_layer_smi_id_en
9407 06:55:42.545660 ccorr_config
9408 06:55:42.545997 aal_config
9409 06:55:42.548663 gamma_config
9410 06:55:42.549181 postmask_config
9411 06:55:42.551684 dither_config
9412 06:55:42.555317 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9413 06:55:42.561853 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9414 06:55:42.565205 Root Device init finished in 555 msecs
9415 06:55:42.565763 CPU_CLUSTER: 0 init
9416 06:55:42.575543 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9417 06:55:42.578192 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9418 06:55:42.581989 APU_MBOX 0x190000b0 = 0x10001
9419 06:55:42.584967 APU_MBOX 0x190001b0 = 0x10001
9420 06:55:42.588657 APU_MBOX 0x190005b0 = 0x10001
9421 06:55:42.591404 APU_MBOX 0x190006b0 = 0x10001
9422 06:55:42.594807 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9423 06:55:42.607437 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9424 06:55:42.619992 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9425 06:55:42.626903 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9426 06:55:42.638448 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9427 06:55:42.647247 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9428 06:55:42.650925 CPU_CLUSTER: 0 init finished in 81 msecs
9429 06:55:42.653984 Devices initialized
9430 06:55:42.657472 Show all devs... After init.
9431 06:55:42.658049 Root Device: enabled 1
9432 06:55:42.660745 CPU_CLUSTER: 0: enabled 1
9433 06:55:42.664265 CPU: 00: enabled 1
9434 06:55:42.667514 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9435 06:55:42.670388 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9436 06:55:42.674021 ELOG: NV offset 0x57f000 size 0x1000
9437 06:55:42.680810 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9438 06:55:42.687164 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9439 06:55:42.690602 ELOG: Event(17) added with size 13 at 2024-02-03 06:55:42 UTC
9440 06:55:42.694062 out: cmd=0x121: 03 db 21 01 00 00 00 00
9441 06:55:42.697902 in-header: 03 65 00 00 2c 00 00 00
9442 06:55:42.710693 in-data: fa 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9443 06:55:42.717216 ELOG: Event(A1) added with size 10 at 2024-02-03 06:55:42 UTC
9444 06:55:42.724122 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9445 06:55:42.731094 ELOG: Event(A0) added with size 9 at 2024-02-03 06:55:42 UTC
9446 06:55:42.734012 elog_add_boot_reason: Logged dev mode boot
9447 06:55:42.737332 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9448 06:55:42.740910 Finalize devices...
9449 06:55:42.741432 Devices finalized
9450 06:55:42.747224 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9451 06:55:42.750672 Writing coreboot table at 0xffe64000
9452 06:55:42.754070 0. 000000000010a000-0000000000113fff: RAMSTAGE
9453 06:55:42.757316 1. 0000000040000000-00000000400fffff: RAM
9454 06:55:42.760633 2. 0000000040100000-000000004032afff: RAMSTAGE
9455 06:55:42.767002 3. 000000004032b000-00000000545fffff: RAM
9456 06:55:42.770471 4. 0000000054600000-000000005465ffff: BL31
9457 06:55:42.773819 5. 0000000054660000-00000000ffe63fff: RAM
9458 06:55:42.780194 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9459 06:55:42.783549 7. 0000000100000000-000000023fffffff: RAM
9460 06:55:42.784012 Passing 5 GPIOs to payload:
9461 06:55:42.790668 NAME | PORT | POLARITY | VALUE
9462 06:55:42.793902 EC in RW | 0x000000aa | low | undefined
9463 06:55:42.800187 EC interrupt | 0x00000005 | low | undefined
9464 06:55:42.803686 TPM interrupt | 0x000000ab | high | undefined
9465 06:55:42.807176 SD card detect | 0x00000011 | high | undefined
9466 06:55:42.814047 speaker enable | 0x00000093 | high | undefined
9467 06:55:42.817122 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9468 06:55:42.819977 in-header: 03 f9 00 00 02 00 00 00
9469 06:55:42.823695 in-data: 02 00
9470 06:55:42.824227 ADC[4]: Raw value=892231 ID=7
9471 06:55:42.827046 ADC[3]: Raw value=213440 ID=1
9472 06:55:42.830019 RAM Code: 0x71
9473 06:55:42.830447 ADC[6]: Raw value=74352 ID=0
9474 06:55:42.833825 ADC[5]: Raw value=212700 ID=1
9475 06:55:42.836742 SKU Code: 0x1
9476 06:55:42.840268 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1c2
9477 06:55:42.843569 coreboot table: 964 bytes.
9478 06:55:42.846798 IMD ROOT 0. 0xfffff000 0x00001000
9479 06:55:42.850017 IMD SMALL 1. 0xffffe000 0x00001000
9480 06:55:42.853548 RO MCACHE 2. 0xffffc000 0x00001104
9481 06:55:42.856586 CONSOLE 3. 0xfff7c000 0x00080000
9482 06:55:42.859889 FMAP 4. 0xfff7b000 0x00000452
9483 06:55:42.863449 TIME STAMP 5. 0xfff7a000 0x00000910
9484 06:55:42.866766 VBOOT WORK 6. 0xfff66000 0x00014000
9485 06:55:42.870097 RAMOOPS 7. 0xffe66000 0x00100000
9486 06:55:42.873461 COREBOOT 8. 0xffe64000 0x00002000
9487 06:55:42.874039 IMD small region:
9488 06:55:42.876997 IMD ROOT 0. 0xffffec00 0x00000400
9489 06:55:42.879954 VPD 1. 0xffffeb80 0x0000006c
9490 06:55:42.883031 MMC STATUS 2. 0xffffeb60 0x00000004
9491 06:55:42.889667 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9492 06:55:42.893636 Probing TPM: done!
9493 06:55:42.896820 Connected to device vid:did:rid of 1ae0:0028:00
9494 06:55:42.906761 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9495 06:55:42.910401 Initialized TPM device CR50 revision 0
9496 06:55:42.914315 Checking cr50 for pending updates
9497 06:55:42.917544 Reading cr50 TPM mode
9498 06:55:42.925816 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9499 06:55:42.932516 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9500 06:55:42.972629 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9501 06:55:42.976070 Checking segment from ROM address 0x40100000
9502 06:55:42.979126 Checking segment from ROM address 0x4010001c
9503 06:55:42.985824 Loading segment from ROM address 0x40100000
9504 06:55:42.986352 code (compression=0)
9505 06:55:42.995923 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9506 06:55:43.002499 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9507 06:55:43.003025 it's not compressed!
9508 06:55:43.009063 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9509 06:55:43.012337 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9510 06:55:43.033056 Loading segment from ROM address 0x4010001c
9511 06:55:43.033635 Entry Point 0x80000000
9512 06:55:43.036459 Loaded segments
9513 06:55:43.039216 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9514 06:55:43.046024 Jumping to boot code at 0x80000000(0xffe64000)
9515 06:55:43.052898 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9516 06:55:43.059495 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9517 06:55:43.067298 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9518 06:55:43.070721 Checking segment from ROM address 0x40100000
9519 06:55:43.073588 Checking segment from ROM address 0x4010001c
9520 06:55:43.080672 Loading segment from ROM address 0x40100000
9521 06:55:43.081222 code (compression=1)
9522 06:55:43.087152 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9523 06:55:43.096724 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9524 06:55:43.097253 using LZMA
9525 06:55:43.105632 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9526 06:55:43.112003 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9527 06:55:43.115526 Loading segment from ROM address 0x4010001c
9528 06:55:43.115949 Entry Point 0x54601000
9529 06:55:43.119104 Loaded segments
9530 06:55:43.122172 NOTICE: MT8192 bl31_setup
9531 06:55:43.129346 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9532 06:55:43.132671 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9533 06:55:43.135663 WARNING: region 0:
9534 06:55:43.139237 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 06:55:43.139816 WARNING: region 1:
9536 06:55:43.146006 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9537 06:55:43.149339 WARNING: region 2:
9538 06:55:43.152620 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9539 06:55:43.155472 WARNING: region 3:
9540 06:55:43.159134 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9541 06:55:43.162225 WARNING: region 4:
9542 06:55:43.169132 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9543 06:55:43.169710 WARNING: region 5:
9544 06:55:43.172180 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 06:55:43.175376 WARNING: region 6:
9546 06:55:43.179180 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 06:55:43.182357 WARNING: region 7:
9548 06:55:43.186160 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 06:55:43.192413 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9550 06:55:43.195550 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9551 06:55:43.198748 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9552 06:55:43.205821 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9553 06:55:43.209682 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9554 06:55:43.212359 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9555 06:55:43.219059 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9556 06:55:43.222022 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9557 06:55:43.229374 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9558 06:55:43.232359 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9559 06:55:43.236122 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9560 06:55:43.242688 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9561 06:55:43.246044 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9562 06:55:43.249050 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9563 06:55:43.256010 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9564 06:55:43.258950 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9565 06:55:43.265896 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9566 06:55:43.269446 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9567 06:55:43.272746 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9568 06:55:43.279125 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9569 06:55:43.282240 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9570 06:55:43.285849 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9571 06:55:43.292655 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9572 06:55:43.295628 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9573 06:55:43.302373 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9574 06:55:43.306018 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9575 06:55:43.309178 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9576 06:55:43.315572 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9577 06:55:43.319049 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9578 06:55:43.325565 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9579 06:55:43.329039 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9580 06:55:43.332243 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9581 06:55:43.339122 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9582 06:55:43.342446 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9583 06:55:43.345863 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9584 06:55:43.349218 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9585 06:55:43.355823 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9586 06:55:43.358680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9587 06:55:43.362135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9588 06:55:43.365881 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9589 06:55:43.372324 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9590 06:55:43.375489 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9591 06:55:43.378873 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9592 06:55:43.382417 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9593 06:55:43.388949 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9594 06:55:43.392240 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9595 06:55:43.395808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9596 06:55:43.398965 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9597 06:55:43.405429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9598 06:55:43.408886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9599 06:55:43.415652 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9600 06:55:43.419237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9601 06:55:43.422216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9602 06:55:43.428900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9603 06:55:43.432312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9604 06:55:43.438997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9605 06:55:43.442276 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9606 06:55:43.449011 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9607 06:55:43.452070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9608 06:55:43.458584 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9609 06:55:43.462111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9610 06:55:43.465530 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9611 06:55:43.472016 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9612 06:55:43.475522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9613 06:55:43.482464 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9614 06:55:43.485349 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9615 06:55:43.492289 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9616 06:55:43.495639 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9617 06:55:43.498978 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9618 06:55:43.505621 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9619 06:55:43.508505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9620 06:55:43.515398 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9621 06:55:43.518709 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9622 06:55:43.525629 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9623 06:55:43.528696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9624 06:55:43.532292 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9625 06:55:43.538819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9626 06:55:43.542054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9627 06:55:43.548893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9628 06:55:43.552026 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9629 06:55:43.558657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9630 06:55:43.561846 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9631 06:55:43.565408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9632 06:55:43.571823 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9633 06:55:43.575448 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9634 06:55:43.581816 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9635 06:55:43.585240 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9636 06:55:43.592122 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9637 06:55:43.595201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9638 06:55:43.598521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9639 06:55:43.605615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9640 06:55:43.608687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9641 06:55:43.615382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9642 06:55:43.618578 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9643 06:55:43.625346 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9644 06:55:43.628894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9645 06:55:43.631757 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9646 06:55:43.638423 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9647 06:55:43.641635 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9648 06:55:43.645550 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9649 06:55:43.648685 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9650 06:55:43.655250 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9651 06:55:43.658901 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9652 06:55:43.665363 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9653 06:55:43.668733 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9654 06:55:43.672160 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9655 06:55:43.678580 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9656 06:55:43.681674 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9657 06:55:43.688690 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9658 06:55:43.691683 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9659 06:55:43.695555 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9660 06:55:43.702324 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9661 06:55:43.705587 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9662 06:55:43.712192 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9663 06:55:43.715435 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9664 06:55:43.718425 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9665 06:55:43.722179 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9666 06:55:43.728709 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9667 06:55:43.732295 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9668 06:55:43.735162 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9669 06:55:43.741818 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9670 06:55:43.745664 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9671 06:55:43.748394 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9672 06:55:43.751980 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9673 06:55:43.758891 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9674 06:55:43.762025 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9675 06:55:43.768989 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9676 06:55:43.772019 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9677 06:55:43.775045 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9678 06:55:43.782171 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9679 06:55:43.785471 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9680 06:55:43.791913 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9681 06:55:43.795336 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9682 06:55:43.798565 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9683 06:55:43.805836 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9684 06:55:43.808879 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9685 06:55:43.812196 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9686 06:55:43.818776 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9687 06:55:43.821968 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9688 06:55:43.828685 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9689 06:55:43.832424 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9690 06:55:43.835507 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9691 06:55:43.841684 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9692 06:55:43.845042 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9693 06:55:43.851896 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9694 06:55:43.855701 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9695 06:55:43.858567 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9696 06:55:43.864885 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9697 06:55:43.868389 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9698 06:55:43.871702 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9699 06:55:43.878511 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9700 06:55:43.881711 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9701 06:55:43.888304 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9702 06:55:43.892271 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9703 06:55:43.895337 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9704 06:55:43.901864 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9705 06:55:43.905614 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9706 06:55:43.911803 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9707 06:55:43.915198 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9708 06:55:43.918520 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9709 06:55:43.924933 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9710 06:55:43.928402 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9711 06:55:43.935123 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9712 06:55:43.938200 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9713 06:55:43.941930 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9714 06:55:43.948555 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9715 06:55:43.951852 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9716 06:55:43.955099 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9717 06:55:43.961531 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9718 06:55:43.965115 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9719 06:55:43.971823 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9720 06:55:43.974907 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9721 06:55:43.978324 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9722 06:55:43.985255 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9723 06:55:43.988600 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9724 06:55:43.994982 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9725 06:55:43.998317 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9726 06:55:44.001254 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9727 06:55:44.008440 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9728 06:55:44.011456 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9729 06:55:44.015008 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9730 06:55:44.021690 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9731 06:55:44.024917 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9732 06:55:44.031331 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9733 06:55:44.034674 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9734 06:55:44.041706 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9735 06:55:44.044245 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9736 06:55:44.047830 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9737 06:55:44.054455 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9738 06:55:44.058078 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9739 06:55:44.064078 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9740 06:55:44.067830 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9741 06:55:44.070860 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9742 06:55:44.077210 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9743 06:55:44.080942 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9744 06:55:44.087304 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9745 06:55:44.090636 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9746 06:55:44.097347 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9747 06:55:44.100741 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9748 06:55:44.104068 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9749 06:55:44.110230 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9750 06:55:44.113674 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9751 06:55:44.120556 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9752 06:55:44.123806 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9753 06:55:44.130393 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9754 06:55:44.133408 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9755 06:55:44.137466 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9756 06:55:44.143916 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9757 06:55:44.146984 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9758 06:55:44.153547 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9759 06:55:44.156465 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9760 06:55:44.163615 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9761 06:55:44.166987 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9762 06:55:44.170183 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9763 06:55:44.176546 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9764 06:55:44.180302 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9765 06:55:44.186491 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9766 06:55:44.189973 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9767 06:55:44.193340 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9768 06:55:44.199911 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9769 06:55:44.203054 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9770 06:55:44.209724 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9771 06:55:44.213019 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9772 06:55:44.219831 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9773 06:55:44.222671 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9774 06:55:44.225957 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9775 06:55:44.232693 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9776 06:55:44.236316 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9777 06:55:44.243176 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9778 06:55:44.246020 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9779 06:55:44.249633 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9780 06:55:44.253293 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9781 06:55:44.259759 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9782 06:55:44.262893 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9783 06:55:44.265934 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9784 06:55:44.272943 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9785 06:55:44.276322 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9786 06:55:44.279481 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9787 06:55:44.286262 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9788 06:55:44.289404 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9789 06:55:44.292939 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9790 06:55:44.299284 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9791 06:55:44.302408 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9792 06:55:44.305591 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9793 06:55:44.312750 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9794 06:55:44.315864 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9795 06:55:44.322330 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9796 06:55:44.325922 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9797 06:55:44.328628 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9798 06:55:44.335460 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9799 06:55:44.338878 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9800 06:55:44.345319 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9801 06:55:44.348727 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9802 06:55:44.352105 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9803 06:55:44.358998 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9804 06:55:44.361844 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9805 06:55:44.365111 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9806 06:55:44.372005 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9807 06:55:44.375257 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9808 06:55:44.378362 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9809 06:55:44.385404 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9810 06:55:44.388300 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9811 06:55:44.394921 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9812 06:55:44.398096 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9813 06:55:44.401802 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9814 06:55:44.408535 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9815 06:55:44.411378 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9816 06:55:44.414800 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9817 06:55:44.421676 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9818 06:55:44.424770 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9819 06:55:44.428138 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9820 06:55:44.431380 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9821 06:55:44.438194 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9822 06:55:44.441436 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9823 06:55:44.444919 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9824 06:55:44.448179 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9825 06:55:44.454591 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9826 06:55:44.458011 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9827 06:55:44.461360 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9828 06:55:44.464439 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9829 06:55:44.470857 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9830 06:55:44.474393 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9831 06:55:44.477751 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9832 06:55:44.484735 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9833 06:55:44.487704 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9834 06:55:44.494422 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9835 06:55:44.497997 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9836 06:55:44.504505 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9837 06:55:44.507933 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9838 06:55:44.510838 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9839 06:55:44.517547 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9840 06:55:44.520868 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9841 06:55:44.527355 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9842 06:55:44.531098 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9843 06:55:44.534385 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9844 06:55:44.540870 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9845 06:55:44.543982 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9846 06:55:44.550779 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9847 06:55:44.553754 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9848 06:55:44.557472 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9849 06:55:44.563545 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9850 06:55:44.567338 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9851 06:55:44.573790 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9852 06:55:44.576720 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9853 06:55:44.583988 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9854 06:55:44.586699 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9855 06:55:44.590299 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9856 06:55:44.596709 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9857 06:55:44.600062 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9858 06:55:44.606793 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9859 06:55:44.609979 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9860 06:55:44.613785 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9861 06:55:44.619815 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9862 06:55:44.623335 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9863 06:55:44.630053 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9864 06:55:44.633439 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9865 06:55:44.636531 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9866 06:55:44.643142 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9867 06:55:44.646371 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9868 06:55:44.653051 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9869 06:55:44.656216 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9870 06:55:44.662688 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9871 06:55:44.666139 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9872 06:55:44.669848 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9873 06:55:44.676515 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9874 06:55:44.679373 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9875 06:55:44.686057 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9876 06:55:44.689087 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9877 06:55:44.696040 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9878 06:55:44.699679 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9879 06:55:44.702562 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9880 06:55:44.709590 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9881 06:55:44.712762 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9882 06:55:44.719058 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9883 06:55:44.722501 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9884 06:55:44.725714 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9885 06:55:44.732587 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9886 06:55:44.736031 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9887 06:55:44.742614 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9888 06:55:44.745992 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9889 06:55:44.748997 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9890 06:55:44.756084 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9891 06:55:44.759206 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9892 06:55:44.765737 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9893 06:55:44.768875 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9894 06:55:44.772022 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9895 06:55:44.778642 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9896 06:55:44.782127 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9897 06:55:44.788969 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9898 06:55:44.792042 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9899 06:55:44.798722 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9900 06:55:44.801961 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9901 06:55:44.805440 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9902 06:55:44.811695 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9903 06:55:44.815282 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9904 06:55:44.822126 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9905 06:55:44.825066 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9906 06:55:44.828841 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9907 06:55:44.835159 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9908 06:55:44.838635 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9909 06:55:44.845176 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9910 06:55:44.848085 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9911 06:55:44.855391 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9912 06:55:44.858299 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9913 06:55:44.861838 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9914 06:55:44.868371 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9915 06:55:44.871733 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9916 06:55:44.878199 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9917 06:55:44.881533 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9918 06:55:44.888300 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9919 06:55:44.891726 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9920 06:55:44.898356 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9921 06:55:44.901809 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9922 06:55:44.905017 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9923 06:55:44.911315 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9924 06:55:44.914805 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9925 06:55:44.921555 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9926 06:55:44.924657 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9927 06:55:44.931473 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9928 06:55:44.935211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9929 06:55:44.938434 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9930 06:55:44.945012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9931 06:55:44.948026 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9932 06:55:44.954482 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9933 06:55:44.957835 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9934 06:55:44.964327 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9935 06:55:44.967755 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9936 06:55:44.971238 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9937 06:55:44.977588 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9938 06:55:44.980743 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9939 06:55:44.987628 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9940 06:55:44.990912 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9941 06:55:44.997951 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9942 06:55:45.000916 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9943 06:55:45.004285 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9944 06:55:45.010902 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9945 06:55:45.014174 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9946 06:55:45.021053 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9947 06:55:45.023985 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9948 06:55:45.030843 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9949 06:55:45.034247 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9950 06:55:45.041091 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9951 06:55:45.044222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9952 06:55:45.047308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9953 06:55:45.053905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9954 06:55:45.057192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9955 06:55:45.063865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9956 06:55:45.067370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9957 06:55:45.073953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9958 06:55:45.077307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9959 06:55:45.084001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9960 06:55:45.087264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9961 06:55:45.093963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9962 06:55:45.096877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9963 06:55:45.103623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9964 06:55:45.107574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9965 06:55:45.113886 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9966 06:55:45.117265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9967 06:55:45.120860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9968 06:55:45.127258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9969 06:55:45.130562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9970 06:55:45.136855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9971 06:55:45.140357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9972 06:55:45.147178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9973 06:55:45.150171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9974 06:55:45.157014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9975 06:55:45.163572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9976 06:55:45.167006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9977 06:55:45.173360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9978 06:55:45.176889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9979 06:55:45.183153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9980 06:55:45.187122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9981 06:55:45.193400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9982 06:55:45.196360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9983 06:55:45.199829 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9984 06:55:45.203246 INFO: [APUAPC] vio 0
9985 06:55:45.206766 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9986 06:55:45.213711 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9987 06:55:45.217176 INFO: [APUAPC] D0_APC_0: 0x400510
9988 06:55:45.219944 INFO: [APUAPC] D0_APC_1: 0x0
9989 06:55:45.223419 INFO: [APUAPC] D0_APC_2: 0x1540
9990 06:55:45.226911 INFO: [APUAPC] D0_APC_3: 0x0
9991 06:55:45.229874 INFO: [APUAPC] D1_APC_0: 0xffffffff
9992 06:55:45.232789 INFO: [APUAPC] D1_APC_1: 0xffffffff
9993 06:55:45.236683 INFO: [APUAPC] D1_APC_2: 0x3fffff
9994 06:55:45.237209 INFO: [APUAPC] D1_APC_3: 0x0
9995 06:55:45.240043 INFO: [APUAPC] D2_APC_0: 0xffffffff
9996 06:55:45.246192 INFO: [APUAPC] D2_APC_1: 0xffffffff
9997 06:55:45.249694 INFO: [APUAPC] D2_APC_2: 0x3fffff
9998 06:55:45.250117 INFO: [APUAPC] D2_APC_3: 0x0
9999 06:55:45.253097 INFO: [APUAPC] D3_APC_0: 0xffffffff
10000 06:55:45.256252 INFO: [APUAPC] D3_APC_1: 0xffffffff
10001 06:55:45.259304 INFO: [APUAPC] D3_APC_2: 0x3fffff
10002 06:55:45.262519 INFO: [APUAPC] D3_APC_3: 0x0
10003 06:55:45.266147 INFO: [APUAPC] D4_APC_0: 0xffffffff
10004 06:55:45.269799 INFO: [APUAPC] D4_APC_1: 0xffffffff
10005 06:55:45.273118 INFO: [APUAPC] D4_APC_2: 0x3fffff
10006 06:55:45.276424 INFO: [APUAPC] D4_APC_3: 0x0
10007 06:55:45.279098 INFO: [APUAPC] D5_APC_0: 0xffffffff
10008 06:55:45.282730 INFO: [APUAPC] D5_APC_1: 0xffffffff
10009 06:55:45.286196 INFO: [APUAPC] D5_APC_2: 0x3fffff
10010 06:55:45.289077 INFO: [APUAPC] D5_APC_3: 0x0
10011 06:55:45.292719 INFO: [APUAPC] D6_APC_0: 0xffffffff
10012 06:55:45.296115 INFO: [APUAPC] D6_APC_1: 0xffffffff
10013 06:55:45.299278 INFO: [APUAPC] D6_APC_2: 0x3fffff
10014 06:55:45.302382 INFO: [APUAPC] D6_APC_3: 0x0
10015 06:55:45.305862 INFO: [APUAPC] D7_APC_0: 0xffffffff
10016 06:55:45.309148 INFO: [APUAPC] D7_APC_1: 0xffffffff
10017 06:55:45.312550 INFO: [APUAPC] D7_APC_2: 0x3fffff
10018 06:55:45.315806 INFO: [APUAPC] D7_APC_3: 0x0
10019 06:55:45.319001 INFO: [APUAPC] D8_APC_0: 0xffffffff
10020 06:55:45.322436 INFO: [APUAPC] D8_APC_1: 0xffffffff
10021 06:55:45.325646 INFO: [APUAPC] D8_APC_2: 0x3fffff
10022 06:55:45.328916 INFO: [APUAPC] D8_APC_3: 0x0
10023 06:55:45.332348 INFO: [APUAPC] D9_APC_0: 0xffffffff
10024 06:55:45.335696 INFO: [APUAPC] D9_APC_1: 0xffffffff
10025 06:55:45.339000 INFO: [APUAPC] D9_APC_2: 0x3fffff
10026 06:55:45.342204 INFO: [APUAPC] D9_APC_3: 0x0
10027 06:55:45.345312 INFO: [APUAPC] D10_APC_0: 0xffffffff
10028 06:55:45.348653 INFO: [APUAPC] D10_APC_1: 0xffffffff
10029 06:55:45.352008 INFO: [APUAPC] D10_APC_2: 0x3fffff
10030 06:55:45.355151 INFO: [APUAPC] D10_APC_3: 0x0
10031 06:55:45.358459 INFO: [APUAPC] D11_APC_0: 0xffffffff
10032 06:55:45.361953 INFO: [APUAPC] D11_APC_1: 0xffffffff
10033 06:55:45.364783 INFO: [APUAPC] D11_APC_2: 0x3fffff
10034 06:55:45.368497 INFO: [APUAPC] D11_APC_3: 0x0
10035 06:55:45.371358 INFO: [APUAPC] D12_APC_0: 0xffffffff
10036 06:55:45.374860 INFO: [APUAPC] D12_APC_1: 0xffffffff
10037 06:55:45.378072 INFO: [APUAPC] D12_APC_2: 0x3fffff
10038 06:55:45.381460 INFO: [APUAPC] D12_APC_3: 0x0
10039 06:55:45.384890 INFO: [APUAPC] D13_APC_0: 0xffffffff
10040 06:55:45.388153 INFO: [APUAPC] D13_APC_1: 0xffffffff
10041 06:55:45.391217 INFO: [APUAPC] D13_APC_2: 0x3fffff
10042 06:55:45.394599 INFO: [APUAPC] D13_APC_3: 0x0
10043 06:55:45.397908 INFO: [APUAPC] D14_APC_0: 0xffffffff
10044 06:55:45.401423 INFO: [APUAPC] D14_APC_1: 0xffffffff
10045 06:55:45.404513 INFO: [APUAPC] D14_APC_2: 0x3fffff
10046 06:55:45.407692 INFO: [APUAPC] D14_APC_3: 0x0
10047 06:55:45.411107 INFO: [APUAPC] D15_APC_0: 0xffffffff
10048 06:55:45.414495 INFO: [APUAPC] D15_APC_1: 0xffffffff
10049 06:55:45.417741 INFO: [APUAPC] D15_APC_2: 0x3fffff
10050 06:55:45.420890 INFO: [APUAPC] D15_APC_3: 0x0
10051 06:55:45.424262 INFO: [APUAPC] APC_CON: 0x4
10052 06:55:45.427499 INFO: [NOCDAPC] D0_APC_0: 0x0
10053 06:55:45.430954 INFO: [NOCDAPC] D0_APC_1: 0x0
10054 06:55:45.433939 INFO: [NOCDAPC] D1_APC_0: 0x0
10055 06:55:45.437527 INFO: [NOCDAPC] D1_APC_1: 0xfff
10056 06:55:45.440751 INFO: [NOCDAPC] D2_APC_0: 0x0
10057 06:55:45.443967 INFO: [NOCDAPC] D2_APC_1: 0xfff
10058 06:55:45.444268 INFO: [NOCDAPC] D3_APC_0: 0x0
10059 06:55:45.447255 INFO: [NOCDAPC] D3_APC_1: 0xfff
10060 06:55:45.450530 INFO: [NOCDAPC] D4_APC_0: 0x0
10061 06:55:45.453821 INFO: [NOCDAPC] D4_APC_1: 0xfff
10062 06:55:45.456880 INFO: [NOCDAPC] D5_APC_0: 0x0
10063 06:55:45.460313 INFO: [NOCDAPC] D5_APC_1: 0xfff
10064 06:55:45.463695 INFO: [NOCDAPC] D6_APC_0: 0x0
10065 06:55:45.467127 INFO: [NOCDAPC] D6_APC_1: 0xfff
10066 06:55:45.470365 INFO: [NOCDAPC] D7_APC_0: 0x0
10067 06:55:45.473629 INFO: [NOCDAPC] D7_APC_1: 0xfff
10068 06:55:45.473752 INFO: [NOCDAPC] D8_APC_0: 0x0
10069 06:55:45.476917 INFO: [NOCDAPC] D8_APC_1: 0xfff
10070 06:55:45.480467 INFO: [NOCDAPC] D9_APC_0: 0x0
10071 06:55:45.483620 INFO: [NOCDAPC] D9_APC_1: 0xfff
10072 06:55:45.487109 INFO: [NOCDAPC] D10_APC_0: 0x0
10073 06:55:45.490122 INFO: [NOCDAPC] D10_APC_1: 0xfff
10074 06:55:45.493550 INFO: [NOCDAPC] D11_APC_0: 0x0
10075 06:55:45.496839 INFO: [NOCDAPC] D11_APC_1: 0xfff
10076 06:55:45.500112 INFO: [NOCDAPC] D12_APC_0: 0x0
10077 06:55:45.503322 INFO: [NOCDAPC] D12_APC_1: 0xfff
10078 06:55:45.506589 INFO: [NOCDAPC] D13_APC_0: 0x0
10079 06:55:45.509928 INFO: [NOCDAPC] D13_APC_1: 0xfff
10080 06:55:45.513221 INFO: [NOCDAPC] D14_APC_0: 0x0
10081 06:55:45.516438 INFO: [NOCDAPC] D14_APC_1: 0xfff
10082 06:55:45.519785 INFO: [NOCDAPC] D15_APC_0: 0x0
10083 06:55:45.523031 INFO: [NOCDAPC] D15_APC_1: 0xfff
10084 06:55:45.523120 INFO: [NOCDAPC] APC_CON: 0x4
10085 06:55:45.526294 INFO: [APUAPC] set_apusys_apc done
10086 06:55:45.529966 INFO: [DEVAPC] devapc_init done
10087 06:55:45.536353 INFO: GICv3 without legacy support detected.
10088 06:55:45.539751 INFO: ARM GICv3 driver initialized in EL3
10089 06:55:45.543130 INFO: Maximum SPI INTID supported: 639
10090 06:55:45.546110 INFO: BL31: Initializing runtime services
10091 06:55:45.552801 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10092 06:55:45.556268 INFO: SPM: enable CPC mode
10093 06:55:45.559388 INFO: mcdi ready for mcusys-off-idle and system suspend
10094 06:55:45.565959 INFO: BL31: Preparing for EL3 exit to normal world
10095 06:55:45.569144 INFO: Entry point address = 0x80000000
10096 06:55:45.569228 INFO: SPSR = 0x8
10097 06:55:45.576555
10098 06:55:45.576671
10099 06:55:45.576741
10100 06:55:45.579960 Starting depthcharge on Spherion...
10101 06:55:45.580045
10102 06:55:45.580110 Wipe memory regions:
10103 06:55:45.580170
10104 06:55:45.580831 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10105 06:55:45.580933 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10106 06:55:45.581015 Setting prompt string to ['asurada:']
10107 06:55:45.581095 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10108 06:55:45.582872 [0x00000040000000, 0x00000054600000)
10109 06:55:45.705733
10110 06:55:45.705924 [0x00000054660000, 0x00000080000000)
10111 06:55:45.966457
10112 06:55:45.966983 [0x000000821a7280, 0x000000ffe64000)
10113 06:55:46.710579
10114 06:55:46.711108 [0x00000100000000, 0x00000240000000)
10115 06:55:48.599773
10116 06:55:48.602718 Initializing XHCI USB controller at 0x11200000.
10117 06:55:49.640744
10118 06:55:49.643802 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10119 06:55:49.643975
10120 06:55:49.644110
10121 06:55:49.644237
10122 06:55:49.644646 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10124 06:55:49.745234 asurada: tftpboot 192.168.201.1 12694862/tftp-deploy-b_wrejdt/kernel/image.itb 12694862/tftp-deploy-b_wrejdt/kernel/cmdline
10125 06:55:49.745810 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10126 06:55:49.746182 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10127 06:55:49.750661 tftpboot 192.168.201.1 12694862/tftp-deploy-b_wrejdt/kernel/image.itp-deploy-b_wrejdt/kernel/cmdline
10128 06:55:49.751054
10129 06:55:49.751355 Waiting for link
10130 06:55:49.911284
10131 06:55:49.911767 R8152: Initializing
10132 06:55:49.912076
10133 06:55:49.914386 Version 6 (ocp_data = 5c30)
10134 06:55:49.914773
10135 06:55:49.917629 R8152: Done initializing
10136 06:55:49.918013
10137 06:55:49.918288 Adding net device
10138 06:55:51.893593
10139 06:55:51.893861 done.
10140 06:55:51.894014
10141 06:55:51.894156 MAC: 00:24:32:30:78:ff
10142 06:55:51.894320
10143 06:55:51.896797 Sending DHCP discover... done.
10144 06:55:51.896992
10145 06:55:51.900063 Waiting for reply... done.
10146 06:55:51.900222
10147 06:55:51.903315 Sending DHCP request... done.
10148 06:55:51.903473
10149 06:55:51.908040 Waiting for reply... done.
10150 06:55:51.908199
10151 06:55:51.908326 My ip is 192.168.201.21
10152 06:55:51.908443
10153 06:55:51.911585 The DHCP server ip is 192.168.201.1
10154 06:55:51.911744
10155 06:55:51.918437 TFTP server IP predefined by user: 192.168.201.1
10156 06:55:51.918867
10157 06:55:51.925128 Bootfile predefined by user: 12694862/tftp-deploy-b_wrejdt/kernel/image.itb
10158 06:55:51.925601
10159 06:55:51.928416 Sending tftp read request... done.
10160 06:55:51.928838
10161 06:55:51.934583 Waiting for the transfer...
10162 06:55:51.935008
10163 06:55:52.611095 00000000 ################################################################
10164 06:55:52.611292
10165 06:55:53.190832 00080000 ################################################################
10166 06:55:53.190989
10167 06:55:53.780285 00100000 ################################################################
10168 06:55:53.780442
10169 06:55:54.380541 00180000 ################################################################
10170 06:55:54.380688
10171 06:55:54.979992 00200000 ################################################################
10172 06:55:54.980159
10173 06:55:55.571616 00280000 ################################################################
10174 06:55:55.571768
10175 06:55:56.169734 00300000 ################################################################
10176 06:55:56.169884
10177 06:55:56.749689 00380000 ################################################################
10178 06:55:56.749837
10179 06:55:57.346467 00400000 ################################################################
10180 06:55:57.346613
10181 06:55:57.949379 00480000 ################################################################
10182 06:55:57.949575
10183 06:55:58.549946 00500000 ################################################################
10184 06:55:58.550096
10185 06:55:59.144465 00580000 ################################################################
10186 06:55:59.144613
10187 06:55:59.745688 00600000 ################################################################
10188 06:55:59.745838
10189 06:56:00.352178 00680000 ################################################################
10190 06:56:00.352332
10191 06:56:00.939492 00700000 ################################################################
10192 06:56:00.939646
10193 06:56:01.527711 00780000 ################################################################
10194 06:56:01.527863
10195 06:56:02.124186 00800000 ################################################################
10196 06:56:02.124340
10197 06:56:02.712739 00880000 ################################################################
10198 06:56:02.712893
10199 06:56:03.313504 00900000 ################################################################
10200 06:56:03.313675
10201 06:56:03.910178 00980000 ################################################################
10202 06:56:03.910337
10203 06:56:04.509421 00a00000 ################################################################
10204 06:56:04.509596
10205 06:56:05.078457 00a80000 ################################################################
10206 06:56:05.078610
10207 06:56:05.665348 00b00000 ################################################################
10208 06:56:05.665518
10209 06:56:06.256108 00b80000 ################################################################
10210 06:56:06.256260
10211 06:56:06.847464 00c00000 ################################################################
10212 06:56:06.847618
10213 06:56:07.443602 00c80000 ################################################################
10214 06:56:07.443756
10215 06:56:08.032789 00d00000 ################################################################
10216 06:56:08.032944
10217 06:56:08.609108 00d80000 ################################################################
10218 06:56:08.609269
10219 06:56:09.210205 00e00000 ################################################################
10220 06:56:09.210367
10221 06:56:09.796380 00e80000 ################################################################
10222 06:56:09.796542
10223 06:56:10.398697 00f00000 ################################################################
10224 06:56:10.398859
10225 06:56:10.991266 00f80000 ################################################################
10226 06:56:10.991430
10227 06:56:11.584682 01000000 ################################################################
10228 06:56:11.584846
10229 06:56:12.178495 01080000 ################################################################
10230 06:56:12.178657
10231 06:56:12.765831 01100000 ################################################################
10232 06:56:12.765995
10233 06:56:13.358610 01180000 ################################################################
10234 06:56:13.358769
10235 06:56:13.938395 01200000 ################################################################
10236 06:56:13.938560
10237 06:56:14.515867 01280000 ################################################################
10238 06:56:14.516028
10239 06:56:15.117256 01300000 ################################################################
10240 06:56:15.117417
10241 06:56:15.708426 01380000 ################################################################
10242 06:56:15.708583
10243 06:56:16.286793 01400000 ################################################################
10244 06:56:16.286949
10245 06:56:16.872657 01480000 ################################################################
10246 06:56:16.872817
10247 06:56:17.451690 01500000 ################################################################
10248 06:56:17.451852
10249 06:56:18.050884 01580000 ################################################################
10250 06:56:18.051038
10251 06:56:18.637402 01600000 ################################################################
10252 06:56:18.637608
10253 06:56:19.246941 01680000 ################################################################
10254 06:56:19.247134
10255 06:56:19.842749 01700000 ################################################################
10256 06:56:19.842908
10257 06:56:20.445951 01780000 ################################################################
10258 06:56:20.446107
10259 06:56:21.063578 01800000 ################################################################
10260 06:56:21.063728
10261 06:56:21.640815 01880000 ################################################################
10262 06:56:21.641066
10263 06:56:22.314414 01900000 ################################################################
10264 06:56:22.314930
10265 06:56:23.037154 01980000 ################################################################
10266 06:56:23.037713
10267 06:56:23.784483 01a00000 ################################################################
10268 06:56:23.785184
10269 06:56:24.525009 01a80000 ################################################################
10270 06:56:24.525586
10271 06:56:25.261941 01b00000 ################################################################
10272 06:56:25.262460
10273 06:56:26.009795 01b80000 ################################################################
10274 06:56:26.010312
10275 06:56:26.753428 01c00000 ################################################################
10276 06:56:26.754035
10277 06:56:26.778448 01c80000 ### done.
10278 06:56:26.778981
10279 06:56:26.781686 The bootfile was 29901398 bytes long.
10280 06:56:26.782108
10281 06:56:26.784874 Sending tftp read request... done.
10282 06:56:26.785318
10283 06:56:26.788135 Waiting for the transfer...
10284 06:56:26.788556
10285 06:56:26.788895 00000000 # done.
10286 06:56:26.791898
10287 06:56:26.798190 Command line loaded dynamically from TFTP file: 12694862/tftp-deploy-b_wrejdt/kernel/cmdline
10288 06:56:26.798720
10289 06:56:26.818273 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694862/extract-nfsrootfs-9tq3hp0n,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10290 06:56:26.821366
10291 06:56:26.821960 Loading FIT.
10292 06:56:26.822309
10293 06:56:26.824799 Image ramdisk-1 has 17801501 bytes.
10294 06:56:26.825321
10295 06:56:26.827998 Image fdt-1 has 47278 bytes.
10296 06:56:26.828415
10297 06:56:26.831216 Image kernel-1 has 12050581 bytes.
10298 06:56:26.831635
10299 06:56:26.838058 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10300 06:56:26.838587
10301 06:56:26.857713 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10302 06:56:26.858239
10303 06:56:26.861537 Choosing best match conf-1 for compat google,spherion-rev2.
10304 06:56:26.866217
10305 06:56:26.870586 Connected to device vid:did:rid of 1ae0:0028:00
10306 06:56:26.878783
10307 06:56:26.882056 tpm_get_response: command 0x17b, return code 0x0
10308 06:56:26.882533
10309 06:56:26.885088 ec_init: CrosEC protocol v3 supported (256, 248)
10310 06:56:26.889192
10311 06:56:26.892916 tpm_cleanup: add release locality here.
10312 06:56:26.893445
10313 06:56:26.893843 Shutting down all USB controllers.
10314 06:56:26.895930
10315 06:56:26.896348 Removing current net device
10316 06:56:26.896679
10317 06:56:26.902697 Exiting depthcharge with code 4 at timestamp: 70626812
10318 06:56:26.903226
10319 06:56:26.905787 LZMA decompressing kernel-1 to 0x821a6718
10320 06:56:26.906207
10321 06:56:26.909284 LZMA decompressing kernel-1 to 0x40000000
10322 06:56:28.407565
10323 06:56:28.408168 jumping to kernel
10324 06:56:28.410017 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10325 06:56:28.410478 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10326 06:56:28.410826 Setting prompt string to ['Linux version [0-9]']
10327 06:56:28.411142 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10328 06:56:28.411456 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10329 06:56:28.489268
10330 06:56:28.492447 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10331 06:56:28.495931 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10332 06:56:28.496022 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10333 06:56:28.496102 Setting prompt string to []
10334 06:56:28.496178 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10335 06:56:28.496248 Using line separator: #'\n'#
10336 06:56:28.496307 No login prompt set.
10337 06:56:28.496369 Parsing kernel messages
10338 06:56:28.496424 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10339 06:56:28.496544 [login-action] Waiting for messages, (timeout 00:03:42)
10340 06:56:28.516023 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10341 06:56:28.519225 [ 0.000000] random: crng init done
10342 06:56:28.525436 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10343 06:56:28.529214 [ 0.000000] efi: UEFI not found.
10344 06:56:28.535747 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10345 06:56:28.542221 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10346 06:56:28.552256 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10347 06:56:28.561960 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10348 06:56:28.568736 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10349 06:56:28.575272 [ 0.000000] printk: bootconsole [mtk8250] enabled
10350 06:56:28.581874 [ 0.000000] NUMA: No NUMA configuration found
10351 06:56:28.588426 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10352 06:56:28.591968 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10353 06:56:28.595166 [ 0.000000] Zone ranges:
10354 06:56:28.601918 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10355 06:56:28.605166 [ 0.000000] DMA32 empty
10356 06:56:28.611779 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10357 06:56:28.614918 [ 0.000000] Movable zone start for each node
10358 06:56:28.618489 [ 0.000000] Early memory node ranges
10359 06:56:28.625167 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10360 06:56:28.631700 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10361 06:56:28.638593 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10362 06:56:28.644918 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10363 06:56:28.648423 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10364 06:56:28.657924 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10365 06:56:28.713584 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10366 06:56:28.720350 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10367 06:56:28.726806 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10368 06:56:28.730051 [ 0.000000] psci: probing for conduit method from DT.
10369 06:56:28.736609 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10370 06:56:28.739852 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10371 06:56:28.746652 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10372 06:56:28.749976 [ 0.000000] psci: SMC Calling Convention v1.2
10373 06:56:28.756486 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10374 06:56:28.760062 [ 0.000000] Detected VIPT I-cache on CPU0
10375 06:56:28.766363 [ 0.000000] CPU features: detected: GIC system register CPU interface
10376 06:56:28.773167 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10377 06:56:28.779481 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10378 06:56:28.786227 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10379 06:56:28.796381 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10380 06:56:28.802810 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10381 06:56:28.806320 [ 0.000000] alternatives: applying boot alternatives
10382 06:56:28.812729 [ 0.000000] Fallback order for Node 0: 0
10383 06:56:28.819338 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10384 06:56:28.822488 [ 0.000000] Policy zone: Normal
10385 06:56:28.846199 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694862/extract-nfsrootfs-9tq3hp0n,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10386 06:56:28.855930 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10387 06:56:28.866888 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10388 06:56:28.876663 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10389 06:56:28.883242 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10390 06:56:28.886576 <6>[ 0.000000] software IO TLB: area num 8.
10391 06:56:28.943343 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10392 06:56:29.092519 <6>[ 0.000000] Memory: 7949872K/8385536K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 402896K reserved, 32768K cma-reserved)
10393 06:56:29.099202 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10394 06:56:29.105952 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10395 06:56:29.109239 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10396 06:56:29.116121 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10397 06:56:29.122432 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10398 06:56:29.125793 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10399 06:56:29.136144 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10400 06:56:29.142414 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10401 06:56:29.145868 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10402 06:56:29.153469 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10403 06:56:29.156957 <6>[ 0.000000] GICv3: 608 SPIs implemented
10404 06:56:29.163455 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10405 06:56:29.166830 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10406 06:56:29.169882 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10407 06:56:29.179715 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10408 06:56:29.189374 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10409 06:56:29.202708 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10410 06:56:29.209235 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10411 06:56:29.219059 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10412 06:56:29.232409 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10413 06:56:29.238955 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10414 06:56:29.245914 <6>[ 0.009143] Console: colour dummy device 80x25
10415 06:56:29.255406 <6>[ 0.013869] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10416 06:56:29.262403 <6>[ 0.024311] pid_max: default: 32768 minimum: 301
10417 06:56:29.265461 <6>[ 0.029212] LSM: Security Framework initializing
10418 06:56:29.272047 <6>[ 0.034153] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10419 06:56:29.282092 <6>[ 0.041967] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10420 06:56:29.292010 <6>[ 0.051434] cblist_init_generic: Setting adjustable number of callback queues.
10421 06:56:29.295307 <6>[ 0.058879] cblist_init_generic: Setting shift to 3 and lim to 1.
10422 06:56:29.305414 <6>[ 0.065216] cblist_init_generic: Setting adjustable number of callback queues.
10423 06:56:29.312517 <6>[ 0.072643] cblist_init_generic: Setting shift to 3 and lim to 1.
10424 06:56:29.315035 <6>[ 0.079081] rcu: Hierarchical SRCU implementation.
10425 06:56:29.321792 <6>[ 0.084097] rcu: Max phase no-delay instances is 1000.
10426 06:56:29.328268 <6>[ 0.091158] EFI services will not be available.
10427 06:56:29.331703 <6>[ 0.096116] smp: Bringing up secondary CPUs ...
10428 06:56:29.340004 <6>[ 0.101165] Detected VIPT I-cache on CPU1
10429 06:56:29.346401 <6>[ 0.101237] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10430 06:56:29.353473 <6>[ 0.101267] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10431 06:56:29.356615 <6>[ 0.101608] Detected VIPT I-cache on CPU2
10432 06:56:29.363170 <6>[ 0.101660] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10433 06:56:29.373190 <6>[ 0.101679] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10434 06:56:29.376363 <6>[ 0.101937] Detected VIPT I-cache on CPU3
10435 06:56:29.382764 <6>[ 0.101983] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10436 06:56:29.389708 <6>[ 0.101997] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10437 06:56:29.392905 <6>[ 0.102302] CPU features: detected: Spectre-v4
10438 06:56:29.399351 <6>[ 0.102309] CPU features: detected: Spectre-BHB
10439 06:56:29.402669 <6>[ 0.102314] Detected PIPT I-cache on CPU4
10440 06:56:29.409438 <6>[ 0.102371] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10441 06:56:29.415987 <6>[ 0.102388] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10442 06:56:29.422639 <6>[ 0.102679] Detected PIPT I-cache on CPU5
10443 06:56:29.429038 <6>[ 0.102741] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10444 06:56:29.435831 <6>[ 0.102758] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10445 06:56:29.439053 <6>[ 0.103040] Detected PIPT I-cache on CPU6
10446 06:56:29.445534 <6>[ 0.103104] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10447 06:56:29.452532 <6>[ 0.103121] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10448 06:56:29.458918 <6>[ 0.103419] Detected PIPT I-cache on CPU7
10449 06:56:29.465647 <6>[ 0.103483] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10450 06:56:29.472527 <6>[ 0.103499] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10451 06:56:29.475804 <6>[ 0.103546] smp: Brought up 1 node, 8 CPUs
10452 06:56:29.482179 <6>[ 0.244759] SMP: Total of 8 processors activated.
10453 06:56:29.485378 <6>[ 0.249680] CPU features: detected: 32-bit EL0 Support
10454 06:56:29.495072 <6>[ 0.255043] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10455 06:56:29.501738 <6>[ 0.263843] CPU features: detected: Common not Private translations
10456 06:56:29.508657 <6>[ 0.270318] CPU features: detected: CRC32 instructions
10457 06:56:29.511727 <6>[ 0.275670] CPU features: detected: RCpc load-acquire (LDAPR)
10458 06:56:29.518340 <6>[ 0.281630] CPU features: detected: LSE atomic instructions
10459 06:56:29.525165 <6>[ 0.287411] CPU features: detected: Privileged Access Never
10460 06:56:29.531919 <6>[ 0.293191] CPU features: detected: RAS Extension Support
10461 06:56:29.538138 <6>[ 0.298800] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10462 06:56:29.541595 <6>[ 0.306022] CPU: All CPU(s) started at EL2
10463 06:56:29.548090 <6>[ 0.310339] alternatives: applying system-wide alternatives
10464 06:56:29.557306 <6>[ 0.321105] devtmpfs: initialized
10465 06:56:29.570329 <6>[ 0.330140] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10466 06:56:29.579743 <6>[ 0.340104] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10467 06:56:29.586595 <6>[ 0.348227] pinctrl core: initialized pinctrl subsystem
10468 06:56:29.589552 <6>[ 0.354892] DMI not present or invalid.
10469 06:56:29.596649 <6>[ 0.359301] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10470 06:56:29.606214 <6>[ 0.366166] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10471 06:56:29.612870 <6>[ 0.373747] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10472 06:56:29.622521 <6>[ 0.381968] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10473 06:56:29.626271 <6>[ 0.390208] audit: initializing netlink subsys (disabled)
10474 06:56:29.636090 <5>[ 0.395900] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10475 06:56:29.642649 <6>[ 0.396611] thermal_sys: Registered thermal governor 'step_wise'
10476 06:56:29.649538 <6>[ 0.403866] thermal_sys: Registered thermal governor 'power_allocator'
10477 06:56:29.652865 <6>[ 0.410121] cpuidle: using governor menu
10478 06:56:29.659049 <6>[ 0.421080] NET: Registered PF_QIPCRTR protocol family
10479 06:56:29.665894 <6>[ 0.426565] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10480 06:56:29.672359 <6>[ 0.433669] ASID allocator initialised with 32768 entries
10481 06:56:29.676128 <6>[ 0.440254] Serial: AMBA PL011 UART driver
10482 06:56:29.685677 <4>[ 0.449011] Trying to register duplicate clock ID: 134
10483 06:56:29.741415 <6>[ 0.508267] KASLR enabled
10484 06:56:29.755569 <6>[ 0.515904] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10485 06:56:29.762163 <6>[ 0.522917] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10486 06:56:29.769390 <6>[ 0.529406] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10487 06:56:29.775805 <6>[ 0.536412] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10488 06:56:29.782227 <6>[ 0.542899] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10489 06:56:29.789059 <6>[ 0.549905] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10490 06:56:29.795194 <6>[ 0.556392] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10491 06:56:29.801785 <6>[ 0.563393] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10492 06:56:29.805529 <6>[ 0.570854] ACPI: Interpreter disabled.
10493 06:56:29.814215 <6>[ 0.577289] iommu: Default domain type: Translated
10494 06:56:29.820183 <6>[ 0.582438] iommu: DMA domain TLB invalidation policy: strict mode
10495 06:56:29.823822 <5>[ 0.589104] SCSI subsystem initialized
10496 06:56:29.830136 <6>[ 0.593356] usbcore: registered new interface driver usbfs
10497 06:56:29.836900 <6>[ 0.599088] usbcore: registered new interface driver hub
10498 06:56:29.840191 <6>[ 0.604643] usbcore: registered new device driver usb
10499 06:56:29.847401 <6>[ 0.610772] pps_core: LinuxPPS API ver. 1 registered
10500 06:56:29.857540 <6>[ 0.615962] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10501 06:56:29.860211 <6>[ 0.625304] PTP clock support registered
10502 06:56:29.863496 <6>[ 0.629546] EDAC MC: Ver: 3.0.0
10503 06:56:29.871344 <6>[ 0.634738] FPGA manager framework
10504 06:56:29.878043 <6>[ 0.638413] Advanced Linux Sound Architecture Driver Initialized.
10505 06:56:29.881007 <6>[ 0.645182] vgaarb: loaded
10506 06:56:29.887656 <6>[ 0.648337] clocksource: Switched to clocksource arch_sys_counter
10507 06:56:29.891112 <5>[ 0.654783] VFS: Disk quotas dquot_6.6.0
10508 06:56:29.897692 <6>[ 0.658968] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10509 06:56:29.900957 <6>[ 0.666160] pnp: PnP ACPI: disabled
10510 06:56:29.909434 <6>[ 0.672844] NET: Registered PF_INET protocol family
10511 06:56:29.919477 <6>[ 0.678436] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10512 06:56:29.930517 <6>[ 0.690754] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10513 06:56:29.940495 <6>[ 0.699571] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10514 06:56:29.946796 <6>[ 0.707543] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10515 06:56:29.956859 <6>[ 0.716241] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10516 06:56:29.964057 <6>[ 0.725991] TCP: Hash tables configured (established 65536 bind 65536)
10517 06:56:29.970510 <6>[ 0.732859] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10518 06:56:29.979894 <6>[ 0.740058] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10519 06:56:29.986671 <6>[ 0.747765] NET: Registered PF_UNIX/PF_LOCAL protocol family
10520 06:56:29.989889 <6>[ 0.753917] RPC: Registered named UNIX socket transport module.
10521 06:56:29.996442 <6>[ 0.760068] RPC: Registered udp transport module.
10522 06:56:30.000192 <6>[ 0.765001] RPC: Registered tcp transport module.
10523 06:56:30.006143 <6>[ 0.769934] RPC: Registered tcp NFSv4.1 backchannel transport module.
10524 06:56:30.012852 <6>[ 0.776598] PCI: CLS 0 bytes, default 64
10525 06:56:30.016431 <6>[ 0.780941] Unpacking initramfs...
10526 06:56:30.040270 <6>[ 0.800440] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10527 06:56:30.050199 <6>[ 0.809088] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10528 06:56:30.053690 <6>[ 0.817935] kvm [1]: IPA Size Limit: 40 bits
10529 06:56:30.060106 <6>[ 0.822464] kvm [1]: GICv3: no GICV resource entry
10530 06:56:30.063999 <6>[ 0.827483] kvm [1]: disabling GICv2 emulation
10531 06:56:30.070422 <6>[ 0.832167] kvm [1]: GIC system register CPU interface enabled
10532 06:56:30.073514 <6>[ 0.838338] kvm [1]: vgic interrupt IRQ18
10533 06:56:30.080331 <6>[ 0.842692] kvm [1]: VHE mode initialized successfully
10534 06:56:30.086589 <5>[ 0.849183] Initialise system trusted keyrings
10535 06:56:30.093407 <6>[ 0.854039] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10536 06:56:30.100965 <6>[ 0.864093] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10537 06:56:30.107359 <5>[ 0.870481] NFS: Registering the id_resolver key type
10538 06:56:30.110511 <5>[ 0.875781] Key type id_resolver registered
10539 06:56:30.117155 <5>[ 0.880196] Key type id_legacy registered
10540 06:56:30.123744 <6>[ 0.884473] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10541 06:56:30.130834 <6>[ 0.891394] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10542 06:56:30.136605 <6>[ 0.899104] 9p: Installing v9fs 9p2000 file system support
10543 06:56:30.172531 <5>[ 0.936004] Key type asymmetric registered
10544 06:56:30.175980 <5>[ 0.940336] Asymmetric key parser 'x509' registered
10545 06:56:30.186066 <6>[ 0.945485] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10546 06:56:30.189054 <6>[ 0.953097] io scheduler mq-deadline registered
10547 06:56:30.192656 <6>[ 0.957856] io scheduler kyber registered
10548 06:56:30.211490 <6>[ 0.974935] EINJ: ACPI disabled.
10549 06:56:30.243630 <4>[ 1.000533] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10550 06:56:30.253448 <4>[ 1.011178] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10551 06:56:30.268551 <6>[ 1.031962] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10552 06:56:30.276359 <6>[ 1.040000] printk: console [ttyS0] disabled
10553 06:56:30.304497 <6>[ 1.064626] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10554 06:56:30.311450 <6>[ 1.074098] printk: console [ttyS0] enabled
10555 06:56:30.314239 <6>[ 1.074098] printk: console [ttyS0] enabled
10556 06:56:30.320884 <6>[ 1.082993] printk: bootconsole [mtk8250] disabled
10557 06:56:30.323976 <6>[ 1.082993] printk: bootconsole [mtk8250] disabled
10558 06:56:30.330979 <6>[ 1.094199] SuperH (H)SCI(F) driver initialized
10559 06:56:30.334462 <6>[ 1.099481] msm_serial: driver initialized
10560 06:56:30.348011 <6>[ 1.108449] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10561 06:56:30.358468 <6>[ 1.116995] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10562 06:56:30.365013 <6>[ 1.125539] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10563 06:56:30.374704 <6>[ 1.134166] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10564 06:56:30.381450 <6>[ 1.142873] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10565 06:56:30.391539 <6>[ 1.151595] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10566 06:56:30.401457 <6>[ 1.160136] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10567 06:56:30.407842 <6>[ 1.168942] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10568 06:56:30.417798 <6>[ 1.177487] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10569 06:56:30.429541 <6>[ 1.193302] loop: module loaded
10570 06:56:30.436607 <6>[ 1.199270] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10571 06:56:30.459186 <4>[ 1.222613] mtk-pmic-keys: Failed to locate of_node [id: -1]
10572 06:56:30.465612 <6>[ 1.229446] megasas: 07.719.03.00-rc1
10573 06:56:30.475447 <6>[ 1.239089] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10574 06:56:30.484194 <6>[ 1.247732] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10575 06:56:30.501217 <6>[ 1.264427] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10576 06:56:30.556897 <6>[ 1.313988] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10577 06:56:30.760578 <6>[ 1.524314] Freeing initrd memory: 17380K
10578 06:56:30.770667 <6>[ 1.534532] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10579 06:56:30.782207 <6>[ 1.545726] tun: Universal TUN/TAP device driver, 1.6
10580 06:56:30.785208 <6>[ 1.551775] thunder_xcv, ver 1.0
10581 06:56:30.788615 <6>[ 1.555281] thunder_bgx, ver 1.0
10582 06:56:30.791998 <6>[ 1.558776] nicpf, ver 1.0
10583 06:56:30.802195 <6>[ 1.562807] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10584 06:56:30.806109 <6>[ 1.570283] hns3: Copyright (c) 2017 Huawei Corporation.
10585 06:56:30.812736 <6>[ 1.575871] hclge is initializing
10586 06:56:30.816085 <6>[ 1.579452] e1000: Intel(R) PRO/1000 Network Driver
10587 06:56:30.822540 <6>[ 1.584581] e1000: Copyright (c) 1999-2006 Intel Corporation.
10588 06:56:30.826031 <6>[ 1.590594] e1000e: Intel(R) PRO/1000 Network Driver
10589 06:56:30.832591 <6>[ 1.595809] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10590 06:56:30.839137 <6>[ 1.601996] igb: Intel(R) Gigabit Ethernet Network Driver
10591 06:56:30.845683 <6>[ 1.607645] igb: Copyright (c) 2007-2014 Intel Corporation.
10592 06:56:30.852415 <6>[ 1.613486] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10593 06:56:30.858707 <6>[ 1.620004] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10594 06:56:30.862356 <6>[ 1.626466] sky2: driver version 1.30
10595 06:56:30.868803 <6>[ 1.631481] VFIO - User Level meta-driver version: 0.3
10596 06:56:30.876199 <6>[ 1.639715] usbcore: registered new interface driver usb-storage
10597 06:56:30.882870 <6>[ 1.646172] usbcore: registered new device driver onboard-usb-hub
10598 06:56:30.891600 <6>[ 1.655344] mt6397-rtc mt6359-rtc: registered as rtc0
10599 06:56:30.901560 <6>[ 1.660810] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:56:30 UTC (1706943390)
10600 06:56:30.905239 <6>[ 1.670379] i2c_dev: i2c /dev entries driver
10601 06:56:30.921755 <6>[ 1.682193] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10602 06:56:30.941921 <6>[ 1.705172] cpu cpu0: EM: created perf domain
10603 06:56:30.944912 <6>[ 1.710091] cpu cpu4: EM: created perf domain
10604 06:56:30.952393 <6>[ 1.715708] sdhci: Secure Digital Host Controller Interface driver
10605 06:56:30.958678 <6>[ 1.722141] sdhci: Copyright(c) Pierre Ossman
10606 06:56:30.965688 <6>[ 1.727095] Synopsys Designware Multimedia Card Interface Driver
10607 06:56:30.972345 <6>[ 1.733739] sdhci-pltfm: SDHCI platform and OF driver helper
10608 06:56:30.975901 <6>[ 1.733787] mmc0: CQHCI version 5.10
10609 06:56:30.982166 <6>[ 1.743734] ledtrig-cpu: registered to indicate activity on CPUs
10610 06:56:30.988587 <6>[ 1.750643] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10611 06:56:30.995418 <6>[ 1.757692] usbcore: registered new interface driver usbhid
10612 06:56:30.998586 <6>[ 1.763513] usbhid: USB HID core driver
10613 06:56:31.005242 <6>[ 1.767716] spi_master spi0: will run message pump with realtime priority
10614 06:56:31.049346 <6>[ 1.806168] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10615 06:56:31.069060 <6>[ 1.822256] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10616 06:56:31.072161 <6>[ 1.836598] mmc0: Command Queue Engine enabled
10617 06:56:31.079136 <6>[ 1.841368] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10618 06:56:31.085574 <6>[ 1.848093] cros-ec-spi spi0.0: Chrome EC device registered
10619 06:56:31.088852 <6>[ 1.848622] mmcblk0: mmc0:0001 DA4128 116 GiB
10620 06:56:31.102638 <6>[ 1.866317] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10621 06:56:31.110430 <6>[ 1.873826] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10622 06:56:31.116871 <6>[ 1.879924] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10623 06:56:31.123319 <6>[ 1.886129] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10624 06:56:31.133663 <6>[ 1.890358] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10625 06:56:31.140266 <6>[ 1.903230] NET: Registered PF_PACKET protocol family
10626 06:56:31.143533 <6>[ 1.908626] 9pnet: Installing 9P2000 support
10627 06:56:31.150232 <5>[ 1.913194] Key type dns_resolver registered
10628 06:56:31.153578 <6>[ 1.918185] registered taskstats version 1
10629 06:56:31.159880 <5>[ 1.922568] Loading compiled-in X.509 certificates
10630 06:56:31.189109 <4>[ 1.946014] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10631 06:56:31.199250 <4>[ 1.956787] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10632 06:56:31.205922 <3>[ 1.967348] debugfs: File 'uA_load' in directory '/' already present!
10633 06:56:31.212507 <3>[ 1.974067] debugfs: File 'min_uV' in directory '/' already present!
10634 06:56:31.218736 <3>[ 1.980693] debugfs: File 'max_uV' in directory '/' already present!
10635 06:56:31.225812 <3>[ 1.987315] debugfs: File 'constraint_flags' in directory '/' already present!
10636 06:56:31.236577 <3>[ 1.997093] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10637 06:56:31.247800 <6>[ 2.011263] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10638 06:56:31.254333 <6>[ 2.018047] xhci-mtk 11200000.usb: xHCI Host Controller
10639 06:56:31.261263 <6>[ 2.023547] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10640 06:56:31.271461 <6>[ 2.031401] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10641 06:56:31.277688 <6>[ 2.040837] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10642 06:56:31.284555 <6>[ 2.046914] xhci-mtk 11200000.usb: xHCI Host Controller
10643 06:56:31.291431 <6>[ 2.052405] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10644 06:56:31.297602 <6>[ 2.060054] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10645 06:56:31.304554 <6>[ 2.067758] hub 1-0:1.0: USB hub found
10646 06:56:31.307589 <6>[ 2.071771] hub 1-0:1.0: 1 port detected
10647 06:56:31.314477 <6>[ 2.076056] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10648 06:56:31.321010 <6>[ 2.084595] hub 2-0:1.0: USB hub found
10649 06:56:31.324023 <6>[ 2.088603] hub 2-0:1.0: 1 port detected
10650 06:56:31.332971 <6>[ 2.096654] mtk-msdc 11f70000.mmc: Got CD GPIO
10651 06:56:31.350531 <6>[ 2.110614] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10652 06:56:31.356936 <6>[ 2.118647] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10653 06:56:31.366885 <4>[ 2.126583] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10654 06:56:31.376972 <6>[ 2.136156] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10655 06:56:31.383280 <6>[ 2.144235] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10656 06:56:31.390023 <6>[ 2.152370] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10657 06:56:31.399751 <6>[ 2.160295] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10658 06:56:31.406656 <6>[ 2.168112] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10659 06:56:31.416809 <6>[ 2.175932] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10660 06:56:31.426364 <6>[ 2.186387] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10661 06:56:31.433037 <6>[ 2.194752] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10662 06:56:31.443028 <6>[ 2.203094] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10663 06:56:31.450109 <6>[ 2.211435] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10664 06:56:31.459591 <6>[ 2.219776] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10665 06:56:31.466578 <6>[ 2.228115] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10666 06:56:31.476687 <6>[ 2.236455] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10667 06:56:31.483109 <6>[ 2.244795] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10668 06:56:31.492842 <6>[ 2.253140] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10669 06:56:31.499612 <6>[ 2.261479] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10670 06:56:31.509630 <6>[ 2.269819] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10671 06:56:31.519575 <6>[ 2.278158] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10672 06:56:31.526043 <6>[ 2.286498] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10673 06:56:31.536212 <6>[ 2.294836] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10674 06:56:31.542890 <6>[ 2.303176] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10675 06:56:31.549720 <6>[ 2.312000] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10676 06:56:31.556077 <6>[ 2.319313] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10677 06:56:31.562707 <6>[ 2.326252] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10678 06:56:31.572640 <6>[ 2.333138] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10679 06:56:31.579028 <6>[ 2.340113] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10680 06:56:31.586027 <6>[ 2.346966] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10681 06:56:31.595723 <6>[ 2.356096] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10682 06:56:31.605632 <6>[ 2.365232] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10683 06:56:31.615834 <6>[ 2.374525] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10684 06:56:31.625333 <6>[ 2.383992] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10685 06:56:31.635578 <6>[ 2.393459] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10686 06:56:31.641940 <6>[ 2.402578] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10687 06:56:31.651730 <6>[ 2.412043] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10688 06:56:31.661944 <6>[ 2.421162] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10689 06:56:31.671839 <6>[ 2.430455] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10690 06:56:31.681704 <6>[ 2.440615] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10691 06:56:31.692090 <6>[ 2.452400] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10692 06:56:31.698765 <6>[ 2.462265] Trying to probe devices needed for running init ...
10693 06:56:31.732553 <6>[ 2.492608] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10694 06:56:31.886767 <6>[ 2.650463] hub 1-1:1.0: USB hub found
10695 06:56:31.890186 <6>[ 2.654966] hub 1-1:1.0: 4 ports detected
10696 06:56:31.900194 <6>[ 2.663921] hub 1-1:1.0: USB hub found
10697 06:56:31.903789 <6>[ 2.668294] hub 1-1:1.0: 4 ports detected
10698 06:56:32.012499 <6>[ 2.772890] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10699 06:56:32.038051 <6>[ 2.801471] hub 2-1:1.0: USB hub found
10700 06:56:32.041030 <6>[ 2.805917] hub 2-1:1.0: 3 ports detected
10701 06:56:32.049362 <6>[ 2.813070] hub 2-1:1.0: USB hub found
10702 06:56:32.052754 <6>[ 2.817439] hub 2-1:1.0: 3 ports detected
10703 06:56:32.228426 <6>[ 2.988704] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10704 06:56:32.360592 <6>[ 3.123839] hub 1-1.4:1.0: USB hub found
10705 06:56:32.363264 <6>[ 3.128432] hub 1-1.4:1.0: 2 ports detected
10706 06:56:32.371564 <6>[ 3.135437] hub 1-1.4:1.0: USB hub found
10707 06:56:32.374773 <6>[ 3.139950] hub 1-1.4:1.0: 2 ports detected
10708 06:56:32.444331 <6>[ 3.204717] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10709 06:56:32.672043 <6>[ 3.432643] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10710 06:56:32.863993 <6>[ 3.624645] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10711 06:56:44.001039 <6>[ 14.769637] ALSA device list:
10712 06:56:44.007591 <6>[ 14.772926] No soundcards found.
10713 06:56:44.015841 <6>[ 14.780822] Freeing unused kernel memory: 8448K
10714 06:56:44.019101 <6>[ 14.785836] Run /init as init process
10715 06:56:44.029664 Loading, please wait...
10716 06:56:44.050573 Starting version 247.3-7+deb11u2
10717 06:56:44.280007 <6>[ 15.042123] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10718 06:56:44.290678 <6>[ 15.055889] remoteproc remoteproc0: scp is available
10719 06:56:44.297468 <6>[ 15.061726] remoteproc remoteproc0: powering up scp
10720 06:56:44.303864 <6>[ 15.067075] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10721 06:56:44.311297 <6>[ 15.076571] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10722 06:56:44.327024 <3>[ 15.088897] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 06:56:44.333545 <3>[ 15.097077] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 06:56:44.343712 <6>[ 15.099858] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10725 06:56:44.350297 <3>[ 15.105227] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 06:56:44.360064 <4>[ 15.121359] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10727 06:56:44.366622 <6>[ 15.121798] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10728 06:56:44.376458 <3>[ 15.122767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 06:56:44.383308 <3>[ 15.122787] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 06:56:44.389929 <3>[ 15.122792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 06:56:44.399657 <3>[ 15.122799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 06:56:44.406564 <3>[ 15.122803] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 06:56:44.412919 <6>[ 15.124517] mc: Linux media interface: v0.10
10734 06:56:44.419917 <3>[ 15.137645] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 06:56:44.429889 <6>[ 15.145616] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10736 06:56:44.436454 <4>[ 15.154964] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10737 06:56:44.443050 <3>[ 15.163032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 06:56:44.452811 <6>[ 15.170553] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10739 06:56:44.460104 <3>[ 15.177985] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 06:56:44.466968 <6>[ 15.185280] videodev: Linux video capture interface: v2.00
10741 06:56:44.473558 <6>[ 15.186014] usbcore: registered new device driver r8152-cfgselector
10742 06:56:44.480079 <3>[ 15.190580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 06:56:44.490623 <3>[ 15.190707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 06:56:44.497391 <4>[ 15.200821] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10745 06:56:44.503963 <4>[ 15.200821] Fallback method does not support PEC.
10746 06:56:44.510304 <3>[ 15.206595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 06:56:44.517276 <3>[ 15.206601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 06:56:44.527040 <3>[ 15.206615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 06:56:44.533671 <6>[ 15.208344] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10750 06:56:44.543408 <6>[ 15.208364] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10751 06:56:44.550099 <6>[ 15.208371] remoteproc remoteproc0: remote processor scp is now up
10752 06:56:44.556950 <6>[ 15.224986] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10753 06:56:44.563328 <3>[ 15.230420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 06:56:44.573589 <3>[ 15.230453] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10755 06:56:44.583451 <3>[ 15.230546] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 06:56:44.589925 <6>[ 15.240478] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10757 06:56:44.599808 <3>[ 15.265505] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10758 06:56:44.609766 <6>[ 15.269016] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10759 06:56:44.616724 <6>[ 15.269405] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10760 06:56:44.626652 <6>[ 15.272940] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10761 06:56:44.632793 <6>[ 15.289754] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10762 06:56:44.642677 <6>[ 15.300134] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10763 06:56:44.649436 <6>[ 15.303931] pci_bus 0000:00: root bus resource [bus 00-ff]
10764 06:56:44.655966 <4>[ 15.323848] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10765 06:56:44.665723 <6>[ 15.327146] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10766 06:56:44.675684 <6>[ 15.327153] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10767 06:56:44.682287 <4>[ 15.335254] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10768 06:56:44.688932 <6>[ 15.344131] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10769 06:56:44.692299 <6>[ 15.352725] Bluetooth: Core ver 2.22
10770 06:56:44.698993 <6>[ 15.360402] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10771 06:56:44.705718 <6>[ 15.369241] NET: Registered PF_BLUETOOTH protocol family
10772 06:56:44.712061 <6>[ 15.370380] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10773 06:56:44.725306 <6>[ 15.371491] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10774 06:56:44.731914 <6>[ 15.371591] usbcore: registered new interface driver uvcvideo
10775 06:56:44.735568 <6>[ 15.379322] pci 0000:00:00.0: supports D1 D2
10776 06:56:44.742086 <6>[ 15.388274] Bluetooth: HCI device and connection manager initialized
10777 06:56:44.748439 <6>[ 15.388290] Bluetooth: HCI socket layer initialized
10778 06:56:44.755249 <6>[ 15.396612] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10779 06:56:44.758423 <6>[ 15.400466] r8152 2-1.3:1.0 eth0: v1.12.13
10780 06:56:44.765107 <6>[ 15.400531] usbcore: registered new interface driver r8152
10781 06:56:44.768498 <6>[ 15.403480] Bluetooth: L2CAP socket layer initialized
10782 06:56:44.775213 <6>[ 15.404010] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10783 06:56:44.784906 <6>[ 15.413707] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10784 06:56:44.788192 <6>[ 15.418512] Bluetooth: SCO socket layer initialized
10785 06:56:44.794747 <6>[ 15.418821] usbcore: registered new interface driver cdc_ether
10786 06:56:44.801446 <6>[ 15.427650] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10787 06:56:44.808100 <6>[ 15.435088] usbcore: registered new interface driver r8153_ecm
10788 06:56:44.814643 <6>[ 15.444589] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10789 06:56:44.820991 <6>[ 15.481228] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10790 06:56:44.827845 <6>[ 15.482823] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10791 06:56:44.834404 <6>[ 15.483294] usbcore: registered new interface driver btusb
10792 06:56:44.844321 <4>[ 15.484260] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10793 06:56:44.850793 <3>[ 15.484274] Bluetooth: hci0: Failed to load firmware file (-2)
10794 06:56:44.857293 <3>[ 15.484278] Bluetooth: hci0: Failed to set up firmware (-2)
10795 06:56:44.867412 <4>[ 15.484282] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10796 06:56:44.874002 <6>[ 15.637596] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10797 06:56:44.880769 <6>[ 15.645174] pci 0000:01:00.0: supports D1 D2
10798 06:56:44.886992 <6>[ 15.649694] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10799 06:56:44.906468 <6>[ 15.668641] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10800 06:56:44.913365 <6>[ 15.675547] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10801 06:56:44.919927 <6>[ 15.683633] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10802 06:56:44.929589 <6>[ 15.691631] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10803 06:56:44.936588 <6>[ 15.699634] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10804 06:56:44.946654 <6>[ 15.707635] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10805 06:56:44.949857 <6>[ 15.715637] pci 0000:00:00.0: PCI bridge to [bus 01]
10806 06:56:44.959439 <6>[ 15.720853] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10807 06:56:44.966273 <6>[ 15.728968] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10808 06:56:44.972719 <6>[ 15.735858] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10809 06:56:44.979488 <6>[ 15.742731] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10810 06:56:45.002287 <5>[ 15.764594] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10811 06:56:45.022502 <5>[ 15.784479] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10812 06:56:45.028873 <5>[ 15.791873] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10813 06:56:45.038956 <4>[ 15.800377] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10814 06:56:45.042294 <6>[ 15.809281] cfg80211: failed to load regulatory.db
10815 06:56:45.101029 <6>[ 15.863136] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10816 06:56:45.107549 <6>[ 15.870953] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10817 06:56:45.132301 <6>[ 15.897771] mt7921e 0000:01:00.0: ASIC revision: 79610010
10818 06:56:45.234205 <6>[ 15.996222] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10819 06:56:45.237301 <6>[ 15.996222]
10820 06:56:45.240931 Begin: Loading essential drivers ... done.
10821 06:56:45.244018 Begin: Running /scripts/init-premount ... done.
10822 06:56:45.250888 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10823 06:56:45.260613 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10824 06:56:45.264124 Device /sys/class/net/enx0024323078ff found
10825 06:56:45.264617 done.
10826 06:56:45.306426 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10827 06:56:45.502452 <6>[ 16.264713] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10828 06:56:46.233215 <6>[ 16.998788] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10829 06:56:46.350955 <6>[ 17.116528] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10830 06:56:46.394819 IP-Config: no response after 2 secs - giving up
10831 06:56:46.426619 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10832 06:56:47.097897 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10833 06:56:47.100903 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10834 06:56:47.107704 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10835 06:56:47.117392 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10836 06:56:47.124045 host : mt8192-asurada-spherion-r0-cbg-8
10837 06:56:47.130688 domain : lava-rack
10838 06:56:47.134067 rootserver: 192.168.201.1 rootpath:
10839 06:56:47.134144 filename :
10840 06:56:47.240401 done.
10841 06:56:47.248874 Begin: Running /scripts/nfs-bottom ... done.
10842 06:56:47.267006 Begin: Running /scripts/init-bottom ... done.
10843 06:56:48.513481 <6>[ 19.279545] NET: Registered PF_INET6 protocol family
10844 06:56:48.521483 <6>[ 19.287407] Segment Routing with IPv6
10845 06:56:48.524547 <6>[ 19.291381] In-situ OAM (IOAM) with IPv6
10846 06:56:48.662275 <30>[ 19.408221] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10847 06:56:48.665735 <30>[ 19.432296] systemd[1]: Detected architecture arm64.
10848 06:56:48.689019
10849 06:56:48.692392 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10850 06:56:48.692809
10851 06:56:48.709914 <30>[ 19.475605] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10852 06:56:49.676274 <30>[ 20.438829] systemd[1]: Queued start job for default target Graphical Interface.
10853 06:56:49.717220 <30>[ 20.483013] systemd[1]: Created slice system-getty.slice.
10854 06:56:49.724181 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10855 06:56:49.740044 <30>[ 20.506076] systemd[1]: Created slice system-modprobe.slice.
10856 06:56:49.746971 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10857 06:56:49.763831 <30>[ 20.529899] systemd[1]: Created slice system-serial\x2dgetty.slice.
10858 06:56:49.774164 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10859 06:56:49.787817 <30>[ 20.553717] systemd[1]: Created slice User and Session Slice.
10860 06:56:49.794583 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10861 06:56:49.815174 <30>[ 20.577469] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10862 06:56:49.824718 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10863 06:56:49.842737 <30>[ 20.605385] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10864 06:56:49.849430 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10865 06:56:49.873560 <30>[ 20.632776] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10866 06:56:49.879973 <30>[ 20.644917] systemd[1]: Reached target Local Encrypted Volumes.
10867 06:56:49.886954 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10868 06:56:49.903419 <30>[ 20.669171] systemd[1]: Reached target Paths.
10869 06:56:49.906821 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10870 06:56:49.922671 <30>[ 20.688615] systemd[1]: Reached target Remote File Systems.
10871 06:56:49.929297 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10872 06:56:49.942564 <30>[ 20.708580] systemd[1]: Reached target Slices.
10873 06:56:49.945955 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10874 06:56:49.962712 <30>[ 20.728609] systemd[1]: Reached target Swap.
10875 06:56:49.965894 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10876 06:56:49.986404 <30>[ 20.749112] systemd[1]: Listening on initctl Compatibility Named Pipe.
10877 06:56:49.992857 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10878 06:56:50.000115 <30>[ 20.765319] systemd[1]: Listening on Journal Audit Socket.
10879 06:56:50.006165 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10880 06:56:50.023879 <30>[ 20.790035] systemd[1]: Listening on Journal Socket (/dev/log).
10881 06:56:50.030755 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10882 06:56:50.047250 <30>[ 20.813246] systemd[1]: Listening on Journal Socket.
10883 06:56:50.053950 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10884 06:56:50.071467 <30>[ 20.834319] systemd[1]: Listening on Network Service Netlink Socket.
10885 06:56:50.078157 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10886 06:56:50.094134 <30>[ 20.859953] systemd[1]: Listening on udev Control Socket.
10887 06:56:50.100423 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10888 06:56:50.115458 <30>[ 20.881073] systemd[1]: Listening on udev Kernel Socket.
10889 06:56:50.121964 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10890 06:56:50.171402 <30>[ 20.937160] systemd[1]: Mounting Huge Pages File System...
10891 06:56:50.177854 Mounting [0;1;39mHuge Pages File System[0m...
10892 06:56:50.192839 <30>[ 20.958995] systemd[1]: Mounting POSIX Message Queue File System...
10893 06:56:50.199580 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10894 06:56:50.217752 <30>[ 20.983833] systemd[1]: Mounting Kernel Debug File System...
10895 06:56:50.224591 Mounting [0;1;39mKernel Debug File System[0m...
10896 06:56:50.242526 <30>[ 21.005183] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10897 06:56:50.261221 <30>[ 21.023988] systemd[1]: Starting Create list of static device nodes for the current kernel...
10898 06:56:50.267775 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10899 06:56:50.287088 <30>[ 21.053061] systemd[1]: Starting Load Kernel Module configfs...
10900 06:56:50.293592 Starting [0;1;39mLoad Kernel Module configfs[0m...
10901 06:56:50.311869 <30>[ 21.077553] systemd[1]: Starting Load Kernel Module drm...
10902 06:56:50.317880 Starting [0;1;39mLoad Kernel Module drm[0m...
10903 06:56:50.335435 <30>[ 21.101419] systemd[1]: Starting Load Kernel Module fuse...
10904 06:56:50.341786 Starting [0;1;39mLoad Kernel Module fuse[0m...
10905 06:56:50.365327 <30>[ 21.128215] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10906 06:56:50.380683 <6>[ 21.146429] fuse: init (API version 7.37)
10907 06:56:50.407448 <30>[ 21.173481] systemd[1]: Starting Journal Service...
10908 06:56:50.414024 Starting [0;1;39mJournal Service[0m...
10909 06:56:50.438775 <30>[ 21.204955] systemd[1]: Starting Load Kernel Modules...
10910 06:56:50.445545 Starting [0;1;39mLoad Kernel Modules[0m...
10911 06:56:50.463969 <30>[ 21.227246] systemd[1]: Starting Remount Root and Kernel File Systems...
10912 06:56:50.470621 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10913 06:56:50.485090 <30>[ 21.251575] systemd[1]: Starting Coldplug All udev Devices...
10914 06:56:50.491751 Starting [0;1;39mColdplug All udev Devices[0m...
10915 06:56:50.510895 <30>[ 21.277128] systemd[1]: Mounted Huge Pages File System.
10916 06:56:50.517397 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10917 06:56:50.535343 <30>[ 21.301337] systemd[1]: Mounted POSIX Message Queue File System.
10918 06:56:50.541892 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10919 06:56:50.559233 <30>[ 21.324904] systemd[1]: Mounted Kernel Debug File System.
10920 06:56:50.572503 [[0;32m OK [0m] Mounted [0;<3>[ 21.332632] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 06:56:50.575430 1;39mKernel Debug File System[0m.
10922 06:56:50.595111 <30>[ 21.357998] systemd[1]: Finished Create list of static device nodes for the current kernel.
10923 06:56:50.608847 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes<3>[ 21.371336] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 06:56:50.611989 for the current kernel[0m.
10925 06:56:50.627294 <30>[ 21.393596] systemd[1]: modprobe@configfs.service: Succeeded.
10926 06:56:50.634363 <30>[ 21.400513] systemd[1]: Finished Load Kernel Module configfs.
10927 06:56:50.641136 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10928 06:56:50.663170 <3>[ 21.425955] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 06:56:50.670790 <30>[ 21.436774] systemd[1]: modprobe@drm.service: Succeeded.
10930 06:56:50.677196 <30>[ 21.443479] systemd[1]: Finished Load Kernel Module drm.
10931 06:56:50.694667 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m<3>[ 21.455315] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 06:56:50.695124 .
10933 06:56:50.713224 <30>[ 21.478558] systemd[1]: modprobe@fuse.service: Succeeded.
10934 06:56:50.723264 <3>[ 21.485167] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 06:56:50.729614 <30>[ 21.485714] systemd[1]: Finished Load Kernel Module fuse.
10936 06:56:50.736375 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10937 06:56:50.752288 <3>[ 21.514761] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 06:56:50.759901 <30>[ 21.526055] systemd[1]: Finished Load Kernel Modules.
10939 06:56:50.766429 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10940 06:56:50.781568 <3>[ 21.544451] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 06:56:50.791693 <30>[ 21.554362] systemd[1]: Finished Remount Root and Kernel File Systems.
10942 06:56:50.798454 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10943 06:56:50.811586 <3>[ 21.574023] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 06:56:50.841177 <3>[ 21.603814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 06:56:50.854873 <30>[ 21.620888] systemd[1]: Mounting FUSE Control File System...
10946 06:56:50.862020 Mounting [0;1;39mFUSE Control File System[0m...
10947 06:56:50.871716 <3>[ 21.633532] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 06:56:50.883102 <30>[ 21.645814] systemd[1]: Mounting Kernel Configuration File System...
10949 06:56:50.886270 Mounting [0;1;39mKernel Configuration File System[0m...
10950 06:56:50.910132 <30>[ 21.673193] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10951 06:56:50.919952 <30>[ 21.682340] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10952 06:56:50.962931 <30>[ 21.729473] systemd[1]: Starting Load/Save Random Seed...
10953 06:56:50.969467 Starting [0;1;39mLoad/Save Random Seed[0m...
10954 06:56:50.986713 <30>[ 21.753303] systemd[1]: Starting Apply Kernel Variables...
10955 06:56:50.993966 Starting [0;1;39mApply Kernel Variables[0m...
10956 06:56:51.010530 <4>[ 21.766028] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10957 06:56:51.017083 <3>[ 21.781742] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10958 06:56:51.023970 <30>[ 21.785577] systemd[1]: Starting Create System Users...
10959 06:56:51.027126 Starting [0;1;39mCreate System Users[0m...
10960 06:56:51.044435 <30>[ 21.810979] systemd[1]: Started Journal Service.
10961 06:56:51.051186 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10962 06:56:51.074956 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10963 06:56:51.086198 See 'systemctl status systemd-udev-trigger.service' for details.
10964 06:56:51.102746 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10965 06:56:51.118707 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10966 06:56:51.135577 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10967 06:56:51.152045 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10968 06:56:51.167843 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10969 06:56:51.223099 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10970 06:56:51.244921 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10971 06:56:51.284315 <46>[ 22.047546] systemd-journald[294]: Received client request to flush runtime journal.
10972 06:56:51.330476 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10973 06:56:51.342633 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10974 06:56:51.358144 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10975 06:56:51.422402 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10976 06:56:52.706951 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10977 06:56:52.754503 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10978 06:56:52.787748 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10979 06:56:52.847441 Starting [0;1;39mNetwork Service[0m...
10980 06:56:53.167391 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10981 06:56:53.187040 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10982 06:56:53.238994 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10983 06:56:53.513032 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10984 06:56:53.529452 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10985 06:56:53.571708 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10986 06:56:53.591135 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10987 06:56:53.611580 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10988 06:56:53.661824 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10989 06:56:53.674629 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10990 06:56:53.731071 Starting [0;1;39mNetwork Name Resolution[0m...
10991 06:56:53.759532 Starting [0;1;39mNetwork Time Synchronization[0m...
10992 06:56:53.779782 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10993 06:56:53.831802 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10994 06:56:53.982461 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10995 06:56:53.998661 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10996 06:56:54.021411 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10997 06:56:54.034445 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10998 06:56:54.049888 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10999 06:56:54.168116 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11000 06:56:54.208800 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11001 06:56:54.235238 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11002 06:56:54.256379 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11003 06:56:54.269849 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11004 06:56:54.304090 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11005 06:56:54.318038 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11006 06:56:54.333887 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11007 06:56:54.370887 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11008 06:56:54.405004 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11009 06:56:54.467941 Starting [0;1;39mUser Login Management[0m...
11010 06:56:54.484158 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11011 06:56:54.506509 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11012 06:56:54.523894 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11013 06:56:54.578759 Starting [0;1;39mPermit User Sessions[0m...
11014 06:56:54.696838 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11015 06:56:54.753987 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11016 06:56:54.776507 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11017 06:56:54.791824 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11018 06:56:54.809382 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11019 06:56:54.827117 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11020 06:56:54.843934 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11021 06:56:54.862280 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11022 06:56:54.923621 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11023 06:56:54.971860 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11024 06:56:55.062736
11025 06:56:55.062877
11026 06:56:55.065576 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11027 06:56:55.065734
11028 06:56:55.069023 debian-bullseye-arm64 login: root (automatic login)
11029 06:56:55.069127
11030 06:56:55.069208
11031 06:56:55.460606 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
11032 06:56:55.461128
11033 06:56:55.467166 The programs included with the Debian GNU/Linux system are free software;
11034 06:56:55.473791 the exact distribution terms for each program are described in the
11035 06:56:55.476953 individual files in /usr/share/doc/*/copyright.
11036 06:56:55.477426
11037 06:56:55.483788 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11038 06:56:55.486706 permitted by applicable law.
11039 06:56:56.522116 Matched prompt #10: / #
11041 06:56:56.522409 Setting prompt string to ['/ #']
11042 06:56:56.522511 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11044 06:56:56.522711 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11045 06:56:56.522807 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11046 06:56:56.522879 Setting prompt string to ['/ #']
11047 06:56:56.522938 Forcing a shell prompt, looking for ['/ #']
11049 06:56:56.573145 / #
11050 06:56:56.573245 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11051 06:56:56.573349 Waiting using forced prompt support (timeout 00:02:30)
11052 06:56:56.578012
11053 06:56:56.578274 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11054 06:56:56.578363 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11056 06:56:56.678678 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694862/extract-nfsrootfs-9tq3hp0n'
11057 06:56:56.683932 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694862/extract-nfsrootfs-9tq3hp0n'
11059 06:56:56.784408 / # export NFS_SERVER_IP='192.168.201.1'
11060 06:56:56.789330 export NFS_SERVER_IP='192.168.201.1'
11061 06:56:56.789630 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11062 06:56:56.789740 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
11063 06:56:56.789833 end: 2 depthcharge-action (duration 00:01:46) [common]
11064 06:56:56.789921 start: 3 lava-test-retry (timeout 00:07:30) [common]
11065 06:56:56.790006 start: 3.1 lava-test-shell (timeout 00:07:30) [common]
11066 06:56:56.790087 Using namespace: common
11068 06:56:56.890393 / # #
11069 06:56:56.890507 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11070 06:56:56.895300 #
11071 06:56:56.895566 Using /lava-12694862
11073 06:56:56.995855 / # export SHELL=/bin/bash
11074 06:56:57.000763 export SHELL=/bin/bash
11076 06:56:57.101222 / # . /lava-12694862/environment
11077 06:56:57.106740 . /lava-12694862/environment
11079 06:56:57.212773 / # /lava-12694862/bin/lava-test-runner /lava-12694862/0
11080 06:56:57.212883 Test shell timeout: 10s (minimum of the action and connection timeout)
11081 06:56:57.217555 /lava-12694862/bin/lava-test-runner /lava-12694862/0
11082 06:56:57.530770 + export TESTRUN_ID=0_timesync-off
11083 06:56:57.534063 + TESTRUN_ID=0_timesync-off
11084 06:56:57.537308 + cd /lava-12694862/0/tests/0_timesync-off
11085 06:56:57.540498 ++ cat uuid
11086 06:56:57.546204 + UUID=12694862_1.6.2.3.1
11087 06:56:57.546283 + set +x
11088 06:56:57.552527 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12694862_1.6.2.3.1>
11089 06:56:57.552781 Received signal: <STARTRUN> 0_timesync-off 12694862_1.6.2.3.1
11090 06:56:57.552858 Starting test lava.0_timesync-off (12694862_1.6.2.3.1)
11091 06:56:57.552953 Skipping test definition patterns.
11092 06:56:57.555918 + systemctl stop systemd-timesyncd
11093 06:56:57.610544 + set +x
11094 06:56:57.613890 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12694862_1.6.2.3.1>
11095 06:56:57.614142 Received signal: <ENDRUN> 0_timesync-off 12694862_1.6.2.3.1
11096 06:56:57.614258 Ending use of test pattern.
11097 06:56:57.614347 Ending test lava.0_timesync-off (12694862_1.6.2.3.1), duration 0.06
11099 06:56:57.704502 + export TESTRUN_ID=1_kselftest-arm64
11100 06:56:57.704641 + TESTRUN_ID=1_kselftest-arm64
11101 06:56:57.711107 + cd /lava-12694862/0/tests/1_kselftest-arm64
11102 06:56:57.711192 ++ cat uuid
11103 06:56:57.716862 + UUID=12694862_1.6.2.3.5
11104 06:56:57.716973 + set +x
11105 06:56:57.723424 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12694862_1.6.2.3.5>
11106 06:56:57.723676 Received signal: <STARTRUN> 1_kselftest-arm64 12694862_1.6.2.3.5
11107 06:56:57.723750 Starting test lava.1_kselftest-arm64 (12694862_1.6.2.3.5)
11108 06:56:57.723833 Skipping test definition patterns.
11109 06:56:57.726745 + cd ./automated/linux/kselftest/
11110 06:56:57.752956 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11111 06:56:57.797131 INFO: install_deps skipped
11112 06:56:57.920198 --2024-02-03 06:56:57-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11113 06:56:57.945323 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11114 06:56:58.085181 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11115 06:56:58.219514 HTTP request sent, awaiting response... 200 OK
11116 06:56:58.223112 Length: 2965368 (2.8M) [application/octet-stream]
11117 06:56:58.226233 Saving to: 'kselftest.tar.xz'
11118 06:56:58.226318
11119 06:56:58.226385
11120 06:56:58.486705 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11121 06:56:58.754581 kselftest.tar.xz 1%[ ] 47.81K 175KB/s
11122 06:56:59.021317 kselftest.tar.xz 7%[> ] 217.50K 397KB/s
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11126 06:56:59.360933
11127 06:56:59.618395 2024-02-03 06:56:59 (2.43 MB/s) - 'kselftest.tar.xz' saved [2965368/2965368]
11128 06:56:59.618554
11129 06:57:05.816370 skiplist:
11130 06:57:05.819512 ========================================
11131 06:57:05.822476 ========================================
11132 06:57:05.872944 arm64:tags_test
11133 06:57:05.876437 arm64:run_tags_test.sh
11134 06:57:05.876514 arm64:fake_sigreturn_bad_magic
11135 06:57:05.879680 arm64:fake_sigreturn_bad_size
11136 06:57:05.882923 arm64:fake_sigreturn_bad_size_for_magic0
11137 06:57:05.886236 arm64:fake_sigreturn_duplicated_fpsimd
11138 06:57:05.889145 arm64:fake_sigreturn_misaligned_sp
11139 06:57:05.892586 arm64:fake_sigreturn_missing_fpsimd
11140 06:57:05.896075 arm64:fake_sigreturn_sme_change_vl
11141 06:57:05.899394 arm64:fake_sigreturn_sve_change_vl
11142 06:57:05.902845 arm64:mangle_pstate_invalid_compat_toggle
11143 06:57:05.905868 arm64:mangle_pstate_invalid_daif_bits
11144 06:57:05.909089 arm64:mangle_pstate_invalid_mode_el1h
11145 06:57:05.912529 arm64:mangle_pstate_invalid_mode_el1t
11146 06:57:05.915597 arm64:mangle_pstate_invalid_mode_el2h
11147 06:57:05.921991 arm64:mangle_pstate_invalid_mode_el2t
11148 06:57:05.925686 arm64:mangle_pstate_invalid_mode_el3h
11149 06:57:05.928863 arm64:mangle_pstate_invalid_mode_el3t
11150 06:57:05.928944 arm64:sme_trap_no_sm
11151 06:57:05.931905 arm64:sme_trap_non_streaming
11152 06:57:05.931975 arm64:sme_trap_za
11153 06:57:05.935171 arm64:sme_vl
11154 06:57:05.935242 arm64:ssve_regs
11155 06:57:05.938546 arm64:sve_regs
11156 06:57:05.938616 arm64:sve_vl
11157 06:57:05.941782 arm64:za_no_regs
11158 06:57:05.941854 arm64:za_regs
11159 06:57:05.941914 arm64:pac
11160 06:57:05.945021 arm64:fp-stress
11161 06:57:05.945091 arm64:sve-ptrace
11162 06:57:05.948395 arm64:sve-probe-vls
11163 06:57:05.948469 arm64:vec-syscfg
11164 06:57:05.951752 arm64:za-fork
11165 06:57:05.951823 arm64:za-ptrace
11166 06:57:05.955064 arm64:check_buffer_fill
11167 06:57:05.955136 arm64:check_child_memory
11168 06:57:05.958796 arm64:check_gcr_el1_cswitch
11169 06:57:05.961787 arm64:check_ksm_options
11170 06:57:05.961870 arm64:check_mmap_options
11171 06:57:05.965297 arm64:check_prctl
11172 06:57:05.968352 arm64:check_tags_inclusion
11173 06:57:05.968435 arm64:check_user_mem
11174 06:57:05.971624 arm64:btitest
11175 06:57:05.971708 arm64:nobtitest
11176 06:57:05.971773 arm64:hwcap
11177 06:57:05.975041 arm64:ptrace
11178 06:57:05.975124 arm64:syscall-abi
11179 06:57:05.978247 arm64:tpidr2
11180 06:57:05.981456 ============== Tests to run ===============
11181 06:57:05.981572 arm64:tags_test
11182 06:57:05.984902 arm64:run_tags_test.sh
11183 06:57:05.987860 arm64:fake_sigreturn_bad_magic
11184 06:57:05.991182 arm64:fake_sigreturn_bad_size
11185 06:57:05.994563 arm64:fake_sigreturn_bad_size_for_magic0
11186 06:57:05.997905 arm64:fake_sigreturn_duplicated_fpsimd
11187 06:57:06.001389 arm64:fake_sigreturn_misaligned_sp
11188 06:57:06.004635 arm64:fake_sigreturn_missing_fpsimd
11189 06:57:06.007657 arm64:fake_sigreturn_sme_change_vl
11190 06:57:06.011084 arm64:fake_sigreturn_sve_change_vl
11191 06:57:06.014491 arm64:mangle_pstate_invalid_compat_toggle
11192 06:57:06.017868 arm64:mangle_pstate_invalid_daif_bits
11193 06:57:06.021048 arm64:mangle_pstate_invalid_mode_el1h
11194 06:57:06.024463 arm64:mangle_pstate_invalid_mode_el1t
11195 06:57:06.027755 arm64:mangle_pstate_invalid_mode_el2h
11196 06:57:06.030852 arm64:mangle_pstate_invalid_mode_el2t
11197 06:57:06.034185 arm64:mangle_pstate_invalid_mode_el3h
11198 06:57:06.037387 arm64:mangle_pstate_invalid_mode_el3t
11199 06:57:06.037516 arm64:sme_trap_no_sm
11200 06:57:06.040821 arm64:sme_trap_non_streaming
11201 06:57:06.044200 arm64:sme_trap_za
11202 06:57:06.044271 arm64:sme_vl
11203 06:57:06.047292 arm64:ssve_regs
11204 06:57:06.047362 arm64:sve_regs
11205 06:57:06.047428 arm64:sve_vl
11206 06:57:06.050507 arm64:za_no_regs
11207 06:57:06.050577 arm64:za_regs
11208 06:57:06.053856 arm64:pac
11209 06:57:06.053930 arm64:fp-stress
11210 06:57:06.053990 arm64:sve-ptrace
11211 06:57:06.057212 arm64:sve-probe-vls
11212 06:57:06.057281 arm64:vec-syscfg
11213 06:57:06.060412 arm64:za-fork
11214 06:57:06.060482 arm64:za-ptrace
11215 06:57:06.064082 arm64:check_buffer_fill
11216 06:57:06.067272 arm64:check_child_memory
11217 06:57:06.067341 arm64:check_gcr_el1_cswitch
11218 06:57:06.070437 arm64:check_ksm_options
11219 06:57:06.073833 arm64:check_mmap_options
11220 06:57:06.073902 arm64:check_prctl
11221 06:57:06.077104 arm64:check_tags_inclusion
11222 06:57:06.080269 arm64:check_user_mem
11223 06:57:06.080339 arm64:btitest
11224 06:57:06.080405 arm64:nobtitest
11225 06:57:06.083492 arm64:hwcap
11226 06:57:06.083568 arm64:ptrace
11227 06:57:06.087255 arm64:syscall-abi
11228 06:57:06.087327 arm64:tpidr2
11229 06:57:06.090524 ===========End Tests to run ===============
11230 06:57:06.093377 shardfile-arm64 pass
11231 06:57:06.389902 <12>[ 37.158152] kselftest: Running tests in arm64
11232 06:57:06.400849 TAP version 13
11233 06:57:06.414844 1..48
11234 06:57:06.434599 # selftests: arm64: tags_test
11235 06:57:06.912985 ok 1 selftests: arm64: tags_test
11236 06:57:06.934268 # selftests: arm64: run_tags_test.sh
11237 06:57:06.993186 # --------------------
11238 06:57:06.996628 # running tags test
11239 06:57:06.997139 # --------------------
11240 06:57:06.999898 # [PASS]
11241 06:57:07.003146 ok 2 selftests: arm64: run_tags_test.sh
11242 06:57:07.019304 # selftests: arm64: fake_sigreturn_bad_magic
11243 06:57:07.090650 # Registered handlers for all signals.
11244 06:57:07.090749 # Detected MINSTKSIGSZ:4720
11245 06:57:07.093913 # Testcase initialized.
11246 06:57:07.097056 # uc context validated.
11247 06:57:07.100344 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11248 06:57:07.103780 # Handled SIG_COPYCTX
11249 06:57:07.103853 # Available space:3568
11250 06:57:07.110407 # Using badly built context - ERR: BAD MAGIC !
11251 06:57:07.116708 # SIG_OK -- SP:0xFFFFDC74FC40 si_addr@:0xffffdc74fc40 si_code:2 token@:0xffffdc74e9e0 offset:-4704
11252 06:57:07.119870 # ==>> completed. PASS(1)
11253 06:57:07.126585 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11254 06:57:07.133391 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDC74E9E0
11255 06:57:07.139898 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11256 06:57:07.143231 # selftests: arm64: fake_sigreturn_bad_size
11257 06:57:07.175454 # Registered handlers for all signals.
11258 06:57:07.175706 # Detected MINSTKSIGSZ:4720
11259 06:57:07.179026 # Testcase initialized.
11260 06:57:07.182166 # uc context validated.
11261 06:57:07.185625 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11262 06:57:07.188755 # Handled SIG_COPYCTX
11263 06:57:07.189173 # Available space:3568
11264 06:57:07.192172 # uc context validated.
11265 06:57:07.199210 # Using badly built context - ERR: Bad size for esr_context
11266 06:57:07.205777 # SIG_OK -- SP:0xFFFFE9FFCEE0 si_addr@:0xffffe9ffcee0 si_code:2 token@:0xffffe9ffbc80 offset:-4704
11267 06:57:07.209051 # ==>> completed. PASS(1)
11268 06:57:07.215271 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11269 06:57:07.222086 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE9FFBC80
11270 06:57:07.225344 ok 4 selftests: arm64: fake_sigreturn_bad_size
11271 06:57:07.231868 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11272 06:57:07.291788 # Registered handlers for all signals.
11273 06:57:07.292233 # Detected MINSTKSIGSZ:4720
11274 06:57:07.294791 # Testcase initialized.
11275 06:57:07.297941 # uc context validated.
11276 06:57:07.301587 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11277 06:57:07.304859 # Handled SIG_COPYCTX
11278 06:57:07.305291 # Available space:3568
11279 06:57:07.311241 # Using badly built context - ERR: Bad size for terminator
11280 06:57:07.321076 # SIG_OK -- SP:0xFFFFE2749020 si_addr@:0xffffe2749020 si_code:2 token@:0xffffe2747dc0 offset:-4704
11281 06:57:07.321640 # ==>> completed. PASS(1)
11282 06:57:07.331040 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11283 06:57:07.337780 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE2747DC0
11284 06:57:07.341346 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11285 06:57:07.347369 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11286 06:57:07.391395 # Registered handlers for all signals.
11287 06:57:07.391863 # Detected MINSTKSIGSZ:4720
11288 06:57:07.394914 # Testcase initialized.
11289 06:57:07.398092 # uc context validated.
11290 06:57:07.401468 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11291 06:57:07.404676 # Handled SIG_COPYCTX
11292 06:57:07.405171 # Available space:3568
11293 06:57:07.411380 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11294 06:57:07.421193 # SIG_OK -- SP:0xFFFFDF1C02E0 si_addr@:0xffffdf1c02e0 si_code:2 token@:0xffffdf1bf080 offset:-4704
11295 06:57:07.421743 # ==>> completed. PASS(1)
11296 06:57:07.431024 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11297 06:57:07.437835 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDF1BF080
11298 06:57:07.441172 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11299 06:57:07.444247 # selftests: arm64: fake_sigreturn_misaligned_sp
11300 06:57:07.486857 # Registered handlers for all signals.
11301 06:57:07.487366 # Detected MINSTKSIGSZ:4720
11302 06:57:07.489800 # Testcase initialized.
11303 06:57:07.493168 # uc context validated.
11304 06:57:07.496354 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11305 06:57:07.499546 # Handled SIG_COPYCTX
11306 06:57:07.506472 # SIG_OK -- SP:0xFFFFE8D84DD3 si_addr@:0xffffe8d84dd3 si_code:2 token@:0xffffe8d84dd3 offset:0
11307 06:57:07.509770 # ==>> completed. PASS(1)
11308 06:57:07.516226 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11309 06:57:07.522888 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE8D84DD3
11310 06:57:07.529770 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11311 06:57:07.532490 # selftests: arm64: fake_sigreturn_missing_fpsimd
11312 06:57:07.595409 # Registered handlers for all signals.
11313 06:57:07.595846 # Detected MINSTKSIGSZ:4720
11314 06:57:07.598620 # Testcase initialized.
11315 06:57:07.601849 # uc context validated.
11316 06:57:07.605193 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11317 06:57:07.608421 # Handled SIG_COPYCTX
11318 06:57:07.611982 # Mangling template header. Spare space:4096
11319 06:57:07.615190 # Using badly built context - ERR: Missing FPSIMD
11320 06:57:07.624817 # SIG_OK -- SP:0xFFFFFD2266D0 si_addr@:0xfffffd2266d0 si_code:2 token@:0xfffffd225470 offset:-4704
11321 06:57:07.628218 # ==>> completed. PASS(1)
11322 06:57:07.634735 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11323 06:57:07.641376 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFD225470
11324 06:57:07.644722 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11325 06:57:07.651229 # selftests: arm64: fake_sigreturn_sme_change_vl
11326 06:57:07.687367 # Registered handlers for all signals.
11327 06:57:07.687999 # Detected MINSTKSIGSZ:4720
11328 06:57:07.690665 # ==>> completed. SKIP.
11329 06:57:07.697292 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11330 06:57:07.699995 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11331 06:57:07.710565 # selftests: arm64: fake_sigreturn_sve_change_vl
11332 06:57:07.780670 # Registered handlers for all signals.
11333 06:57:07.780856 # Detected MINSTKSIGSZ:4720
11334 06:57:07.784293 # ==>> completed. SKIP.
11335 06:57:07.790719 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11336 06:57:07.793846 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11337 06:57:07.803822 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11338 06:57:07.865373 # Registered handlers for all signals.
11339 06:57:07.865894 # Detected MINSTKSIGSZ:4720
11340 06:57:07.868959 # Testcase initialized.
11341 06:57:07.872139 # uc context validated.
11342 06:57:07.872701 # Handled SIG_TRIG
11343 06:57:07.882177 # SIG_OK -- SP:0xFFFFCD0092F0 si_addr@:0xffffcd0092f0 si_code:2 token@:(nil) offset:-281474121110256
11344 06:57:07.885169 # ==>> completed. PASS(1)
11345 06:57:07.891919 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11346 06:57:07.898618 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11347 06:57:07.901946 # selftests: arm64: mangle_pstate_invalid_daif_bits
11348 06:57:07.962769 # Registered handlers for all signals.
11349 06:57:07.963218 # Detected MINSTKSIGSZ:4720
11350 06:57:07.966181 # Testcase initialized.
11351 06:57:07.969534 # uc context validated.
11352 06:57:07.969967 # Handled SIG_TRIG
11353 06:57:07.979237 # SIG_OK -- SP:0xFFFFC1472920 si_addr@:0xffffc1472920 si_code:2 token@:(nil) offset:-281473924409632
11354 06:57:07.982865 # ==>> completed. PASS(1)
11355 06:57:07.989347 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11356 06:57:07.992456 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11357 06:57:07.999067 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11358 06:57:08.043121 # Registered handlers for all signals.
11359 06:57:08.043583 # Detected MINSTKSIGSZ:4720
11360 06:57:08.046739 # Testcase initialized.
11361 06:57:08.050115 # uc context validated.
11362 06:57:08.050529 # Handled SIG_TRIG
11363 06:57:08.059758 # SIG_OK -- SP:0xFFFFCF980AC0 si_addr@:0xffffcf980ac0 si_code:2 token@:(nil) offset:-281474164591296
11364 06:57:08.063426 # ==>> completed. PASS(1)
11365 06:57:08.069849 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11366 06:57:08.073201 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11367 06:57:08.079539 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11368 06:57:08.118310 # Registered handlers for all signals.
11369 06:57:08.118752 # Detected MINSTKSIGSZ:4720
11370 06:57:08.121667 # Testcase initialized.
11371 06:57:08.124772 # uc context validated.
11372 06:57:08.125296 # Handled SIG_TRIG
11373 06:57:08.134884 # SIG_OK -- SP:0xFFFFF527A6C0 si_addr@:0xfffff527a6c0 si_code:2 token@:(nil) offset:-281474794759872
11374 06:57:08.137818 # ==>> completed. PASS(1)
11375 06:57:08.144419 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11376 06:57:08.147799 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11377 06:57:08.154464 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11378 06:57:08.207957 # Registered handlers for all signals.
11379 06:57:08.208387 # Detected MINSTKSIGSZ:4720
11380 06:57:08.211317 # Testcase initialized.
11381 06:57:08.214776 # uc context validated.
11382 06:57:08.215203 # Handled SIG_TRIG
11383 06:57:08.224548 # SIG_OK -- SP:0xFFFFC53D2B00 si_addr@:0xffffc53d2b00 si_code:2 token@:(nil) offset:-281473990863616
11384 06:57:08.227894 # ==>> completed. PASS(1)
11385 06:57:08.234309 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11386 06:57:08.237607 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11387 06:57:08.244096 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11388 06:57:08.305335 # Registered handlers for all signals.
11389 06:57:08.305903 # Detected MINSTKSIGSZ:4720
11390 06:57:08.308829 # Testcase initialized.
11391 06:57:08.312278 # uc context validated.
11392 06:57:08.312704 # Handled SIG_TRIG
11393 06:57:08.322524 # SIG_OK -- SP:0xFFFFC0F99B60 si_addr@:0xffffc0f99b60 si_code:2 token@:(nil) offset:-281473919327072
11394 06:57:08.325260 # ==>> completed. PASS(1)
11395 06:57:08.331979 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11396 06:57:08.335239 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11397 06:57:08.341629 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11398 06:57:08.391682 # Registered handlers for all signals.
11399 06:57:08.392197 # Detected MINSTKSIGSZ:4720
11400 06:57:08.394969 # Testcase initialized.
11401 06:57:08.398365 # uc context validated.
11402 06:57:08.398790 # Handled SIG_TRIG
11403 06:57:08.407901 # SIG_OK -- SP:0xFFFFEAA5F880 si_addr@:0xffffeaa5f880 si_code:2 token@:(nil) offset:-281474618488960
11404 06:57:08.411418 # ==>> completed. PASS(1)
11405 06:57:08.417742 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11406 06:57:08.421090 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11407 06:57:08.427678 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11408 06:57:08.491829 # Registered handlers for all signals.
11409 06:57:08.492313 # Detected MINSTKSIGSZ:4720
11410 06:57:08.495062 # Testcase initialized.
11411 06:57:08.498674 # uc context validated.
11412 06:57:08.499144 # Handled SIG_TRIG
11413 06:57:08.508238 # SIG_OK -- SP:0xFFFFC3723420 si_addr@:0xffffc3723420 si_code:2 token@:(nil) offset:-281473960784928
11414 06:57:08.511449 # ==>> completed. PASS(1)
11415 06:57:08.518139 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11416 06:57:08.521526 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11417 06:57:08.524816 # selftests: arm64: sme_trap_no_sm
11418 06:57:08.590737 # Registered handlers for all signals.
11419 06:57:08.591215 # Detected MINSTKSIGSZ:4720
11420 06:57:08.593876 # ==>> completed. SKIP.
11421 06:57:08.603521 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11422 06:57:08.606997 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11423 06:57:08.614641 # selftests: arm64: sme_trap_non_streaming
11424 06:57:08.684888 # Registered handlers for all signals.
11425 06:57:08.685351 # Detected MINSTKSIGSZ:4720
11426 06:57:08.688194 # ==>> completed. SKIP.
11427 06:57:08.698104 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11428 06:57:08.705127 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11429 06:57:08.707966 # selftests: arm64: sme_trap_za
11430 06:57:08.776652 # Registered handlers for all signals.
11431 06:57:08.777111 # Detected MINSTKSIGSZ:4720
11432 06:57:08.780049 # Testcase initialized.
11433 06:57:08.789806 # SIG_OK -- SP:0xFFFFD3AB8980 si_addr@:0xaaaaca6d2510 si_code:1 token@:(nil) offset:-187650517312784
11434 06:57:08.790324 # ==>> completed. PASS(1)
11435 06:57:08.799861 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11436 06:57:08.800347 ok 21 selftests: arm64: sme_trap_za
11437 06:57:08.802985 # selftests: arm64: sme_vl
11438 06:57:08.855697 # Registered handlers for all signals.
11439 06:57:08.855902 # Detected MINSTKSIGSZ:4720
11440 06:57:08.859068 # ==>> completed. SKIP.
11441 06:57:08.865676 # # SME VL :: Check that we get the right SME VL reported
11442 06:57:08.869144 ok 22 selftests: arm64: sme_vl # SKIP
11443 06:57:08.876242 # selftests: arm64: ssve_regs
11444 06:57:08.930807 # Registered handlers for all signals.
11445 06:57:08.931251 # Detected MINSTKSIGSZ:4720
11446 06:57:08.933831 # ==>> completed. SKIP.
11447 06:57:08.940473 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11448 06:57:08.947223 ok 23 selftests: arm64: ssve_regs # SKIP
11449 06:57:08.950511 # selftests: arm64: sve_regs
11450 06:57:09.027832 # Registered handlers for all signals.
11451 06:57:09.028410 # Detected MINSTKSIGSZ:4720
11452 06:57:09.031283 # ==>> completed. SKIP.
11453 06:57:09.037718 # # SVE registers :: Check that we get the right SVE registers reported
11454 06:57:09.040904 ok 24 selftests: arm64: sve_regs # SKIP
11455 06:57:09.048068 # selftests: arm64: sve_vl
11456 06:57:09.123269 # Registered handlers for all signals.
11457 06:57:09.123762 # Detected MINSTKSIGSZ:4720
11458 06:57:09.126534 # ==>> completed. SKIP.
11459 06:57:09.133085 # # SVE VL :: Check that we get the right SVE VL reported
11460 06:57:09.136497 ok 25 selftests: arm64: sve_vl # SKIP
11461 06:57:09.143763 # selftests: arm64: za_no_regs
11462 06:57:09.225169 # Registered handlers for all signals.
11463 06:57:09.225664 # Detected MINSTKSIGSZ:4720
11464 06:57:09.228649 # ==>> completed. SKIP.
11465 06:57:09.235156 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11466 06:57:09.238368 ok 26 selftests: arm64: za_no_regs # SKIP
11467 06:57:09.251041 # selftests: arm64: za_regs
11468 06:57:09.313242 # Registered handlers for all signals.
11469 06:57:09.313750 # Detected MINSTKSIGSZ:4720
11470 06:57:09.316838 # ==>> completed. SKIP.
11471 06:57:09.323193 # # ZA register :: Check that we get the right ZA registers reported
11472 06:57:09.326341 ok 27 selftests: arm64: za_regs # SKIP
11473 06:57:09.332664 # selftests: arm64: pac
11474 06:57:09.398167 # TAP version 13
11475 06:57:09.398618 # 1..7
11476 06:57:09.401418 # # Starting 7 tests from 1 test cases.
11477 06:57:09.404757 # # RUN global.corrupt_pac ...
11478 06:57:09.407891 # # SKIP PAUTH not enabled
11479 06:57:09.411309 # # OK global.corrupt_pac
11480 06:57:09.414475 # ok 1 # SKIP PAUTH not enabled
11481 06:57:09.421255 # # RUN global.pac_instructions_not_nop ...
11482 06:57:09.424674 # # SKIP PAUTH not enabled
11483 06:57:09.427690 # # OK global.pac_instructions_not_nop
11484 06:57:09.430986 # ok 2 # SKIP PAUTH not enabled
11485 06:57:09.437433 # # RUN global.pac_instructions_not_nop_generic ...
11486 06:57:09.440666 # # SKIP Generic PAUTH not enabled
11487 06:57:09.444159 # # OK global.pac_instructions_not_nop_generic
11488 06:57:09.450635 # ok 3 # SKIP Generic PAUTH not enabled
11489 06:57:09.453907 # # RUN global.single_thread_different_keys ...
11490 06:57:09.457419 # # SKIP PAUTH not enabled
11491 06:57:09.463835 # # OK global.single_thread_different_keys
11492 06:57:09.464300 # ok 4 # SKIP PAUTH not enabled
11493 06:57:09.470675 # # RUN global.exec_changed_keys ...
11494 06:57:09.473869 # # SKIP PAUTH not enabled
11495 06:57:09.477092 # # OK global.exec_changed_keys
11496 06:57:09.480448 # ok 5 # SKIP PAUTH not enabled
11497 06:57:09.484028 # # RUN global.context_switch_keep_keys ...
11498 06:57:09.487006 # # SKIP PAUTH not enabled
11499 06:57:09.493617 # # OK global.context_switch_keep_keys
11500 06:57:09.497006 # ok 6 # SKIP PAUTH not enabled
11501 06:57:09.500214 # # RUN global.context_switch_keep_keys_generic ...
11502 06:57:09.503521 # # SKIP Generic PAUTH not enabled
11503 06:57:09.510108 # # OK global.context_switch_keep_keys_generic
11504 06:57:09.513241 # ok 7 # SKIP Generic PAUTH not enabled
11505 06:57:09.516735 # # PASSED: 7 / 7 tests passed.
11506 06:57:09.520089 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11507 06:57:09.523390 ok 28 selftests: arm64: pac
11508 06:57:09.526626 # selftests: arm64: fp-stress
11509 06:57:15.040381 <6>[ 45.812901] vpu: disabling
11510 06:57:15.043810 <6>[ 45.815949] vproc2: disabling
11511 06:57:15.046982 <6>[ 45.819221] vproc1: disabling
11512 06:57:15.050359 <6>[ 45.822492] vaud18: disabling
11513 06:57:15.056763 <6>[ 45.825909] vsram_others: disabling
11514 06:57:15.060233 <6>[ 45.829793] va09: disabling
11515 06:57:15.063509 <6>[ 45.832906] vsram_md: disabling
11516 06:57:15.066947 <6>[ 45.836397] Vgpu: disabling
11517 06:57:19.455641 # TAP version 13
11518 06:57:19.455779 # 1..16
11519 06:57:19.459003 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11520 06:57:19.462482 # # Will run for 10s
11521 06:57:19.462565 # # Started FPSIMD-0-0
11522 06:57:19.465509 # # Started FPSIMD-0-1
11523 06:57:19.468903 # # Started FPSIMD-1-0
11524 06:57:19.468986 # # Started FPSIMD-1-1
11525 06:57:19.472286 # # Started FPSIMD-2-0
11526 06:57:19.472369 # # Started FPSIMD-2-1
11527 06:57:19.475460 # # Started FPSIMD-3-0
11528 06:57:19.478815 # # Started FPSIMD-3-1
11529 06:57:19.478898 # # Started FPSIMD-4-0
11530 06:57:19.482244 # # Started FPSIMD-4-1
11531 06:57:19.485238 # # Started FPSIMD-5-0
11532 06:57:19.485346 # # Started FPSIMD-5-1
11533 06:57:19.488767 # # Started FPSIMD-6-0
11534 06:57:19.492224 # # Started FPSIMD-6-1
11535 06:57:19.492333 # # Started FPSIMD-7-0
11536 06:57:19.495419 # # Started FPSIMD-7-1
11537 06:57:19.498727 # # FPSIMD-0-0: Vector length: 128 bits
11538 06:57:19.501861 # # FPSIMD-0-0: PID: 1159
11539 06:57:19.505190 # # FPSIMD-0-1: Vector length: 128 bits
11540 06:57:19.505269 # # FPSIMD-0-1: PID: 1160
11541 06:57:19.508535 # # FPSIMD-1-1: Vector length: 128 bits
11542 06:57:19.511721 # # FPSIMD-1-1: PID: 1162
11543 06:57:19.515121 # # FPSIMD-2-1: Vector length: 128 bits
11544 06:57:19.518663 # # FPSIMD-2-1: PID: 1164
11545 06:57:19.521630 # # FPSIMD-4-0: Vector length: 128 bits
11546 06:57:19.524990 # # FPSIMD-4-0: PID: 1167
11547 06:57:19.528355 # # FPSIMD-1-0: Vector length: 128 bits
11548 06:57:19.528433 # # FPSIMD-1-0: PID: 1161
11549 06:57:19.535137 # # FPSIMD-2-0: Vector length: 128 bits
11550 06:57:19.535222 # # FPSIMD-2-0: PID: 1163
11551 06:57:19.538264 # # FPSIMD-3-0: Vector length: 128 bits
11552 06:57:19.541439 # # FPSIMD-3-0: PID: 1165
11553 06:57:19.544908 # # FPSIMD-6-0: Vector length: 128 bits
11554 06:57:19.548282 # # FPSIMD-6-0: PID: 1171
11555 06:57:19.551234 # # FPSIMD-3-1: Vector length: 128 bits
11556 06:57:19.554627 # # FPSIMD-3-1: PID: 1166
11557 06:57:19.558147 # # FPSIMD-6-1: Vector length: 128 bits
11558 06:57:19.558221 # # FPSIMD-6-1: PID: 1172
11559 06:57:19.561667 # # FPSIMD-4-1: Vector length: 128 bits
11560 06:57:19.564516 # # FPSIMD-4-1: PID: 1168
11561 06:57:19.567803 # # FPSIMD-5-1: Vector length: 128 bits
11562 06:57:19.571334 # # FPSIMD-5-1: PID: 1170
11563 06:57:19.574679 # # FPSIMD-7-1: Vector length: 128 bits
11564 06:57:19.577825 # # FPSIMD-7-1: PID: 1174
11565 06:57:19.581257 # # FPSIMD-5-0: Vector length: 128 bits
11566 06:57:19.584482 # # FPSIMD-5-0: PID: 1169
11567 06:57:19.587730 # # FPSIMD-7-0: Vector length: 128 bits
11568 06:57:19.587816 # # FPSIMD-7-0: PID: 1173
11569 06:57:19.591075 # # Finishing up...
11570 06:57:19.597953 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=984309, signals=10
11571 06:57:19.604370 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1720132, signals=10
11572 06:57:19.611178 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1106202, signals=10
11573 06:57:19.621126 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=978549, signals=10
11574 06:57:19.627407 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1039284, signals=10
11575 06:57:19.634297 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1389870, signals=10
11576 06:57:19.641025 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=2068686, signals=10
11577 06:57:19.644318 # ok 1 FPSIMD-0-0
11578 06:57:19.644720 # ok 2 FPSIMD-0-1
11579 06:57:19.647680 # ok 3 FPSIMD-1-0
11580 06:57:19.648056 # ok 4 FPSIMD-1-1
11581 06:57:19.651011 # ok 5 FPSIMD-2-0
11582 06:57:19.651421 # ok 6 FPSIMD-2-1
11583 06:57:19.654050 # ok 7 FPSIMD-3-0
11584 06:57:19.654505 # ok 8 FPSIMD-3-1
11585 06:57:19.657578 # ok 9 FPSIMD-4-0
11586 06:57:19.658033 # ok 10 FPSIMD-4-1
11587 06:57:19.660820 # ok 11 FPSIMD-5-0
11588 06:57:19.661277 # ok 12 FPSIMD-5-1
11589 06:57:19.664362 # ok 13 FPSIMD-6-0
11590 06:57:19.664834 # ok 14 FPSIMD-6-1
11591 06:57:19.667422 # ok 15 FPSIMD-7-0
11592 06:57:19.667843 # ok 16 FPSIMD-7-1
11593 06:57:19.674055 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1145910, signals=9
11594 06:57:19.684154 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1343073, signals=10
11595 06:57:19.690879 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1075793, signals=10
11596 06:57:19.697148 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1686988, signals=9
11597 06:57:19.703938 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=993890, signals=10
11598 06:57:19.710581 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1347260, signals=9
11599 06:57:19.717182 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1127192, signals=10
11600 06:57:19.727111 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=981345, signals=10
11601 06:57:19.733719 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1265891, signals=10
11602 06:57:19.737560 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11603 06:57:19.740079 ok 29 selftests: arm64: fp-stress
11604 06:57:19.743324 # selftests: arm64: sve-ptrace
11605 06:57:19.746332 # TAP version 13
11606 06:57:19.746421 # 1..4104
11607 06:57:19.749582 # ok 2 # SKIP SVE not available
11608 06:57:19.753002 # # Planned tests != run tests (4104 != 1)
11609 06:57:19.756227 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11610 06:57:19.762852 ok 30 selftests: arm64: sve-ptrace # SKIP
11611 06:57:19.762942 # selftests: arm64: sve-probe-vls
11612 06:57:19.766394 # TAP version 13
11613 06:57:19.766483 # 1..2
11614 06:57:19.769381 # ok 2 # SKIP SVE not available
11615 06:57:19.772804 # # Planned tests != run tests (2 != 1)
11616 06:57:19.779400 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11617 06:57:19.782932 ok 31 selftests: arm64: sve-probe-vls # SKIP
11618 06:57:19.785927 # selftests: arm64: vec-syscfg
11619 06:57:19.786054 # TAP version 13
11620 06:57:19.786196 # 1..20
11621 06:57:19.789192 # ok 1 # SKIP SVE not supported
11622 06:57:19.792522 # ok 2 # SKIP SVE not supported
11623 06:57:19.795882 # ok 3 # SKIP SVE not supported
11624 06:57:19.799330 # ok 4 # SKIP SVE not supported
11625 06:57:19.802409 # ok 5 # SKIP SVE not supported
11626 06:57:19.806074 # ok 6 # SKIP SVE not supported
11627 06:57:19.806336 # ok 7 # SKIP SVE not supported
11628 06:57:19.809214 # ok 8 # SKIP SVE not supported
11629 06:57:19.812583 # ok 9 # SKIP SVE not supported
11630 06:57:19.815802 # ok 10 # SKIP SVE not supported
11631 06:57:19.819131 # ok 11 # SKIP SME not supported
11632 06:57:19.822811 # ok 12 # SKIP SME not supported
11633 06:57:19.825730 # ok 13 # SKIP SME not supported
11634 06:57:19.828921 # ok 14 # SKIP SME not supported
11635 06:57:19.832579 # ok 15 # SKIP SME not supported
11636 06:57:19.833046 # ok 16 # SKIP SME not supported
11637 06:57:19.835775 # ok 17 # SKIP SME not supported
11638 06:57:19.838916 # ok 18 # SKIP SME not supported
11639 06:57:19.842076 # ok 19 # SKIP SME not supported
11640 06:57:19.845562 # ok 20 # SKIP SME not supported
11641 06:57:19.852316 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11642 06:57:19.855764 ok 32 selftests: arm64: vec-syscfg
11643 06:57:19.856220 # selftests: arm64: za-fork
11644 06:57:19.858706 # TAP version 13
11645 06:57:19.859161 # 1..1
11646 06:57:19.859609 # # PID: 1249
11647 06:57:19.862957 # # SME support not present
11648 06:57:19.865305 # ok 0 skipped
11649 06:57:19.868702 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11650 06:57:19.871778 ok 33 selftests: arm64: za-fork
11651 06:57:19.875216 # selftests: arm64: za-ptrace
11652 06:57:19.885398 # TAP version 13
11653 06:57:19.885884 # 1..1
11654 06:57:19.889039 # ok 2 # SKIP SME not available
11655 06:57:19.895229 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11656 06:57:19.898533 ok 34 selftests: arm64: za-ptrace # SKIP
11657 06:57:19.913070 # selftests: arm64: check_buffer_fill
11658 06:57:19.974398 # # SKIP: MTE features unavailable
11659 06:57:19.981547 ok 35 selftests: arm64: check_buffer_fill # SKIP
11660 06:57:19.999820 # selftests: arm64: check_child_memory
11661 06:57:20.056701 # # SKIP: MTE features unavailable
11662 06:57:20.064409 ok 36 selftests: arm64: check_child_memory # SKIP
11663 06:57:20.082925 # selftests: arm64: check_gcr_el1_cswitch
11664 06:57:20.146243 # # SKIP: MTE features unavailable
11665 06:57:20.153825 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11666 06:57:20.174930 # selftests: arm64: check_ksm_options
11667 06:57:20.238213 # # SKIP: MTE features unavailable
11668 06:57:20.245620 ok 38 selftests: arm64: check_ksm_options # SKIP
11669 06:57:20.264434 # selftests: arm64: check_mmap_options
11670 06:57:20.336579 # # SKIP: MTE features unavailable
11671 06:57:20.344064 ok 39 selftests: arm64: check_mmap_options # SKIP
11672 06:57:20.358408 # selftests: arm64: check_prctl
11673 06:57:20.426589 # TAP version 13
11674 06:57:20.427035 # 1..5
11675 06:57:20.430090 # ok 1 check_basic_read
11676 06:57:20.430555 # ok 2 NONE
11677 06:57:20.433080 # ok 3 # SKIP SYNC
11678 06:57:20.433561 # ok 4 # SKIP ASYNC
11679 06:57:20.436325 # ok 5 # SKIP SYNC+ASYNC
11680 06:57:20.439646 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11681 06:57:20.443095 ok 40 selftests: arm64: check_prctl
11682 06:57:20.452964 # selftests: arm64: check_tags_inclusion
11683 06:57:20.522082 # # SKIP: MTE features unavailable
11684 06:57:20.530679 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11685 06:57:20.547567 # selftests: arm64: check_user_mem
11686 06:57:20.635180 # # SKIP: MTE features unavailable
11687 06:57:20.643332 ok 42 selftests: arm64: check_user_mem # SKIP
11688 06:57:20.657464 # selftests: arm64: btitest
11689 06:57:20.718182 # TAP version 13
11690 06:57:20.718676 # 1..18
11691 06:57:20.721446 # # HWCAP_PACA not present
11692 06:57:20.724940 # # HWCAP2_BTI not present
11693 06:57:20.725378 # # Test binary built for BTI
11694 06:57:20.731290 # ok 1 nohint_func/call_using_br_x0 # SKIP
11695 06:57:20.734943 # ok 1 nohint_func/call_using_br_x16 # SKIP
11696 06:57:20.738041 # ok 1 nohint_func/call_using_blr # SKIP
11697 06:57:20.741248 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11698 06:57:20.744411 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11699 06:57:20.751470 # ok 1 bti_none_func/call_using_blr # SKIP
11700 06:57:20.754392 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11701 06:57:20.757593 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11702 06:57:20.761189 # ok 1 bti_c_func/call_using_blr # SKIP
11703 06:57:20.764305 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11704 06:57:20.767617 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11705 06:57:20.771157 # ok 1 bti_j_func/call_using_blr # SKIP
11706 06:57:20.774369 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11707 06:57:20.780727 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11708 06:57:20.784202 # ok 1 bti_jc_func/call_using_blr # SKIP
11709 06:57:20.787687 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11710 06:57:20.790988 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11711 06:57:20.794184 # ok 1 paciasp_func/call_using_blr # SKIP
11712 06:57:20.800642 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11713 06:57:20.804206 # # WARNING - EXPECTED TEST COUNT WRONG
11714 06:57:20.807438 ok 43 selftests: arm64: btitest
11715 06:57:20.810596 # selftests: arm64: nobtitest
11716 06:57:20.811054 # TAP version 13
11717 06:57:20.811421 # 1..18
11718 06:57:20.813798 # # HWCAP_PACA not present
11719 06:57:20.817267 # # HWCAP2_BTI not present
11720 06:57:20.820567 # # Test binary not built for BTI
11721 06:57:20.823738 # ok 1 nohint_func/call_using_br_x0 # SKIP
11722 06:57:20.826959 # ok 1 nohint_func/call_using_br_x16 # SKIP
11723 06:57:20.830493 # ok 1 nohint_func/call_using_blr # SKIP
11724 06:57:20.833758 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11725 06:57:20.840102 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11726 06:57:20.843534 # ok 1 bti_none_func/call_using_blr # SKIP
11727 06:57:20.846703 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11728 06:57:20.850033 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11729 06:57:20.853304 # ok 1 bti_c_func/call_using_blr # SKIP
11730 06:57:20.856830 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11731 06:57:20.859898 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11732 06:57:20.863195 # ok 1 bti_j_func/call_using_blr # SKIP
11733 06:57:20.869981 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11734 06:57:20.873195 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11735 06:57:20.876802 # ok 1 bti_jc_func/call_using_blr # SKIP
11736 06:57:20.880057 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11737 06:57:20.883682 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11738 06:57:20.886493 # ok 1 paciasp_func/call_using_blr # SKIP
11739 06:57:20.893171 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11740 06:57:20.896604 # # WARNING - EXPECTED TEST COUNT WRONG
11741 06:57:20.899924 ok 44 selftests: arm64: nobtitest
11742 06:57:20.902945 # selftests: arm64: hwcap
11743 06:57:20.903372 # TAP version 13
11744 06:57:20.903712 # 1..28
11745 06:57:20.906709 # ok 1 cpuinfo_match_RNG
11746 06:57:20.909405 # # SIGILL reported for RNG
11747 06:57:20.909878 # ok 2 # SKIP sigill_RNG
11748 06:57:20.913161 # ok 3 cpuinfo_match_SME
11749 06:57:20.916202 # ok 4 sigill_SME
11750 06:57:20.916765 # ok 5 cpuinfo_match_SVE
11751 06:57:20.919563 # ok 6 sigill_SVE
11752 06:57:20.922685 # ok 7 cpuinfo_match_SVE 2
11753 06:57:20.923130 # # SIGILL reported for SVE 2
11754 06:57:20.926103 # ok 8 # SKIP sigill_SVE 2
11755 06:57:20.929403 # ok 9 cpuinfo_match_SVE AES
11756 06:57:20.932931 # # SIGILL reported for SVE AES
11757 06:57:20.935884 # ok 10 # SKIP sigill_SVE AES
11758 06:57:20.936368 # ok 11 cpuinfo_match_SVE2 PMULL
11759 06:57:20.939153 # # SIGILL reported for SVE2 PMULL
11760 06:57:20.942539 # ok 12 # SKIP sigill_SVE2 PMULL
11761 06:57:20.946012 # ok 13 cpuinfo_match_SVE2 BITPERM
11762 06:57:20.949399 # # SIGILL reported for SVE2 BITPERM
11763 06:57:20.952426 # ok 14 # SKIP sigill_SVE2 BITPERM
11764 06:57:20.956051 # ok 15 cpuinfo_match_SVE2 SHA3
11765 06:57:20.959107 # # SIGILL reported for SVE2 SHA3
11766 06:57:20.962542 # ok 16 # SKIP sigill_SVE2 SHA3
11767 06:57:20.965935 # ok 17 cpuinfo_match_SVE2 SM4
11768 06:57:20.968865 # # SIGILL reported for SVE2 SM4
11769 06:57:20.969295 # ok 18 # SKIP sigill_SVE2 SM4
11770 06:57:20.972297 # ok 19 cpuinfo_match_SVE2 I8MM
11771 06:57:20.975541 # # SIGILL reported for SVE2 I8MM
11772 06:57:20.978952 # ok 20 # SKIP sigill_SVE2 I8MM
11773 06:57:20.982369 # ok 21 cpuinfo_match_SVE2 F32MM
11774 06:57:20.985463 # # SIGILL reported for SVE2 F32MM
11775 06:57:20.988901 # ok 22 # SKIP sigill_SVE2 F32MM
11776 06:57:20.992121 # ok 23 cpuinfo_match_SVE2 F64MM
11777 06:57:20.995710 # # SIGILL reported for SVE2 F64MM
11778 06:57:20.998753 # ok 24 # SKIP sigill_SVE2 F64MM
11779 06:57:20.999186 # ok 25 cpuinfo_match_SVE2 BF16
11780 06:57:21.002196 # # SIGILL reported for SVE2 BF16
11781 06:57:21.005344 # ok 26 # SKIP sigill_SVE2 BF16
11782 06:57:21.008668 # ok 27 cpuinfo_match_SVE2 EBF16
11783 06:57:21.011761 # ok 28 # SKIP sigill_SVE2 EBF16
11784 06:57:21.018490 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11785 06:57:21.018920 ok 45 selftests: arm64: hwcap
11786 06:57:21.021818 # selftests: arm64: ptrace
11787 06:57:21.025042 # TAP version 13
11788 06:57:21.025470 # 1..7
11789 06:57:21.028322 # # Parent is 1491, child is 1492
11790 06:57:21.028817 # ok 1 read_tpidr_one
11791 06:57:21.031569 # ok 2 write_tpidr_one
11792 06:57:21.034991 # ok 3 verify_tpidr_one
11793 06:57:21.035449 # ok 4 count_tpidrs
11794 06:57:21.038238 # ok 5 tpidr2_write
11795 06:57:21.038697 # ok 6 tpidr2_read
11796 06:57:21.041690 # ok 7 write_tpidr_only
11797 06:57:21.044995 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11798 06:57:21.048209 ok 46 selftests: arm64: ptrace
11799 06:57:21.051812 # selftests: arm64: syscall-abi
11800 06:57:21.079751 # TAP version 13
11801 06:57:21.080215 # 1..2
11802 06:57:21.082991 # ok 1 getpid() FPSIMD
11803 06:57:21.086379 # ok 2 sched_yield() FPSIMD
11804 06:57:21.089763 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11805 06:57:21.092574 ok 47 selftests: arm64: syscall-abi
11806 06:57:21.102693 # selftests: arm64: tpidr2
11807 06:57:21.161321 # TAP version 13
11808 06:57:21.161840 # 1..5
11809 06:57:21.164622 # # PID: 1528
11810 06:57:21.165071 # # SME support not present
11811 06:57:21.168300 # ok 0 skipped, TPIDR2 not supported
11812 06:57:21.171445 # ok 1 skipped, TPIDR2 not supported
11813 06:57:21.174805 # ok 2 skipped, TPIDR2 not supported
11814 06:57:21.178145 # ok 3 skipped, TPIDR2 not supported
11815 06:57:21.181135 # ok 4 skipped, TPIDR2 not supported
11816 06:57:21.187914 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11817 06:57:21.191031 ok 48 selftests: arm64: tpidr2
11818 06:57:21.853801 arm64_tags_test pass
11819 06:57:21.856747 arm64_run_tags_test_sh pass
11820 06:57:21.860282 arm64_fake_sigreturn_bad_magic pass
11821 06:57:21.863555 arm64_fake_sigreturn_bad_size pass
11822 06:57:21.866784 arm64_fake_sigreturn_bad_size_for_magic0 pass
11823 06:57:21.870152 arm64_fake_sigreturn_duplicated_fpsimd pass
11824 06:57:21.873157 arm64_fake_sigreturn_misaligned_sp pass
11825 06:57:21.876795 arm64_fake_sigreturn_missing_fpsimd pass
11826 06:57:21.879891 arm64_fake_sigreturn_sme_change_vl skip
11827 06:57:21.886524 arm64_fake_sigreturn_sve_change_vl skip
11828 06:57:21.889939 arm64_mangle_pstate_invalid_compat_toggle pass
11829 06:57:21.893094 arm64_mangle_pstate_invalid_daif_bits pass
11830 06:57:21.896494 arm64_mangle_pstate_invalid_mode_el1h pass
11831 06:57:21.899850 arm64_mangle_pstate_invalid_mode_el1t pass
11832 06:57:21.903216 arm64_mangle_pstate_invalid_mode_el2h pass
11833 06:57:21.909883 arm64_mangle_pstate_invalid_mode_el2t pass
11834 06:57:21.913260 arm64_mangle_pstate_invalid_mode_el3h pass
11835 06:57:21.916350 arm64_mangle_pstate_invalid_mode_el3t pass
11836 06:57:21.919613 arm64_sme_trap_no_sm skip
11837 06:57:21.922810 arm64_sme_trap_non_streaming skip
11838 06:57:21.923242 arm64_sme_trap_za pass
11839 06:57:21.926225 arm64_sme_vl skip
11840 06:57:21.926668 arm64_ssve_regs skip
11841 06:57:21.929603 arm64_sve_regs skip
11842 06:57:21.930067 arm64_sve_vl skip
11843 06:57:21.932892 arm64_za_no_regs skip
11844 06:57:21.933320 arm64_za_regs skip
11845 06:57:21.936209 arm64_pac_pauth_not_enabled skip
11846 06:57:21.939393 arm64_pac_pauth_not_enabled skip
11847 06:57:21.942607 arm64_pac_generic_pauth_not_enabled skip
11848 06:57:21.946034 arm64_pac_pauth_not_enabled skip
11849 06:57:21.949255 arm64_pac_pauth_not_enabled skip
11850 06:57:21.952765 arm64_pac_pauth_not_enabled skip
11851 06:57:21.955854 arm64_pac_generic_pauth_not_enabled skip
11852 06:57:21.959131 arm64_pac pass
11853 06:57:21.959584 arm64_fp-stress_FPSIMD-0-0 pass
11854 06:57:21.962428 arm64_fp-stress_FPSIMD-0-1 pass
11855 06:57:21.965844 arm64_fp-stress_FPSIMD-1-0 pass
11856 06:57:21.968917 arm64_fp-stress_FPSIMD-1-1 pass
11857 06:57:21.972380 arm64_fp-stress_FPSIMD-2-0 pass
11858 06:57:21.975663 arm64_fp-stress_FPSIMD-2-1 pass
11859 06:57:21.979111 arm64_fp-stress_FPSIMD-3-0 pass
11860 06:57:21.979559 arm64_fp-stress_FPSIMD-3-1 pass
11861 06:57:21.982111 arm64_fp-stress_FPSIMD-4-0 pass
11862 06:57:21.985502 arm64_fp-stress_FPSIMD-4-1 pass
11863 06:57:21.988878 arm64_fp-stress_FPSIMD-5-0 pass
11864 06:57:21.992115 arm64_fp-stress_FPSIMD-5-1 pass
11865 06:57:21.995506 arm64_fp-stress_FPSIMD-6-0 pass
11866 06:57:21.998609 arm64_fp-stress_FPSIMD-6-1 pass
11867 06:57:22.002032 arm64_fp-stress_FPSIMD-7-0 pass
11868 06:57:22.002463 arm64_fp-stress_FPSIMD-7-1 pass
11869 06:57:22.005320 arm64_fp-stress pass
11870 06:57:22.008655 arm64_sve-ptrace_sve_not_available skip
11871 06:57:22.011885 arm64_sve-ptrace skip
11872 06:57:22.015041 arm64_sve-probe-vls_sve_not_available skip
11873 06:57:22.018392 arm64_sve-probe-vls skip
11874 06:57:22.021886 arm64_vec-syscfg_sve_not_supported skip
11875 06:57:22.025142 arm64_vec-syscfg_sve_not_supported skip
11876 06:57:22.028283 arm64_vec-syscfg_sve_not_supported skip
11877 06:57:22.031533 arm64_vec-syscfg_sve_not_supported skip
11878 06:57:22.035068 arm64_vec-syscfg_sve_not_supported skip
11879 06:57:22.038206 arm64_vec-syscfg_sve_not_supported skip
11880 06:57:22.041442 arm64_vec-syscfg_sve_not_supported skip
11881 06:57:22.044819 arm64_vec-syscfg_sve_not_supported skip
11882 06:57:22.048207 arm64_vec-syscfg_sve_not_supported skip
11883 06:57:22.051532 arm64_vec-syscfg_sve_not_supported skip
11884 06:57:22.054764 arm64_vec-syscfg_sme_not_supported skip
11885 06:57:22.057943 arm64_vec-syscfg_sme_not_supported skip
11886 06:57:22.064552 arm64_vec-syscfg_sme_not_supported skip
11887 06:57:22.067851 arm64_vec-syscfg_sme_not_supported skip
11888 06:57:22.071291 arm64_vec-syscfg_sme_not_supported skip
11889 06:57:22.074699 arm64_vec-syscfg_sme_not_supported skip
11890 06:57:22.077815 arm64_vec-syscfg_sme_not_supported skip
11891 06:57:22.081098 arm64_vec-syscfg_sme_not_supported skip
11892 06:57:22.084731 arm64_vec-syscfg_sme_not_supported skip
11893 06:57:22.087681 arm64_vec-syscfg_sme_not_supported skip
11894 06:57:22.091106 arm64_vec-syscfg pass
11895 06:57:22.091560 arm64_za-fork_skipped pass
11896 06:57:22.094399 arm64_za-fork pass
11897 06:57:22.097745 arm64_za-ptrace_sme_not_available skip
11898 06:57:22.100973 arm64_za-ptrace skip
11899 06:57:22.101427 arm64_check_buffer_fill skip
11900 06:57:22.104311 arm64_check_child_memory skip
11901 06:57:22.107969 arm64_check_gcr_el1_cswitch skip
11902 06:57:22.111221 arm64_check_ksm_options skip
11903 06:57:22.114360 arm64_check_mmap_options skip
11904 06:57:22.117631 arm64_check_prctl_check_basic_read pass
11905 06:57:22.118089 arm64_check_prctl_NONE pass
11906 06:57:22.120825 arm64_check_prctl_sync skip
11907 06:57:22.124218 arm64_check_prctl_async skip
11908 06:57:22.127496 arm64_check_prctl_sync_async skip
11909 06:57:22.130898 arm64_check_prctl pass
11910 06:57:22.131343 arm64_check_tags_inclusion skip
11911 06:57:22.134290 arm64_check_user_mem skip
11912 06:57:22.137536 arm64_btitest_nohint_func_call_using_br_x0 skip
11913 06:57:22.143937 arm64_btitest_nohint_func_call_using_br_x16 skip
11914 06:57:22.147444 arm64_btitest_nohint_func_call_using_blr skip
11915 06:57:22.150857 arm64_btitest_bti_none_func_call_using_br_x0 skip
11916 06:57:22.157402 arm64_btitest_bti_none_func_call_using_br_x16 skip
11917 06:57:22.160404 arm64_btitest_bti_none_func_call_using_blr skip
11918 06:57:22.163945 arm64_btitest_bti_c_func_call_using_br_x0 skip
11919 06:57:22.170338 arm64_btitest_bti_c_func_call_using_br_x16 skip
11920 06:57:22.173803 arm64_btitest_bti_c_func_call_using_blr skip
11921 06:57:22.177190 arm64_btitest_bti_j_func_call_using_br_x0 skip
11922 06:57:22.180716 arm64_btitest_bti_j_func_call_using_br_x16 skip
11923 06:57:22.183553 arm64_btitest_bti_j_func_call_using_blr skip
11924 06:57:22.190192 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11925 06:57:22.193433 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11926 06:57:22.197060 arm64_btitest_bti_jc_func_call_using_blr skip
11927 06:57:22.203786 arm64_btitest_paciasp_func_call_using_br_x0 skip
11928 06:57:22.206999 arm64_btitest_paciasp_func_call_using_br_x16 skip
11929 06:57:22.210056 arm64_btitest_paciasp_func_call_using_blr skip
11930 06:57:22.213358 arm64_btitest pass
11931 06:57:22.216843 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11932 06:57:22.220251 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11933 06:57:22.226987 arm64_nobtitest_nohint_func_call_using_blr skip
11934 06:57:22.229998 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11935 06:57:22.236876 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11936 06:57:22.239929 arm64_nobtitest_bti_none_func_call_using_blr skip
11937 06:57:22.243224 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11938 06:57:22.250091 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11939 06:57:22.253326 arm64_nobtitest_bti_c_func_call_using_blr skip
11940 06:57:22.256714 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11941 06:57:22.259892 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11942 06:57:22.266286 arm64_nobtitest_bti_j_func_call_using_blr skip
11943 06:57:22.269849 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11944 06:57:22.273211 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11945 06:57:22.279878 arm64_nobtitest_bti_jc_func_call_using_blr skip
11946 06:57:22.282858 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11947 06:57:22.286215 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11948 06:57:22.292790 arm64_nobtitest_paciasp_func_call_using_blr skip
11949 06:57:22.293227 arm64_nobtitest pass
11950 06:57:22.296138 arm64_hwcap_cpuinfo_match_RNG pass
11951 06:57:22.299443 arm64_hwcap_sigill_rng skip
11952 06:57:22.302679 arm64_hwcap_cpuinfo_match_SME pass
11953 06:57:22.306168 arm64_hwcap_sigill_SME pass
11954 06:57:22.309539 arm64_hwcap_cpuinfo_match_SVE pass
11955 06:57:22.309970 arm64_hwcap_sigill_SVE pass
11956 06:57:22.312813 arm64_hwcap_cpuinfo_match_SVE_2 pass
11957 06:57:22.315925 arm64_hwcap_sigill_sve_2 skip
11958 06:57:22.319182 arm64_hwcap_cpuinfo_match_SVE_AES pass
11959 06:57:22.322613 arm64_hwcap_sigill_sve_aes skip
11960 06:57:22.325762 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11961 06:57:22.328964 arm64_hwcap_sigill_sve2_pmull skip
11962 06:57:22.332502 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11963 06:57:22.335574 arm64_hwcap_sigill_sve2_bitperm skip
11964 06:57:22.342208 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11965 06:57:22.342610 arm64_hwcap_sigill_sve2_sha3 skip
11966 06:57:22.348973 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11967 06:57:22.349433 arm64_hwcap_sigill_sve2_sm4 skip
11968 06:57:22.355640 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11969 06:57:22.356174 arm64_hwcap_sigill_sve2_i8mm skip
11970 06:57:22.361986 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11971 06:57:22.365469 arm64_hwcap_sigill_sve2_f32mm skip
11972 06:57:22.368873 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11973 06:57:22.372181 arm64_hwcap_sigill_sve2_f64mm skip
11974 06:57:22.375516 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11975 06:57:22.378622 arm64_hwcap_sigill_sve2_bf16 skip
11976 06:57:22.381850 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11977 06:57:22.385041 arm64_hwcap_sigill_sve2_ebf16 skip
11978 06:57:22.385467 arm64_hwcap pass
11979 06:57:22.388387 arm64_ptrace_read_tpidr_one pass
11980 06:57:22.391861 arm64_ptrace_write_tpidr_one pass
11981 06:57:22.395190 arm64_ptrace_verify_tpidr_one pass
11982 06:57:22.398464 arm64_ptrace_count_tpidrs pass
11983 06:57:22.401767 arm64_ptrace_tpidr2_write pass
11984 06:57:22.402199 arm64_ptrace_tpidr2_read pass
11985 06:57:22.404937 arm64_ptrace_write_tpidr_only pass
11986 06:57:22.408508 arm64_ptrace pass
11987 06:57:22.411473 arm64_syscall-abi_getpid_FPSIMD pass
11988 06:57:22.414731 arm64_syscall-abi_sched_yield_FPSIMD pass
11989 06:57:22.418144 arm64_syscall-abi pass
11990 06:57:22.421441 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11991 06:57:22.424813 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11992 06:57:22.428146 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11993 06:57:22.434553 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11994 06:57:22.437919 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11995 06:57:22.441279 arm64_tpidr2 pass
11996 06:57:22.444406 + ../../utils/send-to-lava.sh ./output/result.txt
11997 06:57:22.450991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11998 06:57:22.451819 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
12000 06:57:22.454832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12001 06:57:22.455503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12003 06:57:22.461141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12004 06:57:22.461828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12006 06:57:22.509872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12007 06:57:22.510575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12009 06:57:22.582110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12010 06:57:22.582811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12012 06:57:22.653414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12013 06:57:22.654186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12015 06:57:22.727359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12016 06:57:22.728066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12018 06:57:22.797865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12019 06:57:22.798583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12021 06:57:22.869020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12022 06:57:22.869922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12024 06:57:22.930007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12025 06:57:22.930290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12027 06:57:22.991500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12028 06:57:22.991769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12030 06:57:23.047918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12031 06:57:23.048188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12033 06:57:23.107813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12034 06:57:23.108081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12036 06:57:23.168849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12037 06:57:23.169115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12039 06:57:23.230108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12040 06:57:23.230378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12042 06:57:23.288091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12043 06:57:23.288364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12045 06:57:23.349434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12046 06:57:23.349745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12048 06:57:23.405982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12049 06:57:23.406255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12051 06:57:23.466744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12052 06:57:23.467009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12054 06:57:23.518099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12055 06:57:23.518364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12057 06:57:23.578037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12059 06:57:23.581225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12060 06:57:23.644487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12061 06:57:23.644791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12063 06:57:23.707683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12064 06:57:23.707955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12066 06:57:23.768039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12067 06:57:23.768307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12069 06:57:23.826690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12070 06:57:23.826960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12072 06:57:23.887263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12073 06:57:23.887533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12075 06:57:23.946386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12076 06:57:23.946728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12078 06:57:24.013591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12079 06:57:24.014465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12081 06:57:24.084696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12083 06:57:24.087903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12084 06:57:24.154455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12086 06:57:24.157611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12087 06:57:24.231097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12088 06:57:24.231824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12090 06:57:24.297680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12092 06:57:24.300453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12093 06:57:24.366555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12095 06:57:24.369597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12096 06:57:24.436311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12098 06:57:24.439475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12099 06:57:24.511084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12100 06:57:24.511982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12102 06:57:24.575116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12103 06:57:24.575845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12105 06:57:24.646144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12106 06:57:24.646969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12108 06:57:24.717169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12109 06:57:24.717912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12111 06:57:24.787598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12112 06:57:24.788295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12114 06:57:24.855572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12115 06:57:24.856427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12117 06:57:24.924056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12118 06:57:24.924771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12120 06:57:24.997637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12121 06:57:24.998363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12123 06:57:25.067070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12124 06:57:25.067781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12126 06:57:25.137853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12127 06:57:25.138586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12129 06:57:25.209368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12130 06:57:25.210162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12132 06:57:25.282725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12133 06:57:25.283459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12135 06:57:25.350638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12136 06:57:25.351346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12138 06:57:25.423110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12139 06:57:25.423894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12141 06:57:25.493365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12142 06:57:25.493637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12144 06:57:25.551301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12145 06:57:25.551568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12147 06:57:25.609674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12148 06:57:25.609938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12150 06:57:25.667684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12151 06:57:25.667946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12153 06:57:25.725688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12154 06:57:25.725954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12156 06:57:25.784309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12157 06:57:25.784572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12159 06:57:25.839493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12160 06:57:25.839763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12162 06:57:25.900457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12163 06:57:25.900729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12165 06:57:25.954980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12166 06:57:25.955242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12168 06:57:26.016893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12169 06:57:26.017168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12171 06:57:26.076840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12172 06:57:26.077107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12174 06:57:26.135225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12175 06:57:26.135493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12177 06:57:26.196025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12178 06:57:26.196321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12180 06:57:26.252247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12181 06:57:26.252515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12183 06:57:26.306340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12184 06:57:26.306613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12186 06:57:26.363207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12187 06:57:26.363475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12189 06:57:26.417341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12190 06:57:26.417662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12192 06:57:26.476293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12193 06:57:26.476618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12195 06:57:26.541072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12196 06:57:26.541434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12198 06:57:26.608746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12199 06:57:26.609532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12201 06:57:26.676420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12202 06:57:26.677178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12204 06:57:26.743825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12205 06:57:26.744719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12207 06:57:26.811807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12208 06:57:26.812701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12210 06:57:26.881947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12211 06:57:26.882658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12213 06:57:26.949956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12214 06:57:26.950698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12216 06:57:27.020332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12217 06:57:27.021195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12219 06:57:27.089747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12220 06:57:27.090456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12222 06:57:27.154920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12223 06:57:27.155622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12225 06:57:27.222469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12226 06:57:27.223250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12228 06:57:27.292658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12229 06:57:27.293367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12231 06:57:27.358484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12232 06:57:27.359205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12234 06:57:27.427948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12235 06:57:27.428878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12237 06:57:27.506593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12238 06:57:27.507319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12240 06:57:27.574994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12241 06:57:27.575753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12243 06:57:27.647880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12244 06:57:27.648594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12246 06:57:27.717899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12247 06:57:27.718614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12249 06:57:27.788850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12251 06:57:27.791558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12252 06:57:27.858175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12253 06:57:27.858885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12255 06:57:27.927785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12256 06:57:27.928492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12258 06:57:28.000091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12259 06:57:28.000809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12261 06:57:28.068909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12262 06:57:28.069683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12264 06:57:28.136842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12265 06:57:28.137566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12267 06:57:28.208515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12268 06:57:28.209330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12270 06:57:28.278493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12271 06:57:28.279268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12273 06:57:28.345800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12274 06:57:28.346512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12276 06:57:28.417938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12277 06:57:28.418670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12279 06:57:28.485468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12280 06:57:28.486255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12282 06:57:28.555682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12283 06:57:28.556443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12285 06:57:28.628971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12286 06:57:28.629790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12288 06:57:28.704014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12289 06:57:28.704978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12291 06:57:28.771479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12292 06:57:28.772293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12294 06:57:28.843948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12295 06:57:28.844718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12297 06:57:28.912898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12298 06:57:28.913876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12300 06:57:28.987354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12301 06:57:28.988087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12303 06:57:29.058201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12304 06:57:29.059018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12306 06:57:29.131621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12307 06:57:29.132430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12309 06:57:29.203659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12310 06:57:29.204432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12312 06:57:29.266911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12313 06:57:29.267181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12315 06:57:29.326080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12316 06:57:29.326350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12318 06:57:29.387341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12319 06:57:29.387614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12321 06:57:29.447329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12322 06:57:29.447601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12324 06:57:29.502728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12325 06:57:29.502990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12327 06:57:29.561490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12328 06:57:29.561782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12330 06:57:29.615757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12331 06:57:29.616031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12333 06:57:29.675730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12334 06:57:29.676163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12336 06:57:29.738936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12337 06:57:29.739706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12339 06:57:29.810460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12340 06:57:29.811286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12342 06:57:29.877809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12343 06:57:29.878510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12345 06:57:29.948378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12346 06:57:29.949094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12348 06:57:30.017600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12349 06:57:30.018345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12351 06:57:30.089855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12352 06:57:30.090579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12354 06:57:30.163226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12355 06:57:30.163963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12357 06:57:30.232492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12358 06:57:30.233196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12360 06:57:30.302226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12361 06:57:30.302950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12363 06:57:30.364809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12364 06:57:30.365081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12366 06:57:30.426568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12367 06:57:30.426844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12369 06:57:30.487964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12370 06:57:30.488245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12372 06:57:30.545403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12373 06:57:30.545717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12375 06:57:30.606947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12376 06:57:30.607224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12378 06:57:30.672387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12379 06:57:30.673173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12381 06:57:30.744054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12382 06:57:30.744780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12384 06:57:30.815086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12385 06:57:30.815900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12387 06:57:30.886719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12388 06:57:30.887457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12390 06:57:30.959977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12391 06:57:30.960703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12393 06:57:31.025941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12394 06:57:31.026682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12396 06:57:31.102479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12397 06:57:31.103212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12399 06:57:31.168471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12400 06:57:31.169177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12402 06:57:31.245449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12403 06:57:31.246324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12405 06:57:31.311180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12406 06:57:31.311965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12408 06:57:31.381421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12409 06:57:31.382190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12411 06:57:31.446809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12412 06:57:31.447557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12414 06:57:31.518301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12415 06:57:31.519125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12417 06:57:31.581778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12418 06:57:31.582587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12420 06:57:31.649894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12421 06:57:31.650743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12423 06:57:31.718990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12424 06:57:31.719700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12426 06:57:31.794142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12427 06:57:31.794857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12429 06:57:31.858605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12430 06:57:31.859335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12432 06:57:31.927918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12433 06:57:31.928657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12435 06:57:31.999393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12436 06:57:32.000118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12438 06:57:32.069904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12439 06:57:32.070671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12441 06:57:32.133831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12443 06:57:32.136843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12444 06:57:32.206312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12445 06:57:32.207164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12447 06:57:32.272909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12449 06:57:32.275689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12450 06:57:32.347621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12451 06:57:32.348339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12453 06:57:32.414257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12455 06:57:32.417196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12456 06:57:32.485459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12457 06:57:32.485755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12459 06:57:32.547305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12460 06:57:32.547583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12462 06:57:32.611534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12463 06:57:32.611795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12465 06:57:32.667470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12466 06:57:32.667750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12468 06:57:32.728274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12469 06:57:32.728541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12471 06:57:32.784342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12473 06:57:32.787504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12474 06:57:32.850786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12475 06:57:32.851063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12477 06:57:32.907784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12478 06:57:32.908069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12480 06:57:32.961751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12481 06:57:32.962559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12483 06:57:33.030413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12485 06:57:33.033522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12486 06:57:33.102667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12488 06:57:33.105715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12489 06:57:33.174617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12490 06:57:33.175384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12492 06:57:33.239874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12493 06:57:33.240583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12495 06:57:33.309960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12496 06:57:33.310671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12498 06:57:33.380816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12499 06:57:33.381563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12501 06:57:33.454270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12502 06:57:33.454991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12504 06:57:33.519360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12505 06:57:33.520151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12507 06:57:33.597457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12508 06:57:33.598296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12510 06:57:33.663331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12511 06:57:33.664055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12513 06:57:33.730112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12514 06:57:33.730822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12516 06:57:33.800263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12517 06:57:33.801041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12519 06:57:33.871269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12520 06:57:33.871981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12522 06:57:33.940709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12523 06:57:33.941462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12525 06:57:34.006316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12526 06:57:34.007031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12528 06:57:34.071888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12529 06:57:34.072629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12531 06:57:34.140781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12532 06:57:34.141364 + set +x
12533 06:57:34.142147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12535 06:57:34.147373 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12694862_1.6.2.3.5>
12536 06:57:34.148172 Received signal: <ENDRUN> 1_kselftest-arm64 12694862_1.6.2.3.5
12537 06:57:34.148596 Ending use of test pattern.
12538 06:57:34.148952 Ending test lava.1_kselftest-arm64 (12694862_1.6.2.3.5), duration 36.43
12540 06:57:34.150617 <LAVA_TEST_RUNNER EXIT>
12541 06:57:34.151257 ok: lava_test_shell seems to have completed
12542 06:57:34.156242 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12543 06:57:34.156985 end: 3.1 lava-test-shell (duration 00:00:37) [common]
12544 06:57:34.157433 end: 3 lava-test-retry (duration 00:00:37) [common]
12545 06:57:34.158016 start: 4 finalize (timeout 00:06:53) [common]
12546 06:57:34.158492 start: 4.1 power-off (timeout 00:00:30) [common]
12547 06:57:34.159263 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
12548 06:57:34.277059 >> Command sent successfully.
12549 06:57:34.280847 Returned 0 in 0 seconds
12550 06:57:34.381941 end: 4.1 power-off (duration 00:00:00) [common]
12552 06:57:34.383722 start: 4.2 read-feedback (timeout 00:06:52) [common]
12553 06:57:34.385278 Listened to connection for namespace 'common' for up to 1s
12554 06:57:35.385694 Finalising connection for namespace 'common'
12555 06:57:35.386565 Disconnecting from shell: Finalise
12556 06:57:35.387105 / #
12557 06:57:35.488170 end: 4.2 read-feedback (duration 00:00:01) [common]
12558 06:57:35.488825 end: 4 finalize (duration 00:00:01) [common]
12559 06:57:35.489416 Cleaning after the job
12560 06:57:35.489983 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/ramdisk
12561 06:57:35.503876 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/kernel
12562 06:57:35.534792 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/dtb
12563 06:57:35.535046 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/nfsrootfs
12564 06:57:35.631041 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694862/tftp-deploy-b_wrejdt/modules
12565 06:57:35.638717 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694862
12566 06:57:36.283766 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694862
12567 06:57:36.283930 Job finished correctly