Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 38
1 06:50:45.406994 lava-dispatcher, installed at version: 2023.10
2 06:50:45.407223 start: 0 validate
3 06:50:45.407358 Start time: 2024-02-03 06:50:45.407351+00:00 (UTC)
4 06:50:45.407486 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:50:45.407631 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 06:50:45.675956 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:50:45.676221 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:50:46.118677 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:50:46.118843 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:50:46.381362 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:50:46.381580 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:50:46.649791 Using caching service: 'http://localhost/cache/?uri=%s'
13 06:50:46.650059 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 06:50:46.918272 validate duration: 1.51
16 06:50:46.918540 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:50:46.918645 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:50:46.918737 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:50:46.918859 Not decompressing ramdisk as can be used compressed.
20 06:50:46.918976 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 06:50:46.919070 saving as /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/ramdisk/initrd.cpio.gz
22 06:50:46.919230 total size: 4665395 (4 MB)
23 06:50:46.920799 progress 0 % (0 MB)
24 06:50:46.922545 progress 5 % (0 MB)
25 06:50:46.924009 progress 10 % (0 MB)
26 06:50:46.925358 progress 15 % (0 MB)
27 06:50:46.926776 progress 20 % (0 MB)
28 06:50:46.928204 progress 25 % (1 MB)
29 06:50:46.929593 progress 30 % (1 MB)
30 06:50:46.930947 progress 35 % (1 MB)
31 06:50:46.932354 progress 40 % (1 MB)
32 06:50:46.933922 progress 45 % (2 MB)
33 06:50:46.935124 progress 50 % (2 MB)
34 06:50:46.936476 progress 55 % (2 MB)
35 06:50:46.937739 progress 60 % (2 MB)
36 06:50:46.938938 progress 65 % (2 MB)
37 06:50:46.940335 progress 70 % (3 MB)
38 06:50:46.941652 progress 75 % (3 MB)
39 06:50:46.942932 progress 80 % (3 MB)
40 06:50:46.944402 progress 85 % (3 MB)
41 06:50:46.945673 progress 90 % (4 MB)
42 06:50:46.946918 progress 95 % (4 MB)
43 06:50:46.948361 progress 100 % (4 MB)
44 06:50:46.948512 4 MB downloaded in 0.03 s (151.95 MB/s)
45 06:50:46.948662 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:50:46.948896 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:50:46.948980 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:50:46.949059 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:50:46.949188 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 06:50:46.949254 saving as /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/kernel/Image
52 06:50:46.949313 total size: 51532288 (49 MB)
53 06:50:46.949373 No compression specified
54 06:50:46.950419 progress 0 % (0 MB)
55 06:50:46.964956 progress 5 % (2 MB)
56 06:50:46.979520 progress 10 % (4 MB)
57 06:50:46.993754 progress 15 % (7 MB)
58 06:50:47.007991 progress 20 % (9 MB)
59 06:50:47.022512 progress 25 % (12 MB)
60 06:50:47.036910 progress 30 % (14 MB)
61 06:50:47.051375 progress 35 % (17 MB)
62 06:50:47.065954 progress 40 % (19 MB)
63 06:50:47.080395 progress 45 % (22 MB)
64 06:50:47.094989 progress 50 % (24 MB)
65 06:50:47.109747 progress 55 % (27 MB)
66 06:50:47.124665 progress 60 % (29 MB)
67 06:50:47.138736 progress 65 % (31 MB)
68 06:50:47.151834 progress 70 % (34 MB)
69 06:50:47.165313 progress 75 % (36 MB)
70 06:50:47.178917 progress 80 % (39 MB)
71 06:50:47.192150 progress 85 % (41 MB)
72 06:50:47.205555 progress 90 % (44 MB)
73 06:50:47.218803 progress 95 % (46 MB)
74 06:50:47.231855 progress 100 % (49 MB)
75 06:50:47.232067 49 MB downloaded in 0.28 s (173.81 MB/s)
76 06:50:47.232217 end: 1.2.1 http-download (duration 00:00:00) [common]
78 06:50:47.232453 end: 1.2 download-retry (duration 00:00:00) [common]
79 06:50:47.232540 start: 1.3 download-retry (timeout 00:10:00) [common]
80 06:50:47.232629 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 06:50:47.232769 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 06:50:47.232841 saving as /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/dtb/mt8192-asurada-spherion-r0.dtb
83 06:50:47.232903 total size: 47278 (0 MB)
84 06:50:47.232962 No compression specified
85 06:50:47.234128 progress 69 % (0 MB)
86 06:50:47.234401 progress 100 % (0 MB)
87 06:50:47.234565 0 MB downloaded in 0.00 s (27.16 MB/s)
88 06:50:47.234687 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:50:47.234913 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:50:47.235001 start: 1.4 download-retry (timeout 00:10:00) [common]
92 06:50:47.235084 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 06:50:47.235195 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 06:50:47.235262 saving as /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/nfsrootfs/full.rootfs.tar
95 06:50:47.235321 total size: 200813988 (191 MB)
96 06:50:47.235381 Using unxz to decompress xz
97 06:50:47.239533 progress 0 % (0 MB)
98 06:50:47.796889 progress 5 % (9 MB)
99 06:50:48.345182 progress 10 % (19 MB)
100 06:50:48.991789 progress 15 % (28 MB)
101 06:50:49.402910 progress 20 % (38 MB)
102 06:50:49.746653 progress 25 % (47 MB)
103 06:50:50.367704 progress 30 % (57 MB)
104 06:50:50.914136 progress 35 % (67 MB)
105 06:50:51.504640 progress 40 % (76 MB)
106 06:50:52.069523 progress 45 % (86 MB)
107 06:50:52.662019 progress 50 % (95 MB)
108 06:50:53.290553 progress 55 % (105 MB)
109 06:50:53.945974 progress 60 % (114 MB)
110 06:50:54.062776 progress 65 % (124 MB)
111 06:50:54.203755 progress 70 % (134 MB)
112 06:50:54.301724 progress 75 % (143 MB)
113 06:50:54.376515 progress 80 % (153 MB)
114 06:50:54.446567 progress 85 % (162 MB)
115 06:50:54.548520 progress 90 % (172 MB)
116 06:50:54.843855 progress 95 % (181 MB)
117 06:50:55.435284 progress 100 % (191 MB)
118 06:50:55.440589 191 MB downloaded in 8.21 s (23.34 MB/s)
119 06:50:55.440915 end: 1.4.1 http-download (duration 00:00:08) [common]
121 06:50:55.441363 end: 1.4 download-retry (duration 00:00:08) [common]
122 06:50:55.441511 start: 1.5 download-retry (timeout 00:09:51) [common]
123 06:50:55.441637 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 06:50:55.441839 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 06:50:55.441940 saving as /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/modules/modules.tar
126 06:50:55.442034 total size: 8624064 (8 MB)
127 06:50:55.442130 Using unxz to decompress xz
128 06:50:55.446924 progress 0 % (0 MB)
129 06:50:55.468048 progress 5 % (0 MB)
130 06:50:55.492190 progress 10 % (0 MB)
131 06:50:55.515722 progress 15 % (1 MB)
132 06:50:55.538880 progress 20 % (1 MB)
133 06:50:55.562655 progress 25 % (2 MB)
134 06:50:55.588908 progress 30 % (2 MB)
135 06:50:55.616618 progress 35 % (2 MB)
136 06:50:55.639881 progress 40 % (3 MB)
137 06:50:55.664700 progress 45 % (3 MB)
138 06:50:55.691249 progress 50 % (4 MB)
139 06:50:55.716537 progress 55 % (4 MB)
140 06:50:55.741542 progress 60 % (4 MB)
141 06:50:55.769126 progress 65 % (5 MB)
142 06:50:55.794269 progress 70 % (5 MB)
143 06:50:55.817791 progress 75 % (6 MB)
144 06:50:55.845196 progress 80 % (6 MB)
145 06:50:55.870962 progress 85 % (7 MB)
146 06:50:55.895799 progress 90 % (7 MB)
147 06:50:55.926830 progress 95 % (7 MB)
148 06:50:55.954981 progress 100 % (8 MB)
149 06:50:55.959842 8 MB downloaded in 0.52 s (15.88 MB/s)
150 06:50:55.960100 end: 1.5.1 http-download (duration 00:00:01) [common]
152 06:50:55.960386 end: 1.5 download-retry (duration 00:00:01) [common]
153 06:50:55.960479 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 06:50:55.960573 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 06:50:59.529457 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12694816/extract-nfsrootfs-_4ca9pq2
156 06:50:59.529665 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 06:50:59.529768 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 06:50:59.529938 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe
159 06:50:59.530071 makedir: /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin
160 06:50:59.530174 makedir: /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/tests
161 06:50:59.530275 makedir: /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/results
162 06:50:59.530377 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-add-keys
163 06:50:59.530524 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-add-sources
164 06:50:59.530654 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-background-process-start
165 06:50:59.530782 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-background-process-stop
166 06:50:59.530910 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-common-functions
167 06:50:59.531036 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-echo-ipv4
168 06:50:59.531161 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-install-packages
169 06:50:59.531287 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-installed-packages
170 06:50:59.531411 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-os-build
171 06:50:59.531537 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-probe-channel
172 06:50:59.531661 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-probe-ip
173 06:50:59.531785 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-target-ip
174 06:50:59.531909 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-target-mac
175 06:50:59.532033 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-target-storage
176 06:50:59.532160 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-test-case
177 06:50:59.532288 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-test-event
178 06:50:59.532413 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-test-feedback
179 06:50:59.532538 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-test-raise
180 06:50:59.532663 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-test-reference
181 06:50:59.532787 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-test-runner
182 06:50:59.532914 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-test-set
183 06:50:59.533038 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-test-shell
184 06:50:59.533163 Updating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-add-keys (debian)
185 06:50:59.533314 Updating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-add-sources (debian)
186 06:50:59.533453 Updating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-install-packages (debian)
187 06:50:59.533806 Updating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-installed-packages (debian)
188 06:50:59.533947 Updating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/bin/lava-os-build (debian)
189 06:50:59.534071 Creating /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/environment
190 06:50:59.534167 LAVA metadata
191 06:50:59.534240 - LAVA_JOB_ID=12694816
192 06:50:59.534304 - LAVA_DISPATCHER_IP=192.168.201.1
193 06:50:59.534403 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 06:50:59.534470 skipped lava-vland-overlay
195 06:50:59.534557 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 06:50:59.534638 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 06:50:59.534699 skipped lava-multinode-overlay
198 06:50:59.534797 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 06:50:59.534890 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 06:50:59.534962 Loading test definitions
201 06:50:59.535051 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 06:50:59.535122 Using /lava-12694816 at stage 0
203 06:50:59.535405 uuid=12694816_1.6.2.3.1 testdef=None
204 06:50:59.535494 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 06:50:59.535597 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 06:50:59.536053 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 06:50:59.536274 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 06:50:59.536835 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 06:50:59.537064 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 06:50:59.537611 runner path: /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/0/tests/0_timesync-off test_uuid 12694816_1.6.2.3.1
213 06:50:59.537764 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 06:50:59.537993 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 06:50:59.538066 Using /lava-12694816 at stage 0
217 06:50:59.538162 Fetching tests from https://github.com/kernelci/test-definitions.git
218 06:50:59.538241 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/0/tests/1_kselftest-tpm2'
219 06:51:03.829941 Running '/usr/bin/git checkout kernelci.org
220 06:51:03.975932 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 06:51:03.976687 uuid=12694816_1.6.2.3.5 testdef=None
222 06:51:03.976846 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 06:51:03.977097 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 06:51:03.977864 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 06:51:03.978100 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 06:51:03.979079 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 06:51:03.979312 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 06:51:03.980257 runner path: /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/0/tests/1_kselftest-tpm2 test_uuid 12694816_1.6.2.3.5
232 06:51:03.980350 BOARD='mt8192-asurada-spherion-r0'
233 06:51:03.980415 BRANCH='cip'
234 06:51:03.980475 SKIPFILE='/dev/null'
235 06:51:03.980534 SKIP_INSTALL='True'
236 06:51:03.980590 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 06:51:03.980650 TST_CASENAME=''
238 06:51:03.980705 TST_CMDFILES='tpm2'
239 06:51:03.980846 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 06:51:03.981051 Creating lava-test-runner.conf files
242 06:51:03.981114 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694816/lava-overlay-zarqo0fe/lava-12694816/0 for stage 0
243 06:51:03.981205 - 0_timesync-off
244 06:51:03.981271 - 1_kselftest-tpm2
245 06:51:03.981366 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 06:51:03.981452 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 06:51:11.432183 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 06:51:11.432332 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 06:51:11.432422 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 06:51:11.432523 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 06:51:11.432614 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 06:51:11.563786 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 06:51:11.564207 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 06:51:11.564374 extracting modules file /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694816/extract-nfsrootfs-_4ca9pq2
255 06:51:11.847761 extracting modules file /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694816/extract-overlay-ramdisk-rev6zhcs/ramdisk
256 06:51:12.076849 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 06:51:12.077060 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 06:51:12.077171 [common] Applying overlay to NFS
259 06:51:12.077241 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694816/compress-overlay-0ux7lbh8/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694816/extract-nfsrootfs-_4ca9pq2
260 06:51:12.990836 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 06:51:12.991008 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 06:51:12.991103 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 06:51:12.991192 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 06:51:12.991278 Building ramdisk /var/lib/lava/dispatcher/tmp/12694816/extract-overlay-ramdisk-rev6zhcs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694816/extract-overlay-ramdisk-rev6zhcs/ramdisk
265 06:51:13.324631 >> 119430 blocks
266 06:51:15.264315 rename /var/lib/lava/dispatcher/tmp/12694816/extract-overlay-ramdisk-rev6zhcs/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/ramdisk/ramdisk.cpio.gz
267 06:51:15.264764 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 06:51:15.264886 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 06:51:15.264990 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 06:51:15.265091 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/kernel/Image'
271 06:51:27.946530 Returned 0 in 12 seconds
272 06:51:28.047417 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/kernel/image.itb
273 06:51:28.442161 output: FIT description: Kernel Image image with one or more FDT blobs
274 06:51:28.442550 output: Created: Sat Feb 3 06:51:28 2024
275 06:51:28.442625 output: Image 0 (kernel-1)
276 06:51:28.442691 output: Description:
277 06:51:28.442756 output: Created: Sat Feb 3 06:51:28 2024
278 06:51:28.442819 output: Type: Kernel Image
279 06:51:28.442882 output: Compression: lzma compressed
280 06:51:28.442942 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
281 06:51:28.443004 output: Architecture: AArch64
282 06:51:28.443061 output: OS: Linux
283 06:51:28.443119 output: Load Address: 0x00000000
284 06:51:28.443177 output: Entry Point: 0x00000000
285 06:51:28.443234 output: Hash algo: crc32
286 06:51:28.443294 output: Hash value: 380e7c3c
287 06:51:28.443349 output: Image 1 (fdt-1)
288 06:51:28.443403 output: Description: mt8192-asurada-spherion-r0
289 06:51:28.443456 output: Created: Sat Feb 3 06:51:28 2024
290 06:51:28.443510 output: Type: Flat Device Tree
291 06:51:28.443564 output: Compression: uncompressed
292 06:51:28.443617 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 06:51:28.443670 output: Architecture: AArch64
294 06:51:28.443723 output: Hash algo: crc32
295 06:51:28.443776 output: Hash value: cc4352de
296 06:51:28.443829 output: Image 2 (ramdisk-1)
297 06:51:28.443882 output: Description: unavailable
298 06:51:28.443935 output: Created: Sat Feb 3 06:51:28 2024
299 06:51:28.443988 output: Type: RAMDisk Image
300 06:51:28.444041 output: Compression: Unknown Compression
301 06:51:28.444094 output: Data Size: 17802292 Bytes = 17385.05 KiB = 16.98 MiB
302 06:51:28.444147 output: Architecture: AArch64
303 06:51:28.444200 output: OS: Linux
304 06:51:28.444253 output: Load Address: unavailable
305 06:51:28.444306 output: Entry Point: unavailable
306 06:51:28.444359 output: Hash algo: crc32
307 06:51:28.444411 output: Hash value: d2d804ef
308 06:51:28.444463 output: Default Configuration: 'conf-1'
309 06:51:28.444516 output: Configuration 0 (conf-1)
310 06:51:28.444569 output: Description: mt8192-asurada-spherion-r0
311 06:51:28.444622 output: Kernel: kernel-1
312 06:51:28.444675 output: Init Ramdisk: ramdisk-1
313 06:51:28.444727 output: FDT: fdt-1
314 06:51:28.444780 output: Loadables: kernel-1
315 06:51:28.444832 output:
316 06:51:28.445035 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 06:51:28.445138 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 06:51:28.445250 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 06:51:28.445347 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 06:51:28.445430 No LXC device requested
321 06:51:28.445548 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 06:51:28.445634 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 06:51:28.445710 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 06:51:28.445781 Checking files for TFTP limit of 4294967296 bytes.
325 06:51:28.446296 end: 1 tftp-deploy (duration 00:00:42) [common]
326 06:51:28.446403 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 06:51:28.446500 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 06:51:28.446628 substitutions:
329 06:51:28.446697 - {DTB}: 12694816/tftp-deploy-t9mq3kaq/dtb/mt8192-asurada-spherion-r0.dtb
330 06:51:28.446763 - {INITRD}: 12694816/tftp-deploy-t9mq3kaq/ramdisk/ramdisk.cpio.gz
331 06:51:28.446823 - {KERNEL}: 12694816/tftp-deploy-t9mq3kaq/kernel/Image
332 06:51:28.446882 - {LAVA_MAC}: None
333 06:51:28.446939 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12694816/extract-nfsrootfs-_4ca9pq2
334 06:51:28.446995 - {NFS_SERVER_IP}: 192.168.201.1
335 06:51:28.447049 - {PRESEED_CONFIG}: None
336 06:51:28.447104 - {PRESEED_LOCAL}: None
337 06:51:28.447158 - {RAMDISK}: 12694816/tftp-deploy-t9mq3kaq/ramdisk/ramdisk.cpio.gz
338 06:51:28.447212 - {ROOT_PART}: None
339 06:51:28.447266 - {ROOT}: None
340 06:51:28.447319 - {SERVER_IP}: 192.168.201.1
341 06:51:28.447372 - {TEE}: None
342 06:51:28.447428 Parsed boot commands:
343 06:51:28.447481 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 06:51:28.447661 Parsed boot commands: tftpboot 192.168.201.1 12694816/tftp-deploy-t9mq3kaq/kernel/image.itb 12694816/tftp-deploy-t9mq3kaq/kernel/cmdline
345 06:51:28.447752 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 06:51:28.447837 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 06:51:28.447930 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 06:51:28.448018 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 06:51:28.448104 Not connected, no need to disconnect.
350 06:51:28.448182 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 06:51:28.448265 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 06:51:28.448335 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 06:51:28.452385 Setting prompt string to ['lava-test: # ']
354 06:51:28.452762 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 06:51:28.452869 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 06:51:28.452970 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 06:51:28.453089 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 06:51:28.453286 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 06:51:33.598158 >> Command sent successfully.
360 06:51:33.602852 Returned 0 in 5 seconds
361 06:51:33.703809 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 06:51:33.705266 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 06:51:33.705841 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 06:51:33.706339 Setting prompt string to 'Starting depthcharge on Spherion...'
366 06:51:33.706688 Changing prompt to 'Starting depthcharge on Spherion...'
367 06:51:33.707149 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 06:51:33.708407 [Enter `^Ec?' for help]
369 06:51:33.874600
370 06:51:33.874778
371 06:51:33.874857 F0: 102B 0000
372 06:51:33.874940
373 06:51:33.875001 F3: 1001 0000 [0200]
374 06:51:33.877682
375 06:51:33.877766 F3: 1001 0000
376 06:51:33.877833
377 06:51:33.877894 F7: 102D 0000
378 06:51:33.877955
379 06:51:33.880968 F1: 0000 0000
380 06:51:33.881052
381 06:51:33.881120 V0: 0000 0000 [0001]
382 06:51:33.881185
383 06:51:33.884430 00: 0007 8000
384 06:51:33.884518
385 06:51:33.884584 01: 0000 0000
386 06:51:33.884647
387 06:51:33.887649 BP: 0C00 0209 [0000]
388 06:51:33.887739
389 06:51:33.887810 G0: 1182 0000
390 06:51:33.887876
391 06:51:33.891595 EC: 0000 0021 [4000]
392 06:51:33.891685
393 06:51:33.891755 S7: 0000 0000 [0000]
394 06:51:33.891821
395 06:51:33.895490 CC: 0000 0000 [0001]
396 06:51:33.895671
397 06:51:33.895758 T0: 0000 0040 [010F]
398 06:51:33.895843
399 06:51:33.895924 Jump to BL
400 06:51:33.896002
401 06:51:33.921702
402 06:51:33.921972
403 06:51:33.922126
404 06:51:33.929331 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 06:51:33.933052 ARM64: Exception handlers installed.
406 06:51:33.936317 ARM64: Testing exception
407 06:51:33.939831 ARM64: Done test exception
408 06:51:33.946274 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 06:51:33.957014 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 06:51:33.963850 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 06:51:33.973410 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 06:51:33.980407 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 06:51:33.986994 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 06:51:33.998909 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 06:51:34.005286 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 06:51:34.024592 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 06:51:34.027632 WDT: Last reset was cold boot
418 06:51:34.031422 SPI1(PAD0) initialized at 2873684 Hz
419 06:51:34.034339 SPI5(PAD0) initialized at 992727 Hz
420 06:51:34.037841 VBOOT: Loading verstage.
421 06:51:34.044700 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 06:51:34.047905 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 06:51:34.051098 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 06:51:34.054476 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 06:51:34.061936 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 06:51:34.068802 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 06:51:34.079354 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 06:51:34.079803
429 06:51:34.080177
430 06:51:34.089581 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 06:51:34.092698 ARM64: Exception handlers installed.
432 06:51:34.095972 ARM64: Testing exception
433 06:51:34.096411 ARM64: Done test exception
434 06:51:34.102929 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 06:51:34.106251 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 06:51:34.119916 Probing TPM: . done!
437 06:51:34.120007 TPM ready after 0 ms
438 06:51:34.127066 Connected to device vid:did:rid of 1ae0:0028:00
439 06:51:34.133863 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 06:51:34.174017 Initialized TPM device CR50 revision 0
441 06:51:34.184895 tlcl_send_startup: Startup return code is 0
442 06:51:34.185152 TPM: setup succeeded
443 06:51:34.195890 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 06:51:34.205340 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 06:51:34.216258 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 06:51:34.226221 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 06:51:34.229686 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 06:51:34.234681 in-header: 03 07 00 00 08 00 00 00
449 06:51:34.238137 in-data: aa e4 47 04 13 02 00 00
450 06:51:34.241619 Chrome EC: UHEPI supported
451 06:51:34.248608 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 06:51:34.252493 in-header: 03 9d 00 00 08 00 00 00
453 06:51:34.256795 in-data: 10 20 20 08 00 00 00 00
454 06:51:34.257383 Phase 1
455 06:51:34.259912 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 06:51:34.266690 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 06:51:34.274215 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 06:51:34.277778 Recovery requested (1009000e)
459 06:51:34.283717 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 06:51:34.289140 tlcl_extend: response is 0
461 06:51:34.297038 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 06:51:34.302763 tlcl_extend: response is 0
463 06:51:34.309519 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 06:51:34.330434 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 06:51:34.337842 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 06:51:34.338434
467 06:51:34.338866
468 06:51:34.345350 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 06:51:34.348924 ARM64: Exception handlers installed.
470 06:51:34.352145 ARM64: Testing exception
471 06:51:34.355848 ARM64: Done test exception
472 06:51:34.375855 pmic_efuse_setting: Set efuses in 11 msecs
473 06:51:34.378955 pmwrap_interface_init: Select PMIF_VLD_RDY
474 06:51:34.386578 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 06:51:34.390320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 06:51:34.394567 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 06:51:34.397758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 06:51:34.405125 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 06:51:34.408781 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 06:51:34.412584 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 06:51:34.419545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 06:51:34.422881 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 06:51:34.426175 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 06:51:34.433205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 06:51:34.436170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 06:51:34.440026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 06:51:34.446781 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 06:51:34.453948 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 06:51:34.460285 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 06:51:34.463314 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 06:51:34.470299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 06:51:34.477176 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 06:51:34.480762 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 06:51:34.488006 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 06:51:34.491689 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 06:51:34.498627 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 06:51:34.502364 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 06:51:34.509513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 06:51:34.516731 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 06:51:34.520175 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 06:51:34.523793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 06:51:34.530632 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 06:51:34.534018 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 06:51:34.537886 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 06:51:34.544389 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 06:51:34.548343 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 06:51:34.555926 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 06:51:34.558915 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 06:51:34.562442 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 06:51:34.569303 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 06:51:34.572810 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 06:51:34.579410 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 06:51:34.582645 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 06:51:34.586419 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 06:51:34.592961 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 06:51:34.596298 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 06:51:34.599554 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 06:51:34.606472 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 06:51:34.609303 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 06:51:34.612922 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 06:51:34.619313 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 06:51:34.622878 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 06:51:34.625882 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 06:51:34.629559 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 06:51:34.639131 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 06:51:34.646172 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 06:51:34.652274 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 06:51:34.659065 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 06:51:34.669451 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 06:51:34.672082 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 06:51:34.675922 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 06:51:34.682447 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 06:51:34.689012 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2a
534 06:51:34.692467 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 06:51:34.699916 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 06:51:34.703230 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 06:51:34.712664 [RTC]rtc_get_frequency_meter,154: input=15, output=794
538 06:51:34.715996 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 06:51:34.722554 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 06:51:34.726099 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 06:51:34.729731 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 06:51:34.732638 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 06:51:34.735991 ADC[4]: Raw value=896300 ID=7
544 06:51:34.739085 ADC[3]: Raw value=213440 ID=1
545 06:51:34.742238 RAM Code: 0x71
546 06:51:34.745887 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 06:51:34.749387 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 06:51:34.759270 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 06:51:34.766003 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 06:51:34.769167 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 06:51:34.772467 in-header: 03 07 00 00 08 00 00 00
552 06:51:34.776202 in-data: aa e4 47 04 13 02 00 00
553 06:51:34.779144 Chrome EC: UHEPI supported
554 06:51:34.783231 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 06:51:34.787943 in-header: 03 d5 00 00 08 00 00 00
556 06:51:34.791308 in-data: 98 20 60 08 00 00 00 00
557 06:51:34.794680 MRC: failed to locate region type 0.
558 06:51:34.801927 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 06:51:34.805395 DRAM-K: Running full calibration
560 06:51:34.812509 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 06:51:34.813095 header.status = 0x0
562 06:51:34.815872 header.version = 0x6 (expected: 0x6)
563 06:51:34.819061 header.size = 0xd00 (expected: 0xd00)
564 06:51:34.822463 header.flags = 0x0
565 06:51:34.826158 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 06:51:34.844763 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
567 06:51:34.851345 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 06:51:34.854959 dram_init: ddr_geometry: 2
569 06:51:34.858465 [EMI] MDL number = 2
570 06:51:34.859061 [EMI] Get MDL freq = 0
571 06:51:34.861636 dram_init: ddr_type: 0
572 06:51:34.862216 is_discrete_lpddr4: 1
573 06:51:34.864534 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 06:51:34.865039
575 06:51:34.865592
576 06:51:34.867848 [Bian_co] ETT version 0.0.0.1
577 06:51:34.874600 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 06:51:34.875081
579 06:51:34.877833 dramc_set_vcore_voltage set vcore to 650000
580 06:51:34.878269 Read voltage for 800, 4
581 06:51:34.881127 Vio18 = 0
582 06:51:34.881617 Vcore = 650000
583 06:51:34.882069 Vdram = 0
584 06:51:34.884862 Vddq = 0
585 06:51:34.885314 Vmddr = 0
586 06:51:34.887937 dram_init: config_dvfs: 1
587 06:51:34.891554 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 06:51:34.898265 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 06:51:34.901228 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 06:51:34.904811 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 06:51:34.908300 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 06:51:34.911574 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 06:51:34.914786 MEM_TYPE=3, freq_sel=18
594 06:51:34.918276 sv_algorithm_assistance_LP4_1600
595 06:51:34.921466 ============ PULL DRAM RESETB DOWN ============
596 06:51:34.924881 ========== PULL DRAM RESETB DOWN end =========
597 06:51:34.931733 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 06:51:34.934919 ===================================
599 06:51:34.938255 LPDDR4 DRAM CONFIGURATION
600 06:51:34.938812 ===================================
601 06:51:34.941673 EX_ROW_EN[0] = 0x0
602 06:51:34.944650 EX_ROW_EN[1] = 0x0
603 06:51:34.945204 LP4Y_EN = 0x0
604 06:51:34.948000 WORK_FSP = 0x0
605 06:51:34.948551 WL = 0x2
606 06:51:34.951669 RL = 0x2
607 06:51:34.952228 BL = 0x2
608 06:51:34.954861 RPST = 0x0
609 06:51:34.955412 RD_PRE = 0x0
610 06:51:34.958047 WR_PRE = 0x1
611 06:51:34.958603 WR_PST = 0x0
612 06:51:34.961439 DBI_WR = 0x0
613 06:51:34.962039 DBI_RD = 0x0
614 06:51:34.964410 OTF = 0x1
615 06:51:34.968017 ===================================
616 06:51:34.971238 ===================================
617 06:51:34.971689 ANA top config
618 06:51:34.974751 ===================================
619 06:51:34.977816 DLL_ASYNC_EN = 0
620 06:51:34.981399 ALL_SLAVE_EN = 1
621 06:51:34.984549 NEW_RANK_MODE = 1
622 06:51:34.985122 DLL_IDLE_MODE = 1
623 06:51:34.987959 LP45_APHY_COMB_EN = 1
624 06:51:34.991652 TX_ODT_DIS = 1
625 06:51:34.995533 NEW_8X_MODE = 1
626 06:51:34.996096 ===================================
627 06:51:34.998561 ===================================
628 06:51:35.002701 data_rate = 1600
629 06:51:35.006479 CKR = 1
630 06:51:35.010243 DQ_P2S_RATIO = 8
631 06:51:35.013634 ===================================
632 06:51:35.014093 CA_P2S_RATIO = 8
633 06:51:35.017720 DQ_CA_OPEN = 0
634 06:51:35.021074 DQ_SEMI_OPEN = 0
635 06:51:35.024847 CA_SEMI_OPEN = 0
636 06:51:35.025287 CA_FULL_RATE = 0
637 06:51:35.028759 DQ_CKDIV4_EN = 1
638 06:51:35.032537 CA_CKDIV4_EN = 1
639 06:51:35.033097 CA_PREDIV_EN = 0
640 06:51:35.036747 PH8_DLY = 0
641 06:51:35.040465 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 06:51:35.044344 DQ_AAMCK_DIV = 4
643 06:51:35.044893 CA_AAMCK_DIV = 4
644 06:51:35.047945 CA_ADMCK_DIV = 4
645 06:51:35.051416 DQ_TRACK_CA_EN = 0
646 06:51:35.055066 CA_PICK = 800
647 06:51:35.055503 CA_MCKIO = 800
648 06:51:35.058749 MCKIO_SEMI = 0
649 06:51:35.062657 PLL_FREQ = 3068
650 06:51:35.066407 DQ_UI_PI_RATIO = 32
651 06:51:35.066848 CA_UI_PI_RATIO = 0
652 06:51:35.070248 ===================================
653 06:51:35.074308 ===================================
654 06:51:35.077789 memory_type:LPDDR4
655 06:51:35.078327 GP_NUM : 10
656 06:51:35.081299 SRAM_EN : 1
657 06:51:35.081774 MD32_EN : 0
658 06:51:35.084436 ===================================
659 06:51:35.087831 [ANA_INIT] >>>>>>>>>>>>>>
660 06:51:35.091138 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 06:51:35.094284 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 06:51:35.098183 ===================================
663 06:51:35.101097 data_rate = 1600,PCW = 0X7600
664 06:51:35.104743 ===================================
665 06:51:35.108007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 06:51:35.114627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 06:51:35.117818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 06:51:35.124495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 06:51:35.128400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 06:51:35.131840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 06:51:35.132332 [ANA_INIT] flow start
672 06:51:35.136060 [ANA_INIT] PLL >>>>>>>>
673 06:51:35.136497 [ANA_INIT] PLL <<<<<<<<
674 06:51:35.139270 [ANA_INIT] MIDPI >>>>>>>>
675 06:51:35.142964 [ANA_INIT] MIDPI <<<<<<<<
676 06:51:35.143531 [ANA_INIT] DLL >>>>>>>>
677 06:51:35.147171 [ANA_INIT] flow end
678 06:51:35.150353 ============ LP4 DIFF to SE enter ============
679 06:51:35.154011 ============ LP4 DIFF to SE exit ============
680 06:51:35.157557 [ANA_INIT] <<<<<<<<<<<<<
681 06:51:35.158000 [Flow] Enable top DCM control >>>>>
682 06:51:35.161005 [Flow] Enable top DCM control <<<<<
683 06:51:35.165053 Enable DLL master slave shuffle
684 06:51:35.171996 ==============================================================
685 06:51:35.172454 Gating Mode config
686 06:51:35.178529 ==============================================================
687 06:51:35.182178 Config description:
688 06:51:35.188531 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 06:51:35.195039 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 06:51:35.202103 SELPH_MODE 0: By rank 1: By Phase
691 06:51:35.205090 ==============================================================
692 06:51:35.209061 GAT_TRACK_EN = 1
693 06:51:35.211861 RX_GATING_MODE = 2
694 06:51:35.215209 RX_GATING_TRACK_MODE = 2
695 06:51:35.218966 SELPH_MODE = 1
696 06:51:35.222009 PICG_EARLY_EN = 1
697 06:51:35.225853 VALID_LAT_VALUE = 1
698 06:51:35.232286 ==============================================================
699 06:51:35.235583 Enter into Gating configuration >>>>
700 06:51:35.238450 Exit from Gating configuration <<<<
701 06:51:35.242298 Enter into DVFS_PRE_config >>>>>
702 06:51:35.252124 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 06:51:35.256151 Exit from DVFS_PRE_config <<<<<
704 06:51:35.256692 Enter into PICG configuration >>>>
705 06:51:35.259794 Exit from PICG configuration <<<<
706 06:51:35.263331 [RX_INPUT] configuration >>>>>
707 06:51:35.266803 [RX_INPUT] configuration <<<<<
708 06:51:35.270435 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 06:51:35.277526 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 06:51:35.285102 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 06:51:35.288671 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 06:51:35.295818 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 06:51:35.303013 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 06:51:35.307029 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 06:51:35.310312 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 06:51:35.314050 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 06:51:35.317675 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 06:51:35.321553 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 06:51:35.328649 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 06:51:35.329089 ===================================
721 06:51:35.332169 LPDDR4 DRAM CONFIGURATION
722 06:51:35.335691 ===================================
723 06:51:35.336134 EX_ROW_EN[0] = 0x0
724 06:51:35.339815 EX_ROW_EN[1] = 0x0
725 06:51:35.340253 LP4Y_EN = 0x0
726 06:51:35.343534 WORK_FSP = 0x0
727 06:51:35.344077 WL = 0x2
728 06:51:35.347503 RL = 0x2
729 06:51:35.348046 BL = 0x2
730 06:51:35.351008 RPST = 0x0
731 06:51:35.351446 RD_PRE = 0x0
732 06:51:35.354327 WR_PRE = 0x1
733 06:51:35.354861 WR_PST = 0x0
734 06:51:35.358178 DBI_WR = 0x0
735 06:51:35.358614 DBI_RD = 0x0
736 06:51:35.361894 OTF = 0x1
737 06:51:35.362335 ===================================
738 06:51:35.365516 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 06:51:35.373024 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 06:51:35.376708 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 06:51:35.380525 ===================================
742 06:51:35.380966 LPDDR4 DRAM CONFIGURATION
743 06:51:35.383798 ===================================
744 06:51:35.387769 EX_ROW_EN[0] = 0x10
745 06:51:35.388311 EX_ROW_EN[1] = 0x0
746 06:51:35.391116 LP4Y_EN = 0x0
747 06:51:35.391554 WORK_FSP = 0x0
748 06:51:35.394905 WL = 0x2
749 06:51:35.395345 RL = 0x2
750 06:51:35.398605 BL = 0x2
751 06:51:35.399043 RPST = 0x0
752 06:51:35.402701 RD_PRE = 0x0
753 06:51:35.403138 WR_PRE = 0x1
754 06:51:35.406161 WR_PST = 0x0
755 06:51:35.406598 DBI_WR = 0x0
756 06:51:35.409790 DBI_RD = 0x0
757 06:51:35.410227 OTF = 0x1
758 06:51:35.413791 ===================================
759 06:51:35.421266 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 06:51:35.424879 nWR fixed to 40
761 06:51:35.425556 [ModeRegInit_LP4] CH0 RK0
762 06:51:35.428629 [ModeRegInit_LP4] CH0 RK1
763 06:51:35.429203 [ModeRegInit_LP4] CH1 RK0
764 06:51:35.432343 [ModeRegInit_LP4] CH1 RK1
765 06:51:35.435874 match AC timing 13
766 06:51:35.439460 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 06:51:35.443117 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 06:51:35.446575 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 06:51:35.450539 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 06:51:35.453939 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 06:51:35.457664 [EMI DOE] emi_dcm 0
772 06:51:35.461464 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 06:51:35.461964 ==
774 06:51:35.465272 Dram Type= 6, Freq= 0, CH_0, rank 0
775 06:51:35.468697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 06:51:35.469156 ==
777 06:51:35.476388 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 06:51:35.479541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 06:51:35.490313 [CA 0] Center 38 (7~69) winsize 63
780 06:51:35.493987 [CA 1] Center 37 (7~68) winsize 62
781 06:51:35.497757 [CA 2] Center 35 (5~66) winsize 62
782 06:51:35.501410 [CA 3] Center 35 (5~66) winsize 62
783 06:51:35.505199 [CA 4] Center 34 (4~65) winsize 62
784 06:51:35.508901 [CA 5] Center 33 (3~64) winsize 62
785 06:51:35.508992
786 06:51:35.512699 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 06:51:35.512788
788 06:51:35.516023 [CATrainingPosCal] consider 1 rank data
789 06:51:35.516112 u2DelayCellTimex100 = 270/100 ps
790 06:51:35.519903 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
791 06:51:35.523298 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
792 06:51:35.526896 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
793 06:51:35.534341 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
794 06:51:35.534432 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
795 06:51:35.538082 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
796 06:51:35.538170
797 06:51:35.545297 CA PerBit enable=1, Macro0, CA PI delay=33
798 06:51:35.545389
799 06:51:35.545527 [CBTSetCACLKResult] CA Dly = 33
800 06:51:35.548741 CS Dly: 6 (0~37)
801 06:51:35.548828 ==
802 06:51:35.551854 Dram Type= 6, Freq= 0, CH_0, rank 1
803 06:51:35.555322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 06:51:35.555410 ==
805 06:51:35.562056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 06:51:35.568524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 06:51:35.576385 [CA 0] Center 38 (7~69) winsize 63
808 06:51:35.579836 [CA 1] Center 38 (7~69) winsize 63
809 06:51:35.583138 [CA 2] Center 35 (5~66) winsize 62
810 06:51:35.586392 [CA 3] Center 35 (5~66) winsize 62
811 06:51:35.589912 [CA 4] Center 34 (4~65) winsize 62
812 06:51:35.593114 [CA 5] Center 34 (4~65) winsize 62
813 06:51:35.593202
814 06:51:35.596462 [CmdBusTrainingLP45] Vref(ca) range 1: 32
815 06:51:35.596549
816 06:51:35.599618 [CATrainingPosCal] consider 2 rank data
817 06:51:35.602967 u2DelayCellTimex100 = 270/100 ps
818 06:51:35.606317 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 06:51:35.609578 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 06:51:35.616317 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 06:51:35.619785 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 06:51:35.623077 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 06:51:35.626381 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
824 06:51:35.626469
825 06:51:35.629804 CA PerBit enable=1, Macro0, CA PI delay=34
826 06:51:35.629892
827 06:51:35.633120 [CBTSetCACLKResult] CA Dly = 34
828 06:51:35.633208 CS Dly: 6 (0~38)
829 06:51:35.633296
830 06:51:35.636401 ----->DramcWriteLeveling(PI) begin...
831 06:51:35.639808 ==
832 06:51:35.639895 Dram Type= 6, Freq= 0, CH_0, rank 0
833 06:51:35.646509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 06:51:35.646597 ==
835 06:51:35.650046 Write leveling (Byte 0): 34 => 34
836 06:51:35.653266 Write leveling (Byte 1): 32 => 32
837 06:51:35.653354 DramcWriteLeveling(PI) end<-----
838 06:51:35.656686
839 06:51:35.656772 ==
840 06:51:35.659798 Dram Type= 6, Freq= 0, CH_0, rank 0
841 06:51:35.663308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 06:51:35.663396 ==
843 06:51:35.666451 [Gating] SW mode calibration
844 06:51:35.673096 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 06:51:35.676474 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 06:51:35.683276 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 06:51:35.686691 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 06:51:35.690009 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
849 06:51:35.696626 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 06:51:35.699974 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 06:51:35.703742 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 06:51:35.710202 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 06:51:35.713930 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 06:51:35.717434 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 06:51:35.720971 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 06:51:35.724746 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 06:51:35.731653 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 06:51:35.734914 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 06:51:35.738347 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 06:51:35.745175 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 06:51:35.748976 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 06:51:35.752359 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 06:51:35.755810 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 06:51:35.762356 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
865 06:51:35.765925 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
866 06:51:35.769067 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 06:51:35.775784 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 06:51:35.779010 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 06:51:35.782353 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 06:51:35.789298 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 06:51:35.792415 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 06:51:35.795887 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 06:51:35.802199 0 9 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
874 06:51:35.805889 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 06:51:35.809104 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 06:51:35.815510 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 06:51:35.818980 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 06:51:35.822146 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 06:51:35.825666 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 06:51:35.832303 0 10 8 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 1)
881 06:51:35.835641 0 10 12 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
882 06:51:35.839024 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 06:51:35.845665 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 06:51:35.848933 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 06:51:35.852356 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 06:51:35.858933 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 06:51:35.862329 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 06:51:35.865877 0 11 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
889 06:51:35.872129 0 11 12 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
890 06:51:35.875632 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 06:51:35.878967 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 06:51:35.885599 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 06:51:35.888997 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 06:51:35.892330 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 06:51:35.898782 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 06:51:35.902322 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 06:51:35.905657 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 06:51:35.912399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 06:51:35.915450 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 06:51:35.919142 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 06:51:35.922320 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 06:51:35.928991 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 06:51:35.932294 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 06:51:35.935619 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 06:51:35.942506 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 06:51:35.945868 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 06:51:35.949312 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 06:51:35.955650 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 06:51:35.959090 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 06:51:35.962148 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 06:51:35.968971 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 06:51:35.972404 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 06:51:35.975673 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
914 06:51:35.979011 Total UI for P1: 0, mck2ui 16
915 06:51:35.982427 best dqsien dly found for B0: ( 0, 14, 10)
916 06:51:35.985839 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 06:51:35.989379 Total UI for P1: 0, mck2ui 16
918 06:51:35.992759 best dqsien dly found for B1: ( 0, 14, 12)
919 06:51:35.998995 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
920 06:51:36.002309 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 06:51:36.002397
922 06:51:36.005753 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
923 06:51:36.009114 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 06:51:36.012419 [Gating] SW calibration Done
925 06:51:36.012510 ==
926 06:51:36.016017 Dram Type= 6, Freq= 0, CH_0, rank 0
927 06:51:36.019579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 06:51:36.019667 ==
929 06:51:36.022780 RX Vref Scan: 0
930 06:51:36.022870
931 06:51:36.022971 RX Vref 0 -> 0, step: 1
932 06:51:36.023054
933 06:51:36.025907 RX Delay -130 -> 252, step: 16
934 06:51:36.029011 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
935 06:51:36.035701 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
936 06:51:36.039218 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 06:51:36.042645 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 06:51:36.046074 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
939 06:51:36.049423 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
940 06:51:36.052452 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 06:51:36.059422 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 06:51:36.062692 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
943 06:51:36.066060 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
944 06:51:36.069299 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
945 06:51:36.072738 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 06:51:36.079128 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 06:51:36.082485 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 06:51:36.085929 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 06:51:36.089231 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 06:51:36.089317 ==
951 06:51:36.092771 Dram Type= 6, Freq= 0, CH_0, rank 0
952 06:51:36.099297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 06:51:36.099385 ==
954 06:51:36.099473 DQS Delay:
955 06:51:36.099555 DQS0 = 0, DQS1 = 0
956 06:51:36.102869 DQM Delay:
957 06:51:36.102955 DQM0 = 81, DQM1 = 70
958 06:51:36.105972 DQ Delay:
959 06:51:36.109273 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
960 06:51:36.109351 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
961 06:51:36.112909 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =61
962 06:51:36.119669 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 06:51:36.119757
964 06:51:36.119845
965 06:51:36.119928 ==
966 06:51:36.123536 Dram Type= 6, Freq= 0, CH_0, rank 0
967 06:51:36.127004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 06:51:36.127096 ==
969 06:51:36.127183
970 06:51:36.127285
971 06:51:36.127386 TX Vref Scan disable
972 06:51:36.130707 == TX Byte 0 ==
973 06:51:36.134072 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
974 06:51:36.140780 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
975 06:51:36.140867 == TX Byte 1 ==
976 06:51:36.143973 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
977 06:51:36.150665 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
978 06:51:36.150754 ==
979 06:51:36.154065 Dram Type= 6, Freq= 0, CH_0, rank 0
980 06:51:36.157100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 06:51:36.157187 ==
982 06:51:36.170050 TX Vref=22, minBit 10, minWin=26, winSum=436
983 06:51:36.173322 TX Vref=24, minBit 14, minWin=26, winSum=437
984 06:51:36.176623 TX Vref=26, minBit 5, minWin=27, winSum=442
985 06:51:36.180176 TX Vref=28, minBit 5, minWin=27, winSum=443
986 06:51:36.183219 TX Vref=30, minBit 14, minWin=26, winSum=442
987 06:51:36.189929 TX Vref=32, minBit 5, minWin=27, winSum=446
988 06:51:36.193338 [TxChooseVref] Worse bit 5, Min win 27, Win sum 446, Final Vref 32
989 06:51:36.193426
990 06:51:36.196646 Final TX Range 1 Vref 32
991 06:51:36.196734
992 06:51:36.196820 ==
993 06:51:36.199761 Dram Type= 6, Freq= 0, CH_0, rank 0
994 06:51:36.203134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 06:51:36.203222 ==
996 06:51:36.206469
997 06:51:36.206556
998 06:51:36.206644 TX Vref Scan disable
999 06:51:36.210088 == TX Byte 0 ==
1000 06:51:36.213213 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1001 06:51:36.216691 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1002 06:51:36.220161 == TX Byte 1 ==
1003 06:51:36.223605 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1004 06:51:36.226840 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1005 06:51:36.230001
1006 06:51:36.230090 [DATLAT]
1007 06:51:36.230178 Freq=800, CH0 RK0
1008 06:51:36.230262
1009 06:51:36.233646 DATLAT Default: 0xa
1010 06:51:36.233733 0, 0xFFFF, sum = 0
1011 06:51:36.236980 1, 0xFFFF, sum = 0
1012 06:51:36.237599 2, 0xFFFF, sum = 0
1013 06:51:36.240492 3, 0xFFFF, sum = 0
1014 06:51:36.240941 4, 0xFFFF, sum = 0
1015 06:51:36.244252 5, 0xFFFF, sum = 0
1016 06:51:36.247147 6, 0xFFFF, sum = 0
1017 06:51:36.247591 7, 0xFFFF, sum = 0
1018 06:51:36.251176 8, 0xFFFF, sum = 0
1019 06:51:36.251728 9, 0x0, sum = 1
1020 06:51:36.252216 10, 0x0, sum = 2
1021 06:51:36.254000 11, 0x0, sum = 3
1022 06:51:36.254440 12, 0x0, sum = 4
1023 06:51:36.257166 best_step = 10
1024 06:51:36.257735
1025 06:51:36.258131 ==
1026 06:51:36.260465 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 06:51:36.263597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 06:51:36.264027 ==
1029 06:51:36.266879 RX Vref Scan: 1
1030 06:51:36.267359
1031 06:51:36.267787 Set Vref Range= 32 -> 127
1032 06:51:36.270450
1033 06:51:36.270876 RX Vref 32 -> 127, step: 1
1034 06:51:36.271219
1035 06:51:36.273768 RX Delay -111 -> 252, step: 8
1036 06:51:36.274212
1037 06:51:36.277093 Set Vref, RX VrefLevel [Byte0]: 32
1038 06:51:36.280573 [Byte1]: 32
1039 06:51:36.281156
1040 06:51:36.283461 Set Vref, RX VrefLevel [Byte0]: 33
1041 06:51:36.287144 [Byte1]: 33
1042 06:51:36.290977
1043 06:51:36.291400 Set Vref, RX VrefLevel [Byte0]: 34
1044 06:51:36.294430 [Byte1]: 34
1045 06:51:36.298774
1046 06:51:36.299300 Set Vref, RX VrefLevel [Byte0]: 35
1047 06:51:36.302009 [Byte1]: 35
1048 06:51:36.306134
1049 06:51:36.306584 Set Vref, RX VrefLevel [Byte0]: 36
1050 06:51:36.309547 [Byte1]: 36
1051 06:51:36.313667
1052 06:51:36.313762 Set Vref, RX VrefLevel [Byte0]: 37
1053 06:51:36.316966 [Byte1]: 37
1054 06:51:36.321267
1055 06:51:36.321418 Set Vref, RX VrefLevel [Byte0]: 38
1056 06:51:36.324636 [Byte1]: 38
1057 06:51:36.329066
1058 06:51:36.329210 Set Vref, RX VrefLevel [Byte0]: 39
1059 06:51:36.332303 [Byte1]: 39
1060 06:51:36.336270
1061 06:51:36.336383 Set Vref, RX VrefLevel [Byte0]: 40
1062 06:51:36.339936 [Byte1]: 40
1063 06:51:36.344520
1064 06:51:36.344687 Set Vref, RX VrefLevel [Byte0]: 41
1065 06:51:36.347965 [Byte1]: 41
1066 06:51:36.351969
1067 06:51:36.352148 Set Vref, RX VrefLevel [Byte0]: 42
1068 06:51:36.355164 [Byte1]: 42
1069 06:51:36.359737
1070 06:51:36.359902 Set Vref, RX VrefLevel [Byte0]: 43
1071 06:51:36.362830 [Byte1]: 43
1072 06:51:36.366963
1073 06:51:36.367130 Set Vref, RX VrefLevel [Byte0]: 44
1074 06:51:36.370544 [Byte1]: 44
1075 06:51:36.375322
1076 06:51:36.375499 Set Vref, RX VrefLevel [Byte0]: 45
1077 06:51:36.378502 [Byte1]: 45
1078 06:51:36.383136
1079 06:51:36.383316 Set Vref, RX VrefLevel [Byte0]: 46
1080 06:51:36.386498 [Byte1]: 46
1081 06:51:36.390671
1082 06:51:36.390876 Set Vref, RX VrefLevel [Byte0]: 47
1083 06:51:36.393667 [Byte1]: 47
1084 06:51:36.398154
1085 06:51:36.398356 Set Vref, RX VrefLevel [Byte0]: 48
1086 06:51:36.401715 [Byte1]: 48
1087 06:51:36.405964
1088 06:51:36.406227 Set Vref, RX VrefLevel [Byte0]: 49
1089 06:51:36.409285 [Byte1]: 49
1090 06:51:36.413239
1091 06:51:36.413514 Set Vref, RX VrefLevel [Byte0]: 50
1092 06:51:36.416822 [Byte1]: 50
1093 06:51:36.420960
1094 06:51:36.421288 Set Vref, RX VrefLevel [Byte0]: 51
1095 06:51:36.424497 [Byte1]: 51
1096 06:51:36.428681
1097 06:51:36.429167 Set Vref, RX VrefLevel [Byte0]: 52
1098 06:51:36.431905 [Byte1]: 52
1099 06:51:36.436667
1100 06:51:36.437194 Set Vref, RX VrefLevel [Byte0]: 53
1101 06:51:36.439919 [Byte1]: 53
1102 06:51:36.444070
1103 06:51:36.444615 Set Vref, RX VrefLevel [Byte0]: 54
1104 06:51:36.447632 [Byte1]: 54
1105 06:51:36.452070
1106 06:51:36.452619 Set Vref, RX VrefLevel [Byte0]: 55
1107 06:51:36.454674 [Byte1]: 55
1108 06:51:36.459463
1109 06:51:36.460005 Set Vref, RX VrefLevel [Byte0]: 56
1110 06:51:36.462270 [Byte1]: 56
1111 06:51:36.466791
1112 06:51:36.467218 Set Vref, RX VrefLevel [Byte0]: 57
1113 06:51:36.470073 [Byte1]: 57
1114 06:51:36.474629
1115 06:51:36.475153 Set Vref, RX VrefLevel [Byte0]: 58
1116 06:51:36.477757 [Byte1]: 58
1117 06:51:36.482088
1118 06:51:36.482512 Set Vref, RX VrefLevel [Byte0]: 59
1119 06:51:36.485546 [Byte1]: 59
1120 06:51:36.489826
1121 06:51:36.490354 Set Vref, RX VrefLevel [Byte0]: 60
1122 06:51:36.493187 [Byte1]: 60
1123 06:51:36.497646
1124 06:51:36.498165 Set Vref, RX VrefLevel [Byte0]: 61
1125 06:51:36.500711 [Byte1]: 61
1126 06:51:36.505292
1127 06:51:36.505865 Set Vref, RX VrefLevel [Byte0]: 62
1128 06:51:36.508300 [Byte1]: 62
1129 06:51:36.512704
1130 06:51:36.513265 Set Vref, RX VrefLevel [Byte0]: 63
1131 06:51:36.516597 [Byte1]: 63
1132 06:51:36.520436
1133 06:51:36.520962 Set Vref, RX VrefLevel [Byte0]: 64
1134 06:51:36.523953 [Byte1]: 64
1135 06:51:36.528107
1136 06:51:36.528632 Set Vref, RX VrefLevel [Byte0]: 65
1137 06:51:36.531692 [Byte1]: 65
1138 06:51:36.535840
1139 06:51:36.536372 Set Vref, RX VrefLevel [Byte0]: 66
1140 06:51:36.539137 [Byte1]: 66
1141 06:51:36.543695
1142 06:51:36.544231 Set Vref, RX VrefLevel [Byte0]: 67
1143 06:51:36.546716 [Byte1]: 67
1144 06:51:36.550999
1145 06:51:36.551525 Set Vref, RX VrefLevel [Byte0]: 68
1146 06:51:36.554153 [Byte1]: 68
1147 06:51:36.558999
1148 06:51:36.559525 Set Vref, RX VrefLevel [Byte0]: 69
1149 06:51:36.562086 [Byte1]: 69
1150 06:51:36.566343
1151 06:51:36.566777 Set Vref, RX VrefLevel [Byte0]: 70
1152 06:51:36.569341 [Byte1]: 70
1153 06:51:36.573754
1154 06:51:36.574187 Set Vref, RX VrefLevel [Byte0]: 71
1155 06:51:36.577543 [Byte1]: 71
1156 06:51:36.581421
1157 06:51:36.581909 Set Vref, RX VrefLevel [Byte0]: 72
1158 06:51:36.584680 [Byte1]: 72
1159 06:51:36.589395
1160 06:51:36.589961 Set Vref, RX VrefLevel [Byte0]: 73
1161 06:51:36.592712 [Byte1]: 73
1162 06:51:36.597074
1163 06:51:36.597653 Set Vref, RX VrefLevel [Byte0]: 74
1164 06:51:36.600685 [Byte1]: 74
1165 06:51:36.604668
1166 06:51:36.605210 Set Vref, RX VrefLevel [Byte0]: 75
1167 06:51:36.608101 [Byte1]: 75
1168 06:51:36.612371
1169 06:51:36.612967 Set Vref, RX VrefLevel [Byte0]: 76
1170 06:51:36.615582 [Byte1]: 76
1171 06:51:36.619665
1172 06:51:36.620206 Set Vref, RX VrefLevel [Byte0]: 77
1173 06:51:36.623026 [Byte1]: 77
1174 06:51:36.627556
1175 06:51:36.628087 Set Vref, RX VrefLevel [Byte0]: 78
1176 06:51:36.630764 [Byte1]: 78
1177 06:51:36.635229
1178 06:51:36.635756 Set Vref, RX VrefLevel [Byte0]: 79
1179 06:51:36.638541 [Byte1]: 79
1180 06:51:36.642815
1181 06:51:36.643339 Set Vref, RX VrefLevel [Byte0]: 80
1182 06:51:36.646228 [Byte1]: 80
1183 06:51:36.650454
1184 06:51:36.650986 Final RX Vref Byte 0 = 59 to rank0
1185 06:51:36.653950 Final RX Vref Byte 1 = 59 to rank0
1186 06:51:36.657298 Final RX Vref Byte 0 = 59 to rank1
1187 06:51:36.660923 Final RX Vref Byte 1 = 59 to rank1==
1188 06:51:36.663506 Dram Type= 6, Freq= 0, CH_0, rank 0
1189 06:51:36.670171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 06:51:36.670696 ==
1191 06:51:36.671044 DQS Delay:
1192 06:51:36.671368 DQS0 = 0, DQS1 = 0
1193 06:51:36.673639 DQM Delay:
1194 06:51:36.674069 DQM0 = 82, DQM1 = 68
1195 06:51:36.677295 DQ Delay:
1196 06:51:36.680481 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1197 06:51:36.681006 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1198 06:51:36.683580 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1199 06:51:36.690441 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =76
1200 06:51:36.690970
1201 06:51:36.691310
1202 06:51:36.696834 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1203 06:51:36.700504 CH0 RK0: MR19=606, MR18=2C2B
1204 06:51:36.706869 CH0_RK0: MR19=0x606, MR18=0x2C2B, DQSOSC=398, MR23=63, INC=93, DEC=62
1205 06:51:36.707398
1206 06:51:36.710469 ----->DramcWriteLeveling(PI) begin...
1207 06:51:36.711003 ==
1208 06:51:36.713786 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 06:51:36.717305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 06:51:36.717889 ==
1211 06:51:36.720486 Write leveling (Byte 0): 31 => 31
1212 06:51:36.723793 Write leveling (Byte 1): 31 => 31
1213 06:51:36.727237 DramcWriteLeveling(PI) end<-----
1214 06:51:36.727769
1215 06:51:36.728108 ==
1216 06:51:36.730531 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 06:51:36.734033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 06:51:36.734566 ==
1219 06:51:36.737342 [Gating] SW mode calibration
1220 06:51:36.744081 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1221 06:51:36.750442 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1222 06:51:36.753710 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 06:51:36.757074 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 06:51:36.763317 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1225 06:51:36.766880 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 06:51:36.770157 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 06:51:36.776756 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 06:51:36.780045 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 06:51:36.783462 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 06:51:36.790210 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 06:51:36.793629 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 06:51:36.796501 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 06:51:36.840775 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 06:51:36.841337 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 06:51:36.841840 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 06:51:36.842265 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 06:51:36.842670 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 06:51:36.843416 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1239 06:51:36.843785 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1240 06:51:36.844193 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1241 06:51:36.844590 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 06:51:36.845084 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 06:51:36.861626 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 06:51:36.862163 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 06:51:36.862613 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 06:51:36.865016 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 06:51:36.865538 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 06:51:36.868455 0 9 8 | B1->B0 | 2323 2c2b | 1 1 | (1 1) (1 1)
1249 06:51:36.871751 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 06:51:36.875009 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 06:51:36.881606 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 06:51:36.885074 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 06:51:36.888484 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 06:51:36.895069 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 06:51:36.898427 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1256 06:51:36.901841 0 10 8 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (1 0)
1257 06:51:36.908945 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 06:51:36.911714 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 06:51:36.914874 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 06:51:36.921670 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 06:51:36.925207 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 06:51:36.928744 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 06:51:36.935325 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1264 06:51:36.938555 0 11 8 | B1->B0 | 2727 3838 | 0 0 | (0 0) (1 1)
1265 06:51:36.942109 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 06:51:36.948842 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 06:51:36.952384 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 06:51:36.955776 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 06:51:36.959686 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 06:51:36.963179 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 06:51:36.970388 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 06:51:36.973720 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1273 06:51:36.977178 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 06:51:36.984607 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 06:51:36.987455 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 06:51:36.991487 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 06:51:36.994339 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 06:51:37.001162 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 06:51:37.004641 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 06:51:37.008239 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 06:51:37.014767 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 06:51:37.018091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 06:51:37.021372 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 06:51:37.024708 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 06:51:37.031564 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 06:51:37.034609 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 06:51:37.038357 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1288 06:51:37.044795 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1289 06:51:37.048243 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 06:51:37.051351 Total UI for P1: 0, mck2ui 16
1291 06:51:37.054919 best dqsien dly found for B0: ( 0, 14, 6)
1292 06:51:37.057980 Total UI for P1: 0, mck2ui 16
1293 06:51:37.061689 best dqsien dly found for B1: ( 0, 14, 10)
1294 06:51:37.064467 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1295 06:51:37.067679 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1296 06:51:37.068134
1297 06:51:37.071225 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1298 06:51:37.074365 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1299 06:51:37.077861 [Gating] SW calibration Done
1300 06:51:37.078387 ==
1301 06:51:37.081210 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 06:51:37.084528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 06:51:37.087689 ==
1304 06:51:37.088114 RX Vref Scan: 0
1305 06:51:37.088457
1306 06:51:37.091415 RX Vref 0 -> 0, step: 1
1307 06:51:37.091943
1308 06:51:37.094419 RX Delay -130 -> 252, step: 16
1309 06:51:37.097676 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1310 06:51:37.101205 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1311 06:51:37.104616 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1312 06:51:37.108220 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1313 06:51:37.114636 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1314 06:51:37.117988 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1315 06:51:37.121169 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1316 06:51:37.124731 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1317 06:51:37.127865 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1318 06:51:37.134533 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1319 06:51:37.138054 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1320 06:51:37.141257 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1321 06:51:37.144618 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1322 06:51:37.148010 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1323 06:51:37.154431 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1324 06:51:37.157784 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1325 06:51:37.158312 ==
1326 06:51:37.161287 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 06:51:37.164688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 06:51:37.165222 ==
1329 06:51:37.167392 DQS Delay:
1330 06:51:37.167816 DQS0 = 0, DQS1 = 0
1331 06:51:37.168153 DQM Delay:
1332 06:51:37.170827 DQM0 = 75, DQM1 = 69
1333 06:51:37.171253 DQ Delay:
1334 06:51:37.174130 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1335 06:51:37.177901 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1336 06:51:37.181366 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1337 06:51:37.184302 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1338 06:51:37.184826
1339 06:51:37.185169
1340 06:51:37.185522 ==
1341 06:51:37.187530 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 06:51:37.194306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 06:51:37.194821 ==
1344 06:51:37.195160
1345 06:51:37.195475
1346 06:51:37.195781 TX Vref Scan disable
1347 06:51:37.197758 == TX Byte 0 ==
1348 06:51:37.201407 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1349 06:51:37.207952 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1350 06:51:37.208483 == TX Byte 1 ==
1351 06:51:37.211402 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1352 06:51:37.217712 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1353 06:51:37.218239 ==
1354 06:51:37.220993 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 06:51:37.224140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 06:51:37.224570 ==
1357 06:51:37.236687 TX Vref=22, minBit 11, minWin=26, winSum=436
1358 06:51:37.239735 TX Vref=24, minBit 11, minWin=26, winSum=437
1359 06:51:37.243223 TX Vref=26, minBit 12, minWin=26, winSum=439
1360 06:51:37.246410 TX Vref=28, minBit 10, minWin=27, winSum=445
1361 06:51:37.249612 TX Vref=30, minBit 11, minWin=26, winSum=439
1362 06:51:37.256433 TX Vref=32, minBit 1, minWin=27, winSum=440
1363 06:51:37.259751 [TxChooseVref] Worse bit 10, Min win 27, Win sum 445, Final Vref 28
1364 06:51:37.260175
1365 06:51:37.263330 Final TX Range 1 Vref 28
1366 06:51:37.263756
1367 06:51:37.264090 ==
1368 06:51:37.266253 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 06:51:37.270079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 06:51:37.272853 ==
1371 06:51:37.273279
1372 06:51:37.273666
1373 06:51:37.273988 TX Vref Scan disable
1374 06:51:37.276610 == TX Byte 0 ==
1375 06:51:37.280094 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1376 06:51:37.283911 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1377 06:51:37.286855 == TX Byte 1 ==
1378 06:51:37.290094 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1379 06:51:37.296869 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1380 06:51:37.297379
1381 06:51:37.297751 [DATLAT]
1382 06:51:37.298064 Freq=800, CH0 RK1
1383 06:51:37.298382
1384 06:51:37.300549 DATLAT Default: 0xa
1385 06:51:37.301420 0, 0xFFFF, sum = 0
1386 06:51:37.303720 1, 0xFFFF, sum = 0
1387 06:51:37.304248 2, 0xFFFF, sum = 0
1388 06:51:37.306901 3, 0xFFFF, sum = 0
1389 06:51:37.307329 4, 0xFFFF, sum = 0
1390 06:51:37.310007 5, 0xFFFF, sum = 0
1391 06:51:37.313354 6, 0xFFFF, sum = 0
1392 06:51:37.314058 7, 0xFFFF, sum = 0
1393 06:51:37.316688 8, 0xFFFF, sum = 0
1394 06:51:37.317202 9, 0x0, sum = 1
1395 06:51:37.317730 10, 0x0, sum = 2
1396 06:51:37.320255 11, 0x0, sum = 3
1397 06:51:37.320824 12, 0x0, sum = 4
1398 06:51:37.323599 best_step = 10
1399 06:51:37.324089
1400 06:51:37.324768 ==
1401 06:51:37.326788 Dram Type= 6, Freq= 0, CH_0, rank 1
1402 06:51:37.330018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 06:51:37.330448 ==
1404 06:51:37.333185 RX Vref Scan: 0
1405 06:51:37.333662
1406 06:51:37.334003 RX Vref 0 -> 0, step: 1
1407 06:51:37.334315
1408 06:51:37.336626 RX Delay -111 -> 252, step: 8
1409 06:51:37.343712 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1410 06:51:37.347031 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1411 06:51:37.350451 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1412 06:51:37.353455 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1413 06:51:37.356805 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1414 06:51:37.363489 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1415 06:51:37.367028 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1416 06:51:37.370060 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1417 06:51:37.373420 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1418 06:51:37.376959 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1419 06:51:37.384360 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1420 06:51:37.386954 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1421 06:51:37.390828 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1422 06:51:37.393865 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1423 06:51:37.397145 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1424 06:51:37.403999 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1425 06:51:37.404525 ==
1426 06:51:37.407142 Dram Type= 6, Freq= 0, CH_0, rank 1
1427 06:51:37.410314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 06:51:37.410737 ==
1429 06:51:37.411072 DQS Delay:
1430 06:51:37.413953 DQS0 = 0, DQS1 = 0
1431 06:51:37.414377 DQM Delay:
1432 06:51:37.417278 DQM0 = 79, DQM1 = 70
1433 06:51:37.417842 DQ Delay:
1434 06:51:37.420489 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1435 06:51:37.423984 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1436 06:51:37.427367 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1437 06:51:37.430424 DQ12 =80, DQ13 =72, DQ14 =80, DQ15 =76
1438 06:51:37.430955
1439 06:51:37.431296
1440 06:51:37.437355 [DQSOSCAuto] RK1, (LSB)MR18= 0x4721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1441 06:51:37.440713 CH0 RK1: MR19=606, MR18=4721
1442 06:51:37.447337 CH0_RK1: MR19=0x606, MR18=0x4721, DQSOSC=392, MR23=63, INC=96, DEC=64
1443 06:51:37.450035 [RxdqsGatingPostProcess] freq 800
1444 06:51:37.457243 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1445 06:51:37.460363 Pre-setting of DQS Precalculation
1446 06:51:37.463864 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1447 06:51:37.464423 ==
1448 06:51:37.466936 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 06:51:37.470439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 06:51:37.470868 ==
1451 06:51:37.477080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1452 06:51:37.483422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1453 06:51:37.491978 [CA 0] Center 36 (6~66) winsize 61
1454 06:51:37.495066 [CA 1] Center 36 (6~67) winsize 62
1455 06:51:37.498725 [CA 2] Center 34 (4~64) winsize 61
1456 06:51:37.502141 [CA 3] Center 34 (4~64) winsize 61
1457 06:51:37.505686 [CA 4] Center 34 (5~64) winsize 60
1458 06:51:37.508936 [CA 5] Center 34 (4~64) winsize 61
1459 06:51:37.509690
1460 06:51:37.512290 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1461 06:51:37.512813
1462 06:51:37.514949 [CATrainingPosCal] consider 1 rank data
1463 06:51:37.518846 u2DelayCellTimex100 = 270/100 ps
1464 06:51:37.522478 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1465 06:51:37.525867 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 06:51:37.532293 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 06:51:37.535660 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1468 06:51:37.539020 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
1469 06:51:37.542206 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1470 06:51:37.542746
1471 06:51:37.545542 CA PerBit enable=1, Macro0, CA PI delay=34
1472 06:51:37.546075
1473 06:51:37.548717 [CBTSetCACLKResult] CA Dly = 34
1474 06:51:37.549248 CS Dly: 5 (0~36)
1475 06:51:37.549632 ==
1476 06:51:37.551955 Dram Type= 6, Freq= 0, CH_1, rank 1
1477 06:51:37.558693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 06:51:37.559205 ==
1479 06:51:37.562086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1480 06:51:37.568499 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1481 06:51:37.577867 [CA 0] Center 37 (7~67) winsize 61
1482 06:51:37.581649 [CA 1] Center 36 (6~67) winsize 62
1483 06:51:37.584619 [CA 2] Center 34 (4~65) winsize 62
1484 06:51:37.588047 [CA 3] Center 34 (4~64) winsize 61
1485 06:51:37.591790 [CA 4] Center 34 (4~65) winsize 62
1486 06:51:37.594547 [CA 5] Center 33 (3~64) winsize 62
1487 06:51:37.594977
1488 06:51:37.597830 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1489 06:51:37.598253
1490 06:51:37.601564 [CATrainingPosCal] consider 2 rank data
1491 06:51:37.604501 u2DelayCellTimex100 = 270/100 ps
1492 06:51:37.608026 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1493 06:51:37.611664 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 06:51:37.614948 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1495 06:51:37.618688 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1496 06:51:37.622533 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
1497 06:51:37.625625 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1498 06:51:37.626056
1499 06:51:37.632921 CA PerBit enable=1, Macro0, CA PI delay=34
1500 06:51:37.633446
1501 06:51:37.633821 [CBTSetCACLKResult] CA Dly = 34
1502 06:51:37.636357 CS Dly: 5 (0~37)
1503 06:51:37.636874
1504 06:51:37.640431 ----->DramcWriteLeveling(PI) begin...
1505 06:51:37.640961 ==
1506 06:51:37.643911 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 06:51:37.647529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 06:51:37.648053 ==
1509 06:51:37.651045 Write leveling (Byte 0): 28 => 28
1510 06:51:37.654182 Write leveling (Byte 1): 33 => 33
1511 06:51:37.657690 DramcWriteLeveling(PI) end<-----
1512 06:51:37.658218
1513 06:51:37.658562 ==
1514 06:51:37.661000 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 06:51:37.663929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 06:51:37.664366 ==
1517 06:51:37.667532 [Gating] SW mode calibration
1518 06:51:37.674105 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1519 06:51:37.680616 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1520 06:51:37.684198 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1521 06:51:37.687826 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1522 06:51:37.693926 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1523 06:51:37.697609 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 06:51:37.701001 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 06:51:37.704683 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 06:51:37.710880 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 06:51:37.714159 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 06:51:37.717542 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 06:51:37.724640 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 06:51:37.727470 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 06:51:37.730931 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 06:51:37.737456 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 06:51:37.740648 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 06:51:37.744321 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 06:51:37.751254 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 06:51:37.754363 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 06:51:37.757873 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1538 06:51:37.764444 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1539 06:51:37.767517 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 06:51:37.770975 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 06:51:37.777461 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 06:51:37.780916 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 06:51:37.784430 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 06:51:37.790829 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 06:51:37.794184 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 06:51:37.797460 0 9 8 | B1->B0 | 2727 2929 | 1 0 | (1 1) (1 1)
1547 06:51:37.800953 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 06:51:37.807703 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 06:51:37.811272 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 06:51:37.814592 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 06:51:37.821084 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 06:51:37.824378 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 06:51:37.827706 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 06:51:37.834171 0 10 8 | B1->B0 | 2c2c 2a2a | 1 1 | (1 1) (1 0)
1555 06:51:37.837453 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 06:51:37.841039 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 06:51:37.848013 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 06:51:37.851391 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 06:51:37.854357 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 06:51:37.861006 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 06:51:37.864267 0 11 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1562 06:51:37.867320 0 11 8 | B1->B0 | 3737 3b3b | 0 0 | (0 0) (0 0)
1563 06:51:37.874038 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 06:51:37.877322 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 06:51:37.880879 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 06:51:37.887345 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 06:51:37.890754 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 06:51:37.894217 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 06:51:37.897451 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1570 06:51:37.904589 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1571 06:51:37.907571 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 06:51:37.911082 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 06:51:37.917785 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 06:51:37.921139 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 06:51:37.924523 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 06:51:37.931147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 06:51:37.934523 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 06:51:37.938043 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 06:51:37.944825 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 06:51:37.948129 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 06:51:37.950789 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 06:51:37.957523 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 06:51:37.960752 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 06:51:37.964172 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 06:51:37.970640 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 06:51:37.974097 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 06:51:37.977323 Total UI for P1: 0, mck2ui 16
1588 06:51:37.980695 best dqsien dly found for B0: ( 0, 14, 6)
1589 06:51:37.984113 Total UI for P1: 0, mck2ui 16
1590 06:51:37.987756 best dqsien dly found for B1: ( 0, 14, 6)
1591 06:51:37.991175 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1592 06:51:37.994030 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1593 06:51:37.994456
1594 06:51:37.997720 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1595 06:51:38.000717 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1596 06:51:38.004564 [Gating] SW calibration Done
1597 06:51:38.005133 ==
1598 06:51:38.007531 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 06:51:38.010991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 06:51:38.011540 ==
1601 06:51:38.014276 RX Vref Scan: 0
1602 06:51:38.014800
1603 06:51:38.017355 RX Vref 0 -> 0, step: 1
1604 06:51:38.017865
1605 06:51:38.018205 RX Delay -130 -> 252, step: 16
1606 06:51:38.024602 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1607 06:51:38.027702 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1608 06:51:38.030609 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1609 06:51:38.034204 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1610 06:51:38.037526 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1611 06:51:38.044113 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1612 06:51:38.047582 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1613 06:51:38.050934 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1614 06:51:38.053991 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1615 06:51:38.057583 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1616 06:51:38.064419 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1617 06:51:38.067310 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1618 06:51:38.070578 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1619 06:51:38.074250 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1620 06:51:38.077434 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1621 06:51:38.084378 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1622 06:51:38.084965 ==
1623 06:51:38.087430 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 06:51:38.091123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 06:51:38.091663 ==
1626 06:51:38.092010 DQS Delay:
1627 06:51:38.094191 DQS0 = 0, DQS1 = 0
1628 06:51:38.094618 DQM Delay:
1629 06:51:38.097201 DQM0 = 83, DQM1 = 76
1630 06:51:38.097665 DQ Delay:
1631 06:51:38.100634 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1632 06:51:38.104351 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1633 06:51:38.107477 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1634 06:51:38.111152 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1635 06:51:38.111678
1636 06:51:38.112016
1637 06:51:38.112330 ==
1638 06:51:38.114210 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 06:51:38.117841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 06:51:38.118378 ==
1641 06:51:38.118718
1642 06:51:38.119033
1643 06:51:38.120725 TX Vref Scan disable
1644 06:51:38.124381 == TX Byte 0 ==
1645 06:51:38.127896 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1646 06:51:38.130812 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1647 06:51:38.134022 == TX Byte 1 ==
1648 06:51:38.137920 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1649 06:51:38.140566 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1650 06:51:38.141025 ==
1651 06:51:38.144265 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 06:51:38.150787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 06:51:38.151316 ==
1654 06:51:38.162856 TX Vref=22, minBit 0, minWin=27, winSum=433
1655 06:51:38.165988 TX Vref=24, minBit 1, minWin=27, winSum=442
1656 06:51:38.169362 TX Vref=26, minBit 1, minWin=27, winSum=442
1657 06:51:38.172833 TX Vref=28, minBit 0, minWin=27, winSum=441
1658 06:51:38.176122 TX Vref=30, minBit 0, minWin=27, winSum=448
1659 06:51:38.179362 TX Vref=32, minBit 5, minWin=27, winSum=446
1660 06:51:38.186304 [TxChooseVref] Worse bit 0, Min win 27, Win sum 448, Final Vref 30
1661 06:51:38.186858
1662 06:51:38.189606 Final TX Range 1 Vref 30
1663 06:51:38.190033
1664 06:51:38.190368 ==
1665 06:51:38.192718 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 06:51:38.196692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 06:51:38.197183 ==
1668 06:51:38.197569
1669 06:51:38.197894
1670 06:51:38.200226 TX Vref Scan disable
1671 06:51:38.203794 == TX Byte 0 ==
1672 06:51:38.206963 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1673 06:51:38.210264 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1674 06:51:38.214134 == TX Byte 1 ==
1675 06:51:38.217142 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1676 06:51:38.220758 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1677 06:51:38.221284
1678 06:51:38.223727 [DATLAT]
1679 06:51:38.224249 Freq=800, CH1 RK0
1680 06:51:38.224591
1681 06:51:38.227183 DATLAT Default: 0xa
1682 06:51:38.227709 0, 0xFFFF, sum = 0
1683 06:51:38.230422 1, 0xFFFF, sum = 0
1684 06:51:38.230958 2, 0xFFFF, sum = 0
1685 06:51:38.233923 3, 0xFFFF, sum = 0
1686 06:51:38.234516 4, 0xFFFF, sum = 0
1687 06:51:38.236949 5, 0xFFFF, sum = 0
1688 06:51:38.237520 6, 0xFFFF, sum = 0
1689 06:51:38.240419 7, 0xFFFF, sum = 0
1690 06:51:38.241001 8, 0xFFFF, sum = 0
1691 06:51:38.244080 9, 0x0, sum = 1
1692 06:51:38.244616 10, 0x0, sum = 2
1693 06:51:38.246852 11, 0x0, sum = 3
1694 06:51:38.247343 12, 0x0, sum = 4
1695 06:51:38.247689 best_step = 10
1696 06:51:38.250524
1697 06:51:38.251051 ==
1698 06:51:38.254110 Dram Type= 6, Freq= 0, CH_1, rank 0
1699 06:51:38.257112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1700 06:51:38.257698 ==
1701 06:51:38.258048 RX Vref Scan: 1
1702 06:51:38.258363
1703 06:51:38.260380 Set Vref Range= 32 -> 127
1704 06:51:38.260801
1705 06:51:38.263883 RX Vref 32 -> 127, step: 1
1706 06:51:38.264522
1707 06:51:38.267057 RX Delay -111 -> 252, step: 8
1708 06:51:38.267480
1709 06:51:38.270377 Set Vref, RX VrefLevel [Byte0]: 32
1710 06:51:38.273829 [Byte1]: 32
1711 06:51:38.274255
1712 06:51:38.276917 Set Vref, RX VrefLevel [Byte0]: 33
1713 06:51:38.280251 [Byte1]: 33
1714 06:51:38.280676
1715 06:51:38.284096 Set Vref, RX VrefLevel [Byte0]: 34
1716 06:51:38.286829 [Byte1]: 34
1717 06:51:38.290670
1718 06:51:38.291089 Set Vref, RX VrefLevel [Byte0]: 35
1719 06:51:38.294091 [Byte1]: 35
1720 06:51:38.298416
1721 06:51:38.298840 Set Vref, RX VrefLevel [Byte0]: 36
1722 06:51:38.301812 [Byte1]: 36
1723 06:51:38.306318
1724 06:51:38.306738 Set Vref, RX VrefLevel [Byte0]: 37
1725 06:51:38.309242 [Byte1]: 37
1726 06:51:38.314175
1727 06:51:38.314703 Set Vref, RX VrefLevel [Byte0]: 38
1728 06:51:38.317513 [Byte1]: 38
1729 06:51:38.321618
1730 06:51:38.322267 Set Vref, RX VrefLevel [Byte0]: 39
1731 06:51:38.324521 [Byte1]: 39
1732 06:51:38.329166
1733 06:51:38.329895 Set Vref, RX VrefLevel [Byte0]: 40
1734 06:51:38.332591 [Byte1]: 40
1735 06:51:38.337055
1736 06:51:38.337626 Set Vref, RX VrefLevel [Byte0]: 41
1737 06:51:38.340069 [Byte1]: 41
1738 06:51:38.344256
1739 06:51:38.344800 Set Vref, RX VrefLevel [Byte0]: 42
1740 06:51:38.347524 [Byte1]: 42
1741 06:51:38.351928
1742 06:51:38.352360 Set Vref, RX VrefLevel [Byte0]: 43
1743 06:51:38.355373 [Byte1]: 43
1744 06:51:38.359821
1745 06:51:38.360444 Set Vref, RX VrefLevel [Byte0]: 44
1746 06:51:38.362761 [Byte1]: 44
1747 06:51:38.366937
1748 06:51:38.367360 Set Vref, RX VrefLevel [Byte0]: 45
1749 06:51:38.370575 [Byte1]: 45
1750 06:51:38.374735
1751 06:51:38.375158 Set Vref, RX VrefLevel [Byte0]: 46
1752 06:51:38.377886 [Byte1]: 46
1753 06:51:38.382327
1754 06:51:38.382764 Set Vref, RX VrefLevel [Byte0]: 47
1755 06:51:38.385523 [Byte1]: 47
1756 06:51:38.390313
1757 06:51:38.390838 Set Vref, RX VrefLevel [Byte0]: 48
1758 06:51:38.393571 [Byte1]: 48
1759 06:51:38.397781
1760 06:51:38.398233 Set Vref, RX VrefLevel [Byte0]: 49
1761 06:51:38.400992 [Byte1]: 49
1762 06:51:38.405319
1763 06:51:38.406014 Set Vref, RX VrefLevel [Byte0]: 50
1764 06:51:38.408560 [Byte1]: 50
1765 06:51:38.413223
1766 06:51:38.413703 Set Vref, RX VrefLevel [Byte0]: 51
1767 06:51:38.416338 [Byte1]: 51
1768 06:51:38.420950
1769 06:51:38.421717 Set Vref, RX VrefLevel [Byte0]: 52
1770 06:51:38.424093 [Byte1]: 52
1771 06:51:38.428368
1772 06:51:38.428792 Set Vref, RX VrefLevel [Byte0]: 53
1773 06:51:38.431636 [Byte1]: 53
1774 06:51:38.435858
1775 06:51:38.436371 Set Vref, RX VrefLevel [Byte0]: 54
1776 06:51:38.439085 [Byte1]: 54
1777 06:51:38.443417
1778 06:51:38.443840 Set Vref, RX VrefLevel [Byte0]: 55
1779 06:51:38.447020 [Byte1]: 55
1780 06:51:38.451260
1781 06:51:38.451683 Set Vref, RX VrefLevel [Byte0]: 56
1782 06:51:38.454470 [Byte1]: 56
1783 06:51:38.459060
1784 06:51:38.459752 Set Vref, RX VrefLevel [Byte0]: 57
1785 06:51:38.462187 [Byte1]: 57
1786 06:51:38.466263
1787 06:51:38.466885 Set Vref, RX VrefLevel [Byte0]: 58
1788 06:51:38.469893 [Byte1]: 58
1789 06:51:38.474189
1790 06:51:38.474645 Set Vref, RX VrefLevel [Byte0]: 59
1791 06:51:38.477578 [Byte1]: 59
1792 06:51:38.481861
1793 06:51:38.482284 Set Vref, RX VrefLevel [Byte0]: 60
1794 06:51:38.485346 [Byte1]: 60
1795 06:51:38.489412
1796 06:51:38.489900 Set Vref, RX VrefLevel [Byte0]: 61
1797 06:51:38.492655 [Byte1]: 61
1798 06:51:38.497033
1799 06:51:38.497616 Set Vref, RX VrefLevel [Byte0]: 62
1800 06:51:38.500525 [Byte1]: 62
1801 06:51:38.505166
1802 06:51:38.505744 Set Vref, RX VrefLevel [Byte0]: 63
1803 06:51:38.508259 [Byte1]: 63
1804 06:51:38.512694
1805 06:51:38.513236 Set Vref, RX VrefLevel [Byte0]: 64
1806 06:51:38.515898 [Byte1]: 64
1807 06:51:38.520005
1808 06:51:38.520526 Set Vref, RX VrefLevel [Byte0]: 65
1809 06:51:38.523630 [Byte1]: 65
1810 06:51:38.528107
1811 06:51:38.528639 Set Vref, RX VrefLevel [Byte0]: 66
1812 06:51:38.531236 [Byte1]: 66
1813 06:51:38.535718
1814 06:51:38.536246 Set Vref, RX VrefLevel [Byte0]: 67
1815 06:51:38.539157 [Byte1]: 67
1816 06:51:38.543267
1817 06:51:38.543793 Set Vref, RX VrefLevel [Byte0]: 68
1818 06:51:38.546325 [Byte1]: 68
1819 06:51:38.550850
1820 06:51:38.551392 Set Vref, RX VrefLevel [Byte0]: 69
1821 06:51:38.554000 [Byte1]: 69
1822 06:51:38.558357
1823 06:51:38.558888 Set Vref, RX VrefLevel [Byte0]: 70
1824 06:51:38.561983 [Byte1]: 70
1825 06:51:38.566081
1826 06:51:38.566604 Set Vref, RX VrefLevel [Byte0]: 71
1827 06:51:38.569204 [Byte1]: 71
1828 06:51:38.573798
1829 06:51:38.574340 Set Vref, RX VrefLevel [Byte0]: 72
1830 06:51:38.577045 [Byte1]: 72
1831 06:51:38.581419
1832 06:51:38.581890 Set Vref, RX VrefLevel [Byte0]: 73
1833 06:51:38.584839 [Byte1]: 73
1834 06:51:38.589388
1835 06:51:38.589969 Final RX Vref Byte 0 = 61 to rank0
1836 06:51:38.592452 Final RX Vref Byte 1 = 55 to rank0
1837 06:51:38.595954 Final RX Vref Byte 0 = 61 to rank1
1838 06:51:38.599050 Final RX Vref Byte 1 = 55 to rank1==
1839 06:51:38.602156 Dram Type= 6, Freq= 0, CH_1, rank 0
1840 06:51:38.609084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 06:51:38.609640 ==
1842 06:51:38.610008 DQS Delay:
1843 06:51:38.610347 DQS0 = 0, DQS1 = 0
1844 06:51:38.612463 DQM Delay:
1845 06:51:38.612998 DQM0 = 81, DQM1 = 72
1846 06:51:38.615635 DQ Delay:
1847 06:51:38.619425 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1848 06:51:38.619956 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1849 06:51:38.622476 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1850 06:51:38.625851 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1851 06:51:38.629366
1852 06:51:38.629940
1853 06:51:38.635809 [DQSOSCAuto] RK0, (LSB)MR18= 0x1721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1854 06:51:38.639187 CH1 RK0: MR19=606, MR18=1721
1855 06:51:38.645146 CH1_RK0: MR19=0x606, MR18=0x1721, DQSOSC=401, MR23=63, INC=91, DEC=61
1856 06:51:38.645233
1857 06:51:38.648474 ----->DramcWriteLeveling(PI) begin...
1858 06:51:38.648559 ==
1859 06:51:38.651882 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 06:51:38.655349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 06:51:38.655438 ==
1862 06:51:38.658702 Write leveling (Byte 0): 25 => 25
1863 06:51:38.661821 Write leveling (Byte 1): 31 => 31
1864 06:51:38.665286 DramcWriteLeveling(PI) end<-----
1865 06:51:38.665514
1866 06:51:38.665618 ==
1867 06:51:38.668708 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 06:51:38.671898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 06:51:38.672033 ==
1870 06:51:38.675333 [Gating] SW mode calibration
1871 06:51:38.681742 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1872 06:51:38.689041 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1873 06:51:38.692566 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1874 06:51:38.695583 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1875 06:51:38.702131 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 06:51:38.705606 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 06:51:38.708673 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 06:51:38.715580 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 06:51:38.718950 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 06:51:38.722121 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 06:51:38.728908 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 06:51:38.732643 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 06:51:38.735677 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 06:51:38.742433 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 06:51:38.745823 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 06:51:38.749082 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 06:51:38.755779 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 06:51:38.758948 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 06:51:38.761798 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1890 06:51:38.765945 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1891 06:51:38.771767 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 06:51:38.775328 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 06:51:38.778832 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 06:51:38.785580 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 06:51:38.788584 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 06:51:38.792066 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 06:51:38.798663 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 06:51:38.802090 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
1899 06:51:38.805741 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
1900 06:51:38.812775 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 06:51:38.815421 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 06:51:38.818986 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 06:51:38.825625 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 06:51:38.828707 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 06:51:38.832547 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 06:51:38.839111 0 10 4 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 0)
1907 06:51:38.841866 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 06:51:38.845589 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 06:51:38.852191 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 06:51:38.855593 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 06:51:38.858888 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 06:51:38.862063 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 06:51:38.868997 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 06:51:38.872173 0 11 4 | B1->B0 | 2828 3939 | 0 1 | (0 0) (0 0)
1915 06:51:38.875112 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1916 06:51:38.881890 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 06:51:38.885471 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 06:51:38.888368 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 06:51:38.895383 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 06:51:38.898601 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 06:51:38.901854 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 06:51:38.908995 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1923 06:51:38.911953 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 06:51:38.915338 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 06:51:38.921792 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 06:51:38.925617 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 06:51:38.928567 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 06:51:38.935674 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 06:51:38.938607 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 06:51:38.941825 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 06:51:38.948828 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 06:51:38.951715 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 06:51:38.955277 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 06:51:38.961741 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 06:51:38.965234 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 06:51:38.968593 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 06:51:38.974978 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1938 06:51:38.978513 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1939 06:51:38.981913 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1940 06:51:38.988219 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 06:51:38.988653 Total UI for P1: 0, mck2ui 16
1942 06:51:38.991778 best dqsien dly found for B0: ( 0, 14, 4)
1943 06:51:38.995493 Total UI for P1: 0, mck2ui 16
1944 06:51:38.998155 best dqsien dly found for B1: ( 0, 14, 8)
1945 06:51:39.001687 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1946 06:51:39.008632 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1947 06:51:39.009163
1948 06:51:39.011890 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1949 06:51:39.014995 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1950 06:51:39.018356 [Gating] SW calibration Done
1951 06:51:39.018883 ==
1952 06:51:39.021640 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 06:51:39.025073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 06:51:39.025645 ==
1955 06:51:39.025995 RX Vref Scan: 0
1956 06:51:39.028193
1957 06:51:39.028613 RX Vref 0 -> 0, step: 1
1958 06:51:39.028948
1959 06:51:39.031756 RX Delay -130 -> 252, step: 16
1960 06:51:39.034631 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1961 06:51:39.038221 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1962 06:51:39.044698 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1963 06:51:39.047837 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1964 06:51:39.051461 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1965 06:51:39.054764 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1966 06:51:39.058406 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1967 06:51:39.064903 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1968 06:51:39.068392 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1969 06:51:39.071097 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1970 06:51:39.074794 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1971 06:51:39.078386 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1972 06:51:39.084834 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1973 06:51:39.088445 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1974 06:51:39.091633 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1975 06:51:39.094801 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1976 06:51:39.095328 ==
1977 06:51:39.098304 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 06:51:39.104968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 06:51:39.105542 ==
1980 06:51:39.105895 DQS Delay:
1981 06:51:39.108382 DQS0 = 0, DQS1 = 0
1982 06:51:39.108908 DQM Delay:
1983 06:51:39.109247 DQM0 = 78, DQM1 = 76
1984 06:51:39.111120 DQ Delay:
1985 06:51:39.114722 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1986 06:51:39.118246 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1987 06:51:39.121638 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =61
1988 06:51:39.125062 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1989 06:51:39.125644
1990 06:51:39.125994
1991 06:51:39.126306 ==
1992 06:51:39.128334 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 06:51:39.131721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 06:51:39.132254 ==
1995 06:51:39.132597
1996 06:51:39.132903
1997 06:51:39.134464 TX Vref Scan disable
1998 06:51:39.134889 == TX Byte 0 ==
1999 06:51:39.141088 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2000 06:51:39.144840 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2001 06:51:39.145364 == TX Byte 1 ==
2002 06:51:39.151414 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2003 06:51:39.154932 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2004 06:51:39.155462 ==
2005 06:51:39.157772 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 06:51:39.160992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 06:51:39.161417 ==
2008 06:51:39.175453 TX Vref=22, minBit 9, minWin=27, winSum=454
2009 06:51:39.178734 TX Vref=24, minBit 2, minWin=28, winSum=457
2010 06:51:39.182346 TX Vref=26, minBit 2, minWin=28, winSum=460
2011 06:51:39.185377 TX Vref=28, minBit 10, minWin=28, winSum=464
2012 06:51:39.188809 TX Vref=30, minBit 1, minWin=28, winSum=466
2013 06:51:39.195388 TX Vref=32, minBit 1, minWin=28, winSum=462
2014 06:51:39.198750 [TxChooseVref] Worse bit 1, Min win 28, Win sum 466, Final Vref 30
2015 06:51:39.199183
2016 06:51:39.202097 Final TX Range 1 Vref 30
2017 06:51:39.202520
2018 06:51:39.202936 ==
2019 06:51:39.205076 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 06:51:39.208911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 06:51:39.211921 ==
2022 06:51:39.212438
2023 06:51:39.212812
2024 06:51:39.213137 TX Vref Scan disable
2025 06:51:39.216013 == TX Byte 0 ==
2026 06:51:39.219536 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2027 06:51:39.222993 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2028 06:51:39.226087 == TX Byte 1 ==
2029 06:51:39.229436 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2030 06:51:39.232803 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2031 06:51:39.235614
2032 06:51:39.236058 [DATLAT]
2033 06:51:39.236399 Freq=800, CH1 RK1
2034 06:51:39.236717
2035 06:51:39.239241 DATLAT Default: 0xa
2036 06:51:39.239694 0, 0xFFFF, sum = 0
2037 06:51:39.242199 1, 0xFFFF, sum = 0
2038 06:51:39.242631 2, 0xFFFF, sum = 0
2039 06:51:39.245918 3, 0xFFFF, sum = 0
2040 06:51:39.246345 4, 0xFFFF, sum = 0
2041 06:51:39.249063 5, 0xFFFF, sum = 0
2042 06:51:39.253003 6, 0xFFFF, sum = 0
2043 06:51:39.253574 7, 0xFFFF, sum = 0
2044 06:51:39.256049 8, 0xFFFF, sum = 0
2045 06:51:39.256689 9, 0x0, sum = 1
2046 06:51:39.257054 10, 0x0, sum = 2
2047 06:51:39.259200 11, 0x0, sum = 3
2048 06:51:39.259730 12, 0x0, sum = 4
2049 06:51:39.262257 best_step = 10
2050 06:51:39.262712
2051 06:51:39.263051 ==
2052 06:51:39.266085 Dram Type= 6, Freq= 0, CH_1, rank 1
2053 06:51:39.269270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2054 06:51:39.269747 ==
2055 06:51:39.272684 RX Vref Scan: 0
2056 06:51:39.273105
2057 06:51:39.273438 RX Vref 0 -> 0, step: 1
2058 06:51:39.273806
2059 06:51:39.275917 RX Delay -111 -> 252, step: 8
2060 06:51:39.282818 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2061 06:51:39.285943 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2062 06:51:39.289223 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2063 06:51:39.292541 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2064 06:51:39.296142 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2065 06:51:39.302507 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2066 06:51:39.306035 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2067 06:51:39.309674 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2068 06:51:39.312968 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2069 06:51:39.316281 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2070 06:51:39.322858 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2071 06:51:39.326304 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2072 06:51:39.329519 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2073 06:51:39.332828 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2074 06:51:39.335919 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2075 06:51:39.342545 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2076 06:51:39.343069 ==
2077 06:51:39.346172 Dram Type= 6, Freq= 0, CH_1, rank 1
2078 06:51:39.349630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2079 06:51:39.350160 ==
2080 06:51:39.350507 DQS Delay:
2081 06:51:39.352790 DQS0 = 0, DQS1 = 0
2082 06:51:39.353310 DQM Delay:
2083 06:51:39.356216 DQM0 = 78, DQM1 = 73
2084 06:51:39.356740 DQ Delay:
2085 06:51:39.359601 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2086 06:51:39.362578 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2087 06:51:39.366069 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2088 06:51:39.369310 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2089 06:51:39.369831
2090 06:51:39.370170
2091 06:51:39.375722 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2092 06:51:39.379093 CH1 RK1: MR19=606, MR18=2139
2093 06:51:39.386058 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2094 06:51:39.389158 [RxdqsGatingPostProcess] freq 800
2095 06:51:39.396417 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2096 06:51:39.399597 Pre-setting of DQS Precalculation
2097 06:51:39.402416 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2098 06:51:39.409852 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2099 06:51:39.416380 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2100 06:51:39.416907
2101 06:51:39.417249
2102 06:51:39.419566 [Calibration Summary] 1600 Mbps
2103 06:51:39.422846 CH 0, Rank 0
2104 06:51:39.423272 SW Impedance : PASS
2105 06:51:39.425980 DUTY Scan : NO K
2106 06:51:39.429792 ZQ Calibration : PASS
2107 06:51:39.430348 Jitter Meter : NO K
2108 06:51:39.433179 CBT Training : PASS
2109 06:51:39.436160 Write leveling : PASS
2110 06:51:39.436746 RX DQS gating : PASS
2111 06:51:39.439459 RX DQ/DQS(RDDQC) : PASS
2112 06:51:39.439991 TX DQ/DQS : PASS
2113 06:51:39.442893 RX DATLAT : PASS
2114 06:51:39.446253 RX DQ/DQS(Engine): PASS
2115 06:51:39.446783 TX OE : NO K
2116 06:51:39.449694 All Pass.
2117 06:51:39.450214
2118 06:51:39.450556 CH 0, Rank 1
2119 06:51:39.452857 SW Impedance : PASS
2120 06:51:39.453386 DUTY Scan : NO K
2121 06:51:39.456147 ZQ Calibration : PASS
2122 06:51:39.459438 Jitter Meter : NO K
2123 06:51:39.459971 CBT Training : PASS
2124 06:51:39.463032 Write leveling : PASS
2125 06:51:39.465956 RX DQS gating : PASS
2126 06:51:39.466436 RX DQ/DQS(RDDQC) : PASS
2127 06:51:39.469544 TX DQ/DQS : PASS
2128 06:51:39.472685 RX DATLAT : PASS
2129 06:51:39.473111 RX DQ/DQS(Engine): PASS
2130 06:51:39.476121 TX OE : NO K
2131 06:51:39.476544 All Pass.
2132 06:51:39.476880
2133 06:51:39.479471 CH 1, Rank 0
2134 06:51:39.479922 SW Impedance : PASS
2135 06:51:39.482611 DUTY Scan : NO K
2136 06:51:39.483035 ZQ Calibration : PASS
2137 06:51:39.485970 Jitter Meter : NO K
2138 06:51:39.489526 CBT Training : PASS
2139 06:51:39.489958 Write leveling : PASS
2140 06:51:39.492664 RX DQS gating : PASS
2141 06:51:39.496356 RX DQ/DQS(RDDQC) : PASS
2142 06:51:39.496884 TX DQ/DQS : PASS
2143 06:51:39.499377 RX DATLAT : PASS
2144 06:51:39.502735 RX DQ/DQS(Engine): PASS
2145 06:51:39.503522 TX OE : NO K
2146 06:51:39.505862 All Pass.
2147 06:51:39.506453
2148 06:51:39.506806 CH 1, Rank 1
2149 06:51:39.509209 SW Impedance : PASS
2150 06:51:39.509754 DUTY Scan : NO K
2151 06:51:39.512559 ZQ Calibration : PASS
2152 06:51:39.515958 Jitter Meter : NO K
2153 06:51:39.516413 CBT Training : PASS
2154 06:51:39.519281 Write leveling : PASS
2155 06:51:39.522472 RX DQS gating : PASS
2156 06:51:39.522994 RX DQ/DQS(RDDQC) : PASS
2157 06:51:39.526229 TX DQ/DQS : PASS
2158 06:51:39.526670 RX DATLAT : PASS
2159 06:51:39.529519 RX DQ/DQS(Engine): PASS
2160 06:51:39.532853 TX OE : NO K
2161 06:51:39.533276 All Pass.
2162 06:51:39.533659
2163 06:51:39.536082 DramC Write-DBI off
2164 06:51:39.536504 PER_BANK_REFRESH: Hybrid Mode
2165 06:51:39.539508 TX_TRACKING: ON
2166 06:51:39.542970 [GetDramInforAfterCalByMRR] Vendor 6.
2167 06:51:39.545916 [GetDramInforAfterCalByMRR] Revision 606.
2168 06:51:39.549584 [GetDramInforAfterCalByMRR] Revision 2 0.
2169 06:51:39.550244 MR0 0x3b3b
2170 06:51:39.552441 MR8 0x5151
2171 06:51:39.555835 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2172 06:51:39.556467
2173 06:51:39.557068 MR0 0x3b3b
2174 06:51:39.559217 MR8 0x5151
2175 06:51:39.562698 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2176 06:51:39.563125
2177 06:51:39.569338 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2178 06:51:39.572762 [FAST_K] Save calibration result to emmc
2179 06:51:39.579170 [FAST_K] Save calibration result to emmc
2180 06:51:39.579594 dram_init: config_dvfs: 1
2181 06:51:39.582604 dramc_set_vcore_voltage set vcore to 662500
2182 06:51:39.585991 Read voltage for 1200, 2
2183 06:51:39.586604 Vio18 = 0
2184 06:51:39.589333 Vcore = 662500
2185 06:51:39.589836 Vdram = 0
2186 06:51:39.590181 Vddq = 0
2187 06:51:39.592543 Vmddr = 0
2188 06:51:39.596442 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2189 06:51:39.602595 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2190 06:51:39.603035 MEM_TYPE=3, freq_sel=15
2191 06:51:39.605939 sv_algorithm_assistance_LP4_1600
2192 06:51:39.612945 ============ PULL DRAM RESETB DOWN ============
2193 06:51:39.616266 ========== PULL DRAM RESETB DOWN end =========
2194 06:51:39.619349 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2195 06:51:39.622490 ===================================
2196 06:51:39.626100 LPDDR4 DRAM CONFIGURATION
2197 06:51:39.629404 ===================================
2198 06:51:39.629997 EX_ROW_EN[0] = 0x0
2199 06:51:39.632673 EX_ROW_EN[1] = 0x0
2200 06:51:39.636004 LP4Y_EN = 0x0
2201 06:51:39.636543 WORK_FSP = 0x0
2202 06:51:39.639127 WL = 0x4
2203 06:51:39.639559 RL = 0x4
2204 06:51:39.642698 BL = 0x2
2205 06:51:39.643241 RPST = 0x0
2206 06:51:39.645787 RD_PRE = 0x0
2207 06:51:39.646221 WR_PRE = 0x1
2208 06:51:39.648995 WR_PST = 0x0
2209 06:51:39.649422 DBI_WR = 0x0
2210 06:51:39.652584 DBI_RD = 0x0
2211 06:51:39.653119 OTF = 0x1
2212 06:51:39.656227 ===================================
2213 06:51:39.659369 ===================================
2214 06:51:39.662182 ANA top config
2215 06:51:39.666033 ===================================
2216 06:51:39.666580 DLL_ASYNC_EN = 0
2217 06:51:39.668922 ALL_SLAVE_EN = 0
2218 06:51:39.672340 NEW_RANK_MODE = 1
2219 06:51:39.675959 DLL_IDLE_MODE = 1
2220 06:51:39.679157 LP45_APHY_COMB_EN = 1
2221 06:51:39.679710 TX_ODT_DIS = 1
2222 06:51:39.682452 NEW_8X_MODE = 1
2223 06:51:39.685732 ===================================
2224 06:51:39.689039 ===================================
2225 06:51:39.692536 data_rate = 2400
2226 06:51:39.695416 CKR = 1
2227 06:51:39.698927 DQ_P2S_RATIO = 8
2228 06:51:39.702331 ===================================
2229 06:51:39.702773 CA_P2S_RATIO = 8
2230 06:51:39.705736 DQ_CA_OPEN = 0
2231 06:51:39.709123 DQ_SEMI_OPEN = 0
2232 06:51:39.712502 CA_SEMI_OPEN = 0
2233 06:51:39.715900 CA_FULL_RATE = 0
2234 06:51:39.719102 DQ_CKDIV4_EN = 0
2235 06:51:39.719544 CA_CKDIV4_EN = 0
2236 06:51:39.722366 CA_PREDIV_EN = 0
2237 06:51:39.725555 PH8_DLY = 17
2238 06:51:39.728818 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2239 06:51:39.732528 DQ_AAMCK_DIV = 4
2240 06:51:39.735705 CA_AAMCK_DIV = 4
2241 06:51:39.736140 CA_ADMCK_DIV = 4
2242 06:51:39.738847 DQ_TRACK_CA_EN = 0
2243 06:51:39.742472 CA_PICK = 1200
2244 06:51:39.745991 CA_MCKIO = 1200
2245 06:51:39.749357 MCKIO_SEMI = 0
2246 06:51:39.752416 PLL_FREQ = 2366
2247 06:51:39.755991 DQ_UI_PI_RATIO = 32
2248 06:51:39.756553 CA_UI_PI_RATIO = 0
2249 06:51:39.759074 ===================================
2250 06:51:39.762243 ===================================
2251 06:51:39.766038 memory_type:LPDDR4
2252 06:51:39.768933 GP_NUM : 10
2253 06:51:39.769521 SRAM_EN : 1
2254 06:51:39.772346 MD32_EN : 0
2255 06:51:39.775827 ===================================
2256 06:51:39.779146 [ANA_INIT] >>>>>>>>>>>>>>
2257 06:51:39.782402 <<<<<< [CONFIGURE PHASE]: ANA_TX
2258 06:51:39.785706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2259 06:51:39.788863 ===================================
2260 06:51:39.789296 data_rate = 2400,PCW = 0X5b00
2261 06:51:39.792410 ===================================
2262 06:51:39.796337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2263 06:51:39.802440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2264 06:51:39.809448 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2265 06:51:39.812697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2266 06:51:39.815905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2267 06:51:39.819176 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2268 06:51:39.822405 [ANA_INIT] flow start
2269 06:51:39.822988 [ANA_INIT] PLL >>>>>>>>
2270 06:51:39.825744 [ANA_INIT] PLL <<<<<<<<
2271 06:51:39.829117 [ANA_INIT] MIDPI >>>>>>>>
2272 06:51:39.832831 [ANA_INIT] MIDPI <<<<<<<<
2273 06:51:39.833364 [ANA_INIT] DLL >>>>>>>>
2274 06:51:39.835927 [ANA_INIT] DLL <<<<<<<<
2275 06:51:39.836358 [ANA_INIT] flow end
2276 06:51:39.842347 ============ LP4 DIFF to SE enter ============
2277 06:51:39.846102 ============ LP4 DIFF to SE exit ============
2278 06:51:39.849613 [ANA_INIT] <<<<<<<<<<<<<
2279 06:51:39.852696 [Flow] Enable top DCM control >>>>>
2280 06:51:39.856199 [Flow] Enable top DCM control <<<<<
2281 06:51:39.856739 Enable DLL master slave shuffle
2282 06:51:39.862460 ==============================================================
2283 06:51:39.866278 Gating Mode config
2284 06:51:39.869058 ==============================================================
2285 06:51:39.872471 Config description:
2286 06:51:39.882574 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2287 06:51:39.889075 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2288 06:51:39.892516 SELPH_MODE 0: By rank 1: By Phase
2289 06:51:39.899108 ==============================================================
2290 06:51:39.902568 GAT_TRACK_EN = 1
2291 06:51:39.905750 RX_GATING_MODE = 2
2292 06:51:39.909230 RX_GATING_TRACK_MODE = 2
2293 06:51:39.912488 SELPH_MODE = 1
2294 06:51:39.913016 PICG_EARLY_EN = 1
2295 06:51:39.916255 VALID_LAT_VALUE = 1
2296 06:51:39.922778 ==============================================================
2297 06:51:39.925626 Enter into Gating configuration >>>>
2298 06:51:39.929362 Exit from Gating configuration <<<<
2299 06:51:39.932499 Enter into DVFS_PRE_config >>>>>
2300 06:51:39.942661 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2301 06:51:39.946044 Exit from DVFS_PRE_config <<<<<
2302 06:51:39.949068 Enter into PICG configuration >>>>
2303 06:51:39.952537 Exit from PICG configuration <<<<
2304 06:51:39.955971 [RX_INPUT] configuration >>>>>
2305 06:51:39.959014 [RX_INPUT] configuration <<<<<
2306 06:51:39.962449 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2307 06:51:39.969254 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2308 06:51:39.975342 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 06:51:39.982417 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 06:51:39.985626 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2311 06:51:39.992721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2312 06:51:39.995751 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2313 06:51:40.002359 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2314 06:51:40.005866 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2315 06:51:40.008867 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2316 06:51:40.012257 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2317 06:51:40.019186 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2318 06:51:40.022477 ===================================
2319 06:51:40.025662 LPDDR4 DRAM CONFIGURATION
2320 06:51:40.029223 ===================================
2321 06:51:40.029799 EX_ROW_EN[0] = 0x0
2322 06:51:40.032469 EX_ROW_EN[1] = 0x0
2323 06:51:40.032997 LP4Y_EN = 0x0
2324 06:51:40.035885 WORK_FSP = 0x0
2325 06:51:40.036414 WL = 0x4
2326 06:51:40.039255 RL = 0x4
2327 06:51:40.039971 BL = 0x2
2328 06:51:40.042328 RPST = 0x0
2329 06:51:40.042857 RD_PRE = 0x0
2330 06:51:40.045572 WR_PRE = 0x1
2331 06:51:40.045995 WR_PST = 0x0
2332 06:51:40.048774 DBI_WR = 0x0
2333 06:51:40.049300 DBI_RD = 0x0
2334 06:51:40.052410 OTF = 0x1
2335 06:51:40.055749 ===================================
2336 06:51:40.059021 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2337 06:51:40.062405 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2338 06:51:40.069055 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2339 06:51:40.072121 ===================================
2340 06:51:40.072548 LPDDR4 DRAM CONFIGURATION
2341 06:51:40.075512 ===================================
2342 06:51:40.079122 EX_ROW_EN[0] = 0x10
2343 06:51:40.082434 EX_ROW_EN[1] = 0x0
2344 06:51:40.082964 LP4Y_EN = 0x0
2345 06:51:40.085416 WORK_FSP = 0x0
2346 06:51:40.085869 WL = 0x4
2347 06:51:40.089147 RL = 0x4
2348 06:51:40.089749 BL = 0x2
2349 06:51:40.092149 RPST = 0x0
2350 06:51:40.092577 RD_PRE = 0x0
2351 06:51:40.095700 WR_PRE = 0x1
2352 06:51:40.096229 WR_PST = 0x0
2353 06:51:40.098723 DBI_WR = 0x0
2354 06:51:40.099183 DBI_RD = 0x0
2355 06:51:40.102265 OTF = 0x1
2356 06:51:40.105717 ===================================
2357 06:51:40.112262 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2358 06:51:40.112819 ==
2359 06:51:40.115523 Dram Type= 6, Freq= 0, CH_0, rank 0
2360 06:51:40.118749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 06:51:40.119174 ==
2362 06:51:40.122042 [Duty_Offset_Calibration]
2363 06:51:40.122473 B0:2 B1:0 CA:3
2364 06:51:40.122820
2365 06:51:40.125344 [DutyScan_Calibration_Flow] k_type=0
2366 06:51:40.135466
2367 06:51:40.135931 ==CLK 0==
2368 06:51:40.139058 Final CLK duty delay cell = 0
2369 06:51:40.142400 [0] MAX Duty = 5062%(X100), DQS PI = 12
2370 06:51:40.145436 [0] MIN Duty = 4875%(X100), DQS PI = 58
2371 06:51:40.146014 [0] AVG Duty = 4968%(X100)
2372 06:51:40.146482
2373 06:51:40.148838 CH0 CLK Duty spec in!! Max-Min= 187%
2374 06:51:40.155437 [DutyScan_Calibration_Flow] ====Done====
2375 06:51:40.155949
2376 06:51:40.158492 [DutyScan_Calibration_Flow] k_type=1
2377 06:51:40.174085
2378 06:51:40.174609 ==DQS 0 ==
2379 06:51:40.177375 Final DQS duty delay cell = 0
2380 06:51:40.180337 [0] MAX Duty = 5093%(X100), DQS PI = 28
2381 06:51:40.183991 [0] MIN Duty = 4907%(X100), DQS PI = 2
2382 06:51:40.184524 [0] AVG Duty = 5000%(X100)
2383 06:51:40.187408
2384 06:51:40.187929 ==DQS 1 ==
2385 06:51:40.190522 Final DQS duty delay cell = -4
2386 06:51:40.193922 [-4] MAX Duty = 5000%(X100), DQS PI = 34
2387 06:51:40.197263 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2388 06:51:40.200429 [-4] AVG Duty = 4937%(X100)
2389 06:51:40.200959
2390 06:51:40.203883 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2391 06:51:40.204322
2392 06:51:40.207370 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2393 06:51:40.210367 [DutyScan_Calibration_Flow] ====Done====
2394 06:51:40.210890
2395 06:51:40.213577 [DutyScan_Calibration_Flow] k_type=3
2396 06:51:40.231809
2397 06:51:40.232327 ==DQM 0 ==
2398 06:51:40.234877 Final DQM duty delay cell = 0
2399 06:51:40.238015 [0] MAX Duty = 5124%(X100), DQS PI = 28
2400 06:51:40.241734 [0] MIN Duty = 4876%(X100), DQS PI = 0
2401 06:51:40.242308 [0] AVG Duty = 5000%(X100)
2402 06:51:40.245115
2403 06:51:40.245696 ==DQM 1 ==
2404 06:51:40.248132 Final DQM duty delay cell = 4
2405 06:51:40.251741 [4] MAX Duty = 5124%(X100), DQS PI = 0
2406 06:51:40.254921 [4] MIN Duty = 5031%(X100), DQS PI = 14
2407 06:51:40.255444 [4] AVG Duty = 5077%(X100)
2408 06:51:40.258118
2409 06:51:40.261360 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2410 06:51:40.261934
2411 06:51:40.264530 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2412 06:51:40.267813 [DutyScan_Calibration_Flow] ====Done====
2413 06:51:40.268239
2414 06:51:40.271314 [DutyScan_Calibration_Flow] k_type=2
2415 06:51:40.286348
2416 06:51:40.286885 ==DQ 0 ==
2417 06:51:40.289464 Final DQ duty delay cell = -4
2418 06:51:40.292857 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2419 06:51:40.296380 [-4] MIN Duty = 4907%(X100), DQS PI = 42
2420 06:51:40.299707 [-4] AVG Duty = 4969%(X100)
2421 06:51:40.300241
2422 06:51:40.300586 ==DQ 1 ==
2423 06:51:40.302854 Final DQ duty delay cell = -4
2424 06:51:40.305775 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2425 06:51:40.309269 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2426 06:51:40.313133 [-4] AVG Duty = 4922%(X100)
2427 06:51:40.313704
2428 06:51:40.316228 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2429 06:51:40.316786
2430 06:51:40.319574 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2431 06:51:40.322674 [DutyScan_Calibration_Flow] ====Done====
2432 06:51:40.323125 ==
2433 06:51:40.326140 Dram Type= 6, Freq= 0, CH_1, rank 0
2434 06:51:40.329355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2435 06:51:40.329830 ==
2436 06:51:40.333127 [Duty_Offset_Calibration]
2437 06:51:40.333702 B0:1 B1:-3 CA:0
2438 06:51:40.334047
2439 06:51:40.336100 [DutyScan_Calibration_Flow] k_type=0
2440 06:51:40.346920
2441 06:51:40.347445 ==CLK 0==
2442 06:51:40.350117 Final CLK duty delay cell = 0
2443 06:51:40.353687 [0] MAX Duty = 5031%(X100), DQS PI = 18
2444 06:51:40.357015 [0] MIN Duty = 4844%(X100), DQS PI = 58
2445 06:51:40.357580 [0] AVG Duty = 4937%(X100)
2446 06:51:40.360101
2447 06:51:40.360671 CH1 CLK Duty spec in!! Max-Min= 187%
2448 06:51:40.367026 [DutyScan_Calibration_Flow] ====Done====
2449 06:51:40.367556
2450 06:51:40.369652 [DutyScan_Calibration_Flow] k_type=1
2451 06:51:40.385399
2452 06:51:40.385966 ==DQS 0 ==
2453 06:51:40.388680 Final DQS duty delay cell = -4
2454 06:51:40.391538 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2455 06:51:40.394940 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2456 06:51:40.398522 [-4] AVG Duty = 4969%(X100)
2457 06:51:40.399041
2458 06:51:40.399377 ==DQS 1 ==
2459 06:51:40.402031 Final DQS duty delay cell = 0
2460 06:51:40.405655 [0] MAX Duty = 5094%(X100), DQS PI = 0
2461 06:51:40.408630 [0] MIN Duty = 4875%(X100), DQS PI = 26
2462 06:51:40.412095 [0] AVG Duty = 4984%(X100)
2463 06:51:40.412620
2464 06:51:40.415529 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2465 06:51:40.416055
2466 06:51:40.418781 CH1 DQS 1 Duty spec in!! Max-Min= 219%
2467 06:51:40.421775 [DutyScan_Calibration_Flow] ====Done====
2468 06:51:40.422305
2469 06:51:40.425131 [DutyScan_Calibration_Flow] k_type=3
2470 06:51:40.442782
2471 06:51:40.443308 ==DQM 0 ==
2472 06:51:40.446237 Final DQM duty delay cell = 4
2473 06:51:40.449574 [4] MAX Duty = 5187%(X100), DQS PI = 22
2474 06:51:40.453036 [4] MIN Duty = 5000%(X100), DQS PI = 54
2475 06:51:40.456362 [4] AVG Duty = 5093%(X100)
2476 06:51:40.456890
2477 06:51:40.457227 ==DQM 1 ==
2478 06:51:40.459549 Final DQM duty delay cell = 0
2479 06:51:40.463009 [0] MAX Duty = 5062%(X100), DQS PI = 36
2480 06:51:40.466212 [0] MIN Duty = 4907%(X100), DQS PI = 14
2481 06:51:40.469438 [0] AVG Duty = 4984%(X100)
2482 06:51:40.469900
2483 06:51:40.472516 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2484 06:51:40.472940
2485 06:51:40.475958 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2486 06:51:40.479006 [DutyScan_Calibration_Flow] ====Done====
2487 06:51:40.479430
2488 06:51:40.482398 [DutyScan_Calibration_Flow] k_type=2
2489 06:51:40.499240
2490 06:51:40.499750 ==DQ 0 ==
2491 06:51:40.502510 Final DQ duty delay cell = 0
2492 06:51:40.505761 [0] MAX Duty = 5062%(X100), DQS PI = 18
2493 06:51:40.509466 [0] MIN Duty = 4938%(X100), DQS PI = 54
2494 06:51:40.510054 [0] AVG Duty = 5000%(X100)
2495 06:51:40.512474
2496 06:51:40.512895 ==DQ 1 ==
2497 06:51:40.516099 Final DQ duty delay cell = 0
2498 06:51:40.519481 [0] MAX Duty = 5124%(X100), DQS PI = 34
2499 06:51:40.523011 [0] MIN Duty = 4938%(X100), DQS PI = 26
2500 06:51:40.523540 [0] AVG Duty = 5031%(X100)
2501 06:51:40.523883
2502 06:51:40.526011 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2503 06:51:40.529427
2504 06:51:40.532663 CH1 DQ 1 Duty spec in!! Max-Min= 186%
2505 06:51:40.535833 [DutyScan_Calibration_Flow] ====Done====
2506 06:51:40.539324 nWR fixed to 30
2507 06:51:40.539854 [ModeRegInit_LP4] CH0 RK0
2508 06:51:40.542736 [ModeRegInit_LP4] CH0 RK1
2509 06:51:40.546109 [ModeRegInit_LP4] CH1 RK0
2510 06:51:40.546639 [ModeRegInit_LP4] CH1 RK1
2511 06:51:40.549649 match AC timing 7
2512 06:51:40.552619 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2513 06:51:40.556051 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2514 06:51:40.562835 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2515 06:51:40.565850 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2516 06:51:40.572579 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2517 06:51:40.573112 ==
2518 06:51:40.575716 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 06:51:40.579044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 06:51:40.579469 ==
2521 06:51:40.585527 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2522 06:51:40.588803 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2523 06:51:40.599691 [CA 0] Center 40 (10~71) winsize 62
2524 06:51:40.602295 [CA 1] Center 40 (10~70) winsize 61
2525 06:51:40.605702 [CA 2] Center 36 (6~66) winsize 61
2526 06:51:40.609237 [CA 3] Center 35 (5~66) winsize 62
2527 06:51:40.612558 [CA 4] Center 34 (4~65) winsize 62
2528 06:51:40.615832 [CA 5] Center 33 (3~64) winsize 62
2529 06:51:40.616394
2530 06:51:40.618919 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2531 06:51:40.619385
2532 06:51:40.622361 [CATrainingPosCal] consider 1 rank data
2533 06:51:40.625770 u2DelayCellTimex100 = 270/100 ps
2534 06:51:40.629168 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2535 06:51:40.636193 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2536 06:51:40.639369 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2537 06:51:40.642483 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2538 06:51:40.645783 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2539 06:51:40.649206 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2540 06:51:40.649664
2541 06:51:40.652865 CA PerBit enable=1, Macro0, CA PI delay=33
2542 06:51:40.653294
2543 06:51:40.655779 [CBTSetCACLKResult] CA Dly = 33
2544 06:51:40.656209 CS Dly: 7 (0~38)
2545 06:51:40.659363 ==
2546 06:51:40.663059 Dram Type= 6, Freq= 0, CH_0, rank 1
2547 06:51:40.666023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2548 06:51:40.666465 ==
2549 06:51:40.669674 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2550 06:51:40.675836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2551 06:51:40.685511 [CA 0] Center 40 (10~70) winsize 61
2552 06:51:40.688953 [CA 1] Center 39 (9~70) winsize 62
2553 06:51:40.692112 [CA 2] Center 35 (5~66) winsize 62
2554 06:51:40.695157 [CA 3] Center 35 (5~66) winsize 62
2555 06:51:40.698858 [CA 4] Center 34 (4~65) winsize 62
2556 06:51:40.702248 [CA 5] Center 33 (3~63) winsize 61
2557 06:51:40.702681
2558 06:51:40.705327 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2559 06:51:40.705801
2560 06:51:40.708930 [CATrainingPosCal] consider 2 rank data
2561 06:51:40.712484 u2DelayCellTimex100 = 270/100 ps
2562 06:51:40.715808 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2563 06:51:40.722155 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2564 06:51:40.725327 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2565 06:51:40.729119 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2566 06:51:40.732488 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2567 06:51:40.735452 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2568 06:51:40.735971
2569 06:51:40.738801 CA PerBit enable=1, Macro0, CA PI delay=33
2570 06:51:40.739325
2571 06:51:40.742118 [CBTSetCACLKResult] CA Dly = 33
2572 06:51:40.742657 CS Dly: 8 (0~40)
2573 06:51:40.745591
2574 06:51:40.749020 ----->DramcWriteLeveling(PI) begin...
2575 06:51:40.749589 ==
2576 06:51:40.752351 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 06:51:40.755811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 06:51:40.756337 ==
2579 06:51:40.758802 Write leveling (Byte 0): 33 => 33
2580 06:51:40.762337 Write leveling (Byte 1): 30 => 30
2581 06:51:40.765414 DramcWriteLeveling(PI) end<-----
2582 06:51:40.765886
2583 06:51:40.766227 ==
2584 06:51:40.769277 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 06:51:40.772377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 06:51:40.772898 ==
2587 06:51:40.775445 [Gating] SW mode calibration
2588 06:51:40.782298 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2589 06:51:40.789142 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2590 06:51:40.791914 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 06:51:40.795351 0 15 4 | B1->B0 | 2727 3333 | 1 0 | (0 0) (0 0)
2592 06:51:40.799091 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 06:51:40.805396 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 06:51:40.809144 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 06:51:40.812057 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 06:51:40.819087 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 06:51:40.821999 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2598 06:51:40.825775 1 0 0 | B1->B0 | 3333 2c2c | 1 0 | (1 0) (1 0)
2599 06:51:40.832019 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 06:51:40.835508 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 06:51:40.838748 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 06:51:40.845651 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 06:51:40.849209 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 06:51:40.852331 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 06:51:40.858851 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 06:51:40.862445 1 1 0 | B1->B0 | 2929 3736 | 0 1 | (0 0) (0 0)
2607 06:51:40.865559 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 06:51:40.872377 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 06:51:40.875229 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 06:51:40.878744 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 06:51:40.885293 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 06:51:40.888795 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 06:51:40.891812 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 06:51:40.895376 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2615 06:51:40.902692 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2616 06:51:40.905511 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 06:51:40.908917 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 06:51:40.915561 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 06:51:40.918602 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 06:51:40.922060 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 06:51:40.928754 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 06:51:40.932088 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 06:51:40.935210 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 06:51:40.942387 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 06:51:40.945186 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 06:51:40.948755 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 06:51:40.955632 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 06:51:40.958850 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 06:51:40.962172 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2630 06:51:40.968276 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2631 06:51:40.968808 Total UI for P1: 0, mck2ui 16
2632 06:51:40.975190 best dqsien dly found for B0: ( 1, 3, 28)
2633 06:51:40.978578 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2634 06:51:40.982239 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 06:51:40.985393 Total UI for P1: 0, mck2ui 16
2636 06:51:40.988416 best dqsien dly found for B1: ( 1, 4, 2)
2637 06:51:40.991974 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2638 06:51:40.995097 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2639 06:51:40.995524
2640 06:51:41.001528 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2641 06:51:41.005237 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2642 06:51:41.005844 [Gating] SW calibration Done
2643 06:51:41.008707 ==
2644 06:51:41.009230 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 06:51:41.014854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 06:51:41.015369 ==
2647 06:51:41.015709 RX Vref Scan: 0
2648 06:51:41.016026
2649 06:51:41.018288 RX Vref 0 -> 0, step: 1
2650 06:51:41.018710
2651 06:51:41.021998 RX Delay -40 -> 252, step: 8
2652 06:51:41.025259 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2653 06:51:41.028677 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2654 06:51:41.032080 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2655 06:51:41.038331 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2656 06:51:41.041839 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2657 06:51:41.044978 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2658 06:51:41.048306 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2659 06:51:41.051961 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2660 06:51:41.055165 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2661 06:51:41.061649 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2662 06:51:41.065124 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2663 06:51:41.068921 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2664 06:51:41.071746 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2665 06:51:41.075000 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2666 06:51:41.081863 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2667 06:51:41.085183 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2668 06:51:41.085826 ==
2669 06:51:41.088372 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 06:51:41.092011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 06:51:41.092554 ==
2672 06:51:41.095043 DQS Delay:
2673 06:51:41.095484 DQS0 = 0, DQS1 = 0
2674 06:51:41.095885 DQM Delay:
2675 06:51:41.098474 DQM0 = 112, DQM1 = 104
2676 06:51:41.098985 DQ Delay:
2677 06:51:41.101531 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2678 06:51:41.105469 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2679 06:51:41.108988 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2680 06:51:41.111819 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2681 06:51:41.115285
2682 06:51:41.115898
2683 06:51:41.116398 ==
2684 06:51:41.118391 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 06:51:41.122150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 06:51:41.122679 ==
2687 06:51:41.123026
2688 06:51:41.123343
2689 06:51:41.125614 TX Vref Scan disable
2690 06:51:41.126143 == TX Byte 0 ==
2691 06:51:41.132086 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2692 06:51:41.134924 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2693 06:51:41.135404 == TX Byte 1 ==
2694 06:51:41.142016 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2695 06:51:41.145300 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2696 06:51:41.145885 ==
2697 06:51:41.148721 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 06:51:41.152050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 06:51:41.152602 ==
2700 06:51:41.164321 TX Vref=22, minBit 0, minWin=26, winSum=417
2701 06:51:41.167653 TX Vref=24, minBit 7, minWin=25, winSum=421
2702 06:51:41.170834 TX Vref=26, minBit 2, minWin=26, winSum=426
2703 06:51:41.174278 TX Vref=28, minBit 7, minWin=26, winSum=433
2704 06:51:41.177524 TX Vref=30, minBit 10, minWin=26, winSum=433
2705 06:51:41.184261 TX Vref=32, minBit 2, minWin=26, winSum=429
2706 06:51:41.187711 [TxChooseVref] Worse bit 7, Min win 26, Win sum 433, Final Vref 28
2707 06:51:41.188241
2708 06:51:41.190800 Final TX Range 1 Vref 28
2709 06:51:41.191232
2710 06:51:41.191585 ==
2711 06:51:41.193941 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 06:51:41.197315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 06:51:41.197809 ==
2714 06:51:41.201225
2715 06:51:41.201810
2716 06:51:41.202161 TX Vref Scan disable
2717 06:51:41.204262 == TX Byte 0 ==
2718 06:51:41.207972 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2719 06:51:41.210893 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2720 06:51:41.214472 == TX Byte 1 ==
2721 06:51:41.217851 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2722 06:51:41.221051 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2723 06:51:41.221618
2724 06:51:41.224505 [DATLAT]
2725 06:51:41.225030 Freq=1200, CH0 RK0
2726 06:51:41.225378
2727 06:51:41.227496 DATLAT Default: 0xd
2728 06:51:41.227926 0, 0xFFFF, sum = 0
2729 06:51:41.230903 1, 0xFFFF, sum = 0
2730 06:51:41.231442 2, 0xFFFF, sum = 0
2731 06:51:41.234356 3, 0xFFFF, sum = 0
2732 06:51:41.234795 4, 0xFFFF, sum = 0
2733 06:51:41.237536 5, 0xFFFF, sum = 0
2734 06:51:41.237976 6, 0xFFFF, sum = 0
2735 06:51:41.241020 7, 0xFFFF, sum = 0
2736 06:51:41.244408 8, 0xFFFF, sum = 0
2737 06:51:41.244945 9, 0xFFFF, sum = 0
2738 06:51:41.247908 10, 0xFFFF, sum = 0
2739 06:51:41.248445 11, 0xFFFF, sum = 0
2740 06:51:41.250912 12, 0x0, sum = 1
2741 06:51:41.251345 13, 0x0, sum = 2
2742 06:51:41.254117 14, 0x0, sum = 3
2743 06:51:41.254553 15, 0x0, sum = 4
2744 06:51:41.254898 best_step = 13
2745 06:51:41.255213
2746 06:51:41.257784 ==
2747 06:51:41.261162 Dram Type= 6, Freq= 0, CH_0, rank 0
2748 06:51:41.264403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2749 06:51:41.264935 ==
2750 06:51:41.265285 RX Vref Scan: 1
2751 06:51:41.265660
2752 06:51:41.267350 Set Vref Range= 32 -> 127
2753 06:51:41.267790
2754 06:51:41.270841 RX Vref 32 -> 127, step: 1
2755 06:51:41.271274
2756 06:51:41.274059 RX Delay -37 -> 252, step: 4
2757 06:51:41.274631
2758 06:51:41.277434 Set Vref, RX VrefLevel [Byte0]: 32
2759 06:51:41.280881 [Byte1]: 32
2760 06:51:41.281310
2761 06:51:41.284173 Set Vref, RX VrefLevel [Byte0]: 33
2762 06:51:41.287259 [Byte1]: 33
2763 06:51:41.290763
2764 06:51:41.291191 Set Vref, RX VrefLevel [Byte0]: 34
2765 06:51:41.294171 [Byte1]: 34
2766 06:51:41.298565
2767 06:51:41.298972 Set Vref, RX VrefLevel [Byte0]: 35
2768 06:51:41.302011 [Byte1]: 35
2769 06:51:41.306670
2770 06:51:41.307097 Set Vref, RX VrefLevel [Byte0]: 36
2771 06:51:41.309934 [Byte1]: 36
2772 06:51:41.314433
2773 06:51:41.314859 Set Vref, RX VrefLevel [Byte0]: 37
2774 06:51:41.318183 [Byte1]: 37
2775 06:51:41.322747
2776 06:51:41.323266 Set Vref, RX VrefLevel [Byte0]: 38
2777 06:51:41.326394 [Byte1]: 38
2778 06:51:41.330727
2779 06:51:41.331252 Set Vref, RX VrefLevel [Byte0]: 39
2780 06:51:41.334067 [Byte1]: 39
2781 06:51:41.338714
2782 06:51:41.339241 Set Vref, RX VrefLevel [Byte0]: 40
2783 06:51:41.342186 [Byte1]: 40
2784 06:51:41.346709
2785 06:51:41.347230 Set Vref, RX VrefLevel [Byte0]: 41
2786 06:51:41.350415 [Byte1]: 41
2787 06:51:41.354854
2788 06:51:41.355382 Set Vref, RX VrefLevel [Byte0]: 42
2789 06:51:41.358374 [Byte1]: 42
2790 06:51:41.362790
2791 06:51:41.363323 Set Vref, RX VrefLevel [Byte0]: 43
2792 06:51:41.366369 [Byte1]: 43
2793 06:51:41.370812
2794 06:51:41.371343 Set Vref, RX VrefLevel [Byte0]: 44
2795 06:51:41.374254 [Byte1]: 44
2796 06:51:41.378731
2797 06:51:41.379161 Set Vref, RX VrefLevel [Byte0]: 45
2798 06:51:41.382024 [Byte1]: 45
2799 06:51:41.386788
2800 06:51:41.387300 Set Vref, RX VrefLevel [Byte0]: 46
2801 06:51:41.389786 [Byte1]: 46
2802 06:51:41.394355
2803 06:51:41.394784 Set Vref, RX VrefLevel [Byte0]: 47
2804 06:51:41.398012 [Byte1]: 47
2805 06:51:41.402576
2806 06:51:41.403057 Set Vref, RX VrefLevel [Byte0]: 48
2807 06:51:41.405658 [Byte1]: 48
2808 06:51:41.410868
2809 06:51:41.411408 Set Vref, RX VrefLevel [Byte0]: 49
2810 06:51:41.413849 [Byte1]: 49
2811 06:51:41.419045
2812 06:51:41.419578 Set Vref, RX VrefLevel [Byte0]: 50
2813 06:51:41.421839 [Byte1]: 50
2814 06:51:41.427001
2815 06:51:41.427534 Set Vref, RX VrefLevel [Byte0]: 51
2816 06:51:41.429859 [Byte1]: 51
2817 06:51:41.435012
2818 06:51:41.435548 Set Vref, RX VrefLevel [Byte0]: 52
2819 06:51:41.438117 [Byte1]: 52
2820 06:51:41.442943
2821 06:51:41.443480 Set Vref, RX VrefLevel [Byte0]: 53
2822 06:51:41.445769 [Byte1]: 53
2823 06:51:41.450875
2824 06:51:41.451404 Set Vref, RX VrefLevel [Byte0]: 54
2825 06:51:41.454068 [Byte1]: 54
2826 06:51:41.459055
2827 06:51:41.459581 Set Vref, RX VrefLevel [Byte0]: 55
2828 06:51:41.462123 [Byte1]: 55
2829 06:51:41.466769
2830 06:51:41.467305 Set Vref, RX VrefLevel [Byte0]: 56
2831 06:51:41.469981 [Byte1]: 56
2832 06:51:41.474486
2833 06:51:41.474915 Set Vref, RX VrefLevel [Byte0]: 57
2834 06:51:41.478033 [Byte1]: 57
2835 06:51:41.482563
2836 06:51:41.483163 Set Vref, RX VrefLevel [Byte0]: 58
2837 06:51:41.485842 [Byte1]: 58
2838 06:51:41.490791
2839 06:51:41.491329 Set Vref, RX VrefLevel [Byte0]: 59
2840 06:51:41.493821 [Byte1]: 59
2841 06:51:41.498586
2842 06:51:41.499014 Set Vref, RX VrefLevel [Byte0]: 60
2843 06:51:41.501926 [Byte1]: 60
2844 06:51:41.506626
2845 06:51:41.507052 Set Vref, RX VrefLevel [Byte0]: 61
2846 06:51:41.510116 [Byte1]: 61
2847 06:51:41.514507
2848 06:51:41.514937 Set Vref, RX VrefLevel [Byte0]: 62
2849 06:51:41.517862 [Byte1]: 62
2850 06:51:41.522782
2851 06:51:41.523321 Set Vref, RX VrefLevel [Byte0]: 63
2852 06:51:41.525843 [Byte1]: 63
2853 06:51:41.531090
2854 06:51:41.531623 Set Vref, RX VrefLevel [Byte0]: 64
2855 06:51:41.533801 [Byte1]: 64
2856 06:51:41.538954
2857 06:51:41.539490 Set Vref, RX VrefLevel [Byte0]: 65
2858 06:51:41.541789 [Byte1]: 65
2859 06:51:41.546975
2860 06:51:41.547508 Set Vref, RX VrefLevel [Byte0]: 66
2861 06:51:41.549857 [Byte1]: 66
2862 06:51:41.555160
2863 06:51:41.555712 Set Vref, RX VrefLevel [Byte0]: 67
2864 06:51:41.557802 [Byte1]: 67
2865 06:51:41.562706
2866 06:51:41.563133 Set Vref, RX VrefLevel [Byte0]: 68
2867 06:51:41.566089 [Byte1]: 68
2868 06:51:41.571133
2869 06:51:41.571671 Set Vref, RX VrefLevel [Byte0]: 69
2870 06:51:41.574273 [Byte1]: 69
2871 06:51:41.578528
2872 06:51:41.578956 Set Vref, RX VrefLevel [Byte0]: 70
2873 06:51:41.582305 [Byte1]: 70
2874 06:51:41.586399
2875 06:51:41.586924 Set Vref, RX VrefLevel [Byte0]: 71
2876 06:51:41.590109 [Byte1]: 71
2877 06:51:41.594855
2878 06:51:41.595285 Set Vref, RX VrefLevel [Byte0]: 72
2879 06:51:41.597952 [Byte1]: 72
2880 06:51:41.602772
2881 06:51:41.603355 Set Vref, RX VrefLevel [Byte0]: 73
2882 06:51:41.606052 [Byte1]: 73
2883 06:51:41.611071
2884 06:51:41.611602 Final RX Vref Byte 0 = 61 to rank0
2885 06:51:41.614127 Final RX Vref Byte 1 = 53 to rank0
2886 06:51:41.617665 Final RX Vref Byte 0 = 61 to rank1
2887 06:51:41.621152 Final RX Vref Byte 1 = 53 to rank1==
2888 06:51:41.624444 Dram Type= 6, Freq= 0, CH_0, rank 0
2889 06:51:41.630887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 06:51:41.631430 ==
2891 06:51:41.631777 DQS Delay:
2892 06:51:41.632097 DQS0 = 0, DQS1 = 0
2893 06:51:41.633896 DQM Delay:
2894 06:51:41.634324 DQM0 = 112, DQM1 = 101
2895 06:51:41.637397 DQ Delay:
2896 06:51:41.640785 DQ0 =112, DQ1 =114, DQ2 =110, DQ3 =108
2897 06:51:41.644244 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2898 06:51:41.647705 DQ8 =92, DQ9 =86, DQ10 =104, DQ11 =94
2899 06:51:41.650878 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2900 06:51:41.651416
2901 06:51:41.651759
2902 06:51:41.657604 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2903 06:51:41.660886 CH0 RK0: MR19=303, MR18=FDFC
2904 06:51:41.667662 CH0_RK0: MR19=0x303, MR18=0xFDFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2905 06:51:41.668208
2906 06:51:41.670611 ----->DramcWriteLeveling(PI) begin...
2907 06:51:41.671047 ==
2908 06:51:41.673928 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 06:51:41.677087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 06:51:41.680694 ==
2911 06:51:41.681123 Write leveling (Byte 0): 31 => 31
2912 06:51:41.683845 Write leveling (Byte 1): 31 => 31
2913 06:51:41.687163 DramcWriteLeveling(PI) end<-----
2914 06:51:41.687610
2915 06:51:41.687997 ==
2916 06:51:41.690329 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 06:51:41.697046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 06:51:41.697909 ==
2919 06:51:41.698480 [Gating] SW mode calibration
2920 06:51:41.707085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2921 06:51:41.710436 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2922 06:51:41.714033 0 15 0 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
2923 06:51:41.720679 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 06:51:41.723909 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 06:51:41.727347 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 06:51:41.733847 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 06:51:41.737349 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 06:51:41.740545 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2929 06:51:41.747367 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2930 06:51:41.750632 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 06:51:41.753906 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 06:51:41.761255 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 06:51:41.764184 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 06:51:41.767673 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 06:51:41.774212 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 06:51:41.777337 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2937 06:51:41.780459 1 0 28 | B1->B0 | 2525 4242 | 0 0 | (0 0) (0 0)
2938 06:51:41.787553 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2939 06:51:41.790488 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 06:51:41.794125 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 06:51:41.801028 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 06:51:41.803962 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 06:51:41.807481 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 06:51:41.810784 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2945 06:51:41.817343 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2946 06:51:41.820845 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2947 06:51:41.823744 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 06:51:41.830484 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 06:51:41.834141 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 06:51:41.837890 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 06:51:41.844185 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 06:51:41.847621 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 06:51:41.850843 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 06:51:41.857574 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 06:51:41.860814 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 06:51:41.864239 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 06:51:41.870596 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 06:51:41.874111 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 06:51:41.877212 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 06:51:41.883979 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2961 06:51:41.887460 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2962 06:51:41.890640 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2963 06:51:41.894090 Total UI for P1: 0, mck2ui 16
2964 06:51:41.897634 best dqsien dly found for B0: ( 1, 3, 26)
2965 06:51:41.900913 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 06:51:41.904211 Total UI for P1: 0, mck2ui 16
2967 06:51:41.907425 best dqsien dly found for B1: ( 1, 4, 0)
2968 06:51:41.910693 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2969 06:51:41.914015 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2970 06:51:41.914552
2971 06:51:41.921130 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2972 06:51:41.924204 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2973 06:51:41.924640 [Gating] SW calibration Done
2974 06:51:41.927924 ==
2975 06:51:41.930590 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 06:51:41.934046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 06:51:41.934591 ==
2978 06:51:41.934948 RX Vref Scan: 0
2979 06:51:41.935275
2980 06:51:41.937316 RX Vref 0 -> 0, step: 1
2981 06:51:41.937772
2982 06:51:41.940833 RX Delay -40 -> 252, step: 8
2983 06:51:41.944250 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2984 06:51:41.947907 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2985 06:51:41.951149 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2986 06:51:41.957702 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2987 06:51:41.961068 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2988 06:51:41.964140 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2989 06:51:41.967321 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2990 06:51:41.971019 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2991 06:51:41.977270 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2992 06:51:41.980910 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2993 06:51:41.984252 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2994 06:51:41.987797 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2995 06:51:41.990899 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2996 06:51:41.997318 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2997 06:51:42.000684 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2998 06:51:42.004450 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2999 06:51:42.004995 ==
3000 06:51:42.007781 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 06:51:42.010475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 06:51:42.010927 ==
3003 06:51:42.013916 DQS Delay:
3004 06:51:42.014360 DQS0 = 0, DQS1 = 0
3005 06:51:42.017864 DQM Delay:
3006 06:51:42.018399 DQM0 = 112, DQM1 = 101
3007 06:51:42.018855 DQ Delay:
3008 06:51:42.020480 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3009 06:51:42.027862 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
3010 06:51:42.030793 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3011 06:51:42.034374 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
3012 06:51:42.035019
3013 06:51:42.035368
3014 06:51:42.035684 ==
3015 06:51:42.037161 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 06:51:42.040874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 06:51:42.041414 ==
3018 06:51:42.041818
3019 06:51:42.042141
3020 06:51:42.044516 TX Vref Scan disable
3021 06:51:42.045164 == TX Byte 0 ==
3022 06:51:42.051021 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3023 06:51:42.053986 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3024 06:51:42.054429 == TX Byte 1 ==
3025 06:51:42.060853 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3026 06:51:42.064000 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3027 06:51:42.064532 ==
3028 06:51:42.067309 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 06:51:42.070694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 06:51:42.071124 ==
3031 06:51:42.083479 TX Vref=22, minBit 1, minWin=26, winSum=427
3032 06:51:42.086854 TX Vref=24, minBit 0, minWin=26, winSum=430
3033 06:51:42.089935 TX Vref=26, minBit 4, minWin=26, winSum=434
3034 06:51:42.093709 TX Vref=28, minBit 5, minWin=26, winSum=442
3035 06:51:42.096856 TX Vref=30, minBit 5, minWin=26, winSum=438
3036 06:51:42.103407 TX Vref=32, minBit 5, minWin=26, winSum=438
3037 06:51:42.106664 [TxChooseVref] Worse bit 5, Min win 26, Win sum 442, Final Vref 28
3038 06:51:42.107101
3039 06:51:42.110158 Final TX Range 1 Vref 28
3040 06:51:42.110698
3041 06:51:42.111040 ==
3042 06:51:42.113590 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 06:51:42.116855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 06:51:42.117286 ==
3045 06:51:42.117745
3046 06:51:42.120594
3047 06:51:42.121130 TX Vref Scan disable
3048 06:51:42.123552 == TX Byte 0 ==
3049 06:51:42.126905 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3050 06:51:42.130017 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3051 06:51:42.133658 == TX Byte 1 ==
3052 06:51:42.137114 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3053 06:51:42.140363 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3054 06:51:42.140897
3055 06:51:42.143387 [DATLAT]
3056 06:51:42.143922 Freq=1200, CH0 RK1
3057 06:51:42.144267
3058 06:51:42.146812 DATLAT Default: 0xd
3059 06:51:42.147416 0, 0xFFFF, sum = 0
3060 06:51:42.150006 1, 0xFFFF, sum = 0
3061 06:51:42.150550 2, 0xFFFF, sum = 0
3062 06:51:42.153371 3, 0xFFFF, sum = 0
3063 06:51:42.153955 4, 0xFFFF, sum = 0
3064 06:51:42.156661 5, 0xFFFF, sum = 0
3065 06:51:42.160153 6, 0xFFFF, sum = 0
3066 06:51:42.160696 7, 0xFFFF, sum = 0
3067 06:51:42.163290 8, 0xFFFF, sum = 0
3068 06:51:42.163836 9, 0xFFFF, sum = 0
3069 06:51:42.166527 10, 0xFFFF, sum = 0
3070 06:51:42.167070 11, 0xFFFF, sum = 0
3071 06:51:42.170046 12, 0x0, sum = 1
3072 06:51:42.170483 13, 0x0, sum = 2
3073 06:51:42.173299 14, 0x0, sum = 3
3074 06:51:42.173871 15, 0x0, sum = 4
3075 06:51:42.174223 best_step = 13
3076 06:51:42.174543
3077 06:51:42.176372 ==
3078 06:51:42.180034 Dram Type= 6, Freq= 0, CH_0, rank 1
3079 06:51:42.182821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 06:51:42.183253 ==
3081 06:51:42.183597 RX Vref Scan: 0
3082 06:51:42.183916
3083 06:51:42.186702 RX Vref 0 -> 0, step: 1
3084 06:51:42.187276
3085 06:51:42.189930 RX Delay -37 -> 252, step: 4
3086 06:51:42.193169 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3087 06:51:42.200055 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3088 06:51:42.203414 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3089 06:51:42.206428 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3090 06:51:42.209621 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3091 06:51:42.212876 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3092 06:51:42.220127 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3093 06:51:42.222944 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3094 06:51:42.226581 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3095 06:51:42.229912 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3096 06:51:42.233162 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3097 06:51:42.236539 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3098 06:51:42.243502 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3099 06:51:42.246355 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3100 06:51:42.250023 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3101 06:51:42.253222 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3102 06:51:42.253804 ==
3103 06:51:42.256256 Dram Type= 6, Freq= 0, CH_0, rank 1
3104 06:51:42.263213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 06:51:42.263756 ==
3106 06:51:42.264105 DQS Delay:
3107 06:51:42.266048 DQS0 = 0, DQS1 = 0
3108 06:51:42.266640 DQM Delay:
3109 06:51:42.269416 DQM0 = 110, DQM1 = 101
3110 06:51:42.269864 DQ Delay:
3111 06:51:42.273065 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3112 06:51:42.276111 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3113 06:51:42.279763 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3114 06:51:42.282811 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3115 06:51:42.283246
3116 06:51:42.283587
3117 06:51:42.293075 [DQSOSCAuto] RK1, (LSB)MR18= 0x12fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3118 06:51:42.293657 CH0 RK1: MR19=403, MR18=12FA
3119 06:51:42.299726 CH0_RK1: MR19=0x403, MR18=0x12FA, DQSOSC=403, MR23=63, INC=40, DEC=26
3120 06:51:42.302948 [RxdqsGatingPostProcess] freq 1200
3121 06:51:42.309473 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3122 06:51:42.312648 best DQS0 dly(2T, 0.5T) = (0, 11)
3123 06:51:42.316058 best DQS1 dly(2T, 0.5T) = (0, 12)
3124 06:51:42.319773 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3125 06:51:42.323276 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3126 06:51:42.323891 best DQS0 dly(2T, 0.5T) = (0, 11)
3127 06:51:42.326164 best DQS1 dly(2T, 0.5T) = (0, 12)
3128 06:51:42.329897 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3129 06:51:42.333223 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3130 06:51:42.336626 Pre-setting of DQS Precalculation
3131 06:51:42.342991 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3132 06:51:42.343532 ==
3133 06:51:42.346386 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 06:51:42.349586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 06:51:42.350116 ==
3136 06:51:42.356086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 06:51:42.359992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3138 06:51:42.369595 [CA 0] Center 37 (7~67) winsize 61
3139 06:51:42.372967 [CA 1] Center 38 (8~68) winsize 61
3140 06:51:42.376414 [CA 2] Center 34 (4~64) winsize 61
3141 06:51:42.379454 [CA 3] Center 33 (3~64) winsize 62
3142 06:51:42.382918 [CA 4] Center 34 (4~64) winsize 61
3143 06:51:42.386078 [CA 5] Center 33 (3~63) winsize 61
3144 06:51:42.386613
3145 06:51:42.389626 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3146 06:51:42.390157
3147 06:51:42.392953 [CATrainingPosCal] consider 1 rank data
3148 06:51:42.396122 u2DelayCellTimex100 = 270/100 ps
3149 06:51:42.399248 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3150 06:51:42.402469 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3151 06:51:42.409707 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 06:51:42.413020 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3153 06:51:42.416391 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3154 06:51:42.419527 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3155 06:51:42.420064
3156 06:51:42.422881 CA PerBit enable=1, Macro0, CA PI delay=33
3157 06:51:42.423417
3158 06:51:42.425697 [CBTSetCACLKResult] CA Dly = 33
3159 06:51:42.426128 CS Dly: 5 (0~36)
3160 06:51:42.426471 ==
3161 06:51:42.429383 Dram Type= 6, Freq= 0, CH_1, rank 1
3162 06:51:42.436197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 06:51:42.436734 ==
3164 06:51:42.439351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3165 06:51:42.445916 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3166 06:51:42.455414 [CA 0] Center 37 (8~67) winsize 60
3167 06:51:42.458421 [CA 1] Center 37 (7~68) winsize 62
3168 06:51:42.461870 [CA 2] Center 34 (4~65) winsize 62
3169 06:51:42.465257 [CA 3] Center 33 (3~64) winsize 62
3170 06:51:42.468758 [CA 4] Center 34 (4~64) winsize 61
3171 06:51:42.471867 [CA 5] Center 32 (2~63) winsize 62
3172 06:51:42.472405
3173 06:51:42.475272 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3174 06:51:42.475813
3175 06:51:42.478432 [CATrainingPosCal] consider 2 rank data
3176 06:51:42.482089 u2DelayCellTimex100 = 270/100 ps
3177 06:51:42.485001 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3178 06:51:42.488594 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3179 06:51:42.494970 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3180 06:51:42.498377 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3181 06:51:42.501730 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3182 06:51:42.505002 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3183 06:51:42.505441
3184 06:51:42.508515 CA PerBit enable=1, Macro0, CA PI delay=33
3185 06:51:42.509071
3186 06:51:42.511643 [CBTSetCACLKResult] CA Dly = 33
3187 06:51:42.512075 CS Dly: 6 (0~39)
3188 06:51:42.512426
3189 06:51:42.514730 ----->DramcWriteLeveling(PI) begin...
3190 06:51:42.518212 ==
3191 06:51:42.521579 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 06:51:42.524684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 06:51:42.525117 ==
3194 06:51:42.528550 Write leveling (Byte 0): 24 => 24
3195 06:51:42.531480 Write leveling (Byte 1): 27 => 27
3196 06:51:42.535071 DramcWriteLeveling(PI) end<-----
3197 06:51:42.535759
3198 06:51:42.536117 ==
3199 06:51:42.538253 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 06:51:42.541457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 06:51:42.541928 ==
3202 06:51:42.544952 [Gating] SW mode calibration
3203 06:51:42.551775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3204 06:51:42.554825 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3205 06:51:42.561701 0 15 0 | B1->B0 | 2e2e 2b2b | 1 1 | (1 1) (0 0)
3206 06:51:42.565066 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 06:51:42.568545 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 06:51:42.574770 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 06:51:42.578118 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 06:51:42.581790 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 06:51:42.588359 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 06:51:42.591395 0 15 28 | B1->B0 | 2f2f 3131 | 0 0 | (0 1) (0 1)
3213 06:51:42.594843 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 06:51:42.601446 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 06:51:42.604664 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 06:51:42.608002 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 06:51:42.614696 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 06:51:42.617849 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 06:51:42.621088 1 0 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
3220 06:51:42.627952 1 0 28 | B1->B0 | 3939 3a3a | 0 0 | (0 0) (0 0)
3221 06:51:42.631177 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 06:51:42.634762 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 06:51:42.641453 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 06:51:42.644509 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 06:51:42.648026 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 06:51:42.654690 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 06:51:42.658085 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 06:51:42.661441 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3229 06:51:42.668021 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3230 06:51:42.670898 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 06:51:42.674490 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 06:51:42.678021 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 06:51:42.684550 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 06:51:42.688098 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 06:51:42.691579 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 06:51:42.697669 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 06:51:42.701330 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 06:51:42.704964 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 06:51:42.711487 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 06:51:42.714467 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 06:51:42.717935 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 06:51:42.724736 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 06:51:42.728080 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3244 06:51:42.731209 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3245 06:51:42.738080 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 06:51:42.738614 Total UI for P1: 0, mck2ui 16
3247 06:51:42.744745 best dqsien dly found for B0: ( 1, 3, 28)
3248 06:51:42.745275 Total UI for P1: 0, mck2ui 16
3249 06:51:42.748150 best dqsien dly found for B1: ( 1, 3, 26)
3250 06:51:42.754579 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3251 06:51:42.758005 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3252 06:51:42.758453
3253 06:51:42.761005 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3254 06:51:42.764624 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3255 06:51:42.767866 [Gating] SW calibration Done
3256 06:51:42.768299 ==
3257 06:51:42.771279 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 06:51:42.774463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 06:51:42.774895 ==
3260 06:51:42.777932 RX Vref Scan: 0
3261 06:51:42.778384
3262 06:51:42.778722 RX Vref 0 -> 0, step: 1
3263 06:51:42.779041
3264 06:51:42.781037 RX Delay -40 -> 252, step: 8
3265 06:51:42.784502 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3266 06:51:42.788043 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3267 06:51:42.794438 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3268 06:51:42.797833 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3269 06:51:42.801270 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3270 06:51:42.804271 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3271 06:51:42.807976 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3272 06:51:42.814480 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3273 06:51:42.817859 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3274 06:51:42.821576 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3275 06:51:42.824876 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3276 06:51:42.827994 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3277 06:51:42.834374 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3278 06:51:42.837931 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3279 06:51:42.840936 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3280 06:51:42.844523 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3281 06:51:42.845050 ==
3282 06:51:42.848053 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 06:51:42.854433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 06:51:42.854965 ==
3285 06:51:42.855314 DQS Delay:
3286 06:51:42.857684 DQS0 = 0, DQS1 = 0
3287 06:51:42.858115 DQM Delay:
3288 06:51:42.858469 DQM0 = 114, DQM1 = 106
3289 06:51:42.861141 DQ Delay:
3290 06:51:42.864905 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3291 06:51:42.867674 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3292 06:51:42.871203 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3293 06:51:42.874444 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3294 06:51:42.875039
3295 06:51:42.875389
3296 06:51:42.875713 ==
3297 06:51:42.877728 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 06:51:42.881565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 06:51:42.882092 ==
3300 06:51:42.884379
3301 06:51:42.884804
3302 06:51:42.885146 TX Vref Scan disable
3303 06:51:42.887650 == TX Byte 0 ==
3304 06:51:42.891400 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3305 06:51:42.894237 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3306 06:51:42.897812 == TX Byte 1 ==
3307 06:51:42.901455 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3308 06:51:42.904320 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3309 06:51:42.904923 ==
3310 06:51:42.907656 Dram Type= 6, Freq= 0, CH_1, rank 0
3311 06:51:42.914071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3312 06:51:42.914500 ==
3313 06:51:42.925374 TX Vref=22, minBit 9, minWin=24, winSum=404
3314 06:51:42.928273 TX Vref=24, minBit 11, minWin=24, winSum=409
3315 06:51:42.931582 TX Vref=26, minBit 9, minWin=25, winSum=420
3316 06:51:42.934980 TX Vref=28, minBit 9, minWin=25, winSum=420
3317 06:51:42.938433 TX Vref=30, minBit 9, minWin=25, winSum=421
3318 06:51:42.945272 TX Vref=32, minBit 9, minWin=24, winSum=418
3319 06:51:42.948349 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 30
3320 06:51:42.948873
3321 06:51:42.951754 Final TX Range 1 Vref 30
3322 06:51:42.952229
3323 06:51:42.952575 ==
3324 06:51:42.954860 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 06:51:42.958226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 06:51:42.958653 ==
3327 06:51:42.958992
3328 06:51:42.961900
3329 06:51:42.962422 TX Vref Scan disable
3330 06:51:42.965278 == TX Byte 0 ==
3331 06:51:42.968773 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3332 06:51:42.971953 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3333 06:51:42.975157 == TX Byte 1 ==
3334 06:51:42.978516 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3335 06:51:42.981898 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3336 06:51:42.982329
3337 06:51:42.985436 [DATLAT]
3338 06:51:42.986015 Freq=1200, CH1 RK0
3339 06:51:42.986368
3340 06:51:42.988342 DATLAT Default: 0xd
3341 06:51:42.988769 0, 0xFFFF, sum = 0
3342 06:51:42.991815 1, 0xFFFF, sum = 0
3343 06:51:42.992336 2, 0xFFFF, sum = 0
3344 06:51:42.995175 3, 0xFFFF, sum = 0
3345 06:51:42.995614 4, 0xFFFF, sum = 0
3346 06:51:42.998583 5, 0xFFFF, sum = 0
3347 06:51:42.999021 6, 0xFFFF, sum = 0
3348 06:51:43.001424 7, 0xFFFF, sum = 0
3349 06:51:43.004784 8, 0xFFFF, sum = 0
3350 06:51:43.005470 9, 0xFFFF, sum = 0
3351 06:51:43.008388 10, 0xFFFF, sum = 0
3352 06:51:43.008918 11, 0xFFFF, sum = 0
3353 06:51:43.011941 12, 0x0, sum = 1
3354 06:51:43.012478 13, 0x0, sum = 2
3355 06:51:43.015051 14, 0x0, sum = 3
3356 06:51:43.015534 15, 0x0, sum = 4
3357 06:51:43.015878 best_step = 13
3358 06:51:43.016194
3359 06:51:43.017983 ==
3360 06:51:43.021431 Dram Type= 6, Freq= 0, CH_1, rank 0
3361 06:51:43.024882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3362 06:51:43.025304 ==
3363 06:51:43.025696 RX Vref Scan: 1
3364 06:51:43.026014
3365 06:51:43.028265 Set Vref Range= 32 -> 127
3366 06:51:43.028684
3367 06:51:43.031317 RX Vref 32 -> 127, step: 1
3368 06:51:43.031735
3369 06:51:43.034636 RX Delay -21 -> 252, step: 4
3370 06:51:43.035054
3371 06:51:43.037930 Set Vref, RX VrefLevel [Byte0]: 32
3372 06:51:43.041651 [Byte1]: 32
3373 06:51:43.042175
3374 06:51:43.044990 Set Vref, RX VrefLevel [Byte0]: 33
3375 06:51:43.048218 [Byte1]: 33
3376 06:51:43.048755
3377 06:51:43.051528 Set Vref, RX VrefLevel [Byte0]: 34
3378 06:51:43.054494 [Byte1]: 34
3379 06:51:43.059353
3380 06:51:43.059926 Set Vref, RX VrefLevel [Byte0]: 35
3381 06:51:43.062479 [Byte1]: 35
3382 06:51:43.067085
3383 06:51:43.067506 Set Vref, RX VrefLevel [Byte0]: 36
3384 06:51:43.070114 [Byte1]: 36
3385 06:51:43.075042
3386 06:51:43.075487 Set Vref, RX VrefLevel [Byte0]: 37
3387 06:51:43.078536 [Byte1]: 37
3388 06:51:43.082727
3389 06:51:43.083219 Set Vref, RX VrefLevel [Byte0]: 38
3390 06:51:43.086210 [Byte1]: 38
3391 06:51:43.091027
3392 06:51:43.091544 Set Vref, RX VrefLevel [Byte0]: 39
3393 06:51:43.094202 [Byte1]: 39
3394 06:51:43.098624
3395 06:51:43.099043 Set Vref, RX VrefLevel [Byte0]: 40
3396 06:51:43.101977 [Byte1]: 40
3397 06:51:43.106363
3398 06:51:43.106784 Set Vref, RX VrefLevel [Byte0]: 41
3399 06:51:43.110018 [Byte1]: 41
3400 06:51:43.114851
3401 06:51:43.115407 Set Vref, RX VrefLevel [Byte0]: 42
3402 06:51:43.118022 [Byte1]: 42
3403 06:51:43.122840
3404 06:51:43.123358 Set Vref, RX VrefLevel [Byte0]: 43
3405 06:51:43.126317 [Byte1]: 43
3406 06:51:43.130641
3407 06:51:43.131162 Set Vref, RX VrefLevel [Byte0]: 44
3408 06:51:43.133977 [Byte1]: 44
3409 06:51:43.138350
3410 06:51:43.138885 Set Vref, RX VrefLevel [Byte0]: 45
3411 06:51:43.142010 [Byte1]: 45
3412 06:51:43.146320
3413 06:51:43.146842 Set Vref, RX VrefLevel [Byte0]: 46
3414 06:51:43.149472 [Byte1]: 46
3415 06:51:43.154172
3416 06:51:43.154727 Set Vref, RX VrefLevel [Byte0]: 47
3417 06:51:43.157688 [Byte1]: 47
3418 06:51:43.162362
3419 06:51:43.162900 Set Vref, RX VrefLevel [Byte0]: 48
3420 06:51:43.165774 [Byte1]: 48
3421 06:51:43.170278
3422 06:51:43.170804 Set Vref, RX VrefLevel [Byte0]: 49
3423 06:51:43.173519 [Byte1]: 49
3424 06:51:43.178029
3425 06:51:43.178452 Set Vref, RX VrefLevel [Byte0]: 50
3426 06:51:43.181255 [Byte1]: 50
3427 06:51:43.186229
3428 06:51:43.186788 Set Vref, RX VrefLevel [Byte0]: 51
3429 06:51:43.189315 [Byte1]: 51
3430 06:51:43.194167
3431 06:51:43.194700 Set Vref, RX VrefLevel [Byte0]: 52
3432 06:51:43.197130 [Byte1]: 52
3433 06:51:43.201818
3434 06:51:43.202343 Set Vref, RX VrefLevel [Byte0]: 53
3435 06:51:43.205440 [Byte1]: 53
3436 06:51:43.209626
3437 06:51:43.210158 Set Vref, RX VrefLevel [Byte0]: 54
3438 06:51:43.213244 [Byte1]: 54
3439 06:51:43.217920
3440 06:51:43.218445 Set Vref, RX VrefLevel [Byte0]: 55
3441 06:51:43.220899 [Byte1]: 55
3442 06:51:43.225678
3443 06:51:43.226207 Set Vref, RX VrefLevel [Byte0]: 56
3444 06:51:43.228863 [Byte1]: 56
3445 06:51:43.233944
3446 06:51:43.234471 Set Vref, RX VrefLevel [Byte0]: 57
3447 06:51:43.236649 [Byte1]: 57
3448 06:51:43.241655
3449 06:51:43.242179 Set Vref, RX VrefLevel [Byte0]: 58
3450 06:51:43.244803 [Byte1]: 58
3451 06:51:43.249397
3452 06:51:43.249969 Set Vref, RX VrefLevel [Byte0]: 59
3453 06:51:43.252820 [Byte1]: 59
3454 06:51:43.257654
3455 06:51:43.258177 Set Vref, RX VrefLevel [Byte0]: 60
3456 06:51:43.260518 [Byte1]: 60
3457 06:51:43.265305
3458 06:51:43.265904 Set Vref, RX VrefLevel [Byte0]: 61
3459 06:51:43.268875 [Byte1]: 61
3460 06:51:43.273132
3461 06:51:43.273804 Set Vref, RX VrefLevel [Byte0]: 62
3462 06:51:43.276358 [Byte1]: 62
3463 06:51:43.280896
3464 06:51:43.281468 Set Vref, RX VrefLevel [Byte0]: 63
3465 06:51:43.283993 [Byte1]: 63
3466 06:51:43.288829
3467 06:51:43.289247 Set Vref, RX VrefLevel [Byte0]: 64
3468 06:51:43.292382 [Byte1]: 64
3469 06:51:43.297007
3470 06:51:43.297593 Set Vref, RX VrefLevel [Byte0]: 65
3471 06:51:43.299996 [Byte1]: 65
3472 06:51:43.304792
3473 06:51:43.305337 Set Vref, RX VrefLevel [Byte0]: 66
3474 06:51:43.307815 [Byte1]: 66
3475 06:51:43.312576
3476 06:51:43.313154 Set Vref, RX VrefLevel [Byte0]: 67
3477 06:51:43.316195 [Byte1]: 67
3478 06:51:43.320561
3479 06:51:43.321015 Set Vref, RX VrefLevel [Byte0]: 68
3480 06:51:43.323717 [Byte1]: 68
3481 06:51:43.328820
3482 06:51:43.329351 Final RX Vref Byte 0 = 57 to rank0
3483 06:51:43.331651 Final RX Vref Byte 1 = 53 to rank0
3484 06:51:43.335177 Final RX Vref Byte 0 = 57 to rank1
3485 06:51:43.338407 Final RX Vref Byte 1 = 53 to rank1==
3486 06:51:43.342139 Dram Type= 6, Freq= 0, CH_1, rank 0
3487 06:51:43.348534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 06:51:43.349072 ==
3489 06:51:43.349418 DQS Delay:
3490 06:51:43.349778 DQS0 = 0, DQS1 = 0
3491 06:51:43.351958 DQM Delay:
3492 06:51:43.352491 DQM0 = 114, DQM1 = 107
3493 06:51:43.355067 DQ Delay:
3494 06:51:43.358460 DQ0 =116, DQ1 =108, DQ2 =104, DQ3 =112
3495 06:51:43.361801 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =112
3496 06:51:43.364963 DQ8 =94, DQ9 =98, DQ10 =104, DQ11 =104
3497 06:51:43.368641 DQ12 =114, DQ13 =114, DQ14 =114, DQ15 =114
3498 06:51:43.369177
3499 06:51:43.369554
3500 06:51:43.375188 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3501 06:51:43.378525 CH1 RK0: MR19=303, MR18=F1F8
3502 06:51:43.385006 CH1_RK0: MR19=0x303, MR18=0xF1F8, DQSOSC=413, MR23=63, INC=38, DEC=25
3503 06:51:43.385586
3504 06:51:43.388786 ----->DramcWriteLeveling(PI) begin...
3505 06:51:43.389322 ==
3506 06:51:43.391498 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 06:51:43.395144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 06:51:43.398561 ==
3509 06:51:43.399018 Write leveling (Byte 0): 24 => 24
3510 06:51:43.402224 Write leveling (Byte 1): 27 => 27
3511 06:51:43.405464 DramcWriteLeveling(PI) end<-----
3512 06:51:43.406047
3513 06:51:43.406386 ==
3514 06:51:43.408471 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 06:51:43.415480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 06:51:43.416009 ==
3517 06:51:43.416356 [Gating] SW mode calibration
3518 06:51:43.425303 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3519 06:51:43.428585 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3520 06:51:43.432102 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 06:51:43.438501 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 06:51:43.441870 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 06:51:43.445243 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 06:51:43.452029 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 06:51:43.455443 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 06:51:43.458705 0 15 24 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
3527 06:51:43.465224 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
3528 06:51:43.468584 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 06:51:43.471626 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 06:51:43.478273 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 06:51:43.481781 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 06:51:43.485204 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 06:51:43.492109 1 0 20 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)
3534 06:51:43.495113 1 0 24 | B1->B0 | 2a2a 4444 | 1 1 | (0 0) (0 0)
3535 06:51:43.498281 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 06:51:43.505201 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 06:51:43.508351 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 06:51:43.511748 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 06:51:43.518331 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 06:51:43.521920 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 06:51:43.524959 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 06:51:43.531682 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3543 06:51:43.535151 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3544 06:51:43.538454 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 06:51:43.541690 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 06:51:43.548160 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 06:51:43.551596 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 06:51:43.555030 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 06:51:43.561733 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 06:51:43.564732 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 06:51:43.568303 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 06:51:43.574600 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 06:51:43.578118 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 06:51:43.581208 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 06:51:43.587895 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 06:51:43.591535 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 06:51:43.594534 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 06:51:43.601315 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3559 06:51:43.604381 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3560 06:51:43.607610 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 06:51:43.610928 Total UI for P1: 0, mck2ui 16
3562 06:51:43.614235 best dqsien dly found for B0: ( 1, 3, 26)
3563 06:51:43.617747 Total UI for P1: 0, mck2ui 16
3564 06:51:43.621341 best dqsien dly found for B1: ( 1, 3, 26)
3565 06:51:43.624488 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3566 06:51:43.627842 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3567 06:51:43.628370
3568 06:51:43.634385 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3569 06:51:43.638073 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3570 06:51:43.640930 [Gating] SW calibration Done
3571 06:51:43.641450 ==
3572 06:51:43.644627 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 06:51:43.647596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 06:51:43.648036 ==
3575 06:51:43.648381 RX Vref Scan: 0
3576 06:51:43.648704
3577 06:51:43.650958 RX Vref 0 -> 0, step: 1
3578 06:51:43.651498
3579 06:51:43.654102 RX Delay -40 -> 252, step: 8
3580 06:51:43.657845 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3581 06:51:43.661106 iDelay=200, Bit 1, Center 107 (40 ~ 175) 136
3582 06:51:43.667684 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3583 06:51:43.671012 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3584 06:51:43.674353 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3585 06:51:43.677652 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3586 06:51:43.680833 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3587 06:51:43.684366 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3588 06:51:43.690830 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3589 06:51:43.694059 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3590 06:51:43.697713 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3591 06:51:43.700745 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3592 06:51:43.704110 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3593 06:51:43.710581 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3594 06:51:43.714155 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3595 06:51:43.717061 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3596 06:51:43.717531 ==
3597 06:51:43.720772 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 06:51:43.723626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 06:51:43.727483 ==
3600 06:51:43.728004 DQS Delay:
3601 06:51:43.728350 DQS0 = 0, DQS1 = 0
3602 06:51:43.730252 DQM Delay:
3603 06:51:43.730681 DQM0 = 111, DQM1 = 109
3604 06:51:43.733793 DQ Delay:
3605 06:51:43.737538 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =111
3606 06:51:43.740957 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3607 06:51:43.743890 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3608 06:51:43.747149 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3609 06:51:43.747678
3610 06:51:43.748018
3611 06:51:43.748334 ==
3612 06:51:43.750175 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 06:51:43.753822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 06:51:43.754349 ==
3615 06:51:43.754692
3616 06:51:43.755010
3617 06:51:43.757330 TX Vref Scan disable
3618 06:51:43.760792 == TX Byte 0 ==
3619 06:51:43.763993 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3620 06:51:43.767220 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3621 06:51:43.770720 == TX Byte 1 ==
3622 06:51:43.773626 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3623 06:51:43.777266 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3624 06:51:43.777854 ==
3625 06:51:43.780274 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 06:51:43.787279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 06:51:43.787813 ==
3628 06:51:43.797411 TX Vref=22, minBit 11, minWin=25, winSum=420
3629 06:51:43.800864 TX Vref=24, minBit 0, minWin=26, winSum=422
3630 06:51:43.804089 TX Vref=26, minBit 1, minWin=26, winSum=428
3631 06:51:43.807337 TX Vref=28, minBit 8, minWin=26, winSum=431
3632 06:51:43.810566 TX Vref=30, minBit 13, minWin=26, winSum=434
3633 06:51:43.817181 TX Vref=32, minBit 1, minWin=26, winSum=427
3634 06:51:43.820478 [TxChooseVref] Worse bit 13, Min win 26, Win sum 434, Final Vref 30
3635 06:51:43.820909
3636 06:51:43.823931 Final TX Range 1 Vref 30
3637 06:51:43.824459
3638 06:51:43.824804 ==
3639 06:51:43.827230 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 06:51:43.830239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 06:51:43.833762 ==
3642 06:51:43.834193
3643 06:51:43.834536
3644 06:51:43.834856 TX Vref Scan disable
3645 06:51:43.837309 == TX Byte 0 ==
3646 06:51:43.840935 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3647 06:51:43.843817 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3648 06:51:43.847404 == TX Byte 1 ==
3649 06:51:43.850617 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3650 06:51:43.857412 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3651 06:51:43.858043
3652 06:51:43.858392 [DATLAT]
3653 06:51:43.858713 Freq=1200, CH1 RK1
3654 06:51:43.859022
3655 06:51:43.860371 DATLAT Default: 0xd
3656 06:51:43.860971 0, 0xFFFF, sum = 0
3657 06:51:43.863884 1, 0xFFFF, sum = 0
3658 06:51:43.867010 2, 0xFFFF, sum = 0
3659 06:51:43.867448 3, 0xFFFF, sum = 0
3660 06:51:43.870812 4, 0xFFFF, sum = 0
3661 06:51:43.871394 5, 0xFFFF, sum = 0
3662 06:51:43.873874 6, 0xFFFF, sum = 0
3663 06:51:43.874479 7, 0xFFFF, sum = 0
3664 06:51:43.876854 8, 0xFFFF, sum = 0
3665 06:51:43.877655 9, 0xFFFF, sum = 0
3666 06:51:43.880189 10, 0xFFFF, sum = 0
3667 06:51:43.880625 11, 0xFFFF, sum = 0
3668 06:51:43.883384 12, 0x0, sum = 1
3669 06:51:43.883881 13, 0x0, sum = 2
3670 06:51:43.886772 14, 0x0, sum = 3
3671 06:51:43.887209 15, 0x0, sum = 4
3672 06:51:43.890350 best_step = 13
3673 06:51:43.890780
3674 06:51:43.891117 ==
3675 06:51:43.893576 Dram Type= 6, Freq= 0, CH_1, rank 1
3676 06:51:43.896674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3677 06:51:43.897243 ==
3678 06:51:43.897786 RX Vref Scan: 0
3679 06:51:43.900001
3680 06:51:43.900516 RX Vref 0 -> 0, step: 1
3681 06:51:43.900989
3682 06:51:43.903418 RX Delay -21 -> 252, step: 4
3683 06:51:43.910323 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3684 06:51:43.913381 iDelay=195, Bit 1, Center 106 (39 ~ 174) 136
3685 06:51:43.916701 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3686 06:51:43.920076 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3687 06:51:43.923361 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3688 06:51:43.930121 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3689 06:51:43.932828 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3690 06:51:43.936390 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3691 06:51:43.939708 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3692 06:51:43.943451 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3693 06:51:43.949787 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3694 06:51:43.952968 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3695 06:51:43.956548 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3696 06:51:43.959693 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3697 06:51:43.962458 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3698 06:51:43.969248 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3699 06:51:43.969472 ==
3700 06:51:43.972626 Dram Type= 6, Freq= 0, CH_1, rank 1
3701 06:51:43.975962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3702 06:51:43.976178 ==
3703 06:51:43.976315 DQS Delay:
3704 06:51:43.979255 DQS0 = 0, DQS1 = 0
3705 06:51:43.979478 DQM Delay:
3706 06:51:43.982412 DQM0 = 111, DQM1 = 110
3707 06:51:43.982655 DQ Delay:
3708 06:51:43.985887 DQ0 =116, DQ1 =106, DQ2 =102, DQ3 =108
3709 06:51:43.989078 DQ4 =106, DQ5 =120, DQ6 =122, DQ7 =108
3710 06:51:43.992288 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =104
3711 06:51:43.995976 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =120
3712 06:51:43.999129
3713 06:51:43.999532
3714 06:51:44.006014 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3715 06:51:44.009302 CH1 RK1: MR19=304, MR18=FA0A
3716 06:51:44.015829 CH1_RK1: MR19=0x304, MR18=0xFA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3717 06:51:44.019130 [RxdqsGatingPostProcess] freq 1200
3718 06:51:44.022346 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3719 06:51:44.025610 best DQS0 dly(2T, 0.5T) = (0, 11)
3720 06:51:44.028838 best DQS1 dly(2T, 0.5T) = (0, 11)
3721 06:51:44.032412 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3722 06:51:44.035604 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3723 06:51:44.039305 best DQS0 dly(2T, 0.5T) = (0, 11)
3724 06:51:44.042644 best DQS1 dly(2T, 0.5T) = (0, 11)
3725 06:51:44.045735 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3726 06:51:44.049271 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3727 06:51:44.052722 Pre-setting of DQS Precalculation
3728 06:51:44.055820 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3729 06:51:44.065747 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3730 06:51:44.072378 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3731 06:51:44.072913
3732 06:51:44.073282
3733 06:51:44.075157 [Calibration Summary] 2400 Mbps
3734 06:51:44.075584 CH 0, Rank 0
3735 06:51:44.078764 SW Impedance : PASS
3736 06:51:44.079191 DUTY Scan : NO K
3737 06:51:44.082098 ZQ Calibration : PASS
3738 06:51:44.085161 Jitter Meter : NO K
3739 06:51:44.085623 CBT Training : PASS
3740 06:51:44.088726 Write leveling : PASS
3741 06:51:44.091824 RX DQS gating : PASS
3742 06:51:44.092252 RX DQ/DQS(RDDQC) : PASS
3743 06:51:44.095829 TX DQ/DQS : PASS
3744 06:51:44.098484 RX DATLAT : PASS
3745 06:51:44.098909 RX DQ/DQS(Engine): PASS
3746 06:51:44.101712 TX OE : NO K
3747 06:51:44.102137 All Pass.
3748 06:51:44.102474
3749 06:51:44.105394 CH 0, Rank 1
3750 06:51:44.105986 SW Impedance : PASS
3751 06:51:44.108431 DUTY Scan : NO K
3752 06:51:44.108854 ZQ Calibration : PASS
3753 06:51:44.111814 Jitter Meter : NO K
3754 06:51:44.115161 CBT Training : PASS
3755 06:51:44.115595 Write leveling : PASS
3756 06:51:44.118502 RX DQS gating : PASS
3757 06:51:44.121528 RX DQ/DQS(RDDQC) : PASS
3758 06:51:44.121967 TX DQ/DQS : PASS
3759 06:51:44.125005 RX DATLAT : PASS
3760 06:51:44.128399 RX DQ/DQS(Engine): PASS
3761 06:51:44.128953 TX OE : NO K
3762 06:51:44.131859 All Pass.
3763 06:51:44.132423
3764 06:51:44.132868 CH 1, Rank 0
3765 06:51:44.135092 SW Impedance : PASS
3766 06:51:44.135530 DUTY Scan : NO K
3767 06:51:44.138118 ZQ Calibration : PASS
3768 06:51:44.141577 Jitter Meter : NO K
3769 06:51:44.142016 CBT Training : PASS
3770 06:51:44.144757 Write leveling : PASS
3771 06:51:44.148233 RX DQS gating : PASS
3772 06:51:44.148670 RX DQ/DQS(RDDQC) : PASS
3773 06:51:44.151623 TX DQ/DQS : PASS
3774 06:51:44.152061 RX DATLAT : PASS
3775 06:51:44.155393 RX DQ/DQS(Engine): PASS
3776 06:51:44.158138 TX OE : NO K
3777 06:51:44.158579 All Pass.
3778 06:51:44.159020
3779 06:51:44.159436 CH 1, Rank 1
3780 06:51:44.162087 SW Impedance : PASS
3781 06:51:44.165040 DUTY Scan : NO K
3782 06:51:44.165629 ZQ Calibration : PASS
3783 06:51:44.168427 Jitter Meter : NO K
3784 06:51:44.171680 CBT Training : PASS
3785 06:51:44.172218 Write leveling : PASS
3786 06:51:44.174768 RX DQS gating : PASS
3787 06:51:44.178141 RX DQ/DQS(RDDQC) : PASS
3788 06:51:44.178574 TX DQ/DQS : PASS
3789 06:51:44.181297 RX DATLAT : PASS
3790 06:51:44.184724 RX DQ/DQS(Engine): PASS
3791 06:51:44.185162 TX OE : NO K
3792 06:51:44.188070 All Pass.
3793 06:51:44.188617
3794 06:51:44.189064 DramC Write-DBI off
3795 06:51:44.191496 PER_BANK_REFRESH: Hybrid Mode
3796 06:51:44.192047 TX_TRACKING: ON
3797 06:51:44.200865 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3798 06:51:44.204860 [FAST_K] Save calibration result to emmc
3799 06:51:44.207848 dramc_set_vcore_voltage set vcore to 650000
3800 06:51:44.211097 Read voltage for 600, 5
3801 06:51:44.211534 Vio18 = 0
3802 06:51:44.214388 Vcore = 650000
3803 06:51:44.214821 Vdram = 0
3804 06:51:44.215261 Vddq = 0
3805 06:51:44.217929 Vmddr = 0
3806 06:51:44.221273 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3807 06:51:44.227648 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3808 06:51:44.228188 MEM_TYPE=3, freq_sel=19
3809 06:51:44.231576 sv_algorithm_assistance_LP4_1600
3810 06:51:44.237604 ============ PULL DRAM RESETB DOWN ============
3811 06:51:44.241377 ========== PULL DRAM RESETB DOWN end =========
3812 06:51:44.244550 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3813 06:51:44.247514 ===================================
3814 06:51:44.251076 LPDDR4 DRAM CONFIGURATION
3815 06:51:44.254423 ===================================
3816 06:51:44.254980 EX_ROW_EN[0] = 0x0
3817 06:51:44.257749 EX_ROW_EN[1] = 0x0
3818 06:51:44.260972 LP4Y_EN = 0x0
3819 06:51:44.261541 WORK_FSP = 0x0
3820 06:51:44.264667 WL = 0x2
3821 06:51:44.265208 RL = 0x2
3822 06:51:44.267667 BL = 0x2
3823 06:51:44.268208 RPST = 0x0
3824 06:51:44.271068 RD_PRE = 0x0
3825 06:51:44.271609 WR_PRE = 0x1
3826 06:51:44.274382 WR_PST = 0x0
3827 06:51:44.274926 DBI_WR = 0x0
3828 06:51:44.277670 DBI_RD = 0x0
3829 06:51:44.278207 OTF = 0x1
3830 06:51:44.280899 ===================================
3831 06:51:44.283789 ===================================
3832 06:51:44.287649 ANA top config
3833 06:51:44.290766 ===================================
3834 06:51:44.291208 DLL_ASYNC_EN = 0
3835 06:51:44.293806 ALL_SLAVE_EN = 1
3836 06:51:44.297167 NEW_RANK_MODE = 1
3837 06:51:44.300339 DLL_IDLE_MODE = 1
3838 06:51:44.303914 LP45_APHY_COMB_EN = 1
3839 06:51:44.304476 TX_ODT_DIS = 1
3840 06:51:44.306983 NEW_8X_MODE = 1
3841 06:51:44.310475 ===================================
3842 06:51:44.313558 ===================================
3843 06:51:44.317015 data_rate = 1200
3844 06:51:44.320730 CKR = 1
3845 06:51:44.323731 DQ_P2S_RATIO = 8
3846 06:51:44.327194 ===================================
3847 06:51:44.330417 CA_P2S_RATIO = 8
3848 06:51:44.330853 DQ_CA_OPEN = 0
3849 06:51:44.333542 DQ_SEMI_OPEN = 0
3850 06:51:44.337273 CA_SEMI_OPEN = 0
3851 06:51:44.340291 CA_FULL_RATE = 0
3852 06:51:44.344099 DQ_CKDIV4_EN = 1
3853 06:51:44.347075 CA_CKDIV4_EN = 1
3854 06:51:44.347629 CA_PREDIV_EN = 0
3855 06:51:44.350394 PH8_DLY = 0
3856 06:51:44.353911 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3857 06:51:44.356952 DQ_AAMCK_DIV = 4
3858 06:51:44.360076 CA_AAMCK_DIV = 4
3859 06:51:44.363627 CA_ADMCK_DIV = 4
3860 06:51:44.364173 DQ_TRACK_CA_EN = 0
3861 06:51:44.367144 CA_PICK = 600
3862 06:51:44.370154 CA_MCKIO = 600
3863 06:51:44.373582 MCKIO_SEMI = 0
3864 06:51:44.376995 PLL_FREQ = 2288
3865 06:51:44.379686 DQ_UI_PI_RATIO = 32
3866 06:51:44.383354 CA_UI_PI_RATIO = 0
3867 06:51:44.386297 ===================================
3868 06:51:44.390041 ===================================
3869 06:51:44.390575 memory_type:LPDDR4
3870 06:51:44.393106 GP_NUM : 10
3871 06:51:44.396794 SRAM_EN : 1
3872 06:51:44.397330 MD32_EN : 0
3873 06:51:44.399643 ===================================
3874 06:51:44.403133 [ANA_INIT] >>>>>>>>>>>>>>
3875 06:51:44.406445 <<<<<< [CONFIGURE PHASE]: ANA_TX
3876 06:51:44.409892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3877 06:51:44.413013 ===================================
3878 06:51:44.416294 data_rate = 1200,PCW = 0X5800
3879 06:51:44.419505 ===================================
3880 06:51:44.422635 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3881 06:51:44.426095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3882 06:51:44.433073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3883 06:51:44.436602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3884 06:51:44.439491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3885 06:51:44.442849 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3886 06:51:44.446174 [ANA_INIT] flow start
3887 06:51:44.449362 [ANA_INIT] PLL >>>>>>>>
3888 06:51:44.449840 [ANA_INIT] PLL <<<<<<<<
3889 06:51:44.452739 [ANA_INIT] MIDPI >>>>>>>>
3890 06:51:44.456348 [ANA_INIT] MIDPI <<<<<<<<
3891 06:51:44.459379 [ANA_INIT] DLL >>>>>>>>
3892 06:51:44.459810 [ANA_INIT] flow end
3893 06:51:44.462677 ============ LP4 DIFF to SE enter ============
3894 06:51:44.469526 ============ LP4 DIFF to SE exit ============
3895 06:51:44.470068 [ANA_INIT] <<<<<<<<<<<<<
3896 06:51:44.473069 [Flow] Enable top DCM control >>>>>
3897 06:51:44.475920 [Flow] Enable top DCM control <<<<<
3898 06:51:44.479336 Enable DLL master slave shuffle
3899 06:51:44.485796 ==============================================================
3900 06:51:44.486228 Gating Mode config
3901 06:51:44.492553 ==============================================================
3902 06:51:44.495724 Config description:
3903 06:51:44.505748 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3904 06:51:44.512312 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3905 06:51:44.516118 SELPH_MODE 0: By rank 1: By Phase
3906 06:51:44.522286 ==============================================================
3907 06:51:44.525711 GAT_TRACK_EN = 1
3908 06:51:44.526146 RX_GATING_MODE = 2
3909 06:51:44.528753 RX_GATING_TRACK_MODE = 2
3910 06:51:44.532368 SELPH_MODE = 1
3911 06:51:44.535732 PICG_EARLY_EN = 1
3912 06:51:44.538968 VALID_LAT_VALUE = 1
3913 06:51:44.545701 ==============================================================
3914 06:51:44.549040 Enter into Gating configuration >>>>
3915 06:51:44.552428 Exit from Gating configuration <<<<
3916 06:51:44.555816 Enter into DVFS_PRE_config >>>>>
3917 06:51:44.565881 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3918 06:51:44.568748 Exit from DVFS_PRE_config <<<<<
3919 06:51:44.571762 Enter into PICG configuration >>>>
3920 06:51:44.575346 Exit from PICG configuration <<<<
3921 06:51:44.578478 [RX_INPUT] configuration >>>>>
3922 06:51:44.581603 [RX_INPUT] configuration <<<<<
3923 06:51:44.584996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3924 06:51:44.591935 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3925 06:51:44.598198 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3926 06:51:44.605140 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3927 06:51:44.608584 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3928 06:51:44.615110 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3929 06:51:44.618241 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3930 06:51:44.624771 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3931 06:51:44.628212 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3932 06:51:44.631544 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3933 06:51:44.634739 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3934 06:51:44.641251 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3935 06:51:44.644798 ===================================
3936 06:51:44.647821 LPDDR4 DRAM CONFIGURATION
3937 06:51:44.651576 ===================================
3938 06:51:44.652120 EX_ROW_EN[0] = 0x0
3939 06:51:44.654763 EX_ROW_EN[1] = 0x0
3940 06:51:44.655217 LP4Y_EN = 0x0
3941 06:51:44.658004 WORK_FSP = 0x0
3942 06:51:44.658441 WL = 0x2
3943 06:51:44.661583 RL = 0x2
3944 06:51:44.662129 BL = 0x2
3945 06:51:44.664942 RPST = 0x0
3946 06:51:44.665691 RD_PRE = 0x0
3947 06:51:44.667994 WR_PRE = 0x1
3948 06:51:44.668550 WR_PST = 0x0
3949 06:51:44.671554 DBI_WR = 0x0
3950 06:51:44.672095 DBI_RD = 0x0
3951 06:51:44.674710 OTF = 0x1
3952 06:51:44.678210 ===================================
3953 06:51:44.681267 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3954 06:51:44.684528 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3955 06:51:44.691108 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3956 06:51:44.694738 ===================================
3957 06:51:44.695286 LPDDR4 DRAM CONFIGURATION
3958 06:51:44.698130 ===================================
3959 06:51:44.701056 EX_ROW_EN[0] = 0x10
3960 06:51:44.704585 EX_ROW_EN[1] = 0x0
3961 06:51:44.705131 LP4Y_EN = 0x0
3962 06:51:44.707812 WORK_FSP = 0x0
3963 06:51:44.708353 WL = 0x2
3964 06:51:44.711020 RL = 0x2
3965 06:51:44.711455 BL = 0x2
3966 06:51:44.714444 RPST = 0x0
3967 06:51:44.715190 RD_PRE = 0x0
3968 06:51:44.717681 WR_PRE = 0x1
3969 06:51:44.718105 WR_PST = 0x0
3970 06:51:44.720914 DBI_WR = 0x0
3971 06:51:44.721528 DBI_RD = 0x0
3972 06:51:44.724043 OTF = 0x1
3973 06:51:44.727918 ===================================
3974 06:51:44.733891 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3975 06:51:44.737639 nWR fixed to 30
3976 06:51:44.740656 [ModeRegInit_LP4] CH0 RK0
3977 06:51:44.741176 [ModeRegInit_LP4] CH0 RK1
3978 06:51:44.744268 [ModeRegInit_LP4] CH1 RK0
3979 06:51:44.747342 [ModeRegInit_LP4] CH1 RK1
3980 06:51:44.747767 match AC timing 17
3981 06:51:44.753833 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3982 06:51:44.757437 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3983 06:51:44.760500 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3984 06:51:44.767017 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3985 06:51:44.770622 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3986 06:51:44.771144 ==
3987 06:51:44.774341 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 06:51:44.777339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 06:51:44.777983 ==
3990 06:51:44.783761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 06:51:44.790345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3992 06:51:44.793689 [CA 0] Center 37 (7~67) winsize 61
3993 06:51:44.797354 [CA 1] Center 36 (6~67) winsize 62
3994 06:51:44.800440 [CA 2] Center 35 (5~65) winsize 61
3995 06:51:44.803365 [CA 3] Center 35 (5~65) winsize 61
3996 06:51:44.807235 [CA 4] Center 34 (4~65) winsize 62
3997 06:51:44.810093 [CA 5] Center 34 (4~64) winsize 61
3998 06:51:44.810520
3999 06:51:44.813472 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4000 06:51:44.813922
4001 06:51:44.816595 [CATrainingPosCal] consider 1 rank data
4002 06:51:44.820441 u2DelayCellTimex100 = 270/100 ps
4003 06:51:44.823831 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4004 06:51:44.827385 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4005 06:51:44.830016 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4006 06:51:44.833664 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4007 06:51:44.837091 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4008 06:51:44.843793 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4009 06:51:44.844354
4010 06:51:44.846989 CA PerBit enable=1, Macro0, CA PI delay=34
4011 06:51:44.847413
4012 06:51:44.849985 [CBTSetCACLKResult] CA Dly = 34
4013 06:51:44.850406 CS Dly: 7 (0~38)
4014 06:51:44.850740 ==
4015 06:51:44.853534 Dram Type= 6, Freq= 0, CH_0, rank 1
4016 06:51:44.857111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 06:51:44.860429 ==
4018 06:51:44.863758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4019 06:51:44.870113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4020 06:51:44.873659 [CA 0] Center 37 (7~67) winsize 61
4021 06:51:44.877067 [CA 1] Center 36 (6~67) winsize 62
4022 06:51:44.879839 [CA 2] Center 35 (5~65) winsize 61
4023 06:51:44.883275 [CA 3] Center 35 (5~65) winsize 61
4024 06:51:44.886325 [CA 4] Center 34 (4~65) winsize 62
4025 06:51:44.889913 [CA 5] Center 34 (3~65) winsize 63
4026 06:51:44.890493
4027 06:51:44.893242 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4028 06:51:44.893838
4029 06:51:44.896811 [CATrainingPosCal] consider 2 rank data
4030 06:51:44.900329 u2DelayCellTimex100 = 270/100 ps
4031 06:51:44.903095 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4032 06:51:44.906352 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4033 06:51:44.910135 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4034 06:51:44.913383 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4035 06:51:44.919602 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4036 06:51:44.923066 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4037 06:51:44.923775
4038 06:51:44.926039 CA PerBit enable=1, Macro0, CA PI delay=34
4039 06:51:44.926467
4040 06:51:44.929860 [CBTSetCACLKResult] CA Dly = 34
4041 06:51:44.930387 CS Dly: 7 (0~38)
4042 06:51:44.930729
4043 06:51:44.932968 ----->DramcWriteLeveling(PI) begin...
4044 06:51:44.933400 ==
4045 06:51:44.935971 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 06:51:44.942726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 06:51:44.943203 ==
4048 06:51:44.946089 Write leveling (Byte 0): 30 => 30
4049 06:51:44.949083 Write leveling (Byte 1): 30 => 30
4050 06:51:44.952562 DramcWriteLeveling(PI) end<-----
4051 06:51:44.953022
4052 06:51:44.953360 ==
4053 06:51:44.955819 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 06:51:44.958959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 06:51:44.959385 ==
4056 06:51:44.962611 [Gating] SW mode calibration
4057 06:51:44.969173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4058 06:51:44.972647 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4059 06:51:44.979269 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 06:51:44.982251 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4061 06:51:44.985652 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4062 06:51:44.992867 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4063 06:51:44.995866 0 9 16 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
4064 06:51:44.999391 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4065 06:51:45.005559 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 06:51:45.008794 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 06:51:45.012270 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 06:51:45.018747 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 06:51:45.022042 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 06:51:45.025411 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4071 06:51:45.031914 0 10 16 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (0 0)
4072 06:51:45.035364 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 06:51:45.038731 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 06:51:45.045401 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 06:51:45.048531 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 06:51:45.052030 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 06:51:45.058472 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 06:51:45.062007 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4079 06:51:45.065210 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4080 06:51:45.072037 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 06:51:45.075079 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 06:51:45.078200 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 06:51:45.084893 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 06:51:45.088152 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 06:51:45.091584 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 06:51:45.098062 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 06:51:45.101614 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 06:51:45.105236 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 06:51:45.111760 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 06:51:45.114978 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 06:51:45.118014 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 06:51:45.124816 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 06:51:45.128333 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 06:51:45.131096 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4095 06:51:45.137714 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4096 06:51:45.138239 Total UI for P1: 0, mck2ui 16
4097 06:51:45.144557 best dqsien dly found for B0: ( 0, 13, 12)
4098 06:51:45.148038 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4099 06:51:45.151195 Total UI for P1: 0, mck2ui 16
4100 06:51:45.154718 best dqsien dly found for B1: ( 0, 13, 16)
4101 06:51:45.157873 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4102 06:51:45.161182 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4103 06:51:45.161752
4104 06:51:45.164372 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4105 06:51:45.167729 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4106 06:51:45.171044 [Gating] SW calibration Done
4107 06:51:45.171568 ==
4108 06:51:45.174092 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 06:51:45.180733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 06:51:45.181249 ==
4111 06:51:45.181626 RX Vref Scan: 0
4112 06:51:45.181948
4113 06:51:45.184067 RX Vref 0 -> 0, step: 1
4114 06:51:45.184493
4115 06:51:45.186968 RX Delay -230 -> 252, step: 16
4116 06:51:45.190609 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4117 06:51:45.193835 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4118 06:51:45.197430 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4119 06:51:45.204106 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4120 06:51:45.206966 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4121 06:51:45.210842 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4122 06:51:45.213900 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4123 06:51:45.217150 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4124 06:51:45.224001 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4125 06:51:45.226951 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4126 06:51:45.230385 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4127 06:51:45.233924 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4128 06:51:45.240622 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4129 06:51:45.244042 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4130 06:51:45.247186 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4131 06:51:45.250373 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4132 06:51:45.250901 ==
4133 06:51:45.254073 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 06:51:45.260426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 06:51:45.261053 ==
4136 06:51:45.261406 DQS Delay:
4137 06:51:45.264203 DQS0 = 0, DQS1 = 0
4138 06:51:45.264740 DQM Delay:
4139 06:51:45.266876 DQM0 = 38, DQM1 = 31
4140 06:51:45.267412 DQ Delay:
4141 06:51:45.270427 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4142 06:51:45.273910 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4143 06:51:45.277347 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4144 06:51:45.280472 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4145 06:51:45.280997
4146 06:51:45.281333
4147 06:51:45.281709 ==
4148 06:51:45.283372 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 06:51:45.286683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 06:51:45.287154 ==
4151 06:51:45.287489
4152 06:51:45.287798
4153 06:51:45.290222 TX Vref Scan disable
4154 06:51:45.293658 == TX Byte 0 ==
4155 06:51:45.297119 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4156 06:51:45.300447 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4157 06:51:45.303328 == TX Byte 1 ==
4158 06:51:45.306938 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4159 06:51:45.310189 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4160 06:51:45.310709 ==
4161 06:51:45.313458 Dram Type= 6, Freq= 0, CH_0, rank 0
4162 06:51:45.317110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 06:51:45.320272 ==
4164 06:51:45.320695
4165 06:51:45.321024
4166 06:51:45.321333 TX Vref Scan disable
4167 06:51:45.323934 == TX Byte 0 ==
4168 06:51:45.327490 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4169 06:51:45.333841 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4170 06:51:45.334283 == TX Byte 1 ==
4171 06:51:45.337338 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4172 06:51:45.343657 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4173 06:51:45.344182
4174 06:51:45.344520 [DATLAT]
4175 06:51:45.344940 Freq=600, CH0 RK0
4176 06:51:45.345263
4177 06:51:45.347378 DATLAT Default: 0x9
4178 06:51:45.347901 0, 0xFFFF, sum = 0
4179 06:51:45.350367 1, 0xFFFF, sum = 0
4180 06:51:45.353971 2, 0xFFFF, sum = 0
4181 06:51:45.354513 3, 0xFFFF, sum = 0
4182 06:51:45.357391 4, 0xFFFF, sum = 0
4183 06:51:45.357976 5, 0xFFFF, sum = 0
4184 06:51:45.360138 6, 0xFFFF, sum = 0
4185 06:51:45.360567 7, 0xFFFF, sum = 0
4186 06:51:45.363671 8, 0x0, sum = 1
4187 06:51:45.364156 9, 0x0, sum = 2
4188 06:51:45.364503 10, 0x0, sum = 3
4189 06:51:45.366909 11, 0x0, sum = 4
4190 06:51:45.367339 best_step = 9
4191 06:51:45.367675
4192 06:51:45.367989 ==
4193 06:51:45.370181 Dram Type= 6, Freq= 0, CH_0, rank 0
4194 06:51:45.376827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 06:51:45.377353 ==
4196 06:51:45.377743 RX Vref Scan: 1
4197 06:51:45.378066
4198 06:51:45.380235 RX Vref 0 -> 0, step: 1
4199 06:51:45.380659
4200 06:51:45.383668 RX Delay -195 -> 252, step: 8
4201 06:51:45.384092
4202 06:51:45.386668 Set Vref, RX VrefLevel [Byte0]: 61
4203 06:51:45.390189 [Byte1]: 53
4204 06:51:45.390616
4205 06:51:45.393458 Final RX Vref Byte 0 = 61 to rank0
4206 06:51:45.396993 Final RX Vref Byte 1 = 53 to rank0
4207 06:51:45.400368 Final RX Vref Byte 0 = 61 to rank1
4208 06:51:45.403415 Final RX Vref Byte 1 = 53 to rank1==
4209 06:51:45.406681 Dram Type= 6, Freq= 0, CH_0, rank 0
4210 06:51:45.410124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 06:51:45.410550 ==
4212 06:51:45.413272 DQS Delay:
4213 06:51:45.413731 DQS0 = 0, DQS1 = 0
4214 06:51:45.417033 DQM Delay:
4215 06:51:45.417593 DQM0 = 34, DQM1 = 29
4216 06:51:45.417938 DQ Delay:
4217 06:51:45.419900 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4218 06:51:45.423273 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4219 06:51:45.426749 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4220 06:51:45.430049 DQ12 =32, DQ13 =36, DQ14 =44, DQ15 =36
4221 06:51:45.430475
4222 06:51:45.430811
4223 06:51:45.440184 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4224 06:51:45.443600 CH0 RK0: MR19=808, MR18=3D3D
4225 06:51:45.446867 CH0_RK0: MR19=0x808, MR18=0x3D3D, DQSOSC=398, MR23=63, INC=165, DEC=110
4226 06:51:45.450452
4227 06:51:45.453415 ----->DramcWriteLeveling(PI) begin...
4228 06:51:45.453994 ==
4229 06:51:45.456897 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 06:51:45.460206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 06:51:45.460731 ==
4232 06:51:45.463615 Write leveling (Byte 0): 32 => 32
4233 06:51:45.466409 Write leveling (Byte 1): 29 => 29
4234 06:51:45.470121 DramcWriteLeveling(PI) end<-----
4235 06:51:45.470642
4236 06:51:45.470986 ==
4237 06:51:45.473072 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 06:51:45.476650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 06:51:45.477181 ==
4240 06:51:45.479824 [Gating] SW mode calibration
4241 06:51:45.486561 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4242 06:51:45.493027 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4243 06:51:45.496529 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 06:51:45.499782 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 06:51:45.506429 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4246 06:51:45.509948 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4247 06:51:45.512881 0 9 16 | B1->B0 | 2b2b 2424 | 1 1 | (1 1) (1 0)
4248 06:51:45.519503 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 06:51:45.522938 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 06:51:45.526058 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 06:51:45.533005 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 06:51:45.536246 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 06:51:45.539705 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 06:51:45.546197 0 10 12 | B1->B0 | 2828 3434 | 0 1 | (1 1) (0 0)
4255 06:51:45.549451 0 10 16 | B1->B0 | 3333 4444 | 0 0 | (0 0) (0 0)
4256 06:51:45.552899 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 06:51:45.559427 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 06:51:45.562918 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 06:51:45.566433 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 06:51:45.569709 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 06:51:45.576289 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 06:51:45.578877 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4263 06:51:45.582194 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4264 06:51:45.589169 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 06:51:45.592605 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 06:51:45.595450 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 06:51:45.602199 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 06:51:45.605421 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 06:51:45.609292 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 06:51:45.615783 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 06:51:45.619004 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 06:51:45.622414 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 06:51:45.629117 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 06:51:45.632661 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 06:51:45.635834 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 06:51:45.642407 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 06:51:45.645417 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 06:51:45.649131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4279 06:51:45.655482 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4280 06:51:45.656006 Total UI for P1: 0, mck2ui 16
4281 06:51:45.662116 best dqsien dly found for B0: ( 0, 13, 12)
4282 06:51:45.665741 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4283 06:51:45.669089 Total UI for P1: 0, mck2ui 16
4284 06:51:45.672476 best dqsien dly found for B1: ( 0, 13, 16)
4285 06:51:45.675886 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4286 06:51:45.679117 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4287 06:51:45.679645
4288 06:51:45.682404 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4289 06:51:45.685219 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4290 06:51:45.689136 [Gating] SW calibration Done
4291 06:51:45.689711 ==
4292 06:51:45.691990 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 06:51:45.695340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 06:51:45.698879 ==
4295 06:51:45.699402 RX Vref Scan: 0
4296 06:51:45.699741
4297 06:51:45.702456 RX Vref 0 -> 0, step: 1
4298 06:51:45.703032
4299 06:51:45.705402 RX Delay -230 -> 252, step: 16
4300 06:51:45.708458 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4301 06:51:45.712133 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4302 06:51:45.714826 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4303 06:51:45.721434 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4304 06:51:45.724765 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4305 06:51:45.728345 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4306 06:51:45.731460 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4307 06:51:45.738064 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4308 06:51:45.741639 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4309 06:51:45.745074 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4310 06:51:45.748408 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4311 06:51:45.751488 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4312 06:51:45.758184 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4313 06:51:45.761371 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4314 06:51:45.764776 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4315 06:51:45.768316 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4316 06:51:45.771657 ==
4317 06:51:45.774455 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 06:51:45.778042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 06:51:45.778468 ==
4320 06:51:45.778802 DQS Delay:
4321 06:51:45.781438 DQS0 = 0, DQS1 = 0
4322 06:51:45.782185 DQM Delay:
4323 06:51:45.784497 DQM0 = 37, DQM1 = 27
4324 06:51:45.784914 DQ Delay:
4325 06:51:45.787978 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4326 06:51:45.791022 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4327 06:51:45.794430 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4328 06:51:45.798204 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4329 06:51:45.798734
4330 06:51:45.799071
4331 06:51:45.799384 ==
4332 06:51:45.800724 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 06:51:45.804215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 06:51:45.804640 ==
4335 06:51:45.804974
4336 06:51:45.805281
4337 06:51:45.807389 TX Vref Scan disable
4338 06:51:45.810954 == TX Byte 0 ==
4339 06:51:45.814200 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4340 06:51:45.817765 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4341 06:51:45.820974 == TX Byte 1 ==
4342 06:51:45.824731 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4343 06:51:45.827814 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4344 06:51:45.828383 ==
4345 06:51:45.831234 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 06:51:45.837856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 06:51:45.838398 ==
4348 06:51:45.838740
4349 06:51:45.839054
4350 06:51:45.839355 TX Vref Scan disable
4351 06:51:45.842023 == TX Byte 0 ==
4352 06:51:45.845618 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4353 06:51:45.852075 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4354 06:51:45.852620 == TX Byte 1 ==
4355 06:51:45.855214 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4356 06:51:45.861714 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4357 06:51:45.862240
4358 06:51:45.862585 [DATLAT]
4359 06:51:45.862901 Freq=600, CH0 RK1
4360 06:51:45.863209
4361 06:51:45.864928 DATLAT Default: 0x9
4362 06:51:45.865349 0, 0xFFFF, sum = 0
4363 06:51:45.868320 1, 0xFFFF, sum = 0
4364 06:51:45.871702 2, 0xFFFF, sum = 0
4365 06:51:45.872127 3, 0xFFFF, sum = 0
4366 06:51:45.875034 4, 0xFFFF, sum = 0
4367 06:51:45.875464 5, 0xFFFF, sum = 0
4368 06:51:45.878039 6, 0xFFFF, sum = 0
4369 06:51:45.878469 7, 0xFFFF, sum = 0
4370 06:51:45.881673 8, 0x0, sum = 1
4371 06:51:45.882115 9, 0x0, sum = 2
4372 06:51:45.882453 10, 0x0, sum = 3
4373 06:51:45.884831 11, 0x0, sum = 4
4374 06:51:45.885260 best_step = 9
4375 06:51:45.885731
4376 06:51:45.886068 ==
4377 06:51:45.888090 Dram Type= 6, Freq= 0, CH_0, rank 1
4378 06:51:45.894776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 06:51:45.895300 ==
4380 06:51:45.895633 RX Vref Scan: 0
4381 06:51:45.896170
4382 06:51:45.898365 RX Vref 0 -> 0, step: 1
4383 06:51:45.898789
4384 06:51:45.901842 RX Delay -195 -> 252, step: 8
4385 06:51:45.904762 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4386 06:51:45.911645 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4387 06:51:45.914713 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4388 06:51:45.918428 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4389 06:51:45.921432 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4390 06:51:45.927871 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4391 06:51:45.931443 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4392 06:51:45.935060 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4393 06:51:45.938014 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4394 06:51:45.941429 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4395 06:51:45.948380 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4396 06:51:45.951293 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4397 06:51:45.954411 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4398 06:51:45.958000 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4399 06:51:45.964887 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4400 06:51:45.968214 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4401 06:51:45.968737 ==
4402 06:51:45.971380 Dram Type= 6, Freq= 0, CH_0, rank 1
4403 06:51:45.974800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 06:51:45.975326 ==
4405 06:51:45.977926 DQS Delay:
4406 06:51:45.978451 DQS0 = 0, DQS1 = 0
4407 06:51:45.978787 DQM Delay:
4408 06:51:45.980974 DQM0 = 33, DQM1 = 27
4409 06:51:45.981393 DQ Delay:
4410 06:51:45.984421 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4411 06:51:45.988205 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4412 06:51:45.991530 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4413 06:51:45.994435 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4414 06:51:45.994958
4415 06:51:45.995288
4416 06:51:46.004540 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b39, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4417 06:51:46.007813 CH0 RK1: MR19=808, MR18=6B39
4418 06:51:46.011349 CH0_RK1: MR19=0x808, MR18=0x6B39, DQSOSC=389, MR23=63, INC=173, DEC=115
4419 06:51:46.014446 [RxdqsGatingPostProcess] freq 600
4420 06:51:46.021086 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4421 06:51:46.024055 Pre-setting of DQS Precalculation
4422 06:51:46.027390 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4423 06:51:46.027864 ==
4424 06:51:46.031288 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 06:51:46.037861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 06:51:46.038408 ==
4427 06:51:46.041150 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4428 06:51:46.047514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4429 06:51:46.050985 [CA 0] Center 36 (6~66) winsize 61
4430 06:51:46.054476 [CA 1] Center 36 (6~66) winsize 61
4431 06:51:46.058096 [CA 2] Center 34 (4~65) winsize 62
4432 06:51:46.061315 [CA 3] Center 34 (4~65) winsize 62
4433 06:51:46.064012 [CA 4] Center 34 (4~65) winsize 62
4434 06:51:46.067665 [CA 5] Center 34 (4~64) winsize 61
4435 06:51:46.068093
4436 06:51:46.070905 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4437 06:51:46.071442
4438 06:51:46.074215 [CATrainingPosCal] consider 1 rank data
4439 06:51:46.077315 u2DelayCellTimex100 = 270/100 ps
4440 06:51:46.080444 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4441 06:51:46.087199 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4442 06:51:46.090627 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4443 06:51:46.093953 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4444 06:51:46.096872 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4445 06:51:46.100219 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4446 06:51:46.101121
4447 06:51:46.103645 CA PerBit enable=1, Macro0, CA PI delay=34
4448 06:51:46.104491
4449 06:51:46.107205 [CBTSetCACLKResult] CA Dly = 34
4450 06:51:46.107669 CS Dly: 4 (0~35)
4451 06:51:46.110123 ==
4452 06:51:46.113598 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 06:51:46.117072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 06:51:46.117551 ==
4455 06:51:46.120236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4456 06:51:46.126403 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4457 06:51:46.130373 [CA 0] Center 35 (5~66) winsize 62
4458 06:51:46.133853 [CA 1] Center 36 (5~67) winsize 63
4459 06:51:46.137353 [CA 2] Center 34 (4~65) winsize 62
4460 06:51:46.140599 [CA 3] Center 34 (3~65) winsize 63
4461 06:51:46.143777 [CA 4] Center 34 (4~65) winsize 62
4462 06:51:46.147181 [CA 5] Center 34 (3~65) winsize 63
4463 06:51:46.147297
4464 06:51:46.150509 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4465 06:51:46.150613
4466 06:51:46.153875 [CATrainingPosCal] consider 2 rank data
4467 06:51:46.157092 u2DelayCellTimex100 = 270/100 ps
4468 06:51:46.160255 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4469 06:51:46.163727 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4470 06:51:46.170424 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4471 06:51:46.173948 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4472 06:51:46.177061 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4473 06:51:46.180239 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4474 06:51:46.180332
4475 06:51:46.183750 CA PerBit enable=1, Macro0, CA PI delay=34
4476 06:51:46.183842
4477 06:51:46.187050 [CBTSetCACLKResult] CA Dly = 34
4478 06:51:46.187143 CS Dly: 5 (0~37)
4479 06:51:46.187217
4480 06:51:46.193435 ----->DramcWriteLeveling(PI) begin...
4481 06:51:46.193559 ==
4482 06:51:46.196886 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 06:51:46.200277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 06:51:46.200398 ==
4485 06:51:46.203496 Write leveling (Byte 0): 31 => 31
4486 06:51:46.206829 Write leveling (Byte 1): 29 => 29
4487 06:51:46.210385 DramcWriteLeveling(PI) end<-----
4488 06:51:46.210800
4489 06:51:46.211135 ==
4490 06:51:46.213753 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 06:51:46.216900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 06:51:46.217327 ==
4493 06:51:46.220373 [Gating] SW mode calibration
4494 06:51:46.226842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4495 06:51:46.233260 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4496 06:51:46.236774 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4497 06:51:46.239740 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4498 06:51:46.246487 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4499 06:51:46.249656 0 9 12 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 1)
4500 06:51:46.253075 0 9 16 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
4501 06:51:46.259879 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 06:51:46.263437 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 06:51:46.266570 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 06:51:46.272924 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 06:51:46.276293 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 06:51:46.279638 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 06:51:46.286078 0 10 12 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 0)
4508 06:51:46.289400 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 06:51:46.292791 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 06:51:46.299722 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 06:51:46.303043 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 06:51:46.305722 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 06:51:46.312382 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 06:51:46.315784 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 06:51:46.319062 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4516 06:51:46.325630 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 06:51:46.328870 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 06:51:46.332550 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 06:51:46.338991 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 06:51:46.342093 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 06:51:46.345536 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 06:51:46.352445 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 06:51:46.355766 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 06:51:46.359163 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 06:51:46.365406 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 06:51:46.368986 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 06:51:46.372242 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 06:51:46.378603 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 06:51:46.382061 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 06:51:46.385218 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 06:51:46.391964 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 06:51:46.394995 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4533 06:51:46.398633 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4534 06:51:46.401864 Total UI for P1: 0, mck2ui 16
4535 06:51:46.405964 best dqsien dly found for B0: ( 0, 13, 16)
4536 06:51:46.408310 Total UI for P1: 0, mck2ui 16
4537 06:51:46.411687 best dqsien dly found for B1: ( 0, 13, 16)
4538 06:51:46.415351 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4539 06:51:46.418380 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4540 06:51:46.418912
4541 06:51:46.424735 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4542 06:51:46.428808 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4543 06:51:46.429345 [Gating] SW calibration Done
4544 06:51:46.431730 ==
4545 06:51:46.435185 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 06:51:46.438295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 06:51:46.438731 ==
4548 06:51:46.439076 RX Vref Scan: 0
4549 06:51:46.439401
4550 06:51:46.441591 RX Vref 0 -> 0, step: 1
4551 06:51:46.442024
4552 06:51:46.445373 RX Delay -230 -> 252, step: 16
4553 06:51:46.448362 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4554 06:51:46.451887 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4555 06:51:46.458073 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4556 06:51:46.461679 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4557 06:51:46.465085 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4558 06:51:46.468011 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4559 06:51:46.474449 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4560 06:51:46.478289 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4561 06:51:46.481239 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4562 06:51:46.484304 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4563 06:51:46.487736 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4564 06:51:46.494262 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4565 06:51:46.497929 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4566 06:51:46.501100 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4567 06:51:46.504293 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4568 06:51:46.511098 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4569 06:51:46.511632 ==
4570 06:51:46.514090 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 06:51:46.517855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 06:51:46.518382 ==
4573 06:51:46.518725 DQS Delay:
4574 06:51:46.520763 DQS0 = 0, DQS1 = 0
4575 06:51:46.521191 DQM Delay:
4576 06:51:46.524259 DQM0 = 37, DQM1 = 30
4577 06:51:46.524838 DQ Delay:
4578 06:51:46.527660 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4579 06:51:46.531433 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4580 06:51:46.533892 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4581 06:51:46.537709 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =33
4582 06:51:46.538231
4583 06:51:46.538576
4584 06:51:46.538896 ==
4585 06:51:46.540757 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 06:51:46.547790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 06:51:46.548322 ==
4588 06:51:46.548670
4589 06:51:46.548989
4590 06:51:46.549295 TX Vref Scan disable
4591 06:51:46.550689 == TX Byte 0 ==
4592 06:51:46.554242 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4593 06:51:46.557407 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4594 06:51:46.560763 == TX Byte 1 ==
4595 06:51:46.564139 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4596 06:51:46.570471 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4597 06:51:46.570996 ==
4598 06:51:46.573951 Dram Type= 6, Freq= 0, CH_1, rank 0
4599 06:51:46.577388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 06:51:46.577988 ==
4601 06:51:46.578338
4602 06:51:46.578660
4603 06:51:46.580429 TX Vref Scan disable
4604 06:51:46.583457 == TX Byte 0 ==
4605 06:51:46.587005 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4606 06:51:46.590201 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4607 06:51:46.593694 == TX Byte 1 ==
4608 06:51:46.596641 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4609 06:51:46.600503 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4610 06:51:46.601032
4611 06:51:46.601372 [DATLAT]
4612 06:51:46.603240 Freq=600, CH1 RK0
4613 06:51:46.603671
4614 06:51:46.606713 DATLAT Default: 0x9
4615 06:51:46.607143 0, 0xFFFF, sum = 0
4616 06:51:46.609975 1, 0xFFFF, sum = 0
4617 06:51:46.610435 2, 0xFFFF, sum = 0
4618 06:51:46.613430 3, 0xFFFF, sum = 0
4619 06:51:46.614052 4, 0xFFFF, sum = 0
4620 06:51:46.616513 5, 0xFFFF, sum = 0
4621 06:51:46.616948 6, 0xFFFF, sum = 0
4622 06:51:46.619922 7, 0xFFFF, sum = 0
4623 06:51:46.620529 8, 0x0, sum = 1
4624 06:51:46.623491 9, 0x0, sum = 2
4625 06:51:46.623926 10, 0x0, sum = 3
4626 06:51:46.626715 11, 0x0, sum = 4
4627 06:51:46.627162 best_step = 9
4628 06:51:46.627507
4629 06:51:46.627823 ==
4630 06:51:46.629790 Dram Type= 6, Freq= 0, CH_1, rank 0
4631 06:51:46.632952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 06:51:46.633406 ==
4633 06:51:46.636806 RX Vref Scan: 1
4634 06:51:46.637333
4635 06:51:46.639577 RX Vref 0 -> 0, step: 1
4636 06:51:46.640007
4637 06:51:46.640347 RX Delay -195 -> 252, step: 8
4638 06:51:46.640671
4639 06:51:46.643148 Set Vref, RX VrefLevel [Byte0]: 57
4640 06:51:46.646750 [Byte1]: 53
4641 06:51:46.651599
4642 06:51:46.652118 Final RX Vref Byte 0 = 57 to rank0
4643 06:51:46.654626 Final RX Vref Byte 1 = 53 to rank0
4644 06:51:46.658080 Final RX Vref Byte 0 = 57 to rank1
4645 06:51:46.661151 Final RX Vref Byte 1 = 53 to rank1==
4646 06:51:46.664594 Dram Type= 6, Freq= 0, CH_1, rank 0
4647 06:51:46.670883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 06:51:46.671414 ==
4649 06:51:46.671893 DQS Delay:
4650 06:51:46.672354 DQS0 = 0, DQS1 = 0
4651 06:51:46.674698 DQM Delay:
4652 06:51:46.675222 DQM0 = 39, DQM1 = 28
4653 06:51:46.678213 DQ Delay:
4654 06:51:46.680990 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =36
4655 06:51:46.684387 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4656 06:51:46.688178 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4657 06:51:46.690940 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4658 06:51:46.691471
4659 06:51:46.691810
4660 06:51:46.697781 [DQSOSCAuto] RK0, (LSB)MR18= 0x2330, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4661 06:51:46.701177 CH1 RK0: MR19=808, MR18=2330
4662 06:51:46.707456 CH1_RK0: MR19=0x808, MR18=0x2330, DQSOSC=400, MR23=63, INC=163, DEC=109
4663 06:51:46.707975
4664 06:51:46.710772 ----->DramcWriteLeveling(PI) begin...
4665 06:51:46.711202 ==
4666 06:51:46.714048 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 06:51:46.717647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 06:51:46.718177 ==
4669 06:51:46.720556 Write leveling (Byte 0): 29 => 29
4670 06:51:46.724015 Write leveling (Byte 1): 30 => 30
4671 06:51:46.727822 DramcWriteLeveling(PI) end<-----
4672 06:51:46.728243
4673 06:51:46.728713 ==
4674 06:51:46.730575 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 06:51:46.733715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 06:51:46.734138 ==
4677 06:51:46.737089 [Gating] SW mode calibration
4678 06:51:46.743885 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4679 06:51:46.750204 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4680 06:51:46.753962 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4681 06:51:46.760623 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4682 06:51:46.763925 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4683 06:51:46.767012 0 9 12 | B1->B0 | 3131 2d2d | 1 1 | (1 0) (1 0)
4684 06:51:46.774057 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
4685 06:51:46.777007 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 06:51:46.780585 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 06:51:46.787198 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 06:51:46.790078 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 06:51:46.793923 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 06:51:46.800531 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4691 06:51:46.803451 0 10 12 | B1->B0 | 3030 4342 | 0 1 | (0 0) (0 0)
4692 06:51:46.806808 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
4693 06:51:46.813767 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 06:51:46.817104 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 06:51:46.820460 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 06:51:46.826715 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 06:51:46.829987 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 06:51:46.833402 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 06:51:46.836752 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 06:51:46.843250 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4701 06:51:46.846366 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 06:51:46.849872 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 06:51:46.856510 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 06:51:46.860004 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 06:51:46.863136 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 06:51:46.870249 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 06:51:46.873238 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 06:51:46.877164 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 06:51:46.883003 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 06:51:46.886329 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 06:51:46.889792 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 06:51:46.896272 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 06:51:46.899648 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 06:51:46.902890 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 06:51:46.909812 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 06:51:46.912717 Total UI for P1: 0, mck2ui 16
4717 06:51:46.916327 best dqsien dly found for B0: ( 0, 13, 10)
4718 06:51:46.916859 Total UI for P1: 0, mck2ui 16
4719 06:51:46.923001 best dqsien dly found for B1: ( 0, 13, 10)
4720 06:51:46.926010 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4721 06:51:46.929967 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4722 06:51:46.930561
4723 06:51:46.932840 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4724 06:51:46.936420 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4725 06:51:46.939245 [Gating] SW calibration Done
4726 06:51:46.939679 ==
4727 06:51:46.942778 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 06:51:46.946239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 06:51:46.946769 ==
4730 06:51:46.949677 RX Vref Scan: 0
4731 06:51:46.950205
4732 06:51:46.950550 RX Vref 0 -> 0, step: 1
4733 06:51:46.952732
4734 06:51:46.953254 RX Delay -230 -> 252, step: 16
4735 06:51:46.959134 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4736 06:51:46.962211 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4737 06:51:46.965855 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4738 06:51:46.969058 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4739 06:51:46.976010 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4740 06:51:46.979055 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4741 06:51:46.982413 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4742 06:51:46.985746 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4743 06:51:46.989907 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4744 06:51:46.996030 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4745 06:51:46.999280 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4746 06:51:47.002372 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4747 06:51:47.005750 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4748 06:51:47.012513 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4749 06:51:47.015648 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4750 06:51:47.018797 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4751 06:51:47.019223 ==
4752 06:51:47.022098 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 06:51:47.025546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 06:51:47.028676 ==
4755 06:51:47.029100 DQS Delay:
4756 06:51:47.029433 DQS0 = 0, DQS1 = 0
4757 06:51:47.032319 DQM Delay:
4758 06:51:47.032838 DQM0 = 35, DQM1 = 29
4759 06:51:47.035549 DQ Delay:
4760 06:51:47.036062 DQ0 =33, DQ1 =33, DQ2 =25, DQ3 =33
4761 06:51:47.038755 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4762 06:51:47.041835 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4763 06:51:47.045637 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4764 06:51:47.046162
4765 06:51:47.048943
4766 06:51:47.049460 ==
4767 06:51:47.052372 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 06:51:47.055714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 06:51:47.056243 ==
4770 06:51:47.056586
4771 06:51:47.056898
4772 06:51:47.058536 TX Vref Scan disable
4773 06:51:47.058959 == TX Byte 0 ==
4774 06:51:47.065528 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4775 06:51:47.068371 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4776 06:51:47.068804 == TX Byte 1 ==
4777 06:51:47.075320 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4778 06:51:47.078557 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4779 06:51:47.079157 ==
4780 06:51:47.081707 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 06:51:47.085147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 06:51:47.085728 ==
4783 06:51:47.086078
4784 06:51:47.086396
4785 06:51:47.088089 TX Vref Scan disable
4786 06:51:47.091283 == TX Byte 0 ==
4787 06:51:47.094857 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4788 06:51:47.098045 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4789 06:51:47.101806 == TX Byte 1 ==
4790 06:51:47.104997 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4791 06:51:47.111434 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4792 06:51:47.111999
4793 06:51:47.112351 [DATLAT]
4794 06:51:47.112669 Freq=600, CH1 RK1
4795 06:51:47.112972
4796 06:51:47.114758 DATLAT Default: 0x9
4797 06:51:47.115187 0, 0xFFFF, sum = 0
4798 06:51:47.118002 1, 0xFFFF, sum = 0
4799 06:51:47.118541 2, 0xFFFF, sum = 0
4800 06:51:47.121446 3, 0xFFFF, sum = 0
4801 06:51:47.124730 4, 0xFFFF, sum = 0
4802 06:51:47.125258 5, 0xFFFF, sum = 0
4803 06:51:47.127815 6, 0xFFFF, sum = 0
4804 06:51:47.128275 7, 0xFFFF, sum = 0
4805 06:51:47.131033 8, 0x0, sum = 1
4806 06:51:47.131461 9, 0x0, sum = 2
4807 06:51:47.131851 10, 0x0, sum = 3
4808 06:51:47.134449 11, 0x0, sum = 4
4809 06:51:47.134880 best_step = 9
4810 06:51:47.135210
4811 06:51:47.135520 ==
4812 06:51:47.137755 Dram Type= 6, Freq= 0, CH_1, rank 1
4813 06:51:47.144780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4814 06:51:47.145311 ==
4815 06:51:47.145691 RX Vref Scan: 0
4816 06:51:47.146008
4817 06:51:47.148122 RX Vref 0 -> 0, step: 1
4818 06:51:47.148650
4819 06:51:47.151566 RX Delay -195 -> 252, step: 8
4820 06:51:47.154530 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4821 06:51:47.161317 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4822 06:51:47.164051 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4823 06:51:47.167665 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4824 06:51:47.171050 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4825 06:51:47.177735 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4826 06:51:47.181012 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4827 06:51:47.184149 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4828 06:51:47.187694 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4829 06:51:47.190628 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4830 06:51:47.197382 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4831 06:51:47.200418 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4832 06:51:47.203982 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4833 06:51:47.207168 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4834 06:51:47.213951 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4835 06:51:47.217149 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4836 06:51:47.217614 ==
4837 06:51:47.220777 Dram Type= 6, Freq= 0, CH_1, rank 1
4838 06:51:47.223819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4839 06:51:47.224251 ==
4840 06:51:47.227432 DQS Delay:
4841 06:51:47.227864 DQS0 = 0, DQS1 = 0
4842 06:51:47.228223 DQM Delay:
4843 06:51:47.230680 DQM0 = 36, DQM1 = 30
4844 06:51:47.231110 DQ Delay:
4845 06:51:47.233789 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4846 06:51:47.237801 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =36
4847 06:51:47.240681 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4848 06:51:47.244077 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4849 06:51:47.244607
4850 06:51:47.244951
4851 06:51:47.254177 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4852 06:51:47.256894 CH1 RK1: MR19=808, MR18=3B5C
4853 06:51:47.260395 CH1_RK1: MR19=0x808, MR18=0x3B5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4854 06:51:47.263838 [RxdqsGatingPostProcess] freq 600
4855 06:51:47.270363 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4856 06:51:47.273758 Pre-setting of DQS Precalculation
4857 06:51:47.276882 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4858 06:51:47.287175 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4859 06:51:47.293445 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4860 06:51:47.293916
4861 06:51:47.294257
4862 06:51:47.296666 [Calibration Summary] 1200 Mbps
4863 06:51:47.297089 CH 0, Rank 0
4864 06:51:47.300088 SW Impedance : PASS
4865 06:51:47.300512 DUTY Scan : NO K
4866 06:51:47.303428 ZQ Calibration : PASS
4867 06:51:47.306391 Jitter Meter : NO K
4868 06:51:47.306824 CBT Training : PASS
4869 06:51:47.310034 Write leveling : PASS
4870 06:51:47.313339 RX DQS gating : PASS
4871 06:51:47.313904 RX DQ/DQS(RDDQC) : PASS
4872 06:51:47.316905 TX DQ/DQS : PASS
4873 06:51:47.320301 RX DATLAT : PASS
4874 06:51:47.320875 RX DQ/DQS(Engine): PASS
4875 06:51:47.323133 TX OE : NO K
4876 06:51:47.323566 All Pass.
4877 06:51:47.323906
4878 06:51:47.326458 CH 0, Rank 1
4879 06:51:47.326887 SW Impedance : PASS
4880 06:51:47.329804 DUTY Scan : NO K
4881 06:51:47.332876 ZQ Calibration : PASS
4882 06:51:47.333306 Jitter Meter : NO K
4883 06:51:47.336557 CBT Training : PASS
4884 06:51:47.339956 Write leveling : PASS
4885 06:51:47.340480 RX DQS gating : PASS
4886 06:51:47.343118 RX DQ/DQS(RDDQC) : PASS
4887 06:51:47.343643 TX DQ/DQS : PASS
4888 06:51:47.346488 RX DATLAT : PASS
4889 06:51:47.349588 RX DQ/DQS(Engine): PASS
4890 06:51:47.350033 TX OE : NO K
4891 06:51:47.352848 All Pass.
4892 06:51:47.353369
4893 06:51:47.353753 CH 1, Rank 0
4894 06:51:47.356106 SW Impedance : PASS
4895 06:51:47.356532 DUTY Scan : NO K
4896 06:51:47.359844 ZQ Calibration : PASS
4897 06:51:47.363306 Jitter Meter : NO K
4898 06:51:47.363833 CBT Training : PASS
4899 06:51:47.366067 Write leveling : PASS
4900 06:51:47.369746 RX DQS gating : PASS
4901 06:51:47.370275 RX DQ/DQS(RDDQC) : PASS
4902 06:51:47.373142 TX DQ/DQS : PASS
4903 06:51:47.376668 RX DATLAT : PASS
4904 06:51:47.377195 RX DQ/DQS(Engine): PASS
4905 06:51:47.379583 TX OE : NO K
4906 06:51:47.380113 All Pass.
4907 06:51:47.380457
4908 06:51:47.382707 CH 1, Rank 1
4909 06:51:47.383212 SW Impedance : PASS
4910 06:51:47.386233 DUTY Scan : NO K
4911 06:51:47.389640 ZQ Calibration : PASS
4912 06:51:47.390163 Jitter Meter : NO K
4913 06:51:47.392710 CBT Training : PASS
4914 06:51:47.396339 Write leveling : PASS
4915 06:51:47.396866 RX DQS gating : PASS
4916 06:51:47.399665 RX DQ/DQS(RDDQC) : PASS
4917 06:51:47.400192 TX DQ/DQS : PASS
4918 06:51:47.402943 RX DATLAT : PASS
4919 06:51:47.406171 RX DQ/DQS(Engine): PASS
4920 06:51:47.406674 TX OE : NO K
4921 06:51:47.409197 All Pass.
4922 06:51:47.409767
4923 06:51:47.410117 DramC Write-DBI off
4924 06:51:47.412489 PER_BANK_REFRESH: Hybrid Mode
4925 06:51:47.415905 TX_TRACKING: ON
4926 06:51:47.422523 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4927 06:51:47.425883 [FAST_K] Save calibration result to emmc
4928 06:51:47.429194 dramc_set_vcore_voltage set vcore to 662500
4929 06:51:47.432842 Read voltage for 933, 3
4930 06:51:47.433552 Vio18 = 0
4931 06:51:47.436155 Vcore = 662500
4932 06:51:47.436683 Vdram = 0
4933 06:51:47.437025 Vddq = 0
4934 06:51:47.439444 Vmddr = 0
4935 06:51:47.442727 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4936 06:51:47.449599 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4937 06:51:47.450144 MEM_TYPE=3, freq_sel=17
4938 06:51:47.452581 sv_algorithm_assistance_LP4_1600
4939 06:51:47.459053 ============ PULL DRAM RESETB DOWN ============
4940 06:51:47.462366 ========== PULL DRAM RESETB DOWN end =========
4941 06:51:47.466263 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4942 06:51:47.468969 ===================================
4943 06:51:47.472699 LPDDR4 DRAM CONFIGURATION
4944 06:51:47.475782 ===================================
4945 06:51:47.479034 EX_ROW_EN[0] = 0x0
4946 06:51:47.479564 EX_ROW_EN[1] = 0x0
4947 06:51:47.482398 LP4Y_EN = 0x0
4948 06:51:47.482924 WORK_FSP = 0x0
4949 06:51:47.485621 WL = 0x3
4950 06:51:47.486141 RL = 0x3
4951 06:51:47.488769 BL = 0x2
4952 06:51:47.489194 RPST = 0x0
4953 06:51:47.492542 RD_PRE = 0x0
4954 06:51:47.493154 WR_PRE = 0x1
4955 06:51:47.495264 WR_PST = 0x0
4956 06:51:47.495688 DBI_WR = 0x0
4957 06:51:47.498875 DBI_RD = 0x0
4958 06:51:47.499402 OTF = 0x1
4959 06:51:47.502425 ===================================
4960 06:51:47.505683 ===================================
4961 06:51:47.508465 ANA top config
4962 06:51:47.511780 ===================================
4963 06:51:47.515262 DLL_ASYNC_EN = 0
4964 06:51:47.515687 ALL_SLAVE_EN = 1
4965 06:51:47.518342 NEW_RANK_MODE = 1
4966 06:51:47.521968 DLL_IDLE_MODE = 1
4967 06:51:47.525286 LP45_APHY_COMB_EN = 1
4968 06:51:47.525750 TX_ODT_DIS = 1
4969 06:51:47.528560 NEW_8X_MODE = 1
4970 06:51:47.531914 ===================================
4971 06:51:47.535215 ===================================
4972 06:51:47.538334 data_rate = 1866
4973 06:51:47.541651 CKR = 1
4974 06:51:47.545059 DQ_P2S_RATIO = 8
4975 06:51:47.548480 ===================================
4976 06:51:47.551839 CA_P2S_RATIO = 8
4977 06:51:47.552384 DQ_CA_OPEN = 0
4978 06:51:47.555272 DQ_SEMI_OPEN = 0
4979 06:51:47.558012 CA_SEMI_OPEN = 0
4980 06:51:47.561580 CA_FULL_RATE = 0
4981 06:51:47.565023 DQ_CKDIV4_EN = 1
4982 06:51:47.568061 CA_CKDIV4_EN = 1
4983 06:51:47.571498 CA_PREDIV_EN = 0
4984 06:51:47.572021 PH8_DLY = 0
4985 06:51:47.574811 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4986 06:51:47.578163 DQ_AAMCK_DIV = 4
4987 06:51:47.581324 CA_AAMCK_DIV = 4
4988 06:51:47.585037 CA_ADMCK_DIV = 4
4989 06:51:47.585614 DQ_TRACK_CA_EN = 0
4990 06:51:47.587978 CA_PICK = 933
4991 06:51:47.591316 CA_MCKIO = 933
4992 06:51:47.595052 MCKIO_SEMI = 0
4993 06:51:47.598429 PLL_FREQ = 3732
4994 06:51:47.601418 DQ_UI_PI_RATIO = 32
4995 06:51:47.605036 CA_UI_PI_RATIO = 0
4996 06:51:47.608154 ===================================
4997 06:51:47.611119 ===================================
4998 06:51:47.611553 memory_type:LPDDR4
4999 06:51:47.614777 GP_NUM : 10
5000 06:51:47.618155 SRAM_EN : 1
5001 06:51:47.618693 MD32_EN : 0
5002 06:51:47.621434 ===================================
5003 06:51:47.624781 [ANA_INIT] >>>>>>>>>>>>>>
5004 06:51:47.627804 <<<<<< [CONFIGURE PHASE]: ANA_TX
5005 06:51:47.631078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5006 06:51:47.634324 ===================================
5007 06:51:47.637750 data_rate = 1866,PCW = 0X8f00
5008 06:51:47.641043 ===================================
5009 06:51:47.644774 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5010 06:51:47.647766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5011 06:51:47.654581 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5012 06:51:47.657541 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5013 06:51:47.660949 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5014 06:51:47.664184 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5015 06:51:47.667524 [ANA_INIT] flow start
5016 06:51:47.671132 [ANA_INIT] PLL >>>>>>>>
5017 06:51:47.671661 [ANA_INIT] PLL <<<<<<<<
5018 06:51:47.674278 [ANA_INIT] MIDPI >>>>>>>>
5019 06:51:47.678170 [ANA_INIT] MIDPI <<<<<<<<
5020 06:51:47.681001 [ANA_INIT] DLL >>>>>>>>
5021 06:51:47.681465 [ANA_INIT] flow end
5022 06:51:47.684435 ============ LP4 DIFF to SE enter ============
5023 06:51:47.691065 ============ LP4 DIFF to SE exit ============
5024 06:51:47.691514 [ANA_INIT] <<<<<<<<<<<<<
5025 06:51:47.694120 [Flow] Enable top DCM control >>>>>
5026 06:51:47.697632 [Flow] Enable top DCM control <<<<<
5027 06:51:47.700958 Enable DLL master slave shuffle
5028 06:51:47.707758 ==============================================================
5029 06:51:47.708307 Gating Mode config
5030 06:51:47.714404 ==============================================================
5031 06:51:47.717155 Config description:
5032 06:51:47.727489 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5033 06:51:47.733988 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5034 06:51:47.737309 SELPH_MODE 0: By rank 1: By Phase
5035 06:51:47.744078 ==============================================================
5036 06:51:47.747426 GAT_TRACK_EN = 1
5037 06:51:47.748058 RX_GATING_MODE = 2
5038 06:51:47.750371 RX_GATING_TRACK_MODE = 2
5039 06:51:47.754179 SELPH_MODE = 1
5040 06:51:47.757522 PICG_EARLY_EN = 1
5041 06:51:47.760888 VALID_LAT_VALUE = 1
5042 06:51:47.767236 ==============================================================
5043 06:51:47.770774 Enter into Gating configuration >>>>
5044 06:51:47.773903 Exit from Gating configuration <<<<
5045 06:51:47.777211 Enter into DVFS_PRE_config >>>>>
5046 06:51:47.786912 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5047 06:51:47.790229 Exit from DVFS_PRE_config <<<<<
5048 06:51:47.793373 Enter into PICG configuration >>>>
5049 06:51:47.796629 Exit from PICG configuration <<<<
5050 06:51:47.800317 [RX_INPUT] configuration >>>>>
5051 06:51:47.803522 [RX_INPUT] configuration <<<<<
5052 06:51:47.806906 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5053 06:51:47.813441 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5054 06:51:47.820153 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5055 06:51:47.826412 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5056 06:51:47.829857 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5057 06:51:47.836721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5058 06:51:47.840226 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5059 06:51:47.847142 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5060 06:51:47.850401 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5061 06:51:47.853831 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5062 06:51:47.856865 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5063 06:51:47.863395 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5064 06:51:47.866922 ===================================
5065 06:51:47.867449 LPDDR4 DRAM CONFIGURATION
5066 06:51:47.869680 ===================================
5067 06:51:47.873441 EX_ROW_EN[0] = 0x0
5068 06:51:47.876809 EX_ROW_EN[1] = 0x0
5069 06:51:47.877339 LP4Y_EN = 0x0
5070 06:51:47.880192 WORK_FSP = 0x0
5071 06:51:47.880717 WL = 0x3
5072 06:51:47.883527 RL = 0x3
5073 06:51:47.883957 BL = 0x2
5074 06:51:47.886824 RPST = 0x0
5075 06:51:47.887354 RD_PRE = 0x0
5076 06:51:47.889974 WR_PRE = 0x1
5077 06:51:47.890403 WR_PST = 0x0
5078 06:51:47.893286 DBI_WR = 0x0
5079 06:51:47.893819 DBI_RD = 0x0
5080 06:51:47.896281 OTF = 0x1
5081 06:51:47.899660 ===================================
5082 06:51:47.903303 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5083 06:51:47.906505 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5084 06:51:47.913231 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5085 06:51:47.916247 ===================================
5086 06:51:47.916796 LPDDR4 DRAM CONFIGURATION
5087 06:51:47.919510 ===================================
5088 06:51:47.922987 EX_ROW_EN[0] = 0x10
5089 06:51:47.926188 EX_ROW_EN[1] = 0x0
5090 06:51:47.926662 LP4Y_EN = 0x0
5091 06:51:47.929813 WORK_FSP = 0x0
5092 06:51:47.930338 WL = 0x3
5093 06:51:47.932950 RL = 0x3
5094 06:51:47.933379 BL = 0x2
5095 06:51:47.936189 RPST = 0x0
5096 06:51:47.936621 RD_PRE = 0x0
5097 06:51:47.939706 WR_PRE = 0x1
5098 06:51:47.940246 WR_PST = 0x0
5099 06:51:47.942739 DBI_WR = 0x0
5100 06:51:47.943170 DBI_RD = 0x0
5101 06:51:47.946288 OTF = 0x1
5102 06:51:47.949606 ===================================
5103 06:51:47.956222 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5104 06:51:47.959626 nWR fixed to 30
5105 06:51:47.960155 [ModeRegInit_LP4] CH0 RK0
5106 06:51:47.962646 [ModeRegInit_LP4] CH0 RK1
5107 06:51:47.966227 [ModeRegInit_LP4] CH1 RK0
5108 06:51:47.969681 [ModeRegInit_LP4] CH1 RK1
5109 06:51:47.970213 match AC timing 9
5110 06:51:47.975891 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5111 06:51:47.979560 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5112 06:51:47.982843 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5113 06:51:47.989556 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5114 06:51:47.992570 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5115 06:51:47.993004 ==
5116 06:51:47.996288 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 06:51:47.999431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 06:51:47.999867 ==
5119 06:51:48.006044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5120 06:51:48.012571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5121 06:51:48.015790 [CA 0] Center 38 (8~69) winsize 62
5122 06:51:48.019213 [CA 1] Center 38 (8~69) winsize 62
5123 06:51:48.022329 [CA 2] Center 35 (5~65) winsize 61
5124 06:51:48.026008 [CA 3] Center 35 (5~65) winsize 61
5125 06:51:48.029241 [CA 4] Center 34 (4~64) winsize 61
5126 06:51:48.032083 [CA 5] Center 33 (3~64) winsize 62
5127 06:51:48.032639
5128 06:51:48.035892 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5129 06:51:48.036420
5130 06:51:48.039376 [CATrainingPosCal] consider 1 rank data
5131 06:51:48.042437 u2DelayCellTimex100 = 270/100 ps
5132 06:51:48.045708 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5133 06:51:48.048771 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5134 06:51:48.052424 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5135 06:51:48.055892 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5136 06:51:48.058963 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5137 06:51:48.062172 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5138 06:51:48.062600
5139 06:51:48.069169 CA PerBit enable=1, Macro0, CA PI delay=33
5140 06:51:48.069795
5141 06:51:48.072346 [CBTSetCACLKResult] CA Dly = 33
5142 06:51:48.072870 CS Dly: 7 (0~38)
5143 06:51:48.073214 ==
5144 06:51:48.076094 Dram Type= 6, Freq= 0, CH_0, rank 1
5145 06:51:48.078946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 06:51:48.079473 ==
5147 06:51:48.085109 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5148 06:51:48.092267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5149 06:51:48.095534 [CA 0] Center 38 (8~69) winsize 62
5150 06:51:48.098578 [CA 1] Center 38 (8~69) winsize 62
5151 06:51:48.101808 [CA 2] Center 35 (5~66) winsize 62
5152 06:51:48.105242 [CA 3] Center 35 (5~66) winsize 62
5153 06:51:48.108395 [CA 4] Center 34 (4~65) winsize 62
5154 06:51:48.111825 [CA 5] Center 34 (3~65) winsize 63
5155 06:51:48.112353
5156 06:51:48.115063 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5157 06:51:48.115590
5158 06:51:48.118267 [CATrainingPosCal] consider 2 rank data
5159 06:51:48.121650 u2DelayCellTimex100 = 270/100 ps
5160 06:51:48.125193 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5161 06:51:48.127960 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5162 06:51:48.131521 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5163 06:51:48.134888 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5164 06:51:48.141593 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5165 06:51:48.145276 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5166 06:51:48.145859
5167 06:51:48.148139 CA PerBit enable=1, Macro0, CA PI delay=33
5168 06:51:48.148667
5169 06:51:48.151596 [CBTSetCACLKResult] CA Dly = 33
5170 06:51:48.152121 CS Dly: 7 (0~38)
5171 06:51:48.152460
5172 06:51:48.154821 ----->DramcWriteLeveling(PI) begin...
5173 06:51:48.155359 ==
5174 06:51:48.158416 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 06:51:48.164792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 06:51:48.165321 ==
5177 06:51:48.167958 Write leveling (Byte 0): 31 => 31
5178 06:51:48.171358 Write leveling (Byte 1): 31 => 31
5179 06:51:48.171885 DramcWriteLeveling(PI) end<-----
5180 06:51:48.172227
5181 06:51:48.174362 ==
5182 06:51:48.178174 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 06:51:48.181305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 06:51:48.181863 ==
5185 06:51:48.184590 [Gating] SW mode calibration
5186 06:51:48.191242 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5187 06:51:48.194385 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5188 06:51:48.200877 0 14 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5189 06:51:48.204438 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5190 06:51:48.207402 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 06:51:48.214356 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 06:51:48.217805 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 06:51:48.220835 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 06:51:48.227254 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 06:51:48.230723 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5196 06:51:48.233596 0 15 0 | B1->B0 | 3232 2727 | 1 0 | (1 0) (0 0)
5197 06:51:48.240961 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 06:51:48.243903 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 06:51:48.247356 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 06:51:48.254124 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 06:51:48.257293 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 06:51:48.260707 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 06:51:48.267002 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5204 06:51:48.270274 1 0 0 | B1->B0 | 2f2f 3d3d | 0 1 | (0 0) (0 0)
5205 06:51:48.273854 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5206 06:51:48.280735 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 06:51:48.283543 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 06:51:48.287023 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 06:51:48.293394 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 06:51:48.297108 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 06:51:48.300230 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5212 06:51:48.306831 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5213 06:51:48.310137 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5214 06:51:48.313577 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 06:51:48.319879 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 06:51:48.323378 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 06:51:48.326496 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 06:51:48.333084 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 06:51:48.336313 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 06:51:48.339716 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 06:51:48.346530 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 06:51:48.349642 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 06:51:48.352810 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 06:51:48.359826 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 06:51:48.363536 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 06:51:48.366225 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 06:51:48.373297 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5228 06:51:48.376863 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5229 06:51:48.379909 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5230 06:51:48.382862 Total UI for P1: 0, mck2ui 16
5231 06:51:48.386241 best dqsien dly found for B0: ( 1, 2, 30)
5232 06:51:48.389725 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5233 06:51:48.392626 Total UI for P1: 0, mck2ui 16
5234 06:51:48.396035 best dqsien dly found for B1: ( 1, 3, 4)
5235 06:51:48.402870 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5236 06:51:48.405910 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5237 06:51:48.406439
5238 06:51:48.409255 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5239 06:51:48.412994 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5240 06:51:48.416221 [Gating] SW calibration Done
5241 06:51:48.416749 ==
5242 06:51:48.419090 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 06:51:48.422250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 06:51:48.422674 ==
5245 06:51:48.426069 RX Vref Scan: 0
5246 06:51:48.426592
5247 06:51:48.426942 RX Vref 0 -> 0, step: 1
5248 06:51:48.427257
5249 06:51:48.428930 RX Delay -80 -> 252, step: 8
5250 06:51:48.432600 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5251 06:51:48.435575 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5252 06:51:48.442458 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5253 06:51:48.445405 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5254 06:51:48.448886 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5255 06:51:48.452347 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5256 06:51:48.455815 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5257 06:51:48.459033 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5258 06:51:48.465245 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5259 06:51:48.468815 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5260 06:51:48.472264 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5261 06:51:48.475649 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5262 06:51:48.482356 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5263 06:51:48.485563 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5264 06:51:48.488529 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5265 06:51:48.491999 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5266 06:51:48.492530 ==
5267 06:51:48.495253 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 06:51:48.498729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 06:51:48.502102 ==
5270 06:51:48.502645 DQS Delay:
5271 06:51:48.502999 DQS0 = 0, DQS1 = 0
5272 06:51:48.505333 DQM Delay:
5273 06:51:48.505959 DQM0 = 94, DQM1 = 83
5274 06:51:48.508780 DQ Delay:
5275 06:51:48.509306 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5276 06:51:48.511797 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5277 06:51:48.515277 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5278 06:51:48.518344 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =91
5279 06:51:48.521863
5280 06:51:48.522459
5281 06:51:48.522806 ==
5282 06:51:48.525035 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 06:51:48.528549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 06:51:48.528984 ==
5285 06:51:48.529327
5286 06:51:48.529704
5287 06:51:48.531888 TX Vref Scan disable
5288 06:51:48.532319 == TX Byte 0 ==
5289 06:51:48.538411 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5290 06:51:48.541654 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5291 06:51:48.542187 == TX Byte 1 ==
5292 06:51:48.548221 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5293 06:51:48.551449 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5294 06:51:48.551974 ==
5295 06:51:48.555094 Dram Type= 6, Freq= 0, CH_0, rank 0
5296 06:51:48.558261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 06:51:48.558697 ==
5298 06:51:48.559039
5299 06:51:48.559358
5300 06:51:48.561607 TX Vref Scan disable
5301 06:51:48.565012 == TX Byte 0 ==
5302 06:51:48.568417 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5303 06:51:48.571460 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5304 06:51:48.574916 == TX Byte 1 ==
5305 06:51:48.578098 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5306 06:51:48.581875 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5307 06:51:48.582405
5308 06:51:48.584942 [DATLAT]
5309 06:51:48.585512 Freq=933, CH0 RK0
5310 06:51:48.585885
5311 06:51:48.588023 DATLAT Default: 0xd
5312 06:51:48.588552 0, 0xFFFF, sum = 0
5313 06:51:48.591094 1, 0xFFFF, sum = 0
5314 06:51:48.591533 2, 0xFFFF, sum = 0
5315 06:51:48.594514 3, 0xFFFF, sum = 0
5316 06:51:48.594951 4, 0xFFFF, sum = 0
5317 06:51:48.597661 5, 0xFFFF, sum = 0
5318 06:51:48.598095 6, 0xFFFF, sum = 0
5319 06:51:48.601456 7, 0xFFFF, sum = 0
5320 06:51:48.602018 8, 0xFFFF, sum = 0
5321 06:51:48.604701 9, 0xFFFF, sum = 0
5322 06:51:48.605240 10, 0x0, sum = 1
5323 06:51:48.607862 11, 0x0, sum = 2
5324 06:51:48.608399 12, 0x0, sum = 3
5325 06:51:48.611137 13, 0x0, sum = 4
5326 06:51:48.611575 best_step = 11
5327 06:51:48.611913
5328 06:51:48.612229 ==
5329 06:51:48.614256 Dram Type= 6, Freq= 0, CH_0, rank 0
5330 06:51:48.621089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 06:51:48.621662 ==
5332 06:51:48.622015 RX Vref Scan: 1
5333 06:51:48.622394
5334 06:51:48.624635 RX Vref 0 -> 0, step: 1
5335 06:51:48.625164
5336 06:51:48.627805 RX Delay -69 -> 252, step: 4
5337 06:51:48.628332
5338 06:51:48.631232 Set Vref, RX VrefLevel [Byte0]: 61
5339 06:51:48.634166 [Byte1]: 53
5340 06:51:48.634608
5341 06:51:48.637318 Final RX Vref Byte 0 = 61 to rank0
5342 06:51:48.641095 Final RX Vref Byte 1 = 53 to rank0
5343 06:51:48.644539 Final RX Vref Byte 0 = 61 to rank1
5344 06:51:48.647897 Final RX Vref Byte 1 = 53 to rank1==
5345 06:51:48.650849 Dram Type= 6, Freq= 0, CH_0, rank 0
5346 06:51:48.654124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 06:51:48.654686 ==
5348 06:51:48.657431 DQS Delay:
5349 06:51:48.658005 DQS0 = 0, DQS1 = 0
5350 06:51:48.661144 DQM Delay:
5351 06:51:48.661831 DQM0 = 95, DQM1 = 83
5352 06:51:48.662181 DQ Delay:
5353 06:51:48.664212 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5354 06:51:48.667312 DQ4 =94, DQ5 =84, DQ6 =102, DQ7 =106
5355 06:51:48.670594 DQ8 =80, DQ9 =72, DQ10 =82, DQ11 =78
5356 06:51:48.673759 DQ12 =86, DQ13 =86, DQ14 =96, DQ15 =90
5357 06:51:48.674179
5358 06:51:48.674512
5359 06:51:48.683891 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5360 06:51:48.687180 CH0 RK0: MR19=505, MR18=1514
5361 06:51:48.693585 CH0_RK0: MR19=0x505, MR18=0x1514, DQSOSC=415, MR23=63, INC=62, DEC=41
5362 06:51:48.694008
5363 06:51:48.697167 ----->DramcWriteLeveling(PI) begin...
5364 06:51:48.697826 ==
5365 06:51:48.700152 Dram Type= 6, Freq= 0, CH_0, rank 1
5366 06:51:48.704149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5367 06:51:48.704678 ==
5368 06:51:48.706724 Write leveling (Byte 0): 33 => 33
5369 06:51:48.710154 Write leveling (Byte 1): 27 => 27
5370 06:51:48.713780 DramcWriteLeveling(PI) end<-----
5371 06:51:48.714209
5372 06:51:48.714544 ==
5373 06:51:48.716847 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 06:51:48.720505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 06:51:48.721033 ==
5376 06:51:48.723873 [Gating] SW mode calibration
5377 06:51:48.730216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5378 06:51:48.736570 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5379 06:51:48.740350 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5380 06:51:48.743755 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5381 06:51:48.749869 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 06:51:48.753234 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 06:51:48.756561 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 06:51:48.763591 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 06:51:48.766622 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 06:51:48.769785 0 14 28 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (0 0)
5387 06:51:48.776942 0 15 0 | B1->B0 | 2929 2323 | 1 0 | (1 1) (0 0)
5388 06:51:48.780168 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 06:51:48.783641 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 06:51:48.789909 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 06:51:48.793531 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 06:51:48.796421 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 06:51:48.802907 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 06:51:48.806234 0 15 28 | B1->B0 | 2525 3a3a | 0 0 | (0 0) (0 0)
5395 06:51:48.809994 1 0 0 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5396 06:51:48.816375 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 06:51:48.819467 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 06:51:48.822443 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 06:51:48.829584 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 06:51:48.832553 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 06:51:48.835683 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 06:51:48.842299 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5403 06:51:48.845845 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5404 06:51:48.849564 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 06:51:48.855939 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 06:51:48.859244 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 06:51:48.862561 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 06:51:48.868995 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 06:51:48.872713 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 06:51:48.875911 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 06:51:48.882225 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 06:51:48.885508 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 06:51:48.888943 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 06:51:48.895376 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 06:51:48.898888 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 06:51:48.902078 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 06:51:48.908837 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 06:51:48.911926 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5419 06:51:48.915674 Total UI for P1: 0, mck2ui 16
5420 06:51:48.918601 best dqsien dly found for B0: ( 1, 2, 26)
5421 06:51:48.921802 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 06:51:48.925289 Total UI for P1: 0, mck2ui 16
5423 06:51:48.928770 best dqsien dly found for B1: ( 1, 2, 28)
5424 06:51:48.932071 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5425 06:51:48.935292 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5426 06:51:48.935815
5427 06:51:48.938260 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5428 06:51:48.945240 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5429 06:51:48.945808 [Gating] SW calibration Done
5430 06:51:48.948577 ==
5431 06:51:48.949104 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 06:51:48.955297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 06:51:48.955882 ==
5434 06:51:48.956232 RX Vref Scan: 0
5435 06:51:48.956554
5436 06:51:48.958414 RX Vref 0 -> 0, step: 1
5437 06:51:48.958846
5438 06:51:48.962099 RX Delay -80 -> 252, step: 8
5439 06:51:48.965051 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5440 06:51:48.968485 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5441 06:51:48.971971 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5442 06:51:48.978256 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5443 06:51:48.981584 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5444 06:51:48.985322 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5445 06:51:48.988392 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5446 06:51:48.991434 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5447 06:51:48.994910 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5448 06:51:49.001519 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5449 06:51:49.004981 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5450 06:51:49.008424 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5451 06:51:49.011381 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5452 06:51:49.018479 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5453 06:51:49.021275 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5454 06:51:49.024916 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5455 06:51:49.025464 ==
5456 06:51:49.027998 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 06:51:49.031052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 06:51:49.031488 ==
5459 06:51:49.034810 DQS Delay:
5460 06:51:49.035433 DQS0 = 0, DQS1 = 0
5461 06:51:49.035795 DQM Delay:
5462 06:51:49.037764 DQM0 = 91, DQM1 = 83
5463 06:51:49.038215 DQ Delay:
5464 06:51:49.041598 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5465 06:51:49.044905 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5466 06:51:49.047864 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5467 06:51:49.051402 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5468 06:51:49.051928
5469 06:51:49.052272
5470 06:51:49.052588 ==
5471 06:51:49.054505 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 06:51:49.061388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 06:51:49.062040 ==
5474 06:51:49.062386
5475 06:51:49.062711
5476 06:51:49.063018 TX Vref Scan disable
5477 06:51:49.065021 == TX Byte 0 ==
5478 06:51:49.068133 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5479 06:51:49.075086 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5480 06:51:49.075780 == TX Byte 1 ==
5481 06:51:49.078683 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5482 06:51:49.084792 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5483 06:51:49.085216 ==
5484 06:51:49.088596 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 06:51:49.091356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 06:51:49.091796 ==
5487 06:51:49.092128
5488 06:51:49.092437
5489 06:51:49.094623 TX Vref Scan disable
5490 06:51:49.095046 == TX Byte 0 ==
5491 06:51:49.101901 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5492 06:51:49.105043 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5493 06:51:49.105597 == TX Byte 1 ==
5494 06:51:49.111396 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5495 06:51:49.114967 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5496 06:51:49.115495
5497 06:51:49.115830 [DATLAT]
5498 06:51:49.117975 Freq=933, CH0 RK1
5499 06:51:49.118399
5500 06:51:49.118731 DATLAT Default: 0xb
5501 06:51:49.121368 0, 0xFFFF, sum = 0
5502 06:51:49.121820 1, 0xFFFF, sum = 0
5503 06:51:49.124986 2, 0xFFFF, sum = 0
5504 06:51:49.128208 3, 0xFFFF, sum = 0
5505 06:51:49.128737 4, 0xFFFF, sum = 0
5506 06:51:49.131204 5, 0xFFFF, sum = 0
5507 06:51:49.131634 6, 0xFFFF, sum = 0
5508 06:51:49.134914 7, 0xFFFF, sum = 0
5509 06:51:49.135481 8, 0xFFFF, sum = 0
5510 06:51:49.137853 9, 0xFFFF, sum = 0
5511 06:51:49.138499 10, 0x0, sum = 1
5512 06:51:49.141245 11, 0x0, sum = 2
5513 06:51:49.141781 12, 0x0, sum = 3
5514 06:51:49.142134 13, 0x0, sum = 4
5515 06:51:49.144826 best_step = 11
5516 06:51:49.145342
5517 06:51:49.145737 ==
5518 06:51:49.148234 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 06:51:49.151190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 06:51:49.151717 ==
5521 06:51:49.154413 RX Vref Scan: 0
5522 06:51:49.154845
5523 06:51:49.157774 RX Vref 0 -> 0, step: 1
5524 06:51:49.158205
5525 06:51:49.158545 RX Delay -77 -> 252, step: 4
5526 06:51:49.165783 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5527 06:51:49.169200 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5528 06:51:49.172354 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5529 06:51:49.175664 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5530 06:51:49.179072 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5531 06:51:49.185510 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5532 06:51:49.188579 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5533 06:51:49.191893 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5534 06:51:49.195278 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5535 06:51:49.198264 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5536 06:51:49.204894 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5537 06:51:49.208397 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5538 06:51:49.211719 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5539 06:51:49.214919 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5540 06:51:49.218087 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5541 06:51:49.224752 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5542 06:51:49.225286 ==
5543 06:51:49.227946 Dram Type= 6, Freq= 0, CH_0, rank 1
5544 06:51:49.231477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 06:51:49.231902 ==
5546 06:51:49.232239 DQS Delay:
5547 06:51:49.234970 DQS0 = 0, DQS1 = 0
5548 06:51:49.235499 DQM Delay:
5549 06:51:49.237823 DQM0 = 93, DQM1 = 85
5550 06:51:49.238384 DQ Delay:
5551 06:51:49.241169 DQ0 =92, DQ1 =94, DQ2 =90, DQ3 =86
5552 06:51:49.244434 DQ4 =92, DQ5 =82, DQ6 =104, DQ7 =104
5553 06:51:49.248040 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =76
5554 06:51:49.251507 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =94
5555 06:51:49.252037
5556 06:51:49.252372
5557 06:51:49.257981 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5558 06:51:49.261381 CH0 RK1: MR19=505, MR18=2D0F
5559 06:51:49.268166 CH0_RK1: MR19=0x505, MR18=0x2D0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5560 06:51:49.271475 [RxdqsGatingPostProcess] freq 933
5561 06:51:49.277868 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5562 06:51:49.281292 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 06:51:49.284641 best DQS1 dly(2T, 0.5T) = (0, 11)
5564 06:51:49.287793 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 06:51:49.291079 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5566 06:51:49.291514 best DQS0 dly(2T, 0.5T) = (0, 10)
5567 06:51:49.294315 best DQS1 dly(2T, 0.5T) = (0, 10)
5568 06:51:49.297840 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5569 06:51:49.300883 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5570 06:51:49.304224 Pre-setting of DQS Precalculation
5571 06:51:49.310645 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5572 06:51:49.311160 ==
5573 06:51:49.314224 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 06:51:49.317305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 06:51:49.317772 ==
5576 06:51:49.323929 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5577 06:51:49.330446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5578 06:51:49.333623 [CA 0] Center 37 (7~67) winsize 61
5579 06:51:49.337348 [CA 1] Center 37 (7~68) winsize 62
5580 06:51:49.340386 [CA 2] Center 34 (5~64) winsize 60
5581 06:51:49.344070 [CA 3] Center 34 (4~64) winsize 61
5582 06:51:49.346897 [CA 4] Center 34 (5~64) winsize 60
5583 06:51:49.350465 [CA 5] Center 33 (4~63) winsize 60
5584 06:51:49.350903
5585 06:51:49.354106 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5586 06:51:49.354651
5587 06:51:49.357000 [CATrainingPosCal] consider 1 rank data
5588 06:51:49.360469 u2DelayCellTimex100 = 270/100 ps
5589 06:51:49.363920 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5590 06:51:49.367384 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5591 06:51:49.370591 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5592 06:51:49.373867 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5593 06:51:49.376813 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5594 06:51:49.380158 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5595 06:51:49.380650
5596 06:51:49.383377 CA PerBit enable=1, Macro0, CA PI delay=33
5597 06:51:49.386927
5598 06:51:49.387478 [CBTSetCACLKResult] CA Dly = 33
5599 06:51:49.390243 CS Dly: 6 (0~37)
5600 06:51:49.390736 ==
5601 06:51:49.393748 Dram Type= 6, Freq= 0, CH_1, rank 1
5602 06:51:49.396627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 06:51:49.397273 ==
5604 06:51:49.403434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5605 06:51:49.410180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5606 06:51:49.413455 [CA 0] Center 37 (7~67) winsize 61
5607 06:51:49.416859 [CA 1] Center 37 (7~68) winsize 62
5608 06:51:49.419837 [CA 2] Center 35 (5~65) winsize 61
5609 06:51:49.423440 [CA 3] Center 34 (4~64) winsize 61
5610 06:51:49.426909 [CA 4] Center 34 (4~65) winsize 62
5611 06:51:49.429877 [CA 5] Center 33 (3~64) winsize 62
5612 06:51:49.430307
5613 06:51:49.433282 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5614 06:51:49.433933
5615 06:51:49.436539 [CATrainingPosCal] consider 2 rank data
5616 06:51:49.439861 u2DelayCellTimex100 = 270/100 ps
5617 06:51:49.443041 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5618 06:51:49.446280 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5619 06:51:49.450024 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5620 06:51:49.453170 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5621 06:51:49.456464 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5622 06:51:49.459819 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5623 06:51:49.460482
5624 06:51:49.466281 CA PerBit enable=1, Macro0, CA PI delay=33
5625 06:51:49.466720
5626 06:51:49.469619 [CBTSetCACLKResult] CA Dly = 33
5627 06:51:49.470056 CS Dly: 7 (0~39)
5628 06:51:49.470498
5629 06:51:49.473120 ----->DramcWriteLeveling(PI) begin...
5630 06:51:49.473606 ==
5631 06:51:49.476156 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 06:51:49.479845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 06:51:49.480390 ==
5634 06:51:49.483174 Write leveling (Byte 0): 29 => 29
5635 06:51:49.486163 Write leveling (Byte 1): 29 => 29
5636 06:51:49.489314 DramcWriteLeveling(PI) end<-----
5637 06:51:49.489792
5638 06:51:49.490236 ==
5639 06:51:49.493066 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 06:51:49.499766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 06:51:49.500316 ==
5642 06:51:49.500770 [Gating] SW mode calibration
5643 06:51:49.509622 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5644 06:51:49.512650 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5645 06:51:49.519536 0 14 0 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
5646 06:51:49.522996 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 06:51:49.525855 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 06:51:49.529564 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 06:51:49.536322 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 06:51:49.539346 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 06:51:49.542862 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 06:51:49.549077 0 14 28 | B1->B0 | 2c2c 2d2d | 1 1 | (1 0) (1 0)
5653 06:51:49.552672 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5654 06:51:49.556088 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 06:51:49.562426 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 06:51:49.565583 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 06:51:49.569062 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 06:51:49.575889 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 06:51:49.579297 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 06:51:49.582259 0 15 28 | B1->B0 | 3131 3232 | 1 0 | (0 0) (0 0)
5661 06:51:49.588990 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 06:51:49.591994 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 06:51:49.595609 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 06:51:49.602211 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 06:51:49.605636 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 06:51:49.608980 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 06:51:49.615337 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 06:51:49.619064 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5669 06:51:49.622365 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5670 06:51:49.628862 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 06:51:49.632076 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 06:51:49.635592 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 06:51:49.641845 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 06:51:49.645378 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 06:51:49.648561 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 06:51:49.655281 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 06:51:49.658331 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 06:51:49.661726 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 06:51:49.668287 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 06:51:49.672010 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 06:51:49.674896 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 06:51:49.681543 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 06:51:49.685199 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 06:51:49.688271 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5685 06:51:49.694541 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5686 06:51:49.698050 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5687 06:51:49.701201 Total UI for P1: 0, mck2ui 16
5688 06:51:49.704446 best dqsien dly found for B0: ( 1, 2, 30)
5689 06:51:49.708200 Total UI for P1: 0, mck2ui 16
5690 06:51:49.711289 best dqsien dly found for B1: ( 1, 2, 30)
5691 06:51:49.714444 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5692 06:51:49.718024 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5693 06:51:49.718448
5694 06:51:49.720935 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5695 06:51:49.724691 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5696 06:51:49.727883 [Gating] SW calibration Done
5697 06:51:49.728308 ==
5698 06:51:49.731073 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 06:51:49.734280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 06:51:49.737813 ==
5701 06:51:49.738237 RX Vref Scan: 0
5702 06:51:49.738577
5703 06:51:49.741200 RX Vref 0 -> 0, step: 1
5704 06:51:49.741778
5705 06:51:49.742121 RX Delay -80 -> 252, step: 8
5706 06:51:49.748149 iDelay=208, Bit 0, Center 103 (0 ~ 207) 208
5707 06:51:49.751406 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5708 06:51:49.754718 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5709 06:51:49.758252 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5710 06:51:49.761745 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5711 06:51:49.768006 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5712 06:51:49.771012 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5713 06:51:49.774602 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5714 06:51:49.777454 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5715 06:51:49.780691 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5716 06:51:49.784749 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5717 06:51:49.791035 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5718 06:51:49.794032 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5719 06:51:49.797403 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5720 06:51:49.800578 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5721 06:51:49.807688 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5722 06:51:49.808221 ==
5723 06:51:49.810763 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 06:51:49.813817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 06:51:49.814277 ==
5726 06:51:49.814673 DQS Delay:
5727 06:51:49.817710 DQS0 = 0, DQS1 = 0
5728 06:51:49.818244 DQM Delay:
5729 06:51:49.820881 DQM0 = 95, DQM1 = 87
5730 06:51:49.821305 DQ Delay:
5731 06:51:49.824283 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5732 06:51:49.827285 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5733 06:51:49.830345 DQ8 =79, DQ9 =83, DQ10 =87, DQ11 =83
5734 06:51:49.833999 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5735 06:51:49.834581
5736 06:51:49.834934
5737 06:51:49.835247 ==
5738 06:51:49.837053 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 06:51:49.840528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 06:51:49.841181 ==
5741 06:51:49.841651
5742 06:51:49.843766
5743 06:51:49.844297 TX Vref Scan disable
5744 06:51:49.847353 == TX Byte 0 ==
5745 06:51:49.850628 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5746 06:51:49.854187 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5747 06:51:49.857517 == TX Byte 1 ==
5748 06:51:49.860798 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5749 06:51:49.863537 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5750 06:51:49.863971 ==
5751 06:51:49.867120 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 06:51:49.873579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 06:51:49.874099 ==
5754 06:51:49.874438
5755 06:51:49.874749
5756 06:51:49.875049 TX Vref Scan disable
5757 06:51:49.877739 == TX Byte 0 ==
5758 06:51:49.881042 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5759 06:51:49.887511 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5760 06:51:49.888027 == TX Byte 1 ==
5761 06:51:49.890880 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5762 06:51:49.897707 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5763 06:51:49.898139
5764 06:51:49.898479 [DATLAT]
5765 06:51:49.898800 Freq=933, CH1 RK0
5766 06:51:49.899116
5767 06:51:49.900823 DATLAT Default: 0xd
5768 06:51:49.901368 0, 0xFFFF, sum = 0
5769 06:51:49.903991 1, 0xFFFF, sum = 0
5770 06:51:49.904441 2, 0xFFFF, sum = 0
5771 06:51:49.907817 3, 0xFFFF, sum = 0
5772 06:51:49.910940 4, 0xFFFF, sum = 0
5773 06:51:49.911379 5, 0xFFFF, sum = 0
5774 06:51:49.914339 6, 0xFFFF, sum = 0
5775 06:51:49.914779 7, 0xFFFF, sum = 0
5776 06:51:49.917678 8, 0xFFFF, sum = 0
5777 06:51:49.918292 9, 0xFFFF, sum = 0
5778 06:51:49.921115 10, 0x0, sum = 1
5779 06:51:49.921703 11, 0x0, sum = 2
5780 06:51:49.924567 12, 0x0, sum = 3
5781 06:51:49.925112 13, 0x0, sum = 4
5782 06:51:49.925464 best_step = 11
5783 06:51:49.925892
5784 06:51:49.927611 ==
5785 06:51:49.931011 Dram Type= 6, Freq= 0, CH_1, rank 0
5786 06:51:49.934366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 06:51:49.934911 ==
5788 06:51:49.935255 RX Vref Scan: 1
5789 06:51:49.935580
5790 06:51:49.937768 RX Vref 0 -> 0, step: 1
5791 06:51:49.938306
5792 06:51:49.941054 RX Delay -61 -> 252, step: 4
5793 06:51:49.941636
5794 06:51:49.944252 Set Vref, RX VrefLevel [Byte0]: 57
5795 06:51:49.947652 [Byte1]: 53
5796 06:51:49.948199
5797 06:51:49.950620 Final RX Vref Byte 0 = 57 to rank0
5798 06:51:49.953846 Final RX Vref Byte 1 = 53 to rank0
5799 06:51:49.957313 Final RX Vref Byte 0 = 57 to rank1
5800 06:51:49.960807 Final RX Vref Byte 1 = 53 to rank1==
5801 06:51:49.963706 Dram Type= 6, Freq= 0, CH_1, rank 0
5802 06:51:49.967269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 06:51:49.970422 ==
5804 06:51:49.970865 DQS Delay:
5805 06:51:49.971279 DQS0 = 0, DQS1 = 0
5806 06:51:49.973989 DQM Delay:
5807 06:51:49.974415 DQM0 = 94, DQM1 = 88
5808 06:51:49.977214 DQ Delay:
5809 06:51:49.977710 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =90
5810 06:51:49.980644 DQ4 =92, DQ5 =104, DQ6 =104, DQ7 =92
5811 06:51:49.983820 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =82
5812 06:51:49.990409 DQ12 =96, DQ13 =92, DQ14 =94, DQ15 =94
5813 06:51:49.990963
5814 06:51:49.991306
5815 06:51:49.997245 [DQSOSCAuto] RK0, (LSB)MR18= 0x8, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5816 06:51:50.000548 CH1 RK0: MR19=505, MR18=8
5817 06:51:50.003945 CH1_RK0: MR19=0x505, MR18=0x8, DQSOSC=419, MR23=63, INC=61, DEC=41
5818 06:51:50.004489
5819 06:51:50.007533 ----->DramcWriteLeveling(PI) begin...
5820 06:51:50.010594 ==
5821 06:51:50.014028 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 06:51:50.017366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 06:51:50.018119 ==
5824 06:51:50.020345 Write leveling (Byte 0): 27 => 27
5825 06:51:50.023809 Write leveling (Byte 1): 28 => 28
5826 06:51:50.027070 DramcWriteLeveling(PI) end<-----
5827 06:51:50.027597
5828 06:51:50.027934 ==
5829 06:51:50.030135 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 06:51:50.033597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 06:51:50.034125 ==
5832 06:51:50.036902 [Gating] SW mode calibration
5833 06:51:50.043491 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5834 06:51:50.050235 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5835 06:51:50.053630 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5836 06:51:50.057124 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 06:51:50.063460 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 06:51:50.066612 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 06:51:50.069601 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5840 06:51:50.076485 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5841 06:51:50.079948 0 14 24 | B1->B0 | 3232 2e2e | 0 1 | (0 0) (1 0)
5842 06:51:50.083241 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
5843 06:51:50.089595 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 06:51:50.092670 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 06:51:50.096401 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 06:51:50.103008 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 06:51:50.106164 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 06:51:50.109669 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5849 06:51:50.116239 0 15 24 | B1->B0 | 2a2a 3434 | 0 0 | (1 1) (0 0)
5850 06:51:50.119119 0 15 28 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
5851 06:51:50.122847 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 06:51:50.129336 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 06:51:50.132633 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 06:51:50.136276 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 06:51:50.142424 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 06:51:50.145654 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 06:51:50.149293 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5858 06:51:50.156277 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5859 06:51:50.159111 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 06:51:50.162425 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 06:51:50.169375 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 06:51:50.172408 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 06:51:50.175944 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 06:51:50.182335 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 06:51:50.185716 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 06:51:50.189067 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 06:51:50.195535 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 06:51:50.198535 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 06:51:50.201885 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 06:51:50.208806 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 06:51:50.211862 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 06:51:50.215130 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 06:51:50.221809 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5874 06:51:50.224838 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5875 06:51:50.228557 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5876 06:51:50.231485 Total UI for P1: 0, mck2ui 16
5877 06:51:50.234909 best dqsien dly found for B0: ( 1, 2, 26)
5878 06:51:50.238490 Total UI for P1: 0, mck2ui 16
5879 06:51:50.241306 best dqsien dly found for B1: ( 1, 2, 28)
5880 06:51:50.244862 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5881 06:51:50.248534 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5882 06:51:50.249104
5883 06:51:50.251834 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5884 06:51:50.258022 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5885 06:51:50.258534 [Gating] SW calibration Done
5886 06:51:50.258873 ==
5887 06:51:50.261332 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 06:51:50.268143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 06:51:50.268674 ==
5890 06:51:50.269013 RX Vref Scan: 0
5891 06:51:50.269328
5892 06:51:50.271424 RX Vref 0 -> 0, step: 1
5893 06:51:50.272108
5894 06:51:50.275071 RX Delay -80 -> 252, step: 8
5895 06:51:50.278394 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5896 06:51:50.281521 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5897 06:51:50.285012 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5898 06:51:50.288450 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5899 06:51:50.294397 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5900 06:51:50.298092 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5901 06:51:50.301535 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5902 06:51:50.304780 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5903 06:51:50.308360 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5904 06:51:50.311035 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5905 06:51:50.318178 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5906 06:51:50.321297 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5907 06:51:50.324795 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5908 06:51:50.327987 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5909 06:51:50.331299 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5910 06:51:50.337800 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5911 06:51:50.338333 ==
5912 06:51:50.341026 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 06:51:50.344498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 06:51:50.345103 ==
5915 06:51:50.345454 DQS Delay:
5916 06:51:50.347803 DQS0 = 0, DQS1 = 0
5917 06:51:50.348381 DQM Delay:
5918 06:51:50.351473 DQM0 = 94, DQM1 = 89
5919 06:51:50.352008 DQ Delay:
5920 06:51:50.354646 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5921 06:51:50.357456 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5922 06:51:50.361050 DQ8 =75, DQ9 =75, DQ10 =95, DQ11 =83
5923 06:51:50.364402 DQ12 =99, DQ13 =99, DQ14 =91, DQ15 =99
5924 06:51:50.364932
5925 06:51:50.365268
5926 06:51:50.365633 ==
5927 06:51:50.367497 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 06:51:50.370888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 06:51:50.371356 ==
5930 06:51:50.374094
5931 06:51:50.374516
5932 06:51:50.374854 TX Vref Scan disable
5933 06:51:50.377827 == TX Byte 0 ==
5934 06:51:50.381082 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5935 06:51:50.384510 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5936 06:51:50.387728 == TX Byte 1 ==
5937 06:51:50.390975 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5938 06:51:50.394249 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5939 06:51:50.394680 ==
5940 06:51:50.397663 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 06:51:50.404375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 06:51:50.404911 ==
5943 06:51:50.405253
5944 06:51:50.405606
5945 06:51:50.405915 TX Vref Scan disable
5946 06:51:50.408622 == TX Byte 0 ==
5947 06:51:50.411980 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5948 06:51:50.418538 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5949 06:51:50.419078 == TX Byte 1 ==
5950 06:51:50.421755 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5951 06:51:50.428399 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5952 06:51:50.428937
5953 06:51:50.429279 [DATLAT]
5954 06:51:50.429638 Freq=933, CH1 RK1
5955 06:51:50.429984
5956 06:51:50.431578 DATLAT Default: 0xb
5957 06:51:50.432001 0, 0xFFFF, sum = 0
5958 06:51:50.434641 1, 0xFFFF, sum = 0
5959 06:51:50.438048 2, 0xFFFF, sum = 0
5960 06:51:50.438482 3, 0xFFFF, sum = 0
5961 06:51:50.441656 4, 0xFFFF, sum = 0
5962 06:51:50.442191 5, 0xFFFF, sum = 0
5963 06:51:50.444808 6, 0xFFFF, sum = 0
5964 06:51:50.445466 7, 0xFFFF, sum = 0
5965 06:51:50.448189 8, 0xFFFF, sum = 0
5966 06:51:50.448731 9, 0xFFFF, sum = 0
5967 06:51:50.451644 10, 0x0, sum = 1
5968 06:51:50.452204 11, 0x0, sum = 2
5969 06:51:50.454851 12, 0x0, sum = 3
5970 06:51:50.455390 13, 0x0, sum = 4
5971 06:51:50.455735 best_step = 11
5972 06:51:50.457875
5973 06:51:50.458452 ==
5974 06:51:50.461040 Dram Type= 6, Freq= 0, CH_1, rank 1
5975 06:51:50.464449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5976 06:51:50.464877 ==
5977 06:51:50.465213 RX Vref Scan: 0
5978 06:51:50.465575
5979 06:51:50.467633 RX Vref 0 -> 0, step: 1
5980 06:51:50.468057
5981 06:51:50.471012 RX Delay -69 -> 252, step: 4
5982 06:51:50.477591 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5983 06:51:50.480926 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5984 06:51:50.484610 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5985 06:51:50.487844 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5986 06:51:50.491043 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5987 06:51:50.494276 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5988 06:51:50.500969 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5989 06:51:50.504253 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5990 06:51:50.507299 iDelay=203, Bit 8, Center 78 (-17 ~ 174) 192
5991 06:51:50.510905 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5992 06:51:50.514195 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5993 06:51:50.520994 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5994 06:51:50.524389 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5995 06:51:50.527058 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5996 06:51:50.530441 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5997 06:51:50.533834 iDelay=203, Bit 15, Center 96 (-1 ~ 194) 196
5998 06:51:50.534264 ==
5999 06:51:50.537232 Dram Type= 6, Freq= 0, CH_1, rank 1
6000 06:51:50.543834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6001 06:51:50.544267 ==
6002 06:51:50.544607 DQS Delay:
6003 06:51:50.547007 DQS0 = 0, DQS1 = 0
6004 06:51:50.547457 DQM Delay:
6005 06:51:50.547911 DQM0 = 92, DQM1 = 89
6006 06:51:50.550453 DQ Delay:
6007 06:51:50.553835 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =90
6008 06:51:50.557229 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =90
6009 06:51:50.560256 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =82
6010 06:51:50.563864 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
6011 06:51:50.564321
6012 06:51:50.564774
6013 06:51:50.570126 [DQSOSCAuto] RK1, (LSB)MR18= 0xe22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
6014 06:51:50.573595 CH1 RK1: MR19=505, MR18=E22
6015 06:51:50.580615 CH1_RK1: MR19=0x505, MR18=0xE22, DQSOSC=411, MR23=63, INC=64, DEC=42
6016 06:51:50.583693 [RxdqsGatingPostProcess] freq 933
6017 06:51:50.587443 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6018 06:51:50.590273 best DQS0 dly(2T, 0.5T) = (0, 10)
6019 06:51:50.593764 best DQS1 dly(2T, 0.5T) = (0, 10)
6020 06:51:50.597130 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6021 06:51:50.600219 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6022 06:51:50.603954 best DQS0 dly(2T, 0.5T) = (0, 10)
6023 06:51:50.607254 best DQS1 dly(2T, 0.5T) = (0, 10)
6024 06:51:50.610046 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6025 06:51:50.613560 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6026 06:51:50.616599 Pre-setting of DQS Precalculation
6027 06:51:50.620165 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6028 06:51:50.630196 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6029 06:51:50.637219 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6030 06:51:50.637803
6031 06:51:50.638147
6032 06:51:50.640045 [Calibration Summary] 1866 Mbps
6033 06:51:50.640474 CH 0, Rank 0
6034 06:51:50.643989 SW Impedance : PASS
6035 06:51:50.644517 DUTY Scan : NO K
6036 06:51:50.646550 ZQ Calibration : PASS
6037 06:51:50.650003 Jitter Meter : NO K
6038 06:51:50.650541 CBT Training : PASS
6039 06:51:50.653326 Write leveling : PASS
6040 06:51:50.657012 RX DQS gating : PASS
6041 06:51:50.657599 RX DQ/DQS(RDDQC) : PASS
6042 06:51:50.660125 TX DQ/DQS : PASS
6043 06:51:50.663620 RX DATLAT : PASS
6044 06:51:50.664158 RX DQ/DQS(Engine): PASS
6045 06:51:50.666456 TX OE : NO K
6046 06:51:50.666882 All Pass.
6047 06:51:50.667219
6048 06:51:50.670086 CH 0, Rank 1
6049 06:51:50.670512 SW Impedance : PASS
6050 06:51:50.673202 DUTY Scan : NO K
6051 06:51:50.676742 ZQ Calibration : PASS
6052 06:51:50.677280 Jitter Meter : NO K
6053 06:51:50.679697 CBT Training : PASS
6054 06:51:50.680120 Write leveling : PASS
6055 06:51:50.683350 RX DQS gating : PASS
6056 06:51:50.686818 RX DQ/DQS(RDDQC) : PASS
6057 06:51:50.687347 TX DQ/DQS : PASS
6058 06:51:50.689719 RX DATLAT : PASS
6059 06:51:50.693187 RX DQ/DQS(Engine): PASS
6060 06:51:50.693828 TX OE : NO K
6061 06:51:50.696828 All Pass.
6062 06:51:50.697360
6063 06:51:50.697880 CH 1, Rank 0
6064 06:51:50.699513 SW Impedance : PASS
6065 06:51:50.699940 DUTY Scan : NO K
6066 06:51:50.703189 ZQ Calibration : PASS
6067 06:51:50.706486 Jitter Meter : NO K
6068 06:51:50.707021 CBT Training : PASS
6069 06:51:50.710058 Write leveling : PASS
6070 06:51:50.713381 RX DQS gating : PASS
6071 06:51:50.713959 RX DQ/DQS(RDDQC) : PASS
6072 06:51:50.716436 TX DQ/DQS : PASS
6073 06:51:50.719429 RX DATLAT : PASS
6074 06:51:50.719856 RX DQ/DQS(Engine): PASS
6075 06:51:50.722956 TX OE : NO K
6076 06:51:50.723408 All Pass.
6077 06:51:50.723756
6078 06:51:50.726200 CH 1, Rank 1
6079 06:51:50.726626 SW Impedance : PASS
6080 06:51:50.729514 DUTY Scan : NO K
6081 06:51:50.732955 ZQ Calibration : PASS
6082 06:51:50.733572 Jitter Meter : NO K
6083 06:51:50.735862 CBT Training : PASS
6084 06:51:50.739501 Write leveling : PASS
6085 06:51:50.740059 RX DQS gating : PASS
6086 06:51:50.743135 RX DQ/DQS(RDDQC) : PASS
6087 06:51:50.746138 TX DQ/DQS : PASS
6088 06:51:50.746968 RX DATLAT : PASS
6089 06:51:50.749063 RX DQ/DQS(Engine): PASS
6090 06:51:50.749522 TX OE : NO K
6091 06:51:50.752624 All Pass.
6092 06:51:50.753159
6093 06:51:50.753551 DramC Write-DBI off
6094 06:51:50.756138 PER_BANK_REFRESH: Hybrid Mode
6095 06:51:50.759445 TX_TRACKING: ON
6096 06:51:50.765636 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6097 06:51:50.769133 [FAST_K] Save calibration result to emmc
6098 06:51:50.776026 dramc_set_vcore_voltage set vcore to 650000
6099 06:51:50.776566 Read voltage for 400, 6
6100 06:51:50.778981 Vio18 = 0
6101 06:51:50.779513 Vcore = 650000
6102 06:51:50.779854 Vdram = 0
6103 06:51:50.780169 Vddq = 0
6104 06:51:50.782040 Vmddr = 0
6105 06:51:50.786057 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6106 06:51:50.792098 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6107 06:51:50.795345 MEM_TYPE=3, freq_sel=20
6108 06:51:50.795770 sv_algorithm_assistance_LP4_800
6109 06:51:50.802036 ============ PULL DRAM RESETB DOWN ============
6110 06:51:50.805334 ========== PULL DRAM RESETB DOWN end =========
6111 06:51:50.809088 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6112 06:51:50.811756 ===================================
6113 06:51:50.815060 LPDDR4 DRAM CONFIGURATION
6114 06:51:50.818445 ===================================
6115 06:51:50.821875 EX_ROW_EN[0] = 0x0
6116 06:51:50.822307 EX_ROW_EN[1] = 0x0
6117 06:51:50.825250 LP4Y_EN = 0x0
6118 06:51:50.825899 WORK_FSP = 0x0
6119 06:51:50.828384 WL = 0x2
6120 06:51:50.828815 RL = 0x2
6121 06:51:50.831748 BL = 0x2
6122 06:51:50.832177 RPST = 0x0
6123 06:51:50.835139 RD_PRE = 0x0
6124 06:51:50.835729 WR_PRE = 0x1
6125 06:51:50.838137 WR_PST = 0x0
6126 06:51:50.842071 DBI_WR = 0x0
6127 06:51:50.842600 DBI_RD = 0x0
6128 06:51:50.844846 OTF = 0x1
6129 06:51:50.848015 ===================================
6130 06:51:50.851435 ===================================
6131 06:51:50.851869 ANA top config
6132 06:51:50.854689 ===================================
6133 06:51:50.858133 DLL_ASYNC_EN = 0
6134 06:51:50.861380 ALL_SLAVE_EN = 1
6135 06:51:50.861963 NEW_RANK_MODE = 1
6136 06:51:50.864770 DLL_IDLE_MODE = 1
6137 06:51:50.867861 LP45_APHY_COMB_EN = 1
6138 06:51:50.871484 TX_ODT_DIS = 1
6139 06:51:50.872021 NEW_8X_MODE = 1
6140 06:51:50.874397 ===================================
6141 06:51:50.878000 ===================================
6142 06:51:50.881435 data_rate = 800
6143 06:51:50.884728 CKR = 1
6144 06:51:50.888080 DQ_P2S_RATIO = 4
6145 06:51:50.890822 ===================================
6146 06:51:50.894219 CA_P2S_RATIO = 4
6147 06:51:50.897615 DQ_CA_OPEN = 0
6148 06:51:50.901362 DQ_SEMI_OPEN = 1
6149 06:51:50.901946 CA_SEMI_OPEN = 1
6150 06:51:50.904078 CA_FULL_RATE = 0
6151 06:51:50.907965 DQ_CKDIV4_EN = 0
6152 06:51:50.911030 CA_CKDIV4_EN = 1
6153 06:51:50.913949 CA_PREDIV_EN = 0
6154 06:51:50.917452 PH8_DLY = 0
6155 06:51:50.917907 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6156 06:51:50.920953 DQ_AAMCK_DIV = 0
6157 06:51:50.924252 CA_AAMCK_DIV = 0
6158 06:51:50.927707 CA_ADMCK_DIV = 4
6159 06:51:50.930881 DQ_TRACK_CA_EN = 0
6160 06:51:50.933796 CA_PICK = 800
6161 06:51:50.934222 CA_MCKIO = 400
6162 06:51:50.937642 MCKIO_SEMI = 400
6163 06:51:50.940888 PLL_FREQ = 3016
6164 06:51:50.943849 DQ_UI_PI_RATIO = 32
6165 06:51:50.947329 CA_UI_PI_RATIO = 32
6166 06:51:50.950492 ===================================
6167 06:51:50.953830 ===================================
6168 06:51:50.957135 memory_type:LPDDR4
6169 06:51:50.957603 GP_NUM : 10
6170 06:51:50.960866 SRAM_EN : 1
6171 06:51:50.964018 MD32_EN : 0
6172 06:51:50.967228 ===================================
6173 06:51:50.967799 [ANA_INIT] >>>>>>>>>>>>>>
6174 06:51:50.970248 <<<<<< [CONFIGURE PHASE]: ANA_TX
6175 06:51:50.973852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6176 06:51:50.977127 ===================================
6177 06:51:50.980543 data_rate = 800,PCW = 0X7400
6178 06:51:50.983796 ===================================
6179 06:51:50.987476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6180 06:51:50.993899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6181 06:51:51.004086 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6182 06:51:51.006802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6183 06:51:51.010417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6184 06:51:51.016768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6185 06:51:51.017371 [ANA_INIT] flow start
6186 06:51:51.020512 [ANA_INIT] PLL >>>>>>>>
6187 06:51:51.021068 [ANA_INIT] PLL <<<<<<<<
6188 06:51:51.023363 [ANA_INIT] MIDPI >>>>>>>>
6189 06:51:51.026463 [ANA_INIT] MIDPI <<<<<<<<
6190 06:51:51.030071 [ANA_INIT] DLL >>>>>>>>
6191 06:51:51.030645 [ANA_INIT] flow end
6192 06:51:51.036519 ============ LP4 DIFF to SE enter ============
6193 06:51:51.039792 ============ LP4 DIFF to SE exit ============
6194 06:51:51.040320 [ANA_INIT] <<<<<<<<<<<<<
6195 06:51:51.043530 [Flow] Enable top DCM control >>>>>
6196 06:51:51.046490 [Flow] Enable top DCM control <<<<<
6197 06:51:51.049818 Enable DLL master slave shuffle
6198 06:51:51.056425 ==============================================================
6199 06:51:51.060131 Gating Mode config
6200 06:51:51.063050 ==============================================================
6201 06:51:51.066376 Config description:
6202 06:51:51.076398 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6203 06:51:51.083312 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6204 06:51:51.086562 SELPH_MODE 0: By rank 1: By Phase
6205 06:51:51.092935 ==============================================================
6206 06:51:51.096552 GAT_TRACK_EN = 0
6207 06:51:51.099324 RX_GATING_MODE = 2
6208 06:51:51.102690 RX_GATING_TRACK_MODE = 2
6209 06:51:51.103119 SELPH_MODE = 1
6210 06:51:51.106462 PICG_EARLY_EN = 1
6211 06:51:51.110052 VALID_LAT_VALUE = 1
6212 06:51:51.116070 ==============================================================
6213 06:51:51.119864 Enter into Gating configuration >>>>
6214 06:51:51.122868 Exit from Gating configuration <<<<
6215 06:51:51.126323 Enter into DVFS_PRE_config >>>>>
6216 06:51:51.136055 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6217 06:51:51.139359 Exit from DVFS_PRE_config <<<<<
6218 06:51:51.142468 Enter into PICG configuration >>>>
6219 06:51:51.145861 Exit from PICG configuration <<<<
6220 06:51:51.149185 [RX_INPUT] configuration >>>>>
6221 06:51:51.153001 [RX_INPUT] configuration <<<<<
6222 06:51:51.156076 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6223 06:51:51.162876 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6224 06:51:51.168887 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6225 06:51:51.176007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6226 06:51:51.182344 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6227 06:51:51.185562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6228 06:51:51.192272 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6229 06:51:51.195413 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6230 06:51:51.198790 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6231 06:51:51.202039 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6232 06:51:51.208858 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6233 06:51:51.212073 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6234 06:51:51.215326 ===================================
6235 06:51:51.218591 LPDDR4 DRAM CONFIGURATION
6236 06:51:51.221989 ===================================
6237 06:51:51.222417 EX_ROW_EN[0] = 0x0
6238 06:51:51.225285 EX_ROW_EN[1] = 0x0
6239 06:51:51.225736 LP4Y_EN = 0x0
6240 06:51:51.228823 WORK_FSP = 0x0
6241 06:51:51.229347 WL = 0x2
6242 06:51:51.231745 RL = 0x2
6243 06:51:51.232173 BL = 0x2
6244 06:51:51.235174 RPST = 0x0
6245 06:51:51.238631 RD_PRE = 0x0
6246 06:51:51.239056 WR_PRE = 0x1
6247 06:51:51.241575 WR_PST = 0x0
6248 06:51:51.242004 DBI_WR = 0x0
6249 06:51:51.245239 DBI_RD = 0x0
6250 06:51:51.245705 OTF = 0x1
6251 06:51:51.248115 ===================================
6252 06:51:51.251611 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6253 06:51:51.258204 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6254 06:51:51.261463 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6255 06:51:51.265174 ===================================
6256 06:51:51.268117 LPDDR4 DRAM CONFIGURATION
6257 06:51:51.271740 ===================================
6258 06:51:51.272271 EX_ROW_EN[0] = 0x10
6259 06:51:51.275150 EX_ROW_EN[1] = 0x0
6260 06:51:51.275674 LP4Y_EN = 0x0
6261 06:51:51.277938 WORK_FSP = 0x0
6262 06:51:51.278380 WL = 0x2
6263 06:51:51.281428 RL = 0x2
6264 06:51:51.281893 BL = 0x2
6265 06:51:51.284503 RPST = 0x0
6266 06:51:51.284926 RD_PRE = 0x0
6267 06:51:51.287850 WR_PRE = 0x1
6268 06:51:51.291291 WR_PST = 0x0
6269 06:51:51.291800 DBI_WR = 0x0
6270 06:51:51.294585 DBI_RD = 0x0
6271 06:51:51.295024 OTF = 0x1
6272 06:51:51.298135 ===================================
6273 06:51:51.304902 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6274 06:51:51.308367 nWR fixed to 30
6275 06:51:51.311852 [ModeRegInit_LP4] CH0 RK0
6276 06:51:51.312396 [ModeRegInit_LP4] CH0 RK1
6277 06:51:51.314987 [ModeRegInit_LP4] CH1 RK0
6278 06:51:51.318072 [ModeRegInit_LP4] CH1 RK1
6279 06:51:51.318511 match AC timing 19
6280 06:51:51.325012 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6281 06:51:51.328390 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6282 06:51:51.331529 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6283 06:51:51.338217 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6284 06:51:51.341432 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6285 06:51:51.342017 ==
6286 06:51:51.344763 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 06:51:51.347972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 06:51:51.348517 ==
6289 06:51:51.354370 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6290 06:51:51.361416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6291 06:51:51.364617 [CA 0] Center 36 (8~64) winsize 57
6292 06:51:51.368086 [CA 1] Center 36 (8~64) winsize 57
6293 06:51:51.371210 [CA 2] Center 36 (8~64) winsize 57
6294 06:51:51.374242 [CA 3] Center 36 (8~64) winsize 57
6295 06:51:51.374687 [CA 4] Center 36 (8~64) winsize 57
6296 06:51:51.378043 [CA 5] Center 36 (8~64) winsize 57
6297 06:51:51.378580
6298 06:51:51.384764 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6299 06:51:51.385308
6300 06:51:51.388109 [CATrainingPosCal] consider 1 rank data
6301 06:51:51.390934 u2DelayCellTimex100 = 270/100 ps
6302 06:51:51.394418 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 06:51:51.397718 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 06:51:51.400865 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 06:51:51.404247 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 06:51:51.407684 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 06:51:51.410763 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 06:51:51.411304
6309 06:51:51.414145 CA PerBit enable=1, Macro0, CA PI delay=36
6310 06:51:51.414585
6311 06:51:51.417660 [CBTSetCACLKResult] CA Dly = 36
6312 06:51:51.421097 CS Dly: 1 (0~32)
6313 06:51:51.421664 ==
6314 06:51:51.424184 Dram Type= 6, Freq= 0, CH_0, rank 1
6315 06:51:51.427250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 06:51:51.427698 ==
6317 06:51:51.433984 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6318 06:51:51.440835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6319 06:51:51.444098 [CA 0] Center 36 (8~64) winsize 57
6320 06:51:51.444764 [CA 1] Center 36 (8~64) winsize 57
6321 06:51:51.447711 [CA 2] Center 36 (8~64) winsize 57
6322 06:51:51.450523 [CA 3] Center 36 (8~64) winsize 57
6323 06:51:51.453986 [CA 4] Center 36 (8~64) winsize 57
6324 06:51:51.457452 [CA 5] Center 36 (8~64) winsize 57
6325 06:51:51.458030
6326 06:51:51.460791 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6327 06:51:51.461361
6328 06:51:51.467158 [CATrainingPosCal] consider 2 rank data
6329 06:51:51.467692 u2DelayCellTimex100 = 270/100 ps
6330 06:51:51.470848 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 06:51:51.477100 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 06:51:51.480367 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 06:51:51.484229 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 06:51:51.487272 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 06:51:51.490524 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 06:51:51.490952
6337 06:51:51.493606 CA PerBit enable=1, Macro0, CA PI delay=36
6338 06:51:51.494033
6339 06:51:51.497264 [CBTSetCACLKResult] CA Dly = 36
6340 06:51:51.500572 CS Dly: 1 (0~32)
6341 06:51:51.500998
6342 06:51:51.503865 ----->DramcWriteLeveling(PI) begin...
6343 06:51:51.504403 ==
6344 06:51:51.506921 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 06:51:51.510465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 06:51:51.511132 ==
6347 06:51:51.513625 Write leveling (Byte 0): 40 => 8
6348 06:51:51.516631 Write leveling (Byte 1): 40 => 8
6349 06:51:51.520441 DramcWriteLeveling(PI) end<-----
6350 06:51:51.520972
6351 06:51:51.521313 ==
6352 06:51:51.523512 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 06:51:51.526591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 06:51:51.527062 ==
6355 06:51:51.530469 [Gating] SW mode calibration
6356 06:51:51.536947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6357 06:51:51.543167 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6358 06:51:51.546900 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6359 06:51:51.549804 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6360 06:51:51.556388 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 06:51:51.559907 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6362 06:51:51.563047 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 06:51:51.569886 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 06:51:51.573243 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6365 06:51:51.576320 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6366 06:51:51.583119 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6367 06:51:51.583971 Total UI for P1: 0, mck2ui 16
6368 06:51:51.589933 best dqsien dly found for B0: ( 0, 14, 24)
6369 06:51:51.590453 Total UI for P1: 0, mck2ui 16
6370 06:51:51.593266 best dqsien dly found for B1: ( 0, 14, 24)
6371 06:51:51.599522 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6372 06:51:51.603179 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6373 06:51:51.603715
6374 06:51:51.606042 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6375 06:51:51.609429 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6376 06:51:51.613080 [Gating] SW calibration Done
6377 06:51:51.613589 ==
6378 06:51:51.616067 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 06:51:51.619337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 06:51:51.619786 ==
6381 06:51:51.622796 RX Vref Scan: 0
6382 06:51:51.623218
6383 06:51:51.623549 RX Vref 0 -> 0, step: 1
6384 06:51:51.623858
6385 06:51:51.626106 RX Delay -410 -> 252, step: 16
6386 06:51:51.632927 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6387 06:51:51.636082 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6388 06:51:51.639247 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6389 06:51:51.642619 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6390 06:51:51.649513 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6391 06:51:51.652324 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6392 06:51:51.655958 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6393 06:51:51.659605 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6394 06:51:51.665874 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6395 06:51:51.669284 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6396 06:51:51.672688 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6397 06:51:51.675979 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6398 06:51:51.682336 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6399 06:51:51.685753 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6400 06:51:51.689231 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6401 06:51:51.692688 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6402 06:51:51.695720 ==
6403 06:51:51.698878 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 06:51:51.702263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 06:51:51.702687 ==
6406 06:51:51.703027 DQS Delay:
6407 06:51:51.705635 DQS0 = 59, DQS1 = 59
6408 06:51:51.706137 DQM Delay:
6409 06:51:51.708915 DQM0 = 18, DQM1 = 10
6410 06:51:51.709338 DQ Delay:
6411 06:51:51.712872 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6412 06:51:51.715471 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6413 06:51:51.719155 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6414 06:51:51.722118 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6415 06:51:51.722545
6416 06:51:51.722880
6417 06:51:51.723187 ==
6418 06:51:51.725664 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 06:51:51.729108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 06:51:51.729676 ==
6421 06:51:51.730015
6422 06:51:51.730324
6423 06:51:51.732091 TX Vref Scan disable
6424 06:51:51.732611 == TX Byte 0 ==
6425 06:51:51.739066 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6426 06:51:51.742362 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6427 06:51:51.742892 == TX Byte 1 ==
6428 06:51:51.748621 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6429 06:51:51.751913 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6430 06:51:51.752572 ==
6431 06:51:51.755627 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 06:51:51.758532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 06:51:51.759057 ==
6434 06:51:51.759393
6435 06:51:51.759742
6436 06:51:51.761830 TX Vref Scan disable
6437 06:51:51.762250 == TX Byte 0 ==
6438 06:51:51.768913 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6439 06:51:51.771902 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6440 06:51:51.772426 == TX Byte 1 ==
6441 06:51:51.778524 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6442 06:51:51.782174 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6443 06:51:51.782704
6444 06:51:51.783041 [DATLAT]
6445 06:51:51.785228 Freq=400, CH0 RK0
6446 06:51:51.785797
6447 06:51:51.786136 DATLAT Default: 0xf
6448 06:51:51.788629 0, 0xFFFF, sum = 0
6449 06:51:51.789173 1, 0xFFFF, sum = 0
6450 06:51:51.791731 2, 0xFFFF, sum = 0
6451 06:51:51.792262 3, 0xFFFF, sum = 0
6452 06:51:51.795130 4, 0xFFFF, sum = 0
6453 06:51:51.795560 5, 0xFFFF, sum = 0
6454 06:51:51.798221 6, 0xFFFF, sum = 0
6455 06:51:51.801783 7, 0xFFFF, sum = 0
6456 06:51:51.802211 8, 0xFFFF, sum = 0
6457 06:51:51.805049 9, 0xFFFF, sum = 0
6458 06:51:51.805629 10, 0xFFFF, sum = 0
6459 06:51:51.808274 11, 0xFFFF, sum = 0
6460 06:51:51.808701 12, 0xFFFF, sum = 0
6461 06:51:51.811784 13, 0x0, sum = 1
6462 06:51:51.812314 14, 0x0, sum = 2
6463 06:51:51.815597 15, 0x0, sum = 3
6464 06:51:51.816128 16, 0x0, sum = 4
6465 06:51:51.816469 best_step = 14
6466 06:51:51.816866
6467 06:51:51.818447 ==
6468 06:51:51.821916 Dram Type= 6, Freq= 0, CH_0, rank 0
6469 06:51:51.824942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 06:51:51.825369 ==
6471 06:51:51.825741 RX Vref Scan: 1
6472 06:51:51.826060
6473 06:51:51.828396 RX Vref 0 -> 0, step: 1
6474 06:51:51.828814
6475 06:51:51.831584 RX Delay -359 -> 252, step: 8
6476 06:51:51.832011
6477 06:51:51.835024 Set Vref, RX VrefLevel [Byte0]: 61
6478 06:51:51.838444 [Byte1]: 53
6479 06:51:51.842477
6480 06:51:51.843006 Final RX Vref Byte 0 = 61 to rank0
6481 06:51:51.845360 Final RX Vref Byte 1 = 53 to rank0
6482 06:51:51.848324 Final RX Vref Byte 0 = 61 to rank1
6483 06:51:51.851769 Final RX Vref Byte 1 = 53 to rank1==
6484 06:51:51.855539 Dram Type= 6, Freq= 0, CH_0, rank 0
6485 06:51:51.861961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 06:51:51.862473 ==
6487 06:51:51.862810 DQS Delay:
6488 06:51:51.865078 DQS0 = 60, DQS1 = 68
6489 06:51:51.865642 DQM Delay:
6490 06:51:51.865991 DQM0 = 14, DQM1 = 13
6491 06:51:51.868522 DQ Delay:
6492 06:51:51.872037 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6493 06:51:51.875508 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6494 06:51:51.876037 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6495 06:51:51.881928 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6496 06:51:51.882456
6497 06:51:51.882794
6498 06:51:51.888770 [DQSOSCAuto] RK0, (LSB)MR18= 0x8584, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6499 06:51:51.891574 CH0 RK0: MR19=C0C, MR18=8584
6500 06:51:51.898231 CH0_RK0: MR19=0xC0C, MR18=0x8584, DQSOSC=393, MR23=63, INC=382, DEC=254
6501 06:51:51.898786 ==
6502 06:51:51.901367 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 06:51:51.905139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 06:51:51.905697 ==
6505 06:51:51.908138 [Gating] SW mode calibration
6506 06:51:51.914732 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6507 06:51:51.921548 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6508 06:51:51.924828 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6509 06:51:51.927771 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6510 06:51:51.934462 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 06:51:51.938055 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6512 06:51:51.942019 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 06:51:51.948022 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 06:51:51.950938 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 06:51:51.954352 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6516 06:51:51.961217 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6517 06:51:51.961792 Total UI for P1: 0, mck2ui 16
6518 06:51:51.967864 best dqsien dly found for B0: ( 0, 14, 24)
6519 06:51:51.968395 Total UI for P1: 0, mck2ui 16
6520 06:51:51.974406 best dqsien dly found for B1: ( 0, 14, 24)
6521 06:51:51.977380 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6522 06:51:51.980984 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6523 06:51:51.981558
6524 06:51:51.984361 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6525 06:51:51.987457 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6526 06:51:51.990796 [Gating] SW calibration Done
6527 06:51:51.991223 ==
6528 06:51:51.993916 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 06:51:51.997752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 06:51:51.998182 ==
6531 06:51:52.001178 RX Vref Scan: 0
6532 06:51:52.001633
6533 06:51:52.001989 RX Vref 0 -> 0, step: 1
6534 06:51:52.002307
6535 06:51:52.004393 RX Delay -410 -> 252, step: 16
6536 06:51:52.011441 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6537 06:51:52.014404 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6538 06:51:52.017379 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6539 06:51:52.020666 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6540 06:51:52.027301 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6541 06:51:52.031096 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6542 06:51:52.034140 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6543 06:51:52.037397 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6544 06:51:52.043736 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6545 06:51:52.047369 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6546 06:51:52.050600 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6547 06:51:52.053969 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6548 06:51:52.060747 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6549 06:51:52.064009 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6550 06:51:52.066888 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6551 06:51:52.073945 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6552 06:51:52.074501 ==
6553 06:51:52.077154 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 06:51:52.080581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 06:51:52.081121 ==
6556 06:51:52.081464 DQS Delay:
6557 06:51:52.083685 DQS0 = 59, DQS1 = 59
6558 06:51:52.084217 DQM Delay:
6559 06:51:52.087104 DQM0 = 15, DQM1 = 10
6560 06:51:52.087637 DQ Delay:
6561 06:51:52.090140 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6562 06:51:52.094014 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6563 06:51:52.097424 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6564 06:51:52.100429 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6565 06:51:52.100964
6566 06:51:52.101301
6567 06:51:52.101691 ==
6568 06:51:52.103329 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 06:51:52.106845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 06:51:52.107411 ==
6571 06:51:52.107755
6572 06:51:52.108069
6573 06:51:52.109855 TX Vref Scan disable
6574 06:51:52.110281 == TX Byte 0 ==
6575 06:51:52.116792 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6576 06:51:52.120096 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6577 06:51:52.120538 == TX Byte 1 ==
6578 06:51:52.126548 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6579 06:51:52.129647 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6580 06:51:52.130079 ==
6581 06:51:52.133312 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 06:51:52.136534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 06:51:52.137013 ==
6584 06:51:52.137361
6585 06:51:52.137711
6586 06:51:52.139816 TX Vref Scan disable
6587 06:51:52.143152 == TX Byte 0 ==
6588 06:51:52.146442 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6589 06:51:52.150215 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6590 06:51:52.153319 == TX Byte 1 ==
6591 06:51:52.156463 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6592 06:51:52.159561 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6593 06:51:52.159986
6594 06:51:52.160320 [DATLAT]
6595 06:51:52.163246 Freq=400, CH0 RK1
6596 06:51:52.163940
6597 06:51:52.164302 DATLAT Default: 0xe
6598 06:51:52.166199 0, 0xFFFF, sum = 0
6599 06:51:52.166631 1, 0xFFFF, sum = 0
6600 06:51:52.169529 2, 0xFFFF, sum = 0
6601 06:51:52.169964 3, 0xFFFF, sum = 0
6602 06:51:52.173235 4, 0xFFFF, sum = 0
6603 06:51:52.176629 5, 0xFFFF, sum = 0
6604 06:51:52.177167 6, 0xFFFF, sum = 0
6605 06:51:52.179772 7, 0xFFFF, sum = 0
6606 06:51:52.180329 8, 0xFFFF, sum = 0
6607 06:51:52.183266 9, 0xFFFF, sum = 0
6608 06:51:52.183818 10, 0xFFFF, sum = 0
6609 06:51:52.186188 11, 0xFFFF, sum = 0
6610 06:51:52.186620 12, 0xFFFF, sum = 0
6611 06:51:52.189469 13, 0x0, sum = 1
6612 06:51:52.189921 14, 0x0, sum = 2
6613 06:51:52.193323 15, 0x0, sum = 3
6614 06:51:52.193912 16, 0x0, sum = 4
6615 06:51:52.196098 best_step = 14
6616 06:51:52.196520
6617 06:51:52.196852 ==
6618 06:51:52.199479 Dram Type= 6, Freq= 0, CH_0, rank 1
6619 06:51:52.202768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 06:51:52.203199 ==
6621 06:51:52.203536 RX Vref Scan: 0
6622 06:51:52.203852
6623 06:51:52.206172 RX Vref 0 -> 0, step: 1
6624 06:51:52.206596
6625 06:51:52.209275 RX Delay -359 -> 252, step: 8
6626 06:51:52.216821 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6627 06:51:52.220036 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6628 06:51:52.223275 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6629 06:51:52.226958 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6630 06:51:52.233298 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6631 06:51:52.236650 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6632 06:51:52.240026 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6633 06:51:52.243074 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6634 06:51:52.250018 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6635 06:51:52.253515 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6636 06:51:52.256763 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6637 06:51:52.260173 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6638 06:51:52.266934 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6639 06:51:52.269986 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6640 06:51:52.273355 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6641 06:51:52.280136 iDelay=217, Bit 15, Center -52 (-303 ~ 200) 504
6642 06:51:52.280680 ==
6643 06:51:52.283526 Dram Type= 6, Freq= 0, CH_0, rank 1
6644 06:51:52.287037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 06:51:52.287577 ==
6646 06:51:52.288030 DQS Delay:
6647 06:51:52.290100 DQS0 = 60, DQS1 = 72
6648 06:51:52.290538 DQM Delay:
6649 06:51:52.293109 DQM0 = 11, DQM1 = 17
6650 06:51:52.293581 DQ Delay:
6651 06:51:52.296361 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6652 06:51:52.299664 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6653 06:51:52.302994 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6654 06:51:52.306650 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =20
6655 06:51:52.307186
6656 06:51:52.307635
6657 06:51:52.313103 [DQSOSCAuto] RK1, (LSB)MR18= 0xcd82, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6658 06:51:52.316404 CH0 RK1: MR19=C0C, MR18=CD82
6659 06:51:52.323117 CH0_RK1: MR19=0xC0C, MR18=0xCD82, DQSOSC=384, MR23=63, INC=400, DEC=267
6660 06:51:52.326624 [RxdqsGatingPostProcess] freq 400
6661 06:51:52.333101 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6662 06:51:52.336601 best DQS0 dly(2T, 0.5T) = (0, 10)
6663 06:51:52.337145 best DQS1 dly(2T, 0.5T) = (0, 10)
6664 06:51:52.339706 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6665 06:51:52.343178 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6666 06:51:52.346094 best DQS0 dly(2T, 0.5T) = (0, 10)
6667 06:51:52.349533 best DQS1 dly(2T, 0.5T) = (0, 10)
6668 06:51:52.352755 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6669 06:51:52.355986 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6670 06:51:52.359978 Pre-setting of DQS Precalculation
6671 06:51:52.366066 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6672 06:51:52.366594 ==
6673 06:51:52.369503 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 06:51:52.372742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 06:51:52.373182 ==
6676 06:51:52.379617 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6677 06:51:52.383101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6678 06:51:52.386171 [CA 0] Center 36 (8~64) winsize 57
6679 06:51:52.389315 [CA 1] Center 36 (8~64) winsize 57
6680 06:51:52.393059 [CA 2] Center 36 (8~64) winsize 57
6681 06:51:52.395764 [CA 3] Center 36 (8~64) winsize 57
6682 06:51:52.399372 [CA 4] Center 36 (8~64) winsize 57
6683 06:51:52.402774 [CA 5] Center 36 (8~64) winsize 57
6684 06:51:52.403213
6685 06:51:52.405821 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6686 06:51:52.406260
6687 06:51:52.408963 [CATrainingPosCal] consider 1 rank data
6688 06:51:52.412493 u2DelayCellTimex100 = 270/100 ps
6689 06:51:52.415599 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 06:51:52.419105 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 06:51:52.422212 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 06:51:52.429162 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 06:51:52.432785 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 06:51:52.435758 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 06:51:52.436196
6696 06:51:52.439624 CA PerBit enable=1, Macro0, CA PI delay=36
6697 06:51:52.440166
6698 06:51:52.442229 [CBTSetCACLKResult] CA Dly = 36
6699 06:51:52.442668 CS Dly: 1 (0~32)
6700 06:51:52.443111 ==
6701 06:51:52.445737 Dram Type= 6, Freq= 0, CH_1, rank 1
6702 06:51:52.452569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 06:51:52.453127 ==
6704 06:51:52.455496 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6705 06:51:52.462149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6706 06:51:52.465443 [CA 0] Center 36 (8~64) winsize 57
6707 06:51:52.468951 [CA 1] Center 36 (8~64) winsize 57
6708 06:51:52.472139 [CA 2] Center 36 (8~64) winsize 57
6709 06:51:52.475791 [CA 3] Center 36 (8~64) winsize 57
6710 06:51:52.478585 [CA 4] Center 36 (8~64) winsize 57
6711 06:51:52.482058 [CA 5] Center 36 (8~64) winsize 57
6712 06:51:52.482485
6713 06:51:52.485729 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6714 06:51:52.486258
6715 06:51:52.488676 [CATrainingPosCal] consider 2 rank data
6716 06:51:52.491878 u2DelayCellTimex100 = 270/100 ps
6717 06:51:52.495210 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 06:51:52.498486 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 06:51:52.501819 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 06:51:52.505381 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 06:51:52.508949 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 06:51:52.515134 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 06:51:52.515662
6724 06:51:52.518228 CA PerBit enable=1, Macro0, CA PI delay=36
6725 06:51:52.518678
6726 06:51:52.521587 [CBTSetCACLKResult] CA Dly = 36
6727 06:51:52.522010 CS Dly: 1 (0~32)
6728 06:51:52.522348
6729 06:51:52.525300 ----->DramcWriteLeveling(PI) begin...
6730 06:51:52.525834 ==
6731 06:51:52.528758 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 06:51:52.534994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 06:51:52.535529 ==
6734 06:51:52.538166 Write leveling (Byte 0): 40 => 8
6735 06:51:52.538594 Write leveling (Byte 1): 40 => 8
6736 06:51:52.541705 DramcWriteLeveling(PI) end<-----
6737 06:51:52.542230
6738 06:51:52.542574 ==
6739 06:51:52.544783 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 06:51:52.551258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 06:51:52.551774 ==
6742 06:51:52.554824 [Gating] SW mode calibration
6743 06:51:52.561581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6744 06:51:52.564706 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6745 06:51:52.571461 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6746 06:51:52.574398 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6747 06:51:52.577560 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 06:51:52.584908 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6749 06:51:52.588151 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 06:51:52.591424 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 06:51:52.597728 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6752 06:51:52.601289 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6753 06:51:52.604541 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6754 06:51:52.607564 Total UI for P1: 0, mck2ui 16
6755 06:51:52.610733 best dqsien dly found for B0: ( 0, 14, 24)
6756 06:51:52.613997 Total UI for P1: 0, mck2ui 16
6757 06:51:52.617431 best dqsien dly found for B1: ( 0, 14, 24)
6758 06:51:52.620576 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6759 06:51:52.623921 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6760 06:51:52.624348
6761 06:51:52.631061 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6762 06:51:52.634259 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6763 06:51:52.634796 [Gating] SW calibration Done
6764 06:51:52.637690 ==
6765 06:51:52.640454 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 06:51:52.643838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 06:51:52.644266 ==
6768 06:51:52.644607 RX Vref Scan: 0
6769 06:51:52.644925
6770 06:51:52.647590 RX Vref 0 -> 0, step: 1
6771 06:51:52.648113
6772 06:51:52.650407 RX Delay -410 -> 252, step: 16
6773 06:51:52.654228 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6774 06:51:52.660789 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6775 06:51:52.663795 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6776 06:51:52.667392 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6777 06:51:52.670296 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6778 06:51:52.676614 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6779 06:51:52.680393 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6780 06:51:52.683437 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6781 06:51:52.686918 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6782 06:51:52.693827 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6783 06:51:52.696612 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6784 06:51:52.700443 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6785 06:51:52.703276 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6786 06:51:52.709699 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6787 06:51:52.712777 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6788 06:51:52.716158 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6789 06:51:52.716586 ==
6790 06:51:52.719947 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 06:51:52.726369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 06:51:52.726803 ==
6793 06:51:52.727143 DQS Delay:
6794 06:51:52.729512 DQS0 = 51, DQS1 = 67
6795 06:51:52.729938 DQM Delay:
6796 06:51:52.730276 DQM0 = 13, DQM1 = 18
6797 06:51:52.733105 DQ Delay:
6798 06:51:52.735959 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6799 06:51:52.736396 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6800 06:51:52.739432 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6801 06:51:52.742594 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6802 06:51:52.746029
6803 06:51:52.746454
6804 06:51:52.746788 ==
6805 06:51:52.749581 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 06:51:52.752598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 06:51:52.753024 ==
6808 06:51:52.753362
6809 06:51:52.753733
6810 06:51:52.756008 TX Vref Scan disable
6811 06:51:52.756432 == TX Byte 0 ==
6812 06:51:52.759406 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6813 06:51:52.766216 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6814 06:51:52.766644 == TX Byte 1 ==
6815 06:51:52.769161 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6816 06:51:52.776071 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6817 06:51:52.776599 ==
6818 06:51:52.779615 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 06:51:52.782378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 06:51:52.782809 ==
6821 06:51:52.783146
6822 06:51:52.783458
6823 06:51:52.785668 TX Vref Scan disable
6824 06:51:52.786095 == TX Byte 0 ==
6825 06:51:52.792575 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6826 06:51:52.795416 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6827 06:51:52.795847 == TX Byte 1 ==
6828 06:51:52.802189 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6829 06:51:52.805722 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6830 06:51:52.806256
6831 06:51:52.806598 [DATLAT]
6832 06:51:52.809069 Freq=400, CH1 RK0
6833 06:51:52.809638
6834 06:51:52.809980 DATLAT Default: 0xf
6835 06:51:52.812268 0, 0xFFFF, sum = 0
6836 06:51:52.812700 1, 0xFFFF, sum = 0
6837 06:51:52.815582 2, 0xFFFF, sum = 0
6838 06:51:52.816115 3, 0xFFFF, sum = 0
6839 06:51:52.818602 4, 0xFFFF, sum = 0
6840 06:51:52.819034 5, 0xFFFF, sum = 0
6841 06:51:52.821859 6, 0xFFFF, sum = 0
6842 06:51:52.822292 7, 0xFFFF, sum = 0
6843 06:51:52.825190 8, 0xFFFF, sum = 0
6844 06:51:52.825665 9, 0xFFFF, sum = 0
6845 06:51:52.829203 10, 0xFFFF, sum = 0
6846 06:51:52.832423 11, 0xFFFF, sum = 0
6847 06:51:52.832950 12, 0xFFFF, sum = 0
6848 06:51:52.835229 13, 0x0, sum = 1
6849 06:51:52.835666 14, 0x0, sum = 2
6850 06:51:52.836012 15, 0x0, sum = 3
6851 06:51:52.838959 16, 0x0, sum = 4
6852 06:51:52.839487 best_step = 14
6853 06:51:52.839829
6854 06:51:52.842267 ==
6855 06:51:52.842797 Dram Type= 6, Freq= 0, CH_1, rank 0
6856 06:51:52.848728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 06:51:52.849257 ==
6858 06:51:52.849654 RX Vref Scan: 1
6859 06:51:52.849983
6860 06:51:52.851932 RX Vref 0 -> 0, step: 1
6861 06:51:52.852461
6862 06:51:52.855142 RX Delay -375 -> 252, step: 8
6863 06:51:52.855567
6864 06:51:52.858454 Set Vref, RX VrefLevel [Byte0]: 57
6865 06:51:52.861379 [Byte1]: 53
6866 06:51:52.865440
6867 06:51:52.866006 Final RX Vref Byte 0 = 57 to rank0
6868 06:51:52.868868 Final RX Vref Byte 1 = 53 to rank0
6869 06:51:52.872551 Final RX Vref Byte 0 = 57 to rank1
6870 06:51:52.875807 Final RX Vref Byte 1 = 53 to rank1==
6871 06:51:52.878981 Dram Type= 6, Freq= 0, CH_1, rank 0
6872 06:51:52.885363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 06:51:52.885993 ==
6874 06:51:52.886344 DQS Delay:
6875 06:51:52.888934 DQS0 = 56, DQS1 = 64
6876 06:51:52.889458 DQM Delay:
6877 06:51:52.889852 DQM0 = 13, DQM1 = 10
6878 06:51:52.891556 DQ Delay:
6879 06:51:52.895159 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6880 06:51:52.895687 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6881 06:51:52.898377 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6882 06:51:52.902081 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6883 06:51:52.905361
6884 06:51:52.905922
6885 06:51:52.911627 [DQSOSCAuto] RK0, (LSB)MR18= 0x596b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6886 06:51:52.915072 CH1 RK0: MR19=C0C, MR18=596B
6887 06:51:52.921447 CH1_RK0: MR19=0xC0C, MR18=0x596B, DQSOSC=396, MR23=63, INC=376, DEC=251
6888 06:51:52.921987 ==
6889 06:51:52.924975 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 06:51:52.928560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 06:51:52.929093 ==
6892 06:51:52.931756 [Gating] SW mode calibration
6893 06:51:52.938341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6894 06:51:52.945074 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6895 06:51:52.948470 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6896 06:51:52.952000 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6897 06:51:52.958480 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 06:51:52.961852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6899 06:51:52.964953 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 06:51:52.971458 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 06:51:52.974615 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6902 06:51:52.978191 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6903 06:51:52.984866 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6904 06:51:52.985430 Total UI for P1: 0, mck2ui 16
6905 06:51:52.988188 best dqsien dly found for B0: ( 0, 14, 24)
6906 06:51:52.991804 Total UI for P1: 0, mck2ui 16
6907 06:51:52.994481 best dqsien dly found for B1: ( 0, 14, 24)
6908 06:51:52.997911 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6909 06:51:53.004383 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6910 06:51:53.004883
6911 06:51:53.007607 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6912 06:51:53.011066 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6913 06:51:53.014732 [Gating] SW calibration Done
6914 06:51:53.015262 ==
6915 06:51:53.018175 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 06:51:53.021415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 06:51:53.021982 ==
6918 06:51:53.024786 RX Vref Scan: 0
6919 06:51:53.025311
6920 06:51:53.025716 RX Vref 0 -> 0, step: 1
6921 06:51:53.026041
6922 06:51:53.028087 RX Delay -410 -> 252, step: 16
6923 06:51:53.031346 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6924 06:51:53.037812 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6925 06:51:53.040747 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6926 06:51:53.044220 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6927 06:51:53.047536 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6928 06:51:53.054470 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6929 06:51:53.057903 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6930 06:51:53.060923 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6931 06:51:53.064365 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6932 06:51:53.071124 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6933 06:51:53.074197 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6934 06:51:53.077702 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6935 06:51:53.084199 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6936 06:51:53.087764 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6937 06:51:53.090896 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6938 06:51:53.094124 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6939 06:51:53.094548 ==
6940 06:51:53.097254 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 06:51:53.103969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 06:51:53.104486 ==
6943 06:51:53.104823 DQS Delay:
6944 06:51:53.107391 DQS0 = 59, DQS1 = 59
6945 06:51:53.107829 DQM Delay:
6946 06:51:53.110656 DQM0 = 19, DQM1 = 14
6947 06:51:53.111180 DQ Delay:
6948 06:51:53.114426 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6949 06:51:53.117316 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6950 06:51:53.121222 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6951 06:51:53.124329 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6952 06:51:53.124850
6953 06:51:53.125187
6954 06:51:53.125551 ==
6955 06:51:53.127193 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 06:51:53.130624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 06:51:53.131154 ==
6958 06:51:53.131487
6959 06:51:53.131798
6960 06:51:53.134116 TX Vref Scan disable
6961 06:51:53.134647 == TX Byte 0 ==
6962 06:51:53.140679 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6963 06:51:53.143842 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6964 06:51:53.144276 == TX Byte 1 ==
6965 06:51:53.150837 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6966 06:51:53.153894 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6967 06:51:53.154422 ==
6968 06:51:53.157152 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 06:51:53.160153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 06:51:53.160749 ==
6971 06:51:53.161093
6972 06:51:53.161404
6973 06:51:53.163830 TX Vref Scan disable
6974 06:51:53.164356 == TX Byte 0 ==
6975 06:51:53.170350 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6976 06:51:53.173461 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6977 06:51:53.173926 == TX Byte 1 ==
6978 06:51:53.180627 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6979 06:51:53.183988 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6980 06:51:53.184517
6981 06:51:53.184854 [DATLAT]
6982 06:51:53.186970 Freq=400, CH1 RK1
6983 06:51:53.187497
6984 06:51:53.187834 DATLAT Default: 0xe
6985 06:51:53.190398 0, 0xFFFF, sum = 0
6986 06:51:53.190926 1, 0xFFFF, sum = 0
6987 06:51:53.193804 2, 0xFFFF, sum = 0
6988 06:51:53.194336 3, 0xFFFF, sum = 0
6989 06:51:53.196602 4, 0xFFFF, sum = 0
6990 06:51:53.197030 5, 0xFFFF, sum = 0
6991 06:51:53.200318 6, 0xFFFF, sum = 0
6992 06:51:53.200850 7, 0xFFFF, sum = 0
6993 06:51:53.203263 8, 0xFFFF, sum = 0
6994 06:51:53.203692 9, 0xFFFF, sum = 0
6995 06:51:53.206699 10, 0xFFFF, sum = 0
6996 06:51:53.210364 11, 0xFFFF, sum = 0
6997 06:51:53.210896 12, 0xFFFF, sum = 0
6998 06:51:53.213308 13, 0x0, sum = 1
6999 06:51:53.213893 14, 0x0, sum = 2
7000 06:51:53.214270 15, 0x0, sum = 3
7001 06:51:53.216966 16, 0x0, sum = 4
7002 06:51:53.217534 best_step = 14
7003 06:51:53.217882
7004 06:51:53.218344 ==
7005 06:51:53.220481 Dram Type= 6, Freq= 0, CH_1, rank 1
7006 06:51:53.226806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7007 06:51:53.227234 ==
7008 06:51:53.227570 RX Vref Scan: 0
7009 06:51:53.227889
7010 06:51:53.229954 RX Vref 0 -> 0, step: 1
7011 06:51:53.230428
7012 06:51:53.233426 RX Delay -359 -> 252, step: 8
7013 06:51:53.240413 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7014 06:51:53.243746 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7015 06:51:53.246788 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7016 06:51:53.250126 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7017 06:51:53.256520 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7018 06:51:53.259681 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7019 06:51:53.263581 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7020 06:51:53.266850 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7021 06:51:53.273301 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7022 06:51:53.276464 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7023 06:51:53.279490 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7024 06:51:53.286364 iDelay=217, Bit 11, Center -56 (-311 ~ 200) 512
7025 06:51:53.290128 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7026 06:51:53.293102 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7027 06:51:53.296465 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7028 06:51:53.303018 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7029 06:51:53.303529 ==
7030 06:51:53.306036 Dram Type= 6, Freq= 0, CH_1, rank 1
7031 06:51:53.309843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7032 06:51:53.310371 ==
7033 06:51:53.310714 DQS Delay:
7034 06:51:53.312668 DQS0 = 60, DQS1 = 64
7035 06:51:53.313091 DQM Delay:
7036 06:51:53.316522 DQM0 = 12, DQM1 = 11
7037 06:51:53.317044 DQ Delay:
7038 06:51:53.319412 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7039 06:51:53.322729 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7040 06:51:53.325951 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
7041 06:51:53.329639 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7042 06:51:53.330161
7043 06:51:53.330499
7044 06:51:53.336115 [DQSOSCAuto] RK1, (LSB)MR18= 0x81b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
7045 06:51:53.339323 CH1 RK1: MR19=C0C, MR18=81B1
7046 06:51:53.346417 CH1_RK1: MR19=0xC0C, MR18=0x81B1, DQSOSC=387, MR23=63, INC=394, DEC=262
7047 06:51:53.349716 [RxdqsGatingPostProcess] freq 400
7048 06:51:53.356356 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7049 06:51:53.359415 best DQS0 dly(2T, 0.5T) = (0, 10)
7050 06:51:53.359842 best DQS1 dly(2T, 0.5T) = (0, 10)
7051 06:51:53.362622 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7052 06:51:53.366199 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7053 06:51:53.369555 best DQS0 dly(2T, 0.5T) = (0, 10)
7054 06:51:53.373069 best DQS1 dly(2T, 0.5T) = (0, 10)
7055 06:51:53.376237 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7056 06:51:53.379683 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7057 06:51:53.382848 Pre-setting of DQS Precalculation
7058 06:51:53.389403 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7059 06:51:53.396166 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7060 06:51:53.402666 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7061 06:51:53.403093
7062 06:51:53.403432
7063 06:51:53.406274 [Calibration Summary] 800 Mbps
7064 06:51:53.406699 CH 0, Rank 0
7065 06:51:53.409428 SW Impedance : PASS
7066 06:51:53.409982 DUTY Scan : NO K
7067 06:51:53.412834 ZQ Calibration : PASS
7068 06:51:53.416280 Jitter Meter : NO K
7069 06:51:53.416807 CBT Training : PASS
7070 06:51:53.419433 Write leveling : PASS
7071 06:51:53.422725 RX DQS gating : PASS
7072 06:51:53.423150 RX DQ/DQS(RDDQC) : PASS
7073 06:51:53.425876 TX DQ/DQS : PASS
7074 06:51:53.429605 RX DATLAT : PASS
7075 06:51:53.430129 RX DQ/DQS(Engine): PASS
7076 06:51:53.432699 TX OE : NO K
7077 06:51:53.433224 All Pass.
7078 06:51:53.433607
7079 06:51:53.436047 CH 0, Rank 1
7080 06:51:53.436573 SW Impedance : PASS
7081 06:51:53.439279 DUTY Scan : NO K
7082 06:51:53.442418 ZQ Calibration : PASS
7083 06:51:53.442855 Jitter Meter : NO K
7084 06:51:53.446067 CBT Training : PASS
7085 06:51:53.449138 Write leveling : NO K
7086 06:51:53.449706 RX DQS gating : PASS
7087 06:51:53.452563 RX DQ/DQS(RDDQC) : PASS
7088 06:51:53.456102 TX DQ/DQS : PASS
7089 06:51:53.456632 RX DATLAT : PASS
7090 06:51:53.458985 RX DQ/DQS(Engine): PASS
7091 06:51:53.462173 TX OE : NO K
7092 06:51:53.462652 All Pass.
7093 06:51:53.462994
7094 06:51:53.463311 CH 1, Rank 0
7095 06:51:53.465533 SW Impedance : PASS
7096 06:51:53.468910 DUTY Scan : NO K
7097 06:51:53.469433 ZQ Calibration : PASS
7098 06:51:53.472441 Jitter Meter : NO K
7099 06:51:53.472966 CBT Training : PASS
7100 06:51:53.475440 Write leveling : PASS
7101 06:51:53.478944 RX DQS gating : PASS
7102 06:51:53.479472 RX DQ/DQS(RDDQC) : PASS
7103 06:51:53.482013 TX DQ/DQS : PASS
7104 06:51:53.485607 RX DATLAT : PASS
7105 06:51:53.486131 RX DQ/DQS(Engine): PASS
7106 06:51:53.489002 TX OE : NO K
7107 06:51:53.489587 All Pass.
7108 06:51:53.489944
7109 06:51:53.492427 CH 1, Rank 1
7110 06:51:53.492953 SW Impedance : PASS
7111 06:51:53.495415 DUTY Scan : NO K
7112 06:51:53.498719 ZQ Calibration : PASS
7113 06:51:53.499146 Jitter Meter : NO K
7114 06:51:53.501885 CBT Training : PASS
7115 06:51:53.505416 Write leveling : NO K
7116 06:51:53.505999 RX DQS gating : PASS
7117 06:51:53.508476 RX DQ/DQS(RDDQC) : PASS
7118 06:51:53.511803 TX DQ/DQS : PASS
7119 06:51:53.512332 RX DATLAT : PASS
7120 06:51:53.515326 RX DQ/DQS(Engine): PASS
7121 06:51:53.518498 TX OE : NO K
7122 06:51:53.519013 All Pass.
7123 06:51:53.519352
7124 06:51:53.519660 DramC Write-DBI off
7125 06:51:53.521776 PER_BANK_REFRESH: Hybrid Mode
7126 06:51:53.525378 TX_TRACKING: ON
7127 06:51:53.532109 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7128 06:51:53.535720 [FAST_K] Save calibration result to emmc
7129 06:51:53.542382 dramc_set_vcore_voltage set vcore to 725000
7130 06:51:53.542914 Read voltage for 1600, 0
7131 06:51:53.545528 Vio18 = 0
7132 06:51:53.546056 Vcore = 725000
7133 06:51:53.546399 Vdram = 0
7134 06:51:53.546715 Vddq = 0
7135 06:51:53.548519 Vmddr = 0
7136 06:51:53.552096 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7137 06:51:53.558464 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7138 06:51:53.561691 MEM_TYPE=3, freq_sel=13
7139 06:51:53.562207 sv_algorithm_assistance_LP4_3733
7140 06:51:53.568839 ============ PULL DRAM RESETB DOWN ============
7141 06:51:53.572094 ========== PULL DRAM RESETB DOWN end =========
7142 06:51:53.575059 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7143 06:51:53.578418 ===================================
7144 06:51:53.581537 LPDDR4 DRAM CONFIGURATION
7145 06:51:53.585253 ===================================
7146 06:51:53.588807 EX_ROW_EN[0] = 0x0
7147 06:51:53.589348 EX_ROW_EN[1] = 0x0
7148 06:51:53.591880 LP4Y_EN = 0x0
7149 06:51:53.592421 WORK_FSP = 0x1
7150 06:51:53.595251 WL = 0x5
7151 06:51:53.595788 RL = 0x5
7152 06:51:53.598069 BL = 0x2
7153 06:51:53.598517 RPST = 0x0
7154 06:51:53.601718 RD_PRE = 0x0
7155 06:51:53.602238 WR_PRE = 0x1
7156 06:51:53.604840 WR_PST = 0x1
7157 06:51:53.608156 DBI_WR = 0x0
7158 06:51:53.608687 DBI_RD = 0x0
7159 06:51:53.611783 OTF = 0x1
7160 06:51:53.615149 ===================================
7161 06:51:53.618342 ===================================
7162 06:51:53.618865 ANA top config
7163 06:51:53.621593 ===================================
7164 06:51:53.624674 DLL_ASYNC_EN = 0
7165 06:51:53.625093 ALL_SLAVE_EN = 0
7166 06:51:53.627953 NEW_RANK_MODE = 1
7167 06:51:53.631500 DLL_IDLE_MODE = 1
7168 06:51:53.634743 LP45_APHY_COMB_EN = 1
7169 06:51:53.637836 TX_ODT_DIS = 0
7170 06:51:53.638356 NEW_8X_MODE = 1
7171 06:51:53.641440 ===================================
7172 06:51:53.644679 ===================================
7173 06:51:53.647814 data_rate = 3200
7174 06:51:53.651203 CKR = 1
7175 06:51:53.654885 DQ_P2S_RATIO = 8
7176 06:51:53.657898 ===================================
7177 06:51:53.661290 CA_P2S_RATIO = 8
7178 06:51:53.664260 DQ_CA_OPEN = 0
7179 06:51:53.664690 DQ_SEMI_OPEN = 0
7180 06:51:53.667893 CA_SEMI_OPEN = 0
7181 06:51:53.671302 CA_FULL_RATE = 0
7182 06:51:53.674310 DQ_CKDIV4_EN = 0
7183 06:51:53.677652 CA_CKDIV4_EN = 0
7184 06:51:53.681134 CA_PREDIV_EN = 0
7185 06:51:53.681719 PH8_DLY = 12
7186 06:51:53.684553 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7187 06:51:53.687894 DQ_AAMCK_DIV = 4
7188 06:51:53.691204 CA_AAMCK_DIV = 4
7189 06:51:53.694334 CA_ADMCK_DIV = 4
7190 06:51:53.697866 DQ_TRACK_CA_EN = 0
7191 06:51:53.698417 CA_PICK = 1600
7192 06:51:53.700884 CA_MCKIO = 1600
7193 06:51:53.704456 MCKIO_SEMI = 0
7194 06:51:53.708046 PLL_FREQ = 3068
7195 06:51:53.710787 DQ_UI_PI_RATIO = 32
7196 06:51:53.714198 CA_UI_PI_RATIO = 0
7197 06:51:53.717659 ===================================
7198 06:51:53.720735 ===================================
7199 06:51:53.724592 memory_type:LPDDR4
7200 06:51:53.725130 GP_NUM : 10
7201 06:51:53.727393 SRAM_EN : 1
7202 06:51:53.727821 MD32_EN : 0
7203 06:51:53.730890 ===================================
7204 06:51:53.734473 [ANA_INIT] >>>>>>>>>>>>>>
7205 06:51:53.737879 <<<<<< [CONFIGURE PHASE]: ANA_TX
7206 06:51:53.740852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7207 06:51:53.744312 ===================================
7208 06:51:53.747749 data_rate = 3200,PCW = 0X7600
7209 06:51:53.750737 ===================================
7210 06:51:53.753872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7211 06:51:53.757641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7212 06:51:53.763730 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7213 06:51:53.770667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7214 06:51:53.774074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7215 06:51:53.776973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7216 06:51:53.777532 [ANA_INIT] flow start
7217 06:51:53.780497 [ANA_INIT] PLL >>>>>>>>
7218 06:51:53.783727 [ANA_INIT] PLL <<<<<<<<
7219 06:51:53.784203 [ANA_INIT] MIDPI >>>>>>>>
7220 06:51:53.786974 [ANA_INIT] MIDPI <<<<<<<<
7221 06:51:53.790124 [ANA_INIT] DLL >>>>>>>>
7222 06:51:53.790566 [ANA_INIT] DLL <<<<<<<<
7223 06:51:53.793416 [ANA_INIT] flow end
7224 06:51:53.796947 ============ LP4 DIFF to SE enter ============
7225 06:51:53.800382 ============ LP4 DIFF to SE exit ============
7226 06:51:53.804054 [ANA_INIT] <<<<<<<<<<<<<
7227 06:51:53.806977 [Flow] Enable top DCM control >>>>>
7228 06:51:53.810085 [Flow] Enable top DCM control <<<<<
7229 06:51:53.813422 Enable DLL master slave shuffle
7230 06:51:53.820007 ==============================================================
7231 06:51:53.820432 Gating Mode config
7232 06:51:53.826810 ==============================================================
7233 06:51:53.830197 Config description:
7234 06:51:53.836625 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7235 06:51:53.843342 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7236 06:51:53.849871 SELPH_MODE 0: By rank 1: By Phase
7237 06:51:53.857056 ==============================================================
7238 06:51:53.857643 GAT_TRACK_EN = 1
7239 06:51:53.859964 RX_GATING_MODE = 2
7240 06:51:53.863247 RX_GATING_TRACK_MODE = 2
7241 06:51:53.866482 SELPH_MODE = 1
7242 06:51:53.869637 PICG_EARLY_EN = 1
7243 06:51:53.873424 VALID_LAT_VALUE = 1
7244 06:51:53.880111 ==============================================================
7245 06:51:53.883482 Enter into Gating configuration >>>>
7246 06:51:53.886582 Exit from Gating configuration <<<<
7247 06:51:53.890159 Enter into DVFS_PRE_config >>>>>
7248 06:51:53.899591 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7249 06:51:53.903309 Exit from DVFS_PRE_config <<<<<
7250 06:51:53.906505 Enter into PICG configuration >>>>
7251 06:51:53.909781 Exit from PICG configuration <<<<
7252 06:51:53.912841 [RX_INPUT] configuration >>>>>
7253 06:51:53.913272 [RX_INPUT] configuration <<<<<
7254 06:51:53.919617 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7255 06:51:53.926337 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7256 06:51:53.929364 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7257 06:51:53.936461 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7258 06:51:53.942644 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7259 06:51:53.949967 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7260 06:51:53.953252 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7261 06:51:53.956410 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7262 06:51:53.962910 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7263 06:51:53.965919 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7264 06:51:53.969356 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7265 06:51:53.976296 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7266 06:51:53.979158 ===================================
7267 06:51:53.979591 LPDDR4 DRAM CONFIGURATION
7268 06:51:53.982531 ===================================
7269 06:51:53.985729 EX_ROW_EN[0] = 0x0
7270 06:51:53.989337 EX_ROW_EN[1] = 0x0
7271 06:51:53.989802 LP4Y_EN = 0x0
7272 06:51:53.992794 WORK_FSP = 0x1
7273 06:51:53.993320 WL = 0x5
7274 06:51:53.996152 RL = 0x5
7275 06:51:53.996700 BL = 0x2
7276 06:51:53.999300 RPST = 0x0
7277 06:51:53.999743 RD_PRE = 0x0
7278 06:51:54.002414 WR_PRE = 0x1
7279 06:51:54.002860 WR_PST = 0x1
7280 06:51:54.005882 DBI_WR = 0x0
7281 06:51:54.006326 DBI_RD = 0x0
7282 06:51:54.009221 OTF = 0x1
7283 06:51:54.012447 ===================================
7284 06:51:54.015739 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7285 06:51:54.018768 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7286 06:51:54.025777 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7287 06:51:54.029177 ===================================
7288 06:51:54.029774 LPDDR4 DRAM CONFIGURATION
7289 06:51:54.032354 ===================================
7290 06:51:54.035748 EX_ROW_EN[0] = 0x10
7291 06:51:54.036300 EX_ROW_EN[1] = 0x0
7292 06:51:54.038870 LP4Y_EN = 0x0
7293 06:51:54.042065 WORK_FSP = 0x1
7294 06:51:54.042617 WL = 0x5
7295 06:51:54.045941 RL = 0x5
7296 06:51:54.046651 BL = 0x2
7297 06:51:54.048921 RPST = 0x0
7298 06:51:54.049364 RD_PRE = 0x0
7299 06:51:54.052612 WR_PRE = 0x1
7300 06:51:54.053165 WR_PST = 0x1
7301 06:51:54.055568 DBI_WR = 0x0
7302 06:51:54.056119 DBI_RD = 0x0
7303 06:51:54.058622 OTF = 0x1
7304 06:51:54.062415 ===================================
7305 06:51:54.068824 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7306 06:51:54.069378 ==
7307 06:51:54.072357 Dram Type= 6, Freq= 0, CH_0, rank 0
7308 06:51:54.075635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7309 06:51:54.076194 ==
7310 06:51:54.078707 [Duty_Offset_Calibration]
7311 06:51:54.079149 B0:2 B1:0 CA:4
7312 06:51:54.079598
7313 06:51:54.082193 [DutyScan_Calibration_Flow] k_type=0
7314 06:51:54.092301
7315 06:51:54.092848 ==CLK 0==
7316 06:51:54.095646 Final CLK duty delay cell = 0
7317 06:51:54.098760 [0] MAX Duty = 5062%(X100), DQS PI = 20
7318 06:51:54.102143 [0] MIN Duty = 4876%(X100), DQS PI = 54
7319 06:51:54.102588 [0] AVG Duty = 4969%(X100)
7320 06:51:54.105750
7321 06:51:54.109067 CH0 CLK Duty spec in!! Max-Min= 186%
7322 06:51:54.112233 [DutyScan_Calibration_Flow] ====Done====
7323 06:51:54.112774
7324 06:51:54.115486 [DutyScan_Calibration_Flow] k_type=1
7325 06:51:54.132342
7326 06:51:54.132870 ==DQS 0 ==
7327 06:51:54.135676 Final DQS duty delay cell = 0
7328 06:51:54.139145 [0] MAX Duty = 5125%(X100), DQS PI = 30
7329 06:51:54.141913 [0] MIN Duty = 4907%(X100), DQS PI = 0
7330 06:51:54.145673 [0] AVG Duty = 5016%(X100)
7331 06:51:54.146211
7332 06:51:54.146561 ==DQS 1 ==
7333 06:51:54.148761 Final DQS duty delay cell = 0
7334 06:51:54.152403 [0] MAX Duty = 5156%(X100), DQS PI = 32
7335 06:51:54.155672 [0] MIN Duty = 5031%(X100), DQS PI = 14
7336 06:51:54.158743 [0] AVG Duty = 5093%(X100)
7337 06:51:54.159264
7338 06:51:54.162147 CH0 DQS 0 Duty spec in!! Max-Min= 218%
7339 06:51:54.162685
7340 06:51:54.165436 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7341 06:51:54.168939 [DutyScan_Calibration_Flow] ====Done====
7342 06:51:54.169467
7343 06:51:54.171924 [DutyScan_Calibration_Flow] k_type=3
7344 06:51:54.190181
7345 06:51:54.190710 ==DQM 0 ==
7346 06:51:54.193649 Final DQM duty delay cell = 0
7347 06:51:54.196907 [0] MAX Duty = 5156%(X100), DQS PI = 30
7348 06:51:54.200036 [0] MIN Duty = 4844%(X100), DQS PI = 50
7349 06:51:54.200470 [0] AVG Duty = 5000%(X100)
7350 06:51:54.203649
7351 06:51:54.204175 ==DQM 1 ==
7352 06:51:54.206715 Final DQM duty delay cell = 4
7353 06:51:54.210022 [4] MAX Duty = 5187%(X100), DQS PI = 60
7354 06:51:54.214015 [4] MIN Duty = 5031%(X100), DQS PI = 26
7355 06:51:54.216691 [4] AVG Duty = 5109%(X100)
7356 06:51:54.217121
7357 06:51:54.220000 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7358 06:51:54.220432
7359 06:51:54.223467 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7360 06:51:54.226592 [DutyScan_Calibration_Flow] ====Done====
7361 06:51:54.227019
7362 06:51:54.230013 [DutyScan_Calibration_Flow] k_type=2
7363 06:51:54.246998
7364 06:51:54.247524 ==DQ 0 ==
7365 06:51:54.249868 Final DQ duty delay cell = -4
7366 06:51:54.253425 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7367 06:51:54.256582 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7368 06:51:54.260077 [-4] AVG Duty = 4938%(X100)
7369 06:51:54.260608
7370 06:51:54.260956 ==DQ 1 ==
7371 06:51:54.263458 Final DQ duty delay cell = 0
7372 06:51:54.266403 [0] MAX Duty = 5156%(X100), DQS PI = 58
7373 06:51:54.269856 [0] MIN Duty = 5000%(X100), DQS PI = 16
7374 06:51:54.272984 [0] AVG Duty = 5078%(X100)
7375 06:51:54.273580
7376 06:51:54.276243 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7377 06:51:54.276686
7378 06:51:54.279509 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7379 06:51:54.282973 [DutyScan_Calibration_Flow] ====Done====
7380 06:51:54.283415 ==
7381 06:51:54.286336 Dram Type= 6, Freq= 0, CH_1, rank 0
7382 06:51:54.289595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7383 06:51:54.290034 ==
7384 06:51:54.292761 [Duty_Offset_Calibration]
7385 06:51:54.293188 B0:1 B1:-2 CA:0
7386 06:51:54.293593
7387 06:51:54.296391 [DutyScan_Calibration_Flow] k_type=0
7388 06:51:54.307135
7389 06:51:54.307671 ==CLK 0==
7390 06:51:54.310347 Final CLK duty delay cell = 0
7391 06:51:54.314092 [0] MAX Duty = 5062%(X100), DQS PI = 20
7392 06:51:54.317260 [0] MIN Duty = 4844%(X100), DQS PI = 2
7393 06:51:54.317851 [0] AVG Duty = 4953%(X100)
7394 06:51:54.320658
7395 06:51:54.323865 CH1 CLK Duty spec in!! Max-Min= 218%
7396 06:51:54.327094 [DutyScan_Calibration_Flow] ====Done====
7397 06:51:54.327524
7398 06:51:54.330149 [DutyScan_Calibration_Flow] k_type=1
7399 06:51:54.346377
7400 06:51:54.346907 ==DQS 0 ==
7401 06:51:54.349857 Final DQS duty delay cell = -4
7402 06:51:54.352852 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7403 06:51:54.356314 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7404 06:51:54.359727 [-4] AVG Duty = 4922%(X100)
7405 06:51:54.360265
7406 06:51:54.360607 ==DQS 1 ==
7407 06:51:54.363248 Final DQS duty delay cell = 0
7408 06:51:54.365868 [0] MAX Duty = 5093%(X100), DQS PI = 60
7409 06:51:54.369145 [0] MIN Duty = 4844%(X100), DQS PI = 24
7410 06:51:54.372803 [0] AVG Duty = 4968%(X100)
7411 06:51:54.373333
7412 06:51:54.376256 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7413 06:51:54.376795
7414 06:51:54.379460 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7415 06:51:54.382506 [DutyScan_Calibration_Flow] ====Done====
7416 06:51:54.382938
7417 06:51:54.385937 [DutyScan_Calibration_Flow] k_type=3
7418 06:51:54.403328
7419 06:51:54.403902 ==DQM 0 ==
7420 06:51:54.406468 Final DQM duty delay cell = 0
7421 06:51:54.409668 [0] MAX Duty = 5031%(X100), DQS PI = 24
7422 06:51:54.413465 [0] MIN Duty = 4813%(X100), DQS PI = 56
7423 06:51:54.416238 [0] AVG Duty = 4922%(X100)
7424 06:51:54.416666
7425 06:51:54.417006 ==DQM 1 ==
7426 06:51:54.419820 Final DQM duty delay cell = 0
7427 06:51:54.423044 [0] MAX Duty = 5062%(X100), DQS PI = 34
7428 06:51:54.426153 [0] MIN Duty = 4875%(X100), DQS PI = 24
7429 06:51:54.429647 [0] AVG Duty = 4968%(X100)
7430 06:51:54.430097
7431 06:51:54.432899 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7432 06:51:54.433348
7433 06:51:54.436467 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7434 06:51:54.439458 [DutyScan_Calibration_Flow] ====Done====
7435 06:51:54.439918
7436 06:51:54.442984 [DutyScan_Calibration_Flow] k_type=2
7437 06:51:54.460344
7438 06:51:54.460895 ==DQ 0 ==
7439 06:51:54.463917 Final DQ duty delay cell = 0
7440 06:51:54.467011 [0] MAX Duty = 5093%(X100), DQS PI = 22
7441 06:51:54.470030 [0] MIN Duty = 4907%(X100), DQS PI = 60
7442 06:51:54.470484 [0] AVG Duty = 5000%(X100)
7443 06:51:54.473570
7444 06:51:54.474014 ==DQ 1 ==
7445 06:51:54.476906 Final DQ duty delay cell = 0
7446 06:51:54.480322 [0] MAX Duty = 5125%(X100), DQS PI = 34
7447 06:51:54.483548 [0] MIN Duty = 4938%(X100), DQS PI = 24
7448 06:51:54.484104 [0] AVG Duty = 5031%(X100)
7449 06:51:54.486990
7450 06:51:54.490107 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7451 06:51:54.490664
7452 06:51:54.493623 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7453 06:51:54.496981 [DutyScan_Calibration_Flow] ====Done====
7454 06:51:54.500166 nWR fixed to 30
7455 06:51:54.500730 [ModeRegInit_LP4] CH0 RK0
7456 06:51:54.503378 [ModeRegInit_LP4] CH0 RK1
7457 06:51:54.506463 [ModeRegInit_LP4] CH1 RK0
7458 06:51:54.509776 [ModeRegInit_LP4] CH1 RK1
7459 06:51:54.510266 match AC timing 5
7460 06:51:54.516763 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7461 06:51:54.519751 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7462 06:51:54.523040 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7463 06:51:54.529517 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7464 06:51:54.532973 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7465 06:51:54.533653 [MiockJmeterHQA]
7466 06:51:54.534075
7467 06:51:54.537105 [DramcMiockJmeter] u1RxGatingPI = 0
7468 06:51:54.539716 0 : 4252, 4026
7469 06:51:54.540157 4 : 4252, 4026
7470 06:51:54.543151 8 : 4255, 4029
7471 06:51:54.543713 12 : 4253, 4026
7472 06:51:54.544069 16 : 4252, 4027
7473 06:51:54.546307 20 : 4252, 4027
7474 06:51:54.546746 24 : 4255, 4029
7475 06:51:54.549397 28 : 4363, 4138
7476 06:51:54.549901 32 : 4252, 4027
7477 06:51:54.552904 36 : 4252, 4027
7478 06:51:54.553379 40 : 4253, 4026
7479 06:51:54.556507 44 : 4255, 4030
7480 06:51:54.557043 48 : 4252, 4027
7481 06:51:54.557421 52 : 4363, 4139
7482 06:51:54.559813 56 : 4361, 4138
7483 06:51:54.560351 60 : 4250, 4027
7484 06:51:54.563175 64 : 4252, 4029
7485 06:51:54.563711 68 : 4250, 4026
7486 06:51:54.566187 72 : 4250, 4027
7487 06:51:54.566624 76 : 4253, 4029
7488 06:51:54.566971 80 : 4360, 4137
7489 06:51:54.569499 84 : 4250, 4026
7490 06:51:54.569944 88 : 4249, 4027
7491 06:51:54.572615 92 : 4250, 4027
7492 06:51:54.573053 96 : 4253, 4029
7493 06:51:54.576032 100 : 4250, 4027
7494 06:51:54.576475 104 : 4250, 3544
7495 06:51:54.579789 108 : 4250, 3
7496 06:51:54.580331 112 : 4250, 0
7497 06:51:54.580682 116 : 4252, 0
7498 06:51:54.583269 120 : 4250, 0
7499 06:51:54.583803 124 : 4250, 0
7500 06:51:54.586005 128 : 4250, 0
7501 06:51:54.586443 132 : 4363, 0
7502 06:51:54.586795 136 : 4249, 0
7503 06:51:54.589772 140 : 4249, 0
7504 06:51:54.590308 144 : 4250, 0
7505 06:51:54.590657 148 : 4253, 0
7506 06:51:54.593138 152 : 4250, 0
7507 06:51:54.593732 156 : 4250, 0
7508 06:51:54.596308 160 : 4253, 0
7509 06:51:54.596842 164 : 4361, 0
7510 06:51:54.597190 168 : 4250, 0
7511 06:51:54.599524 172 : 4250, 0
7512 06:51:54.599962 176 : 4250, 0
7513 06:51:54.602450 180 : 4361, 0
7514 06:51:54.602889 184 : 4250, 0
7515 06:51:54.603235 188 : 4249, 0
7516 06:51:54.606034 192 : 4250, 0
7517 06:51:54.606502 196 : 4250, 0
7518 06:51:54.609624 200 : 4252, 0
7519 06:51:54.610192 204 : 4250, 0
7520 06:51:54.610564 208 : 4250, 0
7521 06:51:54.612797 212 : 4252, 0
7522 06:51:54.613332 216 : 4360, 0
7523 06:51:54.615800 220 : 4250, 0
7524 06:51:54.616236 224 : 4250, 0
7525 06:51:54.616579 228 : 4250, 0
7526 06:51:54.619354 232 : 4361, 0
7527 06:51:54.619790 236 : 4250, 1490
7528 06:51:54.622577 240 : 4250, 4027
7529 06:51:54.623016 244 : 4361, 4137
7530 06:51:54.625588 248 : 4250, 4027
7531 06:51:54.626071 252 : 4250, 4026
7532 06:51:54.626430 256 : 4362, 4140
7533 06:51:54.628901 260 : 4250, 4027
7534 06:51:54.629339 264 : 4250, 4027
7535 06:51:54.632741 268 : 4250, 4026
7536 06:51:54.633276 272 : 4253, 4029
7537 06:51:54.635820 276 : 4250, 4027
7538 06:51:54.636200 280 : 4250, 4027
7539 06:51:54.639089 284 : 4360, 4137
7540 06:51:54.639526 288 : 4249, 4027
7541 06:51:54.642324 292 : 4250, 4026
7542 06:51:54.642763 296 : 4361, 4138
7543 06:51:54.645910 300 : 4250, 4027
7544 06:51:54.646451 304 : 4250, 4027
7545 06:51:54.649042 308 : 4363, 4140
7546 06:51:54.649641 312 : 4250, 4026
7547 06:51:54.650005 316 : 4250, 4027
7548 06:51:54.652783 320 : 4250, 4027
7549 06:51:54.653320 324 : 4253, 4029
7550 06:51:54.655922 328 : 4250, 4027
7551 06:51:54.656466 332 : 4250, 4027
7552 06:51:54.659238 336 : 4360, 4138
7553 06:51:54.659778 340 : 4250, 4027
7554 06:51:54.662883 344 : 4250, 4027
7555 06:51:54.663418 348 : 4360, 4137
7556 06:51:54.666079 352 : 4250, 4024
7557 06:51:54.666682 356 : 4250, 2606
7558 06:51:54.669054 360 : 4363, 2
7559 06:51:54.669733
7560 06:51:54.670089 MIOCK jitter meter ch=0
7561 06:51:54.670415
7562 06:51:54.672390 1T = (360-108) = 252 dly cells
7563 06:51:54.679169 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7564 06:51:54.679706 ==
7565 06:51:54.682092 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 06:51:54.685967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 06:51:54.686497 ==
7568 06:51:54.692568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7569 06:51:54.695647 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7570 06:51:54.698773 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7571 06:51:54.705633 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7572 06:51:54.715475 [CA 0] Center 43 (13~74) winsize 62
7573 06:51:54.718787 [CA 1] Center 43 (13~74) winsize 62
7574 06:51:54.722255 [CA 2] Center 39 (10~68) winsize 59
7575 06:51:54.725256 [CA 3] Center 39 (10~68) winsize 59
7576 06:51:54.728768 [CA 4] Center 36 (7~66) winsize 60
7577 06:51:54.732224 [CA 5] Center 36 (7~66) winsize 60
7578 06:51:54.732754
7579 06:51:54.735338 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7580 06:51:54.735869
7581 06:51:54.738445 [CATrainingPosCal] consider 1 rank data
7582 06:51:54.741772 u2DelayCellTimex100 = 258/100 ps
7583 06:51:54.748659 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7584 06:51:54.751712 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7585 06:51:54.754811 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7586 06:51:54.758400 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7587 06:51:54.761876 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7588 06:51:54.765325 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7589 06:51:54.765914
7590 06:51:54.768519 CA PerBit enable=1, Macro0, CA PI delay=36
7591 06:51:54.769053
7592 06:51:54.771581 [CBTSetCACLKResult] CA Dly = 36
7593 06:51:54.774941 CS Dly: 11 (0~42)
7594 06:51:54.777942 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7595 06:51:54.781643 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7596 06:51:54.782172 ==
7597 06:51:54.784852 Dram Type= 6, Freq= 0, CH_0, rank 1
7598 06:51:54.791530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 06:51:54.792067 ==
7600 06:51:54.794757 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7601 06:51:54.801252 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7602 06:51:54.804838 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7603 06:51:54.810955 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7604 06:51:54.819664 [CA 0] Center 44 (13~75) winsize 63
7605 06:51:54.822409 [CA 1] Center 43 (13~74) winsize 62
7606 06:51:54.826157 [CA 2] Center 39 (10~69) winsize 60
7607 06:51:54.828813 [CA 3] Center 38 (9~68) winsize 60
7608 06:51:54.832189 [CA 4] Center 37 (8~67) winsize 60
7609 06:51:54.835759 [CA 5] Center 36 (7~66) winsize 60
7610 06:51:54.836210
7611 06:51:54.838685 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7612 06:51:54.839116
7613 06:51:54.842224 [CATrainingPosCal] consider 2 rank data
7614 06:51:54.845937 u2DelayCellTimex100 = 258/100 ps
7615 06:51:54.852302 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7616 06:51:54.855876 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7617 06:51:54.858948 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7618 06:51:54.862077 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7619 06:51:54.865303 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7620 06:51:54.868617 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7621 06:51:54.869064
7622 06:51:54.872007 CA PerBit enable=1, Macro0, CA PI delay=36
7623 06:51:54.872455
7624 06:51:54.875298 [CBTSetCACLKResult] CA Dly = 36
7625 06:51:54.878472 CS Dly: 11 (0~43)
7626 06:51:54.882368 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7627 06:51:54.885114 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7628 06:51:54.885585
7629 06:51:54.888380 ----->DramcWriteLeveling(PI) begin...
7630 06:51:54.888831 ==
7631 06:51:54.891787 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 06:51:54.898553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 06:51:54.899003 ==
7634 06:51:54.901766 Write leveling (Byte 0): 36 => 36
7635 06:51:54.904852 Write leveling (Byte 1): 28 => 28
7636 06:51:54.905300 DramcWriteLeveling(PI) end<-----
7637 06:51:54.908273
7638 06:51:54.908713 ==
7639 06:51:54.911925 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 06:51:54.915087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 06:51:54.915537 ==
7642 06:51:54.918337 [Gating] SW mode calibration
7643 06:51:54.925004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7644 06:51:54.928229 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7645 06:51:54.935411 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 06:51:54.938156 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 06:51:54.941724 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 06:51:54.948701 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 06:51:54.951859 1 4 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7650 06:51:54.954862 1 4 20 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7651 06:51:54.961686 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7652 06:51:54.964737 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7653 06:51:54.968106 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7654 06:51:54.974836 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7655 06:51:54.978017 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7656 06:51:54.981583 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7657 06:51:54.988001 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7658 06:51:54.991237 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
7659 06:51:54.994668 1 5 24 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7660 06:51:55.001199 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 06:51:55.004778 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 06:51:55.007545 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 06:51:55.014484 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 06:51:55.018109 1 6 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7665 06:51:55.021246 1 6 16 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
7666 06:51:55.027891 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7667 06:51:55.030960 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7668 06:51:55.034398 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 06:51:55.040913 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 06:51:55.044643 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7671 06:51:55.047545 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 06:51:55.054385 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 06:51:55.057794 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7674 06:51:55.060769 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7675 06:51:55.067341 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7676 06:51:55.070440 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 06:51:55.073696 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 06:51:55.080677 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 06:51:55.083975 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 06:51:55.087339 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 06:51:55.094145 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 06:51:55.097312 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 06:51:55.100488 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 06:51:55.106668 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 06:51:55.110119 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 06:51:55.114065 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 06:51:55.120781 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 06:51:55.123569 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 06:51:55.126732 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7690 06:51:55.134033 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7691 06:51:55.134570 Total UI for P1: 0, mck2ui 16
7692 06:51:55.137042 best dqsien dly found for B0: ( 1, 9, 16)
7693 06:51:55.143609 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7694 06:51:55.146986 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7695 06:51:55.150262 Total UI for P1: 0, mck2ui 16
7696 06:51:55.153823 best dqsien dly found for B1: ( 1, 9, 22)
7697 06:51:55.157173 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7698 06:51:55.160355 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7699 06:51:55.160887
7700 06:51:55.163981 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7701 06:51:55.170423 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7702 06:51:55.170960 [Gating] SW calibration Done
7703 06:51:55.171303 ==
7704 06:51:55.173400 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 06:51:55.180392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 06:51:55.180966 ==
7707 06:51:55.181387 RX Vref Scan: 0
7708 06:51:55.181801
7709 06:51:55.183620 RX Vref 0 -> 0, step: 1
7710 06:51:55.184155
7711 06:51:55.186882 RX Delay 0 -> 252, step: 8
7712 06:51:55.189990 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7713 06:51:55.193649 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7714 06:51:55.197042 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7715 06:51:55.200448 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7716 06:51:55.206698 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7717 06:51:55.210049 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7718 06:51:55.213391 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7719 06:51:55.216932 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7720 06:51:55.220358 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7721 06:51:55.226917 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7722 06:51:55.230171 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7723 06:51:55.233642 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7724 06:51:55.236763 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7725 06:51:55.240037 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7726 06:51:55.247138 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7727 06:51:55.250117 iDelay=192, Bit 15, Center 127 (72 ~ 183) 112
7728 06:51:55.250653 ==
7729 06:51:55.253629 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 06:51:55.256640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 06:51:55.257179 ==
7732 06:51:55.260158 DQS Delay:
7733 06:51:55.260700 DQS0 = 0, DQS1 = 0
7734 06:51:55.261048 DQM Delay:
7735 06:51:55.263380 DQM0 = 129, DQM1 = 123
7736 06:51:55.263919 DQ Delay:
7737 06:51:55.266489 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7738 06:51:55.269888 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
7739 06:51:55.276753 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7740 06:51:55.279376 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7741 06:51:55.279808
7742 06:51:55.280143
7743 06:51:55.280456 ==
7744 06:51:55.283237 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 06:51:55.286376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 06:51:55.286814 ==
7747 06:51:55.287150
7748 06:51:55.287461
7749 06:51:55.289650 TX Vref Scan disable
7750 06:51:55.293319 == TX Byte 0 ==
7751 06:51:55.296634 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7752 06:51:55.299477 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7753 06:51:55.302853 == TX Byte 1 ==
7754 06:51:55.306223 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7755 06:51:55.309613 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7756 06:51:55.310042 ==
7757 06:51:55.313359 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 06:51:55.316326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 06:51:55.319788 ==
7760 06:51:55.331383
7761 06:51:55.334952 TX Vref early break, caculate TX vref
7762 06:51:55.338091 TX Vref=16, minBit 8, minWin=21, winSum=365
7763 06:51:55.341541 TX Vref=18, minBit 8, minWin=22, winSum=375
7764 06:51:55.345101 TX Vref=20, minBit 8, minWin=22, winSum=383
7765 06:51:55.348014 TX Vref=22, minBit 8, minWin=23, winSum=391
7766 06:51:55.351412 TX Vref=24, minBit 8, minWin=23, winSum=400
7767 06:51:55.358079 TX Vref=26, minBit 8, minWin=24, winSum=404
7768 06:51:55.361156 TX Vref=28, minBit 8, minWin=23, winSum=409
7769 06:51:55.364831 TX Vref=30, minBit 8, minWin=23, winSum=399
7770 06:51:55.368208 TX Vref=32, minBit 8, minWin=23, winSum=390
7771 06:51:55.371557 TX Vref=34, minBit 8, minWin=22, winSum=386
7772 06:51:55.377722 [TxChooseVref] Worse bit 8, Min win 24, Win sum 404, Final Vref 26
7773 06:51:55.378252
7774 06:51:55.381452 Final TX Range 0 Vref 26
7775 06:51:55.382027
7776 06:51:55.382366 ==
7777 06:51:55.384664 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 06:51:55.387995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 06:51:55.388531 ==
7780 06:51:55.388869
7781 06:51:55.389179
7782 06:51:55.390920 TX Vref Scan disable
7783 06:51:55.397763 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7784 06:51:55.398302 == TX Byte 0 ==
7785 06:51:55.400984 u2DelayCellOfst[0]=11 cells (3 PI)
7786 06:51:55.404397 u2DelayCellOfst[1]=15 cells (4 PI)
7787 06:51:55.407405 u2DelayCellOfst[2]=7 cells (2 PI)
7788 06:51:55.410757 u2DelayCellOfst[3]=7 cells (2 PI)
7789 06:51:55.414174 u2DelayCellOfst[4]=3 cells (1 PI)
7790 06:51:55.417823 u2DelayCellOfst[5]=0 cells (0 PI)
7791 06:51:55.420968 u2DelayCellOfst[6]=18 cells (5 PI)
7792 06:51:55.424402 u2DelayCellOfst[7]=15 cells (4 PI)
7793 06:51:55.427318 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7794 06:51:55.431072 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7795 06:51:55.434232 == TX Byte 1 ==
7796 06:51:55.437846 u2DelayCellOfst[8]=0 cells (0 PI)
7797 06:51:55.438371 u2DelayCellOfst[9]=0 cells (0 PI)
7798 06:51:55.440806 u2DelayCellOfst[10]=7 cells (2 PI)
7799 06:51:55.444256 u2DelayCellOfst[11]=7 cells (2 PI)
7800 06:51:55.447679 u2DelayCellOfst[12]=11 cells (3 PI)
7801 06:51:55.450769 u2DelayCellOfst[13]=11 cells (3 PI)
7802 06:51:55.454324 u2DelayCellOfst[14]=15 cells (4 PI)
7803 06:51:55.457346 u2DelayCellOfst[15]=11 cells (3 PI)
7804 06:51:55.460641 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7805 06:51:55.467092 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7806 06:51:55.467524 DramC Write-DBI on
7807 06:51:55.467888 ==
7808 06:51:55.470647 Dram Type= 6, Freq= 0, CH_0, rank 0
7809 06:51:55.477079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7810 06:51:55.477688 ==
7811 06:51:55.478152
7812 06:51:55.478649
7813 06:51:55.478982 TX Vref Scan disable
7814 06:51:55.480829 == TX Byte 0 ==
7815 06:51:55.483958 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7816 06:51:55.487741 == TX Byte 1 ==
7817 06:51:55.491142 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7818 06:51:55.494209 DramC Write-DBI off
7819 06:51:55.494638
7820 06:51:55.494975 [DATLAT]
7821 06:51:55.495293 Freq=1600, CH0 RK0
7822 06:51:55.495601
7823 06:51:55.497644 DATLAT Default: 0xf
7824 06:51:55.498171 0, 0xFFFF, sum = 0
7825 06:51:55.501047 1, 0xFFFF, sum = 0
7826 06:51:55.501641 2, 0xFFFF, sum = 0
7827 06:51:55.504223 3, 0xFFFF, sum = 0
7828 06:51:55.507615 4, 0xFFFF, sum = 0
7829 06:51:55.508261 5, 0xFFFF, sum = 0
7830 06:51:55.510526 6, 0xFFFF, sum = 0
7831 06:51:55.510960 7, 0xFFFF, sum = 0
7832 06:51:55.514067 8, 0xFFFF, sum = 0
7833 06:51:55.514538 9, 0xFFFF, sum = 0
7834 06:51:55.517602 10, 0xFFFF, sum = 0
7835 06:51:55.518173 11, 0xFFFF, sum = 0
7836 06:51:55.521332 12, 0xFFFF, sum = 0
7837 06:51:55.521944 13, 0xEFFF, sum = 0
7838 06:51:55.523933 14, 0x0, sum = 1
7839 06:51:55.524365 15, 0x0, sum = 2
7840 06:51:55.527229 16, 0x0, sum = 3
7841 06:51:55.527674 17, 0x0, sum = 4
7842 06:51:55.530562 best_step = 15
7843 06:51:55.531176
7844 06:51:55.531519 ==
7845 06:51:55.534294 Dram Type= 6, Freq= 0, CH_0, rank 0
7846 06:51:55.537462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7847 06:51:55.538041 ==
7848 06:51:55.540683 RX Vref Scan: 1
7849 06:51:55.541122
7850 06:51:55.541458 Set Vref Range= 24 -> 127
7851 06:51:55.541827
7852 06:51:55.544105 RX Vref 24 -> 127, step: 1
7853 06:51:55.544633
7854 06:51:55.547569 RX Delay 11 -> 252, step: 4
7855 06:51:55.548101
7856 06:51:55.550795 Set Vref, RX VrefLevel [Byte0]: 24
7857 06:51:55.553822 [Byte1]: 24
7858 06:51:55.554244
7859 06:51:55.557211 Set Vref, RX VrefLevel [Byte0]: 25
7860 06:51:55.560705 [Byte1]: 25
7861 06:51:55.564056
7862 06:51:55.564586 Set Vref, RX VrefLevel [Byte0]: 26
7863 06:51:55.566852 [Byte1]: 26
7864 06:51:55.571557
7865 06:51:55.572086 Set Vref, RX VrefLevel [Byte0]: 27
7866 06:51:55.574483 [Byte1]: 27
7867 06:51:55.578971
7868 06:51:55.579392 Set Vref, RX VrefLevel [Byte0]: 28
7869 06:51:55.581990 [Byte1]: 28
7870 06:51:55.586879
7871 06:51:55.587405 Set Vref, RX VrefLevel [Byte0]: 29
7872 06:51:55.589860 [Byte1]: 29
7873 06:51:55.594248
7874 06:51:55.594772 Set Vref, RX VrefLevel [Byte0]: 30
7875 06:51:55.597600 [Byte1]: 30
7876 06:51:55.601640
7877 06:51:55.602160 Set Vref, RX VrefLevel [Byte0]: 31
7878 06:51:55.604740 [Byte1]: 31
7879 06:51:55.609469
7880 06:51:55.610042 Set Vref, RX VrefLevel [Byte0]: 32
7881 06:51:55.612721 [Byte1]: 32
7882 06:51:55.617138
7883 06:51:55.617713 Set Vref, RX VrefLevel [Byte0]: 33
7884 06:51:55.620777 [Byte1]: 33
7885 06:51:55.624574
7886 06:51:55.625015 Set Vref, RX VrefLevel [Byte0]: 34
7887 06:51:55.627693 [Byte1]: 34
7888 06:51:55.632546
7889 06:51:55.633073 Set Vref, RX VrefLevel [Byte0]: 35
7890 06:51:55.635332 [Byte1]: 35
7891 06:51:55.640304
7892 06:51:55.640904 Set Vref, RX VrefLevel [Byte0]: 36
7893 06:51:55.643159 [Byte1]: 36
7894 06:51:55.647479
7895 06:51:55.648002 Set Vref, RX VrefLevel [Byte0]: 37
7896 06:51:55.651035 [Byte1]: 37
7897 06:51:55.655385
7898 06:51:55.655878 Set Vref, RX VrefLevel [Byte0]: 38
7899 06:51:55.658138 [Byte1]: 38
7900 06:51:55.662593
7901 06:51:55.663125 Set Vref, RX VrefLevel [Byte0]: 39
7902 06:51:55.666212 [Byte1]: 39
7903 06:51:55.670426
7904 06:51:55.670957 Set Vref, RX VrefLevel [Byte0]: 40
7905 06:51:55.673461 [Byte1]: 40
7906 06:51:55.677860
7907 06:51:55.678279 Set Vref, RX VrefLevel [Byte0]: 41
7908 06:51:55.680967 [Byte1]: 41
7909 06:51:55.685929
7910 06:51:55.686457 Set Vref, RX VrefLevel [Byte0]: 42
7911 06:51:55.688762 [Byte1]: 42
7912 06:51:55.693408
7913 06:51:55.693988 Set Vref, RX VrefLevel [Byte0]: 43
7914 06:51:55.696745 [Byte1]: 43
7915 06:51:55.700867
7916 06:51:55.701411 Set Vref, RX VrefLevel [Byte0]: 44
7917 06:51:55.704055 [Byte1]: 44
7918 06:51:55.708499
7919 06:51:55.709027 Set Vref, RX VrefLevel [Byte0]: 45
7920 06:51:55.711781 [Byte1]: 45
7921 06:51:55.716310
7922 06:51:55.716836 Set Vref, RX VrefLevel [Byte0]: 46
7923 06:51:55.719408 [Byte1]: 46
7924 06:51:55.723746
7925 06:51:55.724272 Set Vref, RX VrefLevel [Byte0]: 47
7926 06:51:55.726781 [Byte1]: 47
7927 06:51:55.731400
7928 06:51:55.731941 Set Vref, RX VrefLevel [Byte0]: 48
7929 06:51:55.734408 [Byte1]: 48
7930 06:51:55.738929
7931 06:51:55.739453 Set Vref, RX VrefLevel [Byte0]: 49
7932 06:51:55.742229 [Byte1]: 49
7933 06:51:55.746566
7934 06:51:55.747092 Set Vref, RX VrefLevel [Byte0]: 50
7935 06:51:55.749969 [Byte1]: 50
7936 06:51:55.754241
7937 06:51:55.754766 Set Vref, RX VrefLevel [Byte0]: 51
7938 06:51:55.757325 [Byte1]: 51
7939 06:51:55.761585
7940 06:51:55.762109 Set Vref, RX VrefLevel [Byte0]: 52
7941 06:51:55.764819 [Byte1]: 52
7942 06:51:55.769270
7943 06:51:55.769849 Set Vref, RX VrefLevel [Byte0]: 53
7944 06:51:55.772712 [Byte1]: 53
7945 06:51:55.776868
7946 06:51:55.777298 Set Vref, RX VrefLevel [Byte0]: 54
7947 06:51:55.779936 [Byte1]: 54
7948 06:51:55.784638
7949 06:51:55.785164 Set Vref, RX VrefLevel [Byte0]: 55
7950 06:51:55.788015 [Byte1]: 55
7951 06:51:55.792281
7952 06:51:55.792814 Set Vref, RX VrefLevel [Byte0]: 56
7953 06:51:55.795798 [Byte1]: 56
7954 06:51:55.799947
7955 06:51:55.800479 Set Vref, RX VrefLevel [Byte0]: 57
7956 06:51:55.802811 [Byte1]: 57
7957 06:51:55.807555
7958 06:51:55.808092 Set Vref, RX VrefLevel [Byte0]: 58
7959 06:51:55.810626 [Byte1]: 58
7960 06:51:55.814803
7961 06:51:55.815333 Set Vref, RX VrefLevel [Byte0]: 59
7962 06:51:55.818406 [Byte1]: 59
7963 06:51:55.822540
7964 06:51:55.823063 Set Vref, RX VrefLevel [Byte0]: 60
7965 06:51:55.825821 [Byte1]: 60
7966 06:51:55.830239
7967 06:51:55.830773 Set Vref, RX VrefLevel [Byte0]: 61
7968 06:51:55.833560 [Byte1]: 61
7969 06:51:55.837839
7970 06:51:55.838371 Set Vref, RX VrefLevel [Byte0]: 62
7971 06:51:55.841004 [Byte1]: 62
7972 06:51:55.845789
7973 06:51:55.846313 Set Vref, RX VrefLevel [Byte0]: 63
7974 06:51:55.848550 [Byte1]: 63
7975 06:51:55.852677
7976 06:51:55.853113 Set Vref, RX VrefLevel [Byte0]: 64
7977 06:51:55.856188 [Byte1]: 64
7978 06:51:55.860828
7979 06:51:55.861356 Set Vref, RX VrefLevel [Byte0]: 65
7980 06:51:55.863946 [Byte1]: 65
7981 06:51:55.868354
7982 06:51:55.868883 Set Vref, RX VrefLevel [Byte0]: 66
7983 06:51:55.871624 [Byte1]: 66
7984 06:51:55.876155
7985 06:51:55.876782 Set Vref, RX VrefLevel [Byte0]: 67
7986 06:51:55.878918 [Byte1]: 67
7987 06:51:55.883207
7988 06:51:55.883627 Set Vref, RX VrefLevel [Byte0]: 68
7989 06:51:55.886473 [Byte1]: 68
7990 06:51:55.891041
7991 06:51:55.891569 Set Vref, RX VrefLevel [Byte0]: 69
7992 06:51:55.894530 [Byte1]: 69
7993 06:51:55.898858
7994 06:51:55.899386 Set Vref, RX VrefLevel [Byte0]: 70
7995 06:51:55.901781 [Byte1]: 70
7996 06:51:55.906347
7997 06:51:55.906910 Set Vref, RX VrefLevel [Byte0]: 71
7998 06:51:55.909681 [Byte1]: 71
7999 06:51:55.913619
8000 06:51:55.914045 Set Vref, RX VrefLevel [Byte0]: 72
8001 06:51:55.916918 [Byte1]: 72
8002 06:51:55.921855
8003 06:51:55.922382 Set Vref, RX VrefLevel [Byte0]: 73
8004 06:51:55.924888 [Byte1]: 73
8005 06:51:55.929248
8006 06:51:55.929811 Set Vref, RX VrefLevel [Byte0]: 74
8007 06:51:55.932783 [Byte1]: 74
8008 06:51:55.936692
8009 06:51:55.937218 Set Vref, RX VrefLevel [Byte0]: 75
8010 06:51:55.940330 [Byte1]: 75
8011 06:51:55.944300
8012 06:51:55.944731 Set Vref, RX VrefLevel [Byte0]: 76
8013 06:51:55.947792 [Byte1]: 76
8014 06:51:55.951889
8015 06:51:55.952316 Set Vref, RX VrefLevel [Byte0]: 77
8016 06:51:55.955380 [Byte1]: 77
8017 06:51:55.959501
8018 06:51:55.959926 Final RX Vref Byte 0 = 64 to rank0
8019 06:51:55.962753 Final RX Vref Byte 1 = 61 to rank0
8020 06:51:55.965982 Final RX Vref Byte 0 = 64 to rank1
8021 06:51:55.969310 Final RX Vref Byte 1 = 61 to rank1==
8022 06:51:55.972448 Dram Type= 6, Freq= 0, CH_0, rank 0
8023 06:51:55.978845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 06:51:55.979275 ==
8025 06:51:55.979617 DQS Delay:
8026 06:51:55.982387 DQS0 = 0, DQS1 = 0
8027 06:51:55.982842 DQM Delay:
8028 06:51:55.985583 DQM0 = 126, DQM1 = 119
8029 06:51:55.986031 DQ Delay:
8030 06:51:55.988938 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8031 06:51:55.992098 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8032 06:51:55.995345 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8033 06:51:55.999083 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8034 06:51:55.999654
8035 06:51:56.000112
8036 06:51:56.000530
8037 06:51:56.002436 [DramC_TX_OE_Calibration] TA2
8038 06:51:56.005282 Original DQ_B0 (3 6) =30, OEN = 27
8039 06:51:56.008604 Original DQ_B1 (3 6) =30, OEN = 27
8040 06:51:56.012003 24, 0x0, End_B0=24 End_B1=24
8041 06:51:56.015355 25, 0x0, End_B0=25 End_B1=25
8042 06:51:56.015812 26, 0x0, End_B0=26 End_B1=26
8043 06:51:56.018775 27, 0x0, End_B0=27 End_B1=27
8044 06:51:56.021956 28, 0x0, End_B0=28 End_B1=28
8045 06:51:56.025316 29, 0x0, End_B0=29 End_B1=29
8046 06:51:56.026049 30, 0x0, End_B0=30 End_B1=30
8047 06:51:56.028263 31, 0x4141, End_B0=30 End_B1=30
8048 06:51:56.031571 Byte0 end_step=30 best_step=27
8049 06:51:56.035168 Byte1 end_step=30 best_step=27
8050 06:51:56.038713 Byte0 TX OE(2T, 0.5T) = (3, 3)
8051 06:51:56.041824 Byte1 TX OE(2T, 0.5T) = (3, 3)
8052 06:51:56.042256
8053 06:51:56.042596
8054 06:51:56.048319 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8055 06:51:56.051897 CH0 RK0: MR19=303, MR18=1212
8056 06:51:56.058323 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=23, DEC=15
8057 06:51:56.058749
8058 06:51:56.061344 ----->DramcWriteLeveling(PI) begin...
8059 06:51:56.061846 ==
8060 06:51:56.064895 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 06:51:56.068397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 06:51:56.068932 ==
8063 06:51:56.071732 Write leveling (Byte 0): 35 => 35
8064 06:51:56.075020 Write leveling (Byte 1): 29 => 29
8065 06:51:56.078109 DramcWriteLeveling(PI) end<-----
8066 06:51:56.078664
8067 06:51:56.079011 ==
8068 06:51:56.081276 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 06:51:56.084651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 06:51:56.088094 ==
8071 06:51:56.088522 [Gating] SW mode calibration
8072 06:51:56.095037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8073 06:51:56.101567 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8074 06:51:56.104702 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 06:51:56.111333 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 06:51:56.114536 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 06:51:56.117959 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8078 06:51:56.125110 1 4 16 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
8079 06:51:56.128052 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8080 06:51:56.131150 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 06:51:56.138217 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8082 06:51:56.141113 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8083 06:51:56.144286 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 06:51:56.151295 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8085 06:51:56.154593 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
8086 06:51:56.157469 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8087 06:51:56.164612 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 06:51:56.168051 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 06:51:56.171098 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 06:51:56.178047 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 06:51:56.180978 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 06:51:56.184386 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8093 06:51:56.190906 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8094 06:51:56.194392 1 6 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
8095 06:51:56.197711 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 06:51:56.204407 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 06:51:56.207852 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 06:51:56.210947 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 06:51:56.217646 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 06:51:56.220651 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8101 06:51:56.224417 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8102 06:51:56.227553 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8103 06:51:56.233937 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8104 06:51:56.237689 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 06:51:56.240864 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 06:51:56.247441 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 06:51:56.250386 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 06:51:56.254055 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 06:51:56.260702 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 06:51:56.263803 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 06:51:56.267378 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 06:51:56.274096 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 06:51:56.277602 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 06:51:56.280426 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 06:51:56.287262 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8116 06:51:56.290475 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8117 06:51:56.293672 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8118 06:51:56.297292 Total UI for P1: 0, mck2ui 16
8119 06:51:56.300295 best dqsien dly found for B0: ( 1, 9, 6)
8120 06:51:56.306877 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8121 06:51:56.310195 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8122 06:51:56.313256 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 06:51:56.316677 Total UI for P1: 0, mck2ui 16
8124 06:51:56.320218 best dqsien dly found for B1: ( 1, 9, 16)
8125 06:51:56.323545 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8126 06:51:56.326918 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8127 06:51:56.327345
8128 06:51:56.333517 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8129 06:51:56.336761 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8130 06:51:56.340205 [Gating] SW calibration Done
8131 06:51:56.340733 ==
8132 06:51:56.343394 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 06:51:56.346372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 06:51:56.346802 ==
8135 06:51:56.347140 RX Vref Scan: 0
8136 06:51:56.347455
8137 06:51:56.350099 RX Vref 0 -> 0, step: 1
8138 06:51:56.350631
8139 06:51:56.353536 RX Delay 0 -> 252, step: 8
8140 06:51:56.356814 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8141 06:51:56.359863 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8142 06:51:56.366805 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8143 06:51:56.369902 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8144 06:51:56.373147 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8145 06:51:56.376760 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8146 06:51:56.379481 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8147 06:51:56.386603 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8148 06:51:56.389458 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8149 06:51:56.393221 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8150 06:51:56.396643 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8151 06:51:56.400102 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8152 06:51:56.406239 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8153 06:51:56.410100 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8154 06:51:56.413084 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8155 06:51:56.416475 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8156 06:51:56.416994 ==
8157 06:51:56.419672 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 06:51:56.426318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 06:51:56.426844 ==
8160 06:51:56.427192 DQS Delay:
8161 06:51:56.427517 DQS0 = 0, DQS1 = 0
8162 06:51:56.429443 DQM Delay:
8163 06:51:56.429918 DQM0 = 128, DQM1 = 122
8164 06:51:56.433183 DQ Delay:
8165 06:51:56.436254 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8166 06:51:56.439818 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8167 06:51:56.443102 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8168 06:51:56.446222 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8169 06:51:56.446656
8170 06:51:56.446996
8171 06:51:56.447316 ==
8172 06:51:56.449740 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 06:51:56.452912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 06:51:56.456348 ==
8175 06:51:56.456876
8176 06:51:56.457223
8177 06:51:56.457590 TX Vref Scan disable
8178 06:51:56.459121 == TX Byte 0 ==
8179 06:51:56.462897 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8180 06:51:56.466096 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8181 06:51:56.469637 == TX Byte 1 ==
8182 06:51:56.473056 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8183 06:51:56.476030 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8184 06:51:56.476553 ==
8185 06:51:56.479476 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 06:51:56.486091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 06:51:56.486603 ==
8188 06:51:56.498337
8189 06:51:56.501662 TX Vref early break, caculate TX vref
8190 06:51:56.504683 TX Vref=16, minBit 8, minWin=22, winSum=371
8191 06:51:56.508015 TX Vref=18, minBit 8, minWin=22, winSum=376
8192 06:51:56.511503 TX Vref=20, minBit 8, minWin=23, winSum=386
8193 06:51:56.515148 TX Vref=22, minBit 9, minWin=23, winSum=395
8194 06:51:56.517979 TX Vref=24, minBit 0, minWin=24, winSum=402
8195 06:51:56.524807 TX Vref=26, minBit 8, minWin=24, winSum=411
8196 06:51:56.527812 TX Vref=28, minBit 0, minWin=25, winSum=412
8197 06:51:56.531286 TX Vref=30, minBit 13, minWin=24, winSum=412
8198 06:51:56.534623 TX Vref=32, minBit 3, minWin=24, winSum=398
8199 06:51:56.537948 TX Vref=34, minBit 8, minWin=23, winSum=390
8200 06:51:56.544998 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 28
8201 06:51:56.545570
8202 06:51:56.547723 Final TX Range 0 Vref 28
8203 06:51:56.548153
8204 06:51:56.548493 ==
8205 06:51:56.551728 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 06:51:56.554674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 06:51:56.555197 ==
8208 06:51:56.555547
8209 06:51:56.555866
8210 06:51:56.557949 TX Vref Scan disable
8211 06:51:56.564703 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8212 06:51:56.565227 == TX Byte 0 ==
8213 06:51:56.567985 u2DelayCellOfst[0]=11 cells (3 PI)
8214 06:51:56.571107 u2DelayCellOfst[1]=18 cells (5 PI)
8215 06:51:56.574215 u2DelayCellOfst[2]=11 cells (3 PI)
8216 06:51:56.577908 u2DelayCellOfst[3]=11 cells (3 PI)
8217 06:51:56.580997 u2DelayCellOfst[4]=7 cells (2 PI)
8218 06:51:56.584682 u2DelayCellOfst[5]=0 cells (0 PI)
8219 06:51:56.587816 u2DelayCellOfst[6]=18 cells (5 PI)
8220 06:51:56.591315 u2DelayCellOfst[7]=18 cells (5 PI)
8221 06:51:56.594307 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8222 06:51:56.597649 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8223 06:51:56.600947 == TX Byte 1 ==
8224 06:51:56.603996 u2DelayCellOfst[8]=0 cells (0 PI)
8225 06:51:56.604431 u2DelayCellOfst[9]=3 cells (1 PI)
8226 06:51:56.607692 u2DelayCellOfst[10]=7 cells (2 PI)
8227 06:51:56.610815 u2DelayCellOfst[11]=7 cells (2 PI)
8228 06:51:56.614169 u2DelayCellOfst[12]=15 cells (4 PI)
8229 06:51:56.617828 u2DelayCellOfst[13]=15 cells (4 PI)
8230 06:51:56.620800 u2DelayCellOfst[14]=18 cells (5 PI)
8231 06:51:56.624317 u2DelayCellOfst[15]=11 cells (3 PI)
8232 06:51:56.627706 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8233 06:51:56.634061 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8234 06:51:56.634517 DramC Write-DBI on
8235 06:51:56.634858 ==
8236 06:51:56.638064 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 06:51:56.643657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 06:51:56.644236 ==
8239 06:51:56.644586
8240 06:51:56.644907
8241 06:51:56.645212 TX Vref Scan disable
8242 06:51:56.648046 == TX Byte 0 ==
8243 06:51:56.651417 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8244 06:51:56.654341 == TX Byte 1 ==
8245 06:51:56.657900 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8246 06:51:56.661368 DramC Write-DBI off
8247 06:51:56.661945
8248 06:51:56.662288 [DATLAT]
8249 06:51:56.662606 Freq=1600, CH0 RK1
8250 06:51:56.662909
8251 06:51:56.664785 DATLAT Default: 0xf
8252 06:51:56.665312 0, 0xFFFF, sum = 0
8253 06:51:56.668295 1, 0xFFFF, sum = 0
8254 06:51:56.668834 2, 0xFFFF, sum = 0
8255 06:51:56.671383 3, 0xFFFF, sum = 0
8256 06:51:56.674597 4, 0xFFFF, sum = 0
8257 06:51:56.675125 5, 0xFFFF, sum = 0
8258 06:51:56.678111 6, 0xFFFF, sum = 0
8259 06:51:56.678649 7, 0xFFFF, sum = 0
8260 06:51:56.681153 8, 0xFFFF, sum = 0
8261 06:51:56.681821 9, 0xFFFF, sum = 0
8262 06:51:56.684392 10, 0xFFFF, sum = 0
8263 06:51:56.684824 11, 0xFFFF, sum = 0
8264 06:51:56.688037 12, 0xFFFF, sum = 0
8265 06:51:56.688574 13, 0xCFFF, sum = 0
8266 06:51:56.691222 14, 0x0, sum = 1
8267 06:51:56.691754 15, 0x0, sum = 2
8268 06:51:56.694374 16, 0x0, sum = 3
8269 06:51:56.694807 17, 0x0, sum = 4
8270 06:51:56.698111 best_step = 15
8271 06:51:56.698634
8272 06:51:56.698973 ==
8273 06:51:56.700914 Dram Type= 6, Freq= 0, CH_0, rank 1
8274 06:51:56.704696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 06:51:56.705232 ==
8276 06:51:56.708148 RX Vref Scan: 0
8277 06:51:56.708832
8278 06:51:56.709246 RX Vref 0 -> 0, step: 1
8279 06:51:56.709626
8280 06:51:56.710889 RX Delay 3 -> 252, step: 4
8281 06:51:56.714267 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
8282 06:51:56.721200 iDelay=195, Bit 1, Center 126 (71 ~ 182) 112
8283 06:51:56.724464 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8284 06:51:56.727565 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8285 06:51:56.731112 iDelay=195, Bit 4, Center 126 (75 ~ 178) 104
8286 06:51:56.734246 iDelay=195, Bit 5, Center 112 (59 ~ 166) 108
8287 06:51:56.741460 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8288 06:51:56.744270 iDelay=195, Bit 7, Center 136 (79 ~ 194) 116
8289 06:51:56.747514 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8290 06:51:56.750957 iDelay=195, Bit 9, Center 104 (47 ~ 162) 116
8291 06:51:56.754344 iDelay=195, Bit 10, Center 120 (63 ~ 178) 116
8292 06:51:56.760682 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8293 06:51:56.764498 iDelay=195, Bit 12, Center 124 (67 ~ 182) 116
8294 06:51:56.767574 iDelay=195, Bit 13, Center 122 (67 ~ 178) 112
8295 06:51:56.770877 iDelay=195, Bit 14, Center 128 (71 ~ 186) 116
8296 06:51:56.777224 iDelay=195, Bit 15, Center 124 (67 ~ 182) 116
8297 06:51:56.777806 ==
8298 06:51:56.780605 Dram Type= 6, Freq= 0, CH_0, rank 1
8299 06:51:56.783863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 06:51:56.784299 ==
8301 06:51:56.784637 DQS Delay:
8302 06:51:56.787402 DQS0 = 0, DQS1 = 0
8303 06:51:56.787929 DQM Delay:
8304 06:51:56.790878 DQM0 = 125, DQM1 = 118
8305 06:51:56.791407 DQ Delay:
8306 06:51:56.793654 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8307 06:51:56.797367 DQ4 =126, DQ5 =112, DQ6 =134, DQ7 =136
8308 06:51:56.800869 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8309 06:51:56.804002 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8310 06:51:56.804533
8311 06:51:56.804872
8312 06:51:56.805187
8313 06:51:56.807110 [DramC_TX_OE_Calibration] TA2
8314 06:51:56.810149 Original DQ_B0 (3 6) =30, OEN = 27
8315 06:51:56.813578 Original DQ_B1 (3 6) =30, OEN = 27
8316 06:51:56.816918 24, 0x0, End_B0=24 End_B1=24
8317 06:51:56.820679 25, 0x0, End_B0=25 End_B1=25
8318 06:51:56.823743 26, 0x0, End_B0=26 End_B1=26
8319 06:51:56.824280 27, 0x0, End_B0=27 End_B1=27
8320 06:51:56.826783 28, 0x0, End_B0=28 End_B1=28
8321 06:51:56.830368 29, 0x0, End_B0=29 End_B1=29
8322 06:51:56.833469 30, 0x0, End_B0=30 End_B1=30
8323 06:51:56.833953 31, 0x4545, End_B0=30 End_B1=30
8324 06:51:56.837094 Byte0 end_step=30 best_step=27
8325 06:51:56.840365 Byte1 end_step=30 best_step=27
8326 06:51:56.843887 Byte0 TX OE(2T, 0.5T) = (3, 3)
8327 06:51:56.846421 Byte1 TX OE(2T, 0.5T) = (3, 3)
8328 06:51:56.846856
8329 06:51:56.847198
8330 06:51:56.853634 [DQSOSCAuto] RK1, (LSB)MR18= 0x2412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8331 06:51:56.856578 CH0 RK1: MR19=303, MR18=2412
8332 06:51:56.863417 CH0_RK1: MR19=0x303, MR18=0x2412, DQSOSC=391, MR23=63, INC=24, DEC=16
8333 06:51:56.866419 [RxdqsGatingPostProcess] freq 1600
8334 06:51:56.873420 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8335 06:51:56.876499 best DQS0 dly(2T, 0.5T) = (1, 1)
8336 06:51:56.877027 best DQS1 dly(2T, 0.5T) = (1, 1)
8337 06:51:56.879798 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8338 06:51:56.883068 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8339 06:51:56.886245 best DQS0 dly(2T, 0.5T) = (1, 1)
8340 06:51:56.889925 best DQS1 dly(2T, 0.5T) = (1, 1)
8341 06:51:56.892828 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8342 06:51:56.896474 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8343 06:51:56.899952 Pre-setting of DQS Precalculation
8344 06:51:56.906205 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8345 06:51:56.906735 ==
8346 06:51:56.909874 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 06:51:56.912590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 06:51:56.913016 ==
8349 06:51:56.919582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8350 06:51:56.923138 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8351 06:51:56.926444 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8352 06:51:56.932337 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8353 06:51:56.941374 [CA 0] Center 41 (12~71) winsize 60
8354 06:51:56.944120 [CA 1] Center 42 (12~72) winsize 61
8355 06:51:56.947853 [CA 2] Center 37 (9~66) winsize 58
8356 06:51:56.951096 [CA 3] Center 36 (7~66) winsize 60
8357 06:51:56.954521 [CA 4] Center 37 (8~66) winsize 59
8358 06:51:56.957458 [CA 5] Center 36 (7~66) winsize 60
8359 06:51:56.957954
8360 06:51:56.960523 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8361 06:51:56.961074
8362 06:51:56.963738 [CATrainingPosCal] consider 1 rank data
8363 06:51:56.967305 u2DelayCellTimex100 = 258/100 ps
8364 06:51:56.970365 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8365 06:51:56.977323 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8366 06:51:56.980843 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8367 06:51:56.983913 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8368 06:51:56.987759 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8369 06:51:56.990640 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8370 06:51:56.991069
8371 06:51:56.993989 CA PerBit enable=1, Macro0, CA PI delay=36
8372 06:51:56.994427
8373 06:51:56.997502 [CBTSetCACLKResult] CA Dly = 36
8374 06:51:57.000785 CS Dly: 10 (0~41)
8375 06:51:57.003877 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8376 06:51:57.007067 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8377 06:51:57.007495 ==
8378 06:51:57.010652 Dram Type= 6, Freq= 0, CH_1, rank 1
8379 06:51:57.013857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 06:51:57.017238 ==
8381 06:51:57.020498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8382 06:51:57.024022 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8383 06:51:57.030533 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8384 06:51:57.037080 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8385 06:51:57.044701 [CA 0] Center 42 (13~72) winsize 60
8386 06:51:57.047279 [CA 1] Center 42 (12~72) winsize 61
8387 06:51:57.050678 [CA 2] Center 38 (9~67) winsize 59
8388 06:51:57.053885 [CA 3] Center 36 (7~66) winsize 60
8389 06:51:57.057419 [CA 4] Center 38 (8~68) winsize 61
8390 06:51:57.060908 [CA 5] Center 36 (6~66) winsize 61
8391 06:51:57.061430
8392 06:51:57.063991 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8393 06:51:57.064569
8394 06:51:57.067305 [CATrainingPosCal] consider 2 rank data
8395 06:51:57.070588 u2DelayCellTimex100 = 258/100 ps
8396 06:51:57.074478 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8397 06:51:57.080943 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8398 06:51:57.083831 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8399 06:51:57.087580 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8400 06:51:57.090720 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8401 06:51:57.094215 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8402 06:51:57.094774
8403 06:51:57.097396 CA PerBit enable=1, Macro0, CA PI delay=36
8404 06:51:57.097980
8405 06:51:57.100973 [CBTSetCACLKResult] CA Dly = 36
8406 06:51:57.104407 CS Dly: 11 (0~43)
8407 06:51:57.107290 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8408 06:51:57.110934 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8409 06:51:57.111458
8410 06:51:57.113984 ----->DramcWriteLeveling(PI) begin...
8411 06:51:57.114454 ==
8412 06:51:57.117386 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 06:51:57.120777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 06:51:57.123617 ==
8415 06:51:57.124046 Write leveling (Byte 0): 25 => 25
8416 06:51:57.126895 Write leveling (Byte 1): 29 => 29
8417 06:51:57.130480 DramcWriteLeveling(PI) end<-----
8418 06:51:57.130907
8419 06:51:57.131243 ==
8420 06:51:57.133781 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 06:51:57.140597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 06:51:57.141125 ==
8423 06:51:57.143563 [Gating] SW mode calibration
8424 06:51:57.150005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8425 06:51:57.153346 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8426 06:51:57.160044 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 06:51:57.163227 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 06:51:57.166550 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 06:51:57.173298 1 4 12 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
8430 06:51:57.176872 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8431 06:51:57.179933 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 06:51:57.186718 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 06:51:57.189618 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8434 06:51:57.193188 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8435 06:51:57.200069 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8436 06:51:57.203107 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8437 06:51:57.206272 1 5 12 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 1)
8438 06:51:57.213067 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8439 06:51:57.216096 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 06:51:57.219695 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 06:51:57.226079 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 06:51:57.229610 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8443 06:51:57.233019 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 06:51:57.239245 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 06:51:57.242681 1 6 12 | B1->B0 | 3131 2d2c | 1 1 | (0 0) (0 0)
8446 06:51:57.245828 1 6 16 | B1->B0 | 4545 4242 | 0 0 | (0 0) (0 0)
8447 06:51:57.252735 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 06:51:57.255986 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 06:51:57.259438 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 06:51:57.265964 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 06:51:57.269754 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 06:51:57.272787 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 06:51:57.276170 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 06:51:57.282417 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8455 06:51:57.285829 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8456 06:51:57.289055 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 06:51:57.295677 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 06:51:57.299442 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 06:51:57.302509 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 06:51:57.308895 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 06:51:57.312299 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 06:51:57.315417 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 06:51:57.322029 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 06:51:57.325518 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 06:51:57.328561 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 06:51:57.335131 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 06:51:57.338828 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 06:51:57.341907 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 06:51:57.348860 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 06:51:57.352170 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8471 06:51:57.355306 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 06:51:57.358729 Total UI for P1: 0, mck2ui 16
8473 06:51:57.362047 best dqsien dly found for B0: ( 1, 9, 16)
8474 06:51:57.365203 Total UI for P1: 0, mck2ui 16
8475 06:51:57.368707 best dqsien dly found for B1: ( 1, 9, 16)
8476 06:51:57.372388 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8477 06:51:57.375394 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8478 06:51:57.375917
8479 06:51:57.381926 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8480 06:51:57.384939 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8481 06:51:57.388394 [Gating] SW calibration Done
8482 06:51:57.388940 ==
8483 06:51:57.391429 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 06:51:57.394550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 06:51:57.394634 ==
8486 06:51:57.394716 RX Vref Scan: 0
8487 06:51:57.397868
8488 06:51:57.397962 RX Vref 0 -> 0, step: 1
8489 06:51:57.398031
8490 06:51:57.400923 RX Delay 0 -> 252, step: 8
8491 06:51:57.404465 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8492 06:51:57.407742 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8493 06:51:57.414364 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8494 06:51:57.417775 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8495 06:51:57.421193 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8496 06:51:57.424318 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8497 06:51:57.427545 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8498 06:51:57.434315 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8499 06:51:57.437877 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8500 06:51:57.441389 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8501 06:51:57.444731 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8502 06:51:57.447603 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8503 06:51:57.454289 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8504 06:51:57.457557 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8505 06:51:57.460730 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8506 06:51:57.464601 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8507 06:51:57.464893 ==
8508 06:51:57.467758 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 06:51:57.474142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 06:51:57.474581 ==
8511 06:51:57.474852 DQS Delay:
8512 06:51:57.477422 DQS0 = 0, DQS1 = 0
8513 06:51:57.477873 DQM Delay:
8514 06:51:57.480739 DQM0 = 132, DQM1 = 127
8515 06:51:57.481130 DQ Delay:
8516 06:51:57.484147 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8517 06:51:57.487261 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8518 06:51:57.491024 DQ8 =115, DQ9 =119, DQ10 =123, DQ11 =119
8519 06:51:57.493803 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8520 06:51:57.494358
8521 06:51:57.494831
8522 06:51:57.495198 ==
8523 06:51:57.497335 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 06:51:57.503961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 06:51:57.504414 ==
8526 06:51:57.504760
8527 06:51:57.505092
8528 06:51:57.505398 TX Vref Scan disable
8529 06:51:57.507741 == TX Byte 0 ==
8530 06:51:57.510555 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8531 06:51:57.517261 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8532 06:51:57.517840 == TX Byte 1 ==
8533 06:51:57.520726 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8534 06:51:57.527318 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8535 06:51:57.527963 ==
8536 06:51:57.530345 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 06:51:57.533764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 06:51:57.534252 ==
8539 06:51:57.546322
8540 06:51:57.549423 TX Vref early break, caculate TX vref
8541 06:51:57.552783 TX Vref=16, minBit 8, minWin=21, winSum=361
8542 06:51:57.556228 TX Vref=18, minBit 11, minWin=21, winSum=371
8543 06:51:57.559534 TX Vref=20, minBit 8, minWin=22, winSum=375
8544 06:51:57.562849 TX Vref=22, minBit 11, minWin=22, winSum=388
8545 06:51:57.566084 TX Vref=24, minBit 0, minWin=24, winSum=397
8546 06:51:57.572744 TX Vref=26, minBit 1, minWin=24, winSum=411
8547 06:51:57.576235 TX Vref=28, minBit 0, minWin=25, winSum=414
8548 06:51:57.579586 TX Vref=30, minBit 0, minWin=24, winSum=408
8549 06:51:57.582680 TX Vref=32, minBit 1, minWin=24, winSum=400
8550 06:51:57.586265 TX Vref=34, minBit 1, minWin=23, winSum=388
8551 06:51:57.593293 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
8552 06:51:57.593929
8553 06:51:57.596401 Final TX Range 0 Vref 28
8554 06:51:57.596940
8555 06:51:57.597282 ==
8556 06:51:57.599990 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 06:51:57.603167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 06:51:57.603910 ==
8559 06:51:57.604321
8560 06:51:57.604648
8561 06:51:57.606190 TX Vref Scan disable
8562 06:51:57.612838 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8563 06:51:57.613374 == TX Byte 0 ==
8564 06:51:57.616050 u2DelayCellOfst[0]=18 cells (5 PI)
8565 06:51:57.619185 u2DelayCellOfst[1]=15 cells (4 PI)
8566 06:51:57.622538 u2DelayCellOfst[2]=0 cells (0 PI)
8567 06:51:57.625753 u2DelayCellOfst[3]=7 cells (2 PI)
8568 06:51:57.629079 u2DelayCellOfst[4]=11 cells (3 PI)
8569 06:51:57.632288 u2DelayCellOfst[5]=22 cells (6 PI)
8570 06:51:57.635728 u2DelayCellOfst[6]=26 cells (7 PI)
8571 06:51:57.639138 u2DelayCellOfst[7]=7 cells (2 PI)
8572 06:51:57.642298 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8573 06:51:57.645791 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8574 06:51:57.649141 == TX Byte 1 ==
8575 06:51:57.649611 u2DelayCellOfst[8]=0 cells (0 PI)
8576 06:51:57.652501 u2DelayCellOfst[9]=11 cells (3 PI)
8577 06:51:57.655735 u2DelayCellOfst[10]=18 cells (5 PI)
8578 06:51:57.659212 u2DelayCellOfst[11]=11 cells (3 PI)
8579 06:51:57.662401 u2DelayCellOfst[12]=18 cells (5 PI)
8580 06:51:57.666051 u2DelayCellOfst[13]=22 cells (6 PI)
8581 06:51:57.669540 u2DelayCellOfst[14]=22 cells (6 PI)
8582 06:51:57.672599 u2DelayCellOfst[15]=22 cells (6 PI)
8583 06:51:57.676020 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8584 06:51:57.682334 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8585 06:51:57.682937 DramC Write-DBI on
8586 06:51:57.683290 ==
8587 06:51:57.685557 Dram Type= 6, Freq= 0, CH_1, rank 0
8588 06:51:57.692415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8589 06:51:57.692958 ==
8590 06:51:57.693303
8591 06:51:57.693689
8592 06:51:57.694006 TX Vref Scan disable
8593 06:51:57.696221 == TX Byte 0 ==
8594 06:51:57.699779 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8595 06:51:57.702599 == TX Byte 1 ==
8596 06:51:57.705977 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8597 06:51:57.709411 DramC Write-DBI off
8598 06:51:57.709889
8599 06:51:57.710229 [DATLAT]
8600 06:51:57.710546 Freq=1600, CH1 RK0
8601 06:51:57.710855
8602 06:51:57.712406 DATLAT Default: 0xf
8603 06:51:57.712834 0, 0xFFFF, sum = 0
8604 06:51:57.716104 1, 0xFFFF, sum = 0
8605 06:51:57.719286 2, 0xFFFF, sum = 0
8606 06:51:57.719721 3, 0xFFFF, sum = 0
8607 06:51:57.722446 4, 0xFFFF, sum = 0
8608 06:51:57.723275 5, 0xFFFF, sum = 0
8609 06:51:57.725602 6, 0xFFFF, sum = 0
8610 06:51:57.726346 7, 0xFFFF, sum = 0
8611 06:51:57.728899 8, 0xFFFF, sum = 0
8612 06:51:57.729657 9, 0xFFFF, sum = 0
8613 06:51:57.732147 10, 0xFFFF, sum = 0
8614 06:51:57.732584 11, 0xFFFF, sum = 0
8615 06:51:57.735848 12, 0xFFFF, sum = 0
8616 06:51:57.736287 13, 0x8FFF, sum = 0
8617 06:51:57.739023 14, 0x0, sum = 1
8618 06:51:57.739518 15, 0x0, sum = 2
8619 06:51:57.742569 16, 0x0, sum = 3
8620 06:51:57.743121 17, 0x0, sum = 4
8621 06:51:57.745460 best_step = 15
8622 06:51:57.745965
8623 06:51:57.746481 ==
8624 06:51:57.749168 Dram Type= 6, Freq= 0, CH_1, rank 0
8625 06:51:57.752410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8626 06:51:57.752958 ==
8627 06:51:57.755866 RX Vref Scan: 1
8628 06:51:57.756409
8629 06:51:57.756755 Set Vref Range= 24 -> 127
8630 06:51:57.757074
8631 06:51:57.758746 RX Vref 24 -> 127, step: 1
8632 06:51:57.759327
8633 06:51:57.762198 RX Delay 19 -> 252, step: 4
8634 06:51:57.762750
8635 06:51:57.765436 Set Vref, RX VrefLevel [Byte0]: 24
8636 06:51:57.768494 [Byte1]: 24
8637 06:51:57.769067
8638 06:51:57.772045 Set Vref, RX VrefLevel [Byte0]: 25
8639 06:51:57.775271 [Byte1]: 25
8640 06:51:57.778670
8641 06:51:57.779244 Set Vref, RX VrefLevel [Byte0]: 26
8642 06:51:57.782094 [Byte1]: 26
8643 06:51:57.786340
8644 06:51:57.786769 Set Vref, RX VrefLevel [Byte0]: 27
8645 06:51:57.789625 [Byte1]: 27
8646 06:51:57.793594
8647 06:51:57.794108 Set Vref, RX VrefLevel [Byte0]: 28
8648 06:51:57.796918 [Byte1]: 28
8649 06:51:57.801279
8650 06:51:57.801759 Set Vref, RX VrefLevel [Byte0]: 29
8651 06:51:57.804356 [Byte1]: 29
8652 06:51:57.808931
8653 06:51:57.809361 Set Vref, RX VrefLevel [Byte0]: 30
8654 06:51:57.812221 [Byte1]: 30
8655 06:51:57.816743
8656 06:51:57.817171 Set Vref, RX VrefLevel [Byte0]: 31
8657 06:51:57.819805 [Byte1]: 31
8658 06:51:57.824276
8659 06:51:57.824809 Set Vref, RX VrefLevel [Byte0]: 32
8660 06:51:57.827567 [Byte1]: 32
8661 06:51:57.831351
8662 06:51:57.831779 Set Vref, RX VrefLevel [Byte0]: 33
8663 06:51:57.834831 [Byte1]: 33
8664 06:51:57.839121
8665 06:51:57.839589 Set Vref, RX VrefLevel [Byte0]: 34
8666 06:51:57.842319 [Byte1]: 34
8667 06:51:57.846611
8668 06:51:57.847207 Set Vref, RX VrefLevel [Byte0]: 35
8669 06:51:57.849981 [Byte1]: 35
8670 06:51:57.854179
8671 06:51:57.854785 Set Vref, RX VrefLevel [Byte0]: 36
8672 06:51:57.857425 [Byte1]: 36
8673 06:51:57.861640
8674 06:51:57.862061 Set Vref, RX VrefLevel [Byte0]: 37
8675 06:51:57.865131 [Byte1]: 37
8676 06:51:57.869532
8677 06:51:57.869961 Set Vref, RX VrefLevel [Byte0]: 38
8678 06:51:57.873250 [Byte1]: 38
8679 06:51:57.877606
8680 06:51:57.878132 Set Vref, RX VrefLevel [Byte0]: 39
8681 06:51:57.880281 [Byte1]: 39
8682 06:51:57.885104
8683 06:51:57.885692 Set Vref, RX VrefLevel [Byte0]: 40
8684 06:51:57.888043 [Byte1]: 40
8685 06:51:57.892416
8686 06:51:57.892845 Set Vref, RX VrefLevel [Byte0]: 41
8687 06:51:57.895721 [Byte1]: 41
8688 06:51:57.899747
8689 06:51:57.900272 Set Vref, RX VrefLevel [Byte0]: 42
8690 06:51:57.903342 [Byte1]: 42
8691 06:51:57.907309
8692 06:51:57.907730 Set Vref, RX VrefLevel [Byte0]: 43
8693 06:51:57.910606 [Byte1]: 43
8694 06:51:57.914999
8695 06:51:57.915417 Set Vref, RX VrefLevel [Byte0]: 44
8696 06:51:57.918868 [Byte1]: 44
8697 06:51:57.923023
8698 06:51:57.923593 Set Vref, RX VrefLevel [Byte0]: 45
8699 06:51:57.926066 [Byte1]: 45
8700 06:51:57.929959
8701 06:51:57.930559 Set Vref, RX VrefLevel [Byte0]: 46
8702 06:51:57.933160 [Byte1]: 46
8703 06:51:57.937821
8704 06:51:57.938239 Set Vref, RX VrefLevel [Byte0]: 47
8705 06:51:57.941413 [Byte1]: 47
8706 06:51:57.945694
8707 06:51:57.946219 Set Vref, RX VrefLevel [Byte0]: 48
8708 06:51:57.948731 [Byte1]: 48
8709 06:51:57.952672
8710 06:51:57.956006 Set Vref, RX VrefLevel [Byte0]: 49
8711 06:51:57.956539 [Byte1]: 49
8712 06:51:57.960796
8713 06:51:57.961323 Set Vref, RX VrefLevel [Byte0]: 50
8714 06:51:57.963752 [Byte1]: 50
8715 06:51:57.967914
8716 06:51:57.968336 Set Vref, RX VrefLevel [Byte0]: 51
8717 06:51:57.971533 [Byte1]: 51
8718 06:51:57.975836
8719 06:51:57.976366 Set Vref, RX VrefLevel [Byte0]: 52
8720 06:51:57.979064 [Byte1]: 52
8721 06:51:57.983091
8722 06:51:57.983517 Set Vref, RX VrefLevel [Byte0]: 53
8723 06:51:57.986335 [Byte1]: 53
8724 06:51:57.990562
8725 06:51:57.990988 Set Vref, RX VrefLevel [Byte0]: 54
8726 06:51:57.993795 [Byte1]: 54
8727 06:51:57.998119
8728 06:51:57.998542 Set Vref, RX VrefLevel [Byte0]: 55
8729 06:51:58.001644 [Byte1]: 55
8730 06:51:58.005795
8731 06:51:58.006217 Set Vref, RX VrefLevel [Byte0]: 56
8732 06:51:58.009013 [Byte1]: 56
8733 06:51:58.013451
8734 06:51:58.014098 Set Vref, RX VrefLevel [Byte0]: 57
8735 06:51:58.016477 [Byte1]: 57
8736 06:51:58.021045
8737 06:51:58.021699 Set Vref, RX VrefLevel [Byte0]: 58
8738 06:51:58.024050 [Byte1]: 58
8739 06:51:58.028175
8740 06:51:58.028793 Set Vref, RX VrefLevel [Byte0]: 59
8741 06:51:58.031800 [Byte1]: 59
8742 06:51:58.036213
8743 06:51:58.036637 Set Vref, RX VrefLevel [Byte0]: 60
8744 06:51:58.039661 [Byte1]: 60
8745 06:51:58.044178
8746 06:51:58.044712 Set Vref, RX VrefLevel [Byte0]: 61
8747 06:51:58.047341 [Byte1]: 61
8748 06:51:58.051717
8749 06:51:58.052253 Set Vref, RX VrefLevel [Byte0]: 62
8750 06:51:58.054505 [Byte1]: 62
8751 06:51:58.058750
8752 06:51:58.059175 Set Vref, RX VrefLevel [Byte0]: 63
8753 06:51:58.061821 [Byte1]: 63
8754 06:51:58.066422
8755 06:51:58.066846 Set Vref, RX VrefLevel [Byte0]: 64
8756 06:51:58.069547 [Byte1]: 64
8757 06:51:58.073870
8758 06:51:58.074295 Set Vref, RX VrefLevel [Byte0]: 65
8759 06:51:58.077117 [Byte1]: 65
8760 06:51:58.081397
8761 06:51:58.082050 Set Vref, RX VrefLevel [Byte0]: 66
8762 06:51:58.084505 [Byte1]: 66
8763 06:51:58.088948
8764 06:51:58.089519 Set Vref, RX VrefLevel [Byte0]: 67
8765 06:51:58.092320 [Byte1]: 67
8766 06:51:58.096514
8767 06:51:58.096937 Set Vref, RX VrefLevel [Byte0]: 68
8768 06:51:58.100051 [Byte1]: 68
8769 06:51:58.104325
8770 06:51:58.104744 Set Vref, RX VrefLevel [Byte0]: 69
8771 06:51:58.107677 [Byte1]: 69
8772 06:51:58.112048
8773 06:51:58.112574 Set Vref, RX VrefLevel [Byte0]: 70
8774 06:51:58.115450 [Byte1]: 70
8775 06:51:58.119665
8776 06:51:58.120195 Set Vref, RX VrefLevel [Byte0]: 71
8777 06:51:58.122919 [Byte1]: 71
8778 06:51:58.127254
8779 06:51:58.127781 Final RX Vref Byte 0 = 61 to rank0
8780 06:51:58.130359 Final RX Vref Byte 1 = 55 to rank0
8781 06:51:58.133681 Final RX Vref Byte 0 = 61 to rank1
8782 06:51:58.136939 Final RX Vref Byte 1 = 55 to rank1==
8783 06:51:58.140350 Dram Type= 6, Freq= 0, CH_1, rank 0
8784 06:51:58.146812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 06:51:58.147331 ==
8786 06:51:58.147672 DQS Delay:
8787 06:51:58.150435 DQS0 = 0, DQS1 = 0
8788 06:51:58.150966 DQM Delay:
8789 06:51:58.151310 DQM0 = 131, DQM1 = 123
8790 06:51:58.153969 DQ Delay:
8791 06:51:58.156744 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =126
8792 06:51:58.160182 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =126
8793 06:51:58.163234 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8794 06:51:58.166772 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8795 06:51:58.167198
8796 06:51:58.167531
8797 06:51:58.167841
8798 06:51:58.170467 [DramC_TX_OE_Calibration] TA2
8799 06:51:58.173645 Original DQ_B0 (3 6) =30, OEN = 27
8800 06:51:58.176725 Original DQ_B1 (3 6) =30, OEN = 27
8801 06:51:58.180349 24, 0x0, End_B0=24 End_B1=24
8802 06:51:58.180905 25, 0x0, End_B0=25 End_B1=25
8803 06:51:58.183488 26, 0x0, End_B0=26 End_B1=26
8804 06:51:58.186476 27, 0x0, End_B0=27 End_B1=27
8805 06:51:58.190061 28, 0x0, End_B0=28 End_B1=28
8806 06:51:58.193306 29, 0x0, End_B0=29 End_B1=29
8807 06:51:58.193767 30, 0x0, End_B0=30 End_B1=30
8808 06:51:58.196601 31, 0x4141, End_B0=30 End_B1=30
8809 06:51:58.200377 Byte0 end_step=30 best_step=27
8810 06:51:58.203083 Byte1 end_step=30 best_step=27
8811 06:51:58.206533 Byte0 TX OE(2T, 0.5T) = (3, 3)
8812 06:51:58.209967 Byte1 TX OE(2T, 0.5T) = (3, 3)
8813 06:51:58.210394
8814 06:51:58.210728
8815 06:51:58.216816 [DQSOSCAuto] RK0, (LSB)MR18= 0x70c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8816 06:51:58.219957 CH1 RK0: MR19=303, MR18=70C
8817 06:51:58.226362 CH1_RK0: MR19=0x303, MR18=0x70C, DQSOSC=403, MR23=63, INC=22, DEC=15
8818 06:51:58.226902
8819 06:51:58.229576 ----->DramcWriteLeveling(PI) begin...
8820 06:51:58.230059 ==
8821 06:51:58.232897 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 06:51:58.236406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 06:51:58.236835 ==
8824 06:51:58.239740 Write leveling (Byte 0): 23 => 23
8825 06:51:58.242820 Write leveling (Byte 1): 29 => 29
8826 06:51:58.246223 DramcWriteLeveling(PI) end<-----
8827 06:51:58.246675
8828 06:51:58.247016 ==
8829 06:51:58.249411 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 06:51:58.252579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 06:51:58.253013 ==
8832 06:51:58.256061 [Gating] SW mode calibration
8833 06:51:58.262861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8834 06:51:58.269252 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8835 06:51:58.272759 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 06:51:58.275873 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8837 06:51:58.282525 1 4 8 | B1->B0 | 2323 3434 | 1 0 | (0 0) (0 0)
8838 06:51:58.285773 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 06:51:58.289259 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 06:51:58.295830 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 06:51:58.299155 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 06:51:58.302462 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8843 06:51:58.309221 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8844 06:51:58.312348 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8845 06:51:58.315324 1 5 8 | B1->B0 | 3434 2727 | 0 0 | (0 1) (1 0)
8846 06:51:58.321968 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8847 06:51:58.325380 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 06:51:58.328681 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 06:51:58.335668 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 06:51:58.338746 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 06:51:58.342224 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 06:51:58.348639 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 06:51:58.352018 1 6 8 | B1->B0 | 2424 4242 | 0 0 | (0 0) (0 0)
8854 06:51:58.355392 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8855 06:51:58.362151 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 06:51:58.365726 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 06:51:58.368981 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 06:51:58.375294 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 06:51:58.378538 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 06:51:58.382083 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 06:51:58.388652 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8862 06:51:58.391706 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8863 06:51:58.395142 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8864 06:51:58.401821 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 06:51:58.405447 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 06:51:58.408361 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 06:51:58.414958 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 06:51:58.418368 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 06:51:58.421825 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 06:51:58.428474 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 06:51:58.431626 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 06:51:58.435303 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 06:51:58.441747 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 06:51:58.444755 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 06:51:58.448239 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 06:51:58.454563 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 06:51:58.457894 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8878 06:51:58.461612 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8879 06:51:58.467806 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8880 06:51:58.468295 Total UI for P1: 0, mck2ui 16
8881 06:51:58.474463 best dqsien dly found for B0: ( 1, 9, 10)
8882 06:51:58.474896 Total UI for P1: 0, mck2ui 16
8883 06:51:58.477644 best dqsien dly found for B1: ( 1, 9, 12)
8884 06:51:58.484117 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8885 06:51:58.487441 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8886 06:51:58.487526
8887 06:51:58.490786 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8888 06:51:58.494061 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8889 06:51:58.497615 [Gating] SW calibration Done
8890 06:51:58.497699 ==
8891 06:51:58.500797 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 06:51:58.504223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 06:51:58.504308 ==
8894 06:51:58.507234 RX Vref Scan: 0
8895 06:51:58.507318
8896 06:51:58.507384 RX Vref 0 -> 0, step: 1
8897 06:51:58.507446
8898 06:51:58.510611 RX Delay 0 -> 252, step: 8
8899 06:51:58.513918 iDelay=200, Bit 0, Center 135 (72 ~ 199) 128
8900 06:51:58.520507 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8901 06:51:58.523844 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8902 06:51:58.527263 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8903 06:51:58.530624 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8904 06:51:58.534060 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8905 06:51:58.540553 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8906 06:51:58.543591 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8907 06:51:58.547141 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8908 06:51:58.550386 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8909 06:51:58.553469 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8910 06:51:58.560529 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8911 06:51:58.563854 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8912 06:51:58.567376 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8913 06:51:58.570692 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8914 06:51:58.574099 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8915 06:51:58.577239 ==
8916 06:51:58.580626 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 06:51:58.583744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 06:51:58.583966 ==
8919 06:51:58.584120 DQS Delay:
8920 06:51:58.587260 DQS0 = 0, DQS1 = 0
8921 06:51:58.587552 DQM Delay:
8922 06:51:58.590218 DQM0 = 129, DQM1 = 127
8923 06:51:58.590426 DQ Delay:
8924 06:51:58.593595 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =127
8925 06:51:58.597327 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8926 06:51:58.600848 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =123
8927 06:51:58.604088 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8928 06:51:58.604589
8929 06:51:58.604915
8930 06:51:58.605205 ==
8931 06:51:58.606977 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 06:51:58.613894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 06:51:58.614331 ==
8934 06:51:58.614675
8935 06:51:58.614991
8936 06:51:58.615295 TX Vref Scan disable
8937 06:51:58.617288 == TX Byte 0 ==
8938 06:51:58.620681 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8939 06:51:58.627484 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8940 06:51:58.627983 == TX Byte 1 ==
8941 06:51:58.630814 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8942 06:51:58.637167 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8943 06:51:58.637631 ==
8944 06:51:58.640626 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 06:51:58.644191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 06:51:58.644736 ==
8947 06:51:58.657962
8948 06:51:58.661244 TX Vref early break, caculate TX vref
8949 06:51:58.664366 TX Vref=16, minBit 0, minWin=22, winSum=375
8950 06:51:58.667857 TX Vref=18, minBit 0, minWin=23, winSum=383
8951 06:51:58.671150 TX Vref=20, minBit 8, minWin=23, winSum=393
8952 06:51:58.674300 TX Vref=22, minBit 0, minWin=24, winSum=399
8953 06:51:58.678001 TX Vref=24, minBit 0, minWin=24, winSum=404
8954 06:51:58.684530 TX Vref=26, minBit 0, minWin=24, winSum=411
8955 06:51:58.687823 TX Vref=28, minBit 0, minWin=24, winSum=411
8956 06:51:58.690788 TX Vref=30, minBit 0, minWin=25, winSum=415
8957 06:51:58.694233 TX Vref=32, minBit 1, minWin=23, winSum=401
8958 06:51:58.697668 TX Vref=34, minBit 1, minWin=23, winSum=395
8959 06:51:58.700836 TX Vref=36, minBit 0, minWin=22, winSum=386
8960 06:51:58.707712 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 30
8961 06:51:58.708146
8962 06:51:58.710927 Final TX Range 0 Vref 30
8963 06:51:58.711360
8964 06:51:58.711702 ==
8965 06:51:58.714415 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 06:51:58.717444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 06:51:58.717933 ==
8968 06:51:58.718348
8969 06:51:58.718721
8970 06:51:58.720884 TX Vref Scan disable
8971 06:51:58.727988 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8972 06:51:58.728518 == TX Byte 0 ==
8973 06:51:58.730940 u2DelayCellOfst[0]=18 cells (5 PI)
8974 06:51:58.734288 u2DelayCellOfst[1]=15 cells (4 PI)
8975 06:51:58.737788 u2DelayCellOfst[2]=0 cells (0 PI)
8976 06:51:58.741095 u2DelayCellOfst[3]=7 cells (2 PI)
8977 06:51:58.744015 u2DelayCellOfst[4]=7 cells (2 PI)
8978 06:51:58.747579 u2DelayCellOfst[5]=22 cells (6 PI)
8979 06:51:58.750673 u2DelayCellOfst[6]=22 cells (6 PI)
8980 06:51:58.754083 u2DelayCellOfst[7]=7 cells (2 PI)
8981 06:51:58.757419 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8982 06:51:58.760696 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8983 06:51:58.763755 == TX Byte 1 ==
8984 06:51:58.767273 u2DelayCellOfst[8]=0 cells (0 PI)
8985 06:51:58.767711 u2DelayCellOfst[9]=3 cells (1 PI)
8986 06:51:58.770489 u2DelayCellOfst[10]=11 cells (3 PI)
8987 06:51:58.773718 u2DelayCellOfst[11]=3 cells (1 PI)
8988 06:51:58.777280 u2DelayCellOfst[12]=15 cells (4 PI)
8989 06:51:58.780514 u2DelayCellOfst[13]=15 cells (4 PI)
8990 06:51:58.784019 u2DelayCellOfst[14]=18 cells (5 PI)
8991 06:51:58.787149 u2DelayCellOfst[15]=15 cells (4 PI)
8992 06:51:58.793833 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8993 06:51:58.796992 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8994 06:51:58.797425 DramC Write-DBI on
8995 06:51:58.797820 ==
8996 06:51:58.800327 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 06:51:58.807390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 06:51:58.807912 ==
8999 06:51:58.808258
9000 06:51:58.808574
9001 06:51:58.808879 TX Vref Scan disable
9002 06:51:58.811289 == TX Byte 0 ==
9003 06:51:58.814627 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9004 06:51:58.818123 == TX Byte 1 ==
9005 06:51:58.821438 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
9006 06:51:58.824644 DramC Write-DBI off
9007 06:51:58.825170
9008 06:51:58.825565 [DATLAT]
9009 06:51:58.825901 Freq=1600, CH1 RK1
9010 06:51:58.826210
9011 06:51:58.828198 DATLAT Default: 0xf
9012 06:51:58.828727 0, 0xFFFF, sum = 0
9013 06:51:58.831124 1, 0xFFFF, sum = 0
9014 06:51:58.834456 2, 0xFFFF, sum = 0
9015 06:51:58.834995 3, 0xFFFF, sum = 0
9016 06:51:58.837639 4, 0xFFFF, sum = 0
9017 06:51:58.838126 5, 0xFFFF, sum = 0
9018 06:51:58.840909 6, 0xFFFF, sum = 0
9019 06:51:58.841406 7, 0xFFFF, sum = 0
9020 06:51:58.844195 8, 0xFFFF, sum = 0
9021 06:51:58.844671 9, 0xFFFF, sum = 0
9022 06:51:58.847646 10, 0xFFFF, sum = 0
9023 06:51:58.848207 11, 0xFFFF, sum = 0
9024 06:51:58.851472 12, 0xFFFF, sum = 0
9025 06:51:58.852017 13, 0x8FFF, sum = 0
9026 06:51:58.854378 14, 0x0, sum = 1
9027 06:51:58.854930 15, 0x0, sum = 2
9028 06:51:58.857563 16, 0x0, sum = 3
9029 06:51:58.858003 17, 0x0, sum = 4
9030 06:51:58.860832 best_step = 15
9031 06:51:58.861292
9032 06:51:58.861822 ==
9033 06:51:58.863938 Dram Type= 6, Freq= 0, CH_1, rank 1
9034 06:51:58.867310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9035 06:51:58.867745 ==
9036 06:51:58.870689 RX Vref Scan: 0
9037 06:51:58.871121
9038 06:51:58.871465 RX Vref 0 -> 0, step: 1
9039 06:51:58.871785
9040 06:51:58.874383 RX Delay 3 -> 252, step: 4
9041 06:51:58.878004 iDelay=195, Bit 0, Center 136 (83 ~ 190) 108
9042 06:51:58.884614 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9043 06:51:58.887433 iDelay=195, Bit 2, Center 116 (59 ~ 174) 116
9044 06:51:58.890639 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9045 06:51:58.894107 iDelay=195, Bit 4, Center 122 (67 ~ 178) 112
9046 06:51:58.897594 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9047 06:51:58.903919 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9048 06:51:58.907247 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9049 06:51:58.910688 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9050 06:51:58.914022 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9051 06:51:58.917640 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9052 06:51:58.923868 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9053 06:51:58.926972 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9054 06:51:58.930555 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9055 06:51:58.933590 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9056 06:51:58.937110 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9057 06:51:58.940472 ==
9058 06:51:58.943898 Dram Type= 6, Freq= 0, CH_1, rank 1
9059 06:51:58.947243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9060 06:51:58.947683 ==
9061 06:51:58.948156 DQS Delay:
9062 06:51:58.950525 DQS0 = 0, DQS1 = 0
9063 06:51:58.950961 DQM Delay:
9064 06:51:58.953780 DQM0 = 128, DQM1 = 125
9065 06:51:58.954281 DQ Delay:
9066 06:51:58.957028 DQ0 =136, DQ1 =126, DQ2 =116, DQ3 =124
9067 06:51:58.960412 DQ4 =122, DQ5 =138, DQ6 =140, DQ7 =124
9068 06:51:58.963583 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9069 06:51:58.966977 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =134
9070 06:51:58.967401
9071 06:51:58.967733
9072 06:51:58.968046
9073 06:51:58.970229 [DramC_TX_OE_Calibration] TA2
9074 06:51:58.973736 Original DQ_B0 (3 6) =30, OEN = 27
9075 06:51:58.977263 Original DQ_B1 (3 6) =30, OEN = 27
9076 06:51:58.980023 24, 0x0, End_B0=24 End_B1=24
9077 06:51:58.983699 25, 0x0, End_B0=25 End_B1=25
9078 06:51:58.984150 26, 0x0, End_B0=26 End_B1=26
9079 06:51:58.986742 27, 0x0, End_B0=27 End_B1=27
9080 06:51:58.990247 28, 0x0, End_B0=28 End_B1=28
9081 06:51:58.993636 29, 0x0, End_B0=29 End_B1=29
9082 06:51:58.997098 30, 0x0, End_B0=30 End_B1=30
9083 06:51:58.997593 31, 0x4545, End_B0=30 End_B1=30
9084 06:51:59.000474 Byte0 end_step=30 best_step=27
9085 06:51:59.004032 Byte1 end_step=30 best_step=27
9086 06:51:59.007295 Byte0 TX OE(2T, 0.5T) = (3, 3)
9087 06:51:59.010428 Byte1 TX OE(2T, 0.5T) = (3, 3)
9088 06:51:59.010876
9089 06:51:59.011325
9090 06:51:59.017174 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9091 06:51:59.020935 CH1 RK1: MR19=303, MR18=F1C
9092 06:51:59.027496 CH1_RK1: MR19=0x303, MR18=0xF1C, DQSOSC=395, MR23=63, INC=23, DEC=15
9093 06:51:59.030417 [RxdqsGatingPostProcess] freq 1600
9094 06:51:59.033649 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9095 06:51:59.037179 best DQS0 dly(2T, 0.5T) = (1, 1)
9096 06:51:59.040038 best DQS1 dly(2T, 0.5T) = (1, 1)
9097 06:51:59.043962 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9098 06:51:59.047421 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9099 06:51:59.050187 best DQS0 dly(2T, 0.5T) = (1, 1)
9100 06:51:59.053739 best DQS1 dly(2T, 0.5T) = (1, 1)
9101 06:51:59.057184 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9102 06:51:59.059911 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9103 06:51:59.063286 Pre-setting of DQS Precalculation
9104 06:51:59.066450 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9105 06:51:59.073094 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9106 06:51:59.083157 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 06:51:59.083593
9108 06:51:59.083934
9109 06:51:59.086328 [Calibration Summary] 3200 Mbps
9110 06:51:59.086762 CH 0, Rank 0
9111 06:51:59.089939 SW Impedance : PASS
9112 06:51:59.090372 DUTY Scan : NO K
9113 06:51:59.093581 ZQ Calibration : PASS
9114 06:51:59.096770 Jitter Meter : NO K
9115 06:51:59.097201 CBT Training : PASS
9116 06:51:59.099971 Write leveling : PASS
9117 06:51:59.100400 RX DQS gating : PASS
9118 06:51:59.103563 RX DQ/DQS(RDDQC) : PASS
9119 06:51:59.106944 TX DQ/DQS : PASS
9120 06:51:59.107379 RX DATLAT : PASS
9121 06:51:59.110051 RX DQ/DQS(Engine): PASS
9122 06:51:59.113454 TX OE : PASS
9123 06:51:59.113917 All Pass.
9124 06:51:59.114257
9125 06:51:59.114571 CH 0, Rank 1
9126 06:51:59.116561 SW Impedance : PASS
9127 06:51:59.119916 DUTY Scan : NO K
9128 06:51:59.120430 ZQ Calibration : PASS
9129 06:51:59.122973 Jitter Meter : NO K
9130 06:51:59.126494 CBT Training : PASS
9131 06:51:59.126927 Write leveling : PASS
9132 06:51:59.129949 RX DQS gating : PASS
9133 06:51:59.133073 RX DQ/DQS(RDDQC) : PASS
9134 06:51:59.133539 TX DQ/DQS : PASS
9135 06:51:59.136453 RX DATLAT : PASS
9136 06:51:59.139503 RX DQ/DQS(Engine): PASS
9137 06:51:59.139933 TX OE : PASS
9138 06:51:59.140276 All Pass.
9139 06:51:59.143130
9140 06:51:59.143556 CH 1, Rank 0
9141 06:51:59.146797 SW Impedance : PASS
9142 06:51:59.147347 DUTY Scan : NO K
9143 06:51:59.149566 ZQ Calibration : PASS
9144 06:51:59.153283 Jitter Meter : NO K
9145 06:51:59.153864 CBT Training : PASS
9146 06:51:59.156077 Write leveling : PASS
9147 06:51:59.159482 RX DQS gating : PASS
9148 06:51:59.159961 RX DQ/DQS(RDDQC) : PASS
9149 06:51:59.162615 TX DQ/DQS : PASS
9150 06:51:59.163048 RX DATLAT : PASS
9151 06:51:59.166211 RX DQ/DQS(Engine): PASS
9152 06:51:59.169501 TX OE : PASS
9153 06:51:59.169937 All Pass.
9154 06:51:59.170276
9155 06:51:59.170590 CH 1, Rank 1
9156 06:51:59.172778 SW Impedance : PASS
9157 06:51:59.175917 DUTY Scan : NO K
9158 06:51:59.176344 ZQ Calibration : PASS
9159 06:51:59.179471 Jitter Meter : NO K
9160 06:51:59.182930 CBT Training : PASS
9161 06:51:59.183360 Write leveling : PASS
9162 06:51:59.186132 RX DQS gating : PASS
9163 06:51:59.189262 RX DQ/DQS(RDDQC) : PASS
9164 06:51:59.189724 TX DQ/DQS : PASS
9165 06:51:59.192473 RX DATLAT : PASS
9166 06:51:59.196063 RX DQ/DQS(Engine): PASS
9167 06:51:59.196498 TX OE : PASS
9168 06:51:59.199467 All Pass.
9169 06:51:59.199994
9170 06:51:59.200403 DramC Write-DBI on
9171 06:51:59.202585 PER_BANK_REFRESH: Hybrid Mode
9172 06:51:59.203087 TX_TRACKING: ON
9173 06:51:59.212420 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9174 06:51:59.219012 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9175 06:51:59.229103 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9176 06:51:59.232502 [FAST_K] Save calibration result to emmc
9177 06:51:59.236058 sync common calibartion params.
9178 06:51:59.236504 sync cbt_mode0:1, 1:1
9179 06:51:59.239174 dram_init: ddr_geometry: 2
9180 06:51:59.242246 dram_init: ddr_geometry: 2
9181 06:51:59.242689 dram_init: ddr_geometry: 2
9182 06:51:59.245998 0:dram_rank_size:100000000
9183 06:51:59.249573 1:dram_rank_size:100000000
9184 06:51:59.256037 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9185 06:51:59.256591 DFS_SHUFFLE_HW_MODE: ON
9186 06:51:59.259082 dramc_set_vcore_voltage set vcore to 725000
9187 06:51:59.262658 Read voltage for 1600, 0
9188 06:51:59.263211 Vio18 = 0
9189 06:51:59.266111 Vcore = 725000
9190 06:51:59.266662 Vdram = 0
9191 06:51:59.267122 Vddq = 0
9192 06:51:59.269389 Vmddr = 0
9193 06:51:59.269987 switch to 3200 Mbps bootup
9194 06:51:59.272323 [DramcRunTimeConfig]
9195 06:51:59.272879 PHYPLL
9196 06:51:59.276120 DPM_CONTROL_AFTERK: ON
9197 06:51:59.276681 PER_BANK_REFRESH: ON
9198 06:51:59.278810 REFRESH_OVERHEAD_REDUCTION: ON
9199 06:51:59.282126 CMD_PICG_NEW_MODE: OFF
9200 06:51:59.282571 XRTWTW_NEW_MODE: ON
9201 06:51:59.285656 XRTRTR_NEW_MODE: ON
9202 06:51:59.286213 TX_TRACKING: ON
9203 06:51:59.289091 RDSEL_TRACKING: OFF
9204 06:51:59.292137 DQS Precalculation for DVFS: ON
9205 06:51:59.292570 RX_TRACKING: OFF
9206 06:51:59.295287 HW_GATING DBG: ON
9207 06:51:59.295736 ZQCS_ENABLE_LP4: ON
9208 06:51:59.299121 RX_PICG_NEW_MODE: ON
9209 06:51:59.299566 TX_PICG_NEW_MODE: ON
9210 06:51:59.302171 ENABLE_RX_DCM_DPHY: ON
9211 06:51:59.305565 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9212 06:51:59.308654 DUMMY_READ_FOR_TRACKING: OFF
9213 06:51:59.309098 !!! SPM_CONTROL_AFTERK: OFF
9214 06:51:59.311953 !!! SPM could not control APHY
9215 06:51:59.315374 IMPEDANCE_TRACKING: ON
9216 06:51:59.315819 TEMP_SENSOR: ON
9217 06:51:59.318768 HW_SAVE_FOR_SR: OFF
9218 06:51:59.322034 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9219 06:51:59.325732 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9220 06:51:59.326286 Read ODT Tracking: ON
9221 06:51:59.328764 Refresh Rate DeBounce: ON
9222 06:51:59.331847 DFS_NO_QUEUE_FLUSH: ON
9223 06:51:59.335359 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9224 06:51:59.335807 ENABLE_DFS_RUNTIME_MRW: OFF
9225 06:51:59.338440 DDR_RESERVE_NEW_MODE: ON
9226 06:51:59.341773 MR_CBT_SWITCH_FREQ: ON
9227 06:51:59.344962 =========================
9228 06:51:59.362173 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9229 06:51:59.365702 dram_init: ddr_geometry: 2
9230 06:51:59.383840 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9231 06:51:59.387274 dram_init: dram init end (result: 0)
9232 06:51:59.394046 DRAM-K: Full calibration passed in 24577 msecs
9233 06:51:59.397190 MRC: failed to locate region type 0.
9234 06:51:59.397894 DRAM rank0 size:0x100000000,
9235 06:51:59.400445 DRAM rank1 size=0x100000000
9236 06:51:59.410579 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9237 06:51:59.417302 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9238 06:51:59.423614 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9239 06:51:59.430239 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9240 06:51:59.433390 DRAM rank0 size:0x100000000,
9241 06:51:59.436854 DRAM rank1 size=0x100000000
9242 06:51:59.437284 CBMEM:
9243 06:51:59.440293 IMD: root @ 0xfffff000 254 entries.
9244 06:51:59.443702 IMD: root @ 0xffffec00 62 entries.
9245 06:51:59.446653 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9246 06:51:59.450081 WARNING: RO_VPD is uninitialized or empty.
9247 06:51:59.456882 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9248 06:51:59.464356 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9249 06:51:59.476798 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9250 06:51:59.488242 BS: romstage times (exec / console): total (unknown) / 24042 ms
9251 06:51:59.488805
9252 06:51:59.489265
9253 06:51:59.498147 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9254 06:51:59.501604 ARM64: Exception handlers installed.
9255 06:51:59.504934 ARM64: Testing exception
9256 06:51:59.507813 ARM64: Done test exception
9257 06:51:59.508266 Enumerating buses...
9258 06:51:59.511092 Show all devs... Before device enumeration.
9259 06:51:59.514781 Root Device: enabled 1
9260 06:51:59.518066 CPU_CLUSTER: 0: enabled 1
9261 06:51:59.518509 CPU: 00: enabled 1
9262 06:51:59.521210 Compare with tree...
9263 06:51:59.521698 Root Device: enabled 1
9264 06:51:59.524455 CPU_CLUSTER: 0: enabled 1
9265 06:51:59.528053 CPU: 00: enabled 1
9266 06:51:59.528500 Root Device scanning...
9267 06:51:59.531373 scan_static_bus for Root Device
9268 06:51:59.534507 CPU_CLUSTER: 0 enabled
9269 06:51:59.537916 scan_static_bus for Root Device done
9270 06:51:59.541084 scan_bus: bus Root Device finished in 8 msecs
9271 06:51:59.541570 done
9272 06:51:59.548346 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9273 06:51:59.551353 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9274 06:51:59.558084 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9275 06:51:59.561165 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9276 06:51:59.564154 Allocating resources...
9277 06:51:59.567936 Reading resources...
9278 06:51:59.570912 Root Device read_resources bus 0 link: 0
9279 06:51:59.571345 DRAM rank0 size:0x100000000,
9280 06:51:59.574264 DRAM rank1 size=0x100000000
9281 06:51:59.577363 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9282 06:51:59.580827 CPU: 00 missing read_resources
9283 06:51:59.584204 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9284 06:51:59.590811 Root Device read_resources bus 0 link: 0 done
9285 06:51:59.591246 Done reading resources.
9286 06:51:59.597319 Show resources in subtree (Root Device)...After reading.
9287 06:51:59.600595 Root Device child on link 0 CPU_CLUSTER: 0
9288 06:51:59.603987 CPU_CLUSTER: 0 child on link 0 CPU: 00
9289 06:51:59.613879 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9290 06:51:59.614334 CPU: 00
9291 06:51:59.617253 Root Device assign_resources, bus 0 link: 0
9292 06:51:59.620803 CPU_CLUSTER: 0 missing set_resources
9293 06:51:59.627212 Root Device assign_resources, bus 0 link: 0 done
9294 06:51:59.627724 Done setting resources.
9295 06:51:59.633812 Show resources in subtree (Root Device)...After assigning values.
9296 06:51:59.637034 Root Device child on link 0 CPU_CLUSTER: 0
9297 06:51:59.640536 CPU_CLUSTER: 0 child on link 0 CPU: 00
9298 06:51:59.650523 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9299 06:51:59.650977 CPU: 00
9300 06:51:59.653744 Done allocating resources.
9301 06:51:59.656826 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9302 06:51:59.660341 Enabling resources...
9303 06:51:59.660786 done.
9304 06:51:59.666960 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9305 06:51:59.667410 Initializing devices...
9306 06:51:59.670065 Root Device init
9307 06:51:59.670508 init hardware done!
9308 06:51:59.673609 0x00000018: ctrlr->caps
9309 06:51:59.677068 52.000 MHz: ctrlr->f_max
9310 06:51:59.677547 0.400 MHz: ctrlr->f_min
9311 06:51:59.680780 0x40ff8080: ctrlr->voltages
9312 06:51:59.681343 sclk: 390625
9313 06:51:59.684257 Bus Width = 1
9314 06:51:59.684809 sclk: 390625
9315 06:51:59.687139 Bus Width = 1
9316 06:51:59.687608 Early init status = 3
9317 06:51:59.693822 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9318 06:51:59.696834 in-header: 03 fc 00 00 01 00 00 00
9319 06:51:59.697278 in-data: 00
9320 06:51:59.703564 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9321 06:51:59.707447 in-header: 03 fd 00 00 00 00 00 00
9322 06:51:59.710542 in-data:
9323 06:51:59.713730 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9324 06:51:59.717880 in-header: 03 fc 00 00 01 00 00 00
9325 06:51:59.721182 in-data: 00
9326 06:51:59.724289 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9327 06:51:59.729955 in-header: 03 fd 00 00 00 00 00 00
9328 06:51:59.733012 in-data:
9329 06:51:59.736363 [SSUSB] Setting up USB HOST controller...
9330 06:51:59.739904 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9331 06:51:59.742864 [SSUSB] phy power-on done.
9332 06:51:59.746261 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9333 06:51:59.752501 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9334 06:51:59.756009 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9335 06:51:59.762281 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9336 06:51:59.768915 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9337 06:51:59.775682 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9338 06:51:59.782120 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9339 06:51:59.788836 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9340 06:51:59.791931 SPM: binary array size = 0x9dc
9341 06:51:59.795426 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9342 06:51:59.802273 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9343 06:51:59.808707 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9344 06:51:59.815399 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9345 06:51:59.818361 configure_display: Starting display init
9346 06:51:59.852651 anx7625_power_on_init: Init interface.
9347 06:51:59.856150 anx7625_disable_pd_protocol: Disabled PD feature.
9348 06:51:59.859312 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9349 06:51:59.887276 anx7625_start_dp_work: Secure OCM version=00
9350 06:51:59.890740 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9351 06:51:59.905525 sp_tx_get_edid_block: EDID Block = 1
9352 06:52:00.008064 Extracted contents:
9353 06:52:00.011313 header: 00 ff ff ff ff ff ff 00
9354 06:52:00.014516 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9355 06:52:00.017714 version: 01 04
9356 06:52:00.020989 basic params: 95 1f 11 78 0a
9357 06:52:00.024329 chroma info: 76 90 94 55 54 90 27 21 50 54
9358 06:52:00.027539 established: 00 00 00
9359 06:52:00.034120 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9360 06:52:00.037458 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9361 06:52:00.044295 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9362 06:52:00.050693 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9363 06:52:00.057390 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9364 06:52:00.060819 extensions: 00
9365 06:52:00.061054 checksum: fb
9366 06:52:00.061342
9367 06:52:00.063999 Manufacturer: IVO Model 57d Serial Number 0
9368 06:52:00.067298 Made week 0 of 2020
9369 06:52:00.070532 EDID version: 1.4
9370 06:52:00.070845 Digital display
9371 06:52:00.073605 6 bits per primary color channel
9372 06:52:00.073933 DisplayPort interface
9373 06:52:00.076915 Maximum image size: 31 cm x 17 cm
9374 06:52:00.080482 Gamma: 220%
9375 06:52:00.080777 Check DPMS levels
9376 06:52:00.083727 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9377 06:52:00.090162 First detailed timing is preferred timing
9378 06:52:00.090390 Established timings supported:
9379 06:52:00.093692 Standard timings supported:
9380 06:52:00.096765 Detailed timings
9381 06:52:00.100253 Hex of detail: 383680a07038204018303c0035ae10000019
9382 06:52:00.106832 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9383 06:52:00.110062 0780 0798 07c8 0820 hborder 0
9384 06:52:00.113639 0438 043b 0447 0458 vborder 0
9385 06:52:00.116777 -hsync -vsync
9386 06:52:00.117031 Did detailed timing
9387 06:52:00.123234 Hex of detail: 000000000000000000000000000000000000
9388 06:52:00.126722 Manufacturer-specified data, tag 0
9389 06:52:00.130121 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9390 06:52:00.133516 ASCII string: InfoVision
9391 06:52:00.136676 Hex of detail: 000000fe00523134304e574635205248200a
9392 06:52:00.139961 ASCII string: R140NWF5 RH
9393 06:52:00.140284 Checksum
9394 06:52:00.143487 Checksum: 0xfb (valid)
9395 06:52:00.146701 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9396 06:52:00.149920 DSI data_rate: 832800000 bps
9397 06:52:00.156762 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9398 06:52:00.159743 anx7625_parse_edid: pixelclock(138800).
9399 06:52:00.163152 hactive(1920), hsync(48), hfp(24), hbp(88)
9400 06:52:00.166472 vactive(1080), vsync(12), vfp(3), vbp(17)
9401 06:52:00.169868 anx7625_dsi_config: config dsi.
9402 06:52:00.176148 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9403 06:52:00.190187 anx7625_dsi_config: success to config DSI
9404 06:52:00.193466 anx7625_dp_start: MIPI phy setup OK.
9405 06:52:00.196422 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9406 06:52:00.200136 mtk_ddp_mode_set invalid vrefresh 60
9407 06:52:00.203183 main_disp_path_setup
9408 06:52:00.203409 ovl_layer_smi_id_en
9409 06:52:00.206600 ovl_layer_smi_id_en
9410 06:52:00.206827 ccorr_config
9411 06:52:00.207026 aal_config
9412 06:52:00.209716 gamma_config
9413 06:52:00.209944 postmask_config
9414 06:52:00.212998 dither_config
9415 06:52:00.216545 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9416 06:52:00.223102 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9417 06:52:00.226471 Root Device init finished in 553 msecs
9418 06:52:00.230028 CPU_CLUSTER: 0 init
9419 06:52:00.236400 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9420 06:52:00.239723 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9421 06:52:00.242998 APU_MBOX 0x190000b0 = 0x10001
9422 06:52:00.246286 APU_MBOX 0x190001b0 = 0x10001
9423 06:52:00.249800 APU_MBOX 0x190005b0 = 0x10001
9424 06:52:00.252998 APU_MBOX 0x190006b0 = 0x10001
9425 06:52:00.256459 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9426 06:52:00.268707 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9427 06:52:00.281120 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9428 06:52:00.287833 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9429 06:52:00.299574 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9430 06:52:00.308591 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9431 06:52:00.312226 CPU_CLUSTER: 0 init finished in 81 msecs
9432 06:52:00.315442 Devices initialized
9433 06:52:00.318830 Show all devs... After init.
9434 06:52:00.319061 Root Device: enabled 1
9435 06:52:00.321771 CPU_CLUSTER: 0: enabled 1
9436 06:52:00.325416 CPU: 00: enabled 1
9437 06:52:00.328505 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9438 06:52:00.331921 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9439 06:52:00.335263 ELOG: NV offset 0x57f000 size 0x1000
9440 06:52:00.341876 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9441 06:52:00.348916 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9442 06:52:00.351993 ELOG: Event(17) added with size 13 at 2024-02-03 06:52:00 UTC
9443 06:52:00.355079 out: cmd=0x121: 03 db 21 01 00 00 00 00
9444 06:52:00.359042 in-header: 03 59 00 00 2c 00 00 00
9445 06:52:00.372407 in-data: 05 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9446 06:52:00.378790 ELOG: Event(A1) added with size 10 at 2024-02-03 06:52:00 UTC
9447 06:52:00.385562 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9448 06:52:00.392251 ELOG: Event(A0) added with size 9 at 2024-02-03 06:52:00 UTC
9449 06:52:00.395508 elog_add_boot_reason: Logged dev mode boot
9450 06:52:00.398668 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9451 06:52:00.402152 Finalize devices...
9452 06:52:00.402391 Devices finalized
9453 06:52:00.408708 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9454 06:52:00.411886 Writing coreboot table at 0xffe64000
9455 06:52:00.415245 0. 000000000010a000-0000000000113fff: RAMSTAGE
9456 06:52:00.418361 1. 0000000040000000-00000000400fffff: RAM
9457 06:52:00.425150 2. 0000000040100000-000000004032afff: RAMSTAGE
9458 06:52:00.428451 3. 000000004032b000-00000000545fffff: RAM
9459 06:52:00.431920 4. 0000000054600000-000000005465ffff: BL31
9460 06:52:00.435223 5. 0000000054660000-00000000ffe63fff: RAM
9461 06:52:00.441824 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9462 06:52:00.444810 7. 0000000100000000-000000023fffffff: RAM
9463 06:52:00.448242 Passing 5 GPIOs to payload:
9464 06:52:00.451459 NAME | PORT | POLARITY | VALUE
9465 06:52:00.455099 EC in RW | 0x000000aa | low | undefined
9466 06:52:00.461698 EC interrupt | 0x00000005 | low | undefined
9467 06:52:00.464753 TPM interrupt | 0x000000ab | high | undefined
9468 06:52:00.471241 SD card detect | 0x00000011 | high | undefined
9469 06:52:00.474733 speaker enable | 0x00000093 | high | undefined
9470 06:52:00.477807 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9471 06:52:00.481105 in-header: 03 f9 00 00 02 00 00 00
9472 06:52:00.484441 in-data: 02 00
9473 06:52:00.484548 ADC[4]: Raw value=895930 ID=7
9474 06:52:00.487756 ADC[3]: Raw value=212700 ID=1
9475 06:52:00.491270 RAM Code: 0x71
9476 06:52:00.491348 ADC[6]: Raw value=74352 ID=0
9477 06:52:00.494427 ADC[5]: Raw value=212700 ID=1
9478 06:52:00.497668 SKU Code: 0x1
9479 06:52:00.501119 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1c2
9480 06:52:00.504539 coreboot table: 964 bytes.
9481 06:52:00.507771 IMD ROOT 0. 0xfffff000 0x00001000
9482 06:52:00.511001 IMD SMALL 1. 0xffffe000 0x00001000
9483 06:52:00.514202 RO MCACHE 2. 0xffffc000 0x00001104
9484 06:52:00.517603 CONSOLE 3. 0xfff7c000 0x00080000
9485 06:52:00.520952 FMAP 4. 0xfff7b000 0x00000452
9486 06:52:00.524418 TIME STAMP 5. 0xfff7a000 0x00000910
9487 06:52:00.527860 VBOOT WORK 6. 0xfff66000 0x00014000
9488 06:52:00.530858 RAMOOPS 7. 0xffe66000 0x00100000
9489 06:52:00.534230 COREBOOT 8. 0xffe64000 0x00002000
9490 06:52:00.534359 IMD small region:
9491 06:52:00.537524 IMD ROOT 0. 0xffffec00 0x00000400
9492 06:52:00.541062 VPD 1. 0xffffeb80 0x0000006c
9493 06:52:00.544159 MMC STATUS 2. 0xffffeb60 0x00000004
9494 06:52:00.550883 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9495 06:52:00.554503 Probing TPM: done!
9496 06:52:00.557633 Connected to device vid:did:rid of 1ae0:0028:00
9497 06:52:00.567593 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9498 06:52:00.571196 Initialized TPM device CR50 revision 0
9499 06:52:00.574895 Checking cr50 for pending updates
9500 06:52:00.578315 Reading cr50 TPM mode
9501 06:52:00.586784 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9502 06:52:00.593422 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9503 06:52:00.633885 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9504 06:52:00.637350 Checking segment from ROM address 0x40100000
9505 06:52:00.640592 Checking segment from ROM address 0x4010001c
9506 06:52:00.647240 Loading segment from ROM address 0x40100000
9507 06:52:00.647794 code (compression=0)
9508 06:52:00.657244 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9509 06:52:00.663637 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9510 06:52:00.664066 it's not compressed!
9511 06:52:00.670467 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9512 06:52:00.676845 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9513 06:52:00.693823 Loading segment from ROM address 0x4010001c
9514 06:52:00.693912 Entry Point 0x80000000
9515 06:52:00.697507 Loaded segments
9516 06:52:00.700682 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9517 06:52:00.707292 Jumping to boot code at 0x80000000(0xffe64000)
9518 06:52:00.713744 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9519 06:52:00.720527 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9520 06:52:00.728409 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9521 06:52:00.731765 Checking segment from ROM address 0x40100000
9522 06:52:00.735107 Checking segment from ROM address 0x4010001c
9523 06:52:00.741676 Loading segment from ROM address 0x40100000
9524 06:52:00.741808 code (compression=1)
9525 06:52:00.748281 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9526 06:52:00.758110 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9527 06:52:00.758207 using LZMA
9528 06:52:00.766689 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9529 06:52:00.773636 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9530 06:52:00.776691 Loading segment from ROM address 0x4010001c
9531 06:52:00.776774 Entry Point 0x54601000
9532 06:52:00.779769 Loaded segments
9533 06:52:00.783083 NOTICE: MT8192 bl31_setup
9534 06:52:00.790375 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9535 06:52:00.793766 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9536 06:52:00.797425 WARNING: region 0:
9537 06:52:00.800227 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 06:52:00.800339 WARNING: region 1:
9539 06:52:00.807041 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9540 06:52:00.810413 WARNING: region 2:
9541 06:52:00.813816 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9542 06:52:00.817196 WARNING: region 3:
9543 06:52:00.820682 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9544 06:52:00.824014 WARNING: region 4:
9545 06:52:00.830381 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9546 06:52:00.830659 WARNING: region 5:
9547 06:52:00.833819 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 06:52:00.837038 WARNING: region 6:
9549 06:52:00.840454 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 06:52:00.843968 WARNING: region 7:
9551 06:52:00.847112 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9552 06:52:00.853801 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9553 06:52:00.857205 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9554 06:52:00.860451 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9555 06:52:00.867026 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9556 06:52:00.870737 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9557 06:52:00.874199 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9558 06:52:00.880459 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9559 06:52:00.884027 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9560 06:52:00.890285 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9561 06:52:00.893800 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9562 06:52:00.896958 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9563 06:52:00.904010 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9564 06:52:00.907147 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9565 06:52:00.910402 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9566 06:52:00.916957 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9567 06:52:00.920559 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9568 06:52:00.927208 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9569 06:52:00.930501 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9570 06:52:00.933905 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9571 06:52:00.940545 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9572 06:52:00.943744 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9573 06:52:00.947105 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9574 06:52:00.954267 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9575 06:52:00.957553 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9576 06:52:00.964337 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9577 06:52:00.967685 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9578 06:52:00.970597 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9579 06:52:00.977386 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9580 06:52:00.980551 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9581 06:52:00.984084 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9582 06:52:00.990400 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9583 06:52:00.993891 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9584 06:52:01.000713 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9585 06:52:01.004200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9586 06:52:01.007348 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9587 06:52:01.010335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9588 06:52:01.017160 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9589 06:52:01.020623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9590 06:52:01.024324 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9591 06:52:01.027687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9592 06:52:01.034413 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9593 06:52:01.037559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9594 06:52:01.040487 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9595 06:52:01.043872 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9596 06:52:01.050874 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9597 06:52:01.053765 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9598 06:52:01.057160 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9599 06:52:01.060557 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9600 06:52:01.067096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9601 06:52:01.070621 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9602 06:52:01.077244 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9603 06:52:01.080173 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9604 06:52:01.083505 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9605 06:52:01.090103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9606 06:52:01.093438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9607 06:52:01.100008 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9608 06:52:01.103212 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9609 06:52:01.110141 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9610 06:52:01.113501 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9611 06:52:01.116796 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9612 06:52:01.123238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9613 06:52:01.126889 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9614 06:52:01.133466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9615 06:52:01.136992 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9616 06:52:01.143248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9617 06:52:01.146489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9618 06:52:01.153173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9619 06:52:01.156678 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9620 06:52:01.159950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9621 06:52:01.166542 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9622 06:52:01.169818 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9623 06:52:01.176612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9624 06:52:01.179969 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9625 06:52:01.186767 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9626 06:52:01.189765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9627 06:52:01.193166 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9628 06:52:01.199832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9629 06:52:01.203336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9630 06:52:01.209808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9631 06:52:01.213069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9632 06:52:01.220099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9633 06:52:01.223131 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9634 06:52:01.229805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9635 06:52:01.233312 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9636 06:52:01.236247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9637 06:52:01.243076 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9638 06:52:01.246519 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9639 06:52:01.253268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9640 06:52:01.256474 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9641 06:52:01.259917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9642 06:52:01.266627 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9643 06:52:01.270130 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9644 06:52:01.276774 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9645 06:52:01.279810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9646 06:52:01.286750 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9647 06:52:01.289826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9648 06:52:01.293516 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9649 06:52:01.300314 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9650 06:52:01.303472 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9651 06:52:01.306895 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9652 06:52:01.310384 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9653 06:52:01.316928 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9654 06:52:01.320125 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9655 06:52:01.326761 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9656 06:52:01.330138 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9657 06:52:01.333537 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9658 06:52:01.340236 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9659 06:52:01.343375 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9660 06:52:01.350305 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9661 06:52:01.353587 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9662 06:52:01.356774 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9663 06:52:01.362992 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9664 06:52:01.366569 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9665 06:52:01.373204 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9666 06:52:01.376365 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9667 06:52:01.379735 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9668 06:52:01.383139 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9669 06:52:01.389746 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9670 06:52:01.393065 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9671 06:52:01.396322 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9672 06:52:01.403000 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9673 06:52:01.406319 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9674 06:52:01.409567 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9675 06:52:01.412861 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9676 06:52:01.419877 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9677 06:52:01.422951 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9678 06:52:01.429455 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9679 06:52:01.433193 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9680 06:52:01.436281 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9681 06:52:01.442883 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9682 06:52:01.446517 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9683 06:52:01.452670 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9684 06:52:01.456386 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9685 06:52:01.459439 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9686 06:52:01.466419 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9687 06:52:01.469744 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9688 06:52:01.476529 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9689 06:52:01.479826 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9690 06:52:01.483179 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9691 06:52:01.489451 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9692 06:52:01.493032 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9693 06:52:01.496852 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9694 06:52:01.503501 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9695 06:52:01.506998 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9696 06:52:01.513587 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9697 06:52:01.516762 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9698 06:52:01.520011 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9699 06:52:01.526703 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9700 06:52:01.529932 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9701 06:52:01.536532 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9702 06:52:01.539696 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9703 06:52:01.543180 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9704 06:52:01.550088 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9705 06:52:01.553276 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9706 06:52:01.557056 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9707 06:52:01.563256 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9708 06:52:01.566827 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9709 06:52:01.573676 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9710 06:52:01.576644 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9711 06:52:01.579909 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9712 06:52:01.586415 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9713 06:52:01.589955 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9714 06:52:01.596491 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9715 06:52:01.599921 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9716 06:52:01.603359 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9717 06:52:01.609767 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9718 06:52:01.612995 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9719 06:52:01.616424 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9720 06:52:01.622917 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9721 06:52:01.626211 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9722 06:52:01.632841 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9723 06:52:01.636144 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9724 06:52:01.639415 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9725 06:52:01.646018 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9726 06:52:01.649436 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9727 06:52:01.656254 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9728 06:52:01.659220 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9729 06:52:01.665804 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9730 06:52:01.669365 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9731 06:52:01.672599 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9732 06:52:01.679175 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9733 06:52:01.682453 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9734 06:52:01.685595 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9735 06:52:01.691910 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9736 06:52:01.695477 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9737 06:52:01.702091 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9738 06:52:01.705284 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9739 06:52:01.708734 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9740 06:52:01.715000 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9741 06:52:01.718454 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9742 06:52:01.725438 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9743 06:52:01.728858 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9744 06:52:01.735553 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9745 06:52:01.738438 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9746 06:52:01.741975 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9747 06:52:01.748435 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9748 06:52:01.752050 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9749 06:52:01.758315 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9750 06:52:01.761696 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9751 06:52:01.768844 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9752 06:52:01.771914 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9753 06:52:01.775135 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9754 06:52:01.781593 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9755 06:52:01.785084 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9756 06:52:01.791776 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9757 06:52:01.795198 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9758 06:52:01.798466 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9759 06:52:01.804959 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9760 06:52:01.808244 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9761 06:52:01.814940 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9762 06:52:01.817860 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9763 06:52:01.824640 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9764 06:52:01.827973 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9765 06:52:01.831381 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9766 06:52:01.838031 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9767 06:52:01.841398 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9768 06:52:01.848280 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9769 06:52:01.851558 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9770 06:52:01.854707 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9771 06:52:01.861189 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9772 06:52:01.864660 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9773 06:52:01.870964 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9774 06:52:01.874710 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9775 06:52:01.881341 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9776 06:52:01.884457 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9777 06:52:01.887705 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9778 06:52:01.894312 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9779 06:52:01.897557 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9780 06:52:01.904220 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9781 06:52:01.907451 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9782 06:52:01.911096 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9783 06:52:01.914246 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9784 06:52:01.920747 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9785 06:52:01.923965 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9786 06:52:01.927901 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9787 06:52:01.934216 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9788 06:52:01.937372 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9789 06:52:01.940703 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9790 06:52:01.947346 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9791 06:52:01.950886 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9792 06:52:01.954139 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9793 06:52:01.961134 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9794 06:52:01.963954 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9795 06:52:01.967220 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9796 06:52:01.973760 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9797 06:52:01.977044 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9798 06:52:01.983654 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9799 06:52:01.986845 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9800 06:52:01.990341 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9801 06:52:01.997169 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9802 06:52:02.000695 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9803 06:52:02.003994 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9804 06:52:02.010606 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9805 06:52:02.013846 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9806 06:52:02.020571 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9807 06:52:02.023515 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9808 06:52:02.026778 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9809 06:52:02.033299 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9810 06:52:02.036878 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9811 06:52:02.040140 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9812 06:52:02.046513 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9813 06:52:02.049889 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9814 06:52:02.056477 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9815 06:52:02.059897 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9816 06:52:02.063196 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9817 06:52:02.069983 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9818 06:52:02.073157 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9819 06:52:02.076847 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9820 06:52:02.083102 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9821 06:52:02.086603 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9822 06:52:02.090026 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9823 06:52:02.093260 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9824 06:52:02.100053 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9825 06:52:02.103182 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9826 06:52:02.106277 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9827 06:52:02.109757 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9828 06:52:02.113036 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9829 06:52:02.119389 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9830 06:52:02.122781 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9831 06:52:02.126056 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9832 06:52:02.132933 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9833 06:52:02.135932 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9834 06:52:02.139276 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9835 06:52:02.145947 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9836 06:52:02.149401 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9837 06:52:02.156316 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9838 06:52:02.159925 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9839 06:52:02.163115 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9840 06:52:02.169804 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9841 06:52:02.173227 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9842 06:52:02.180057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9843 06:52:02.183093 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9844 06:52:02.186712 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9845 06:52:02.193031 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9846 06:52:02.196404 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9847 06:52:02.202720 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9848 06:52:02.206039 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9849 06:52:02.209381 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9850 06:52:02.215924 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9851 06:52:02.219344 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9852 06:52:02.225960 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9853 06:52:02.229003 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9854 06:52:02.235705 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9855 06:52:02.239184 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9856 06:52:02.242218 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9857 06:52:02.249191 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9858 06:52:02.252778 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9859 06:52:02.259321 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9860 06:52:02.262080 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9861 06:52:02.265618 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9862 06:52:02.272176 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9863 06:52:02.275237 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9864 06:52:02.281883 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9865 06:52:02.285256 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9866 06:52:02.288649 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9867 06:52:02.295068 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9868 06:52:02.298551 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9869 06:52:02.305314 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9870 06:52:02.308265 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9871 06:52:02.315226 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9872 06:52:02.318328 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9873 06:52:02.321729 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9874 06:52:02.327901 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9875 06:52:02.331562 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9876 06:52:02.337896 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9877 06:52:02.341049 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9878 06:52:02.347638 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9879 06:52:02.351323 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9880 06:52:02.354495 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9881 06:52:02.361187 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9882 06:52:02.364555 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9883 06:52:02.370833 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9884 06:52:02.374314 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9885 06:52:02.377816 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9886 06:52:02.384335 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9887 06:52:02.387415 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9888 06:52:02.394606 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9889 06:52:02.397622 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9890 06:52:02.400881 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9891 06:52:02.407318 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9892 06:52:02.410768 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9893 06:52:02.417471 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9894 06:52:02.420747 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9895 06:52:02.427458 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9896 06:52:02.430937 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9897 06:52:02.434020 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9898 06:52:02.440401 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9899 06:52:02.443806 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9900 06:52:02.450752 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9901 06:52:02.454111 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9902 06:52:02.460374 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9903 06:52:02.463546 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9904 06:52:02.466814 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9905 06:52:02.473851 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9906 06:52:02.476769 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9907 06:52:02.483383 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9908 06:52:02.486896 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9909 06:52:02.493209 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9910 06:52:02.496753 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9911 06:52:02.499898 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9912 06:52:02.506315 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9913 06:52:02.509555 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9914 06:52:02.516052 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9915 06:52:02.519564 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9916 06:52:02.525910 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9917 06:52:02.529307 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9918 06:52:02.536466 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9919 06:52:02.539277 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9920 06:52:02.542979 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9921 06:52:02.549402 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9922 06:52:02.552596 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9923 06:52:02.559336 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9924 06:52:02.562540 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9925 06:52:02.569340 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9926 06:52:02.572365 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9927 06:52:02.578890 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9928 06:52:02.582260 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9929 06:52:02.585417 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9930 06:52:02.592294 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9931 06:52:02.595303 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9932 06:52:02.602136 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9933 06:52:02.605460 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9934 06:52:02.612188 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9935 06:52:02.615219 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9936 06:52:02.621787 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9937 06:52:02.625203 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9938 06:52:02.628739 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9939 06:52:02.635049 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9940 06:52:02.638312 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9941 06:52:02.645165 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9942 06:52:02.648422 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9943 06:52:02.655044 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9944 06:52:02.658331 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9945 06:52:02.661327 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9946 06:52:02.667910 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9947 06:52:02.671496 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9948 06:52:02.677916 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9949 06:52:02.681004 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9950 06:52:02.687726 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9951 06:52:02.690957 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9952 06:52:02.697750 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9953 06:52:02.700883 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9954 06:52:02.704283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9955 06:52:02.710788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9956 06:52:02.714054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9957 06:52:02.720921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9958 06:52:02.724215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9959 06:52:02.727387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9960 06:52:02.734214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9961 06:52:02.737666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9962 06:52:02.744361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9963 06:52:02.747497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9964 06:52:02.753869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9965 06:52:02.757377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9966 06:52:02.764074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9967 06:52:02.767488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9968 06:52:02.773763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9969 06:52:02.777063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9970 06:52:02.783729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9971 06:52:02.787105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9972 06:52:02.793833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9973 06:52:02.796725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9974 06:52:02.803538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9975 06:52:02.807027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9976 06:52:02.813243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9977 06:52:02.816859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9978 06:52:02.823176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9979 06:52:02.826721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9980 06:52:02.833460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9981 06:52:02.836518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9982 06:52:02.843090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9983 06:52:02.846615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9984 06:52:02.853125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9985 06:52:02.856255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9986 06:52:02.863026 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9987 06:52:02.863124 INFO: [APUAPC] vio 0
9988 06:52:02.870148 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9989 06:52:02.873327 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9990 06:52:02.876905 INFO: [APUAPC] D0_APC_0: 0x400510
9991 06:52:02.879968 INFO: [APUAPC] D0_APC_1: 0x0
9992 06:52:02.883377 INFO: [APUAPC] D0_APC_2: 0x1540
9993 06:52:02.887122 INFO: [APUAPC] D0_APC_3: 0x0
9994 06:52:02.890194 INFO: [APUAPC] D1_APC_0: 0xffffffff
9995 06:52:02.893273 INFO: [APUAPC] D1_APC_1: 0xffffffff
9996 06:52:02.896514 INFO: [APUAPC] D1_APC_2: 0x3fffff
9997 06:52:02.900005 INFO: [APUAPC] D1_APC_3: 0x0
9998 06:52:02.903481 INFO: [APUAPC] D2_APC_0: 0xffffffff
9999 06:52:02.906914 INFO: [APUAPC] D2_APC_1: 0xffffffff
10000 06:52:02.909888 INFO: [APUAPC] D2_APC_2: 0x3fffff
10001 06:52:02.913243 INFO: [APUAPC] D2_APC_3: 0x0
10002 06:52:02.916450 INFO: [APUAPC] D3_APC_0: 0xffffffff
10003 06:52:02.920005 INFO: [APUAPC] D3_APC_1: 0xffffffff
10004 06:52:02.923650 INFO: [APUAPC] D3_APC_2: 0x3fffff
10005 06:52:02.926775 INFO: [APUAPC] D3_APC_3: 0x0
10006 06:52:02.929674 INFO: [APUAPC] D4_APC_0: 0xffffffff
10007 06:52:02.933092 INFO: [APUAPC] D4_APC_1: 0xffffffff
10008 06:52:02.936226 INFO: [APUAPC] D4_APC_2: 0x3fffff
10009 06:52:02.940011 INFO: [APUAPC] D4_APC_3: 0x0
10010 06:52:02.943145 INFO: [APUAPC] D5_APC_0: 0xffffffff
10011 06:52:02.946615 INFO: [APUAPC] D5_APC_1: 0xffffffff
10012 06:52:02.949835 INFO: [APUAPC] D5_APC_2: 0x3fffff
10013 06:52:02.950258 INFO: [APUAPC] D5_APC_3: 0x0
10014 06:52:02.956274 INFO: [APUAPC] D6_APC_0: 0xffffffff
10015 06:52:02.960064 INFO: [APUAPC] D6_APC_1: 0xffffffff
10016 06:52:02.963179 INFO: [APUAPC] D6_APC_2: 0x3fffff
10017 06:52:02.963607 INFO: [APUAPC] D6_APC_3: 0x0
10018 06:52:02.966744 INFO: [APUAPC] D7_APC_0: 0xffffffff
10019 06:52:02.970004 INFO: [APUAPC] D7_APC_1: 0xffffffff
10020 06:52:02.973265 INFO: [APUAPC] D7_APC_2: 0x3fffff
10021 06:52:02.976331 INFO: [APUAPC] D7_APC_3: 0x0
10022 06:52:02.979713 INFO: [APUAPC] D8_APC_0: 0xffffffff
10023 06:52:02.983191 INFO: [APUAPC] D8_APC_1: 0xffffffff
10024 06:52:02.986297 INFO: [APUAPC] D8_APC_2: 0x3fffff
10025 06:52:02.989464 INFO: [APUAPC] D8_APC_3: 0x0
10026 06:52:02.992641 INFO: [APUAPC] D9_APC_0: 0xffffffff
10027 06:52:02.995981 INFO: [APUAPC] D9_APC_1: 0xffffffff
10028 06:52:02.999189 INFO: [APUAPC] D9_APC_2: 0x3fffff
10029 06:52:03.002379 INFO: [APUAPC] D9_APC_3: 0x0
10030 06:52:03.005841 INFO: [APUAPC] D10_APC_0: 0xffffffff
10031 06:52:03.009105 INFO: [APUAPC] D10_APC_1: 0xffffffff
10032 06:52:03.012557 INFO: [APUAPC] D10_APC_2: 0x3fffff
10033 06:52:03.016026 INFO: [APUAPC] D10_APC_3: 0x0
10034 06:52:03.019062 INFO: [APUAPC] D11_APC_0: 0xffffffff
10035 06:52:03.022353 INFO: [APUAPC] D11_APC_1: 0xffffffff
10036 06:52:03.025722 INFO: [APUAPC] D11_APC_2: 0x3fffff
10037 06:52:03.028915 INFO: [APUAPC] D11_APC_3: 0x0
10038 06:52:03.032506 INFO: [APUAPC] D12_APC_0: 0xffffffff
10039 06:52:03.035610 INFO: [APUAPC] D12_APC_1: 0xffffffff
10040 06:52:03.038985 INFO: [APUAPC] D12_APC_2: 0x3fffff
10041 06:52:03.042448 INFO: [APUAPC] D12_APC_3: 0x0
10042 06:52:03.045604 INFO: [APUAPC] D13_APC_0: 0xffffffff
10043 06:52:03.049444 INFO: [APUAPC] D13_APC_1: 0xffffffff
10044 06:52:03.052729 INFO: [APUAPC] D13_APC_2: 0x3fffff
10045 06:52:03.056104 INFO: [APUAPC] D13_APC_3: 0x0
10046 06:52:03.059067 INFO: [APUAPC] D14_APC_0: 0xffffffff
10047 06:52:03.062412 INFO: [APUAPC] D14_APC_1: 0xffffffff
10048 06:52:03.065516 INFO: [APUAPC] D14_APC_2: 0x3fffff
10049 06:52:03.068950 INFO: [APUAPC] D14_APC_3: 0x0
10050 06:52:03.072360 INFO: [APUAPC] D15_APC_0: 0xffffffff
10051 06:52:03.075843 INFO: [APUAPC] D15_APC_1: 0xffffffff
10052 06:52:03.082266 INFO: [APUAPC] D15_APC_2: 0x3fffff
10053 06:52:03.082861 INFO: [APUAPC] D15_APC_3: 0x0
10054 06:52:03.085840 INFO: [APUAPC] APC_CON: 0x4
10055 06:52:03.089344 INFO: [NOCDAPC] D0_APC_0: 0x0
10056 06:52:03.092679 INFO: [NOCDAPC] D0_APC_1: 0x0
10057 06:52:03.095691 INFO: [NOCDAPC] D1_APC_0: 0x0
10058 06:52:03.098829 INFO: [NOCDAPC] D1_APC_1: 0xfff
10059 06:52:03.102093 INFO: [NOCDAPC] D2_APC_0: 0x0
10060 06:52:03.105363 INFO: [NOCDAPC] D2_APC_1: 0xfff
10061 06:52:03.108794 INFO: [NOCDAPC] D3_APC_0: 0x0
10062 06:52:03.109350 INFO: [NOCDAPC] D3_APC_1: 0xfff
10063 06:52:03.112076 INFO: [NOCDAPC] D4_APC_0: 0x0
10064 06:52:03.115571 INFO: [NOCDAPC] D4_APC_1: 0xfff
10065 06:52:03.118501 INFO: [NOCDAPC] D5_APC_0: 0x0
10066 06:52:03.121928 INFO: [NOCDAPC] D5_APC_1: 0xfff
10067 06:52:03.125251 INFO: [NOCDAPC] D6_APC_0: 0x0
10068 06:52:03.128733 INFO: [NOCDAPC] D6_APC_1: 0xfff
10069 06:52:03.131989 INFO: [NOCDAPC] D7_APC_0: 0x0
10070 06:52:03.135619 INFO: [NOCDAPC] D7_APC_1: 0xfff
10071 06:52:03.138633 INFO: [NOCDAPC] D8_APC_0: 0x0
10072 06:52:03.141927 INFO: [NOCDAPC] D8_APC_1: 0xfff
10073 06:52:03.142480 INFO: [NOCDAPC] D9_APC_0: 0x0
10074 06:52:03.145305 INFO: [NOCDAPC] D9_APC_1: 0xfff
10075 06:52:03.148477 INFO: [NOCDAPC] D10_APC_0: 0x0
10076 06:52:03.151877 INFO: [NOCDAPC] D10_APC_1: 0xfff
10077 06:52:03.155297 INFO: [NOCDAPC] D11_APC_0: 0x0
10078 06:52:03.158402 INFO: [NOCDAPC] D11_APC_1: 0xfff
10079 06:52:03.161632 INFO: [NOCDAPC] D12_APC_0: 0x0
10080 06:52:03.165040 INFO: [NOCDAPC] D12_APC_1: 0xfff
10081 06:52:03.168389 INFO: [NOCDAPC] D13_APC_0: 0x0
10082 06:52:03.171528 INFO: [NOCDAPC] D13_APC_1: 0xfff
10083 06:52:03.175079 INFO: [NOCDAPC] D14_APC_0: 0x0
10084 06:52:03.178137 INFO: [NOCDAPC] D14_APC_1: 0xfff
10085 06:52:03.181571 INFO: [NOCDAPC] D15_APC_0: 0x0
10086 06:52:03.184849 INFO: [NOCDAPC] D15_APC_1: 0xfff
10087 06:52:03.185275 INFO: [NOCDAPC] APC_CON: 0x4
10088 06:52:03.191761 INFO: [APUAPC] set_apusys_apc done
10089 06:52:03.192295 INFO: [DEVAPC] devapc_init done
10090 06:52:03.198296 INFO: GICv3 without legacy support detected.
10091 06:52:03.201919 INFO: ARM GICv3 driver initialized in EL3
10092 06:52:03.204755 INFO: Maximum SPI INTID supported: 639
10093 06:52:03.208330 INFO: BL31: Initializing runtime services
10094 06:52:03.214515 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10095 06:52:03.217991 INFO: SPM: enable CPC mode
10096 06:52:03.221086 INFO: mcdi ready for mcusys-off-idle and system suspend
10097 06:52:03.227860 INFO: BL31: Preparing for EL3 exit to normal world
10098 06:52:03.231331 INFO: Entry point address = 0x80000000
10099 06:52:03.234096 INFO: SPSR = 0x8
10100 06:52:03.238676
10101 06:52:03.239197
10102 06:52:03.239625
10103 06:52:03.242174 Starting depthcharge on Spherion...
10104 06:52:03.242707
10105 06:52:03.243132 Wipe memory regions:
10106 06:52:03.243543
10107 06:52:03.246724 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10108 06:52:03.247363 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10109 06:52:03.247816 Setting prompt string to ['asurada:']
10110 06:52:03.248344 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10111 06:52:03.249363 [0x00000040000000, 0x00000054600000)
10112 06:52:03.367792
10113 06:52:03.368309 [0x00000054660000, 0x00000080000000)
10114 06:52:03.628083
10115 06:52:03.628766 [0x000000821a7280, 0x000000ffe64000)
10116 06:52:04.373210
10117 06:52:04.373779 [0x00000100000000, 0x00000240000000)
10118 06:52:06.263434
10119 06:52:06.266462 Initializing XHCI USB controller at 0x11200000.
10120 06:52:07.304062
10121 06:52:07.307426 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10122 06:52:07.307519
10123 06:52:07.307585
10124 06:52:07.307646
10125 06:52:07.307931 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10127 06:52:07.408303 asurada: tftpboot 192.168.201.1 12694816/tftp-deploy-t9mq3kaq/kernel/image.itb 12694816/tftp-deploy-t9mq3kaq/kernel/cmdline
10128 06:52:07.408484 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10129 06:52:07.408573 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10130 06:52:07.412376 tftpboot 192.168.201.1 12694816/tftp-deploy-t9mq3kaq/kernel/image.ittp-deploy-t9mq3kaq/kernel/cmdline
10131 06:52:07.412463
10132 06:52:07.412528 Waiting for link
10133 06:52:07.573331
10134 06:52:07.573495 R8152: Initializing
10135 06:52:07.573605
10136 06:52:07.576266 Version 6 (ocp_data = 5c30)
10137 06:52:07.576349
10138 06:52:07.579606 R8152: Done initializing
10139 06:52:07.579688
10140 06:52:07.579754 Adding net device
10141 06:52:09.483637
10142 06:52:09.483791 done.
10143 06:52:09.483861
10144 06:52:09.483923 MAC: 00:24:32:30:78:ff
10145 06:52:09.483982
10146 06:52:09.486879 Sending DHCP discover... done.
10147 06:52:09.486964
10148 06:52:09.490144 Waiting for reply... done.
10149 06:52:09.490256
10150 06:52:09.493178 Sending DHCP request... done.
10151 06:52:09.493260
10152 06:52:09.498109 Waiting for reply... done.
10153 06:52:09.498231
10154 06:52:09.498301 My ip is 192.168.201.21
10155 06:52:09.498364
10156 06:52:09.501615 The DHCP server ip is 192.168.201.1
10157 06:52:09.501699
10158 06:52:09.507925 TFTP server IP predefined by user: 192.168.201.1
10159 06:52:09.508007
10160 06:52:09.514876 Bootfile predefined by user: 12694816/tftp-deploy-t9mq3kaq/kernel/image.itb
10161 06:52:09.514959
10162 06:52:09.515024 Sending tftp read request... done.
10163 06:52:09.518117
10164 06:52:09.521435 Waiting for the transfer...
10165 06:52:09.521568
10166 06:52:10.107828 00000000 ################################################################
10167 06:52:10.107983
10168 06:52:10.686906 00080000 ################################################################
10169 06:52:10.687056
10170 06:52:11.260078 00100000 ################################################################
10171 06:52:11.260223
10172 06:52:11.826107 00180000 ################################################################
10173 06:52:11.826250
10174 06:52:12.397633 00200000 ################################################################
10175 06:52:12.397766
10176 06:52:12.980778 00280000 ################################################################
10177 06:52:12.980962
10178 06:52:13.561349 00300000 ################################################################
10179 06:52:13.561566
10180 06:52:14.138560 00380000 ################################################################
10181 06:52:14.138700
10182 06:52:14.707682 00400000 ################################################################
10183 06:52:14.707855
10184 06:52:15.277443 00480000 ################################################################
10185 06:52:15.277624
10186 06:52:15.844163 00500000 ################################################################
10187 06:52:15.844306
10188 06:52:16.428016 00580000 ################################################################
10189 06:52:16.428167
10190 06:52:17.002302 00600000 ################################################################
10191 06:52:17.002452
10192 06:52:17.583446 00680000 ################################################################
10193 06:52:17.583599
10194 06:52:18.164764 00700000 ################################################################
10195 06:52:18.164944
10196 06:52:18.761381 00780000 ################################################################
10197 06:52:18.761556
10198 06:52:19.344780 00800000 ################################################################
10199 06:52:19.344933
10200 06:52:20.038380 00880000 ################################################################
10201 06:52:20.038714
10202 06:52:20.667093 00900000 ################################################################
10203 06:52:20.667246
10204 06:52:21.276535 00980000 ################################################################
10205 06:52:21.276713
10206 06:52:21.817877 00a00000 ################################################################
10207 06:52:21.818022
10208 06:52:22.362335 00a80000 ################################################################
10209 06:52:22.362511
10210 06:52:22.919596 00b00000 ################################################################
10211 06:52:22.919745
10212 06:52:23.481193 00b80000 ################################################################
10213 06:52:23.481358
10214 06:52:24.066651 00c00000 ################################################################
10215 06:52:24.066796
10216 06:52:24.668325 00c80000 ################################################################
10217 06:52:24.668480
10218 06:52:25.240114 00d00000 ################################################################
10219 06:52:25.240265
10220 06:52:25.799727 00d80000 ################################################################
10221 06:52:25.799867
10222 06:52:26.388467 00e00000 ################################################################
10223 06:52:26.388612
10224 06:52:26.977421 00e80000 ################################################################
10225 06:52:26.977608
10226 06:52:27.585684 00f00000 ################################################################
10227 06:52:27.585834
10228 06:52:28.186060 00f80000 ################################################################
10229 06:52:28.186219
10230 06:52:28.742648 01000000 ################################################################
10231 06:52:28.742810
10232 06:52:29.343606 01080000 ################################################################
10233 06:52:29.343755
10234 06:52:29.950390 01100000 ################################################################
10235 06:52:29.950534
10236 06:52:30.554727 01180000 ################################################################
10237 06:52:30.554874
10238 06:52:31.124027 01200000 ################################################################
10239 06:52:31.124161
10240 06:52:31.689312 01280000 ################################################################
10241 06:52:31.689464
10242 06:52:32.296997 01300000 ################################################################
10243 06:52:32.297151
10244 06:52:32.903305 01380000 ################################################################
10245 06:52:32.903455
10246 06:52:33.510525 01400000 ################################################################
10247 06:52:33.510679
10248 06:52:34.093859 01480000 ################################################################
10249 06:52:34.094005
10250 06:52:34.663824 01500000 ################################################################
10251 06:52:34.663980
10252 06:52:35.257684 01580000 ################################################################
10253 06:52:35.257842
10254 06:52:35.858836 01600000 ################################################################
10255 06:52:35.858997
10256 06:52:36.448366 01680000 ################################################################
10257 06:52:36.448535
10258 06:52:37.023362 01700000 ################################################################
10259 06:52:37.023536
10260 06:52:37.591911 01780000 ################################################################
10261 06:52:37.592073
10262 06:52:38.150523 01800000 ################################################################
10263 06:52:38.150687
10264 06:52:38.732240 01880000 ################################################################
10265 06:52:38.732401
10266 06:52:39.328616 01900000 ################################################################
10267 06:52:39.328781
10268 06:52:39.907296 01980000 ################################################################
10269 06:52:39.907450
10270 06:52:40.476920 01a00000 ################################################################
10271 06:52:40.477128
10272 06:52:41.068227 01a80000 ################################################################
10273 06:52:41.068385
10274 06:52:41.662159 01b00000 ################################################################
10275 06:52:41.662315
10276 06:52:42.260102 01b80000 ################################################################
10277 06:52:42.260254
10278 06:52:42.844916 01c00000 ################################################################
10279 06:52:42.845053
10280 06:52:42.863504 01c80000 ### done.
10281 06:52:42.863631
10282 06:52:42.866667 The bootfile was 29902186 bytes long.
10283 06:52:42.866752
10284 06:52:42.870140 Sending tftp read request... done.
10285 06:52:42.870253
10286 06:52:42.873612 Waiting for the transfer...
10287 06:52:42.873701
10288 06:52:42.873767 00000000 # done.
10289 06:52:42.873830
10290 06:52:42.883668 Command line loaded dynamically from TFTP file: 12694816/tftp-deploy-t9mq3kaq/kernel/cmdline
10291 06:52:42.883769
10292 06:52:42.902961 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694816/extract-nfsrootfs-_4ca9pq2,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10293 06:52:42.903128
10294 06:52:42.906434 Loading FIT.
10295 06:52:42.906548
10296 06:52:42.909785 Image ramdisk-1 has 17802292 bytes.
10297 06:52:42.909870
10298 06:52:42.909936 Image fdt-1 has 47278 bytes.
10299 06:52:42.909997
10300 06:52:42.912872 Image kernel-1 has 12050581 bytes.
10301 06:52:42.912982
10302 06:52:42.923194 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10303 06:52:42.923314
10304 06:52:42.939490 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10305 06:52:42.939635
10306 06:52:42.946100 Choosing best match conf-1 for compat google,spherion-rev2.
10307 06:52:42.950270
10308 06:52:42.954879 Connected to device vid:did:rid of 1ae0:0028:00
10309 06:52:42.962039
10310 06:52:42.964956 tpm_get_response: command 0x17b, return code 0x0
10311 06:52:42.965066
10312 06:52:42.968428 ec_init: CrosEC protocol v3 supported (256, 248)
10313 06:52:42.972462
10314 06:52:42.975626 tpm_cleanup: add release locality here.
10315 06:52:42.975730
10316 06:52:42.975829 Shutting down all USB controllers.
10317 06:52:42.979127
10318 06:52:42.979229 Removing current net device
10319 06:52:42.979321
10320 06:52:42.985496 Exiting depthcharge with code 4 at timestamp: 69060717
10321 06:52:42.985596
10322 06:52:42.988857 LZMA decompressing kernel-1 to 0x821a6718
10323 06:52:42.988964
10324 06:52:42.992297 LZMA decompressing kernel-1 to 0x40000000
10325 06:52:44.491071
10326 06:52:44.491232 jumping to kernel
10327 06:52:44.491681 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10328 06:52:44.491782 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10329 06:52:44.491857 Setting prompt string to ['Linux version [0-9]']
10330 06:52:44.491925 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10331 06:52:44.491991 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10332 06:52:44.573219
10333 06:52:44.576258 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10334 06:52:44.579844 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10335 06:52:44.579934 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10336 06:52:44.580036 Setting prompt string to []
10337 06:52:44.580162 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10338 06:52:44.580234 Using line separator: #'\n'#
10339 06:52:44.580321 No login prompt set.
10340 06:52:44.580398 Parsing kernel messages
10341 06:52:44.580452 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10342 06:52:44.580557 [login-action] Waiting for messages, (timeout 00:03:44)
10343 06:52:44.599701 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10344 06:52:44.602808 [ 0.000000] random: crng init done
10345 06:52:44.609351 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10346 06:52:44.612735 [ 0.000000] efi: UEFI not found.
10347 06:52:44.619597 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10348 06:52:44.626090 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10349 06:52:44.635883 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10350 06:52:44.645740 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10351 06:52:44.652738 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10352 06:52:44.658753 [ 0.000000] printk: bootconsole [mtk8250] enabled
10353 06:52:44.665633 [ 0.000000] NUMA: No NUMA configuration found
10354 06:52:44.672214 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10355 06:52:44.675609 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10356 06:52:44.678728 [ 0.000000] Zone ranges:
10357 06:52:44.685226 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10358 06:52:44.688543 [ 0.000000] DMA32 empty
10359 06:52:44.695192 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10360 06:52:44.698606 [ 0.000000] Movable zone start for each node
10361 06:52:44.701839 [ 0.000000] Early memory node ranges
10362 06:52:44.708624 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10363 06:52:44.715160 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10364 06:52:44.721843 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10365 06:52:44.728472 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10366 06:52:44.734737 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10367 06:52:44.741685 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10368 06:52:44.797057 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10369 06:52:44.803872 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10370 06:52:44.810476 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10371 06:52:44.813750 [ 0.000000] psci: probing for conduit method from DT.
10372 06:52:44.820256 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10373 06:52:44.823477 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10374 06:52:44.830115 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10375 06:52:44.833612 [ 0.000000] psci: SMC Calling Convention v1.2
10376 06:52:44.840437 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10377 06:52:44.843789 [ 0.000000] Detected VIPT I-cache on CPU0
10378 06:52:44.850028 [ 0.000000] CPU features: detected: GIC system register CPU interface
10379 06:52:44.856754 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10380 06:52:44.863200 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10381 06:52:44.869872 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10382 06:52:44.879717 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10383 06:52:44.886413 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10384 06:52:44.889769 [ 0.000000] alternatives: applying boot alternatives
10385 06:52:44.896172 [ 0.000000] Fallback order for Node 0: 0
10386 06:52:44.903173 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10387 06:52:44.906307 [ 0.000000] Policy zone: Normal
10388 06:52:44.929249 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694816/extract-nfsrootfs-_4ca9pq2,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10389 06:52:44.939224 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10390 06:52:44.949578 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10391 06:52:44.959797 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10392 06:52:44.966409 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10393 06:52:44.969697 <6>[ 0.000000] software IO TLB: area num 8.
10394 06:52:45.026133 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10395 06:52:45.175273 <6>[ 0.000000] Memory: 7949868K/8385536K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 402900K reserved, 32768K cma-reserved)
10396 06:52:45.181955 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10397 06:52:45.188466 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10398 06:52:45.192177 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10399 06:52:45.198433 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10400 06:52:45.205018 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10401 06:52:45.208543 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10402 06:52:45.218312 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10403 06:52:45.225095 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10404 06:52:45.231427 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10405 06:52:45.238163 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10406 06:52:45.241602 <6>[ 0.000000] GICv3: 608 SPIs implemented
10407 06:52:45.244575 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10408 06:52:45.251452 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10409 06:52:45.254556 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10410 06:52:45.261363 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10411 06:52:45.274448 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10412 06:52:45.287640 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10413 06:52:45.294232 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10414 06:52:45.301977 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10415 06:52:45.315294 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10416 06:52:45.321706 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10417 06:52:45.328551 <6>[ 0.009230] Console: colour dummy device 80x25
10418 06:52:45.338403 <6>[ 0.013984] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10419 06:52:45.345056 <6>[ 0.024491] pid_max: default: 32768 minimum: 301
10420 06:52:45.348528 <6>[ 0.029356] LSM: Security Framework initializing
10421 06:52:45.355253 <6>[ 0.034295] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10422 06:52:45.365005 <6>[ 0.042158] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10423 06:52:45.371782 <6>[ 0.051573] cblist_init_generic: Setting adjustable number of callback queues.
10424 06:52:45.378225 <6>[ 0.059016] cblist_init_generic: Setting shift to 3 and lim to 1.
10425 06:52:45.388421 <6>[ 0.065355] cblist_init_generic: Setting adjustable number of callback queues.
10426 06:52:45.394700 <6>[ 0.072783] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 06:52:45.398347 <6>[ 0.079184] rcu: Hierarchical SRCU implementation.
10428 06:52:45.404746 <6>[ 0.084199] rcu: Max phase no-delay instances is 1000.
10429 06:52:45.411356 <6>[ 0.091227] EFI services will not be available.
10430 06:52:45.414767 <6>[ 0.096175] smp: Bringing up secondary CPUs ...
10431 06:52:45.422881 <6>[ 0.101226] Detected VIPT I-cache on CPU1
10432 06:52:45.429342 <6>[ 0.101297] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10433 06:52:45.436117 <6>[ 0.101328] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10434 06:52:45.439414 <6>[ 0.101667] Detected VIPT I-cache on CPU2
10435 06:52:45.445884 <6>[ 0.101714] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10436 06:52:45.455783 <6>[ 0.101731] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10437 06:52:45.459163 <6>[ 0.101989] Detected VIPT I-cache on CPU3
10438 06:52:45.465736 <6>[ 0.102034] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10439 06:52:45.472400 <6>[ 0.102048] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10440 06:52:45.475958 <6>[ 0.102349] CPU features: detected: Spectre-v4
10441 06:52:45.482251 <6>[ 0.102356] CPU features: detected: Spectre-BHB
10442 06:52:45.485691 <6>[ 0.102360] Detected PIPT I-cache on CPU4
10443 06:52:45.492679 <6>[ 0.102418] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10444 06:52:45.498849 <6>[ 0.102434] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10445 06:52:45.505682 <6>[ 0.102727] Detected PIPT I-cache on CPU5
10446 06:52:45.512473 <6>[ 0.102790] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10447 06:52:45.518999 <6>[ 0.102807] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10448 06:52:45.522228 <6>[ 0.103088] Detected PIPT I-cache on CPU6
10449 06:52:45.528654 <6>[ 0.103153] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10450 06:52:45.535259 <6>[ 0.103169] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10451 06:52:45.541901 <6>[ 0.103465] Detected PIPT I-cache on CPU7
10452 06:52:45.548316 <6>[ 0.103530] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10453 06:52:45.555183 <6>[ 0.103546] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10454 06:52:45.558604 <6>[ 0.103593] smp: Brought up 1 node, 8 CPUs
10455 06:52:45.565130 <6>[ 0.244915] SMP: Total of 8 processors activated.
10456 06:52:45.568159 <6>[ 0.249836] CPU features: detected: 32-bit EL0 Support
10457 06:52:45.578032 <6>[ 0.255199] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10458 06:52:45.584793 <6>[ 0.263998] CPU features: detected: Common not Private translations
10459 06:52:45.591453 <6>[ 0.270474] CPU features: detected: CRC32 instructions
10460 06:52:45.594460 <6>[ 0.275825] CPU features: detected: RCpc load-acquire (LDAPR)
10461 06:52:45.601292 <6>[ 0.281785] CPU features: detected: LSE atomic instructions
10462 06:52:45.607666 <6>[ 0.287567] CPU features: detected: Privileged Access Never
10463 06:52:45.614566 <6>[ 0.293382] CPU features: detected: RAS Extension Support
10464 06:52:45.620836 <6>[ 0.298991] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10465 06:52:45.624299 <6>[ 0.306256] CPU: All CPU(s) started at EL2
10466 06:52:45.630776 <6>[ 0.310573] alternatives: applying system-wide alternatives
10467 06:52:45.640482 <6>[ 0.321295] devtmpfs: initialized
10468 06:52:45.655946 <6>[ 0.330172] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10469 06:52:45.662685 <6>[ 0.340132] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10470 06:52:45.669188 <6>[ 0.347856] pinctrl core: initialized pinctrl subsystem
10471 06:52:45.672592 <6>[ 0.354514] DMI not present or invalid.
10472 06:52:45.679400 <6>[ 0.358928] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10473 06:52:45.689050 <6>[ 0.365808] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10474 06:52:45.695474 <6>[ 0.373393] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10475 06:52:45.705783 <6>[ 0.381603] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10476 06:52:45.708957 <6>[ 0.389846] audit: initializing netlink subsys (disabled)
10477 06:52:45.718836 <5>[ 0.395539] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10478 06:52:45.725368 <6>[ 0.396236] thermal_sys: Registered thermal governor 'step_wise'
10479 06:52:45.731858 <6>[ 0.403505] thermal_sys: Registered thermal governor 'power_allocator'
10480 06:52:45.735239 <6>[ 0.409757] cpuidle: using governor menu
10481 06:52:45.741789 <6>[ 0.420712] NET: Registered PF_QIPCRTR protocol family
10482 06:52:45.748603 <6>[ 0.426195] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10483 06:52:45.751784 <6>[ 0.433300] ASID allocator initialised with 32768 entries
10484 06:52:45.759096 <6>[ 0.439865] Serial: AMBA PL011 UART driver
10485 06:52:45.767995 <4>[ 0.448638] Trying to register duplicate clock ID: 134
10486 06:52:45.821472 <6>[ 0.505579] KASLR enabled
10487 06:52:45.835813 <6>[ 0.513263] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10488 06:52:45.842489 <6>[ 0.520272] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10489 06:52:45.849109 <6>[ 0.526763] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10490 06:52:45.855715 <6>[ 0.533770] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10491 06:52:45.862130 <6>[ 0.540258] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10492 06:52:45.868861 <6>[ 0.547261] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10493 06:52:45.875342 <6>[ 0.553748] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10494 06:52:45.881897 <6>[ 0.560753] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10495 06:52:45.885216 <6>[ 0.568250] ACPI: Interpreter disabled.
10496 06:52:45.893598 <6>[ 0.574673] iommu: Default domain type: Translated
10497 06:52:45.900184 <6>[ 0.579783] iommu: DMA domain TLB invalidation policy: strict mode
10498 06:52:45.903588 <5>[ 0.586444] SCSI subsystem initialized
10499 06:52:45.910257 <6>[ 0.590604] usbcore: registered new interface driver usbfs
10500 06:52:45.916912 <6>[ 0.596335] usbcore: registered new interface driver hub
10501 06:52:45.920208 <6>[ 0.601887] usbcore: registered new device driver usb
10502 06:52:45.927072 <6>[ 0.607984] pps_core: LinuxPPS API ver. 1 registered
10503 06:52:45.936925 <6>[ 0.613177] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10504 06:52:45.940352 <6>[ 0.622522] PTP clock support registered
10505 06:52:45.943748 <6>[ 0.626763] EDAC MC: Ver: 3.0.0
10506 06:52:45.950967 <6>[ 0.631915] FPGA manager framework
10507 06:52:45.957540 <6>[ 0.635594] Advanced Linux Sound Architecture Driver Initialized.
10508 06:52:45.960876 <6>[ 0.642365] vgaarb: loaded
10509 06:52:45.967424 <6>[ 0.645519] clocksource: Switched to clocksource arch_sys_counter
10510 06:52:45.970625 <5>[ 0.651959] VFS: Disk quotas dquot_6.6.0
10511 06:52:45.977331 <6>[ 0.656145] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10512 06:52:45.980564 <6>[ 0.663331] pnp: PnP ACPI: disabled
10513 06:52:45.989079 <6>[ 0.670005] NET: Registered PF_INET protocol family
10514 06:52:45.998900 <6>[ 0.675599] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10515 06:52:46.010162 <6>[ 0.687931] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10516 06:52:46.020203 <6>[ 0.696748] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10517 06:52:46.026810 <6>[ 0.704720] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10518 06:52:46.036564 <6>[ 0.713417] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10519 06:52:46.043379 <6>[ 0.723171] TCP: Hash tables configured (established 65536 bind 65536)
10520 06:52:46.050144 <6>[ 0.730034] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10521 06:52:46.059900 <6>[ 0.737230] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10522 06:52:46.066522 <6>[ 0.744933] NET: Registered PF_UNIX/PF_LOCAL protocol family
10523 06:52:46.073052 <6>[ 0.751088] RPC: Registered named UNIX socket transport module.
10524 06:52:46.076063 <6>[ 0.757243] RPC: Registered udp transport module.
10525 06:52:46.082756 <6>[ 0.762175] RPC: Registered tcp transport module.
10526 06:52:46.089396 <6>[ 0.767107] RPC: Registered tcp NFSv4.1 backchannel transport module.
10527 06:52:46.092682 <6>[ 0.773774] PCI: CLS 0 bytes, default 64
10528 06:52:46.095893 <6>[ 0.778079] Unpacking initramfs...
10529 06:52:46.112703 <6>[ 0.790108] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10530 06:52:46.122662 <6>[ 0.798746] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10531 06:52:46.125940 <6>[ 0.807584] kvm [1]: IPA Size Limit: 40 bits
10532 06:52:46.132469 <6>[ 0.812112] kvm [1]: GICv3: no GICV resource entry
10533 06:52:46.135670 <6>[ 0.817131] kvm [1]: disabling GICv2 emulation
10534 06:52:46.142541 <6>[ 0.821823] kvm [1]: GIC system register CPU interface enabled
10535 06:52:46.145935 <6>[ 0.827986] kvm [1]: vgic interrupt IRQ18
10536 06:52:46.152303 <6>[ 0.832340] kvm [1]: VHE mode initialized successfully
10537 06:52:46.158776 <5>[ 0.838787] Initialise system trusted keyrings
10538 06:52:46.165306 <6>[ 0.843588] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10539 06:52:46.172858 <6>[ 0.853552] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10540 06:52:46.179475 <5>[ 0.859943] NFS: Registering the id_resolver key type
10541 06:52:46.182817 <5>[ 0.865248] Key type id_resolver registered
10542 06:52:46.189190 <5>[ 0.869664] Key type id_legacy registered
10543 06:52:46.195778 <6>[ 0.873943] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10544 06:52:46.202392 <6>[ 0.880868] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10545 06:52:46.208878 <6>[ 0.888598] 9p: Installing v9fs 9p2000 file system support
10546 06:52:46.245736 <5>[ 0.926477] Key type asymmetric registered
10547 06:52:46.248971 <5>[ 0.930811] Asymmetric key parser 'x509' registered
10548 06:52:46.258765 <6>[ 0.935955] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10549 06:52:46.262354 <6>[ 0.943583] io scheduler mq-deadline registered
10550 06:52:46.265544 <6>[ 0.948350] io scheduler kyber registered
10551 06:52:46.284472 <6>[ 0.965483] EINJ: ACPI disabled.
10552 06:52:46.316698 <4>[ 0.991051] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10553 06:52:46.326453 <4>[ 1.001674] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10554 06:52:46.341488 <6>[ 1.022553] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10555 06:52:46.349443 <6>[ 1.030552] printk: console [ttyS0] disabled
10556 06:52:46.377766 <6>[ 1.055184] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10557 06:52:46.384479 <6>[ 1.064660] printk: console [ttyS0] enabled
10558 06:52:46.387897 <6>[ 1.064660] printk: console [ttyS0] enabled
10559 06:52:46.394226 <6>[ 1.073553] printk: bootconsole [mtk8250] disabled
10560 06:52:46.397663 <6>[ 1.073553] printk: bootconsole [mtk8250] disabled
10561 06:52:46.404383 <6>[ 1.084793] SuperH (H)SCI(F) driver initialized
10562 06:52:46.407436 <6>[ 1.090098] msm_serial: driver initialized
10563 06:52:46.421592 <6>[ 1.099112] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10564 06:52:46.431665 <6>[ 1.107660] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10565 06:52:46.438326 <6>[ 1.116204] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10566 06:52:46.448301 <6>[ 1.124838] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10567 06:52:46.458212 <6>[ 1.133544] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10568 06:52:46.464830 <6>[ 1.142269] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10569 06:52:46.474843 <6>[ 1.150809] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10570 06:52:46.481220 <6>[ 1.159617] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10571 06:52:46.491200 <6>[ 1.168161] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10572 06:52:46.503097 <6>[ 1.183927] loop: module loaded
10573 06:52:46.509759 <6>[ 1.189998] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10574 06:52:46.532472 <4>[ 1.213488] mtk-pmic-keys: Failed to locate of_node [id: -1]
10575 06:52:46.539664 <6>[ 1.220541] megasas: 07.719.03.00-rc1
10576 06:52:46.549558 <6>[ 1.230471] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10577 06:52:46.556463 <6>[ 1.236911] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10578 06:52:46.573191 <6>[ 1.253745] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10579 06:52:46.629486 <6>[ 1.303736] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10580 06:52:46.842364 <6>[ 1.523330] Freeing initrd memory: 17384K
10581 06:52:46.852847 <6>[ 1.533534] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10582 06:52:46.863812 <6>[ 1.544627] tun: Universal TUN/TAP device driver, 1.6
10583 06:52:46.867052 <6>[ 1.550710] thunder_xcv, ver 1.0
10584 06:52:46.870458 <6>[ 1.554215] thunder_bgx, ver 1.0
10585 06:52:46.873719 <6>[ 1.557712] nicpf, ver 1.0
10586 06:52:46.884220 <6>[ 1.561725] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10587 06:52:46.887817 <6>[ 1.569204] hns3: Copyright (c) 2017 Huawei Corporation.
10588 06:52:46.894283 <6>[ 1.574798] hclge is initializing
10589 06:52:46.897442 <6>[ 1.578380] e1000: Intel(R) PRO/1000 Network Driver
10590 06:52:46.904302 <6>[ 1.583511] e1000: Copyright (c) 1999-2006 Intel Corporation.
10591 06:52:46.907423 <6>[ 1.589531] e1000e: Intel(R) PRO/1000 Network Driver
10592 06:52:46.914250 <6>[ 1.594747] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10593 06:52:46.920974 <6>[ 1.600934] igb: Intel(R) Gigabit Ethernet Network Driver
10594 06:52:46.927523 <6>[ 1.606584] igb: Copyright (c) 2007-2014 Intel Corporation.
10595 06:52:46.933944 <6>[ 1.612421] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10596 06:52:46.940678 <6>[ 1.618939] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10597 06:52:46.944051 <6>[ 1.625404] sky2: driver version 1.30
10598 06:52:46.950904 <6>[ 1.630395] VFIO - User Level meta-driver version: 0.3
10599 06:52:46.958056 <6>[ 1.638607] usbcore: registered new interface driver usb-storage
10600 06:52:46.964857 <6>[ 1.645049] usbcore: registered new device driver onboard-usb-hub
10601 06:52:46.973889 <6>[ 1.654242] mt6397-rtc mt6359-rtc: registered as rtc0
10602 06:52:46.983989 <6>[ 1.659707] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:52:46 UTC (1706943166)
10603 06:52:46.987178 <6>[ 1.669277] i2c_dev: i2c /dev entries driver
10604 06:52:47.003764 <6>[ 1.681023] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10605 06:52:47.023083 <6>[ 1.704003] cpu cpu0: EM: created perf domain
10606 06:52:47.026183 <6>[ 1.708952] cpu cpu4: EM: created perf domain
10607 06:52:47.033766 <6>[ 1.714578] sdhci: Secure Digital Host Controller Interface driver
10608 06:52:47.040471 <6>[ 1.721012] sdhci: Copyright(c) Pierre Ossman
10609 06:52:47.046902 <6>[ 1.725964] Synopsys Designware Multimedia Card Interface Driver
10610 06:52:47.053585 <6>[ 1.732600] sdhci-pltfm: SDHCI platform and OF driver helper
10611 06:52:47.057029 <6>[ 1.732659] mmc0: CQHCI version 5.10
10612 06:52:47.063723 <6>[ 1.742496] ledtrig-cpu: registered to indicate activity on CPUs
10613 06:52:47.070389 <6>[ 1.749619] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10614 06:52:47.076906 <6>[ 1.756679] usbcore: registered new interface driver usbhid
10615 06:52:47.080166 <6>[ 1.762502] usbhid: USB HID core driver
10616 06:52:47.086717 <6>[ 1.766728] spi_master spi0: will run message pump with realtime priority
10617 06:52:47.133667 <6>[ 1.807884] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10618 06:52:47.150350 <6>[ 1.824521] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10619 06:52:47.157704 <6>[ 1.838162] mmc0: Command Queue Engine enabled
10620 06:52:47.164625 <6>[ 1.839848] cros-ec-spi spi0.0: Chrome EC device registered
10621 06:52:47.168005 <6>[ 1.842888] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10622 06:52:47.174783 <6>[ 1.855946] mmcblk0: mmc0:0001 DA4128 116 GiB
10623 06:52:47.187940 <6>[ 1.865782] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10624 06:52:47.194683 <6>[ 1.869099] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10625 06:52:47.201220 <6>[ 1.876271] NET: Registered PF_PACKET protocol family
10626 06:52:47.204747 <6>[ 1.883671] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10627 06:52:47.211587 <6>[ 1.886421] 9pnet: Installing 9P2000 support
10628 06:52:47.214486 <6>[ 1.892471] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10629 06:52:47.221572 <5>[ 1.896105] Key type dns_resolver registered
10630 06:52:47.227806 <6>[ 1.902233] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10631 06:52:47.231318 <6>[ 1.906284] registered taskstats version 1
10632 06:52:47.234570 <5>[ 1.916714] Loading compiled-in X.509 certificates
10633 06:52:47.265611 <4>[ 1.939874] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10634 06:52:47.275492 <4>[ 1.950513] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 06:52:47.282486 <3>[ 1.961030] debugfs: File 'uA_load' in directory '/' already present!
10636 06:52:47.289211 <3>[ 1.967721] debugfs: File 'min_uV' in directory '/' already present!
10637 06:52:47.295502 <3>[ 1.974322] debugfs: File 'max_uV' in directory '/' already present!
10638 06:52:47.301961 <3>[ 1.980922] debugfs: File 'constraint_flags' in directory '/' already present!
10639 06:52:47.312130 <3>[ 1.989987] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10640 06:52:47.321282 <6>[ 2.002125] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10641 06:52:47.328073 <6>[ 2.008813] xhci-mtk 11200000.usb: xHCI Host Controller
10642 06:52:47.334389 <6>[ 2.014302] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10643 06:52:47.344771 <6>[ 2.022136] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10644 06:52:47.351143 <6>[ 2.031570] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10645 06:52:47.357778 <6>[ 2.037677] xhci-mtk 11200000.usb: xHCI Host Controller
10646 06:52:47.364596 <6>[ 2.043154] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10647 06:52:47.371123 <6>[ 2.050801] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10648 06:52:47.377944 <6>[ 2.058473] hub 1-0:1.0: USB hub found
10649 06:52:47.381231 <6>[ 2.062485] hub 1-0:1.0: 1 port detected
10650 06:52:47.388072 <6>[ 2.066748] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10651 06:52:47.394655 <6>[ 2.075267] hub 2-0:1.0: USB hub found
10652 06:52:47.397861 <6>[ 2.079271] hub 2-0:1.0: 1 port detected
10653 06:52:47.406553 <6>[ 2.087378] mtk-msdc 11f70000.mmc: Got CD GPIO
10654 06:52:47.418486 <6>[ 2.095764] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10655 06:52:47.424837 <6>[ 2.103806] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10656 06:52:47.435188 <4>[ 2.111713] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10657 06:52:47.444880 <6>[ 2.121241] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10658 06:52:47.451713 <6>[ 2.129318] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10659 06:52:47.458206 <6>[ 2.137333] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10660 06:52:47.468521 <6>[ 2.145252] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10661 06:52:47.475115 <6>[ 2.153069] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10662 06:52:47.485121 <6>[ 2.160887] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10663 06:52:47.495277 <6>[ 2.171212] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10664 06:52:47.501466 <6>[ 2.179572] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10665 06:52:47.511438 <6>[ 2.187916] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10666 06:52:47.518027 <6>[ 2.196255] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10667 06:52:47.528315 <6>[ 2.204594] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10668 06:52:47.534838 <6>[ 2.212935] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10669 06:52:47.544942 <6>[ 2.221274] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10670 06:52:47.551739 <6>[ 2.229612] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10671 06:52:47.561403 <6>[ 2.237963] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10672 06:52:47.567897 <6>[ 2.246302] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10673 06:52:47.577812 <6>[ 2.254651] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10674 06:52:47.584631 <6>[ 2.262991] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10675 06:52:47.594582 <6>[ 2.271329] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10676 06:52:47.601134 <6>[ 2.279668] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10677 06:52:47.610977 <6>[ 2.288008] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10678 06:52:47.617859 <6>[ 2.296739] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10679 06:52:47.624988 <6>[ 2.303882] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10680 06:52:47.630942 <6>[ 2.310632] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10681 06:52:47.637380 <6>[ 2.317378] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10682 06:52:47.644564 <6>[ 2.324328] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10683 06:52:47.654436 <6>[ 2.331175] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10684 06:52:47.664190 <6>[ 2.340304] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10685 06:52:47.673927 <6>[ 2.349422] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10686 06:52:47.684058 <6>[ 2.358715] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10687 06:52:47.693805 <6>[ 2.368182] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10688 06:52:47.700229 <6>[ 2.377649] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10689 06:52:47.710218 <6>[ 2.386768] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10690 06:52:47.720405 <6>[ 2.396234] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10691 06:52:47.730055 <6>[ 2.405353] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10692 06:52:47.740187 <6>[ 2.414647] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10693 06:52:47.749900 <6>[ 2.424807] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10694 06:52:47.760128 <6>[ 2.436414] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10695 06:52:47.766071 <6>[ 2.446132] Trying to probe devices needed for running init ...
10696 06:52:47.789009 <6>[ 2.466050] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10697 06:52:47.817185 <6>[ 2.497487] hub 2-1:1.0: USB hub found
10698 06:52:47.820183 <6>[ 2.502027] hub 2-1:1.0: 3 ports detected
10699 06:52:47.829153 <6>[ 2.509396] hub 2-1:1.0: USB hub found
10700 06:52:47.832185 <6>[ 2.513769] hub 2-1:1.0: 3 ports detected
10701 06:52:47.940967 <6>[ 2.617791] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10702 06:52:48.095868 <6>[ 2.775911] hub 1-1:1.0: USB hub found
10703 06:52:48.098813 <6>[ 2.780407] hub 1-1:1.0: 4 ports detected
10704 06:52:48.108934 <6>[ 2.789132] hub 1-1:1.0: USB hub found
10705 06:52:48.112337 <6>[ 2.793642] hub 1-1:1.0: 4 ports detected
10706 06:52:48.180665 <6>[ 2.858042] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10707 06:52:48.431754 <6>[ 3.109775] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10708 06:52:48.564514 <6>[ 3.245773] hub 1-1.4:1.0: USB hub found
10709 06:52:48.568030 <6>[ 3.250443] hub 1-1.4:1.0: 2 ports detected
10710 06:52:48.577696 <6>[ 3.258841] hub 1-1.4:1.0: USB hub found
10711 06:52:48.581006 <6>[ 3.263435] hub 1-1.4:1.0: 2 ports detected
10712 06:52:48.880065 <6>[ 3.557803] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10713 06:52:49.071580 <6>[ 3.749768] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10714 06:53:00.048964 <6>[ 14.734799] ALSA device list:
10715 06:53:00.055375 <6>[ 14.738094] No soundcards found.
10716 06:53:00.063526 <6>[ 14.746081] Freeing unused kernel memory: 8448K
10717 06:53:00.067248 <6>[ 14.751074] Run /init as init process
10718 06:53:00.078515 Loading, please wait...
10719 06:53:00.099119 Starting version 247.3-7+deb11u2
10720 06:53:00.277566 <6>[ 14.956853] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10721 06:53:00.286617 <6>[ 14.968964] remoteproc remoteproc0: scp is available
10722 06:53:00.293337 <6>[ 14.974473] remoteproc remoteproc0: powering up scp
10723 06:53:00.299505 <6>[ 14.979664] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10724 06:53:00.309008 <6>[ 14.991528] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10725 06:53:00.322675 <3>[ 15.001613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 06:53:00.329020 <3>[ 15.009763] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 06:53:00.339209 <3>[ 15.017892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 06:53:00.342394 <6>[ 15.018508] mc: Linux media interface: v0.10
10729 06:53:00.349177 <6>[ 15.018723] usbcore: registered new device driver r8152-cfgselector
10730 06:53:00.355510 <6>[ 15.026570] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10731 06:53:00.365776 <3>[ 15.031821] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 06:53:00.375233 <6>[ 15.037264] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10733 06:53:00.382008 <3>[ 15.045089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 06:53:00.392081 <6>[ 15.054104] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10735 06:53:00.398655 <3>[ 15.061719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 06:53:00.405262 <6>[ 15.081259] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10737 06:53:00.411805 <6>[ 15.081431] videodev: Linux video capture interface: v2.00
10738 06:53:00.421785 <3>[ 15.086334] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 06:53:00.428184 <3>[ 15.086340] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 06:53:00.434845 <4>[ 15.096556] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10741 06:53:00.444813 <3>[ 15.099783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 06:53:00.451558 <4>[ 15.114299] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10743 06:53:00.457863 <3>[ 15.116089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 06:53:00.467864 <6>[ 15.122557] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10745 06:53:00.474438 <6>[ 15.122561] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10746 06:53:00.481125 <6>[ 15.122568] remoteproc remoteproc0: remote processor scp is now up
10747 06:53:00.491353 <6>[ 15.156583] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10748 06:53:00.497733 <3>[ 15.162334] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 06:53:00.504143 <6>[ 15.171481] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10750 06:53:00.514294 <3>[ 15.176961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 06:53:00.520838 <6>[ 15.194859] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10752 06:53:00.527326 <3>[ 15.201399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 06:53:00.534062 <6>[ 15.208242] pci_bus 0000:00: root bus resource [bus 00-ff]
10754 06:53:00.543896 <3>[ 15.216328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 06:53:00.550525 <3>[ 15.216332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 06:53:00.560345 <3>[ 15.216337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 06:53:00.566777 <3>[ 15.216339] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 06:53:00.573619 <3>[ 15.216365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 06:53:00.583384 <6>[ 15.222308] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10760 06:53:00.589826 <6>[ 15.230372] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10761 06:53:00.600262 <6>[ 15.278199] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10762 06:53:00.609990 <6>[ 15.280603] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10763 06:53:00.616550 <6>[ 15.288191] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10764 06:53:00.626624 <6>[ 15.298051] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10765 06:53:00.633184 <6>[ 15.303713] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10766 06:53:00.639884 <6>[ 15.303793] pci 0000:00:00.0: supports D1 D2
10767 06:53:00.646574 <6>[ 15.314373] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10768 06:53:00.652896 <6>[ 15.321279] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10769 06:53:00.662995 <6>[ 15.322331] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10770 06:53:00.672673 <4>[ 15.329993] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10771 06:53:00.679266 <6>[ 15.335002] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10772 06:53:00.686137 <4>[ 15.341823] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10773 06:53:00.692503 <6>[ 15.350069] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10774 06:53:00.696021 <6>[ 15.350766] Bluetooth: Core ver 2.22
10775 06:53:00.702693 <6>[ 15.350882] NET: Registered PF_BLUETOOTH protocol family
10776 06:53:00.709255 <6>[ 15.350884] Bluetooth: HCI device and connection manager initialized
10777 06:53:00.715762 <6>[ 15.350916] Bluetooth: HCI socket layer initialized
10778 06:53:00.718943 <6>[ 15.350926] Bluetooth: L2CAP socket layer initialized
10779 06:53:00.726164 <6>[ 15.350942] Bluetooth: SCO socket layer initialized
10780 06:53:00.732561 <4>[ 15.352045] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10781 06:53:00.739423 <4>[ 15.352045] Fallback method does not support PEC.
10782 06:53:00.745921 <6>[ 15.366560] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10783 06:53:00.752667 <6>[ 15.373431] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10784 06:53:00.765840 <6>[ 15.382169] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10785 06:53:00.772249 <6>[ 15.384731] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10786 06:53:00.779651 <6>[ 15.390446] usbcore: registered new interface driver uvcvideo
10787 06:53:00.782847 <6>[ 15.396989] pci 0000:01:00.0: supports D1 D2
10788 06:53:00.789391 <6>[ 15.403209] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10789 06:53:00.796012 <6>[ 15.407312] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10790 06:53:00.802999 <6>[ 15.407716] usbcore: registered new interface driver btusb
10791 06:53:00.812957 <4>[ 15.408601] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10792 06:53:00.819741 <3>[ 15.408617] Bluetooth: hci0: Failed to load firmware file (-2)
10793 06:53:00.826266 <3>[ 15.408623] Bluetooth: hci0: Failed to set up firmware (-2)
10794 06:53:00.836362 <4>[ 15.408629] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10795 06:53:00.839565 <6>[ 15.413659] r8152 2-1.3:1.0 eth0: v1.12.13
10796 06:53:00.846519 <6>[ 15.437732] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10797 06:53:00.852973 <6>[ 15.440815] usbcore: registered new interface driver r8152
10798 06:53:00.859510 <6>[ 15.453107] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10799 06:53:00.869260 <6>[ 15.453111] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10800 06:53:00.876049 <6>[ 15.453120] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10801 06:53:00.886073 <6>[ 15.453133] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10802 06:53:00.892645 <6>[ 15.453145] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10803 06:53:00.899164 <6>[ 15.453158] pci 0000:00:00.0: PCI bridge to [bus 01]
10804 06:53:00.905656 <6>[ 15.453164] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10805 06:53:00.912325 <6>[ 15.453298] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10806 06:53:00.922330 <3>[ 15.464730] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10807 06:53:00.925467 <6>[ 15.467183] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10808 06:53:00.932053 <6>[ 15.471506] usbcore: registered new interface driver cdc_ether
10809 06:53:00.938764 <6>[ 15.478166] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10810 06:53:00.948646 <3>[ 15.493495] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10811 06:53:00.955297 <6>[ 15.501015] usbcore: registered new interface driver r8153_ecm
10812 06:53:00.962292 <5>[ 15.525816] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10813 06:53:00.968654 <6>[ 15.546627] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10814 06:53:00.975429 <5>[ 15.560163] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10815 06:53:00.984742 <5>[ 15.663183] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10816 06:53:00.998924 <4>[ 15.678095] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10817 06:53:01.005381 <6>[ 15.687003] cfg80211: failed to load regulatory.db
10818 06:53:01.041668 <6>[ 15.720771] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10819 06:53:01.047952 <6>[ 15.728270] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10820 06:53:01.072350 <6>[ 15.754895] mt7921e 0000:01:00.0: ASIC revision: 79610010
10821 06:53:01.173537 <6>[ 15.852745] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10822 06:53:01.176812 <6>[ 15.852745]
10823 06:53:01.180055 Begin: Loading essential drivers ... done.
10824 06:53:01.183301 Begin: Running /scripts/init-premount ... done.
10825 06:53:01.189829 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10826 06:53:01.199857 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10827 06:53:01.203022 Device /sys/class/net/enx0024323078ff found
10828 06:53:01.203125 done.
10829 06:53:01.262445 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10830 06:53:01.441588 <6>[ 16.120848] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10831 06:53:02.290662 <6>[ 16.973202] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10832 06:53:02.322987 <6>[ 17.005584] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10833 06:53:02.477174 IP-Config: no response after 2 secs - giving up
10834 06:53:02.506906 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10835 06:53:03.230257 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10836 06:53:03.233362 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10837 06:53:03.240061 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10838 06:53:03.250170 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10839 06:53:03.256595 host : mt8192-asurada-spherion-r0-cbg-8
10840 06:53:03.263095 domain : lava-rack
10841 06:53:03.266536 rootserver: 192.168.201.1 rootpath:
10842 06:53:03.266645 filename :
10843 06:53:03.369817 done.
10844 06:53:03.377256 Begin: Running /scripts/nfs-bottom ... done.
10845 06:53:03.401242 Begin: Running /scripts/init-bottom ... done.
10846 06:53:04.631883 <6>[ 19.314947] NET: Registered PF_INET6 protocol family
10847 06:53:04.639742 <6>[ 19.322692] Segment Routing with IPv6
10848 06:53:04.642876 <6>[ 19.326693] In-situ OAM (IOAM) with IPv6
10849 06:53:04.782145 <30>[ 19.445278] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10850 06:53:04.788418 <30>[ 19.469721] systemd[1]: Detected architecture arm64.
10851 06:53:04.808229
10852 06:53:04.811712 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10853 06:53:04.811819
10854 06:53:04.829536 <30>[ 19.512543] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10855 06:53:05.713594 <30>[ 20.393265] systemd[1]: Queued start job for default target Graphical Interface.
10856 06:53:05.753141 <30>[ 20.436169] systemd[1]: Created slice system-getty.slice.
10857 06:53:05.759686 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10858 06:53:05.776009 <30>[ 20.459186] systemd[1]: Created slice system-modprobe.slice.
10859 06:53:05.782555 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10860 06:53:05.800907 <30>[ 20.483920] systemd[1]: Created slice system-serial\x2dgetty.slice.
10861 06:53:05.810837 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10862 06:53:05.823683 <30>[ 20.506893] systemd[1]: Created slice User and Session Slice.
10863 06:53:05.830314 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10864 06:53:05.850973 <30>[ 20.530651] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10865 06:53:05.860708 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10866 06:53:05.878585 <30>[ 20.558480] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10867 06:53:05.885430 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10868 06:53:05.909897 <30>[ 20.586408] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10869 06:53:05.916750 <30>[ 20.598642] systemd[1]: Reached target Local Encrypted Volumes.
10870 06:53:05.923117 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10871 06:53:05.939249 <30>[ 20.622286] systemd[1]: Reached target Paths.
10872 06:53:05.942627 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10873 06:53:05.958863 <30>[ 20.641809] systemd[1]: Reached target Remote File Systems.
10874 06:53:05.965433 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10875 06:53:05.983216 <30>[ 20.666183] systemd[1]: Reached target Slices.
10876 06:53:05.989454 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10877 06:53:06.002645 <30>[ 20.685842] systemd[1]: Reached target Swap.
10878 06:53:06.005747 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10879 06:53:06.026616 <30>[ 20.706299] systemd[1]: Listening on initctl Compatibility Named Pipe.
10880 06:53:06.033087 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10881 06:53:06.039709 <30>[ 20.722444] systemd[1]: Listening on Journal Audit Socket.
10882 06:53:06.046219 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10883 06:53:06.063955 <30>[ 20.747106] systemd[1]: Listening on Journal Socket (/dev/log).
10884 06:53:06.070518 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10885 06:53:06.087140 <30>[ 20.770374] systemd[1]: Listening on Journal Socket.
10886 06:53:06.093970 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10887 06:53:06.111474 <30>[ 20.791291] systemd[1]: Listening on Network Service Netlink Socket.
10888 06:53:06.117930 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10889 06:53:06.133741 <30>[ 20.816709] systemd[1]: Listening on udev Control Socket.
10890 06:53:06.140380 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10891 06:53:06.155206 <30>[ 20.838241] systemd[1]: Listening on udev Kernel Socket.
10892 06:53:06.161930 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10893 06:53:06.211444 <30>[ 20.894286] systemd[1]: Mounting Huge Pages File System...
10894 06:53:06.217834 Mounting [0;1;39mHuge Pages File System[0m...
10895 06:53:06.232718 <30>[ 20.915946] systemd[1]: Mounting POSIX Message Queue File System...
10896 06:53:06.239735 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10897 06:53:06.258610 <30>[ 20.941554] systemd[1]: Mounting Kernel Debug File System...
10898 06:53:06.264887 Mounting [0;1;39mKernel Debug File System[0m...
10899 06:53:06.282577 <30>[ 20.962527] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10900 06:53:06.310922 <30>[ 20.990858] systemd[1]: Starting Create list of static device nodes for the current kernel...
10901 06:53:06.321013 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10902 06:53:06.379293 <30>[ 21.062554] systemd[1]: Starting Load Kernel Module configfs...
10903 06:53:06.386053 Starting [0;1;39mLoad Kernel Module configfs[0m...
10904 06:53:06.401441 <30>[ 21.084444] systemd[1]: Starting Load Kernel Module drm...
10905 06:53:06.407907 Starting [0;1;39mLoad Kernel Module drm[0m...
10906 06:53:06.427610 <30>[ 21.110576] systemd[1]: Starting Load Kernel Module fuse...
10907 06:53:06.434273 Starting [0;1;39mLoad Kernel Module fuse[0m...
10908 06:53:06.464989 <30>[ 21.144758] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10909 06:53:06.471919 <6>[ 21.154953] fuse: init (API version 7.37)
10910 06:53:06.499459 <30>[ 21.182612] systemd[1]: Starting Journal Service...
10911 06:53:06.502855 Starting [0;1;39mJournal Service[0m...
10912 06:53:06.529810 <30>[ 21.213104] systemd[1]: Starting Load Kernel Modules...
10913 06:53:06.536402 Starting [0;1;39mLoad Kernel Modules[0m...
10914 06:53:06.558849 <30>[ 21.238654] systemd[1]: Starting Remount Root and Kernel File Systems...
10915 06:53:06.565175 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10916 06:53:06.584133 <30>[ 21.267169] systemd[1]: Starting Coldplug All udev Devices...
10917 06:53:06.590459 Starting [0;1;39mColdplug All udev Devices[0m...
10918 06:53:06.610963 <30>[ 21.294105] systemd[1]: Mounted Huge Pages File System.
10919 06:53:06.617487 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10920 06:53:06.631558 <30>[ 21.314709] systemd[1]: Mounted POSIX Message Queue File System.
10921 06:53:06.638416 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10922 06:53:06.652668 <3>[ 21.332470] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 06:53:06.659195 <30>[ 21.341807] systemd[1]: Mounted Kernel Debug File System.
10924 06:53:06.665663 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10925 06:53:06.683057 <30>[ 21.362823] systemd[1]: Finished Create list of static device nodes for the current kernel.
10926 06:53:06.692998 <3>[ 21.365387] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 06:53:06.699732 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10928 06:53:06.715716 <30>[ 21.398847] systemd[1]: modprobe@configfs.service: Succeeded.
10929 06:53:06.723124 <30>[ 21.406023] systemd[1]: Finished Load Kernel Module configfs.
10930 06:53:06.733444 <3>[ 21.408253] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 06:53:06.739801 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10932 06:53:06.755941 <30>[ 21.438680] systemd[1]: modprobe@drm.service: Succeeded.
10933 06:53:06.762380 <30>[ 21.445382] systemd[1]: Finished Load Kernel Module drm.
10934 06:53:06.772306 <3>[ 21.446479] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 06:53:06.778862 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10936 06:53:06.796535 <30>[ 21.479383] systemd[1]: modprobe@fuse.service: Succeeded.
10937 06:53:06.806597 <3>[ 21.485426] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 06:53:06.813262 <30>[ 21.486450] systemd[1]: Finished Load Kernel Module fuse.
10939 06:53:06.819642 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10940 06:53:06.839431 <3>[ 21.519501] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 06:53:06.846670 <30>[ 21.519747] systemd[1]: Finished Load Kernel Modules.
10942 06:53:06.853026 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10943 06:53:06.872667 <30>[ 21.552389] systemd[1]: Finished Remount Root and Kernel File Systems.
10944 06:53:06.879127 <3>[ 21.553358] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 06:53:06.885610 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10946 06:53:06.916538 <3>[ 21.596534] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 06:53:06.952042 <3>[ 21.632114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 06:53:06.968642 <30>[ 21.651818] systemd[1]: Mounting FUSE Control File System...
10949 06:53:06.975467 Mounting [0;1;39mFUSE Control File System[0m...
10950 06:53:06.986467 <3>[ 21.666339] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 06:53:07.002503 <30>[ 21.682530] systemd[1]: Mounting Kernel Configuration File System...
10952 06:53:07.006034 Mounting [0;1;39mKernel Configuration File System[0m...
10953 06:53:07.034321 <30>[ 21.714195] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10954 06:53:07.044338 <30>[ 21.723261] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10955 06:53:07.075417 <30>[ 21.758768] systemd[1]: Starting Load/Save Random Seed...
10956 06:53:07.082089 Starting [0;1;39mLoad/Save Random Seed[0m...
10957 06:53:07.099377 <30>[ 21.782218] systemd[1]: Starting Apply Kernel Variables...
10958 06:53:07.106060 Starting [0;1;39mApply Kernel Variables[0m...
10959 06:53:07.123049 <30>[ 21.806272] systemd[1]: Starting Create System Users...
10960 06:53:07.129987 Starting [0;1;39mCreate System Users[0m...
10961 06:53:07.147694 <4>[ 21.821030] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10962 06:53:07.157661 <3>[ 21.837151] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10963 06:53:07.160973 <30>[ 21.839834] systemd[1]: Started Journal Service.
10964 06:53:07.167409 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10965 06:53:07.192110 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10966 06:53:07.206686 See 'systemctl status systemd-udev-trigger.service' for details.
10967 06:53:07.227302 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10968 06:53:07.243919 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10969 06:53:07.260544 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10970 06:53:07.276427 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10971 06:53:07.292311 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10972 06:53:07.335473 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10973 06:53:07.352493 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10974 06:53:07.391460 <46>[ 22.071416] systemd-journald[290]: Received client request to flush runtime journal.
10975 06:53:08.495682 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10976 06:53:08.511290 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10977 06:53:08.526782 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10978 06:53:08.574223 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10979 06:53:08.808660 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10980 06:53:08.855528 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10981 06:53:08.948669 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10982 06:53:09.012064 Starting [0;1;39mNetwork Service[0m...
10983 06:53:09.310470 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10984 06:53:09.337115 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10985 06:53:09.398008 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10986 06:53:09.709257 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10987 06:53:09.766439 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10988 06:53:09.791516 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10989 06:53:09.810649 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10990 06:53:09.834025 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10991 06:53:09.887174 Starting [0;1;39mNetwork Name Resolution[0m...
10992 06:53:09.916684 Starting [0;1;39mNetwork Time Synchronization[0m...
10993 06:53:09.933977 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10994 06:53:09.955871 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10995 06:53:10.003401 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10996 06:53:10.030941 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10997 06:53:10.384710 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10998 06:53:10.402641 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10999 06:53:10.421590 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11000 06:53:10.434351 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11001 06:53:10.450285 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11002 06:53:10.499699 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11003 06:53:10.520557 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11004 06:53:10.540495 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11005 06:53:10.560124 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11006 06:53:10.574000 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11007 06:53:10.595745 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11008 06:53:10.610213 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11009 06:53:10.626436 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11010 06:53:10.674369 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11011 06:53:10.774357 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11012 06:53:10.813568 Starting [0;1;39mUser Login Management[0m...
11013 06:53:10.827125 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11014 06:53:10.845429 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11015 06:53:10.861609 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11016 06:53:10.915346 Starting [0;1;39mPermit User Sessions[0m...
11017 06:53:11.023290 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11018 06:53:11.067326 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11019 06:53:11.123243 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11020 06:53:11.138550 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11021 06:53:11.161512 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11022 06:53:11.179297 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11023 06:53:11.196941 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11024 06:53:11.216265 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11025 06:53:11.263779 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11026 06:53:11.310222 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11027 06:53:11.398635
11028 06:53:11.398783
11029 06:53:11.401788 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11030 06:53:11.401865
11031 06:53:11.405356 debian-bullseye-arm64 login: root (automatic login)
11032 06:53:11.405457
11033 06:53:11.405565
11034 06:53:11.777676 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
11035 06:53:11.777838
11036 06:53:11.783975 The programs included with the Debian GNU/Linux system are free software;
11037 06:53:11.790851 the exact distribution terms for each program are described in the
11038 06:53:11.794174 individual files in /usr/share/doc/*/copyright.
11039 06:53:11.794283
11040 06:53:11.800652 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11041 06:53:11.803741 permitted by applicable law.
11042 06:53:12.821118 Matched prompt #10: / #
11044 06:53:12.822229 Setting prompt string to ['/ #']
11045 06:53:12.822636 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11047 06:53:12.823602 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11048 06:53:12.824016 start: 2.2.6 expect-shell-connection (timeout 00:03:16) [common]
11049 06:53:12.824341 Setting prompt string to ['/ #']
11050 06:53:12.824644 Forcing a shell prompt, looking for ['/ #']
11052 06:53:12.875428 / #
11053 06:53:12.876300 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11054 06:53:12.876796 Waiting using forced prompt support (timeout 00:02:30)
11055 06:53:12.881961
11056 06:53:12.882907 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11057 06:53:12.883458 start: 2.2.7 export-device-env (timeout 00:03:16) [common]
11059 06:53:12.984463 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694816/extract-nfsrootfs-_4ca9pq2'
11060 06:53:12.989317 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694816/extract-nfsrootfs-_4ca9pq2'
11062 06:53:13.089992 / # export NFS_SERVER_IP='192.168.201.1'
11063 06:53:13.095664 export NFS_SERVER_IP='192.168.201.1'
11064 06:53:13.096381 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11065 06:53:13.096757 end: 2.2 depthcharge-retry (duration 00:01:45) [common]
11066 06:53:13.097100 end: 2 depthcharge-action (duration 00:01:45) [common]
11067 06:53:13.097432 start: 3 lava-test-retry (timeout 00:07:34) [common]
11068 06:53:13.097771 start: 3.1 lava-test-shell (timeout 00:07:34) [common]
11069 06:53:13.098046 Using namespace: common
11071 06:53:13.198963 / # #
11072 06:53:13.199637 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11073 06:53:13.204869 #
11074 06:53:13.205646 Using /lava-12694816
11076 06:53:13.306771 / # export SHELL=/bin/bash
11077 06:53:13.312887 export SHELL=/bin/bash
11079 06:53:13.415093 / # . /lava-12694816/environment
11080 06:53:13.421237 . /lava-12694816/environment
11082 06:53:13.529723 / # /lava-12694816/bin/lava-test-runner /lava-12694816/0
11083 06:53:13.530333 Test shell timeout: 10s (minimum of the action and connection timeout)
11084 06:53:13.536173 /lava-12694816/bin/lava-test-runner /lava-12694816/0
11085 06:53:13.901950 + export TESTRUN_ID=0_timesync-off
11086 06:53:13.905030 + TESTRUN_ID=0_timesync-off
11087 06:53:13.908331 + cd /lava-12694816/0/tests/0_timesync-off
11088 06:53:13.911694 ++ cat uuid
11089 06:53:13.922152 + UUID=12694816_1.6.2.3.1
11090 06:53:13.922582 + set +x
11091 06:53:13.928913 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12694816_1.6.2.3.1>
11092 06:53:13.929616 Received signal: <STARTRUN> 0_timesync-off 12694816_1.6.2.3.1
11093 06:53:13.930021 Starting test lava.0_timesync-off (12694816_1.6.2.3.1)
11094 06:53:13.930460 Skipping test definition patterns.
11095 06:53:13.931920 + systemctl stop systemd-timesyncd
11096 06:53:14.014843 + set +x
11097 06:53:14.017975 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12694816_1.6.2.3.1>
11098 06:53:14.018662 Received signal: <ENDRUN> 0_timesync-off 12694816_1.6.2.3.1
11099 06:53:14.019084 Ending use of test pattern.
11100 06:53:14.019414 Ending test lava.0_timesync-off (12694816_1.6.2.3.1), duration 0.09
11102 06:53:14.129974 + export TESTRUN_ID=1_kselftest-tpm2
11103 06:53:14.133328 + TESTRUN_ID=1_kselftest-tpm2
11104 06:53:14.139686 + cd /lava-12694816/0/tests/1_kselftest-tpm2
11105 06:53:14.140122 ++ cat uuid
11106 06:53:14.151882 + UUID=12694816_1.6.2.3.5
11107 06:53:14.152465 + set +x
11108 06:53:14.158054 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12694816_1.6.2.3.5>
11109 06:53:14.158757 Received signal: <STARTRUN> 1_kselftest-tpm2 12694816_1.6.2.3.5
11110 06:53:14.159120 Starting test lava.1_kselftest-tpm2 (12694816_1.6.2.3.5)
11111 06:53:14.159558 Skipping test definition patterns.
11112 06:53:14.161401 + cd ./automated/linux/kselftest/
11113 06:53:14.187665 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11114 06:53:14.264023 INFO: install_deps skipped
11115 06:53:14.394871 --2024-02-03 06:53:14-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11116 06:53:14.410486 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11117 06:53:14.544720 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11118 06:53:14.678313 HTTP request sent, awaiting response... 200 OK
11119 06:53:14.681509 Length: 2965368 (2.8M) [application/octet-stream]
11120 06:53:14.684721 Saving to: 'kselftest.tar.xz'
11121 06:53:14.685340
11122 06:53:14.685830
11123 06:53:14.945163 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11124 06:53:15.212021 kselftest.tar.xz 1%[ ] 47.81K 180KB/s
11125 06:53:15.478023 kselftest.tar.xz 7%[> ] 217.50K 408KB/s
11126 06:53:15.678226 kselftest.tar.xz 30%[=====> ] 893.42K 1.09MB/s
11127 06:53:15.811512 kselftest.tar.xz 51%[=========> ] 1.46M 1.46MB/s
11128 06:53:15.818211 kselftest.tar.xz 100%[===================>] 2.83M 2.50MB/s in 1.1s
11129 06:53:15.818340
11130 06:53:16.076295 2024-02-03 06:53:16 (2.50 MB/s) - 'kselftest.tar.xz' saved [2965368/2965368]
11131 06:53:16.076808
11132 06:53:23.190959 skiplist:
11133 06:53:23.194402 ========================================
11134 06:53:23.197358 ========================================
11135 06:53:23.262912 tpm2:test_smoke.sh
11136 06:53:23.266126 tpm2:test_space.sh
11137 06:53:23.286158 ============== Tests to run ===============
11138 06:53:23.289444 tpm2:test_smoke.sh
11139 06:53:23.292955 tpm2:test_space.sh
11140 06:53:23.296183 ===========End Tests to run ===============
11141 06:53:23.299572 shardfile-tpm2 pass
11142 06:53:23.433613 <12>[ 38.118459] kselftest: Running tests in tpm2
11143 06:53:23.446291 TAP version 13
11144 06:53:23.462162 1..2
11145 06:53:23.504011 # selftests: tpm2: test_smoke.sh
11146 06:53:25.040434 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11147 06:53:25.043844 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11148 06:53:25.050283 # Exception ignored in: <function Client.__del__ at 0xffffb105bd30>
11149 06:53:25.053860 # Traceback (most recent call last):
11150 06:53:25.063860 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11151 06:53:25.067029 # if self.tpm:
11152 06:53:25.070101 # AttributeError: 'Client' object has no attribute 'tpm'
11153 06:53:25.077293 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11154 06:53:25.080501 # Exception ignored in: <function Client.__del__ at 0xffffb105bd30>
11155 06:53:25.083759 # Traceback (most recent call last):
11156 06:53:25.094004 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11157 06:53:25.097081 # if self.tpm:
11158 06:53:25.100525 # AttributeError: 'Client' object has no attribute 'tpm'
11159 06:53:25.106976 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11160 06:53:25.113793 # Exception ignored in: <function Client.__del__ at 0xffffb105bd30>
11161 06:53:25.116945 # Traceback (most recent call last):
11162 06:53:25.126956 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11163 06:53:25.127548 # if self.tpm:
11164 06:53:25.133275 # AttributeError: 'Client' object has no attribute 'tpm'
11165 06:53:25.136851 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11166 06:53:25.143407 # Exception ignored in: <function Client.__del__ at 0xffffb105bd30>
11167 06:53:25.146876 # Traceback (most recent call last):
11168 06:53:25.156693 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11169 06:53:25.160144 # if self.tpm:
11170 06:53:25.164223 # AttributeError: 'Client' object has no attribute 'tpm'
11171 06:53:25.167145 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11172 06:53:25.173567 # Exception ignored in: <function Client.__del__ at 0xffffb105bd30>
11173 06:53:25.176686 # Traceback (most recent call last):
11174 06:53:25.186795 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11175 06:53:25.190103 # if self.tpm:
11176 06:53:25.193548 # AttributeError: 'Client' object has no attribute 'tpm'
11177 06:53:25.200103 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11178 06:53:25.203632 # Exception ignored in: <function Client.__del__ at 0xffffb105bd30>
11179 06:53:25.206510 # Traceback (most recent call last):
11180 06:53:25.216586 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11181 06:53:25.219922 # if self.tpm:
11182 06:53:25.223261 # AttributeError: 'Client' object has no attribute 'tpm'
11183 06:53:25.229842 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11184 06:53:25.236511 # Exception ignored in: <function Client.__del__ at 0xffffb105bd30>
11185 06:53:25.240153 # Traceback (most recent call last):
11186 06:53:25.249684 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11187 06:53:25.250255 # if self.tpm:
11188 06:53:25.256442 # AttributeError: 'Client' object has no attribute 'tpm'
11189 06:53:25.263126 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11190 06:53:25.266294 # Exception ignored in: <function Client.__del__ at 0xffffb105bd30>
11191 06:53:25.269668 # Traceback (most recent call last):
11192 06:53:25.279734 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11193 06:53:25.282954 # if self.tpm:
11194 06:53:25.286241 # AttributeError: 'Client' object has no attribute 'tpm'
11195 06:53:25.289587 #
11196 06:53:25.293067 # ======================================================================
11197 06:53:25.299517 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11198 06:53:25.306039 # ----------------------------------------------------------------------
11199 06:53:25.309709 # Traceback (most recent call last):
11200 06:53:25.320034 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11201 06:53:25.323325 # self.root_key = self.client.create_root_key()
11202 06:53:25.336434 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11203 06:53:25.339864 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11204 06:53:25.350041 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11205 06:53:25.353130 # raise ProtocolError(cc, rc)
11206 06:53:25.359626 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11207 06:53:25.360205 #
11208 06:53:25.366396 # ======================================================================
11209 06:53:25.369704 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11210 06:53:25.376414 # ----------------------------------------------------------------------
11211 06:53:25.379997 # Traceback (most recent call last):
11212 06:53:25.390840 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11213 06:53:25.394172 # self.client = tpm2.Client()
11214 06:53:25.404264 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11215 06:53:25.408039 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11216 06:53:25.414411 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11217 06:53:25.414984 #
11218 06:53:25.421079 # ======================================================================
11219 06:53:25.424076 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11220 06:53:25.430709 # ----------------------------------------------------------------------
11221 06:53:25.434070 # Traceback (most recent call last):
11222 06:53:25.443767 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11223 06:53:25.447079 # self.client = tpm2.Client()
11224 06:53:25.457147 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11225 06:53:25.463608 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11226 06:53:25.467018 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11227 06:53:25.467456 #
11228 06:53:25.473584 # ======================================================================
11229 06:53:25.480412 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11230 06:53:25.487077 # ----------------------------------------------------------------------
11231 06:53:25.490347 # Traceback (most recent call last):
11232 06:53:25.500305 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11233 06:53:25.503587 # self.client = tpm2.Client()
11234 06:53:25.513439 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11235 06:53:25.516754 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11236 06:53:25.523431 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11237 06:53:25.523885 #
11238 06:53:25.530103 # ======================================================================
11239 06:53:25.533472 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11240 06:53:25.539974 # ----------------------------------------------------------------------
11241 06:53:25.543028 # Traceback (most recent call last):
11242 06:53:25.553425 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11243 06:53:25.556512 # self.client = tpm2.Client()
11244 06:53:25.566598 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11245 06:53:25.573064 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11246 06:53:25.576671 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11247 06:53:25.577111 #
11248 06:53:25.583245 # ======================================================================
11249 06:53:25.586808 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11250 06:53:25.593280 # ----------------------------------------------------------------------
11251 06:53:25.596586 # Traceback (most recent call last):
11252 06:53:25.607117 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11253 06:53:25.610194 # self.client = tpm2.Client()
11254 06:53:25.619992 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11255 06:53:25.626607 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11256 06:53:25.629868 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11257 06:53:25.630301 #
11258 06:53:25.636755 # ======================================================================
11259 06:53:25.643283 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11260 06:53:25.649724 # ----------------------------------------------------------------------
11261 06:53:25.653426 # Traceback (most recent call last):
11262 06:53:25.663311 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11263 06:53:25.666317 # self.client = tpm2.Client()
11264 06:53:25.676457 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11265 06:53:25.679908 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11266 06:53:25.686405 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11267 06:53:25.686950 #
11268 06:53:25.692940 # ======================================================================
11269 06:53:25.696347 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11270 06:53:25.703184 # ----------------------------------------------------------------------
11271 06:53:25.706714 # Traceback (most recent call last):
11272 06:53:25.716836 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11273 06:53:25.719822 # self.client = tpm2.Client()
11274 06:53:25.729678 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11275 06:53:25.736164 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11276 06:53:25.739782 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11277 06:53:25.740331 #
11278 06:53:25.746313 # ======================================================================
11279 06:53:25.753187 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11280 06:53:25.759542 # ----------------------------------------------------------------------
11281 06:53:25.762751 # Traceback (most recent call last):
11282 06:53:25.772662 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11283 06:53:25.775934 # self.client = tpm2.Client()
11284 06:53:25.783507 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11285 06:53:25.790315 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11286 06:53:25.794141 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11287 06:53:25.794576 #
11288 06:53:25.803979 # ----------------------------------------------------------------------
11289 06:53:25.804503 # Ran 9 tests in 0.044s
11290 06:53:25.804847 #
11291 06:53:25.807933 # FAILED (errors=9)
11292 06:53:25.811788 # test_async (tpm2_tests.AsyncTest) ... ok
11293 06:53:25.817772 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11294 06:53:25.818299 #
11295 06:53:25.821260 # ----------------------------------------------------------------------
11296 06:53:25.825067 # Ran 2 tests in 0.031s
11297 06:53:25.825647 #
11298 06:53:25.825995 # OK
11299 06:53:25.828122 ok 1 selftests: tpm2: test_smoke.sh
11300 06:53:25.834861 # selftests: tpm2: test_space.sh
11301 06:53:25.838285 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11302 06:53:25.841452 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11303 06:53:25.845297 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11304 06:53:25.851727 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11305 06:53:25.852257 #
11306 06:53:25.858306 # ======================================================================
11307 06:53:25.861981 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11308 06:53:25.868390 # ----------------------------------------------------------------------
11309 06:53:25.871387 # Traceback (most recent call last):
11310 06:53:25.881638 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11311 06:53:25.885096 # root1 = space1.create_root_key()
11312 06:53:25.895085 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11313 06:53:25.901618 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11314 06:53:25.911221 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11315 06:53:25.914511 # raise ProtocolError(cc, rc)
11316 06:53:25.921365 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11317 06:53:25.921841 #
11318 06:53:25.927599 # ======================================================================
11319 06:53:25.931018 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11320 06:53:25.937570 # ----------------------------------------------------------------------
11321 06:53:25.941280 # Traceback (most recent call last):
11322 06:53:25.950998 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11323 06:53:25.954496 # space1.create_root_key()
11324 06:53:25.964427 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11325 06:53:25.970905 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11326 06:53:25.980836 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11327 06:53:25.984208 # raise ProtocolError(cc, rc)
11328 06:53:25.990685 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11329 06:53:25.991211 #
11330 06:53:25.997214 # ======================================================================
11331 06:53:26.000687 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11332 06:53:26.007526 # ----------------------------------------------------------------------
11333 06:53:26.011162 # Traceback (most recent call last):
11334 06:53:26.020779 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11335 06:53:26.027208 # root1 = space1.create_root_key()
11336 06:53:26.037084 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11337 06:53:26.040874 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11338 06:53:26.050238 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11339 06:53:26.053582 # raise ProtocolError(cc, rc)
11340 06:53:26.060394 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11341 06:53:26.060930 #
11342 06:53:26.067278 # ======================================================================
11343 06:53:26.073588 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11344 06:53:26.077125 # ----------------------------------------------------------------------
11345 06:53:26.080320 # Traceback (most recent call last):
11346 06:53:26.093702 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11347 06:53:26.097141 # root1 = space1.create_root_key()
11348 06:53:26.106974 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11349 06:53:26.113530 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11350 06:53:26.123249 # File "/lava-12694816/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11351 06:53:26.126604 # raise ProtocolError(cc, rc)
11352 06:53:26.133413 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11353 06:53:26.133893 #
11354 06:53:26.139888 # ----------------------------------------------------------------------
11355 06:53:26.140472 # Ran 4 tests in 0.065s
11356 06:53:26.140964 #
11357 06:53:26.143314 # FAILED (errors=4)
11358 06:53:26.146396 not ok 2 selftests: tpm2: test_space.sh # exit=1
11359 06:53:26.150197 tpm2_test_smoke_sh pass
11360 06:53:26.150625 tpm2_test_space_sh fail
11361 06:53:26.156856 + ../../utils/send-to-lava.sh ./output/result.txt
11362 06:53:26.160102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11363 06:53:26.160875 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11365 06:53:26.230787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11366 06:53:26.231526 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11368 06:53:26.302398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11369 06:53:26.303116 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11371 06:53:26.305672 + set +x
11372 06:53:26.309061 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12694816_1.6.2.3.5>
11373 06:53:26.309797 Received signal: <ENDRUN> 1_kselftest-tpm2 12694816_1.6.2.3.5
11374 06:53:26.310218 Ending use of test pattern.
11375 06:53:26.310634 Ending test lava.1_kselftest-tpm2 (12694816_1.6.2.3.5), duration 12.15
11377 06:53:26.312115 <LAVA_TEST_RUNNER EXIT>
11378 06:53:26.312762 ok: lava_test_shell seems to have completed
11379 06:53:26.313461 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11380 06:53:26.314003 end: 3.1 lava-test-shell (duration 00:00:13) [common]
11381 06:53:26.314507 end: 3 lava-test-retry (duration 00:00:13) [common]
11382 06:53:26.315069 start: 4 finalize (timeout 00:07:21) [common]
11383 06:53:26.315616 start: 4.1 power-off (timeout 00:00:30) [common]
11384 06:53:26.316459 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11385 06:53:26.437877 >> Command sent successfully.
11386 06:53:26.441801 Returned 0 in 0 seconds
11387 06:53:26.542717 end: 4.1 power-off (duration 00:00:00) [common]
11389 06:53:26.544655 start: 4.2 read-feedback (timeout 00:07:20) [common]
11390 06:53:26.546013 Listened to connection for namespace 'common' for up to 1s
11391 06:53:27.545799 Finalising connection for namespace 'common'
11392 06:53:27.546516 Disconnecting from shell: Finalise
11393 06:53:27.547013 / #
11394 06:53:27.647976 end: 4.2 read-feedback (duration 00:00:01) [common]
11395 06:53:27.648639 end: 4 finalize (duration 00:00:01) [common]
11396 06:53:27.649199 Cleaning after the job
11397 06:53:27.649753 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/ramdisk
11398 06:53:27.663065 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/kernel
11399 06:53:27.695931 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/dtb
11400 06:53:27.696218 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/nfsrootfs
11401 06:53:27.787769 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694816/tftp-deploy-t9mq3kaq/modules
11402 06:53:27.795060 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694816
11403 06:53:28.430324 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694816
11404 06:53:28.430511 Job finished correctly