Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 37
1 06:56:01.880039 lava-dispatcher, installed at version: 2023.10
2 06:56:01.880261 start: 0 validate
3 06:56:01.880433 Start time: 2024-02-03 06:56:01.880426+00:00 (UTC)
4 06:56:01.880553 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:56:01.880685 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 06:56:02.154331 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:56:02.155014 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:56:02.423675 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:56:02.424400 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:56:02.694082 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:56:02.694844 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:56:02.965571 Using caching service: 'http://localhost/cache/?uri=%s'
13 06:56:02.966267 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 06:56:03.240334 validate duration: 1.36
16 06:56:03.240606 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:56:03.240705 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:56:03.240789 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:56:03.240911 Not decompressing ramdisk as can be used compressed.
20 06:56:03.240995 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 06:56:03.241060 saving as /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/ramdisk/initrd.cpio.gz
22 06:56:03.241123 total size: 4665398 (4 MB)
23 06:56:03.243078 progress 0 % (0 MB)
24 06:56:03.244668 progress 5 % (0 MB)
25 06:56:03.246025 progress 10 % (0 MB)
26 06:56:03.247363 progress 15 % (0 MB)
27 06:56:03.248702 progress 20 % (0 MB)
28 06:56:03.250020 progress 25 % (1 MB)
29 06:56:03.251330 progress 30 % (1 MB)
30 06:56:03.252665 progress 35 % (1 MB)
31 06:56:03.253975 progress 40 % (1 MB)
32 06:56:03.255452 progress 45 % (2 MB)
33 06:56:03.256768 progress 50 % (2 MB)
34 06:56:03.258091 progress 55 % (2 MB)
35 06:56:03.259432 progress 60 % (2 MB)
36 06:56:03.260770 progress 65 % (2 MB)
37 06:56:03.262073 progress 70 % (3 MB)
38 06:56:03.263433 progress 75 % (3 MB)
39 06:56:03.264773 progress 80 % (3 MB)
40 06:56:03.266279 progress 85 % (3 MB)
41 06:56:03.267587 progress 90 % (4 MB)
42 06:56:03.268907 progress 95 % (4 MB)
43 06:56:03.270204 progress 100 % (4 MB)
44 06:56:03.270356 4 MB downloaded in 0.03 s (152.20 MB/s)
45 06:56:03.270510 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:56:03.270743 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:56:03.270827 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:56:03.270908 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:56:03.271050 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 06:56:03.271117 saving as /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/kernel/Image
52 06:56:03.271176 total size: 51532288 (49 MB)
53 06:56:03.271236 No compression specified
54 06:56:03.272339 progress 0 % (0 MB)
55 06:56:03.285640 progress 5 % (2 MB)
56 06:56:03.299187 progress 10 % (4 MB)
57 06:56:03.312512 progress 15 % (7 MB)
58 06:56:03.326083 progress 20 % (9 MB)
59 06:56:03.340060 progress 25 % (12 MB)
60 06:56:03.354116 progress 30 % (14 MB)
61 06:56:03.368666 progress 35 % (17 MB)
62 06:56:03.383974 progress 40 % (19 MB)
63 06:56:03.399210 progress 45 % (22 MB)
64 06:56:03.414166 progress 50 % (24 MB)
65 06:56:03.427493 progress 55 % (27 MB)
66 06:56:03.440912 progress 60 % (29 MB)
67 06:56:03.454304 progress 65 % (31 MB)
68 06:56:03.467704 progress 70 % (34 MB)
69 06:56:03.481228 progress 75 % (36 MB)
70 06:56:03.494883 progress 80 % (39 MB)
71 06:56:03.508178 progress 85 % (41 MB)
72 06:56:03.521580 progress 90 % (44 MB)
73 06:56:03.534835 progress 95 % (46 MB)
74 06:56:03.547836 progress 100 % (49 MB)
75 06:56:03.548085 49 MB downloaded in 0.28 s (177.48 MB/s)
76 06:56:03.548248 end: 1.2.1 http-download (duration 00:00:00) [common]
78 06:56:03.548533 end: 1.2 download-retry (duration 00:00:00) [common]
79 06:56:03.548622 start: 1.3 download-retry (timeout 00:10:00) [common]
80 06:56:03.548705 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 06:56:03.548836 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 06:56:03.548906 saving as /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/dtb/mt8192-asurada-spherion-r0.dtb
83 06:56:03.548964 total size: 47278 (0 MB)
84 06:56:03.549023 No compression specified
85 06:56:03.550133 progress 69 % (0 MB)
86 06:56:03.550405 progress 100 % (0 MB)
87 06:56:03.550561 0 MB downloaded in 0.00 s (28.28 MB/s)
88 06:56:03.550681 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:56:03.550897 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:56:03.550982 start: 1.4 download-retry (timeout 00:10:00) [common]
92 06:56:03.551063 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 06:56:03.551175 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 06:56:03.551241 saving as /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/nfsrootfs/full.rootfs.tar
95 06:56:03.551301 total size: 89451516 (85 MB)
96 06:56:03.551361 Using unxz to decompress xz
97 06:56:03.556408 progress 0 % (0 MB)
98 06:56:03.773915 progress 5 % (4 MB)
99 06:56:03.996420 progress 10 % (8 MB)
100 06:56:04.259303 progress 15 % (12 MB)
101 06:56:04.462051 progress 20 % (17 MB)
102 06:56:04.562892 progress 25 % (21 MB)
103 06:56:04.812903 progress 30 % (25 MB)
104 06:56:05.096149 progress 35 % (29 MB)
105 06:56:05.355848 progress 40 % (34 MB)
106 06:56:05.617375 progress 45 % (38 MB)
107 06:56:05.862939 progress 50 % (42 MB)
108 06:56:06.123433 progress 55 % (46 MB)
109 06:56:06.381282 progress 60 % (51 MB)
110 06:56:06.654972 progress 65 % (55 MB)
111 06:56:06.955076 progress 70 % (59 MB)
112 06:56:07.260784 progress 75 % (64 MB)
113 06:56:07.559800 progress 80 % (68 MB)
114 06:56:07.821591 progress 85 % (72 MB)
115 06:56:08.046937 progress 90 % (76 MB)
116 06:56:08.308967 progress 95 % (81 MB)
117 06:56:08.578492 progress 100 % (85 MB)
118 06:56:08.584912 85 MB downloaded in 5.03 s (16.95 MB/s)
119 06:56:08.585172 end: 1.4.1 http-download (duration 00:00:05) [common]
121 06:56:08.585433 end: 1.4 download-retry (duration 00:00:05) [common]
122 06:56:08.585522 start: 1.5 download-retry (timeout 00:09:55) [common]
123 06:56:08.585609 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 06:56:08.585764 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 06:56:08.585832 saving as /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/modules/modules.tar
126 06:56:08.585892 total size: 8624064 (8 MB)
127 06:56:08.585952 Using unxz to decompress xz
128 06:56:08.590104 progress 0 % (0 MB)
129 06:56:08.611124 progress 5 % (0 MB)
130 06:56:08.634637 progress 10 % (0 MB)
131 06:56:08.658040 progress 15 % (1 MB)
132 06:56:08.681562 progress 20 % (1 MB)
133 06:56:08.706056 progress 25 % (2 MB)
134 06:56:08.731756 progress 30 % (2 MB)
135 06:56:08.757639 progress 35 % (2 MB)
136 06:56:08.780913 progress 40 % (3 MB)
137 06:56:08.804963 progress 45 % (3 MB)
138 06:56:08.830292 progress 50 % (4 MB)
139 06:56:08.854535 progress 55 % (4 MB)
140 06:56:08.879200 progress 60 % (4 MB)
141 06:56:08.906405 progress 65 % (5 MB)
142 06:56:08.931355 progress 70 % (5 MB)
143 06:56:08.954427 progress 75 % (6 MB)
144 06:56:08.981320 progress 80 % (6 MB)
145 06:56:09.006595 progress 85 % (7 MB)
146 06:56:09.031464 progress 90 % (7 MB)
147 06:56:09.062623 progress 95 % (7 MB)
148 06:56:09.090579 progress 100 % (8 MB)
149 06:56:09.095432 8 MB downloaded in 0.51 s (16.14 MB/s)
150 06:56:09.095694 end: 1.5.1 http-download (duration 00:00:01) [common]
152 06:56:09.095954 end: 1.5 download-retry (duration 00:00:01) [common]
153 06:56:09.096045 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 06:56:09.096142 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 06:56:10.820737 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12694854/extract-nfsrootfs-u46__al4
156 06:56:10.820929 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 06:56:10.821028 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 06:56:10.821186 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed
159 06:56:10.821316 makedir: /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin
160 06:56:10.821418 makedir: /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/tests
161 06:56:10.821515 makedir: /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/results
162 06:56:10.821614 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-add-keys
163 06:56:10.821755 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-add-sources
164 06:56:10.821883 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-background-process-start
165 06:56:10.822009 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-background-process-stop
166 06:56:10.822134 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-common-functions
167 06:56:10.822258 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-echo-ipv4
168 06:56:10.822381 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-install-packages
169 06:56:10.822503 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-installed-packages
170 06:56:10.822624 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-os-build
171 06:56:10.822746 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-probe-channel
172 06:56:10.822868 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-probe-ip
173 06:56:10.822990 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-target-ip
174 06:56:10.823111 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-target-mac
175 06:56:10.823232 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-target-storage
176 06:56:10.823354 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-test-case
177 06:56:10.823479 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-test-event
178 06:56:10.823600 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-test-feedback
179 06:56:10.823723 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-test-raise
180 06:56:10.823844 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-test-reference
181 06:56:10.823967 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-test-runner
182 06:56:10.824090 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-test-set
183 06:56:10.824214 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-test-shell
184 06:56:10.824400 Updating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-install-packages (oe)
185 06:56:10.824555 Updating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/bin/lava-installed-packages (oe)
186 06:56:10.824704 Creating /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/environment
187 06:56:10.824815 LAVA metadata
188 06:56:10.824885 - LAVA_JOB_ID=12694854
189 06:56:10.824951 - LAVA_DISPATCHER_IP=192.168.201.1
190 06:56:10.825049 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 06:56:10.825115 skipped lava-vland-overlay
192 06:56:10.825187 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 06:56:10.825277 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 06:56:10.825337 skipped lava-multinode-overlay
195 06:56:10.825408 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 06:56:10.825484 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 06:56:10.825555 Loading test definitions
198 06:56:10.825642 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 06:56:10.825710 Using /lava-12694854 at stage 0
200 06:56:10.826008 uuid=12694854_1.6.2.3.1 testdef=None
201 06:56:10.826094 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 06:56:10.826176 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 06:56:10.826657 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 06:56:10.826870 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 06:56:10.827468 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 06:56:10.827689 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 06:56:10.828407 runner path: /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/0/tests/0_lc-compliance test_uuid 12694854_1.6.2.3.1
210 06:56:10.828572 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 06:56:10.828770 Creating lava-test-runner.conf files
213 06:56:10.828832 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694854/lava-overlay-6k0jkxed/lava-12694854/0 for stage 0
214 06:56:10.828920 - 0_lc-compliance
215 06:56:10.829013 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 06:56:10.829095 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 06:56:10.834897 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 06:56:10.834995 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 06:56:10.835076 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 06:56:10.835156 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 06:56:10.835238 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 06:56:10.955803 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 06:56:10.956192 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 06:56:10.956310 extracting modules file /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694854/extract-nfsrootfs-u46__al4
225 06:56:11.176947 extracting modules file /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694854/extract-overlay-ramdisk-417_wqx5/ramdisk
226 06:56:11.402700 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 06:56:11.402869 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 06:56:11.402959 [common] Applying overlay to NFS
229 06:56:11.403039 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694854/compress-overlay-ytyqs_2v/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694854/extract-nfsrootfs-u46__al4
230 06:56:11.409482 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 06:56:11.409585 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 06:56:11.409673 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 06:56:11.409760 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 06:56:11.409836 Building ramdisk /var/lib/lava/dispatcher/tmp/12694854/extract-overlay-ramdisk-417_wqx5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694854/extract-overlay-ramdisk-417_wqx5/ramdisk
235 06:56:11.757152 >> 119430 blocks
236 06:56:13.719717 rename /var/lib/lava/dispatcher/tmp/12694854/extract-overlay-ramdisk-417_wqx5/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/ramdisk/ramdisk.cpio.gz
237 06:56:13.720179 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 06:56:13.720329 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 06:56:13.720444 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 06:56:13.720547 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/kernel/Image'
241 06:56:26.198719 Returned 0 in 12 seconds
242 06:56:26.299344 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/kernel/image.itb
243 06:56:26.717955 output: FIT description: Kernel Image image with one or more FDT blobs
244 06:56:26.718361 output: Created: Sat Feb 3 06:56:26 2024
245 06:56:26.718469 output: Image 0 (kernel-1)
246 06:56:26.718560 output: Description:
247 06:56:26.718655 output: Created: Sat Feb 3 06:56:26 2024
248 06:56:26.718718 output: Type: Kernel Image
249 06:56:26.718777 output: Compression: lzma compressed
250 06:56:26.718838 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
251 06:56:26.718899 output: Architecture: AArch64
252 06:56:26.718962 output: OS: Linux
253 06:56:26.719021 output: Load Address: 0x00000000
254 06:56:26.719076 output: Entry Point: 0x00000000
255 06:56:26.719133 output: Hash algo: crc32
256 06:56:26.719190 output: Hash value: 380e7c3c
257 06:56:26.719246 output: Image 1 (fdt-1)
258 06:56:26.719332 output: Description: mt8192-asurada-spherion-r0
259 06:56:26.719415 output: Created: Sat Feb 3 06:56:26 2024
260 06:56:26.719497 output: Type: Flat Device Tree
261 06:56:26.719583 output: Compression: uncompressed
262 06:56:26.719665 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 06:56:26.719747 output: Architecture: AArch64
264 06:56:26.719828 output: Hash algo: crc32
265 06:56:26.719913 output: Hash value: cc4352de
266 06:56:26.719994 output: Image 2 (ramdisk-1)
267 06:56:26.720076 output: Description: unavailable
268 06:56:26.720159 output: Created: Sat Feb 3 06:56:26 2024
269 06:56:26.720242 output: Type: RAMDisk Image
270 06:56:26.720333 output: Compression: Unknown Compression
271 06:56:26.720416 output: Data Size: 17800812 Bytes = 17383.61 KiB = 16.98 MiB
272 06:56:26.720501 output: Architecture: AArch64
273 06:56:26.720582 output: OS: Linux
274 06:56:26.720708 output: Load Address: unavailable
275 06:56:26.720783 output: Entry Point: unavailable
276 06:56:26.720836 output: Hash algo: crc32
277 06:56:26.720888 output: Hash value: fba36619
278 06:56:26.720940 output: Default Configuration: 'conf-1'
279 06:56:26.720992 output: Configuration 0 (conf-1)
280 06:56:26.721050 output: Description: mt8192-asurada-spherion-r0
281 06:56:26.721104 output: Kernel: kernel-1
282 06:56:26.721156 output: Init Ramdisk: ramdisk-1
283 06:56:26.721208 output: FDT: fdt-1
284 06:56:26.721259 output: Loadables: kernel-1
285 06:56:26.721314 output:
286 06:56:26.721553 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 06:56:26.721681 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 06:56:26.721796 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 06:56:26.721893 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 06:56:26.721976 No LXC device requested
291 06:56:26.722058 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 06:56:26.722142 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 06:56:26.722227 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 06:56:26.722298 Checking files for TFTP limit of 4294967296 bytes.
295 06:56:26.722803 end: 1 tftp-deploy (duration 00:00:23) [common]
296 06:56:26.722935 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 06:56:26.723070 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 06:56:26.723245 substitutions:
299 06:56:26.723339 - {DTB}: 12694854/tftp-deploy-w1pzfpjm/dtb/mt8192-asurada-spherion-r0.dtb
300 06:56:26.723407 - {INITRD}: 12694854/tftp-deploy-w1pzfpjm/ramdisk/ramdisk.cpio.gz
301 06:56:26.723467 - {KERNEL}: 12694854/tftp-deploy-w1pzfpjm/kernel/Image
302 06:56:26.723527 - {LAVA_MAC}: None
303 06:56:26.723588 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12694854/extract-nfsrootfs-u46__al4
304 06:56:26.723644 - {NFS_SERVER_IP}: 192.168.201.1
305 06:56:26.723699 - {PRESEED_CONFIG}: None
306 06:56:26.723753 - {PRESEED_LOCAL}: None
307 06:56:26.723812 - {RAMDISK}: 12694854/tftp-deploy-w1pzfpjm/ramdisk/ramdisk.cpio.gz
308 06:56:26.723866 - {ROOT_PART}: None
309 06:56:26.723919 - {ROOT}: None
310 06:56:26.723973 - {SERVER_IP}: 192.168.201.1
311 06:56:26.724029 - {TEE}: None
312 06:56:26.724113 Parsed boot commands:
313 06:56:26.724197 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 06:56:26.724434 Parsed boot commands: tftpboot 192.168.201.1 12694854/tftp-deploy-w1pzfpjm/kernel/image.itb 12694854/tftp-deploy-w1pzfpjm/kernel/cmdline
315 06:56:26.724552 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 06:56:26.724669 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 06:56:26.724790 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 06:56:26.724909 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 06:56:26.725008 Not connected, no need to disconnect.
320 06:56:26.725115 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 06:56:26.725225 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 06:56:26.725321 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
323 06:56:26.729468 Setting prompt string to ['lava-test: # ']
324 06:56:26.729835 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 06:56:26.729972 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 06:56:26.730103 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 06:56:26.730237 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 06:56:26.730578 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
329 06:56:31.879124 >> Command sent successfully.
330 06:56:31.891397 Returned 0 in 5 seconds
331 06:56:31.992755 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 06:56:31.994402 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 06:56:31.995175 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 06:56:31.995793 Setting prompt string to 'Starting depthcharge on Spherion...'
336 06:56:31.996425 Changing prompt to 'Starting depthcharge on Spherion...'
337 06:56:31.996945 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 06:56:31.998534 [Enter `^Ec?' for help]
339 06:56:32.153468
340 06:56:32.153607
341 06:56:32.153680 F0: 102B 0000
342 06:56:32.153751
343 06:56:32.153812 F3: 1001 0000 [0200]
344 06:56:32.153871
345 06:56:32.157880 F3: 1001 0000
346 06:56:32.157954
347 06:56:32.158014 F7: 102D 0000
348 06:56:32.158072
349 06:56:32.158156 F1: 0000 0000
350 06:56:32.158242
351 06:56:32.160988 V0: 0000 0000 [0001]
352 06:56:32.161065
353 06:56:32.161126 00: 0007 8000
354 06:56:32.161187
355 06:56:32.164934 01: 0000 0000
356 06:56:32.165034
357 06:56:32.165126 BP: 0C00 0209 [0000]
358 06:56:32.165216
359 06:56:32.168627 G0: 1182 0000
360 06:56:32.168726
361 06:56:32.168814 EC: 0000 0021 [4000]
362 06:56:32.168900
363 06:56:32.172304 S7: 0000 0000 [0000]
364 06:56:32.172413
365 06:56:32.172500 CC: 0000 0000 [0001]
366 06:56:32.172589
367 06:56:32.175355 T0: 0000 0040 [010F]
368 06:56:32.175424
369 06:56:32.175483 Jump to BL
370 06:56:32.175538
371 06:56:32.200875
372 06:56:32.200998
373 06:56:32.201096
374 06:56:32.208118 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 06:56:32.211905 ARM64: Exception handlers installed.
376 06:56:32.215544 ARM64: Testing exception
377 06:56:32.219614 ARM64: Done test exception
378 06:56:32.223205 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 06:56:32.234926 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 06:56:32.241922 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 06:56:32.251631 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 06:56:32.258402 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 06:56:32.268362 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 06:56:32.278887 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 06:56:32.285398 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 06:56:32.303700 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 06:56:32.307057 WDT: Last reset was cold boot
388 06:56:32.310272 SPI1(PAD0) initialized at 2873684 Hz
389 06:56:32.313424 SPI5(PAD0) initialized at 992727 Hz
390 06:56:32.316631 VBOOT: Loading verstage.
391 06:56:32.323672 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 06:56:32.327631 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 06:56:32.330822 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 06:56:32.333990 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 06:56:32.341171 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 06:56:32.347802 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 06:56:32.358196 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 06:56:32.358275
399 06:56:32.358340
400 06:56:32.369488 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 06:56:32.372452 ARM64: Exception handlers installed.
402 06:56:32.372532 ARM64: Testing exception
403 06:56:32.376267 ARM64: Done test exception
404 06:56:32.379065 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 06:56:32.385995 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 06:56:32.399820 Probing TPM: . done!
407 06:56:32.399924 TPM ready after 0 ms
408 06:56:32.407063 Connected to device vid:did:rid of 1ae0:0028:00
409 06:56:32.413723 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 06:56:32.473256 Initialized TPM device CR50 revision 0
411 06:56:32.484762 tlcl_send_startup: Startup return code is 0
412 06:56:32.484849 TPM: setup succeeded
413 06:56:32.496651 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 06:56:32.505104 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 06:56:32.519399 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 06:56:32.526431 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 06:56:32.530302 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 06:56:32.534207 in-header: 03 07 00 00 08 00 00 00
419 06:56:32.537563 in-data: aa e4 47 04 13 02 00 00
420 06:56:32.541448 Chrome EC: UHEPI supported
421 06:56:32.548548 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 06:56:32.552250 in-header: 03 95 00 00 08 00 00 00
423 06:56:32.555543 in-data: 18 20 20 08 00 00 00 00
424 06:56:32.555624 Phase 1
425 06:56:32.559367 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 06:56:32.567057 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 06:56:32.570311 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 06:56:32.574764 Recovery requested (1009000e)
429 06:56:32.582732 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 06:56:32.588048 tlcl_extend: response is 0
431 06:56:32.597149 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 06:56:32.602552 tlcl_extend: response is 0
433 06:56:32.609459 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 06:56:32.629572 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 06:56:32.636332 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 06:56:32.636429
437 06:56:32.636494
438 06:56:32.646702 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 06:56:32.649857 ARM64: Exception handlers installed.
440 06:56:32.653003 ARM64: Testing exception
441 06:56:32.653083 ARM64: Done test exception
442 06:56:32.675321 pmic_efuse_setting: Set efuses in 11 msecs
443 06:56:32.678972 pmwrap_interface_init: Select PMIF_VLD_RDY
444 06:56:32.685465 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 06:56:32.688747 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 06:56:32.692571 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 06:56:32.700169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 06:56:32.703265 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 06:56:32.706913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 06:56:32.714671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 06:56:32.718741 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 06:56:32.722534 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 06:56:32.726156 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 06:56:32.733777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 06:56:32.737965 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 06:56:32.741197 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 06:56:32.748346 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 06:56:32.752526 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 06:56:32.759544 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 06:56:32.763443 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 06:56:32.770677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 06:56:32.775001 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 06:56:32.781786 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 06:56:32.785824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 06:56:32.792840 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 06:56:32.796526 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 06:56:32.804215 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 06:56:32.808181 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 06:56:32.815106 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 06:56:32.818741 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 06:56:32.826123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 06:56:32.829417 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 06:56:32.833711 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 06:56:32.837667 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 06:56:32.845198 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 06:56:32.848867 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 06:56:32.856099 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 06:56:32.859674 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 06:56:32.863576 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 06:56:32.870992 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 06:56:32.874781 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 06:56:32.878399 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 06:56:32.882369 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 06:56:32.889404 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 06:56:32.893176 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 06:56:32.896519 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 06:56:32.900511 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 06:56:32.904191 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 06:56:32.908088 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 06:56:32.915021 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 06:56:32.919449 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 06:56:32.923176 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 06:56:32.926967 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 06:56:32.930260 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 06:56:32.938087 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 06:56:32.945116 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 06:56:32.952084 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 06:56:32.959706 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 06:56:32.967394 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 06:56:32.970994 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 06:56:32.978524 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 06:56:32.982004 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 06:56:32.989240 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
504 06:56:32.992241 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 06:56:33.000444 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 06:56:33.003530 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 06:56:33.012749 [RTC]rtc_get_frequency_meter,154: input=15, output=758
508 06:56:33.022462 [RTC]rtc_get_frequency_meter,154: input=23, output=940
509 06:56:33.031852 [RTC]rtc_get_frequency_meter,154: input=19, output=850
510 06:56:33.041623 [RTC]rtc_get_frequency_meter,154: input=17, output=805
511 06:56:33.051187 [RTC]rtc_get_frequency_meter,154: input=16, output=782
512 06:56:33.060490 [RTC]rtc_get_frequency_meter,154: input=16, output=783
513 06:56:33.070543 [RTC]rtc_get_frequency_meter,154: input=17, output=805
514 06:56:33.074494 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
515 06:56:33.078361 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 06:56:33.081910 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 06:56:33.089402 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 06:56:33.093323 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 06:56:33.096558 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 06:56:33.100482 ADC[4]: Raw value=906573 ID=7
521 06:56:33.101067 ADC[3]: Raw value=213810 ID=1
522 06:56:33.104060 RAM Code: 0x71
523 06:56:33.107979 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 06:56:33.111347 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 06:56:33.122785 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 06:56:33.126825 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 06:56:33.129733 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 06:56:33.134234 in-header: 03 07 00 00 08 00 00 00
529 06:56:33.138954 in-data: aa e4 47 04 13 02 00 00
530 06:56:33.142309 Chrome EC: UHEPI supported
531 06:56:33.149467 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 06:56:33.152947 in-header: 03 95 00 00 08 00 00 00
533 06:56:33.153520 in-data: 18 20 20 08 00 00 00 00
534 06:56:33.156990 MRC: failed to locate region type 0.
535 06:56:33.164393 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 06:56:33.168078 DRAM-K: Running full calibration
537 06:56:33.175352 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 06:56:33.175773 header.status = 0x0
539 06:56:33.179588 header.version = 0x6 (expected: 0x6)
540 06:56:33.183130 header.size = 0xd00 (expected: 0xd00)
541 06:56:33.183685 header.flags = 0x0
542 06:56:33.190098 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 06:56:33.208075 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
544 06:56:33.215938 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 06:56:33.216675 dram_init: ddr_geometry: 2
546 06:56:33.219206 [EMI] MDL number = 2
547 06:56:33.222901 [EMI] Get MDL freq = 0
548 06:56:33.223346 dram_init: ddr_type: 0
549 06:56:33.226850 is_discrete_lpddr4: 1
550 06:56:33.230658 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 06:56:33.231087
552 06:56:33.231438
553 06:56:33.231751 [Bian_co] ETT version 0.0.0.1
554 06:56:33.238120 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 06:56:33.238543
556 06:56:33.241625 dramc_set_vcore_voltage set vcore to 650000
557 06:56:33.242045 Read voltage for 800, 4
558 06:56:33.245303 Vio18 = 0
559 06:56:33.245724 Vcore = 650000
560 06:56:33.246060 Vdram = 0
561 06:56:33.246376 Vddq = 0
562 06:56:33.248803 Vmddr = 0
563 06:56:33.249340 dram_init: config_dvfs: 1
564 06:56:33.256600 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 06:56:33.260422 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 06:56:33.263986 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
567 06:56:33.267656 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
568 06:56:33.270974 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
569 06:56:33.275018 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
570 06:56:33.277926 MEM_TYPE=3, freq_sel=18
571 06:56:33.281161 sv_algorithm_assistance_LP4_1600
572 06:56:33.284823 ============ PULL DRAM RESETB DOWN ============
573 06:56:33.288251 ========== PULL DRAM RESETB DOWN end =========
574 06:56:33.295188 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 06:56:33.298756 ===================================
576 06:56:33.299178 LPDDR4 DRAM CONFIGURATION
577 06:56:33.302376 ===================================
578 06:56:33.306219 EX_ROW_EN[0] = 0x0
579 06:56:33.306653 EX_ROW_EN[1] = 0x0
580 06:56:33.309714 LP4Y_EN = 0x0
581 06:56:33.310129 WORK_FSP = 0x0
582 06:56:33.313456 WL = 0x2
583 06:56:33.313871 RL = 0x2
584 06:56:33.317036 BL = 0x2
585 06:56:33.317479 RPST = 0x0
586 06:56:33.320617 RD_PRE = 0x0
587 06:56:33.321031 WR_PRE = 0x1
588 06:56:33.323844 WR_PST = 0x0
589 06:56:33.324258 DBI_WR = 0x0
590 06:56:33.327105 DBI_RD = 0x0
591 06:56:33.327518 OTF = 0x1
592 06:56:33.330193 ===================================
593 06:56:33.334005 ===================================
594 06:56:33.334422 ANA top config
595 06:56:33.337840 ===================================
596 06:56:33.341451 DLL_ASYNC_EN = 0
597 06:56:33.344849 ALL_SLAVE_EN = 1
598 06:56:33.345267 NEW_RANK_MODE = 1
599 06:56:33.347894 DLL_IDLE_MODE = 1
600 06:56:33.351792 LP45_APHY_COMB_EN = 1
601 06:56:33.355367 TX_ODT_DIS = 1
602 06:56:33.358719 NEW_8X_MODE = 1
603 06:56:33.359247 ===================================
604 06:56:33.362195 ===================================
605 06:56:33.365869 data_rate = 1600
606 06:56:33.369148 CKR = 1
607 06:56:33.372379 DQ_P2S_RATIO = 8
608 06:56:33.375966 ===================================
609 06:56:33.378926 CA_P2S_RATIO = 8
610 06:56:33.379361 DQ_CA_OPEN = 0
611 06:56:33.383006 DQ_SEMI_OPEN = 0
612 06:56:33.386031 CA_SEMI_OPEN = 0
613 06:56:33.389116 CA_FULL_RATE = 0
614 06:56:33.392210 DQ_CKDIV4_EN = 1
615 06:56:33.396206 CA_CKDIV4_EN = 1
616 06:56:33.396686 CA_PREDIV_EN = 0
617 06:56:33.399015 PH8_DLY = 0
618 06:56:33.402821 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 06:56:33.405799 DQ_AAMCK_DIV = 4
620 06:56:33.409162 CA_AAMCK_DIV = 4
621 06:56:33.409615 CA_ADMCK_DIV = 4
622 06:56:33.412576 DQ_TRACK_CA_EN = 0
623 06:56:33.415909 CA_PICK = 800
624 06:56:33.419072 CA_MCKIO = 800
625 06:56:33.423468 MCKIO_SEMI = 0
626 06:56:33.427450 PLL_FREQ = 3068
627 06:56:33.427874 DQ_UI_PI_RATIO = 32
628 06:56:33.431440 CA_UI_PI_RATIO = 0
629 06:56:33.434545 ===================================
630 06:56:33.438229 ===================================
631 06:56:33.438651 memory_type:LPDDR4
632 06:56:33.442000 GP_NUM : 10
633 06:56:33.445686 SRAM_EN : 1
634 06:56:33.446122 MD32_EN : 0
635 06:56:33.449748 ===================================
636 06:56:33.453512 [ANA_INIT] >>>>>>>>>>>>>>
637 06:56:33.453939 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 06:56:33.457360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 06:56:33.460657 ===================================
640 06:56:33.463855 data_rate = 1600,PCW = 0X7600
641 06:56:33.467995 ===================================
642 06:56:33.470871 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 06:56:33.477547 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 06:56:33.480876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 06:56:33.487380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 06:56:33.491055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 06:56:33.494138 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 06:56:33.494655 [ANA_INIT] flow start
649 06:56:33.497303 [ANA_INIT] PLL >>>>>>>>
650 06:56:33.500825 [ANA_INIT] PLL <<<<<<<<
651 06:56:33.501250 [ANA_INIT] MIDPI >>>>>>>>
652 06:56:33.504075 [ANA_INIT] MIDPI <<<<<<<<
653 06:56:33.507367 [ANA_INIT] DLL >>>>>>>>
654 06:56:33.507881 [ANA_INIT] flow end
655 06:56:33.514376 ============ LP4 DIFF to SE enter ============
656 06:56:33.517784 ============ LP4 DIFF to SE exit ============
657 06:56:33.520835 [ANA_INIT] <<<<<<<<<<<<<
658 06:56:33.521430 [Flow] Enable top DCM control >>>>>
659 06:56:33.524118 [Flow] Enable top DCM control <<<<<
660 06:56:33.527607 Enable DLL master slave shuffle
661 06:56:33.534432 ==============================================================
662 06:56:33.537346 Gating Mode config
663 06:56:33.540802 ==============================================================
664 06:56:33.544939 Config description:
665 06:56:33.554893 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 06:56:33.561028 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 06:56:33.565000 SELPH_MODE 0: By rank 1: By Phase
668 06:56:33.571554 ==============================================================
669 06:56:33.574812 GAT_TRACK_EN = 1
670 06:56:33.575378 RX_GATING_MODE = 2
671 06:56:33.578141 RX_GATING_TRACK_MODE = 2
672 06:56:33.581134 SELPH_MODE = 1
673 06:56:33.584444 PICG_EARLY_EN = 1
674 06:56:33.588258 VALID_LAT_VALUE = 1
675 06:56:33.594237 ==============================================================
676 06:56:33.598338 Enter into Gating configuration >>>>
677 06:56:33.601387 Exit from Gating configuration <<<<
678 06:56:33.604464 Enter into DVFS_PRE_config >>>>>
679 06:56:33.614637 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 06:56:33.618167 Exit from DVFS_PRE_config <<<<<
681 06:56:33.621055 Enter into PICG configuration >>>>
682 06:56:33.625132 Exit from PICG configuration <<<<
683 06:56:33.628145 [RX_INPUT] configuration >>>>>
684 06:56:33.628865 [RX_INPUT] configuration <<<<<
685 06:56:33.634878 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 06:56:33.641350 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 06:56:33.644842 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 06:56:33.651936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 06:56:33.658126 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 06:56:33.665305 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 06:56:33.668469 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 06:56:33.671631 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 06:56:33.678286 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 06:56:33.681903 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 06:56:33.685124 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 06:56:33.688521 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 06:56:33.691552 ===================================
698 06:56:33.695340 LPDDR4 DRAM CONFIGURATION
699 06:56:33.698700 ===================================
700 06:56:33.701989 EX_ROW_EN[0] = 0x0
701 06:56:33.702552 EX_ROW_EN[1] = 0x0
702 06:56:33.704955 LP4Y_EN = 0x0
703 06:56:33.705415 WORK_FSP = 0x0
704 06:56:33.708219 WL = 0x2
705 06:56:33.708714 RL = 0x2
706 06:56:33.712137 BL = 0x2
707 06:56:33.712631 RPST = 0x0
708 06:56:33.715352 RD_PRE = 0x0
709 06:56:33.715808 WR_PRE = 0x1
710 06:56:33.718842 WR_PST = 0x0
711 06:56:33.719408 DBI_WR = 0x0
712 06:56:33.721903 DBI_RD = 0x0
713 06:56:33.722362 OTF = 0x1
714 06:56:33.725031 ===================================
715 06:56:33.732452 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 06:56:33.735208 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 06:56:33.738301 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 06:56:33.741900 ===================================
719 06:56:33.745900 LPDDR4 DRAM CONFIGURATION
720 06:56:33.748882 ===================================
721 06:56:33.752071 EX_ROW_EN[0] = 0x10
722 06:56:33.752732 EX_ROW_EN[1] = 0x0
723 06:56:33.755370 LP4Y_EN = 0x0
724 06:56:33.755868 WORK_FSP = 0x0
725 06:56:33.758403 WL = 0x2
726 06:56:33.759018 RL = 0x2
727 06:56:33.762158 BL = 0x2
728 06:56:33.762618 RPST = 0x0
729 06:56:33.765606 RD_PRE = 0x0
730 06:56:33.766168 WR_PRE = 0x1
731 06:56:33.768452 WR_PST = 0x0
732 06:56:33.768917 DBI_WR = 0x0
733 06:56:33.772076 DBI_RD = 0x0
734 06:56:33.772644 OTF = 0x1
735 06:56:33.775669 ===================================
736 06:56:33.781752 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 06:56:33.786743 nWR fixed to 40
738 06:56:33.789818 [ModeRegInit_LP4] CH0 RK0
739 06:56:33.790293 [ModeRegInit_LP4] CH0 RK1
740 06:56:33.793043 [ModeRegInit_LP4] CH1 RK0
741 06:56:33.796174 [ModeRegInit_LP4] CH1 RK1
742 06:56:33.796731 match AC timing 13
743 06:56:33.803055 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 06:56:33.806496 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 06:56:33.809474 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 06:56:33.816787 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 06:56:33.820387 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 06:56:33.820963 [EMI DOE] emi_dcm 0
749 06:56:33.826739 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 06:56:33.827200 ==
751 06:56:33.830228 Dram Type= 6, Freq= 0, CH_0, rank 0
752 06:56:33.833409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 06:56:33.833972 ==
754 06:56:33.839698 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 06:56:33.843344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 06:56:33.854100 [CA 0] Center 36 (6~67) winsize 62
757 06:56:33.857173 [CA 1] Center 36 (6~67) winsize 62
758 06:56:33.860596 [CA 2] Center 34 (4~65) winsize 62
759 06:56:33.863906 [CA 3] Center 34 (4~64) winsize 61
760 06:56:33.867250 [CA 4] Center 33 (3~63) winsize 61
761 06:56:33.870636 [CA 5] Center 32 (2~62) winsize 61
762 06:56:33.871099
763 06:56:33.873765 [CmdBusTrainingLP45] Vref(ca) range 1: 32
764 06:56:33.874227
765 06:56:33.876827 [CATrainingPosCal] consider 1 rank data
766 06:56:33.880269 u2DelayCellTimex100 = 270/100 ps
767 06:56:33.883473 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
768 06:56:33.886870 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
769 06:56:33.893818 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
770 06:56:33.896956 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
771 06:56:33.900675 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
772 06:56:33.904323 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
773 06:56:33.904906
774 06:56:33.907180 CA PerBit enable=1, Macro0, CA PI delay=32
775 06:56:33.907647
776 06:56:33.910493 [CBTSetCACLKResult] CA Dly = 32
777 06:56:33.911080 CS Dly: 4 (0~35)
778 06:56:33.911451 ==
779 06:56:33.913952 Dram Type= 6, Freq= 0, CH_0, rank 1
780 06:56:33.920465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 06:56:33.921031 ==
782 06:56:33.924210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 06:56:33.930675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 06:56:33.939955 [CA 0] Center 36 (6~67) winsize 62
785 06:56:33.943123 [CA 1] Center 36 (6~67) winsize 62
786 06:56:33.946601 [CA 2] Center 34 (4~65) winsize 62
787 06:56:33.949718 [CA 3] Center 33 (3~64) winsize 62
788 06:56:33.952983 [CA 4] Center 33 (3~63) winsize 61
789 06:56:33.956452 [CA 5] Center 32 (2~63) winsize 62
790 06:56:33.957024
791 06:56:33.959713 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 06:56:33.960331
793 06:56:33.963416 [CATrainingPosCal] consider 2 rank data
794 06:56:33.966800 u2DelayCellTimex100 = 270/100 ps
795 06:56:33.969835 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
796 06:56:33.976521 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
797 06:56:33.979524 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
798 06:56:33.983129 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
799 06:56:33.986713 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
800 06:56:33.989831 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
801 06:56:33.990307
802 06:56:33.992958 CA PerBit enable=1, Macro0, CA PI delay=32
803 06:56:33.993439
804 06:56:33.996105 [CBTSetCACLKResult] CA Dly = 32
805 06:56:33.996673 CS Dly: 5 (0~37)
806 06:56:33.999758
807 06:56:34.000231 ----->DramcWriteLeveling(PI) begin...
808 06:56:34.003778 ==
809 06:56:34.004253 Dram Type= 6, Freq= 0, CH_0, rank 0
810 06:56:34.010582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 06:56:34.011108 ==
812 06:56:34.011490 Write leveling (Byte 0): 33 => 33
813 06:56:34.014665 Write leveling (Byte 1): 31 => 31
814 06:56:34.018709 DramcWriteLeveling(PI) end<-----
815 06:56:34.019262
816 06:56:34.019607 ==
817 06:56:34.021676 Dram Type= 6, Freq= 0, CH_0, rank 0
818 06:56:34.025540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 06:56:34.026044 ==
820 06:56:34.028600 [Gating] SW mode calibration
821 06:56:34.035869 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 06:56:34.042616 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 06:56:34.046543 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 06:56:34.049663 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 06:56:34.056073 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 06:56:34.059725 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 06:56:34.062653 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 06:56:34.069825 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 06:56:34.072968 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 06:56:34.076385 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 06:56:34.079647 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 06:56:34.086407 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 06:56:34.089729 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 06:56:34.092870 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 06:56:34.100061 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 06:56:34.103284 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 06:56:34.106296 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 06:56:34.112992 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 06:56:34.116405 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
840 06:56:34.119395 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 06:56:34.126059 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
842 06:56:34.129794 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 06:56:34.132902 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 06:56:34.139780 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 06:56:34.142849 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 06:56:34.146904 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 06:56:34.149634 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 06:56:34.157002 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 06:56:34.159461 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
850 06:56:34.163172 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
851 06:56:34.169516 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 06:56:34.172848 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 06:56:34.176432 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 06:56:34.183411 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 06:56:34.187067 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 06:56:34.189784 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
857 06:56:34.196832 0 10 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (1 1)
858 06:56:34.200376 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
859 06:56:34.203476 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 06:56:34.210034 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 06:56:34.213519 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 06:56:34.216942 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 06:56:34.220217 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 06:56:34.226505 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
865 06:56:34.230106 0 11 8 | B1->B0 | 2a2a 3f3f | 0 0 | (0 0) (0 0)
866 06:56:34.233091 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
867 06:56:34.240156 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 06:56:34.242997 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 06:56:34.246190 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 06:56:34.253400 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 06:56:34.256331 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 06:56:34.260159 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 06:56:34.266669 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
874 06:56:34.269908 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
875 06:56:34.273086 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 06:56:34.280435 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 06:56:34.284127 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 06:56:34.286378 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 06:56:34.293647 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 06:56:34.296834 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 06:56:34.299975 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 06:56:34.307013 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 06:56:34.310457 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 06:56:34.313434 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 06:56:34.316999 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 06:56:34.323977 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 06:56:34.326971 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 06:56:34.330391 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 06:56:34.337203 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
890 06:56:34.340412 Total UI for P1: 0, mck2ui 16
891 06:56:34.343615 best dqsien dly found for B0: ( 0, 14, 6)
892 06:56:34.346917 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 06:56:34.350101 Total UI for P1: 0, mck2ui 16
894 06:56:34.353655 best dqsien dly found for B1: ( 0, 14, 8)
895 06:56:34.357152 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
896 06:56:34.360964 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
897 06:56:34.361596
898 06:56:34.364329 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
899 06:56:34.367840 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
900 06:56:34.370703 [Gating] SW calibration Done
901 06:56:34.371366 ==
902 06:56:34.374232 Dram Type= 6, Freq= 0, CH_0, rank 0
903 06:56:34.377458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 06:56:34.377930 ==
905 06:56:34.380801 RX Vref Scan: 0
906 06:56:34.381338
907 06:56:34.381717 RX Vref 0 -> 0, step: 1
908 06:56:34.382169
909 06:56:34.384261 RX Delay -130 -> 252, step: 16
910 06:56:34.387598 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 06:56:34.394306 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
912 06:56:34.397542 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 06:56:34.400858 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 06:56:34.404558 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
915 06:56:34.407854 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
916 06:56:34.414318 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
917 06:56:34.417421 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
918 06:56:34.421050 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
919 06:56:34.424246 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
920 06:56:34.427912 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
921 06:56:34.434664 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
922 06:56:34.438137 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
923 06:56:34.441395 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
924 06:56:34.444444 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
925 06:56:34.447904 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
926 06:56:34.451265 ==
927 06:56:34.452018 Dram Type= 6, Freq= 0, CH_0, rank 0
928 06:56:34.458232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 06:56:34.458811 ==
930 06:56:34.459191 DQS Delay:
931 06:56:34.461161 DQS0 = 0, DQS1 = 0
932 06:56:34.461685 DQM Delay:
933 06:56:34.464644 DQM0 = 89, DQM1 = 83
934 06:56:34.465214 DQ Delay:
935 06:56:34.468000 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
936 06:56:34.471308 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
937 06:56:34.474337 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
938 06:56:34.477721 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
939 06:56:34.478297
940 06:56:34.478670
941 06:56:34.479008 ==
942 06:56:34.481417 Dram Type= 6, Freq= 0, CH_0, rank 0
943 06:56:34.484569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 06:56:34.485067 ==
945 06:56:34.485445
946 06:56:34.485824
947 06:56:34.487549 TX Vref Scan disable
948 06:56:34.491177 == TX Byte 0 ==
949 06:56:34.494417 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
950 06:56:34.497396 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
951 06:56:34.501159 == TX Byte 1 ==
952 06:56:34.504507 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
953 06:56:34.507485 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
954 06:56:34.507954 ==
955 06:56:34.510805 Dram Type= 6, Freq= 0, CH_0, rank 0
956 06:56:34.514268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 06:56:34.517667 ==
958 06:56:34.529029 TX Vref=22, minBit 8, minWin=27, winSum=446
959 06:56:34.532424 TX Vref=24, minBit 8, minWin=27, winSum=449
960 06:56:34.535846 TX Vref=26, minBit 9, minWin=27, winSum=453
961 06:56:34.539519 TX Vref=28, minBit 8, minWin=28, winSum=457
962 06:56:34.542297 TX Vref=30, minBit 0, minWin=28, winSum=455
963 06:56:34.545369 TX Vref=32, minBit 6, minWin=27, winSum=451
964 06:56:34.552571 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 28
965 06:56:34.553039
966 06:56:34.555396 Final TX Range 1 Vref 28
967 06:56:34.555860
968 06:56:34.556227 ==
969 06:56:34.559219 Dram Type= 6, Freq= 0, CH_0, rank 0
970 06:56:34.562355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 06:56:34.562828 ==
972 06:56:34.563202
973 06:56:34.565447
974 06:56:34.565914 TX Vref Scan disable
975 06:56:34.568849 == TX Byte 0 ==
976 06:56:34.572363 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
977 06:56:34.575814 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
978 06:56:34.579132 == TX Byte 1 ==
979 06:56:34.582330 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 06:56:34.585578 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 06:56:34.589295
982 06:56:34.589848 [DATLAT]
983 06:56:34.590227 Freq=800, CH0 RK0
984 06:56:34.590579
985 06:56:34.592209 DATLAT Default: 0xa
986 06:56:34.592728 0, 0xFFFF, sum = 0
987 06:56:34.595422 1, 0xFFFF, sum = 0
988 06:56:34.596014 2, 0xFFFF, sum = 0
989 06:56:34.599449 3, 0xFFFF, sum = 0
990 06:56:34.600029 4, 0xFFFF, sum = 0
991 06:56:34.602678 5, 0xFFFF, sum = 0
992 06:56:34.603248 6, 0xFFFF, sum = 0
993 06:56:34.605596 7, 0xFFFF, sum = 0
994 06:56:34.608778 8, 0xFFFF, sum = 0
995 06:56:34.609274 9, 0x0, sum = 1
996 06:56:34.609654 10, 0x0, sum = 2
997 06:56:34.611859 11, 0x0, sum = 3
998 06:56:34.612381 12, 0x0, sum = 4
999 06:56:34.615579 best_step = 10
1000 06:56:34.616041
1001 06:56:34.616465 ==
1002 06:56:34.619261 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 06:56:34.622448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 06:56:34.623011 ==
1005 06:56:34.625479 RX Vref Scan: 1
1006 06:56:34.625940
1007 06:56:34.626314 Set Vref Range= 32 -> 127
1008 06:56:34.626664
1009 06:56:34.628849 RX Vref 32 -> 127, step: 1
1010 06:56:34.629319
1011 06:56:34.632369 RX Delay -79 -> 252, step: 8
1012 06:56:34.632843
1013 06:56:34.635662 Set Vref, RX VrefLevel [Byte0]: 32
1014 06:56:34.638914 [Byte1]: 32
1015 06:56:34.639500
1016 06:56:34.642200 Set Vref, RX VrefLevel [Byte0]: 33
1017 06:56:34.646066 [Byte1]: 33
1018 06:56:34.649070
1019 06:56:34.649612 Set Vref, RX VrefLevel [Byte0]: 34
1020 06:56:34.652516 [Byte1]: 34
1021 06:56:34.656458
1022 06:56:34.657040 Set Vref, RX VrefLevel [Byte0]: 35
1023 06:56:34.659860 [Byte1]: 35
1024 06:56:34.664643
1025 06:56:34.665222 Set Vref, RX VrefLevel [Byte0]: 36
1026 06:56:34.667582 [Byte1]: 36
1027 06:56:34.672334
1028 06:56:34.672831 Set Vref, RX VrefLevel [Byte0]: 37
1029 06:56:34.675149 [Byte1]: 37
1030 06:56:34.679537
1031 06:56:34.679993 Set Vref, RX VrefLevel [Byte0]: 38
1032 06:56:34.682810 [Byte1]: 38
1033 06:56:34.687374
1034 06:56:34.687918 Set Vref, RX VrefLevel [Byte0]: 39
1035 06:56:34.690539 [Byte1]: 39
1036 06:56:34.694419
1037 06:56:34.694853 Set Vref, RX VrefLevel [Byte0]: 40
1038 06:56:34.698290 [Byte1]: 40
1039 06:56:34.701804
1040 06:56:34.704834 Set Vref, RX VrefLevel [Byte0]: 41
1041 06:56:34.705256 [Byte1]: 41
1042 06:56:34.709474
1043 06:56:34.709888 Set Vref, RX VrefLevel [Byte0]: 42
1044 06:56:34.712812 [Byte1]: 42
1045 06:56:34.717279
1046 06:56:34.717860 Set Vref, RX VrefLevel [Byte0]: 43
1047 06:56:34.720548 [Byte1]: 43
1048 06:56:34.724564
1049 06:56:34.725073 Set Vref, RX VrefLevel [Byte0]: 44
1050 06:56:34.727615 [Byte1]: 44
1051 06:56:34.732402
1052 06:56:34.732939 Set Vref, RX VrefLevel [Byte0]: 45
1053 06:56:34.735452 [Byte1]: 45
1054 06:56:34.739699
1055 06:56:34.740208 Set Vref, RX VrefLevel [Byte0]: 46
1056 06:56:34.743121 [Byte1]: 46
1057 06:56:34.747184
1058 06:56:34.747683 Set Vref, RX VrefLevel [Byte0]: 47
1059 06:56:34.750322 [Byte1]: 47
1060 06:56:34.754966
1061 06:56:34.755474 Set Vref, RX VrefLevel [Byte0]: 48
1062 06:56:34.757886 [Byte1]: 48
1063 06:56:34.762343
1064 06:56:34.762846 Set Vref, RX VrefLevel [Byte0]: 49
1065 06:56:34.765573 [Byte1]: 49
1066 06:56:34.770272
1067 06:56:34.770777 Set Vref, RX VrefLevel [Byte0]: 50
1068 06:56:34.772936 [Byte1]: 50
1069 06:56:34.776992
1070 06:56:34.777406 Set Vref, RX VrefLevel [Byte0]: 51
1071 06:56:34.780600 [Byte1]: 51
1072 06:56:34.784676
1073 06:56:34.785132 Set Vref, RX VrefLevel [Byte0]: 52
1074 06:56:34.788262 [Byte1]: 52
1075 06:56:34.793068
1076 06:56:34.793625 Set Vref, RX VrefLevel [Byte0]: 53
1077 06:56:34.795593 [Byte1]: 53
1078 06:56:34.800267
1079 06:56:34.800893 Set Vref, RX VrefLevel [Byte0]: 54
1080 06:56:34.803734 [Byte1]: 54
1081 06:56:34.807403
1082 06:56:34.807987 Set Vref, RX VrefLevel [Byte0]: 55
1083 06:56:34.811114 [Byte1]: 55
1084 06:56:34.815409
1085 06:56:34.815882 Set Vref, RX VrefLevel [Byte0]: 56
1086 06:56:34.818792 [Byte1]: 56
1087 06:56:34.822866
1088 06:56:34.823441 Set Vref, RX VrefLevel [Byte0]: 57
1089 06:56:34.825841 [Byte1]: 57
1090 06:56:34.830386
1091 06:56:34.830856 Set Vref, RX VrefLevel [Byte0]: 58
1092 06:56:34.833255 [Byte1]: 58
1093 06:56:34.837720
1094 06:56:34.838292 Set Vref, RX VrefLevel [Byte0]: 59
1095 06:56:34.841600 [Byte1]: 59
1096 06:56:34.845415
1097 06:56:34.845986 Set Vref, RX VrefLevel [Byte0]: 60
1098 06:56:34.848682 [Byte1]: 60
1099 06:56:34.853021
1100 06:56:34.853495 Set Vref, RX VrefLevel [Byte0]: 61
1101 06:56:34.856668 [Byte1]: 61
1102 06:56:34.861066
1103 06:56:34.861636 Set Vref, RX VrefLevel [Byte0]: 62
1104 06:56:34.863777 [Byte1]: 62
1105 06:56:34.868751
1106 06:56:34.869324 Set Vref, RX VrefLevel [Byte0]: 63
1107 06:56:34.871308 [Byte1]: 63
1108 06:56:34.875718
1109 06:56:34.876193 Set Vref, RX VrefLevel [Byte0]: 64
1110 06:56:34.879164 [Byte1]: 64
1111 06:56:34.883595
1112 06:56:34.884171 Set Vref, RX VrefLevel [Byte0]: 65
1113 06:56:34.886635 [Byte1]: 65
1114 06:56:34.890777
1115 06:56:34.891263 Set Vref, RX VrefLevel [Byte0]: 66
1116 06:56:34.893675 [Byte1]: 66
1117 06:56:34.898208
1118 06:56:34.898678 Set Vref, RX VrefLevel [Byte0]: 67
1119 06:56:34.901482 [Byte1]: 67
1120 06:56:34.905631
1121 06:56:34.906183 Set Vref, RX VrefLevel [Byte0]: 68
1122 06:56:34.908944 [Byte1]: 68
1123 06:56:34.913163
1124 06:56:34.913737 Set Vref, RX VrefLevel [Byte0]: 69
1125 06:56:34.916679 [Byte1]: 69
1126 06:56:34.921274
1127 06:56:34.921866 Set Vref, RX VrefLevel [Byte0]: 70
1128 06:56:34.924197 [Byte1]: 70
1129 06:56:34.928418
1130 06:56:34.928972 Set Vref, RX VrefLevel [Byte0]: 71
1131 06:56:34.932042 [Byte1]: 71
1132 06:56:34.935831
1133 06:56:34.936498 Set Vref, RX VrefLevel [Byte0]: 72
1134 06:56:34.939504 [Byte1]: 72
1135 06:56:34.943591
1136 06:56:34.944145 Set Vref, RX VrefLevel [Byte0]: 73
1137 06:56:34.946576 [Byte1]: 73
1138 06:56:34.950998
1139 06:56:34.951456 Set Vref, RX VrefLevel [Byte0]: 74
1140 06:56:34.954177 [Byte1]: 74
1141 06:56:34.958829
1142 06:56:34.959385 Set Vref, RX VrefLevel [Byte0]: 75
1143 06:56:34.961980 [Byte1]: 75
1144 06:56:34.966016
1145 06:56:34.966570 Set Vref, RX VrefLevel [Byte0]: 76
1146 06:56:34.969323 [Byte1]: 76
1147 06:56:34.973898
1148 06:56:34.974354 Set Vref, RX VrefLevel [Byte0]: 77
1149 06:56:34.976908 [Byte1]: 77
1150 06:56:34.981467
1151 06:56:34.981922 Final RX Vref Byte 0 = 57 to rank0
1152 06:56:34.984658 Final RX Vref Byte 1 = 59 to rank0
1153 06:56:34.987394 Final RX Vref Byte 0 = 57 to rank1
1154 06:56:34.991360 Final RX Vref Byte 1 = 59 to rank1==
1155 06:56:34.994700 Dram Type= 6, Freq= 0, CH_0, rank 0
1156 06:56:35.001137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 06:56:35.001657 ==
1158 06:56:35.001995 DQS Delay:
1159 06:56:35.002307 DQS0 = 0, DQS1 = 0
1160 06:56:35.004720 DQM Delay:
1161 06:56:35.005232 DQM0 = 92, DQM1 = 85
1162 06:56:35.007872 DQ Delay:
1163 06:56:35.010868 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1164 06:56:35.014750 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1165 06:56:35.015200 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1166 06:56:35.021194 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1167 06:56:35.021727
1168 06:56:35.022063
1169 06:56:35.028077 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1170 06:56:35.031036 CH0 RK0: MR19=606, MR18=4D43
1171 06:56:35.037849 CH0_RK0: MR19=0x606, MR18=0x4D43, DQSOSC=390, MR23=63, INC=97, DEC=64
1172 06:56:35.038279
1173 06:56:35.041397 ----->DramcWriteLeveling(PI) begin...
1174 06:56:35.041936 ==
1175 06:56:35.044757 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 06:56:35.047973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 06:56:35.048419 ==
1178 06:56:35.051211 Write leveling (Byte 0): 31 => 31
1179 06:56:35.054506 Write leveling (Byte 1): 31 => 31
1180 06:56:35.058381 DramcWriteLeveling(PI) end<-----
1181 06:56:35.059185
1182 06:56:35.059592 ==
1183 06:56:35.060932 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 06:56:35.064638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 06:56:35.065104 ==
1186 06:56:35.068038 [Gating] SW mode calibration
1187 06:56:35.074640 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1188 06:56:35.118509 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1189 06:56:35.119066 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 06:56:35.119437 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1191 06:56:35.119776 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1192 06:56:35.120108 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 06:56:35.120881 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 06:56:35.121247 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 06:56:35.121576 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 06:56:35.121893 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 06:56:35.122207 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 06:56:35.162676 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 06:56:35.163515 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 06:56:35.164005 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 06:56:35.164693 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 06:56:35.165127 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 06:56:35.165668 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 06:56:35.166081 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 06:56:35.166638 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 06:56:35.167180 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1207 06:56:35.167585 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1208 06:56:35.188565 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1209 06:56:35.189289 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 06:56:35.190313 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 06:56:35.190870 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 06:56:35.191242 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 06:56:35.192144 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 06:56:35.195609 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 06:56:35.198459 0 9 8 | B1->B0 | 3030 2a2a | 0 1 | (0 0) (1 1)
1216 06:56:35.202286 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 06:56:35.208808 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 06:56:35.212606 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 06:56:35.215757 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 06:56:35.222234 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 06:56:35.225679 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 06:56:35.229024 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
1223 06:56:35.235337 0 10 8 | B1->B0 | 2525 2929 | 0 0 | (1 0) (0 0)
1224 06:56:35.239086 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 06:56:35.242205 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 06:56:35.246020 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 06:56:35.254028 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 06:56:35.257835 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 06:56:35.261525 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 06:56:35.264773 0 11 4 | B1->B0 | 2525 2423 | 0 1 | (0 0) (0 0)
1231 06:56:35.268140 0 11 8 | B1->B0 | 3f3f 3b3b | 0 0 | (0 0) (0 0)
1232 06:56:35.275386 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 06:56:35.278813 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 06:56:35.281934 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 06:56:35.285804 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 06:56:35.292090 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 06:56:35.295683 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 06:56:35.299029 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 06:56:35.305604 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1240 06:56:35.309285 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 06:56:35.312268 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 06:56:35.319285 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 06:56:35.322294 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 06:56:35.325890 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 06:56:35.329179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 06:56:35.335448 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 06:56:35.338941 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 06:56:35.342224 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 06:56:35.349021 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 06:56:35.352475 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 06:56:35.355802 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 06:56:35.362415 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 06:56:35.365524 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 06:56:35.368680 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1255 06:56:35.375511 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1256 06:56:35.378847 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 06:56:35.382069 Total UI for P1: 0, mck2ui 16
1258 06:56:35.385921 best dqsien dly found for B0: ( 0, 14, 8)
1259 06:56:35.389034 Total UI for P1: 0, mck2ui 16
1260 06:56:35.392206 best dqsien dly found for B1: ( 0, 14, 6)
1261 06:56:35.395519 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1262 06:56:35.399144 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1263 06:56:35.399328
1264 06:56:35.402304 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1265 06:56:35.405555 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1266 06:56:35.409299 [Gating] SW calibration Done
1267 06:56:35.409532 ==
1268 06:56:35.412347 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 06:56:35.415673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 06:56:35.415864 ==
1271 06:56:35.418893 RX Vref Scan: 0
1272 06:56:35.419171
1273 06:56:35.419417 RX Vref 0 -> 0, step: 1
1274 06:56:35.419563
1275 06:56:35.422478 RX Delay -130 -> 252, step: 16
1276 06:56:35.428940 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1277 06:56:35.432317 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1278 06:56:35.435951 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1279 06:56:35.439001 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1280 06:56:35.443244 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1281 06:56:35.445860 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1282 06:56:35.452579 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1283 06:56:35.456052 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1284 06:56:35.459225 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1285 06:56:35.462628 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1286 06:56:35.466210 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1287 06:56:35.472661 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1288 06:56:35.476369 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1289 06:56:35.479845 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1290 06:56:35.483306 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1291 06:56:35.486127 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1292 06:56:35.489878 ==
1293 06:56:35.490471 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 06:56:35.496335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 06:56:35.496762 ==
1296 06:56:35.497095 DQS Delay:
1297 06:56:35.500165 DQS0 = 0, DQS1 = 0
1298 06:56:35.500654 DQM Delay:
1299 06:56:35.503290 DQM0 = 93, DQM1 = 85
1300 06:56:35.503704 DQ Delay:
1301 06:56:35.506642 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1302 06:56:35.509896 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1303 06:56:35.513178 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1304 06:56:35.516201 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1305 06:56:35.516681
1306 06:56:35.517011
1307 06:56:35.517319 ==
1308 06:56:35.520114 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 06:56:35.523433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 06:56:35.523870 ==
1311 06:56:35.524343
1312 06:56:35.524764
1313 06:56:35.526793 TX Vref Scan disable
1314 06:56:35.529967 == TX Byte 0 ==
1315 06:56:35.533561 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1316 06:56:35.536615 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1317 06:56:35.539828 == TX Byte 1 ==
1318 06:56:35.542850 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1319 06:56:35.546792 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1320 06:56:35.547023 ==
1321 06:56:35.549904 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 06:56:35.553206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 06:56:35.553438 ==
1324 06:56:35.567429 TX Vref=22, minBit 1, minWin=28, winSum=452
1325 06:56:35.570650 TX Vref=24, minBit 0, minWin=28, winSum=451
1326 06:56:35.573948 TX Vref=26, minBit 5, minWin=28, winSum=457
1327 06:56:35.577234 TX Vref=28, minBit 7, minWin=28, winSum=460
1328 06:56:35.580569 TX Vref=30, minBit 5, minWin=28, winSum=456
1329 06:56:35.584343 TX Vref=32, minBit 7, minWin=28, winSum=459
1330 06:56:35.590624 [TxChooseVref] Worse bit 7, Min win 28, Win sum 460, Final Vref 28
1331 06:56:35.590922
1332 06:56:35.593701 Final TX Range 1 Vref 28
1333 06:56:35.593928
1334 06:56:35.594105 ==
1335 06:56:35.597184 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 06:56:35.600870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 06:56:35.601112 ==
1338 06:56:35.601291
1339 06:56:35.601454
1340 06:56:35.603851 TX Vref Scan disable
1341 06:56:35.607263 == TX Byte 0 ==
1342 06:56:35.610654 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1343 06:56:35.613848 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1344 06:56:35.617330 == TX Byte 1 ==
1345 06:56:35.621074 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1346 06:56:35.624181 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1347 06:56:35.624454
1348 06:56:35.627458 [DATLAT]
1349 06:56:35.627678 Freq=800, CH0 RK1
1350 06:56:35.627853
1351 06:56:35.630633 DATLAT Default: 0xa
1352 06:56:35.630855 0, 0xFFFF, sum = 0
1353 06:56:35.634416 1, 0xFFFF, sum = 0
1354 06:56:35.634639 2, 0xFFFF, sum = 0
1355 06:56:35.637497 3, 0xFFFF, sum = 0
1356 06:56:35.637721 4, 0xFFFF, sum = 0
1357 06:56:35.640881 5, 0xFFFF, sum = 0
1358 06:56:35.641106 6, 0xFFFF, sum = 0
1359 06:56:35.644702 7, 0xFFFF, sum = 0
1360 06:56:35.644881 8, 0xFFFF, sum = 0
1361 06:56:35.647672 9, 0x0, sum = 1
1362 06:56:35.647852 10, 0x0, sum = 2
1363 06:56:35.651034 11, 0x0, sum = 3
1364 06:56:35.651298 12, 0x0, sum = 4
1365 06:56:35.654081 best_step = 10
1366 06:56:35.654261
1367 06:56:35.654399 ==
1368 06:56:35.657958 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 06:56:35.661121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 06:56:35.661299 ==
1371 06:56:35.664219 RX Vref Scan: 0
1372 06:56:35.664478
1373 06:56:35.664626 RX Vref 0 -> 0, step: 1
1374 06:56:35.664763
1375 06:56:35.667649 RX Delay -79 -> 252, step: 8
1376 06:56:35.674407 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1377 06:56:35.677794 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1378 06:56:35.680902 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1379 06:56:35.684119 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1380 06:56:35.687748 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1381 06:56:35.691313 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1382 06:56:35.697799 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1383 06:56:35.700887 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1384 06:56:35.704218 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1385 06:56:35.707391 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1386 06:56:35.711215 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1387 06:56:35.717342 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1388 06:56:35.720909 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1389 06:56:35.724411 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1390 06:56:35.727855 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1391 06:56:35.730748 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1392 06:56:35.734279 ==
1393 06:56:35.737873 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 06:56:35.740733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 06:56:35.740911 ==
1396 06:56:35.741052 DQS Delay:
1397 06:56:35.744143 DQS0 = 0, DQS1 = 0
1398 06:56:35.744339 DQM Delay:
1399 06:56:35.747384 DQM0 = 94, DQM1 = 83
1400 06:56:35.747560 DQ Delay:
1401 06:56:35.751267 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =92
1402 06:56:35.753997 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1403 06:56:35.757673 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1404 06:56:35.761018 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1405 06:56:35.761145
1406 06:56:35.761245
1407 06:56:35.767269 [DQSOSCAuto] RK1, (LSB)MR18= 0x4516, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1408 06:56:35.771354 CH0 RK1: MR19=606, MR18=4516
1409 06:56:35.777635 CH0_RK1: MR19=0x606, MR18=0x4516, DQSOSC=392, MR23=63, INC=96, DEC=64
1410 06:56:35.781303 [RxdqsGatingPostProcess] freq 800
1411 06:56:35.787345 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1412 06:56:35.787519 Pre-setting of DQS Precalculation
1413 06:56:35.794945 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1414 06:56:35.795079 ==
1415 06:56:35.797629 Dram Type= 6, Freq= 0, CH_1, rank 0
1416 06:56:35.800871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 06:56:35.801006 ==
1418 06:56:35.807922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1419 06:56:35.813989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1420 06:56:35.822547 [CA 0] Center 36 (6~67) winsize 62
1421 06:56:35.825261 [CA 1] Center 36 (6~67) winsize 62
1422 06:56:35.828586 [CA 2] Center 34 (4~65) winsize 62
1423 06:56:35.831769 [CA 3] Center 35 (5~65) winsize 61
1424 06:56:35.835622 [CA 4] Center 35 (5~65) winsize 61
1425 06:56:35.838777 [CA 5] Center 34 (4~64) winsize 61
1426 06:56:35.838910
1427 06:56:35.842316 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1428 06:56:35.842456
1429 06:56:35.845249 [CATrainingPosCal] consider 1 rank data
1430 06:56:35.848710 u2DelayCellTimex100 = 270/100 ps
1431 06:56:35.852150 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 06:56:35.855346 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1433 06:56:35.862460 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1434 06:56:35.866017 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1435 06:56:35.869011 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1436 06:56:35.872070 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1437 06:56:35.872318
1438 06:56:35.875728 CA PerBit enable=1, Macro0, CA PI delay=34
1439 06:56:35.875972
1440 06:56:35.879336 [CBTSetCACLKResult] CA Dly = 34
1441 06:56:35.879568 CS Dly: 5 (0~36)
1442 06:56:35.879805 ==
1443 06:56:35.882747 Dram Type= 6, Freq= 0, CH_1, rank 1
1444 06:56:35.889432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 06:56:35.889673 ==
1446 06:56:35.892387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1447 06:56:35.898915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1448 06:56:35.908649 [CA 0] Center 36 (6~67) winsize 62
1449 06:56:35.912751 [CA 1] Center 36 (6~67) winsize 62
1450 06:56:35.916123 [CA 2] Center 35 (5~66) winsize 62
1451 06:56:35.919955 [CA 3] Center 34 (4~65) winsize 62
1452 06:56:35.923857 [CA 4] Center 35 (5~66) winsize 62
1453 06:56:35.924089 [CA 5] Center 34 (4~65) winsize 62
1454 06:56:35.927695
1455 06:56:35.931245 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1456 06:56:35.931477
1457 06:56:35.931713 [CATrainingPosCal] consider 2 rank data
1458 06:56:35.934932 u2DelayCellTimex100 = 270/100 ps
1459 06:56:35.938944 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 06:56:35.942057 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1461 06:56:35.946090 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1462 06:56:35.949199 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1463 06:56:35.952574 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1464 06:56:35.959374 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1465 06:56:35.959607
1466 06:56:35.962491 CA PerBit enable=1, Macro0, CA PI delay=34
1467 06:56:35.962723
1468 06:56:35.965648 [CBTSetCACLKResult] CA Dly = 34
1469 06:56:35.965881 CS Dly: 6 (0~38)
1470 06:56:35.966117
1471 06:56:35.969441 ----->DramcWriteLeveling(PI) begin...
1472 06:56:35.969677 ==
1473 06:56:35.972739 Dram Type= 6, Freq= 0, CH_1, rank 0
1474 06:56:35.976019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 06:56:35.978888 ==
1476 06:56:35.979121 Write leveling (Byte 0): 26 => 26
1477 06:56:35.982406 Write leveling (Byte 1): 27 => 27
1478 06:56:35.985563 DramcWriteLeveling(PI) end<-----
1479 06:56:35.985792
1480 06:56:35.986035 ==
1481 06:56:35.988928 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 06:56:35.995797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1483 06:56:35.996032 ==
1484 06:56:35.998899 [Gating] SW mode calibration
1485 06:56:36.005912 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1486 06:56:36.009112 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1487 06:56:36.012442 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1488 06:56:36.019209 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1489 06:56:36.022760 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 06:56:36.025770 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 06:56:36.032236 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 06:56:36.036197 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 06:56:36.038901 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 06:56:36.045993 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 06:56:36.048998 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 06:56:36.052314 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 06:56:36.059491 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 06:56:36.062332 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 06:56:36.066308 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 06:56:36.072815 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 06:56:36.076129 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 06:56:36.079359 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 06:56:36.085766 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1504 06:56:36.089023 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1505 06:56:36.092107 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 06:56:36.098886 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 06:56:36.102490 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 06:56:36.106097 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 06:56:36.109084 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 06:56:36.115906 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 06:56:36.119200 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 06:56:36.122830 0 9 4 | B1->B0 | 2323 2626 | 1 1 | (1 1) (1 1)
1513 06:56:36.129479 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1514 06:56:36.132686 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 06:56:36.135998 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 06:56:36.142582 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 06:56:36.146067 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 06:56:36.149321 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 06:56:36.155805 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 06:56:36.159760 0 10 4 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (0 0)
1521 06:56:36.162895 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1522 06:56:36.169869 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 06:56:36.172778 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 06:56:36.176488 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 06:56:36.179587 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 06:56:36.186187 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 06:56:36.189701 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 06:56:36.192799 0 11 4 | B1->B0 | 2d2c 3232 | 1 0 | (1 1) (1 1)
1529 06:56:36.199560 0 11 8 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
1530 06:56:36.203226 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 06:56:36.206262 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 06:56:36.212836 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 06:56:36.216038 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 06:56:36.219998 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 06:56:36.226001 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 06:56:36.229237 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1537 06:56:36.232776 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 06:56:36.239535 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 06:56:36.242907 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 06:56:36.246416 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 06:56:36.252947 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 06:56:36.255999 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 06:56:36.259885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 06:56:36.262999 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 06:56:36.269454 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 06:56:36.273033 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 06:56:36.275911 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 06:56:36.282979 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 06:56:36.285993 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 06:56:36.289264 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 06:56:36.296302 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 06:56:36.299565 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1553 06:56:36.302866 Total UI for P1: 0, mck2ui 16
1554 06:56:36.306109 best dqsien dly found for B1: ( 0, 14, 2)
1555 06:56:36.309513 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1556 06:56:36.316213 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 06:56:36.316307 Total UI for P1: 0, mck2ui 16
1558 06:56:36.322410 best dqsien dly found for B0: ( 0, 14, 6)
1559 06:56:36.326058 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1560 06:56:36.329253 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1561 06:56:36.329334
1562 06:56:36.332687 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1563 06:56:36.335965 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1564 06:56:36.339772 [Gating] SW calibration Done
1565 06:56:36.339852 ==
1566 06:56:36.343168 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 06:56:36.345993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 06:56:36.346073 ==
1569 06:56:36.349691 RX Vref Scan: 0
1570 06:56:36.349771
1571 06:56:36.349835 RX Vref 0 -> 0, step: 1
1572 06:56:36.349895
1573 06:56:36.353020 RX Delay -130 -> 252, step: 16
1574 06:56:36.356203 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1575 06:56:36.362757 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1576 06:56:36.366526 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1577 06:56:36.370278 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1578 06:56:36.372656 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1579 06:56:36.376048 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1580 06:56:36.379598 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1581 06:56:36.386104 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1582 06:56:36.390016 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1583 06:56:36.393280 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1584 06:56:36.396211 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1585 06:56:36.399598 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1586 06:56:36.406466 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1587 06:56:36.409559 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1588 06:56:36.412915 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1589 06:56:36.416159 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1590 06:56:36.416329 ==
1591 06:56:36.419706 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 06:56:36.426297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 06:56:36.426447 ==
1594 06:56:36.426565 DQS Delay:
1595 06:56:36.430055 DQS0 = 0, DQS1 = 0
1596 06:56:36.430203 DQM Delay:
1597 06:56:36.430321 DQM0 = 93, DQM1 = 87
1598 06:56:36.433283 DQ Delay:
1599 06:56:36.436824 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1600 06:56:36.439980 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1601 06:56:36.443780 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1602 06:56:36.446845 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1603 06:56:36.446998
1604 06:56:36.447116
1605 06:56:36.447224 ==
1606 06:56:36.450139 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 06:56:36.453365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 06:56:36.453515 ==
1609 06:56:36.453634
1610 06:56:36.453744
1611 06:56:36.456610 TX Vref Scan disable
1612 06:56:36.456761 == TX Byte 0 ==
1613 06:56:36.463136 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1614 06:56:36.467150 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1615 06:56:36.467300 == TX Byte 1 ==
1616 06:56:36.473424 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1617 06:56:36.476537 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1618 06:56:36.476687 ==
1619 06:56:36.480241 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 06:56:36.483427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 06:56:36.483656 ==
1622 06:56:36.494503 TX Vref=22, minBit 11, minWin=26, winSum=438
1623 06:56:36.501478 TX Vref=24, minBit 0, minWin=27, winSum=442
1624 06:56:36.504752 TX Vref=26, minBit 1, minWin=27, winSum=446
1625 06:56:36.508110 TX Vref=28, minBit 1, minWin=27, winSum=449
1626 06:56:36.511332 TX Vref=30, minBit 1, minWin=27, winSum=452
1627 06:56:36.514541 TX Vref=32, minBit 1, minWin=27, winSum=447
1628 06:56:36.521124 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
1629 06:56:36.521421
1630 06:56:36.524705 Final TX Range 1 Vref 30
1631 06:56:36.524999
1632 06:56:36.525231 ==
1633 06:56:36.527856 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 06:56:36.531728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 06:56:36.532025 ==
1636 06:56:36.532261
1637 06:56:36.532504
1638 06:56:36.534861 TX Vref Scan disable
1639 06:56:36.538186 == TX Byte 0 ==
1640 06:56:36.541303 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1641 06:56:36.544654 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1642 06:56:36.548185 == TX Byte 1 ==
1643 06:56:36.551635 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1644 06:56:36.554970 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1645 06:56:36.555372
1646 06:56:36.558539 [DATLAT]
1647 06:56:36.558836 Freq=800, CH1 RK0
1648 06:56:36.559071
1649 06:56:36.561921 DATLAT Default: 0xa
1650 06:56:36.562298 0, 0xFFFF, sum = 0
1651 06:56:36.565320 1, 0xFFFF, sum = 0
1652 06:56:36.565836 2, 0xFFFF, sum = 0
1653 06:56:36.568349 3, 0xFFFF, sum = 0
1654 06:56:36.568771 4, 0xFFFF, sum = 0
1655 06:56:36.571812 5, 0xFFFF, sum = 0
1656 06:56:36.572231 6, 0xFFFF, sum = 0
1657 06:56:36.575315 7, 0xFFFF, sum = 0
1658 06:56:36.575825 8, 0xFFFF, sum = 0
1659 06:56:36.578023 9, 0x0, sum = 1
1660 06:56:36.578593 10, 0x0, sum = 2
1661 06:56:36.581685 11, 0x0, sum = 3
1662 06:56:36.582257 12, 0x0, sum = 4
1663 06:56:36.582763 best_step = 10
1664 06:56:36.585194
1665 06:56:36.585599 ==
1666 06:56:36.588346 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 06:56:36.591679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 06:56:36.592204 ==
1669 06:56:36.592668 RX Vref Scan: 1
1670 06:56:36.592986
1671 06:56:36.594821 Set Vref Range= 32 -> 127
1672 06:56:36.595408
1673 06:56:36.598010 RX Vref 32 -> 127, step: 1
1674 06:56:36.598584
1675 06:56:36.601951 RX Delay -79 -> 252, step: 8
1676 06:56:36.602360
1677 06:56:36.604996 Set Vref, RX VrefLevel [Byte0]: 32
1678 06:56:36.608415 [Byte1]: 32
1679 06:56:36.608807
1680 06:56:36.611893 Set Vref, RX VrefLevel [Byte0]: 33
1681 06:56:36.615317 [Byte1]: 33
1682 06:56:36.615832
1683 06:56:36.618275 Set Vref, RX VrefLevel [Byte0]: 34
1684 06:56:36.621509 [Byte1]: 34
1685 06:56:36.625195
1686 06:56:36.625603 Set Vref, RX VrefLevel [Byte0]: 35
1687 06:56:36.628231 [Byte1]: 35
1688 06:56:36.632696
1689 06:56:36.633226 Set Vref, RX VrefLevel [Byte0]: 36
1690 06:56:36.635947 [Byte1]: 36
1691 06:56:36.640410
1692 06:56:36.640999 Set Vref, RX VrefLevel [Byte0]: 37
1693 06:56:36.643594 [Byte1]: 37
1694 06:56:36.647564
1695 06:56:36.648151 Set Vref, RX VrefLevel [Byte0]: 38
1696 06:56:36.650724 [Byte1]: 38
1697 06:56:36.655031
1698 06:56:36.655335 Set Vref, RX VrefLevel [Byte0]: 39
1699 06:56:36.658493 [Byte1]: 39
1700 06:56:36.662326
1701 06:56:36.662555 Set Vref, RX VrefLevel [Byte0]: 40
1702 06:56:36.666062 [Byte1]: 40
1703 06:56:36.669848
1704 06:56:36.669995 Set Vref, RX VrefLevel [Byte0]: 41
1705 06:56:36.673275 [Byte1]: 41
1706 06:56:36.677382
1707 06:56:36.677528 Set Vref, RX VrefLevel [Byte0]: 42
1708 06:56:36.681106 [Byte1]: 42
1709 06:56:36.685372
1710 06:56:36.685519 Set Vref, RX VrefLevel [Byte0]: 43
1711 06:56:36.688575 [Byte1]: 43
1712 06:56:36.693031
1713 06:56:36.693177 Set Vref, RX VrefLevel [Byte0]: 44
1714 06:56:36.695985 [Byte1]: 44
1715 06:56:36.700557
1716 06:56:36.700745 Set Vref, RX VrefLevel [Byte0]: 45
1717 06:56:36.703788 [Byte1]: 45
1718 06:56:36.707776
1719 06:56:36.707923 Set Vref, RX VrefLevel [Byte0]: 46
1720 06:56:36.711035 [Byte1]: 46
1721 06:56:36.715526
1722 06:56:36.715729 Set Vref, RX VrefLevel [Byte0]: 47
1723 06:56:36.718939 [Byte1]: 47
1724 06:56:36.722642
1725 06:56:36.722787 Set Vref, RX VrefLevel [Byte0]: 48
1726 06:56:36.726018 [Byte1]: 48
1727 06:56:36.730362
1728 06:56:36.730562 Set Vref, RX VrefLevel [Byte0]: 49
1729 06:56:36.733867 [Byte1]: 49
1730 06:56:36.737872
1731 06:56:36.738019 Set Vref, RX VrefLevel [Byte0]: 50
1732 06:56:36.741064 [Byte1]: 50
1733 06:56:36.745377
1734 06:56:36.745582 Set Vref, RX VrefLevel [Byte0]: 51
1735 06:56:36.748867 [Byte1]: 51
1736 06:56:36.753073
1737 06:56:36.753220 Set Vref, RX VrefLevel [Byte0]: 52
1738 06:56:36.756172 [Byte1]: 52
1739 06:56:36.760678
1740 06:56:36.760844 Set Vref, RX VrefLevel [Byte0]: 53
1741 06:56:36.763894 [Byte1]: 53
1742 06:56:36.768198
1743 06:56:36.768403 Set Vref, RX VrefLevel [Byte0]: 54
1744 06:56:36.771438 [Byte1]: 54
1745 06:56:36.776028
1746 06:56:36.776445 Set Vref, RX VrefLevel [Byte0]: 55
1747 06:56:36.779560 [Byte1]: 55
1748 06:56:36.783640
1749 06:56:36.784116 Set Vref, RX VrefLevel [Byte0]: 56
1750 06:56:36.787516 [Byte1]: 56
1751 06:56:36.791201
1752 06:56:36.791652 Set Vref, RX VrefLevel [Byte0]: 57
1753 06:56:36.794503 [Byte1]: 57
1754 06:56:36.798712
1755 06:56:36.799163 Set Vref, RX VrefLevel [Byte0]: 58
1756 06:56:36.802104 [Byte1]: 58
1757 06:56:36.806664
1758 06:56:36.807356 Set Vref, RX VrefLevel [Byte0]: 59
1759 06:56:36.809521 [Byte1]: 59
1760 06:56:36.814321
1761 06:56:36.814867 Set Vref, RX VrefLevel [Byte0]: 60
1762 06:56:36.817289 [Byte1]: 60
1763 06:56:36.821338
1764 06:56:36.821788 Set Vref, RX VrefLevel [Byte0]: 61
1765 06:56:36.824470 [Byte1]: 61
1766 06:56:36.828966
1767 06:56:36.829536 Set Vref, RX VrefLevel [Byte0]: 62
1768 06:56:36.832737 [Byte1]: 62
1769 06:56:36.836552
1770 06:56:36.837039 Set Vref, RX VrefLevel [Byte0]: 63
1771 06:56:36.839813 [Byte1]: 63
1772 06:56:36.844353
1773 06:56:36.844905 Set Vref, RX VrefLevel [Byte0]: 64
1774 06:56:36.847701 [Byte1]: 64
1775 06:56:36.851942
1776 06:56:36.852550 Set Vref, RX VrefLevel [Byte0]: 65
1777 06:56:36.855118 [Byte1]: 65
1778 06:56:36.859189
1779 06:56:36.859734 Set Vref, RX VrefLevel [Byte0]: 66
1780 06:56:36.862603 [Byte1]: 66
1781 06:56:36.866694
1782 06:56:36.867244 Set Vref, RX VrefLevel [Byte0]: 67
1783 06:56:36.869911 [Byte1]: 67
1784 06:56:36.874140
1785 06:56:36.874678 Set Vref, RX VrefLevel [Byte0]: 68
1786 06:56:36.877729 [Byte1]: 68
1787 06:56:36.881948
1788 06:56:36.882401 Set Vref, RX VrefLevel [Byte0]: 69
1789 06:56:36.885024 [Byte1]: 69
1790 06:56:36.889503
1791 06:56:36.890045 Set Vref, RX VrefLevel [Byte0]: 70
1792 06:56:36.892655 [Byte1]: 70
1793 06:56:36.896842
1794 06:56:36.897298 Set Vref, RX VrefLevel [Byte0]: 71
1795 06:56:36.900002 [Byte1]: 71
1796 06:56:36.904747
1797 06:56:36.905287 Final RX Vref Byte 0 = 57 to rank0
1798 06:56:36.907581 Final RX Vref Byte 1 = 59 to rank0
1799 06:56:36.911434 Final RX Vref Byte 0 = 57 to rank1
1800 06:56:36.914691 Final RX Vref Byte 1 = 59 to rank1==
1801 06:56:36.917455 Dram Type= 6, Freq= 0, CH_1, rank 0
1802 06:56:36.924613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 06:56:36.925163 ==
1804 06:56:36.925530 DQS Delay:
1805 06:56:36.925870 DQS0 = 0, DQS1 = 0
1806 06:56:36.927596 DQM Delay:
1807 06:56:36.928051 DQM0 = 94, DQM1 = 89
1808 06:56:36.931467 DQ Delay:
1809 06:56:36.934632 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1810 06:56:36.935210 DQ4 =96, DQ5 =108, DQ6 =100, DQ7 =92
1811 06:56:36.937852 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1812 06:56:36.941037 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1813 06:56:36.945158
1814 06:56:36.945707
1815 06:56:36.951769 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
1816 06:56:36.954638 CH1 RK0: MR19=606, MR18=2F4B
1817 06:56:36.961173 CH1_RK0: MR19=0x606, MR18=0x2F4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1818 06:56:36.961711
1819 06:56:36.964599 ----->DramcWriteLeveling(PI) begin...
1820 06:56:36.965159 ==
1821 06:56:36.968171 Dram Type= 6, Freq= 0, CH_1, rank 1
1822 06:56:36.971277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1823 06:56:36.971740 ==
1824 06:56:36.974904 Write leveling (Byte 0): 27 => 27
1825 06:56:36.977609 Write leveling (Byte 1): 27 => 27
1826 06:56:36.981109 DramcWriteLeveling(PI) end<-----
1827 06:56:36.981715
1828 06:56:36.982193 ==
1829 06:56:36.984387 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 06:56:36.987984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 06:56:36.988482 ==
1832 06:56:36.991573 [Gating] SW mode calibration
1833 06:56:36.998245 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1834 06:56:37.004242 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1835 06:56:37.007610 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1836 06:56:37.011661 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1837 06:56:37.017798 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 06:56:37.021087 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 06:56:37.024236 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 06:56:37.031199 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 06:56:37.034159 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 06:56:37.037533 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 06:56:37.044298 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 06:56:37.047581 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 06:56:37.050841 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 06:56:37.054328 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 06:56:37.060766 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 06:56:37.064262 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 06:56:37.067838 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 06:56:37.074118 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 06:56:37.077666 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1852 06:56:37.080912 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1853 06:56:37.087821 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 06:56:37.090842 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 06:56:37.094338 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 06:56:37.100937 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 06:56:37.104183 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 06:56:37.107448 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 06:56:37.114264 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 06:56:37.117631 0 9 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1861 06:56:37.121087 0 9 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
1862 06:56:37.127727 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 06:56:37.131294 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 06:56:37.134067 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 06:56:37.137364 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 06:56:37.144114 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 06:56:37.147624 0 10 0 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
1868 06:56:37.150859 0 10 4 | B1->B0 | 2d2d 3131 | 1 1 | (1 0) (1 0)
1869 06:56:37.158094 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
1870 06:56:37.161458 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 06:56:37.164867 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 06:56:37.171770 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 06:56:37.175258 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 06:56:37.178244 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 06:56:37.184856 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1876 06:56:37.188266 0 11 4 | B1->B0 | 3d3d 2b2b | 0 0 | (0 0) (0 0)
1877 06:56:37.191580 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 06:56:37.198358 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 06:56:37.202065 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 06:56:37.205123 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 06:56:37.208430 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 06:56:37.215139 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 06:56:37.218504 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 06:56:37.221631 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1885 06:56:37.228346 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 06:56:37.231816 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 06:56:37.235336 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 06:56:37.241461 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 06:56:37.244814 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 06:56:37.248568 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 06:56:37.255189 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 06:56:37.258208 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 06:56:37.261627 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 06:56:37.268547 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 06:56:37.272108 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 06:56:37.275106 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 06:56:37.281462 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 06:56:37.285267 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 06:56:37.288215 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1900 06:56:37.291519 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 06:56:37.294718 Total UI for P1: 0, mck2ui 16
1902 06:56:37.298063 best dqsien dly found for B0: ( 0, 14, 2)
1903 06:56:37.301730 Total UI for P1: 0, mck2ui 16
1904 06:56:37.304978 best dqsien dly found for B1: ( 0, 14, 0)
1905 06:56:37.308804 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1906 06:56:37.311938 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1907 06:56:37.314983
1908 06:56:37.318661 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1909 06:56:37.321451 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1910 06:56:37.321676 [Gating] SW calibration Done
1911 06:56:37.324810 ==
1912 06:56:37.328602 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 06:56:37.332040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 06:56:37.332368 ==
1915 06:56:37.332566 RX Vref Scan: 0
1916 06:56:37.332835
1917 06:56:37.335268 RX Vref 0 -> 0, step: 1
1918 06:56:37.335507
1919 06:56:37.338291 RX Delay -130 -> 252, step: 16
1920 06:56:37.341785 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1921 06:56:37.344978 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1922 06:56:37.351721 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1923 06:56:37.354829 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1924 06:56:37.358213 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1925 06:56:37.361493 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1926 06:56:37.364820 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1927 06:56:37.368399 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1928 06:56:37.375033 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1929 06:56:37.378389 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1930 06:56:37.381781 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1931 06:56:37.385077 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1932 06:56:37.388861 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1933 06:56:37.395262 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1934 06:56:37.398341 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1935 06:56:37.401769 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1936 06:56:37.401919 ==
1937 06:56:37.405058 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 06:56:37.408659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 06:56:37.408811 ==
1940 06:56:37.412057 DQS Delay:
1941 06:56:37.412206 DQS0 = 0, DQS1 = 0
1942 06:56:37.415280 DQM Delay:
1943 06:56:37.415430 DQM0 = 91, DQM1 = 87
1944 06:56:37.415550 DQ Delay:
1945 06:56:37.418538 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1946 06:56:37.422619 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1947 06:56:37.425516 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1948 06:56:37.428591 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1949 06:56:37.428774
1950 06:56:37.428899
1951 06:56:37.432029 ==
1952 06:56:37.435527 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 06:56:37.438441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 06:56:37.438593 ==
1955 06:56:37.438712
1956 06:56:37.438824
1957 06:56:37.441839 TX Vref Scan disable
1958 06:56:37.442068 == TX Byte 0 ==
1959 06:56:37.445524 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1960 06:56:37.452442 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1961 06:56:37.452720 == TX Byte 1 ==
1962 06:56:37.455410 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1963 06:56:37.461994 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1964 06:56:37.462385 ==
1965 06:56:37.465825 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 06:56:37.469140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 06:56:37.469679 ==
1968 06:56:37.482477 TX Vref=22, minBit 1, minWin=26, winSum=440
1969 06:56:37.485714 TX Vref=24, minBit 0, minWin=27, winSum=443
1970 06:56:37.489192 TX Vref=26, minBit 2, minWin=27, winSum=448
1971 06:56:37.492658 TX Vref=28, minBit 2, minWin=27, winSum=449
1972 06:56:37.495889 TX Vref=30, minBit 2, minWin=27, winSum=451
1973 06:56:37.498800 TX Vref=32, minBit 2, minWin=27, winSum=447
1974 06:56:37.505482 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
1975 06:56:37.505940
1976 06:56:37.508834 Final TX Range 1 Vref 30
1977 06:56:37.509289
1978 06:56:37.509643 ==
1979 06:56:37.512559 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 06:56:37.516149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 06:56:37.516747 ==
1982 06:56:37.517113
1983 06:56:37.517448
1984 06:56:37.519165 TX Vref Scan disable
1985 06:56:37.522687 == TX Byte 0 ==
1986 06:56:37.525587 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1987 06:56:37.528663 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1988 06:56:37.532760 == TX Byte 1 ==
1989 06:56:37.535871 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1990 06:56:37.539069 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1991 06:56:37.539534
1992 06:56:37.542014 [DATLAT]
1993 06:56:37.542429 Freq=800, CH1 RK1
1994 06:56:37.542761
1995 06:56:37.545971 DATLAT Default: 0xa
1996 06:56:37.546384 0, 0xFFFF, sum = 0
1997 06:56:37.549103 1, 0xFFFF, sum = 0
1998 06:56:37.549565 2, 0xFFFF, sum = 0
1999 06:56:37.552420 3, 0xFFFF, sum = 0
2000 06:56:37.552838 4, 0xFFFF, sum = 0
2001 06:56:37.555716 5, 0xFFFF, sum = 0
2002 06:56:37.556132 6, 0xFFFF, sum = 0
2003 06:56:37.559515 7, 0xFFFF, sum = 0
2004 06:56:37.560030 8, 0xFFFF, sum = 0
2005 06:56:37.562426 9, 0x0, sum = 1
2006 06:56:37.562864 10, 0x0, sum = 2
2007 06:56:37.565463 11, 0x0, sum = 3
2008 06:56:37.565879 12, 0x0, sum = 4
2009 06:56:37.568814 best_step = 10
2010 06:56:37.569316
2011 06:56:37.569649 ==
2012 06:56:37.572456 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 06:56:37.576164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 06:56:37.576796 ==
2015 06:56:37.579425 RX Vref Scan: 0
2016 06:56:37.579971
2017 06:56:37.580397 RX Vref 0 -> 0, step: 1
2018 06:56:37.580750
2019 06:56:37.582417 RX Delay -79 -> 252, step: 8
2020 06:56:37.586169 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2021 06:56:37.592508 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2022 06:56:37.596095 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2023 06:56:37.599627 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2024 06:56:37.602976 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2025 06:56:37.606412 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2026 06:56:37.609154 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2027 06:56:37.615869 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2028 06:56:37.619487 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2029 06:56:37.623125 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2030 06:56:37.625992 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
2031 06:56:37.629996 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2032 06:56:37.636099 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2033 06:56:37.639404 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2034 06:56:37.642982 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2035 06:56:37.646659 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2036 06:56:37.647209 ==
2037 06:56:37.649747 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 06:56:37.652969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 06:56:37.656253 ==
2040 06:56:37.656866 DQS Delay:
2041 06:56:37.657233 DQS0 = 0, DQS1 = 0
2042 06:56:37.659826 DQM Delay:
2043 06:56:37.660428 DQM0 = 97, DQM1 = 91
2044 06:56:37.660985 DQ Delay:
2045 06:56:37.663330 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2046 06:56:37.666524 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2047 06:56:37.669708 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2048 06:56:37.673068 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2049 06:56:37.676634
2050 06:56:37.677087
2051 06:56:37.682815 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2052 06:56:37.686303 CH1 RK1: MR19=606, MR18=4A13
2053 06:56:37.692795 CH1_RK1: MR19=0x606, MR18=0x4A13, DQSOSC=391, MR23=63, INC=96, DEC=64
2054 06:56:37.696149 [RxdqsGatingPostProcess] freq 800
2055 06:56:37.699190 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2056 06:56:37.702745 Pre-setting of DQS Precalculation
2057 06:56:37.710066 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2058 06:56:37.716507 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2059 06:56:37.723613 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2060 06:56:37.724129
2061 06:56:37.724520
2062 06:56:37.726581 [Calibration Summary] 1600 Mbps
2063 06:56:37.726996 CH 0, Rank 0
2064 06:56:37.729704 SW Impedance : PASS
2065 06:56:37.730116 DUTY Scan : NO K
2066 06:56:37.733386 ZQ Calibration : PASS
2067 06:56:37.736548 Jitter Meter : NO K
2068 06:56:37.737053 CBT Training : PASS
2069 06:56:37.740351 Write leveling : PASS
2070 06:56:37.742994 RX DQS gating : PASS
2071 06:56:37.743406 RX DQ/DQS(RDDQC) : PASS
2072 06:56:37.746463 TX DQ/DQS : PASS
2073 06:56:37.749564 RX DATLAT : PASS
2074 06:56:37.750010 RX DQ/DQS(Engine): PASS
2075 06:56:37.753500 TX OE : NO K
2076 06:56:37.753913 All Pass.
2077 06:56:37.754239
2078 06:56:37.756638 CH 0, Rank 1
2079 06:56:37.757053 SW Impedance : PASS
2080 06:56:37.759791 DUTY Scan : NO K
2081 06:56:37.763816 ZQ Calibration : PASS
2082 06:56:37.764231 Jitter Meter : NO K
2083 06:56:37.766297 CBT Training : PASS
2084 06:56:37.766710 Write leveling : PASS
2085 06:56:37.769775 RX DQS gating : PASS
2086 06:56:37.773517 RX DQ/DQS(RDDQC) : PASS
2087 06:56:37.773932 TX DQ/DQS : PASS
2088 06:56:37.776784 RX DATLAT : PASS
2089 06:56:37.779647 RX DQ/DQS(Engine): PASS
2090 06:56:37.780060 TX OE : NO K
2091 06:56:37.783048 All Pass.
2092 06:56:37.783458
2093 06:56:37.783785 CH 1, Rank 0
2094 06:56:37.786338 SW Impedance : PASS
2095 06:56:37.786756 DUTY Scan : NO K
2096 06:56:37.790284 ZQ Calibration : PASS
2097 06:56:37.793367 Jitter Meter : NO K
2098 06:56:37.793881 CBT Training : PASS
2099 06:56:37.796831 Write leveling : PASS
2100 06:56:37.799857 RX DQS gating : PASS
2101 06:56:37.800269 RX DQ/DQS(RDDQC) : PASS
2102 06:56:37.803302 TX DQ/DQS : PASS
2103 06:56:37.803721 RX DATLAT : PASS
2104 06:56:37.806375 RX DQ/DQS(Engine): PASS
2105 06:56:37.810503 TX OE : NO K
2106 06:56:37.811009 All Pass.
2107 06:56:37.811340
2108 06:56:37.811647 CH 1, Rank 1
2109 06:56:37.813304 SW Impedance : PASS
2110 06:56:37.816556 DUTY Scan : NO K
2111 06:56:37.816968 ZQ Calibration : PASS
2112 06:56:37.819664 Jitter Meter : NO K
2113 06:56:37.823178 CBT Training : PASS
2114 06:56:37.823693 Write leveling : PASS
2115 06:56:37.827104 RX DQS gating : PASS
2116 06:56:37.829935 RX DQ/DQS(RDDQC) : PASS
2117 06:56:37.830349 TX DQ/DQS : PASS
2118 06:56:37.833160 RX DATLAT : PASS
2119 06:56:37.836823 RX DQ/DQS(Engine): PASS
2120 06:56:37.837330 TX OE : NO K
2121 06:56:37.840086 All Pass.
2122 06:56:37.840720
2123 06:56:37.841065 DramC Write-DBI off
2124 06:56:37.843349 PER_BANK_REFRESH: Hybrid Mode
2125 06:56:37.843760 TX_TRACKING: ON
2126 06:56:37.846589 [GetDramInforAfterCalByMRR] Vendor 6.
2127 06:56:37.849881 [GetDramInforAfterCalByMRR] Revision 606.
2128 06:56:37.856503 [GetDramInforAfterCalByMRR] Revision 2 0.
2129 06:56:37.857018 MR0 0x3b3b
2130 06:56:37.857348 MR8 0x5151
2131 06:56:37.860399 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2132 06:56:37.860855
2133 06:56:37.863492 MR0 0x3b3b
2134 06:56:37.863950 MR8 0x5151
2135 06:56:37.867004 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2136 06:56:37.867460
2137 06:56:37.876589 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2138 06:56:37.880262 [FAST_K] Save calibration result to emmc
2139 06:56:37.883619 [FAST_K] Save calibration result to emmc
2140 06:56:37.886561 dram_init: config_dvfs: 1
2141 06:56:37.891215 dramc_set_vcore_voltage set vcore to 662500
2142 06:56:37.891770 Read voltage for 1200, 2
2143 06:56:37.893503 Vio18 = 0
2144 06:56:37.893959 Vcore = 662500
2145 06:56:37.894323 Vdram = 0
2146 06:56:37.896816 Vddq = 0
2147 06:56:37.897269 Vmddr = 0
2148 06:56:37.900103 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2149 06:56:37.907097 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2150 06:56:37.910212 MEM_TYPE=3, freq_sel=15
2151 06:56:37.913437 sv_algorithm_assistance_LP4_1600
2152 06:56:37.916646 ============ PULL DRAM RESETB DOWN ============
2153 06:56:37.920595 ========== PULL DRAM RESETB DOWN end =========
2154 06:56:37.926903 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2155 06:56:37.929993 ===================================
2156 06:56:37.930413 LPDDR4 DRAM CONFIGURATION
2157 06:56:37.933290 ===================================
2158 06:56:37.936591 EX_ROW_EN[0] = 0x0
2159 06:56:37.937005 EX_ROW_EN[1] = 0x0
2160 06:56:37.939936 LP4Y_EN = 0x0
2161 06:56:37.940379 WORK_FSP = 0x0
2162 06:56:37.944135 WL = 0x4
2163 06:56:37.944705 RL = 0x4
2164 06:56:37.947269 BL = 0x2
2165 06:56:37.947775 RPST = 0x0
2166 06:56:37.950031 RD_PRE = 0x0
2167 06:56:37.953496 WR_PRE = 0x1
2168 06:56:37.953908 WR_PST = 0x0
2169 06:56:37.957063 DBI_WR = 0x0
2170 06:56:37.957604 DBI_RD = 0x0
2171 06:56:37.960017 OTF = 0x1
2172 06:56:37.963450 ===================================
2173 06:56:37.967161 ===================================
2174 06:56:37.967577 ANA top config
2175 06:56:37.970306 ===================================
2176 06:56:37.973622 DLL_ASYNC_EN = 0
2177 06:56:37.974137 ALL_SLAVE_EN = 0
2178 06:56:37.976915 NEW_RANK_MODE = 1
2179 06:56:37.980186 DLL_IDLE_MODE = 1
2180 06:56:37.983220 LP45_APHY_COMB_EN = 1
2181 06:56:37.987055 TX_ODT_DIS = 1
2182 06:56:37.987525 NEW_8X_MODE = 1
2183 06:56:37.990513 ===================================
2184 06:56:37.993692 ===================================
2185 06:56:37.996772 data_rate = 2400
2186 06:56:38.000364 CKR = 1
2187 06:56:38.003351 DQ_P2S_RATIO = 8
2188 06:56:38.006498 ===================================
2189 06:56:38.009840 CA_P2S_RATIO = 8
2190 06:56:38.013472 DQ_CA_OPEN = 0
2191 06:56:38.013769 DQ_SEMI_OPEN = 0
2192 06:56:38.016769 CA_SEMI_OPEN = 0
2193 06:56:38.019980 CA_FULL_RATE = 0
2194 06:56:38.023520 DQ_CKDIV4_EN = 0
2195 06:56:38.026368 CA_CKDIV4_EN = 0
2196 06:56:38.026519 CA_PREDIV_EN = 0
2197 06:56:38.029855 PH8_DLY = 17
2198 06:56:38.033030 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2199 06:56:38.036741 DQ_AAMCK_DIV = 4
2200 06:56:38.040015 CA_AAMCK_DIV = 4
2201 06:56:38.043193 CA_ADMCK_DIV = 4
2202 06:56:38.043294 DQ_TRACK_CA_EN = 0
2203 06:56:38.046523 CA_PICK = 1200
2204 06:56:38.049698 CA_MCKIO = 1200
2205 06:56:38.053102 MCKIO_SEMI = 0
2206 06:56:38.056809 PLL_FREQ = 2366
2207 06:56:38.060178 DQ_UI_PI_RATIO = 32
2208 06:56:38.063250 CA_UI_PI_RATIO = 0
2209 06:56:38.066974 ===================================
2210 06:56:38.070154 ===================================
2211 06:56:38.070236 memory_type:LPDDR4
2212 06:56:38.073008 GP_NUM : 10
2213 06:56:38.076417 SRAM_EN : 1
2214 06:56:38.076499 MD32_EN : 0
2215 06:56:38.080248 ===================================
2216 06:56:38.083401 [ANA_INIT] >>>>>>>>>>>>>>
2217 06:56:38.086409 <<<<<< [CONFIGURE PHASE]: ANA_TX
2218 06:56:38.090193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2219 06:56:38.093303 ===================================
2220 06:56:38.096436 data_rate = 2400,PCW = 0X5b00
2221 06:56:38.099715 ===================================
2222 06:56:38.103109 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2223 06:56:38.106463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2224 06:56:38.113375 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2225 06:56:38.116374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2226 06:56:38.119869 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2227 06:56:38.123118 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2228 06:56:38.126878 [ANA_INIT] flow start
2229 06:56:38.130046 [ANA_INIT] PLL >>>>>>>>
2230 06:56:38.130161 [ANA_INIT] PLL <<<<<<<<
2231 06:56:38.133707 [ANA_INIT] MIDPI >>>>>>>>
2232 06:56:38.136939 [ANA_INIT] MIDPI <<<<<<<<
2233 06:56:38.137054 [ANA_INIT] DLL >>>>>>>>
2234 06:56:38.139868 [ANA_INIT] DLL <<<<<<<<
2235 06:56:38.142938 [ANA_INIT] flow end
2236 06:56:38.146747 ============ LP4 DIFF to SE enter ============
2237 06:56:38.149651 ============ LP4 DIFF to SE exit ============
2238 06:56:38.153162 [ANA_INIT] <<<<<<<<<<<<<
2239 06:56:38.156346 [Flow] Enable top DCM control >>>>>
2240 06:56:38.160184 [Flow] Enable top DCM control <<<<<
2241 06:56:38.163279 Enable DLL master slave shuffle
2242 06:56:38.166606 ==============================================================
2243 06:56:38.169860 Gating Mode config
2244 06:56:38.176277 ==============================================================
2245 06:56:38.176402 Config description:
2246 06:56:38.186863 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2247 06:56:38.193340 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2248 06:56:38.196740 SELPH_MODE 0: By rank 1: By Phase
2249 06:56:38.203596 ==============================================================
2250 06:56:38.206894 GAT_TRACK_EN = 1
2251 06:56:38.210190 RX_GATING_MODE = 2
2252 06:56:38.213758 RX_GATING_TRACK_MODE = 2
2253 06:56:38.216728 SELPH_MODE = 1
2254 06:56:38.220049 PICG_EARLY_EN = 1
2255 06:56:38.220199 VALID_LAT_VALUE = 1
2256 06:56:38.226891 ==============================================================
2257 06:56:38.230159 Enter into Gating configuration >>>>
2258 06:56:38.233596 Exit from Gating configuration <<<<
2259 06:56:38.236938 Enter into DVFS_PRE_config >>>>>
2260 06:56:38.247921 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2261 06:56:38.250846 Exit from DVFS_PRE_config <<<<<
2262 06:56:38.253750 Enter into PICG configuration >>>>
2263 06:56:38.257532 Exit from PICG configuration <<<<
2264 06:56:38.260345 [RX_INPUT] configuration >>>>>
2265 06:56:38.264387 [RX_INPUT] configuration <<<<<
2266 06:56:38.267098 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2267 06:56:38.274250 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2268 06:56:38.280941 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2269 06:56:38.287817 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2270 06:56:38.293814 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2271 06:56:38.297289 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2272 06:56:38.304040 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2273 06:56:38.307080 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2274 06:56:38.310491 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2275 06:56:38.314240 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2276 06:56:38.317211 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2277 06:56:38.324187 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 06:56:38.327546 ===================================
2279 06:56:38.330481 LPDDR4 DRAM CONFIGURATION
2280 06:56:38.334444 ===================================
2281 06:56:38.334859 EX_ROW_EN[0] = 0x0
2282 06:56:38.337407 EX_ROW_EN[1] = 0x0
2283 06:56:38.337825 LP4Y_EN = 0x0
2284 06:56:38.340728 WORK_FSP = 0x0
2285 06:56:38.341143 WL = 0x4
2286 06:56:38.343938 RL = 0x4
2287 06:56:38.344421 BL = 0x2
2288 06:56:38.346969 RPST = 0x0
2289 06:56:38.347266 RD_PRE = 0x0
2290 06:56:38.350442 WR_PRE = 0x1
2291 06:56:38.350758 WR_PST = 0x0
2292 06:56:38.353877 DBI_WR = 0x0
2293 06:56:38.354100 DBI_RD = 0x0
2294 06:56:38.356947 OTF = 0x1
2295 06:56:38.360263 ===================================
2296 06:56:38.364016 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2297 06:56:38.367234 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2298 06:56:38.374046 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2299 06:56:38.377152 ===================================
2300 06:56:38.377326 LPDDR4 DRAM CONFIGURATION
2301 06:56:38.380611 ===================================
2302 06:56:38.383994 EX_ROW_EN[0] = 0x10
2303 06:56:38.387073 EX_ROW_EN[1] = 0x0
2304 06:56:38.387179 LP4Y_EN = 0x0
2305 06:56:38.390962 WORK_FSP = 0x0
2306 06:56:38.391069 WL = 0x4
2307 06:56:38.394161 RL = 0x4
2308 06:56:38.394241 BL = 0x2
2309 06:56:38.397351 RPST = 0x0
2310 06:56:38.397430 RD_PRE = 0x0
2311 06:56:38.400591 WR_PRE = 0x1
2312 06:56:38.400670 WR_PST = 0x0
2313 06:56:38.403800 DBI_WR = 0x0
2314 06:56:38.403901 DBI_RD = 0x0
2315 06:56:38.407523 OTF = 0x1
2316 06:56:38.410789 ===================================
2317 06:56:38.417679 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2318 06:56:38.417788 ==
2319 06:56:38.421034 Dram Type= 6, Freq= 0, CH_0, rank 0
2320 06:56:38.423875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2321 06:56:38.423955 ==
2322 06:56:38.427546 [Duty_Offset_Calibration]
2323 06:56:38.427655 B0:2 B1:1 CA:1
2324 06:56:38.427750
2325 06:56:38.430752 [DutyScan_Calibration_Flow] k_type=0
2326 06:56:38.440603
2327 06:56:38.440708 ==CLK 0==
2328 06:56:38.443775 Final CLK duty delay cell = 0
2329 06:56:38.447051 [0] MAX Duty = 5156%(X100), DQS PI = 24
2330 06:56:38.450364 [0] MIN Duty = 4844%(X100), DQS PI = 48
2331 06:56:38.450443 [0] AVG Duty = 5000%(X100)
2332 06:56:38.450506
2333 06:56:38.453966 CH0 CLK Duty spec in!! Max-Min= 312%
2334 06:56:38.460208 [DutyScan_Calibration_Flow] ====Done====
2335 06:56:38.460351
2336 06:56:38.463362 [DutyScan_Calibration_Flow] k_type=1
2337 06:56:38.478887
2338 06:56:38.478969 ==DQS 0 ==
2339 06:56:38.482039 Final DQS duty delay cell = -4
2340 06:56:38.485534 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2341 06:56:38.488859 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2342 06:56:38.492228 [-4] AVG Duty = 4953%(X100)
2343 06:56:38.492331
2344 06:56:38.492407 ==DQS 1 ==
2345 06:56:38.496270 Final DQS duty delay cell = 0
2346 06:56:38.499116 [0] MAX Duty = 5156%(X100), DQS PI = 62
2347 06:56:38.502989 [0] MIN Duty = 5000%(X100), DQS PI = 32
2348 06:56:38.506508 [0] AVG Duty = 5078%(X100)
2349 06:56:38.507028
2350 06:56:38.509417 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2351 06:56:38.510027
2352 06:56:38.513155 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2353 06:56:38.516645 [DutyScan_Calibration_Flow] ====Done====
2354 06:56:38.517161
2355 06:56:38.519763 [DutyScan_Calibration_Flow] k_type=3
2356 06:56:38.536267
2357 06:56:38.536897 ==DQM 0 ==
2358 06:56:38.539761 Final DQM duty delay cell = 0
2359 06:56:38.542892 [0] MAX Duty = 5156%(X100), DQS PI = 30
2360 06:56:38.547007 [0] MIN Duty = 4906%(X100), DQS PI = 2
2361 06:56:38.547570 [0] AVG Duty = 5031%(X100)
2362 06:56:38.550006
2363 06:56:38.550462 ==DQM 1 ==
2364 06:56:38.552944 Final DQM duty delay cell = 0
2365 06:56:38.556271 [0] MAX Duty = 5093%(X100), DQS PI = 0
2366 06:56:38.560052 [0] MIN Duty = 5031%(X100), DQS PI = 14
2367 06:56:38.560500 [0] AVG Duty = 5062%(X100)
2368 06:56:38.560829
2369 06:56:38.563461 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2370 06:56:38.566675
2371 06:56:38.569665 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2372 06:56:38.573186 [DutyScan_Calibration_Flow] ====Done====
2373 06:56:38.573744
2374 06:56:38.576961 [DutyScan_Calibration_Flow] k_type=2
2375 06:56:38.592916
2376 06:56:38.593470 ==DQ 0 ==
2377 06:56:38.595914 Final DQ duty delay cell = 0
2378 06:56:38.599498 [0] MAX Duty = 5062%(X100), DQS PI = 32
2379 06:56:38.602473 [0] MIN Duty = 4875%(X100), DQS PI = 62
2380 06:56:38.603073 [0] AVG Duty = 4968%(X100)
2381 06:56:38.603636
2382 06:56:38.605853 ==DQ 1 ==
2383 06:56:38.609433 Final DQ duty delay cell = 0
2384 06:56:38.612846 [0] MAX Duty = 5093%(X100), DQS PI = 10
2385 06:56:38.616128 [0] MIN Duty = 4969%(X100), DQS PI = 2
2386 06:56:38.616642 [0] AVG Duty = 5031%(X100)
2387 06:56:38.617008
2388 06:56:38.619335 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2389 06:56:38.619791
2390 06:56:38.623162 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2391 06:56:38.629314 [DutyScan_Calibration_Flow] ====Done====
2392 06:56:38.629771 ==
2393 06:56:38.632565 Dram Type= 6, Freq= 0, CH_1, rank 0
2394 06:56:38.636160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2395 06:56:38.636753 ==
2396 06:56:38.639703 [Duty_Offset_Calibration]
2397 06:56:38.640257 B0:1 B1:0 CA:1
2398 06:56:38.640673
2399 06:56:38.642641 [DutyScan_Calibration_Flow] k_type=0
2400 06:56:38.651618
2401 06:56:38.652126 ==CLK 0==
2402 06:56:38.655335 Final CLK duty delay cell = -4
2403 06:56:38.658614 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2404 06:56:38.662189 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2405 06:56:38.665333 [-4] AVG Duty = 4953%(X100)
2406 06:56:38.665914
2407 06:56:38.668201 CH1 CLK Duty spec in!! Max-Min= 93%
2408 06:56:38.672366 [DutyScan_Calibration_Flow] ====Done====
2409 06:56:38.672888
2410 06:56:38.675433 [DutyScan_Calibration_Flow] k_type=1
2411 06:56:38.691806
2412 06:56:38.692420 ==DQS 0 ==
2413 06:56:38.694920 Final DQS duty delay cell = 0
2414 06:56:38.698118 [0] MAX Duty = 5094%(X100), DQS PI = 26
2415 06:56:38.701377 [0] MIN Duty = 4875%(X100), DQS PI = 0
2416 06:56:38.701839 [0] AVG Duty = 4984%(X100)
2417 06:56:38.704957
2418 06:56:38.705413 ==DQS 1 ==
2419 06:56:38.708060 Final DQS duty delay cell = 0
2420 06:56:38.711185 [0] MAX Duty = 5187%(X100), DQS PI = 18
2421 06:56:38.714802 [0] MIN Duty = 4969%(X100), DQS PI = 8
2422 06:56:38.715454 [0] AVG Duty = 5078%(X100)
2423 06:56:38.717877
2424 06:56:38.721399 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2425 06:56:38.721909
2426 06:56:38.724662 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2427 06:56:38.728317 [DutyScan_Calibration_Flow] ====Done====
2428 06:56:38.728786
2429 06:56:38.731028 [DutyScan_Calibration_Flow] k_type=3
2430 06:56:38.748452
2431 06:56:38.749007 ==DQM 0 ==
2432 06:56:38.751493 Final DQM duty delay cell = 0
2433 06:56:38.754850 [0] MAX Duty = 5156%(X100), DQS PI = 6
2434 06:56:38.757849 [0] MIN Duty = 5031%(X100), DQS PI = 46
2435 06:56:38.758314 [0] AVG Duty = 5093%(X100)
2436 06:56:38.761259
2437 06:56:38.761713 ==DQM 1 ==
2438 06:56:38.764717 Final DQM duty delay cell = 0
2439 06:56:38.768236 [0] MAX Duty = 5031%(X100), DQS PI = 16
2440 06:56:38.771238 [0] MIN Duty = 4907%(X100), DQS PI = 34
2441 06:56:38.771731 [0] AVG Duty = 4969%(X100)
2442 06:56:38.772103
2443 06:56:38.778051 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2444 06:56:38.778614
2445 06:56:38.781199 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2446 06:56:38.785225 [DutyScan_Calibration_Flow] ====Done====
2447 06:56:38.785788
2448 06:56:38.788278 [DutyScan_Calibration_Flow] k_type=2
2449 06:56:38.803881
2450 06:56:38.804492 ==DQ 0 ==
2451 06:56:38.807533 Final DQ duty delay cell = -4
2452 06:56:38.810717 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2453 06:56:38.813907 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2454 06:56:38.814374 [-4] AVG Duty = 5000%(X100)
2455 06:56:38.817052
2456 06:56:38.817513 ==DQ 1 ==
2457 06:56:38.820143 Final DQ duty delay cell = 0
2458 06:56:38.823482 [0] MAX Duty = 5125%(X100), DQS PI = 20
2459 06:56:38.827495 [0] MIN Duty = 4969%(X100), DQS PI = 12
2460 06:56:38.828040 [0] AVG Duty = 5047%(X100)
2461 06:56:38.828617
2462 06:56:38.830513 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2463 06:56:38.833861
2464 06:56:38.837068 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2465 06:56:38.840588 [DutyScan_Calibration_Flow] ====Done====
2466 06:56:38.843822 nWR fixed to 30
2467 06:56:38.844346 [ModeRegInit_LP4] CH0 RK0
2468 06:56:38.847101 [ModeRegInit_LP4] CH0 RK1
2469 06:56:38.850357 [ModeRegInit_LP4] CH1 RK0
2470 06:56:38.850782 [ModeRegInit_LP4] CH1 RK1
2471 06:56:38.853849 match AC timing 7
2472 06:56:38.856773 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2473 06:56:38.860667 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2474 06:56:38.867178 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2475 06:56:38.870428 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2476 06:56:38.877018 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2477 06:56:38.877437 ==
2478 06:56:38.880904 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 06:56:38.883925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 06:56:38.884487 ==
2481 06:56:38.890572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 06:56:38.893875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2483 06:56:38.903718 [CA 0] Center 39 (8~70) winsize 63
2484 06:56:38.907153 [CA 1] Center 39 (8~70) winsize 63
2485 06:56:38.910972 [CA 2] Center 35 (5~66) winsize 62
2486 06:56:38.913876 [CA 3] Center 34 (4~65) winsize 62
2487 06:56:38.916966 [CA 4] Center 33 (3~64) winsize 62
2488 06:56:38.920472 [CA 5] Center 32 (3~62) winsize 60
2489 06:56:38.920935
2490 06:56:38.924009 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2491 06:56:38.924610
2492 06:56:38.927835 [CATrainingPosCal] consider 1 rank data
2493 06:56:38.930773 u2DelayCellTimex100 = 270/100 ps
2494 06:56:38.933862 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2495 06:56:38.937768 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2496 06:56:38.944374 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2497 06:56:38.947508 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2498 06:56:38.950616 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2499 06:56:38.953893 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2500 06:56:38.954438
2501 06:56:38.956957 CA PerBit enable=1, Macro0, CA PI delay=32
2502 06:56:38.957413
2503 06:56:38.961069 [CBTSetCACLKResult] CA Dly = 32
2504 06:56:38.961634 CS Dly: 6 (0~37)
2505 06:56:38.962006 ==
2506 06:56:38.964261 Dram Type= 6, Freq= 0, CH_0, rank 1
2507 06:56:38.970645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 06:56:38.971215 ==
2509 06:56:38.974321 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2510 06:56:38.980453 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2511 06:56:38.989552 [CA 0] Center 38 (8~69) winsize 62
2512 06:56:38.992946 [CA 1] Center 38 (8~69) winsize 62
2513 06:56:38.996089 [CA 2] Center 35 (5~66) winsize 62
2514 06:56:38.999756 [CA 3] Center 34 (4~65) winsize 62
2515 06:56:39.002868 [CA 4] Center 33 (3~64) winsize 62
2516 06:56:39.006402 [CA 5] Center 32 (2~62) winsize 61
2517 06:56:39.006863
2518 06:56:39.009680 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2519 06:56:39.010141
2520 06:56:39.012586 [CATrainingPosCal] consider 2 rank data
2521 06:56:39.016422 u2DelayCellTimex100 = 270/100 ps
2522 06:56:39.019935 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2523 06:56:39.022951 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2524 06:56:39.029668 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2525 06:56:39.033262 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2526 06:56:39.036884 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2527 06:56:39.040137 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2528 06:56:39.040761
2529 06:56:39.043309 CA PerBit enable=1, Macro0, CA PI delay=32
2530 06:56:39.043874
2531 06:56:39.046556 [CBTSetCACLKResult] CA Dly = 32
2532 06:56:39.047017 CS Dly: 6 (0~38)
2533 06:56:39.047382
2534 06:56:39.050003 ----->DramcWriteLeveling(PI) begin...
2535 06:56:39.050574 ==
2536 06:56:39.052998 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 06:56:39.059718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 06:56:39.060284 ==
2539 06:56:39.063264 Write leveling (Byte 0): 34 => 34
2540 06:56:39.066628 Write leveling (Byte 1): 28 => 28
2541 06:56:39.067191 DramcWriteLeveling(PI) end<-----
2542 06:56:39.069848
2543 06:56:39.070608 ==
2544 06:56:39.072989 Dram Type= 6, Freq= 0, CH_0, rank 0
2545 06:56:39.076936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 06:56:39.077504 ==
2547 06:56:39.080048 [Gating] SW mode calibration
2548 06:56:39.086983 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2549 06:56:39.089574 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2550 06:56:39.096744 0 15 0 | B1->B0 | 2424 3333 | 1 1 | (1 1) (1 1)
2551 06:56:39.100098 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2552 06:56:39.103506 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2553 06:56:39.110761 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2554 06:56:39.113540 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2555 06:56:39.116814 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2556 06:56:39.123531 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2557 06:56:39.127129 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
2558 06:56:39.130657 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
2559 06:56:39.133262 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 06:56:39.140214 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 06:56:39.143390 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 06:56:39.147074 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2563 06:56:39.154250 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 06:56:39.156767 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2565 06:56:39.160172 1 0 28 | B1->B0 | 2b2b 4444 | 1 0 | (0 0) (0 0)
2566 06:56:39.167165 1 1 0 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
2567 06:56:39.170494 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 06:56:39.173489 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 06:56:39.180707 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 06:56:39.184079 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 06:56:39.187392 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 06:56:39.193525 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 06:56:39.197233 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2574 06:56:39.200235 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2575 06:56:39.206960 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 06:56:39.210691 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 06:56:39.213485 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 06:56:39.216855 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 06:56:39.223822 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 06:56:39.226892 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 06:56:39.230317 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 06:56:39.237174 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 06:56:39.240927 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 06:56:39.244004 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 06:56:39.250136 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 06:56:39.253846 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 06:56:39.257225 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 06:56:39.263967 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 06:56:39.266972 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2590 06:56:39.270696 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 06:56:39.274184 Total UI for P1: 0, mck2ui 16
2592 06:56:39.277651 best dqsien dly found for B0: ( 1, 3, 28)
2593 06:56:39.280569 Total UI for P1: 0, mck2ui 16
2594 06:56:39.283884 best dqsien dly found for B1: ( 1, 3, 28)
2595 06:56:39.287147 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2596 06:56:39.290892 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2597 06:56:39.291460
2598 06:56:39.294031 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2599 06:56:39.300415 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2600 06:56:39.300968 [Gating] SW calibration Done
2601 06:56:39.301451 ==
2602 06:56:39.304170 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 06:56:39.310582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 06:56:39.311094 ==
2605 06:56:39.311571 RX Vref Scan: 0
2606 06:56:39.312019
2607 06:56:39.313667 RX Vref 0 -> 0, step: 1
2608 06:56:39.314163
2609 06:56:39.317621 RX Delay -40 -> 252, step: 8
2610 06:56:39.320537 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2611 06:56:39.323764 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2612 06:56:39.327247 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2613 06:56:39.330884 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2614 06:56:39.337077 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2615 06:56:39.340815 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2616 06:56:39.344031 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2617 06:56:39.347730 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2618 06:56:39.350606 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2619 06:56:39.357669 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2620 06:56:39.360829 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2621 06:56:39.364775 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2622 06:56:39.368045 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2623 06:56:39.370938 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2624 06:56:39.377792 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2625 06:56:39.380843 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2626 06:56:39.381298 ==
2627 06:56:39.384209 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 06:56:39.387799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 06:56:39.388258 ==
2630 06:56:39.388762 DQS Delay:
2631 06:56:39.390617 DQS0 = 0, DQS1 = 0
2632 06:56:39.391314 DQM Delay:
2633 06:56:39.393922 DQM0 = 121, DQM1 = 113
2634 06:56:39.394465 DQ Delay:
2635 06:56:39.397175 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2636 06:56:39.400984 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2637 06:56:39.404184 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2638 06:56:39.407202 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2639 06:56:39.411042
2640 06:56:39.411457
2641 06:56:39.411786 ==
2642 06:56:39.414144 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 06:56:39.417372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 06:56:39.417794 ==
2645 06:56:39.418126
2646 06:56:39.418527
2647 06:56:39.420637 TX Vref Scan disable
2648 06:56:39.421050 == TX Byte 0 ==
2649 06:56:39.427671 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2650 06:56:39.431020 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2651 06:56:39.431544 == TX Byte 1 ==
2652 06:56:39.437478 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2653 06:56:39.440909 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2654 06:56:39.441436 ==
2655 06:56:39.444020 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 06:56:39.447747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 06:56:39.448268 ==
2658 06:56:39.460359 TX Vref=22, minBit 0, minWin=24, winSum=406
2659 06:56:39.463941 TX Vref=24, minBit 3, minWin=25, winSum=416
2660 06:56:39.467156 TX Vref=26, minBit 7, minWin=25, winSum=420
2661 06:56:39.470577 TX Vref=28, minBit 0, minWin=26, winSum=420
2662 06:56:39.474304 TX Vref=30, minBit 0, minWin=26, winSum=423
2663 06:56:39.477207 TX Vref=32, minBit 0, minWin=26, winSum=424
2664 06:56:39.484281 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 32
2665 06:56:39.484889
2666 06:56:39.487483 Final TX Range 1 Vref 32
2667 06:56:39.488042
2668 06:56:39.488465 ==
2669 06:56:39.490719 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 06:56:39.494266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 06:56:39.494731 ==
2672 06:56:39.495096
2673 06:56:39.495432
2674 06:56:39.497199 TX Vref Scan disable
2675 06:56:39.500985 == TX Byte 0 ==
2676 06:56:39.504012 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2677 06:56:39.507490 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2678 06:56:39.510829 == TX Byte 1 ==
2679 06:56:39.514131 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2680 06:56:39.517206 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2681 06:56:39.517707
2682 06:56:39.520979 [DATLAT]
2683 06:56:39.521439 Freq=1200, CH0 RK0
2684 06:56:39.521806
2685 06:56:39.524042 DATLAT Default: 0xd
2686 06:56:39.524544 0, 0xFFFF, sum = 0
2687 06:56:39.527458 1, 0xFFFF, sum = 0
2688 06:56:39.528025 2, 0xFFFF, sum = 0
2689 06:56:39.531144 3, 0xFFFF, sum = 0
2690 06:56:39.531764 4, 0xFFFF, sum = 0
2691 06:56:39.533858 5, 0xFFFF, sum = 0
2692 06:56:39.534480 6, 0xFFFF, sum = 0
2693 06:56:39.537572 7, 0xFFFF, sum = 0
2694 06:56:39.538041 8, 0xFFFF, sum = 0
2695 06:56:39.540626 9, 0xFFFF, sum = 0
2696 06:56:39.541096 10, 0xFFFF, sum = 0
2697 06:56:39.543885 11, 0xFFFF, sum = 0
2698 06:56:39.544386 12, 0x0, sum = 1
2699 06:56:39.547688 13, 0x0, sum = 2
2700 06:56:39.548254 14, 0x0, sum = 3
2701 06:56:39.550876 15, 0x0, sum = 4
2702 06:56:39.551441 best_step = 13
2703 06:56:39.551807
2704 06:56:39.552142 ==
2705 06:56:39.554879 Dram Type= 6, Freq= 0, CH_0, rank 0
2706 06:56:39.560970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2707 06:56:39.561537 ==
2708 06:56:39.561924 RX Vref Scan: 1
2709 06:56:39.562271
2710 06:56:39.564574 Set Vref Range= 32 -> 127
2711 06:56:39.565137
2712 06:56:39.567342 RX Vref 32 -> 127, step: 1
2713 06:56:39.567799
2714 06:56:39.568163 RX Delay -13 -> 252, step: 4
2715 06:56:39.571009
2716 06:56:39.571571 Set Vref, RX VrefLevel [Byte0]: 32
2717 06:56:39.573912 [Byte1]: 32
2718 06:56:39.578520
2719 06:56:39.579075 Set Vref, RX VrefLevel [Byte0]: 33
2720 06:56:39.582187 [Byte1]: 33
2721 06:56:39.586665
2722 06:56:39.587223 Set Vref, RX VrefLevel [Byte0]: 34
2723 06:56:39.589775 [Byte1]: 34
2724 06:56:39.594212
2725 06:56:39.594780 Set Vref, RX VrefLevel [Byte0]: 35
2726 06:56:39.597642 [Byte1]: 35
2727 06:56:39.602593
2728 06:56:39.603051 Set Vref, RX VrefLevel [Byte0]: 36
2729 06:56:39.605811 [Byte1]: 36
2730 06:56:39.610434
2731 06:56:39.610988 Set Vref, RX VrefLevel [Byte0]: 37
2732 06:56:39.613669 [Byte1]: 37
2733 06:56:39.617729
2734 06:56:39.618279 Set Vref, RX VrefLevel [Byte0]: 38
2735 06:56:39.621391 [Byte1]: 38
2736 06:56:39.626266
2737 06:56:39.626827 Set Vref, RX VrefLevel [Byte0]: 39
2738 06:56:39.629538 [Byte1]: 39
2739 06:56:39.633884
2740 06:56:39.634341 Set Vref, RX VrefLevel [Byte0]: 40
2741 06:56:39.637590 [Byte1]: 40
2742 06:56:39.641457
2743 06:56:39.642038 Set Vref, RX VrefLevel [Byte0]: 41
2744 06:56:39.644626 [Byte1]: 41
2745 06:56:39.649394
2746 06:56:39.649851 Set Vref, RX VrefLevel [Byte0]: 42
2747 06:56:39.652979 [Byte1]: 42
2748 06:56:39.657102
2749 06:56:39.657674 Set Vref, RX VrefLevel [Byte0]: 43
2750 06:56:39.660703 [Byte1]: 43
2751 06:56:39.665049
2752 06:56:39.665621 Set Vref, RX VrefLevel [Byte0]: 44
2753 06:56:39.668554 [Byte1]: 44
2754 06:56:39.673190
2755 06:56:39.673605 Set Vref, RX VrefLevel [Byte0]: 45
2756 06:56:39.676280 [Byte1]: 45
2757 06:56:39.681156
2758 06:56:39.681569 Set Vref, RX VrefLevel [Byte0]: 46
2759 06:56:39.684786 [Byte1]: 46
2760 06:56:39.688989
2761 06:56:39.689513 Set Vref, RX VrefLevel [Byte0]: 47
2762 06:56:39.692128 [Byte1]: 47
2763 06:56:39.696623
2764 06:56:39.697040 Set Vref, RX VrefLevel [Byte0]: 48
2765 06:56:39.700045 [Byte1]: 48
2766 06:56:39.704876
2767 06:56:39.705294 Set Vref, RX VrefLevel [Byte0]: 49
2768 06:56:39.708422 [Byte1]: 49
2769 06:56:39.712996
2770 06:56:39.713516 Set Vref, RX VrefLevel [Byte0]: 50
2771 06:56:39.716126 [Byte1]: 50
2772 06:56:39.720276
2773 06:56:39.720776 Set Vref, RX VrefLevel [Byte0]: 51
2774 06:56:39.723676 [Byte1]: 51
2775 06:56:39.728364
2776 06:56:39.728872 Set Vref, RX VrefLevel [Byte0]: 52
2777 06:56:39.731701 [Byte1]: 52
2778 06:56:39.736517
2779 06:56:39.737047 Set Vref, RX VrefLevel [Byte0]: 53
2780 06:56:39.739808 [Byte1]: 53
2781 06:56:39.744129
2782 06:56:39.744740 Set Vref, RX VrefLevel [Byte0]: 54
2783 06:56:39.747608 [Byte1]: 54
2784 06:56:39.752622
2785 06:56:39.753196 Set Vref, RX VrefLevel [Byte0]: 55
2786 06:56:39.755484 [Byte1]: 55
2787 06:56:39.760017
2788 06:56:39.760622 Set Vref, RX VrefLevel [Byte0]: 56
2789 06:56:39.763012 [Byte1]: 56
2790 06:56:39.767854
2791 06:56:39.768351 Set Vref, RX VrefLevel [Byte0]: 57
2792 06:56:39.771353 [Byte1]: 57
2793 06:56:39.776197
2794 06:56:39.776785 Set Vref, RX VrefLevel [Byte0]: 58
2795 06:56:39.779373 [Byte1]: 58
2796 06:56:39.783508
2797 06:56:39.783968 Set Vref, RX VrefLevel [Byte0]: 59
2798 06:56:39.787464 [Byte1]: 59
2799 06:56:39.791959
2800 06:56:39.792560 Set Vref, RX VrefLevel [Byte0]: 60
2801 06:56:39.795397 [Byte1]: 60
2802 06:56:39.799516
2803 06:56:39.800217 Set Vref, RX VrefLevel [Byte0]: 61
2804 06:56:39.802727 [Byte1]: 61
2805 06:56:39.807057
2806 06:56:39.807532 Set Vref, RX VrefLevel [Byte0]: 62
2807 06:56:39.810830 [Byte1]: 62
2808 06:56:39.815353
2809 06:56:39.815809 Set Vref, RX VrefLevel [Byte0]: 63
2810 06:56:39.818684 [Byte1]: 63
2811 06:56:39.823190
2812 06:56:39.823649 Set Vref, RX VrefLevel [Byte0]: 64
2813 06:56:39.826641 [Byte1]: 64
2814 06:56:39.831078
2815 06:56:39.831627 Set Vref, RX VrefLevel [Byte0]: 65
2816 06:56:39.833999 [Byte1]: 65
2817 06:56:39.839061
2818 06:56:39.839562 Set Vref, RX VrefLevel [Byte0]: 66
2819 06:56:39.842461 [Byte1]: 66
2820 06:56:39.847467
2821 06:56:39.848015 Set Vref, RX VrefLevel [Byte0]: 67
2822 06:56:39.849740 [Byte1]: 67
2823 06:56:39.854872
2824 06:56:39.855416 Set Vref, RX VrefLevel [Byte0]: 68
2825 06:56:39.857989 [Byte1]: 68
2826 06:56:39.862740
2827 06:56:39.863142 Final RX Vref Byte 0 = 54 to rank0
2828 06:56:39.866380 Final RX Vref Byte 1 = 46 to rank0
2829 06:56:39.869677 Final RX Vref Byte 0 = 54 to rank1
2830 06:56:39.873000 Final RX Vref Byte 1 = 46 to rank1==
2831 06:56:39.876153 Dram Type= 6, Freq= 0, CH_0, rank 0
2832 06:56:39.882921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 06:56:39.883506 ==
2834 06:56:39.883888 DQS Delay:
2835 06:56:39.884232 DQS0 = 0, DQS1 = 0
2836 06:56:39.886380 DQM Delay:
2837 06:56:39.886931 DQM0 = 120, DQM1 = 110
2838 06:56:39.889191 DQ Delay:
2839 06:56:39.892768 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2840 06:56:39.896402 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =124
2841 06:56:39.899164 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =102
2842 06:56:39.902298 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2843 06:56:39.902760
2844 06:56:39.903125
2845 06:56:39.909237 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2846 06:56:39.912401 CH0 RK0: MR19=404, MR18=1610
2847 06:56:39.919305 CH0_RK0: MR19=0x404, MR18=0x1610, DQSOSC=401, MR23=63, INC=40, DEC=27
2848 06:56:39.919848
2849 06:56:39.922560 ----->DramcWriteLeveling(PI) begin...
2850 06:56:39.923042 ==
2851 06:56:39.925512 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 06:56:39.929407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 06:56:39.932405 ==
2854 06:56:39.932870 Write leveling (Byte 0): 35 => 35
2855 06:56:39.936281 Write leveling (Byte 1): 29 => 29
2856 06:56:39.939785 DramcWriteLeveling(PI) end<-----
2857 06:56:39.940385
2858 06:56:39.940763 ==
2859 06:56:39.943095 Dram Type= 6, Freq= 0, CH_0, rank 1
2860 06:56:39.949143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 06:56:39.949610 ==
2862 06:56:39.949976 [Gating] SW mode calibration
2863 06:56:39.959196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2864 06:56:39.963179 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2865 06:56:39.966113 0 15 0 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
2866 06:56:39.973061 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 06:56:39.976094 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 06:56:39.979231 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 06:56:39.985811 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 06:56:39.989045 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 06:56:39.993295 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 06:56:39.999447 0 15 28 | B1->B0 | 2f2f 2e2e | 0 0 | (0 1) (0 1)
2873 06:56:40.002354 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 06:56:40.006007 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 06:56:40.013098 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 06:56:40.016097 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 06:56:40.019264 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 06:56:40.026009 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 06:56:40.029377 1 0 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
2880 06:56:40.032671 1 0 28 | B1->B0 | 3e3e 3a3a | 0 1 | (0 0) (0 0)
2881 06:56:40.036008 1 1 0 | B1->B0 | 4646 4544 | 0 1 | (0 0) (0 0)
2882 06:56:40.042711 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 06:56:40.045888 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 06:56:40.049561 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 06:56:40.055917 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 06:56:40.059287 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 06:56:40.062850 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 06:56:40.069756 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2889 06:56:40.073188 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2890 06:56:40.076321 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 06:56:40.082985 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 06:56:40.086779 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 06:56:40.090312 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 06:56:40.096459 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 06:56:40.099641 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 06:56:40.102901 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 06:56:40.106115 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 06:56:40.113233 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 06:56:40.116568 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 06:56:40.119503 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 06:56:40.126722 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 06:56:40.130265 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 06:56:40.133199 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 06:56:40.139845 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2905 06:56:40.143068 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2906 06:56:40.146478 Total UI for P1: 0, mck2ui 16
2907 06:56:40.150191 best dqsien dly found for B1: ( 1, 3, 28)
2908 06:56:40.153206 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 06:56:40.156469 Total UI for P1: 0, mck2ui 16
2910 06:56:40.159937 best dqsien dly found for B0: ( 1, 3, 30)
2911 06:56:40.163859 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2912 06:56:40.166755 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2913 06:56:40.167345
2914 06:56:40.170276 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2915 06:56:40.176412 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2916 06:56:40.176877 [Gating] SW calibration Done
2917 06:56:40.177245 ==
2918 06:56:40.179798 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 06:56:40.186751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 06:56:40.187306 ==
2921 06:56:40.187802 RX Vref Scan: 0
2922 06:56:40.188161
2923 06:56:40.189575 RX Vref 0 -> 0, step: 1
2924 06:56:40.190036
2925 06:56:40.192930 RX Delay -40 -> 252, step: 8
2926 06:56:40.196281 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2927 06:56:40.199837 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2928 06:56:40.202679 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2929 06:56:40.210014 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2930 06:56:40.212933 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2931 06:56:40.216835 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2932 06:56:40.219801 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
2933 06:56:40.222872 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2934 06:56:40.229809 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2935 06:56:40.233309 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2936 06:56:40.236691 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2937 06:56:40.239686 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2938 06:56:40.243285 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2939 06:56:40.249737 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2940 06:56:40.253146 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2941 06:56:40.256421 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2942 06:56:40.256975 ==
2943 06:56:40.259525 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 06:56:40.263215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 06:56:40.263754 ==
2946 06:56:40.266413 DQS Delay:
2947 06:56:40.266872 DQS0 = 0, DQS1 = 0
2948 06:56:40.269813 DQM Delay:
2949 06:56:40.270366 DQM0 = 122, DQM1 = 111
2950 06:56:40.270736 DQ Delay:
2951 06:56:40.273683 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2952 06:56:40.279670 DQ4 =127, DQ5 =119, DQ6 =123, DQ7 =127
2953 06:56:40.282921 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
2954 06:56:40.286332 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2955 06:56:40.286796
2956 06:56:40.287160
2957 06:56:40.287495 ==
2958 06:56:40.290275 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 06:56:40.293272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 06:56:40.293824 ==
2961 06:56:40.294189
2962 06:56:40.294527
2963 06:56:40.296405 TX Vref Scan disable
2964 06:56:40.299708 == TX Byte 0 ==
2965 06:56:40.303039 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2966 06:56:40.306512 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2967 06:56:40.310233 == TX Byte 1 ==
2968 06:56:40.313737 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2969 06:56:40.316548 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2970 06:56:40.317107 ==
2971 06:56:40.319941 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 06:56:40.323597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 06:56:40.324061 ==
2974 06:56:40.336984 TX Vref=22, minBit 3, minWin=24, winSum=412
2975 06:56:40.340044 TX Vref=24, minBit 1, minWin=25, winSum=419
2976 06:56:40.343136 TX Vref=26, minBit 1, minWin=25, winSum=419
2977 06:56:40.346640 TX Vref=28, minBit 1, minWin=26, winSum=427
2978 06:56:40.350439 TX Vref=30, minBit 5, minWin=25, winSum=429
2979 06:56:40.353809 TX Vref=32, minBit 5, minWin=25, winSum=427
2980 06:56:40.360469 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
2981 06:56:40.361022
2982 06:56:40.363641 Final TX Range 1 Vref 28
2983 06:56:40.364194
2984 06:56:40.364609 ==
2985 06:56:40.366882 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 06:56:40.370179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 06:56:40.370736 ==
2988 06:56:40.371100
2989 06:56:40.371436
2990 06:56:40.373755 TX Vref Scan disable
2991 06:56:40.377155 == TX Byte 0 ==
2992 06:56:40.380040 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2993 06:56:40.383843 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2994 06:56:40.387092 == TX Byte 1 ==
2995 06:56:40.390245 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2996 06:56:40.393718 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2997 06:56:40.394272
2998 06:56:40.396763 [DATLAT]
2999 06:56:40.397238 Freq=1200, CH0 RK1
3000 06:56:40.397855
3001 06:56:40.400251 DATLAT Default: 0xd
3002 06:56:40.400760 0, 0xFFFF, sum = 0
3003 06:56:40.403558 1, 0xFFFF, sum = 0
3004 06:56:40.404028 2, 0xFFFF, sum = 0
3005 06:56:40.406750 3, 0xFFFF, sum = 0
3006 06:56:40.407216 4, 0xFFFF, sum = 0
3007 06:56:40.410002 5, 0xFFFF, sum = 0
3008 06:56:40.410493 6, 0xFFFF, sum = 0
3009 06:56:40.414035 7, 0xFFFF, sum = 0
3010 06:56:40.414845 8, 0xFFFF, sum = 0
3011 06:56:40.416976 9, 0xFFFF, sum = 0
3012 06:56:40.417488 10, 0xFFFF, sum = 0
3013 06:56:40.420198 11, 0xFFFF, sum = 0
3014 06:56:40.420814 12, 0x0, sum = 1
3015 06:56:40.423941 13, 0x0, sum = 2
3016 06:56:40.424835 14, 0x0, sum = 3
3017 06:56:40.426804 15, 0x0, sum = 4
3018 06:56:40.427466 best_step = 13
3019 06:56:40.427987
3020 06:56:40.428641 ==
3021 06:56:40.429927 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 06:56:40.436584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 06:56:40.436899 ==
3024 06:56:40.437140 RX Vref Scan: 0
3025 06:56:40.437365
3026 06:56:40.440252 RX Vref 0 -> 0, step: 1
3027 06:56:40.440583
3028 06:56:40.444051 RX Delay -13 -> 252, step: 4
3029 06:56:40.446727 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3030 06:56:40.450840 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3031 06:56:40.456792 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3032 06:56:40.460023 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3033 06:56:40.463719 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3034 06:56:40.467248 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3035 06:56:40.470373 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3036 06:56:40.477065 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3037 06:56:40.480883 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3038 06:56:40.483847 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3039 06:56:40.487287 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3040 06:56:40.490575 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3041 06:56:40.497434 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3042 06:56:40.500461 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3043 06:56:40.503532 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3044 06:56:40.506756 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3045 06:56:40.507253 ==
3046 06:56:40.510469 Dram Type= 6, Freq= 0, CH_0, rank 1
3047 06:56:40.514045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 06:56:40.517090 ==
3049 06:56:40.517545 DQS Delay:
3050 06:56:40.517908 DQS0 = 0, DQS1 = 0
3051 06:56:40.520373 DQM Delay:
3052 06:56:40.520835 DQM0 = 121, DQM1 = 109
3053 06:56:40.523723 DQ Delay:
3054 06:56:40.527344 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3055 06:56:40.530528 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3056 06:56:40.533673 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3057 06:56:40.537254 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3058 06:56:40.537713
3059 06:56:40.538077
3060 06:56:40.543883 [DQSOSCAuto] RK1, (LSB)MR18= 0xded, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3061 06:56:40.547279 CH0 RK1: MR19=403, MR18=DED
3062 06:56:40.553763 CH0_RK1: MR19=0x403, MR18=0xDED, DQSOSC=405, MR23=63, INC=39, DEC=26
3063 06:56:40.557521 [RxdqsGatingPostProcess] freq 1200
3064 06:56:40.560927 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3065 06:56:40.564256 best DQS0 dly(2T, 0.5T) = (0, 11)
3066 06:56:40.567306 best DQS1 dly(2T, 0.5T) = (0, 11)
3067 06:56:40.570373 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3068 06:56:40.574281 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3069 06:56:40.577232 best DQS0 dly(2T, 0.5T) = (0, 11)
3070 06:56:40.580539 best DQS1 dly(2T, 0.5T) = (0, 11)
3071 06:56:40.584167 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3072 06:56:40.587327 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3073 06:56:40.591099 Pre-setting of DQS Precalculation
3074 06:56:40.593890 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3075 06:56:40.594441 ==
3076 06:56:40.597466 Dram Type= 6, Freq= 0, CH_1, rank 0
3077 06:56:40.604598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 06:56:40.605196 ==
3079 06:56:40.607612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3080 06:56:40.614526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3081 06:56:40.622941 [CA 0] Center 37 (7~68) winsize 62
3082 06:56:40.626232 [CA 1] Center 37 (7~68) winsize 62
3083 06:56:40.629330 [CA 2] Center 35 (5~65) winsize 61
3084 06:56:40.633330 [CA 3] Center 34 (4~64) winsize 61
3085 06:56:40.636415 [CA 4] Center 34 (5~64) winsize 60
3086 06:56:40.639556 [CA 5] Center 33 (3~63) winsize 61
3087 06:56:40.640030
3088 06:56:40.643133 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3089 06:56:40.643683
3090 06:56:40.646403 [CATrainingPosCal] consider 1 rank data
3091 06:56:40.650345 u2DelayCellTimex100 = 270/100 ps
3092 06:56:40.653285 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 06:56:40.656702 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3094 06:56:40.663067 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3095 06:56:40.666133 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 06:56:40.669477 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3097 06:56:40.673383 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3098 06:56:40.673944
3099 06:56:40.676719 CA PerBit enable=1, Macro0, CA PI delay=33
3100 06:56:40.677276
3101 06:56:40.679931 [CBTSetCACLKResult] CA Dly = 33
3102 06:56:40.680529 CS Dly: 8 (0~39)
3103 06:56:40.680903 ==
3104 06:56:40.682902 Dram Type= 6, Freq= 0, CH_1, rank 1
3105 06:56:40.690199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 06:56:40.690754 ==
3107 06:56:40.693519 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 06:56:40.699762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3109 06:56:40.708405 [CA 0] Center 37 (7~68) winsize 62
3110 06:56:40.711993 [CA 1] Center 37 (7~68) winsize 62
3111 06:56:40.715479 [CA 2] Center 35 (5~65) winsize 61
3112 06:56:40.718426 [CA 3] Center 34 (4~65) winsize 62
3113 06:56:40.721664 [CA 4] Center 34 (4~65) winsize 62
3114 06:56:40.724911 [CA 5] Center 34 (4~64) winsize 61
3115 06:56:40.725374
3116 06:56:40.728422 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3117 06:56:40.728884
3118 06:56:40.732029 [CATrainingPosCal] consider 2 rank data
3119 06:56:40.735333 u2DelayCellTimex100 = 270/100 ps
3120 06:56:40.738565 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3121 06:56:40.742119 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 06:56:40.745522 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3123 06:56:40.752220 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 06:56:40.755366 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3125 06:56:40.758578 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3126 06:56:40.759139
3127 06:56:40.761973 CA PerBit enable=1, Macro0, CA PI delay=33
3128 06:56:40.762498
3129 06:56:40.765309 [CBTSetCACLKResult] CA Dly = 33
3130 06:56:40.765795 CS Dly: 9 (0~41)
3131 06:56:40.766340
3132 06:56:40.768456 ----->DramcWriteLeveling(PI) begin...
3133 06:56:40.768917 ==
3134 06:56:40.772005 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 06:56:40.778985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 06:56:40.779546 ==
3137 06:56:40.782220 Write leveling (Byte 0): 26 => 26
3138 06:56:40.785404 Write leveling (Byte 1): 28 => 28
3139 06:56:40.785954 DramcWriteLeveling(PI) end<-----
3140 06:56:40.788774
3141 06:56:40.789324 ==
3142 06:56:40.791912 Dram Type= 6, Freq= 0, CH_1, rank 0
3143 06:56:40.795252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 06:56:40.795810 ==
3145 06:56:40.798537 [Gating] SW mode calibration
3146 06:56:40.805022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3147 06:56:40.808117 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3148 06:56:40.815524 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 06:56:40.818750 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 06:56:40.821648 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 06:56:40.828168 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 06:56:40.832147 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 06:56:40.835240 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 06:56:40.842490 0 15 24 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 1)
3155 06:56:40.845338 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 06:56:40.848527 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 06:56:40.855160 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 06:56:40.858690 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 06:56:40.861958 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 06:56:40.868531 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 06:56:40.871867 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 06:56:40.875058 1 0 24 | B1->B0 | 3131 3d3d | 0 1 | (1 1) (0 0)
3163 06:56:40.881902 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 06:56:40.885286 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 06:56:40.888862 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 06:56:40.895147 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 06:56:40.898372 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 06:56:40.901620 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 06:56:40.905308 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 06:56:40.912191 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3171 06:56:40.915475 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3172 06:56:40.918846 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 06:56:40.925069 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 06:56:40.928365 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 06:56:40.931944 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 06:56:40.938552 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 06:56:40.942477 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 06:56:40.945778 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 06:56:40.952388 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 06:56:40.955313 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 06:56:40.958731 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 06:56:40.961899 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 06:56:40.968781 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 06:56:40.971975 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 06:56:40.975245 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 06:56:40.981954 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3187 06:56:40.985119 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3188 06:56:40.988993 Total UI for P1: 0, mck2ui 16
3189 06:56:40.992204 best dqsien dly found for B0: ( 1, 3, 24)
3190 06:56:40.995273 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 06:56:40.998978 Total UI for P1: 0, mck2ui 16
3192 06:56:41.002531 best dqsien dly found for B1: ( 1, 3, 26)
3193 06:56:41.005779 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3194 06:56:41.008877 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3195 06:56:41.009002
3196 06:56:41.012301 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3197 06:56:41.018562 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3198 06:56:41.018658 [Gating] SW calibration Done
3199 06:56:41.018732 ==
3200 06:56:41.021868 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 06:56:41.028960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 06:56:41.029052 ==
3203 06:56:41.029121 RX Vref Scan: 0
3204 06:56:41.029184
3205 06:56:41.032021 RX Vref 0 -> 0, step: 1
3206 06:56:41.032109
3207 06:56:41.035398 RX Delay -40 -> 252, step: 8
3208 06:56:41.038838 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3209 06:56:41.041976 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3210 06:56:41.045545 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3211 06:56:41.052439 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3212 06:56:41.055999 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3213 06:56:41.059168 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3214 06:56:41.062622 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3215 06:56:41.065569 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3216 06:56:41.068732 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3217 06:56:41.075584 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3218 06:56:41.078834 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3219 06:56:41.081944 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3220 06:56:41.085764 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3221 06:56:41.092236 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3222 06:56:41.095486 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3223 06:56:41.099401 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3224 06:56:41.099815 ==
3225 06:56:41.102584 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 06:56:41.105813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 06:56:41.106231 ==
3228 06:56:41.109222 DQS Delay:
3229 06:56:41.109611 DQS0 = 0, DQS1 = 0
3230 06:56:41.109847 DQM Delay:
3231 06:56:41.112839 DQM0 = 120, DQM1 = 116
3232 06:56:41.113134 DQ Delay:
3233 06:56:41.115359 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3234 06:56:41.119314 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3235 06:56:41.125291 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3236 06:56:41.128837 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3237 06:56:41.128990
3238 06:56:41.129109
3239 06:56:41.129220 ==
3240 06:56:41.132190 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 06:56:41.135738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 06:56:41.135853 ==
3243 06:56:41.135943
3244 06:56:41.136027
3245 06:56:41.138702 TX Vref Scan disable
3246 06:56:41.138815 == TX Byte 0 ==
3247 06:56:41.145641 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3248 06:56:41.148776 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3249 06:56:41.148867 == TX Byte 1 ==
3250 06:56:41.155391 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3251 06:56:41.158894 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3252 06:56:41.158985 ==
3253 06:56:41.162382 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 06:56:41.165691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 06:56:41.165801 ==
3256 06:56:41.178268 TX Vref=22, minBit 9, minWin=24, winSum=409
3257 06:56:41.182203 TX Vref=24, minBit 10, minWin=25, winSum=418
3258 06:56:41.185204 TX Vref=26, minBit 9, minWin=25, winSum=421
3259 06:56:41.188491 TX Vref=28, minBit 1, minWin=26, winSum=430
3260 06:56:41.191654 TX Vref=30, minBit 9, minWin=26, winSum=432
3261 06:56:41.198523 TX Vref=32, minBit 10, minWin=26, winSum=432
3262 06:56:41.202034 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3263 06:56:41.202466
3264 06:56:41.205145 Final TX Range 1 Vref 30
3265 06:56:41.205573
3266 06:56:41.205905 ==
3267 06:56:41.208386 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 06:56:41.212207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 06:56:41.212676 ==
3270 06:56:41.213015
3271 06:56:41.215457
3272 06:56:41.215870 TX Vref Scan disable
3273 06:56:41.218478 == TX Byte 0 ==
3274 06:56:41.222373 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3275 06:56:41.225682 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3276 06:56:41.228979 == TX Byte 1 ==
3277 06:56:41.231868 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3278 06:56:41.235247 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3279 06:56:41.235481
3280 06:56:41.238388 [DATLAT]
3281 06:56:41.238613 Freq=1200, CH1 RK0
3282 06:56:41.238792
3283 06:56:41.242104 DATLAT Default: 0xd
3284 06:56:41.242284 0, 0xFFFF, sum = 0
3285 06:56:41.245465 1, 0xFFFF, sum = 0
3286 06:56:41.245618 2, 0xFFFF, sum = 0
3287 06:56:41.248602 3, 0xFFFF, sum = 0
3288 06:56:41.248755 4, 0xFFFF, sum = 0
3289 06:56:41.251840 5, 0xFFFF, sum = 0
3290 06:56:41.251972 6, 0xFFFF, sum = 0
3291 06:56:41.255092 7, 0xFFFF, sum = 0
3292 06:56:41.258351 8, 0xFFFF, sum = 0
3293 06:56:41.258466 9, 0xFFFF, sum = 0
3294 06:56:41.262016 10, 0xFFFF, sum = 0
3295 06:56:41.262120 11, 0xFFFF, sum = 0
3296 06:56:41.264807 12, 0x0, sum = 1
3297 06:56:41.264909 13, 0x0, sum = 2
3298 06:56:41.265000 14, 0x0, sum = 3
3299 06:56:41.269058 15, 0x0, sum = 4
3300 06:56:41.269152 best_step = 13
3301 06:56:41.269224
3302 06:56:41.271543 ==
3303 06:56:41.271626 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 06:56:41.278605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 06:56:41.278687 ==
3306 06:56:41.278752 RX Vref Scan: 1
3307 06:56:41.278812
3308 06:56:41.281738 Set Vref Range= 32 -> 127
3309 06:56:41.281819
3310 06:56:41.285851 RX Vref 32 -> 127, step: 1
3311 06:56:41.286282
3312 06:56:41.289097 RX Delay -5 -> 252, step: 4
3313 06:56:41.289526
3314 06:56:41.292112 Set Vref, RX VrefLevel [Byte0]: 32
3315 06:56:41.292605 [Byte1]: 32
3316 06:56:41.297265
3317 06:56:41.297678 Set Vref, RX VrefLevel [Byte0]: 33
3318 06:56:41.300357 [Byte1]: 33
3319 06:56:41.304816
3320 06:56:41.305237 Set Vref, RX VrefLevel [Byte0]: 34
3321 06:56:41.308264 [Byte1]: 34
3322 06:56:41.312773
3323 06:56:41.313187 Set Vref, RX VrefLevel [Byte0]: 35
3324 06:56:41.316154 [Byte1]: 35
3325 06:56:41.320709
3326 06:56:41.321202 Set Vref, RX VrefLevel [Byte0]: 36
3327 06:56:41.323902 [Byte1]: 36
3328 06:56:41.328208
3329 06:56:41.328703 Set Vref, RX VrefLevel [Byte0]: 37
3330 06:56:41.331338 [Byte1]: 37
3331 06:56:41.335772
3332 06:56:41.335951 Set Vref, RX VrefLevel [Byte0]: 38
3333 06:56:41.339098 [Byte1]: 38
3334 06:56:41.343721
3335 06:56:41.343915 Set Vref, RX VrefLevel [Byte0]: 39
3336 06:56:41.347181 [Byte1]: 39
3337 06:56:41.351601
3338 06:56:41.354780 Set Vref, RX VrefLevel [Byte0]: 40
3339 06:56:41.357979 [Byte1]: 40
3340 06:56:41.358080
3341 06:56:41.361180 Set Vref, RX VrefLevel [Byte0]: 41
3342 06:56:41.364967 [Byte1]: 41
3343 06:56:41.365050
3344 06:56:41.367952 Set Vref, RX VrefLevel [Byte0]: 42
3345 06:56:41.371463 [Byte1]: 42
3346 06:56:41.375069
3347 06:56:41.375149 Set Vref, RX VrefLevel [Byte0]: 43
3348 06:56:41.378327 [Byte1]: 43
3349 06:56:41.383143
3350 06:56:41.383555 Set Vref, RX VrefLevel [Byte0]: 44
3351 06:56:41.386822 [Byte1]: 44
3352 06:56:41.391486
3353 06:56:41.391896 Set Vref, RX VrefLevel [Byte0]: 45
3354 06:56:41.394597 [Byte1]: 45
3355 06:56:41.399192
3356 06:56:41.399649 Set Vref, RX VrefLevel [Byte0]: 46
3357 06:56:41.402403 [Byte1]: 46
3358 06:56:41.406921
3359 06:56:41.407329 Set Vref, RX VrefLevel [Byte0]: 47
3360 06:56:41.410580 [Byte1]: 47
3361 06:56:41.414756
3362 06:56:41.415167 Set Vref, RX VrefLevel [Byte0]: 48
3363 06:56:41.418334 [Byte1]: 48
3364 06:56:41.422561
3365 06:56:41.422973 Set Vref, RX VrefLevel [Byte0]: 49
3366 06:56:41.425751 [Byte1]: 49
3367 06:56:41.430854
3368 06:56:41.431309 Set Vref, RX VrefLevel [Byte0]: 50
3369 06:56:41.434252 [Byte1]: 50
3370 06:56:41.438626
3371 06:56:41.439039 Set Vref, RX VrefLevel [Byte0]: 51
3372 06:56:41.441380 [Byte1]: 51
3373 06:56:41.446493
3374 06:56:41.446905 Set Vref, RX VrefLevel [Byte0]: 52
3375 06:56:41.449547 [Byte1]: 52
3376 06:56:41.453949
3377 06:56:41.454477 Set Vref, RX VrefLevel [Byte0]: 53
3378 06:56:41.457711 [Byte1]: 53
3379 06:56:41.462236
3380 06:56:41.462664 Set Vref, RX VrefLevel [Byte0]: 54
3381 06:56:41.465508 [Byte1]: 54
3382 06:56:41.469912
3383 06:56:41.470322 Set Vref, RX VrefLevel [Byte0]: 55
3384 06:56:41.473024 [Byte1]: 55
3385 06:56:41.477349
3386 06:56:41.477763 Set Vref, RX VrefLevel [Byte0]: 56
3387 06:56:41.481144 [Byte1]: 56
3388 06:56:41.485469
3389 06:56:41.485886 Set Vref, RX VrefLevel [Byte0]: 57
3390 06:56:41.488703 [Byte1]: 57
3391 06:56:41.492967
3392 06:56:41.493404 Set Vref, RX VrefLevel [Byte0]: 58
3393 06:56:41.496574 [Byte1]: 58
3394 06:56:41.501096
3395 06:56:41.501765 Set Vref, RX VrefLevel [Byte0]: 59
3396 06:56:41.504253 [Byte1]: 59
3397 06:56:41.508752
3398 06:56:41.509458 Set Vref, RX VrefLevel [Byte0]: 60
3399 06:56:41.512599 [Byte1]: 60
3400 06:56:41.516919
3401 06:56:41.519565 Set Vref, RX VrefLevel [Byte0]: 61
3402 06:56:41.523252 [Byte1]: 61
3403 06:56:41.523578
3404 06:56:41.526386 Set Vref, RX VrefLevel [Byte0]: 62
3405 06:56:41.529608 [Byte1]: 62
3406 06:56:41.529802
3407 06:56:41.532902 Set Vref, RX VrefLevel [Byte0]: 63
3408 06:56:41.536082 [Byte1]: 63
3409 06:56:41.540210
3410 06:56:41.540430 Set Vref, RX VrefLevel [Byte0]: 64
3411 06:56:41.543349 [Byte1]: 64
3412 06:56:41.547756
3413 06:56:41.547870 Set Vref, RX VrefLevel [Byte0]: 65
3414 06:56:41.551250 [Byte1]: 65
3415 06:56:41.555711
3416 06:56:41.555802 Set Vref, RX VrefLevel [Byte0]: 66
3417 06:56:41.558890 [Byte1]: 66
3418 06:56:41.563429
3419 06:56:41.563511 Set Vref, RX VrefLevel [Byte0]: 67
3420 06:56:41.566655 [Byte1]: 67
3421 06:56:41.571307
3422 06:56:41.571392 Set Vref, RX VrefLevel [Byte0]: 68
3423 06:56:41.574606 [Byte1]: 68
3424 06:56:41.578900
3425 06:56:41.578985 Set Vref, RX VrefLevel [Byte0]: 69
3426 06:56:41.582663 [Byte1]: 69
3427 06:56:41.586797
3428 06:56:41.586881 Final RX Vref Byte 0 = 55 to rank0
3429 06:56:41.590487 Final RX Vref Byte 1 = 49 to rank0
3430 06:56:41.593814 Final RX Vref Byte 0 = 55 to rank1
3431 06:56:41.597302 Final RX Vref Byte 1 = 49 to rank1==
3432 06:56:41.600808 Dram Type= 6, Freq= 0, CH_1, rank 0
3433 06:56:41.607441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 06:56:41.607630 ==
3435 06:56:41.607772 DQS Delay:
3436 06:56:41.607897 DQS0 = 0, DQS1 = 0
3437 06:56:41.610389 DQM Delay:
3438 06:56:41.610521 DQM0 = 120, DQM1 = 116
3439 06:56:41.613819 DQ Delay:
3440 06:56:41.617535 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3441 06:56:41.621067 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =120
3442 06:56:41.624228 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3443 06:56:41.627590 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3444 06:56:41.627860
3445 06:56:41.628084
3446 06:56:41.634186 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3447 06:56:41.637357 CH1 RK0: MR19=304, MR18=FF12
3448 06:56:41.644428 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3449 06:56:41.644947
3450 06:56:41.647988 ----->DramcWriteLeveling(PI) begin...
3451 06:56:41.648574 ==
3452 06:56:41.651211 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 06:56:41.654196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 06:56:41.657930 ==
3455 06:56:41.658405 Write leveling (Byte 0): 27 => 27
3456 06:56:41.661153 Write leveling (Byte 1): 28 => 28
3457 06:56:41.664707 DramcWriteLeveling(PI) end<-----
3458 06:56:41.665255
3459 06:56:41.665617 ==
3460 06:56:41.667689 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 06:56:41.674722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 06:56:41.675305 ==
3463 06:56:41.675675 [Gating] SW mode calibration
3464 06:56:41.684566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3465 06:56:41.687984 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3466 06:56:41.691230 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 06:56:41.697906 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 06:56:41.701234 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 06:56:41.704282 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 06:56:41.711255 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 06:56:41.714691 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3472 06:56:41.717963 0 15 24 | B1->B0 | 2626 3333 | 0 1 | (1 0) (1 0)
3473 06:56:41.724890 0 15 28 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 0)
3474 06:56:41.727982 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 06:56:41.731467 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 06:56:41.737882 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 06:56:41.741838 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 06:56:41.745246 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 06:56:41.751555 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3480 06:56:41.754576 1 0 24 | B1->B0 | 4040 2929 | 0 1 | (0 0) (0 0)
3481 06:56:41.758449 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 06:56:41.764946 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 06:56:41.768040 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 06:56:41.771241 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 06:56:41.774789 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 06:56:41.781194 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 06:56:41.784458 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3488 06:56:41.788329 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3489 06:56:41.794535 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3490 06:56:41.797660 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 06:56:41.801681 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 06:56:41.808007 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 06:56:41.811280 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 06:56:41.814410 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 06:56:41.821426 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 06:56:41.824363 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 06:56:41.828076 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 06:56:41.834179 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 06:56:41.837625 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 06:56:41.841147 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 06:56:41.847580 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 06:56:41.851345 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 06:56:41.854686 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3504 06:56:41.861557 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3505 06:56:41.864428 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3506 06:56:41.867591 Total UI for P1: 0, mck2ui 16
3507 06:56:41.870915 best dqsien dly found for B1: ( 1, 3, 22)
3508 06:56:41.874433 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 06:56:41.877751 Total UI for P1: 0, mck2ui 16
3510 06:56:41.881573 best dqsien dly found for B0: ( 1, 3, 24)
3511 06:56:41.884359 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3512 06:56:41.887877 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3513 06:56:41.888367
3514 06:56:41.891269 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3515 06:56:41.897925 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3516 06:56:41.898477 [Gating] SW calibration Done
3517 06:56:41.898845 ==
3518 06:56:41.900892 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 06:56:41.907878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 06:56:41.908496 ==
3521 06:56:41.908872 RX Vref Scan: 0
3522 06:56:41.909212
3523 06:56:41.911197 RX Vref 0 -> 0, step: 1
3524 06:56:41.911649
3525 06:56:41.914612 RX Delay -40 -> 252, step: 8
3526 06:56:41.917769 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3527 06:56:41.921085 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3528 06:56:41.924013 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3529 06:56:41.930857 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3530 06:56:41.934202 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3531 06:56:41.937067 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3532 06:56:41.940692 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3533 06:56:41.944060 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3534 06:56:41.950938 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3535 06:56:41.954105 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3536 06:56:41.957324 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3537 06:56:41.960623 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3538 06:56:41.964429 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3539 06:56:41.970410 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3540 06:56:41.973679 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3541 06:56:41.976928 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3542 06:56:41.977386 ==
3543 06:56:41.980505 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 06:56:41.984201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 06:56:41.984851 ==
3546 06:56:41.986958 DQS Delay:
3547 06:56:41.987413 DQS0 = 0, DQS1 = 0
3548 06:56:41.990206 DQM Delay:
3549 06:56:41.990694 DQM0 = 120, DQM1 = 118
3550 06:56:41.994108 DQ Delay:
3551 06:56:41.997307 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3552 06:56:42.000601 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3553 06:56:42.004139 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3554 06:56:42.007058 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3555 06:56:42.007515
3556 06:56:42.007891
3557 06:56:42.008226 ==
3558 06:56:42.010378 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 06:56:42.013647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 06:56:42.014320 ==
3561 06:56:42.014694
3562 06:56:42.015027
3563 06:56:42.017224 TX Vref Scan disable
3564 06:56:42.020789 == TX Byte 0 ==
3565 06:56:42.023785 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3566 06:56:42.027167 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3567 06:56:42.030416 == TX Byte 1 ==
3568 06:56:42.033560 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3569 06:56:42.037283 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3570 06:56:42.037745 ==
3571 06:56:42.040318 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 06:56:42.043667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 06:56:42.047267 ==
3574 06:56:42.056996 TX Vref=22, minBit 0, minWin=26, winSum=420
3575 06:56:42.060945 TX Vref=24, minBit 1, minWin=26, winSum=426
3576 06:56:42.063348 TX Vref=26, minBit 1, minWin=26, winSum=426
3577 06:56:42.066859 TX Vref=28, minBit 9, minWin=26, winSum=433
3578 06:56:42.070338 TX Vref=30, minBit 9, minWin=26, winSum=434
3579 06:56:42.073826 TX Vref=32, minBit 9, minWin=26, winSum=432
3580 06:56:42.080369 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3581 06:56:42.080936
3582 06:56:42.083520 Final TX Range 1 Vref 30
3583 06:56:42.083977
3584 06:56:42.084377 ==
3585 06:56:42.087443 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 06:56:42.090278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 06:56:42.090740 ==
3588 06:56:42.091105
3589 06:56:42.093674
3590 06:56:42.094222 TX Vref Scan disable
3591 06:56:42.096976 == TX Byte 0 ==
3592 06:56:42.100726 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3593 06:56:42.103919 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3594 06:56:42.106685 == TX Byte 1 ==
3595 06:56:42.109774 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3596 06:56:42.113103 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3597 06:56:42.116778
3598 06:56:42.117324 [DATLAT]
3599 06:56:42.117683 Freq=1200, CH1 RK1
3600 06:56:42.118021
3601 06:56:42.120063 DATLAT Default: 0xd
3602 06:56:42.120577 0, 0xFFFF, sum = 0
3603 06:56:42.123211 1, 0xFFFF, sum = 0
3604 06:56:42.123799 2, 0xFFFF, sum = 0
3605 06:56:42.126437 3, 0xFFFF, sum = 0
3606 06:56:42.129526 4, 0xFFFF, sum = 0
3607 06:56:42.129990 5, 0xFFFF, sum = 0
3608 06:56:42.133536 6, 0xFFFF, sum = 0
3609 06:56:42.133997 7, 0xFFFF, sum = 0
3610 06:56:42.136490 8, 0xFFFF, sum = 0
3611 06:56:42.136988 9, 0xFFFF, sum = 0
3612 06:56:42.139622 10, 0xFFFF, sum = 0
3613 06:56:42.140086 11, 0xFFFF, sum = 0
3614 06:56:42.142978 12, 0x0, sum = 1
3615 06:56:42.143601 13, 0x0, sum = 2
3616 06:56:42.146310 14, 0x0, sum = 3
3617 06:56:42.146773 15, 0x0, sum = 4
3618 06:56:42.149470 best_step = 13
3619 06:56:42.149922
3620 06:56:42.150282 ==
3621 06:56:42.152950 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 06:56:42.156792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 06:56:42.157244 ==
3624 06:56:42.157587 RX Vref Scan: 0
3625 06:56:42.157895
3626 06:56:42.159873 RX Vref 0 -> 0, step: 1
3627 06:56:42.160453
3628 06:56:42.162770 RX Delay -5 -> 252, step: 4
3629 06:56:42.166228 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3630 06:56:42.172963 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3631 06:56:42.176702 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3632 06:56:42.179910 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3633 06:56:42.182968 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3634 06:56:42.186315 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3635 06:56:42.192814 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3636 06:56:42.195899 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3637 06:56:42.199654 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3638 06:56:42.202671 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3639 06:56:42.205775 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3640 06:56:42.212945 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3641 06:56:42.216150 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3642 06:56:42.219611 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3643 06:56:42.222778 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3644 06:56:42.229501 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3645 06:56:42.230009 ==
3646 06:56:42.232921 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 06:56:42.236406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 06:56:42.236950 ==
3649 06:56:42.237342 DQS Delay:
3650 06:56:42.239259 DQS0 = 0, DQS1 = 0
3651 06:56:42.239670 DQM Delay:
3652 06:56:42.242521 DQM0 = 120, DQM1 = 117
3653 06:56:42.242938 DQ Delay:
3654 06:56:42.245834 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3655 06:56:42.249315 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3656 06:56:42.252456 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3657 06:56:42.256056 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =124
3658 06:56:42.256626
3659 06:56:42.256960
3660 06:56:42.265821 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3661 06:56:42.269235 CH1 RK1: MR19=403, MR18=12F0
3662 06:56:42.272405 CH1_RK1: MR19=0x403, MR18=0x12F0, DQSOSC=403, MR23=63, INC=40, DEC=26
3663 06:56:42.275694 [RxdqsGatingPostProcess] freq 1200
3664 06:56:42.282198 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3665 06:56:42.285584 best DQS0 dly(2T, 0.5T) = (0, 11)
3666 06:56:42.289113 best DQS1 dly(2T, 0.5T) = (0, 11)
3667 06:56:42.292335 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3668 06:56:42.295744 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3669 06:56:42.299169 best DQS0 dly(2T, 0.5T) = (0, 11)
3670 06:56:42.302871 best DQS1 dly(2T, 0.5T) = (0, 11)
3671 06:56:42.305660 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3672 06:56:42.309164 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3673 06:56:42.309617 Pre-setting of DQS Precalculation
3674 06:56:42.315987 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3675 06:56:42.322281 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3676 06:56:42.329415 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3677 06:56:42.329962
3678 06:56:42.330318
3679 06:56:42.333074 [Calibration Summary] 2400 Mbps
3680 06:56:42.335590 CH 0, Rank 0
3681 06:56:42.336144 SW Impedance : PASS
3682 06:56:42.338931 DUTY Scan : NO K
3683 06:56:42.342961 ZQ Calibration : PASS
3684 06:56:42.343540 Jitter Meter : NO K
3685 06:56:42.346316 CBT Training : PASS
3686 06:56:42.348870 Write leveling : PASS
3687 06:56:42.349329 RX DQS gating : PASS
3688 06:56:42.353147 RX DQ/DQS(RDDQC) : PASS
3689 06:56:42.353706 TX DQ/DQS : PASS
3690 06:56:42.356244 RX DATLAT : PASS
3691 06:56:42.359490 RX DQ/DQS(Engine): PASS
3692 06:56:42.360048 TX OE : NO K
3693 06:56:42.362719 All Pass.
3694 06:56:42.363276
3695 06:56:42.363645 CH 0, Rank 1
3696 06:56:42.365520 SW Impedance : PASS
3697 06:56:42.365980 DUTY Scan : NO K
3698 06:56:42.369488 ZQ Calibration : PASS
3699 06:56:42.372493 Jitter Meter : NO K
3700 06:56:42.372956 CBT Training : PASS
3701 06:56:42.376170 Write leveling : PASS
3702 06:56:42.378831 RX DQS gating : PASS
3703 06:56:42.379327 RX DQ/DQS(RDDQC) : PASS
3704 06:56:42.381978 TX DQ/DQS : PASS
3705 06:56:42.385457 RX DATLAT : PASS
3706 06:56:42.386017 RX DQ/DQS(Engine): PASS
3707 06:56:42.388936 TX OE : NO K
3708 06:56:42.389396 All Pass.
3709 06:56:42.389755
3710 06:56:42.391980 CH 1, Rank 0
3711 06:56:42.392479 SW Impedance : PASS
3712 06:56:42.395623 DUTY Scan : NO K
3713 06:56:42.399109 ZQ Calibration : PASS
3714 06:56:42.399714 Jitter Meter : NO K
3715 06:56:42.402106 CBT Training : PASS
3716 06:56:42.405540 Write leveling : PASS
3717 06:56:42.406149 RX DQS gating : PASS
3718 06:56:42.408583 RX DQ/DQS(RDDQC) : PASS
3719 06:56:42.409102 TX DQ/DQS : PASS
3720 06:56:42.412122 RX DATLAT : PASS
3721 06:56:42.415635 RX DQ/DQS(Engine): PASS
3722 06:56:42.416203 TX OE : NO K
3723 06:56:42.419166 All Pass.
3724 06:56:42.419751
3725 06:56:42.420121 CH 1, Rank 1
3726 06:56:42.422015 SW Impedance : PASS
3727 06:56:42.422472 DUTY Scan : NO K
3728 06:56:42.425230 ZQ Calibration : PASS
3729 06:56:42.428791 Jitter Meter : NO K
3730 06:56:42.429251 CBT Training : PASS
3731 06:56:42.431886 Write leveling : PASS
3732 06:56:42.435529 RX DQS gating : PASS
3733 06:56:42.436112 RX DQ/DQS(RDDQC) : PASS
3734 06:56:42.438880 TX DQ/DQS : PASS
3735 06:56:42.442148 RX DATLAT : PASS
3736 06:56:42.442609 RX DQ/DQS(Engine): PASS
3737 06:56:42.445561 TX OE : NO K
3738 06:56:42.446084 All Pass.
3739 06:56:42.446421
3740 06:56:42.448497 DramC Write-DBI off
3741 06:56:42.452507 PER_BANK_REFRESH: Hybrid Mode
3742 06:56:42.453021 TX_TRACKING: ON
3743 06:56:42.462211 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3744 06:56:42.465237 [FAST_K] Save calibration result to emmc
3745 06:56:42.468272 dramc_set_vcore_voltage set vcore to 650000
3746 06:56:42.471426 Read voltage for 600, 5
3747 06:56:42.471843 Vio18 = 0
3748 06:56:42.472175 Vcore = 650000
3749 06:56:42.475284 Vdram = 0
3750 06:56:42.475699 Vddq = 0
3751 06:56:42.476025 Vmddr = 0
3752 06:56:42.481588 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3753 06:56:42.484870 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3754 06:56:42.488149 MEM_TYPE=3, freq_sel=19
3755 06:56:42.491201 sv_algorithm_assistance_LP4_1600
3756 06:56:42.494970 ============ PULL DRAM RESETB DOWN ============
3757 06:56:42.498321 ========== PULL DRAM RESETB DOWN end =========
3758 06:56:42.505195 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3759 06:56:42.507948 ===================================
3760 06:56:42.511473 LPDDR4 DRAM CONFIGURATION
3761 06:56:42.511992 ===================================
3762 06:56:42.514853 EX_ROW_EN[0] = 0x0
3763 06:56:42.518040 EX_ROW_EN[1] = 0x0
3764 06:56:42.518567 LP4Y_EN = 0x0
3765 06:56:42.521618 WORK_FSP = 0x0
3766 06:56:42.522073 WL = 0x2
3767 06:56:42.524800 RL = 0x2
3768 06:56:42.525226 BL = 0x2
3769 06:56:42.528031 RPST = 0x0
3770 06:56:42.528479 RD_PRE = 0x0
3771 06:56:42.531422 WR_PRE = 0x1
3772 06:56:42.531840 WR_PST = 0x0
3773 06:56:42.534421 DBI_WR = 0x0
3774 06:56:42.534868 DBI_RD = 0x0
3775 06:56:42.538205 OTF = 0x1
3776 06:56:42.541257 ===================================
3777 06:56:42.544620 ===================================
3778 06:56:42.545032 ANA top config
3779 06:56:42.547983 ===================================
3780 06:56:42.551262 DLL_ASYNC_EN = 0
3781 06:56:42.554910 ALL_SLAVE_EN = 1
3782 06:56:42.557996 NEW_RANK_MODE = 1
3783 06:56:42.558418 DLL_IDLE_MODE = 1
3784 06:56:42.561000 LP45_APHY_COMB_EN = 1
3785 06:56:42.564581 TX_ODT_DIS = 1
3786 06:56:42.567871 NEW_8X_MODE = 1
3787 06:56:42.571180 ===================================
3788 06:56:42.574402 ===================================
3789 06:56:42.577769 data_rate = 1200
3790 06:56:42.578185 CKR = 1
3791 06:56:42.580994 DQ_P2S_RATIO = 8
3792 06:56:42.584540 ===================================
3793 06:56:42.587829 CA_P2S_RATIO = 8
3794 06:56:42.591121 DQ_CA_OPEN = 0
3795 06:56:42.594963 DQ_SEMI_OPEN = 0
3796 06:56:42.598286 CA_SEMI_OPEN = 0
3797 06:56:42.598801 CA_FULL_RATE = 0
3798 06:56:42.601460 DQ_CKDIV4_EN = 1
3799 06:56:42.604321 CA_CKDIV4_EN = 1
3800 06:56:42.607981 CA_PREDIV_EN = 0
3801 06:56:42.610994 PH8_DLY = 0
3802 06:56:42.614254 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3803 06:56:42.614776 DQ_AAMCK_DIV = 4
3804 06:56:42.617284 CA_AAMCK_DIV = 4
3805 06:56:42.621213 CA_ADMCK_DIV = 4
3806 06:56:42.624040 DQ_TRACK_CA_EN = 0
3807 06:56:42.628017 CA_PICK = 600
3808 06:56:42.630797 CA_MCKIO = 600
3809 06:56:42.634341 MCKIO_SEMI = 0
3810 06:56:42.634929 PLL_FREQ = 2288
3811 06:56:42.637354 DQ_UI_PI_RATIO = 32
3812 06:56:42.640630 CA_UI_PI_RATIO = 0
3813 06:56:42.644152 ===================================
3814 06:56:42.647326 ===================================
3815 06:56:42.650250 memory_type:LPDDR4
3816 06:56:42.653856 GP_NUM : 10
3817 06:56:42.654372 SRAM_EN : 1
3818 06:56:42.657672 MD32_EN : 0
3819 06:56:42.660872 ===================================
3820 06:56:42.661393 [ANA_INIT] >>>>>>>>>>>>>>
3821 06:56:42.664047 <<<<<< [CONFIGURE PHASE]: ANA_TX
3822 06:56:42.666807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3823 06:56:42.670070 ===================================
3824 06:56:42.673873 data_rate = 1200,PCW = 0X5800
3825 06:56:42.676959 ===================================
3826 06:56:42.680175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3827 06:56:42.686916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3828 06:56:42.694132 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3829 06:56:42.697125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3830 06:56:42.700239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3831 06:56:42.703825 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3832 06:56:42.706951 [ANA_INIT] flow start
3833 06:56:42.707411 [ANA_INIT] PLL >>>>>>>>
3834 06:56:42.709953 [ANA_INIT] PLL <<<<<<<<
3835 06:56:42.713368 [ANA_INIT] MIDPI >>>>>>>>
3836 06:56:42.713840 [ANA_INIT] MIDPI <<<<<<<<
3837 06:56:42.716660 [ANA_INIT] DLL >>>>>>>>
3838 06:56:42.720136 [ANA_INIT] flow end
3839 06:56:42.723267 ============ LP4 DIFF to SE enter ============
3840 06:56:42.726776 ============ LP4 DIFF to SE exit ============
3841 06:56:42.729935 [ANA_INIT] <<<<<<<<<<<<<
3842 06:56:42.733641 [Flow] Enable top DCM control >>>>>
3843 06:56:42.736796 [Flow] Enable top DCM control <<<<<
3844 06:56:42.739927 Enable DLL master slave shuffle
3845 06:56:42.743514 ==============================================================
3846 06:56:42.746687 Gating Mode config
3847 06:56:42.753749 ==============================================================
3848 06:56:42.754292 Config description:
3849 06:56:42.763556 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3850 06:56:42.770366 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3851 06:56:42.777245 SELPH_MODE 0: By rank 1: By Phase
3852 06:56:42.779884 ==============================================================
3853 06:56:42.783753 GAT_TRACK_EN = 1
3854 06:56:42.786956 RX_GATING_MODE = 2
3855 06:56:42.789704 RX_GATING_TRACK_MODE = 2
3856 06:56:42.793165 SELPH_MODE = 1
3857 06:56:42.796668 PICG_EARLY_EN = 1
3858 06:56:42.800153 VALID_LAT_VALUE = 1
3859 06:56:42.803325 ==============================================================
3860 06:56:42.806883 Enter into Gating configuration >>>>
3861 06:56:42.809444 Exit from Gating configuration <<<<
3862 06:56:42.812698 Enter into DVFS_PRE_config >>>>>
3863 06:56:42.826403 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3864 06:56:42.826980 Exit from DVFS_PRE_config <<<<<
3865 06:56:42.830089 Enter into PICG configuration >>>>
3866 06:56:42.832856 Exit from PICG configuration <<<<
3867 06:56:42.836405 [RX_INPUT] configuration >>>>>
3868 06:56:42.839163 [RX_INPUT] configuration <<<<<
3869 06:56:42.846551 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3870 06:56:42.849445 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3871 06:56:42.856380 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3872 06:56:42.863190 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3873 06:56:42.869448 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3874 06:56:42.876035 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3875 06:56:42.879450 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3876 06:56:42.882605 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3877 06:56:42.885662 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3878 06:56:42.893055 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3879 06:56:42.896203 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3880 06:56:42.899508 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3881 06:56:42.902511 ===================================
3882 06:56:42.905961 LPDDR4 DRAM CONFIGURATION
3883 06:56:42.909021 ===================================
3884 06:56:42.912790 EX_ROW_EN[0] = 0x0
3885 06:56:42.913261 EX_ROW_EN[1] = 0x0
3886 06:56:42.916133 LP4Y_EN = 0x0
3887 06:56:42.916811 WORK_FSP = 0x0
3888 06:56:42.918870 WL = 0x2
3889 06:56:42.919338 RL = 0x2
3890 06:56:42.922587 BL = 0x2
3891 06:56:42.923108 RPST = 0x0
3892 06:56:42.925634 RD_PRE = 0x0
3893 06:56:42.926061 WR_PRE = 0x1
3894 06:56:42.928858 WR_PST = 0x0
3895 06:56:42.929286 DBI_WR = 0x0
3896 06:56:42.932351 DBI_RD = 0x0
3897 06:56:42.932868 OTF = 0x1
3898 06:56:42.935707 ===================================
3899 06:56:42.941874 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3900 06:56:42.945973 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3901 06:56:42.949025 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3902 06:56:42.952407 ===================================
3903 06:56:42.956180 LPDDR4 DRAM CONFIGURATION
3904 06:56:42.959005 ===================================
3905 06:56:42.959434 EX_ROW_EN[0] = 0x10
3906 06:56:42.962808 EX_ROW_EN[1] = 0x0
3907 06:56:42.965510 LP4Y_EN = 0x0
3908 06:56:42.965939 WORK_FSP = 0x0
3909 06:56:42.969099 WL = 0x2
3910 06:56:42.969528 RL = 0x2
3911 06:56:42.972204 BL = 0x2
3912 06:56:42.972756 RPST = 0x0
3913 06:56:42.975564 RD_PRE = 0x0
3914 06:56:42.976074 WR_PRE = 0x1
3915 06:56:42.979134 WR_PST = 0x0
3916 06:56:42.979645 DBI_WR = 0x0
3917 06:56:42.982271 DBI_RD = 0x0
3918 06:56:42.982834 OTF = 0x1
3919 06:56:42.985631 ===================================
3920 06:56:42.992279 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3921 06:56:42.997079 nWR fixed to 30
3922 06:56:42.999604 [ModeRegInit_LP4] CH0 RK0
3923 06:56:43.000154 [ModeRegInit_LP4] CH0 RK1
3924 06:56:43.002951 [ModeRegInit_LP4] CH1 RK0
3925 06:56:43.006092 [ModeRegInit_LP4] CH1 RK1
3926 06:56:43.006564 match AC timing 17
3927 06:56:43.013198 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3928 06:56:43.016375 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3929 06:56:43.019866 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3930 06:56:43.026119 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3931 06:56:43.029740 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3932 06:56:43.030163 ==
3933 06:56:43.032970 Dram Type= 6, Freq= 0, CH_0, rank 0
3934 06:56:43.036224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3935 06:56:43.036779 ==
3936 06:56:43.042520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3937 06:56:43.049188 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3938 06:56:43.053237 [CA 0] Center 35 (5~66) winsize 62
3939 06:56:43.056542 [CA 1] Center 35 (5~66) winsize 62
3940 06:56:43.059537 [CA 2] Center 33 (3~64) winsize 62
3941 06:56:43.062699 [CA 3] Center 33 (2~64) winsize 63
3942 06:56:43.065792 [CA 4] Center 33 (2~64) winsize 63
3943 06:56:43.069581 [CA 5] Center 32 (2~63) winsize 62
3944 06:56:43.070001
3945 06:56:43.073059 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3946 06:56:43.073640
3947 06:56:43.076002 [CATrainingPosCal] consider 1 rank data
3948 06:56:43.079263 u2DelayCellTimex100 = 270/100 ps
3949 06:56:43.083027 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3950 06:56:43.086122 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3951 06:56:43.089467 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3952 06:56:43.092991 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3953 06:56:43.096001 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3954 06:56:43.102845 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3955 06:56:43.103358
3956 06:56:43.106237 CA PerBit enable=1, Macro0, CA PI delay=32
3957 06:56:43.106747
3958 06:56:43.108970 [CBTSetCACLKResult] CA Dly = 32
3959 06:56:43.109449 CS Dly: 4 (0~35)
3960 06:56:43.109788 ==
3961 06:56:43.112611 Dram Type= 6, Freq= 0, CH_0, rank 1
3962 06:56:43.115886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 06:56:43.119568 ==
3964 06:56:43.122451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3965 06:56:43.129282 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3966 06:56:43.132331 [CA 0] Center 35 (5~66) winsize 62
3967 06:56:43.135771 [CA 1] Center 35 (5~66) winsize 62
3968 06:56:43.139038 [CA 2] Center 34 (3~65) winsize 63
3969 06:56:43.142151 [CA 3] Center 33 (3~64) winsize 62
3970 06:56:43.145899 [CA 4] Center 33 (2~64) winsize 63
3971 06:56:43.149158 [CA 5] Center 32 (2~63) winsize 62
3972 06:56:43.149720
3973 06:56:43.152600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3974 06:56:43.153082
3975 06:56:43.155411 [CATrainingPosCal] consider 2 rank data
3976 06:56:43.158916 u2DelayCellTimex100 = 270/100 ps
3977 06:56:43.162097 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3978 06:56:43.165993 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3979 06:56:43.168634 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3980 06:56:43.172695 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3981 06:56:43.178765 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3982 06:56:43.182150 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3983 06:56:43.182700
3984 06:56:43.185373 CA PerBit enable=1, Macro0, CA PI delay=32
3985 06:56:43.185961
3986 06:56:43.189101 [CBTSetCACLKResult] CA Dly = 32
3987 06:56:43.189640 CS Dly: 4 (0~36)
3988 06:56:43.190019
3989 06:56:43.192129 ----->DramcWriteLeveling(PI) begin...
3990 06:56:43.192630 ==
3991 06:56:43.195644 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 06:56:43.202637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 06:56:43.203199 ==
3994 06:56:43.205750 Write leveling (Byte 0): 33 => 33
3995 06:56:43.208566 Write leveling (Byte 1): 29 => 29
3996 06:56:43.209031 DramcWriteLeveling(PI) end<-----
3997 06:56:43.209476
3998 06:56:43.212191 ==
3999 06:56:43.215483 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 06:56:43.219328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 06:56:43.219844 ==
4002 06:56:43.222534 [Gating] SW mode calibration
4003 06:56:43.228946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4004 06:56:43.231998 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4005 06:56:43.238994 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 06:56:43.242275 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 06:56:43.245801 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4008 06:56:43.252068 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4009 06:56:43.255364 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4010 06:56:43.258515 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 06:56:43.265083 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 06:56:43.268782 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 06:56:43.272099 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 06:56:43.278332 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 06:56:43.282203 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 06:56:43.284831 0 10 12 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
4017 06:56:43.291870 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4018 06:56:43.295363 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 06:56:43.298938 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 06:56:43.305203 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 06:56:43.308964 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 06:56:43.311965 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 06:56:43.315466 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 06:56:43.322056 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4025 06:56:43.325232 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 06:56:43.329016 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 06:56:43.335501 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 06:56:43.338905 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 06:56:43.341990 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 06:56:43.348494 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 06:56:43.351589 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 06:56:43.354767 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 06:56:43.361783 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 06:56:43.365136 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 06:56:43.368647 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 06:56:43.375261 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 06:56:43.378501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 06:56:43.381987 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 06:56:43.388938 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 06:56:43.391906 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4041 06:56:43.395514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4042 06:56:43.398425 Total UI for P1: 0, mck2ui 16
4043 06:56:43.402566 best dqsien dly found for B0: ( 0, 13, 12)
4044 06:56:43.405391 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 06:56:43.408439 Total UI for P1: 0, mck2ui 16
4046 06:56:43.411379 best dqsien dly found for B1: ( 0, 13, 14)
4047 06:56:43.418149 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4048 06:56:43.421945 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4049 06:56:43.422498
4050 06:56:43.424626 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4051 06:56:43.428350 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4052 06:56:43.431370 [Gating] SW calibration Done
4053 06:56:43.431828 ==
4054 06:56:43.435250 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 06:56:43.438654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 06:56:43.439207 ==
4057 06:56:43.441654 RX Vref Scan: 0
4058 06:56:43.442111
4059 06:56:43.442546 RX Vref 0 -> 0, step: 1
4060 06:56:43.442896
4061 06:56:43.444868 RX Delay -230 -> 252, step: 16
4062 06:56:43.448450 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4063 06:56:43.454833 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4064 06:56:43.458013 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4065 06:56:43.461036 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4066 06:56:43.464991 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4067 06:56:43.471012 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4068 06:56:43.474246 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4069 06:56:43.478489 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4070 06:56:43.481520 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4071 06:56:43.484660 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4072 06:56:43.491442 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4073 06:56:43.494604 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4074 06:56:43.497625 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4075 06:56:43.501048 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4076 06:56:43.507365 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4077 06:56:43.510869 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4078 06:56:43.511288 ==
4079 06:56:43.514253 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 06:56:43.517636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 06:56:43.518058 ==
4082 06:56:43.521166 DQS Delay:
4083 06:56:43.521593 DQS0 = 0, DQS1 = 0
4084 06:56:43.522052 DQM Delay:
4085 06:56:43.523998 DQM0 = 51, DQM1 = 46
4086 06:56:43.524707 DQ Delay:
4087 06:56:43.527273 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4088 06:56:43.531060 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4089 06:56:43.533959 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4090 06:56:43.537536 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4091 06:56:43.537944
4092 06:56:43.538265
4093 06:56:43.538561 ==
4094 06:56:43.540763 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 06:56:43.547150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 06:56:43.547560 ==
4097 06:56:43.547884
4098 06:56:43.548187
4099 06:56:43.550257 TX Vref Scan disable
4100 06:56:43.550663 == TX Byte 0 ==
4101 06:56:43.553620 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4102 06:56:43.560194 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4103 06:56:43.560777 == TX Byte 1 ==
4104 06:56:43.567431 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4105 06:56:43.570354 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4106 06:56:43.570776 ==
4107 06:56:43.574045 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 06:56:43.577502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 06:56:43.578031 ==
4110 06:56:43.578366
4111 06:56:43.578670
4112 06:56:43.580390 TX Vref Scan disable
4113 06:56:43.583715 == TX Byte 0 ==
4114 06:56:43.587011 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4115 06:56:43.590026 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4116 06:56:43.594005 == TX Byte 1 ==
4117 06:56:43.597252 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4118 06:56:43.600454 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4119 06:56:43.601005
4120 06:56:43.603718 [DATLAT]
4121 06:56:43.604276 Freq=600, CH0 RK0
4122 06:56:43.604688
4123 06:56:43.606886 DATLAT Default: 0x9
4124 06:56:43.607436 0, 0xFFFF, sum = 0
4125 06:56:43.610627 1, 0xFFFF, sum = 0
4126 06:56:43.611185 2, 0xFFFF, sum = 0
4127 06:56:43.613698 3, 0xFFFF, sum = 0
4128 06:56:43.614164 4, 0xFFFF, sum = 0
4129 06:56:43.616989 5, 0xFFFF, sum = 0
4130 06:56:43.617457 6, 0xFFFF, sum = 0
4131 06:56:43.620477 7, 0xFFFF, sum = 0
4132 06:56:43.621029 8, 0x0, sum = 1
4133 06:56:43.623636 9, 0x0, sum = 2
4134 06:56:43.624194 10, 0x0, sum = 3
4135 06:56:43.627057 11, 0x0, sum = 4
4136 06:56:43.627577 best_step = 9
4137 06:56:43.627955
4138 06:56:43.628340 ==
4139 06:56:43.630093 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 06:56:43.633175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 06:56:43.636867 ==
4142 06:56:43.637489 RX Vref Scan: 1
4143 06:56:43.637862
4144 06:56:43.640275 RX Vref 0 -> 0, step: 1
4145 06:56:43.640808
4146 06:56:43.643364 RX Delay -163 -> 252, step: 8
4147 06:56:43.643780
4148 06:56:43.646939 Set Vref, RX VrefLevel [Byte0]: 54
4149 06:56:43.647505 [Byte1]: 46
4150 06:56:43.651488
4151 06:56:43.651906 Final RX Vref Byte 0 = 54 to rank0
4152 06:56:43.655046 Final RX Vref Byte 1 = 46 to rank0
4153 06:56:43.658543 Final RX Vref Byte 0 = 54 to rank1
4154 06:56:43.661517 Final RX Vref Byte 1 = 46 to rank1==
4155 06:56:43.665095 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 06:56:43.672135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 06:56:43.672765 ==
4158 06:56:43.673107 DQS Delay:
4159 06:56:43.673421 DQS0 = 0, DQS1 = 0
4160 06:56:43.675031 DQM Delay:
4161 06:56:43.675447 DQM0 = 53, DQM1 = 45
4162 06:56:43.678222 DQ Delay:
4163 06:56:43.681703 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =48
4164 06:56:43.684869 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =56
4165 06:56:43.688130 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4166 06:56:43.691588 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4167 06:56:43.692009
4168 06:56:43.692369
4169 06:56:43.698627 [DQSOSCAuto] RK0, (LSB)MR18= 0x7165, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4170 06:56:43.701746 CH0 RK0: MR19=808, MR18=7165
4171 06:56:43.708448 CH0_RK0: MR19=0x808, MR18=0x7165, DQSOSC=388, MR23=63, INC=174, DEC=116
4172 06:56:43.708979
4173 06:56:43.711310 ----->DramcWriteLeveling(PI) begin...
4174 06:56:43.711735 ==
4175 06:56:43.714537 Dram Type= 6, Freq= 0, CH_0, rank 1
4176 06:56:43.718767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 06:56:43.719282 ==
4178 06:56:43.721331 Write leveling (Byte 0): 37 => 37
4179 06:56:43.725216 Write leveling (Byte 1): 32 => 32
4180 06:56:43.728366 DramcWriteLeveling(PI) end<-----
4181 06:56:43.728789
4182 06:56:43.729123 ==
4183 06:56:43.731507 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 06:56:43.734902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 06:56:43.735452 ==
4186 06:56:43.738298 [Gating] SW mode calibration
4187 06:56:43.745390 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4188 06:56:43.751819 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4189 06:56:43.755107 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 06:56:43.758884 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 06:56:43.765180 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 06:56:43.768454 0 9 12 | B1->B0 | 3333 3333 | 1 1 | (1 0) (1 0)
4193 06:56:43.771704 0 9 16 | B1->B0 | 2b2b 2929 | 0 0 | (0 0) (0 0)
4194 06:56:43.778080 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 06:56:43.781560 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 06:56:43.784889 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 06:56:43.790855 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 06:56:43.794796 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 06:56:43.797844 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 06:56:43.804386 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
4201 06:56:43.807622 0 10 16 | B1->B0 | 3a3a 4040 | 0 1 | (0 0) (0 0)
4202 06:56:43.810891 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 06:56:43.817684 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 06:56:43.820917 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 06:56:43.824278 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 06:56:43.830487 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 06:56:43.833823 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 06:56:43.837689 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4209 06:56:43.844182 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 06:56:43.847476 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 06:56:43.850842 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 06:56:43.857702 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 06:56:43.860839 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 06:56:43.864053 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 06:56:43.871206 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 06:56:43.874445 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 06:56:43.877637 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 06:56:43.884041 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 06:56:43.887338 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 06:56:43.891101 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 06:56:43.897296 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 06:56:43.900742 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 06:56:43.904498 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 06:56:43.910503 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4225 06:56:43.914268 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 06:56:43.917336 Total UI for P1: 0, mck2ui 16
4227 06:56:43.920481 best dqsien dly found for B0: ( 0, 13, 12)
4228 06:56:43.923738 Total UI for P1: 0, mck2ui 16
4229 06:56:43.927150 best dqsien dly found for B1: ( 0, 13, 14)
4230 06:56:43.930934 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4231 06:56:43.934291 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4232 06:56:43.934741
4233 06:56:43.936951 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4234 06:56:43.940262 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4235 06:56:43.943429 [Gating] SW calibration Done
4236 06:56:43.943886 ==
4237 06:56:43.947792 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 06:56:43.950492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 06:56:43.950953 ==
4240 06:56:43.953818 RX Vref Scan: 0
4241 06:56:43.954463
4242 06:56:43.957138 RX Vref 0 -> 0, step: 1
4243 06:56:43.957634
4244 06:56:43.958001 RX Delay -230 -> 252, step: 16
4245 06:56:43.964048 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4246 06:56:43.967245 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4247 06:56:43.970643 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4248 06:56:43.973793 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4249 06:56:43.980486 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4250 06:56:43.983832 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4251 06:56:43.987015 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4252 06:56:43.990264 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4253 06:56:43.997211 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4254 06:56:44.000513 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4255 06:56:44.003812 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4256 06:56:44.007852 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4257 06:56:44.010093 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4258 06:56:44.017186 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4259 06:56:44.020236 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4260 06:56:44.023775 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4261 06:56:44.024374 ==
4262 06:56:44.027475 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 06:56:44.030698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 06:56:44.033608 ==
4265 06:56:44.034069 DQS Delay:
4266 06:56:44.034454 DQS0 = 0, DQS1 = 0
4267 06:56:44.036811 DQM Delay:
4268 06:56:44.037270 DQM0 = 52, DQM1 = 46
4269 06:56:44.040060 DQ Delay:
4270 06:56:44.040641 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4271 06:56:44.043975 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4272 06:56:44.046997 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =41
4273 06:56:44.050484 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4274 06:56:44.050945
4275 06:56:44.053817
4276 06:56:44.054275 ==
4277 06:56:44.057275 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 06:56:44.060366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 06:56:44.060924 ==
4280 06:56:44.061289
4281 06:56:44.061704
4282 06:56:44.063237 TX Vref Scan disable
4283 06:56:44.063699 == TX Byte 0 ==
4284 06:56:44.070642 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4285 06:56:44.073363 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4286 06:56:44.073828 == TX Byte 1 ==
4287 06:56:44.080401 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4288 06:56:44.083429 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4289 06:56:44.083974 ==
4290 06:56:44.087026 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 06:56:44.090323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 06:56:44.090787 ==
4293 06:56:44.091158
4294 06:56:44.091499
4295 06:56:44.092946 TX Vref Scan disable
4296 06:56:44.097043 == TX Byte 0 ==
4297 06:56:44.100496 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4298 06:56:44.103365 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4299 06:56:44.106992 == TX Byte 1 ==
4300 06:56:44.110318 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4301 06:56:44.113321 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4302 06:56:44.116895
4303 06:56:44.117353 [DATLAT]
4304 06:56:44.117725 Freq=600, CH0 RK1
4305 06:56:44.118072
4306 06:56:44.120083 DATLAT Default: 0x9
4307 06:56:44.120628 0, 0xFFFF, sum = 0
4308 06:56:44.123505 1, 0xFFFF, sum = 0
4309 06:56:44.124059 2, 0xFFFF, sum = 0
4310 06:56:44.126707 3, 0xFFFF, sum = 0
4311 06:56:44.127168 4, 0xFFFF, sum = 0
4312 06:56:44.130397 5, 0xFFFF, sum = 0
4313 06:56:44.130854 6, 0xFFFF, sum = 0
4314 06:56:44.133366 7, 0xFFFF, sum = 0
4315 06:56:44.133824 8, 0x0, sum = 1
4316 06:56:44.136664 9, 0x0, sum = 2
4317 06:56:44.137119 10, 0x0, sum = 3
4318 06:56:44.140144 11, 0x0, sum = 4
4319 06:56:44.140658 best_step = 9
4320 06:56:44.141023
4321 06:56:44.141356 ==
4322 06:56:44.143371 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 06:56:44.149774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 06:56:44.150223 ==
4325 06:56:44.150558 RX Vref Scan: 0
4326 06:56:44.150868
4327 06:56:44.152991 RX Vref 0 -> 0, step: 1
4328 06:56:44.153408
4329 06:56:44.156791 RX Delay -147 -> 252, step: 8
4330 06:56:44.159735 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4331 06:56:44.163044 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4332 06:56:44.169631 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4333 06:56:44.173359 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4334 06:56:44.176611 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4335 06:56:44.179917 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4336 06:56:44.183267 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4337 06:56:44.189946 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4338 06:56:44.193223 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4339 06:56:44.196098 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4340 06:56:44.199644 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4341 06:56:44.206619 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4342 06:56:44.209481 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4343 06:56:44.212666 iDelay=197, Bit 13, Center 48 (-91 ~ 188) 280
4344 06:56:44.216204 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4345 06:56:44.220000 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4346 06:56:44.220508 ==
4347 06:56:44.222940 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 06:56:44.229361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 06:56:44.229898 ==
4350 06:56:44.230261 DQS Delay:
4351 06:56:44.232895 DQS0 = 0, DQS1 = 0
4352 06:56:44.233352 DQM Delay:
4353 06:56:44.233713 DQM0 = 53, DQM1 = 45
4354 06:56:44.235979 DQ Delay:
4355 06:56:44.239409 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4356 06:56:44.242668 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4357 06:56:44.246666 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4358 06:56:44.249866 DQ12 =48, DQ13 =48, DQ14 =56, DQ15 =52
4359 06:56:44.250373
4360 06:56:44.250702
4361 06:56:44.256233 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4362 06:56:44.259404 CH0 RK1: MR19=808, MR18=5F20
4363 06:56:44.266260 CH0_RK1: MR19=0x808, MR18=0x5F20, DQSOSC=391, MR23=63, INC=171, DEC=114
4364 06:56:44.269685 [RxdqsGatingPostProcess] freq 600
4365 06:56:44.272989 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4366 06:56:44.276261 Pre-setting of DQS Precalculation
4367 06:56:44.282591 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4368 06:56:44.283059 ==
4369 06:56:44.285980 Dram Type= 6, Freq= 0, CH_1, rank 0
4370 06:56:44.289621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 06:56:44.290248 ==
4372 06:56:44.296414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 06:56:44.303159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4374 06:56:44.306270 [CA 0] Center 36 (5~67) winsize 63
4375 06:56:44.309515 [CA 1] Center 36 (5~67) winsize 63
4376 06:56:44.312503 [CA 2] Center 34 (4~65) winsize 62
4377 06:56:44.316149 [CA 3] Center 34 (4~65) winsize 62
4378 06:56:44.319890 [CA 4] Center 34 (4~65) winsize 62
4379 06:56:44.322713 [CA 5] Center 34 (3~65) winsize 63
4380 06:56:44.323259
4381 06:56:44.326480 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4382 06:56:44.327034
4383 06:56:44.329592 [CATrainingPosCal] consider 1 rank data
4384 06:56:44.332987 u2DelayCellTimex100 = 270/100 ps
4385 06:56:44.335632 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4386 06:56:44.339144 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4387 06:56:44.342563 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 06:56:44.345572 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 06:56:44.349150 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 06:56:44.352425 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4391 06:56:44.352962
4392 06:56:44.356395 CA PerBit enable=1, Macro0, CA PI delay=34
4393 06:56:44.356899
4394 06:56:44.359429 [CBTSetCACLKResult] CA Dly = 34
4395 06:56:44.362590 CS Dly: 6 (0~37)
4396 06:56:44.363003 ==
4397 06:56:44.365756 Dram Type= 6, Freq= 0, CH_1, rank 1
4398 06:56:44.369902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 06:56:44.370412 ==
4400 06:56:44.375539 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4401 06:56:44.382354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4402 06:56:44.385816 [CA 0] Center 36 (5~67) winsize 63
4403 06:56:44.389510 [CA 1] Center 36 (5~67) winsize 63
4404 06:56:44.392738 [CA 2] Center 34 (4~65) winsize 62
4405 06:56:44.395746 [CA 3] Center 34 (4~65) winsize 62
4406 06:56:44.398928 [CA 4] Center 34 (4~65) winsize 62
4407 06:56:44.402870 [CA 5] Center 34 (4~65) winsize 62
4408 06:56:44.403417
4409 06:56:44.406112 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4410 06:56:44.406664
4411 06:56:44.409236 [CATrainingPosCal] consider 2 rank data
4412 06:56:44.412474 u2DelayCellTimex100 = 270/100 ps
4413 06:56:44.415834 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4414 06:56:44.419218 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4415 06:56:44.423038 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4416 06:56:44.425887 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4417 06:56:44.429313 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4418 06:56:44.432448 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4419 06:56:44.433015
4420 06:56:44.439184 CA PerBit enable=1, Macro0, CA PI delay=34
4421 06:56:44.439719
4422 06:56:44.440082 [CBTSetCACLKResult] CA Dly = 34
4423 06:56:44.442525 CS Dly: 6 (0~37)
4424 06:56:44.442987
4425 06:56:44.445639 ----->DramcWriteLeveling(PI) begin...
4426 06:56:44.446099 ==
4427 06:56:44.448845 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 06:56:44.452659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 06:56:44.453193 ==
4430 06:56:44.455562 Write leveling (Byte 0): 32 => 32
4431 06:56:44.459108 Write leveling (Byte 1): 32 => 32
4432 06:56:44.462445 DramcWriteLeveling(PI) end<-----
4433 06:56:44.462859
4434 06:56:44.463184 ==
4435 06:56:44.465365 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 06:56:44.469006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 06:56:44.472596 ==
4438 06:56:44.473018 [Gating] SW mode calibration
4439 06:56:44.482286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4440 06:56:44.485979 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4441 06:56:44.488639 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 06:56:44.495637 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 06:56:44.498841 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 06:56:44.502489 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
4445 06:56:44.509264 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 06:56:44.512370 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 06:56:44.515827 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 06:56:44.522392 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 06:56:44.525511 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 06:56:44.528640 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 06:56:44.535370 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4452 06:56:44.538478 0 10 12 | B1->B0 | 3535 3939 | 1 0 | (0 0) (0 0)
4453 06:56:44.541869 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 06:56:44.548857 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 06:56:44.551651 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 06:56:44.555030 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 06:56:44.561813 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 06:56:44.564688 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 06:56:44.568693 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 06:56:44.575046 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4461 06:56:44.578516 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 06:56:44.582237 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 06:56:44.588027 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 06:56:44.591607 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 06:56:44.595012 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 06:56:44.601541 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 06:56:44.604908 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 06:56:44.608520 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 06:56:44.611666 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 06:56:44.618544 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 06:56:44.621140 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 06:56:44.624777 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 06:56:44.631187 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 06:56:44.635091 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 06:56:44.638345 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 06:56:44.644600 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 06:56:44.648164 Total UI for P1: 0, mck2ui 16
4478 06:56:44.651454 best dqsien dly found for B0: ( 0, 13, 10)
4479 06:56:44.654603 Total UI for P1: 0, mck2ui 16
4480 06:56:44.658487 best dqsien dly found for B1: ( 0, 13, 10)
4481 06:56:44.661447 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4482 06:56:44.664824 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4483 06:56:44.665242
4484 06:56:44.667906 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4485 06:56:44.671754 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4486 06:56:44.674409 [Gating] SW calibration Done
4487 06:56:44.674827 ==
4488 06:56:44.677948 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 06:56:44.681333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 06:56:44.681842 ==
4491 06:56:44.684449 RX Vref Scan: 0
4492 06:56:44.684866
4493 06:56:44.685194 RX Vref 0 -> 0, step: 1
4494 06:56:44.685503
4495 06:56:44.687775 RX Delay -230 -> 252, step: 16
4496 06:56:44.695030 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4497 06:56:44.698080 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4498 06:56:44.701415 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4499 06:56:44.704765 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4500 06:56:44.708406 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4501 06:56:44.714842 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4502 06:56:44.717952 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4503 06:56:44.721113 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4504 06:56:44.724751 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4505 06:56:44.731161 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4506 06:56:44.734597 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4507 06:56:44.737858 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4508 06:56:44.741252 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4509 06:56:44.744708 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4510 06:56:44.751576 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4511 06:56:44.754696 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4512 06:56:44.755209 ==
4513 06:56:44.757979 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 06:56:44.761518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 06:56:44.762028 ==
4516 06:56:44.764690 DQS Delay:
4517 06:56:44.765103 DQS0 = 0, DQS1 = 0
4518 06:56:44.765432 DQM Delay:
4519 06:56:44.768370 DQM0 = 49, DQM1 = 46
4520 06:56:44.768792 DQ Delay:
4521 06:56:44.771252 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4522 06:56:44.774943 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4523 06:56:44.777984 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4524 06:56:44.781743 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4525 06:56:44.782259
4526 06:56:44.782587
4527 06:56:44.782894 ==
4528 06:56:44.784453 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 06:56:44.791619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 06:56:44.792136 ==
4531 06:56:44.792513
4532 06:56:44.792824
4533 06:56:44.793113 TX Vref Scan disable
4534 06:56:44.795258 == TX Byte 0 ==
4535 06:56:44.798464 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4536 06:56:44.805207 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4537 06:56:44.805721 == TX Byte 1 ==
4538 06:56:44.808707 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4539 06:56:44.814782 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4540 06:56:44.815281 ==
4541 06:56:44.818740 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 06:56:44.821525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 06:56:44.821948 ==
4544 06:56:44.822282
4545 06:56:44.822594
4546 06:56:44.825131 TX Vref Scan disable
4547 06:56:44.828626 == TX Byte 0 ==
4548 06:56:44.831705 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4549 06:56:44.834977 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4550 06:56:44.838440 == TX Byte 1 ==
4551 06:56:44.841473 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4552 06:56:44.845205 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4553 06:56:44.845625
4554 06:56:44.845959 [DATLAT]
4555 06:56:44.848374 Freq=600, CH1 RK0
4556 06:56:44.848823
4557 06:56:44.849160 DATLAT Default: 0x9
4558 06:56:44.851405 0, 0xFFFF, sum = 0
4559 06:56:44.851830 1, 0xFFFF, sum = 0
4560 06:56:44.854805 2, 0xFFFF, sum = 0
4561 06:56:44.858151 3, 0xFFFF, sum = 0
4562 06:56:44.858574 4, 0xFFFF, sum = 0
4563 06:56:44.861265 5, 0xFFFF, sum = 0
4564 06:56:44.861708 6, 0xFFFF, sum = 0
4565 06:56:44.864726 7, 0xFFFF, sum = 0
4566 06:56:44.865151 8, 0x0, sum = 1
4567 06:56:44.865488 9, 0x0, sum = 2
4568 06:56:44.867983 10, 0x0, sum = 3
4569 06:56:44.868544 11, 0x0, sum = 4
4570 06:56:44.871575 best_step = 9
4571 06:56:44.872081
4572 06:56:44.872466 ==
4573 06:56:44.874856 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 06:56:44.877672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 06:56:44.878095 ==
4576 06:56:44.881175 RX Vref Scan: 1
4577 06:56:44.881737
4578 06:56:44.882087 RX Vref 0 -> 0, step: 1
4579 06:56:44.884750
4580 06:56:44.885259 RX Delay -163 -> 252, step: 8
4581 06:56:44.885597
4582 06:56:44.887878 Set Vref, RX VrefLevel [Byte0]: 55
4583 06:56:44.891266 [Byte1]: 49
4584 06:56:44.895150
4585 06:56:44.895561 Final RX Vref Byte 0 = 55 to rank0
4586 06:56:44.898467 Final RX Vref Byte 1 = 49 to rank0
4587 06:56:44.902683 Final RX Vref Byte 0 = 55 to rank1
4588 06:56:44.905740 Final RX Vref Byte 1 = 49 to rank1==
4589 06:56:44.908984 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 06:56:44.915605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 06:56:44.916166 ==
4592 06:56:44.916601 DQS Delay:
4593 06:56:44.917010 DQS0 = 0, DQS1 = 0
4594 06:56:44.918725 DQM Delay:
4595 06:56:44.919176 DQM0 = 48, DQM1 = 45
4596 06:56:44.921942 DQ Delay:
4597 06:56:44.925892 DQ0 =48, DQ1 =40, DQ2 =40, DQ3 =48
4598 06:56:44.926411 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4599 06:56:44.928849 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4600 06:56:44.935675 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4601 06:56:44.936089
4602 06:56:44.936507
4603 06:56:44.942445 [DQSOSCAuto] RK0, (LSB)MR18= 0x4469, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 396 ps
4604 06:56:44.945390 CH1 RK0: MR19=808, MR18=4469
4605 06:56:44.952256 CH1_RK0: MR19=0x808, MR18=0x4469, DQSOSC=390, MR23=63, INC=172, DEC=114
4606 06:56:44.952809
4607 06:56:44.955413 ----->DramcWriteLeveling(PI) begin...
4608 06:56:44.955829 ==
4609 06:56:44.958870 Dram Type= 6, Freq= 0, CH_1, rank 1
4610 06:56:44.961729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 06:56:44.962187 ==
4612 06:56:44.965711 Write leveling (Byte 0): 31 => 31
4613 06:56:44.968862 Write leveling (Byte 1): 32 => 32
4614 06:56:44.971962 DramcWriteLeveling(PI) end<-----
4615 06:56:44.972553
4616 06:56:44.972924 ==
4617 06:56:44.975220 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 06:56:44.978423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 06:56:44.978938 ==
4620 06:56:44.981845 [Gating] SW mode calibration
4621 06:56:44.988426 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4622 06:56:44.995274 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4623 06:56:44.998818 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4624 06:56:45.004885 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4625 06:56:45.008638 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 06:56:45.012035 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (1 1) (1 0)
4627 06:56:45.014877 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 06:56:45.021355 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 06:56:45.025185 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 06:56:45.028428 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 06:56:45.034664 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 06:56:45.038486 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 06:56:45.041304 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4634 06:56:45.048090 0 10 12 | B1->B0 | 3b3b 3837 | 1 1 | (0 0) (0 0)
4635 06:56:45.051434 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 06:56:45.054618 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 06:56:45.061773 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 06:56:45.064824 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 06:56:45.068076 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 06:56:45.074597 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 06:56:45.078014 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4642 06:56:45.081420 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4643 06:56:45.087607 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 06:56:45.091330 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 06:56:45.094641 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 06:56:45.101436 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 06:56:45.104658 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 06:56:45.107605 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 06:56:45.114358 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 06:56:45.117637 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 06:56:45.120766 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 06:56:45.127420 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 06:56:45.130744 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 06:56:45.134245 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 06:56:45.140835 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 06:56:45.143804 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 06:56:45.147519 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 06:56:45.154460 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 06:56:45.154963 Total UI for P1: 0, mck2ui 16
4660 06:56:45.157774 best dqsien dly found for B0: ( 0, 13, 10)
4661 06:56:45.160857 Total UI for P1: 0, mck2ui 16
4662 06:56:45.163944 best dqsien dly found for B1: ( 0, 13, 10)
4663 06:56:45.171034 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4664 06:56:45.174372 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4665 06:56:45.174890
4666 06:56:45.177863 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4667 06:56:45.181209 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4668 06:56:45.184183 [Gating] SW calibration Done
4669 06:56:45.184639 ==
4670 06:56:45.187781 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 06:56:45.191048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 06:56:45.191584 ==
4673 06:56:45.194454 RX Vref Scan: 0
4674 06:56:45.194964
4675 06:56:45.195294 RX Vref 0 -> 0, step: 1
4676 06:56:45.195601
4677 06:56:45.197757 RX Delay -230 -> 252, step: 16
4678 06:56:45.200814 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4679 06:56:45.207560 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4680 06:56:45.210955 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4681 06:56:45.213767 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4682 06:56:45.217334 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4683 06:56:45.223912 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4684 06:56:45.227679 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4685 06:56:45.230685 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4686 06:56:45.233832 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4687 06:56:45.237538 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4688 06:56:45.243605 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4689 06:56:45.247089 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4690 06:56:45.250673 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4691 06:56:45.253872 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4692 06:56:45.260251 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4693 06:56:45.263892 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4694 06:56:45.264490 ==
4695 06:56:45.266968 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 06:56:45.270618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 06:56:45.271075 ==
4698 06:56:45.273476 DQS Delay:
4699 06:56:45.274016 DQS0 = 0, DQS1 = 0
4700 06:56:45.274473 DQM Delay:
4701 06:56:45.276694 DQM0 = 51, DQM1 = 47
4702 06:56:45.277109 DQ Delay:
4703 06:56:45.280446 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4704 06:56:45.283531 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4705 06:56:45.286772 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4706 06:56:45.289868 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4707 06:56:45.290278
4708 06:56:45.290601
4709 06:56:45.290898 ==
4710 06:56:45.293456 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 06:56:45.300529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 06:56:45.301041 ==
4713 06:56:45.301371
4714 06:56:45.301675
4715 06:56:45.301965 TX Vref Scan disable
4716 06:56:45.303860 == TX Byte 0 ==
4717 06:56:45.307065 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4718 06:56:45.314051 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4719 06:56:45.314557 == TX Byte 1 ==
4720 06:56:45.316969 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4721 06:56:45.323490 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4722 06:56:45.323990 ==
4723 06:56:45.327084 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 06:56:45.330569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 06:56:45.330992 ==
4726 06:56:45.331318
4727 06:56:45.331616
4728 06:56:45.334137 TX Vref Scan disable
4729 06:56:45.336903 == TX Byte 0 ==
4730 06:56:45.340426 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4731 06:56:45.343938 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4732 06:56:45.344567 == TX Byte 1 ==
4733 06:56:45.350088 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4734 06:56:45.354163 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4735 06:56:45.354703
4736 06:56:45.355042 [DATLAT]
4737 06:56:45.357070 Freq=600, CH1 RK1
4738 06:56:45.357488
4739 06:56:45.357821 DATLAT Default: 0x9
4740 06:56:45.360185 0, 0xFFFF, sum = 0
4741 06:56:45.360726 1, 0xFFFF, sum = 0
4742 06:56:45.363929 2, 0xFFFF, sum = 0
4743 06:56:45.364396 3, 0xFFFF, sum = 0
4744 06:56:45.367445 4, 0xFFFF, sum = 0
4745 06:56:45.370405 5, 0xFFFF, sum = 0
4746 06:56:45.370934 6, 0xFFFF, sum = 0
4747 06:56:45.373514 7, 0xFFFF, sum = 0
4748 06:56:45.374089 8, 0x0, sum = 1
4749 06:56:45.374466 9, 0x0, sum = 2
4750 06:56:45.377149 10, 0x0, sum = 3
4751 06:56:45.377717 11, 0x0, sum = 4
4752 06:56:45.380770 best_step = 9
4753 06:56:45.381329
4754 06:56:45.381697 ==
4755 06:56:45.383825 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 06:56:45.386901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 06:56:45.387367 ==
4758 06:56:45.390458 RX Vref Scan: 0
4759 06:56:45.390897
4760 06:56:45.391227 RX Vref 0 -> 0, step: 1
4761 06:56:45.391560
4762 06:56:45.393207 RX Delay -163 -> 252, step: 8
4763 06:56:45.400612 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4764 06:56:45.404620 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4765 06:56:45.407409 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4766 06:56:45.410847 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4767 06:56:45.414091 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4768 06:56:45.421124 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4769 06:56:45.424521 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4770 06:56:45.427471 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4771 06:56:45.430583 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4772 06:56:45.437005 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4773 06:56:45.440859 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4774 06:56:45.443940 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4775 06:56:45.447128 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4776 06:56:45.451190 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4777 06:56:45.457855 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4778 06:56:45.460812 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4779 06:56:45.461404 ==
4780 06:56:45.463979 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 06:56:45.467240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 06:56:45.468012 ==
4783 06:56:45.470950 DQS Delay:
4784 06:56:45.471505 DQS0 = 0, DQS1 = 0
4785 06:56:45.471867 DQM Delay:
4786 06:56:45.474357 DQM0 = 48, DQM1 = 45
4787 06:56:45.474923 DQ Delay:
4788 06:56:45.477632 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4789 06:56:45.480359 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4790 06:56:45.483849 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4791 06:56:45.487713 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4792 06:56:45.488268
4793 06:56:45.488696
4794 06:56:45.497376 [DQSOSCAuto] RK1, (LSB)MR18= 0x691f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4795 06:56:45.497939 CH1 RK1: MR19=808, MR18=691F
4796 06:56:45.503696 CH1_RK1: MR19=0x808, MR18=0x691F, DQSOSC=390, MR23=63, INC=172, DEC=114
4797 06:56:45.507253 [RxdqsGatingPostProcess] freq 600
4798 06:56:45.513621 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4799 06:56:45.517004 Pre-setting of DQS Precalculation
4800 06:56:45.520611 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4801 06:56:45.526884 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4802 06:56:45.536650 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4803 06:56:45.537319
4804 06:56:45.537897
4805 06:56:45.540106 [Calibration Summary] 1200 Mbps
4806 06:56:45.540569 CH 0, Rank 0
4807 06:56:45.543673 SW Impedance : PASS
4808 06:56:45.544090 DUTY Scan : NO K
4809 06:56:45.546578 ZQ Calibration : PASS
4810 06:56:45.550141 Jitter Meter : NO K
4811 06:56:45.550660 CBT Training : PASS
4812 06:56:45.553213 Write leveling : PASS
4813 06:56:45.553629 RX DQS gating : PASS
4814 06:56:45.557235 RX DQ/DQS(RDDQC) : PASS
4815 06:56:45.560512 TX DQ/DQS : PASS
4816 06:56:45.561104 RX DATLAT : PASS
4817 06:56:45.563456 RX DQ/DQS(Engine): PASS
4818 06:56:45.567260 TX OE : NO K
4819 06:56:45.567819 All Pass.
4820 06:56:45.568189
4821 06:56:45.568602 CH 0, Rank 1
4822 06:56:45.570238 SW Impedance : PASS
4823 06:56:45.573127 DUTY Scan : NO K
4824 06:56:45.573547 ZQ Calibration : PASS
4825 06:56:45.576858 Jitter Meter : NO K
4826 06:56:45.580187 CBT Training : PASS
4827 06:56:45.580654 Write leveling : PASS
4828 06:56:45.583244 RX DQS gating : PASS
4829 06:56:45.586579 RX DQ/DQS(RDDQC) : PASS
4830 06:56:45.586996 TX DQ/DQS : PASS
4831 06:56:45.589716 RX DATLAT : PASS
4832 06:56:45.593148 RX DQ/DQS(Engine): PASS
4833 06:56:45.593564 TX OE : NO K
4834 06:56:45.596878 All Pass.
4835 06:56:45.597295
4836 06:56:45.597623 CH 1, Rank 0
4837 06:56:45.600093 SW Impedance : PASS
4838 06:56:45.600548 DUTY Scan : NO K
4839 06:56:45.603436 ZQ Calibration : PASS
4840 06:56:45.606561 Jitter Meter : NO K
4841 06:56:45.606976 CBT Training : PASS
4842 06:56:45.609992 Write leveling : PASS
4843 06:56:45.610404 RX DQS gating : PASS
4844 06:56:45.613182 RX DQ/DQS(RDDQC) : PASS
4845 06:56:45.616356 TX DQ/DQS : PASS
4846 06:56:45.616777 RX DATLAT : PASS
4847 06:56:45.619908 RX DQ/DQS(Engine): PASS
4848 06:56:45.622706 TX OE : NO K
4849 06:56:45.623125 All Pass.
4850 06:56:45.623455
4851 06:56:45.623758 CH 1, Rank 1
4852 06:56:45.626151 SW Impedance : PASS
4853 06:56:45.629786 DUTY Scan : NO K
4854 06:56:45.630205 ZQ Calibration : PASS
4855 06:56:45.632894 Jitter Meter : NO K
4856 06:56:45.636210 CBT Training : PASS
4857 06:56:45.636809 Write leveling : PASS
4858 06:56:45.639415 RX DQS gating : PASS
4859 06:56:45.642974 RX DQ/DQS(RDDQC) : PASS
4860 06:56:45.643499 TX DQ/DQS : PASS
4861 06:56:45.646374 RX DATLAT : PASS
4862 06:56:45.649795 RX DQ/DQS(Engine): PASS
4863 06:56:45.650208 TX OE : NO K
4864 06:56:45.652694 All Pass.
4865 06:56:45.653107
4866 06:56:45.653456 DramC Write-DBI off
4867 06:56:45.655965 PER_BANK_REFRESH: Hybrid Mode
4868 06:56:45.656426 TX_TRACKING: ON
4869 06:56:45.666456 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4870 06:56:45.669616 [FAST_K] Save calibration result to emmc
4871 06:56:45.672412 dramc_set_vcore_voltage set vcore to 662500
4872 06:56:45.676059 Read voltage for 933, 3
4873 06:56:45.676656 Vio18 = 0
4874 06:56:45.679604 Vcore = 662500
4875 06:56:45.680116 Vdram = 0
4876 06:56:45.680532 Vddq = 0
4877 06:56:45.680851 Vmddr = 0
4878 06:56:45.685728 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4879 06:56:45.693113 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4880 06:56:45.693624 MEM_TYPE=3, freq_sel=17
4881 06:56:45.696250 sv_algorithm_assistance_LP4_1600
4882 06:56:45.699556 ============ PULL DRAM RESETB DOWN ============
4883 06:56:45.706023 ========== PULL DRAM RESETB DOWN end =========
4884 06:56:45.709835 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4885 06:56:45.712646 ===================================
4886 06:56:45.716478 LPDDR4 DRAM CONFIGURATION
4887 06:56:45.719478 ===================================
4888 06:56:45.719893 EX_ROW_EN[0] = 0x0
4889 06:56:45.723041 EX_ROW_EN[1] = 0x0
4890 06:56:45.723550 LP4Y_EN = 0x0
4891 06:56:45.726067 WORK_FSP = 0x0
4892 06:56:45.729159 WL = 0x3
4893 06:56:45.729571 RL = 0x3
4894 06:56:45.732197 BL = 0x2
4895 06:56:45.732687 RPST = 0x0
4896 06:56:45.735791 RD_PRE = 0x0
4897 06:56:45.736408 WR_PRE = 0x1
4898 06:56:45.739443 WR_PST = 0x0
4899 06:56:45.739900 DBI_WR = 0x0
4900 06:56:45.742543 DBI_RD = 0x0
4901 06:56:45.742999 OTF = 0x1
4902 06:56:45.745936 ===================================
4903 06:56:45.749258 ===================================
4904 06:56:45.752367 ANA top config
4905 06:56:45.756227 ===================================
4906 06:56:45.756803 DLL_ASYNC_EN = 0
4907 06:56:45.759169 ALL_SLAVE_EN = 1
4908 06:56:45.762645 NEW_RANK_MODE = 1
4909 06:56:45.766092 DLL_IDLE_MODE = 1
4910 06:56:45.766652 LP45_APHY_COMB_EN = 1
4911 06:56:45.769210 TX_ODT_DIS = 1
4912 06:56:45.772650 NEW_8X_MODE = 1
4913 06:56:45.776202 ===================================
4914 06:56:45.779312 ===================================
4915 06:56:45.782575 data_rate = 1866
4916 06:56:45.785613 CKR = 1
4917 06:56:45.789490 DQ_P2S_RATIO = 8
4918 06:56:45.790052 ===================================
4919 06:56:45.792172 CA_P2S_RATIO = 8
4920 06:56:45.795999 DQ_CA_OPEN = 0
4921 06:56:45.799192 DQ_SEMI_OPEN = 0
4922 06:56:45.802961 CA_SEMI_OPEN = 0
4923 06:56:45.805857 CA_FULL_RATE = 0
4924 06:56:45.806432 DQ_CKDIV4_EN = 1
4925 06:56:45.809377 CA_CKDIV4_EN = 1
4926 06:56:45.812530 CA_PREDIV_EN = 0
4927 06:56:45.815899 PH8_DLY = 0
4928 06:56:45.819194 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4929 06:56:45.823143 DQ_AAMCK_DIV = 4
4930 06:56:45.823712 CA_AAMCK_DIV = 4
4931 06:56:45.826041 CA_ADMCK_DIV = 4
4932 06:56:45.829217 DQ_TRACK_CA_EN = 0
4933 06:56:45.832618 CA_PICK = 933
4934 06:56:45.835903 CA_MCKIO = 933
4935 06:56:45.838899 MCKIO_SEMI = 0
4936 06:56:45.842474 PLL_FREQ = 3732
4937 06:56:45.842941 DQ_UI_PI_RATIO = 32
4938 06:56:45.845363 CA_UI_PI_RATIO = 0
4939 06:56:45.849030 ===================================
4940 06:56:45.852369 ===================================
4941 06:56:45.855476 memory_type:LPDDR4
4942 06:56:45.858875 GP_NUM : 10
4943 06:56:45.859383 SRAM_EN : 1
4944 06:56:45.862316 MD32_EN : 0
4945 06:56:45.866144 ===================================
4946 06:56:45.869001 [ANA_INIT] >>>>>>>>>>>>>>
4947 06:56:45.869455 <<<<<< [CONFIGURE PHASE]: ANA_TX
4948 06:56:45.872668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4949 06:56:45.875684 ===================================
4950 06:56:45.878934 data_rate = 1866,PCW = 0X8f00
4951 06:56:45.882381 ===================================
4952 06:56:45.885235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4953 06:56:45.892469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4954 06:56:45.899046 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4955 06:56:45.902225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4956 06:56:45.905284 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4957 06:56:45.909029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4958 06:56:45.912367 [ANA_INIT] flow start
4959 06:56:45.912894 [ANA_INIT] PLL >>>>>>>>
4960 06:56:45.915018 [ANA_INIT] PLL <<<<<<<<
4961 06:56:45.918445 [ANA_INIT] MIDPI >>>>>>>>
4962 06:56:45.922171 [ANA_INIT] MIDPI <<<<<<<<
4963 06:56:45.922719 [ANA_INIT] DLL >>>>>>>>
4964 06:56:45.925042 [ANA_INIT] flow end
4965 06:56:45.928799 ============ LP4 DIFF to SE enter ============
4966 06:56:45.932163 ============ LP4 DIFF to SE exit ============
4967 06:56:45.935047 [ANA_INIT] <<<<<<<<<<<<<
4968 06:56:45.938334 [Flow] Enable top DCM control >>>>>
4969 06:56:45.941486 [Flow] Enable top DCM control <<<<<
4970 06:56:45.945356 Enable DLL master slave shuffle
4971 06:56:45.951671 ==============================================================
4972 06:56:45.952080 Gating Mode config
4973 06:56:45.958591 ==============================================================
4974 06:56:45.959108 Config description:
4975 06:56:45.968740 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4976 06:56:45.975223 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4977 06:56:45.981546 SELPH_MODE 0: By rank 1: By Phase
4978 06:56:45.984922 ==============================================================
4979 06:56:45.989008 GAT_TRACK_EN = 1
4980 06:56:45.992003 RX_GATING_MODE = 2
4981 06:56:45.994841 RX_GATING_TRACK_MODE = 2
4982 06:56:45.998736 SELPH_MODE = 1
4983 06:56:46.002084 PICG_EARLY_EN = 1
4984 06:56:46.004886 VALID_LAT_VALUE = 1
4985 06:56:46.008448 ==============================================================
4986 06:56:46.011531 Enter into Gating configuration >>>>
4987 06:56:46.014666 Exit from Gating configuration <<<<
4988 06:56:46.018443 Enter into DVFS_PRE_config >>>>>
4989 06:56:46.031418 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4990 06:56:46.034773 Exit from DVFS_PRE_config <<<<<
4991 06:56:46.037726 Enter into PICG configuration >>>>
4992 06:56:46.038188 Exit from PICG configuration <<<<
4993 06:56:46.041452 [RX_INPUT] configuration >>>>>
4994 06:56:46.044471 [RX_INPUT] configuration <<<<<
4995 06:56:46.051269 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4996 06:56:46.054781 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4997 06:56:46.061589 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4998 06:56:46.068110 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4999 06:56:46.074849 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5000 06:56:46.081691 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5001 06:56:46.084975 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5002 06:56:46.087880 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5003 06:56:46.091214 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5004 06:56:46.098701 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5005 06:56:46.101525 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5006 06:56:46.105078 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5007 06:56:46.108386 ===================================
5008 06:56:46.111364 LPDDR4 DRAM CONFIGURATION
5009 06:56:46.114391 ===================================
5010 06:56:46.118294 EX_ROW_EN[0] = 0x0
5011 06:56:46.118756 EX_ROW_EN[1] = 0x0
5012 06:56:46.121518 LP4Y_EN = 0x0
5013 06:56:46.121977 WORK_FSP = 0x0
5014 06:56:46.124623 WL = 0x3
5015 06:56:46.125081 RL = 0x3
5016 06:56:46.128068 BL = 0x2
5017 06:56:46.128690 RPST = 0x0
5018 06:56:46.131649 RD_PRE = 0x0
5019 06:56:46.132170 WR_PRE = 0x1
5020 06:56:46.134784 WR_PST = 0x0
5021 06:56:46.135244 DBI_WR = 0x0
5022 06:56:46.138165 DBI_RD = 0x0
5023 06:56:46.138630 OTF = 0x1
5024 06:56:46.141594 ===================================
5025 06:56:46.144841 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5026 06:56:46.150921 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5027 06:56:46.154865 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5028 06:56:46.158013 ===================================
5029 06:56:46.161181 LPDDR4 DRAM CONFIGURATION
5030 06:56:46.164386 ===================================
5031 06:56:46.164945 EX_ROW_EN[0] = 0x10
5032 06:56:46.167684 EX_ROW_EN[1] = 0x0
5033 06:56:46.171320 LP4Y_EN = 0x0
5034 06:56:46.171888 WORK_FSP = 0x0
5035 06:56:46.174275 WL = 0x3
5036 06:56:46.174729 RL = 0x3
5037 06:56:46.177628 BL = 0x2
5038 06:56:46.178183 RPST = 0x0
5039 06:56:46.180779 RD_PRE = 0x0
5040 06:56:46.181254 WR_PRE = 0x1
5041 06:56:46.184641 WR_PST = 0x0
5042 06:56:46.185236 DBI_WR = 0x0
5043 06:56:46.187682 DBI_RD = 0x0
5044 06:56:46.188235 OTF = 0x1
5045 06:56:46.190896 ===================================
5046 06:56:46.197742 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5047 06:56:46.201976 nWR fixed to 30
5048 06:56:46.205402 [ModeRegInit_LP4] CH0 RK0
5049 06:56:46.205863 [ModeRegInit_LP4] CH0 RK1
5050 06:56:46.208657 [ModeRegInit_LP4] CH1 RK0
5051 06:56:46.211659 [ModeRegInit_LP4] CH1 RK1
5052 06:56:46.212204 match AC timing 9
5053 06:56:46.218386 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5054 06:56:46.221460 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5055 06:56:46.225297 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5056 06:56:46.231439 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5057 06:56:46.235159 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5058 06:56:46.235621 ==
5059 06:56:46.238456 Dram Type= 6, Freq= 0, CH_0, rank 0
5060 06:56:46.241990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5061 06:56:46.242556 ==
5062 06:56:46.248118 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5063 06:56:46.255406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5064 06:56:46.259001 [CA 0] Center 37 (7~68) winsize 62
5065 06:56:46.261908 [CA 1] Center 37 (7~68) winsize 62
5066 06:56:46.265005 [CA 2] Center 34 (4~65) winsize 62
5067 06:56:46.268606 [CA 3] Center 34 (3~65) winsize 63
5068 06:56:46.272111 [CA 4] Center 33 (3~64) winsize 62
5069 06:56:46.275163 [CA 5] Center 32 (2~62) winsize 61
5070 06:56:46.275729
5071 06:56:46.278920 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5072 06:56:46.279488
5073 06:56:46.281892 [CATrainingPosCal] consider 1 rank data
5074 06:56:46.284947 u2DelayCellTimex100 = 270/100 ps
5075 06:56:46.288350 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5076 06:56:46.291481 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5077 06:56:46.295571 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5078 06:56:46.298415 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5079 06:56:46.301410 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5080 06:56:46.305492 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5081 06:56:46.306051
5082 06:56:46.311916 CA PerBit enable=1, Macro0, CA PI delay=32
5083 06:56:46.312528
5084 06:56:46.314940 [CBTSetCACLKResult] CA Dly = 32
5085 06:56:46.315444 CS Dly: 5 (0~36)
5086 06:56:46.315808 ==
5087 06:56:46.318179 Dram Type= 6, Freq= 0, CH_0, rank 1
5088 06:56:46.321809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 06:56:46.322264 ==
5090 06:56:46.328011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 06:56:46.334992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5092 06:56:46.338256 [CA 0] Center 37 (6~68) winsize 63
5093 06:56:46.341543 [CA 1] Center 37 (6~68) winsize 63
5094 06:56:46.344798 [CA 2] Center 34 (4~65) winsize 62
5095 06:56:46.347875 [CA 3] Center 34 (4~65) winsize 62
5096 06:56:46.350995 [CA 4] Center 33 (3~63) winsize 61
5097 06:56:46.354599 [CA 5] Center 32 (2~62) winsize 61
5098 06:56:46.355147
5099 06:56:46.358235 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5100 06:56:46.358689
5101 06:56:46.361595 [CATrainingPosCal] consider 2 rank data
5102 06:56:46.364695 u2DelayCellTimex100 = 270/100 ps
5103 06:56:46.368099 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5104 06:56:46.371002 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5105 06:56:46.374663 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5106 06:56:46.380973 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5107 06:56:46.384340 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5108 06:56:46.387981 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5109 06:56:46.388709
5110 06:56:46.391035 CA PerBit enable=1, Macro0, CA PI delay=32
5111 06:56:46.391604
5112 06:56:46.394039 [CBTSetCACLKResult] CA Dly = 32
5113 06:56:46.394496 CS Dly: 5 (0~37)
5114 06:56:46.394855
5115 06:56:46.397188 ----->DramcWriteLeveling(PI) begin...
5116 06:56:46.397647 ==
5117 06:56:46.400476 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 06:56:46.407674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 06:56:46.408233 ==
5120 06:56:46.410909 Write leveling (Byte 0): 34 => 34
5121 06:56:46.414169 Write leveling (Byte 1): 29 => 29
5122 06:56:46.417287 DramcWriteLeveling(PI) end<-----
5123 06:56:46.417741
5124 06:56:46.418162 ==
5125 06:56:46.420473 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 06:56:46.423855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 06:56:46.424448 ==
5128 06:56:46.427581 [Gating] SW mode calibration
5129 06:56:46.434039 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5130 06:56:46.437065 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5131 06:56:46.443797 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5132 06:56:46.447663 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 06:56:46.450838 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 06:56:46.457438 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 06:56:46.460464 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 06:56:46.463933 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 06:56:46.470737 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5138 06:56:46.473994 0 14 28 | B1->B0 | 3131 2525 | 0 0 | (0 0) (0 0)
5139 06:56:46.476981 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
5140 06:56:46.483872 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 06:56:46.487265 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 06:56:46.490645 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 06:56:46.497197 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 06:56:46.500183 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 06:56:46.503758 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 06:56:46.510845 0 15 28 | B1->B0 | 2626 4141 | 0 1 | (0 0) (0 0)
5147 06:56:46.514018 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5148 06:56:46.517021 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 06:56:46.524064 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 06:56:46.527403 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 06:56:46.530357 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 06:56:46.536843 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 06:56:46.540394 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 06:56:46.543427 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5155 06:56:46.546720 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 06:56:46.554038 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 06:56:46.557221 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 06:56:46.560448 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 06:56:46.567326 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 06:56:46.570624 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 06:56:46.573954 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 06:56:46.580383 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 06:56:46.583495 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 06:56:46.586854 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 06:56:46.593487 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 06:56:46.596852 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 06:56:46.599846 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 06:56:46.606554 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 06:56:46.610069 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5170 06:56:46.613271 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5171 06:56:46.620030 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 06:56:46.620598 Total UI for P1: 0, mck2ui 16
5173 06:56:46.626520 best dqsien dly found for B0: ( 1, 2, 26)
5174 06:56:46.626933 Total UI for P1: 0, mck2ui 16
5175 06:56:46.633354 best dqsien dly found for B1: ( 1, 2, 30)
5176 06:56:46.636558 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5177 06:56:46.639945 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5178 06:56:46.640516
5179 06:56:46.642897 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5180 06:56:46.646455 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5181 06:56:46.649881 [Gating] SW calibration Done
5182 06:56:46.650288 ==
5183 06:56:46.653093 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 06:56:46.656384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 06:56:46.656796 ==
5186 06:56:46.659867 RX Vref Scan: 0
5187 06:56:46.660441
5188 06:56:46.660781 RX Vref 0 -> 0, step: 1
5189 06:56:46.661086
5190 06:56:46.662945 RX Delay -80 -> 252, step: 8
5191 06:56:46.666450 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5192 06:56:46.672966 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5193 06:56:46.676582 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5194 06:56:46.679467 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5195 06:56:46.683397 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5196 06:56:46.686401 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5197 06:56:46.689826 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5198 06:56:46.696376 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5199 06:56:46.699470 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5200 06:56:46.703213 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5201 06:56:46.706629 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5202 06:56:46.709820 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5203 06:56:46.715945 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5204 06:56:46.719106 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5205 06:56:46.722832 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5206 06:56:46.726335 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5207 06:56:46.726896 ==
5208 06:56:46.729419 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 06:56:46.732520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 06:56:46.735922 ==
5211 06:56:46.736433 DQS Delay:
5212 06:56:46.736809 DQS0 = 0, DQS1 = 0
5213 06:56:46.739571 DQM Delay:
5214 06:56:46.740120 DQM0 = 104, DQM1 = 95
5215 06:56:46.742845 DQ Delay:
5216 06:56:46.746321 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5217 06:56:46.749412 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5218 06:56:46.752854 DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =91
5219 06:56:46.756046 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5220 06:56:46.756642
5221 06:56:46.757010
5222 06:56:46.757347 ==
5223 06:56:46.759332 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 06:56:46.762732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 06:56:46.763286 ==
5226 06:56:46.763748
5227 06:56:46.764099
5228 06:56:46.765743 TX Vref Scan disable
5229 06:56:46.769610 == TX Byte 0 ==
5230 06:56:46.772496 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5231 06:56:46.776422 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5232 06:56:46.779300 == TX Byte 1 ==
5233 06:56:46.782676 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5234 06:56:46.786540 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5235 06:56:46.787096 ==
5236 06:56:46.789749 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 06:56:46.792810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 06:56:46.793276 ==
5239 06:56:46.793640
5240 06:56:46.795986
5241 06:56:46.796525 TX Vref Scan disable
5242 06:56:46.799243 == TX Byte 0 ==
5243 06:56:46.803153 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5244 06:56:46.806631 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5245 06:56:46.809971 == TX Byte 1 ==
5246 06:56:46.813133 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5247 06:56:46.816072 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5248 06:56:46.819293
5249 06:56:46.819743 [DATLAT]
5250 06:56:46.820100 Freq=933, CH0 RK0
5251 06:56:46.820485
5252 06:56:46.822628 DATLAT Default: 0xd
5253 06:56:46.823101 0, 0xFFFF, sum = 0
5254 06:56:46.826369 1, 0xFFFF, sum = 0
5255 06:56:46.826829 2, 0xFFFF, sum = 0
5256 06:56:46.829702 3, 0xFFFF, sum = 0
5257 06:56:46.830278 4, 0xFFFF, sum = 0
5258 06:56:46.832605 5, 0xFFFF, sum = 0
5259 06:56:46.833317 6, 0xFFFF, sum = 0
5260 06:56:46.836025 7, 0xFFFF, sum = 0
5261 06:56:46.839541 8, 0xFFFF, sum = 0
5262 06:56:46.840097 9, 0xFFFF, sum = 0
5263 06:56:46.840578 10, 0x0, sum = 1
5264 06:56:46.843111 11, 0x0, sum = 2
5265 06:56:46.843743 12, 0x0, sum = 3
5266 06:56:46.846518 13, 0x0, sum = 4
5267 06:56:46.846976 best_step = 11
5268 06:56:46.847334
5269 06:56:46.847662 ==
5270 06:56:46.849564 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 06:56:46.856620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 06:56:46.857077 ==
5273 06:56:46.857432 RX Vref Scan: 1
5274 06:56:46.857763
5275 06:56:46.859982 RX Vref 0 -> 0, step: 1
5276 06:56:46.860663
5277 06:56:46.863357 RX Delay -53 -> 252, step: 4
5278 06:56:46.863929
5279 06:56:46.866508 Set Vref, RX VrefLevel [Byte0]: 54
5280 06:56:46.869640 [Byte1]: 46
5281 06:56:46.870196
5282 06:56:46.873088 Final RX Vref Byte 0 = 54 to rank0
5283 06:56:46.876179 Final RX Vref Byte 1 = 46 to rank0
5284 06:56:46.879301 Final RX Vref Byte 0 = 54 to rank1
5285 06:56:46.882778 Final RX Vref Byte 1 = 46 to rank1==
5286 06:56:46.886426 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 06:56:46.889321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 06:56:46.889876 ==
5289 06:56:46.892900 DQS Delay:
5290 06:56:46.893550 DQS0 = 0, DQS1 = 0
5291 06:56:46.893920 DQM Delay:
5292 06:56:46.896333 DQM0 = 104, DQM1 = 94
5293 06:56:46.896798 DQ Delay:
5294 06:56:46.899655 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5295 06:56:46.903226 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5296 06:56:46.905720 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =88
5297 06:56:46.913213 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5298 06:56:46.913750
5299 06:56:46.914109
5300 06:56:46.919501 [DQSOSCAuto] RK0, (LSB)MR18= 0x3028, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5301 06:56:46.922672 CH0 RK0: MR19=505, MR18=3028
5302 06:56:46.929177 CH0_RK0: MR19=0x505, MR18=0x3028, DQSOSC=406, MR23=63, INC=65, DEC=43
5303 06:56:46.929752
5304 06:56:46.933263 ----->DramcWriteLeveling(PI) begin...
5305 06:56:46.934005 ==
5306 06:56:46.936245 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 06:56:46.939610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 06:56:46.940165 ==
5309 06:56:46.942879 Write leveling (Byte 0): 34 => 34
5310 06:56:46.945885 Write leveling (Byte 1): 29 => 29
5311 06:56:46.949391 DramcWriteLeveling(PI) end<-----
5312 06:56:46.949847
5313 06:56:46.950210 ==
5314 06:56:46.952931 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 06:56:46.955942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 06:56:46.956532 ==
5317 06:56:46.959429 [Gating] SW mode calibration
5318 06:56:46.965819 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5319 06:56:46.972924 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5320 06:56:46.975933 0 14 0 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (1 1)
5321 06:56:46.979576 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 06:56:46.986759 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 06:56:46.989840 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 06:56:46.992903 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 06:56:46.999527 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 06:56:47.002379 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5327 06:56:47.005891 0 14 28 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
5328 06:56:47.012680 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5329 06:56:47.015606 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 06:56:47.018752 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 06:56:47.025762 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 06:56:47.028815 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 06:56:47.032150 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 06:56:47.039364 0 15 24 | B1->B0 | 2323 2424 | 1 0 | (0 0) (0 0)
5335 06:56:47.042352 0 15 28 | B1->B0 | 3c3c 3433 | 0 1 | (0 0) (0 0)
5336 06:56:47.045521 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 06:56:47.052249 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 06:56:47.055466 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 06:56:47.059183 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 06:56:47.065792 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 06:56:47.068640 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 06:56:47.072156 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 06:56:47.078593 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5344 06:56:47.082023 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5345 06:56:47.085746 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 06:56:47.088507 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 06:56:47.095587 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 06:56:47.099400 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 06:56:47.102599 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 06:56:47.108797 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 06:56:47.112379 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 06:56:47.115583 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 06:56:47.122505 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 06:56:47.125739 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 06:56:47.128943 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 06:56:47.135565 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 06:56:47.138879 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 06:56:47.142026 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5359 06:56:47.148907 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5360 06:56:47.151731 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5361 06:56:47.155781 Total UI for P1: 0, mck2ui 16
5362 06:56:47.159019 best dqsien dly found for B1: ( 1, 2, 28)
5363 06:56:47.161960 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 06:56:47.165545 Total UI for P1: 0, mck2ui 16
5365 06:56:47.168690 best dqsien dly found for B0: ( 1, 2, 28)
5366 06:56:47.172152 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5367 06:56:47.175051 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5368 06:56:47.175506
5369 06:56:47.182317 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5370 06:56:47.185218 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5371 06:56:47.185673 [Gating] SW calibration Done
5372 06:56:47.188393 ==
5373 06:56:47.192120 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 06:56:47.195442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 06:56:47.195994 ==
5376 06:56:47.196408 RX Vref Scan: 0
5377 06:56:47.196750
5378 06:56:47.198590 RX Vref 0 -> 0, step: 1
5379 06:56:47.199042
5380 06:56:47.201998 RX Delay -80 -> 252, step: 8
5381 06:56:47.205182 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5382 06:56:47.208795 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5383 06:56:47.211808 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5384 06:56:47.218679 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5385 06:56:47.221961 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5386 06:56:47.225166 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5387 06:56:47.228613 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5388 06:56:47.231653 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5389 06:56:47.235300 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5390 06:56:47.241752 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5391 06:56:47.245153 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5392 06:56:47.248273 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5393 06:56:47.251399 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5394 06:56:47.254871 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5395 06:56:47.258002 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5396 06:56:47.265256 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5397 06:56:47.265811 ==
5398 06:56:47.268215 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 06:56:47.271942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 06:56:47.272558 ==
5401 06:56:47.272933 DQS Delay:
5402 06:56:47.274929 DQS0 = 0, DQS1 = 0
5403 06:56:47.275385 DQM Delay:
5404 06:56:47.278140 DQM0 = 104, DQM1 = 94
5405 06:56:47.278598 DQ Delay:
5406 06:56:47.281959 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5407 06:56:47.285203 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5408 06:56:47.288550 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5409 06:56:47.291791 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5410 06:56:47.292545
5411 06:56:47.292998
5412 06:56:47.293449 ==
5413 06:56:47.294907 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 06:56:47.301796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 06:56:47.302255 ==
5416 06:56:47.302618
5417 06:56:47.302951
5418 06:56:47.303274 TX Vref Scan disable
5419 06:56:47.304987 == TX Byte 0 ==
5420 06:56:47.308621 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5421 06:56:47.312038 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5422 06:56:47.315123 == TX Byte 1 ==
5423 06:56:47.318753 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5424 06:56:47.325190 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5425 06:56:47.325657 ==
5426 06:56:47.328711 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 06:56:47.331653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 06:56:47.332114 ==
5429 06:56:47.332543
5430 06:56:47.332888
5431 06:56:47.335153 TX Vref Scan disable
5432 06:56:47.335857 == TX Byte 0 ==
5433 06:56:47.341632 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5434 06:56:47.344608 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5435 06:56:47.345064 == TX Byte 1 ==
5436 06:56:47.351753 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5437 06:56:47.355313 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5438 06:56:47.355875
5439 06:56:47.356240 [DATLAT]
5440 06:56:47.358232 Freq=933, CH0 RK1
5441 06:56:47.358690
5442 06:56:47.359069 DATLAT Default: 0xb
5443 06:56:47.361948 0, 0xFFFF, sum = 0
5444 06:56:47.362367 1, 0xFFFF, sum = 0
5445 06:56:47.365186 2, 0xFFFF, sum = 0
5446 06:56:47.365704 3, 0xFFFF, sum = 0
5447 06:56:47.368226 4, 0xFFFF, sum = 0
5448 06:56:47.371590 5, 0xFFFF, sum = 0
5449 06:56:47.372104 6, 0xFFFF, sum = 0
5450 06:56:47.374757 7, 0xFFFF, sum = 0
5451 06:56:47.375269 8, 0xFFFF, sum = 0
5452 06:56:47.378072 9, 0xFFFF, sum = 0
5453 06:56:47.378589 10, 0x0, sum = 1
5454 06:56:47.381625 11, 0x0, sum = 2
5455 06:56:47.382047 12, 0x0, sum = 3
5456 06:56:47.382380 13, 0x0, sum = 4
5457 06:56:47.384971 best_step = 11
5458 06:56:47.385382
5459 06:56:47.385708 ==
5460 06:56:47.388565 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 06:56:47.391730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 06:56:47.392259 ==
5463 06:56:47.394694 RX Vref Scan: 0
5464 06:56:47.395108
5465 06:56:47.395434 RX Vref 0 -> 0, step: 1
5466 06:56:47.397971
5467 06:56:47.398380 RX Delay -45 -> 252, step: 4
5468 06:56:47.405486 iDelay=195, Bit 0, Center 102 (15 ~ 190) 176
5469 06:56:47.408892 iDelay=195, Bit 1, Center 108 (23 ~ 194) 172
5470 06:56:47.411855 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5471 06:56:47.415848 iDelay=195, Bit 3, Center 100 (11 ~ 190) 180
5472 06:56:47.419082 iDelay=195, Bit 4, Center 106 (19 ~ 194) 176
5473 06:56:47.425951 iDelay=195, Bit 5, Center 98 (11 ~ 186) 176
5474 06:56:47.428640 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5475 06:56:47.431814 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5476 06:56:47.435501 iDelay=195, Bit 8, Center 88 (7 ~ 170) 164
5477 06:56:47.438686 iDelay=195, Bit 9, Center 82 (-1 ~ 166) 168
5478 06:56:47.441868 iDelay=195, Bit 10, Center 96 (15 ~ 178) 164
5479 06:56:47.448323 iDelay=195, Bit 11, Center 90 (11 ~ 170) 160
5480 06:56:47.451872 iDelay=195, Bit 12, Center 98 (19 ~ 178) 160
5481 06:56:47.455453 iDelay=195, Bit 13, Center 98 (15 ~ 182) 168
5482 06:56:47.458765 iDelay=195, Bit 14, Center 102 (19 ~ 186) 168
5483 06:56:47.465648 iDelay=195, Bit 15, Center 102 (19 ~ 186) 168
5484 06:56:47.466202 ==
5485 06:56:47.468459 Dram Type= 6, Freq= 0, CH_0, rank 1
5486 06:56:47.472485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 06:56:47.473051 ==
5488 06:56:47.473433 DQS Delay:
5489 06:56:47.475499 DQS0 = 0, DQS1 = 0
5490 06:56:47.475960 DQM Delay:
5491 06:56:47.479157 DQM0 = 104, DQM1 = 94
5492 06:56:47.479706 DQ Delay:
5493 06:56:47.482047 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =100
5494 06:56:47.485307 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =110
5495 06:56:47.488673 DQ8 =88, DQ9 =82, DQ10 =96, DQ11 =90
5496 06:56:47.491944 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5497 06:56:47.492543
5498 06:56:47.492906
5499 06:56:47.501545 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5500 06:56:47.502093 CH0 RK1: MR19=505, MR18=2A03
5501 06:56:47.508328 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5502 06:56:47.511505 [RxdqsGatingPostProcess] freq 933
5503 06:56:47.518748 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5504 06:56:47.521688 best DQS0 dly(2T, 0.5T) = (0, 10)
5505 06:56:47.524803 best DQS1 dly(2T, 0.5T) = (0, 10)
5506 06:56:47.529012 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5507 06:56:47.531993 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5508 06:56:47.534813 best DQS0 dly(2T, 0.5T) = (0, 10)
5509 06:56:47.535286 best DQS1 dly(2T, 0.5T) = (0, 10)
5510 06:56:47.538746 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5511 06:56:47.541690 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5512 06:56:47.544805 Pre-setting of DQS Precalculation
5513 06:56:47.551781 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5514 06:56:47.552241 ==
5515 06:56:47.554771 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 06:56:47.558067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 06:56:47.558529 ==
5518 06:56:47.564716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 06:56:47.571836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5520 06:56:47.575119 [CA 0] Center 36 (6~67) winsize 62
5521 06:56:47.578175 [CA 1] Center 37 (6~68) winsize 63
5522 06:56:47.581545 [CA 2] Center 34 (4~65) winsize 62
5523 06:56:47.585143 [CA 3] Center 34 (4~65) winsize 62
5524 06:56:47.588574 [CA 4] Center 34 (4~64) winsize 61
5525 06:56:47.591671 [CA 5] Center 33 (3~64) winsize 62
5526 06:56:47.592225
5527 06:56:47.594712 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5528 06:56:47.595184
5529 06:56:47.597955 [CATrainingPosCal] consider 1 rank data
5530 06:56:47.601474 u2DelayCellTimex100 = 270/100 ps
5531 06:56:47.604740 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 06:56:47.608580 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5533 06:56:47.611628 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5534 06:56:47.614743 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5535 06:56:47.618298 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5536 06:56:47.621870 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5537 06:56:47.622423
5538 06:56:47.625061 CA PerBit enable=1, Macro0, CA PI delay=33
5539 06:56:47.627983
5540 06:56:47.628591 [CBTSetCACLKResult] CA Dly = 33
5541 06:56:47.631301 CS Dly: 6 (0~37)
5542 06:56:47.631845 ==
5543 06:56:47.634242 Dram Type= 6, Freq= 0, CH_1, rank 1
5544 06:56:47.637574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 06:56:47.638039 ==
5546 06:56:47.644248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 06:56:47.651004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5548 06:56:47.654293 [CA 0] Center 36 (6~67) winsize 62
5549 06:56:47.657593 [CA 1] Center 37 (7~68) winsize 62
5550 06:56:47.660954 [CA 2] Center 35 (5~65) winsize 61
5551 06:56:47.664059 [CA 3] Center 34 (4~65) winsize 62
5552 06:56:47.667704 [CA 4] Center 34 (4~65) winsize 62
5553 06:56:47.670728 [CA 5] Center 33 (3~64) winsize 62
5554 06:56:47.671144
5555 06:56:47.674035 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5556 06:56:47.674452
5557 06:56:47.677976 [CATrainingPosCal] consider 2 rank data
5558 06:56:47.680982 u2DelayCellTimex100 = 270/100 ps
5559 06:56:47.684488 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 06:56:47.687523 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5561 06:56:47.691150 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5562 06:56:47.694456 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5563 06:56:47.697452 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5564 06:56:47.701138 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5565 06:56:47.701698
5566 06:56:47.707758 CA PerBit enable=1, Macro0, CA PI delay=33
5567 06:56:47.708364
5568 06:56:47.710864 [CBTSetCACLKResult] CA Dly = 33
5569 06:56:47.711424 CS Dly: 7 (0~40)
5570 06:56:47.711795
5571 06:56:47.714302 ----->DramcWriteLeveling(PI) begin...
5572 06:56:47.714875 ==
5573 06:56:47.717972 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 06:56:47.720519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 06:56:47.724564 ==
5576 06:56:47.725135 Write leveling (Byte 0): 28 => 28
5577 06:56:47.727907 Write leveling (Byte 1): 26 => 26
5578 06:56:47.731077 DramcWriteLeveling(PI) end<-----
5579 06:56:47.731631
5580 06:56:47.732068 ==
5581 06:56:47.733836 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 06:56:47.740433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 06:56:47.740900 ==
5584 06:56:47.741271 [Gating] SW mode calibration
5585 06:56:47.750671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5586 06:56:47.753982 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5587 06:56:47.757204 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 06:56:47.764232 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 06:56:47.767664 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 06:56:47.770832 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 06:56:47.777199 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 06:56:47.780899 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 06:56:47.783994 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5594 06:56:47.790837 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5595 06:56:47.793926 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 06:56:47.796826 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 06:56:47.804005 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 06:56:47.807043 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 06:56:47.810752 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 06:56:47.817010 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 06:56:47.820473 0 15 24 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
5602 06:56:47.823824 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5603 06:56:47.830472 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 06:56:47.833692 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 06:56:47.836750 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 06:56:47.843534 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 06:56:47.847423 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 06:56:47.850280 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 06:56:47.857416 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5610 06:56:47.860454 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 06:56:47.863749 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 06:56:47.870219 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 06:56:47.874023 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 06:56:47.877550 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 06:56:47.880623 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 06:56:47.887318 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 06:56:47.890289 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 06:56:47.893603 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 06:56:47.900421 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 06:56:47.903986 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 06:56:47.906901 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 06:56:47.913943 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 06:56:47.917040 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 06:56:47.920051 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 06:56:47.926870 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5626 06:56:47.930895 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5627 06:56:47.933935 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 06:56:47.936977 Total UI for P1: 0, mck2ui 16
5629 06:56:47.940587 best dqsien dly found for B0: ( 1, 2, 26)
5630 06:56:47.943566 Total UI for P1: 0, mck2ui 16
5631 06:56:47.947041 best dqsien dly found for B1: ( 1, 2, 28)
5632 06:56:47.949987 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5633 06:56:47.954107 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5634 06:56:47.954659
5635 06:56:47.960265 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5636 06:56:47.963646 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5637 06:56:47.964110 [Gating] SW calibration Done
5638 06:56:47.967138 ==
5639 06:56:47.970285 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 06:56:47.973992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 06:56:47.974546 ==
5642 06:56:47.974916 RX Vref Scan: 0
5643 06:56:47.975264
5644 06:56:47.976791 RX Vref 0 -> 0, step: 1
5645 06:56:47.977249
5646 06:56:47.980142 RX Delay -80 -> 252, step: 8
5647 06:56:47.983733 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5648 06:56:47.987122 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5649 06:56:47.990205 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5650 06:56:47.997010 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5651 06:56:48.000454 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5652 06:56:48.003522 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5653 06:56:48.006643 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5654 06:56:48.010316 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5655 06:56:48.013250 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5656 06:56:48.020099 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5657 06:56:48.023385 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5658 06:56:48.026333 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5659 06:56:48.029997 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5660 06:56:48.033601 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5661 06:56:48.036379 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5662 06:56:48.043280 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5663 06:56:48.043739 ==
5664 06:56:48.046799 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 06:56:48.049793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 06:56:48.050262 ==
5667 06:56:48.050631 DQS Delay:
5668 06:56:48.053449 DQS0 = 0, DQS1 = 0
5669 06:56:48.053908 DQM Delay:
5670 06:56:48.056646 DQM0 = 102, DQM1 = 99
5671 06:56:48.057107 DQ Delay:
5672 06:56:48.059713 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5673 06:56:48.063660 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5674 06:56:48.066698 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5675 06:56:48.070378 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5676 06:56:48.070889
5677 06:56:48.071221
5678 06:56:48.071523 ==
5679 06:56:48.073370 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 06:56:48.080462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 06:56:48.080977 ==
5682 06:56:48.081311
5683 06:56:48.081623
5684 06:56:48.081920 TX Vref Scan disable
5685 06:56:48.083609 == TX Byte 0 ==
5686 06:56:48.086702 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5687 06:56:48.093545 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5688 06:56:48.094057 == TX Byte 1 ==
5689 06:56:48.096588 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5690 06:56:48.103427 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5691 06:56:48.103978 ==
5692 06:56:48.106867 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 06:56:48.110458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 06:56:48.110971 ==
5695 06:56:48.111309
5696 06:56:48.111617
5697 06:56:48.113553 TX Vref Scan disable
5698 06:56:48.114065 == TX Byte 0 ==
5699 06:56:48.120062 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5700 06:56:48.123574 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5701 06:56:48.124085 == TX Byte 1 ==
5702 06:56:48.130032 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5703 06:56:48.133231 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5704 06:56:48.133652
5705 06:56:48.133982 [DATLAT]
5706 06:56:48.136540 Freq=933, CH1 RK0
5707 06:56:48.137054
5708 06:56:48.137390 DATLAT Default: 0xd
5709 06:56:48.140106 0, 0xFFFF, sum = 0
5710 06:56:48.140665 1, 0xFFFF, sum = 0
5711 06:56:48.142961 2, 0xFFFF, sum = 0
5712 06:56:48.143385 3, 0xFFFF, sum = 0
5713 06:56:48.146641 4, 0xFFFF, sum = 0
5714 06:56:48.149692 5, 0xFFFF, sum = 0
5715 06:56:48.150193 6, 0xFFFF, sum = 0
5716 06:56:48.153042 7, 0xFFFF, sum = 0
5717 06:56:48.153552 8, 0xFFFF, sum = 0
5718 06:56:48.156601 9, 0xFFFF, sum = 0
5719 06:56:48.157053 10, 0x0, sum = 1
5720 06:56:48.159446 11, 0x0, sum = 2
5721 06:56:48.159871 12, 0x0, sum = 3
5722 06:56:48.160207 13, 0x0, sum = 4
5723 06:56:48.163073 best_step = 11
5724 06:56:48.163485
5725 06:56:48.163809 ==
5726 06:56:48.166209 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 06:56:48.169720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 06:56:48.170138 ==
5729 06:56:48.172830 RX Vref Scan: 1
5730 06:56:48.173247
5731 06:56:48.173576 RX Vref 0 -> 0, step: 1
5732 06:56:48.176373
5733 06:56:48.176879 RX Delay -45 -> 252, step: 4
5734 06:56:48.177216
5735 06:56:48.179866 Set Vref, RX VrefLevel [Byte0]: 55
5736 06:56:48.182941 [Byte1]: 49
5737 06:56:48.187572
5738 06:56:48.188078 Final RX Vref Byte 0 = 55 to rank0
5739 06:56:48.190545 Final RX Vref Byte 1 = 49 to rank0
5740 06:56:48.194399 Final RX Vref Byte 0 = 55 to rank1
5741 06:56:48.197514 Final RX Vref Byte 1 = 49 to rank1==
5742 06:56:48.200737 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 06:56:48.206856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 06:56:48.207359 ==
5745 06:56:48.207694 DQS Delay:
5746 06:56:48.208005 DQS0 = 0, DQS1 = 0
5747 06:56:48.210778 DQM Delay:
5748 06:56:48.211194 DQM0 = 104, DQM1 = 101
5749 06:56:48.214141 DQ Delay:
5750 06:56:48.217451 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5751 06:56:48.220529 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =104
5752 06:56:48.223572 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =94
5753 06:56:48.227050 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =110
5754 06:56:48.227564
5755 06:56:48.227895
5756 06:56:48.233789 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5757 06:56:48.237355 CH1 RK0: MR19=505, MR18=1830
5758 06:56:48.243071 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5759 06:56:48.243494
5760 06:56:48.247048 ----->DramcWriteLeveling(PI) begin...
5761 06:56:48.247568 ==
5762 06:56:48.249948 Dram Type= 6, Freq= 0, CH_1, rank 1
5763 06:56:48.256174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 06:56:48.256677 ==
5765 06:56:48.260126 Write leveling (Byte 0): 28 => 28
5766 06:56:48.260620 Write leveling (Byte 1): 29 => 29
5767 06:56:48.262898 DramcWriteLeveling(PI) end<-----
5768 06:56:48.263315
5769 06:56:48.266534 ==
5770 06:56:48.266998 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 06:56:48.273038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 06:56:48.273458 ==
5773 06:56:48.276463 [Gating] SW mode calibration
5774 06:56:48.282903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5775 06:56:48.286783 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5776 06:56:48.293118 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 06:56:48.296267 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 06:56:48.299935 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 06:56:48.306102 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 06:56:48.309520 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 06:56:48.313068 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 06:56:48.319618 0 14 24 | B1->B0 | 2d2d 3030 | 0 1 | (0 0) (1 1)
5783 06:56:48.322766 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5784 06:56:48.325983 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 06:56:48.332868 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 06:56:48.336365 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 06:56:48.339022 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 06:56:48.345955 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 06:56:48.349017 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 06:56:48.352522 0 15 24 | B1->B0 | 3333 2929 | 0 0 | (1 1) (1 1)
5791 06:56:48.359119 0 15 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5792 06:56:48.362513 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 06:56:48.366252 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 06:56:48.372388 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 06:56:48.375717 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 06:56:48.379132 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 06:56:48.385606 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 06:56:48.388679 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5799 06:56:48.392415 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5800 06:56:48.398913 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 06:56:48.402155 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 06:56:48.405700 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 06:56:48.408699 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 06:56:48.415682 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 06:56:48.419088 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 06:56:48.422124 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 06:56:48.429069 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 06:56:48.432725 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 06:56:48.435343 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 06:56:48.442382 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 06:56:48.445611 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 06:56:48.448549 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 06:56:48.455766 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 06:56:48.458962 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 06:56:48.462600 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5816 06:56:48.465435 Total UI for P1: 0, mck2ui 16
5817 06:56:48.469271 best dqsien dly found for B1: ( 1, 2, 26)
5818 06:56:48.475477 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 06:56:48.476038 Total UI for P1: 0, mck2ui 16
5820 06:56:48.482313 best dqsien dly found for B0: ( 1, 2, 28)
5821 06:56:48.485734 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5822 06:56:48.488715 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5823 06:56:48.489174
5824 06:56:48.491792 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5825 06:56:48.495544 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5826 06:56:48.498799 [Gating] SW calibration Done
5827 06:56:48.499256 ==
5828 06:56:48.502043 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 06:56:48.505444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 06:56:48.506020 ==
5831 06:56:48.508541 RX Vref Scan: 0
5832 06:56:48.508999
5833 06:56:48.509363 RX Vref 0 -> 0, step: 1
5834 06:56:48.509703
5835 06:56:48.511755 RX Delay -80 -> 252, step: 8
5836 06:56:48.515472 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5837 06:56:48.522046 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5838 06:56:48.525300 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5839 06:56:48.528547 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5840 06:56:48.531804 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5841 06:56:48.535447 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5842 06:56:48.538519 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5843 06:56:48.545459 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5844 06:56:48.548651 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5845 06:56:48.551628 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5846 06:56:48.554963 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5847 06:56:48.558644 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5848 06:56:48.561971 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5849 06:56:48.568558 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5850 06:56:48.572214 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5851 06:56:48.575122 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5852 06:56:48.575542 ==
5853 06:56:48.578617 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 06:56:48.581545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 06:56:48.581965 ==
5856 06:56:48.584998 DQS Delay:
5857 06:56:48.585503 DQS0 = 0, DQS1 = 0
5858 06:56:48.588488 DQM Delay:
5859 06:56:48.588904 DQM0 = 102, DQM1 = 99
5860 06:56:48.591903 DQ Delay:
5861 06:56:48.592359 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5862 06:56:48.594810 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5863 06:56:48.598101 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =91
5864 06:56:48.604918 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5865 06:56:48.605416
5866 06:56:48.605747
5867 06:56:48.606050 ==
5868 06:56:48.608454 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 06:56:48.611629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 06:56:48.612142 ==
5871 06:56:48.612593
5872 06:56:48.612913
5873 06:56:48.614890 TX Vref Scan disable
5874 06:56:48.615398 == TX Byte 0 ==
5875 06:56:48.621485 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5876 06:56:48.625159 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5877 06:56:48.625679 == TX Byte 1 ==
5878 06:56:48.631641 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5879 06:56:48.634877 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5880 06:56:48.635390 ==
5881 06:56:48.638415 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 06:56:48.641467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 06:56:48.641889 ==
5884 06:56:48.642217
5885 06:56:48.644949
5886 06:56:48.645399 TX Vref Scan disable
5887 06:56:48.648100 == TX Byte 0 ==
5888 06:56:48.651291 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5889 06:56:48.654455 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5890 06:56:48.658341 == TX Byte 1 ==
5891 06:56:48.661073 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5892 06:56:48.664684 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5893 06:56:48.667698
5894 06:56:48.668133 [DATLAT]
5895 06:56:48.668542 Freq=933, CH1 RK1
5896 06:56:48.668860
5897 06:56:48.671249 DATLAT Default: 0xb
5898 06:56:48.671663 0, 0xFFFF, sum = 0
5899 06:56:48.674927 1, 0xFFFF, sum = 0
5900 06:56:48.675444 2, 0xFFFF, sum = 0
5901 06:56:48.678212 3, 0xFFFF, sum = 0
5902 06:56:48.678876 4, 0xFFFF, sum = 0
5903 06:56:48.681137 5, 0xFFFF, sum = 0
5904 06:56:48.681561 6, 0xFFFF, sum = 0
5905 06:56:48.684507 7, 0xFFFF, sum = 0
5906 06:56:48.687751 8, 0xFFFF, sum = 0
5907 06:56:48.688472 9, 0xFFFF, sum = 0
5908 06:56:48.688841 10, 0x0, sum = 1
5909 06:56:48.691381 11, 0x0, sum = 2
5910 06:56:48.691812 12, 0x0, sum = 3
5911 06:56:48.694688 13, 0x0, sum = 4
5912 06:56:48.695132 best_step = 11
5913 06:56:48.695486
5914 06:56:48.695831 ==
5915 06:56:48.698103 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 06:56:48.704863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 06:56:48.705335 ==
5918 06:56:48.705673 RX Vref Scan: 0
5919 06:56:48.706020
5920 06:56:48.707728 RX Vref 0 -> 0, step: 1
5921 06:56:48.708143
5922 06:56:48.711168 RX Delay -45 -> 252, step: 4
5923 06:56:48.714815 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5924 06:56:48.721797 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5925 06:56:48.724976 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5926 06:56:48.728262 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5927 06:56:48.731442 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5928 06:56:48.734925 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5929 06:56:48.738158 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5930 06:56:48.744667 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5931 06:56:48.748141 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5932 06:56:48.751256 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5933 06:56:48.754588 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5934 06:56:48.758060 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5935 06:56:48.761726 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5936 06:56:48.767717 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5937 06:56:48.771433 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5938 06:56:48.774822 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5939 06:56:48.775373 ==
5940 06:56:48.778004 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 06:56:48.784424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 06:56:48.784995 ==
5943 06:56:48.785362 DQS Delay:
5944 06:56:48.785703 DQS0 = 0, DQS1 = 0
5945 06:56:48.788000 DQM Delay:
5946 06:56:48.788651 DQM0 = 104, DQM1 = 100
5947 06:56:48.791093 DQ Delay:
5948 06:56:48.794789 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5949 06:56:48.797771 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5950 06:56:48.801071 DQ8 =88, DQ9 =88, DQ10 =98, DQ11 =94
5951 06:56:48.804597 DQ12 =110, DQ13 =108, DQ14 =106, DQ15 =110
5952 06:56:48.805208
5953 06:56:48.805620
5954 06:56:48.811078 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5955 06:56:48.814465 CH1 RK1: MR19=505, MR18=2E01
5956 06:56:48.821189 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5957 06:56:48.824259 [RxdqsGatingPostProcess] freq 933
5958 06:56:48.830779 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5959 06:56:48.834139 best DQS0 dly(2T, 0.5T) = (0, 10)
5960 06:56:48.834704 best DQS1 dly(2T, 0.5T) = (0, 10)
5961 06:56:48.837214 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5962 06:56:48.841297 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5963 06:56:48.843829 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 06:56:48.847842 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 06:56:48.850779 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 06:56:48.854110 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 06:56:48.857665 Pre-setting of DQS Precalculation
5968 06:56:48.864383 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5969 06:56:48.871098 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5970 06:56:48.877615 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5971 06:56:48.878170
5972 06:56:48.878534
5973 06:56:48.880959 [Calibration Summary] 1866 Mbps
5974 06:56:48.881419 CH 0, Rank 0
5975 06:56:48.884019 SW Impedance : PASS
5976 06:56:48.887581 DUTY Scan : NO K
5977 06:56:48.888131 ZQ Calibration : PASS
5978 06:56:48.890662 Jitter Meter : NO K
5979 06:56:48.891121 CBT Training : PASS
5980 06:56:48.894175 Write leveling : PASS
5981 06:56:48.897318 RX DQS gating : PASS
5982 06:56:48.897875 RX DQ/DQS(RDDQC) : PASS
5983 06:56:48.901196 TX DQ/DQS : PASS
5984 06:56:48.904474 RX DATLAT : PASS
5985 06:56:48.905023 RX DQ/DQS(Engine): PASS
5986 06:56:48.907056 TX OE : NO K
5987 06:56:48.907519 All Pass.
5988 06:56:48.907883
5989 06:56:48.910538 CH 0, Rank 1
5990 06:56:48.910996 SW Impedance : PASS
5991 06:56:48.914449 DUTY Scan : NO K
5992 06:56:48.917236 ZQ Calibration : PASS
5993 06:56:48.917696 Jitter Meter : NO K
5994 06:56:48.920666 CBT Training : PASS
5995 06:56:48.924244 Write leveling : PASS
5996 06:56:48.924750 RX DQS gating : PASS
5997 06:56:48.927063 RX DQ/DQS(RDDQC) : PASS
5998 06:56:48.930775 TX DQ/DQS : PASS
5999 06:56:48.931335 RX DATLAT : PASS
6000 06:56:48.934181 RX DQ/DQS(Engine): PASS
6001 06:56:48.937158 TX OE : NO K
6002 06:56:48.937626 All Pass.
6003 06:56:48.938047
6004 06:56:48.938399 CH 1, Rank 0
6005 06:56:48.940263 SW Impedance : PASS
6006 06:56:48.943934 DUTY Scan : NO K
6007 06:56:48.944585 ZQ Calibration : PASS
6008 06:56:48.947174 Jitter Meter : NO K
6009 06:56:48.947635 CBT Training : PASS
6010 06:56:48.950083 Write leveling : PASS
6011 06:56:48.953856 RX DQS gating : PASS
6012 06:56:48.954412 RX DQ/DQS(RDDQC) : PASS
6013 06:56:48.956939 TX DQ/DQS : PASS
6014 06:56:48.959933 RX DATLAT : PASS
6015 06:56:48.960444 RX DQ/DQS(Engine): PASS
6016 06:56:48.963409 TX OE : NO K
6017 06:56:48.963889 All Pass.
6018 06:56:48.964423
6019 06:56:48.966857 CH 1, Rank 1
6020 06:56:48.967318 SW Impedance : PASS
6021 06:56:48.970465 DUTY Scan : NO K
6022 06:56:48.973932 ZQ Calibration : PASS
6023 06:56:48.974483 Jitter Meter : NO K
6024 06:56:48.976926 CBT Training : PASS
6025 06:56:48.980442 Write leveling : PASS
6026 06:56:48.980996 RX DQS gating : PASS
6027 06:56:48.983714 RX DQ/DQS(RDDQC) : PASS
6028 06:56:48.987271 TX DQ/DQS : PASS
6029 06:56:48.987735 RX DATLAT : PASS
6030 06:56:48.990173 RX DQ/DQS(Engine): PASS
6031 06:56:48.990725 TX OE : NO K
6032 06:56:48.994108 All Pass.
6033 06:56:48.994656
6034 06:56:48.995019 DramC Write-DBI off
6035 06:56:48.997017 PER_BANK_REFRESH: Hybrid Mode
6036 06:56:49.000391 TX_TRACKING: ON
6037 06:56:49.007487 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6038 06:56:49.010621 [FAST_K] Save calibration result to emmc
6039 06:56:49.016801 dramc_set_vcore_voltage set vcore to 650000
6040 06:56:49.017344 Read voltage for 400, 6
6041 06:56:49.017713 Vio18 = 0
6042 06:56:49.020671 Vcore = 650000
6043 06:56:49.021242 Vdram = 0
6044 06:56:49.021612 Vddq = 0
6045 06:56:49.023548 Vmddr = 0
6046 06:56:49.027104 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6047 06:56:49.033389 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6048 06:56:49.037247 MEM_TYPE=3, freq_sel=20
6049 06:56:49.037797 sv_algorithm_assistance_LP4_800
6050 06:56:49.043323 ============ PULL DRAM RESETB DOWN ============
6051 06:56:49.046636 ========== PULL DRAM RESETB DOWN end =========
6052 06:56:49.049817 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6053 06:56:49.053641 ===================================
6054 06:56:49.057117 LPDDR4 DRAM CONFIGURATION
6055 06:56:49.060166 ===================================
6056 06:56:49.063279 EX_ROW_EN[0] = 0x0
6057 06:56:49.063825 EX_ROW_EN[1] = 0x0
6058 06:56:49.066999 LP4Y_EN = 0x0
6059 06:56:49.067550 WORK_FSP = 0x0
6060 06:56:49.070377 WL = 0x2
6061 06:56:49.070928 RL = 0x2
6062 06:56:49.073191 BL = 0x2
6063 06:56:49.073651 RPST = 0x0
6064 06:56:49.076469 RD_PRE = 0x0
6065 06:56:49.076930 WR_PRE = 0x1
6066 06:56:49.079883 WR_PST = 0x0
6067 06:56:49.080488 DBI_WR = 0x0
6068 06:56:49.083367 DBI_RD = 0x0
6069 06:56:49.083923 OTF = 0x1
6070 06:56:49.086915 ===================================
6071 06:56:49.089671 ===================================
6072 06:56:49.093385 ANA top config
6073 06:56:49.096687 ===================================
6074 06:56:49.100246 DLL_ASYNC_EN = 0
6075 06:56:49.100855 ALL_SLAVE_EN = 1
6076 06:56:49.103529 NEW_RANK_MODE = 1
6077 06:56:49.106519 DLL_IDLE_MODE = 1
6078 06:56:49.110164 LP45_APHY_COMB_EN = 1
6079 06:56:49.110625 TX_ODT_DIS = 1
6080 06:56:49.113718 NEW_8X_MODE = 1
6081 06:56:49.117138 ===================================
6082 06:56:49.120419 ===================================
6083 06:56:49.123621 data_rate = 800
6084 06:56:49.126959 CKR = 1
6085 06:56:49.130223 DQ_P2S_RATIO = 4
6086 06:56:49.133624 ===================================
6087 06:56:49.136368 CA_P2S_RATIO = 4
6088 06:56:49.136857 DQ_CA_OPEN = 0
6089 06:56:49.140423 DQ_SEMI_OPEN = 1
6090 06:56:49.143460 CA_SEMI_OPEN = 1
6091 06:56:49.146471 CA_FULL_RATE = 0
6092 06:56:49.149831 DQ_CKDIV4_EN = 0
6093 06:56:49.153373 CA_CKDIV4_EN = 1
6094 06:56:49.153873 CA_PREDIV_EN = 0
6095 06:56:49.156984 PH8_DLY = 0
6096 06:56:49.160087 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6097 06:56:49.162796 DQ_AAMCK_DIV = 0
6098 06:56:49.166384 CA_AAMCK_DIV = 0
6099 06:56:49.169771 CA_ADMCK_DIV = 4
6100 06:56:49.170334 DQ_TRACK_CA_EN = 0
6101 06:56:49.173652 CA_PICK = 800
6102 06:56:49.177103 CA_MCKIO = 400
6103 06:56:49.179839 MCKIO_SEMI = 400
6104 06:56:49.183098 PLL_FREQ = 3016
6105 06:56:49.186576 DQ_UI_PI_RATIO = 32
6106 06:56:49.189966 CA_UI_PI_RATIO = 32
6107 06:56:49.193250 ===================================
6108 06:56:49.196398 ===================================
6109 06:56:49.196948 memory_type:LPDDR4
6110 06:56:49.199711 GP_NUM : 10
6111 06:56:49.203469 SRAM_EN : 1
6112 06:56:49.204031 MD32_EN : 0
6113 06:56:49.206782 ===================================
6114 06:56:49.209376 [ANA_INIT] >>>>>>>>>>>>>>
6115 06:56:49.212866 <<<<<< [CONFIGURE PHASE]: ANA_TX
6116 06:56:49.216969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6117 06:56:49.219586 ===================================
6118 06:56:49.222714 data_rate = 800,PCW = 0X7400
6119 06:56:49.226610 ===================================
6120 06:56:49.229697 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6121 06:56:49.232752 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6122 06:56:49.245993 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6123 06:56:49.249591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6124 06:56:49.252780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6125 06:56:49.255840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6126 06:56:49.259388 [ANA_INIT] flow start
6127 06:56:49.259937 [ANA_INIT] PLL >>>>>>>>
6128 06:56:49.263184 [ANA_INIT] PLL <<<<<<<<
6129 06:56:49.265962 [ANA_INIT] MIDPI >>>>>>>>
6130 06:56:49.269278 [ANA_INIT] MIDPI <<<<<<<<
6131 06:56:49.269804 [ANA_INIT] DLL >>>>>>>>
6132 06:56:49.272626 [ANA_INIT] flow end
6133 06:56:49.276529 ============ LP4 DIFF to SE enter ============
6134 06:56:49.279707 ============ LP4 DIFF to SE exit ============
6135 06:56:49.283033 [ANA_INIT] <<<<<<<<<<<<<
6136 06:56:49.286290 [Flow] Enable top DCM control >>>>>
6137 06:56:49.289338 [Flow] Enable top DCM control <<<<<
6138 06:56:49.292463 Enable DLL master slave shuffle
6139 06:56:49.299121 ==============================================================
6140 06:56:49.299685 Gating Mode config
6141 06:56:49.305831 ==============================================================
6142 06:56:49.306290 Config description:
6143 06:56:49.316207 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6144 06:56:49.322390 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6145 06:56:49.329436 SELPH_MODE 0: By rank 1: By Phase
6146 06:56:49.332520 ==============================================================
6147 06:56:49.335837 GAT_TRACK_EN = 0
6148 06:56:49.338895 RX_GATING_MODE = 2
6149 06:56:49.342610 RX_GATING_TRACK_MODE = 2
6150 06:56:49.345828 SELPH_MODE = 1
6151 06:56:49.348845 PICG_EARLY_EN = 1
6152 06:56:49.352411 VALID_LAT_VALUE = 1
6153 06:56:49.355787 ==============================================================
6154 06:56:49.359301 Enter into Gating configuration >>>>
6155 06:56:49.362781 Exit from Gating configuration <<<<
6156 06:56:49.365494 Enter into DVFS_PRE_config >>>>>
6157 06:56:49.378754 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6158 06:56:49.382197 Exit from DVFS_PRE_config <<<<<
6159 06:56:49.385332 Enter into PICG configuration >>>>
6160 06:56:49.385795 Exit from PICG configuration <<<<
6161 06:56:49.389358 [RX_INPUT] configuration >>>>>
6162 06:56:49.392464 [RX_INPUT] configuration <<<<<
6163 06:56:49.399193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6164 06:56:49.402225 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6165 06:56:49.409262 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6166 06:56:49.416133 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6167 06:56:49.422108 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6168 06:56:49.429449 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6169 06:56:49.432868 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6170 06:56:49.436018 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6171 06:56:49.438868 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6172 06:56:49.445506 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6173 06:56:49.449180 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6174 06:56:49.452229 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6175 06:56:49.455641 ===================================
6176 06:56:49.459231 LPDDR4 DRAM CONFIGURATION
6177 06:56:49.462105 ===================================
6178 06:56:49.465306 EX_ROW_EN[0] = 0x0
6179 06:56:49.465770 EX_ROW_EN[1] = 0x0
6180 06:56:49.468688 LP4Y_EN = 0x0
6181 06:56:49.469145 WORK_FSP = 0x0
6182 06:56:49.472341 WL = 0x2
6183 06:56:49.472806 RL = 0x2
6184 06:56:49.475502 BL = 0x2
6185 06:56:49.476059 RPST = 0x0
6186 06:56:49.478962 RD_PRE = 0x0
6187 06:56:49.479443 WR_PRE = 0x1
6188 06:56:49.482499 WR_PST = 0x0
6189 06:56:49.483057 DBI_WR = 0x0
6190 06:56:49.485564 DBI_RD = 0x0
6191 06:56:49.486030 OTF = 0x1
6192 06:56:49.488485 ===================================
6193 06:56:49.495768 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6194 06:56:49.499025 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6195 06:56:49.502024 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6196 06:56:49.505312 ===================================
6197 06:56:49.508732 LPDDR4 DRAM CONFIGURATION
6198 06:56:49.512231 ===================================
6199 06:56:49.512852 EX_ROW_EN[0] = 0x10
6200 06:56:49.515896 EX_ROW_EN[1] = 0x0
6201 06:56:49.518830 LP4Y_EN = 0x0
6202 06:56:49.519386 WORK_FSP = 0x0
6203 06:56:49.521725 WL = 0x2
6204 06:56:49.522182 RL = 0x2
6205 06:56:49.525507 BL = 0x2
6206 06:56:49.525969 RPST = 0x0
6207 06:56:49.528679 RD_PRE = 0x0
6208 06:56:49.529136 WR_PRE = 0x1
6209 06:56:49.532116 WR_PST = 0x0
6210 06:56:49.532737 DBI_WR = 0x0
6211 06:56:49.535309 DBI_RD = 0x0
6212 06:56:49.535869 OTF = 0x1
6213 06:56:49.538980 ===================================
6214 06:56:49.545497 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6215 06:56:49.549642 nWR fixed to 30
6216 06:56:49.552851 [ModeRegInit_LP4] CH0 RK0
6217 06:56:49.553312 [ModeRegInit_LP4] CH0 RK1
6218 06:56:49.555934 [ModeRegInit_LP4] CH1 RK0
6219 06:56:49.559439 [ModeRegInit_LP4] CH1 RK1
6220 06:56:49.560001 match AC timing 19
6221 06:56:49.566017 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6222 06:56:49.569143 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6223 06:56:49.572969 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6224 06:56:49.579525 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6225 06:56:49.582677 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6226 06:56:49.583239 ==
6227 06:56:49.586189 Dram Type= 6, Freq= 0, CH_0, rank 0
6228 06:56:49.589542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6229 06:56:49.590140 ==
6230 06:56:49.596117 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6231 06:56:49.602494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6232 06:56:49.605730 [CA 0] Center 36 (8~64) winsize 57
6233 06:56:49.609224 [CA 1] Center 36 (8~64) winsize 57
6234 06:56:49.612674 [CA 2] Center 36 (8~64) winsize 57
6235 06:56:49.616180 [CA 3] Center 36 (8~64) winsize 57
6236 06:56:49.616798 [CA 4] Center 36 (8~64) winsize 57
6237 06:56:49.619645 [CA 5] Center 36 (8~64) winsize 57
6238 06:56:49.620214
6239 06:56:49.626052 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6240 06:56:49.626510
6241 06:56:49.628961 [CATrainingPosCal] consider 1 rank data
6242 06:56:49.632781 u2DelayCellTimex100 = 270/100 ps
6243 06:56:49.636112 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 06:56:49.639201 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 06:56:49.642483 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 06:56:49.645482 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 06:56:49.649337 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 06:56:49.652499 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 06:56:49.652964
6250 06:56:49.655658 CA PerBit enable=1, Macro0, CA PI delay=36
6251 06:56:49.656125
6252 06:56:49.659475 [CBTSetCACLKResult] CA Dly = 36
6253 06:56:49.662568 CS Dly: 1 (0~32)
6254 06:56:49.663027 ==
6255 06:56:49.665835 Dram Type= 6, Freq= 0, CH_0, rank 1
6256 06:56:49.668857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 06:56:49.669318 ==
6258 06:56:49.675923 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 06:56:49.678705 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6260 06:56:49.682808 [CA 0] Center 36 (8~64) winsize 57
6261 06:56:49.685864 [CA 1] Center 36 (8~64) winsize 57
6262 06:56:49.689079 [CA 2] Center 36 (8~64) winsize 57
6263 06:56:49.692330 [CA 3] Center 36 (8~64) winsize 57
6264 06:56:49.695457 [CA 4] Center 36 (8~64) winsize 57
6265 06:56:49.698983 [CA 5] Center 36 (8~64) winsize 57
6266 06:56:49.699440
6267 06:56:49.701989 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6268 06:56:49.702449
6269 06:56:49.705219 [CATrainingPosCal] consider 2 rank data
6270 06:56:49.708779 u2DelayCellTimex100 = 270/100 ps
6271 06:56:49.712113 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 06:56:49.715373 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 06:56:49.722358 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 06:56:49.724891 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 06:56:49.728926 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 06:56:49.731864 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 06:56:49.732277
6278 06:56:49.734825 CA PerBit enable=1, Macro0, CA PI delay=36
6279 06:56:49.735242
6280 06:56:49.738776 [CBTSetCACLKResult] CA Dly = 36
6281 06:56:49.739280 CS Dly: 1 (0~32)
6282 06:56:49.739802
6283 06:56:49.741627 ----->DramcWriteLeveling(PI) begin...
6284 06:56:49.744878 ==
6285 06:56:49.748321 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 06:56:49.751516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 06:56:49.751938 ==
6288 06:56:49.754832 Write leveling (Byte 0): 40 => 8
6289 06:56:49.758402 Write leveling (Byte 1): 40 => 8
6290 06:56:49.762134 DramcWriteLeveling(PI) end<-----
6291 06:56:49.762653
6292 06:56:49.762987 ==
6293 06:56:49.764865 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 06:56:49.768233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 06:56:49.768682 ==
6296 06:56:49.771715 [Gating] SW mode calibration
6297 06:56:49.778454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6298 06:56:49.784986 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6299 06:56:49.788916 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6300 06:56:49.791668 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6301 06:56:49.795533 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 06:56:49.802196 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6303 06:56:49.804985 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 06:56:49.808211 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 06:56:49.815687 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 06:56:49.818719 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 06:56:49.821548 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 06:56:49.825328 Total UI for P1: 0, mck2ui 16
6309 06:56:49.828345 best dqsien dly found for B0: ( 0, 14, 24)
6310 06:56:49.831931 Total UI for P1: 0, mck2ui 16
6311 06:56:49.835260 best dqsien dly found for B1: ( 0, 14, 24)
6312 06:56:49.839007 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6313 06:56:49.841817 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6314 06:56:49.842274
6315 06:56:49.848437 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6316 06:56:49.851670 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6317 06:56:49.852131 [Gating] SW calibration Done
6318 06:56:49.855521 ==
6319 06:56:49.858920 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 06:56:49.861579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 06:56:49.862044 ==
6322 06:56:49.862410 RX Vref Scan: 0
6323 06:56:49.862746
6324 06:56:49.864917 RX Vref 0 -> 0, step: 1
6325 06:56:49.865374
6326 06:56:49.868151 RX Delay -410 -> 252, step: 16
6327 06:56:49.872364 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6328 06:56:49.875041 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6329 06:56:49.881727 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6330 06:56:49.884867 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6331 06:56:49.888418 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6332 06:56:49.891643 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6333 06:56:49.898146 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6334 06:56:49.901495 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6335 06:56:49.905012 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6336 06:56:49.908693 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6337 06:56:49.915442 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6338 06:56:49.918565 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6339 06:56:49.921781 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6340 06:56:49.924994 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6341 06:56:49.931600 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6342 06:56:49.935478 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6343 06:56:49.935947 ==
6344 06:56:49.938412 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 06:56:49.941437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 06:56:49.941895 ==
6347 06:56:49.945422 DQS Delay:
6348 06:56:49.945965 DQS0 = 27, DQS1 = 35
6349 06:56:49.948686 DQM Delay:
6350 06:56:49.949240 DQM0 = 8, DQM1 = 12
6351 06:56:49.949602 DQ Delay:
6352 06:56:49.951744 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6353 06:56:49.954930 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6354 06:56:49.958110 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6355 06:56:49.961611 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6356 06:56:49.962235
6357 06:56:49.962595
6358 06:56:49.962924 ==
6359 06:56:49.965163 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 06:56:49.968410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 06:56:49.971822 ==
6362 06:56:49.972424
6363 06:56:49.972795
6364 06:56:49.973127 TX Vref Scan disable
6365 06:56:49.975219 == TX Byte 0 ==
6366 06:56:49.978524 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 06:56:49.981996 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 06:56:49.984711 == TX Byte 1 ==
6369 06:56:49.988786 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 06:56:49.991656 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 06:56:49.992200 ==
6372 06:56:49.994771 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 06:56:50.001460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 06:56:50.001994 ==
6375 06:56:50.002351
6376 06:56:50.002680
6377 06:56:50.002997 TX Vref Scan disable
6378 06:56:50.004592 == TX Byte 0 ==
6379 06:56:50.007909 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6380 06:56:50.011614 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6381 06:56:50.014977 == TX Byte 1 ==
6382 06:56:50.018481 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6383 06:56:50.021283 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6384 06:56:50.021742
6385 06:56:50.024712 [DATLAT]
6386 06:56:50.025166 Freq=400, CH0 RK0
6387 06:56:50.025525
6388 06:56:50.027755 DATLAT Default: 0xf
6389 06:56:50.028206 0, 0xFFFF, sum = 0
6390 06:56:50.031878 1, 0xFFFF, sum = 0
6391 06:56:50.032472 2, 0xFFFF, sum = 0
6392 06:56:50.035035 3, 0xFFFF, sum = 0
6393 06:56:50.035588 4, 0xFFFF, sum = 0
6394 06:56:50.038412 5, 0xFFFF, sum = 0
6395 06:56:50.038970 6, 0xFFFF, sum = 0
6396 06:56:50.041138 7, 0xFFFF, sum = 0
6397 06:56:50.041701 8, 0xFFFF, sum = 0
6398 06:56:50.044759 9, 0xFFFF, sum = 0
6399 06:56:50.045307 10, 0xFFFF, sum = 0
6400 06:56:50.048074 11, 0xFFFF, sum = 0
6401 06:56:50.051501 12, 0xFFFF, sum = 0
6402 06:56:50.051969 13, 0x0, sum = 1
6403 06:56:50.052387 14, 0x0, sum = 2
6404 06:56:50.054763 15, 0x0, sum = 3
6405 06:56:50.055222 16, 0x0, sum = 4
6406 06:56:50.058154 best_step = 14
6407 06:56:50.058611
6408 06:56:50.058969 ==
6409 06:56:50.061188 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 06:56:50.064542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 06:56:50.065004 ==
6412 06:56:50.067916 RX Vref Scan: 1
6413 06:56:50.068510
6414 06:56:50.068949 RX Vref 0 -> 0, step: 1
6415 06:56:50.069473
6416 06:56:50.071751 RX Delay -311 -> 252, step: 8
6417 06:56:50.072358
6418 06:56:50.075157 Set Vref, RX VrefLevel [Byte0]: 54
6419 06:56:50.077756 [Byte1]: 46
6420 06:56:50.082790
6421 06:56:50.083337 Final RX Vref Byte 0 = 54 to rank0
6422 06:56:50.085840 Final RX Vref Byte 1 = 46 to rank0
6423 06:56:50.089123 Final RX Vref Byte 0 = 54 to rank1
6424 06:56:50.092644 Final RX Vref Byte 1 = 46 to rank1==
6425 06:56:50.095990 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 06:56:50.102467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 06:56:50.103009 ==
6428 06:56:50.103373 DQS Delay:
6429 06:56:50.105908 DQS0 = 28, DQS1 = 36
6430 06:56:50.106367 DQM Delay:
6431 06:56:50.106729 DQM0 = 11, DQM1 = 13
6432 06:56:50.108891 DQ Delay:
6433 06:56:50.112273 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6434 06:56:50.112780 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6435 06:56:50.115780 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6436 06:56:50.118935 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6437 06:56:50.119397
6438 06:56:50.119756
6439 06:56:50.129158 [DQSOSCAuto] RK0, (LSB)MR18= 0xc7b2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6440 06:56:50.133005 CH0 RK0: MR19=C0C, MR18=C7B2
6441 06:56:50.139215 CH0_RK0: MR19=0xC0C, MR18=0xC7B2, DQSOSC=385, MR23=63, INC=398, DEC=265
6442 06:56:50.139773 ==
6443 06:56:50.142103 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 06:56:50.145912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 06:56:50.146669 ==
6446 06:56:50.148990 [Gating] SW mode calibration
6447 06:56:50.155670 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6448 06:56:50.159280 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6449 06:56:50.166072 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6450 06:56:50.169087 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6451 06:56:50.172408 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 06:56:50.179414 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 06:56:50.182919 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 06:56:50.185911 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 06:56:50.192911 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 06:56:50.195725 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 06:56:50.199284 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 06:56:50.201972 Total UI for P1: 0, mck2ui 16
6459 06:56:50.205826 best dqsien dly found for B0: ( 0, 14, 24)
6460 06:56:50.208977 Total UI for P1: 0, mck2ui 16
6461 06:56:50.212139 best dqsien dly found for B1: ( 0, 14, 24)
6462 06:56:50.215706 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6463 06:56:50.219084 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6464 06:56:50.219633
6465 06:56:50.225234 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6466 06:56:50.229009 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6467 06:56:50.232209 [Gating] SW calibration Done
6468 06:56:50.232709 ==
6469 06:56:50.235372 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 06:56:50.239177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 06:56:50.239804 ==
6472 06:56:50.240184 RX Vref Scan: 0
6473 06:56:50.240632
6474 06:56:50.242405 RX Vref 0 -> 0, step: 1
6475 06:56:50.242880
6476 06:56:50.245944 RX Delay -410 -> 252, step: 16
6477 06:56:50.248808 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6478 06:56:50.255437 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6479 06:56:50.258550 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6480 06:56:50.262424 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6481 06:56:50.265237 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6482 06:56:50.271775 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6483 06:56:50.275976 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6484 06:56:50.278681 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6485 06:56:50.282520 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6486 06:56:50.285325 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6487 06:56:50.292001 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6488 06:56:50.295929 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6489 06:56:50.299182 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6490 06:56:50.305091 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6491 06:56:50.308201 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6492 06:56:50.311946 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6493 06:56:50.312443 ==
6494 06:56:50.315325 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 06:56:50.318641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 06:56:50.321778 ==
6497 06:56:50.322331 DQS Delay:
6498 06:56:50.322759 DQS0 = 19, DQS1 = 35
6499 06:56:50.324884 DQM Delay:
6500 06:56:50.325340 DQM0 = 5, DQM1 = 12
6501 06:56:50.328430 DQ Delay:
6502 06:56:50.328886 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6503 06:56:50.331693 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6504 06:56:50.335100 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6505 06:56:50.339030 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6506 06:56:50.339584
6507 06:56:50.339940
6508 06:56:50.340267 ==
6509 06:56:50.342052 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 06:56:50.348390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 06:56:50.348982 ==
6512 06:56:50.349363
6513 06:56:50.349786
6514 06:56:50.350124 TX Vref Scan disable
6515 06:56:50.351598 == TX Byte 0 ==
6516 06:56:50.355290 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6517 06:56:50.358491 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6518 06:56:50.361793 == TX Byte 1 ==
6519 06:56:50.365070 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6520 06:56:50.368888 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6521 06:56:50.369343 ==
6522 06:56:50.371867 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 06:56:50.378424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 06:56:50.378983 ==
6525 06:56:50.379342
6526 06:56:50.379671
6527 06:56:50.379984 TX Vref Scan disable
6528 06:56:50.381973 == TX Byte 0 ==
6529 06:56:50.385270 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6530 06:56:50.388213 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6531 06:56:50.391616 == TX Byte 1 ==
6532 06:56:50.394768 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6533 06:56:50.398588 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6534 06:56:50.399095
6535 06:56:50.402299 [DATLAT]
6536 06:56:50.402838 Freq=400, CH0 RK1
6537 06:56:50.403172
6538 06:56:50.405183 DATLAT Default: 0xe
6539 06:56:50.405588 0, 0xFFFF, sum = 0
6540 06:56:50.408129 1, 0xFFFF, sum = 0
6541 06:56:50.408619 2, 0xFFFF, sum = 0
6542 06:56:50.411356 3, 0xFFFF, sum = 0
6543 06:56:50.411791 4, 0xFFFF, sum = 0
6544 06:56:50.415160 5, 0xFFFF, sum = 0
6545 06:56:50.415702 6, 0xFFFF, sum = 0
6546 06:56:50.418414 7, 0xFFFF, sum = 0
6547 06:56:50.418939 8, 0xFFFF, sum = 0
6548 06:56:50.422037 9, 0xFFFF, sum = 0
6549 06:56:50.422565 10, 0xFFFF, sum = 0
6550 06:56:50.425016 11, 0xFFFF, sum = 0
6551 06:56:50.428317 12, 0xFFFF, sum = 0
6552 06:56:50.428733 13, 0x0, sum = 1
6553 06:56:50.429062 14, 0x0, sum = 2
6554 06:56:50.431865 15, 0x0, sum = 3
6555 06:56:50.432470 16, 0x0, sum = 4
6556 06:56:50.434962 best_step = 14
6557 06:56:50.435509
6558 06:56:50.435858 ==
6559 06:56:50.438305 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 06:56:50.441885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 06:56:50.442315 ==
6562 06:56:50.444710 RX Vref Scan: 0
6563 06:56:50.445119
6564 06:56:50.445443 RX Vref 0 -> 0, step: 1
6565 06:56:50.445751
6566 06:56:50.448314 RX Delay -311 -> 252, step: 8
6567 06:56:50.456224 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6568 06:56:50.459886 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6569 06:56:50.463081 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6570 06:56:50.469093 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6571 06:56:50.472720 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6572 06:56:50.476199 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6573 06:56:50.479200 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6574 06:56:50.483009 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6575 06:56:50.489291 iDelay=217, Bit 8, Center -36 (-255 ~ 184) 440
6576 06:56:50.492869 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6577 06:56:50.496577 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6578 06:56:50.499951 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6579 06:56:50.506103 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6580 06:56:50.508996 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6581 06:56:50.512763 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6582 06:56:50.519493 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6583 06:56:50.520005 ==
6584 06:56:50.522755 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 06:56:50.526015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 06:56:50.526440 ==
6587 06:56:50.526765 DQS Delay:
6588 06:56:50.529150 DQS0 = 24, DQS1 = 36
6589 06:56:50.529646 DQM Delay:
6590 06:56:50.532859 DQM0 = 9, DQM1 = 13
6591 06:56:50.533369 DQ Delay:
6592 06:56:50.535670 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6593 06:56:50.539272 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6594 06:56:50.542487 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6595 06:56:50.546192 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6596 06:56:50.546606
6597 06:56:50.546927
6598 06:56:50.552655 [DQSOSCAuto] RK1, (LSB)MR18= 0xb656, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6599 06:56:50.555465 CH0 RK1: MR19=C0C, MR18=B656
6600 06:56:50.562636 CH0_RK1: MR19=0xC0C, MR18=0xB656, DQSOSC=387, MR23=63, INC=394, DEC=262
6601 06:56:50.565769 [RxdqsGatingPostProcess] freq 400
6602 06:56:50.572410 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6603 06:56:50.572932 best DQS0 dly(2T, 0.5T) = (0, 10)
6604 06:56:50.576594 best DQS1 dly(2T, 0.5T) = (0, 10)
6605 06:56:50.579117 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6606 06:56:50.582490 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6607 06:56:50.585842 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 06:56:50.588822 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 06:56:50.591791 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 06:56:50.595857 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 06:56:50.599241 Pre-setting of DQS Precalculation
6612 06:56:50.602571 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6613 06:56:50.605528 ==
6614 06:56:50.608931 Dram Type= 6, Freq= 0, CH_1, rank 0
6615 06:56:50.612170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 06:56:50.612780 ==
6617 06:56:50.618759 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6618 06:56:50.621815 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6619 06:56:50.625152 [CA 0] Center 36 (8~64) winsize 57
6620 06:56:50.629260 [CA 1] Center 36 (8~64) winsize 57
6621 06:56:50.632516 [CA 2] Center 36 (8~64) winsize 57
6622 06:56:50.635531 [CA 3] Center 36 (8~64) winsize 57
6623 06:56:50.638822 [CA 4] Center 36 (8~64) winsize 57
6624 06:56:50.641734 [CA 5] Center 36 (8~64) winsize 57
6625 06:56:50.642188
6626 06:56:50.645225 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6627 06:56:50.645712
6628 06:56:50.648509 [CATrainingPosCal] consider 1 rank data
6629 06:56:50.651653 u2DelayCellTimex100 = 270/100 ps
6630 06:56:50.655363 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 06:56:50.658617 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 06:56:50.662235 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 06:56:50.668221 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 06:56:50.671637 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 06:56:50.674861 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 06:56:50.675272
6637 06:56:50.678535 CA PerBit enable=1, Macro0, CA PI delay=36
6638 06:56:50.679044
6639 06:56:50.681895 [CBTSetCACLKResult] CA Dly = 36
6640 06:56:50.682303 CS Dly: 1 (0~32)
6641 06:56:50.682629 ==
6642 06:56:50.684864 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 06:56:50.691623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 06:56:50.692139 ==
6645 06:56:50.695157 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 06:56:50.701940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6647 06:56:50.704820 [CA 0] Center 36 (8~64) winsize 57
6648 06:56:50.708146 [CA 1] Center 36 (8~64) winsize 57
6649 06:56:50.712275 [CA 2] Center 36 (8~64) winsize 57
6650 06:56:50.715349 [CA 3] Center 36 (8~64) winsize 57
6651 06:56:50.718488 [CA 4] Center 36 (8~64) winsize 57
6652 06:56:50.721717 [CA 5] Center 36 (8~64) winsize 57
6653 06:56:50.722267
6654 06:56:50.724688 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6655 06:56:50.725140
6656 06:56:50.728773 [CATrainingPosCal] consider 2 rank data
6657 06:56:50.731772 u2DelayCellTimex100 = 270/100 ps
6658 06:56:50.735207 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 06:56:50.738466 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 06:56:50.741574 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 06:56:50.744506 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 06:56:50.747931 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 06:56:50.751219 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 06:56:50.751671
6665 06:56:50.757777 CA PerBit enable=1, Macro0, CA PI delay=36
6666 06:56:50.758232
6667 06:56:50.761407 [CBTSetCACLKResult] CA Dly = 36
6668 06:56:50.761817 CS Dly: 1 (0~32)
6669 06:56:50.762142
6670 06:56:50.764667 ----->DramcWriteLeveling(PI) begin...
6671 06:56:50.765082 ==
6672 06:56:50.768419 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 06:56:50.771694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 06:56:50.772144 ==
6675 06:56:50.774572 Write leveling (Byte 0): 40 => 8
6676 06:56:50.778255 Write leveling (Byte 1): 40 => 8
6677 06:56:50.781239 DramcWriteLeveling(PI) end<-----
6678 06:56:50.781654
6679 06:56:50.781980 ==
6680 06:56:50.784741 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 06:56:50.788461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 06:56:50.791519 ==
6683 06:56:50.791925 [Gating] SW mode calibration
6684 06:56:50.797815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6685 06:56:50.804483 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6686 06:56:50.807923 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6687 06:56:50.814613 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6688 06:56:50.818017 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 06:56:50.821178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 06:56:50.828043 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 06:56:50.831206 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 06:56:50.834452 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 06:56:50.841698 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 06:56:50.844259 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 06:56:50.848130 Total UI for P1: 0, mck2ui 16
6696 06:56:50.851332 best dqsien dly found for B0: ( 0, 14, 24)
6697 06:56:50.854311 Total UI for P1: 0, mck2ui 16
6698 06:56:50.857913 best dqsien dly found for B1: ( 0, 14, 24)
6699 06:56:50.861152 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6700 06:56:50.864448 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6701 06:56:50.864960
6702 06:56:50.867646 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6703 06:56:50.871095 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6704 06:56:50.874097 [Gating] SW calibration Done
6705 06:56:50.874507 ==
6706 06:56:50.877988 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 06:56:50.880789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 06:56:50.884572 ==
6709 06:56:50.885088 RX Vref Scan: 0
6710 06:56:50.885423
6711 06:56:50.887429 RX Vref 0 -> 0, step: 1
6712 06:56:50.887843
6713 06:56:50.891551 RX Delay -410 -> 252, step: 16
6714 06:56:50.894741 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6715 06:56:50.897695 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6716 06:56:50.900874 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6717 06:56:50.907614 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6718 06:56:50.911082 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6719 06:56:50.914577 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6720 06:56:50.917688 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6721 06:56:50.924191 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6722 06:56:50.927565 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6723 06:56:50.931170 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6724 06:56:50.934151 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6725 06:56:50.940906 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6726 06:56:50.944034 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6727 06:56:50.947938 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6728 06:56:50.951029 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6729 06:56:50.957349 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6730 06:56:50.957804 ==
6731 06:56:50.960790 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 06:56:50.964446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 06:56:50.964999 ==
6734 06:56:50.965359 DQS Delay:
6735 06:56:50.967348 DQS0 = 35, DQS1 = 35
6736 06:56:50.967798 DQM Delay:
6737 06:56:50.970388 DQM0 = 18, DQM1 = 13
6738 06:56:50.970846 DQ Delay:
6739 06:56:50.974776 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6740 06:56:50.977152 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6741 06:56:50.980992 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6742 06:56:50.984393 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6743 06:56:50.984951
6744 06:56:50.985315
6745 06:56:50.985651 ==
6746 06:56:50.987145 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 06:56:50.990668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 06:56:50.991134 ==
6749 06:56:50.994168
6750 06:56:50.994726
6751 06:56:50.995091 TX Vref Scan disable
6752 06:56:50.997535 == TX Byte 0 ==
6753 06:56:51.000828 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 06:56:51.004040 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 06:56:51.007766 == TX Byte 1 ==
6756 06:56:51.010691 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 06:56:51.014656 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 06:56:51.015224 ==
6759 06:56:51.017885 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 06:56:51.021017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 06:56:51.021586 ==
6762 06:56:51.023898
6763 06:56:51.024415
6764 06:56:51.024782 TX Vref Scan disable
6765 06:56:51.026936 == TX Byte 0 ==
6766 06:56:51.030545 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 06:56:51.034214 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 06:56:51.037423 == TX Byte 1 ==
6769 06:56:51.040539 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 06:56:51.043849 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 06:56:51.044352
6772 06:56:51.044724 [DATLAT]
6773 06:56:51.047047 Freq=400, CH1 RK0
6774 06:56:51.047593
6775 06:56:51.050512 DATLAT Default: 0xf
6776 06:56:51.050966 0, 0xFFFF, sum = 0
6777 06:56:51.053973 1, 0xFFFF, sum = 0
6778 06:56:51.054432 2, 0xFFFF, sum = 0
6779 06:56:51.057093 3, 0xFFFF, sum = 0
6780 06:56:51.057556 4, 0xFFFF, sum = 0
6781 06:56:51.060554 5, 0xFFFF, sum = 0
6782 06:56:51.061017 6, 0xFFFF, sum = 0
6783 06:56:51.064471 7, 0xFFFF, sum = 0
6784 06:56:51.065026 8, 0xFFFF, sum = 0
6785 06:56:51.067348 9, 0xFFFF, sum = 0
6786 06:56:51.067808 10, 0xFFFF, sum = 0
6787 06:56:51.070372 11, 0xFFFF, sum = 0
6788 06:56:51.070958 12, 0xFFFF, sum = 0
6789 06:56:51.073573 13, 0x0, sum = 1
6790 06:56:51.074044 14, 0x0, sum = 2
6791 06:56:51.076813 15, 0x0, sum = 3
6792 06:56:51.077277 16, 0x0, sum = 4
6793 06:56:51.081082 best_step = 14
6794 06:56:51.081628
6795 06:56:51.081989 ==
6796 06:56:51.083730 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 06:56:51.087201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 06:56:51.087808 ==
6799 06:56:51.090332 RX Vref Scan: 1
6800 06:56:51.090790
6801 06:56:51.091152 RX Vref 0 -> 0, step: 1
6802 06:56:51.091484
6803 06:56:51.093416 RX Delay -311 -> 252, step: 8
6804 06:56:51.093876
6805 06:56:51.097218 Set Vref, RX VrefLevel [Byte0]: 55
6806 06:56:51.100556 [Byte1]: 49
6807 06:56:51.104532
6808 06:56:51.105081 Final RX Vref Byte 0 = 55 to rank0
6809 06:56:51.108344 Final RX Vref Byte 1 = 49 to rank0
6810 06:56:51.111414 Final RX Vref Byte 0 = 55 to rank1
6811 06:56:51.114736 Final RX Vref Byte 1 = 49 to rank1==
6812 06:56:51.117982 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 06:56:51.124676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 06:56:51.125230 ==
6815 06:56:51.125593 DQS Delay:
6816 06:56:51.128003 DQS0 = 28, DQS1 = 32
6817 06:56:51.128491 DQM Delay:
6818 06:56:51.128856 DQM0 = 9, DQM1 = 10
6819 06:56:51.131011 DQ Delay:
6820 06:56:51.134947 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6821 06:56:51.135527 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6822 06:56:51.138151 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6823 06:56:51.141103 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6824 06:56:51.141561
6825 06:56:51.141922
6826 06:56:51.151026 [DQSOSCAuto] RK0, (LSB)MR18= 0x8bc5, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6827 06:56:51.154288 CH1 RK0: MR19=C0C, MR18=8BC5
6828 06:56:51.161065 CH1_RK0: MR19=0xC0C, MR18=0x8BC5, DQSOSC=385, MR23=63, INC=398, DEC=265
6829 06:56:51.161619 ==
6830 06:56:51.164793 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 06:56:51.167673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 06:56:51.168132 ==
6833 06:56:51.171136 [Gating] SW mode calibration
6834 06:56:51.178003 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6835 06:56:51.180890 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6836 06:56:51.187992 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6837 06:56:51.191054 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6838 06:56:51.194395 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 06:56:51.200860 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 06:56:51.204254 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 06:56:51.207868 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 06:56:51.214292 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 06:56:51.217831 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 06:56:51.220994 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 06:56:51.224250 Total UI for P1: 0, mck2ui 16
6846 06:56:51.227113 best dqsien dly found for B0: ( 0, 14, 24)
6847 06:56:51.231237 Total UI for P1: 0, mck2ui 16
6848 06:56:51.234302 best dqsien dly found for B1: ( 0, 14, 24)
6849 06:56:51.237811 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6850 06:56:51.240847 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6851 06:56:51.244104
6852 06:56:51.247604 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6853 06:56:51.250459 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6854 06:56:51.253918 [Gating] SW calibration Done
6855 06:56:51.254389 ==
6856 06:56:51.257119 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 06:56:51.260870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 06:56:51.261330 ==
6859 06:56:51.261691 RX Vref Scan: 0
6860 06:56:51.262033
6861 06:56:51.264366 RX Vref 0 -> 0, step: 1
6862 06:56:51.264932
6863 06:56:51.267368 RX Delay -410 -> 252, step: 16
6864 06:56:51.270908 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6865 06:56:51.277011 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6866 06:56:51.280783 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6867 06:56:51.284677 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6868 06:56:51.287373 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6869 06:56:51.290683 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6870 06:56:51.297506 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6871 06:56:51.300464 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6872 06:56:51.304353 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6873 06:56:51.307416 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6874 06:56:51.313948 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6875 06:56:51.317285 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6876 06:56:51.320799 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6877 06:56:51.324027 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6878 06:56:51.330324 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6879 06:56:51.334126 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6880 06:56:51.334583 ==
6881 06:56:51.337497 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 06:56:51.340944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 06:56:51.341495 ==
6884 06:56:51.344075 DQS Delay:
6885 06:56:51.344675 DQS0 = 27, DQS1 = 35
6886 06:56:51.347425 DQM Delay:
6887 06:56:51.347974 DQM0 = 11, DQM1 = 15
6888 06:56:51.348390 DQ Delay:
6889 06:56:51.350844 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6890 06:56:51.353690 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6891 06:56:51.357044 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6892 06:56:51.360516 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6893 06:56:51.361143
6894 06:56:51.361662
6895 06:56:51.362162 ==
6896 06:56:51.364053 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 06:56:51.370910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 06:56:51.371442 ==
6899 06:56:51.371780
6900 06:56:51.372091
6901 06:56:51.372438 TX Vref Scan disable
6902 06:56:51.373953 == TX Byte 0 ==
6903 06:56:51.377301 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6904 06:56:51.380905 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6905 06:56:51.383953 == TX Byte 1 ==
6906 06:56:51.387270 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6907 06:56:51.390285 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6908 06:56:51.390848 ==
6909 06:56:51.394104 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 06:56:51.400338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 06:56:51.400910 ==
6912 06:56:51.401282
6913 06:56:51.401618
6914 06:56:51.401940 TX Vref Scan disable
6915 06:56:51.403350 == TX Byte 0 ==
6916 06:56:51.406937 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6917 06:56:51.410080 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6918 06:56:51.413342 == TX Byte 1 ==
6919 06:56:51.416997 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6920 06:56:51.420640 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6921 06:56:51.421203
6922 06:56:51.423554 [DATLAT]
6923 06:56:51.424113 Freq=400, CH1 RK1
6924 06:56:51.424635
6925 06:56:51.426950 DATLAT Default: 0xe
6926 06:56:51.427484 0, 0xFFFF, sum = 0
6927 06:56:51.429722 1, 0xFFFF, sum = 0
6928 06:56:51.430189 2, 0xFFFF, sum = 0
6929 06:56:51.433526 3, 0xFFFF, sum = 0
6930 06:56:51.433994 4, 0xFFFF, sum = 0
6931 06:56:51.437013 5, 0xFFFF, sum = 0
6932 06:56:51.437581 6, 0xFFFF, sum = 0
6933 06:56:51.439864 7, 0xFFFF, sum = 0
6934 06:56:51.440394 8, 0xFFFF, sum = 0
6935 06:56:51.443313 9, 0xFFFF, sum = 0
6936 06:56:51.446469 10, 0xFFFF, sum = 0
6937 06:56:51.446978 11, 0xFFFF, sum = 0
6938 06:56:51.450058 12, 0xFFFF, sum = 0
6939 06:56:51.450524 13, 0x0, sum = 1
6940 06:56:51.453271 14, 0x0, sum = 2
6941 06:56:51.453739 15, 0x0, sum = 3
6942 06:56:51.454110 16, 0x0, sum = 4
6943 06:56:51.456278 best_step = 14
6944 06:56:51.456726
6945 06:56:51.457137 ==
6946 06:56:51.460071 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 06:56:51.463301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 06:56:51.463868 ==
6949 06:56:51.466666 RX Vref Scan: 0
6950 06:56:51.467127
6951 06:56:51.467492 RX Vref 0 -> 0, step: 1
6952 06:56:51.470494
6953 06:56:51.471051 RX Delay -311 -> 252, step: 8
6954 06:56:51.478132 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6955 06:56:51.481747 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6956 06:56:51.484999 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6957 06:56:51.488602 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6958 06:56:51.495148 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6959 06:56:51.498373 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6960 06:56:51.501577 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6961 06:56:51.505244 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6962 06:56:51.511424 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6963 06:56:51.515062 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6964 06:56:51.518528 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6965 06:56:51.521715 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6966 06:56:51.528261 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6967 06:56:51.531777 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6968 06:56:51.535468 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6969 06:56:51.538269 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6970 06:56:51.541582 ==
6971 06:56:51.544549 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 06:56:51.548722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 06:56:51.549276 ==
6974 06:56:51.549637 DQS Delay:
6975 06:56:51.551734 DQS0 = 28, DQS1 = 32
6976 06:56:51.552283 DQM Delay:
6977 06:56:51.554600 DQM0 = 10, DQM1 = 11
6978 06:56:51.555056 DQ Delay:
6979 06:56:51.558439 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6980 06:56:51.561256 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6981 06:56:51.564279 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6982 06:56:51.567808 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6983 06:56:51.568264
6984 06:56:51.568672
6985 06:56:51.574732 [DQSOSCAuto] RK1, (LSB)MR18= 0xc052, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
6986 06:56:51.577981 CH1 RK1: MR19=C0C, MR18=C052
6987 06:56:51.584402 CH1_RK1: MR19=0xC0C, MR18=0xC052, DQSOSC=386, MR23=63, INC=396, DEC=264
6988 06:56:51.588095 [RxdqsGatingPostProcess] freq 400
6989 06:56:51.594579 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6990 06:56:51.595136 best DQS0 dly(2T, 0.5T) = (0, 10)
6991 06:56:51.597519 best DQS1 dly(2T, 0.5T) = (0, 10)
6992 06:56:51.601500 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6993 06:56:51.604843 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6994 06:56:51.607731 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 06:56:51.611282 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 06:56:51.614320 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 06:56:51.617591 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 06:56:51.620712 Pre-setting of DQS Precalculation
6999 06:56:51.627442 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7000 06:56:51.633977 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7001 06:56:51.640811 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7002 06:56:51.641359
7003 06:56:51.641759
7004 06:56:51.643615 [Calibration Summary] 800 Mbps
7005 06:56:51.644072 CH 0, Rank 0
7006 06:56:51.647070 SW Impedance : PASS
7007 06:56:51.650363 DUTY Scan : NO K
7008 06:56:51.650825 ZQ Calibration : PASS
7009 06:56:51.653567 Jitter Meter : NO K
7010 06:56:51.656852 CBT Training : PASS
7011 06:56:51.657310 Write leveling : PASS
7012 06:56:51.660077 RX DQS gating : PASS
7013 06:56:51.660661 RX DQ/DQS(RDDQC) : PASS
7014 06:56:51.664263 TX DQ/DQS : PASS
7015 06:56:51.667306 RX DATLAT : PASS
7016 06:56:51.667860 RX DQ/DQS(Engine): PASS
7017 06:56:51.670431 TX OE : NO K
7018 06:56:51.670888 All Pass.
7019 06:56:51.671248
7020 06:56:51.673691 CH 0, Rank 1
7021 06:56:51.674245 SW Impedance : PASS
7022 06:56:51.676939 DUTY Scan : NO K
7023 06:56:51.680182 ZQ Calibration : PASS
7024 06:56:51.680780 Jitter Meter : NO K
7025 06:56:51.683823 CBT Training : PASS
7026 06:56:51.687270 Write leveling : NO K
7027 06:56:51.687822 RX DQS gating : PASS
7028 06:56:51.690236 RX DQ/DQS(RDDQC) : PASS
7029 06:56:51.693162 TX DQ/DQS : PASS
7030 06:56:51.693621 RX DATLAT : PASS
7031 06:56:51.696859 RX DQ/DQS(Engine): PASS
7032 06:56:51.699945 TX OE : NO K
7033 06:56:51.700508 All Pass.
7034 06:56:51.700883
7035 06:56:51.701223 CH 1, Rank 0
7036 06:56:51.703609 SW Impedance : PASS
7037 06:56:51.706964 DUTY Scan : NO K
7038 06:56:51.707525 ZQ Calibration : PASS
7039 06:56:51.710260 Jitter Meter : NO K
7040 06:56:51.710716 CBT Training : PASS
7041 06:56:51.713599 Write leveling : PASS
7042 06:56:51.716779 RX DQS gating : PASS
7043 06:56:51.717233 RX DQ/DQS(RDDQC) : PASS
7044 06:56:51.720198 TX DQ/DQS : PASS
7045 06:56:51.723244 RX DATLAT : PASS
7046 06:56:51.723790 RX DQ/DQS(Engine): PASS
7047 06:56:51.727051 TX OE : NO K
7048 06:56:51.727511 All Pass.
7049 06:56:51.727873
7050 06:56:51.729662 CH 1, Rank 1
7051 06:56:51.730117 SW Impedance : PASS
7052 06:56:51.733146 DUTY Scan : NO K
7053 06:56:51.736868 ZQ Calibration : PASS
7054 06:56:51.737420 Jitter Meter : NO K
7055 06:56:51.739744 CBT Training : PASS
7056 06:56:51.743342 Write leveling : NO K
7057 06:56:51.743892 RX DQS gating : PASS
7058 06:56:51.746473 RX DQ/DQS(RDDQC) : PASS
7059 06:56:51.750155 TX DQ/DQS : PASS
7060 06:56:51.750770 RX DATLAT : PASS
7061 06:56:51.752889 RX DQ/DQS(Engine): PASS
7062 06:56:51.756405 TX OE : NO K
7063 06:56:51.757131 All Pass.
7064 06:56:51.757570
7065 06:56:51.757918 DramC Write-DBI off
7066 06:56:51.759566 PER_BANK_REFRESH: Hybrid Mode
7067 06:56:51.762769 TX_TRACKING: ON
7068 06:56:51.769914 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7069 06:56:51.772910 [FAST_K] Save calibration result to emmc
7070 06:56:51.779912 dramc_set_vcore_voltage set vcore to 725000
7071 06:56:51.780496 Read voltage for 1600, 0
7072 06:56:51.783026 Vio18 = 0
7073 06:56:51.783482 Vcore = 725000
7074 06:56:51.783844 Vdram = 0
7075 06:56:51.786156 Vddq = 0
7076 06:56:51.786633 Vmddr = 0
7077 06:56:51.789440 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7078 06:56:51.796346 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7079 06:56:51.799517 MEM_TYPE=3, freq_sel=13
7080 06:56:51.802842 sv_algorithm_assistance_LP4_3733
7081 06:56:51.806286 ============ PULL DRAM RESETB DOWN ============
7082 06:56:51.809637 ========== PULL DRAM RESETB DOWN end =========
7083 06:56:51.812723 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7084 06:56:51.816055 ===================================
7085 06:56:51.819342 LPDDR4 DRAM CONFIGURATION
7086 06:56:51.823126 ===================================
7087 06:56:51.826148 EX_ROW_EN[0] = 0x0
7088 06:56:51.826570 EX_ROW_EN[1] = 0x0
7089 06:56:51.829374 LP4Y_EN = 0x0
7090 06:56:51.829888 WORK_FSP = 0x1
7091 06:56:51.832813 WL = 0x5
7092 06:56:51.833228 RL = 0x5
7093 06:56:51.836384 BL = 0x2
7094 06:56:51.836905 RPST = 0x0
7095 06:56:51.839509 RD_PRE = 0x0
7096 06:56:51.840030 WR_PRE = 0x1
7097 06:56:51.843413 WR_PST = 0x1
7098 06:56:51.846286 DBI_WR = 0x0
7099 06:56:51.846706 DBI_RD = 0x0
7100 06:56:51.849505 OTF = 0x1
7101 06:56:51.852505 ===================================
7102 06:56:51.856216 ===================================
7103 06:56:51.856776 ANA top config
7104 06:56:51.859492 ===================================
7105 06:56:51.863089 DLL_ASYNC_EN = 0
7106 06:56:51.863635 ALL_SLAVE_EN = 0
7107 06:56:51.865868 NEW_RANK_MODE = 1
7108 06:56:51.869224 DLL_IDLE_MODE = 1
7109 06:56:51.872526 LP45_APHY_COMB_EN = 1
7110 06:56:51.876235 TX_ODT_DIS = 0
7111 06:56:51.876848 NEW_8X_MODE = 1
7112 06:56:51.879430 ===================================
7113 06:56:51.883307 ===================================
7114 06:56:51.886384 data_rate = 3200
7115 06:56:51.889613 CKR = 1
7116 06:56:51.892948 DQ_P2S_RATIO = 8
7117 06:56:51.896465 ===================================
7118 06:56:51.899274 CA_P2S_RATIO = 8
7119 06:56:51.902742 DQ_CA_OPEN = 0
7120 06:56:51.903309 DQ_SEMI_OPEN = 0
7121 06:56:51.906500 CA_SEMI_OPEN = 0
7122 06:56:51.909494 CA_FULL_RATE = 0
7123 06:56:51.912461 DQ_CKDIV4_EN = 0
7124 06:56:51.916278 CA_CKDIV4_EN = 0
7125 06:56:51.919714 CA_PREDIV_EN = 0
7126 06:56:51.920263 PH8_DLY = 12
7127 06:56:51.922634 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7128 06:56:51.926148 DQ_AAMCK_DIV = 4
7129 06:56:51.929156 CA_AAMCK_DIV = 4
7130 06:56:51.932692 CA_ADMCK_DIV = 4
7131 06:56:51.933151 DQ_TRACK_CA_EN = 0
7132 06:56:51.935744 CA_PICK = 1600
7133 06:56:51.939359 CA_MCKIO = 1600
7134 06:56:51.942696 MCKIO_SEMI = 0
7135 06:56:51.945721 PLL_FREQ = 3068
7136 06:56:51.949114 DQ_UI_PI_RATIO = 32
7137 06:56:51.952837 CA_UI_PI_RATIO = 0
7138 06:56:51.955893 ===================================
7139 06:56:51.959291 ===================================
7140 06:56:51.959871 memory_type:LPDDR4
7141 06:56:51.962351 GP_NUM : 10
7142 06:56:51.966309 SRAM_EN : 1
7143 06:56:51.966872 MD32_EN : 0
7144 06:56:51.968984 ===================================
7145 06:56:51.972491 [ANA_INIT] >>>>>>>>>>>>>>
7146 06:56:51.975639 <<<<<< [CONFIGURE PHASE]: ANA_TX
7147 06:56:51.979132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7148 06:56:51.982596 ===================================
7149 06:56:51.985580 data_rate = 3200,PCW = 0X7600
7150 06:56:51.988915 ===================================
7151 06:56:51.992565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7152 06:56:51.995736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7153 06:56:52.002582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7154 06:56:52.005494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7155 06:56:52.008780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7156 06:56:52.015839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7157 06:56:52.016480 [ANA_INIT] flow start
7158 06:56:52.018744 [ANA_INIT] PLL >>>>>>>>
7159 06:56:52.019150 [ANA_INIT] PLL <<<<<<<<
7160 06:56:52.022143 [ANA_INIT] MIDPI >>>>>>>>
7161 06:56:52.025364 [ANA_INIT] MIDPI <<<<<<<<
7162 06:56:52.029181 [ANA_INIT] DLL >>>>>>>>
7163 06:56:52.029634 [ANA_INIT] DLL <<<<<<<<
7164 06:56:52.032453 [ANA_INIT] flow end
7165 06:56:52.035832 ============ LP4 DIFF to SE enter ============
7166 06:56:52.038892 ============ LP4 DIFF to SE exit ============
7167 06:56:52.041729 [ANA_INIT] <<<<<<<<<<<<<
7168 06:56:52.045231 [Flow] Enable top DCM control >>>>>
7169 06:56:52.048965 [Flow] Enable top DCM control <<<<<
7170 06:56:52.051970 Enable DLL master slave shuffle
7171 06:56:52.058811 ==============================================================
7172 06:56:52.059329 Gating Mode config
7173 06:56:52.065984 ==============================================================
7174 06:56:52.066534 Config description:
7175 06:56:52.075373 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7176 06:56:52.082665 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7177 06:56:52.089322 SELPH_MODE 0: By rank 1: By Phase
7178 06:56:52.092316 ==============================================================
7179 06:56:52.095417 GAT_TRACK_EN = 1
7180 06:56:52.098949 RX_GATING_MODE = 2
7181 06:56:52.102343 RX_GATING_TRACK_MODE = 2
7182 06:56:52.105709 SELPH_MODE = 1
7183 06:56:52.109129 PICG_EARLY_EN = 1
7184 06:56:52.112515 VALID_LAT_VALUE = 1
7185 06:56:52.115506 ==============================================================
7186 06:56:52.118501 Enter into Gating configuration >>>>
7187 06:56:52.122664 Exit from Gating configuration <<<<
7188 06:56:52.125301 Enter into DVFS_PRE_config >>>>>
7189 06:56:52.139168 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7190 06:56:52.142114 Exit from DVFS_PRE_config <<<<<
7191 06:56:52.144919 Enter into PICG configuration >>>>
7192 06:56:52.148868 Exit from PICG configuration <<<<
7193 06:56:52.149425 [RX_INPUT] configuration >>>>>
7194 06:56:52.152095 [RX_INPUT] configuration <<<<<
7195 06:56:52.158398 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7196 06:56:52.161283 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7197 06:56:52.168530 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7198 06:56:52.175098 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7199 06:56:52.181739 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7200 06:56:52.188467 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7201 06:56:52.191706 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7202 06:56:52.194401 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7203 06:56:52.201124 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7204 06:56:52.205094 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7205 06:56:52.207840 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7206 06:56:52.214381 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7207 06:56:52.214914 ===================================
7208 06:56:52.218083 LPDDR4 DRAM CONFIGURATION
7209 06:56:52.220910 ===================================
7210 06:56:52.224450 EX_ROW_EN[0] = 0x0
7211 06:56:52.225009 EX_ROW_EN[1] = 0x0
7212 06:56:52.227411 LP4Y_EN = 0x0
7213 06:56:52.227868 WORK_FSP = 0x1
7214 06:56:52.230856 WL = 0x5
7215 06:56:52.233992 RL = 0x5
7216 06:56:52.234446 BL = 0x2
7217 06:56:52.238107 RPST = 0x0
7218 06:56:52.238661 RD_PRE = 0x0
7219 06:56:52.240518 WR_PRE = 0x1
7220 06:56:52.240977 WR_PST = 0x1
7221 06:56:52.244089 DBI_WR = 0x0
7222 06:56:52.244671 DBI_RD = 0x0
7223 06:56:52.247488 OTF = 0x1
7224 06:56:52.250605 ===================================
7225 06:56:52.254207 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7226 06:56:52.257244 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7227 06:56:52.263678 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7228 06:56:52.267794 ===================================
7229 06:56:52.268473 LPDDR4 DRAM CONFIGURATION
7230 06:56:52.270873 ===================================
7231 06:56:52.274088 EX_ROW_EN[0] = 0x10
7232 06:56:52.274643 EX_ROW_EN[1] = 0x0
7233 06:56:52.276960 LP4Y_EN = 0x0
7234 06:56:52.277415 WORK_FSP = 0x1
7235 06:56:52.281112 WL = 0x5
7236 06:56:52.281661 RL = 0x5
7237 06:56:52.283785 BL = 0x2
7238 06:56:52.287329 RPST = 0x0
7239 06:56:52.287875 RD_PRE = 0x0
7240 06:56:52.290545 WR_PRE = 0x1
7241 06:56:52.291002 WR_PST = 0x1
7242 06:56:52.293464 DBI_WR = 0x0
7243 06:56:52.293918 DBI_RD = 0x0
7244 06:56:52.297285 OTF = 0x1
7245 06:56:52.300336 ===================================
7246 06:56:52.304005 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7247 06:56:52.307314 ==
7248 06:56:52.310598 Dram Type= 6, Freq= 0, CH_0, rank 0
7249 06:56:52.313503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7250 06:56:52.314021 ==
7251 06:56:52.317188 [Duty_Offset_Calibration]
7252 06:56:52.317642 B0:2 B1:1 CA:1
7253 06:56:52.318097
7254 06:56:52.320171 [DutyScan_Calibration_Flow] k_type=0
7255 06:56:52.330510
7256 06:56:52.331051 ==CLK 0==
7257 06:56:52.333590 Final CLK duty delay cell = 0
7258 06:56:52.336972 [0] MAX Duty = 5156%(X100), DQS PI = 22
7259 06:56:52.340196 [0] MIN Duty = 4876%(X100), DQS PI = 48
7260 06:56:52.340658 [0] AVG Duty = 5016%(X100)
7261 06:56:52.343441
7262 06:56:52.346691 CH0 CLK Duty spec in!! Max-Min= 280%
7263 06:56:52.350048 [DutyScan_Calibration_Flow] ====Done====
7264 06:56:52.350466
7265 06:56:52.353232 [DutyScan_Calibration_Flow] k_type=1
7266 06:56:52.369434
7267 06:56:52.369861 ==DQS 0 ==
7268 06:56:52.372592 Final DQS duty delay cell = -4
7269 06:56:52.375891 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7270 06:56:52.379317 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7271 06:56:52.382193 [-4] AVG Duty = 4891%(X100)
7272 06:56:52.382620
7273 06:56:52.383186 ==DQS 1 ==
7274 06:56:52.386133 Final DQS duty delay cell = 0
7275 06:56:52.389325 [0] MAX Duty = 5187%(X100), DQS PI = 4
7276 06:56:52.392586 [0] MIN Duty = 5062%(X100), DQS PI = 32
7277 06:56:52.395663 [0] AVG Duty = 5124%(X100)
7278 06:56:52.396211
7279 06:56:52.399208 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7280 06:56:52.399621
7281 06:56:52.402170 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7282 06:56:52.405435 [DutyScan_Calibration_Flow] ====Done====
7283 06:56:52.405849
7284 06:56:52.409347 [DutyScan_Calibration_Flow] k_type=3
7285 06:56:52.426038
7286 06:56:52.426553 ==DQM 0 ==
7287 06:56:52.429198 Final DQM duty delay cell = 0
7288 06:56:52.432335 [0] MAX Duty = 5218%(X100), DQS PI = 32
7289 06:56:52.435823 [0] MIN Duty = 4876%(X100), DQS PI = 60
7290 06:56:52.439483 [0] AVG Duty = 5047%(X100)
7291 06:56:52.439990
7292 06:56:52.440447 ==DQM 1 ==
7293 06:56:52.442255 Final DQM duty delay cell = -4
7294 06:56:52.445856 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7295 06:56:52.449179 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7296 06:56:52.452407 [-4] AVG Duty = 4891%(X100)
7297 06:56:52.452822
7298 06:56:52.455638 CH0 DQM 0 Duty spec in!! Max-Min= 342%
7299 06:56:52.456065
7300 06:56:52.459022 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7301 06:56:52.462086 [DutyScan_Calibration_Flow] ====Done====
7302 06:56:52.462504
7303 06:56:52.465469 [DutyScan_Calibration_Flow] k_type=2
7304 06:56:52.483785
7305 06:56:52.484392 ==DQ 0 ==
7306 06:56:52.487097 Final DQ duty delay cell = 0
7307 06:56:52.490084 [0] MAX Duty = 5062%(X100), DQS PI = 26
7308 06:56:52.493704 [0] MIN Duty = 4907%(X100), DQS PI = 0
7309 06:56:52.494121 [0] AVG Duty = 4984%(X100)
7310 06:56:52.494453
7311 06:56:52.496919 ==DQ 1 ==
7312 06:56:52.500063 Final DQ duty delay cell = 0
7313 06:56:52.503250 [0] MAX Duty = 5125%(X100), DQS PI = 6
7314 06:56:52.506529 [0] MIN Duty = 4938%(X100), DQS PI = 34
7315 06:56:52.506977 [0] AVG Duty = 5031%(X100)
7316 06:56:52.507306
7317 06:56:52.510127 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7318 06:56:52.510542
7319 06:56:52.513662 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7320 06:56:52.519939 [DutyScan_Calibration_Flow] ====Done====
7321 06:56:52.520396 ==
7322 06:56:52.523073 Dram Type= 6, Freq= 0, CH_1, rank 0
7323 06:56:52.526861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7324 06:56:52.527279 ==
7325 06:56:52.529875 [Duty_Offset_Calibration]
7326 06:56:52.530299 B0:1 B1:0 CA:0
7327 06:56:52.530626
7328 06:56:52.533602 [DutyScan_Calibration_Flow] k_type=0
7329 06:56:52.542695
7330 06:56:52.543234 ==CLK 0==
7331 06:56:52.545544 Final CLK duty delay cell = -4
7332 06:56:52.549203 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7333 06:56:52.552663 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7334 06:56:52.555981 [-4] AVG Duty = 4906%(X100)
7335 06:56:52.556451
7336 06:56:52.559324 CH1 CLK Duty spec in!! Max-Min= 125%
7337 06:56:52.562862 [DutyScan_Calibration_Flow] ====Done====
7338 06:56:52.563359
7339 06:56:52.565939 [DutyScan_Calibration_Flow] k_type=1
7340 06:56:52.582909
7341 06:56:52.583386 ==DQS 0 ==
7342 06:56:52.585885 Final DQS duty delay cell = 0
7343 06:56:52.588997 [0] MAX Duty = 5094%(X100), DQS PI = 24
7344 06:56:52.592259 [0] MIN Duty = 4875%(X100), DQS PI = 0
7345 06:56:52.592854 [0] AVG Duty = 4984%(X100)
7346 06:56:52.595899
7347 06:56:52.596324 ==DQS 1 ==
7348 06:56:52.599297 Final DQS duty delay cell = 0
7349 06:56:52.602328 [0] MAX Duty = 5249%(X100), DQS PI = 16
7350 06:56:52.605689 [0] MIN Duty = 4969%(X100), DQS PI = 6
7351 06:56:52.605937 [0] AVG Duty = 5109%(X100)
7352 06:56:52.608947
7353 06:56:52.612251 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7354 06:56:52.612434
7355 06:56:52.615626 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7356 06:56:52.619303 [DutyScan_Calibration_Flow] ====Done====
7357 06:56:52.619430
7358 06:56:52.622540 [DutyScan_Calibration_Flow] k_type=3
7359 06:56:52.639241
7360 06:56:52.639353 ==DQM 0 ==
7361 06:56:52.642366 Final DQM duty delay cell = 0
7362 06:56:52.645611 [0] MAX Duty = 5218%(X100), DQS PI = 20
7363 06:56:52.648933 [0] MIN Duty = 4969%(X100), DQS PI = 48
7364 06:56:52.652784 [0] AVG Duty = 5093%(X100)
7365 06:56:52.652896
7366 06:56:52.652984 ==DQM 1 ==
7367 06:56:52.655690 Final DQM duty delay cell = 0
7368 06:56:52.658758 [0] MAX Duty = 5093%(X100), DQS PI = 16
7369 06:56:52.662064 [0] MIN Duty = 4907%(X100), DQS PI = 50
7370 06:56:52.665437 [0] AVG Duty = 5000%(X100)
7371 06:56:52.665546
7372 06:56:52.668659 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7373 06:56:52.668758
7374 06:56:52.672088 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7375 06:56:52.675304 [DutyScan_Calibration_Flow] ====Done====
7376 06:56:52.675383
7377 06:56:52.679067 [DutyScan_Calibration_Flow] k_type=2
7378 06:56:52.695299
7379 06:56:52.695379 ==DQ 0 ==
7380 06:56:52.698417 Final DQ duty delay cell = -4
7381 06:56:52.702020 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7382 06:56:52.705213 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7383 06:56:52.708428 [-4] AVG Duty = 4968%(X100)
7384 06:56:52.708508
7385 06:56:52.708571 ==DQ 1 ==
7386 06:56:52.711634 Final DQ duty delay cell = 0
7387 06:56:52.715555 [0] MAX Duty = 5156%(X100), DQS PI = 18
7388 06:56:52.718734 [0] MIN Duty = 4938%(X100), DQS PI = 8
7389 06:56:52.722090 [0] AVG Duty = 5047%(X100)
7390 06:56:52.722253
7391 06:56:52.725223 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7392 06:56:52.725389
7393 06:56:52.728478 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7394 06:56:52.731661 [DutyScan_Calibration_Flow] ====Done====
7395 06:56:52.734888 nWR fixed to 30
7396 06:56:52.738952 [ModeRegInit_LP4] CH0 RK0
7397 06:56:52.739078 [ModeRegInit_LP4] CH0 RK1
7398 06:56:52.741441 [ModeRegInit_LP4] CH1 RK0
7399 06:56:52.744754 [ModeRegInit_LP4] CH1 RK1
7400 06:56:52.744854 match AC timing 5
7401 06:56:52.751753 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7402 06:56:52.754853 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7403 06:56:52.758125 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7404 06:56:52.765022 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7405 06:56:52.768789 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7406 06:56:52.768886 [MiockJmeterHQA]
7407 06:56:52.768965
7408 06:56:52.772019 [DramcMiockJmeter] u1RxGatingPI = 0
7409 06:56:52.775220 0 : 4257, 4029
7410 06:56:52.775665 4 : 4252, 4027
7411 06:56:52.778881 8 : 4363, 4138
7412 06:56:52.779354 12 : 4253, 4026
7413 06:56:52.779694 16 : 4252, 4027
7414 06:56:52.782147 20 : 4363, 4137
7415 06:56:52.782685 24 : 4363, 4138
7416 06:56:52.785141 28 : 4253, 4026
7417 06:56:52.785563 32 : 4252, 4027
7418 06:56:52.788452 36 : 4249, 4027
7419 06:56:52.788873 40 : 4361, 4137
7420 06:56:52.792230 44 : 4250, 4027
7421 06:56:52.792683 48 : 4360, 4138
7422 06:56:52.793024 52 : 4250, 4027
7423 06:56:52.795268 56 : 4250, 4027
7424 06:56:52.795689 60 : 4250, 4026
7425 06:56:52.798710 64 : 4252, 4030
7426 06:56:52.799131 68 : 4361, 4137
7427 06:56:52.801972 72 : 4253, 4029
7428 06:56:52.802393 76 : 4360, 4137
7429 06:56:52.802820 80 : 4250, 4026
7430 06:56:52.805197 84 : 4250, 4027
7431 06:56:52.805618 88 : 4250, 124
7432 06:56:52.808795 92 : 4250, 0
7433 06:56:52.809216 96 : 4361, 0
7434 06:56:52.809566 100 : 4361, 0
7435 06:56:52.811638 104 : 4250, 0
7436 06:56:52.811940 108 : 4360, 0
7437 06:56:52.814799 112 : 4250, 0
7438 06:56:52.815099 116 : 4249, 0
7439 06:56:52.815336 120 : 4250, 0
7440 06:56:52.818632 124 : 4250, 0
7441 06:56:52.818858 128 : 4249, 0
7442 06:56:52.821306 132 : 4250, 0
7443 06:56:52.821533 136 : 4252, 0
7444 06:56:52.821713 140 : 4252, 0
7445 06:56:52.824693 144 : 4250, 0
7446 06:56:52.824919 148 : 4252, 0
7447 06:56:52.828067 152 : 4360, 0
7448 06:56:52.828313 156 : 4360, 0
7449 06:56:52.828500 160 : 4363, 0
7450 06:56:52.831351 164 : 4250, 0
7451 06:56:52.831721 168 : 4249, 0
7452 06:56:52.831994 172 : 4252, 0
7453 06:56:52.835288 176 : 4250, 0
7454 06:56:52.835511 180 : 4249, 0
7455 06:56:52.837742 184 : 4250, 0
7456 06:56:52.837969 188 : 4253, 0
7457 06:56:52.838149 192 : 4252, 0
7458 06:56:52.841872 196 : 4250, 0
7459 06:56:52.842097 200 : 4253, 0
7460 06:56:52.844996 204 : 4250, 1398
7461 06:56:52.845329 208 : 4252, 4014
7462 06:56:52.848254 212 : 4250, 4027
7463 06:56:52.848491 216 : 4249, 4027
7464 06:56:52.851753 220 : 4363, 4139
7465 06:56:52.851977 224 : 4363, 4140
7466 06:56:52.852154 228 : 4250, 4027
7467 06:56:52.855092 232 : 4362, 4140
7468 06:56:52.855317 236 : 4361, 4137
7469 06:56:52.857884 240 : 4253, 4029
7470 06:56:52.858108 244 : 4250, 4027
7471 06:56:52.861567 248 : 4250, 4027
7472 06:56:52.861792 252 : 4250, 4026
7473 06:56:52.864605 256 : 4250, 4026
7474 06:56:52.864941 260 : 4250, 4027
7475 06:56:52.868107 264 : 4252, 4029
7476 06:56:52.868355 268 : 4250, 4026
7477 06:56:52.871714 272 : 4361, 4137
7478 06:56:52.872282 276 : 4361, 4137
7479 06:56:52.875324 280 : 4247, 4025
7480 06:56:52.875900 284 : 4363, 4140
7481 06:56:52.876462 288 : 4361, 4137
7482 06:56:52.878214 292 : 4250, 4026
7483 06:56:52.878652 296 : 4250, 4027
7484 06:56:52.881612 300 : 4252, 4029
7485 06:56:52.882141 304 : 4250, 4026
7486 06:56:52.885001 308 : 4250, 3964
7487 06:56:52.885452 312 : 4250, 1971
7488 06:56:52.885833
7489 06:56:52.888010 MIOCK jitter meter ch=0
7490 06:56:52.888456
7491 06:56:52.891506 1T = (312-88) = 224 dly cells
7492 06:56:52.898925 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7493 06:56:52.899436 ==
7494 06:56:52.901918 Dram Type= 6, Freq= 0, CH_0, rank 0
7495 06:56:52.904601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7496 06:56:52.905034 ==
7497 06:56:52.911233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7498 06:56:52.914849 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7499 06:56:52.918242 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7500 06:56:52.924730 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7501 06:56:52.932820 [CA 0] Center 42 (12~73) winsize 62
7502 06:56:52.936098 [CA 1] Center 42 (12~73) winsize 62
7503 06:56:52.940165 [CA 2] Center 38 (8~68) winsize 61
7504 06:56:52.943772 [CA 3] Center 37 (8~67) winsize 60
7505 06:56:52.946336 [CA 4] Center 36 (6~66) winsize 61
7506 06:56:52.950280 [CA 5] Center 35 (6~64) winsize 59
7507 06:56:52.950588
7508 06:56:52.953420 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7509 06:56:52.953649
7510 06:56:52.956462 [CATrainingPosCal] consider 1 rank data
7511 06:56:52.959690 u2DelayCellTimex100 = 290/100 ps
7512 06:56:52.963594 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7513 06:56:52.970283 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7514 06:56:52.973412 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7515 06:56:52.976943 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7516 06:56:52.979741 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7517 06:56:52.983641 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7518 06:56:52.984194
7519 06:56:52.986876 CA PerBit enable=1, Macro0, CA PI delay=35
7520 06:56:52.987333
7521 06:56:52.990427 [CBTSetCACLKResult] CA Dly = 35
7522 06:56:52.993095 CS Dly: 9 (0~40)
7523 06:56:52.996532 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7524 06:56:52.999812 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7525 06:56:53.000269 ==
7526 06:56:53.003196 Dram Type= 6, Freq= 0, CH_0, rank 1
7527 06:56:53.006717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 06:56:53.007403 ==
7529 06:56:53.013153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7530 06:56:53.016203 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7531 06:56:53.023661 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7532 06:56:53.026504 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7533 06:56:53.036591 [CA 0] Center 42 (12~73) winsize 62
7534 06:56:53.039922 [CA 1] Center 42 (12~73) winsize 62
7535 06:56:53.043294 [CA 2] Center 38 (8~68) winsize 61
7536 06:56:53.046596 [CA 3] Center 37 (7~67) winsize 61
7537 06:56:53.050469 [CA 4] Center 36 (6~66) winsize 61
7538 06:56:53.053765 [CA 5] Center 35 (5~65) winsize 61
7539 06:56:53.054318
7540 06:56:53.056608 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7541 06:56:53.057063
7542 06:56:53.059716 [CATrainingPosCal] consider 2 rank data
7543 06:56:53.063648 u2DelayCellTimex100 = 290/100 ps
7544 06:56:53.066626 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7545 06:56:53.073557 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7546 06:56:53.076865 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7547 06:56:53.079939 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7548 06:56:53.083446 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7549 06:56:53.086591 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7550 06:56:53.087152
7551 06:56:53.090246 CA PerBit enable=1, Macro0, CA PI delay=35
7552 06:56:53.090702
7553 06:56:53.093430 [CBTSetCACLKResult] CA Dly = 35
7554 06:56:53.096717 CS Dly: 10 (0~42)
7555 06:56:53.100153 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7556 06:56:53.103512 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7557 06:56:53.104059
7558 06:56:53.106438 ----->DramcWriteLeveling(PI) begin...
7559 06:56:53.106993 ==
7560 06:56:53.109690 Dram Type= 6, Freq= 0, CH_0, rank 0
7561 06:56:53.113475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 06:56:53.116518 ==
7563 06:56:53.116973 Write leveling (Byte 0): 34 => 34
7564 06:56:53.120104 Write leveling (Byte 1): 26 => 26
7565 06:56:53.123542 DramcWriteLeveling(PI) end<-----
7566 06:56:53.124091
7567 06:56:53.124495 ==
7568 06:56:53.126430 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 06:56:53.133173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 06:56:53.133636 ==
7571 06:56:53.133994 [Gating] SW mode calibration
7572 06:56:53.143275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7573 06:56:53.146567 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7574 06:56:53.150003 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7575 06:56:53.156336 1 4 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7576 06:56:53.159649 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7577 06:56:53.162978 1 4 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7578 06:56:53.169889 1 4 16 | B1->B0 | 2424 3838 | 0 1 | (0 0) (1 1)
7579 06:56:53.173282 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 06:56:53.176371 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7581 06:56:53.183614 1 4 28 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7582 06:56:53.186737 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7583 06:56:53.189995 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 06:56:53.196953 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7585 06:56:53.200325 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7586 06:56:53.203444 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
7587 06:56:53.209923 1 5 20 | B1->B0 | 2b2b 2b2b | 0 1 | (1 0) (0 0)
7588 06:56:53.213168 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7589 06:56:53.216219 1 5 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
7590 06:56:53.223536 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 06:56:53.227028 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7592 06:56:53.229944 1 6 8 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7593 06:56:53.236881 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7594 06:56:53.240117 1 6 16 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
7595 06:56:53.243371 1 6 20 | B1->B0 | 4545 4646 | 0 1 | (0 0) (0 0)
7596 06:56:53.249582 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 06:56:53.253109 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 06:56:53.256141 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 06:56:53.262803 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 06:56:53.266417 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 06:56:53.269659 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7602 06:56:53.273026 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7603 06:56:53.279644 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 06:56:53.282731 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7605 06:56:53.285988 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 06:56:53.293152 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 06:56:53.296255 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 06:56:53.299705 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 06:56:53.306674 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 06:56:53.309915 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 06:56:53.313008 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 06:56:53.319197 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 06:56:53.322960 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 06:56:53.326180 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 06:56:53.332513 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 06:56:53.336340 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 06:56:53.339342 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7618 06:56:53.346173 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7619 06:56:53.346725 Total UI for P1: 0, mck2ui 16
7620 06:56:53.352885 best dqsien dly found for B0: ( 1, 9, 12)
7621 06:56:53.355898 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7622 06:56:53.359176 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 06:56:53.362861 Total UI for P1: 0, mck2ui 16
7624 06:56:53.366213 best dqsien dly found for B1: ( 1, 9, 18)
7625 06:56:53.369272 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7626 06:56:53.373007 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7627 06:56:53.373553
7628 06:56:53.379113 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7629 06:56:53.382618 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7630 06:56:53.383171 [Gating] SW calibration Done
7631 06:56:53.385900 ==
7632 06:56:53.389402 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 06:56:53.393029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 06:56:53.393594 ==
7635 06:56:53.393958 RX Vref Scan: 0
7636 06:56:53.394291
7637 06:56:53.396056 RX Vref 0 -> 0, step: 1
7638 06:56:53.396562
7639 06:56:53.399312 RX Delay 0 -> 252, step: 8
7640 06:56:53.402772 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7641 06:56:53.405573 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7642 06:56:53.409562 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7643 06:56:53.415581 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7644 06:56:53.419265 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7645 06:56:53.422614 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7646 06:56:53.425508 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7647 06:56:53.428913 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7648 06:56:53.435770 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7649 06:56:53.438944 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7650 06:56:53.442186 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7651 06:56:53.445588 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7652 06:56:53.448861 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7653 06:56:53.455560 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7654 06:56:53.458876 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7655 06:56:53.462141 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7656 06:56:53.462600 ==
7657 06:56:53.465357 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 06:56:53.468899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 06:56:53.469508 ==
7660 06:56:53.472324 DQS Delay:
7661 06:56:53.472788 DQS0 = 0, DQS1 = 0
7662 06:56:53.475446 DQM Delay:
7663 06:56:53.475900 DQM0 = 137, DQM1 = 130
7664 06:56:53.478726 DQ Delay:
7665 06:56:53.482354 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7666 06:56:53.485776 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7667 06:56:53.488946 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7668 06:56:53.491890 DQ12 =131, DQ13 =139, DQ14 =139, DQ15 =135
7669 06:56:53.492432
7670 06:56:53.492811
7671 06:56:53.493147 ==
7672 06:56:53.495502 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 06:56:53.499383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 06:56:53.499937 ==
7675 06:56:53.500338
7676 06:56:53.500681
7677 06:56:53.502052 TX Vref Scan disable
7678 06:56:53.505611 == TX Byte 0 ==
7679 06:56:53.508898 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7680 06:56:53.512589 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7681 06:56:53.515884 == TX Byte 1 ==
7682 06:56:53.518600 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7683 06:56:53.522700 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7684 06:56:53.523253 ==
7685 06:56:53.525778 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 06:56:53.528928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 06:56:53.532339 ==
7688 06:56:53.544259
7689 06:56:53.547676 TX Vref early break, caculate TX vref
7690 06:56:53.550951 TX Vref=16, minBit 3, minWin=23, winSum=382
7691 06:56:53.553922 TX Vref=18, minBit 7, minWin=23, winSum=389
7692 06:56:53.557438 TX Vref=20, minBit 0, minWin=24, winSum=401
7693 06:56:53.560843 TX Vref=22, minBit 4, minWin=24, winSum=408
7694 06:56:53.563992 TX Vref=24, minBit 11, minWin=25, winSum=420
7695 06:56:53.570696 TX Vref=26, minBit 7, minWin=25, winSum=428
7696 06:56:53.574555 TX Vref=28, minBit 1, minWin=25, winSum=425
7697 06:56:53.577353 TX Vref=30, minBit 6, minWin=24, winSum=415
7698 06:56:53.580792 TX Vref=32, minBit 6, minWin=24, winSum=407
7699 06:56:53.584389 TX Vref=34, minBit 6, minWin=22, winSum=397
7700 06:56:53.590772 [TxChooseVref] Worse bit 7, Min win 25, Win sum 428, Final Vref 26
7701 06:56:53.591327
7702 06:56:53.593773 Final TX Range 0 Vref 26
7703 06:56:53.594232
7704 06:56:53.594595 ==
7705 06:56:53.597388 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 06:56:53.600551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 06:56:53.601012 ==
7708 06:56:53.601369
7709 06:56:53.601700
7710 06:56:53.603784 TX Vref Scan disable
7711 06:56:53.610725 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7712 06:56:53.611274 == TX Byte 0 ==
7713 06:56:53.614120 u2DelayCellOfst[0]=10 cells (3 PI)
7714 06:56:53.617404 u2DelayCellOfst[1]=13 cells (4 PI)
7715 06:56:53.620836 u2DelayCellOfst[2]=10 cells (3 PI)
7716 06:56:53.623706 u2DelayCellOfst[3]=6 cells (2 PI)
7717 06:56:53.627357 u2DelayCellOfst[4]=6 cells (2 PI)
7718 06:56:53.630356 u2DelayCellOfst[5]=0 cells (0 PI)
7719 06:56:53.633840 u2DelayCellOfst[6]=16 cells (5 PI)
7720 06:56:53.637192 u2DelayCellOfst[7]=16 cells (5 PI)
7721 06:56:53.640163 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7722 06:56:53.643670 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7723 06:56:53.647199 == TX Byte 1 ==
7724 06:56:53.647751 u2DelayCellOfst[8]=0 cells (0 PI)
7725 06:56:53.650113 u2DelayCellOfst[9]=0 cells (0 PI)
7726 06:56:53.653776 u2DelayCellOfst[10]=3 cells (1 PI)
7727 06:56:53.657053 u2DelayCellOfst[11]=0 cells (0 PI)
7728 06:56:53.660167 u2DelayCellOfst[12]=6 cells (2 PI)
7729 06:56:53.663160 u2DelayCellOfst[13]=10 cells (3 PI)
7730 06:56:53.666923 u2DelayCellOfst[14]=13 cells (4 PI)
7731 06:56:53.669934 u2DelayCellOfst[15]=6 cells (2 PI)
7732 06:56:53.673793 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7733 06:56:53.680340 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7734 06:56:53.680912 DramC Write-DBI on
7735 06:56:53.681274 ==
7736 06:56:53.683374 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 06:56:53.686568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 06:56:53.689581 ==
7739 06:56:53.690030
7740 06:56:53.690387
7741 06:56:53.690715 TX Vref Scan disable
7742 06:56:53.693241 == TX Byte 0 ==
7743 06:56:53.697195 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7744 06:56:53.700018 == TX Byte 1 ==
7745 06:56:53.703272 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7746 06:56:53.703822 DramC Write-DBI off
7747 06:56:53.707099
7748 06:56:53.707646 [DATLAT]
7749 06:56:53.708008 Freq=1600, CH0 RK0
7750 06:56:53.708414
7751 06:56:53.710037 DATLAT Default: 0xf
7752 06:56:53.710502 0, 0xFFFF, sum = 0
7753 06:56:53.713365 1, 0xFFFF, sum = 0
7754 06:56:53.713924 2, 0xFFFF, sum = 0
7755 06:56:53.717204 3, 0xFFFF, sum = 0
7756 06:56:53.719935 4, 0xFFFF, sum = 0
7757 06:56:53.720538 5, 0xFFFF, sum = 0
7758 06:56:53.723729 6, 0xFFFF, sum = 0
7759 06:56:53.724322 7, 0xFFFF, sum = 0
7760 06:56:53.727235 8, 0xFFFF, sum = 0
7761 06:56:53.727970 9, 0xFFFF, sum = 0
7762 06:56:53.729886 10, 0xFFFF, sum = 0
7763 06:56:53.730349 11, 0xFFFF, sum = 0
7764 06:56:53.733373 12, 0xFFFF, sum = 0
7765 06:56:53.733830 13, 0xFFFF, sum = 0
7766 06:56:53.736691 14, 0x0, sum = 1
7767 06:56:53.737252 15, 0x0, sum = 2
7768 06:56:53.740214 16, 0x0, sum = 3
7769 06:56:53.740724 17, 0x0, sum = 4
7770 06:56:53.743029 best_step = 15
7771 06:56:53.743505
7772 06:56:53.743897 ==
7773 06:56:53.746939 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 06:56:53.749790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 06:56:53.750246 ==
7776 06:56:53.750601 RX Vref Scan: 1
7777 06:56:53.753511
7778 06:56:53.753962 Set Vref Range= 24 -> 127
7779 06:56:53.754319
7780 06:56:53.756798 RX Vref 24 -> 127, step: 1
7781 06:56:53.757251
7782 06:56:53.760105 RX Delay 27 -> 252, step: 4
7783 06:56:53.760663
7784 06:56:53.763245 Set Vref, RX VrefLevel [Byte0]: 24
7785 06:56:53.767068 [Byte1]: 24
7786 06:56:53.767581
7787 06:56:53.769547 Set Vref, RX VrefLevel [Byte0]: 25
7788 06:56:53.773231 [Byte1]: 25
7789 06:56:53.773641
7790 06:56:53.776754 Set Vref, RX VrefLevel [Byte0]: 26
7791 06:56:53.779882 [Byte1]: 26
7792 06:56:53.783619
7793 06:56:53.784123 Set Vref, RX VrefLevel [Byte0]: 27
7794 06:56:53.786793 [Byte1]: 27
7795 06:56:53.791228
7796 06:56:53.791736 Set Vref, RX VrefLevel [Byte0]: 28
7797 06:56:53.794462 [Byte1]: 28
7798 06:56:53.798862
7799 06:56:53.799371 Set Vref, RX VrefLevel [Byte0]: 29
7800 06:56:53.801998 [Byte1]: 29
7801 06:56:53.806168
7802 06:56:53.806673 Set Vref, RX VrefLevel [Byte0]: 30
7803 06:56:53.809713 [Byte1]: 30
7804 06:56:53.813329
7805 06:56:53.813814 Set Vref, RX VrefLevel [Byte0]: 31
7806 06:56:53.816896 [Byte1]: 31
7807 06:56:53.821071
7808 06:56:53.821497 Set Vref, RX VrefLevel [Byte0]: 32
7809 06:56:53.824237 [Byte1]: 32
7810 06:56:53.828665
7811 06:56:53.829114 Set Vref, RX VrefLevel [Byte0]: 33
7812 06:56:53.831771 [Byte1]: 33
7813 06:56:53.836703
7814 06:56:53.837288 Set Vref, RX VrefLevel [Byte0]: 34
7815 06:56:53.839433 [Byte1]: 34
7816 06:56:53.844064
7817 06:56:53.844664 Set Vref, RX VrefLevel [Byte0]: 35
7818 06:56:53.847100 [Byte1]: 35
7819 06:56:53.851186
7820 06:56:53.851641 Set Vref, RX VrefLevel [Byte0]: 36
7821 06:56:53.854708 [Byte1]: 36
7822 06:56:53.858572
7823 06:56:53.859076 Set Vref, RX VrefLevel [Byte0]: 37
7824 06:56:53.861821 [Byte1]: 37
7825 06:56:53.866264
7826 06:56:53.866718 Set Vref, RX VrefLevel [Byte0]: 38
7827 06:56:53.869583 [Byte1]: 38
7828 06:56:53.873927
7829 06:56:53.874349 Set Vref, RX VrefLevel [Byte0]: 39
7830 06:56:53.877035 [Byte1]: 39
7831 06:56:53.881494
7832 06:56:53.881908 Set Vref, RX VrefLevel [Byte0]: 40
7833 06:56:53.884567 [Byte1]: 40
7834 06:56:53.889191
7835 06:56:53.889606 Set Vref, RX VrefLevel [Byte0]: 41
7836 06:56:53.892365 [Byte1]: 41
7837 06:56:53.896852
7838 06:56:53.897377 Set Vref, RX VrefLevel [Byte0]: 42
7839 06:56:53.900031 [Byte1]: 42
7840 06:56:53.904049
7841 06:56:53.904658 Set Vref, RX VrefLevel [Byte0]: 43
7842 06:56:53.907665 [Byte1]: 43
7843 06:56:53.911560
7844 06:56:53.912110 Set Vref, RX VrefLevel [Byte0]: 44
7845 06:56:53.915442 [Byte1]: 44
7846 06:56:53.919199
7847 06:56:53.919749 Set Vref, RX VrefLevel [Byte0]: 45
7848 06:56:53.922806 [Byte1]: 45
7849 06:56:53.926389
7850 06:56:53.926842 Set Vref, RX VrefLevel [Byte0]: 46
7851 06:56:53.930071 [Byte1]: 46
7852 06:56:53.933979
7853 06:56:53.934433 Set Vref, RX VrefLevel [Byte0]: 47
7854 06:56:53.937253 [Byte1]: 47
7855 06:56:53.942218
7856 06:56:53.942766 Set Vref, RX VrefLevel [Byte0]: 48
7857 06:56:53.945030 [Byte1]: 48
7858 06:56:53.949390
7859 06:56:53.950048 Set Vref, RX VrefLevel [Byte0]: 49
7860 06:56:53.952593 [Byte1]: 49
7861 06:56:53.956917
7862 06:56:53.957426 Set Vref, RX VrefLevel [Byte0]: 50
7863 06:56:53.960273 [Byte1]: 50
7864 06:56:53.964480
7865 06:56:53.964900 Set Vref, RX VrefLevel [Byte0]: 51
7866 06:56:53.967840 [Byte1]: 51
7867 06:56:53.971612
7868 06:56:53.972096 Set Vref, RX VrefLevel [Byte0]: 52
7869 06:56:53.975032 [Byte1]: 52
7870 06:56:53.979410
7871 06:56:53.979862 Set Vref, RX VrefLevel [Byte0]: 53
7872 06:56:53.982675 [Byte1]: 53
7873 06:56:53.987254
7874 06:56:53.987797 Set Vref, RX VrefLevel [Byte0]: 54
7875 06:56:53.990202 [Byte1]: 54
7876 06:56:53.994367
7877 06:56:53.994824 Set Vref, RX VrefLevel [Byte0]: 55
7878 06:56:53.998025 [Byte1]: 55
7879 06:56:54.002062
7880 06:56:54.002518 Set Vref, RX VrefLevel [Byte0]: 56
7881 06:56:54.005541 [Byte1]: 56
7882 06:56:54.009920
7883 06:56:54.010475 Set Vref, RX VrefLevel [Byte0]: 57
7884 06:56:54.012842 [Byte1]: 57
7885 06:56:54.017636
7886 06:56:54.018186 Set Vref, RX VrefLevel [Byte0]: 58
7887 06:56:54.020583 [Byte1]: 58
7888 06:56:54.024659
7889 06:56:54.025210 Set Vref, RX VrefLevel [Byte0]: 59
7890 06:56:54.027856 [Byte1]: 59
7891 06:56:54.032396
7892 06:56:54.032891 Set Vref, RX VrefLevel [Byte0]: 60
7893 06:56:54.035232 [Byte1]: 60
7894 06:56:54.039438
7895 06:56:54.039887 Set Vref, RX VrefLevel [Byte0]: 61
7896 06:56:54.043584 [Byte1]: 61
7897 06:56:54.047236
7898 06:56:54.047865 Set Vref, RX VrefLevel [Byte0]: 62
7899 06:56:54.050358 [Byte1]: 62
7900 06:56:54.054580
7901 06:56:54.055043 Set Vref, RX VrefLevel [Byte0]: 63
7902 06:56:54.057660 [Byte1]: 63
7903 06:56:54.062088
7904 06:56:54.062537 Set Vref, RX VrefLevel [Byte0]: 64
7905 06:56:54.065445 [Byte1]: 64
7906 06:56:54.070072
7907 06:56:54.070617 Set Vref, RX VrefLevel [Byte0]: 65
7908 06:56:54.073143 [Byte1]: 65
7909 06:56:54.077563
7910 06:56:54.078012 Set Vref, RX VrefLevel [Byte0]: 66
7911 06:56:54.080596 [Byte1]: 66
7912 06:56:54.084808
7913 06:56:54.085344 Set Vref, RX VrefLevel [Byte0]: 67
7914 06:56:54.088195 [Byte1]: 67
7915 06:56:54.092172
7916 06:56:54.092801 Set Vref, RX VrefLevel [Byte0]: 68
7917 06:56:54.095751 [Byte1]: 68
7918 06:56:54.100254
7919 06:56:54.100930 Set Vref, RX VrefLevel [Byte0]: 69
7920 06:56:54.103486 [Byte1]: 69
7921 06:56:54.107137
7922 06:56:54.107588 Set Vref, RX VrefLevel [Byte0]: 70
7923 06:56:54.110640 [Byte1]: 70
7924 06:56:54.115219
7925 06:56:54.115697 Set Vref, RX VrefLevel [Byte0]: 71
7926 06:56:54.118158 [Byte1]: 71
7927 06:56:54.122020
7928 06:56:54.122485 Set Vref, RX VrefLevel [Byte0]: 72
7929 06:56:54.126008 [Byte1]: 72
7930 06:56:54.129564
7931 06:56:54.130005 Final RX Vref Byte 0 = 57 to rank0
7932 06:56:54.133463 Final RX Vref Byte 1 = 65 to rank0
7933 06:56:54.136698 Final RX Vref Byte 0 = 57 to rank1
7934 06:56:54.140101 Final RX Vref Byte 1 = 65 to rank1==
7935 06:56:54.143561 Dram Type= 6, Freq= 0, CH_0, rank 0
7936 06:56:54.149702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7937 06:56:54.150198 ==
7938 06:56:54.150524 DQS Delay:
7939 06:56:54.150826 DQS0 = 0, DQS1 = 0
7940 06:56:54.152978 DQM Delay:
7941 06:56:54.153386 DQM0 = 133, DQM1 = 128
7942 06:56:54.156540 DQ Delay:
7943 06:56:54.159453 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7944 06:56:54.162950 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7945 06:56:54.167093 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
7946 06:56:54.170005 DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136
7947 06:56:54.170516
7948 06:56:54.170843
7949 06:56:54.171143
7950 06:56:54.173071 [DramC_TX_OE_Calibration] TA2
7951 06:56:54.176516 Original DQ_B0 (3 6) =30, OEN = 27
7952 06:56:54.179996 Original DQ_B1 (3 6) =30, OEN = 27
7953 06:56:54.183194 24, 0x0, End_B0=24 End_B1=24
7954 06:56:54.183753 25, 0x0, End_B0=25 End_B1=25
7955 06:56:54.186827 26, 0x0, End_B0=26 End_B1=26
7956 06:56:54.189719 27, 0x0, End_B0=27 End_B1=27
7957 06:56:54.193276 28, 0x0, End_B0=28 End_B1=28
7958 06:56:54.193741 29, 0x0, End_B0=29 End_B1=29
7959 06:56:54.196589 30, 0x0, End_B0=30 End_B1=30
7960 06:56:54.199592 31, 0x4141, End_B0=30 End_B1=30
7961 06:56:54.203171 Byte0 end_step=30 best_step=27
7962 06:56:54.206363 Byte1 end_step=30 best_step=27
7963 06:56:54.209863 Byte0 TX OE(2T, 0.5T) = (3, 3)
7964 06:56:54.210319 Byte1 TX OE(2T, 0.5T) = (3, 3)
7965 06:56:54.212888
7966 06:56:54.213373
7967 06:56:54.219794 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7968 06:56:54.223686 CH0 RK0: MR19=303, MR18=2521
7969 06:56:54.229968 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7970 06:56:54.230607
7971 06:56:54.232941 ----->DramcWriteLeveling(PI) begin...
7972 06:56:54.233423 ==
7973 06:56:54.236381 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 06:56:54.239436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7975 06:56:54.239913 ==
7976 06:56:54.243185 Write leveling (Byte 0): 35 => 35
7977 06:56:54.246666 Write leveling (Byte 1): 27 => 27
7978 06:56:54.249569 DramcWriteLeveling(PI) end<-----
7979 06:56:54.250040
7980 06:56:54.250521 ==
7981 06:56:54.252602 Dram Type= 6, Freq= 0, CH_0, rank 1
7982 06:56:54.256210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 06:56:54.256732 ==
7984 06:56:54.259339 [Gating] SW mode calibration
7985 06:56:54.266560 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7986 06:56:54.272671 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7987 06:56:54.275992 1 4 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7988 06:56:54.279951 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7989 06:56:54.286524 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 06:56:54.289499 1 4 12 | B1->B0 | 2322 2727 | 1 0 | (0 0) (1 1)
7991 06:56:54.292943 1 4 16 | B1->B0 | 3030 3636 | 1 0 | (1 1) (0 0)
7992 06:56:54.299486 1 4 20 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7993 06:56:54.302734 1 4 24 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7994 06:56:54.305806 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7995 06:56:54.312816 1 5 0 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7996 06:56:54.316253 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7997 06:56:54.319326 1 5 8 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7998 06:56:54.325562 1 5 12 | B1->B0 | 3434 3535 | 1 1 | (1 0) (0 1)
7999 06:56:54.329036 1 5 16 | B1->B0 | 2f2f 2929 | 0 0 | (0 1) (1 0)
8000 06:56:54.332434 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8001 06:56:54.339269 1 5 24 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
8002 06:56:54.342696 1 5 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8003 06:56:54.346146 1 6 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
8004 06:56:54.352516 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8005 06:56:54.356251 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8006 06:56:54.359395 1 6 12 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (1 1)
8007 06:56:54.365913 1 6 16 | B1->B0 | 3e3e 4645 | 0 1 | (0 0) (0 0)
8008 06:56:54.368995 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 06:56:54.372517 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8010 06:56:54.379201 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 06:56:54.382308 1 7 0 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8012 06:56:54.385807 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 06:56:54.392851 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 06:56:54.396059 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8015 06:56:54.399128 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8016 06:56:54.402301 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 06:56:54.409003 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 06:56:54.412371 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 06:56:54.415568 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 06:56:54.422720 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 06:56:54.425596 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 06:56:54.428967 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 06:56:54.435861 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 06:56:54.438806 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 06:56:54.442056 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 06:56:54.448900 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 06:56:54.452329 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 06:56:54.455244 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 06:56:54.461847 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 06:56:54.465476 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8031 06:56:54.469143 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8032 06:56:54.475337 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 06:56:54.475884 Total UI for P1: 0, mck2ui 16
8034 06:56:54.482161 best dqsien dly found for B0: ( 1, 9, 14)
8035 06:56:54.482648 Total UI for P1: 0, mck2ui 16
8036 06:56:54.488947 best dqsien dly found for B1: ( 1, 9, 14)
8037 06:56:54.491917 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8038 06:56:54.495265 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8039 06:56:54.495861
8040 06:56:54.498477 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8041 06:56:54.502476 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8042 06:56:54.505649 [Gating] SW calibration Done
8043 06:56:54.506200 ==
8044 06:56:54.508861 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 06:56:54.512178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 06:56:54.512761 ==
8047 06:56:54.515381 RX Vref Scan: 0
8048 06:56:54.515933
8049 06:56:54.516333 RX Vref 0 -> 0, step: 1
8050 06:56:54.516679
8051 06:56:54.518522 RX Delay 0 -> 252, step: 8
8052 06:56:54.521642 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8053 06:56:54.528931 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8054 06:56:54.531886 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8055 06:56:54.535143 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8056 06:56:54.538899 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8057 06:56:54.541956 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8058 06:56:54.548555 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8059 06:56:54.551704 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8060 06:56:54.554663 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8061 06:56:54.558690 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8062 06:56:54.561862 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8063 06:56:54.568165 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8064 06:56:54.571757 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8065 06:56:54.575141 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8066 06:56:54.578248 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8067 06:56:54.585104 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8068 06:56:54.585514 ==
8069 06:56:54.588050 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 06:56:54.591564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 06:56:54.592079 ==
8072 06:56:54.592463 DQS Delay:
8073 06:56:54.594812 DQS0 = 0, DQS1 = 0
8074 06:56:54.595222 DQM Delay:
8075 06:56:54.597980 DQM0 = 137, DQM1 = 131
8076 06:56:54.598388 DQ Delay:
8077 06:56:54.601787 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8078 06:56:54.604893 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8079 06:56:54.608176 DQ8 =123, DQ9 =119, DQ10 =131, DQ11 =123
8080 06:56:54.611579 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8081 06:56:54.612103
8082 06:56:54.612586
8083 06:56:54.612994 ==
8084 06:56:54.614745 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 06:56:54.621243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 06:56:54.621772 ==
8087 06:56:54.622215
8088 06:56:54.622624
8089 06:56:54.624670 TX Vref Scan disable
8090 06:56:54.625198 == TX Byte 0 ==
8091 06:56:54.627854 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8092 06:56:54.634924 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8093 06:56:54.635448 == TX Byte 1 ==
8094 06:56:54.638089 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8095 06:56:54.644498 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8096 06:56:54.645021 ==
8097 06:56:54.647829 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 06:56:54.651235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 06:56:54.651761 ==
8100 06:56:54.665213
8101 06:56:54.668616 TX Vref early break, caculate TX vref
8102 06:56:54.671770 TX Vref=16, minBit 1, minWin=22, winSum=385
8103 06:56:54.674669 TX Vref=18, minBit 1, minWin=22, winSum=395
8104 06:56:54.678543 TX Vref=20, minBit 3, minWin=23, winSum=403
8105 06:56:54.681864 TX Vref=22, minBit 1, minWin=24, winSum=414
8106 06:56:54.684906 TX Vref=24, minBit 2, minWin=25, winSum=420
8107 06:56:54.691801 TX Vref=26, minBit 4, minWin=24, winSum=427
8108 06:56:54.695036 TX Vref=28, minBit 1, minWin=25, winSum=425
8109 06:56:54.698733 TX Vref=30, minBit 0, minWin=25, winSum=418
8110 06:56:54.701678 TX Vref=32, minBit 0, minWin=24, winSum=405
8111 06:56:54.705352 TX Vref=34, minBit 0, minWin=23, winSum=399
8112 06:56:54.711768 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 28
8113 06:56:54.712397
8114 06:56:54.714977 Final TX Range 0 Vref 28
8115 06:56:54.715429
8116 06:56:54.715784 ==
8117 06:56:54.718682 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 06:56:54.721631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 06:56:54.722140 ==
8120 06:56:54.722504
8121 06:56:54.722837
8122 06:56:54.724953 TX Vref Scan disable
8123 06:56:54.731547 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8124 06:56:54.731978 == TX Byte 0 ==
8125 06:56:54.734633 u2DelayCellOfst[0]=13 cells (4 PI)
8126 06:56:54.738585 u2DelayCellOfst[1]=16 cells (5 PI)
8127 06:56:54.741630 u2DelayCellOfst[2]=13 cells (4 PI)
8128 06:56:54.744846 u2DelayCellOfst[3]=10 cells (3 PI)
8129 06:56:54.748483 u2DelayCellOfst[4]=6 cells (2 PI)
8130 06:56:54.751682 u2DelayCellOfst[5]=0 cells (0 PI)
8131 06:56:54.754855 u2DelayCellOfst[6]=16 cells (5 PI)
8132 06:56:54.757828 u2DelayCellOfst[7]=16 cells (5 PI)
8133 06:56:54.761364 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8134 06:56:54.764403 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8135 06:56:54.768177 == TX Byte 1 ==
8136 06:56:54.771167 u2DelayCellOfst[8]=3 cells (1 PI)
8137 06:56:54.771644 u2DelayCellOfst[9]=0 cells (0 PI)
8138 06:56:54.774349 u2DelayCellOfst[10]=6 cells (2 PI)
8139 06:56:54.777812 u2DelayCellOfst[11]=3 cells (1 PI)
8140 06:56:54.780814 u2DelayCellOfst[12]=13 cells (4 PI)
8141 06:56:54.784644 u2DelayCellOfst[13]=10 cells (3 PI)
8142 06:56:54.787941 u2DelayCellOfst[14]=13 cells (4 PI)
8143 06:56:54.790827 u2DelayCellOfst[15]=13 cells (4 PI)
8144 06:56:54.794417 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8145 06:56:54.800885 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8146 06:56:54.801447 DramC Write-DBI on
8147 06:56:54.801815 ==
8148 06:56:54.803874 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 06:56:54.810941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 06:56:54.811507 ==
8151 06:56:54.811875
8152 06:56:54.812212
8153 06:56:54.812583 TX Vref Scan disable
8154 06:56:54.814532 == TX Byte 0 ==
8155 06:56:54.818510 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8156 06:56:54.821405 == TX Byte 1 ==
8157 06:56:54.824922 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8158 06:56:54.827989 DramC Write-DBI off
8159 06:56:54.828613
8160 06:56:54.829097 [DATLAT]
8161 06:56:54.829550 Freq=1600, CH0 RK1
8162 06:56:54.829988
8163 06:56:54.831009 DATLAT Default: 0xf
8164 06:56:54.831552 0, 0xFFFF, sum = 0
8165 06:56:54.834483 1, 0xFFFF, sum = 0
8166 06:56:54.834958 2, 0xFFFF, sum = 0
8167 06:56:54.837783 3, 0xFFFF, sum = 0
8168 06:56:54.841080 4, 0xFFFF, sum = 0
8169 06:56:54.841559 5, 0xFFFF, sum = 0
8170 06:56:54.844697 6, 0xFFFF, sum = 0
8171 06:56:54.845174 7, 0xFFFF, sum = 0
8172 06:56:54.848165 8, 0xFFFF, sum = 0
8173 06:56:54.848735 9, 0xFFFF, sum = 0
8174 06:56:54.851311 10, 0xFFFF, sum = 0
8175 06:56:54.851836 11, 0xFFFF, sum = 0
8176 06:56:54.854862 12, 0xFFFF, sum = 0
8177 06:56:54.855406 13, 0xFFFF, sum = 0
8178 06:56:54.858149 14, 0x0, sum = 1
8179 06:56:54.858578 15, 0x0, sum = 2
8180 06:56:54.861342 16, 0x0, sum = 3
8181 06:56:54.861771 17, 0x0, sum = 4
8182 06:56:54.864460 best_step = 15
8183 06:56:54.864896
8184 06:56:54.865258 ==
8185 06:56:54.867567 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 06:56:54.871906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 06:56:54.872464 ==
8188 06:56:54.872992 RX Vref Scan: 0
8189 06:56:54.874410
8190 06:56:54.874814 RX Vref 0 -> 0, step: 1
8191 06:56:54.875140
8192 06:56:54.878081 RX Delay 19 -> 252, step: 4
8193 06:56:54.881157 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8194 06:56:54.888425 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8195 06:56:54.891746 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8196 06:56:54.894342 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8197 06:56:54.897517 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8198 06:56:54.901188 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8199 06:56:54.904696 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8200 06:56:54.911030 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8201 06:56:54.914150 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8202 06:56:54.918025 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8203 06:56:54.921321 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8204 06:56:54.924482 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8205 06:56:54.931667 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8206 06:56:54.934268 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8207 06:56:54.938207 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8208 06:56:54.941229 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8209 06:56:54.941659 ==
8210 06:56:54.944586 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 06:56:54.951522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 06:56:54.952091 ==
8213 06:56:54.952610 DQS Delay:
8214 06:56:54.954568 DQS0 = 0, DQS1 = 0
8215 06:56:54.955033 DQM Delay:
8216 06:56:54.955509 DQM0 = 134, DQM1 = 126
8217 06:56:54.957618 DQ Delay:
8218 06:56:54.961109 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8219 06:56:54.964449 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8220 06:56:54.967788 DQ8 =120, DQ9 =116, DQ10 =126, DQ11 =118
8221 06:56:54.970943 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8222 06:56:54.971370
8223 06:56:54.971810
8224 06:56:54.972221
8225 06:56:54.974501 [DramC_TX_OE_Calibration] TA2
8226 06:56:54.977998 Original DQ_B0 (3 6) =30, OEN = 27
8227 06:56:54.980990 Original DQ_B1 (3 6) =30, OEN = 27
8228 06:56:54.984403 24, 0x0, End_B0=24 End_B1=24
8229 06:56:54.984838 25, 0x0, End_B0=25 End_B1=25
8230 06:56:54.987830 26, 0x0, End_B0=26 End_B1=26
8231 06:56:54.990640 27, 0x0, End_B0=27 End_B1=27
8232 06:56:54.994517 28, 0x0, End_B0=28 End_B1=28
8233 06:56:54.997929 29, 0x0, End_B0=29 End_B1=29
8234 06:56:54.998463 30, 0x0, End_B0=30 End_B1=30
8235 06:56:55.001203 31, 0x4545, End_B0=30 End_B1=30
8236 06:56:55.004324 Byte0 end_step=30 best_step=27
8237 06:56:55.007803 Byte1 end_step=30 best_step=27
8238 06:56:55.011295 Byte0 TX OE(2T, 0.5T) = (3, 3)
8239 06:56:55.014007 Byte1 TX OE(2T, 0.5T) = (3, 3)
8240 06:56:55.014433
8241 06:56:55.014864
8242 06:56:55.021157 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8243 06:56:55.024332 CH0 RK1: MR19=303, MR18=2109
8244 06:56:55.031001 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8245 06:56:55.034050 [RxdqsGatingPostProcess] freq 1600
8246 06:56:55.037855 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8247 06:56:55.040718 best DQS0 dly(2T, 0.5T) = (1, 1)
8248 06:56:55.044433 best DQS1 dly(2T, 0.5T) = (1, 1)
8249 06:56:55.048055 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8250 06:56:55.051253 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8251 06:56:55.054305 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 06:56:55.057387 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 06:56:55.061064 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 06:56:55.064477 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 06:56:55.067799 Pre-setting of DQS Precalculation
8256 06:56:55.070830 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8257 06:56:55.071284 ==
8258 06:56:55.074000 Dram Type= 6, Freq= 0, CH_1, rank 0
8259 06:56:55.077139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 06:56:55.081079 ==
8261 06:56:55.083993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8262 06:56:55.087790 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8263 06:56:55.094414 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8264 06:56:55.097034 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8265 06:56:55.107433 [CA 0] Center 41 (12~71) winsize 60
8266 06:56:55.111026 [CA 1] Center 41 (12~71) winsize 60
8267 06:56:55.114101 [CA 2] Center 38 (9~68) winsize 60
8268 06:56:55.117217 [CA 3] Center 37 (9~66) winsize 58
8269 06:56:55.120947 [CA 4] Center 37 (8~67) winsize 60
8270 06:56:55.124263 [CA 5] Center 36 (7~66) winsize 60
8271 06:56:55.124754
8272 06:56:55.127718 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8273 06:56:55.128351
8274 06:56:55.130562 [CATrainingPosCal] consider 1 rank data
8275 06:56:55.134176 u2DelayCellTimex100 = 290/100 ps
8276 06:56:55.137353 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8277 06:56:55.143861 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8278 06:56:55.147465 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8279 06:56:55.150391 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8280 06:56:55.153671 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8281 06:56:55.157249 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8282 06:56:55.157810
8283 06:56:55.160195 CA PerBit enable=1, Macro0, CA PI delay=36
8284 06:56:55.160700
8285 06:56:55.164038 [CBTSetCACLKResult] CA Dly = 36
8286 06:56:55.167413 CS Dly: 10 (0~41)
8287 06:56:55.170417 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8288 06:56:55.173960 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8289 06:56:55.174427 ==
8290 06:56:55.177319 Dram Type= 6, Freq= 0, CH_1, rank 1
8291 06:56:55.180769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 06:56:55.184017 ==
8293 06:56:55.187240 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 06:56:55.190475 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 06:56:55.197054 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 06:56:55.203812 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 06:56:55.211079 [CA 0] Center 42 (12~72) winsize 61
8298 06:56:55.213755 [CA 1] Center 41 (12~71) winsize 60
8299 06:56:55.217454 [CA 2] Center 38 (9~68) winsize 60
8300 06:56:55.220932 [CA 3] Center 38 (8~68) winsize 61
8301 06:56:55.224316 [CA 4] Center 38 (8~68) winsize 61
8302 06:56:55.227161 [CA 5] Center 37 (7~67) winsize 61
8303 06:56:55.227612
8304 06:56:55.230838 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8305 06:56:55.231469
8306 06:56:55.234000 [CATrainingPosCal] consider 2 rank data
8307 06:56:55.237217 u2DelayCellTimex100 = 290/100 ps
8308 06:56:55.241026 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8309 06:56:55.247346 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8310 06:56:55.250273 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8311 06:56:55.253717 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8312 06:56:55.257200 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8313 06:56:55.260362 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8314 06:56:55.260775
8315 06:56:55.264139 CA PerBit enable=1, Macro0, CA PI delay=36
8316 06:56:55.264595
8317 06:56:55.267555 [CBTSetCACLKResult] CA Dly = 36
8318 06:56:55.270752 CS Dly: 12 (0~45)
8319 06:56:55.273678 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 06:56:55.277628 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 06:56:55.278171
8322 06:56:55.280790 ----->DramcWriteLeveling(PI) begin...
8323 06:56:55.281204 ==
8324 06:56:55.284023 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 06:56:55.287390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 06:56:55.290596 ==
8327 06:56:55.291109 Write leveling (Byte 0): 25 => 25
8328 06:56:55.294575 Write leveling (Byte 1): 28 => 28
8329 06:56:55.296916 DramcWriteLeveling(PI) end<-----
8330 06:56:55.297322
8331 06:56:55.297642 ==
8332 06:56:55.300132 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 06:56:55.307197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 06:56:55.307722 ==
8335 06:56:55.308176 [Gating] SW mode calibration
8336 06:56:55.316788 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8337 06:56:55.320758 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8338 06:56:55.327223 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 06:56:55.330161 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 06:56:55.333928 1 4 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
8341 06:56:55.337232 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8342 06:56:55.343813 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 06:56:55.346639 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 06:56:55.350628 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 06:56:55.356947 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 06:56:55.360097 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 06:56:55.363292 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 06:56:55.370119 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
8349 06:56:55.373688 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
8350 06:56:55.376943 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 06:56:55.383421 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 06:56:55.386830 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 06:56:55.390668 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 06:56:55.397149 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 06:56:55.400332 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 06:56:55.404442 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
8357 06:56:55.410581 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8358 06:56:55.413836 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 06:56:55.416780 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 06:56:55.423419 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 06:56:55.427255 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 06:56:55.430060 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 06:56:55.436649 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 06:56:55.440570 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8365 06:56:55.443574 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8366 06:56:55.450242 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 06:56:55.453155 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 06:56:55.456527 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 06:56:55.463457 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 06:56:55.467234 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 06:56:55.469845 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 06:56:55.476624 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 06:56:55.479605 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 06:56:55.483495 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 06:56:55.489948 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 06:56:55.492816 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 06:56:55.496745 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 06:56:55.499878 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 06:56:55.506237 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 06:56:55.509482 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8381 06:56:55.512860 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8382 06:56:55.519557 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 06:56:55.523212 Total UI for P1: 0, mck2ui 16
8384 06:56:55.526448 best dqsien dly found for B0: ( 1, 9, 10)
8385 06:56:55.527019 Total UI for P1: 0, mck2ui 16
8386 06:56:55.533277 best dqsien dly found for B1: ( 1, 9, 10)
8387 06:56:55.536265 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8388 06:56:55.539736 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8389 06:56:55.540321
8390 06:56:55.543600 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8391 06:56:55.546755 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8392 06:56:55.549706 [Gating] SW calibration Done
8393 06:56:55.550253 ==
8394 06:56:55.552881 Dram Type= 6, Freq= 0, CH_1, rank 0
8395 06:56:55.556669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8396 06:56:55.557227 ==
8397 06:56:55.559359 RX Vref Scan: 0
8398 06:56:55.559966
8399 06:56:55.560384 RX Vref 0 -> 0, step: 1
8400 06:56:55.563036
8401 06:56:55.563484 RX Delay 0 -> 252, step: 8
8402 06:56:55.566251 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8403 06:56:55.573101 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8404 06:56:55.576139 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8405 06:56:55.579390 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8406 06:56:55.583115 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8407 06:56:55.586151 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8408 06:56:55.592749 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8409 06:56:55.596461 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8410 06:56:55.599525 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8411 06:56:55.602820 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8412 06:56:55.606017 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8413 06:56:55.612437 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8414 06:56:55.616316 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8415 06:56:55.619356 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8416 06:56:55.622236 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8417 06:56:55.629146 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8418 06:56:55.629699 ==
8419 06:56:55.632678 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 06:56:55.635610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 06:56:55.636097 ==
8422 06:56:55.636618 DQS Delay:
8423 06:56:55.638829 DQS0 = 0, DQS1 = 0
8424 06:56:55.639294 DQM Delay:
8425 06:56:55.642735 DQM0 = 135, DQM1 = 133
8426 06:56:55.643303 DQ Delay:
8427 06:56:55.645991 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8428 06:56:55.649012 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8429 06:56:55.652251 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8430 06:56:55.655666 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8431 06:56:55.656135
8432 06:56:55.656645
8433 06:56:55.658868 ==
8434 06:56:55.659336 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 06:56:55.665676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 06:56:55.666187 ==
8437 06:56:55.666669
8438 06:56:55.667117
8439 06:56:55.667552 TX Vref Scan disable
8440 06:56:55.669304 == TX Byte 0 ==
8441 06:56:55.672718 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8442 06:56:55.676455 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8443 06:56:55.679532 == TX Byte 1 ==
8444 06:56:55.683126 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8445 06:56:55.686310 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8446 06:56:55.689457 ==
8447 06:56:55.692574 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 06:56:55.695907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 06:56:55.696545 ==
8450 06:56:55.709563
8451 06:56:55.712755 TX Vref early break, caculate TX vref
8452 06:56:55.716227 TX Vref=16, minBit 9, minWin=22, winSum=374
8453 06:56:55.719627 TX Vref=18, minBit 1, minWin=23, winSum=384
8454 06:56:55.722447 TX Vref=20, minBit 1, minWin=23, winSum=394
8455 06:56:55.725976 TX Vref=22, minBit 9, minWin=24, winSum=409
8456 06:56:55.729402 TX Vref=24, minBit 0, minWin=25, winSum=416
8457 06:56:55.735872 TX Vref=26, minBit 1, minWin=25, winSum=424
8458 06:56:55.739682 TX Vref=28, minBit 0, minWin=24, winSum=424
8459 06:56:55.742814 TX Vref=30, minBit 0, minWin=24, winSum=416
8460 06:56:55.745905 TX Vref=32, minBit 6, minWin=24, winSum=413
8461 06:56:55.749118 TX Vref=34, minBit 2, minWin=24, winSum=402
8462 06:56:55.752648 TX Vref=36, minBit 0, minWin=23, winSum=387
8463 06:56:55.759510 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 26
8464 06:56:55.760092
8465 06:56:55.762412 Final TX Range 0 Vref 26
8466 06:56:55.762869
8467 06:56:55.763261 ==
8468 06:56:55.765650 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 06:56:55.768890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 06:56:55.769350 ==
8471 06:56:55.769709
8472 06:56:55.770044
8473 06:56:55.772801 TX Vref Scan disable
8474 06:56:55.779386 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8475 06:56:55.779948 == TX Byte 0 ==
8476 06:56:55.782320 u2DelayCellOfst[0]=16 cells (5 PI)
8477 06:56:55.785578 u2DelayCellOfst[1]=10 cells (3 PI)
8478 06:56:55.789350 u2DelayCellOfst[2]=0 cells (0 PI)
8479 06:56:55.792676 u2DelayCellOfst[3]=6 cells (2 PI)
8480 06:56:55.795696 u2DelayCellOfst[4]=6 cells (2 PI)
8481 06:56:55.799138 u2DelayCellOfst[5]=16 cells (5 PI)
8482 06:56:55.802527 u2DelayCellOfst[6]=16 cells (5 PI)
8483 06:56:55.806090 u2DelayCellOfst[7]=3 cells (1 PI)
8484 06:56:55.809045 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8485 06:56:55.812520 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8486 06:56:55.815588 == TX Byte 1 ==
8487 06:56:55.819439 u2DelayCellOfst[8]=0 cells (0 PI)
8488 06:56:55.820015 u2DelayCellOfst[9]=3 cells (1 PI)
8489 06:56:55.821913 u2DelayCellOfst[10]=13 cells (4 PI)
8490 06:56:55.825769 u2DelayCellOfst[11]=6 cells (2 PI)
8491 06:56:55.829098 u2DelayCellOfst[12]=16 cells (5 PI)
8492 06:56:55.832517 u2DelayCellOfst[13]=16 cells (5 PI)
8493 06:56:55.835560 u2DelayCellOfst[14]=16 cells (5 PI)
8494 06:56:55.838807 u2DelayCellOfst[15]=16 cells (5 PI)
8495 06:56:55.842756 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8496 06:56:55.848988 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8497 06:56:55.849471 DramC Write-DBI on
8498 06:56:55.849946 ==
8499 06:56:55.851881 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 06:56:55.858909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 06:56:55.859464 ==
8502 06:56:55.859945
8503 06:56:55.860523
8504 06:56:55.860966 TX Vref Scan disable
8505 06:56:55.862163 == TX Byte 0 ==
8506 06:56:55.865788 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8507 06:56:55.869566 == TX Byte 1 ==
8508 06:56:55.872187 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8509 06:56:55.875463 DramC Write-DBI off
8510 06:56:55.875956
8511 06:56:55.876533 [DATLAT]
8512 06:56:55.876988 Freq=1600, CH1 RK0
8513 06:56:55.877423
8514 06:56:55.879109 DATLAT Default: 0xf
8515 06:56:55.879572 0, 0xFFFF, sum = 0
8516 06:56:55.882122 1, 0xFFFF, sum = 0
8517 06:56:55.885571 2, 0xFFFF, sum = 0
8518 06:56:55.886154 3, 0xFFFF, sum = 0
8519 06:56:55.888647 4, 0xFFFF, sum = 0
8520 06:56:55.889075 5, 0xFFFF, sum = 0
8521 06:56:55.892740 6, 0xFFFF, sum = 0
8522 06:56:55.893168 7, 0xFFFF, sum = 0
8523 06:56:55.895384 8, 0xFFFF, sum = 0
8524 06:56:55.895813 9, 0xFFFF, sum = 0
8525 06:56:55.899451 10, 0xFFFF, sum = 0
8526 06:56:55.900009 11, 0xFFFF, sum = 0
8527 06:56:55.902251 12, 0xFFFF, sum = 0
8528 06:56:55.902678 13, 0xFFFF, sum = 0
8529 06:56:55.905290 14, 0x0, sum = 1
8530 06:56:55.905724 15, 0x0, sum = 2
8531 06:56:55.909523 16, 0x0, sum = 3
8532 06:56:55.910064 17, 0x0, sum = 4
8533 06:56:55.912672 best_step = 15
8534 06:56:55.913197
8535 06:56:55.913635 ==
8536 06:56:55.915428 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 06:56:55.918915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 06:56:55.919468 ==
8539 06:56:55.921990 RX Vref Scan: 1
8540 06:56:55.922480
8541 06:56:55.922912 Set Vref Range= 24 -> 127
8542 06:56:55.923322
8543 06:56:55.925321 RX Vref 24 -> 127, step: 1
8544 06:56:55.925745
8545 06:56:55.928420 RX Delay 27 -> 252, step: 4
8546 06:56:55.928976
8547 06:56:55.932236 Set Vref, RX VrefLevel [Byte0]: 24
8548 06:56:55.935457 [Byte1]: 24
8549 06:56:55.935965
8550 06:56:55.938545 Set Vref, RX VrefLevel [Byte0]: 25
8551 06:56:55.941693 [Byte1]: 25
8552 06:56:55.944937
8553 06:56:55.945488 Set Vref, RX VrefLevel [Byte0]: 26
8554 06:56:55.948075 [Byte1]: 26
8555 06:56:55.952832
8556 06:56:55.953239 Set Vref, RX VrefLevel [Byte0]: 27
8557 06:56:55.956047 [Byte1]: 27
8558 06:56:55.959817
8559 06:56:55.960224 Set Vref, RX VrefLevel [Byte0]: 28
8560 06:56:55.963045 [Byte1]: 28
8561 06:56:55.967440
8562 06:56:55.967848 Set Vref, RX VrefLevel [Byte0]: 29
8563 06:56:55.970961 [Byte1]: 29
8564 06:56:55.975242
8565 06:56:55.975707 Set Vref, RX VrefLevel [Byte0]: 30
8566 06:56:55.978236 [Byte1]: 30
8567 06:56:55.982702
8568 06:56:55.983122 Set Vref, RX VrefLevel [Byte0]: 31
8569 06:56:55.986663 [Byte1]: 31
8570 06:56:55.990676
8571 06:56:55.991188 Set Vref, RX VrefLevel [Byte0]: 32
8572 06:56:55.993476 [Byte1]: 32
8573 06:56:55.998004
8574 06:56:55.998513 Set Vref, RX VrefLevel [Byte0]: 33
8575 06:56:56.000834 [Byte1]: 33
8576 06:56:56.005381
8577 06:56:56.005790 Set Vref, RX VrefLevel [Byte0]: 34
8578 06:56:56.008961 [Byte1]: 34
8579 06:56:56.013154
8580 06:56:56.013705 Set Vref, RX VrefLevel [Byte0]: 35
8581 06:56:56.016444 [Byte1]: 35
8582 06:56:56.020466
8583 06:56:56.021024 Set Vref, RX VrefLevel [Byte0]: 36
8584 06:56:56.023580 [Byte1]: 36
8585 06:56:56.027915
8586 06:56:56.028722 Set Vref, RX VrefLevel [Byte0]: 37
8587 06:56:56.031428 [Byte1]: 37
8588 06:56:56.035726
8589 06:56:56.036247 Set Vref, RX VrefLevel [Byte0]: 38
8590 06:56:56.039206 [Byte1]: 38
8591 06:56:56.043096
8592 06:56:56.043676 Set Vref, RX VrefLevel [Byte0]: 39
8593 06:56:56.046848 [Byte1]: 39
8594 06:56:56.050560
8595 06:56:56.051195 Set Vref, RX VrefLevel [Byte0]: 40
8596 06:56:56.053859 [Byte1]: 40
8597 06:56:56.057844
8598 06:56:56.058304 Set Vref, RX VrefLevel [Byte0]: 41
8599 06:56:56.061881 [Byte1]: 41
8600 06:56:56.065534
8601 06:56:56.066076 Set Vref, RX VrefLevel [Byte0]: 42
8602 06:56:56.068710 [Byte1]: 42
8603 06:56:56.073175
8604 06:56:56.073781 Set Vref, RX VrefLevel [Byte0]: 43
8605 06:56:56.076394 [Byte1]: 43
8606 06:56:56.080933
8607 06:56:56.081492 Set Vref, RX VrefLevel [Byte0]: 44
8608 06:56:56.083645 [Byte1]: 44
8609 06:56:56.088502
8610 06:56:56.088963 Set Vref, RX VrefLevel [Byte0]: 45
8611 06:56:56.092133 [Byte1]: 45
8612 06:56:56.095978
8613 06:56:56.096597 Set Vref, RX VrefLevel [Byte0]: 46
8614 06:56:56.099371 [Byte1]: 46
8615 06:56:56.103163
8616 06:56:56.103747 Set Vref, RX VrefLevel [Byte0]: 47
8617 06:56:56.106849 [Byte1]: 47
8618 06:56:56.110719
8619 06:56:56.111193 Set Vref, RX VrefLevel [Byte0]: 48
8620 06:56:56.114293 [Byte1]: 48
8621 06:56:56.118771
8622 06:56:56.119331 Set Vref, RX VrefLevel [Byte0]: 49
8623 06:56:56.121832 [Byte1]: 49
8624 06:56:56.125838
8625 06:56:56.126298 Set Vref, RX VrefLevel [Byte0]: 50
8626 06:56:56.129358 [Byte1]: 50
8627 06:56:56.133590
8628 06:56:56.134168 Set Vref, RX VrefLevel [Byte0]: 51
8629 06:56:56.136584 [Byte1]: 51
8630 06:56:56.140876
8631 06:56:56.141497 Set Vref, RX VrefLevel [Byte0]: 52
8632 06:56:56.144506 [Byte1]: 52
8633 06:56:56.148895
8634 06:56:56.149463 Set Vref, RX VrefLevel [Byte0]: 53
8635 06:56:56.151893 [Byte1]: 53
8636 06:56:56.155902
8637 06:56:56.156627 Set Vref, RX VrefLevel [Byte0]: 54
8638 06:56:56.159391 [Byte1]: 54
8639 06:56:56.163648
8640 06:56:56.164122 Set Vref, RX VrefLevel [Byte0]: 55
8641 06:56:56.166584 [Byte1]: 55
8642 06:56:56.171286
8643 06:56:56.171759 Set Vref, RX VrefLevel [Byte0]: 56
8644 06:56:56.174494 [Byte1]: 56
8645 06:56:56.178743
8646 06:56:56.179302 Set Vref, RX VrefLevel [Byte0]: 57
8647 06:56:56.181941 [Byte1]: 57
8648 06:56:56.186412
8649 06:56:56.186867 Set Vref, RX VrefLevel [Byte0]: 58
8650 06:56:56.189668 [Byte1]: 58
8651 06:56:56.194000
8652 06:56:56.194575 Set Vref, RX VrefLevel [Byte0]: 59
8653 06:56:56.197077 [Byte1]: 59
8654 06:56:56.201317
8655 06:56:56.201879 Set Vref, RX VrefLevel [Byte0]: 60
8656 06:56:56.204149 [Byte1]: 60
8657 06:56:56.209010
8658 06:56:56.209568 Set Vref, RX VrefLevel [Byte0]: 61
8659 06:56:56.212098 [Byte1]: 61
8660 06:56:56.216250
8661 06:56:56.216750 Set Vref, RX VrefLevel [Byte0]: 62
8662 06:56:56.219673 [Byte1]: 62
8663 06:56:56.223861
8664 06:56:56.224479 Set Vref, RX VrefLevel [Byte0]: 63
8665 06:56:56.227082 [Byte1]: 63
8666 06:56:56.231619
8667 06:56:56.232182 Set Vref, RX VrefLevel [Byte0]: 64
8668 06:56:56.234543 [Byte1]: 64
8669 06:56:56.239234
8670 06:56:56.239803 Set Vref, RX VrefLevel [Byte0]: 65
8671 06:56:56.242266 [Byte1]: 65
8672 06:56:56.246549
8673 06:56:56.247014 Set Vref, RX VrefLevel [Byte0]: 66
8674 06:56:56.250265 [Byte1]: 66
8675 06:56:56.253975
8676 06:56:56.254537 Set Vref, RX VrefLevel [Byte0]: 67
8677 06:56:56.257004 [Byte1]: 67
8678 06:56:56.261183
8679 06:56:56.261650 Set Vref, RX VrefLevel [Byte0]: 68
8680 06:56:56.265045 [Byte1]: 68
8681 06:56:56.269234
8682 06:56:56.269695 Set Vref, RX VrefLevel [Byte0]: 69
8683 06:56:56.272333 [Byte1]: 69
8684 06:56:56.276924
8685 06:56:56.277482 Set Vref, RX VrefLevel [Byte0]: 70
8686 06:56:56.279645 [Byte1]: 70
8687 06:56:56.284009
8688 06:56:56.284620 Set Vref, RX VrefLevel [Byte0]: 71
8689 06:56:56.287522 [Byte1]: 71
8690 06:56:56.291779
8691 06:56:56.292397 Set Vref, RX VrefLevel [Byte0]: 72
8692 06:56:56.294971 [Byte1]: 72
8693 06:56:56.299201
8694 06:56:56.299660 Set Vref, RX VrefLevel [Byte0]: 73
8695 06:56:56.302546 [Byte1]: 73
8696 06:56:56.306513
8697 06:56:56.306990 Set Vref, RX VrefLevel [Byte0]: 74
8698 06:56:56.310159 [Byte1]: 74
8699 06:56:56.314312
8700 06:56:56.314773 Set Vref, RX VrefLevel [Byte0]: 75
8701 06:56:56.317475 [Byte1]: 75
8702 06:56:56.322155
8703 06:56:56.322718 Final RX Vref Byte 0 = 56 to rank0
8704 06:56:56.324935 Final RX Vref Byte 1 = 55 to rank0
8705 06:56:56.328342 Final RX Vref Byte 0 = 56 to rank1
8706 06:56:56.331980 Final RX Vref Byte 1 = 55 to rank1==
8707 06:56:56.335172 Dram Type= 6, Freq= 0, CH_1, rank 0
8708 06:56:56.342000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8709 06:56:56.342564 ==
8710 06:56:56.342930 DQS Delay:
8711 06:56:56.343267 DQS0 = 0, DQS1 = 0
8712 06:56:56.344936 DQM Delay:
8713 06:56:56.345392 DQM0 = 134, DQM1 = 131
8714 06:56:56.348403 DQ Delay:
8715 06:56:56.351685 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8716 06:56:56.355199 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8717 06:56:56.358327 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8718 06:56:56.361645 DQ12 =140, DQ13 =138, DQ14 =140, DQ15 =140
8719 06:56:56.362121
8720 06:56:56.362484
8721 06:56:56.362819
8722 06:56:56.364912 [DramC_TX_OE_Calibration] TA2
8723 06:56:56.368082 Original DQ_B0 (3 6) =30, OEN = 27
8724 06:56:56.371499 Original DQ_B1 (3 6) =30, OEN = 27
8725 06:56:56.374845 24, 0x0, End_B0=24 End_B1=24
8726 06:56:56.375411 25, 0x0, End_B0=25 End_B1=25
8727 06:56:56.377880 26, 0x0, End_B0=26 End_B1=26
8728 06:56:56.381923 27, 0x0, End_B0=27 End_B1=27
8729 06:56:56.384993 28, 0x0, End_B0=28 End_B1=28
8730 06:56:56.385465 29, 0x0, End_B0=29 End_B1=29
8731 06:56:56.388142 30, 0x0, End_B0=30 End_B1=30
8732 06:56:56.391625 31, 0x4141, End_B0=30 End_B1=30
8733 06:56:56.394757 Byte0 end_step=30 best_step=27
8734 06:56:56.398146 Byte1 end_step=30 best_step=27
8735 06:56:56.401227 Byte0 TX OE(2T, 0.5T) = (3, 3)
8736 06:56:56.404980 Byte1 TX OE(2T, 0.5T) = (3, 3)
8737 06:56:56.405676
8738 06:56:56.406050
8739 06:56:56.411231 [DQSOSCAuto] RK0, (LSB)MR18= 0x1422, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8740 06:56:56.415111 CH1 RK0: MR19=303, MR18=1422
8741 06:56:56.421403 CH1_RK0: MR19=0x303, MR18=0x1422, DQSOSC=392, MR23=63, INC=24, DEC=16
8742 06:56:56.421962
8743 06:56:56.424635 ----->DramcWriteLeveling(PI) begin...
8744 06:56:56.425119 ==
8745 06:56:56.428383 Dram Type= 6, Freq= 0, CH_1, rank 1
8746 06:56:56.431408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8747 06:56:56.431963 ==
8748 06:56:56.435117 Write leveling (Byte 0): 25 => 25
8749 06:56:56.438067 Write leveling (Byte 1): 28 => 28
8750 06:56:56.441657 DramcWriteLeveling(PI) end<-----
8751 06:56:56.442116
8752 06:56:56.442628 ==
8753 06:56:56.444268 Dram Type= 6, Freq= 0, CH_1, rank 1
8754 06:56:56.447947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 06:56:56.448568 ==
8756 06:56:56.451760 [Gating] SW mode calibration
8757 06:56:56.457698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8758 06:56:56.464452 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8759 06:56:56.468009 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 06:56:56.471615 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 06:56:56.478003 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
8762 06:56:56.481285 1 4 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8763 06:56:56.484383 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 06:56:56.491071 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 06:56:56.494848 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 06:56:56.498037 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 06:56:56.504773 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 06:56:56.507558 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8769 06:56:56.510899 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8770 06:56:56.517260 1 5 12 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
8771 06:56:56.521043 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 06:56:56.524518 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 06:56:56.531564 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 06:56:56.534257 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 06:56:56.537612 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 06:56:56.544564 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 06:56:56.547560 1 6 8 | B1->B0 | 3e3e 2828 | 0 0 | (0 0) (0 0)
8778 06:56:56.551121 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8779 06:56:56.557348 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 06:56:56.561146 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 06:56:56.563999 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 06:56:56.570469 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 06:56:56.573841 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 06:56:56.577447 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8785 06:56:56.584061 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8786 06:56:56.587148 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8787 06:56:56.590341 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 06:56:56.593926 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 06:56:56.600403 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 06:56:56.603620 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 06:56:56.607173 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 06:56:56.613775 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 06:56:56.617361 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 06:56:56.620491 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 06:56:56.627498 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 06:56:56.630979 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 06:56:56.634086 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 06:56:56.640779 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 06:56:56.643934 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 06:56:56.647336 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8801 06:56:56.654027 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8802 06:56:56.657092 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8803 06:56:56.660455 Total UI for P1: 0, mck2ui 16
8804 06:56:56.664268 best dqsien dly found for B1: ( 1, 9, 6)
8805 06:56:56.667400 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 06:56:56.670689 Total UI for P1: 0, mck2ui 16
8807 06:56:56.674410 best dqsien dly found for B0: ( 1, 9, 12)
8808 06:56:56.677391 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8809 06:56:56.680751 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8810 06:56:56.681301
8811 06:56:56.686892 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8812 06:56:56.690828 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8813 06:56:56.691380 [Gating] SW calibration Done
8814 06:56:56.693566 ==
8815 06:56:56.697038 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 06:56:56.700378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 06:56:56.700929 ==
8818 06:56:56.701296 RX Vref Scan: 0
8819 06:56:56.701635
8820 06:56:56.703592 RX Vref 0 -> 0, step: 1
8821 06:56:56.704180
8822 06:56:56.706897 RX Delay 0 -> 252, step: 8
8823 06:56:56.710499 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8824 06:56:56.713674 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8825 06:56:56.716878 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8826 06:56:56.723567 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8827 06:56:56.726757 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8828 06:56:56.730368 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8829 06:56:56.733501 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8830 06:56:56.736878 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8831 06:56:56.743712 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8832 06:56:56.746710 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8833 06:56:56.750753 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8834 06:56:56.753627 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8835 06:56:56.756807 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8836 06:56:56.763356 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8837 06:56:56.766518 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8838 06:56:56.770602 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8839 06:56:56.771155 ==
8840 06:56:56.773574 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 06:56:56.776945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 06:56:56.779862 ==
8843 06:56:56.780481 DQS Delay:
8844 06:56:56.781045 DQS0 = 0, DQS1 = 0
8845 06:56:56.783546 DQM Delay:
8846 06:56:56.784004 DQM0 = 136, DQM1 = 133
8847 06:56:56.786850 DQ Delay:
8848 06:56:56.790108 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8849 06:56:56.793413 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8850 06:56:56.796369 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8851 06:56:56.799793 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8852 06:56:56.800407
8853 06:56:56.800790
8854 06:56:56.801130 ==
8855 06:56:56.803569 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 06:56:56.806774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 06:56:56.807343 ==
8858 06:56:56.807957
8859 06:56:56.808392
8860 06:56:56.809744 TX Vref Scan disable
8861 06:56:56.813243 == TX Byte 0 ==
8862 06:56:56.816377 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8863 06:56:56.820146 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8864 06:56:56.823432 == TX Byte 1 ==
8865 06:56:56.826263 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8866 06:56:56.830058 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8867 06:56:56.830519 ==
8868 06:56:56.833225 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 06:56:56.839750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 06:56:56.840215 ==
8871 06:56:56.852095
8872 06:56:56.855168 TX Vref early break, caculate TX vref
8873 06:56:56.858486 TX Vref=16, minBit 0, minWin=23, winSum=383
8874 06:56:56.861681 TX Vref=18, minBit 0, minWin=24, winSum=394
8875 06:56:56.865230 TX Vref=20, minBit 0, minWin=24, winSum=401
8876 06:56:56.868346 TX Vref=22, minBit 0, minWin=25, winSum=413
8877 06:56:56.871776 TX Vref=24, minBit 0, minWin=25, winSum=419
8878 06:56:56.878937 TX Vref=26, minBit 0, minWin=25, winSum=424
8879 06:56:56.882149 TX Vref=28, minBit 1, minWin=25, winSum=426
8880 06:56:56.885223 TX Vref=30, minBit 1, minWin=25, winSum=418
8881 06:56:56.888887 TX Vref=32, minBit 0, minWin=25, winSum=413
8882 06:56:56.892065 TX Vref=34, minBit 0, minWin=24, winSum=406
8883 06:56:56.895205 TX Vref=36, minBit 1, minWin=23, winSum=397
8884 06:56:56.902460 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 28
8885 06:56:56.903035
8886 06:56:56.905340 Final TX Range 0 Vref 28
8887 06:56:56.905802
8888 06:56:56.906165 ==
8889 06:56:56.908408 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 06:56:56.912098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 06:56:56.912706 ==
8892 06:56:56.913182
8893 06:56:56.913533
8894 06:56:56.914966 TX Vref Scan disable
8895 06:56:56.921645 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8896 06:56:56.922180 == TX Byte 0 ==
8897 06:56:56.925244 u2DelayCellOfst[0]=16 cells (5 PI)
8898 06:56:56.928771 u2DelayCellOfst[1]=13 cells (4 PI)
8899 06:56:56.932010 u2DelayCellOfst[2]=0 cells (0 PI)
8900 06:56:56.935126 u2DelayCellOfst[3]=6 cells (2 PI)
8901 06:56:56.938798 u2DelayCellOfst[4]=10 cells (3 PI)
8902 06:56:56.942154 u2DelayCellOfst[5]=16 cells (5 PI)
8903 06:56:56.945437 u2DelayCellOfst[6]=16 cells (5 PI)
8904 06:56:56.948755 u2DelayCellOfst[7]=6 cells (2 PI)
8905 06:56:56.952054 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8906 06:56:56.955138 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8907 06:56:56.958802 == TX Byte 1 ==
8908 06:56:56.961986 u2DelayCellOfst[8]=0 cells (0 PI)
8909 06:56:56.962449 u2DelayCellOfst[9]=3 cells (1 PI)
8910 06:56:56.965025 u2DelayCellOfst[10]=10 cells (3 PI)
8911 06:56:56.968554 u2DelayCellOfst[11]=6 cells (2 PI)
8912 06:56:56.971409 u2DelayCellOfst[12]=13 cells (4 PI)
8913 06:56:56.975436 u2DelayCellOfst[13]=13 cells (4 PI)
8914 06:56:56.978661 u2DelayCellOfst[14]=16 cells (5 PI)
8915 06:56:56.981486 u2DelayCellOfst[15]=16 cells (5 PI)
8916 06:56:56.984662 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8917 06:56:56.991709 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8918 06:56:56.992267 DramC Write-DBI on
8919 06:56:56.992796 ==
8920 06:56:56.994626 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 06:56:57.001433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 06:56:57.002043 ==
8923 06:56:57.002557
8924 06:56:57.003044
8925 06:56:57.003493 TX Vref Scan disable
8926 06:56:57.005038 == TX Byte 0 ==
8927 06:56:57.008456 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8928 06:56:57.012043 == TX Byte 1 ==
8929 06:56:57.015335 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8930 06:56:57.018883 DramC Write-DBI off
8931 06:56:57.019861
8932 06:56:57.020599 [DATLAT]
8933 06:56:57.020939 Freq=1600, CH1 RK1
8934 06:56:57.021263
8935 06:56:57.022390 DATLAT Default: 0xf
8936 06:56:57.023157 0, 0xFFFF, sum = 0
8937 06:56:57.025017 1, 0xFFFF, sum = 0
8938 06:56:57.028846 2, 0xFFFF, sum = 0
8939 06:56:57.029268 3, 0xFFFF, sum = 0
8940 06:56:57.031782 4, 0xFFFF, sum = 0
8941 06:56:57.032211 5, 0xFFFF, sum = 0
8942 06:56:57.034881 6, 0xFFFF, sum = 0
8943 06:56:57.035305 7, 0xFFFF, sum = 0
8944 06:56:57.038274 8, 0xFFFF, sum = 0
8945 06:56:57.038717 9, 0xFFFF, sum = 0
8946 06:56:57.041728 10, 0xFFFF, sum = 0
8947 06:56:57.042144 11, 0xFFFF, sum = 0
8948 06:56:57.044937 12, 0xFFFF, sum = 0
8949 06:56:57.045351 13, 0xFFFF, sum = 0
8950 06:56:57.048849 14, 0x0, sum = 1
8951 06:56:57.049262 15, 0x0, sum = 2
8952 06:56:57.052048 16, 0x0, sum = 3
8953 06:56:57.052513 17, 0x0, sum = 4
8954 06:56:57.055155 best_step = 15
8955 06:56:57.055585
8956 06:56:57.055912 ==
8957 06:56:57.058272 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 06:56:57.061719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 06:56:57.062130 ==
8960 06:56:57.062456 RX Vref Scan: 0
8961 06:56:57.064939
8962 06:56:57.065346 RX Vref 0 -> 0, step: 1
8963 06:56:57.065719
8964 06:56:57.068162 RX Delay 19 -> 252, step: 4
8965 06:56:57.072227 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8966 06:56:57.078830 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8967 06:56:57.082116 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8968 06:56:57.085003 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8969 06:56:57.088362 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8970 06:56:57.092177 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8971 06:56:57.095025 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8972 06:56:57.101596 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8973 06:56:57.104931 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8974 06:56:57.108807 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8975 06:56:57.111778 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8976 06:56:57.115150 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8977 06:56:57.121891 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8978 06:56:57.125019 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
8979 06:56:57.128082 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8980 06:56:57.131862 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8981 06:56:57.132426 ==
8982 06:56:57.135037 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 06:56:57.141583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 06:56:57.142095 ==
8985 06:56:57.142432 DQS Delay:
8986 06:56:57.144869 DQS0 = 0, DQS1 = 0
8987 06:56:57.145285 DQM Delay:
8988 06:56:57.148425 DQM0 = 134, DQM1 = 130
8989 06:56:57.148959 DQ Delay:
8990 06:56:57.151401 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8991 06:56:57.154522 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8992 06:56:57.158379 DQ8 =118, DQ9 =120, DQ10 =132, DQ11 =124
8993 06:56:57.161492 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =138
8994 06:56:57.161911
8995 06:56:57.162240
8996 06:56:57.162546
8997 06:56:57.164820 [DramC_TX_OE_Calibration] TA2
8998 06:56:57.167982 Original DQ_B0 (3 6) =30, OEN = 27
8999 06:56:57.171401 Original DQ_B1 (3 6) =30, OEN = 27
9000 06:56:57.175162 24, 0x0, End_B0=24 End_B1=24
9001 06:56:57.175580 25, 0x0, End_B0=25 End_B1=25
9002 06:56:57.178626 26, 0x0, End_B0=26 End_B1=26
9003 06:56:57.181798 27, 0x0, End_B0=27 End_B1=27
9004 06:56:57.185074 28, 0x0, End_B0=28 End_B1=28
9005 06:56:57.188121 29, 0x0, End_B0=29 End_B1=29
9006 06:56:57.188625 30, 0x0, End_B0=30 End_B1=30
9007 06:56:57.191627 31, 0x4141, End_B0=30 End_B1=30
9008 06:56:57.194878 Byte0 end_step=30 best_step=27
9009 06:56:57.198104 Byte1 end_step=30 best_step=27
9010 06:56:57.201109 Byte0 TX OE(2T, 0.5T) = (3, 3)
9011 06:56:57.204695 Byte1 TX OE(2T, 0.5T) = (3, 3)
9012 06:56:57.205305
9013 06:56:57.205685
9014 06:56:57.211572 [DQSOSCAuto] RK1, (LSB)MR18= 0x2106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9015 06:56:57.214654 CH1 RK1: MR19=303, MR18=2106
9016 06:56:57.221000 CH1_RK1: MR19=0x303, MR18=0x2106, DQSOSC=393, MR23=63, INC=23, DEC=15
9017 06:56:57.224843 [RxdqsGatingPostProcess] freq 1600
9018 06:56:57.228066 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9019 06:56:57.231576 best DQS0 dly(2T, 0.5T) = (1, 1)
9020 06:56:57.234770 best DQS1 dly(2T, 0.5T) = (1, 1)
9021 06:56:57.238587 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9022 06:56:57.241352 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9023 06:56:57.244438 best DQS0 dly(2T, 0.5T) = (1, 1)
9024 06:56:57.248504 best DQS1 dly(2T, 0.5T) = (1, 1)
9025 06:56:57.251715 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9026 06:56:57.254991 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9027 06:56:57.257667 Pre-setting of DQS Precalculation
9028 06:56:57.261356 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9029 06:56:57.267989 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9030 06:56:57.277785 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9031 06:56:57.278251
9032 06:56:57.278613
9033 06:56:57.278948 [Calibration Summary] 3200 Mbps
9034 06:56:57.281168 CH 0, Rank 0
9035 06:56:57.281630 SW Impedance : PASS
9036 06:56:57.284802 DUTY Scan : NO K
9037 06:56:57.287663 ZQ Calibration : PASS
9038 06:56:57.288121 Jitter Meter : NO K
9039 06:56:57.291029 CBT Training : PASS
9040 06:56:57.294566 Write leveling : PASS
9041 06:56:57.295118 RX DQS gating : PASS
9042 06:56:57.297393 RX DQ/DQS(RDDQC) : PASS
9043 06:56:57.301300 TX DQ/DQS : PASS
9044 06:56:57.301764 RX DATLAT : PASS
9045 06:56:57.304479 RX DQ/DQS(Engine): PASS
9046 06:56:57.308044 TX OE : PASS
9047 06:56:57.308681 All Pass.
9048 06:56:57.309054
9049 06:56:57.309441 CH 0, Rank 1
9050 06:56:57.310902 SW Impedance : PASS
9051 06:56:57.314960 DUTY Scan : NO K
9052 06:56:57.315510 ZQ Calibration : PASS
9053 06:56:57.318245 Jitter Meter : NO K
9054 06:56:57.318812 CBT Training : PASS
9055 06:56:57.321330 Write leveling : PASS
9056 06:56:57.324983 RX DQS gating : PASS
9057 06:56:57.325446 RX DQ/DQS(RDDQC) : PASS
9058 06:56:57.328003 TX DQ/DQS : PASS
9059 06:56:57.331580 RX DATLAT : PASS
9060 06:56:57.332200 RX DQ/DQS(Engine): PASS
9061 06:56:57.334335 TX OE : PASS
9062 06:56:57.334902 All Pass.
9063 06:56:57.335277
9064 06:56:57.337760 CH 1, Rank 0
9065 06:56:57.338225 SW Impedance : PASS
9066 06:56:57.341080 DUTY Scan : NO K
9067 06:56:57.344593 ZQ Calibration : PASS
9068 06:56:57.345143 Jitter Meter : NO K
9069 06:56:57.347755 CBT Training : PASS
9070 06:56:57.351524 Write leveling : PASS
9071 06:56:57.352208 RX DQS gating : PASS
9072 06:56:57.354431 RX DQ/DQS(RDDQC) : PASS
9073 06:56:57.358216 TX DQ/DQS : PASS
9074 06:56:57.358771 RX DATLAT : PASS
9075 06:56:57.361151 RX DQ/DQS(Engine): PASS
9076 06:56:57.361614 TX OE : PASS
9077 06:56:57.364267 All Pass.
9078 06:56:57.364758
9079 06:56:57.365122 CH 1, Rank 1
9080 06:56:57.367547 SW Impedance : PASS
9081 06:56:57.371534 DUTY Scan : NO K
9082 06:56:57.372090 ZQ Calibration : PASS
9083 06:56:57.374509 Jitter Meter : NO K
9084 06:56:57.374972 CBT Training : PASS
9085 06:56:57.377632 Write leveling : PASS
9086 06:56:57.380696 RX DQS gating : PASS
9087 06:56:57.381157 RX DQ/DQS(RDDQC) : PASS
9088 06:56:57.384388 TX DQ/DQS : PASS
9089 06:56:57.387547 RX DATLAT : PASS
9090 06:56:57.388010 RX DQ/DQS(Engine): PASS
9091 06:56:57.391149 TX OE : PASS
9092 06:56:57.391612 All Pass.
9093 06:56:57.391976
9094 06:56:57.394519 DramC Write-DBI on
9095 06:56:57.397218 PER_BANK_REFRESH: Hybrid Mode
9096 06:56:57.397678 TX_TRACKING: ON
9097 06:56:57.407392 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9098 06:56:57.414122 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9099 06:56:57.420602 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9100 06:56:57.424329 [FAST_K] Save calibration result to emmc
9101 06:56:57.427403 sync common calibartion params.
9102 06:56:57.430466 sync cbt_mode0:1, 1:1
9103 06:56:57.434030 dram_init: ddr_geometry: 2
9104 06:56:57.434585 dram_init: ddr_geometry: 2
9105 06:56:57.437384 dram_init: ddr_geometry: 2
9106 06:56:57.441155 0:dram_rank_size:100000000
9107 06:56:57.444191 1:dram_rank_size:100000000
9108 06:56:57.447192 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9109 06:56:57.450896 DFS_SHUFFLE_HW_MODE: ON
9110 06:56:57.454037 dramc_set_vcore_voltage set vcore to 725000
9111 06:56:57.457796 Read voltage for 1600, 0
9112 06:56:57.458344 Vio18 = 0
9113 06:56:57.458836 Vcore = 725000
9114 06:56:57.460663 Vdram = 0
9115 06:56:57.461140 Vddq = 0
9116 06:56:57.461506 Vmddr = 0
9117 06:56:57.463724 switch to 3200 Mbps bootup
9118 06:56:57.467108 [DramcRunTimeConfig]
9119 06:56:57.467618 PHYPLL
9120 06:56:57.468001 DPM_CONTROL_AFTERK: ON
9121 06:56:57.470310 PER_BANK_REFRESH: ON
9122 06:56:57.473794 REFRESH_OVERHEAD_REDUCTION: ON
9123 06:56:57.474345 CMD_PICG_NEW_MODE: OFF
9124 06:56:57.477400 XRTWTW_NEW_MODE: ON
9125 06:56:57.480818 XRTRTR_NEW_MODE: ON
9126 06:56:57.481370 TX_TRACKING: ON
9127 06:56:57.483833 RDSEL_TRACKING: OFF
9128 06:56:57.484319 DQS Precalculation for DVFS: ON
9129 06:56:57.487155 RX_TRACKING: OFF
9130 06:56:57.487613 HW_GATING DBG: ON
9131 06:56:57.490291 ZQCS_ENABLE_LP4: ON
9132 06:56:57.490770 RX_PICG_NEW_MODE: ON
9133 06:56:57.493884 TX_PICG_NEW_MODE: ON
9134 06:56:57.497115 ENABLE_RX_DCM_DPHY: ON
9135 06:56:57.500852 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9136 06:56:57.501406 DUMMY_READ_FOR_TRACKING: OFF
9137 06:56:57.504092 !!! SPM_CONTROL_AFTERK: OFF
9138 06:56:57.507234 !!! SPM could not control APHY
9139 06:56:57.510037 IMPEDANCE_TRACKING: ON
9140 06:56:57.510499 TEMP_SENSOR: ON
9141 06:56:57.513812 HW_SAVE_FOR_SR: OFF
9142 06:56:57.514269 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9143 06:56:57.520264 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9144 06:56:57.520913 Read ODT Tracking: ON
9145 06:56:57.523445 Refresh Rate DeBounce: ON
9146 06:56:57.526730 DFS_NO_QUEUE_FLUSH: ON
9147 06:56:57.527192 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9148 06:56:57.529954 ENABLE_DFS_RUNTIME_MRW: OFF
9149 06:56:57.533983 DDR_RESERVE_NEW_MODE: ON
9150 06:56:57.536912 MR_CBT_SWITCH_FREQ: ON
9151 06:56:57.537409 =========================
9152 06:56:57.556439 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9153 06:56:57.559859 dram_init: ddr_geometry: 2
9154 06:56:57.577743 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9155 06:56:57.581125 dram_init: dram init end (result: 0)
9156 06:56:57.587795 DRAM-K: Full calibration passed in 24408 msecs
9157 06:56:57.591381 MRC: failed to locate region type 0.
9158 06:56:57.592029 DRAM rank0 size:0x100000000,
9159 06:56:57.594648 DRAM rank1 size=0x100000000
9160 06:56:57.604645 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9161 06:56:57.611043 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9162 06:56:57.618166 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9163 06:56:57.624939 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9164 06:56:57.628054 DRAM rank0 size:0x100000000,
9165 06:56:57.631434 DRAM rank1 size=0x100000000
9166 06:56:57.631990 CBMEM:
9167 06:56:57.634533 IMD: root @ 0xfffff000 254 entries.
9168 06:56:57.638002 IMD: root @ 0xffffec00 62 entries.
9169 06:56:57.641033 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9170 06:56:57.644765 WARNING: RO_VPD is uninitialized or empty.
9171 06:56:57.650781 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9172 06:56:57.657951 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9173 06:56:57.670736 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9174 06:56:57.682155 BS: romstage times (exec / console): total (unknown) / 23948 ms
9175 06:56:57.682698
9176 06:56:57.683064
9177 06:56:57.691948 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9178 06:56:57.695589 ARM64: Exception handlers installed.
9179 06:56:57.698428 ARM64: Testing exception
9180 06:56:57.701802 ARM64: Done test exception
9181 06:56:57.702258 Enumerating buses...
9182 06:56:57.705140 Show all devs... Before device enumeration.
9183 06:56:57.708909 Root Device: enabled 1
9184 06:56:57.712150 CPU_CLUSTER: 0: enabled 1
9185 06:56:57.712647 CPU: 00: enabled 1
9186 06:56:57.715249 Compare with tree...
9187 06:56:57.715705 Root Device: enabled 1
9188 06:56:57.718530 CPU_CLUSTER: 0: enabled 1
9189 06:56:57.722035 CPU: 00: enabled 1
9190 06:56:57.722626 Root Device scanning...
9191 06:56:57.725251 scan_static_bus for Root Device
9192 06:56:57.728633 CPU_CLUSTER: 0 enabled
9193 06:56:57.732456 scan_static_bus for Root Device done
9194 06:56:57.735695 scan_bus: bus Root Device finished in 8 msecs
9195 06:56:57.736214 done
9196 06:56:57.742286 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9197 06:56:57.745072 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9198 06:56:57.751891 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9199 06:56:57.755519 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9200 06:56:57.758750 Allocating resources...
9201 06:56:57.762003 Reading resources...
9202 06:56:57.765068 Root Device read_resources bus 0 link: 0
9203 06:56:57.765527 DRAM rank0 size:0x100000000,
9204 06:56:57.768475 DRAM rank1 size=0x100000000
9205 06:56:57.771934 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9206 06:56:57.775747 CPU: 00 missing read_resources
9207 06:56:57.778599 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9208 06:56:57.785598 Root Device read_resources bus 0 link: 0 done
9209 06:56:57.786158 Done reading resources.
9210 06:56:57.791855 Show resources in subtree (Root Device)...After reading.
9211 06:56:57.795336 Root Device child on link 0 CPU_CLUSTER: 0
9212 06:56:57.798317 CPU_CLUSTER: 0 child on link 0 CPU: 00
9213 06:56:57.808901 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9214 06:56:57.809466 CPU: 00
9215 06:56:57.812046 Root Device assign_resources, bus 0 link: 0
9216 06:56:57.815186 CPU_CLUSTER: 0 missing set_resources
9217 06:56:57.818856 Root Device assign_resources, bus 0 link: 0 done
9218 06:56:57.822752 Done setting resources.
9219 06:56:57.828402 Show resources in subtree (Root Device)...After assigning values.
9220 06:56:57.831581 Root Device child on link 0 CPU_CLUSTER: 0
9221 06:56:57.835115 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 06:56:57.845155 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 06:56:57.845620 CPU: 00
9224 06:56:57.848689 Done allocating resources.
9225 06:56:57.851946 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9226 06:56:57.855089 Enabling resources...
9227 06:56:57.855544 done.
9228 06:56:57.862216 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9229 06:56:57.862822 Initializing devices...
9230 06:56:57.864922 Root Device init
9231 06:56:57.865377 init hardware done!
9232 06:56:57.868184 0x00000018: ctrlr->caps
9233 06:56:57.872006 52.000 MHz: ctrlr->f_max
9234 06:56:57.872511 0.400 MHz: ctrlr->f_min
9235 06:56:57.875455 0x40ff8080: ctrlr->voltages
9236 06:56:57.876018 sclk: 390625
9237 06:56:57.878621 Bus Width = 1
9238 06:56:57.879171 sclk: 390625
9239 06:56:57.879535 Bus Width = 1
9240 06:56:57.881865 Early init status = 3
9241 06:56:57.888170 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9242 06:56:57.892100 in-header: 03 fc 00 00 01 00 00 00
9243 06:56:57.892710 in-data: 00
9244 06:56:57.898460 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9245 06:56:57.901446 in-header: 03 fd 00 00 00 00 00 00
9246 06:56:57.904935 in-data:
9247 06:56:57.908222 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9248 06:56:57.911862 in-header: 03 fc 00 00 01 00 00 00
9249 06:56:57.915118 in-data: 00
9250 06:56:57.918572 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9251 06:56:57.923169 in-header: 03 fd 00 00 00 00 00 00
9252 06:56:57.926094 in-data:
9253 06:56:57.929547 [SSUSB] Setting up USB HOST controller...
9254 06:56:57.932864 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9255 06:56:57.936059 [SSUSB] phy power-on done.
9256 06:56:57.939605 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9257 06:56:57.945815 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9258 06:56:57.949325 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9259 06:56:57.956222 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9260 06:56:57.962470 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9261 06:56:57.968984 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9262 06:56:57.975847 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9263 06:56:57.982464 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9264 06:56:57.985831 SPM: binary array size = 0x9dc
9265 06:56:57.989100 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9266 06:56:57.995603 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9267 06:56:58.002522 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9268 06:56:58.005803 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9269 06:56:58.012245 configure_display: Starting display init
9270 06:56:58.046223 anx7625_power_on_init: Init interface.
9271 06:56:58.049416 anx7625_disable_pd_protocol: Disabled PD feature.
9272 06:56:58.052614 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9273 06:56:58.080432 anx7625_start_dp_work: Secure OCM version=00
9274 06:56:58.083730 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9275 06:56:58.098477 sp_tx_get_edid_block: EDID Block = 1
9276 06:56:58.201065 Extracted contents:
9277 06:56:58.204038 header: 00 ff ff ff ff ff ff 00
9278 06:56:58.207839 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9279 06:56:58.210918 version: 01 04
9280 06:56:58.214167 basic params: 95 1f 11 78 0a
9281 06:56:58.217778 chroma info: 76 90 94 55 54 90 27 21 50 54
9282 06:56:58.221280 established: 00 00 00
9283 06:56:58.227515 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9284 06:56:58.231314 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9285 06:56:58.237430 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9286 06:56:58.244078 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9287 06:56:58.251226 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9288 06:56:58.254166 extensions: 00
9289 06:56:58.254732 checksum: fb
9290 06:56:58.255230
9291 06:56:58.257718 Manufacturer: IVO Model 57d Serial Number 0
9292 06:56:58.260846 Made week 0 of 2020
9293 06:56:58.261404 EDID version: 1.4
9294 06:56:58.264140 Digital display
9295 06:56:58.267286 6 bits per primary color channel
9296 06:56:58.267754 DisplayPort interface
9297 06:56:58.270307 Maximum image size: 31 cm x 17 cm
9298 06:56:58.274423 Gamma: 220%
9299 06:56:58.274976 Check DPMS levels
9300 06:56:58.277313 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9301 06:56:58.284139 First detailed timing is preferred timing
9302 06:56:58.284729 Established timings supported:
9303 06:56:58.287388 Standard timings supported:
9304 06:56:58.290293 Detailed timings
9305 06:56:58.293811 Hex of detail: 383680a07038204018303c0035ae10000019
9306 06:56:58.296849 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9307 06:56:58.303641 0780 0798 07c8 0820 hborder 0
9308 06:56:58.306884 0438 043b 0447 0458 vborder 0
9309 06:56:58.310557 -hsync -vsync
9310 06:56:58.311115 Did detailed timing
9311 06:56:58.316678 Hex of detail: 000000000000000000000000000000000000
9312 06:56:58.320686 Manufacturer-specified data, tag 0
9313 06:56:58.323856 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9314 06:56:58.327074 ASCII string: InfoVision
9315 06:56:58.329874 Hex of detail: 000000fe00523134304e574635205248200a
9316 06:56:58.333890 ASCII string: R140NWF5 RH
9317 06:56:58.334447 Checksum
9318 06:56:58.336953 Checksum: 0xfb (valid)
9319 06:56:58.340007 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9320 06:56:58.343058 DSI data_rate: 832800000 bps
9321 06:56:58.350511 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9322 06:56:58.353788 anx7625_parse_edid: pixelclock(138800).
9323 06:56:58.357021 hactive(1920), hsync(48), hfp(24), hbp(88)
9324 06:56:58.359775 vactive(1080), vsync(12), vfp(3), vbp(17)
9325 06:56:58.363747 anx7625_dsi_config: config dsi.
9326 06:56:58.370099 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9327 06:56:58.383578 anx7625_dsi_config: success to config DSI
9328 06:56:58.386708 anx7625_dp_start: MIPI phy setup OK.
9329 06:56:58.389337 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9330 06:56:58.392554 mtk_ddp_mode_set invalid vrefresh 60
9331 06:56:58.396644 main_disp_path_setup
9332 06:56:58.397095 ovl_layer_smi_id_en
9333 06:56:58.399247 ovl_layer_smi_id_en
9334 06:56:58.399699 ccorr_config
9335 06:56:58.400072 aal_config
9336 06:56:58.403094 gamma_config
9337 06:56:58.403542 postmask_config
9338 06:56:58.406254 dither_config
9339 06:56:58.409215 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9340 06:56:58.415791 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9341 06:56:58.419665 Root Device init finished in 552 msecs
9342 06:56:58.422831 CPU_CLUSTER: 0 init
9343 06:56:58.429291 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9344 06:56:58.432699 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9345 06:56:58.436029 APU_MBOX 0x190000b0 = 0x10001
9346 06:56:58.439644 APU_MBOX 0x190001b0 = 0x10001
9347 06:56:58.443173 APU_MBOX 0x190005b0 = 0x10001
9348 06:56:58.446026 APU_MBOX 0x190006b0 = 0x10001
9349 06:56:58.449041 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9350 06:56:58.461906 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9351 06:56:58.474738 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9352 06:56:58.481153 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9353 06:56:58.493307 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9354 06:56:58.502020 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9355 06:56:58.504857 CPU_CLUSTER: 0 init finished in 81 msecs
9356 06:56:58.508692 Devices initialized
9357 06:56:58.511668 Show all devs... After init.
9358 06:56:58.512124 Root Device: enabled 1
9359 06:56:58.515413 CPU_CLUSTER: 0: enabled 1
9360 06:56:58.518621 CPU: 00: enabled 1
9361 06:56:58.521787 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9362 06:56:58.524632 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9363 06:56:58.528518 ELOG: NV offset 0x57f000 size 0x1000
9364 06:56:58.535448 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9365 06:56:58.541571 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9366 06:56:58.545065 ELOG: Event(17) added with size 13 at 2024-02-03 06:54:15 UTC
9367 06:56:58.551614 out: cmd=0x121: 03 db 21 01 00 00 00 00
9368 06:56:58.554924 in-header: 03 0f 00 00 2c 00 00 00
9369 06:56:58.564820 in-data: 50 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9370 06:56:58.571120 ELOG: Event(A1) added with size 10 at 2024-02-03 06:54:15 UTC
9371 06:56:58.578152 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9372 06:56:58.584422 ELOG: Event(A0) added with size 9 at 2024-02-03 06:54:15 UTC
9373 06:56:58.588510 elog_add_boot_reason: Logged dev mode boot
9374 06:56:58.591271 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9375 06:56:58.594463 Finalize devices...
9376 06:56:58.597635 Devices finalized
9377 06:56:58.600921 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9378 06:56:58.604316 Writing coreboot table at 0xffe64000
9379 06:56:58.607710 0. 000000000010a000-0000000000113fff: RAMSTAGE
9380 06:56:58.611016 1. 0000000040000000-00000000400fffff: RAM
9381 06:56:58.617820 2. 0000000040100000-000000004032afff: RAMSTAGE
9382 06:56:58.620946 3. 000000004032b000-00000000545fffff: RAM
9383 06:56:58.624618 4. 0000000054600000-000000005465ffff: BL31
9384 06:56:58.627594 5. 0000000054660000-00000000ffe63fff: RAM
9385 06:56:58.634568 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9386 06:56:58.637591 7. 0000000100000000-000000023fffffff: RAM
9387 06:56:58.641118 Passing 5 GPIOs to payload:
9388 06:56:58.644797 NAME | PORT | POLARITY | VALUE
9389 06:56:58.648256 EC in RW | 0x000000aa | low | undefined
9390 06:56:58.654202 EC interrupt | 0x00000005 | low | undefined
9391 06:56:58.657459 TPM interrupt | 0x000000ab | high | undefined
9392 06:56:58.664732 SD card detect | 0x00000011 | high | undefined
9393 06:56:58.667804 speaker enable | 0x00000093 | high | undefined
9394 06:56:58.670587 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9395 06:56:58.673838 in-header: 03 f9 00 00 02 00 00 00
9396 06:56:58.677631 in-data: 02 00
9397 06:56:58.678087 ADC[4]: Raw value=903988 ID=7
9398 06:56:58.680892 ADC[3]: Raw value=213810 ID=1
9399 06:56:58.684335 RAM Code: 0x71
9400 06:56:58.684892 ADC[6]: Raw value=75701 ID=0
9401 06:56:58.687416 ADC[5]: Raw value=212703 ID=1
9402 06:56:58.690430 SKU Code: 0x1
9403 06:56:58.694398 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3253
9404 06:56:58.697395 coreboot table: 964 bytes.
9405 06:56:58.700728 IMD ROOT 0. 0xfffff000 0x00001000
9406 06:56:58.703861 IMD SMALL 1. 0xffffe000 0x00001000
9407 06:56:58.707158 RO MCACHE 2. 0xffffc000 0x00001104
9408 06:56:58.710941 CONSOLE 3. 0xfff7c000 0x00080000
9409 06:56:58.713978 FMAP 4. 0xfff7b000 0x00000452
9410 06:56:58.717189 TIME STAMP 5. 0xfff7a000 0x00000910
9411 06:56:58.721342 VBOOT WORK 6. 0xfff66000 0x00014000
9412 06:56:58.724013 RAMOOPS 7. 0xffe66000 0x00100000
9413 06:56:58.727375 COREBOOT 8. 0xffe64000 0x00002000
9414 06:56:58.727928 IMD small region:
9415 06:56:58.731103 IMD ROOT 0. 0xffffec00 0x00000400
9416 06:56:58.734717 VPD 1. 0xffffeb80 0x0000006c
9417 06:56:58.737912 MMC STATUS 2. 0xffffeb60 0x00000004
9418 06:56:58.744359 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9419 06:56:58.747572 Probing TPM: done!
9420 06:56:58.750831 Connected to device vid:did:rid of 1ae0:0028:00
9421 06:56:58.761240 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9422 06:56:58.764259 Initialized TPM device CR50 revision 0
9423 06:56:58.767483 Checking cr50 for pending updates
9424 06:56:58.771451 Reading cr50 TPM mode
9425 06:56:58.780520 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9426 06:56:58.786996 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9427 06:56:58.826934 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9428 06:56:58.830765 Checking segment from ROM address 0x40100000
9429 06:56:58.834030 Checking segment from ROM address 0x4010001c
9430 06:56:58.840541 Loading segment from ROM address 0x40100000
9431 06:56:58.841096 code (compression=0)
9432 06:56:58.847333 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9433 06:56:58.857350 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9434 06:56:58.857979 it's not compressed!
9435 06:56:58.863635 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9436 06:56:58.866760 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9437 06:56:58.887403 Loading segment from ROM address 0x4010001c
9438 06:56:58.887989 Entry Point 0x80000000
9439 06:56:58.890803 Loaded segments
9440 06:56:58.894180 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9441 06:56:58.900854 Jumping to boot code at 0x80000000(0xffe64000)
9442 06:56:58.907280 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9443 06:56:58.914357 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9444 06:56:58.921573 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9445 06:56:58.925190 Checking segment from ROM address 0x40100000
9446 06:56:58.928199 Checking segment from ROM address 0x4010001c
9447 06:56:58.935158 Loading segment from ROM address 0x40100000
9448 06:56:58.935705 code (compression=1)
9449 06:56:58.942014 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9450 06:56:58.951601 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9451 06:56:58.952143 using LZMA
9452 06:56:58.960452 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9453 06:56:58.967150 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9454 06:56:58.970163 Loading segment from ROM address 0x4010001c
9455 06:56:58.970625 Entry Point 0x54601000
9456 06:56:58.973240 Loaded segments
9457 06:56:58.976431 NOTICE: MT8192 bl31_setup
9458 06:56:58.983847 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9459 06:56:58.987103 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9460 06:56:58.990426 WARNING: region 0:
9461 06:56:58.994390 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 06:56:58.994942 WARNING: region 1:
9463 06:56:59.000585 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9464 06:56:59.003972 WARNING: region 2:
9465 06:56:59.007298 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9466 06:56:59.010530 WARNING: region 3:
9467 06:56:59.014366 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9468 06:56:59.017368 WARNING: region 4:
9469 06:56:59.020844 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9470 06:56:59.023888 WARNING: region 5:
9471 06:56:59.027236 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 06:56:59.030511 WARNING: region 6:
9473 06:56:59.034022 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 06:56:59.034551 WARNING: region 7:
9475 06:56:59.040705 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 06:56:59.047223 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9477 06:56:59.050924 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9478 06:56:59.053925 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9479 06:56:59.057942 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9480 06:56:59.064346 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9481 06:56:59.067683 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9482 06:56:59.074259 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9483 06:56:59.077699 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9484 06:56:59.081037 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9485 06:56:59.087730 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9486 06:56:59.090883 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9487 06:56:59.094072 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9488 06:56:59.100612 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9489 06:56:59.104451 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9490 06:56:59.111052 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9491 06:56:59.114275 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9492 06:56:59.117833 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9493 06:56:59.124709 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9494 06:56:59.127695 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9495 06:56:59.131070 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9496 06:56:59.137647 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9497 06:56:59.141051 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9498 06:56:59.147783 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9499 06:56:59.151651 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9500 06:56:59.154591 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9501 06:56:59.160779 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9502 06:56:59.164281 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9503 06:56:59.170861 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9504 06:56:59.174353 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9505 06:56:59.177790 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9506 06:56:59.184350 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9507 06:56:59.187989 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9508 06:56:59.190839 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9509 06:56:59.197588 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9510 06:56:59.201233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9511 06:56:59.204400 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9512 06:56:59.207784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9513 06:56:59.211460 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9514 06:56:59.217945 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9515 06:56:59.221097 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9516 06:56:59.224704 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9517 06:56:59.227813 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9518 06:56:59.234435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9519 06:56:59.237961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9520 06:56:59.241710 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9521 06:56:59.244702 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9522 06:56:59.251994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9523 06:56:59.255118 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9524 06:56:59.258562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9525 06:56:59.264982 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9526 06:56:59.268220 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9527 06:56:59.274707 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9528 06:56:59.278640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9529 06:56:59.281726 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9530 06:56:59.288449 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9531 06:56:59.291892 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9532 06:56:59.298551 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9533 06:56:59.301752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9534 06:56:59.308508 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9535 06:56:59.311867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9536 06:56:59.315353 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9537 06:56:59.321570 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9538 06:56:59.324954 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9539 06:56:59.331720 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9540 06:56:59.334766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9541 06:56:59.341502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9542 06:56:59.344930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9543 06:56:59.348167 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9544 06:56:59.355623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9545 06:56:59.358542 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9546 06:56:59.365325 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9547 06:56:59.368951 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9548 06:56:59.375237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9549 06:56:59.378740 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9550 06:56:59.381846 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9551 06:56:59.389303 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9552 06:56:59.392137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9553 06:56:59.398291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9554 06:56:59.401547 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9555 06:56:59.408631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9556 06:56:59.411753 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9557 06:56:59.415255 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9558 06:56:59.421769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9559 06:56:59.425052 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9560 06:56:59.432184 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9561 06:56:59.435329 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9562 06:56:59.442482 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9563 06:56:59.445602 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9564 06:56:59.449144 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9565 06:56:59.455830 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9566 06:56:59.458972 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9567 06:56:59.465410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9568 06:56:59.469268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9569 06:56:59.475442 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9570 06:56:59.479069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9571 06:56:59.482140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9572 06:56:59.489115 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9573 06:56:59.492231 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9574 06:56:59.495707 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9575 06:56:59.499007 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9576 06:56:59.505780 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9577 06:56:59.508948 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9578 06:56:59.512464 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9579 06:56:59.519117 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9580 06:56:59.522575 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9581 06:56:59.529255 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9582 06:56:59.532179 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9583 06:56:59.535844 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9584 06:56:59.542241 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9585 06:56:59.545770 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9586 06:56:59.552976 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9587 06:56:59.555879 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9588 06:56:59.559388 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9589 06:56:59.565879 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9590 06:56:59.568964 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9591 06:56:59.575901 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9592 06:56:59.579274 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9593 06:56:59.582415 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9594 06:56:59.585844 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9595 06:56:59.592435 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9596 06:56:59.596052 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9597 06:56:59.599244 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9598 06:56:59.602218 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9599 06:56:59.609613 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9600 06:56:59.612606 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9601 06:56:59.615913 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9602 06:56:59.622296 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9603 06:56:59.625810 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9604 06:56:59.633034 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9605 06:56:59.635952 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9606 06:56:59.639414 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9607 06:56:59.645918 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9608 06:56:59.649152 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9609 06:56:59.652604 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9610 06:56:59.659795 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9611 06:56:59.662837 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9612 06:56:59.669318 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9613 06:56:59.672422 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9614 06:56:59.675842 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9615 06:56:59.682679 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9616 06:56:59.685531 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9617 06:56:59.692554 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9618 06:56:59.696171 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9619 06:56:59.699149 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9620 06:56:59.705502 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9621 06:56:59.708875 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9622 06:56:59.712814 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9623 06:56:59.719110 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9624 06:56:59.722504 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9625 06:56:59.729078 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9626 06:56:59.732482 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9627 06:56:59.735801 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9628 06:56:59.742892 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9629 06:56:59.745823 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9630 06:56:59.752431 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9631 06:56:59.755827 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9632 06:56:59.759027 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9633 06:56:59.766143 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9634 06:56:59.769152 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9635 06:56:59.772498 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9636 06:56:59.779244 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9637 06:56:59.782963 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9638 06:56:59.789341 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9639 06:56:59.792694 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9640 06:56:59.795840 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9641 06:56:59.802705 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9642 06:56:59.805719 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9643 06:56:59.812912 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9644 06:56:59.815822 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9645 06:56:59.819430 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9646 06:56:59.826149 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9647 06:56:59.829397 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9648 06:56:59.832367 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9649 06:56:59.839308 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9650 06:56:59.842375 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9651 06:56:59.849245 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9652 06:56:59.852406 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9653 06:56:59.858972 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9654 06:56:59.861794 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9655 06:56:59.865726 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9656 06:56:59.872242 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9657 06:56:59.875187 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9658 06:56:59.882287 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9659 06:56:59.885517 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9660 06:56:59.888509 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9661 06:56:59.895641 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9662 06:56:59.898534 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9663 06:56:59.901599 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9664 06:56:59.908382 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9665 06:56:59.911565 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9666 06:56:59.918248 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9667 06:56:59.921917 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9668 06:56:59.928495 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9669 06:56:59.931634 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9670 06:56:59.934959 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9671 06:56:59.941299 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9672 06:56:59.944340 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9673 06:56:59.951452 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9674 06:56:59.954472 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9675 06:56:59.961143 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9676 06:56:59.964660 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9677 06:56:59.967715 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9678 06:56:59.974401 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9679 06:56:59.977634 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9680 06:56:59.984412 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9681 06:56:59.987919 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9682 06:56:59.994865 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9683 06:56:59.997757 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9684 06:57:00.000906 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9685 06:57:00.007488 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9686 06:57:00.011209 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9687 06:57:00.017857 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9688 06:57:00.021329 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9689 06:57:00.024329 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9690 06:57:00.031343 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9691 06:57:00.034198 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9692 06:57:00.040999 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9693 06:57:00.044541 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9694 06:57:00.051243 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9695 06:57:00.054155 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9696 06:57:00.057389 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9697 06:57:00.064228 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9698 06:57:00.067855 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9699 06:57:00.074207 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9700 06:57:00.077658 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9701 06:57:00.081069 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9702 06:57:00.087512 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9703 06:57:00.090565 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9704 06:57:00.097236 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9705 06:57:00.100990 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9706 06:57:00.103720 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9707 06:57:00.107131 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9708 06:57:00.113994 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9709 06:57:00.117144 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9710 06:57:00.120491 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9711 06:57:00.127240 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9712 06:57:00.130658 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9713 06:57:00.134150 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9714 06:57:00.140590 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9715 06:57:00.143576 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9716 06:57:00.147243 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9717 06:57:00.153764 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9718 06:57:00.157437 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9719 06:57:00.160979 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9720 06:57:00.167323 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9721 06:57:00.170496 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9722 06:57:00.177407 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9723 06:57:00.180745 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9724 06:57:00.183939 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9725 06:57:00.190020 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9726 06:57:00.193895 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9727 06:57:00.197237 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9728 06:57:00.203702 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9729 06:57:00.206709 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9730 06:57:00.210348 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9731 06:57:00.216936 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9732 06:57:00.220438 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9733 06:57:00.227226 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9734 06:57:00.230596 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9735 06:57:00.233389 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9736 06:57:00.240364 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9737 06:57:00.243601 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9738 06:57:00.246586 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9739 06:57:00.253160 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9740 06:57:00.256672 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9741 06:57:00.260224 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9742 06:57:00.266672 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9743 06:57:00.269793 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9744 06:57:00.276559 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9745 06:57:00.280154 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9746 06:57:00.283406 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9747 06:57:00.286676 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9748 06:57:00.290148 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9749 06:57:00.296901 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9750 06:57:00.299522 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9751 06:57:00.303673 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9752 06:57:00.306668 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9753 06:57:00.313653 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9754 06:57:00.316791 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9755 06:57:00.319745 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9756 06:57:00.326494 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9757 06:57:00.329479 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9758 06:57:00.332792 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9759 06:57:00.339174 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9760 06:57:00.343361 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9761 06:57:00.349564 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9762 06:57:00.352479 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9763 06:57:00.356024 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9764 06:57:00.362848 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9765 06:57:00.365663 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9766 06:57:00.372455 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9767 06:57:00.375746 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9768 06:57:00.379483 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9769 06:57:00.385879 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9770 06:57:00.389607 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9771 06:57:00.396403 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9772 06:57:00.399736 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9773 06:57:00.402472 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9774 06:57:00.409363 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9775 06:57:00.412636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9776 06:57:00.419597 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9777 06:57:00.422417 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9778 06:57:00.425350 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9779 06:57:00.432967 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9780 06:57:00.435794 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9781 06:57:00.442479 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9782 06:57:00.445422 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9783 06:57:00.448935 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9784 06:57:00.455936 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9785 06:57:00.459274 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9786 06:57:00.465795 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9787 06:57:00.468986 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9788 06:57:00.475244 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9789 06:57:00.478766 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9790 06:57:00.482053 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9791 06:57:00.488512 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9792 06:57:00.491833 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9793 06:57:00.499261 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9794 06:57:00.502196 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9795 06:57:00.505107 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9796 06:57:00.512150 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9797 06:57:00.515319 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9798 06:57:00.521877 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9799 06:57:00.524844 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9800 06:57:00.528228 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9801 06:57:00.535054 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9802 06:57:00.538569 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9803 06:57:00.545268 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9804 06:57:00.548614 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9805 06:57:00.551977 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9806 06:57:00.558126 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9807 06:57:00.561796 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9808 06:57:00.568487 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9809 06:57:00.571862 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9810 06:57:00.578427 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9811 06:57:00.581608 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9812 06:57:00.585452 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9813 06:57:00.591990 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9814 06:57:00.594944 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9815 06:57:00.602221 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9816 06:57:00.605147 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9817 06:57:00.608744 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9818 06:57:00.615127 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9819 06:57:00.618682 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9820 06:57:00.624778 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9821 06:57:00.628428 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9822 06:57:00.631630 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9823 06:57:00.638473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9824 06:57:00.641679 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9825 06:57:00.648144 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9826 06:57:00.651248 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9827 06:57:00.654959 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9828 06:57:00.661112 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9829 06:57:00.664610 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9830 06:57:00.671434 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9831 06:57:00.674598 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9832 06:57:00.681869 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9833 06:57:00.685168 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9834 06:57:00.688241 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9835 06:57:00.694753 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9836 06:57:00.698255 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9837 06:57:00.705296 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9838 06:57:00.708192 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9839 06:57:00.711587 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9840 06:57:00.718110 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9841 06:57:00.721952 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9842 06:57:00.728409 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9843 06:57:00.731505 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9844 06:57:00.737823 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9845 06:57:00.741305 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9846 06:57:00.747446 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9847 06:57:00.751420 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9848 06:57:00.754312 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9849 06:57:00.760833 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9850 06:57:00.764369 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9851 06:57:00.770471 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9852 06:57:00.774129 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9853 06:57:00.780767 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9854 06:57:00.784381 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9855 06:57:00.790386 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9856 06:57:00.793698 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9857 06:57:00.797310 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9858 06:57:00.803895 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9859 06:57:00.807499 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9860 06:57:00.814403 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9861 06:57:00.817546 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9862 06:57:00.824086 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9863 06:57:00.827259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9864 06:57:00.830874 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9865 06:57:00.837249 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9866 06:57:00.840587 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9867 06:57:00.846995 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9868 06:57:00.851193 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9869 06:57:00.857318 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9870 06:57:00.860912 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9871 06:57:00.864086 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9872 06:57:00.870253 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9873 06:57:00.873722 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9874 06:57:00.880986 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9875 06:57:00.883991 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9876 06:57:00.891103 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9877 06:57:00.893598 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9878 06:57:00.897119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9879 06:57:00.904242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9880 06:57:00.907468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9881 06:57:00.914279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9882 06:57:00.916729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9883 06:57:00.923641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9884 06:57:00.926703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9885 06:57:00.934025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9886 06:57:00.936910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9887 06:57:00.944173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9888 06:57:00.947019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9889 06:57:00.953846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9890 06:57:00.956927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9891 06:57:00.960332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9892 06:57:00.966843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9893 06:57:00.969903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9894 06:57:00.976861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9895 06:57:00.980574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9896 06:57:00.987252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9897 06:57:00.990573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9898 06:57:00.996651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9899 06:57:01.000102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9900 06:57:01.006500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9901 06:57:01.010810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9902 06:57:01.016451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9903 06:57:01.020351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9904 06:57:01.026506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9905 06:57:01.030091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9906 06:57:01.036090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9907 06:57:01.039558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9908 06:57:01.046544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9909 06:57:01.050221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9910 06:57:01.056057 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9911 06:57:01.056562 INFO: [APUAPC] vio 0
9912 06:57:01.063511 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9913 06:57:01.066952 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9914 06:57:01.070105 INFO: [APUAPC] D0_APC_0: 0x400510
9915 06:57:01.073762 INFO: [APUAPC] D0_APC_1: 0x0
9916 06:57:01.077011 INFO: [APUAPC] D0_APC_2: 0x1540
9917 06:57:01.080420 INFO: [APUAPC] D0_APC_3: 0x0
9918 06:57:01.083472 INFO: [APUAPC] D1_APC_0: 0xffffffff
9919 06:57:01.086471 INFO: [APUAPC] D1_APC_1: 0xffffffff
9920 06:57:01.090424 INFO: [APUAPC] D1_APC_2: 0x3fffff
9921 06:57:01.093913 INFO: [APUAPC] D1_APC_3: 0x0
9922 06:57:01.097112 INFO: [APUAPC] D2_APC_0: 0xffffffff
9923 06:57:01.100188 INFO: [APUAPC] D2_APC_1: 0xffffffff
9924 06:57:01.103819 INFO: [APUAPC] D2_APC_2: 0x3fffff
9925 06:57:01.106608 INFO: [APUAPC] D2_APC_3: 0x0
9926 06:57:01.110464 INFO: [APUAPC] D3_APC_0: 0xffffffff
9927 06:57:01.113812 INFO: [APUAPC] D3_APC_1: 0xffffffff
9928 06:57:01.116944 INFO: [APUAPC] D3_APC_2: 0x3fffff
9929 06:57:01.117503 INFO: [APUAPC] D3_APC_3: 0x0
9930 06:57:01.120492 INFO: [APUAPC] D4_APC_0: 0xffffffff
9931 06:57:01.123758 INFO: [APUAPC] D4_APC_1: 0xffffffff
9932 06:57:01.126998 INFO: [APUAPC] D4_APC_2: 0x3fffff
9933 06:57:01.130895 INFO: [APUAPC] D4_APC_3: 0x0
9934 06:57:01.134072 INFO: [APUAPC] D5_APC_0: 0xffffffff
9935 06:57:01.137249 INFO: [APUAPC] D5_APC_1: 0xffffffff
9936 06:57:01.140266 INFO: [APUAPC] D5_APC_2: 0x3fffff
9937 06:57:01.143490 INFO: [APUAPC] D5_APC_3: 0x0
9938 06:57:01.146980 INFO: [APUAPC] D6_APC_0: 0xffffffff
9939 06:57:01.150416 INFO: [APUAPC] D6_APC_1: 0xffffffff
9940 06:57:01.153268 INFO: [APUAPC] D6_APC_2: 0x3fffff
9941 06:57:01.156882 INFO: [APUAPC] D6_APC_3: 0x0
9942 06:57:01.160317 INFO: [APUAPC] D7_APC_0: 0xffffffff
9943 06:57:01.163700 INFO: [APUAPC] D7_APC_1: 0xffffffff
9944 06:57:01.166957 INFO: [APUAPC] D7_APC_2: 0x3fffff
9945 06:57:01.170310 INFO: [APUAPC] D7_APC_3: 0x0
9946 06:57:01.173644 INFO: [APUAPC] D8_APC_0: 0xffffffff
9947 06:57:01.176519 INFO: [APUAPC] D8_APC_1: 0xffffffff
9948 06:57:01.179738 INFO: [APUAPC] D8_APC_2: 0x3fffff
9949 06:57:01.183267 INFO: [APUAPC] D8_APC_3: 0x0
9950 06:57:01.186433 INFO: [APUAPC] D9_APC_0: 0xffffffff
9951 06:57:01.190459 INFO: [APUAPC] D9_APC_1: 0xffffffff
9952 06:57:01.193792 INFO: [APUAPC] D9_APC_2: 0x3fffff
9953 06:57:01.196656 INFO: [APUAPC] D9_APC_3: 0x0
9954 06:57:01.199770 INFO: [APUAPC] D10_APC_0: 0xffffffff
9955 06:57:01.203630 INFO: [APUAPC] D10_APC_1: 0xffffffff
9956 06:57:01.206474 INFO: [APUAPC] D10_APC_2: 0x3fffff
9957 06:57:01.210008 INFO: [APUAPC] D10_APC_3: 0x0
9958 06:57:01.213336 INFO: [APUAPC] D11_APC_0: 0xffffffff
9959 06:57:01.216687 INFO: [APUAPC] D11_APC_1: 0xffffffff
9960 06:57:01.219501 INFO: [APUAPC] D11_APC_2: 0x3fffff
9961 06:57:01.222825 INFO: [APUAPC] D11_APC_3: 0x0
9962 06:57:01.226809 INFO: [APUAPC] D12_APC_0: 0xffffffff
9963 06:57:01.229618 INFO: [APUAPC] D12_APC_1: 0xffffffff
9964 06:57:01.233417 INFO: [APUAPC] D12_APC_2: 0x3fffff
9965 06:57:01.236735 INFO: [APUAPC] D12_APC_3: 0x0
9966 06:57:01.239589 INFO: [APUAPC] D13_APC_0: 0xffffffff
9967 06:57:01.243671 INFO: [APUAPC] D13_APC_1: 0xffffffff
9968 06:57:01.246002 INFO: [APUAPC] D13_APC_2: 0x3fffff
9969 06:57:01.250148 INFO: [APUAPC] D13_APC_3: 0x0
9970 06:57:01.253411 INFO: [APUAPC] D14_APC_0: 0xffffffff
9971 06:57:01.256327 INFO: [APUAPC] D14_APC_1: 0xffffffff
9972 06:57:01.259856 INFO: [APUAPC] D14_APC_2: 0x3fffff
9973 06:57:01.262832 INFO: [APUAPC] D14_APC_3: 0x0
9974 06:57:01.266436 INFO: [APUAPC] D15_APC_0: 0xffffffff
9975 06:57:01.269311 INFO: [APUAPC] D15_APC_1: 0xffffffff
9976 06:57:01.272965 INFO: [APUAPC] D15_APC_2: 0x3fffff
9977 06:57:01.276153 INFO: [APUAPC] D15_APC_3: 0x0
9978 06:57:01.279783 INFO: [APUAPC] APC_CON: 0x4
9979 06:57:01.283053 INFO: [NOCDAPC] D0_APC_0: 0x0
9980 06:57:01.286007 INFO: [NOCDAPC] D0_APC_1: 0x0
9981 06:57:01.290204 INFO: [NOCDAPC] D1_APC_0: 0x0
9982 06:57:01.290771 INFO: [NOCDAPC] D1_APC_1: 0xfff
9983 06:57:01.292837 INFO: [NOCDAPC] D2_APC_0: 0x0
9984 06:57:01.295963 INFO: [NOCDAPC] D2_APC_1: 0xfff
9985 06:57:01.299767 INFO: [NOCDAPC] D3_APC_0: 0x0
9986 06:57:01.303134 INFO: [NOCDAPC] D3_APC_1: 0xfff
9987 06:57:01.306254 INFO: [NOCDAPC] D4_APC_0: 0x0
9988 06:57:01.309260 INFO: [NOCDAPC] D4_APC_1: 0xfff
9989 06:57:01.312818 INFO: [NOCDAPC] D5_APC_0: 0x0
9990 06:57:01.316768 INFO: [NOCDAPC] D5_APC_1: 0xfff
9991 06:57:01.319498 INFO: [NOCDAPC] D6_APC_0: 0x0
9992 06:57:01.322960 INFO: [NOCDAPC] D6_APC_1: 0xfff
9993 06:57:01.323508 INFO: [NOCDAPC] D7_APC_0: 0x0
9994 06:57:01.326787 INFO: [NOCDAPC] D7_APC_1: 0xfff
9995 06:57:01.329765 INFO: [NOCDAPC] D8_APC_0: 0x0
9996 06:57:01.332997 INFO: [NOCDAPC] D8_APC_1: 0xfff
9997 06:57:01.336552 INFO: [NOCDAPC] D9_APC_0: 0x0
9998 06:57:01.339808 INFO: [NOCDAPC] D9_APC_1: 0xfff
9999 06:57:01.343328 INFO: [NOCDAPC] D10_APC_0: 0x0
10000 06:57:01.346126 INFO: [NOCDAPC] D10_APC_1: 0xfff
10001 06:57:01.349862 INFO: [NOCDAPC] D11_APC_0: 0x0
10002 06:57:01.352984 INFO: [NOCDAPC] D11_APC_1: 0xfff
10003 06:57:01.356163 INFO: [NOCDAPC] D12_APC_0: 0x0
10004 06:57:01.359181 INFO: [NOCDAPC] D12_APC_1: 0xfff
10005 06:57:01.359638 INFO: [NOCDAPC] D13_APC_0: 0x0
10006 06:57:01.363313 INFO: [NOCDAPC] D13_APC_1: 0xfff
10007 06:57:01.366453 INFO: [NOCDAPC] D14_APC_0: 0x0
10008 06:57:01.369226 INFO: [NOCDAPC] D14_APC_1: 0xfff
10009 06:57:01.372737 INFO: [NOCDAPC] D15_APC_0: 0x0
10010 06:57:01.375767 INFO: [NOCDAPC] D15_APC_1: 0xfff
10011 06:57:01.379504 INFO: [NOCDAPC] APC_CON: 0x4
10012 06:57:01.382875 INFO: [APUAPC] set_apusys_apc done
10013 06:57:01.386795 INFO: [DEVAPC] devapc_init done
10014 06:57:01.389706 INFO: GICv3 without legacy support detected.
10015 06:57:01.392618 INFO: ARM GICv3 driver initialized in EL3
10016 06:57:01.399443 INFO: Maximum SPI INTID supported: 639
10017 06:57:01.402563 INFO: BL31: Initializing runtime services
10018 06:57:01.406277 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10019 06:57:01.409583 INFO: SPM: enable CPC mode
10020 06:57:01.416092 INFO: mcdi ready for mcusys-off-idle and system suspend
10021 06:57:01.419161 INFO: BL31: Preparing for EL3 exit to normal world
10022 06:57:01.422895 INFO: Entry point address = 0x80000000
10023 06:57:01.425617 INFO: SPSR = 0x8
10024 06:57:01.431723
10025 06:57:01.432268
10026 06:57:01.432704
10027 06:57:01.434828 Starting depthcharge on Spherion...
10028 06:57:01.435375
10029 06:57:01.435741 Wipe memory regions:
10030 06:57:01.436086
10031 06:57:01.438864 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10032 06:57:01.439415 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10033 06:57:01.439858 Setting prompt string to ['asurada:']
10034 06:57:01.440329 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10035 06:57:01.441067 [0x00000040000000, 0x00000054600000)
10036 06:57:01.560533
10037 06:57:01.561085 [0x00000054660000, 0x00000080000000)
10038 06:57:01.821304
10039 06:57:01.821849 [0x000000821a7280, 0x000000ffe64000)
10040 06:57:02.565534
10041 06:57:02.566080 [0x00000100000000, 0x00000240000000)
10042 06:57:04.455750
10043 06:57:04.458148 Initializing XHCI USB controller at 0x11200000.
10044 06:57:05.496176
10045 06:57:05.499342 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10046 06:57:05.499763
10047 06:57:05.500087
10048 06:57:05.500440
10049 06:57:05.501185 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10051 06:57:05.602329 asurada: tftpboot 192.168.201.1 12694854/tftp-deploy-w1pzfpjm/kernel/image.itb 12694854/tftp-deploy-w1pzfpjm/kernel/cmdline
10052 06:57:05.602887 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 06:57:05.603287 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10054 06:57:05.608230 tftpboot 192.168.201.1 12694854/tftp-deploy-w1pzfpjm/kernel/image.ittp-deploy-w1pzfpjm/kernel/cmdline
10055 06:57:05.608709
10056 06:57:05.609046 Waiting for link
10057 06:57:05.768443
10058 06:57:05.768911 R8152: Initializing
10059 06:57:05.769249
10060 06:57:05.772157 Version 9 (ocp_data = 6010)
10061 06:57:05.772630
10062 06:57:05.775157 R8152: Done initializing
10063 06:57:05.775572
10064 06:57:05.775897 Adding net device
10065 06:57:07.781073
10066 06:57:07.781575 done.
10067 06:57:07.781903
10068 06:57:07.782207 MAC: 00:e0:4c:78:7a:aa
10069 06:57:07.782580
10070 06:57:07.784174 Sending DHCP discover... done.
10071 06:57:07.784657
10072 06:57:07.788253 Waiting for reply... done.
10073 06:57:07.788717
10074 06:57:07.790717 Sending DHCP request... done.
10075 06:57:07.791127
10076 06:57:07.795902 Waiting for reply... done.
10077 06:57:07.796362
10078 06:57:07.796703 My ip is 192.168.201.12
10079 06:57:07.797010
10080 06:57:07.799859 The DHCP server ip is 192.168.201.1
10081 06:57:07.800422
10082 06:57:07.806355 TFTP server IP predefined by user: 192.168.201.1
10083 06:57:07.806769
10084 06:57:07.812705 Bootfile predefined by user: 12694854/tftp-deploy-w1pzfpjm/kernel/image.itb
10085 06:57:07.813120
10086 06:57:07.816215 Sending tftp read request... done.
10087 06:57:07.816667
10088 06:57:07.822543 Waiting for the transfer...
10089 06:57:07.823056
10090 06:57:08.196787 00000000 ################################################################
10091 06:57:08.197296
10092 06:57:08.466244 00080000 ################################################################
10093 06:57:08.466374
10094 06:57:08.730270 00100000 ################################################################
10095 06:57:08.730402
10096 06:57:08.996868 00180000 ################################################################
10097 06:57:08.997010
10098 06:57:09.267566 00200000 ################################################################
10099 06:57:09.267718
10100 06:57:09.533349 00280000 ################################################################
10101 06:57:09.533498
10102 06:57:09.802058 00300000 ################################################################
10103 06:57:09.802204
10104 06:57:10.066373 00380000 ################################################################
10105 06:57:10.066544
10106 06:57:10.321852 00400000 ################################################################
10107 06:57:10.321985
10108 06:57:10.594246 00480000 ################################################################
10109 06:57:10.594421
10110 06:57:10.852176 00500000 ################################################################
10111 06:57:10.852344
10112 06:57:11.136957 00580000 ################################################################
10113 06:57:11.137103
10114 06:57:11.404507 00600000 ################################################################
10115 06:57:11.404638
10116 06:57:11.670773 00680000 ################################################################
10117 06:57:11.670928
10118 06:57:11.938215 00700000 ################################################################
10119 06:57:11.938352
10120 06:57:12.204689 00780000 ################################################################
10121 06:57:12.204845
10122 06:57:12.489025 00800000 ################################################################
10123 06:57:12.489191
10124 06:57:12.778071 00880000 ################################################################
10125 06:57:12.778227
10126 06:57:13.056713 00900000 ################################################################
10127 06:57:13.056844
10128 06:57:13.333401 00980000 ################################################################
10129 06:57:13.333537
10130 06:57:13.620824 00a00000 ################################################################
10131 06:57:13.620952
10132 06:57:13.894898 00a80000 ################################################################
10133 06:57:13.895056
10134 06:57:14.165913 00b00000 ################################################################
10135 06:57:14.166040
10136 06:57:14.457311 00b80000 ################################################################
10137 06:57:14.457468
10138 06:57:14.738882 00c00000 ################################################################
10139 06:57:14.739011
10140 06:57:15.001026 00c80000 ################################################################
10141 06:57:15.001165
10142 06:57:15.264754 00d00000 ################################################################
10143 06:57:15.264884
10144 06:57:15.534069 00d80000 ################################################################
10145 06:57:15.534198
10146 06:57:15.794445 00e00000 ################################################################
10147 06:57:15.794604
10148 06:57:16.081722 00e80000 ################################################################
10149 06:57:16.081902
10150 06:57:16.367165 00f00000 ################################################################
10151 06:57:16.367321
10152 06:57:16.630756 00f80000 ################################################################
10153 06:57:16.630923
10154 06:57:16.897393 01000000 ################################################################
10155 06:57:16.897565
10156 06:57:17.168553 01080000 ################################################################
10157 06:57:17.168730
10158 06:57:17.437644 01100000 ################################################################
10159 06:57:17.437791
10160 06:57:17.702281 01180000 ################################################################
10161 06:57:17.702451
10162 06:57:17.962126 01200000 ################################################################
10163 06:57:17.962309
10164 06:57:18.240576 01280000 ################################################################
10165 06:57:18.240720
10166 06:57:18.510632 01300000 ################################################################
10167 06:57:18.510806
10168 06:57:18.789602 01380000 ################################################################
10169 06:57:18.789780
10170 06:57:19.064413 01400000 ################################################################
10171 06:57:19.064612
10172 06:57:19.334801 01480000 ################################################################
10173 06:57:19.334949
10174 06:57:19.601507 01500000 ################################################################
10175 06:57:19.601673
10176 06:57:19.872009 01580000 ################################################################
10177 06:57:19.872159
10178 06:57:20.145268 01600000 ################################################################
10179 06:57:20.145414
10180 06:57:20.419094 01680000 ################################################################
10181 06:57:20.419238
10182 06:57:20.693402 01700000 ################################################################
10183 06:57:20.693536
10184 06:57:20.982069 01780000 ################################################################
10185 06:57:20.982214
10186 06:57:21.249681 01800000 ################################################################
10187 06:57:21.249819
10188 06:57:21.613822 01880000 ################################################################
10189 06:57:21.613963
10190 06:57:21.909285 01900000 ################################################################
10191 06:57:21.909432
10192 06:57:22.183962 01980000 ################################################################
10193 06:57:22.184105
10194 06:57:22.442612 01a00000 ################################################################
10195 06:57:22.442753
10196 06:57:22.721191 01a80000 ################################################################
10197 06:57:22.721324
10198 06:57:22.988198 01b00000 ################################################################
10199 06:57:22.988395
10200 06:57:23.250091 01b80000 ################################################################
10201 06:57:23.250240
10202 06:57:23.516314 01c00000 ################################################################
10203 06:57:23.516473
10204 06:57:23.525825 01c80000 ## done.
10205 06:57:23.525936
10206 06:57:23.528925 The bootfile was 29900706 bytes long.
10207 06:57:23.529050
10208 06:57:23.532202 Sending tftp read request... done.
10209 06:57:23.532283
10210 06:57:23.532358 Waiting for the transfer...
10211 06:57:23.532420
10212 06:57:23.535548 00000000 # done.
10213 06:57:23.535631
10214 06:57:23.542249 Command line loaded dynamically from TFTP file: 12694854/tftp-deploy-w1pzfpjm/kernel/cmdline
10215 06:57:23.542331
10216 06:57:23.565900 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694854/extract-nfsrootfs-u46__al4,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10217 06:57:23.565985
10218 06:57:23.566049 Loading FIT.
10219 06:57:23.566108
10220 06:57:23.569093 Image ramdisk-1 has 17800812 bytes.
10221 06:57:23.569174
10222 06:57:23.572440 Image fdt-1 has 47278 bytes.
10223 06:57:23.572521
10224 06:57:23.575088 Image kernel-1 has 12050581 bytes.
10225 06:57:23.575168
10226 06:57:23.585243 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10227 06:57:23.585328
10228 06:57:23.602105 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10229 06:57:23.602192
10230 06:57:23.608919 Choosing best match conf-1 for compat google,spherion-rev2.
10231 06:57:23.609001
10232 06:57:23.611997 Connected to device vid:did:rid of 1ae0:0028:00
10233 06:57:23.624276
10234 06:57:23.627443 tpm_get_response: command 0x17b, return code 0x0
10235 06:57:23.627524
10236 06:57:23.630772 ec_init: CrosEC protocol v3 supported (256, 248)
10237 06:57:23.634817
10238 06:57:23.637775 tpm_cleanup: add release locality here.
10239 06:57:23.637857
10240 06:57:23.637920 Shutting down all USB controllers.
10241 06:57:23.641306
10242 06:57:23.641387 Removing current net device
10243 06:57:23.641452
10244 06:57:23.647961 Exiting depthcharge with code 4 at timestamp: 51443596
10245 06:57:23.648042
10246 06:57:23.651535 LZMA decompressing kernel-1 to 0x821a6718
10247 06:57:23.651616
10248 06:57:23.654611 LZMA decompressing kernel-1 to 0x40000000
10249 06:57:25.153429
10250 06:57:25.153600 jumping to kernel
10251 06:57:25.154055 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10252 06:57:25.154154 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10253 06:57:25.154231 Setting prompt string to ['Linux version [0-9]']
10254 06:57:25.154300 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10255 06:57:25.154368 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10256 06:57:25.236627
10257 06:57:25.239589 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10258 06:57:25.243350 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10259 06:57:25.243441 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10260 06:57:25.243512 Setting prompt string to []
10261 06:57:25.243603 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10262 06:57:25.243677 Using line separator: #'\n'#
10263 06:57:25.243736 No login prompt set.
10264 06:57:25.243799 Parsing kernel messages
10265 06:57:25.243854 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10266 06:57:25.243956 [login-action] Waiting for messages, (timeout 00:04:01)
10267 06:57:25.262668 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10268 06:57:25.266125 [ 0.000000] random: crng init done
10269 06:57:25.272740 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10270 06:57:25.275693 [ 0.000000] efi: UEFI not found.
10271 06:57:25.282744 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10272 06:57:25.289635 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10273 06:57:25.298906 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10274 06:57:25.309159 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10275 06:57:25.315522 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10276 06:57:25.322184 [ 0.000000] printk: bootconsole [mtk8250] enabled
10277 06:57:25.329167 [ 0.000000] NUMA: No NUMA configuration found
10278 06:57:25.335929 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10279 06:57:25.339160 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10280 06:57:25.342323 [ 0.000000] Zone ranges:
10281 06:57:25.349256 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10282 06:57:25.352299 [ 0.000000] DMA32 empty
10283 06:57:25.359191 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10284 06:57:25.362360 [ 0.000000] Movable zone start for each node
10285 06:57:25.365439 [ 0.000000] Early memory node ranges
10286 06:57:25.371976 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10287 06:57:25.379012 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10288 06:57:25.385521 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10289 06:57:25.392175 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10290 06:57:25.395488 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10291 06:57:25.405345 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10292 06:57:25.460421 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10293 06:57:25.467269 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10294 06:57:25.473770 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10295 06:57:25.477070 [ 0.000000] psci: probing for conduit method from DT.
10296 06:57:25.484120 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10297 06:57:25.487477 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10298 06:57:25.493936 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10299 06:57:25.497204 [ 0.000000] psci: SMC Calling Convention v1.2
10300 06:57:25.503768 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10301 06:57:25.506982 [ 0.000000] Detected VIPT I-cache on CPU0
10302 06:57:25.514102 [ 0.000000] CPU features: detected: GIC system register CPU interface
10303 06:57:25.520628 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10304 06:57:25.527306 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10305 06:57:25.533940 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10306 06:57:25.540473 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10307 06:57:25.546767 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10308 06:57:25.553440 [ 0.000000] alternatives: applying boot alternatives
10309 06:57:25.556663 [ 0.000000] Fallback order for Node 0: 0
10310 06:57:25.563873 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10311 06:57:25.566745 [ 0.000000] Policy zone: Normal
10312 06:57:25.590411 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12694854/extract-nfsrootfs-u46__al4,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10313 06:57:25.603401 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10314 06:57:25.613515 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10315 06:57:25.623219 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10316 06:57:25.630494 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10317 06:57:25.633099 <6>[ 0.000000] software IO TLB: area num 8.
10318 06:57:25.689891 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10319 06:57:25.839094 <6>[ 0.000000] Memory: 7949872K/8385536K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 402896K reserved, 32768K cma-reserved)
10320 06:57:25.846030 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10321 06:57:25.852558 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10322 06:57:25.855806 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10323 06:57:25.862237 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10324 06:57:25.868984 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10325 06:57:25.872501 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10326 06:57:25.882477 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10327 06:57:25.888942 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10328 06:57:25.892805 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10329 06:57:25.900559 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10330 06:57:25.903676 <6>[ 0.000000] GICv3: 608 SPIs implemented
10331 06:57:25.909883 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10332 06:57:25.913789 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10333 06:57:25.917000 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10334 06:57:25.927179 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10335 06:57:25.936667 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10336 06:57:25.949897 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10337 06:57:25.956627 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10338 06:57:25.966123 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10339 06:57:25.978777 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10340 06:57:25.985343 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10341 06:57:25.992253 <6>[ 0.009229] Console: colour dummy device 80x25
10342 06:57:26.002018 <6>[ 0.013946] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10343 06:57:26.008819 <6>[ 0.024452] pid_max: default: 32768 minimum: 301
10344 06:57:26.012022 <6>[ 0.029353] LSM: Security Framework initializing
10345 06:57:26.019035 <6>[ 0.034324] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10346 06:57:26.028399 <6>[ 0.042188] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10347 06:57:26.035635 <6>[ 0.051657] cblist_init_generic: Setting adjustable number of callback queues.
10348 06:57:26.041995 <6>[ 0.059102] cblist_init_generic: Setting shift to 3 and lim to 1.
10349 06:57:26.052090 <6>[ 0.065480] cblist_init_generic: Setting adjustable number of callback queues.
10350 06:57:26.058979 <6>[ 0.072907] cblist_init_generic: Setting shift to 3 and lim to 1.
10351 06:57:26.062055 <6>[ 0.079309] rcu: Hierarchical SRCU implementation.
10352 06:57:26.069043 <6>[ 0.084324] rcu: Max phase no-delay instances is 1000.
10353 06:57:26.075605 <6>[ 0.091349] EFI services will not be available.
10354 06:57:26.078784 <6>[ 0.096307] smp: Bringing up secondary CPUs ...
10355 06:57:26.086568 <6>[ 0.101356] Detected VIPT I-cache on CPU1
10356 06:57:26.093586 <6>[ 0.101425] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10357 06:57:26.100439 <6>[ 0.101458] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10358 06:57:26.103393 <6>[ 0.101789] Detected VIPT I-cache on CPU2
10359 06:57:26.109930 <6>[ 0.101839] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10360 06:57:26.116939 <6>[ 0.101855] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10361 06:57:26.123006 <6>[ 0.102119] Detected VIPT I-cache on CPU3
10362 06:57:26.129954 <6>[ 0.102165] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10363 06:57:26.136387 <6>[ 0.102178] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10364 06:57:26.139833 <6>[ 0.102484] CPU features: detected: Spectre-v4
10365 06:57:26.146465 <6>[ 0.102491] CPU features: detected: Spectre-BHB
10366 06:57:26.149911 <6>[ 0.102496] Detected PIPT I-cache on CPU4
10367 06:57:26.156458 <6>[ 0.102552] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10368 06:57:26.163478 <6>[ 0.102569] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10369 06:57:26.170132 <6>[ 0.102861] Detected PIPT I-cache on CPU5
10370 06:57:26.176300 <6>[ 0.102923] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10371 06:57:26.183281 <6>[ 0.102939] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10372 06:57:26.186606 <6>[ 0.103221] Detected PIPT I-cache on CPU6
10373 06:57:26.193140 <6>[ 0.103287] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10374 06:57:26.199518 <6>[ 0.103303] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10375 06:57:26.206364 <6>[ 0.103599] Detected PIPT I-cache on CPU7
10376 06:57:26.213237 <6>[ 0.103664] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10377 06:57:26.219575 <6>[ 0.103681] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10378 06:57:26.222566 <6>[ 0.103727] smp: Brought up 1 node, 8 CPUs
10379 06:57:26.226217 <6>[ 0.244981] SMP: Total of 8 processors activated.
10380 06:57:26.232752 <6>[ 0.249902] CPU features: detected: 32-bit EL0 Support
10381 06:57:26.242671 <6>[ 0.255265] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10382 06:57:26.249370 <6>[ 0.264065] CPU features: detected: Common not Private translations
10383 06:57:26.252625 <6>[ 0.270581] CPU features: detected: CRC32 instructions
10384 06:57:26.259566 <6>[ 0.275932] CPU features: detected: RCpc load-acquire (LDAPR)
10385 06:57:26.266261 <6>[ 0.281929] CPU features: detected: LSE atomic instructions
10386 06:57:26.272729 <6>[ 0.287746] CPU features: detected: Privileged Access Never
10387 06:57:26.275914 <6>[ 0.293526] CPU features: detected: RAS Extension Support
10388 06:57:26.282854 <6>[ 0.299135] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10389 06:57:26.289364 <6>[ 0.306355] CPU: All CPU(s) started at EL2
10390 06:57:26.295594 <6>[ 0.310698] alternatives: applying system-wide alternatives
10391 06:57:26.304446 <6>[ 0.321455] devtmpfs: initialized
10392 06:57:26.316795 <6>[ 0.330352] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10393 06:57:26.326231 <6>[ 0.340314] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10394 06:57:26.333417 <6>[ 0.348538] pinctrl core: initialized pinctrl subsystem
10395 06:57:26.336717 <6>[ 0.355205] DMI not present or invalid.
10396 06:57:26.343043 <6>[ 0.359614] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10397 06:57:26.352708 <6>[ 0.366373] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10398 06:57:26.359696 <6>[ 0.373960] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10399 06:57:26.369128 <6>[ 0.382189] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10400 06:57:26.372896 <6>[ 0.390432] audit: initializing netlink subsys (disabled)
10401 06:57:26.382491 <5>[ 0.396126] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10402 06:57:26.389346 <6>[ 0.396819] thermal_sys: Registered thermal governor 'step_wise'
10403 06:57:26.396124 <6>[ 0.404094] thermal_sys: Registered thermal governor 'power_allocator'
10404 06:57:26.399585 <6>[ 0.410346] cpuidle: using governor menu
10405 06:57:26.405687 <6>[ 0.421306] NET: Registered PF_QIPCRTR protocol family
10406 06:57:26.412163 <6>[ 0.426787] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10407 06:57:26.415847 <6>[ 0.433893] ASID allocator initialised with 32768 entries
10408 06:57:26.423174 <6>[ 0.440455] Serial: AMBA PL011 UART driver
10409 06:57:26.431806 <4>[ 0.449235] Trying to register duplicate clock ID: 134
10410 06:57:26.485471 <6>[ 0.506234] KASLR enabled
10411 06:57:26.500123 <6>[ 0.513863] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10412 06:57:26.506551 <6>[ 0.520874] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10413 06:57:26.513344 <6>[ 0.527363] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10414 06:57:26.519734 <6>[ 0.534370] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10415 06:57:26.526820 <6>[ 0.540856] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10416 06:57:26.533286 <6>[ 0.547859] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10417 06:57:26.540470 <6>[ 0.554345] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10418 06:57:26.546219 <6>[ 0.561348] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10419 06:57:26.549590 <6>[ 0.568811] ACPI: Interpreter disabled.
10420 06:57:26.558066 <6>[ 0.575257] iommu: Default domain type: Translated
10421 06:57:26.565213 <6>[ 0.580369] iommu: DMA domain TLB invalidation policy: strict mode
10422 06:57:26.568364 <5>[ 0.587033] SCSI subsystem initialized
10423 06:57:26.574669 <6>[ 0.591282] usbcore: registered new interface driver usbfs
10424 06:57:26.581532 <6>[ 0.597013] usbcore: registered new interface driver hub
10425 06:57:26.584735 <6>[ 0.602567] usbcore: registered new device driver usb
10426 06:57:26.591339 <6>[ 0.608682] pps_core: LinuxPPS API ver. 1 registered
10427 06:57:26.601361 <6>[ 0.613875] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10428 06:57:26.604656 <6>[ 0.623219] PTP clock support registered
10429 06:57:26.608145 <6>[ 0.627461] EDAC MC: Ver: 3.0.0
10430 06:57:26.615265 <6>[ 0.632654] FPGA manager framework
10431 06:57:26.622059 <6>[ 0.636332] Advanced Linux Sound Architecture Driver Initialized.
10432 06:57:26.625468 <6>[ 0.643100] vgaarb: loaded
10433 06:57:26.631747 <6>[ 0.646238] clocksource: Switched to clocksource arch_sys_counter
10434 06:57:26.635104 <5>[ 0.652680] VFS: Disk quotas dquot_6.6.0
10435 06:57:26.641955 <6>[ 0.656868] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10436 06:57:26.645087 <6>[ 0.664058] pnp: PnP ACPI: disabled
10437 06:57:26.653773 <6>[ 0.670726] NET: Registered PF_INET protocol family
10438 06:57:26.663636 <6>[ 0.676318] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10439 06:57:26.675064 <6>[ 0.688647] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10440 06:57:26.685076 <6>[ 0.697462] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10441 06:57:26.691408 <6>[ 0.705436] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10442 06:57:26.698162 <6>[ 0.714135] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10443 06:57:26.709889 <6>[ 0.723892] TCP: Hash tables configured (established 65536 bind 65536)
10444 06:57:26.716670 <6>[ 0.730762] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10445 06:57:26.723853 <6>[ 0.737959] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10446 06:57:26.730729 <6>[ 0.745667] NET: Registered PF_UNIX/PF_LOCAL protocol family
10447 06:57:26.736926 <6>[ 0.751803] RPC: Registered named UNIX socket transport module.
10448 06:57:26.740372 <6>[ 0.757955] RPC: Registered udp transport module.
10449 06:57:26.746768 <6>[ 0.762885] RPC: Registered tcp transport module.
10450 06:57:26.754152 <6>[ 0.767819] RPC: Registered tcp NFSv4.1 backchannel transport module.
10451 06:57:26.757308 <6>[ 0.774482] PCI: CLS 0 bytes, default 64
10452 06:57:26.760719 <6>[ 0.778833] Unpacking initramfs...
10453 06:57:26.778054 <6>[ 0.790823] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10454 06:57:26.787281 <6>[ 0.799468] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10455 06:57:26.791057 <6>[ 0.808318] kvm [1]: IPA Size Limit: 40 bits
10456 06:57:26.797100 <6>[ 0.812848] kvm [1]: GICv3: no GICV resource entry
10457 06:57:26.800491 <6>[ 0.817866] kvm [1]: disabling GICv2 emulation
10458 06:57:26.807338 <6>[ 0.822551] kvm [1]: GIC system register CPU interface enabled
10459 06:57:26.810737 <6>[ 0.828736] kvm [1]: vgic interrupt IRQ18
10460 06:57:26.817436 <6>[ 0.833094] kvm [1]: VHE mode initialized successfully
10461 06:57:26.823519 <5>[ 0.839586] Initialise system trusted keyrings
10462 06:57:26.830832 <6>[ 0.844429] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10463 06:57:26.837751 <6>[ 0.854377] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10464 06:57:26.844719 <5>[ 0.860825] NFS: Registering the id_resolver key type
10465 06:57:26.848041 <5>[ 0.866130] Key type id_resolver registered
10466 06:57:26.854602 <5>[ 0.870547] Key type id_legacy registered
10467 06:57:26.861316 <6>[ 0.874831] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10468 06:57:26.867671 <6>[ 0.881754] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10469 06:57:26.874063 <6>[ 0.889482] 9p: Installing v9fs 9p2000 file system support
10470 06:57:26.910614 <5>[ 0.926920] Key type asymmetric registered
10471 06:57:26.913687 <5>[ 0.931252] Asymmetric key parser 'x509' registered
10472 06:57:26.923428 <6>[ 0.936395] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10473 06:57:26.926791 <6>[ 0.944012] io scheduler mq-deadline registered
10474 06:57:26.929960 <6>[ 0.948788] io scheduler kyber registered
10475 06:57:26.949539 <6>[ 0.965956] EINJ: ACPI disabled.
10476 06:57:26.981450 <4>[ 0.991566] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10477 06:57:26.991229 <4>[ 1.002181] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10478 06:57:27.006450 <6>[ 1.023053] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10479 06:57:27.014643 <6>[ 1.031164] printk: console [ttyS0] disabled
10480 06:57:27.042453 <6>[ 1.055811] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10481 06:57:27.049404 <6>[ 1.065285] printk: console [ttyS0] enabled
10482 06:57:27.052447 <6>[ 1.065285] printk: console [ttyS0] enabled
10483 06:57:27.059582 <6>[ 1.074180] printk: bootconsole [mtk8250] disabled
10484 06:57:27.062904 <6>[ 1.074180] printk: bootconsole [mtk8250] disabled
10485 06:57:27.069569 <6>[ 1.085439] SuperH (H)SCI(F) driver initialized
10486 06:57:27.072727 <6>[ 1.090742] msm_serial: driver initialized
10487 06:57:27.086298 <6>[ 1.099698] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10488 06:57:27.096567 <6>[ 1.108244] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10489 06:57:27.103208 <6>[ 1.116785] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10490 06:57:27.112803 <6>[ 1.125414] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10491 06:57:27.122629 <6>[ 1.134122] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10492 06:57:27.129761 <6>[ 1.142841] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10493 06:57:27.140149 <6>[ 1.151383] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10494 06:57:27.146179 <6>[ 1.160196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10495 06:57:27.155325 <6>[ 1.168741] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10496 06:57:27.166948 <6>[ 1.184296] loop: module loaded
10497 06:57:27.173871 <6>[ 1.190307] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10498 06:57:27.196805 <4>[ 1.213718] mtk-pmic-keys: Failed to locate of_node [id: -1]
10499 06:57:27.203267 <6>[ 1.220698] megasas: 07.719.03.00-rc1
10500 06:57:27.213771 <6>[ 1.230767] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10501 06:57:27.220703 <6>[ 1.237661] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10502 06:57:27.237296 <6>[ 1.254240] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10503 06:57:27.293702 <6>[ 1.304455] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10504 06:57:27.506083 <6>[ 1.523238] Freeing initrd memory: 17380K
10505 06:57:27.516797 <6>[ 1.533705] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10506 06:57:27.527266 <6>[ 1.544603] tun: Universal TUN/TAP device driver, 1.6
10507 06:57:27.530552 <6>[ 1.550677] thunder_xcv, ver 1.0
10508 06:57:27.534359 <6>[ 1.554174] thunder_bgx, ver 1.0
10509 06:57:27.537390 <6>[ 1.557669] nicpf, ver 1.0
10510 06:57:27.548051 <6>[ 1.561668] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10511 06:57:27.551066 <6>[ 1.569144] hns3: Copyright (c) 2017 Huawei Corporation.
10512 06:57:27.557472 <6>[ 1.574729] hclge is initializing
10513 06:57:27.560860 <6>[ 1.578309] e1000: Intel(R) PRO/1000 Network Driver
10514 06:57:27.567990 <6>[ 1.583438] e1000: Copyright (c) 1999-2006 Intel Corporation.
10515 06:57:27.571191 <6>[ 1.589449] e1000e: Intel(R) PRO/1000 Network Driver
10516 06:57:27.577639 <6>[ 1.594665] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10517 06:57:27.584627 <6>[ 1.600849] igb: Intel(R) Gigabit Ethernet Network Driver
10518 06:57:27.591124 <6>[ 1.606499] igb: Copyright (c) 2007-2014 Intel Corporation.
10519 06:57:27.597584 <6>[ 1.612337] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10520 06:57:27.604325 <6>[ 1.618856] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10521 06:57:27.607382 <6>[ 1.625315] sky2: driver version 1.30
10522 06:57:27.613863 <6>[ 1.630308] VFIO - User Level meta-driver version: 0.3
10523 06:57:27.621383 <6>[ 1.638534] usbcore: registered new interface driver usb-storage
10524 06:57:27.628166 <6>[ 1.644976] usbcore: registered new device driver onboard-usb-hub
10525 06:57:27.636975 <6>[ 1.654098] mt6397-rtc mt6359-rtc: registered as rtc0
10526 06:57:27.646784 <6>[ 1.659563] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:54:44 UTC (1706943284)
10527 06:57:27.650128 <6>[ 1.669118] i2c_dev: i2c /dev entries driver
10528 06:57:27.666581 <6>[ 1.680736] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10529 06:57:27.686835 <6>[ 1.703710] cpu cpu0: EM: created perf domain
10530 06:57:27.689913 <6>[ 1.708654] cpu cpu4: EM: created perf domain
10531 06:57:27.697152 <6>[ 1.714221] sdhci: Secure Digital Host Controller Interface driver
10532 06:57:27.703627 <6>[ 1.720652] sdhci: Copyright(c) Pierre Ossman
10533 06:57:27.710614 <6>[ 1.725603] Synopsys Designware Multimedia Card Interface Driver
10534 06:57:27.717439 <6>[ 1.732243] sdhci-pltfm: SDHCI platform and OF driver helper
10535 06:57:27.720687 <6>[ 1.732287] mmc0: CQHCI version 5.10
10536 06:57:27.727341 <6>[ 1.742319] ledtrig-cpu: registered to indicate activity on CPUs
10537 06:57:27.734070 <6>[ 1.749409] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10538 06:57:27.740485 <6>[ 1.756466] usbcore: registered new interface driver usbhid
10539 06:57:27.743619 <6>[ 1.762288] usbhid: USB HID core driver
10540 06:57:27.750284 <6>[ 1.766479] spi_master spi0: will run message pump with realtime priority
10541 06:57:27.793885 <6>[ 1.804670] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10542 06:57:27.813640 <6>[ 1.820414] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10543 06:57:27.816837 <6>[ 1.834436] mmc0: Command Queue Engine enabled
10544 06:57:27.823325 <6>[ 1.839202] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10545 06:57:27.830287 <6>[ 1.845916] cros-ec-spi spi0.0: Chrome EC device registered
10546 06:57:27.833738 <6>[ 1.846560] mmcblk0: mmc0:0001 DA4128 116 GiB
10547 06:57:27.844911 <6>[ 1.862387] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10548 06:57:27.852870 <6>[ 1.869976] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10549 06:57:27.859434 <6>[ 1.875903] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10550 06:57:27.866471 <6>[ 1.882016] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10551 06:57:27.876525 <6>[ 1.888425] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10552 06:57:27.882931 <6>[ 1.899137] NET: Registered PF_PACKET protocol family
10553 06:57:27.886275 <6>[ 1.904539] 9pnet: Installing 9P2000 support
10554 06:57:27.893182 <5>[ 1.909103] Key type dns_resolver registered
10555 06:57:27.896146 <6>[ 1.914082] registered taskstats version 1
10556 06:57:27.899377 <5>[ 1.918467] Loading compiled-in X.509 certificates
10557 06:57:27.932423 <4>[ 1.943303] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10558 06:57:27.942853 <4>[ 1.954317] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10559 06:57:27.949550 <3>[ 1.964876] debugfs: File 'uA_load' in directory '/' already present!
10560 06:57:27.956271 <3>[ 1.971594] debugfs: File 'min_uV' in directory '/' already present!
10561 06:57:27.962928 <3>[ 1.978223] debugfs: File 'max_uV' in directory '/' already present!
10562 06:57:27.969578 <3>[ 1.984836] debugfs: File 'constraint_flags' in directory '/' already present!
10563 06:57:27.980694 <3>[ 1.994454] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10564 06:57:27.990416 <6>[ 2.007861] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10565 06:57:27.997318 <6>[ 2.014645] xhci-mtk 11200000.usb: xHCI Host Controller
10566 06:57:28.004062 <6>[ 2.020147] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10567 06:57:28.014121 <6>[ 2.027990] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10568 06:57:28.020780 <6>[ 2.037409] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10569 06:57:28.027172 <6>[ 2.043471] xhci-mtk 11200000.usb: xHCI Host Controller
10570 06:57:28.034180 <6>[ 2.048946] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10571 06:57:28.040557 <6>[ 2.056597] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10572 06:57:28.047459 <6>[ 2.064263] hub 1-0:1.0: USB hub found
10573 06:57:28.050673 <6>[ 2.068277] hub 1-0:1.0: 1 port detected
10574 06:57:28.057547 <6>[ 2.072549] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10575 06:57:28.063871 <6>[ 2.081082] hub 2-0:1.0: USB hub found
10576 06:57:28.066838 <6>[ 2.085088] hub 2-0:1.0: 1 port detected
10577 06:57:28.076831 <6>[ 2.093884] mtk-msdc 11f70000.mmc: Got CD GPIO
10578 06:57:28.088001 <6>[ 2.101755] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10579 06:57:28.094580 <6>[ 2.109792] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10580 06:57:28.104545 <4>[ 2.117779] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10581 06:57:28.114461 <6>[ 2.127318] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10582 06:57:28.121261 <6>[ 2.135420] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10583 06:57:28.127967 <6>[ 2.143452] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10584 06:57:28.137648 <6>[ 2.151380] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10585 06:57:28.144816 <6>[ 2.159197] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10586 06:57:28.154960 <6>[ 2.167026] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10587 06:57:28.164636 <6>[ 2.177446] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10588 06:57:28.171609 <6>[ 2.185832] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10589 06:57:28.181549 <6>[ 2.194174] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10590 06:57:28.188449 <6>[ 2.202527] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10591 06:57:28.198278 <6>[ 2.210866] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10592 06:57:28.204813 <6>[ 2.219215] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10593 06:57:28.214976 <6>[ 2.227556] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10594 06:57:28.221330 <6>[ 2.235906] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10595 06:57:28.231153 <6>[ 2.244245] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10596 06:57:28.238398 <6>[ 2.252600] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10597 06:57:28.248096 <6>[ 2.260938] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10598 06:57:28.254832 <6>[ 2.269277] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10599 06:57:28.264546 <6>[ 2.277615] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10600 06:57:28.271324 <6>[ 2.285953] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10601 06:57:28.281558 <6>[ 2.294291] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10602 06:57:28.287841 <6>[ 2.303050] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10603 06:57:28.294509 <6>[ 2.310016] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10604 06:57:28.301123 <6>[ 2.316770] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10605 06:57:28.307585 <6>[ 2.323524] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10606 06:57:28.314061 <6>[ 2.330456] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10607 06:57:28.323995 <6>[ 2.337297] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10608 06:57:28.334091 <6>[ 2.346427] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10609 06:57:28.343908 <6>[ 2.355545] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10610 06:57:28.350904 <6>[ 2.364862] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10611 06:57:28.360519 <6>[ 2.374335] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10612 06:57:28.370867 <6>[ 2.383804] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10613 06:57:28.381032 <6>[ 2.392923] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10614 06:57:28.390703 <6>[ 2.402389] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10615 06:57:28.397079 <6>[ 2.411507] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10616 06:57:28.407060 <6>[ 2.420800] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10617 06:57:28.420439 <6>[ 2.430960] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10618 06:57:28.426767 <6>[ 2.442496] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10619 06:57:28.434833 <6>[ 2.452223] Trying to probe devices needed for running init ...
10620 06:57:28.456518 <6>[ 2.470541] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10621 06:57:28.483810 <6>[ 2.501363] hub 2-1:1.0: USB hub found
10622 06:57:28.487220 <6>[ 2.505794] hub 2-1:1.0: 3 ports detected
10623 06:57:28.495595 <6>[ 2.512703] hub 2-1:1.0: USB hub found
10624 06:57:28.498771 <6>[ 2.517174] hub 2-1:1.0: 3 ports detected
10625 06:57:28.608580 <6>[ 2.622538] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10626 06:57:28.767546 <6>[ 2.784466] hub 1-1:1.0: USB hub found
10627 06:57:28.770695 <6>[ 2.788966] hub 1-1:1.0: 4 ports detected
10628 06:57:28.781059 <6>[ 2.797856] hub 1-1:1.0: USB hub found
10629 06:57:28.783581 <6>[ 2.802464] hub 1-1:1.0: 4 ports detected
10630 06:57:28.852751 <6>[ 2.866720] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10631 06:57:29.104589 <6>[ 3.118596] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10632 06:57:29.237207 <6>[ 3.254511] hub 1-1.4:1.0: USB hub found
10633 06:57:29.240213 <6>[ 3.259191] hub 1-1.4:1.0: 2 ports detected
10634 06:57:29.250628 <6>[ 3.267914] hub 1-1.4:1.0: USB hub found
10635 06:57:29.253736 <6>[ 3.272559] hub 1-1.4:1.0: 2 ports detected
10636 06:57:29.552104 <6>[ 3.566530] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10637 06:57:29.744158 <6>[ 3.758527] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10638 06:57:40.713879 <6>[ 14.735530] ALSA device list:
10639 06:57:40.720068 <6>[ 14.738821] No soundcards found.
10640 06:57:40.727979 <6>[ 14.746744] Freeing unused kernel memory: 8448K
10641 06:57:40.731189 <6>[ 14.751746] Run /init as init process
10642 06:57:40.742746 Loading, please wait...
10643 06:57:40.763914 Starting version 247.3-7+deb11u2
10644 06:57:40.989429 <6>[ 15.004834] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10645 06:57:41.004504 <6>[ 15.023472] remoteproc remoteproc0: scp is available
10646 06:57:41.011133 <6>[ 15.029889] remoteproc remoteproc0: powering up scp
10647 06:57:41.018078 <6>[ 15.034989] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10648 06:57:41.027745 <6>[ 15.035082] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10649 06:57:41.034697 <6>[ 15.043834] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10650 06:57:41.044395 <3>[ 15.044032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10651 06:57:41.051295 <3>[ 15.044047] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10652 06:57:41.060771 <3>[ 15.044055] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10653 06:57:41.064491 <6>[ 15.051026] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10654 06:57:41.074581 <3>[ 15.059828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 06:57:41.084068 <6>[ 15.067835] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10656 06:57:41.090728 <6>[ 15.076562] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10657 06:57:41.097418 <3>[ 15.084083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 06:57:41.104322 <6>[ 15.116717] mc: Linux media interface: v0.10
10659 06:57:41.111282 <6>[ 15.117729] usbcore: registered new device driver r8152-cfgselector
10660 06:57:41.118083 <4>[ 15.117990] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10661 06:57:41.124818 <4>[ 15.120532] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10662 06:57:41.131534 <4>[ 15.120603] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10663 06:57:41.138329 <4>[ 15.120603] Fallback method does not support PEC.
10664 06:57:41.145857 <3>[ 15.122305] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 06:57:41.155964 <3>[ 15.138024] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10666 06:57:41.162893 <3>[ 15.140777] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 06:57:41.169379 <6>[ 15.150778] videodev: Linux video capture interface: v2.00
10668 06:57:41.175553 <3>[ 15.161714] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 06:57:41.185803 <3>[ 15.161839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 06:57:41.192177 <3>[ 15.169169] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10671 06:57:41.202634 <6>[ 15.176266] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10672 06:57:41.209160 <6>[ 15.176274] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10673 06:57:41.218932 <3>[ 15.178701] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10674 06:57:41.222416 <6>[ 15.186704] remoteproc remoteproc0: remote processor scp is now up
10675 06:57:41.232384 <6>[ 15.187903] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10676 06:57:41.239134 <6>[ 15.189519] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10677 06:57:41.248920 <6>[ 15.192130] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10678 06:57:41.255570 <3>[ 15.192540] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10679 06:57:41.261599 <6>[ 15.200641] pci_bus 0000:00: root bus resource [bus 00-ff]
10680 06:57:41.268188 <3>[ 15.208707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10681 06:57:41.278562 <3>[ 15.208762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 06:57:41.285024 <6>[ 15.217485] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10683 06:57:41.291349 <3>[ 15.225993] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10684 06:57:41.301527 <3>[ 15.225997] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 06:57:41.308187 <3>[ 15.226000] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 06:57:41.318086 <3>[ 15.226002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 06:57:41.324188 <3>[ 15.226025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 06:57:41.334388 <6>[ 15.230574] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10689 06:57:41.344721 <6>[ 15.233045] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10690 06:57:41.351390 <6>[ 15.234593] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10691 06:57:41.361110 <6>[ 15.235115] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10692 06:57:41.370916 <6>[ 15.235423] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10693 06:57:41.380733 <4>[ 15.258026] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10694 06:57:41.387415 <6>[ 15.262880] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10695 06:57:41.394193 <4>[ 15.271005] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10696 06:57:41.397768 <6>[ 15.279789] Bluetooth: Core ver 2.22
10697 06:57:41.407643 <6>[ 15.285202] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10698 06:57:41.410772 <6>[ 15.293257] NET: Registered PF_BLUETOOTH protocol family
10699 06:57:41.417931 <6>[ 15.293855] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10700 06:57:41.430832 <6>[ 15.295208] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10701 06:57:41.437260 <6>[ 15.295440] usbcore: registered new interface driver uvcvideo
10702 06:57:41.440518 <6>[ 15.301163] pci 0000:00:00.0: supports D1 D2
10703 06:57:41.447364 <6>[ 15.308209] Bluetooth: HCI device and connection manager initialized
10704 06:57:41.453936 <6>[ 15.316288] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10705 06:57:41.460606 <6>[ 15.322419] r8152 2-1.3:1.0 eth0: v1.12.13
10706 06:57:41.463803 <6>[ 15.322458] usbcore: registered new interface driver r8152
10707 06:57:41.470927 <6>[ 15.324378] Bluetooth: HCI socket layer initialized
10708 06:57:41.477432 <6>[ 15.324848] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10709 06:57:41.484337 <6>[ 15.333378] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10710 06:57:41.490660 <6>[ 15.340530] Bluetooth: L2CAP socket layer initialized
10711 06:57:41.497544 <6>[ 15.340900] usbcore: registered new interface driver cdc_ether
10712 06:57:41.503618 <6>[ 15.348723] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10713 06:57:41.506958 <6>[ 15.357906] Bluetooth: SCO socket layer initialized
10714 06:57:41.513504 <6>[ 15.358081] usbcore: registered new interface driver r8153_ecm
10715 06:57:41.520327 <6>[ 15.367820] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10716 06:57:41.527304 <6>[ 15.382272] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10717 06:57:41.533674 <6>[ 15.386221] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10718 06:57:41.540528 <6>[ 15.443038] usbcore: registered new interface driver btusb
10719 06:57:41.550128 <4>[ 15.444063] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10720 06:57:41.556894 <3>[ 15.444076] Bluetooth: hci0: Failed to load firmware file (-2)
10721 06:57:41.563890 <3>[ 15.444081] Bluetooth: hci0: Failed to set up firmware (-2)
10722 06:57:41.573888 <4>[ 15.444086] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10723 06:57:41.580433 <6>[ 15.454923] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10724 06:57:41.586938 <6>[ 15.604814] pci 0000:01:00.0: supports D1 D2
10725 06:57:41.593308 <6>[ 15.609333] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10726 06:57:41.611444 <6>[ 15.626470] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10727 06:57:41.617914 <6>[ 15.633367] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10728 06:57:41.624264 <6>[ 15.641447] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10729 06:57:41.634539 <6>[ 15.649443] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10730 06:57:41.641052 <6>[ 15.657444] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10731 06:57:41.651222 <6>[ 15.665444] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10732 06:57:41.654379 <6>[ 15.673444] pci 0000:00:00.0: PCI bridge to [bus 01]
10733 06:57:41.664450 <6>[ 15.678660] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10734 06:57:41.671111 <6>[ 15.686783] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10735 06:57:41.678082 <6>[ 15.693601] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10736 06:57:41.683976 <6>[ 15.700457] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10737 06:57:41.698660 <5>[ 15.713950] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10738 06:57:41.719479 <5>[ 15.734905] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10739 06:57:41.726178 <5>[ 15.742296] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10740 06:57:41.735931 <4>[ 15.750789] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10741 06:57:41.742798 <6>[ 15.759673] cfg80211: failed to load regulatory.db
10742 06:57:41.790733 <6>[ 15.806166] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10743 06:57:41.797093 <6>[ 15.813685] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10744 06:57:41.821586 <6>[ 15.840327] mt7921e 0000:01:00.0: ASIC revision: 79610010
10745 06:57:41.922779 <6>[ 15.938105] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10746 06:57:41.926092 <6>[ 15.938105]
10747 06:57:41.929171 Begin: Loading essential drivers ... done.
10748 06:57:41.932308 Begin: Running /scripts/init-premount ... done.
10749 06:57:41.939202 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10750 06:57:41.949125 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10751 06:57:41.952598 Device /sys/class/net/enx00e04c787aaa found
10752 06:57:41.952679 done.
10753 06:57:42.011156 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10754 06:57:42.192593 <6>[ 16.208077] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10755 06:57:42.898299 <6>[ 16.917331] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10756 06:57:43.038240 <6>[ 17.057292] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10757 06:57:43.140742 IP-Config: no response after 2 secs - giving up
10758 06:57:43.179377 IP-Config: wlp1s0 hardware address d8:f3:bc:78:17:6f mtu 1500 DHCP
10759 06:57:43.895732 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10760 06:57:43.902618 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10761 06:57:43.909139 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10762 06:57:43.915944 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10763 06:57:43.922320 host : mt8192-asurada-spherion-r0-cbg-0
10764 06:57:43.929103 domain : lava-rack
10765 06:57:43.932274 rootserver: 192.168.201.1 rootpath:
10766 06:57:43.935500 filename :
10767 06:57:44.087044 done.
10768 06:57:44.093578 Begin: Running /scripts/nfs-bottom ... done.
10769 06:57:44.116966 Begin: Running /scripts/init-bottom ... done.
10770 06:57:45.277818 <6>[ 19.297053] NET: Registered PF_INET6 protocol family
10771 06:57:45.285415 <6>[ 19.304712] Segment Routing with IPv6
10772 06:57:45.288587 <6>[ 19.308722] In-situ OAM (IOAM) with IPv6
10773 06:57:45.433127 <30>[ 19.432424] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10774 06:57:45.439409 <30>[ 19.456856] systemd[1]: Detected architecture arm64.
10775 06:57:45.456707
10776 06:57:45.459957 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10777 06:57:45.460109
10778 06:57:45.476936 <30>[ 19.496242] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10779 06:57:46.235022 <30>[ 20.250833] systemd[1]: Queued start job for default target Graphical Interface.
10780 06:57:46.257984 <30>[ 20.276904] systemd[1]: Created slice system-getty.slice.
10781 06:57:46.264179 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10782 06:57:46.280989 <30>[ 20.299930] systemd[1]: Created slice system-modprobe.slice.
10783 06:57:46.287414 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10784 06:57:46.304197 <30>[ 20.323771] systemd[1]: Created slice system-serial\x2dgetty.slice.
10785 06:57:46.314797 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10786 06:57:46.328204 <30>[ 20.347580] systemd[1]: Created slice User and Session Slice.
10787 06:57:46.334589 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10788 06:57:46.355148 <30>[ 20.371296] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10789 06:57:46.365378 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10790 06:57:46.383308 <30>[ 20.399296] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10791 06:57:46.389870 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10792 06:57:46.414022 <30>[ 20.426657] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10793 06:57:46.420671 <30>[ 20.438798] systemd[1]: Reached target Local Encrypted Volumes.
10794 06:57:46.426795 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10795 06:57:46.443649 <30>[ 20.463088] systemd[1]: Reached target Paths.
10796 06:57:46.447017 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10797 06:57:46.463775 <30>[ 20.482971] systemd[1]: Reached target Remote File Systems.
10798 06:57:46.470640 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10799 06:57:46.487685 <30>[ 20.506899] systemd[1]: Reached target Slices.
10800 06:57:46.494123 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10801 06:57:46.507126 <30>[ 20.526565] systemd[1]: Reached target Swap.
10802 06:57:46.510366 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10803 06:57:46.530971 <30>[ 20.547017] systemd[1]: Listening on initctl Compatibility Named Pipe.
10804 06:57:46.537680 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10805 06:57:46.544236 <30>[ 20.563073] systemd[1]: Listening on Journal Audit Socket.
10806 06:57:46.550909 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10807 06:57:46.568344 <30>[ 20.587669] systemd[1]: Listening on Journal Socket (/dev/log).
10808 06:57:46.575004 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10809 06:57:46.591642 <30>[ 20.611097] systemd[1]: Listening on Journal Socket.
10810 06:57:46.598090 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10811 06:57:46.612540 <30>[ 20.631867] systemd[1]: Listening on Network Service Netlink Socket.
10812 06:57:46.622556 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10813 06:57:46.637595 <30>[ 20.656895] systemd[1]: Listening on udev Control Socket.
10814 06:57:46.644030 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10815 06:57:46.659749 <30>[ 20.678969] systemd[1]: Listening on udev Kernel Socket.
10816 06:57:46.666641 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10817 06:57:46.719730 <30>[ 20.738726] systemd[1]: Mounting Huge Pages File System...
10818 06:57:46.725963 Mounting [0;1;39mHuge Pages File System[0m...
10819 06:57:46.743528 <30>[ 20.762748] systemd[1]: Mounting POSIX Message Queue File System...
10820 06:57:46.750438 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10821 06:57:46.771691 <30>[ 20.790983] systemd[1]: Mounting Kernel Debug File System...
10822 06:57:46.778458 Mounting [0;1;39mKernel Debug File System[0m...
10823 06:57:46.795202 <30>[ 20.811309] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10824 06:57:46.855609 <30>[ 20.871438] systemd[1]: Starting Create list of static device nodes for the current kernel...
10825 06:57:46.861923 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10826 06:57:46.882077 <30>[ 20.901622] systemd[1]: Starting Load Kernel Module configfs...
10827 06:57:46.888959 Starting [0;1;39mLoad Kernel Module configfs[0m...
10828 06:57:46.907782 <30>[ 20.927130] systemd[1]: Starting Load Kernel Module drm...
10829 06:57:46.914455 Starting [0;1;39mLoad Kernel Module drm[0m...
10830 06:57:46.930435 <30>[ 20.949803] systemd[1]: Starting Load Kernel Module fuse...
10831 06:57:46.936695 Starting [0;1;39mLoad Kernel Module fuse[0m...
10832 06:57:46.969236 <30>[ 20.985501] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10833 06:57:46.976243 <6>[ 20.995982] fuse: init (API version 7.37)
10834 06:57:46.983716 <30>[ 21.003071] systemd[1]: Starting Journal Service...
10835 06:57:46.986751 Starting [0;1;39mJournal Service[0m...
10836 06:57:47.008421 <30>[ 21.027650] systemd[1]: Starting Load Kernel Modules...
10837 06:57:47.014693 Starting [0;1;39mLoad Kernel Modules[0m...
10838 06:57:47.033925 <30>[ 21.049987] systemd[1]: Starting Remount Root and Kernel File Systems...
10839 06:57:47.040718 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10840 06:57:47.059201 <30>[ 21.078583] systemd[1]: Starting Coldplug All udev Devices...
10841 06:57:47.066111 Starting [0;1;39mColdplug All udev Devices[0m...
10842 06:57:47.086640 <30>[ 21.105550] systemd[1]: Mounted Huge Pages File System.
10843 06:57:47.092966 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10844 06:57:47.107717 <30>[ 21.127257] systemd[1]: Mounted POSIX Message Queue File System.
10845 06:57:47.114213 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10846 06:57:47.130890 <3>[ 21.146875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10847 06:57:47.137207 <30>[ 21.156445] systemd[1]: Mounted Kernel Debug File System.
10848 06:57:47.144084 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10849 06:57:47.164172 <30>[ 21.180144] systemd[1]: Finished Create list of static device nodes for the current kernel.
10850 06:57:47.177673 [[0;32m OK [0m] Finished [0<3>[ 21.191230] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10851 06:57:47.181031 ;1;39mCreate list of st… nodes for the current kernel[0m.
10852 06:57:47.200401 <30>[ 21.219698] systemd[1]: modprobe@configfs.service: Succeeded.
10853 06:57:47.207784 <30>[ 21.226633] systemd[1]: Finished Load Kernel Module configfs.
10854 06:57:47.213808 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10855 06:57:47.234621 <3>[ 21.250580] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10856 06:57:47.241460 <30>[ 21.251874] systemd[1]: modprobe@drm.service: Succeeded.
10857 06:57:47.248277 <30>[ 21.265738] systemd[1]: Finished Load Kernel Module drm.
10858 06:57:47.254600 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10859 06:57:47.265413 <3>[ 21.280737] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 06:57:47.272391 <30>[ 21.291568] systemd[1]: modprobe@fuse.service: Succeeded.
10861 06:57:47.279679 <30>[ 21.298424] systemd[1]: Finished Load Kernel Module fuse.
10862 06:57:47.286541 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10863 06:57:47.296513 <3>[ 21.310368] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10864 06:57:47.303157 <30>[ 21.321531] systemd[1]: Finished Load Kernel Modules.
10865 06:57:47.309855 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10866 06:57:47.327550 <3>[ 21.343522] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10867 06:57:47.334678 <30>[ 21.344196] systemd[1]: Finished Remount Root and Kernel File Systems.
10868 06:57:47.340827 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10869 06:57:47.359190 <3>[ 21.374830] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10870 06:57:47.391558 <3>[ 21.407660] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 06:57:47.403272 <30>[ 21.422719] systemd[1]: Mounting FUSE Control File System...
10872 06:57:47.410750 Mounting [0;1;39mFUSE Control File System[0m...
10873 06:57:47.421721 <3>[ 21.437892] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 06:57:47.430195 <30>[ 21.449586] systemd[1]: Mounting Kernel Configuration File System...
10875 06:57:47.437122 Mounting [0;1;39mKernel Configuration File System[0m...
10876 06:57:47.452146 <3>[ 21.467888] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 06:57:47.463843 <30>[ 21.479964] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10878 06:57:47.473645 <30>[ 21.489049] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10879 06:57:47.523705 <30>[ 21.543124] systemd[1]: Starting Load/Save Random Seed...
10880 06:57:47.530634 Starting [0;1;39mLoad/Save Random Seed[0m...
10881 06:57:47.548071 <30>[ 21.567231] systemd[1]: Starting Apply Kernel Variables...
10882 06:57:47.554675 Starting [0;1;39mApply Kernel Variables[0m...
10883 06:57:47.573433 <4>[ 21.582972] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10884 06:57:47.583443 <3>[ 21.598676] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10885 06:57:47.587142 <30>[ 21.604234] systemd[1]: Starting Create System Users...
10886 06:57:47.593427 Starting [0;1;39mCreate System Users[0m...
10887 06:57:47.609447 <30>[ 21.628291] systemd[1]: Started Journal Service.
10888 06:57:47.612882 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10889 06:57:47.635897 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10890 06:57:47.647214 See 'systemctl status systemd-udev-trigger.service' for details.
10891 06:57:47.663859 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10892 06:57:47.679774 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10893 06:57:47.696682 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10894 06:57:47.713257 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10895 06:57:47.728879 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10896 06:57:47.776152 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10897 06:57:47.793648 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10898 06:57:47.819081 <46>[ 21.834899] systemd-journald[299]: Received client request to flush runtime journal.
10899 06:57:47.857836 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10900 06:57:47.876228 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10901 06:57:47.895762 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10902 06:57:47.960016 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10903 06:57:49.201896 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10904 06:57:49.247752 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10905 06:57:49.267912 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10906 06:57:49.289360 Starting [0;1;39mNetwork Service[0m...
10907 06:57:49.628702 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10908 06:57:49.648802 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10909 06:57:49.711643 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10910 06:57:49.949050 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10911 06:57:49.970639 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10912 06:57:50.003925 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10913 06:57:50.024019 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10914 06:57:50.044114 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10915 06:57:50.059820 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10916 06:57:50.085325 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10917 06:57:50.163823 Starting [0;1;39mNetwork Name Resolution[0m...
10918 06:57:50.194371 Starting [0;1;39mNetwork Time Synchronization[0m...
10919 06:57:50.215747 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10920 06:57:50.260198 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10921 06:57:50.402733 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10922 06:57:50.419661 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10923 06:57:50.442447 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10924 06:57:50.459121 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10925 06:57:50.479046 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10926 06:57:50.564489 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10927 06:57:50.613965 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10928 06:57:50.653203 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10929 06:57:50.678221 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10930 06:57:50.690763 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10931 06:57:50.711931 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10932 06:57:50.726532 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10933 06:57:50.743164 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10934 06:57:50.799884 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10935 06:57:50.857848 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10936 06:57:50.890719 Starting [0;1;39mUser Login Management[0m...
10937 06:57:50.908573 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10938 06:57:50.924267 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10939 06:57:50.941708 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10940 06:57:50.983782 Starting [0;1;39mPermit User Sessions[0m...
10941 06:57:51.137222 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10942 06:57:51.190882 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10943 06:57:51.216588 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10944 06:57:51.238509 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10945 06:57:51.261140 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10946 06:57:51.280429 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10947 06:57:51.303153 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10948 06:57:51.325504 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10949 06:57:51.389083 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10950 06:57:51.425013 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10951 06:57:51.481177
10952 06:57:51.481339
10953 06:57:51.484481 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10954 06:57:51.484556
10955 06:57:51.487639 debian-bullseye-arm64 login: root (automatic login)
10956 06:57:51.487743
10957 06:57:51.487832
10958 06:57:51.738956 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
10959 06:57:51.739137
10960 06:57:51.745402 The programs included with the Debian GNU/Linux system are free software;
10961 06:57:51.752016 the exact distribution terms for each program are described in the
10962 06:57:51.755771 individual files in /usr/share/doc/*/copyright.
10963 06:57:51.755889
10964 06:57:51.761903 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10965 06:57:51.765531 permitted by applicable law.
10966 06:57:51.812988 Matched prompt #10: / #
10968 06:57:51.813236 Setting prompt string to ['/ #']
10969 06:57:51.813354 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10971 06:57:51.813552 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10972 06:57:51.813638 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
10973 06:57:51.813705 Setting prompt string to ['/ #']
10974 06:57:51.813765 Forcing a shell prompt, looking for ['/ #']
10976 06:57:51.863950 / #
10977 06:57:51.864108 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10978 06:57:51.864213 Waiting using forced prompt support (timeout 00:02:30)
10979 06:57:51.869107
10980 06:57:51.869403 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10981 06:57:51.869534 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
10983 06:57:51.969890 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694854/extract-nfsrootfs-u46__al4'
10984 06:57:51.975744 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12694854/extract-nfsrootfs-u46__al4'
10986 06:57:52.076236 / # export NFS_SERVER_IP='192.168.201.1'
10987 06:57:52.081099 export NFS_SERVER_IP='192.168.201.1'
10988 06:57:52.081405 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10989 06:57:52.081526 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
10990 06:57:52.081622 end: 2 depthcharge-action (duration 00:01:25) [common]
10991 06:57:52.081715 start: 3 lava-test-retry (timeout 00:30:00) [common]
10992 06:57:52.081812 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10993 06:57:52.081920 Using namespace: common
10995 06:57:52.182268 / # #
10996 06:57:52.182453 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10997 06:57:52.187683 #
10998 06:57:52.187974 Using /lava-12694854
11000 06:57:52.288308 / # export SHELL=/bin/sh
11001 06:57:52.293917 export SHELL=/bin/sh
11003 06:57:52.394454 / # . /lava-12694854/environment
11004 06:57:52.399948 . /lava-12694854/environment
11006 06:57:52.505180 / # /lava-12694854/bin/lava-test-runner /lava-12694854/0
11007 06:57:52.505352 Test shell timeout: 10s (minimum of the action and connection timeout)
11008 06:57:52.510280 /lava-12694854/bin/lava-test-runner /lava-12694854/0
11009 06:57:52.686505 + export TESTRUN_ID=0_lc-compliance
11010 06:57:52.693543 + cd /lava-12694854/0/tests/0_lc-compliance
11011 06:57:52.693632 + cat uuid
11012 06:57:52.696752 + UUID=12694854_1.6.2.3.1
11013 06:57:52.696835 + set +x
11014 06:57:52.703118 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12694854_1.6.2.3.1>
11015 06:57:52.703377 Received signal: <STARTRUN> 0_lc-compliance 12694854_1.6.2.3.1
11016 06:57:52.703456 Starting test lava.0_lc-compliance (12694854_1.6.2.3.1)
11017 06:57:52.703541 Skipping test definition patterns.
11018 06:57:52.706111 + /usr/bin/lc-compliance-parser.sh
11019 06:57:53.868290 [0:00:27.794435375] [408] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
11020 06:57:53.871549 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11021 06:57:53.887381 [0:00:27.814048659] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11022 06:57:53.927534 [==========] Running 120 tests from 1 test suite.
11023 06:57:53.943320 [0:00:27.870844891] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11024 06:57:53.980908 [----------] Global test environment set-up.
11025 06:57:53.996163 [0:00:27.924014297] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11026 06:57:54.034895 [----------] 120 tests from CaptureTests/SingleStream
11027 06:57:54.050477 [0:00:27.978798954] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11028 06:57:54.092374 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11029 06:57:54.137296 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11030 06:57:54.137632 Received signal: <TESTSET> START CaptureTests/SingleStream
11031 06:57:54.137739 Starting test_set CaptureTests/SingleStream
11032 06:57:54.141026 Camera needs 4 requests, can't test only 1
11033 06:57:54.194768 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11034 06:57:54.251576
11035 06:57:54.316485 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (57 ms)
11036 06:57:54.388548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11037 06:57:54.388858 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11039 06:57:54.398380 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11040 06:57:54.435532 Camera needs 4 requests, can't test only 2
11041 06:57:54.477398 [0:00:28.408808718] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11042 06:57:54.493919 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11043 06:57:54.554588
11044 06:57:54.618203 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (54 ms)
11045 06:57:54.683935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11046 06:57:54.684277 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11048 06:57:54.696473 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11049 06:57:54.738228 Camera needs 4 requests, can't test only 3
11050 06:57:54.800642 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11051 06:57:54.860816
11052 06:57:54.929377 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (54 ms)
11053 06:57:54.993767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11054 06:57:54.994073 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11056 06:57:55.004616 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11057 06:57:55.043000 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (430 ms)
11058 06:57:55.110796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11059 06:57:55.111106 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11061 06:57:55.123247 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11062 06:57:55.167396 [0:00:29.104396897] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11063 06:57:55.171051 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (696 ms)
11064 06:57:55.229566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11065 06:57:55.229864 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11067 06:57:55.240283 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11068 06:57:56.414185 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1262 ms)
11069 06:57:56.423933 [0:00:30.367838125] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11070 06:57:56.472143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11071 06:57:56.472444 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11073 06:57:56.485084 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11074 06:57:58.229791 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1825 ms)
11075 06:57:58.239631 [0:00:32.192510207] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11076 06:57:58.296378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11077 06:57:58.296703 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11079 06:57:58.307907 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11080 06:58:00.954805 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2736 ms)
11081 06:58:00.964444 [0:00:34.929042546] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11082 06:58:01.026456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11083 06:58:01.026757 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11085 06:58:01.037395 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11086 06:58:05.150671 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4207 ms)
11087 06:58:05.160803 [0:00:39.136065720] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11088 06:58:05.228885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11089 06:58:05.229192 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11091 06:58:05.242347 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11092 06:58:11.727033 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6585 ms)
11093 06:58:11.737281 [0:00:45.721673163] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11094 06:58:11.792413 [0:00:45.777871883] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11095 06:58:11.809592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11096 06:58:11.809875 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11098 06:58:11.824277 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11099 06:58:11.848690 [0:00:45.834160904] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11100 06:58:11.866106 Camera needs 4 requests, can't test only 1
11101 06:58:11.902973 [0:00:45.888564451] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11102 06:58:11.925053 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11103 06:58:11.978384
11104 06:58:12.040782 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (56 ms)
11105 06:58:12.052548 <6>[ 46.078003] vpu: disabling
11106 06:58:12.055946 <6>[ 46.081263] vproc2: disabling
11107 06:58:12.061005 <6>[ 46.086472] vproc1: disabling
11108 06:58:12.064573 <6>[ 46.090022] vaud18: disabling
11109 06:58:12.072537 <6>[ 46.094564] vsram_others: disabling
11110 06:58:12.075835 <6>[ 46.098764] va09: disabling
11111 06:58:12.079222 <6>[ 46.102683] vsram_md: disabling
11112 06:58:12.082272 <6>[ 46.106756] Vgpu: disabling
11113 06:58:12.134370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11114 06:58:12.134656 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11116 06:58:12.144321 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11117 06:58:12.190658 Camera needs 4 requests, can't test only 2
11118 06:58:12.248702 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11119 06:58:12.302183
11120 06:58:12.364030 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (57 ms)
11121 06:58:12.431620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11122 06:58:12.431934 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11124 06:58:12.443105 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11125 06:58:12.484121 Camera needs 4 requests, can't test only 3
11126 06:58:12.544398 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11127 06:58:12.598286 [0:00:46.583821070] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11128 06:58:12.615248
11129 06:58:12.678647 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (54 ms)
11130 06:58:12.745590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11131 06:58:12.745900 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11133 06:58:12.760903 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11134 06:58:12.809028 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (695 ms)
11135 06:58:12.882742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11136 06:58:12.883053 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11138 06:58:12.897014 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11139 06:58:13.497050 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (909 ms)
11140 06:58:13.510347 [0:00:47.492760773] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11141 06:58:13.569648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11142 06:58:13.569942 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11144 06:58:13.584436 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11145 06:58:14.753559 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1256 ms)
11146 06:58:14.766033 [0:00:48.749549387] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11147 06:58:14.832477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11148 06:58:14.832777 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11150 06:58:14.844732 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11151 06:58:16.569795 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1817 ms)
11152 06:58:16.582762 [0:00:50.567146718] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11153 06:58:16.646811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11154 06:58:16.647117 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11156 06:58:16.659899 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11157 06:58:19.297657 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2730 ms)
11158 06:58:19.311192 [0:00:53.296710100] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11159 06:58:19.373272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11160 06:58:19.373568 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11162 06:58:19.387133 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11163 06:58:23.494917 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4197 ms)
11164 06:58:23.507719 [0:00:57.494527816] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11165 06:58:23.580028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11166 06:58:23.580376 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11168 06:58:23.592633 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11169 06:58:30.070671 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6576 ms)
11170 06:58:30.084567 [0:01:04.070762079] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11171 06:58:30.135246 [0:01:04.126251027] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11172 06:58:30.148982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11173 06:58:30.149290 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11175 06:58:30.160877 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11176 06:58:30.188027 [0:01:04.179669824] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11177 06:58:30.200875 Camera needs 4 requests, can't test only 1
11178 06:58:30.241784 [0:01:04.232878867] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11179 06:58:30.258547 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11180 06:58:30.310465
11181 06:58:30.369859 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (55 ms)
11182 06:58:30.443716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11183 06:58:30.444028 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11185 06:58:30.457584 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11186 06:58:30.503802 Camera needs 4 requests, can't test only 2
11187 06:58:30.563011 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11188 06:58:30.622167
11189 06:58:30.689771 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (55 ms)
11190 06:58:30.765740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11191 06:58:30.766061 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11193 06:58:30.778506 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11194 06:58:30.813154 Camera needs 4 requests, can't test only 3
11195 06:58:30.863682 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11196 06:58:30.925558
11197 06:58:30.934778 [0:01:04.926448906] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11198 06:58:30.988334 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (53 ms)
11199 06:58:31.056280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11200 06:58:31.056721 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11202 06:58:31.068754 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11203 06:58:31.109444 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (693 ms)
11204 06:58:31.180844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11205 06:58:31.181174 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11207 06:58:31.193197 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11208 06:58:31.835533 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (908 ms)
11209 06:58:31.848606 [0:01:05.835492253] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11210 06:58:31.912605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11211 06:58:31.912930 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11213 06:58:31.924944 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11214 06:58:33.091003 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1255 ms)
11215 06:58:33.104217 [0:01:07.091284718] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11216 06:58:33.159495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11217 06:58:33.159820 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11219 06:58:33.172652 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11220 06:58:34.907159 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1816 ms)
11221 06:58:34.920493 [0:01:08.907411408] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11222 06:58:34.980757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11223 06:58:34.981081 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11225 06:58:34.993461 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11226 06:58:37.635166 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2729 ms)
11227 06:58:37.648564 [0:01:11.635796712] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11228 06:58:37.711049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11229 06:58:37.711368 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11231 06:58:37.723086 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11232 06:58:41.831115 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4196 ms)
11233 06:58:41.844557 [0:01:15.831885021] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11234 06:58:41.904626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11235 06:58:41.904906 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11237 06:58:41.919850 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11238 06:58:48.407833 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6577 ms)
11239 06:58:48.421042 [0:01:22.408838455] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11240 06:58:48.471796 [0:01:22.463981598] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11241 06:58:48.485821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11242 06:58:48.486139 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11244 06:58:48.500042 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11245 06:58:48.525894 [0:01:22.518141466] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11246 06:58:48.544555 Camera needs 4 requests, can't test only 1
11247 06:58:48.580445 [0:01:22.572301026] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11248 06:58:48.616266 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11249 06:58:48.677571
11250 06:58:48.747268 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (55 ms)
11251 06:58:48.822464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11252 06:58:48.822795 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11254 06:58:48.838004 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11255 06:58:48.889293 Camera needs 4 requests, can't test only 2
11256 06:58:48.960426 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11257 06:58:49.025851
11258 06:58:49.096004 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (54 ms)
11259 06:58:49.172569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11260 06:58:49.172900 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11262 06:58:49.187619 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11263 06:58:49.233693 Camera needs 4 requests, can't test only 3
11264 06:58:49.277088 [0:01:23.268905506] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11265 06:58:49.303254 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11266 06:58:49.351578
11267 06:58:49.416200 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (53 ms)
11268 06:58:49.485242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11269 06:58:49.485571 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11271 06:58:49.497273 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11272 06:58:49.546941 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (695 ms)
11273 06:58:49.620415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11274 06:58:49.620765 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11276 06:58:49.632007 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11277 06:58:50.174519 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (907 ms)
11278 06:58:50.187525 [0:01:24.175852428] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11279 06:58:50.252054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11280 06:58:50.252403 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11282 06:58:50.265592 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11283 06:58:51.430252 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1256 ms)
11284 06:58:51.443688 [0:01:25.431865865] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11285 06:58:51.506953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11286 06:58:51.507286 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11288 06:58:51.521207 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11289 06:58:53.246324 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1816 ms)
11290 06:58:53.259531 [0:01:27.248075235] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11291 06:58:53.330924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11292 06:58:53.331252 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11294 06:58:53.344207 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11295 06:58:55.972349 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2726 ms)
11296 06:58:55.985879 [0:01:29.974144902] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11297 06:58:56.056452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11298 06:58:56.056783 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11300 06:58:56.070511 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11301 06:59:00.169019 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4197 ms)
11302 06:59:00.181655 [0:01:34.170904774] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11303 06:59:00.255416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11304 06:59:00.255737 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11306 06:59:00.271050 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11307 06:59:06.744973 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6577 ms)
11308 06:59:06.758162 [0:01:40.747550076] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11309 06:59:06.809065 [0:01:40.802794353] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11310 06:59:06.837591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11311 06:59:06.837955 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11313 06:59:06.856125 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11314 06:59:06.866126 [0:01:40.858617774] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11315 06:59:06.913370 Camera needs 4 requests, can't test only 1
11316 06:59:06.922494 [0:01:40.914898109] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11317 06:59:07.004737 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11318 06:59:07.083060
11319 06:59:07.174122 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (54 ms)
11320 06:59:07.280381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11321 06:59:07.281145 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11323 06:59:07.298749 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11324 06:59:07.353506 Camera needs 4 requests, can't test only 2
11325 06:59:07.429907 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11326 06:59:07.502081
11327 06:59:07.568194 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (55 ms)
11328 06:59:07.641962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11329 06:59:07.642287 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11331 06:59:07.653233 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11332 06:59:07.695911 Camera needs 4 requests, can't test only 3
11333 06:59:07.753021 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11334 06:59:07.810227
11335 06:59:07.872491 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (56 ms)
11336 06:59:07.940522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11337 06:59:07.940835 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11339 06:59:07.952982 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11340 06:59:08.992084 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2080 ms)
11341 06:59:09.005647 [0:01:42.994666809] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11342 06:59:09.102807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11343 06:59:09.103590 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11345 06:59:09.121958 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11346 06:59:11.705181 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2713 ms)
11347 06:59:11.718468 [0:01:45.709683701] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11348 06:59:11.806394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11349 06:59:11.807179 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11351 06:59:11.824690 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11352 06:59:15.466714 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3761 ms)
11353 06:59:15.479293 [0:01:49.471128736] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11354 06:59:15.566588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11355 06:59:15.567309 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11357 06:59:15.584869 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11358 06:59:20.904747 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5440 ms)
11359 06:59:20.917746 [0:01:54.910895800] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11360 06:59:20.985345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11361 06:59:20.985665 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11363 06:59:20.996555 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11364 06:59:29.077381 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8173 ms)
11365 06:59:29.090862 [0:02:03.083884884] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11366 06:59:29.156763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11367 06:59:29.157075 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11369 06:59:29.169571 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11370 06:59:41.658908 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12580 ms)
11371 06:59:41.671765 [0:02:15.663240642] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11372 06:59:41.751403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11373 06:59:41.751693 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11375 06:59:41.766166 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11376 07:00:01.378949 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19720 ms)
11377 07:00:01.392165 [0:02:35.384938142] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11378 07:00:01.444662 [0:02:35.438612355] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11379 07:00:01.455334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11380 07:00:01.455598 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11382 07:00:01.470207 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11383 07:00:01.498779 [0:02:35.492630452] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11384 07:00:01.513374 Camera needs 4 requests, can't test only 1
11385 07:00:01.554021 [0:02:35.547144264] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11386 07:00:01.590195 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11387 07:00:01.671081
11388 07:00:01.755734 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (55 ms)
11389 07:00:01.829671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11390 07:00:01.829974 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11392 07:00:01.842296 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11393 07:00:01.895996 Camera needs 4 requests, can't test only 2
11394 07:00:01.959174 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11395 07:00:02.024088
11396 07:00:02.105719 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (54 ms)
11397 07:00:02.200038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11398 07:00:02.201002 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11400 07:00:02.214116 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11401 07:00:02.267322 Camera needs 4 requests, can't test only 3
11402 07:00:02.336255 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11403 07:00:02.400734
11404 07:00:02.478074 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (54 ms)
11405 07:00:02.563886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11406 07:00:02.564344 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11408 07:00:02.573919 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11409 07:00:03.625729 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2078 ms)
11410 07:00:03.635669 [0:02:37.624700939] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11411 07:00:03.718347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11412 07:00:03.718789 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11414 07:00:03.729390 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11415 07:00:06.335388 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2709 ms)
11416 07:00:06.345193 [0:02:40.335720235] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11417 07:00:06.425701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11418 07:00:06.426429 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11420 07:00:06.439523 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11421 07:00:10.095515 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3760 ms)
11422 07:00:10.105006 [0:02:44.095899705] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11423 07:00:10.192368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11424 07:00:10.193136 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11426 07:00:10.203849 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11427 07:00:15.535812 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5440 ms)
11428 07:00:15.545539 [0:02:49.535875096] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11429 07:00:15.646290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11430 07:00:15.647012 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11432 07:00:15.662868 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11433 07:00:23.707169 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8173 ms)
11434 07:00:23.717315 [0:02:57.708979457] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11435 07:00:23.782142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11436 07:00:23.782415 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11438 07:00:23.793926 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11439 07:00:36.287892 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12579 ms)
11440 07:00:36.297865 [0:03:10.290018009] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11441 07:00:36.402028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11442 07:00:36.402800 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11444 07:00:36.418760 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11445 07:00:56.009320 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19721 ms)
11446 07:00:56.019112 [0:03:30.012664313] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11447 07:00:56.069949 [0:03:30.066136473] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11448 07:00:56.076691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11449 07:00:56.076967 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11451 07:00:56.086031 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11452 07:00:56.124806 [0:03:30.120601136] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11453 07:00:56.127951 Camera needs 4 requests, can't test only 1
11454 07:00:56.179363 [0:03:30.175176100] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11455 07:00:56.194255 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11456 07:00:56.249978
11457 07:00:56.317037 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (54 ms)
11458 07:00:56.384777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11459 07:00:56.385079 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11461 07:00:56.392939 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11462 07:00:56.431366 Camera needs 4 requests, can't test only 2
11463 07:00:56.488369 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11464 07:00:56.537450
11465 07:00:56.602764 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (54 ms)
11466 07:00:56.666526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11467 07:00:56.666840 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11469 07:00:56.674851 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11470 07:00:56.713886 Camera needs 4 requests, can't test only 3
11471 07:00:56.763903 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11472 07:00:56.812939
11473 07:00:56.871229 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (55 ms)
11474 07:00:56.938326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11475 07:00:56.938665 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11477 07:00:56.948430 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11478 07:00:58.251775 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2077 ms)
11479 07:00:58.261337 [0:03:32.253217624] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11480 07:00:58.322573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11481 07:00:58.322872 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11483 07:00:58.330347 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11484 07:01:00.961419 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2710 ms)
11485 07:01:00.971214 [0:03:34.965284596] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11486 07:01:01.035955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11487 07:01:01.036254 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11489 07:01:01.046003 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11490 07:01:04.721798 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3761 ms)
11491 07:01:04.732133 [0:03:38.725596650] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11492 07:01:04.795082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11493 07:01:04.795402 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11495 07:01:04.805840 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11496 07:01:10.161900 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5440 ms)
11497 07:01:10.171357 [0:03:44.166221435] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11498 07:01:10.234951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11499 07:01:10.235275 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11501 07:01:10.245623 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11502 07:01:18.334233 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8171 ms)
11503 07:01:18.344087 [0:03:52.339312734] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11504 07:01:18.403147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11505 07:01:18.403458 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11507 07:01:18.411238 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11508 07:01:30.916257 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12581 ms)
11509 07:01:30.925980 [0:04:04.921856650] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11510 07:01:31.013567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11511 07:01:31.014293 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11513 07:01:31.027285 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11514 07:01:50.636521 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19718 ms)
11515 07:01:50.646115 [0:04:24.641662255] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11516 07:01:50.699573 [0:04:24.696779354] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11517 07:01:50.720972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11518 07:01:50.721244 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11520 07:01:50.731662 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11521 07:01:50.755383 [0:04:24.752352526] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11522 07:01:50.786087 Camera needs 4 requests, can't test only 1
11523 07:01:50.807380 [0:04:24.804244200] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11524 07:01:50.873144 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11525 07:01:50.946011
11526 07:01:51.027307 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (55 ms)
11527 07:01:51.102446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11528 07:01:51.102739 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11530 07:01:51.114858 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11531 07:01:51.160180 Camera needs 4 requests, can't test only 2
11532 07:01:51.222914 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11533 07:01:51.280653
11534 07:01:51.352078 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (54 ms)
11535 07:01:51.424729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11536 07:01:51.425033 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11538 07:01:51.435419 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11539 07:01:51.473352 Camera needs 4 requests, can't test only 3
11540 07:01:51.537303 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11541 07:01:51.597355
11542 07:01:51.674208 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (54 ms)
11543 07:01:51.746005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11544 07:01:51.746358 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11546 07:01:51.754866 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11547 07:01:52.879707 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2076 ms)
11548 07:01:52.889819 [0:04:26.881860423] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11549 07:01:52.975752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11550 07:01:52.976489 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11552 07:01:52.988588 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11553 07:01:55.587711 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2708 ms)
11554 07:01:55.597529 [0:04:29.591063575] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11555 07:01:55.683950 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11557 07:01:55.687528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11558 07:01:55.701166 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11559 07:01:59.346098 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3758 ms)
11560 07:01:59.355761 [0:04:33.348851721] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11561 07:01:59.451418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11562 07:01:59.452261 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11564 07:01:59.466720 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11565 07:02:04.782898 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5437 ms)
11566 07:02:04.792706 [0:04:38.786070899] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11567 07:02:04.880766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11568 07:02:04.881046 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11570 07:02:04.893525 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11571 07:02:12.953225 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8170 ms)
11572 07:02:12.963285 [0:04:46.956043993] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11573 07:02:13.050594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11574 07:02:13.051305 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11576 07:02:13.063689 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11577 07:02:25.531616 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12578 ms)
11578 07:02:25.541634 [0:04:59.534073370] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11579 07:02:25.628028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11580 07:02:25.628798 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11582 07:02:25.638867 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11583 07:02:45.249886 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19718 ms)
11584 07:02:45.259734 [0:05:19.253287365] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11585 07:02:45.345920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11586 07:02:45.346787 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11588 07:02:45.358131 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11589 07:02:45.664789 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (416 ms)
11590 07:02:45.674698 [0:05:19.668831644] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11591 07:02:45.767839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11592 07:02:45.768640 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11594 07:02:45.784720 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11595 07:02:46.153117 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (488 ms)
11596 07:02:46.162973 [0:05:20.156913379] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11597 07:02:46.252350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11598 07:02:46.253135 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11600 07:02:46.268775 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11601 07:02:46.708724 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (556 ms)
11602 07:02:46.718537 [0:05:20.712733205] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11603 07:02:46.811304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11604 07:02:46.812067 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11606 07:02:46.827884 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11607 07:02:47.404275 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (695 ms)
11608 07:02:47.417103 [0:05:21.408220288] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11609 07:02:47.503576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11610 07:02:47.504329 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11612 07:02:47.518607 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11613 07:02:48.309759 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (906 ms)
11614 07:02:48.319730 [0:05:22.313920924] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11615 07:02:48.402857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11616 07:02:48.403138 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11618 07:02:48.414458 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11619 07:02:49.566234 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1256 ms)
11620 07:02:49.579113 [0:05:23.569933381] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11621 07:02:49.659409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11622 07:02:49.660125 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11624 07:02:49.674770 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11625 07:02:51.381869 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1816 ms)
11626 07:02:51.394147 [0:05:25.385964839] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11627 07:02:51.493176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11628 07:02:51.494127 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11630 07:02:51.510872 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11631 07:02:54.108144 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2726 ms)
11632 07:02:54.120881 [0:05:28.113418198] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11633 07:02:54.194616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11634 07:02:54.195337 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11636 07:02:54.209346 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11637 07:02:58.304279 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4197 ms)
11638 07:02:58.317106 [0:05:32.310333776] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11639 07:02:58.402674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11640 07:02:58.403458 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11642 07:02:58.418733 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11643 07:03:04.881916 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6577 ms)
11644 07:03:04.895301 [0:05:38.887623179] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11645 07:03:04.988247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11646 07:03:04.989062 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11648 07:03:05.004848 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11649 07:03:05.301701 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (417 ms)
11650 07:03:05.311679 [0:05:39.303128830] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11651 07:03:05.410265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11652 07:03:05.410980 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11654 07:03:05.426678 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11655 07:03:05.788387 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (486 ms)
11656 07:03:05.797995 [0:05:39.789301039] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11657 07:03:05.896341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11658 07:03:05.897203 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11660 07:03:05.910965 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11661 07:03:06.344256 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (556 ms)
11662 07:03:06.353609 [0:05:40.345082216] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11663 07:03:06.451637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11664 07:03:06.452414 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11666 07:03:06.466051 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11667 07:03:07.039810 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (696 ms)
11668 07:03:07.049425 [0:05:41.040619701] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11669 07:03:07.148967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11670 07:03:07.149742 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11672 07:03:07.163813 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11673 07:03:07.947233 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (907 ms)
11674 07:03:07.957016 [0:05:41.948227055] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11675 07:03:08.047055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11676 07:03:08.047828 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11678 07:03:08.061788 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11679 07:03:09.203278 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1256 ms)
11680 07:03:09.213105 [0:05:43.204146112] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11681 07:03:09.312698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11682 07:03:09.313425 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11684 07:03:09.326825 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11685 07:03:11.018420 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1816 ms)
11686 07:03:11.028856 [0:05:45.019823178] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11687 07:03:11.128414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11688 07:03:11.129180 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11690 07:03:11.145452 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11691 07:03:13.746576 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2728 ms)
11692 07:03:13.756061 [0:05:47.749448989] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11693 07:03:13.843823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11694 07:03:13.844846 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11696 07:03:13.858061 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11697 07:03:17.943883 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4197 ms)
11698 07:03:17.953835 [0:05:51.947015160] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11699 07:03:18.029097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11700 07:03:18.029403 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11702 07:03:18.043116 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11703 07:03:24.521519 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6578 ms)
11704 07:03:24.530935 [0:05:58.524422003] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11705 07:03:24.613062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11706 07:03:24.613555 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11708 07:03:24.625814 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11709 07:03:24.938301 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (417 ms)
11710 07:03:24.948094 [0:05:58.939884806] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11711 07:03:25.044337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11712 07:03:25.045110 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11714 07:03:25.059673 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11715 07:03:25.425149 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (486 ms)
11716 07:03:25.435292 [0:05:59.426572940] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11717 07:03:25.528226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11718 07:03:25.529028 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11720 07:03:25.541594 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11721 07:03:25.981005 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (555 ms)
11722 07:03:25.990847 [0:05:59.982090448] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11723 07:03:26.078476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11724 07:03:26.079190 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11726 07:03:26.094194 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11727 07:03:26.676515 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (696 ms)
11728 07:03:26.686353 [0:06:00.677946033] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11729 07:03:26.781380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11730 07:03:26.782215 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11732 07:03:26.796234 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11733 07:03:27.584334 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (907 ms)
11734 07:03:27.593537 [0:06:01.585246903] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11735 07:03:27.688388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11736 07:03:27.689181 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11738 07:03:27.701687 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11739 07:03:28.839702 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1256 ms)
11740 07:03:28.849150 [0:06:02.840805136] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11741 07:03:28.936912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11742 07:03:28.937697 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11744 07:03:28.951734 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11745 07:03:30.655032 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1816 ms)
11746 07:03:30.664764 [0:06:04.656737319] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11747 07:03:30.754049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11748 07:03:30.754380 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11750 07:03:30.767177 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11751 07:03:33.381268 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2726 ms)
11752 07:03:33.391301 [0:06:07.385058156] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11753 07:03:33.477664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11754 07:03:33.478526 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11756 07:03:33.491841 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11757 07:03:37.578815 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4198 ms)
11758 07:03:37.588950 [0:06:11.582517196] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11759 07:03:37.679182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11760 07:03:37.679958 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11762 07:03:37.693776 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11763 07:03:44.156798 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6577 ms)
11764 07:03:44.165977 [0:06:18.159969264] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11765 07:03:44.248254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11766 07:03:44.248544 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11768 07:03:44.260259 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11769 07:03:44.569599 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (416 ms)
11770 07:03:44.583046 [0:06:18.574916186] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11771 07:03:44.667108 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11773 07:03:44.669593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11774 07:03:44.680652 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11775 07:03:45.058893 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (486 ms)
11776 07:03:45.068458 [0:06:19.060791524] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11777 07:03:45.163581 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11779 07:03:45.166498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11780 07:03:45.181681 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11781 07:03:45.614638 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (556 ms)
11782 07:03:45.624560 [0:06:19.616799894] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11783 07:03:45.712680 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11785 07:03:45.715987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11786 07:03:45.728647 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11787 07:03:46.310848 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (696 ms)
11788 07:03:46.320346 [0:06:20.312548074] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11789 07:03:46.413664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11790 07:03:46.414431 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11792 07:03:46.433408 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11793 07:03:47.216492 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (905 ms)
11794 07:03:47.226303 [0:06:21.218547313] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11795 07:03:47.313801 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11797 07:03:47.316684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11798 07:03:47.331257 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11799 07:03:48.472192 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1256 ms)
11800 07:03:48.481861 [0:06:22.474166761] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11801 07:03:48.568353 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11803 07:03:48.571202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11804 07:03:48.585471 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11805 07:03:50.288046 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1816 ms)
11806 07:03:50.297825 [0:06:24.290279962] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11807 07:03:50.386861 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11809 07:03:50.389713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11810 07:03:50.404148 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11811 07:03:53.014003 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2726 ms)
11812 07:03:53.023595 [0:06:27.017826161] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11813 07:03:53.123096 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11815 07:03:53.125917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11816 07:03:53.141061 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11817 07:03:57.210730 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4198 ms)
11818 07:03:57.221031 [0:06:31.215254317] [408] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11819 07:03:57.304552 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11821 07:03:57.307396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11822 07:03:57.319316 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11823 07:04:03.788355 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6577 ms)
11824 07:04:03.878977 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11826 07:04:03.881921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11827 07:04:03.896195 [----------] 120 tests from CaptureTests/SingleStream (369978 ms total)
11828 07:04:03.975931
11829 07:04:04.058041 [----------] Global test environment tear-down
11830 07:04:04.135591 [==========] 120 tests from 1 test suite ran. (369978 ms total)
11831 07:04:04.217597 <LAVA_SIGNAL_TESTSET STOP>
11832 07:04:04.218289 Received signal: <TESTSET> STOP
11833 07:04:04.218653 Closing test_set CaptureTests/SingleStream
11834 07:04:04.228502 + set +x
11835 07:04:04.231652 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12694854_1.6.2.3.1>
11836 07:04:04.232361 Received signal: <ENDRUN> 0_lc-compliance 12694854_1.6.2.3.1
11837 07:04:04.232765 Ending use of test pattern.
11838 07:04:04.233081 Ending test lava.0_lc-compliance (12694854_1.6.2.3.1), duration 371.53
11840 07:04:04.234938 <LAVA_TEST_RUNNER EXIT>
11841 07:04:04.235601 ok: lava_test_shell seems to have completed
11842 07:04:04.241514 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11843 07:04:04.241689 end: 3.1 lava-test-shell (duration 00:06:12) [common]
11844 07:04:04.241778 end: 3 lava-test-retry (duration 00:06:12) [common]
11845 07:04:04.241863 start: 4 finalize (timeout 00:10:00) [common]
11846 07:04:04.241950 start: 4.1 power-off (timeout 00:00:30) [common]
11847 07:04:04.242099 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11848 07:04:04.322997 >> Command sent successfully.
11849 07:04:04.335087 Returned 0 in 0 seconds
11850 07:04:04.436536 end: 4.1 power-off (duration 00:00:00) [common]
11852 07:04:04.438063 start: 4.2 read-feedback (timeout 00:10:00) [common]
11853 07:04:04.439529 Listened to connection for namespace 'common' for up to 1s
11854 07:04:05.439997 Finalising connection for namespace 'common'
11855 07:04:05.440747 Disconnecting from shell: Finalise
11856 07:04:05.441171 / #
11857 07:04:05.542143 end: 4.2 read-feedback (duration 00:00:01) [common]
11858 07:04:05.542911 end: 4 finalize (duration 00:00:01) [common]
11859 07:04:05.543595 Cleaning after the job
11860 07:04:05.544190 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/ramdisk
11861 07:04:05.557287 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/kernel
11862 07:04:05.593264 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/dtb
11863 07:04:05.593576 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/nfsrootfs
11864 07:04:05.653018 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694854/tftp-deploy-w1pzfpjm/modules
11865 07:04:05.660118 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694854
11866 07:04:05.976462 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694854
11867 07:04:05.976642 Job finished correctly