Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 38
- Kernel Errors: 32
1 06:47:44.507459 lava-dispatcher, installed at version: 2023.10
2 06:47:44.507683 start: 0 validate
3 06:47:44.507813 Start time: 2024-02-03 06:47:44.507806+00:00 (UTC)
4 06:47:44.507932 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:47:44.508061 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 06:47:44.774331 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:47:44.774526 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:48:13.561227 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:48:13.562017 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:48:13.832753 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:48:13.833447 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 06:48:18.608219 validate duration: 34.10
14 06:48:18.609499 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:48:18.610070 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:48:18.610559 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:48:18.611147 Not decompressing ramdisk as can be used compressed.
18 06:48:18.611600 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 06:48:18.611953 saving as /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/ramdisk/rootfs.cpio.gz
20 06:48:18.612303 total size: 84918747 (80 MB)
21 06:48:18.880237 progress 0 % (0 MB)
22 06:48:18.902553 progress 5 % (4 MB)
23 06:48:18.926307 progress 10 % (8 MB)
24 06:48:18.947320 progress 15 % (12 MB)
25 06:48:18.968851 progress 20 % (16 MB)
26 06:48:18.990531 progress 25 % (20 MB)
27 06:48:19.012514 progress 30 % (24 MB)
28 06:48:19.034519 progress 35 % (28 MB)
29 06:48:19.056035 progress 40 % (32 MB)
30 06:48:19.077506 progress 45 % (36 MB)
31 06:48:19.099062 progress 50 % (40 MB)
32 06:48:19.121100 progress 55 % (44 MB)
33 06:48:19.142467 progress 60 % (48 MB)
34 06:48:19.185204 progress 65 % (52 MB)
35 06:48:19.234560 progress 70 % (56 MB)
36 06:48:19.282095 progress 75 % (60 MB)
37 06:48:19.328478 progress 80 % (64 MB)
38 06:48:19.379045 progress 85 % (68 MB)
39 06:48:19.414189 progress 90 % (72 MB)
40 06:48:19.462048 progress 95 % (76 MB)
41 06:48:19.498466 progress 100 % (80 MB)
42 06:48:19.498707 80 MB downloaded in 0.89 s (91.36 MB/s)
43 06:48:19.498865 end: 1.1.1 http-download (duration 00:00:01) [common]
45 06:48:19.499102 end: 1.1 download-retry (duration 00:00:01) [common]
46 06:48:19.499188 start: 1.2 download-retry (timeout 00:09:59) [common]
47 06:48:19.499271 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 06:48:19.499402 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 06:48:19.499470 saving as /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/kernel/Image
50 06:48:19.499532 total size: 51532288 (49 MB)
51 06:48:19.499593 No compression specified
52 06:48:19.500649 progress 0 % (0 MB)
53 06:48:19.513236 progress 5 % (2 MB)
54 06:48:19.526513 progress 10 % (4 MB)
55 06:48:19.539806 progress 15 % (7 MB)
56 06:48:19.553045 progress 20 % (9 MB)
57 06:48:19.566404 progress 25 % (12 MB)
58 06:48:19.579226 progress 30 % (14 MB)
59 06:48:19.592229 progress 35 % (17 MB)
60 06:48:19.605133 progress 40 % (19 MB)
61 06:48:19.617924 progress 45 % (22 MB)
62 06:48:19.630980 progress 50 % (24 MB)
63 06:48:19.644081 progress 55 % (27 MB)
64 06:48:19.657149 progress 60 % (29 MB)
65 06:48:19.670292 progress 65 % (31 MB)
66 06:48:19.683299 progress 70 % (34 MB)
67 06:48:19.696338 progress 75 % (36 MB)
68 06:48:19.709420 progress 80 % (39 MB)
69 06:48:19.722326 progress 85 % (41 MB)
70 06:48:19.735395 progress 90 % (44 MB)
71 06:48:19.748831 progress 95 % (46 MB)
72 06:48:19.761776 progress 100 % (49 MB)
73 06:48:19.762080 49 MB downloaded in 0.26 s (187.19 MB/s)
74 06:48:19.762240 end: 1.2.1 http-download (duration 00:00:00) [common]
76 06:48:19.762473 end: 1.2 download-retry (duration 00:00:00) [common]
77 06:48:19.762561 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:48:19.762653 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:48:19.762796 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 06:48:19.762869 saving as /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/dtb/mt8192-asurada-spherion-r0.dtb
81 06:48:19.762931 total size: 47278 (0 MB)
82 06:48:19.762994 No compression specified
83 06:48:19.764113 progress 69 % (0 MB)
84 06:48:19.764385 progress 100 % (0 MB)
85 06:48:19.764539 0 MB downloaded in 0.00 s (28.09 MB/s)
86 06:48:19.764660 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:48:19.764884 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:48:19.764970 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:48:19.765057 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:48:19.765173 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 06:48:19.765241 saving as /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/modules/modules.tar
93 06:48:19.765302 total size: 8624064 (8 MB)
94 06:48:19.765364 Using unxz to decompress xz
95 06:48:19.769067 progress 0 % (0 MB)
96 06:48:19.790461 progress 5 % (0 MB)
97 06:48:19.813708 progress 10 % (0 MB)
98 06:48:19.837133 progress 15 % (1 MB)
99 06:48:19.860790 progress 20 % (1 MB)
100 06:48:19.885225 progress 25 % (2 MB)
101 06:48:19.910839 progress 30 % (2 MB)
102 06:48:19.937267 progress 35 % (2 MB)
103 06:48:19.960570 progress 40 % (3 MB)
104 06:48:19.985890 progress 45 % (3 MB)
105 06:48:20.011420 progress 50 % (4 MB)
106 06:48:20.035994 progress 55 % (4 MB)
107 06:48:20.061488 progress 60 % (4 MB)
108 06:48:20.089646 progress 65 % (5 MB)
109 06:48:20.114470 progress 70 % (5 MB)
110 06:48:20.137932 progress 75 % (6 MB)
111 06:48:20.164793 progress 80 % (6 MB)
112 06:48:20.190851 progress 85 % (7 MB)
113 06:48:20.216619 progress 90 % (7 MB)
114 06:48:20.248510 progress 95 % (7 MB)
115 06:48:20.276117 progress 100 % (8 MB)
116 06:48:20.281022 8 MB downloaded in 0.52 s (15.95 MB/s)
117 06:48:20.281281 end: 1.4.1 http-download (duration 00:00:01) [common]
119 06:48:20.281547 end: 1.4 download-retry (duration 00:00:01) [common]
120 06:48:20.281643 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 06:48:20.281740 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 06:48:20.281826 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:48:20.281913 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 06:48:20.282175 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w
125 06:48:20.282307 makedir: /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin
126 06:48:20.282414 makedir: /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/tests
127 06:48:20.282518 makedir: /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/results
128 06:48:20.282644 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-add-keys
129 06:48:20.282794 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-add-sources
130 06:48:20.282923 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-background-process-start
131 06:48:20.283051 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-background-process-stop
132 06:48:20.283177 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-common-functions
133 06:48:20.283300 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-echo-ipv4
134 06:48:20.283426 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-install-packages
135 06:48:20.283551 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-installed-packages
136 06:48:20.283673 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-os-build
137 06:48:20.283795 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-probe-channel
138 06:48:20.283917 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-probe-ip
139 06:48:20.284038 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-target-ip
140 06:48:20.284160 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-target-mac
141 06:48:20.284282 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-target-storage
142 06:48:20.284408 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-test-case
143 06:48:20.284531 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-test-event
144 06:48:20.284696 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-test-feedback
145 06:48:20.284820 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-test-raise
146 06:48:20.284944 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-test-reference
147 06:48:20.285066 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-test-runner
148 06:48:20.285188 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-test-set
149 06:48:20.285311 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-test-shell
150 06:48:20.285439 Updating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-install-packages (oe)
151 06:48:20.285590 Updating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/bin/lava-installed-packages (oe)
152 06:48:20.285711 Creating /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/environment
153 06:48:20.285820 LAVA metadata
154 06:48:20.285897 - LAVA_JOB_ID=12694799
155 06:48:20.286002 - LAVA_DISPATCHER_IP=192.168.201.1
156 06:48:20.286109 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 06:48:20.286178 skipped lava-vland-overlay
158 06:48:20.286255 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 06:48:20.286338 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 06:48:20.286406 skipped lava-multinode-overlay
161 06:48:20.286484 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 06:48:20.286571 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 06:48:20.286694 Loading test definitions
164 06:48:20.286828 start: 1.5.2.3.1 git-repo-action (timeout 00:09:58) [common]
165 06:48:20.286903 Using /lava-12694799 at stage 0
166 06:48:20.287002 Fetching tests from https://github.com/kernelci/kernelci-core
167 06:48:20.287087 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/0/tests/0_sleep'
168 06:48:26.486600 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/0/tests/0_sleep
169 06:48:26.496493 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 06:48:26.497014 uuid=12694799_1.5.2.3.1 testdef=None
171 06:48:26.497187 end: 1.5.2.3.1 git-repo-action (duration 00:00:06) [common]
173 06:48:26.497565 start: 1.5.2.3.2 test-overlay (timeout 00:09:52) [common]
174 06:48:26.498282 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 06:48:26.498528 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:52) [common]
177 06:48:26.546776 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 06:48:26.547326 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
180 06:48:26.754695 runner path: /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/0/tests/0_sleep test_uuid 12694799_1.5.2.3.1
181 06:48:26.754881 sleep_params='mem'
182 06:48:26.755113 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 06:48:26.755339 Creating lava-test-runner.conf files
185 06:48:26.755412 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694799/lava-overlay-rvhi805w/lava-12694799/0 for stage 0
186 06:48:26.755510 - 0_sleep
187 06:48:26.755622 end: 1.5.2.3 test-definition (duration 00:00:06) [common]
188 06:48:26.755714 start: 1.5.2.4 compress-overlay (timeout 00:09:52) [common]
189 06:48:26.890523 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 06:48:26.890680 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
191 06:48:26.890782 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 06:48:26.890886 end: 1.5.2 lava-overlay (duration 00:00:07) [common]
193 06:48:26.890978 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
194 06:48:29.181459 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 06:48:29.181821 start: 1.5.4 extract-modules (timeout 00:09:49) [common]
196 06:48:29.181967 extracting modules file /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694799/extract-overlay-ramdisk-grx40jmo/ramdisk
197 06:48:29.399336 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 06:48:29.399515 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
199 06:48:29.399622 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694799/compress-overlay-iw_uqkvv/overlay-1.5.2.4.tar.gz to ramdisk
200 06:48:29.399698 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694799/compress-overlay-iw_uqkvv/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694799/extract-overlay-ramdisk-grx40jmo/ramdisk
201 06:48:29.501306 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 06:48:29.501528 start: 1.5.6 configure-preseed-file (timeout 00:09:49) [common]
203 06:48:29.501632 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 06:48:29.501727 start: 1.5.7 compress-ramdisk (timeout 00:09:49) [common]
205 06:48:29.501836 Building ramdisk /var/lib/lava/dispatcher/tmp/12694799/extract-overlay-ramdisk-grx40jmo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694799/extract-overlay-ramdisk-grx40jmo/ramdisk
206 06:48:38.195561 >> 563699 blocks
207 06:48:47.885447 rename /var/lib/lava/dispatcher/tmp/12694799/extract-overlay-ramdisk-grx40jmo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/ramdisk/ramdisk.cpio.gz
208 06:48:47.885876 end: 1.5.7 compress-ramdisk (duration 00:00:18) [common]
209 06:48:47.886017 start: 1.5.8 prepare-kernel (timeout 00:09:31) [common]
210 06:48:47.886122 start: 1.5.8.1 prepare-fit (timeout 00:09:31) [common]
211 06:48:47.886243 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/kernel/Image'
212 06:49:01.131705 Returned 0 in 13 seconds
213 06:49:01.232301 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/kernel/image.itb
214 06:49:02.497452 output: FIT description: Kernel Image image with one or more FDT blobs
215 06:49:02.497801 output: Created: Sat Feb 3 06:49:02 2024
216 06:49:02.497883 output: Image 0 (kernel-1)
217 06:49:02.497979 output: Description:
218 06:49:02.498059 output: Created: Sat Feb 3 06:49:02 2024
219 06:49:02.498122 output: Type: Kernel Image
220 06:49:02.498182 output: Compression: lzma compressed
221 06:49:02.498253 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
222 06:49:02.498313 output: Architecture: AArch64
223 06:49:02.498371 output: OS: Linux
224 06:49:02.498429 output: Load Address: 0x00000000
225 06:49:02.498486 output: Entry Point: 0x00000000
226 06:49:02.498541 output: Hash algo: crc32
227 06:49:02.498597 output: Hash value: 380e7c3c
228 06:49:02.498668 output: Image 1 (fdt-1)
229 06:49:02.498731 output: Description: mt8192-asurada-spherion-r0
230 06:49:02.498785 output: Created: Sat Feb 3 06:49:02 2024
231 06:49:02.498840 output: Type: Flat Device Tree
232 06:49:02.498895 output: Compression: uncompressed
233 06:49:02.498949 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 06:49:02.499003 output: Architecture: AArch64
235 06:49:02.499056 output: Hash algo: crc32
236 06:49:02.499109 output: Hash value: cc4352de
237 06:49:02.499162 output: Image 2 (ramdisk-1)
238 06:49:02.499216 output: Description: unavailable
239 06:49:02.499268 output: Created: Sat Feb 3 06:49:02 2024
240 06:49:02.499322 output: Type: RAMDisk Image
241 06:49:02.499376 output: Compression: Unknown Compression
242 06:49:02.499429 output: Data Size: 98367757 Bytes = 96062.26 KiB = 93.81 MiB
243 06:49:02.499483 output: Architecture: AArch64
244 06:49:02.499536 output: OS: Linux
245 06:49:02.499589 output: Load Address: unavailable
246 06:49:02.499642 output: Entry Point: unavailable
247 06:49:02.499694 output: Hash algo: crc32
248 06:49:02.499747 output: Hash value: c81c7483
249 06:49:02.499800 output: Default Configuration: 'conf-1'
250 06:49:02.499853 output: Configuration 0 (conf-1)
251 06:49:02.499906 output: Description: mt8192-asurada-spherion-r0
252 06:49:02.499958 output: Kernel: kernel-1
253 06:49:02.500012 output: Init Ramdisk: ramdisk-1
254 06:49:02.500064 output: FDT: fdt-1
255 06:49:02.500117 output: Loadables: kernel-1
256 06:49:02.500168 output:
257 06:49:02.500371 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 06:49:02.500469 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 06:49:02.500576 end: 1.5 prepare-tftp-overlay (duration 00:00:42) [common]
260 06:49:02.500671 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:16) [common]
261 06:49:02.500749 No LXC device requested
262 06:49:02.500827 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 06:49:02.500913 start: 1.7 deploy-device-env (timeout 00:09:16) [common]
264 06:49:02.500990 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 06:49:02.501061 Checking files for TFTP limit of 4294967296 bytes.
266 06:49:02.501542 end: 1 tftp-deploy (duration 00:00:44) [common]
267 06:49:02.501649 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 06:49:02.501738 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 06:49:02.501872 substitutions:
270 06:49:02.501949 - {DTB}: 12694799/tftp-deploy-zve8fp0e/dtb/mt8192-asurada-spherion-r0.dtb
271 06:49:02.502052 - {INITRD}: 12694799/tftp-deploy-zve8fp0e/ramdisk/ramdisk.cpio.gz
272 06:49:02.502114 - {KERNEL}: 12694799/tftp-deploy-zve8fp0e/kernel/Image
273 06:49:02.502173 - {LAVA_MAC}: None
274 06:49:02.502230 - {PRESEED_CONFIG}: None
275 06:49:02.502287 - {PRESEED_LOCAL}: None
276 06:49:02.502343 - {RAMDISK}: 12694799/tftp-deploy-zve8fp0e/ramdisk/ramdisk.cpio.gz
277 06:49:02.502398 - {ROOT_PART}: None
278 06:49:02.502455 - {ROOT}: None
279 06:49:02.502518 - {SERVER_IP}: 192.168.201.1
280 06:49:02.502579 - {TEE}: None
281 06:49:02.502643 Parsed boot commands:
282 06:49:02.502719 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 06:49:02.502935 Parsed boot commands: tftpboot 192.168.201.1 12694799/tftp-deploy-zve8fp0e/kernel/image.itb 12694799/tftp-deploy-zve8fp0e/kernel/cmdline
284 06:49:02.503053 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 06:49:02.503169 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 06:49:02.503293 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 06:49:02.503410 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 06:49:02.503512 Not connected, no need to disconnect.
289 06:49:02.503618 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 06:49:02.503732 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 06:49:02.503827 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
292 06:49:02.507434 Setting prompt string to ['lava-test: # ']
293 06:49:02.507768 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 06:49:02.507882 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 06:49:02.507982 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 06:49:02.508103 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 06:49:02.508335 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
298 06:49:07.636494 >> Command sent successfully.
299 06:49:07.638771 Returned 0 in 5 seconds
300 06:49:07.739154 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 06:49:07.739474 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 06:49:07.739581 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 06:49:07.739668 Setting prompt string to 'Starting depthcharge on Spherion...'
305 06:49:07.739737 Changing prompt to 'Starting depthcharge on Spherion...'
306 06:49:07.739804 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 06:49:07.740063 [Enter `^Ec?' for help]
308 06:49:07.912683
309 06:49:07.912818
310 06:49:07.912897 F0: 102B 0000
311 06:49:07.912965
312 06:49:07.913027 F3: 1001 0000 [0200]
313 06:49:07.913088
314 06:49:07.916567 F3: 1001 0000
315 06:49:07.916652
316 06:49:07.916718 F7: 102D 0000
317 06:49:07.916781
318 06:49:07.916840 F1: 0000 0000
319 06:49:07.916899
320 06:49:07.920441 V0: 0000 0000 [0001]
321 06:49:07.920526
322 06:49:07.920592 00: 0007 8000
323 06:49:07.920659
324 06:49:07.924096 01: 0000 0000
325 06:49:07.924181
326 06:49:07.924252 BP: 0C00 0209 [0000]
327 06:49:07.924315
328 06:49:07.927769 G0: 1182 0000
329 06:49:07.927852
330 06:49:07.927919 EC: 0000 0021 [4000]
331 06:49:07.927981
332 06:49:07.931493 S7: 0000 0000 [0000]
333 06:49:07.931578
334 06:49:07.931644 CC: 0000 0000 [0001]
335 06:49:07.931705
336 06:49:07.935065 T0: 0000 0040 [010F]
337 06:49:07.935149
338 06:49:07.935215 Jump to BL
339 06:49:07.935277
340 06:49:07.959567
341 06:49:07.959654
342 06:49:07.959722
343 06:49:07.967199 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 06:49:07.970902 ARM64: Exception handlers installed.
345 06:49:07.974607 ARM64: Testing exception
346 06:49:07.978101 ARM64: Done test exception
347 06:49:07.985484 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 06:49:07.992514 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 06:49:08.002920 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 06:49:08.012885 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 06:49:08.019718 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 06:49:08.025909 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 06:49:08.036401 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 06:49:08.043175 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 06:49:08.062346 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 06:49:08.065884 WDT: Last reset was cold boot
357 06:49:08.069191 SPI1(PAD0) initialized at 2873684 Hz
358 06:49:08.072408 SPI5(PAD0) initialized at 992727 Hz
359 06:49:08.076141 VBOOT: Loading verstage.
360 06:49:08.082646 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 06:49:08.085707 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 06:49:08.089187 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 06:49:08.092702 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 06:49:08.100097 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 06:49:08.106398 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 06:49:08.117549 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
367 06:49:08.117636
368 06:49:08.117703
369 06:49:08.127697 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 06:49:08.130677 ARM64: Exception handlers installed.
371 06:49:08.134616 ARM64: Testing exception
372 06:49:08.134703 ARM64: Done test exception
373 06:49:08.141156 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 06:49:08.144488 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 06:49:08.158209 Probing TPM: . done!
376 06:49:08.158293 TPM ready after 0 ms
377 06:49:08.165207 Connected to device vid:did:rid of 1ae0:0028:00
378 06:49:08.172144 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 06:49:08.175954 Initialized TPM device CR50 revision 0
380 06:49:08.240238 tlcl_send_startup: Startup return code is 0
381 06:49:08.240331 TPM: setup succeeded
382 06:49:08.252023 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 06:49:08.260541 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 06:49:08.270522 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 06:49:08.279905 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 06:49:08.283395 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 06:49:08.291941 in-header: 03 07 00 00 08 00 00 00
388 06:49:08.296027 in-data: aa e4 47 04 13 02 00 00
389 06:49:08.299315 Chrome EC: UHEPI supported
390 06:49:08.306777 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 06:49:08.310662 in-header: 03 ad 00 00 08 00 00 00
392 06:49:08.314049 in-data: 00 20 20 08 00 00 00 00
393 06:49:08.314133 Phase 1
394 06:49:08.317742 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 06:49:08.324908 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 06:49:08.328939 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 06:49:08.332585 Recovery requested (1009000e)
398 06:49:08.341291 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 06:49:08.346567 tlcl_extend: response is 0
400 06:49:08.356448 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 06:49:08.361986 tlcl_extend: response is 0
402 06:49:08.368933 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 06:49:08.389008 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 06:49:08.396013 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 06:49:08.396125
406 06:49:08.396225
407 06:49:08.406106 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 06:49:08.409350 ARM64: Exception handlers installed.
409 06:49:08.409451 ARM64: Testing exception
410 06:49:08.412624 ARM64: Done test exception
411 06:49:08.434218 pmic_efuse_setting: Set efuses in 11 msecs
412 06:49:08.437225 pmwrap_interface_init: Select PMIF_VLD_RDY
413 06:49:08.444376 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 06:49:08.448162 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 06:49:08.454602 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 06:49:08.457901 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 06:49:08.461299 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 06:49:08.468821 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 06:49:08.472431 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 06:49:08.476396 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 06:49:08.480140 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 06:49:08.487592 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 06:49:08.491763 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 06:49:08.495074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 06:49:08.498595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 06:49:08.505719 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 06:49:08.512723 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 06:49:08.519607 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 06:49:08.522960 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 06:49:08.530485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 06:49:08.534018 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 06:49:08.540664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 06:49:08.543952 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 06:49:08.552137 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 06:49:08.558624 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 06:49:08.561675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 06:49:08.568715 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 06:49:08.575217 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 06:49:08.578741 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 06:49:08.582011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 06:49:08.588701 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 06:49:08.592206 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 06:49:08.598619 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 06:49:08.602272 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 06:49:08.609346 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 06:49:08.612281 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 06:49:08.618990 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 06:49:08.622420 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 06:49:08.629097 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 06:49:08.632327 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 06:49:08.638724 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 06:49:08.642514 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 06:49:08.645488 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 06:49:08.652592 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 06:49:08.656359 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 06:49:08.659726 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 06:49:08.663490 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 06:49:08.666741 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 06:49:08.673417 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 06:49:08.676851 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 06:49:08.679895 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 06:49:08.686599 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 06:49:08.689677 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 06:49:08.696599 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 06:49:08.706733 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 06:49:08.709967 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 06:49:08.716400 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 06:49:08.726423 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 06:49:08.730143 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 06:49:08.736893 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 06:49:08.739995 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 06:49:08.746511 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1d
473 06:49:08.753308 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 06:49:08.756688 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 06:49:08.760297 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 06:49:08.771970 [RTC]rtc_get_frequency_meter,154: input=15, output=773
477 06:49:08.781228 [RTC]rtc_get_frequency_meter,154: input=23, output=958
478 06:49:08.790383 [RTC]rtc_get_frequency_meter,154: input=19, output=864
479 06:49:08.799963 [RTC]rtc_get_frequency_meter,154: input=17, output=820
480 06:49:08.809599 [RTC]rtc_get_frequency_meter,154: input=16, output=796
481 06:49:08.812985 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
482 06:49:08.819494 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
483 06:49:08.823059 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
484 06:49:08.826246 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
485 06:49:08.829646 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
486 06:49:08.832782 ADC[4]: Raw value=902507 ID=7
487 06:49:08.836222 ADC[3]: Raw value=213179 ID=1
488 06:49:08.836307 RAM Code: 0x71
489 06:49:08.842735 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
490 06:49:08.846204 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
491 06:49:08.856514 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
492 06:49:08.862826 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 06:49:08.866418 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
494 06:49:08.869720 in-header: 03 07 00 00 08 00 00 00
495 06:49:08.873156 in-data: aa e4 47 04 13 02 00 00
496 06:49:08.876543 Chrome EC: UHEPI supported
497 06:49:08.883050 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
498 06:49:08.886315 in-header: 03 ed 00 00 08 00 00 00
499 06:49:08.889718 in-data: 80 20 60 08 00 00 00 00
500 06:49:08.893204 MRC: failed to locate region type 0.
501 06:49:08.899626 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
502 06:49:08.903508 DRAM-K: Running full calibration
503 06:49:08.906445 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
504 06:49:08.909890 header.status = 0x0
505 06:49:08.912937 header.version = 0x6 (expected: 0x6)
506 06:49:08.916727 header.size = 0xd00 (expected: 0xd00)
507 06:49:08.920128 header.flags = 0x0
508 06:49:08.923467 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
509 06:49:08.943110 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
510 06:49:08.950498 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
511 06:49:08.950584 dram_init: ddr_geometry: 2
512 06:49:08.953926 [EMI] MDL number = 2
513 06:49:08.958607 [EMI] Get MDL freq = 0
514 06:49:08.958692 dram_init: ddr_type: 0
515 06:49:08.961754 is_discrete_lpddr4: 1
516 06:49:08.961839 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
517 06:49:08.961907
518 06:49:08.965404
519 06:49:08.965489 [Bian_co] ETT version 0.0.0.1
520 06:49:08.969044 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
521 06:49:08.969129
522 06:49:08.976658 dramc_set_vcore_voltage set vcore to 650000
523 06:49:08.976743 Read voltage for 800, 4
524 06:49:08.976816 Vio18 = 0
525 06:49:08.980134 Vcore = 650000
526 06:49:08.980213 Vdram = 0
527 06:49:08.980278 Vddq = 0
528 06:49:08.983303 Vmddr = 0
529 06:49:08.983443 dram_init: config_dvfs: 1
530 06:49:08.989934 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
531 06:49:08.993416 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
532 06:49:08.996913 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
533 06:49:09.003665 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
534 06:49:09.006660 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
535 06:49:09.010098 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
536 06:49:09.013530 MEM_TYPE=3, freq_sel=18
537 06:49:09.013616 sv_algorithm_assistance_LP4_1600
538 06:49:09.020276 ============ PULL DRAM RESETB DOWN ============
539 06:49:09.023848 ========== PULL DRAM RESETB DOWN end =========
540 06:49:09.027192 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
541 06:49:09.030364 ===================================
542 06:49:09.033765 LPDDR4 DRAM CONFIGURATION
543 06:49:09.037485 ===================================
544 06:49:09.037566 EX_ROW_EN[0] = 0x0
545 06:49:09.041244 EX_ROW_EN[1] = 0x0
546 06:49:09.041323 LP4Y_EN = 0x0
547 06:49:09.044706 WORK_FSP = 0x0
548 06:49:09.044788 WL = 0x2
549 06:49:09.048610 RL = 0x2
550 06:49:09.048690 BL = 0x2
551 06:49:09.052328 RPST = 0x0
552 06:49:09.052406 RD_PRE = 0x0
553 06:49:09.056209 WR_PRE = 0x1
554 06:49:09.056288 WR_PST = 0x0
555 06:49:09.059896 DBI_WR = 0x0
556 06:49:09.059976 DBI_RD = 0x0
557 06:49:09.063394 OTF = 0x1
558 06:49:09.063480 ===================================
559 06:49:09.066931 ===================================
560 06:49:09.070450 ANA top config
561 06:49:09.073493 ===================================
562 06:49:09.077021 DLL_ASYNC_EN = 0
563 06:49:09.077099 ALL_SLAVE_EN = 1
564 06:49:09.080157 NEW_RANK_MODE = 1
565 06:49:09.083530 DLL_IDLE_MODE = 1
566 06:49:09.086659 LP45_APHY_COMB_EN = 1
567 06:49:09.086733 TX_ODT_DIS = 1
568 06:49:09.089821 NEW_8X_MODE = 1
569 06:49:09.093568 ===================================
570 06:49:09.096743 ===================================
571 06:49:09.100216 data_rate = 1600
572 06:49:09.103406 CKR = 1
573 06:49:09.106998 DQ_P2S_RATIO = 8
574 06:49:09.110207 ===================================
575 06:49:09.113450 CA_P2S_RATIO = 8
576 06:49:09.113522 DQ_CA_OPEN = 0
577 06:49:09.116820 DQ_SEMI_OPEN = 0
578 06:49:09.120097 CA_SEMI_OPEN = 0
579 06:49:09.123355 CA_FULL_RATE = 0
580 06:49:09.127097 DQ_CKDIV4_EN = 1
581 06:49:09.130063 CA_CKDIV4_EN = 1
582 06:49:09.130135 CA_PREDIV_EN = 0
583 06:49:09.133517 PH8_DLY = 0
584 06:49:09.136758 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
585 06:49:09.140174 DQ_AAMCK_DIV = 4
586 06:49:09.143385 CA_AAMCK_DIV = 4
587 06:49:09.143464 CA_ADMCK_DIV = 4
588 06:49:09.146951 DQ_TRACK_CA_EN = 0
589 06:49:09.150232 CA_PICK = 800
590 06:49:09.153506 CA_MCKIO = 800
591 06:49:09.156818 MCKIO_SEMI = 0
592 06:49:09.160419 PLL_FREQ = 3068
593 06:49:09.163500 DQ_UI_PI_RATIO = 32
594 06:49:09.163571 CA_UI_PI_RATIO = 0
595 06:49:09.167062 ===================================
596 06:49:09.170215 ===================================
597 06:49:09.173757 memory_type:LPDDR4
598 06:49:09.177152 GP_NUM : 10
599 06:49:09.177225 SRAM_EN : 1
600 06:49:09.180354 MD32_EN : 0
601 06:49:09.183592 ===================================
602 06:49:09.187336 [ANA_INIT] >>>>>>>>>>>>>>
603 06:49:09.187431 <<<<<< [CONFIGURE PHASE]: ANA_TX
604 06:49:09.190873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
605 06:49:09.194674 ===================================
606 06:49:09.198218 data_rate = 1600,PCW = 0X7600
607 06:49:09.201822 ===================================
608 06:49:09.206046 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
609 06:49:09.209492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
610 06:49:09.216441 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
611 06:49:09.220331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
612 06:49:09.223672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
613 06:49:09.227028 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
614 06:49:09.230219 [ANA_INIT] flow start
615 06:49:09.230303 [ANA_INIT] PLL >>>>>>>>
616 06:49:09.233513 [ANA_INIT] PLL <<<<<<<<
617 06:49:09.236988 [ANA_INIT] MIDPI >>>>>>>>
618 06:49:09.240407 [ANA_INIT] MIDPI <<<<<<<<
619 06:49:09.240491 [ANA_INIT] DLL >>>>>>>>
620 06:49:09.243677 [ANA_INIT] flow end
621 06:49:09.247014 ============ LP4 DIFF to SE enter ============
622 06:49:09.250282 ============ LP4 DIFF to SE exit ============
623 06:49:09.253908 [ANA_INIT] <<<<<<<<<<<<<
624 06:49:09.257125 [Flow] Enable top DCM control >>>>>
625 06:49:09.260546 [Flow] Enable top DCM control <<<<<
626 06:49:09.264058 Enable DLL master slave shuffle
627 06:49:09.267156 ==============================================================
628 06:49:09.270875 Gating Mode config
629 06:49:09.277200 ==============================================================
630 06:49:09.277285 Config description:
631 06:49:09.287064 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
632 06:49:09.293847 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
633 06:49:09.297364 SELPH_MODE 0: By rank 1: By Phase
634 06:49:09.304006 ==============================================================
635 06:49:09.307255 GAT_TRACK_EN = 1
636 06:49:09.310843 RX_GATING_MODE = 2
637 06:49:09.313823 RX_GATING_TRACK_MODE = 2
638 06:49:09.317390 SELPH_MODE = 1
639 06:49:09.320876 PICG_EARLY_EN = 1
640 06:49:09.324216 VALID_LAT_VALUE = 1
641 06:49:09.327636 ==============================================================
642 06:49:09.330629 Enter into Gating configuration >>>>
643 06:49:09.334514 Exit from Gating configuration <<<<
644 06:49:09.338445 Enter into DVFS_PRE_config >>>>>
645 06:49:09.349458 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
646 06:49:09.352918 Exit from DVFS_PRE_config <<<<<
647 06:49:09.356802 Enter into PICG configuration >>>>
648 06:49:09.356886 Exit from PICG configuration <<<<
649 06:49:09.360353 [RX_INPUT] configuration >>>>>
650 06:49:09.364027 [RX_INPUT] configuration <<<<<
651 06:49:09.368071 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
652 06:49:09.374625 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
653 06:49:09.381952 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
654 06:49:09.385853 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
655 06:49:09.393151 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
656 06:49:09.400536 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
657 06:49:09.404513 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
658 06:49:09.408224 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
659 06:49:09.412065 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
660 06:49:09.415614 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
661 06:49:09.419441 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
662 06:49:09.423144 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
663 06:49:09.426939 ===================================
664 06:49:09.430759 LPDDR4 DRAM CONFIGURATION
665 06:49:09.434323 ===================================
666 06:49:09.434409 EX_ROW_EN[0] = 0x0
667 06:49:09.438066 EX_ROW_EN[1] = 0x0
668 06:49:09.438150 LP4Y_EN = 0x0
669 06:49:09.442425 WORK_FSP = 0x0
670 06:49:09.442510 WL = 0x2
671 06:49:09.445411 RL = 0x2
672 06:49:09.445496 BL = 0x2
673 06:49:09.449395 RPST = 0x0
674 06:49:09.449480 RD_PRE = 0x0
675 06:49:09.449546 WR_PRE = 0x1
676 06:49:09.452906 WR_PST = 0x0
677 06:49:09.452991 DBI_WR = 0x0
678 06:49:09.456485 DBI_RD = 0x0
679 06:49:09.456570 OTF = 0x1
680 06:49:09.460034 ===================================
681 06:49:09.463744 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
682 06:49:09.467301 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
683 06:49:09.475340 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
684 06:49:09.478621 ===================================
685 06:49:09.478706 LPDDR4 DRAM CONFIGURATION
686 06:49:09.482543 ===================================
687 06:49:09.486245 EX_ROW_EN[0] = 0x10
688 06:49:09.486330 EX_ROW_EN[1] = 0x0
689 06:49:09.489639 LP4Y_EN = 0x0
690 06:49:09.489723 WORK_FSP = 0x0
691 06:49:09.493898 WL = 0x2
692 06:49:09.494031 RL = 0x2
693 06:49:09.494099 BL = 0x2
694 06:49:09.497372 RPST = 0x0
695 06:49:09.497456 RD_PRE = 0x0
696 06:49:09.501162 WR_PRE = 0x1
697 06:49:09.501247 WR_PST = 0x0
698 06:49:09.505009 DBI_WR = 0x0
699 06:49:09.505093 DBI_RD = 0x0
700 06:49:09.508360 OTF = 0x1
701 06:49:09.512309 ===================================
702 06:49:09.515719 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
703 06:49:09.520828 nWR fixed to 40
704 06:49:09.520916 [ModeRegInit_LP4] CH0 RK0
705 06:49:09.524801 [ModeRegInit_LP4] CH0 RK1
706 06:49:09.528510 [ModeRegInit_LP4] CH1 RK0
707 06:49:09.528648 [ModeRegInit_LP4] CH1 RK1
708 06:49:09.532411 match AC timing 13
709 06:49:09.536181 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
710 06:49:09.539789 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
711 06:49:09.543288 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
712 06:49:09.550815 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
713 06:49:09.554595 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
714 06:49:09.554670 [EMI DOE] emi_dcm 0
715 06:49:09.558207 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
716 06:49:09.558316 ==
717 06:49:09.562078 Dram Type= 6, Freq= 0, CH_0, rank 0
718 06:49:09.565907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
719 06:49:09.569440 ==
720 06:49:09.573077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
721 06:49:09.577043 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
722 06:49:09.588177 [CA 0] Center 38 (7~69) winsize 63
723 06:49:09.591766 [CA 1] Center 38 (7~69) winsize 63
724 06:49:09.595512 [CA 2] Center 35 (5~66) winsize 62
725 06:49:09.599014 [CA 3] Center 35 (5~66) winsize 62
726 06:49:09.603175 [CA 4] Center 34 (4~65) winsize 62
727 06:49:09.606733 [CA 5] Center 34 (3~65) winsize 63
728 06:49:09.606813
729 06:49:09.610199 [CmdBusTrainingLP45] Vref(ca) range 1: 34
730 06:49:09.610278
731 06:49:09.613925 [CATrainingPosCal] consider 1 rank data
732 06:49:09.614045 u2DelayCellTimex100 = 270/100 ps
733 06:49:09.617635 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
734 06:49:09.621895 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
735 06:49:09.624997 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
736 06:49:09.628634 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
737 06:49:09.632615 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
738 06:49:09.635947 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
739 06:49:09.636024
740 06:49:09.639598 CA PerBit enable=1, Macro0, CA PI delay=34
741 06:49:09.639673
742 06:49:09.643710 [CBTSetCACLKResult] CA Dly = 34
743 06:49:09.646950 CS Dly: 5 (0~36)
744 06:49:09.647023 ==
745 06:49:09.650221 Dram Type= 6, Freq= 0, CH_0, rank 1
746 06:49:09.653837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
747 06:49:09.653948 ==
748 06:49:09.660491 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
749 06:49:09.663840 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
750 06:49:09.674363 [CA 0] Center 38 (7~69) winsize 63
751 06:49:09.677812 [CA 1] Center 38 (7~69) winsize 63
752 06:49:09.680706 [CA 2] Center 36 (5~67) winsize 63
753 06:49:09.684177 [CA 3] Center 35 (5~66) winsize 62
754 06:49:09.687397 [CA 4] Center 35 (4~66) winsize 63
755 06:49:09.690970 [CA 5] Center 34 (4~65) winsize 62
756 06:49:09.691071
757 06:49:09.693929 [CmdBusTrainingLP45] Vref(ca) range 1: 32
758 06:49:09.694043
759 06:49:09.697590 [CATrainingPosCal] consider 2 rank data
760 06:49:09.700966 u2DelayCellTimex100 = 270/100 ps
761 06:49:09.704383 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
762 06:49:09.707574 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
763 06:49:09.713901 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
764 06:49:09.717569 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
765 06:49:09.720876 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
766 06:49:09.724261 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
767 06:49:09.724335
768 06:49:09.727961 CA PerBit enable=1, Macro0, CA PI delay=34
769 06:49:09.728062
770 06:49:09.730802 [CBTSetCACLKResult] CA Dly = 34
771 06:49:09.730875 CS Dly: 6 (0~38)
772 06:49:09.730938
773 06:49:09.734671 ----->DramcWriteLeveling(PI) begin...
774 06:49:09.734772 ==
775 06:49:09.737624 Dram Type= 6, Freq= 0, CH_0, rank 0
776 06:49:09.744617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
777 06:49:09.744724 ==
778 06:49:09.747933 Write leveling (Byte 0): 30 => 30
779 06:49:09.751243 Write leveling (Byte 1): 31 => 31
780 06:49:09.751318 DramcWriteLeveling(PI) end<-----
781 06:49:09.754484
782 06:49:09.754560 ==
783 06:49:09.757628 Dram Type= 6, Freq= 0, CH_0, rank 0
784 06:49:09.761005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
785 06:49:09.761106 ==
786 06:49:09.764283 [Gating] SW mode calibration
787 06:49:09.772181 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
788 06:49:09.775627 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
789 06:49:09.779631 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
790 06:49:09.783762 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
791 06:49:09.790145 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
792 06:49:09.793516 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 06:49:09.797655 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 06:49:09.800543 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 06:49:09.807395 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 06:49:09.810635 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 06:49:09.814018 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 06:49:09.820933 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 06:49:09.824159 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 06:49:09.827701 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 06:49:09.834104 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 06:49:09.837495 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 06:49:09.840835 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 06:49:09.847267 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 06:49:09.850969 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 06:49:09.854526 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
807 06:49:09.861078 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
808 06:49:09.863988 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 06:49:09.867385 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 06:49:09.871002 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 06:49:09.877707 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 06:49:09.880605 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 06:49:09.884332 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 06:49:09.890929 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
815 06:49:09.894304 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
816 06:49:09.897482 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
817 06:49:09.904392 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 06:49:09.907514 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 06:49:09.910820 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 06:49:09.917283 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 06:49:09.921191 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
822 06:49:09.924028 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
823 06:49:09.930852 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
824 06:49:09.934518 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
825 06:49:09.937396 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 06:49:09.944071 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 06:49:09.947808 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 06:49:09.950803 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 06:49:09.954089 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 06:49:09.960870 0 11 4 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
831 06:49:09.964112 0 11 8 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
832 06:49:09.967578 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
833 06:49:09.974053 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 06:49:09.977565 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 06:49:09.980676 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 06:49:09.987774 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 06:49:09.990994 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 06:49:09.994179 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
839 06:49:10.000780 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 06:49:10.004511 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 06:49:10.007762 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 06:49:10.014408 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 06:49:10.017571 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 06:49:10.020888 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 06:49:10.027455 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 06:49:10.031056 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 06:49:10.034258 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 06:49:10.037670 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 06:49:10.044236 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 06:49:10.047899 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 06:49:10.051366 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 06:49:10.057727 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 06:49:10.061346 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 06:49:10.064440 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
855 06:49:10.071159 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 06:49:10.071258 Total UI for P1: 0, mck2ui 16
857 06:49:10.078029 best dqsien dly found for B0: ( 0, 14, 4)
858 06:49:10.078116 Total UI for P1: 0, mck2ui 16
859 06:49:10.081232 best dqsien dly found for B1: ( 0, 14, 6)
860 06:49:10.087954 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
861 06:49:10.091698 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
862 06:49:10.091802
863 06:49:10.094452 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
864 06:49:10.097850 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
865 06:49:10.101112 [Gating] SW calibration Done
866 06:49:10.101227 ==
867 06:49:10.104431 Dram Type= 6, Freq= 0, CH_0, rank 0
868 06:49:10.107966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
869 06:49:10.108068 ==
870 06:49:10.110966 RX Vref Scan: 0
871 06:49:10.111040
872 06:49:10.111109 RX Vref 0 -> 0, step: 1
873 06:49:10.111171
874 06:49:10.114560 RX Delay -130 -> 252, step: 16
875 06:49:10.117778 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
876 06:49:10.121693 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
877 06:49:10.127768 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
878 06:49:10.131399 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
879 06:49:10.134689 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
880 06:49:10.137822 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
881 06:49:10.141210 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
882 06:49:10.148320 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
883 06:49:10.151339 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
884 06:49:10.154712 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
885 06:49:10.157819 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
886 06:49:10.161461 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
887 06:49:10.167991 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
888 06:49:10.171490 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
889 06:49:10.174528 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
890 06:49:10.178059 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
891 06:49:10.178158 ==
892 06:49:10.181356 Dram Type= 6, Freq= 0, CH_0, rank 0
893 06:49:10.188259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
894 06:49:10.188362 ==
895 06:49:10.188458 DQS Delay:
896 06:49:10.191561 DQS0 = 0, DQS1 = 0
897 06:49:10.191663 DQM Delay:
898 06:49:10.191757 DQM0 = 93, DQM1 = 82
899 06:49:10.194638 DQ Delay:
900 06:49:10.198159 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
901 06:49:10.201152 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
902 06:49:10.205170 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =85
903 06:49:10.207838 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
904 06:49:10.207940
905 06:49:10.208035
906 06:49:10.208125 ==
907 06:49:10.211340 Dram Type= 6, Freq= 0, CH_0, rank 0
908 06:49:10.214863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
909 06:49:10.214940 ==
910 06:49:10.215004
911 06:49:10.215069
912 06:49:10.218115 TX Vref Scan disable
913 06:49:10.218187 == TX Byte 0 ==
914 06:49:10.224571 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 06:49:10.227807 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 06:49:10.227893 == TX Byte 1 ==
917 06:49:10.234699 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
918 06:49:10.238013 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
919 06:49:10.238089 ==
920 06:49:10.241498 Dram Type= 6, Freq= 0, CH_0, rank 0
921 06:49:10.244531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
922 06:49:10.244633 ==
923 06:49:10.258457 TX Vref=22, minBit 6, minWin=27, winSum=442
924 06:49:10.261942 TX Vref=24, minBit 6, minWin=27, winSum=442
925 06:49:10.265425 TX Vref=26, minBit 6, minWin=27, winSum=445
926 06:49:10.268730 TX Vref=28, minBit 10, minWin=27, winSum=454
927 06:49:10.272118 TX Vref=30, minBit 8, minWin=27, winSum=455
928 06:49:10.275389 TX Vref=32, minBit 8, minWin=27, winSum=453
929 06:49:10.281846 [TxChooseVref] Worse bit 8, Min win 27, Win sum 455, Final Vref 30
930 06:49:10.281973
931 06:49:10.285408 Final TX Range 1 Vref 30
932 06:49:10.285511
933 06:49:10.285609 ==
934 06:49:10.288735 Dram Type= 6, Freq= 0, CH_0, rank 0
935 06:49:10.291888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 06:49:10.291959 ==
937 06:49:10.292021
938 06:49:10.295368
939 06:49:10.295466 TX Vref Scan disable
940 06:49:10.298870 == TX Byte 0 ==
941 06:49:10.301953 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
942 06:49:10.305144 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
943 06:49:10.308838 == TX Byte 1 ==
944 06:49:10.311850 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
945 06:49:10.315173 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
946 06:49:10.315272
947 06:49:10.318744 [DATLAT]
948 06:49:10.318842 Freq=800, CH0 RK0
949 06:49:10.318906
950 06:49:10.321869 DATLAT Default: 0xa
951 06:49:10.322009 0, 0xFFFF, sum = 0
952 06:49:10.325432 1, 0xFFFF, sum = 0
953 06:49:10.325534 2, 0xFFFF, sum = 0
954 06:49:10.328914 3, 0xFFFF, sum = 0
955 06:49:10.329015 4, 0xFFFF, sum = 0
956 06:49:10.331915 5, 0xFFFF, sum = 0
957 06:49:10.331987 6, 0xFFFF, sum = 0
958 06:49:10.335636 7, 0xFFFF, sum = 0
959 06:49:10.335741 8, 0xFFFF, sum = 0
960 06:49:10.338520 9, 0x0, sum = 1
961 06:49:10.338595 10, 0x0, sum = 2
962 06:49:10.342071 11, 0x0, sum = 3
963 06:49:10.342142 12, 0x0, sum = 4
964 06:49:10.345240 best_step = 10
965 06:49:10.345334
966 06:49:10.345424 ==
967 06:49:10.348442 Dram Type= 6, Freq= 0, CH_0, rank 0
968 06:49:10.351719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
969 06:49:10.351800 ==
970 06:49:10.355284 RX Vref Scan: 1
971 06:49:10.355354
972 06:49:10.355416 Set Vref Range= 32 -> 127
973 06:49:10.355490
974 06:49:10.358807 RX Vref 32 -> 127, step: 1
975 06:49:10.358908
976 06:49:10.362145 RX Delay -95 -> 252, step: 8
977 06:49:10.362215
978 06:49:10.365271 Set Vref, RX VrefLevel [Byte0]: 32
979 06:49:10.368533 [Byte1]: 32
980 06:49:10.368629
981 06:49:10.372243 Set Vref, RX VrefLevel [Byte0]: 33
982 06:49:10.375273 [Byte1]: 33
983 06:49:10.378795
984 06:49:10.378892 Set Vref, RX VrefLevel [Byte0]: 34
985 06:49:10.382183 [Byte1]: 34
986 06:49:10.386372
987 06:49:10.386445 Set Vref, RX VrefLevel [Byte0]: 35
988 06:49:10.390056 [Byte1]: 35
989 06:49:10.394096
990 06:49:10.394202 Set Vref, RX VrefLevel [Byte0]: 36
991 06:49:10.397349 [Byte1]: 36
992 06:49:10.401506
993 06:49:10.401606 Set Vref, RX VrefLevel [Byte0]: 37
994 06:49:10.404994 [Byte1]: 37
995 06:49:10.409594
996 06:49:10.409694 Set Vref, RX VrefLevel [Byte0]: 38
997 06:49:10.412801 [Byte1]: 38
998 06:49:10.417251
999 06:49:10.417338 Set Vref, RX VrefLevel [Byte0]: 39
1000 06:49:10.420321 [Byte1]: 39
1001 06:49:10.424276
1002 06:49:10.424348 Set Vref, RX VrefLevel [Byte0]: 40
1003 06:49:10.427665 [Byte1]: 40
1004 06:49:10.431934
1005 06:49:10.432021 Set Vref, RX VrefLevel [Byte0]: 41
1006 06:49:10.435295 [Byte1]: 41
1007 06:49:10.439818
1008 06:49:10.439900 Set Vref, RX VrefLevel [Byte0]: 42
1009 06:49:10.443476 [Byte1]: 42
1010 06:49:10.448156
1011 06:49:10.448240 Set Vref, RX VrefLevel [Byte0]: 43
1012 06:49:10.451231 [Byte1]: 43
1013 06:49:10.455099
1014 06:49:10.455181 Set Vref, RX VrefLevel [Byte0]: 44
1015 06:49:10.458541 [Byte1]: 44
1016 06:49:10.462336
1017 06:49:10.462418 Set Vref, RX VrefLevel [Byte0]: 45
1018 06:49:10.466062 [Byte1]: 45
1019 06:49:10.470135
1020 06:49:10.470216 Set Vref, RX VrefLevel [Byte0]: 46
1021 06:49:10.473311 [Byte1]: 46
1022 06:49:10.477512
1023 06:49:10.477591 Set Vref, RX VrefLevel [Byte0]: 47
1024 06:49:10.480732 [Byte1]: 47
1025 06:49:10.485014
1026 06:49:10.485104 Set Vref, RX VrefLevel [Byte0]: 48
1027 06:49:10.488572 [Byte1]: 48
1028 06:49:10.493072
1029 06:49:10.493154 Set Vref, RX VrefLevel [Byte0]: 49
1030 06:49:10.495927 [Byte1]: 49
1031 06:49:10.500626
1032 06:49:10.500711 Set Vref, RX VrefLevel [Byte0]: 50
1033 06:49:10.503741 [Byte1]: 50
1034 06:49:10.508181
1035 06:49:10.508259 Set Vref, RX VrefLevel [Byte0]: 51
1036 06:49:10.511610 [Byte1]: 51
1037 06:49:10.515522
1038 06:49:10.515608 Set Vref, RX VrefLevel [Byte0]: 52
1039 06:49:10.518906 [Byte1]: 52
1040 06:49:10.523249
1041 06:49:10.523322 Set Vref, RX VrefLevel [Byte0]: 53
1042 06:49:10.526383 [Byte1]: 53
1043 06:49:10.530602
1044 06:49:10.530676 Set Vref, RX VrefLevel [Byte0]: 54
1045 06:49:10.534171 [Byte1]: 54
1046 06:49:10.538118
1047 06:49:10.538201 Set Vref, RX VrefLevel [Byte0]: 55
1048 06:49:10.541656 [Byte1]: 55
1049 06:49:10.545800
1050 06:49:10.545887 Set Vref, RX VrefLevel [Byte0]: 56
1051 06:49:10.549452 [Byte1]: 56
1052 06:49:10.553839
1053 06:49:10.553921 Set Vref, RX VrefLevel [Byte0]: 57
1054 06:49:10.556861 [Byte1]: 57
1055 06:49:10.561079
1056 06:49:10.561161 Set Vref, RX VrefLevel [Byte0]: 58
1057 06:49:10.564628 [Byte1]: 58
1058 06:49:10.568630
1059 06:49:10.568706 Set Vref, RX VrefLevel [Byte0]: 59
1060 06:49:10.572272 [Byte1]: 59
1061 06:49:10.576415
1062 06:49:10.576492 Set Vref, RX VrefLevel [Byte0]: 60
1063 06:49:10.579587 [Byte1]: 60
1064 06:49:10.583905
1065 06:49:10.583986 Set Vref, RX VrefLevel [Byte0]: 61
1066 06:49:10.587183 [Byte1]: 61
1067 06:49:10.591578
1068 06:49:10.591659 Set Vref, RX VrefLevel [Byte0]: 62
1069 06:49:10.595031 [Byte1]: 62
1070 06:49:10.599181
1071 06:49:10.599260 Set Vref, RX VrefLevel [Byte0]: 63
1072 06:49:10.602438 [Byte1]: 63
1073 06:49:10.606970
1074 06:49:10.607045 Set Vref, RX VrefLevel [Byte0]: 64
1075 06:49:10.609931 [Byte1]: 64
1076 06:49:10.614329
1077 06:49:10.614409 Set Vref, RX VrefLevel [Byte0]: 65
1078 06:49:10.617542 [Byte1]: 65
1079 06:49:10.621861
1080 06:49:10.621947 Set Vref, RX VrefLevel [Byte0]: 66
1081 06:49:10.625539 [Byte1]: 66
1082 06:49:10.630063
1083 06:49:10.630145 Set Vref, RX VrefLevel [Byte0]: 67
1084 06:49:10.632598 [Byte1]: 67
1085 06:49:10.637091
1086 06:49:10.637165 Set Vref, RX VrefLevel [Byte0]: 68
1087 06:49:10.640468 [Byte1]: 68
1088 06:49:10.644856
1089 06:49:10.644933 Set Vref, RX VrefLevel [Byte0]: 69
1090 06:49:10.648031 [Byte1]: 69
1091 06:49:10.652223
1092 06:49:10.652297 Set Vref, RX VrefLevel [Byte0]: 70
1093 06:49:10.655898 [Byte1]: 70
1094 06:49:10.659776
1095 06:49:10.659860 Set Vref, RX VrefLevel [Byte0]: 71
1096 06:49:10.663172 [Byte1]: 71
1097 06:49:10.667741
1098 06:49:10.667826 Set Vref, RX VrefLevel [Byte0]: 72
1099 06:49:10.670728 [Byte1]: 72
1100 06:49:10.675269
1101 06:49:10.675346 Set Vref, RX VrefLevel [Byte0]: 73
1102 06:49:10.678449 [Byte1]: 73
1103 06:49:10.682547
1104 06:49:10.682621 Set Vref, RX VrefLevel [Byte0]: 74
1105 06:49:10.685870 [Byte1]: 74
1106 06:49:10.690371
1107 06:49:10.690451 Set Vref, RX VrefLevel [Byte0]: 75
1108 06:49:10.693602 [Byte1]: 75
1109 06:49:10.697910
1110 06:49:10.698030 Set Vref, RX VrefLevel [Byte0]: 76
1111 06:49:10.701063 [Byte1]: 76
1112 06:49:10.705666
1113 06:49:10.705741 Set Vref, RX VrefLevel [Byte0]: 77
1114 06:49:10.709046 [Byte1]: 77
1115 06:49:10.713305
1116 06:49:10.716566 Set Vref, RX VrefLevel [Byte0]: 78
1117 06:49:10.716639 [Byte1]: 78
1118 06:49:10.720865
1119 06:49:10.720948 Final RX Vref Byte 0 = 63 to rank0
1120 06:49:10.724142 Final RX Vref Byte 1 = 62 to rank0
1121 06:49:10.727185 Final RX Vref Byte 0 = 63 to rank1
1122 06:49:10.730933 Final RX Vref Byte 1 = 62 to rank1==
1123 06:49:10.734131 Dram Type= 6, Freq= 0, CH_0, rank 0
1124 06:49:10.740620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1125 06:49:10.740696 ==
1126 06:49:10.740785 DQS Delay:
1127 06:49:10.740862 DQS0 = 0, DQS1 = 0
1128 06:49:10.744459 DQM Delay:
1129 06:49:10.744531 DQM0 = 93, DQM1 = 83
1130 06:49:10.747494 DQ Delay:
1131 06:49:10.750902 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1132 06:49:10.754160 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1133 06:49:10.754240 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1134 06:49:10.760756 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1135 06:49:10.760836
1136 06:49:10.760914
1137 06:49:10.767352 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1138 06:49:10.770797 CH0 RK0: MR19=606, MR18=3D38
1139 06:49:10.777451 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1140 06:49:10.777527
1141 06:49:10.780497 ----->DramcWriteLeveling(PI) begin...
1142 06:49:10.780578 ==
1143 06:49:10.783852 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 06:49:10.787446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 06:49:10.787523 ==
1146 06:49:10.790614 Write leveling (Byte 0): 35 => 35
1147 06:49:10.793925 Write leveling (Byte 1): 29 => 29
1148 06:49:10.797297 DramcWriteLeveling(PI) end<-----
1149 06:49:10.797372
1150 06:49:10.797451 ==
1151 06:49:10.800926 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 06:49:10.804025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 06:49:10.804099 ==
1154 06:49:10.807515 [Gating] SW mode calibration
1155 06:49:10.813841 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1156 06:49:10.820619 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1157 06:49:10.823732 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1158 06:49:10.827297 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1159 06:49:10.833680 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1160 06:49:10.837299 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 06:49:10.881326 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 06:49:10.881637 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 06:49:10.881718 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 06:49:10.881826 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 06:49:10.882112 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 06:49:10.882696 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 06:49:10.882950 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 06:49:10.883035 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 06:49:10.883132 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 06:49:10.883634 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 06:49:10.925579 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 06:49:10.925863 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 06:49:10.925962 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 06:49:10.926047 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1175 06:49:10.926314 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 06:49:10.926408 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 06:49:10.926667 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 06:49:10.926923 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 06:49:10.926994 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 06:49:10.927072 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 06:49:10.941327 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 06:49:10.941595 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 06:49:10.944840 0 9 8 | B1->B0 | 2c2c 3333 | 1 0 | (0 0) (0 0)
1184 06:49:10.944931 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 06:49:10.947725 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 06:49:10.951262 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 06:49:10.954455 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 06:49:10.960994 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 06:49:10.964368 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 06:49:10.967827 0 10 4 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
1191 06:49:10.974652 0 10 8 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
1192 06:49:10.977799 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 06:49:10.981503 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 06:49:10.987700 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 06:49:10.990975 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 06:49:10.994614 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 06:49:11.001024 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 06:49:11.004736 0 11 4 | B1->B0 | 2727 3838 | 1 0 | (0 0) (0 0)
1199 06:49:11.007917 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1200 06:49:11.014613 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 06:49:11.018469 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 06:49:11.021790 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 06:49:11.025903 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 06:49:11.029373 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 06:49:11.036510 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 06:49:11.039901 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 06:49:11.043508 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1208 06:49:11.047220 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 06:49:11.053915 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 06:49:11.057824 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 06:49:11.061039 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 06:49:11.067477 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 06:49:11.070712 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 06:49:11.074073 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 06:49:11.077354 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 06:49:11.084354 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 06:49:11.087531 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 06:49:11.090808 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 06:49:11.097554 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 06:49:11.100968 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 06:49:11.104142 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 06:49:11.110701 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1223 06:49:11.114385 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 06:49:11.117583 Total UI for P1: 0, mck2ui 16
1225 06:49:11.120893 best dqsien dly found for B0: ( 0, 14, 4)
1226 06:49:11.124370 Total UI for P1: 0, mck2ui 16
1227 06:49:11.127530 best dqsien dly found for B1: ( 0, 14, 4)
1228 06:49:11.131013 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1229 06:49:11.134379 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1230 06:49:11.134462
1231 06:49:11.137611 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1232 06:49:11.141509 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1233 06:49:11.144164 [Gating] SW calibration Done
1234 06:49:11.144247 ==
1235 06:49:11.147939 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 06:49:11.151031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 06:49:11.151115 ==
1238 06:49:11.154846 RX Vref Scan: 0
1239 06:49:11.154929
1240 06:49:11.157747 RX Vref 0 -> 0, step: 1
1241 06:49:11.157830
1242 06:49:11.157896 RX Delay -130 -> 252, step: 16
1243 06:49:11.164508 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1244 06:49:11.167746 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1245 06:49:11.171068 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1246 06:49:11.174672 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1247 06:49:11.177986 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1248 06:49:11.184462 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1249 06:49:11.187908 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1250 06:49:11.191181 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1251 06:49:11.194778 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1252 06:49:11.197739 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1253 06:49:11.204435 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1254 06:49:11.207639 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1255 06:49:11.211118 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1256 06:49:11.214516 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1257 06:49:11.217725 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1258 06:49:11.224154 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1259 06:49:11.224237 ==
1260 06:49:11.228004 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 06:49:11.230857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 06:49:11.230941 ==
1263 06:49:11.231007 DQS Delay:
1264 06:49:11.234334 DQS0 = 0, DQS1 = 0
1265 06:49:11.234417 DQM Delay:
1266 06:49:11.237457 DQM0 = 87, DQM1 = 80
1267 06:49:11.237540 DQ Delay:
1268 06:49:11.241113 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1269 06:49:11.244186 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1270 06:49:11.247925 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1271 06:49:11.250813 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1272 06:49:11.250895
1273 06:49:11.250962
1274 06:49:11.251022 ==
1275 06:49:11.254192 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 06:49:11.257494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 06:49:11.257577 ==
1278 06:49:11.261007
1279 06:49:11.261090
1280 06:49:11.261155 TX Vref Scan disable
1281 06:49:11.264232 == TX Byte 0 ==
1282 06:49:11.267525 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1283 06:49:11.270707 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1284 06:49:11.274254 == TX Byte 1 ==
1285 06:49:11.277267 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1286 06:49:11.281041 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1287 06:49:11.281123 ==
1288 06:49:11.284242 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 06:49:11.290784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 06:49:11.290869 ==
1291 06:49:11.303431 TX Vref=22, minBit 1, minWin=27, winSum=443
1292 06:49:11.306513 TX Vref=24, minBit 1, minWin=27, winSum=449
1293 06:49:11.309819 TX Vref=26, minBit 8, minWin=27, winSum=452
1294 06:49:11.313585 TX Vref=28, minBit 8, minWin=27, winSum=453
1295 06:49:11.316822 TX Vref=30, minBit 4, minWin=28, winSum=455
1296 06:49:11.323390 TX Vref=32, minBit 8, minWin=27, winSum=453
1297 06:49:11.326798 [TxChooseVref] Worse bit 4, Min win 28, Win sum 455, Final Vref 30
1298 06:49:11.326882
1299 06:49:11.330310 Final TX Range 1 Vref 30
1300 06:49:11.330393
1301 06:49:11.330457 ==
1302 06:49:11.333818 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 06:49:11.336719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 06:49:11.336800 ==
1305 06:49:11.339950
1306 06:49:11.340030
1307 06:49:11.340093 TX Vref Scan disable
1308 06:49:11.343589 == TX Byte 0 ==
1309 06:49:11.347011 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1310 06:49:11.350141 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1311 06:49:11.353521 == TX Byte 1 ==
1312 06:49:11.357245 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1313 06:49:11.360090 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1314 06:49:11.363572
1315 06:49:11.363652 [DATLAT]
1316 06:49:11.363716 Freq=800, CH0 RK1
1317 06:49:11.363777
1318 06:49:11.367130 DATLAT Default: 0xa
1319 06:49:11.367210 0, 0xFFFF, sum = 0
1320 06:49:11.370282 1, 0xFFFF, sum = 0
1321 06:49:11.370364 2, 0xFFFF, sum = 0
1322 06:49:11.373716 3, 0xFFFF, sum = 0
1323 06:49:11.373798 4, 0xFFFF, sum = 0
1324 06:49:11.376930 5, 0xFFFF, sum = 0
1325 06:49:11.377012 6, 0xFFFF, sum = 0
1326 06:49:11.380260 7, 0xFFFF, sum = 0
1327 06:49:11.383583 8, 0xFFFF, sum = 0
1328 06:49:11.383666 9, 0x0, sum = 1
1329 06:49:11.383731 10, 0x0, sum = 2
1330 06:49:11.386960 11, 0x0, sum = 3
1331 06:49:11.387043 12, 0x0, sum = 4
1332 06:49:11.390316 best_step = 10
1333 06:49:11.390398
1334 06:49:11.390462 ==
1335 06:49:11.393613 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 06:49:11.396936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 06:49:11.397018 ==
1338 06:49:11.400356 RX Vref Scan: 0
1339 06:49:11.400437
1340 06:49:11.400501 RX Vref 0 -> 0, step: 1
1341 06:49:11.400561
1342 06:49:11.403650 RX Delay -95 -> 252, step: 8
1343 06:49:11.410510 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1344 06:49:11.413752 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1345 06:49:11.417100 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1346 06:49:11.420905 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1347 06:49:11.423830 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1348 06:49:11.430452 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1349 06:49:11.433905 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1350 06:49:11.437072 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1351 06:49:11.440586 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1352 06:49:11.443699 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1353 06:49:11.450229 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1354 06:49:11.454173 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1355 06:49:11.457075 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1356 06:49:11.460350 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1357 06:49:11.463891 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1358 06:49:11.470447 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1359 06:49:11.470528 ==
1360 06:49:11.473836 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 06:49:11.477006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 06:49:11.477088 ==
1363 06:49:11.477153 DQS Delay:
1364 06:49:11.480239 DQS0 = 0, DQS1 = 0
1365 06:49:11.480320 DQM Delay:
1366 06:49:11.483891 DQM0 = 91, DQM1 = 81
1367 06:49:11.483972 DQ Delay:
1368 06:49:11.486992 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84
1369 06:49:11.490484 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1370 06:49:11.493865 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1371 06:49:11.496938 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =84
1372 06:49:11.497019
1373 06:49:11.497084
1374 06:49:11.503969 [DQSOSCAuto] RK1, (LSB)MR18= 0x4820, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1375 06:49:11.506882 CH0 RK1: MR19=606, MR18=4820
1376 06:49:11.513595 CH0_RK1: MR19=0x606, MR18=0x4820, DQSOSC=391, MR23=63, INC=96, DEC=64
1377 06:49:11.516895 [RxdqsGatingPostProcess] freq 800
1378 06:49:11.523760 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1379 06:49:11.526884 Pre-setting of DQS Precalculation
1380 06:49:11.530278 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1381 06:49:11.530361 ==
1382 06:49:11.534058 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 06:49:11.537216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 06:49:11.537298 ==
1385 06:49:11.543611 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1386 06:49:11.550052 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1387 06:49:11.558839 [CA 0] Center 36 (6~67) winsize 62
1388 06:49:11.561972 [CA 1] Center 36 (6~67) winsize 62
1389 06:49:11.565193 [CA 2] Center 34 (4~65) winsize 62
1390 06:49:11.568749 [CA 3] Center 34 (4~65) winsize 62
1391 06:49:11.572191 [CA 4] Center 34 (4~65) winsize 62
1392 06:49:11.575519 [CA 5] Center 33 (3~64) winsize 62
1393 06:49:11.575603
1394 06:49:11.578697 [CmdBusTrainingLP45] Vref(ca) range 1: 28
1395 06:49:11.578781
1396 06:49:11.582301 [CATrainingPosCal] consider 1 rank data
1397 06:49:11.585523 u2DelayCellTimex100 = 270/100 ps
1398 06:49:11.588973 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1399 06:49:11.592183 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1400 06:49:11.595597 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1401 06:49:11.602399 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1402 06:49:11.605586 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1403 06:49:11.608979 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1404 06:49:11.609063
1405 06:49:11.612331 CA PerBit enable=1, Macro0, CA PI delay=33
1406 06:49:11.612415
1407 06:49:11.615693 [CBTSetCACLKResult] CA Dly = 33
1408 06:49:11.615777 CS Dly: 5 (0~36)
1409 06:49:11.615845 ==
1410 06:49:11.619278 Dram Type= 6, Freq= 0, CH_1, rank 1
1411 06:49:11.625899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 06:49:11.626021 ==
1413 06:49:11.628930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 06:49:11.635773 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 06:49:11.644815 [CA 0] Center 37 (6~68) winsize 63
1416 06:49:11.647985 [CA 1] Center 37 (6~68) winsize 63
1417 06:49:11.651590 [CA 2] Center 35 (5~66) winsize 62
1418 06:49:11.654703 [CA 3] Center 34 (4~65) winsize 62
1419 06:49:11.658274 [CA 4] Center 34 (4~65) winsize 62
1420 06:49:11.661568 [CA 5] Center 34 (4~64) winsize 61
1421 06:49:11.661652
1422 06:49:11.664729 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1423 06:49:11.664814
1424 06:49:11.668329 [CATrainingPosCal] consider 2 rank data
1425 06:49:11.671866 u2DelayCellTimex100 = 270/100 ps
1426 06:49:11.675266 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 06:49:11.678197 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1428 06:49:11.685383 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1429 06:49:11.685468 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 06:49:11.688985 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1431 06:49:11.692906 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1432 06:49:11.692990
1433 06:49:11.696887 CA PerBit enable=1, Macro0, CA PI delay=34
1434 06:49:11.700191
1435 06:49:11.700274 [CBTSetCACLKResult] CA Dly = 34
1436 06:49:11.704066 CS Dly: 6 (0~38)
1437 06:49:11.704149
1438 06:49:11.707979 ----->DramcWriteLeveling(PI) begin...
1439 06:49:11.708064 ==
1440 06:49:11.711783 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 06:49:11.715334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 06:49:11.715419 ==
1443 06:49:11.719126 Write leveling (Byte 0): 27 => 27
1444 06:49:11.719210 Write leveling (Byte 1): 31 => 31
1445 06:49:11.722499 DramcWriteLeveling(PI) end<-----
1446 06:49:11.722583
1447 06:49:11.722649 ==
1448 06:49:11.725860 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 06:49:11.732212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 06:49:11.732301 ==
1451 06:49:11.732367 [Gating] SW mode calibration
1452 06:49:11.742447 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1453 06:49:11.745837 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1454 06:49:11.749244 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1455 06:49:11.755599 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1456 06:49:11.759211 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 06:49:11.762467 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 06:49:11.769076 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 06:49:11.772679 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 06:49:11.775930 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 06:49:11.782517 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 06:49:11.785729 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 06:49:11.789535 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 06:49:11.795781 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 06:49:11.799311 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 06:49:11.802397 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 06:49:11.809199 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 06:49:11.812678 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 06:49:11.816251 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1470 06:49:11.819411 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1471 06:49:11.825851 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1472 06:49:11.829374 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 06:49:11.832569 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 06:49:11.839654 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 06:49:11.842545 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 06:49:11.845887 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 06:49:11.852387 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 06:49:11.855971 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 06:49:11.859258 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1480 06:49:11.866020 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 06:49:11.869384 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 06:49:11.872475 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 06:49:11.879172 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 06:49:11.883093 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 06:49:11.886044 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 06:49:11.892613 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 06:49:11.896063 0 10 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
1488 06:49:11.899245 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 06:49:11.902846 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 06:49:11.909738 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 06:49:11.912727 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 06:49:11.916126 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 06:49:11.922797 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 06:49:11.926182 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 06:49:11.929839 0 11 4 | B1->B0 | 3030 3a3a | 1 0 | (0 0) (0 0)
1496 06:49:11.936102 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1497 06:49:11.939486 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 06:49:11.942824 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 06:49:11.949388 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 06:49:11.953414 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 06:49:11.955949 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 06:49:11.962491 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 06:49:11.966203 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1504 06:49:11.969484 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1505 06:49:11.975921 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 06:49:11.979677 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 06:49:11.982912 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 06:49:11.986140 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 06:49:11.992724 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 06:49:11.996044 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 06:49:11.999407 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 06:49:12.006114 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 06:49:12.009377 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 06:49:12.012839 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 06:49:12.019938 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 06:49:12.022837 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 06:49:12.026181 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 06:49:12.033069 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1519 06:49:12.036180 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 06:49:12.039430 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 06:49:12.042945 Total UI for P1: 0, mck2ui 16
1522 06:49:12.046271 best dqsien dly found for B0: ( 0, 14, 2)
1523 06:49:12.049640 Total UI for P1: 0, mck2ui 16
1524 06:49:12.052994 best dqsien dly found for B1: ( 0, 14, 2)
1525 06:49:12.056562 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1526 06:49:12.059674 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1527 06:49:12.059758
1528 06:49:12.062934 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1529 06:49:12.069554 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1530 06:49:12.069638 [Gating] SW calibration Done
1531 06:49:12.069705 ==
1532 06:49:12.072857 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 06:49:12.079769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 06:49:12.079853 ==
1535 06:49:12.079921 RX Vref Scan: 0
1536 06:49:12.079984
1537 06:49:12.082888 RX Vref 0 -> 0, step: 1
1538 06:49:12.082971
1539 06:49:12.086108 RX Delay -130 -> 252, step: 16
1540 06:49:12.090017 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1541 06:49:12.092905 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1542 06:49:12.096593 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1543 06:49:12.100134 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1544 06:49:12.106723 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1545 06:49:12.109713 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1546 06:49:12.113196 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1547 06:49:12.116538 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1548 06:49:12.119800 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1549 06:49:12.126907 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1550 06:49:12.129673 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1551 06:49:12.133089 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1552 06:49:12.136603 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1553 06:49:12.139977 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1554 06:49:12.146319 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1555 06:49:12.149440 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1556 06:49:12.149523 ==
1557 06:49:12.153108 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 06:49:12.156499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 06:49:12.156584 ==
1560 06:49:12.159898 DQS Delay:
1561 06:49:12.159982 DQS0 = 0, DQS1 = 0
1562 06:49:12.160048 DQM Delay:
1563 06:49:12.163009 DQM0 = 87, DQM1 = 80
1564 06:49:12.163093 DQ Delay:
1565 06:49:12.166470 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1566 06:49:12.169611 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1567 06:49:12.172927 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1568 06:49:12.176276 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1569 06:49:12.176385
1570 06:49:12.176479
1571 06:49:12.176557 ==
1572 06:49:12.179645 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 06:49:12.186584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 06:49:12.186668 ==
1575 06:49:12.186735
1576 06:49:12.186797
1577 06:49:12.186856 TX Vref Scan disable
1578 06:49:12.190175 == TX Byte 0 ==
1579 06:49:12.193482 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1580 06:49:12.196916 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1581 06:49:12.199867 == TX Byte 1 ==
1582 06:49:12.203513 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1583 06:49:12.207060 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1584 06:49:12.210021 ==
1585 06:49:12.213503 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 06:49:12.216767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 06:49:12.216851 ==
1588 06:49:12.229352 TX Vref=22, minBit 15, minWin=26, winSum=449
1589 06:49:12.232514 TX Vref=24, minBit 15, minWin=27, winSum=452
1590 06:49:12.236200 TX Vref=26, minBit 15, minWin=27, winSum=456
1591 06:49:12.239687 TX Vref=28, minBit 15, minWin=27, winSum=455
1592 06:49:12.242648 TX Vref=30, minBit 15, minWin=27, winSum=459
1593 06:49:12.249175 TX Vref=32, minBit 12, minWin=27, winSum=459
1594 06:49:12.252624 [TxChooseVref] Worse bit 15, Min win 27, Win sum 459, Final Vref 30
1595 06:49:12.252709
1596 06:49:12.256327 Final TX Range 1 Vref 30
1597 06:49:12.256411
1598 06:49:12.256478 ==
1599 06:49:12.259184 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 06:49:12.262589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 06:49:12.266064 ==
1602 06:49:12.266148
1603 06:49:12.266214
1604 06:49:12.266276 TX Vref Scan disable
1605 06:49:12.270440 == TX Byte 0 ==
1606 06:49:12.273493 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1607 06:49:12.277191 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1608 06:49:12.280483 == TX Byte 1 ==
1609 06:49:12.283836 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1610 06:49:12.287029 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1611 06:49:12.287113
1612 06:49:12.290544 [DATLAT]
1613 06:49:12.290628 Freq=800, CH1 RK0
1614 06:49:12.290695
1615 06:49:12.293827 DATLAT Default: 0xa
1616 06:49:12.293936 0, 0xFFFF, sum = 0
1617 06:49:12.296919 1, 0xFFFF, sum = 0
1618 06:49:12.297004 2, 0xFFFF, sum = 0
1619 06:49:12.300618 3, 0xFFFF, sum = 0
1620 06:49:12.300704 4, 0xFFFF, sum = 0
1621 06:49:12.303915 5, 0xFFFF, sum = 0
1622 06:49:12.304000 6, 0xFFFF, sum = 0
1623 06:49:12.306969 7, 0xFFFF, sum = 0
1624 06:49:12.307055 8, 0xFFFF, sum = 0
1625 06:49:12.310116 9, 0x0, sum = 1
1626 06:49:12.310201 10, 0x0, sum = 2
1627 06:49:12.313543 11, 0x0, sum = 3
1628 06:49:12.313628 12, 0x0, sum = 4
1629 06:49:12.317202 best_step = 10
1630 06:49:12.317286
1631 06:49:12.317352 ==
1632 06:49:12.320352 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 06:49:12.323727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 06:49:12.323811 ==
1635 06:49:12.326983 RX Vref Scan: 1
1636 06:49:12.327066
1637 06:49:12.327133 Set Vref Range= 32 -> 127
1638 06:49:12.327195
1639 06:49:12.330451 RX Vref 32 -> 127, step: 1
1640 06:49:12.330536
1641 06:49:12.333508 RX Delay -95 -> 252, step: 8
1642 06:49:12.333592
1643 06:49:12.336974 Set Vref, RX VrefLevel [Byte0]: 32
1644 06:49:12.340376 [Byte1]: 32
1645 06:49:12.340460
1646 06:49:12.343640 Set Vref, RX VrefLevel [Byte0]: 33
1647 06:49:12.347071 [Byte1]: 33
1648 06:49:12.347155
1649 06:49:12.350163 Set Vref, RX VrefLevel [Byte0]: 34
1650 06:49:12.353841 [Byte1]: 34
1651 06:49:12.357813
1652 06:49:12.357922 Set Vref, RX VrefLevel [Byte0]: 35
1653 06:49:12.360868 [Byte1]: 35
1654 06:49:12.365535
1655 06:49:12.365619 Set Vref, RX VrefLevel [Byte0]: 36
1656 06:49:12.368540 [Byte1]: 36
1657 06:49:12.373238
1658 06:49:12.373322 Set Vref, RX VrefLevel [Byte0]: 37
1659 06:49:12.376103 [Byte1]: 37
1660 06:49:12.380334
1661 06:49:12.380417 Set Vref, RX VrefLevel [Byte0]: 38
1662 06:49:12.383905 [Byte1]: 38
1663 06:49:12.388383
1664 06:49:12.388467 Set Vref, RX VrefLevel [Byte0]: 39
1665 06:49:12.391248 [Byte1]: 39
1666 06:49:12.395763
1667 06:49:12.395846 Set Vref, RX VrefLevel [Byte0]: 40
1668 06:49:12.398808 [Byte1]: 40
1669 06:49:12.403420
1670 06:49:12.403503 Set Vref, RX VrefLevel [Byte0]: 41
1671 06:49:12.406684 [Byte1]: 41
1672 06:49:12.410681
1673 06:49:12.410765 Set Vref, RX VrefLevel [Byte0]: 42
1674 06:49:12.414353 [Byte1]: 42
1675 06:49:12.418347
1676 06:49:12.418431 Set Vref, RX VrefLevel [Byte0]: 43
1677 06:49:12.421915 [Byte1]: 43
1678 06:49:12.426382
1679 06:49:12.426465 Set Vref, RX VrefLevel [Byte0]: 44
1680 06:49:12.429500 [Byte1]: 44
1681 06:49:12.433592
1682 06:49:12.433676 Set Vref, RX VrefLevel [Byte0]: 45
1683 06:49:12.437002 [Byte1]: 45
1684 06:49:12.441419
1685 06:49:12.441502 Set Vref, RX VrefLevel [Byte0]: 46
1686 06:49:12.445104 [Byte1]: 46
1687 06:49:12.448986
1688 06:49:12.449070 Set Vref, RX VrefLevel [Byte0]: 47
1689 06:49:12.452177 [Byte1]: 47
1690 06:49:12.456693
1691 06:49:12.456776 Set Vref, RX VrefLevel [Byte0]: 48
1692 06:49:12.459937 [Byte1]: 48
1693 06:49:12.464146
1694 06:49:12.464229 Set Vref, RX VrefLevel [Byte0]: 49
1695 06:49:12.467242 [Byte1]: 49
1696 06:49:12.471768
1697 06:49:12.471852 Set Vref, RX VrefLevel [Byte0]: 50
1698 06:49:12.475042 [Byte1]: 50
1699 06:49:12.479143
1700 06:49:12.479227 Set Vref, RX VrefLevel [Byte0]: 51
1701 06:49:12.482937 [Byte1]: 51
1702 06:49:12.486717
1703 06:49:12.486801 Set Vref, RX VrefLevel [Byte0]: 52
1704 06:49:12.490269 [Byte1]: 52
1705 06:49:12.494805
1706 06:49:12.494888 Set Vref, RX VrefLevel [Byte0]: 53
1707 06:49:12.497850 [Byte1]: 53
1708 06:49:12.501994
1709 06:49:12.502077 Set Vref, RX VrefLevel [Byte0]: 54
1710 06:49:12.505775 [Byte1]: 54
1711 06:49:12.509854
1712 06:49:12.509962 Set Vref, RX VrefLevel [Byte0]: 55
1713 06:49:12.512882 [Byte1]: 55
1714 06:49:12.517184
1715 06:49:12.517267 Set Vref, RX VrefLevel [Byte0]: 56
1716 06:49:12.520624 [Byte1]: 56
1717 06:49:12.525065
1718 06:49:12.525148 Set Vref, RX VrefLevel [Byte0]: 57
1719 06:49:12.528545 [Byte1]: 57
1720 06:49:12.532349
1721 06:49:12.532433 Set Vref, RX VrefLevel [Byte0]: 58
1722 06:49:12.535567 [Byte1]: 58
1723 06:49:12.540187
1724 06:49:12.540271 Set Vref, RX VrefLevel [Byte0]: 59
1725 06:49:12.543289 [Byte1]: 59
1726 06:49:12.547903
1727 06:49:12.547987 Set Vref, RX VrefLevel [Byte0]: 60
1728 06:49:12.551090 [Byte1]: 60
1729 06:49:12.555085
1730 06:49:12.555169 Set Vref, RX VrefLevel [Byte0]: 61
1731 06:49:12.558711 [Byte1]: 61
1732 06:49:12.562854
1733 06:49:12.562964 Set Vref, RX VrefLevel [Byte0]: 62
1734 06:49:12.566195 [Byte1]: 62
1735 06:49:12.570414
1736 06:49:12.570497 Set Vref, RX VrefLevel [Byte0]: 63
1737 06:49:12.573867 [Byte1]: 63
1738 06:49:12.578043
1739 06:49:12.578126 Set Vref, RX VrefLevel [Byte0]: 64
1740 06:49:12.581284 [Byte1]: 64
1741 06:49:12.585732
1742 06:49:12.585816 Set Vref, RX VrefLevel [Byte0]: 65
1743 06:49:12.588918 [Byte1]: 65
1744 06:49:12.593328
1745 06:49:12.593439 Set Vref, RX VrefLevel [Byte0]: 66
1746 06:49:12.596765 [Byte1]: 66
1747 06:49:12.601065
1748 06:49:12.601143 Set Vref, RX VrefLevel [Byte0]: 67
1749 06:49:12.604231 [Byte1]: 67
1750 06:49:12.608284
1751 06:49:12.608364 Set Vref, RX VrefLevel [Byte0]: 68
1752 06:49:12.612103 [Byte1]: 68
1753 06:49:12.615906
1754 06:49:12.615983 Set Vref, RX VrefLevel [Byte0]: 69
1755 06:49:12.619382 [Byte1]: 69
1756 06:49:12.623822
1757 06:49:12.623910 Set Vref, RX VrefLevel [Byte0]: 70
1758 06:49:12.626902 [Byte1]: 70
1759 06:49:12.631167
1760 06:49:12.631250 Set Vref, RX VrefLevel [Byte0]: 71
1761 06:49:12.634531 [Byte1]: 71
1762 06:49:12.638903
1763 06:49:12.638997 Set Vref, RX VrefLevel [Byte0]: 72
1764 06:49:12.642149 [Byte1]: 72
1765 06:49:12.646416
1766 06:49:12.646519 Set Vref, RX VrefLevel [Byte0]: 73
1767 06:49:12.649551 [Byte1]: 73
1768 06:49:12.654133
1769 06:49:12.654215 Set Vref, RX VrefLevel [Byte0]: 74
1770 06:49:12.657337 [Byte1]: 74
1771 06:49:12.661573
1772 06:49:12.661659 Set Vref, RX VrefLevel [Byte0]: 75
1773 06:49:12.665046 [Byte1]: 75
1774 06:49:12.669354
1775 06:49:12.669437 Set Vref, RX VrefLevel [Byte0]: 76
1776 06:49:12.672348 [Byte1]: 76
1777 06:49:12.677081
1778 06:49:12.677163 Set Vref, RX VrefLevel [Byte0]: 77
1779 06:49:12.680426 [Byte1]: 77
1780 06:49:12.684359
1781 06:49:12.684442 Set Vref, RX VrefLevel [Byte0]: 78
1782 06:49:12.687491 [Byte1]: 78
1783 06:49:12.692181
1784 06:49:12.692264 Final RX Vref Byte 0 = 52 to rank0
1785 06:49:12.695467 Final RX Vref Byte 1 = 63 to rank0
1786 06:49:12.698700 Final RX Vref Byte 0 = 52 to rank1
1787 06:49:12.701937 Final RX Vref Byte 1 = 63 to rank1==
1788 06:49:12.705409 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 06:49:12.708880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 06:49:12.711947 ==
1791 06:49:12.712030 DQS Delay:
1792 06:49:12.712095 DQS0 = 0, DQS1 = 0
1793 06:49:12.715294 DQM Delay:
1794 06:49:12.715377 DQM0 = 91, DQM1 = 81
1795 06:49:12.718746 DQ Delay:
1796 06:49:12.722047 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1797 06:49:12.725497 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1798 06:49:12.725579 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1799 06:49:12.732380 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1800 06:49:12.732463
1801 06:49:12.732528
1802 06:49:12.738600 [DQSOSCAuto] RK0, (LSB)MR18= 0x304d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1803 06:49:12.742429 CH1 RK0: MR19=606, MR18=304D
1804 06:49:12.748622 CH1_RK0: MR19=0x606, MR18=0x304D, DQSOSC=390, MR23=63, INC=97, DEC=64
1805 06:49:12.748705
1806 06:49:12.751880 ----->DramcWriteLeveling(PI) begin...
1807 06:49:12.751964 ==
1808 06:49:12.755440 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 06:49:12.758641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 06:49:12.758723 ==
1811 06:49:12.762247 Write leveling (Byte 0): 29 => 29
1812 06:49:12.765667 Write leveling (Byte 1): 29 => 29
1813 06:49:12.768918 DramcWriteLeveling(PI) end<-----
1814 06:49:12.769000
1815 06:49:12.769065 ==
1816 06:49:12.772338 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 06:49:12.775393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 06:49:12.775476 ==
1819 06:49:12.778937 [Gating] SW mode calibration
1820 06:49:12.785833 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 06:49:12.792200 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 06:49:12.795712 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1823 06:49:12.798919 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1824 06:49:12.805891 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1825 06:49:12.808987 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 06:49:12.813348 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 06:49:12.818890 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 06:49:12.822271 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 06:49:12.825849 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 06:49:12.829221 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 06:49:12.835673 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 06:49:12.839027 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 06:49:12.842985 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 06:49:12.849244 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 06:49:12.852537 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 06:49:12.855773 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 06:49:12.862858 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 06:49:12.865799 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 06:49:12.869294 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1840 06:49:12.875752 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 06:49:12.879301 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 06:49:12.882655 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 06:49:12.889379 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 06:49:12.892546 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 06:49:12.895632 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 06:49:12.902478 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 06:49:12.905932 0 9 4 | B1->B0 | 2424 2424 | 1 1 | (1 1) (1 1)
1848 06:49:12.909113 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1849 06:49:12.915893 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 06:49:12.919064 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 06:49:12.922391 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 06:49:12.925965 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 06:49:12.932847 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 06:49:12.935970 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 06:49:12.939378 0 10 4 | B1->B0 | 2a2a 2f2f | 1 1 | (1 0) (1 0)
1856 06:49:12.946112 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 06:49:12.949144 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 06:49:12.952610 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 06:49:12.959239 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 06:49:12.962938 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 06:49:12.965855 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 06:49:12.972598 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 06:49:12.976110 0 11 4 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
1864 06:49:12.979314 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1865 06:49:12.985853 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 06:49:12.989082 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 06:49:12.992365 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 06:49:12.999087 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 06:49:13.002359 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 06:49:13.006304 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 06:49:13.012554 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1872 06:49:13.015710 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 06:49:13.018981 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 06:49:13.022302 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 06:49:13.029352 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 06:49:13.032685 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 06:49:13.036075 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 06:49:13.042422 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 06:49:13.045764 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 06:49:13.049414 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 06:49:13.055893 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 06:49:13.058990 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 06:49:13.062341 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 06:49:13.069043 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 06:49:13.072757 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 06:49:13.075834 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 06:49:13.082544 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1888 06:49:13.085586 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1889 06:49:13.089289 Total UI for P1: 0, mck2ui 16
1890 06:49:13.092522 best dqsien dly found for B1: ( 0, 14, 4)
1891 06:49:13.095848 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 06:49:13.099119 Total UI for P1: 0, mck2ui 16
1893 06:49:13.102431 best dqsien dly found for B0: ( 0, 14, 6)
1894 06:49:13.106115 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1895 06:49:13.109238 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1896 06:49:13.109321
1897 06:49:13.112523 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1898 06:49:13.119131 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1899 06:49:13.119214 [Gating] SW calibration Done
1900 06:49:13.119281 ==
1901 06:49:13.122601 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 06:49:13.129350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 06:49:13.129434 ==
1904 06:49:13.129501 RX Vref Scan: 0
1905 06:49:13.129562
1906 06:49:13.132740 RX Vref 0 -> 0, step: 1
1907 06:49:13.132823
1908 06:49:13.136454 RX Delay -130 -> 252, step: 16
1909 06:49:13.139403 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1910 06:49:13.142631 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1911 06:49:13.145862 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1912 06:49:13.149291 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1913 06:49:13.155795 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1914 06:49:13.159406 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1915 06:49:13.162409 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1916 06:49:13.166170 iDelay=222, Bit 7, Center 85 (-18 ~ 189) 208
1917 06:49:13.169299 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1918 06:49:13.175652 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1919 06:49:13.179294 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1920 06:49:13.182695 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1921 06:49:13.185775 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1922 06:49:13.189264 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1923 06:49:13.196060 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1924 06:49:13.199233 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1925 06:49:13.199316 ==
1926 06:49:13.202635 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 06:49:13.205828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 06:49:13.205915 ==
1929 06:49:13.209346 DQS Delay:
1930 06:49:13.209430 DQS0 = 0, DQS1 = 0
1931 06:49:13.209496 DQM Delay:
1932 06:49:13.212895 DQM0 = 91, DQM1 = 82
1933 06:49:13.212979 DQ Delay:
1934 06:49:13.216059 DQ0 =101, DQ1 =77, DQ2 =77, DQ3 =85
1935 06:49:13.219314 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =85
1936 06:49:13.222865 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1937 06:49:13.226344 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1938 06:49:13.226428
1939 06:49:13.226494
1940 06:49:13.226556 ==
1941 06:49:13.229641 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 06:49:13.236029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 06:49:13.236114 ==
1944 06:49:13.236181
1945 06:49:13.236243
1946 06:49:13.236302 TX Vref Scan disable
1947 06:49:13.239598 == TX Byte 0 ==
1948 06:49:13.242849 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1949 06:49:13.246301 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1950 06:49:13.249488 == TX Byte 1 ==
1951 06:49:13.252634 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1952 06:49:13.259660 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1953 06:49:13.259747 ==
1954 06:49:13.262817 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 06:49:13.266506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 06:49:13.266591 ==
1957 06:49:13.278492 TX Vref=22, minBit 13, minWin=27, winSum=449
1958 06:49:13.282192 TX Vref=24, minBit 13, minWin=27, winSum=455
1959 06:49:13.285562 TX Vref=26, minBit 0, minWin=28, winSum=457
1960 06:49:13.288958 TX Vref=28, minBit 9, minWin=28, winSum=458
1961 06:49:13.292059 TX Vref=30, minBit 15, minWin=27, winSum=459
1962 06:49:13.295438 TX Vref=32, minBit 8, minWin=28, winSum=457
1963 06:49:13.302075 [TxChooseVref] Worse bit 9, Min win 28, Win sum 458, Final Vref 28
1964 06:49:13.302159
1965 06:49:13.305218 Final TX Range 1 Vref 28
1966 06:49:13.305302
1967 06:49:13.305368 ==
1968 06:49:13.309216 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 06:49:13.312077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 06:49:13.312162 ==
1971 06:49:13.312229
1972 06:49:13.315613
1973 06:49:13.315697 TX Vref Scan disable
1974 06:49:13.318861 == TX Byte 0 ==
1975 06:49:13.322187 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1976 06:49:13.325498 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1977 06:49:13.328805 == TX Byte 1 ==
1978 06:49:13.331781 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1979 06:49:13.335491 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1980 06:49:13.338606
1981 06:49:13.338690 [DATLAT]
1982 06:49:13.338756 Freq=800, CH1 RK1
1983 06:49:13.338819
1984 06:49:13.342209 DATLAT Default: 0xa
1985 06:49:13.342293 0, 0xFFFF, sum = 0
1986 06:49:13.345428 1, 0xFFFF, sum = 0
1987 06:49:13.345514 2, 0xFFFF, sum = 0
1988 06:49:13.348797 3, 0xFFFF, sum = 0
1989 06:49:13.348883 4, 0xFFFF, sum = 0
1990 06:49:13.352051 5, 0xFFFF, sum = 0
1991 06:49:13.352137 6, 0xFFFF, sum = 0
1992 06:49:13.355859 7, 0xFFFF, sum = 0
1993 06:49:13.355944 8, 0xFFFF, sum = 0
1994 06:49:13.358807 9, 0x0, sum = 1
1995 06:49:13.358893 10, 0x0, sum = 2
1996 06:49:13.362481 11, 0x0, sum = 3
1997 06:49:13.362567 12, 0x0, sum = 4
1998 06:49:13.365367 best_step = 10
1999 06:49:13.365450
2000 06:49:13.365516 ==
2001 06:49:13.368858 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 06:49:13.372136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 06:49:13.372221 ==
2004 06:49:13.375344 RX Vref Scan: 0
2005 06:49:13.375427
2006 06:49:13.375494 RX Vref 0 -> 0, step: 1
2007 06:49:13.375557
2008 06:49:13.378881 RX Delay -95 -> 252, step: 8
2009 06:49:13.385499 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2010 06:49:13.389206 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2011 06:49:13.392399 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2012 06:49:13.395501 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2013 06:49:13.398691 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2014 06:49:13.402470 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2015 06:49:13.409177 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2016 06:49:13.412289 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2017 06:49:13.415496 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2018 06:49:13.419054 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2019 06:49:13.422069 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2020 06:49:13.428870 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2021 06:49:13.432357 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2022 06:49:13.435768 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2023 06:49:13.438854 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2024 06:49:13.442313 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2025 06:49:13.445855 ==
2026 06:49:13.448997 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 06:49:13.452668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 06:49:13.452751 ==
2029 06:49:13.452815 DQS Delay:
2030 06:49:13.455894 DQS0 = 0, DQS1 = 0
2031 06:49:13.455976 DQM Delay:
2032 06:49:13.459089 DQM0 = 91, DQM1 = 82
2033 06:49:13.459171 DQ Delay:
2034 06:49:13.462281 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2035 06:49:13.466190 DQ4 =96, DQ5 =100, DQ6 =96, DQ7 =88
2036 06:49:13.468946 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2037 06:49:13.472372 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =92
2038 06:49:13.472454
2039 06:49:13.472519
2040 06:49:13.479037 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2041 06:49:13.482161 CH1 RK1: MR19=606, MR18=3B10
2042 06:49:13.489067 CH1_RK1: MR19=0x606, MR18=0x3B10, DQSOSC=394, MR23=63, INC=95, DEC=63
2043 06:49:13.492042 [RxdqsGatingPostProcess] freq 800
2044 06:49:13.495548 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2045 06:49:13.498990 Pre-setting of DQS Precalculation
2046 06:49:13.505554 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2047 06:49:13.512121 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2048 06:49:13.518743 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2049 06:49:13.518826
2050 06:49:13.518891
2051 06:49:13.522380 [Calibration Summary] 1600 Mbps
2052 06:49:13.525493 CH 0, Rank 0
2053 06:49:13.525601 SW Impedance : PASS
2054 06:49:13.528826 DUTY Scan : NO K
2055 06:49:13.528908 ZQ Calibration : PASS
2056 06:49:13.532070 Jitter Meter : NO K
2057 06:49:13.535724 CBT Training : PASS
2058 06:49:13.535806 Write leveling : PASS
2059 06:49:13.539236 RX DQS gating : PASS
2060 06:49:13.542378 RX DQ/DQS(RDDQC) : PASS
2061 06:49:13.542486 TX DQ/DQS : PASS
2062 06:49:13.545671 RX DATLAT : PASS
2063 06:49:13.548855 RX DQ/DQS(Engine): PASS
2064 06:49:13.548937 TX OE : NO K
2065 06:49:13.552186 All Pass.
2066 06:49:13.552268
2067 06:49:13.552333 CH 0, Rank 1
2068 06:49:13.555687 SW Impedance : PASS
2069 06:49:13.555769 DUTY Scan : NO K
2070 06:49:13.558855 ZQ Calibration : PASS
2071 06:49:13.562267 Jitter Meter : NO K
2072 06:49:13.562359 CBT Training : PASS
2073 06:49:13.565752 Write leveling : PASS
2074 06:49:13.565860 RX DQS gating : PASS
2075 06:49:13.569261 RX DQ/DQS(RDDQC) : PASS
2076 06:49:13.572258 TX DQ/DQS : PASS
2077 06:49:13.572340 RX DATLAT : PASS
2078 06:49:13.575543 RX DQ/DQS(Engine): PASS
2079 06:49:13.579104 TX OE : NO K
2080 06:49:13.579212 All Pass.
2081 06:49:13.579305
2082 06:49:13.579393 CH 1, Rank 0
2083 06:49:13.582732 SW Impedance : PASS
2084 06:49:13.586035 DUTY Scan : NO K
2085 06:49:13.586118 ZQ Calibration : PASS
2086 06:49:13.589172 Jitter Meter : NO K
2087 06:49:13.592603 CBT Training : PASS
2088 06:49:13.592685 Write leveling : PASS
2089 06:49:13.595855 RX DQS gating : PASS
2090 06:49:13.599193 RX DQ/DQS(RDDQC) : PASS
2091 06:49:13.599276 TX DQ/DQS : PASS
2092 06:49:13.602937 RX DATLAT : PASS
2093 06:49:13.603045 RX DQ/DQS(Engine): PASS
2094 06:49:13.605712 TX OE : NO K
2095 06:49:13.605811 All Pass.
2096 06:49:13.605902
2097 06:49:13.608925 CH 1, Rank 1
2098 06:49:13.609008 SW Impedance : PASS
2099 06:49:13.612427 DUTY Scan : NO K
2100 06:49:13.615515 ZQ Calibration : PASS
2101 06:49:13.615598 Jitter Meter : NO K
2102 06:49:13.618877 CBT Training : PASS
2103 06:49:13.622242 Write leveling : PASS
2104 06:49:13.622325 RX DQS gating : PASS
2105 06:49:13.625643 RX DQ/DQS(RDDQC) : PASS
2106 06:49:13.629113 TX DQ/DQS : PASS
2107 06:49:13.629196 RX DATLAT : PASS
2108 06:49:13.632688 RX DQ/DQS(Engine): PASS
2109 06:49:13.635728 TX OE : NO K
2110 06:49:13.635811 All Pass.
2111 06:49:13.635877
2112 06:49:13.635937 DramC Write-DBI off
2113 06:49:13.639319 PER_BANK_REFRESH: Hybrid Mode
2114 06:49:13.642258 TX_TRACKING: ON
2115 06:49:13.645842 [GetDramInforAfterCalByMRR] Vendor 6.
2116 06:49:13.648875 [GetDramInforAfterCalByMRR] Revision 606.
2117 06:49:13.652201 [GetDramInforAfterCalByMRR] Revision 2 0.
2118 06:49:13.652284 MR0 0x3b3b
2119 06:49:13.655829 MR8 0x5151
2120 06:49:13.658810 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 06:49:13.658893
2122 06:49:13.659010 MR0 0x3b3b
2123 06:49:13.659074 MR8 0x5151
2124 06:49:13.665753 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2125 06:49:13.665838
2126 06:49:13.672133 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2127 06:49:13.675748 [FAST_K] Save calibration result to emmc
2128 06:49:13.679137 [FAST_K] Save calibration result to emmc
2129 06:49:13.682451 dram_init: config_dvfs: 1
2130 06:49:13.685535 dramc_set_vcore_voltage set vcore to 662500
2131 06:49:13.689132 Read voltage for 1200, 2
2132 06:49:13.689217 Vio18 = 0
2133 06:49:13.692338 Vcore = 662500
2134 06:49:13.692422 Vdram = 0
2135 06:49:13.692489 Vddq = 0
2136 06:49:13.692552 Vmddr = 0
2137 06:49:13.699009 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2138 06:49:13.705599 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2139 06:49:13.705685 MEM_TYPE=3, freq_sel=15
2140 06:49:13.708977 sv_algorithm_assistance_LP4_1600
2141 06:49:13.712339 ============ PULL DRAM RESETB DOWN ============
2142 06:49:13.718782 ========== PULL DRAM RESETB DOWN end =========
2143 06:49:13.722348 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2144 06:49:13.725745 ===================================
2145 06:49:13.729189 LPDDR4 DRAM CONFIGURATION
2146 06:49:13.732671 ===================================
2147 06:49:13.732755 EX_ROW_EN[0] = 0x0
2148 06:49:13.735814 EX_ROW_EN[1] = 0x0
2149 06:49:13.735898 LP4Y_EN = 0x0
2150 06:49:13.738815 WORK_FSP = 0x0
2151 06:49:13.738899 WL = 0x4
2152 06:49:13.742311 RL = 0x4
2153 06:49:13.742394 BL = 0x2
2154 06:49:13.745597 RPST = 0x0
2155 06:49:13.745681 RD_PRE = 0x0
2156 06:49:13.748854 WR_PRE = 0x1
2157 06:49:13.748938 WR_PST = 0x0
2158 06:49:13.752623 DBI_WR = 0x0
2159 06:49:13.752706 DBI_RD = 0x0
2160 06:49:13.756193 OTF = 0x1
2161 06:49:13.759052 ===================================
2162 06:49:13.762361 ===================================
2163 06:49:13.762445 ANA top config
2164 06:49:13.765764 ===================================
2165 06:49:13.769382 DLL_ASYNC_EN = 0
2166 06:49:13.773009 ALL_SLAVE_EN = 0
2167 06:49:13.775897 NEW_RANK_MODE = 1
2168 06:49:13.775981 DLL_IDLE_MODE = 1
2169 06:49:13.779177 LP45_APHY_COMB_EN = 1
2170 06:49:13.782308 TX_ODT_DIS = 1
2171 06:49:13.785618 NEW_8X_MODE = 1
2172 06:49:13.789078 ===================================
2173 06:49:13.792389 ===================================
2174 06:49:13.795774 data_rate = 2400
2175 06:49:13.795859 CKR = 1
2176 06:49:13.799048 DQ_P2S_RATIO = 8
2177 06:49:13.802346 ===================================
2178 06:49:13.805806 CA_P2S_RATIO = 8
2179 06:49:13.808994 DQ_CA_OPEN = 0
2180 06:49:13.812344 DQ_SEMI_OPEN = 0
2181 06:49:13.815825 CA_SEMI_OPEN = 0
2182 06:49:13.815910 CA_FULL_RATE = 0
2183 06:49:13.819427 DQ_CKDIV4_EN = 0
2184 06:49:13.822372 CA_CKDIV4_EN = 0
2185 06:49:13.825854 CA_PREDIV_EN = 0
2186 06:49:13.829444 PH8_DLY = 17
2187 06:49:13.832352 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2188 06:49:13.832436 DQ_AAMCK_DIV = 4
2189 06:49:13.835887 CA_AAMCK_DIV = 4
2190 06:49:13.839074 CA_ADMCK_DIV = 4
2191 06:49:13.842444 DQ_TRACK_CA_EN = 0
2192 06:49:13.845850 CA_PICK = 1200
2193 06:49:13.849242 CA_MCKIO = 1200
2194 06:49:13.852277 MCKIO_SEMI = 0
2195 06:49:13.852361 PLL_FREQ = 2366
2196 06:49:13.855834 DQ_UI_PI_RATIO = 32
2197 06:49:13.858926 CA_UI_PI_RATIO = 0
2198 06:49:13.862456 ===================================
2199 06:49:13.865904 ===================================
2200 06:49:13.869158 memory_type:LPDDR4
2201 06:49:13.869241 GP_NUM : 10
2202 06:49:13.872808 SRAM_EN : 1
2203 06:49:13.876045 MD32_EN : 0
2204 06:49:13.879306 ===================================
2205 06:49:13.879391 [ANA_INIT] >>>>>>>>>>>>>>
2206 06:49:13.882732 <<<<<< [CONFIGURE PHASE]: ANA_TX
2207 06:49:13.885867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2208 06:49:13.889402 ===================================
2209 06:49:13.892794 data_rate = 2400,PCW = 0X5b00
2210 06:49:13.896067 ===================================
2211 06:49:13.899105 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2212 06:49:13.905829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 06:49:13.909516 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 06:49:13.916035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2215 06:49:13.919481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2216 06:49:13.922857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2217 06:49:13.922963 [ANA_INIT] flow start
2218 06:49:13.926160 [ANA_INIT] PLL >>>>>>>>
2219 06:49:13.929676 [ANA_INIT] PLL <<<<<<<<
2220 06:49:13.929761 [ANA_INIT] MIDPI >>>>>>>>
2221 06:49:13.933027 [ANA_INIT] MIDPI <<<<<<<<
2222 06:49:13.936433 [ANA_INIT] DLL >>>>>>>>
2223 06:49:13.936516 [ANA_INIT] DLL <<<<<<<<
2224 06:49:13.939475 [ANA_INIT] flow end
2225 06:49:13.943055 ============ LP4 DIFF to SE enter ============
2226 06:49:13.949563 ============ LP4 DIFF to SE exit ============
2227 06:49:13.949665 [ANA_INIT] <<<<<<<<<<<<<
2228 06:49:13.952737 [Flow] Enable top DCM control >>>>>
2229 06:49:13.956117 [Flow] Enable top DCM control <<<<<
2230 06:49:13.959397 Enable DLL master slave shuffle
2231 06:49:13.966381 ==============================================================
2232 06:49:13.966466 Gating Mode config
2233 06:49:13.973072 ==============================================================
2234 06:49:13.976159 Config description:
2235 06:49:13.983104 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2236 06:49:13.989374 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2237 06:49:13.996181 SELPH_MODE 0: By rank 1: By Phase
2238 06:49:13.999710 ==============================================================
2239 06:49:14.002674 GAT_TRACK_EN = 1
2240 06:49:14.006257 RX_GATING_MODE = 2
2241 06:49:14.009585 RX_GATING_TRACK_MODE = 2
2242 06:49:14.012861 SELPH_MODE = 1
2243 06:49:14.016355 PICG_EARLY_EN = 1
2244 06:49:14.019290 VALID_LAT_VALUE = 1
2245 06:49:14.026245 ==============================================================
2246 06:49:14.029580 Enter into Gating configuration >>>>
2247 06:49:14.032873 Exit from Gating configuration <<<<
2248 06:49:14.032975 Enter into DVFS_PRE_config >>>>>
2249 06:49:14.046682 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2250 06:49:14.049754 Exit from DVFS_PRE_config <<<<<
2251 06:49:14.052828 Enter into PICG configuration >>>>
2252 06:49:14.056669 Exit from PICG configuration <<<<
2253 06:49:14.056773 [RX_INPUT] configuration >>>>>
2254 06:49:14.059783 [RX_INPUT] configuration <<<<<
2255 06:49:14.066149 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2256 06:49:14.069558 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2257 06:49:14.076440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 06:49:14.083053 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 06:49:14.089981 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 06:49:14.096448 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 06:49:14.099628 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2262 06:49:14.102907 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2263 06:49:14.106393 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2264 06:49:14.113531 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2265 06:49:14.116353 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2266 06:49:14.119746 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 06:49:14.123537 ===================================
2268 06:49:14.126295 LPDDR4 DRAM CONFIGURATION
2269 06:49:14.130120 ===================================
2270 06:49:14.133290 EX_ROW_EN[0] = 0x0
2271 06:49:14.133367 EX_ROW_EN[1] = 0x0
2272 06:49:14.136535 LP4Y_EN = 0x0
2273 06:49:14.136619 WORK_FSP = 0x0
2274 06:49:14.139913 WL = 0x4
2275 06:49:14.139996 RL = 0x4
2276 06:49:14.142939 BL = 0x2
2277 06:49:14.143022 RPST = 0x0
2278 06:49:14.146521 RD_PRE = 0x0
2279 06:49:14.146603 WR_PRE = 0x1
2280 06:49:14.149566 WR_PST = 0x0
2281 06:49:14.149650 DBI_WR = 0x0
2282 06:49:14.152963 DBI_RD = 0x0
2283 06:49:14.153047 OTF = 0x1
2284 06:49:14.156967 ===================================
2285 06:49:14.159782 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2286 06:49:14.166668 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2287 06:49:14.170181 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 06:49:14.173423 ===================================
2289 06:49:14.176585 LPDDR4 DRAM CONFIGURATION
2290 06:49:14.180024 ===================================
2291 06:49:14.180106 EX_ROW_EN[0] = 0x10
2292 06:49:14.183316 EX_ROW_EN[1] = 0x0
2293 06:49:14.183399 LP4Y_EN = 0x0
2294 06:49:14.186448 WORK_FSP = 0x0
2295 06:49:14.186546 WL = 0x4
2296 06:49:14.190098 RL = 0x4
2297 06:49:14.193239 BL = 0x2
2298 06:49:14.193322 RPST = 0x0
2299 06:49:14.196619 RD_PRE = 0x0
2300 06:49:14.196700 WR_PRE = 0x1
2301 06:49:14.200079 WR_PST = 0x0
2302 06:49:14.200160 DBI_WR = 0x0
2303 06:49:14.203121 DBI_RD = 0x0
2304 06:49:14.203205 OTF = 0x1
2305 06:49:14.206763 ===================================
2306 06:49:14.213439 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2307 06:49:14.213522 ==
2308 06:49:14.216855 Dram Type= 6, Freq= 0, CH_0, rank 0
2309 06:49:14.219913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2310 06:49:14.219999 ==
2311 06:49:14.223270 [Duty_Offset_Calibration]
2312 06:49:14.223352 B0:2 B1:0 CA:1
2313 06:49:14.226925
2314 06:49:14.229808 [DutyScan_Calibration_Flow] k_type=0
2315 06:49:14.236933
2316 06:49:14.237014 ==CLK 0==
2317 06:49:14.240288 Final CLK duty delay cell = -4
2318 06:49:14.243938 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2319 06:49:14.246790 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2320 06:49:14.250210 [-4] AVG Duty = 4953%(X100)
2321 06:49:14.250318
2322 06:49:14.254178 CH0 CLK Duty spec in!! Max-Min= 156%
2323 06:49:14.256785 [DutyScan_Calibration_Flow] ====Done====
2324 06:49:14.256866
2325 06:49:14.260099 [DutyScan_Calibration_Flow] k_type=1
2326 06:49:14.275677
2327 06:49:14.275759 ==DQS 0 ==
2328 06:49:14.279145 Final DQS duty delay cell = 0
2329 06:49:14.282618 [0] MAX Duty = 5187%(X100), DQS PI = 30
2330 06:49:14.285751 [0] MIN Duty = 4938%(X100), DQS PI = 0
2331 06:49:14.285858 [0] AVG Duty = 5062%(X100)
2332 06:49:14.289201
2333 06:49:14.289282 ==DQS 1 ==
2334 06:49:14.292584 Final DQS duty delay cell = -4
2335 06:49:14.295892 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2336 06:49:14.299351 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2337 06:49:14.302586 [-4] AVG Duty = 5031%(X100)
2338 06:49:14.302668
2339 06:49:14.305852 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2340 06:49:14.305995
2341 06:49:14.309096 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2342 06:49:14.312778 [DutyScan_Calibration_Flow] ====Done====
2343 06:49:14.312885
2344 06:49:14.316241 [DutyScan_Calibration_Flow] k_type=3
2345 06:49:14.332779
2346 06:49:14.332860 ==DQM 0 ==
2347 06:49:14.335908 Final DQM duty delay cell = 0
2348 06:49:14.339368 [0] MAX Duty = 5062%(X100), DQS PI = 24
2349 06:49:14.342519 [0] MIN Duty = 4844%(X100), DQS PI = 2
2350 06:49:14.345952 [0] AVG Duty = 4953%(X100)
2351 06:49:14.346034
2352 06:49:14.346098 ==DQM 1 ==
2353 06:49:14.349311 Final DQM duty delay cell = 0
2354 06:49:14.352706 [0] MAX Duty = 5187%(X100), DQS PI = 32
2355 06:49:14.356012 [0] MIN Duty = 5000%(X100), DQS PI = 22
2356 06:49:14.356093 [0] AVG Duty = 5093%(X100)
2357 06:49:14.359272
2358 06:49:14.362742 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2359 06:49:14.362825
2360 06:49:14.366046 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2361 06:49:14.369278 [DutyScan_Calibration_Flow] ====Done====
2362 06:49:14.369359
2363 06:49:14.372734 [DutyScan_Calibration_Flow] k_type=2
2364 06:49:14.389142
2365 06:49:14.389223 ==DQ 0 ==
2366 06:49:14.392283 Final DQ duty delay cell = -4
2367 06:49:14.395765 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2368 06:49:14.398958 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2369 06:49:14.402486 [-4] AVG Duty = 4968%(X100)
2370 06:49:14.402557
2371 06:49:14.402619 ==DQ 1 ==
2372 06:49:14.405812 Final DQ duty delay cell = 4
2373 06:49:14.409067 [4] MAX Duty = 5093%(X100), DQS PI = 6
2374 06:49:14.412403 [4] MIN Duty = 5031%(X100), DQS PI = 14
2375 06:49:14.412474 [4] AVG Duty = 5062%(X100)
2376 06:49:14.415666
2377 06:49:14.419308 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2378 06:49:14.419385
2379 06:49:14.422313 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2380 06:49:14.425739 [DutyScan_Calibration_Flow] ====Done====
2381 06:49:14.425815 ==
2382 06:49:14.429147 Dram Type= 6, Freq= 0, CH_1, rank 0
2383 06:49:14.432248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2384 06:49:14.432322 ==
2385 06:49:14.435967 [Duty_Offset_Calibration]
2386 06:49:14.436073 B0:0 B1:-1 CA:2
2387 06:49:14.436173
2388 06:49:14.439123 [DutyScan_Calibration_Flow] k_type=0
2389 06:49:14.449568
2390 06:49:14.449655 ==CLK 0==
2391 06:49:14.452862 Final CLK duty delay cell = 0
2392 06:49:14.456252 [0] MAX Duty = 5156%(X100), DQS PI = 16
2393 06:49:14.459361 [0] MIN Duty = 4938%(X100), DQS PI = 44
2394 06:49:14.459442 [0] AVG Duty = 5047%(X100)
2395 06:49:14.463110
2396 06:49:14.463194 CH1 CLK Duty spec in!! Max-Min= 218%
2397 06:49:14.469440 [DutyScan_Calibration_Flow] ====Done====
2398 06:49:14.469548
2399 06:49:14.472943 [DutyScan_Calibration_Flow] k_type=1
2400 06:49:14.488914
2401 06:49:14.488995 ==DQS 0 ==
2402 06:49:14.492261 Final DQS duty delay cell = 0
2403 06:49:14.495441 [0] MAX Duty = 5093%(X100), DQS PI = 24
2404 06:49:14.498947 [0] MIN Duty = 4969%(X100), DQS PI = 0
2405 06:49:14.499031 [0] AVG Duty = 5031%(X100)
2406 06:49:14.502528
2407 06:49:14.502611 ==DQS 1 ==
2408 06:49:14.505309 Final DQS duty delay cell = 0
2409 06:49:14.508956 [0] MAX Duty = 5156%(X100), DQS PI = 0
2410 06:49:14.512160 [0] MIN Duty = 4844%(X100), DQS PI = 34
2411 06:49:14.512244 [0] AVG Duty = 5000%(X100)
2412 06:49:14.515516
2413 06:49:14.518697 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2414 06:49:14.518780
2415 06:49:14.521875 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2416 06:49:14.525719 [DutyScan_Calibration_Flow] ====Done====
2417 06:49:14.525802
2418 06:49:14.528459 [DutyScan_Calibration_Flow] k_type=3
2419 06:49:14.545470
2420 06:49:14.545554 ==DQM 0 ==
2421 06:49:14.548569 Final DQM duty delay cell = 4
2422 06:49:14.551721 [4] MAX Duty = 5093%(X100), DQS PI = 22
2423 06:49:14.555448 [4] MIN Duty = 4969%(X100), DQS PI = 28
2424 06:49:14.555532 [4] AVG Duty = 5031%(X100)
2425 06:49:14.558746
2426 06:49:14.558847 ==DQM 1 ==
2427 06:49:14.561852 Final DQM duty delay cell = -4
2428 06:49:14.565259 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2429 06:49:14.568815 [-4] MIN Duty = 4720%(X100), DQS PI = 36
2430 06:49:14.571717 [-4] AVG Duty = 4860%(X100)
2431 06:49:14.571799
2432 06:49:14.574946 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2433 06:49:14.575028
2434 06:49:14.578862 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2435 06:49:14.581866 [DutyScan_Calibration_Flow] ====Done====
2436 06:49:14.581976
2437 06:49:14.585245 [DutyScan_Calibration_Flow] k_type=2
2438 06:49:14.602159
2439 06:49:14.602268 ==DQ 0 ==
2440 06:49:14.605631 Final DQ duty delay cell = 0
2441 06:49:14.608979 [0] MAX Duty = 5062%(X100), DQS PI = 20
2442 06:49:14.612394 [0] MIN Duty = 4938%(X100), DQS PI = 0
2443 06:49:14.612478 [0] AVG Duty = 5000%(X100)
2444 06:49:14.612544
2445 06:49:14.615783 ==DQ 1 ==
2446 06:49:14.618850 Final DQ duty delay cell = 0
2447 06:49:14.622331 [0] MAX Duty = 5062%(X100), DQS PI = 4
2448 06:49:14.625729 [0] MIN Duty = 4813%(X100), DQS PI = 36
2449 06:49:14.625812 [0] AVG Duty = 4937%(X100)
2450 06:49:14.625879
2451 06:49:14.628699 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2452 06:49:14.628781
2453 06:49:14.632275 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2454 06:49:14.638927 [DutyScan_Calibration_Flow] ====Done====
2455 06:49:14.642166 nWR fixed to 30
2456 06:49:14.642249 [ModeRegInit_LP4] CH0 RK0
2457 06:49:14.645420 [ModeRegInit_LP4] CH0 RK1
2458 06:49:14.648933 [ModeRegInit_LP4] CH1 RK0
2459 06:49:14.649016 [ModeRegInit_LP4] CH1 RK1
2460 06:49:14.652385 match AC timing 7
2461 06:49:14.655404 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2462 06:49:14.659028 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2463 06:49:14.665669 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2464 06:49:14.668769 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2465 06:49:14.675630 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2466 06:49:14.675740 ==
2467 06:49:14.678830 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 06:49:14.682306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 06:49:14.682391 ==
2470 06:49:14.689005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 06:49:14.692500 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2472 06:49:14.701820 [CA 0] Center 38 (7~69) winsize 63
2473 06:49:14.705357 [CA 1] Center 38 (8~69) winsize 62
2474 06:49:14.708594 [CA 2] Center 35 (5~66) winsize 62
2475 06:49:14.711680 [CA 3] Center 34 (4~65) winsize 62
2476 06:49:14.715197 [CA 4] Center 34 (4~65) winsize 62
2477 06:49:14.718490 [CA 5] Center 33 (3~64) winsize 62
2478 06:49:14.718565
2479 06:49:14.721674 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2480 06:49:14.721774
2481 06:49:14.725541 [CATrainingPosCal] consider 1 rank data
2482 06:49:14.728420 u2DelayCellTimex100 = 270/100 ps
2483 06:49:14.731935 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2484 06:49:14.735191 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2485 06:49:14.742047 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2486 06:49:14.745358 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2487 06:49:14.748595 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2488 06:49:14.752056 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2489 06:49:14.752154
2490 06:49:14.755414 CA PerBit enable=1, Macro0, CA PI delay=33
2491 06:49:14.755524
2492 06:49:14.758438 [CBTSetCACLKResult] CA Dly = 33
2493 06:49:14.758508 CS Dly: 6 (0~37)
2494 06:49:14.758572 ==
2495 06:49:14.761631 Dram Type= 6, Freq= 0, CH_0, rank 1
2496 06:49:14.768395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 06:49:14.768501 ==
2498 06:49:14.771613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 06:49:14.778391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2500 06:49:14.787788 [CA 0] Center 39 (8~70) winsize 63
2501 06:49:14.791018 [CA 1] Center 38 (8~69) winsize 62
2502 06:49:14.794145 [CA 2] Center 35 (5~66) winsize 62
2503 06:49:14.797789 [CA 3] Center 35 (5~66) winsize 62
2504 06:49:14.800968 [CA 4] Center 34 (4~65) winsize 62
2505 06:49:14.804452 [CA 5] Center 33 (3~64) winsize 62
2506 06:49:14.804526
2507 06:49:14.807710 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2508 06:49:14.807806
2509 06:49:14.810882 [CATrainingPosCal] consider 2 rank data
2510 06:49:14.814243 u2DelayCellTimex100 = 270/100 ps
2511 06:49:14.817629 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2512 06:49:14.821087 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2513 06:49:14.827642 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 06:49:14.831179 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2515 06:49:14.834237 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2516 06:49:14.837551 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2517 06:49:14.837628
2518 06:49:14.840728 CA PerBit enable=1, Macro0, CA PI delay=33
2519 06:49:14.840798
2520 06:49:14.844269 [CBTSetCACLKResult] CA Dly = 33
2521 06:49:14.844365 CS Dly: 7 (0~39)
2522 06:49:14.844454
2523 06:49:14.847692 ----->DramcWriteLeveling(PI) begin...
2524 06:49:14.850926 ==
2525 06:49:14.854232 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 06:49:14.857433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 06:49:14.857506 ==
2528 06:49:14.860901 Write leveling (Byte 0): 35 => 35
2529 06:49:14.864027 Write leveling (Byte 1): 32 => 32
2530 06:49:14.867868 DramcWriteLeveling(PI) end<-----
2531 06:49:14.867953
2532 06:49:14.868027 ==
2533 06:49:14.870867 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 06:49:14.874198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 06:49:14.874276 ==
2536 06:49:14.877519 [Gating] SW mode calibration
2537 06:49:14.884293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2538 06:49:14.887663 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2539 06:49:14.894302 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2540 06:49:14.897496 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2541 06:49:14.900864 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 06:49:14.907537 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 06:49:14.910900 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 06:49:14.914414 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 06:49:14.920738 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
2546 06:49:14.924450 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
2547 06:49:14.927527 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2548 06:49:14.934407 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 06:49:14.937810 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 06:49:14.940957 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 06:49:14.947926 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 06:49:14.951176 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 06:49:14.954391 1 0 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
2554 06:49:14.957810 1 0 28 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
2555 06:49:14.964381 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2556 06:49:14.967800 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 06:49:14.971264 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 06:49:14.978175 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 06:49:14.981394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 06:49:14.984876 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 06:49:14.991147 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2562 06:49:14.994578 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2563 06:49:14.997803 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 06:49:15.004671 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 06:49:15.008076 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 06:49:15.011352 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 06:49:15.017817 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 06:49:15.021508 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 06:49:15.024534 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 06:49:15.031129 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 06:49:15.034903 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 06:49:15.037810 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 06:49:15.041078 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 06:49:15.048134 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 06:49:15.051177 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 06:49:15.054657 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 06:49:15.061558 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 06:49:15.064702 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2579 06:49:15.068359 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2580 06:49:15.071703 Total UI for P1: 0, mck2ui 16
2581 06:49:15.075096 best dqsien dly found for B0: ( 1, 3, 28)
2582 06:49:15.081388 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 06:49:15.081487 Total UI for P1: 0, mck2ui 16
2584 06:49:15.084772 best dqsien dly found for B1: ( 1, 4, 0)
2585 06:49:15.091687 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2586 06:49:15.095039 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2587 06:49:15.095122
2588 06:49:15.098313 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2589 06:49:15.101625 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2590 06:49:15.104936 [Gating] SW calibration Done
2591 06:49:15.105034 ==
2592 06:49:15.108603 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 06:49:15.111551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 06:49:15.111634 ==
2595 06:49:15.111700 RX Vref Scan: 0
2596 06:49:15.115042
2597 06:49:15.115149 RX Vref 0 -> 0, step: 1
2598 06:49:15.115217
2599 06:49:15.118281 RX Delay -40 -> 252, step: 8
2600 06:49:15.121826 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2601 06:49:15.124914 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2602 06:49:15.132220 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2603 06:49:15.135437 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2604 06:49:15.138445 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2605 06:49:15.142069 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2606 06:49:15.145335 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2607 06:49:15.148820 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2608 06:49:15.155325 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2609 06:49:15.158517 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2610 06:49:15.162151 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2611 06:49:15.165418 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2612 06:49:15.168647 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2613 06:49:15.175307 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2614 06:49:15.178529 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2615 06:49:15.181880 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2616 06:49:15.181971 ==
2617 06:49:15.185451 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 06:49:15.188630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 06:49:15.188713 ==
2620 06:49:15.192242 DQS Delay:
2621 06:49:15.192326 DQS0 = 0, DQS1 = 0
2622 06:49:15.195779 DQM Delay:
2623 06:49:15.195888 DQM0 = 122, DQM1 = 110
2624 06:49:15.195983 DQ Delay:
2625 06:49:15.201897 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2626 06:49:15.205449 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2627 06:49:15.208721 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2628 06:49:15.212020 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2629 06:49:15.212099
2630 06:49:15.212162
2631 06:49:15.212222 ==
2632 06:49:15.215649 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 06:49:15.218900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 06:49:15.218973 ==
2635 06:49:15.219037
2636 06:49:15.219096
2637 06:49:15.222237 TX Vref Scan disable
2638 06:49:15.225411 == TX Byte 0 ==
2639 06:49:15.228652 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2640 06:49:15.232283 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2641 06:49:15.235264 == TX Byte 1 ==
2642 06:49:15.238748 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2643 06:49:15.242296 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2644 06:49:15.242374 ==
2645 06:49:15.245518 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 06:49:15.248953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 06:49:15.249031 ==
2648 06:49:15.261954 TX Vref=22, minBit 7, minWin=22, winSum=398
2649 06:49:15.265461 TX Vref=24, minBit 7, minWin=23, winSum=406
2650 06:49:15.268756 TX Vref=26, minBit 0, minWin=24, winSum=413
2651 06:49:15.272005 TX Vref=28, minBit 0, minWin=25, winSum=418
2652 06:49:15.275232 TX Vref=30, minBit 7, minWin=24, winSum=415
2653 06:49:15.278894 TX Vref=32, minBit 3, minWin=25, winSum=416
2654 06:49:15.285221 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
2655 06:49:15.285299
2656 06:49:15.288561 Final TX Range 1 Vref 28
2657 06:49:15.288636
2658 06:49:15.288702 ==
2659 06:49:15.291940 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 06:49:15.295389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 06:49:15.295466 ==
2662 06:49:15.295535
2663 06:49:15.299166
2664 06:49:15.299269 TX Vref Scan disable
2665 06:49:15.302007 == TX Byte 0 ==
2666 06:49:15.305281 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2667 06:49:15.308756 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2668 06:49:15.312174 == TX Byte 1 ==
2669 06:49:15.315282 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2670 06:49:15.318442 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2671 06:49:15.318521
2672 06:49:15.321981 [DATLAT]
2673 06:49:15.322070 Freq=1200, CH0 RK0
2674 06:49:15.322134
2675 06:49:15.325190 DATLAT Default: 0xd
2676 06:49:15.325264 0, 0xFFFF, sum = 0
2677 06:49:15.328611 1, 0xFFFF, sum = 0
2678 06:49:15.328691 2, 0xFFFF, sum = 0
2679 06:49:15.332230 3, 0xFFFF, sum = 0
2680 06:49:15.332309 4, 0xFFFF, sum = 0
2681 06:49:15.335212 5, 0xFFFF, sum = 0
2682 06:49:15.335292 6, 0xFFFF, sum = 0
2683 06:49:15.338727 7, 0xFFFF, sum = 0
2684 06:49:15.338836 8, 0xFFFF, sum = 0
2685 06:49:15.342141 9, 0xFFFF, sum = 0
2686 06:49:15.345250 10, 0xFFFF, sum = 0
2687 06:49:15.345358 11, 0xFFFF, sum = 0
2688 06:49:15.348837 12, 0x0, sum = 1
2689 06:49:15.348944 13, 0x0, sum = 2
2690 06:49:15.349046 14, 0x0, sum = 3
2691 06:49:15.351848 15, 0x0, sum = 4
2692 06:49:15.351948 best_step = 13
2693 06:49:15.352048
2694 06:49:15.352148 ==
2695 06:49:15.355335 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 06:49:15.362464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 06:49:15.362544 ==
2698 06:49:15.362613 RX Vref Scan: 1
2699 06:49:15.362675
2700 06:49:15.365355 Set Vref Range= 32 -> 127
2701 06:49:15.365450
2702 06:49:15.368603 RX Vref 32 -> 127, step: 1
2703 06:49:15.368697
2704 06:49:15.372012 RX Delay -13 -> 252, step: 4
2705 06:49:15.372099
2706 06:49:15.375651 Set Vref, RX VrefLevel [Byte0]: 32
2707 06:49:15.375727 [Byte1]: 32
2708 06:49:15.380310
2709 06:49:15.380386 Set Vref, RX VrefLevel [Byte0]: 33
2710 06:49:15.383679 [Byte1]: 33
2711 06:49:15.388348
2712 06:49:15.388426 Set Vref, RX VrefLevel [Byte0]: 34
2713 06:49:15.391211 [Byte1]: 34
2714 06:49:15.396515
2715 06:49:15.396595 Set Vref, RX VrefLevel [Byte0]: 35
2716 06:49:15.399148 [Byte1]: 35
2717 06:49:15.403851
2718 06:49:15.403933 Set Vref, RX VrefLevel [Byte0]: 36
2719 06:49:15.407238 [Byte1]: 36
2720 06:49:15.411702
2721 06:49:15.411783 Set Vref, RX VrefLevel [Byte0]: 37
2722 06:49:15.415101 [Byte1]: 37
2723 06:49:15.419635
2724 06:49:15.419717 Set Vref, RX VrefLevel [Byte0]: 38
2725 06:49:15.423073 [Byte1]: 38
2726 06:49:15.427327
2727 06:49:15.427409 Set Vref, RX VrefLevel [Byte0]: 39
2728 06:49:15.430781 [Byte1]: 39
2729 06:49:15.435593
2730 06:49:15.435670 Set Vref, RX VrefLevel [Byte0]: 40
2731 06:49:15.438829 [Byte1]: 40
2732 06:49:15.443262
2733 06:49:15.443336 Set Vref, RX VrefLevel [Byte0]: 41
2734 06:49:15.447001 [Byte1]: 41
2735 06:49:15.451322
2736 06:49:15.451397 Set Vref, RX VrefLevel [Byte0]: 42
2737 06:49:15.454844 [Byte1]: 42
2738 06:49:15.459346
2739 06:49:15.459429 Set Vref, RX VrefLevel [Byte0]: 43
2740 06:49:15.462419 [Byte1]: 43
2741 06:49:15.466985
2742 06:49:15.467059 Set Vref, RX VrefLevel [Byte0]: 44
2743 06:49:15.470446 [Byte1]: 44
2744 06:49:15.474900
2745 06:49:15.474982 Set Vref, RX VrefLevel [Byte0]: 45
2746 06:49:15.478284 [Byte1]: 45
2747 06:49:15.482677
2748 06:49:15.482763 Set Vref, RX VrefLevel [Byte0]: 46
2749 06:49:15.486446 [Byte1]: 46
2750 06:49:15.490593
2751 06:49:15.490692 Set Vref, RX VrefLevel [Byte0]: 47
2752 06:49:15.493924 [Byte1]: 47
2753 06:49:15.498504
2754 06:49:15.498587 Set Vref, RX VrefLevel [Byte0]: 48
2755 06:49:15.501676 [Byte1]: 48
2756 06:49:15.506440
2757 06:49:15.506522 Set Vref, RX VrefLevel [Byte0]: 49
2758 06:49:15.509895 [Byte1]: 49
2759 06:49:15.514662
2760 06:49:15.514742 Set Vref, RX VrefLevel [Byte0]: 50
2761 06:49:15.517671 [Byte1]: 50
2762 06:49:15.522579
2763 06:49:15.522656 Set Vref, RX VrefLevel [Byte0]: 51
2764 06:49:15.525905 [Byte1]: 51
2765 06:49:15.530282
2766 06:49:15.530358 Set Vref, RX VrefLevel [Byte0]: 52
2767 06:49:15.533492 [Byte1]: 52
2768 06:49:15.537834
2769 06:49:15.537948 Set Vref, RX VrefLevel [Byte0]: 53
2770 06:49:15.541512 [Byte1]: 53
2771 06:49:15.546054
2772 06:49:15.546131 Set Vref, RX VrefLevel [Byte0]: 54
2773 06:49:15.549349 [Byte1]: 54
2774 06:49:15.553587
2775 06:49:15.553692 Set Vref, RX VrefLevel [Byte0]: 55
2776 06:49:15.556839 [Byte1]: 55
2777 06:49:15.561933
2778 06:49:15.562022 Set Vref, RX VrefLevel [Byte0]: 56
2779 06:49:15.565105 [Byte1]: 56
2780 06:49:15.569363
2781 06:49:15.569439 Set Vref, RX VrefLevel [Byte0]: 57
2782 06:49:15.572893 [Byte1]: 57
2783 06:49:15.577703
2784 06:49:15.577779 Set Vref, RX VrefLevel [Byte0]: 58
2785 06:49:15.580919 [Byte1]: 58
2786 06:49:15.585363
2787 06:49:15.585436 Set Vref, RX VrefLevel [Byte0]: 59
2788 06:49:15.588660 [Byte1]: 59
2789 06:49:15.593465
2790 06:49:15.593572 Set Vref, RX VrefLevel [Byte0]: 60
2791 06:49:15.596927 [Byte1]: 60
2792 06:49:15.600996
2793 06:49:15.601070 Set Vref, RX VrefLevel [Byte0]: 61
2794 06:49:15.604527 [Byte1]: 61
2795 06:49:15.609133
2796 06:49:15.609216 Set Vref, RX VrefLevel [Byte0]: 62
2797 06:49:15.612339 [Byte1]: 62
2798 06:49:15.617018
2799 06:49:15.617101 Set Vref, RX VrefLevel [Byte0]: 63
2800 06:49:15.620226 [Byte1]: 63
2801 06:49:15.624899
2802 06:49:15.624989 Set Vref, RX VrefLevel [Byte0]: 64
2803 06:49:15.627964 [Byte1]: 64
2804 06:49:15.632673
2805 06:49:15.632757 Set Vref, RX VrefLevel [Byte0]: 65
2806 06:49:15.635813 [Byte1]: 65
2807 06:49:15.640869
2808 06:49:15.640970 Set Vref, RX VrefLevel [Byte0]: 66
2809 06:49:15.644104 [Byte1]: 66
2810 06:49:15.648885
2811 06:49:15.648968 Set Vref, RX VrefLevel [Byte0]: 67
2812 06:49:15.652046 [Byte1]: 67
2813 06:49:15.656241
2814 06:49:15.656325 Set Vref, RX VrefLevel [Byte0]: 68
2815 06:49:15.659844 [Byte1]: 68
2816 06:49:15.664140
2817 06:49:15.664223 Final RX Vref Byte 0 = 56 to rank0
2818 06:49:15.667859 Final RX Vref Byte 1 = 49 to rank0
2819 06:49:15.670963 Final RX Vref Byte 0 = 56 to rank1
2820 06:49:15.674368 Final RX Vref Byte 1 = 49 to rank1==
2821 06:49:15.677844 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 06:49:15.681078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 06:49:15.684274 ==
2824 06:49:15.684347 DQS Delay:
2825 06:49:15.684413 DQS0 = 0, DQS1 = 0
2826 06:49:15.687643 DQM Delay:
2827 06:49:15.687712 DQM0 = 122, DQM1 = 109
2828 06:49:15.691139 DQ Delay:
2829 06:49:15.694393 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2830 06:49:15.697838 DQ4 =124, DQ5 =116, DQ6 =130, DQ7 =128
2831 06:49:15.700900 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =108
2832 06:49:15.704354 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2833 06:49:15.704430
2834 06:49:15.704497
2835 06:49:15.711103 [DQSOSCAuto] RK0, (LSB)MR18= 0x804, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2836 06:49:15.714549 CH0 RK0: MR19=404, MR18=804
2837 06:49:15.721301 CH0_RK0: MR19=0x404, MR18=0x804, DQSOSC=406, MR23=63, INC=39, DEC=26
2838 06:49:15.721384
2839 06:49:15.724466 ----->DramcWriteLeveling(PI) begin...
2840 06:49:15.724554 ==
2841 06:49:15.727960 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 06:49:15.731017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 06:49:15.731093 ==
2844 06:49:15.734537 Write leveling (Byte 0): 35 => 35
2845 06:49:15.737611 Write leveling (Byte 1): 30 => 30
2846 06:49:15.740987 DramcWriteLeveling(PI) end<-----
2847 06:49:15.741061
2848 06:49:15.741129 ==
2849 06:49:15.744384 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 06:49:15.747820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 06:49:15.751157 ==
2852 06:49:15.751231 [Gating] SW mode calibration
2853 06:49:15.757875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 06:49:15.764549 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 06:49:15.768275 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2856 06:49:15.774532 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 06:49:15.778059 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 06:49:15.781280 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 06:49:15.787820 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 06:49:15.791156 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 06:49:15.795118 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2862 06:49:15.798030 0 15 28 | B1->B0 | 3030 2b2b | 0 0 | (0 1) (0 0)
2863 06:49:15.804896 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 06:49:15.808332 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 06:49:15.811383 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 06:49:15.817970 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 06:49:15.821281 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 06:49:15.824927 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 06:49:15.831161 1 0 24 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
2870 06:49:15.834494 1 0 28 | B1->B0 | 3a3a 4444 | 1 0 | (0 0) (0 0)
2871 06:49:15.838074 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 06:49:15.844683 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 06:49:15.847889 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 06:49:15.851143 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 06:49:15.857859 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 06:49:15.861267 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 06:49:15.864498 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 06:49:15.871173 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2879 06:49:15.874908 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2880 06:49:15.877890 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 06:49:15.884670 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 06:49:15.888225 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 06:49:15.891189 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 06:49:15.897849 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 06:49:15.901459 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 06:49:15.904789 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 06:49:15.907822 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 06:49:15.914583 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 06:49:15.918166 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 06:49:15.921378 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 06:49:15.927975 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 06:49:15.931473 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 06:49:15.934546 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 06:49:15.941416 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2895 06:49:15.944910 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 06:49:15.948216 Total UI for P1: 0, mck2ui 16
2897 06:49:15.951489 best dqsien dly found for B0: ( 1, 3, 28)
2898 06:49:15.955123 Total UI for P1: 0, mck2ui 16
2899 06:49:15.958428 best dqsien dly found for B1: ( 1, 3, 28)
2900 06:49:15.961529 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2901 06:49:15.964837 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2902 06:49:15.964923
2903 06:49:15.968183 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2904 06:49:15.971383 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2905 06:49:15.974922 [Gating] SW calibration Done
2906 06:49:15.974993 ==
2907 06:49:15.978626 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 06:49:15.981856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 06:49:15.981987 ==
2910 06:49:15.984845 RX Vref Scan: 0
2911 06:49:15.984913
2912 06:49:15.988196 RX Vref 0 -> 0, step: 1
2913 06:49:15.988265
2914 06:49:15.988326 RX Delay -40 -> 252, step: 8
2915 06:49:15.994980 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2916 06:49:15.998195 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2917 06:49:16.001757 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2918 06:49:16.005319 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2919 06:49:16.008471 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2920 06:49:16.015078 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2921 06:49:16.018218 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2922 06:49:16.021893 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2923 06:49:16.024883 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2924 06:49:16.028488 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2925 06:49:16.031689 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2926 06:49:16.038396 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2927 06:49:16.041670 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2928 06:49:16.045461 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2929 06:49:16.048327 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2930 06:49:16.051878 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2931 06:49:16.055488 ==
2932 06:49:16.058453 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 06:49:16.061927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 06:49:16.062008 ==
2935 06:49:16.062073 DQS Delay:
2936 06:49:16.065214 DQS0 = 0, DQS1 = 0
2937 06:49:16.065285 DQM Delay:
2938 06:49:16.068579 DQM0 = 120, DQM1 = 108
2939 06:49:16.068659 DQ Delay:
2940 06:49:16.072150 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2941 06:49:16.075311 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2942 06:49:16.078460 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2943 06:49:16.081874 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2944 06:49:16.082017
2945 06:49:16.082082
2946 06:49:16.082147 ==
2947 06:49:16.085503 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 06:49:16.092052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 06:49:16.092127 ==
2950 06:49:16.092197
2951 06:49:16.092263
2952 06:49:16.092320 TX Vref Scan disable
2953 06:49:16.095239 == TX Byte 0 ==
2954 06:49:16.098689 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2955 06:49:16.105023 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2956 06:49:16.105104 == TX Byte 1 ==
2957 06:49:16.108735 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2958 06:49:16.115366 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2959 06:49:16.115439 ==
2960 06:49:16.118786 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 06:49:16.121881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 06:49:16.122015 ==
2963 06:49:16.133567 TX Vref=22, minBit 4, minWin=24, winSum=412
2964 06:49:16.137187 TX Vref=24, minBit 1, minWin=24, winSum=417
2965 06:49:16.140318 TX Vref=26, minBit 1, minWin=25, winSum=419
2966 06:49:16.143760 TX Vref=28, minBit 1, minWin=24, winSum=421
2967 06:49:16.146976 TX Vref=30, minBit 3, minWin=25, winSum=422
2968 06:49:16.150227 TX Vref=32, minBit 3, minWin=25, winSum=422
2969 06:49:16.156891 [TxChooseVref] Worse bit 3, Min win 25, Win sum 422, Final Vref 30
2970 06:49:16.156966
2971 06:49:16.160111 Final TX Range 1 Vref 30
2972 06:49:16.160181
2973 06:49:16.160248 ==
2974 06:49:16.163556 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 06:49:16.167087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 06:49:16.167203 ==
2977 06:49:16.167264
2978 06:49:16.170219
2979 06:49:16.170309 TX Vref Scan disable
2980 06:49:16.173786 == TX Byte 0 ==
2981 06:49:16.177034 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2982 06:49:16.180366 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2983 06:49:16.183479 == TX Byte 1 ==
2984 06:49:16.187129 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2985 06:49:16.190522 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2986 06:49:16.190600
2987 06:49:16.193547 [DATLAT]
2988 06:49:16.193624 Freq=1200, CH0 RK1
2989 06:49:16.193686
2990 06:49:16.196971 DATLAT Default: 0xd
2991 06:49:16.197039 0, 0xFFFF, sum = 0
2992 06:49:16.200216 1, 0xFFFF, sum = 0
2993 06:49:16.200287 2, 0xFFFF, sum = 0
2994 06:49:16.203846 3, 0xFFFF, sum = 0
2995 06:49:16.203924 4, 0xFFFF, sum = 0
2996 06:49:16.206966 5, 0xFFFF, sum = 0
2997 06:49:16.207045 6, 0xFFFF, sum = 0
2998 06:49:16.210539 7, 0xFFFF, sum = 0
2999 06:49:16.210628 8, 0xFFFF, sum = 0
3000 06:49:16.214159 9, 0xFFFF, sum = 0
3001 06:49:16.214236 10, 0xFFFF, sum = 0
3002 06:49:16.217482 11, 0xFFFF, sum = 0
3003 06:49:16.217556 12, 0x0, sum = 1
3004 06:49:16.220533 13, 0x0, sum = 2
3005 06:49:16.220608 14, 0x0, sum = 3
3006 06:49:16.223836 15, 0x0, sum = 4
3007 06:49:16.223914 best_step = 13
3008 06:49:16.223977
3009 06:49:16.224036 ==
3010 06:49:16.227208 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 06:49:16.233843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 06:49:16.233924 ==
3013 06:49:16.234033 RX Vref Scan: 0
3014 06:49:16.234095
3015 06:49:16.237327 RX Vref 0 -> 0, step: 1
3016 06:49:16.237398
3017 06:49:16.240444 RX Delay -21 -> 252, step: 4
3018 06:49:16.244038 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3019 06:49:16.247263 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3020 06:49:16.253862 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3021 06:49:16.257411 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3022 06:49:16.260626 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3023 06:49:16.264146 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3024 06:49:16.267712 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3025 06:49:16.271233 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3026 06:49:16.277477 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3027 06:49:16.280594 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3028 06:49:16.284189 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3029 06:49:16.287839 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3030 06:49:16.290931 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3031 06:49:16.297449 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3032 06:49:16.300840 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3033 06:49:16.304554 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3034 06:49:16.304637 ==
3035 06:49:16.307705 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 06:49:16.310910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 06:49:16.310984 ==
3038 06:49:16.314235 DQS Delay:
3039 06:49:16.314313 DQS0 = 0, DQS1 = 0
3040 06:49:16.317459 DQM Delay:
3041 06:49:16.317528 DQM0 = 119, DQM1 = 107
3042 06:49:16.320811 DQ Delay:
3043 06:49:16.324269 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3044 06:49:16.327615 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3045 06:49:16.330778 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3046 06:49:16.334599 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3047 06:49:16.334669
3048 06:49:16.334737
3049 06:49:16.341262 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3050 06:49:16.344351 CH0 RK1: MR19=403, MR18=CF3
3051 06:49:16.351056 CH0_RK1: MR19=0x403, MR18=0xCF3, DQSOSC=405, MR23=63, INC=39, DEC=26
3052 06:49:16.354827 [RxdqsGatingPostProcess] freq 1200
3053 06:49:16.357614 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3054 06:49:16.361013 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 06:49:16.364527 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 06:49:16.367546 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 06:49:16.370819 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 06:49:16.374327 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 06:49:16.377599 best DQS1 dly(2T, 0.5T) = (0, 11)
3060 06:49:16.381252 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 06:49:16.384295 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3062 06:49:16.388022 Pre-setting of DQS Precalculation
3063 06:49:16.391237 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3064 06:49:16.391320 ==
3065 06:49:16.394275 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 06:49:16.400886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 06:49:16.400969 ==
3068 06:49:16.404544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3069 06:49:16.411013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=23, u1VrefScanEnd=33
3070 06:49:16.419345 [CA 0] Center 37 (7~68) winsize 62
3071 06:49:16.422603 [CA 1] Center 37 (7~68) winsize 62
3072 06:49:16.426356 [CA 2] Center 35 (5~65) winsize 61
3073 06:49:16.429173 [CA 3] Center 34 (4~65) winsize 62
3074 06:49:16.432545 [CA 4] Center 34 (4~64) winsize 61
3075 06:49:16.436159 [CA 5] Center 33 (3~64) winsize 62
3076 06:49:16.436241
3077 06:49:16.439304 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3078 06:49:16.439387
3079 06:49:16.442676 [CATrainingPosCal] consider 1 rank data
3080 06:49:16.446272 u2DelayCellTimex100 = 270/100 ps
3081 06:49:16.449447 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3082 06:49:16.452607 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3083 06:49:16.459686 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3084 06:49:16.462804 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3085 06:49:16.466172 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3086 06:49:16.469367 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3087 06:49:16.469450
3088 06:49:16.472957 CA PerBit enable=1, Macro0, CA PI delay=33
3089 06:49:16.473039
3090 06:49:16.476255 [CBTSetCACLKResult] CA Dly = 33
3091 06:49:16.476337 CS Dly: 5 (0~36)
3092 06:49:16.476402 ==
3093 06:49:16.479285 Dram Type= 6, Freq= 0, CH_1, rank 1
3094 06:49:16.486697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 06:49:16.486779 ==
3096 06:49:16.489423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 06:49:16.496148 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3098 06:49:16.505188 [CA 0] Center 38 (8~68) winsize 61
3099 06:49:16.508607 [CA 1] Center 38 (7~69) winsize 63
3100 06:49:16.511885 [CA 2] Center 35 (5~66) winsize 62
3101 06:49:16.515120 [CA 3] Center 34 (4~65) winsize 62
3102 06:49:16.518285 [CA 4] Center 35 (5~65) winsize 61
3103 06:49:16.521488 [CA 5] Center 34 (4~64) winsize 61
3104 06:49:16.521571
3105 06:49:16.525070 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3106 06:49:16.525152
3107 06:49:16.528448 [CATrainingPosCal] consider 2 rank data
3108 06:49:16.531773 u2DelayCellTimex100 = 270/100 ps
3109 06:49:16.534930 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3110 06:49:16.538145 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3111 06:49:16.544987 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3112 06:49:16.548132 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3113 06:49:16.551555 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3114 06:49:16.554761 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3115 06:49:16.554843
3116 06:49:16.558191 CA PerBit enable=1, Macro0, CA PI delay=34
3117 06:49:16.558274
3118 06:49:16.561636 [CBTSetCACLKResult] CA Dly = 34
3119 06:49:16.561718 CS Dly: 6 (0~39)
3120 06:49:16.561783
3121 06:49:16.565206 ----->DramcWriteLeveling(PI) begin...
3122 06:49:16.568456 ==
3123 06:49:16.568539 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 06:49:16.575065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 06:49:16.575147 ==
3126 06:49:16.578510 Write leveling (Byte 0): 24 => 24
3127 06:49:16.581816 Write leveling (Byte 1): 26 => 26
3128 06:49:16.585017 DramcWriteLeveling(PI) end<-----
3129 06:49:16.585099
3130 06:49:16.585164 ==
3131 06:49:16.588291 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 06:49:16.591670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 06:49:16.591753 ==
3134 06:49:16.595072 [Gating] SW mode calibration
3135 06:49:16.601555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3136 06:49:16.605031 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3137 06:49:16.611740 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 06:49:16.615224 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 06:49:16.618344 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 06:49:16.625136 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 06:49:16.628280 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 06:49:16.632064 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3143 06:49:16.638487 0 15 24 | B1->B0 | 3030 2929 | 1 0 | (1 0) (1 0)
3144 06:49:16.641632 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 06:49:16.645011 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 06:49:16.651608 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 06:49:16.655068 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 06:49:16.658359 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 06:49:16.665067 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 06:49:16.668409 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3151 06:49:16.672018 1 0 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3152 06:49:16.678493 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 06:49:16.681644 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 06:49:16.684924 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 06:49:16.688416 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 06:49:16.695014 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 06:49:16.698679 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 06:49:16.701839 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3159 06:49:16.708289 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3160 06:49:16.711806 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3161 06:49:16.715137 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 06:49:16.721731 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 06:49:16.725351 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 06:49:16.728394 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 06:49:16.735234 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 06:49:16.738350 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 06:49:16.741740 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 06:49:16.748524 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 06:49:16.751724 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 06:49:16.755397 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 06:49:16.761866 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 06:49:16.765444 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 06:49:16.768803 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 06:49:16.772140 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3175 06:49:16.778874 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3176 06:49:16.781894 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 06:49:16.785540 Total UI for P1: 0, mck2ui 16
3178 06:49:16.788803 best dqsien dly found for B0: ( 1, 3, 22)
3179 06:49:16.792038 Total UI for P1: 0, mck2ui 16
3180 06:49:16.795384 best dqsien dly found for B1: ( 1, 3, 24)
3181 06:49:16.798783 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3182 06:49:16.801762 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3183 06:49:16.801866
3184 06:49:16.805319 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3185 06:49:16.808856 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3186 06:49:16.812357 [Gating] SW calibration Done
3187 06:49:16.812442 ==
3188 06:49:16.815082 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 06:49:16.818653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 06:49:16.822174 ==
3191 06:49:16.822285 RX Vref Scan: 0
3192 06:49:16.822385
3193 06:49:16.825660 RX Vref 0 -> 0, step: 1
3194 06:49:16.825744
3195 06:49:16.828974 RX Delay -40 -> 252, step: 8
3196 06:49:16.832299 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3197 06:49:16.835743 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3198 06:49:16.838961 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3199 06:49:16.842123 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3200 06:49:16.849042 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3201 06:49:16.852088 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3202 06:49:16.855372 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3203 06:49:16.858623 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3204 06:49:16.862449 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3205 06:49:16.865351 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3206 06:49:16.872219 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3207 06:49:16.875471 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3208 06:49:16.878872 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3209 06:49:16.881841 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3210 06:49:16.888475 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3211 06:49:16.892277 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3212 06:49:16.892361 ==
3213 06:49:16.895267 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 06:49:16.898879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 06:49:16.898964 ==
3216 06:49:16.899030 DQS Delay:
3217 06:49:16.901771 DQS0 = 0, DQS1 = 0
3218 06:49:16.901855 DQM Delay:
3219 06:49:16.905208 DQM0 = 121, DQM1 = 112
3220 06:49:16.905322 DQ Delay:
3221 06:49:16.908525 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3222 06:49:16.912084 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =123
3223 06:49:16.915372 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3224 06:49:16.918500 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3225 06:49:16.918584
3226 06:49:16.922148
3227 06:49:16.922231 ==
3228 06:49:16.925258 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 06:49:16.928625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 06:49:16.928770 ==
3231 06:49:16.928870
3232 06:49:16.928960
3233 06:49:16.932005 TX Vref Scan disable
3234 06:49:16.932090 == TX Byte 0 ==
3235 06:49:16.935317 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3236 06:49:16.941855 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3237 06:49:16.941963 == TX Byte 1 ==
3238 06:49:16.945537 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3239 06:49:16.952294 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3240 06:49:16.952405 ==
3241 06:49:16.955612 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 06:49:16.958618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 06:49:16.958702 ==
3244 06:49:16.970677 TX Vref=22, minBit 10, minWin=24, winSum=405
3245 06:49:16.973702 TX Vref=24, minBit 11, minWin=24, winSum=410
3246 06:49:16.977058 TX Vref=26, minBit 1, minWin=25, winSum=416
3247 06:49:16.980748 TX Vref=28, minBit 9, minWin=25, winSum=417
3248 06:49:16.983740 TX Vref=30, minBit 10, minWin=25, winSum=420
3249 06:49:16.990951 TX Vref=32, minBit 1, minWin=26, winSum=422
3250 06:49:16.994390 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 32
3251 06:49:16.994474
3252 06:49:16.997385 Final TX Range 1 Vref 32
3253 06:49:16.997469
3254 06:49:16.997536 ==
3255 06:49:17.000713 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 06:49:17.003945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 06:49:17.004029 ==
3258 06:49:17.007417
3259 06:49:17.007499
3260 06:49:17.007566 TX Vref Scan disable
3261 06:49:17.010859 == TX Byte 0 ==
3262 06:49:17.014089 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3263 06:49:17.017501 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3264 06:49:17.020828 == TX Byte 1 ==
3265 06:49:17.023827 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3266 06:49:17.027327 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3267 06:49:17.030915
3268 06:49:17.030999 [DATLAT]
3269 06:49:17.031065 Freq=1200, CH1 RK0
3270 06:49:17.031127
3271 06:49:17.033817 DATLAT Default: 0xd
3272 06:49:17.033918 0, 0xFFFF, sum = 0
3273 06:49:17.037534 1, 0xFFFF, sum = 0
3274 06:49:17.037619 2, 0xFFFF, sum = 0
3275 06:49:17.040652 3, 0xFFFF, sum = 0
3276 06:49:17.040737 4, 0xFFFF, sum = 0
3277 06:49:17.044411 5, 0xFFFF, sum = 0
3278 06:49:17.044496 6, 0xFFFF, sum = 0
3279 06:49:17.047312 7, 0xFFFF, sum = 0
3280 06:49:17.050548 8, 0xFFFF, sum = 0
3281 06:49:17.050659 9, 0xFFFF, sum = 0
3282 06:49:17.054070 10, 0xFFFF, sum = 0
3283 06:49:17.054181 11, 0xFFFF, sum = 0
3284 06:49:17.057372 12, 0x0, sum = 1
3285 06:49:17.057457 13, 0x0, sum = 2
3286 06:49:17.060422 14, 0x0, sum = 3
3287 06:49:17.060508 15, 0x0, sum = 4
3288 06:49:17.060575 best_step = 13
3289 06:49:17.060637
3290 06:49:17.063998 ==
3291 06:49:17.067319 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 06:49:17.070972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 06:49:17.071057 ==
3294 06:49:17.071123 RX Vref Scan: 1
3295 06:49:17.071184
3296 06:49:17.073789 Set Vref Range= 32 -> 127
3297 06:49:17.073916
3298 06:49:17.077246 RX Vref 32 -> 127, step: 1
3299 06:49:17.077330
3300 06:49:17.080649 RX Delay -13 -> 252, step: 4
3301 06:49:17.080730
3302 06:49:17.084006 Set Vref, RX VrefLevel [Byte0]: 32
3303 06:49:17.087391 [Byte1]: 32
3304 06:49:17.087473
3305 06:49:17.090545 Set Vref, RX VrefLevel [Byte0]: 33
3306 06:49:17.093786 [Byte1]: 33
3307 06:49:17.093894
3308 06:49:17.097385 Set Vref, RX VrefLevel [Byte0]: 34
3309 06:49:17.100773 [Byte1]: 34
3310 06:49:17.104751
3311 06:49:17.104832 Set Vref, RX VrefLevel [Byte0]: 35
3312 06:49:17.107786 [Byte1]: 35
3313 06:49:17.112417
3314 06:49:17.112498 Set Vref, RX VrefLevel [Byte0]: 36
3315 06:49:17.116279 [Byte1]: 36
3316 06:49:17.120442
3317 06:49:17.120523 Set Vref, RX VrefLevel [Byte0]: 37
3318 06:49:17.124195 [Byte1]: 37
3319 06:49:17.128326
3320 06:49:17.128407 Set Vref, RX VrefLevel [Byte0]: 38
3321 06:49:17.131972 [Byte1]: 38
3322 06:49:17.136149
3323 06:49:17.136230 Set Vref, RX VrefLevel [Byte0]: 39
3324 06:49:17.139596 [Byte1]: 39
3325 06:49:17.144268
3326 06:49:17.144350 Set Vref, RX VrefLevel [Byte0]: 40
3327 06:49:17.147350 [Byte1]: 40
3328 06:49:17.152324
3329 06:49:17.152405 Set Vref, RX VrefLevel [Byte0]: 41
3330 06:49:17.155263 [Byte1]: 41
3331 06:49:17.159854
3332 06:49:17.159935 Set Vref, RX VrefLevel [Byte0]: 42
3333 06:49:17.163865 [Byte1]: 42
3334 06:49:17.167819
3335 06:49:17.167900 Set Vref, RX VrefLevel [Byte0]: 43
3336 06:49:17.171011 [Byte1]: 43
3337 06:49:17.175755
3338 06:49:17.175839 Set Vref, RX VrefLevel [Byte0]: 44
3339 06:49:17.179319 [Byte1]: 44
3340 06:49:17.183730
3341 06:49:17.183811 Set Vref, RX VrefLevel [Byte0]: 45
3342 06:49:17.186910 [Byte1]: 45
3343 06:49:17.191295
3344 06:49:17.191379 Set Vref, RX VrefLevel [Byte0]: 46
3345 06:49:17.194781 [Byte1]: 46
3346 06:49:17.199502
3347 06:49:17.199579 Set Vref, RX VrefLevel [Byte0]: 47
3348 06:49:17.202776 [Byte1]: 47
3349 06:49:17.207637
3350 06:49:17.207738 Set Vref, RX VrefLevel [Byte0]: 48
3351 06:49:17.210763 [Byte1]: 48
3352 06:49:17.215179
3353 06:49:17.215281 Set Vref, RX VrefLevel [Byte0]: 49
3354 06:49:17.218605 [Byte1]: 49
3355 06:49:17.223386
3356 06:49:17.223483 Set Vref, RX VrefLevel [Byte0]: 50
3357 06:49:17.226593 [Byte1]: 50
3358 06:49:17.230811
3359 06:49:17.230882 Set Vref, RX VrefLevel [Byte0]: 51
3360 06:49:17.234270 [Byte1]: 51
3361 06:49:17.238792
3362 06:49:17.238893 Set Vref, RX VrefLevel [Byte0]: 52
3363 06:49:17.242440 [Byte1]: 52
3364 06:49:17.246884
3365 06:49:17.246991 Set Vref, RX VrefLevel [Byte0]: 53
3366 06:49:17.250177 [Byte1]: 53
3367 06:49:17.254644
3368 06:49:17.254728 Set Vref, RX VrefLevel [Byte0]: 54
3369 06:49:17.257831 [Byte1]: 54
3370 06:49:17.262781
3371 06:49:17.262856 Set Vref, RX VrefLevel [Byte0]: 55
3372 06:49:17.265863 [Byte1]: 55
3373 06:49:17.270214
3374 06:49:17.270300 Set Vref, RX VrefLevel [Byte0]: 56
3375 06:49:17.273548 [Byte1]: 56
3376 06:49:17.278298
3377 06:49:17.278370 Set Vref, RX VrefLevel [Byte0]: 57
3378 06:49:17.281481 [Byte1]: 57
3379 06:49:17.286447
3380 06:49:17.286527 Set Vref, RX VrefLevel [Byte0]: 58
3381 06:49:17.289328 [Byte1]: 58
3382 06:49:17.293804
3383 06:49:17.293877 Set Vref, RX VrefLevel [Byte0]: 59
3384 06:49:17.297124 [Byte1]: 59
3385 06:49:17.302183
3386 06:49:17.302258 Set Vref, RX VrefLevel [Byte0]: 60
3387 06:49:17.305301 [Byte1]: 60
3388 06:49:17.309877
3389 06:49:17.309974 Set Vref, RX VrefLevel [Byte0]: 61
3390 06:49:17.312911 [Byte1]: 61
3391 06:49:17.317674
3392 06:49:17.317746 Set Vref, RX VrefLevel [Byte0]: 62
3393 06:49:17.320858 [Byte1]: 62
3394 06:49:17.325565
3395 06:49:17.325637 Set Vref, RX VrefLevel [Byte0]: 63
3396 06:49:17.329054 [Byte1]: 63
3397 06:49:17.333609
3398 06:49:17.333683 Set Vref, RX VrefLevel [Byte0]: 64
3399 06:49:17.336875 [Byte1]: 64
3400 06:49:17.341669
3401 06:49:17.341745 Set Vref, RX VrefLevel [Byte0]: 65
3402 06:49:17.344883 [Byte1]: 65
3403 06:49:17.349148
3404 06:49:17.349222 Set Vref, RX VrefLevel [Byte0]: 66
3405 06:49:17.352544 [Byte1]: 66
3406 06:49:17.357184
3407 06:49:17.357288 Set Vref, RX VrefLevel [Byte0]: 67
3408 06:49:17.360820 [Byte1]: 67
3409 06:49:17.365128
3410 06:49:17.365205 Final RX Vref Byte 0 = 52 to rank0
3411 06:49:17.368312 Final RX Vref Byte 1 = 57 to rank0
3412 06:49:17.371662 Final RX Vref Byte 0 = 52 to rank1
3413 06:49:17.375075 Final RX Vref Byte 1 = 57 to rank1==
3414 06:49:17.378327 Dram Type= 6, Freq= 0, CH_1, rank 0
3415 06:49:17.385136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3416 06:49:17.385237 ==
3417 06:49:17.385303 DQS Delay:
3418 06:49:17.385362 DQS0 = 0, DQS1 = 0
3419 06:49:17.388340 DQM Delay:
3420 06:49:17.388408 DQM0 = 119, DQM1 = 113
3421 06:49:17.391944 DQ Delay:
3422 06:49:17.394870 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3423 06:49:17.398480 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =116
3424 06:49:17.401834 DQ8 =102, DQ9 =100, DQ10 =116, DQ11 =106
3425 06:49:17.405140 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =120
3426 06:49:17.405249
3427 06:49:17.405337
3428 06:49:17.411738 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3429 06:49:17.415153 CH1 RK0: MR19=404, MR18=114
3430 06:49:17.421899 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3431 06:49:17.422020
3432 06:49:17.425078 ----->DramcWriteLeveling(PI) begin...
3433 06:49:17.425188 ==
3434 06:49:17.428427 Dram Type= 6, Freq= 0, CH_1, rank 1
3435 06:49:17.431798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3436 06:49:17.431874 ==
3437 06:49:17.435024 Write leveling (Byte 0): 25 => 25
3438 06:49:17.438713 Write leveling (Byte 1): 29 => 29
3439 06:49:17.441910 DramcWriteLeveling(PI) end<-----
3440 06:49:17.442002
3441 06:49:17.442070 ==
3442 06:49:17.445252 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 06:49:17.448375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3444 06:49:17.451925 ==
3445 06:49:17.452001 [Gating] SW mode calibration
3446 06:49:17.458670 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3447 06:49:17.465353 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3448 06:49:17.468497 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 06:49:17.475616 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 06:49:17.478859 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 06:49:17.482447 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 06:49:17.488519 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 06:49:17.492505 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3454 06:49:17.495736 0 15 24 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 0)
3455 06:49:17.502078 0 15 28 | B1->B0 | 2323 2a2a | 0 1 | (1 0) (1 0)
3456 06:49:17.505645 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 06:49:17.508701 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 06:49:17.512314 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 06:49:17.519047 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 06:49:17.522183 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 06:49:17.525411 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 06:49:17.532143 1 0 24 | B1->B0 | 3838 2828 | 0 0 | (0 0) (0 0)
3463 06:49:17.535517 1 0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
3464 06:49:17.539090 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 06:49:17.545472 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 06:49:17.548567 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 06:49:17.552315 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 06:49:17.559104 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 06:49:17.562312 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 06:49:17.565679 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3471 06:49:17.572385 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3472 06:49:17.575406 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 06:49:17.578525 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 06:49:17.585234 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 06:49:17.588514 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 06:49:17.591972 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 06:49:17.598532 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 06:49:17.601874 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 06:49:17.605037 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 06:49:17.611838 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 06:49:17.615152 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 06:49:17.618876 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 06:49:17.621617 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 06:49:17.629092 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 06:49:17.632033 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 06:49:17.635123 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3487 06:49:17.641792 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 06:49:17.645273 Total UI for P1: 0, mck2ui 16
3489 06:49:17.648272 best dqsien dly found for B0: ( 1, 3, 24)
3490 06:49:17.651748 Total UI for P1: 0, mck2ui 16
3491 06:49:17.655440 best dqsien dly found for B1: ( 1, 3, 24)
3492 06:49:17.658588 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3493 06:49:17.662126 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3494 06:49:17.662198
3495 06:49:17.665142 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3496 06:49:17.668279 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3497 06:49:17.671585 [Gating] SW calibration Done
3498 06:49:17.671656 ==
3499 06:49:17.675311 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 06:49:17.678650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 06:49:17.678728 ==
3502 06:49:17.681824 RX Vref Scan: 0
3503 06:49:17.681900
3504 06:49:17.681975 RX Vref 0 -> 0, step: 1
3505 06:49:17.682039
3506 06:49:17.685187 RX Delay -40 -> 252, step: 8
3507 06:49:17.691895 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3508 06:49:17.695511 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3509 06:49:17.698487 iDelay=200, Bit 2, Center 103 (40 ~ 167) 128
3510 06:49:17.701603 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3511 06:49:17.705022 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3512 06:49:17.708475 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3513 06:49:17.714861 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3514 06:49:17.718272 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3515 06:49:17.721834 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3516 06:49:17.725046 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3517 06:49:17.728522 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3518 06:49:17.735150 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3519 06:49:17.738584 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3520 06:49:17.741404 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3521 06:49:17.744976 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3522 06:49:17.751725 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3523 06:49:17.751798 ==
3524 06:49:17.754870 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 06:49:17.757963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 06:49:17.758032 ==
3527 06:49:17.758094 DQS Delay:
3528 06:49:17.761504 DQS0 = 0, DQS1 = 0
3529 06:49:17.761568 DQM Delay:
3530 06:49:17.764731 DQM0 = 118, DQM1 = 113
3531 06:49:17.764815 DQ Delay:
3532 06:49:17.768207 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =119
3533 06:49:17.771307 DQ4 =119, DQ5 =131, DQ6 =123, DQ7 =115
3534 06:49:17.774887 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3535 06:49:17.778230 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3536 06:49:17.778308
3537 06:49:17.778372
3538 06:49:17.778433 ==
3539 06:49:17.781448 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 06:49:17.788183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 06:49:17.788307 ==
3542 06:49:17.788420
3543 06:49:17.788586
3544 06:49:17.788669 TX Vref Scan disable
3545 06:49:17.791463 == TX Byte 0 ==
3546 06:49:17.795004 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3547 06:49:17.801670 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3548 06:49:17.801748 == TX Byte 1 ==
3549 06:49:17.805130 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3550 06:49:17.811693 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3551 06:49:17.811776 ==
3552 06:49:17.815004 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 06:49:17.818369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 06:49:17.818452 ==
3555 06:49:17.829564 TX Vref=22, minBit 1, minWin=25, winSum=420
3556 06:49:17.833114 TX Vref=24, minBit 1, minWin=25, winSum=423
3557 06:49:17.836576 TX Vref=26, minBit 1, minWin=26, winSum=427
3558 06:49:17.839571 TX Vref=28, minBit 0, minWin=26, winSum=428
3559 06:49:17.843015 TX Vref=30, minBit 0, minWin=26, winSum=428
3560 06:49:17.849621 TX Vref=32, minBit 1, minWin=26, winSum=428
3561 06:49:17.853157 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
3562 06:49:17.853240
3563 06:49:17.856324 Final TX Range 1 Vref 28
3564 06:49:17.856407
3565 06:49:17.856472 ==
3566 06:49:17.859432 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 06:49:17.862979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 06:49:17.863062 ==
3569 06:49:17.866347
3570 06:49:17.866429
3571 06:49:17.866494 TX Vref Scan disable
3572 06:49:17.869710 == TX Byte 0 ==
3573 06:49:17.873109 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3574 06:49:17.876312 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3575 06:49:17.879484 == TX Byte 1 ==
3576 06:49:17.882934 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3577 06:49:17.886585 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3578 06:49:17.886667
3579 06:49:17.889441 [DATLAT]
3580 06:49:17.889523 Freq=1200, CH1 RK1
3581 06:49:17.889589
3582 06:49:17.892939 DATLAT Default: 0xd
3583 06:49:17.893047 0, 0xFFFF, sum = 0
3584 06:49:17.896312 1, 0xFFFF, sum = 0
3585 06:49:17.896408 2, 0xFFFF, sum = 0
3586 06:49:17.899584 3, 0xFFFF, sum = 0
3587 06:49:17.899668 4, 0xFFFF, sum = 0
3588 06:49:17.903020 5, 0xFFFF, sum = 0
3589 06:49:17.906235 6, 0xFFFF, sum = 0
3590 06:49:17.906318 7, 0xFFFF, sum = 0
3591 06:49:17.909373 8, 0xFFFF, sum = 0
3592 06:49:17.909457 9, 0xFFFF, sum = 0
3593 06:49:17.912579 10, 0xFFFF, sum = 0
3594 06:49:17.912663 11, 0xFFFF, sum = 0
3595 06:49:17.915880 12, 0x0, sum = 1
3596 06:49:17.915964 13, 0x0, sum = 2
3597 06:49:17.919113 14, 0x0, sum = 3
3598 06:49:17.919196 15, 0x0, sum = 4
3599 06:49:17.919264 best_step = 13
3600 06:49:17.922601
3601 06:49:17.922683 ==
3602 06:49:17.925916 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 06:49:17.929430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 06:49:17.929513 ==
3605 06:49:17.929578 RX Vref Scan: 0
3606 06:49:17.929639
3607 06:49:17.932691 RX Vref 0 -> 0, step: 1
3608 06:49:17.932773
3609 06:49:17.935955 RX Delay -13 -> 252, step: 4
3610 06:49:17.939478 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3611 06:49:17.945589 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3612 06:49:17.948824 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3613 06:49:17.952361 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3614 06:49:17.955540 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3615 06:49:17.958890 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3616 06:49:17.965700 iDelay=195, Bit 6, Center 124 (63 ~ 186) 124
3617 06:49:17.969112 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3618 06:49:17.972470 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3619 06:49:17.975664 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3620 06:49:17.979354 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3621 06:49:17.985566 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3622 06:49:17.988976 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3623 06:49:17.992384 iDelay=195, Bit 13, Center 120 (55 ~ 186) 132
3624 06:49:17.995573 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3625 06:49:17.999222 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3626 06:49:18.002405 ==
3627 06:49:18.005706 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 06:49:18.009061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 06:49:18.009148 ==
3630 06:49:18.009215 DQS Delay:
3631 06:49:18.012357 DQS0 = 0, DQS1 = 0
3632 06:49:18.012440 DQM Delay:
3633 06:49:18.016009 DQM0 = 119, DQM1 = 113
3634 06:49:18.016092 DQ Delay:
3635 06:49:18.019135 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3636 06:49:18.022371 DQ4 =122, DQ5 =130, DQ6 =124, DQ7 =116
3637 06:49:18.025633 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108
3638 06:49:18.028928 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =124
3639 06:49:18.029010
3640 06:49:18.029075
3641 06:49:18.038843 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3642 06:49:18.042394 CH1 RK1: MR19=403, MR18=BF0
3643 06:49:18.045553 CH1_RK1: MR19=0x403, MR18=0xBF0, DQSOSC=405, MR23=63, INC=39, DEC=26
3644 06:49:18.048901 [RxdqsGatingPostProcess] freq 1200
3645 06:49:18.055415 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3646 06:49:18.058838 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 06:49:18.061897 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 06:49:18.065210 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 06:49:18.068653 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 06:49:18.072212 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 06:49:18.075444 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 06:49:18.079332 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 06:49:18.082265 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 06:49:18.082347 Pre-setting of DQS Precalculation
3655 06:49:18.088559 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3656 06:49:18.095326 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3657 06:49:18.101929 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3658 06:49:18.102050
3659 06:49:18.102115
3660 06:49:18.105366 [Calibration Summary] 2400 Mbps
3661 06:49:18.108707 CH 0, Rank 0
3662 06:49:18.108789 SW Impedance : PASS
3663 06:49:18.111976 DUTY Scan : NO K
3664 06:49:18.115120 ZQ Calibration : PASS
3665 06:49:18.115202 Jitter Meter : NO K
3666 06:49:18.118895 CBT Training : PASS
3667 06:49:18.121907 Write leveling : PASS
3668 06:49:18.121998 RX DQS gating : PASS
3669 06:49:18.125185 RX DQ/DQS(RDDQC) : PASS
3670 06:49:18.125267 TX DQ/DQS : PASS
3671 06:49:18.128604 RX DATLAT : PASS
3672 06:49:18.131637 RX DQ/DQS(Engine): PASS
3673 06:49:18.131719 TX OE : NO K
3674 06:49:18.134972 All Pass.
3675 06:49:18.135054
3676 06:49:18.135118 CH 0, Rank 1
3677 06:49:18.138509 SW Impedance : PASS
3678 06:49:18.138591 DUTY Scan : NO K
3679 06:49:18.141533 ZQ Calibration : PASS
3680 06:49:18.144875 Jitter Meter : NO K
3681 06:49:18.144957 CBT Training : PASS
3682 06:49:18.148233 Write leveling : PASS
3683 06:49:18.151812 RX DQS gating : PASS
3684 06:49:18.151894 RX DQ/DQS(RDDQC) : PASS
3685 06:49:18.154682 TX DQ/DQS : PASS
3686 06:49:18.158265 RX DATLAT : PASS
3687 06:49:18.158347 RX DQ/DQS(Engine): PASS
3688 06:49:18.161607 TX OE : NO K
3689 06:49:18.161689 All Pass.
3690 06:49:18.161753
3691 06:49:18.164956 CH 1, Rank 0
3692 06:49:18.165037 SW Impedance : PASS
3693 06:49:18.168483 DUTY Scan : NO K
3694 06:49:18.171798 ZQ Calibration : PASS
3695 06:49:18.171880 Jitter Meter : NO K
3696 06:49:18.174713 CBT Training : PASS
3697 06:49:18.178153 Write leveling : PASS
3698 06:49:18.178235 RX DQS gating : PASS
3699 06:49:18.181436 RX DQ/DQS(RDDQC) : PASS
3700 06:49:18.181518 TX DQ/DQS : PASS
3701 06:49:18.184647 RX DATLAT : PASS
3702 06:49:18.188510 RX DQ/DQS(Engine): PASS
3703 06:49:18.188592 TX OE : NO K
3704 06:49:18.191692 All Pass.
3705 06:49:18.191774
3706 06:49:18.191839 CH 1, Rank 1
3707 06:49:18.194551 SW Impedance : PASS
3708 06:49:18.194634 DUTY Scan : NO K
3709 06:49:18.198200 ZQ Calibration : PASS
3710 06:49:18.201298 Jitter Meter : NO K
3711 06:49:18.201380 CBT Training : PASS
3712 06:49:18.204644 Write leveling : PASS
3713 06:49:18.207801 RX DQS gating : PASS
3714 06:49:18.207883 RX DQ/DQS(RDDQC) : PASS
3715 06:49:18.211400 TX DQ/DQS : PASS
3716 06:49:18.214677 RX DATLAT : PASS
3717 06:49:18.214764 RX DQ/DQS(Engine): PASS
3718 06:49:18.217874 TX OE : NO K
3719 06:49:18.217995 All Pass.
3720 06:49:18.218061
3721 06:49:18.221983 DramC Write-DBI off
3722 06:49:18.224670 PER_BANK_REFRESH: Hybrid Mode
3723 06:49:18.224754 TX_TRACKING: ON
3724 06:49:18.234959 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3725 06:49:18.238106 [FAST_K] Save calibration result to emmc
3726 06:49:18.241474 dramc_set_vcore_voltage set vcore to 650000
3727 06:49:18.244895 Read voltage for 600, 5
3728 06:49:18.244977 Vio18 = 0
3729 06:49:18.245072 Vcore = 650000
3730 06:49:18.248329 Vdram = 0
3731 06:49:18.248411 Vddq = 0
3732 06:49:18.248476 Vmddr = 0
3733 06:49:18.255012 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3734 06:49:18.257971 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3735 06:49:18.261395 MEM_TYPE=3, freq_sel=19
3736 06:49:18.264837 sv_algorithm_assistance_LP4_1600
3737 06:49:18.267863 ============ PULL DRAM RESETB DOWN ============
3738 06:49:18.271150 ========== PULL DRAM RESETB DOWN end =========
3739 06:49:18.277988 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3740 06:49:18.281362 ===================================
3741 06:49:18.281445 LPDDR4 DRAM CONFIGURATION
3742 06:49:18.284465 ===================================
3743 06:49:18.287690 EX_ROW_EN[0] = 0x0
3744 06:49:18.291209 EX_ROW_EN[1] = 0x0
3745 06:49:18.291291 LP4Y_EN = 0x0
3746 06:49:18.294521 WORK_FSP = 0x0
3747 06:49:18.294604 WL = 0x2
3748 06:49:18.297837 RL = 0x2
3749 06:49:18.297919 BL = 0x2
3750 06:49:18.301232 RPST = 0x0
3751 06:49:18.301314 RD_PRE = 0x0
3752 06:49:18.304429 WR_PRE = 0x1
3753 06:49:18.304511 WR_PST = 0x0
3754 06:49:18.307728 DBI_WR = 0x0
3755 06:49:18.307810 DBI_RD = 0x0
3756 06:49:18.311094 OTF = 0x1
3757 06:49:18.314369 ===================================
3758 06:49:18.317795 ===================================
3759 06:49:18.317877 ANA top config
3760 06:49:18.320854 ===================================
3761 06:49:18.324147 DLL_ASYNC_EN = 0
3762 06:49:18.327755 ALL_SLAVE_EN = 1
3763 06:49:18.330771 NEW_RANK_MODE = 1
3764 06:49:18.330855 DLL_IDLE_MODE = 1
3765 06:49:18.334948 LP45_APHY_COMB_EN = 1
3766 06:49:18.337467 TX_ODT_DIS = 1
3767 06:49:18.340966 NEW_8X_MODE = 1
3768 06:49:18.344083 ===================================
3769 06:49:18.347652 ===================================
3770 06:49:18.347735 data_rate = 1200
3771 06:49:18.351078 CKR = 1
3772 06:49:18.354352 DQ_P2S_RATIO = 8
3773 06:49:18.357485 ===================================
3774 06:49:18.360945 CA_P2S_RATIO = 8
3775 06:49:18.364068 DQ_CA_OPEN = 0
3776 06:49:18.367763 DQ_SEMI_OPEN = 0
3777 06:49:18.367847 CA_SEMI_OPEN = 0
3778 06:49:18.370877 CA_FULL_RATE = 0
3779 06:49:18.374172 DQ_CKDIV4_EN = 1
3780 06:49:18.377538 CA_CKDIV4_EN = 1
3781 06:49:18.380788 CA_PREDIV_EN = 0
3782 06:49:18.384372 PH8_DLY = 0
3783 06:49:18.384456 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3784 06:49:18.387451 DQ_AAMCK_DIV = 4
3785 06:49:18.390774 CA_AAMCK_DIV = 4
3786 06:49:18.394201 CA_ADMCK_DIV = 4
3787 06:49:18.397323 DQ_TRACK_CA_EN = 0
3788 06:49:18.400675 CA_PICK = 600
3789 06:49:18.404314 CA_MCKIO = 600
3790 06:49:18.404399 MCKIO_SEMI = 0
3791 06:49:18.407534 PLL_FREQ = 2288
3792 06:49:18.410892 DQ_UI_PI_RATIO = 32
3793 06:49:18.414280 CA_UI_PI_RATIO = 0
3794 06:49:18.417361 ===================================
3795 06:49:18.420865 ===================================
3796 06:49:18.424206 memory_type:LPDDR4
3797 06:49:18.424290 GP_NUM : 10
3798 06:49:18.427194 SRAM_EN : 1
3799 06:49:18.427277 MD32_EN : 0
3800 06:49:18.431123 ===================================
3801 06:49:18.433922 [ANA_INIT] >>>>>>>>>>>>>>
3802 06:49:18.437426 <<<<<< [CONFIGURE PHASE]: ANA_TX
3803 06:49:18.440877 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3804 06:49:18.444103 ===================================
3805 06:49:18.447368 data_rate = 1200,PCW = 0X5800
3806 06:49:18.450805 ===================================
3807 06:49:18.453801 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3808 06:49:18.460791 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 06:49:18.463988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3810 06:49:18.470552 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3811 06:49:18.474175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3812 06:49:18.477085 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3813 06:49:18.477161 [ANA_INIT] flow start
3814 06:49:18.480217 [ANA_INIT] PLL >>>>>>>>
3815 06:49:18.484020 [ANA_INIT] PLL <<<<<<<<
3816 06:49:18.484090 [ANA_INIT] MIDPI >>>>>>>>
3817 06:49:18.486741 [ANA_INIT] MIDPI <<<<<<<<
3818 06:49:18.490106 [ANA_INIT] DLL >>>>>>>>
3819 06:49:18.490175 [ANA_INIT] flow end
3820 06:49:18.497020 ============ LP4 DIFF to SE enter ============
3821 06:49:18.500253 ============ LP4 DIFF to SE exit ============
3822 06:49:18.503275 [ANA_INIT] <<<<<<<<<<<<<
3823 06:49:18.506596 [Flow] Enable top DCM control >>>>>
3824 06:49:18.510172 [Flow] Enable top DCM control <<<<<
3825 06:49:18.513544 Enable DLL master slave shuffle
3826 06:49:18.516521 ==============================================================
3827 06:49:18.519790 Gating Mode config
3828 06:49:18.523163 ==============================================================
3829 06:49:18.526772 Config description:
3830 06:49:18.536561 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3831 06:49:18.543129 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3832 06:49:18.546567 SELPH_MODE 0: By rank 1: By Phase
3833 06:49:18.552987 ==============================================================
3834 06:49:18.556283 GAT_TRACK_EN = 1
3835 06:49:18.559518 RX_GATING_MODE = 2
3836 06:49:18.562942 RX_GATING_TRACK_MODE = 2
3837 06:49:18.566435 SELPH_MODE = 1
3838 06:49:18.569614 PICG_EARLY_EN = 1
3839 06:49:18.569682 VALID_LAT_VALUE = 1
3840 06:49:18.576117 ==============================================================
3841 06:49:18.579856 Enter into Gating configuration >>>>
3842 06:49:18.582708 Exit from Gating configuration <<<<
3843 06:49:18.586326 Enter into DVFS_PRE_config >>>>>
3844 06:49:18.596564 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3845 06:49:18.599325 Exit from DVFS_PRE_config <<<<<
3846 06:49:18.602849 Enter into PICG configuration >>>>
3847 06:49:18.606128 Exit from PICG configuration <<<<
3848 06:49:18.609373 [RX_INPUT] configuration >>>>>
3849 06:49:18.612757 [RX_INPUT] configuration <<<<<
3850 06:49:18.619692 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3851 06:49:18.622631 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3852 06:49:18.629239 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 06:49:18.636007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 06:49:18.642612 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 06:49:18.649287 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 06:49:18.652630 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3857 06:49:18.655644 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3858 06:49:18.659052 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3859 06:49:18.665838 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3860 06:49:18.668948 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3861 06:49:18.672620 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 06:49:18.675854 ===================================
3863 06:49:18.678910 LPDDR4 DRAM CONFIGURATION
3864 06:49:18.682621 ===================================
3865 06:49:18.682704 EX_ROW_EN[0] = 0x0
3866 06:49:18.685710 EX_ROW_EN[1] = 0x0
3867 06:49:18.685782 LP4Y_EN = 0x0
3868 06:49:18.688915 WORK_FSP = 0x0
3869 06:49:18.692625 WL = 0x2
3870 06:49:18.692702 RL = 0x2
3871 06:49:18.695940 BL = 0x2
3872 06:49:18.696014 RPST = 0x0
3873 06:49:18.699123 RD_PRE = 0x0
3874 06:49:18.699194 WR_PRE = 0x1
3875 06:49:18.702385 WR_PST = 0x0
3876 06:49:18.702472 DBI_WR = 0x0
3877 06:49:18.705638 DBI_RD = 0x0
3878 06:49:18.705713 OTF = 0x1
3879 06:49:18.708897 ===================================
3880 06:49:18.712429 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3881 06:49:18.719184 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3882 06:49:18.722281 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3883 06:49:18.725633 ===================================
3884 06:49:18.728831 LPDDR4 DRAM CONFIGURATION
3885 06:49:18.732026 ===================================
3886 06:49:18.732105 EX_ROW_EN[0] = 0x10
3887 06:49:18.735466 EX_ROW_EN[1] = 0x0
3888 06:49:18.735539 LP4Y_EN = 0x0
3889 06:49:18.738726 WORK_FSP = 0x0
3890 06:49:18.738798 WL = 0x2
3891 06:49:18.742173 RL = 0x2
3892 06:49:18.742245 BL = 0x2
3893 06:49:18.745701 RPST = 0x0
3894 06:49:18.748888 RD_PRE = 0x0
3895 06:49:18.748968 WR_PRE = 0x1
3896 06:49:18.751982 WR_PST = 0x0
3897 06:49:18.752053 DBI_WR = 0x0
3898 06:49:18.755517 DBI_RD = 0x0
3899 06:49:18.755587 OTF = 0x1
3900 06:49:18.758815 ===================================
3901 06:49:18.765822 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3902 06:49:18.769190 nWR fixed to 30
3903 06:49:18.772486 [ModeRegInit_LP4] CH0 RK0
3904 06:49:18.772568 [ModeRegInit_LP4] CH0 RK1
3905 06:49:18.775749 [ModeRegInit_LP4] CH1 RK0
3906 06:49:18.778937 [ModeRegInit_LP4] CH1 RK1
3907 06:49:18.779020 match AC timing 17
3908 06:49:18.785667 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3909 06:49:18.788844 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3910 06:49:18.792540 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3911 06:49:18.799159 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3912 06:49:18.802177 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3913 06:49:18.802260 ==
3914 06:49:18.805898 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 06:49:18.808764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3916 06:49:18.808847 ==
3917 06:49:18.815353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3918 06:49:18.822325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3919 06:49:18.825535 [CA 0] Center 36 (6~67) winsize 62
3920 06:49:18.828843 [CA 1] Center 36 (6~67) winsize 62
3921 06:49:18.832233 [CA 2] Center 34 (4~65) winsize 62
3922 06:49:18.835304 [CA 3] Center 34 (3~65) winsize 63
3923 06:49:18.838758 [CA 4] Center 34 (3~65) winsize 63
3924 06:49:18.841867 [CA 5] Center 33 (3~64) winsize 62
3925 06:49:18.842006
3926 06:49:18.845524 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3927 06:49:18.845607
3928 06:49:18.848847 [CATrainingPosCal] consider 1 rank data
3929 06:49:18.851955 u2DelayCellTimex100 = 270/100 ps
3930 06:49:18.855759 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3931 06:49:18.859019 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3932 06:49:18.861862 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3933 06:49:18.865362 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3934 06:49:18.868557 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3935 06:49:18.875316 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3936 06:49:18.875408
3937 06:49:18.878856 CA PerBit enable=1, Macro0, CA PI delay=33
3938 06:49:18.878938
3939 06:49:18.881975 [CBTSetCACLKResult] CA Dly = 33
3940 06:49:18.882071 CS Dly: 5 (0~36)
3941 06:49:18.882140 ==
3942 06:49:18.885152 Dram Type= 6, Freq= 0, CH_0, rank 1
3943 06:49:18.888421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 06:49:18.891925 ==
3945 06:49:18.895307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3946 06:49:18.902102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3947 06:49:18.905437 [CA 0] Center 36 (6~67) winsize 62
3948 06:49:18.908614 [CA 1] Center 36 (6~67) winsize 62
3949 06:49:18.912166 [CA 2] Center 35 (5~66) winsize 62
3950 06:49:18.915201 [CA 3] Center 34 (4~65) winsize 62
3951 06:49:18.918365 [CA 4] Center 34 (4~65) winsize 62
3952 06:49:18.921719 [CA 5] Center 33 (3~64) winsize 62
3953 06:49:18.921802
3954 06:49:18.925359 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3955 06:49:18.925442
3956 06:49:18.928576 [CATrainingPosCal] consider 2 rank data
3957 06:49:18.931798 u2DelayCellTimex100 = 270/100 ps
3958 06:49:18.935064 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3959 06:49:18.938552 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3960 06:49:18.941906 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3961 06:49:18.945216 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3962 06:49:18.951935 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3963 06:49:18.955324 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3964 06:49:18.955407
3965 06:49:18.958175 CA PerBit enable=1, Macro0, CA PI delay=33
3966 06:49:18.958265
3967 06:49:18.961440 [CBTSetCACLKResult] CA Dly = 33
3968 06:49:18.961523 CS Dly: 5 (0~37)
3969 06:49:18.961589
3970 06:49:18.964856 ----->DramcWriteLeveling(PI) begin...
3971 06:49:18.964939 ==
3972 06:49:18.968377 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 06:49:18.975208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 06:49:18.975291 ==
3975 06:49:18.978417 Write leveling (Byte 0): 32 => 32
3976 06:49:18.981807 Write leveling (Byte 1): 31 => 31
3977 06:49:18.981932 DramcWriteLeveling(PI) end<-----
3978 06:49:18.982042
3979 06:49:18.984887 ==
3980 06:49:18.988216 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 06:49:18.991616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 06:49:18.991699 ==
3983 06:49:18.994871 [Gating] SW mode calibration
3984 06:49:19.001507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3985 06:49:19.005230 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3986 06:49:19.011522 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 06:49:19.014642 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 06:49:19.018301 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 06:49:19.025040 0 9 12 | B1->B0 | 3333 3030 | 0 0 | (0 1) (1 1)
3990 06:49:19.027944 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3991 06:49:19.031872 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 06:49:19.038058 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 06:49:19.041319 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 06:49:19.044871 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 06:49:19.051325 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 06:49:19.054576 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3997 06:49:19.057930 0 10 12 | B1->B0 | 2626 3b3b | 0 1 | (0 0) (0 0)
3998 06:49:19.064682 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3999 06:49:19.068144 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 06:49:19.071580 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 06:49:19.074849 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 06:49:19.081222 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 06:49:19.084845 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 06:49:19.088174 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 06:49:19.094853 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4006 06:49:19.097777 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 06:49:19.101392 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 06:49:19.108112 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 06:49:19.111078 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 06:49:19.114352 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 06:49:19.121281 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 06:49:19.124430 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 06:49:19.127729 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 06:49:19.134722 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 06:49:19.137933 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 06:49:19.141557 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 06:49:19.147972 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 06:49:19.150905 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 06:49:19.154199 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 06:49:19.160886 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 06:49:19.164324 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4022 06:49:19.167360 Total UI for P1: 0, mck2ui 16
4023 06:49:19.170702 best dqsien dly found for B0: ( 0, 13, 10)
4024 06:49:19.173805 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 06:49:19.177328 Total UI for P1: 0, mck2ui 16
4026 06:49:19.180713 best dqsien dly found for B1: ( 0, 13, 12)
4027 06:49:19.184089 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4028 06:49:19.187619 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4029 06:49:19.190463
4030 06:49:19.193818 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4031 06:49:19.197047 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4032 06:49:19.200640 [Gating] SW calibration Done
4033 06:49:19.200726 ==
4034 06:49:19.204069 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 06:49:19.207265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 06:49:19.207349 ==
4037 06:49:19.207414 RX Vref Scan: 0
4038 06:49:19.207476
4039 06:49:19.210409 RX Vref 0 -> 0, step: 1
4040 06:49:19.210491
4041 06:49:19.213611 RX Delay -230 -> 252, step: 16
4042 06:49:19.217112 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4043 06:49:19.220579 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4044 06:49:19.227002 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4045 06:49:19.230533 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4046 06:49:19.233843 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4047 06:49:19.236856 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4048 06:49:19.243495 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4049 06:49:19.247014 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4050 06:49:19.250419 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4051 06:49:19.253557 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4052 06:49:19.260402 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4053 06:49:19.263425 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4054 06:49:19.266918 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4055 06:49:19.270272 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4056 06:49:19.276647 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4057 06:49:19.280424 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4058 06:49:19.280507 ==
4059 06:49:19.283400 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 06:49:19.286706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 06:49:19.286788 ==
4062 06:49:19.286854 DQS Delay:
4063 06:49:19.289865 DQS0 = 0, DQS1 = 0
4064 06:49:19.290005 DQM Delay:
4065 06:49:19.293651 DQM0 = 51, DQM1 = 41
4066 06:49:19.293733 DQ Delay:
4067 06:49:19.296826 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4068 06:49:19.300574 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4069 06:49:19.303533 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4070 06:49:19.306878 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4071 06:49:19.306985
4072 06:49:19.307077
4073 06:49:19.307172 ==
4074 06:49:19.309964 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 06:49:19.313341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 06:49:19.316642 ==
4077 06:49:19.316724
4078 06:49:19.316790
4079 06:49:19.316851 TX Vref Scan disable
4080 06:49:19.319972 == TX Byte 0 ==
4081 06:49:19.323071 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4082 06:49:19.326624 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4083 06:49:19.330099 == TX Byte 1 ==
4084 06:49:19.333473 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4085 06:49:19.336608 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4086 06:49:19.339910 ==
4087 06:49:19.343394 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 06:49:19.346687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 06:49:19.346770 ==
4090 06:49:19.346836
4091 06:49:19.346897
4092 06:49:19.349994 TX Vref Scan disable
4093 06:49:19.350076 == TX Byte 0 ==
4094 06:49:19.356393 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4095 06:49:19.359551 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4096 06:49:19.359633 == TX Byte 1 ==
4097 06:49:19.366322 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4098 06:49:19.369733 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4099 06:49:19.369816
4100 06:49:19.369880 [DATLAT]
4101 06:49:19.372940 Freq=600, CH0 RK0
4102 06:49:19.373023
4103 06:49:19.373088 DATLAT Default: 0x9
4104 06:49:19.376849 0, 0xFFFF, sum = 0
4105 06:49:19.376933 1, 0xFFFF, sum = 0
4106 06:49:19.379733 2, 0xFFFF, sum = 0
4107 06:49:19.379818 3, 0xFFFF, sum = 0
4108 06:49:19.383099 4, 0xFFFF, sum = 0
4109 06:49:19.386121 5, 0xFFFF, sum = 0
4110 06:49:19.386206 6, 0xFFFF, sum = 0
4111 06:49:19.389630 7, 0xFFFF, sum = 0
4112 06:49:19.389714 8, 0x0, sum = 1
4113 06:49:19.389781 9, 0x0, sum = 2
4114 06:49:19.393137 10, 0x0, sum = 3
4115 06:49:19.393224 11, 0x0, sum = 4
4116 06:49:19.396317 best_step = 9
4117 06:49:19.396420
4118 06:49:19.396523 ==
4119 06:49:19.399716 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 06:49:19.403278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 06:49:19.403362 ==
4122 06:49:19.406351 RX Vref Scan: 1
4123 06:49:19.406433
4124 06:49:19.406499 RX Vref 0 -> 0, step: 1
4125 06:49:19.406559
4126 06:49:19.409722 RX Delay -179 -> 252, step: 8
4127 06:49:19.409805
4128 06:49:19.413093 Set Vref, RX VrefLevel [Byte0]: 56
4129 06:49:19.416410 [Byte1]: 49
4130 06:49:19.420405
4131 06:49:19.420488 Final RX Vref Byte 0 = 56 to rank0
4132 06:49:19.423393 Final RX Vref Byte 1 = 49 to rank0
4133 06:49:19.427059 Final RX Vref Byte 0 = 56 to rank1
4134 06:49:19.430124 Final RX Vref Byte 1 = 49 to rank1==
4135 06:49:19.433413 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 06:49:19.440031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 06:49:19.440116 ==
4138 06:49:19.440183 DQS Delay:
4139 06:49:19.443347 DQS0 = 0, DQS1 = 0
4140 06:49:19.443431 DQM Delay:
4141 06:49:19.443498 DQM0 = 48, DQM1 = 38
4142 06:49:19.447153 DQ Delay:
4143 06:49:19.450301 DQ0 =48, DQ1 =44, DQ2 =44, DQ3 =44
4144 06:49:19.453542 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4145 06:49:19.456846 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4146 06:49:19.459895 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =44
4147 06:49:19.459980
4148 06:49:19.460046
4149 06:49:19.466806 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a54, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4150 06:49:19.470086 CH0 RK0: MR19=808, MR18=5A54
4151 06:49:19.476581 CH0_RK0: MR19=0x808, MR18=0x5A54, DQSOSC=392, MR23=63, INC=170, DEC=113
4152 06:49:19.476669
4153 06:49:19.480063 ----->DramcWriteLeveling(PI) begin...
4154 06:49:19.480148 ==
4155 06:49:19.483277 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 06:49:19.486824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 06:49:19.486909 ==
4158 06:49:19.490167 Write leveling (Byte 0): 33 => 33
4159 06:49:19.493716 Write leveling (Byte 1): 29 => 29
4160 06:49:19.496629 DramcWriteLeveling(PI) end<-----
4161 06:49:19.496723
4162 06:49:19.496821 ==
4163 06:49:19.499841 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 06:49:19.503609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 06:49:19.503694 ==
4166 06:49:19.506784 [Gating] SW mode calibration
4167 06:49:19.513305 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4168 06:49:19.519817 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4169 06:49:19.523448 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 06:49:19.526872 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 06:49:19.533324 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4172 06:49:19.536838 0 9 12 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (0 0)
4173 06:49:19.540083 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
4174 06:49:19.546867 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 06:49:19.549825 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 06:49:19.553437 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 06:49:19.559942 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 06:49:19.563480 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 06:49:19.567174 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 06:49:19.573350 0 10 12 | B1->B0 | 3131 3131 | 0 0 | (0 0) (0 0)
4181 06:49:19.576605 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4182 06:49:19.580063 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 06:49:19.586758 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 06:49:19.589874 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 06:49:19.593003 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 06:49:19.599829 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 06:49:19.603164 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 06:49:19.606265 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 06:49:19.613064 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 06:49:19.616621 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 06:49:19.619788 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 06:49:19.626314 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 06:49:19.629329 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 06:49:19.632805 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 06:49:19.639638 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 06:49:19.642979 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 06:49:19.646201 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 06:49:19.652885 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 06:49:19.656020 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 06:49:19.659573 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 06:49:19.665789 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 06:49:19.669462 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 06:49:19.672455 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 06:49:19.675938 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4205 06:49:19.682571 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 06:49:19.686291 Total UI for P1: 0, mck2ui 16
4207 06:49:19.689077 best dqsien dly found for B0: ( 0, 13, 12)
4208 06:49:19.692890 Total UI for P1: 0, mck2ui 16
4209 06:49:19.695757 best dqsien dly found for B1: ( 0, 13, 14)
4210 06:49:19.699367 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4211 06:49:19.702561 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4212 06:49:19.702644
4213 06:49:19.705654 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4214 06:49:19.709309 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4215 06:49:19.712391 [Gating] SW calibration Done
4216 06:49:19.712474 ==
4217 06:49:19.715905 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 06:49:19.719346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 06:49:19.719437 ==
4220 06:49:19.722532 RX Vref Scan: 0
4221 06:49:19.722614
4222 06:49:19.726132 RX Vref 0 -> 0, step: 1
4223 06:49:19.726214
4224 06:49:19.726279 RX Delay -230 -> 252, step: 16
4225 06:49:19.732445 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4226 06:49:19.735903 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4227 06:49:19.738982 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4228 06:49:19.742235 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4229 06:49:19.748840 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4230 06:49:19.752102 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4231 06:49:19.755754 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4232 06:49:19.758862 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4233 06:49:19.762433 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4234 06:49:19.768960 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4235 06:49:19.772057 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4236 06:49:19.775382 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4237 06:49:19.778948 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4238 06:49:19.785329 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4239 06:49:19.788768 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4240 06:49:19.792041 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4241 06:49:19.792123 ==
4242 06:49:19.795680 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 06:49:19.798766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 06:49:19.802238 ==
4245 06:49:19.802321 DQS Delay:
4246 06:49:19.802387 DQS0 = 0, DQS1 = 0
4247 06:49:19.805333 DQM Delay:
4248 06:49:19.805416 DQM0 = 51, DQM1 = 43
4249 06:49:19.809830 DQ Delay:
4250 06:49:19.809960 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =41
4251 06:49:19.811906 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4252 06:49:19.815476 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4253 06:49:19.818678 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4254 06:49:19.818761
4255 06:49:19.821972
4256 06:49:19.822054 ==
4257 06:49:19.825531 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 06:49:19.828371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 06:49:19.828454 ==
4260 06:49:19.828520
4261 06:49:19.828580
4262 06:49:19.832033 TX Vref Scan disable
4263 06:49:19.832115 == TX Byte 0 ==
4264 06:49:19.838504 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4265 06:49:19.842003 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4266 06:49:19.842086 == TX Byte 1 ==
4267 06:49:19.848738 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4268 06:49:19.851961 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4269 06:49:19.852044 ==
4270 06:49:19.855242 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 06:49:19.858796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 06:49:19.858879 ==
4273 06:49:19.858944
4274 06:49:19.859003
4275 06:49:19.861809 TX Vref Scan disable
4276 06:49:19.865219 == TX Byte 0 ==
4277 06:49:19.868696 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4278 06:49:19.871689 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4279 06:49:19.875048 == TX Byte 1 ==
4280 06:49:19.878676 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4281 06:49:19.881830 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4282 06:49:19.881976
4283 06:49:19.884937 [DATLAT]
4284 06:49:19.885061 Freq=600, CH0 RK1
4285 06:49:19.885185
4286 06:49:19.888604 DATLAT Default: 0x9
4287 06:49:19.888690 0, 0xFFFF, sum = 0
4288 06:49:19.891650 1, 0xFFFF, sum = 0
4289 06:49:19.891734 2, 0xFFFF, sum = 0
4290 06:49:19.895421 3, 0xFFFF, sum = 0
4291 06:49:19.895531 4, 0xFFFF, sum = 0
4292 06:49:19.898508 5, 0xFFFF, sum = 0
4293 06:49:19.898592 6, 0xFFFF, sum = 0
4294 06:49:19.901524 7, 0xFFFF, sum = 0
4295 06:49:19.901653 8, 0x0, sum = 1
4296 06:49:19.905295 9, 0x0, sum = 2
4297 06:49:19.905436 10, 0x0, sum = 3
4298 06:49:19.908441 11, 0x0, sum = 4
4299 06:49:19.908522 best_step = 9
4300 06:49:19.908586
4301 06:49:19.908646 ==
4302 06:49:19.911771 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 06:49:19.918400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 06:49:19.918481 ==
4305 06:49:19.918545 RX Vref Scan: 0
4306 06:49:19.918605
4307 06:49:19.921844 RX Vref 0 -> 0, step: 1
4308 06:49:19.921974
4309 06:49:19.925081 RX Delay -163 -> 252, step: 8
4310 06:49:19.928233 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4311 06:49:19.931388 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4312 06:49:19.938351 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4313 06:49:19.941512 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4314 06:49:19.944738 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4315 06:49:19.947991 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4316 06:49:19.951361 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4317 06:49:19.958264 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4318 06:49:19.961663 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4319 06:49:19.964667 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4320 06:49:19.967923 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4321 06:49:19.974828 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4322 06:49:19.977820 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4323 06:49:19.981393 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4324 06:49:19.984516 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4325 06:49:19.991358 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4326 06:49:19.991468 ==
4327 06:49:19.994681 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 06:49:19.997700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 06:49:19.997810 ==
4330 06:49:19.997904 DQS Delay:
4331 06:49:20.001500 DQS0 = 0, DQS1 = 0
4332 06:49:20.001620 DQM Delay:
4333 06:49:20.004507 DQM0 = 48, DQM1 = 41
4334 06:49:20.004628 DQ Delay:
4335 06:49:20.007984 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4336 06:49:20.011289 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4337 06:49:20.014501 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4338 06:49:20.018153 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4339 06:49:20.018326
4340 06:49:20.018462
4341 06:49:20.024631 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f2c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4342 06:49:20.027921 CH0 RK1: MR19=808, MR18=5F2C
4343 06:49:20.034709 CH0_RK1: MR19=0x808, MR18=0x5F2C, DQSOSC=391, MR23=63, INC=171, DEC=114
4344 06:49:20.037932 [RxdqsGatingPostProcess] freq 600
4345 06:49:20.044451 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4346 06:49:20.047908 Pre-setting of DQS Precalculation
4347 06:49:20.051506 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4348 06:49:20.051964 ==
4349 06:49:20.054551 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 06:49:20.057802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 06:49:20.058306 ==
4352 06:49:20.064500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4353 06:49:20.071341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4354 06:49:20.074381 [CA 0] Center 35 (5~66) winsize 62
4355 06:49:20.078013 [CA 1] Center 35 (5~66) winsize 62
4356 06:49:20.081388 [CA 2] Center 34 (4~64) winsize 61
4357 06:49:20.084763 [CA 3] Center 33 (3~64) winsize 62
4358 06:49:20.088279 [CA 4] Center 34 (3~65) winsize 63
4359 06:49:20.091420 [CA 5] Center 33 (3~64) winsize 62
4360 06:49:20.091847
4361 06:49:20.094226 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4362 06:49:20.094656
4363 06:49:20.097859 [CATrainingPosCal] consider 1 rank data
4364 06:49:20.101497 u2DelayCellTimex100 = 270/100 ps
4365 06:49:20.105043 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4366 06:49:20.107757 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4367 06:49:20.111137 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4368 06:49:20.114685 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4369 06:49:20.117993 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4370 06:49:20.121120 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4371 06:49:20.121546
4372 06:49:20.127844 CA PerBit enable=1, Macro0, CA PI delay=33
4373 06:49:20.128272
4374 06:49:20.131454 [CBTSetCACLKResult] CA Dly = 33
4375 06:49:20.131889 CS Dly: 5 (0~36)
4376 06:49:20.132232 ==
4377 06:49:20.134300 Dram Type= 6, Freq= 0, CH_1, rank 1
4378 06:49:20.137764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 06:49:20.138242 ==
4380 06:49:20.144356 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 06:49:20.150916 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4382 06:49:20.154521 [CA 0] Center 36 (6~66) winsize 61
4383 06:49:20.157907 [CA 1] Center 35 (5~66) winsize 62
4384 06:49:20.161291 [CA 2] Center 34 (4~65) winsize 62
4385 06:49:20.164407 [CA 3] Center 34 (4~65) winsize 62
4386 06:49:20.167693 [CA 4] Center 34 (4~65) winsize 62
4387 06:49:20.171445 [CA 5] Center 34 (3~65) winsize 63
4388 06:49:20.171853
4389 06:49:20.174635 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4390 06:49:20.175016
4391 06:49:20.177590 [CATrainingPosCal] consider 2 rank data
4392 06:49:20.181361 u2DelayCellTimex100 = 270/100 ps
4393 06:49:20.184533 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4394 06:49:20.187791 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4395 06:49:20.191280 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4396 06:49:20.194673 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4397 06:49:20.197558 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 06:49:20.200908 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 06:49:20.204425
4400 06:49:20.207871 CA PerBit enable=1, Macro0, CA PI delay=33
4401 06:49:20.208302
4402 06:49:20.211102 [CBTSetCACLKResult] CA Dly = 33
4403 06:49:20.211551 CS Dly: 5 (0~37)
4404 06:49:20.211981
4405 06:49:20.214435 ----->DramcWriteLeveling(PI) begin...
4406 06:49:20.214871 ==
4407 06:49:20.218320 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 06:49:20.221217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 06:49:20.224448 ==
4410 06:49:20.224875 Write leveling (Byte 0): 30 => 30
4411 06:49:20.227665 Write leveling (Byte 1): 30 => 30
4412 06:49:20.231022 DramcWriteLeveling(PI) end<-----
4413 06:49:20.231453
4414 06:49:20.231791 ==
4415 06:49:20.234231 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 06:49:20.240948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 06:49:20.241385 ==
4418 06:49:20.241734 [Gating] SW mode calibration
4419 06:49:20.250543 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4420 06:49:20.254138 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4421 06:49:20.260709 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 06:49:20.264036 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 06:49:20.267340 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4424 06:49:20.270335 0 9 12 | B1->B0 | 2a2a 2424 | 1 0 | (1 0) (1 0)
4425 06:49:20.277154 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 06:49:20.280524 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 06:49:20.283635 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 06:49:20.290268 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 06:49:20.293606 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 06:49:20.297254 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 06:49:20.304044 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4432 06:49:20.307255 0 10 12 | B1->B0 | 3a3a 4141 | 1 0 | (0 0) (0 0)
4433 06:49:20.310284 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 06:49:20.317209 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 06:49:20.320543 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 06:49:20.323946 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 06:49:20.330746 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 06:49:20.333658 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 06:49:20.337169 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4440 06:49:20.344061 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4441 06:49:20.347288 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 06:49:20.350299 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 06:49:20.357329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 06:49:20.360596 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 06:49:20.363752 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 06:49:20.370339 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 06:49:20.374016 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 06:49:20.377068 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 06:49:20.383527 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 06:49:20.387013 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 06:49:20.389964 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 06:49:20.396690 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 06:49:20.399895 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 06:49:20.403415 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 06:49:20.410216 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 06:49:20.413058 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4457 06:49:20.418246 Total UI for P1: 0, mck2ui 16
4458 06:49:20.419730 best dqsien dly found for B0: ( 0, 13, 10)
4459 06:49:20.423328 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 06:49:20.426746 Total UI for P1: 0, mck2ui 16
4461 06:49:20.429757 best dqsien dly found for B1: ( 0, 13, 14)
4462 06:49:20.433408 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4463 06:49:20.436315 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4464 06:49:20.436745
4465 06:49:20.439766 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4466 06:49:20.446370 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4467 06:49:20.446782 [Gating] SW calibration Done
4468 06:49:20.449896 ==
4469 06:49:20.450322 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 06:49:20.456265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 06:49:20.456775 ==
4472 06:49:20.457168 RX Vref Scan: 0
4473 06:49:20.457545
4474 06:49:20.459782 RX Vref 0 -> 0, step: 1
4475 06:49:20.460277
4476 06:49:20.463362 RX Delay -230 -> 252, step: 16
4477 06:49:20.466250 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4478 06:49:20.469676 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4479 06:49:20.473295 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4480 06:49:20.479670 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4481 06:49:20.483176 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4482 06:49:20.486305 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4483 06:49:20.489671 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4484 06:49:20.496050 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4485 06:49:20.499612 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4486 06:49:20.502843 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4487 06:49:20.506207 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4488 06:49:20.509484 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4489 06:49:20.516230 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4490 06:49:20.519873 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4491 06:49:20.523062 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4492 06:49:20.526792 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4493 06:49:20.529997 ==
4494 06:49:20.533090 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 06:49:20.536222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 06:49:20.536652 ==
4497 06:49:20.536992 DQS Delay:
4498 06:49:20.539457 DQS0 = 0, DQS1 = 0
4499 06:49:20.539879 DQM Delay:
4500 06:49:20.542693 DQM0 = 52, DQM1 = 39
4501 06:49:20.543116 DQ Delay:
4502 06:49:20.546361 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4503 06:49:20.549537 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4504 06:49:20.552808 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4505 06:49:20.556540 DQ12 =57, DQ13 =41, DQ14 =41, DQ15 =41
4506 06:49:20.556984
4507 06:49:20.557424
4508 06:49:20.557838 ==
4509 06:49:20.559670 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 06:49:20.562784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 06:49:20.563229 ==
4512 06:49:20.563671
4513 06:49:20.564084
4514 06:49:20.565983 TX Vref Scan disable
4515 06:49:20.569717 == TX Byte 0 ==
4516 06:49:20.572877 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4517 06:49:20.576210 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4518 06:49:20.579182 == TX Byte 1 ==
4519 06:49:20.582543 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4520 06:49:20.586302 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4521 06:49:20.586754 ==
4522 06:49:20.589122 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 06:49:20.592599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 06:49:20.596064 ==
4525 06:49:20.596513
4526 06:49:20.596853
4527 06:49:20.597165 TX Vref Scan disable
4528 06:49:20.599762 == TX Byte 0 ==
4529 06:49:20.603731 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4530 06:49:20.609738 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4531 06:49:20.610279 == TX Byte 1 ==
4532 06:49:20.613302 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4533 06:49:20.616571 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4534 06:49:20.619725
4535 06:49:20.620177 [DATLAT]
4536 06:49:20.620541 Freq=600, CH1 RK0
4537 06:49:20.620884
4538 06:49:20.623283 DATLAT Default: 0x9
4539 06:49:20.623682 0, 0xFFFF, sum = 0
4540 06:49:20.626348 1, 0xFFFF, sum = 0
4541 06:49:20.626805 2, 0xFFFF, sum = 0
4542 06:49:20.629989 3, 0xFFFF, sum = 0
4543 06:49:20.630437 4, 0xFFFF, sum = 0
4544 06:49:20.633115 5, 0xFFFF, sum = 0
4545 06:49:20.636611 6, 0xFFFF, sum = 0
4546 06:49:20.637058 7, 0xFFFF, sum = 0
4547 06:49:20.637507 8, 0x0, sum = 1
4548 06:49:20.639596 9, 0x0, sum = 2
4549 06:49:20.640045 10, 0x0, sum = 3
4550 06:49:20.643326 11, 0x0, sum = 4
4551 06:49:20.643774 best_step = 9
4552 06:49:20.644212
4553 06:49:20.644626 ==
4554 06:49:20.646370 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 06:49:20.653256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 06:49:20.653669 ==
4557 06:49:20.654071 RX Vref Scan: 1
4558 06:49:20.654409
4559 06:49:20.656335 RX Vref 0 -> 0, step: 1
4560 06:49:20.656706
4561 06:49:20.659640 RX Delay -179 -> 252, step: 8
4562 06:49:20.660056
4563 06:49:20.663364 Set Vref, RX VrefLevel [Byte0]: 52
4564 06:49:20.666241 [Byte1]: 57
4565 06:49:20.666650
4566 06:49:20.669972 Final RX Vref Byte 0 = 52 to rank0
4567 06:49:20.672859 Final RX Vref Byte 1 = 57 to rank0
4568 06:49:20.676508 Final RX Vref Byte 0 = 52 to rank1
4569 06:49:20.679933 Final RX Vref Byte 1 = 57 to rank1==
4570 06:49:20.683601 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 06:49:20.686628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 06:49:20.687156 ==
4573 06:49:20.689676 DQS Delay:
4574 06:49:20.690258 DQS0 = 0, DQS1 = 0
4575 06:49:20.690656 DQM Delay:
4576 06:49:20.693003 DQM0 = 47, DQM1 = 40
4577 06:49:20.693508 DQ Delay:
4578 06:49:20.696391 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4579 06:49:20.699957 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4580 06:49:20.703002 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4581 06:49:20.706418 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =44
4582 06:49:20.706911
4583 06:49:20.707298
4584 06:49:20.716414 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d74, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4585 06:49:20.716927 CH1 RK0: MR19=808, MR18=4D74
4586 06:49:20.723186 CH1_RK0: MR19=0x808, MR18=0x4D74, DQSOSC=388, MR23=63, INC=174, DEC=116
4587 06:49:20.723679
4588 06:49:20.726391 ----->DramcWriteLeveling(PI) begin...
4589 06:49:20.729528 ==
4590 06:49:20.730068 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 06:49:20.736243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 06:49:20.736740 ==
4593 06:49:20.739952 Write leveling (Byte 0): 29 => 29
4594 06:49:20.743317 Write leveling (Byte 1): 30 => 30
4595 06:49:20.746637 DramcWriteLeveling(PI) end<-----
4596 06:49:20.747129
4597 06:49:20.747523 ==
4598 06:49:20.749871 Dram Type= 6, Freq= 0, CH_1, rank 1
4599 06:49:20.752840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 06:49:20.753308 ==
4601 06:49:20.756179 [Gating] SW mode calibration
4602 06:49:20.762886 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4603 06:49:20.766177 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4604 06:49:20.772641 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4605 06:49:20.776336 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 06:49:20.779599 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4607 06:49:20.786301 0 9 12 | B1->B0 | 2828 3030 | 0 1 | (0 1) (1 0)
4608 06:49:20.789432 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4609 06:49:20.792828 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 06:49:20.799633 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 06:49:20.802750 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 06:49:20.806170 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 06:49:20.812656 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 06:49:20.815985 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 06:49:20.819555 0 10 12 | B1->B0 | 3b3b 2e2e | 0 0 | (0 0) (0 0)
4616 06:49:20.825783 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 06:49:20.829145 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 06:49:20.832697 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 06:49:20.839294 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 06:49:20.842910 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 06:49:20.846088 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 06:49:20.852698 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4623 06:49:20.856002 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4624 06:49:20.859246 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 06:49:20.862538 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 06:49:20.869359 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 06:49:20.872734 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 06:49:20.876239 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 06:49:20.882421 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 06:49:20.885580 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 06:49:20.888969 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 06:49:20.895748 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 06:49:20.899216 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 06:49:20.902348 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 06:49:20.909141 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 06:49:20.912254 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 06:49:20.915500 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 06:49:20.922353 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 06:49:20.925976 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4640 06:49:20.929462 Total UI for P1: 0, mck2ui 16
4641 06:49:20.932409 best dqsien dly found for B1: ( 0, 13, 10)
4642 06:49:20.935776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 06:49:20.939187 Total UI for P1: 0, mck2ui 16
4644 06:49:20.942461 best dqsien dly found for B0: ( 0, 13, 12)
4645 06:49:20.945726 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4646 06:49:20.948916 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4647 06:49:20.949460
4648 06:49:20.955884 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4649 06:49:20.959518 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4650 06:49:20.960019 [Gating] SW calibration Done
4651 06:49:20.962553 ==
4652 06:49:20.966111 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 06:49:20.969593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 06:49:20.970177 ==
4655 06:49:20.970590 RX Vref Scan: 0
4656 06:49:20.970977
4657 06:49:20.972655 RX Vref 0 -> 0, step: 1
4658 06:49:20.973156
4659 06:49:20.976094 RX Delay -230 -> 252, step: 16
4660 06:49:20.979275 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4661 06:49:20.982866 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4662 06:49:20.989591 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4663 06:49:20.992432 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4664 06:49:20.996077 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4665 06:49:20.999526 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4666 06:49:21.002636 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4667 06:49:21.009154 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4668 06:49:21.012694 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4669 06:49:21.016066 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4670 06:49:21.019348 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4671 06:49:21.026359 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4672 06:49:21.029344 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4673 06:49:21.032767 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4674 06:49:21.035701 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4675 06:49:21.042588 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4676 06:49:21.043077 ==
4677 06:49:21.045835 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 06:49:21.049208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 06:49:21.049678 ==
4680 06:49:21.050156 DQS Delay:
4681 06:49:21.052371 DQS0 = 0, DQS1 = 0
4682 06:49:21.052833 DQM Delay:
4683 06:49:21.055690 DQM0 = 51, DQM1 = 44
4684 06:49:21.056203 DQ Delay:
4685 06:49:21.059041 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4686 06:49:21.062023 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4687 06:49:21.065535 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4688 06:49:21.068805 DQ12 =57, DQ13 =57, DQ14 =41, DQ15 =57
4689 06:49:21.069227
4690 06:49:21.069559
4691 06:49:21.069868 ==
4692 06:49:21.072104 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 06:49:21.075605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 06:49:21.076029 ==
4695 06:49:21.076362
4696 06:49:21.076673
4697 06:49:21.078724 TX Vref Scan disable
4698 06:49:21.082095 == TX Byte 0 ==
4699 06:49:21.085421 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4700 06:49:21.088803 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4701 06:49:21.092239 == TX Byte 1 ==
4702 06:49:21.095430 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4703 06:49:21.098601 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4704 06:49:21.099026 ==
4705 06:49:21.101811 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 06:49:21.108268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 06:49:21.108735 ==
4708 06:49:21.109240
4709 06:49:21.109728
4710 06:49:21.110108 TX Vref Scan disable
4711 06:49:21.113097 == TX Byte 0 ==
4712 06:49:21.116243 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4713 06:49:21.122918 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4714 06:49:21.123431 == TX Byte 1 ==
4715 06:49:21.126688 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4716 06:49:21.132665 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4717 06:49:21.133164
4718 06:49:21.133558 [DATLAT]
4719 06:49:21.133936 Freq=600, CH1 RK1
4720 06:49:21.134347
4721 06:49:21.136249 DATLAT Default: 0x9
4722 06:49:21.136785 0, 0xFFFF, sum = 0
4723 06:49:21.139399 1, 0xFFFF, sum = 0
4724 06:49:21.142614 2, 0xFFFF, sum = 0
4725 06:49:21.143174 3, 0xFFFF, sum = 0
4726 06:49:21.146084 4, 0xFFFF, sum = 0
4727 06:49:21.146641 5, 0xFFFF, sum = 0
4728 06:49:21.149192 6, 0xFFFF, sum = 0
4729 06:49:21.149755 7, 0xFFFF, sum = 0
4730 06:49:21.152674 8, 0x0, sum = 1
4731 06:49:21.153169 9, 0x0, sum = 2
4732 06:49:21.153577 10, 0x0, sum = 3
4733 06:49:21.156018 11, 0x0, sum = 4
4734 06:49:21.156600 best_step = 9
4735 06:49:21.157025
4736 06:49:21.157417 ==
4737 06:49:21.159442 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 06:49:21.166085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 06:49:21.166574 ==
4740 06:49:21.166978 RX Vref Scan: 0
4741 06:49:21.167357
4742 06:49:21.169520 RX Vref 0 -> 0, step: 1
4743 06:49:21.170047
4744 06:49:21.172726 RX Delay -179 -> 252, step: 8
4745 06:49:21.176031 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4746 06:49:21.182663 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4747 06:49:21.185744 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4748 06:49:21.189165 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4749 06:49:21.192444 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4750 06:49:21.195957 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4751 06:49:21.202727 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4752 06:49:21.205936 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4753 06:49:21.209293 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4754 06:49:21.212598 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4755 06:49:21.215832 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4756 06:49:21.222333 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4757 06:49:21.225881 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4758 06:49:21.228903 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4759 06:49:21.232573 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4760 06:49:21.239168 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4761 06:49:21.239659 ==
4762 06:49:21.242779 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 06:49:21.245589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 06:49:21.246209 ==
4765 06:49:21.246778 DQS Delay:
4766 06:49:21.249556 DQS0 = 0, DQS1 = 0
4767 06:49:21.250074 DQM Delay:
4768 06:49:21.252854 DQM0 = 48, DQM1 = 42
4769 06:49:21.253374 DQ Delay:
4770 06:49:21.255750 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4771 06:49:21.258910 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4772 06:49:21.262253 DQ8 =24, DQ9 =32, DQ10 =44, DQ11 =40
4773 06:49:21.265536 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4774 06:49:21.266053
4775 06:49:21.266420
4776 06:49:21.271959 [DQSOSCAuto] RK1, (LSB)MR18= 0x551d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4777 06:49:21.275134 CH1 RK1: MR19=808, MR18=551D
4778 06:49:21.281841 CH1_RK1: MR19=0x808, MR18=0x551D, DQSOSC=393, MR23=63, INC=169, DEC=113
4779 06:49:21.285304 [RxdqsGatingPostProcess] freq 600
4780 06:49:21.291682 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4781 06:49:21.295026 Pre-setting of DQS Precalculation
4782 06:49:21.298472 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4783 06:49:21.304953 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4784 06:49:21.311837 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4785 06:49:21.311917
4786 06:49:21.311985
4787 06:49:21.314937 [Calibration Summary] 1200 Mbps
4788 06:49:21.318367 CH 0, Rank 0
4789 06:49:21.318466 SW Impedance : PASS
4790 06:49:21.321541 DUTY Scan : NO K
4791 06:49:21.325077 ZQ Calibration : PASS
4792 06:49:21.325149 Jitter Meter : NO K
4793 06:49:21.328617 CBT Training : PASS
4794 06:49:21.328689 Write leveling : PASS
4795 06:49:21.331616 RX DQS gating : PASS
4796 06:49:21.334837 RX DQ/DQS(RDDQC) : PASS
4797 06:49:21.334909 TX DQ/DQS : PASS
4798 06:49:21.338213 RX DATLAT : PASS
4799 06:49:21.341612 RX DQ/DQS(Engine): PASS
4800 06:49:21.341711 TX OE : NO K
4801 06:49:21.344943 All Pass.
4802 06:49:21.345041
4803 06:49:21.345130 CH 0, Rank 1
4804 06:49:21.348377 SW Impedance : PASS
4805 06:49:21.348448 DUTY Scan : NO K
4806 06:49:21.351389 ZQ Calibration : PASS
4807 06:49:21.355176 Jitter Meter : NO K
4808 06:49:21.355258 CBT Training : PASS
4809 06:49:21.358002 Write leveling : PASS
4810 06:49:21.361620 RX DQS gating : PASS
4811 06:49:21.361717 RX DQ/DQS(RDDQC) : PASS
4812 06:49:21.364936 TX DQ/DQS : PASS
4813 06:49:21.368490 RX DATLAT : PASS
4814 06:49:21.368588 RX DQ/DQS(Engine): PASS
4815 06:49:21.371533 TX OE : NO K
4816 06:49:21.371629 All Pass.
4817 06:49:21.371721
4818 06:49:21.374855 CH 1, Rank 0
4819 06:49:21.374926 SW Impedance : PASS
4820 06:49:21.378057 DUTY Scan : NO K
4821 06:49:21.381709 ZQ Calibration : PASS
4822 06:49:21.381809 Jitter Meter : NO K
4823 06:49:21.384696 CBT Training : PASS
4824 06:49:21.384793 Write leveling : PASS
4825 06:49:21.387970 RX DQS gating : PASS
4826 06:49:21.391441 RX DQ/DQS(RDDQC) : PASS
4827 06:49:21.391538 TX DQ/DQS : PASS
4828 06:49:21.394666 RX DATLAT : PASS
4829 06:49:21.397847 RX DQ/DQS(Engine): PASS
4830 06:49:21.397965 TX OE : NO K
4831 06:49:21.401610 All Pass.
4832 06:49:21.401680
4833 06:49:21.401747 CH 1, Rank 1
4834 06:49:21.404869 SW Impedance : PASS
4835 06:49:21.404965 DUTY Scan : NO K
4836 06:49:21.407794 ZQ Calibration : PASS
4837 06:49:21.411385 Jitter Meter : NO K
4838 06:49:21.411461 CBT Training : PASS
4839 06:49:21.414601 Write leveling : PASS
4840 06:49:21.417771 RX DQS gating : PASS
4841 06:49:21.417870 RX DQ/DQS(RDDQC) : PASS
4842 06:49:21.421126 TX DQ/DQS : PASS
4843 06:49:21.424890 RX DATLAT : PASS
4844 06:49:21.425006 RX DQ/DQS(Engine): PASS
4845 06:49:21.427772 TX OE : NO K
4846 06:49:21.427870 All Pass.
4847 06:49:21.427959
4848 06:49:21.431056 DramC Write-DBI off
4849 06:49:21.434503 PER_BANK_REFRESH: Hybrid Mode
4850 06:49:21.434588 TX_TRACKING: ON
4851 06:49:21.444558 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4852 06:49:21.447977 [FAST_K] Save calibration result to emmc
4853 06:49:21.451157 dramc_set_vcore_voltage set vcore to 662500
4854 06:49:21.454828 Read voltage for 933, 3
4855 06:49:21.454906 Vio18 = 0
4856 06:49:21.454980 Vcore = 662500
4857 06:49:21.457763 Vdram = 0
4858 06:49:21.457858 Vddq = 0
4859 06:49:21.457968 Vmddr = 0
4860 06:49:21.464535 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4861 06:49:21.467767 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4862 06:49:21.471038 MEM_TYPE=3, freq_sel=17
4863 06:49:21.474664 sv_algorithm_assistance_LP4_1600
4864 06:49:21.477823 ============ PULL DRAM RESETB DOWN ============
4865 06:49:21.480868 ========== PULL DRAM RESETB DOWN end =========
4866 06:49:21.487483 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4867 06:49:21.490794 ===================================
4868 06:49:21.490897 LPDDR4 DRAM CONFIGURATION
4869 06:49:21.494314 ===================================
4870 06:49:21.497552 EX_ROW_EN[0] = 0x0
4871 06:49:21.500945 EX_ROW_EN[1] = 0x0
4872 06:49:21.501022 LP4Y_EN = 0x0
4873 06:49:21.504684 WORK_FSP = 0x0
4874 06:49:21.504758 WL = 0x3
4875 06:49:21.507595 RL = 0x3
4876 06:49:21.507670 BL = 0x2
4877 06:49:21.510913 RPST = 0x0
4878 06:49:21.510986 RD_PRE = 0x0
4879 06:49:21.514359 WR_PRE = 0x1
4880 06:49:21.514457 WR_PST = 0x0
4881 06:49:21.517515 DBI_WR = 0x0
4882 06:49:21.517586 DBI_RD = 0x0
4883 06:49:21.521001 OTF = 0x1
4884 06:49:21.524591 ===================================
4885 06:49:21.527798 ===================================
4886 06:49:21.527869 ANA top config
4887 06:49:21.530904 ===================================
4888 06:49:21.534258 DLL_ASYNC_EN = 0
4889 06:49:21.537627 ALL_SLAVE_EN = 1
4890 06:49:21.537705 NEW_RANK_MODE = 1
4891 06:49:21.540829 DLL_IDLE_MODE = 1
4892 06:49:21.544088 LP45_APHY_COMB_EN = 1
4893 06:49:21.547367 TX_ODT_DIS = 1
4894 06:49:21.550902 NEW_8X_MODE = 1
4895 06:49:21.554192 ===================================
4896 06:49:21.557239 ===================================
4897 06:49:21.557311 data_rate = 1866
4898 06:49:21.560910 CKR = 1
4899 06:49:21.564266 DQ_P2S_RATIO = 8
4900 06:49:21.567799 ===================================
4901 06:49:21.570854 CA_P2S_RATIO = 8
4902 06:49:21.574328 DQ_CA_OPEN = 0
4903 06:49:21.577558 DQ_SEMI_OPEN = 0
4904 06:49:21.577657 CA_SEMI_OPEN = 0
4905 06:49:21.581157 CA_FULL_RATE = 0
4906 06:49:21.584320 DQ_CKDIV4_EN = 1
4907 06:49:21.588046 CA_CKDIV4_EN = 1
4908 06:49:21.590882 CA_PREDIV_EN = 0
4909 06:49:21.590981 PH8_DLY = 0
4910 06:49:21.594423 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4911 06:49:21.597757 DQ_AAMCK_DIV = 4
4912 06:49:21.601144 CA_AAMCK_DIV = 4
4913 06:49:21.604554 CA_ADMCK_DIV = 4
4914 06:49:21.607491 DQ_TRACK_CA_EN = 0
4915 06:49:21.611107 CA_PICK = 933
4916 06:49:21.611179 CA_MCKIO = 933
4917 06:49:21.614131 MCKIO_SEMI = 0
4918 06:49:21.617580 PLL_FREQ = 3732
4919 06:49:21.620849 DQ_UI_PI_RATIO = 32
4920 06:49:21.624226 CA_UI_PI_RATIO = 0
4921 06:49:21.627419 ===================================
4922 06:49:21.630840 ===================================
4923 06:49:21.634436 memory_type:LPDDR4
4924 06:49:21.634538 GP_NUM : 10
4925 06:49:21.637701 SRAM_EN : 1
4926 06:49:21.637781 MD32_EN : 0
4927 06:49:21.641026 ===================================
4928 06:49:21.644142 [ANA_INIT] >>>>>>>>>>>>>>
4929 06:49:21.647367 <<<<<< [CONFIGURE PHASE]: ANA_TX
4930 06:49:21.651144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4931 06:49:21.654016 ===================================
4932 06:49:21.657250 data_rate = 1866,PCW = 0X8f00
4933 06:49:21.660886 ===================================
4934 06:49:21.664000 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4935 06:49:21.667417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4936 06:49:21.673923 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 06:49:21.680442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4938 06:49:21.683748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4939 06:49:21.687442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4940 06:49:21.687518 [ANA_INIT] flow start
4941 06:49:21.690460 [ANA_INIT] PLL >>>>>>>>
4942 06:49:21.693750 [ANA_INIT] PLL <<<<<<<<
4943 06:49:21.693827 [ANA_INIT] MIDPI >>>>>>>>
4944 06:49:21.697162 [ANA_INIT] MIDPI <<<<<<<<
4945 06:49:21.700834 [ANA_INIT] DLL >>>>>>>>
4946 06:49:21.700910 [ANA_INIT] flow end
4947 06:49:21.703891 ============ LP4 DIFF to SE enter ============
4948 06:49:21.710556 ============ LP4 DIFF to SE exit ============
4949 06:49:21.710631 [ANA_INIT] <<<<<<<<<<<<<
4950 06:49:21.713888 [Flow] Enable top DCM control >>>>>
4951 06:49:21.717521 [Flow] Enable top DCM control <<<<<
4952 06:49:21.720696 Enable DLL master slave shuffle
4953 06:49:21.727155 ==============================================================
4954 06:49:21.727231 Gating Mode config
4955 06:49:21.733994 ==============================================================
4956 06:49:21.737452 Config description:
4957 06:49:21.747391 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4958 06:49:21.753769 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4959 06:49:21.757500 SELPH_MODE 0: By rank 1: By Phase
4960 06:49:21.763664 ==============================================================
4961 06:49:21.767328 GAT_TRACK_EN = 1
4962 06:49:21.770583 RX_GATING_MODE = 2
4963 06:49:21.770654 RX_GATING_TRACK_MODE = 2
4964 06:49:21.773718 SELPH_MODE = 1
4965 06:49:21.776929 PICG_EARLY_EN = 1
4966 06:49:21.780692 VALID_LAT_VALUE = 1
4967 06:49:21.787076 ==============================================================
4968 06:49:21.790146 Enter into Gating configuration >>>>
4969 06:49:21.793640 Exit from Gating configuration <<<<
4970 06:49:21.796789 Enter into DVFS_PRE_config >>>>>
4971 06:49:21.806993 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4972 06:49:21.810425 Exit from DVFS_PRE_config <<<<<
4973 06:49:21.813688 Enter into PICG configuration >>>>
4974 06:49:21.817405 Exit from PICG configuration <<<<
4975 06:49:21.820162 [RX_INPUT] configuration >>>>>
4976 06:49:21.823460 [RX_INPUT] configuration <<<<<
4977 06:49:21.826836 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4978 06:49:21.833518 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4979 06:49:21.840439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 06:49:21.843662 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 06:49:21.850541 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4982 06:49:21.856999 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4983 06:49:21.860149 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4984 06:49:21.866813 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4985 06:49:21.870087 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4986 06:49:21.873461 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4987 06:49:21.876817 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4988 06:49:21.883595 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 06:49:21.886600 ===================================
4990 06:49:21.886707 LPDDR4 DRAM CONFIGURATION
4991 06:49:21.889814 ===================================
4992 06:49:21.893301 EX_ROW_EN[0] = 0x0
4993 06:49:21.896747 EX_ROW_EN[1] = 0x0
4994 06:49:21.896858 LP4Y_EN = 0x0
4995 06:49:21.900211 WORK_FSP = 0x0
4996 06:49:21.900320 WL = 0x3
4997 06:49:21.903476 RL = 0x3
4998 06:49:21.903550 BL = 0x2
4999 06:49:21.906822 RPST = 0x0
5000 06:49:21.906895 RD_PRE = 0x0
5001 06:49:21.910351 WR_PRE = 0x1
5002 06:49:21.910424 WR_PST = 0x0
5003 06:49:21.913346 DBI_WR = 0x0
5004 06:49:21.913446 DBI_RD = 0x0
5005 06:49:21.916639 OTF = 0x1
5006 06:49:21.919927 ===================================
5007 06:49:21.923231 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5008 06:49:21.926307 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5009 06:49:21.933146 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 06:49:21.936212 ===================================
5011 06:49:21.936286 LPDDR4 DRAM CONFIGURATION
5012 06:49:21.939964 ===================================
5013 06:49:21.943065 EX_ROW_EN[0] = 0x10
5014 06:49:21.946205 EX_ROW_EN[1] = 0x0
5015 06:49:21.946305 LP4Y_EN = 0x0
5016 06:49:21.949844 WORK_FSP = 0x0
5017 06:49:21.949948 WL = 0x3
5018 06:49:21.953143 RL = 0x3
5019 06:49:21.953240 BL = 0x2
5020 06:49:21.956542 RPST = 0x0
5021 06:49:21.956639 RD_PRE = 0x0
5022 06:49:21.959665 WR_PRE = 0x1
5023 06:49:21.959738 WR_PST = 0x0
5024 06:49:21.962843 DBI_WR = 0x0
5025 06:49:21.962920 DBI_RD = 0x0
5026 06:49:21.966658 OTF = 0x1
5027 06:49:21.969355 ===================================
5028 06:49:21.976445 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5029 06:49:21.979599 nWR fixed to 30
5030 06:49:21.979680 [ModeRegInit_LP4] CH0 RK0
5031 06:49:21.982696 [ModeRegInit_LP4] CH0 RK1
5032 06:49:21.986427 [ModeRegInit_LP4] CH1 RK0
5033 06:49:21.989531 [ModeRegInit_LP4] CH1 RK1
5034 06:49:21.989630 match AC timing 9
5035 06:49:21.992823 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5036 06:49:21.999482 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5037 06:49:22.002855 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5038 06:49:22.005968 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5039 06:49:22.013283 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5040 06:49:22.013360 ==
5041 06:49:22.016357 Dram Type= 6, Freq= 0, CH_0, rank 0
5042 06:49:22.019412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5043 06:49:22.019518 ==
5044 06:49:22.025975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5045 06:49:22.032567 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5046 06:49:22.036014 [CA 0] Center 38 (7~69) winsize 63
5047 06:49:22.039448 [CA 1] Center 38 (8~69) winsize 62
5048 06:49:22.042684 [CA 2] Center 35 (5~66) winsize 62
5049 06:49:22.046199 [CA 3] Center 35 (5~65) winsize 61
5050 06:49:22.049241 [CA 4] Center 34 (4~65) winsize 62
5051 06:49:22.049314 [CA 5] Center 33 (3~64) winsize 62
5052 06:49:22.052860
5053 06:49:22.055997 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5054 06:49:22.056073
5055 06:49:22.059604 [CATrainingPosCal] consider 1 rank data
5056 06:49:22.062867 u2DelayCellTimex100 = 270/100 ps
5057 06:49:22.066290 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5058 06:49:22.069573 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5059 06:49:22.072907 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5060 06:49:22.076611 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5061 06:49:22.079687 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5062 06:49:22.082559 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5063 06:49:22.082631
5064 06:49:22.085906 CA PerBit enable=1, Macro0, CA PI delay=33
5065 06:49:22.086044
5066 06:49:22.089476 [CBTSetCACLKResult] CA Dly = 33
5067 06:49:22.092706 CS Dly: 7 (0~38)
5068 06:49:22.092779 ==
5069 06:49:22.095756 Dram Type= 6, Freq= 0, CH_0, rank 1
5070 06:49:22.099240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5071 06:49:22.099312 ==
5072 06:49:22.106126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5073 06:49:22.112390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5074 06:49:22.115773 [CA 0] Center 38 (8~69) winsize 62
5075 06:49:22.119616 [CA 1] Center 38 (8~68) winsize 61
5076 06:49:22.122330 [CA 2] Center 36 (6~66) winsize 61
5077 06:49:22.125916 [CA 3] Center 35 (5~66) winsize 62
5078 06:49:22.129037 [CA 4] Center 34 (4~65) winsize 62
5079 06:49:22.132501 [CA 5] Center 34 (4~64) winsize 61
5080 06:49:22.132599
5081 06:49:22.135997 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5082 06:49:22.136072
5083 06:49:22.139329 [CATrainingPosCal] consider 2 rank data
5084 06:49:22.142147 u2DelayCellTimex100 = 270/100 ps
5085 06:49:22.145679 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5086 06:49:22.148926 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5087 06:49:22.152605 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5088 06:49:22.155513 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5089 06:49:22.159079 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5090 06:49:22.162457 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5091 06:49:22.162528
5092 06:49:22.168894 CA PerBit enable=1, Macro0, CA PI delay=34
5093 06:49:22.168967
5094 06:49:22.169032 [CBTSetCACLKResult] CA Dly = 34
5095 06:49:22.172423 CS Dly: 8 (0~40)
5096 06:49:22.172519
5097 06:49:22.175834 ----->DramcWriteLeveling(PI) begin...
5098 06:49:22.175910 ==
5099 06:49:22.178790 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 06:49:22.182585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 06:49:22.182683 ==
5102 06:49:22.185532 Write leveling (Byte 0): 34 => 34
5103 06:49:22.189127 Write leveling (Byte 1): 27 => 27
5104 06:49:22.192559 DramcWriteLeveling(PI) end<-----
5105 06:49:22.192658
5106 06:49:22.192747 ==
5107 06:49:22.195405 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 06:49:22.198913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 06:49:22.201829 ==
5110 06:49:22.201929 [Gating] SW mode calibration
5111 06:49:22.212150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5112 06:49:22.215173 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5113 06:49:22.218834 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5114 06:49:22.225123 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 06:49:22.228547 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 06:49:22.231658 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 06:49:22.238668 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 06:49:22.241776 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 06:49:22.244788 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5120 06:49:22.251889 0 14 28 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
5121 06:49:22.255256 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5122 06:49:22.258244 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 06:49:22.265264 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 06:49:22.268231 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 06:49:22.271980 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 06:49:22.278597 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 06:49:22.281374 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5128 06:49:22.284915 0 15 28 | B1->B0 | 2828 4545 | 1 0 | (0 0) (0 0)
5129 06:49:22.291582 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5130 06:49:22.294836 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 06:49:22.298305 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 06:49:22.304973 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 06:49:22.307781 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 06:49:22.311353 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 06:49:22.317822 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5136 06:49:22.321077 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5137 06:49:22.324556 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 06:49:22.330953 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 06:49:22.334782 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 06:49:22.337818 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 06:49:22.344363 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 06:49:22.347649 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 06:49:22.351163 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 06:49:22.357717 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 06:49:22.361064 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 06:49:22.364545 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 06:49:22.370643 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 06:49:22.374362 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 06:49:22.377274 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 06:49:22.384073 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 06:49:22.387516 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5152 06:49:22.391213 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5153 06:49:22.394269 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 06:49:22.397645 Total UI for P1: 0, mck2ui 16
5155 06:49:22.400866 best dqsien dly found for B0: ( 1, 2, 26)
5156 06:49:22.404032 Total UI for P1: 0, mck2ui 16
5157 06:49:22.407606 best dqsien dly found for B1: ( 1, 2, 28)
5158 06:49:22.411131 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5159 06:49:22.414150 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5160 06:49:22.417801
5161 06:49:22.421214 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5162 06:49:22.424228 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5163 06:49:22.427748 [Gating] SW calibration Done
5164 06:49:22.427978 ==
5165 06:49:22.431107 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 06:49:22.434409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 06:49:22.434686 ==
5168 06:49:22.434963 RX Vref Scan: 0
5169 06:49:22.435282
5170 06:49:22.437882 RX Vref 0 -> 0, step: 1
5171 06:49:22.438302
5172 06:49:22.441396 RX Delay -80 -> 252, step: 8
5173 06:49:22.444579 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5174 06:49:22.447871 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5175 06:49:22.454448 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5176 06:49:22.457752 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5177 06:49:22.461207 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5178 06:49:22.464346 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5179 06:49:22.467513 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5180 06:49:22.470935 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5181 06:49:22.477845 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5182 06:49:22.480986 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5183 06:49:22.484257 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5184 06:49:22.487733 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5185 06:49:22.491316 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5186 06:49:22.494654 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5187 06:49:22.500940 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5188 06:49:22.504240 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5189 06:49:22.504821 ==
5190 06:49:22.507426 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 06:49:22.510807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 06:49:22.511237 ==
5193 06:49:22.514001 DQS Delay:
5194 06:49:22.514421 DQS0 = 0, DQS1 = 0
5195 06:49:22.514837 DQM Delay:
5196 06:49:22.517310 DQM0 = 106, DQM1 = 91
5197 06:49:22.517730 DQ Delay:
5198 06:49:22.520690 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5199 06:49:22.524367 DQ4 =107, DQ5 =99, DQ6 =119, DQ7 =115
5200 06:49:22.527748 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5201 06:49:22.530760 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5202 06:49:22.531227
5203 06:49:22.531596
5204 06:49:22.531944 ==
5205 06:49:22.534083 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 06:49:22.540956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 06:49:22.541425 ==
5208 06:49:22.541799
5209 06:49:22.542177
5210 06:49:22.542514 TX Vref Scan disable
5211 06:49:22.544640 == TX Byte 0 ==
5212 06:49:22.547846 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5213 06:49:22.551325 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5214 06:49:22.554533 == TX Byte 1 ==
5215 06:49:22.557881 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5216 06:49:22.564428 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5217 06:49:22.564854 ==
5218 06:49:22.567864 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 06:49:22.570959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 06:49:22.571385 ==
5221 06:49:22.571717
5222 06:49:22.572024
5223 06:49:22.574524 TX Vref Scan disable
5224 06:49:22.574946 == TX Byte 0 ==
5225 06:49:22.580962 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5226 06:49:22.584172 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5227 06:49:22.584595 == TX Byte 1 ==
5228 06:49:22.590762 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5229 06:49:22.594238 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5230 06:49:22.594661
5231 06:49:22.594992 [DATLAT]
5232 06:49:22.597496 Freq=933, CH0 RK0
5233 06:49:22.597916
5234 06:49:22.598295 DATLAT Default: 0xd
5235 06:49:22.601072 0, 0xFFFF, sum = 0
5236 06:49:22.601501 1, 0xFFFF, sum = 0
5237 06:49:22.603953 2, 0xFFFF, sum = 0
5238 06:49:22.607592 3, 0xFFFF, sum = 0
5239 06:49:22.608057 4, 0xFFFF, sum = 0
5240 06:49:22.610775 5, 0xFFFF, sum = 0
5241 06:49:22.611247 6, 0xFFFF, sum = 0
5242 06:49:22.614154 7, 0xFFFF, sum = 0
5243 06:49:22.614586 8, 0xFFFF, sum = 0
5244 06:49:22.617403 9, 0xFFFF, sum = 0
5245 06:49:22.617852 10, 0x0, sum = 1
5246 06:49:22.620920 11, 0x0, sum = 2
5247 06:49:22.621351 12, 0x0, sum = 3
5248 06:49:22.621696 13, 0x0, sum = 4
5249 06:49:22.623931 best_step = 11
5250 06:49:22.624356
5251 06:49:22.624691 ==
5252 06:49:22.627440 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 06:49:22.630638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 06:49:22.631098 ==
5255 06:49:22.634205 RX Vref Scan: 1
5256 06:49:22.634630
5257 06:49:22.637536 RX Vref 0 -> 0, step: 1
5258 06:49:22.637996
5259 06:49:22.638343 RX Delay -53 -> 252, step: 4
5260 06:49:22.638661
5261 06:49:22.640914 Set Vref, RX VrefLevel [Byte0]: 56
5262 06:49:22.643947 [Byte1]: 49
5263 06:49:22.648341
5264 06:49:22.648763 Final RX Vref Byte 0 = 56 to rank0
5265 06:49:22.651897 Final RX Vref Byte 1 = 49 to rank0
5266 06:49:22.654878 Final RX Vref Byte 0 = 56 to rank1
5267 06:49:22.658499 Final RX Vref Byte 1 = 49 to rank1==
5268 06:49:22.661811 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 06:49:22.668558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 06:49:22.669032 ==
5271 06:49:22.669409 DQS Delay:
5272 06:49:22.669761 DQS0 = 0, DQS1 = 0
5273 06:49:22.671924 DQM Delay:
5274 06:49:22.672374 DQM0 = 107, DQM1 = 93
5275 06:49:22.674883 DQ Delay:
5276 06:49:22.678464 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5277 06:49:22.681844 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5278 06:49:22.685134 DQ8 =88, DQ9 =78, DQ10 =92, DQ11 =90
5279 06:49:22.688320 DQ12 =96, DQ13 =94, DQ14 =106, DQ15 =100
5280 06:49:22.688742
5281 06:49:22.689071
5282 06:49:22.694944 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
5283 06:49:22.698558 CH0 RK0: MR19=505, MR18=241F
5284 06:49:22.705223 CH0_RK0: MR19=0x505, MR18=0x241F, DQSOSC=410, MR23=63, INC=64, DEC=42
5285 06:49:22.705702
5286 06:49:22.708376 ----->DramcWriteLeveling(PI) begin...
5287 06:49:22.708811 ==
5288 06:49:22.711494 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 06:49:22.714716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 06:49:22.715147 ==
5291 06:49:22.718155 Write leveling (Byte 0): 34 => 34
5292 06:49:22.721496 Write leveling (Byte 1): 30 => 30
5293 06:49:22.724797 DramcWriteLeveling(PI) end<-----
5294 06:49:22.725224
5295 06:49:22.725562 ==
5296 06:49:22.728367 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 06:49:22.731487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 06:49:22.734864 ==
5299 06:49:22.735281 [Gating] SW mode calibration
5300 06:49:22.744890 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5301 06:49:22.748086 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5302 06:49:22.751339 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 06:49:22.758094 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 06:49:22.761273 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 06:49:22.764743 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 06:49:22.771488 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 06:49:22.774774 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 06:49:22.778139 0 14 24 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
5309 06:49:22.784595 0 14 28 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (1 0)
5310 06:49:22.787870 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 06:49:22.791107 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 06:49:22.797968 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 06:49:22.801150 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 06:49:22.804817 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 06:49:22.811327 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 06:49:22.814342 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5317 06:49:22.817875 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5318 06:49:22.824488 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 06:49:22.828129 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 06:49:22.831082 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 06:49:22.834727 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 06:49:22.841333 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 06:49:22.844546 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 06:49:22.847877 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 06:49:22.854827 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 06:49:22.858048 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 06:49:22.861356 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 06:49:22.868043 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 06:49:22.871064 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 06:49:22.874694 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 06:49:22.881222 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 06:49:22.884701 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 06:49:22.887864 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 06:49:22.894529 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 06:49:22.898353 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 06:49:22.901276 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 06:49:22.907868 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 06:49:22.910959 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 06:49:22.914613 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 06:49:22.920712 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 06:49:22.924807 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 06:49:22.927389 Total UI for P1: 0, mck2ui 16
5343 06:49:22.931187 best dqsien dly found for B0: ( 1, 2, 26)
5344 06:49:22.934039 Total UI for P1: 0, mck2ui 16
5345 06:49:22.937773 best dqsien dly found for B1: ( 1, 2, 26)
5346 06:49:22.940901 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5347 06:49:22.944038 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5348 06:49:22.944623
5349 06:49:22.947495 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5350 06:49:22.950843 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5351 06:49:22.954239 [Gating] SW calibration Done
5352 06:49:22.954683 ==
5353 06:49:22.957767 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 06:49:22.960616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 06:49:22.964582 ==
5356 06:49:22.965026 RX Vref Scan: 0
5357 06:49:22.965465
5358 06:49:22.967478 RX Vref 0 -> 0, step: 1
5359 06:49:22.967935
5360 06:49:22.968432 RX Delay -80 -> 252, step: 8
5361 06:49:22.974013 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5362 06:49:22.977460 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5363 06:49:22.981023 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5364 06:49:22.984188 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5365 06:49:22.987551 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5366 06:49:22.991101 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5367 06:49:22.997764 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5368 06:49:23.001124 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5369 06:49:23.004343 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5370 06:49:23.007400 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5371 06:49:23.010923 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5372 06:49:23.014184 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5373 06:49:23.020834 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5374 06:49:23.024239 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5375 06:49:23.027661 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5376 06:49:23.030743 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5377 06:49:23.031286 ==
5378 06:49:23.034164 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 06:49:23.037435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 06:49:23.040796 ==
5381 06:49:23.041306 DQS Delay:
5382 06:49:23.041865 DQS0 = 0, DQS1 = 0
5383 06:49:23.044207 DQM Delay:
5384 06:49:23.044705 DQM0 = 104, DQM1 = 90
5385 06:49:23.047698 DQ Delay:
5386 06:49:23.050880 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5387 06:49:23.054331 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5388 06:49:23.057339 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5389 06:49:23.061307 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5390 06:49:23.061912
5391 06:49:23.062491
5392 06:49:23.063025 ==
5393 06:49:23.064321 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 06:49:23.067802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 06:49:23.068425 ==
5396 06:49:23.068991
5397 06:49:23.069507
5398 06:49:23.070966 TX Vref Scan disable
5399 06:49:23.071516 == TX Byte 0 ==
5400 06:49:23.077679 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5401 06:49:23.081070 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5402 06:49:23.081521 == TX Byte 1 ==
5403 06:49:23.087695 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5404 06:49:23.091056 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5405 06:49:23.091500 ==
5406 06:49:23.094398 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 06:49:23.097642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 06:49:23.098240 ==
5409 06:49:23.098621
5410 06:49:23.099144
5411 06:49:23.101093 TX Vref Scan disable
5412 06:49:23.104343 == TX Byte 0 ==
5413 06:49:23.107607 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5414 06:49:23.110652 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5415 06:49:23.114576 == TX Byte 1 ==
5416 06:49:23.117724 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5417 06:49:23.120812 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5418 06:49:23.121254
5419 06:49:23.123937 [DATLAT]
5420 06:49:23.124375 Freq=933, CH0 RK1
5421 06:49:23.124754
5422 06:49:23.127396 DATLAT Default: 0xb
5423 06:49:23.127838 0, 0xFFFF, sum = 0
5424 06:49:23.130708 1, 0xFFFF, sum = 0
5425 06:49:23.131174 2, 0xFFFF, sum = 0
5426 06:49:23.133969 3, 0xFFFF, sum = 0
5427 06:49:23.134436 4, 0xFFFF, sum = 0
5428 06:49:23.137141 5, 0xFFFF, sum = 0
5429 06:49:23.137609 6, 0xFFFF, sum = 0
5430 06:49:23.140580 7, 0xFFFF, sum = 0
5431 06:49:23.144057 8, 0xFFFF, sum = 0
5432 06:49:23.144524 9, 0xFFFF, sum = 0
5433 06:49:23.145043 10, 0x0, sum = 1
5434 06:49:23.147442 11, 0x0, sum = 2
5435 06:49:23.148020 12, 0x0, sum = 3
5436 06:49:23.150324 13, 0x0, sum = 4
5437 06:49:23.150828 best_step = 11
5438 06:49:23.151271
5439 06:49:23.151675 ==
5440 06:49:23.153631 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 06:49:23.160655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 06:49:23.161227 ==
5443 06:49:23.161598 RX Vref Scan: 0
5444 06:49:23.162105
5445 06:49:23.163624 RX Vref 0 -> 0, step: 1
5446 06:49:23.164065
5447 06:49:23.166817 RX Delay -53 -> 252, step: 4
5448 06:49:23.170156 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5449 06:49:23.176991 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5450 06:49:23.180285 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5451 06:49:23.183664 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5452 06:49:23.186999 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5453 06:49:23.190185 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5454 06:49:23.196562 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5455 06:49:23.199923 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5456 06:49:23.203602 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5457 06:49:23.206727 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5458 06:49:23.209752 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5459 06:49:23.213380 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5460 06:49:23.220140 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5461 06:49:23.223265 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5462 06:49:23.226684 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5463 06:49:23.229835 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5464 06:49:23.230359 ==
5465 06:49:23.233368 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 06:49:23.239866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 06:49:23.240320 ==
5468 06:49:23.240685 DQS Delay:
5469 06:49:23.241026 DQS0 = 0, DQS1 = 0
5470 06:49:23.243179 DQM Delay:
5471 06:49:23.243617 DQM0 = 103, DQM1 = 92
5472 06:49:23.246425 DQ Delay:
5473 06:49:23.249666 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5474 06:49:23.253133 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5475 06:49:23.256133 DQ8 =84, DQ9 =80, DQ10 =92, DQ11 =90
5476 06:49:23.259616 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =98
5477 06:49:23.260192
5478 06:49:23.260646
5479 06:49:23.266491 [DQSOSCAuto] RK1, (LSB)MR18= 0x2809, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5480 06:49:23.269589 CH0 RK1: MR19=505, MR18=2809
5481 06:49:23.276309 CH0_RK1: MR19=0x505, MR18=0x2809, DQSOSC=409, MR23=63, INC=64, DEC=43
5482 06:49:23.279537 [RxdqsGatingPostProcess] freq 933
5483 06:49:23.285882 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5484 06:49:23.286364 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 06:49:23.289414 best DQS1 dly(2T, 0.5T) = (0, 10)
5486 06:49:23.292671 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 06:49:23.295847 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5488 06:49:23.299478 best DQS0 dly(2T, 0.5T) = (0, 10)
5489 06:49:23.302975 best DQS1 dly(2T, 0.5T) = (0, 10)
5490 06:49:23.305838 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5491 06:49:23.309330 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5492 06:49:23.312722 Pre-setting of DQS Precalculation
5493 06:49:23.319354 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5494 06:49:23.319801 ==
5495 06:49:23.322731 Dram Type= 6, Freq= 0, CH_1, rank 0
5496 06:49:23.325675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 06:49:23.326212 ==
5498 06:49:23.332522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5499 06:49:23.335725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5500 06:49:23.340087 [CA 0] Center 37 (7~68) winsize 62
5501 06:49:23.343050 [CA 1] Center 38 (8~68) winsize 61
5502 06:49:23.346545 [CA 2] Center 36 (6~66) winsize 61
5503 06:49:23.349671 [CA 3] Center 34 (4~65) winsize 62
5504 06:49:23.353110 [CA 4] Center 35 (5~66) winsize 62
5505 06:49:23.356456 [CA 5] Center 34 (4~64) winsize 61
5506 06:49:23.356912
5507 06:49:23.359885 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5508 06:49:23.360349
5509 06:49:23.363039 [CATrainingPosCal] consider 1 rank data
5510 06:49:23.366602 u2DelayCellTimex100 = 270/100 ps
5511 06:49:23.369996 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5512 06:49:23.373124 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5513 06:49:23.379495 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5514 06:49:23.383266 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5515 06:49:23.386535 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5516 06:49:23.389433 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5517 06:49:23.389996
5518 06:49:23.392953 CA PerBit enable=1, Macro0, CA PI delay=34
5519 06:49:23.393489
5520 06:49:23.396130 [CBTSetCACLKResult] CA Dly = 34
5521 06:49:23.396697 CS Dly: 6 (0~37)
5522 06:49:23.399437 ==
5523 06:49:23.402666 Dram Type= 6, Freq= 0, CH_1, rank 1
5524 06:49:23.405994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 06:49:23.406438 ==
5526 06:49:23.409617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5527 06:49:23.416271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5528 06:49:23.419552 [CA 0] Center 38 (7~69) winsize 63
5529 06:49:23.422837 [CA 1] Center 38 (7~69) winsize 63
5530 06:49:23.426268 [CA 2] Center 36 (6~66) winsize 61
5531 06:49:23.429717 [CA 3] Center 35 (6~65) winsize 60
5532 06:49:23.432856 [CA 4] Center 36 (6~66) winsize 61
5533 06:49:23.436148 [CA 5] Center 35 (5~65) winsize 61
5534 06:49:23.436658
5535 06:49:23.439601 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5536 06:49:23.440119
5537 06:49:23.443094 [CATrainingPosCal] consider 2 rank data
5538 06:49:23.446313 u2DelayCellTimex100 = 270/100 ps
5539 06:49:23.449650 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5540 06:49:23.452948 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5541 06:49:23.459750 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5542 06:49:23.462990 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5543 06:49:23.466734 CA4 delay=36 (6~66),Diff = 2 PI (12 cell)
5544 06:49:23.469698 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5545 06:49:23.470164
5546 06:49:23.472935 CA PerBit enable=1, Macro0, CA PI delay=34
5547 06:49:23.473378
5548 06:49:23.476131 [CBTSetCACLKResult] CA Dly = 34
5549 06:49:23.476571 CS Dly: 7 (0~39)
5550 06:49:23.476930
5551 06:49:23.479715 ----->DramcWriteLeveling(PI) begin...
5552 06:49:23.483273 ==
5553 06:49:23.486323 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 06:49:23.489555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 06:49:23.490017 ==
5556 06:49:23.493196 Write leveling (Byte 0): 24 => 24
5557 06:49:23.496389 Write leveling (Byte 1): 29 => 29
5558 06:49:23.499422 DramcWriteLeveling(PI) end<-----
5559 06:49:23.499877
5560 06:49:23.500239 ==
5561 06:49:23.502984 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 06:49:23.506347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 06:49:23.506801 ==
5564 06:49:23.509532 [Gating] SW mode calibration
5565 06:49:23.516439 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5566 06:49:23.522839 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5567 06:49:23.526256 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 06:49:23.529814 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 06:49:23.533142 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 06:49:23.539474 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 06:49:23.543052 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 06:49:23.546180 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 06:49:23.553033 0 14 24 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 0)
5574 06:49:23.556328 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5575 06:49:23.559490 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 06:49:23.566322 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 06:49:23.569591 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 06:49:23.573324 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 06:49:23.579544 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 06:49:23.583248 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 06:49:23.586224 0 15 24 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (0 0)
5582 06:49:23.592802 0 15 28 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5583 06:49:23.596071 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 06:49:23.599729 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 06:49:23.605998 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 06:49:23.609204 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 06:49:23.613150 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 06:49:23.619446 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 06:49:23.622498 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5590 06:49:23.626280 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5591 06:49:23.632780 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 06:49:23.636087 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 06:49:23.639482 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 06:49:23.646049 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 06:49:23.649191 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 06:49:23.652527 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 06:49:23.656154 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 06:49:23.662373 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 06:49:23.665897 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 06:49:23.669503 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 06:49:23.676010 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 06:49:23.679267 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 06:49:23.682233 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 06:49:23.688970 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5605 06:49:23.692629 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5606 06:49:23.695819 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5607 06:49:23.702427 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 06:49:23.705914 Total UI for P1: 0, mck2ui 16
5609 06:49:23.708973 best dqsien dly found for B0: ( 1, 2, 24)
5610 06:49:23.709425 Total UI for P1: 0, mck2ui 16
5611 06:49:23.715578 best dqsien dly found for B1: ( 1, 2, 28)
5612 06:49:23.719166 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5613 06:49:23.722780 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5614 06:49:23.723203
5615 06:49:23.725732 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5616 06:49:23.729163 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5617 06:49:23.732485 [Gating] SW calibration Done
5618 06:49:23.733031 ==
5619 06:49:23.735708 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 06:49:23.739340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 06:49:23.739809 ==
5622 06:49:23.742531 RX Vref Scan: 0
5623 06:49:23.742996
5624 06:49:23.743365 RX Vref 0 -> 0, step: 1
5625 06:49:23.743707
5626 06:49:23.745644 RX Delay -80 -> 252, step: 8
5627 06:49:23.749230 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5628 06:49:23.756019 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5629 06:49:23.758938 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5630 06:49:23.762183 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5631 06:49:23.765726 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5632 06:49:23.769204 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5633 06:49:23.775729 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5634 06:49:23.778834 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5635 06:49:23.782701 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5636 06:49:23.785482 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5637 06:49:23.789332 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5638 06:49:23.792568 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5639 06:49:23.798932 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5640 06:49:23.802506 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5641 06:49:23.805592 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5642 06:49:23.809152 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5643 06:49:23.809572 ==
5644 06:49:23.812474 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 06:49:23.815721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 06:49:23.818712 ==
5647 06:49:23.819181 DQS Delay:
5648 06:49:23.819550 DQS0 = 0, DQS1 = 0
5649 06:49:23.822451 DQM Delay:
5650 06:49:23.822871 DQM0 = 103, DQM1 = 95
5651 06:49:23.825471 DQ Delay:
5652 06:49:23.828710 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =103
5653 06:49:23.832330 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5654 06:49:23.835539 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5655 06:49:23.838964 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5656 06:49:23.839472
5657 06:49:23.839810
5658 06:49:23.840121 ==
5659 06:49:23.842305 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 06:49:23.845521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 06:49:23.845978 ==
5662 06:49:23.846325
5663 06:49:23.846643
5664 06:49:23.848761 TX Vref Scan disable
5665 06:49:23.852289 == TX Byte 0 ==
5666 06:49:23.855385 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5667 06:49:23.858895 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5668 06:49:23.861879 == TX Byte 1 ==
5669 06:49:23.865456 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5670 06:49:23.868877 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5671 06:49:23.869302 ==
5672 06:49:23.872220 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 06:49:23.875555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 06:49:23.875979 ==
5675 06:49:23.878566
5676 06:49:23.878987
5677 06:49:23.879322 TX Vref Scan disable
5678 06:49:23.882056 == TX Byte 0 ==
5679 06:49:23.885490 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5680 06:49:23.891768 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5681 06:49:23.892190 == TX Byte 1 ==
5682 06:49:23.895128 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5683 06:49:23.902278 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5684 06:49:23.902705
5685 06:49:23.903039 [DATLAT]
5686 06:49:23.903368 Freq=933, CH1 RK0
5687 06:49:23.903709
5688 06:49:23.905316 DATLAT Default: 0xd
5689 06:49:23.905736 0, 0xFFFF, sum = 0
5690 06:49:23.908662 1, 0xFFFF, sum = 0
5691 06:49:23.909087 2, 0xFFFF, sum = 0
5692 06:49:23.912066 3, 0xFFFF, sum = 0
5693 06:49:23.915234 4, 0xFFFF, sum = 0
5694 06:49:23.915857 5, 0xFFFF, sum = 0
5695 06:49:23.918667 6, 0xFFFF, sum = 0
5696 06:49:23.919220 7, 0xFFFF, sum = 0
5697 06:49:23.921811 8, 0xFFFF, sum = 0
5698 06:49:23.922471 9, 0xFFFF, sum = 0
5699 06:49:23.925054 10, 0x0, sum = 1
5700 06:49:23.925525 11, 0x0, sum = 2
5701 06:49:23.928704 12, 0x0, sum = 3
5702 06:49:23.929177 13, 0x0, sum = 4
5703 06:49:23.929569 best_step = 11
5704 06:49:23.929920
5705 06:49:23.932387 ==
5706 06:49:23.935198 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 06:49:23.938612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 06:49:23.939147 ==
5709 06:49:23.939588 RX Vref Scan: 1
5710 06:49:23.939995
5711 06:49:23.941650 RX Vref 0 -> 0, step: 1
5712 06:49:23.942179
5713 06:49:23.944879 RX Delay -53 -> 252, step: 4
5714 06:49:23.945389
5715 06:49:23.948356 Set Vref, RX VrefLevel [Byte0]: 52
5716 06:49:23.951724 [Byte1]: 57
5717 06:49:23.952214
5718 06:49:23.954909 Final RX Vref Byte 0 = 52 to rank0
5719 06:49:23.958334 Final RX Vref Byte 1 = 57 to rank0
5720 06:49:23.963254 Final RX Vref Byte 0 = 52 to rank1
5721 06:49:23.965293 Final RX Vref Byte 1 = 57 to rank1==
5722 06:49:23.968006 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 06:49:23.971583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 06:49:23.974872 ==
5725 06:49:23.975076 DQS Delay:
5726 06:49:23.975225 DQS0 = 0, DQS1 = 0
5727 06:49:23.977882 DQM Delay:
5728 06:49:23.978152 DQM0 = 104, DQM1 = 98
5729 06:49:23.981479 DQ Delay:
5730 06:49:23.984794 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5731 06:49:23.988175 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =102
5732 06:49:23.991273 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =92
5733 06:49:23.994768 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =104
5734 06:49:23.994895
5735 06:49:23.994978
5736 06:49:24.000953 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5737 06:49:24.004663 CH1 RK0: MR19=505, MR18=1C34
5738 06:49:24.011207 CH1_RK0: MR19=0x505, MR18=0x1C34, DQSOSC=405, MR23=63, INC=66, DEC=44
5739 06:49:24.011293
5740 06:49:24.014543 ----->DramcWriteLeveling(PI) begin...
5741 06:49:24.014634 ==
5742 06:49:24.017566 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 06:49:24.021523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 06:49:24.021640 ==
5745 06:49:24.024503 Write leveling (Byte 0): 27 => 27
5746 06:49:24.027651 Write leveling (Byte 1): 28 => 28
5747 06:49:24.030923 DramcWriteLeveling(PI) end<-----
5748 06:49:24.031000
5749 06:49:24.031070 ==
5750 06:49:24.034478 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 06:49:24.037548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 06:49:24.040912 ==
5753 06:49:24.040989 [Gating] SW mode calibration
5754 06:49:24.047990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5755 06:49:24.054787 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5756 06:49:24.058226 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 06:49:24.064571 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 06:49:24.068002 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 06:49:24.071175 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 06:49:24.077755 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 06:49:24.081039 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5762 06:49:24.084303 0 14 24 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
5763 06:49:24.091133 0 14 28 | B1->B0 | 2525 2d2d | 0 1 | (0 0) (1 0)
5764 06:49:24.094364 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 06:49:24.097816 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 06:49:24.101378 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 06:49:24.107496 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 06:49:24.110822 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 06:49:24.114409 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 06:49:24.120814 0 15 24 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (0 0)
5771 06:49:24.124015 0 15 28 | B1->B0 | 4444 3b3b | 0 0 | (0 0) (0 0)
5772 06:49:24.127859 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 06:49:24.133915 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 06:49:24.137346 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 06:49:24.141162 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 06:49:24.147333 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 06:49:24.150725 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 06:49:24.153908 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5779 06:49:24.160805 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5780 06:49:24.164120 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 06:49:24.167458 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 06:49:24.174703 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 06:49:24.177585 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 06:49:24.180833 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 06:49:24.187272 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 06:49:24.190680 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 06:49:24.193821 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 06:49:24.200741 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 06:49:24.204063 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 06:49:24.207164 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 06:49:24.214190 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 06:49:24.217132 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 06:49:24.220762 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 06:49:24.227186 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5795 06:49:24.230714 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5796 06:49:24.233880 Total UI for P1: 0, mck2ui 16
5797 06:49:24.237130 best dqsien dly found for B1: ( 1, 2, 24)
5798 06:49:24.240366 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 06:49:24.243885 Total UI for P1: 0, mck2ui 16
5800 06:49:24.247476 best dqsien dly found for B0: ( 1, 2, 28)
5801 06:49:24.250633 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5802 06:49:24.253862 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5803 06:49:24.253974
5804 06:49:24.257542 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5805 06:49:24.260428 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5806 06:49:24.263956 [Gating] SW calibration Done
5807 06:49:24.264038 ==
5808 06:49:24.267234 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 06:49:24.273772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 06:49:24.273855 ==
5811 06:49:24.273957 RX Vref Scan: 0
5812 06:49:24.274033
5813 06:49:24.277444 RX Vref 0 -> 0, step: 1
5814 06:49:24.277526
5815 06:49:24.280196 RX Delay -80 -> 252, step: 8
5816 06:49:24.283644 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5817 06:49:24.286933 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5818 06:49:24.290326 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5819 06:49:24.293771 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5820 06:49:24.300420 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5821 06:49:24.303689 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5822 06:49:24.306737 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5823 06:49:24.310120 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5824 06:49:24.313515 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5825 06:49:24.320377 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5826 06:49:24.323501 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5827 06:49:24.327223 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5828 06:49:24.330217 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5829 06:49:24.333617 iDelay=200, Bit 13, Center 107 (16 ~ 199) 184
5830 06:49:24.336889 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5831 06:49:24.343807 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5832 06:49:24.343889 ==
5833 06:49:24.347051 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 06:49:24.350298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 06:49:24.350380 ==
5836 06:49:24.350446 DQS Delay:
5837 06:49:24.353946 DQS0 = 0, DQS1 = 0
5838 06:49:24.354029 DQM Delay:
5839 06:49:24.357016 DQM0 = 102, DQM1 = 97
5840 06:49:24.357098 DQ Delay:
5841 06:49:24.360641 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5842 06:49:24.363593 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =103
5843 06:49:24.367246 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5844 06:49:24.370195 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5845 06:49:24.370277
5846 06:49:24.370342
5847 06:49:24.370402 ==
5848 06:49:24.373387 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 06:49:24.380481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 06:49:24.380564 ==
5851 06:49:24.380629
5852 06:49:24.380689
5853 06:49:24.380747 TX Vref Scan disable
5854 06:49:24.384023 == TX Byte 0 ==
5855 06:49:24.387151 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5856 06:49:24.393789 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5857 06:49:24.393872 == TX Byte 1 ==
5858 06:49:24.397155 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5859 06:49:24.400483 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5860 06:49:24.403981 ==
5861 06:49:24.407210 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 06:49:24.410364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 06:49:24.410447 ==
5864 06:49:24.410513
5865 06:49:24.410572
5866 06:49:24.414034 TX Vref Scan disable
5867 06:49:24.414120 == TX Byte 0 ==
5868 06:49:24.420286 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5869 06:49:24.423864 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5870 06:49:24.423946 == TX Byte 1 ==
5871 06:49:24.430353 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5872 06:49:24.433468 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5873 06:49:24.433551
5874 06:49:24.433617 [DATLAT]
5875 06:49:24.437056 Freq=933, CH1 RK1
5876 06:49:24.437139
5877 06:49:24.437204 DATLAT Default: 0xb
5878 06:49:24.440728 0, 0xFFFF, sum = 0
5879 06:49:24.440813 1, 0xFFFF, sum = 0
5880 06:49:24.443940 2, 0xFFFF, sum = 0
5881 06:49:24.444023 3, 0xFFFF, sum = 0
5882 06:49:24.447016 4, 0xFFFF, sum = 0
5883 06:49:24.447099 5, 0xFFFF, sum = 0
5884 06:49:24.450322 6, 0xFFFF, sum = 0
5885 06:49:24.453815 7, 0xFFFF, sum = 0
5886 06:49:24.453905 8, 0xFFFF, sum = 0
5887 06:49:24.456890 9, 0xFFFF, sum = 0
5888 06:49:24.456977 10, 0x0, sum = 1
5889 06:49:24.457063 11, 0x0, sum = 2
5890 06:49:24.460360 12, 0x0, sum = 3
5891 06:49:24.460446 13, 0x0, sum = 4
5892 06:49:24.463721 best_step = 11
5893 06:49:24.463806
5894 06:49:24.463891 ==
5895 06:49:24.466701 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 06:49:24.470509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 06:49:24.470595 ==
5898 06:49:24.473334 RX Vref Scan: 0
5899 06:49:24.473418
5900 06:49:24.473502 RX Vref 0 -> 0, step: 1
5901 06:49:24.476646
5902 06:49:24.476731 RX Delay -53 -> 252, step: 4
5903 06:49:24.484211 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5904 06:49:24.487698 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5905 06:49:24.490686 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5906 06:49:24.493890 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5907 06:49:24.497611 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5908 06:49:24.504426 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5909 06:49:24.507741 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5910 06:49:24.511108 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5911 06:49:24.514253 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5912 06:49:24.517437 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5913 06:49:24.520909 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5914 06:49:24.527736 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5915 06:49:24.530753 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5916 06:49:24.534309 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5917 06:49:24.537347 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5918 06:49:24.544135 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5919 06:49:24.544222 ==
5920 06:49:24.547237 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 06:49:24.550811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 06:49:24.550897 ==
5923 06:49:24.550983 DQS Delay:
5924 06:49:24.554093 DQS0 = 0, DQS1 = 0
5925 06:49:24.554177 DQM Delay:
5926 06:49:24.557554 DQM0 = 104, DQM1 = 97
5927 06:49:24.557639 DQ Delay:
5928 06:49:24.560702 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =102
5929 06:49:24.564168 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5930 06:49:24.567340 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =92
5931 06:49:24.570664 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =106
5932 06:49:24.570749
5933 06:49:24.570834
5934 06:49:24.580515 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5935 06:49:24.580602 CH1 RK1: MR19=504, MR18=20FC
5936 06:49:24.587946 CH1_RK1: MR19=0x504, MR18=0x20FC, DQSOSC=411, MR23=63, INC=64, DEC=42
5937 06:49:24.590463 [RxdqsGatingPostProcess] freq 933
5938 06:49:24.597401 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5939 06:49:24.600518 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 06:49:24.603847 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 06:49:24.607166 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 06:49:24.610719 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 06:49:24.613784 best DQS0 dly(2T, 0.5T) = (0, 10)
5944 06:49:24.613894 best DQS1 dly(2T, 0.5T) = (0, 10)
5945 06:49:24.616982 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5946 06:49:24.620612 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5947 06:49:24.623705 Pre-setting of DQS Precalculation
5948 06:49:24.630487 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5949 06:49:24.637446 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5950 06:49:24.643748 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5951 06:49:24.643832
5952 06:49:24.643898
5953 06:49:24.647388 [Calibration Summary] 1866 Mbps
5954 06:49:24.650472 CH 0, Rank 0
5955 06:49:24.650555 SW Impedance : PASS
5956 06:49:24.653867 DUTY Scan : NO K
5957 06:49:24.653995 ZQ Calibration : PASS
5958 06:49:24.657213 Jitter Meter : NO K
5959 06:49:24.660538 CBT Training : PASS
5960 06:49:24.660621 Write leveling : PASS
5961 06:49:24.664108 RX DQS gating : PASS
5962 06:49:24.667461 RX DQ/DQS(RDDQC) : PASS
5963 06:49:24.667545 TX DQ/DQS : PASS
5964 06:49:24.670247 RX DATLAT : PASS
5965 06:49:24.673720 RX DQ/DQS(Engine): PASS
5966 06:49:24.673804 TX OE : NO K
5967 06:49:24.677149 All Pass.
5968 06:49:24.677232
5969 06:49:24.677298 CH 0, Rank 1
5970 06:49:24.680695 SW Impedance : PASS
5971 06:49:24.680779 DUTY Scan : NO K
5972 06:49:24.684098 ZQ Calibration : PASS
5973 06:49:24.687013 Jitter Meter : NO K
5974 06:49:24.687097 CBT Training : PASS
5975 06:49:24.690231 Write leveling : PASS
5976 06:49:24.693874 RX DQS gating : PASS
5977 06:49:24.694016 RX DQ/DQS(RDDQC) : PASS
5978 06:49:24.696806 TX DQ/DQS : PASS
5979 06:49:24.696890 RX DATLAT : PASS
5980 06:49:24.700395 RX DQ/DQS(Engine): PASS
5981 06:49:24.703530 TX OE : NO K
5982 06:49:24.703614 All Pass.
5983 06:49:24.703680
5984 06:49:24.703741 CH 1, Rank 0
5985 06:49:24.707072 SW Impedance : PASS
5986 06:49:24.710414 DUTY Scan : NO K
5987 06:49:24.710498 ZQ Calibration : PASS
5988 06:49:24.713499 Jitter Meter : NO K
5989 06:49:24.716869 CBT Training : PASS
5990 06:49:24.716953 Write leveling : PASS
5991 06:49:24.720083 RX DQS gating : PASS
5992 06:49:24.723267 RX DQ/DQS(RDDQC) : PASS
5993 06:49:24.723351 TX DQ/DQS : PASS
5994 06:49:24.726696 RX DATLAT : PASS
5995 06:49:24.730182 RX DQ/DQS(Engine): PASS
5996 06:49:24.730266 TX OE : NO K
5997 06:49:24.733333 All Pass.
5998 06:49:24.733417
5999 06:49:24.733483 CH 1, Rank 1
6000 06:49:24.736855 SW Impedance : PASS
6001 06:49:24.736939 DUTY Scan : NO K
6002 06:49:24.740278 ZQ Calibration : PASS
6003 06:49:24.743235 Jitter Meter : NO K
6004 06:49:24.743319 CBT Training : PASS
6005 06:49:24.747074 Write leveling : PASS
6006 06:49:24.750045 RX DQS gating : PASS
6007 06:49:24.750129 RX DQ/DQS(RDDQC) : PASS
6008 06:49:24.753417 TX DQ/DQS : PASS
6009 06:49:24.756492 RX DATLAT : PASS
6010 06:49:24.756577 RX DQ/DQS(Engine): PASS
6011 06:49:24.759724 TX OE : NO K
6012 06:49:24.759808 All Pass.
6013 06:49:24.759875
6014 06:49:24.763212 DramC Write-DBI off
6015 06:49:24.766896 PER_BANK_REFRESH: Hybrid Mode
6016 06:49:24.766981 TX_TRACKING: ON
6017 06:49:24.776299 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6018 06:49:24.779938 [FAST_K] Save calibration result to emmc
6019 06:49:24.783354 dramc_set_vcore_voltage set vcore to 650000
6020 06:49:24.783438 Read voltage for 400, 6
6021 06:49:24.786404 Vio18 = 0
6022 06:49:24.786488 Vcore = 650000
6023 06:49:24.786555 Vdram = 0
6024 06:49:24.790093 Vddq = 0
6025 06:49:24.790177 Vmddr = 0
6026 06:49:24.796604 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6027 06:49:24.799922 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6028 06:49:24.803189 MEM_TYPE=3, freq_sel=20
6029 06:49:24.806302 sv_algorithm_assistance_LP4_800
6030 06:49:24.809773 ============ PULL DRAM RESETB DOWN ============
6031 06:49:24.813033 ========== PULL DRAM RESETB DOWN end =========
6032 06:49:24.819693 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6033 06:49:24.822820 ===================================
6034 06:49:24.822904 LPDDR4 DRAM CONFIGURATION
6035 06:49:24.826084 ===================================
6036 06:49:24.829738 EX_ROW_EN[0] = 0x0
6037 06:49:24.829821 EX_ROW_EN[1] = 0x0
6038 06:49:24.833036 LP4Y_EN = 0x0
6039 06:49:24.836295 WORK_FSP = 0x0
6040 06:49:24.836379 WL = 0x2
6041 06:49:24.839372 RL = 0x2
6042 06:49:24.839455 BL = 0x2
6043 06:49:24.842969 RPST = 0x0
6044 06:49:24.843052 RD_PRE = 0x0
6045 06:49:24.846206 WR_PRE = 0x1
6046 06:49:24.846290 WR_PST = 0x0
6047 06:49:24.849539 DBI_WR = 0x0
6048 06:49:24.849623 DBI_RD = 0x0
6049 06:49:24.853095 OTF = 0x1
6050 06:49:24.856219 ===================================
6051 06:49:24.859557 ===================================
6052 06:49:24.859671 ANA top config
6053 06:49:24.862833 ===================================
6054 06:49:24.865957 DLL_ASYNC_EN = 0
6055 06:49:24.869466 ALL_SLAVE_EN = 1
6056 06:49:24.869549 NEW_RANK_MODE = 1
6057 06:49:24.873048 DLL_IDLE_MODE = 1
6058 06:49:24.876187 LP45_APHY_COMB_EN = 1
6059 06:49:24.879341 TX_ODT_DIS = 1
6060 06:49:24.882844 NEW_8X_MODE = 1
6061 06:49:24.886429 ===================================
6062 06:49:24.889516 ===================================
6063 06:49:24.889600 data_rate = 800
6064 06:49:24.892974 CKR = 1
6065 06:49:24.896299 DQ_P2S_RATIO = 4
6066 06:49:24.899512 ===================================
6067 06:49:24.902620 CA_P2S_RATIO = 4
6068 06:49:24.906058 DQ_CA_OPEN = 0
6069 06:49:24.909419 DQ_SEMI_OPEN = 1
6070 06:49:24.909503 CA_SEMI_OPEN = 1
6071 06:49:24.912609 CA_FULL_RATE = 0
6072 06:49:24.916010 DQ_CKDIV4_EN = 0
6073 06:49:24.919338 CA_CKDIV4_EN = 1
6074 06:49:24.922533 CA_PREDIV_EN = 0
6075 06:49:24.925916 PH8_DLY = 0
6076 06:49:24.926021 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6077 06:49:24.929257 DQ_AAMCK_DIV = 0
6078 06:49:24.932654 CA_AAMCK_DIV = 0
6079 06:49:24.935992 CA_ADMCK_DIV = 4
6080 06:49:24.939346 DQ_TRACK_CA_EN = 0
6081 06:49:24.942820 CA_PICK = 800
6082 06:49:24.942894 CA_MCKIO = 400
6083 06:49:24.946060 MCKIO_SEMI = 400
6084 06:49:24.949227 PLL_FREQ = 3016
6085 06:49:24.953067 DQ_UI_PI_RATIO = 32
6086 06:49:24.955954 CA_UI_PI_RATIO = 32
6087 06:49:24.959510 ===================================
6088 06:49:24.962707 ===================================
6089 06:49:24.966336 memory_type:LPDDR4
6090 06:49:24.966405 GP_NUM : 10
6091 06:49:24.969149 SRAM_EN : 1
6092 06:49:24.969216 MD32_EN : 0
6093 06:49:24.972834 ===================================
6094 06:49:24.975983 [ANA_INIT] >>>>>>>>>>>>>>
6095 06:49:24.979261 <<<<<< [CONFIGURE PHASE]: ANA_TX
6096 06:49:24.982793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6097 06:49:24.985682 ===================================
6098 06:49:24.989144 data_rate = 800,PCW = 0X7400
6099 06:49:24.992654 ===================================
6100 06:49:24.995658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6101 06:49:25.002455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6102 06:49:25.012117 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6103 06:49:25.015309 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6104 06:49:25.018633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6105 06:49:25.025514 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6106 06:49:25.025599 [ANA_INIT] flow start
6107 06:49:25.028854 [ANA_INIT] PLL >>>>>>>>
6108 06:49:25.031926 [ANA_INIT] PLL <<<<<<<<
6109 06:49:25.032010 [ANA_INIT] MIDPI >>>>>>>>
6110 06:49:25.035420 [ANA_INIT] MIDPI <<<<<<<<
6111 06:49:25.039074 [ANA_INIT] DLL >>>>>>>>
6112 06:49:25.039158 [ANA_INIT] flow end
6113 06:49:25.041743 ============ LP4 DIFF to SE enter ============
6114 06:49:25.048450 ============ LP4 DIFF to SE exit ============
6115 06:49:25.048534 [ANA_INIT] <<<<<<<<<<<<<
6116 06:49:25.051921 [Flow] Enable top DCM control >>>>>
6117 06:49:25.055140 [Flow] Enable top DCM control <<<<<
6118 06:49:25.058353 Enable DLL master slave shuffle
6119 06:49:25.064840 ==============================================================
6120 06:49:25.068364 Gating Mode config
6121 06:49:25.071675 ==============================================================
6122 06:49:25.074646 Config description:
6123 06:49:25.084951 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6124 06:49:25.091541 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6125 06:49:25.094767 SELPH_MODE 0: By rank 1: By Phase
6126 06:49:25.101826 ==============================================================
6127 06:49:25.105055 GAT_TRACK_EN = 0
6128 06:49:25.108003 RX_GATING_MODE = 2
6129 06:49:25.111234 RX_GATING_TRACK_MODE = 2
6130 06:49:25.111318 SELPH_MODE = 1
6131 06:49:25.114608 PICG_EARLY_EN = 1
6132 06:49:25.118104 VALID_LAT_VALUE = 1
6133 06:49:25.124653 ==============================================================
6134 06:49:25.127752 Enter into Gating configuration >>>>
6135 06:49:25.131190 Exit from Gating configuration <<<<
6136 06:49:25.134517 Enter into DVFS_PRE_config >>>>>
6137 06:49:25.144452 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6138 06:49:25.147727 Exit from DVFS_PRE_config <<<<<
6139 06:49:25.151140 Enter into PICG configuration >>>>
6140 06:49:25.154368 Exit from PICG configuration <<<<
6141 06:49:25.157672 [RX_INPUT] configuration >>>>>
6142 06:49:25.161150 [RX_INPUT] configuration <<<<<
6143 06:49:25.164462 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6144 06:49:25.171186 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6145 06:49:25.177529 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6146 06:49:25.184383 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6147 06:49:25.190943 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6148 06:49:25.194309 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6149 06:49:25.201267 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6150 06:49:25.203974 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6151 06:49:25.207441 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6152 06:49:25.210824 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6153 06:49:25.214558 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6154 06:49:25.220919 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6155 06:49:25.224039 ===================================
6156 06:49:25.227461 LPDDR4 DRAM CONFIGURATION
6157 06:49:25.230866 ===================================
6158 06:49:25.230947 EX_ROW_EN[0] = 0x0
6159 06:49:25.234324 EX_ROW_EN[1] = 0x0
6160 06:49:25.234403 LP4Y_EN = 0x0
6161 06:49:25.237367 WORK_FSP = 0x0
6162 06:49:25.237442 WL = 0x2
6163 06:49:25.240614 RL = 0x2
6164 06:49:25.240692 BL = 0x2
6165 06:49:25.243874 RPST = 0x0
6166 06:49:25.243952 RD_PRE = 0x0
6167 06:49:25.247479 WR_PRE = 0x1
6168 06:49:25.247550 WR_PST = 0x0
6169 06:49:25.250457 DBI_WR = 0x0
6170 06:49:25.250528 DBI_RD = 0x0
6171 06:49:25.253733 OTF = 0x1
6172 06:49:25.257149 ===================================
6173 06:49:25.260381 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6174 06:49:25.263691 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6175 06:49:25.270407 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6176 06:49:25.274147 ===================================
6177 06:49:25.274225 LPDDR4 DRAM CONFIGURATION
6178 06:49:25.277206 ===================================
6179 06:49:25.280912 EX_ROW_EN[0] = 0x10
6180 06:49:25.284120 EX_ROW_EN[1] = 0x0
6181 06:49:25.284192 LP4Y_EN = 0x0
6182 06:49:25.287346 WORK_FSP = 0x0
6183 06:49:25.287418 WL = 0x2
6184 06:49:25.290418 RL = 0x2
6185 06:49:25.290490 BL = 0x2
6186 06:49:25.293691 RPST = 0x0
6187 06:49:25.293762 RD_PRE = 0x0
6188 06:49:25.297480 WR_PRE = 0x1
6189 06:49:25.297558 WR_PST = 0x0
6190 06:49:25.300240 DBI_WR = 0x0
6191 06:49:25.300328 DBI_RD = 0x0
6192 06:49:25.303791 OTF = 0x1
6193 06:49:25.307065 ===================================
6194 06:49:25.313588 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6195 06:49:25.317118 nWR fixed to 30
6196 06:49:25.320367 [ModeRegInit_LP4] CH0 RK0
6197 06:49:25.320452 [ModeRegInit_LP4] CH0 RK1
6198 06:49:25.323820 [ModeRegInit_LP4] CH1 RK0
6199 06:49:25.326817 [ModeRegInit_LP4] CH1 RK1
6200 06:49:25.326900 match AC timing 19
6201 06:49:25.333644 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6202 06:49:25.336893 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6203 06:49:25.340178 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6204 06:49:25.346859 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6205 06:49:25.350174 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6206 06:49:25.350253 ==
6207 06:49:25.353571 Dram Type= 6, Freq= 0, CH_0, rank 0
6208 06:49:25.357191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6209 06:49:25.357265 ==
6210 06:49:25.363325 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6211 06:49:25.370020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6212 06:49:25.374094 [CA 0] Center 36 (8~64) winsize 57
6213 06:49:25.376881 [CA 1] Center 36 (8~64) winsize 57
6214 06:49:25.376954 [CA 2] Center 36 (8~64) winsize 57
6215 06:49:25.380103 [CA 3] Center 36 (8~64) winsize 57
6216 06:49:25.383675 [CA 4] Center 36 (8~64) winsize 57
6217 06:49:25.386766 [CA 5] Center 36 (8~64) winsize 57
6218 06:49:25.386840
6219 06:49:25.389890 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6220 06:49:25.390030
6221 06:49:25.396964 [CATrainingPosCal] consider 1 rank data
6222 06:49:25.397057 u2DelayCellTimex100 = 270/100 ps
6223 06:49:25.403264 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 06:49:25.406612 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 06:49:25.410305 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 06:49:25.413656 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 06:49:25.416689 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 06:49:25.420032 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 06:49:25.420124
6230 06:49:25.423107 CA PerBit enable=1, Macro0, CA PI delay=36
6231 06:49:25.423195
6232 06:49:25.426604 [CBTSetCACLKResult] CA Dly = 36
6233 06:49:25.429965 CS Dly: 1 (0~32)
6234 06:49:25.430059 ==
6235 06:49:25.433190 Dram Type= 6, Freq= 0, CH_0, rank 1
6236 06:49:25.436449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 06:49:25.436553 ==
6238 06:49:25.443288 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6239 06:49:25.446422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6240 06:49:25.449788 [CA 0] Center 36 (8~64) winsize 57
6241 06:49:25.453136 [CA 1] Center 36 (8~64) winsize 57
6242 06:49:25.456635 [CA 2] Center 36 (8~64) winsize 57
6243 06:49:25.459786 [CA 3] Center 36 (8~64) winsize 57
6244 06:49:25.463114 [CA 4] Center 36 (8~64) winsize 57
6245 06:49:25.466776 [CA 5] Center 36 (8~64) winsize 57
6246 06:49:25.466873
6247 06:49:25.469875 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6248 06:49:25.469989
6249 06:49:25.472952 [CATrainingPosCal] consider 2 rank data
6250 06:49:25.476382 u2DelayCellTimex100 = 270/100 ps
6251 06:49:25.479756 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 06:49:25.482910 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 06:49:25.486376 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 06:49:25.492763 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 06:49:25.496208 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 06:49:25.499637 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 06:49:25.499741
6258 06:49:25.502897 CA PerBit enable=1, Macro0, CA PI delay=36
6259 06:49:25.502999
6260 06:49:25.506588 [CBTSetCACLKResult] CA Dly = 36
6261 06:49:25.506680 CS Dly: 1 (0~32)
6262 06:49:25.506748
6263 06:49:25.509311 ----->DramcWriteLeveling(PI) begin...
6264 06:49:25.509417 ==
6265 06:49:25.513312 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 06:49:25.519519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 06:49:25.519611 ==
6268 06:49:25.522590 Write leveling (Byte 0): 40 => 8
6269 06:49:25.526115 Write leveling (Byte 1): 32 => 0
6270 06:49:25.526192 DramcWriteLeveling(PI) end<-----
6271 06:49:25.526255
6272 06:49:25.529566 ==
6273 06:49:25.529665 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 06:49:25.536176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 06:49:25.536278 ==
6276 06:49:25.539267 [Gating] SW mode calibration
6277 06:49:25.546036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6278 06:49:25.549266 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6279 06:49:25.556294 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6280 06:49:25.559449 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6281 06:49:25.562703 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 06:49:25.569329 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 06:49:25.572900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 06:49:25.576031 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 06:49:25.582705 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 06:49:25.585823 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 06:49:25.589084 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 06:49:25.592559 Total UI for P1: 0, mck2ui 16
6289 06:49:25.596182 best dqsien dly found for B0: ( 0, 14, 24)
6290 06:49:25.599223 Total UI for P1: 0, mck2ui 16
6291 06:49:25.602981 best dqsien dly found for B1: ( 0, 14, 24)
6292 06:49:25.606070 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6293 06:49:25.609517 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6294 06:49:25.609593
6295 06:49:25.612858 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6296 06:49:25.619709 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6297 06:49:25.619818 [Gating] SW calibration Done
6298 06:49:25.619914 ==
6299 06:49:25.622859 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 06:49:25.629767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 06:49:25.629876 ==
6302 06:49:25.629991 RX Vref Scan: 0
6303 06:49:25.630067
6304 06:49:25.632697 RX Vref 0 -> 0, step: 1
6305 06:49:25.632792
6306 06:49:25.636144 RX Delay -410 -> 252, step: 16
6307 06:49:25.639291 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6308 06:49:25.643016 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6309 06:49:25.649606 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6310 06:49:25.652670 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6311 06:49:25.655937 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6312 06:49:25.659362 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6313 06:49:25.666166 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6314 06:49:25.668896 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6315 06:49:25.672209 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6316 06:49:25.675635 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6317 06:49:25.682510 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6318 06:49:25.685559 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6319 06:49:25.688878 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6320 06:49:25.692490 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6321 06:49:25.699009 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6322 06:49:25.702380 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6323 06:49:25.702463 ==
6324 06:49:25.705380 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 06:49:25.708562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 06:49:25.708645 ==
6327 06:49:25.712308 DQS Delay:
6328 06:49:25.712389 DQS0 = 27, DQS1 = 35
6329 06:49:25.715377 DQM Delay:
6330 06:49:25.715459 DQM0 = 13, DQM1 = 6
6331 06:49:25.715541 DQ Delay:
6332 06:49:25.718836 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6333 06:49:25.722088 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6334 06:49:25.725277 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6335 06:49:25.728949 DQ12 =8, DQ13 =8, DQ14 =16, DQ15 =8
6336 06:49:25.729026
6337 06:49:25.729089
6338 06:49:25.729148 ==
6339 06:49:25.732334 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 06:49:25.735245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 06:49:25.738710 ==
6342 06:49:25.738783
6343 06:49:25.738844
6344 06:49:25.738903 TX Vref Scan disable
6345 06:49:25.742213 == TX Byte 0 ==
6346 06:49:25.745546 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 06:49:25.748863 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 06:49:25.751837 == TX Byte 1 ==
6349 06:49:25.755431 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6350 06:49:25.758487 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6351 06:49:25.758564 ==
6352 06:49:25.761713 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 06:49:25.768311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 06:49:25.768416 ==
6355 06:49:25.768507
6356 06:49:25.768598
6357 06:49:25.768685 TX Vref Scan disable
6358 06:49:25.771998 == TX Byte 0 ==
6359 06:49:25.775130 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 06:49:25.778536 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 06:49:25.781880 == TX Byte 1 ==
6362 06:49:25.785156 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6363 06:49:25.788331 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6364 06:49:25.788406
6365 06:49:25.791770 [DATLAT]
6366 06:49:25.791873 Freq=400, CH0 RK0
6367 06:49:25.791965
6368 06:49:25.795004 DATLAT Default: 0xf
6369 06:49:25.795078 0, 0xFFFF, sum = 0
6370 06:49:25.798564 1, 0xFFFF, sum = 0
6371 06:49:25.798637 2, 0xFFFF, sum = 0
6372 06:49:25.801934 3, 0xFFFF, sum = 0
6373 06:49:25.802068 4, 0xFFFF, sum = 0
6374 06:49:25.805117 5, 0xFFFF, sum = 0
6375 06:49:25.805189 6, 0xFFFF, sum = 0
6376 06:49:25.808209 7, 0xFFFF, sum = 0
6377 06:49:25.808279 8, 0xFFFF, sum = 0
6378 06:49:25.811777 9, 0xFFFF, sum = 0
6379 06:49:25.811848 10, 0xFFFF, sum = 0
6380 06:49:25.814984 11, 0xFFFF, sum = 0
6381 06:49:25.818300 12, 0xFFFF, sum = 0
6382 06:49:25.818406 13, 0x0, sum = 1
6383 06:49:25.821489 14, 0x0, sum = 2
6384 06:49:25.821591 15, 0x0, sum = 3
6385 06:49:25.821684 16, 0x0, sum = 4
6386 06:49:25.825066 best_step = 14
6387 06:49:25.825137
6388 06:49:25.825205 ==
6389 06:49:25.828276 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 06:49:25.831791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 06:49:25.831888 ==
6392 06:49:25.834790 RX Vref Scan: 1
6393 06:49:25.834860
6394 06:49:25.834922 RX Vref 0 -> 0, step: 1
6395 06:49:25.838457
6396 06:49:25.838525 RX Delay -311 -> 252, step: 8
6397 06:49:25.838593
6398 06:49:25.841751 Set Vref, RX VrefLevel [Byte0]: 56
6399 06:49:25.844777 [Byte1]: 49
6400 06:49:25.850321
6401 06:49:25.850393 Final RX Vref Byte 0 = 56 to rank0
6402 06:49:25.853310 Final RX Vref Byte 1 = 49 to rank0
6403 06:49:25.856705 Final RX Vref Byte 0 = 56 to rank1
6404 06:49:25.859717 Final RX Vref Byte 1 = 49 to rank1==
6405 06:49:25.863214 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 06:49:25.869928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 06:49:25.870077 ==
6408 06:49:25.870170 DQS Delay:
6409 06:49:25.873107 DQS0 = 28, DQS1 = 48
6410 06:49:25.873205 DQM Delay:
6411 06:49:25.873294 DQM0 = 12, DQM1 = 15
6412 06:49:25.876607 DQ Delay:
6413 06:49:25.879759 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =12
6414 06:49:25.883289 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6415 06:49:25.883388 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6416 06:49:25.886520 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6417 06:49:25.889849
6418 06:49:25.889975
6419 06:49:25.896840 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
6420 06:49:25.899798 CH0 RK0: MR19=C0C, MR18=B0A7
6421 06:49:25.906784 CH0_RK0: MR19=0xC0C, MR18=0xB0A7, DQSOSC=387, MR23=63, INC=394, DEC=262
6422 06:49:25.906871 ==
6423 06:49:25.909870 Dram Type= 6, Freq= 0, CH_0, rank 1
6424 06:49:25.913343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 06:49:25.913418 ==
6426 06:49:25.916742 [Gating] SW mode calibration
6427 06:49:25.923168 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6428 06:49:25.930063 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6429 06:49:25.933164 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 06:49:25.936987 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 06:49:25.942954 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 06:49:25.946467 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 06:49:25.949771 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 06:49:25.953044 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 06:49:25.960210 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 06:49:25.963115 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 06:49:25.966761 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 06:49:25.969749 Total UI for P1: 0, mck2ui 16
6439 06:49:25.972919 best dqsien dly found for B0: ( 0, 14, 24)
6440 06:49:25.976621 Total UI for P1: 0, mck2ui 16
6441 06:49:25.979740 best dqsien dly found for B1: ( 0, 14, 24)
6442 06:49:25.983021 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6443 06:49:25.989627 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6444 06:49:25.989762
6445 06:49:25.993281 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6446 06:49:25.996286 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6447 06:49:25.999733 [Gating] SW calibration Done
6448 06:49:25.999820 ==
6449 06:49:26.003157 Dram Type= 6, Freq= 0, CH_0, rank 1
6450 06:49:26.006338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 06:49:26.006453 ==
6452 06:49:26.009618 RX Vref Scan: 0
6453 06:49:26.009692
6454 06:49:26.009769 RX Vref 0 -> 0, step: 1
6455 06:49:26.009856
6456 06:49:26.013188 RX Delay -410 -> 252, step: 16
6457 06:49:26.016731 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6458 06:49:26.022698 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6459 06:49:26.026392 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6460 06:49:26.029838 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6461 06:49:26.033067 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6462 06:49:26.039615 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6463 06:49:26.043029 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6464 06:49:26.046211 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6465 06:49:26.049291 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6466 06:49:26.056243 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6467 06:49:26.059458 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6468 06:49:26.062534 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6469 06:49:26.065916 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6470 06:49:26.072683 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6471 06:49:26.075858 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6472 06:49:26.079595 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6473 06:49:26.079669 ==
6474 06:49:26.082723 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 06:49:26.089263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 06:49:26.089341 ==
6477 06:49:26.089408 DQS Delay:
6478 06:49:26.092506 DQS0 = 27, DQS1 = 43
6479 06:49:26.092583 DQM Delay:
6480 06:49:26.092656 DQM0 = 9, DQM1 = 16
6481 06:49:26.096039 DQ Delay:
6482 06:49:26.099267 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6483 06:49:26.099340 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6484 06:49:26.102679 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6485 06:49:26.106138 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6486 06:49:26.106215
6487 06:49:26.106279
6488 06:49:26.109133 ==
6489 06:49:26.112624 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 06:49:26.115821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 06:49:26.115924 ==
6492 06:49:26.116016
6493 06:49:26.116106
6494 06:49:26.119155 TX Vref Scan disable
6495 06:49:26.119228 == TX Byte 0 ==
6496 06:49:26.122295 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6497 06:49:26.129044 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6498 06:49:26.129151 == TX Byte 1 ==
6499 06:49:26.132412 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6500 06:49:26.138937 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6501 06:49:26.139044 ==
6502 06:49:26.142823 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 06:49:26.145805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 06:49:26.145888 ==
6505 06:49:26.145993
6506 06:49:26.146079
6507 06:49:26.148931 TX Vref Scan disable
6508 06:49:26.149030 == TX Byte 0 ==
6509 06:49:26.152515 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6510 06:49:26.158953 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6511 06:49:26.159054 == TX Byte 1 ==
6512 06:49:26.162308 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6513 06:49:26.168861 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6514 06:49:26.168940
6515 06:49:26.169005 [DATLAT]
6516 06:49:26.169071 Freq=400, CH0 RK1
6517 06:49:26.169133
6518 06:49:26.172265 DATLAT Default: 0xe
6519 06:49:26.172366 0, 0xFFFF, sum = 0
6520 06:49:26.175388 1, 0xFFFF, sum = 0
6521 06:49:26.178822 2, 0xFFFF, sum = 0
6522 06:49:26.178926 3, 0xFFFF, sum = 0
6523 06:49:26.182177 4, 0xFFFF, sum = 0
6524 06:49:26.182284 5, 0xFFFF, sum = 0
6525 06:49:26.185763 6, 0xFFFF, sum = 0
6526 06:49:26.185840 7, 0xFFFF, sum = 0
6527 06:49:26.188915 8, 0xFFFF, sum = 0
6528 06:49:26.189016 9, 0xFFFF, sum = 0
6529 06:49:26.192266 10, 0xFFFF, sum = 0
6530 06:49:26.192369 11, 0xFFFF, sum = 0
6531 06:49:26.195288 12, 0xFFFF, sum = 0
6532 06:49:26.195369 13, 0x0, sum = 1
6533 06:49:26.199044 14, 0x0, sum = 2
6534 06:49:26.199118 15, 0x0, sum = 3
6535 06:49:26.202209 16, 0x0, sum = 4
6536 06:49:26.202311 best_step = 14
6537 06:49:26.202401
6538 06:49:26.202491 ==
6539 06:49:26.205435 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 06:49:26.208685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 06:49:26.212025 ==
6542 06:49:26.212100 RX Vref Scan: 0
6543 06:49:26.212171
6544 06:49:26.215403 RX Vref 0 -> 0, step: 1
6545 06:49:26.215482
6546 06:49:26.218458 RX Delay -327 -> 252, step: 8
6547 06:49:26.222705 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6548 06:49:26.228647 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6549 06:49:26.231806 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6550 06:49:26.235586 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6551 06:49:26.238541 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6552 06:49:26.245115 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6553 06:49:26.248822 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6554 06:49:26.252041 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6555 06:49:26.255228 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6556 06:49:26.261833 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6557 06:49:26.264949 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6558 06:49:26.268551 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6559 06:49:26.271736 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6560 06:49:26.278674 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6561 06:49:26.281543 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6562 06:49:26.284955 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6563 06:49:26.285043 ==
6564 06:49:26.288271 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 06:49:26.294992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 06:49:26.295085 ==
6567 06:49:26.295153 DQS Delay:
6568 06:49:26.298201 DQS0 = 28, DQS1 = 40
6569 06:49:26.298316 DQM Delay:
6570 06:49:26.298384 DQM0 = 11, DQM1 = 12
6571 06:49:26.301489 DQ Delay:
6572 06:49:26.305367 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6573 06:49:26.308197 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6574 06:49:26.308344 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6575 06:49:26.311811 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6576 06:49:26.314970
6577 06:49:26.315055
6578 06:49:26.321374 [DQSOSCAuto] RK1, (LSB)MR18= 0xb669, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6579 06:49:26.324756 CH0 RK1: MR19=C0C, MR18=B669
6580 06:49:26.331338 CH0_RK1: MR19=0xC0C, MR18=0xB669, DQSOSC=387, MR23=63, INC=394, DEC=262
6581 06:49:26.334805 [RxdqsGatingPostProcess] freq 400
6582 06:49:26.338405 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6583 06:49:26.341460 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 06:49:26.344786 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 06:49:26.347930 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 06:49:26.351328 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 06:49:26.354660 best DQS0 dly(2T, 0.5T) = (0, 10)
6588 06:49:26.358263 best DQS1 dly(2T, 0.5T) = (0, 10)
6589 06:49:26.361415 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6590 06:49:26.364493 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6591 06:49:26.367902 Pre-setting of DQS Precalculation
6592 06:49:26.371193 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6593 06:49:26.371278 ==
6594 06:49:26.374891 Dram Type= 6, Freq= 0, CH_1, rank 0
6595 06:49:26.381181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 06:49:26.381268 ==
6597 06:49:26.384794 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6598 06:49:26.391080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6599 06:49:26.394539 [CA 0] Center 36 (8~64) winsize 57
6600 06:49:26.397769 [CA 1] Center 36 (8~64) winsize 57
6601 06:49:26.401080 [CA 2] Center 36 (8~64) winsize 57
6602 06:49:26.404456 [CA 3] Center 36 (8~64) winsize 57
6603 06:49:26.407710 [CA 4] Center 36 (8~64) winsize 57
6604 06:49:26.410829 [CA 5] Center 36 (8~64) winsize 57
6605 06:49:26.410906
6606 06:49:26.414524 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6607 06:49:26.414620
6608 06:49:26.418089 [CATrainingPosCal] consider 1 rank data
6609 06:49:26.421196 u2DelayCellTimex100 = 270/100 ps
6610 06:49:26.424189 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 06:49:26.427535 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 06:49:26.430837 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 06:49:26.434264 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 06:49:26.437801 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 06:49:26.441034 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 06:49:26.441109
6617 06:49:26.448157 CA PerBit enable=1, Macro0, CA PI delay=36
6618 06:49:26.448246
6619 06:49:26.448316 [CBTSetCACLKResult] CA Dly = 36
6620 06:49:26.451437 CS Dly: 1 (0~32)
6621 06:49:26.451530 ==
6622 06:49:26.454403 Dram Type= 6, Freq= 0, CH_1, rank 1
6623 06:49:26.457999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 06:49:26.458083 ==
6625 06:49:26.464320 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6626 06:49:26.471125 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6627 06:49:26.474593 [CA 0] Center 36 (8~64) winsize 57
6628 06:49:26.478112 [CA 1] Center 36 (8~64) winsize 57
6629 06:49:26.480958 [CA 2] Center 36 (8~64) winsize 57
6630 06:49:26.481044 [CA 3] Center 36 (8~64) winsize 57
6631 06:49:26.484498 [CA 4] Center 36 (8~64) winsize 57
6632 06:49:26.487782 [CA 5] Center 36 (8~64) winsize 57
6633 06:49:26.487866
6634 06:49:26.491593 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6635 06:49:26.494856
6636 06:49:26.497931 [CATrainingPosCal] consider 2 rank data
6637 06:49:26.498060 u2DelayCellTimex100 = 270/100 ps
6638 06:49:26.504574 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 06:49:26.507713 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 06:49:26.511099 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 06:49:26.514416 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 06:49:26.517622 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 06:49:26.521299 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 06:49:26.521415
6645 06:49:26.524650 CA PerBit enable=1, Macro0, CA PI delay=36
6646 06:49:26.524728
6647 06:49:26.527669 [CBTSetCACLKResult] CA Dly = 36
6648 06:49:26.530934 CS Dly: 1 (0~32)
6649 06:49:26.531012
6650 06:49:26.534407 ----->DramcWriteLeveling(PI) begin...
6651 06:49:26.534513 ==
6652 06:49:26.537716 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 06:49:26.541416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 06:49:26.541520 ==
6655 06:49:26.544436 Write leveling (Byte 0): 40 => 8
6656 06:49:26.547548 Write leveling (Byte 1): 32 => 0
6657 06:49:26.551010 DramcWriteLeveling(PI) end<-----
6658 06:49:26.551113
6659 06:49:26.551182 ==
6660 06:49:26.554448 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 06:49:26.557597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 06:49:26.557699 ==
6663 06:49:26.561132 [Gating] SW mode calibration
6664 06:49:26.567608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6665 06:49:26.574495 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6666 06:49:26.577696 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6667 06:49:26.581323 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6668 06:49:26.587631 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 06:49:26.591068 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 06:49:26.594113 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 06:49:26.600879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 06:49:26.604541 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 06:49:26.607433 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 06:49:26.614125 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 06:49:26.614241 Total UI for P1: 0, mck2ui 16
6676 06:49:26.617437 best dqsien dly found for B0: ( 0, 14, 24)
6677 06:49:26.620745 Total UI for P1: 0, mck2ui 16
6678 06:49:26.623913 best dqsien dly found for B1: ( 0, 14, 24)
6679 06:49:26.630860 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6680 06:49:26.634280 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6681 06:49:26.634362
6682 06:49:26.637665 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6683 06:49:26.640655 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6684 06:49:26.643988 [Gating] SW calibration Done
6685 06:49:26.644072 ==
6686 06:49:26.647077 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 06:49:26.650363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 06:49:26.650443 ==
6689 06:49:26.653916 RX Vref Scan: 0
6690 06:49:26.654034
6691 06:49:26.654102 RX Vref 0 -> 0, step: 1
6692 06:49:26.654163
6693 06:49:26.656991 RX Delay -410 -> 252, step: 16
6694 06:49:26.663427 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6695 06:49:26.666888 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6696 06:49:26.670474 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6697 06:49:26.673752 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6698 06:49:26.680357 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6699 06:49:26.683462 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6700 06:49:26.686774 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6701 06:49:26.690063 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6702 06:49:26.696518 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6703 06:49:26.699709 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6704 06:49:26.702927 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6705 06:49:26.706487 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6706 06:49:26.712994 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6707 06:49:26.716516 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6708 06:49:26.719681 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6709 06:49:26.723233 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6710 06:49:26.726027 ==
6711 06:49:26.729583 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 06:49:26.732888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 06:49:26.732968 ==
6714 06:49:26.733035 DQS Delay:
6715 06:49:26.736527 DQS0 = 27, DQS1 = 43
6716 06:49:26.736602 DQM Delay:
6717 06:49:26.739980 DQM0 = 11, DQM1 = 16
6718 06:49:26.740057 DQ Delay:
6719 06:49:26.742890 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6720 06:49:26.746229 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =0
6721 06:49:26.749662 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6722 06:49:26.752992 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6723 06:49:26.753071
6724 06:49:26.753140
6725 06:49:26.753206 ==
6726 06:49:26.756263 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 06:49:26.759686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 06:49:26.759766 ==
6729 06:49:26.759831
6730 06:49:26.759892
6731 06:49:26.762778 TX Vref Scan disable
6732 06:49:26.762851 == TX Byte 0 ==
6733 06:49:26.769406 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 06:49:26.772836 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 06:49:26.772914 == TX Byte 1 ==
6736 06:49:26.779541 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6737 06:49:26.782856 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6738 06:49:26.782940 ==
6739 06:49:26.786025 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 06:49:26.789291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 06:49:26.789371 ==
6742 06:49:26.789435
6743 06:49:26.789497
6744 06:49:26.792715 TX Vref Scan disable
6745 06:49:26.792792 == TX Byte 0 ==
6746 06:49:26.799686 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 06:49:26.802602 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 06:49:26.802682 == TX Byte 1 ==
6749 06:49:26.809634 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6750 06:49:26.812756 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6751 06:49:26.812833
6752 06:49:26.812901 [DATLAT]
6753 06:49:26.816068 Freq=400, CH1 RK0
6754 06:49:26.816158
6755 06:49:26.816263 DATLAT Default: 0xf
6756 06:49:26.819384 0, 0xFFFF, sum = 0
6757 06:49:26.819465 1, 0xFFFF, sum = 0
6758 06:49:26.822892 2, 0xFFFF, sum = 0
6759 06:49:26.822974 3, 0xFFFF, sum = 0
6760 06:49:26.826106 4, 0xFFFF, sum = 0
6761 06:49:26.826186 5, 0xFFFF, sum = 0
6762 06:49:26.829688 6, 0xFFFF, sum = 0
6763 06:49:26.829764 7, 0xFFFF, sum = 0
6764 06:49:26.832773 8, 0xFFFF, sum = 0
6765 06:49:26.832851 9, 0xFFFF, sum = 0
6766 06:49:26.835955 10, 0xFFFF, sum = 0
6767 06:49:26.839851 11, 0xFFFF, sum = 0
6768 06:49:26.839937 12, 0xFFFF, sum = 0
6769 06:49:26.842743 13, 0x0, sum = 1
6770 06:49:26.842821 14, 0x0, sum = 2
6771 06:49:26.846428 15, 0x0, sum = 3
6772 06:49:26.846504 16, 0x0, sum = 4
6773 06:49:26.846568 best_step = 14
6774 06:49:26.846633
6775 06:49:26.849608 ==
6776 06:49:26.852735 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 06:49:26.855932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 06:49:26.856029 ==
6779 06:49:26.856098 RX Vref Scan: 1
6780 06:49:26.856163
6781 06:49:26.859544 RX Vref 0 -> 0, step: 1
6782 06:49:26.859621
6783 06:49:26.862906 RX Delay -327 -> 252, step: 8
6784 06:49:26.862990
6785 06:49:26.866011 Set Vref, RX VrefLevel [Byte0]: 52
6786 06:49:26.869316 [Byte1]: 57
6787 06:49:26.872874
6788 06:49:26.872959 Final RX Vref Byte 0 = 52 to rank0
6789 06:49:26.876097 Final RX Vref Byte 1 = 57 to rank0
6790 06:49:26.879708 Final RX Vref Byte 0 = 52 to rank1
6791 06:49:26.882716 Final RX Vref Byte 1 = 57 to rank1==
6792 06:49:26.886134 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 06:49:26.893021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 06:49:26.893107 ==
6795 06:49:26.893184 DQS Delay:
6796 06:49:26.896170 DQS0 = 32, DQS1 = 44
6797 06:49:26.896247 DQM Delay:
6798 06:49:26.896311 DQM0 = 10, DQM1 = 15
6799 06:49:26.899525 DQ Delay:
6800 06:49:26.902820 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6801 06:49:26.902896 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6802 06:49:26.906024 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6803 06:49:26.909188 DQ12 =28, DQ13 =24, DQ14 =20, DQ15 =20
6804 06:49:26.909264
6805 06:49:26.912683
6806 06:49:26.919708 [DQSOSCAuto] RK0, (LSB)MR18= 0x9cd7, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6807 06:49:26.922665 CH1 RK0: MR19=C0C, MR18=9CD7
6808 06:49:26.929342 CH1_RK0: MR19=0xC0C, MR18=0x9CD7, DQSOSC=383, MR23=63, INC=402, DEC=268
6809 06:49:26.929434 ==
6810 06:49:26.932595 Dram Type= 6, Freq= 0, CH_1, rank 1
6811 06:49:26.936032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 06:49:26.936113 ==
6813 06:49:26.939215 [Gating] SW mode calibration
6814 06:49:26.946016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6815 06:49:26.952763 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6816 06:49:26.955907 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6817 06:49:26.959201 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6818 06:49:26.965551 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 06:49:26.969112 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 06:49:26.972395 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 06:49:26.975879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 06:49:26.982588 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 06:49:26.986043 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 06:49:26.988694 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 06:49:26.992140 Total UI for P1: 0, mck2ui 16
6826 06:49:26.995746 best dqsien dly found for B0: ( 0, 14, 24)
6827 06:49:26.999150 Total UI for P1: 0, mck2ui 16
6828 06:49:27.002411 best dqsien dly found for B1: ( 0, 14, 24)
6829 06:49:27.005812 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6830 06:49:27.012285 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6831 06:49:27.012365
6832 06:49:27.015428 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6833 06:49:27.019364 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6834 06:49:27.022150 [Gating] SW calibration Done
6835 06:49:27.022232 ==
6836 06:49:27.025436 Dram Type= 6, Freq= 0, CH_1, rank 1
6837 06:49:27.029035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 06:49:27.029116 ==
6839 06:49:27.029191 RX Vref Scan: 0
6840 06:49:27.032155
6841 06:49:27.032295 RX Vref 0 -> 0, step: 1
6842 06:49:27.032359
6843 06:49:27.035346 RX Delay -410 -> 252, step: 16
6844 06:49:27.038737 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6845 06:49:27.045206 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6846 06:49:27.048848 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6847 06:49:27.052212 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6848 06:49:27.055802 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6849 06:49:27.062312 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6850 06:49:27.065461 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6851 06:49:27.068977 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6852 06:49:27.072350 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6853 06:49:27.078561 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6854 06:49:27.082153 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6855 06:49:27.085731 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6856 06:49:27.089106 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6857 06:49:27.095936 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6858 06:49:27.098966 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6859 06:49:27.101988 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6860 06:49:27.102074 ==
6861 06:49:27.105328 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 06:49:27.108841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 06:49:27.112422 ==
6864 06:49:27.112523 DQS Delay:
6865 06:49:27.112593 DQS0 = 35, DQS1 = 43
6866 06:49:27.115194 DQM Delay:
6867 06:49:27.115280 DQM0 = 16, DQM1 = 18
6868 06:49:27.118797 DQ Delay:
6869 06:49:27.122311 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6870 06:49:27.122402 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6871 06:49:27.125358 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6872 06:49:27.128902 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6873 06:49:27.132129
6874 06:49:27.132218
6875 06:49:27.132286 ==
6876 06:49:27.135475 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 06:49:27.138575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 06:49:27.138662 ==
6879 06:49:27.138731
6880 06:49:27.138794
6881 06:49:27.141735 TX Vref Scan disable
6882 06:49:27.141820 == TX Byte 0 ==
6883 06:49:27.145240 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6884 06:49:27.151801 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6885 06:49:27.151890 == TX Byte 1 ==
6886 06:49:27.155185 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6887 06:49:27.161839 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6888 06:49:27.161928 ==
6889 06:49:27.165064 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 06:49:27.168582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 06:49:27.168670 ==
6892 06:49:27.168738
6893 06:49:27.168800
6894 06:49:27.171812 TX Vref Scan disable
6895 06:49:27.171898 == TX Byte 0 ==
6896 06:49:27.175184 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6897 06:49:27.181790 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6898 06:49:27.181880 == TX Byte 1 ==
6899 06:49:27.185130 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6900 06:49:27.191391 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6901 06:49:27.191479
6902 06:49:27.191547 [DATLAT]
6903 06:49:27.191611 Freq=400, CH1 RK1
6904 06:49:27.194759
6905 06:49:27.194845 DATLAT Default: 0xe
6906 06:49:27.197982 0, 0xFFFF, sum = 0
6907 06:49:27.198070 1, 0xFFFF, sum = 0
6908 06:49:27.201439 2, 0xFFFF, sum = 0
6909 06:49:27.201526 3, 0xFFFF, sum = 0
6910 06:49:27.205047 4, 0xFFFF, sum = 0
6911 06:49:27.205134 5, 0xFFFF, sum = 0
6912 06:49:27.208285 6, 0xFFFF, sum = 0
6913 06:49:27.208373 7, 0xFFFF, sum = 0
6914 06:49:27.211695 8, 0xFFFF, sum = 0
6915 06:49:27.211785 9, 0xFFFF, sum = 0
6916 06:49:27.214988 10, 0xFFFF, sum = 0
6917 06:49:27.215075 11, 0xFFFF, sum = 0
6918 06:49:27.218394 12, 0xFFFF, sum = 0
6919 06:49:27.218484 13, 0x0, sum = 1
6920 06:49:27.221480 14, 0x0, sum = 2
6921 06:49:27.221566 15, 0x0, sum = 3
6922 06:49:27.224752 16, 0x0, sum = 4
6923 06:49:27.224860 best_step = 14
6924 06:49:27.224966
6925 06:49:27.225032 ==
6926 06:49:27.228089 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 06:49:27.234813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 06:49:27.234934 ==
6929 06:49:27.235032 RX Vref Scan: 0
6930 06:49:27.235123
6931 06:49:27.238227 RX Vref 0 -> 0, step: 1
6932 06:49:27.238303
6933 06:49:27.241630 RX Delay -327 -> 252, step: 8
6934 06:49:27.248294 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6935 06:49:27.251305 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6936 06:49:27.254601 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6937 06:49:27.258026 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6938 06:49:27.264437 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6939 06:49:27.268194 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6940 06:49:27.271477 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6941 06:49:27.274483 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6942 06:49:27.281256 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6943 06:49:27.284422 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6944 06:49:27.287797 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6945 06:49:27.291360 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6946 06:49:27.297617 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6947 06:49:27.301114 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6948 06:49:27.304477 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6949 06:49:27.307933 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6950 06:49:27.311251 ==
6951 06:49:27.311337 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 06:49:27.317889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 06:49:27.317987 ==
6954 06:49:27.318055 DQS Delay:
6955 06:49:27.320993 DQS0 = 32, DQS1 = 36
6956 06:49:27.321127 DQM Delay:
6957 06:49:27.324323 DQM0 = 12, DQM1 = 11
6958 06:49:27.324441 DQ Delay:
6959 06:49:27.327826 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =16
6960 06:49:27.330891 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
6961 06:49:27.334306 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6962 06:49:27.337631 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6963 06:49:27.337738
6964 06:49:27.337830
6965 06:49:27.344350 [DQSOSCAuto] RK1, (LSB)MR18= 0xaa54, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6966 06:49:27.347674 CH1 RK1: MR19=C0C, MR18=AA54
6967 06:49:27.354448 CH1_RK1: MR19=0xC0C, MR18=0xAA54, DQSOSC=388, MR23=63, INC=392, DEC=261
6968 06:49:27.357702 [RxdqsGatingPostProcess] freq 400
6969 06:49:27.360726 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6970 06:49:27.364057 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 06:49:27.367614 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 06:49:27.370788 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 06:49:27.374202 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 06:49:27.377699 best DQS0 dly(2T, 0.5T) = (0, 10)
6975 06:49:27.380980 best DQS1 dly(2T, 0.5T) = (0, 10)
6976 06:49:27.384094 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6977 06:49:27.387613 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6978 06:49:27.390923 Pre-setting of DQS Precalculation
6979 06:49:27.394070 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6980 06:49:27.404442 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6981 06:49:27.411038 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6982 06:49:27.411125
6983 06:49:27.411193
6984 06:49:27.414165 [Calibration Summary] 800 Mbps
6985 06:49:27.414251 CH 0, Rank 0
6986 06:49:27.417569 SW Impedance : PASS
6987 06:49:27.417654 DUTY Scan : NO K
6988 06:49:27.421022 ZQ Calibration : PASS
6989 06:49:27.424091 Jitter Meter : NO K
6990 06:49:27.424169 CBT Training : PASS
6991 06:49:27.427290 Write leveling : PASS
6992 06:49:27.430788 RX DQS gating : PASS
6993 06:49:27.430872 RX DQ/DQS(RDDQC) : PASS
6994 06:49:27.434104 TX DQ/DQS : PASS
6995 06:49:27.434204 RX DATLAT : PASS
6996 06:49:27.437650 RX DQ/DQS(Engine): PASS
6997 06:49:27.440566 TX OE : NO K
6998 06:49:27.440652 All Pass.
6999 06:49:27.440731
7000 06:49:27.440793 CH 0, Rank 1
7001 06:49:27.443862 SW Impedance : PASS
7002 06:49:27.447254 DUTY Scan : NO K
7003 06:49:27.447365 ZQ Calibration : PASS
7004 06:49:27.450896 Jitter Meter : NO K
7005 06:49:27.453868 CBT Training : PASS
7006 06:49:27.453999 Write leveling : NO K
7007 06:49:27.457495 RX DQS gating : PASS
7008 06:49:27.460749 RX DQ/DQS(RDDQC) : PASS
7009 06:49:27.460835 TX DQ/DQS : PASS
7010 06:49:27.464182 RX DATLAT : PASS
7011 06:49:27.467135 RX DQ/DQS(Engine): PASS
7012 06:49:27.467221 TX OE : NO K
7013 06:49:27.470797 All Pass.
7014 06:49:27.470883
7015 06:49:27.470951 CH 1, Rank 0
7016 06:49:27.473893 SW Impedance : PASS
7017 06:49:27.473988 DUTY Scan : NO K
7018 06:49:27.477060 ZQ Calibration : PASS
7019 06:49:27.480771 Jitter Meter : NO K
7020 06:49:27.480860 CBT Training : PASS
7021 06:49:27.483877 Write leveling : PASS
7022 06:49:27.487298 RX DQS gating : PASS
7023 06:49:27.487412 RX DQ/DQS(RDDQC) : PASS
7024 06:49:27.490444 TX DQ/DQS : PASS
7025 06:49:27.490530 RX DATLAT : PASS
7026 06:49:27.493972 RX DQ/DQS(Engine): PASS
7027 06:49:27.497058 TX OE : NO K
7028 06:49:27.497145 All Pass.
7029 06:49:27.497213
7030 06:49:27.497277 CH 1, Rank 1
7031 06:49:27.500324 SW Impedance : PASS
7032 06:49:27.503543 DUTY Scan : NO K
7033 06:49:27.503637 ZQ Calibration : PASS
7034 06:49:27.507054 Jitter Meter : NO K
7035 06:49:27.510544 CBT Training : PASS
7036 06:49:27.510629 Write leveling : NO K
7037 06:49:27.513641 RX DQS gating : PASS
7038 06:49:27.517317 RX DQ/DQS(RDDQC) : PASS
7039 06:49:27.517404 TX DQ/DQS : PASS
7040 06:49:27.520375 RX DATLAT : PASS
7041 06:49:27.523428 RX DQ/DQS(Engine): PASS
7042 06:49:27.523534 TX OE : NO K
7043 06:49:27.527170 All Pass.
7044 06:49:27.527248
7045 06:49:27.527313 DramC Write-DBI off
7046 06:49:27.530497 PER_BANK_REFRESH: Hybrid Mode
7047 06:49:27.530583 TX_TRACKING: ON
7048 06:49:27.540327 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7049 06:49:27.543381 [FAST_K] Save calibration result to emmc
7050 06:49:27.546959 dramc_set_vcore_voltage set vcore to 725000
7051 06:49:27.550150 Read voltage for 1600, 0
7052 06:49:27.550235 Vio18 = 0
7053 06:49:27.553506 Vcore = 725000
7054 06:49:27.553623 Vdram = 0
7055 06:49:27.553717 Vddq = 0
7056 06:49:27.556715 Vmddr = 0
7057 06:49:27.560033 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7058 06:49:27.566634 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7059 06:49:27.566720 MEM_TYPE=3, freq_sel=13
7060 06:49:27.570381 sv_algorithm_assistance_LP4_3733
7061 06:49:27.577044 ============ PULL DRAM RESETB DOWN ============
7062 06:49:27.580328 ========== PULL DRAM RESETB DOWN end =========
7063 06:49:27.583394 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7064 06:49:27.586828 ===================================
7065 06:49:27.590199 LPDDR4 DRAM CONFIGURATION
7066 06:49:27.593432 ===================================
7067 06:49:27.593519 EX_ROW_EN[0] = 0x0
7068 06:49:27.596814 EX_ROW_EN[1] = 0x0
7069 06:49:27.599944 LP4Y_EN = 0x0
7070 06:49:27.600057 WORK_FSP = 0x1
7071 06:49:27.603501 WL = 0x5
7072 06:49:27.603612 RL = 0x5
7073 06:49:27.606475 BL = 0x2
7074 06:49:27.606562 RPST = 0x0
7075 06:49:27.609853 RD_PRE = 0x0
7076 06:49:27.609972 WR_PRE = 0x1
7077 06:49:27.613206 WR_PST = 0x1
7078 06:49:27.613309 DBI_WR = 0x0
7079 06:49:27.616605 DBI_RD = 0x0
7080 06:49:27.616712 OTF = 0x1
7081 06:49:27.619967 ===================================
7082 06:49:27.623100 ===================================
7083 06:49:27.626421 ANA top config
7084 06:49:27.629749 ===================================
7085 06:49:27.629826 DLL_ASYNC_EN = 0
7086 06:49:27.633113 ALL_SLAVE_EN = 0
7087 06:49:27.636460 NEW_RANK_MODE = 1
7088 06:49:27.639444 DLL_IDLE_MODE = 1
7089 06:49:27.643039 LP45_APHY_COMB_EN = 1
7090 06:49:27.643125 TX_ODT_DIS = 0
7091 06:49:27.646217 NEW_8X_MODE = 1
7092 06:49:27.649686 ===================================
7093 06:49:27.652749 ===================================
7094 06:49:27.656266 data_rate = 3200
7095 06:49:27.659539 CKR = 1
7096 06:49:27.662919 DQ_P2S_RATIO = 8
7097 06:49:27.666110 ===================================
7098 06:49:27.669583 CA_P2S_RATIO = 8
7099 06:49:27.669668 DQ_CA_OPEN = 0
7100 06:49:27.672899 DQ_SEMI_OPEN = 0
7101 06:49:27.675978 CA_SEMI_OPEN = 0
7102 06:49:27.679238 CA_FULL_RATE = 0
7103 06:49:27.682728 DQ_CKDIV4_EN = 0
7104 06:49:27.686031 CA_CKDIV4_EN = 0
7105 06:49:27.686116 CA_PREDIV_EN = 0
7106 06:49:27.689353 PH8_DLY = 12
7107 06:49:27.692556 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7108 06:49:27.695760 DQ_AAMCK_DIV = 4
7109 06:49:27.699247 CA_AAMCK_DIV = 4
7110 06:49:27.702954 CA_ADMCK_DIV = 4
7111 06:49:27.703039 DQ_TRACK_CA_EN = 0
7112 06:49:27.706015 CA_PICK = 1600
7113 06:49:27.709399 CA_MCKIO = 1600
7114 06:49:27.712359 MCKIO_SEMI = 0
7115 06:49:27.715711 PLL_FREQ = 3068
7116 06:49:27.719121 DQ_UI_PI_RATIO = 32
7117 06:49:27.722333 CA_UI_PI_RATIO = 0
7118 06:49:27.725905 ===================================
7119 06:49:27.729155 ===================================
7120 06:49:27.729270 memory_type:LPDDR4
7121 06:49:27.732399 GP_NUM : 10
7122 06:49:27.735902 SRAM_EN : 1
7123 06:49:27.736014 MD32_EN : 0
7124 06:49:27.738969 ===================================
7125 06:49:27.742288 [ANA_INIT] >>>>>>>>>>>>>>
7126 06:49:27.745815 <<<<<< [CONFIGURE PHASE]: ANA_TX
7127 06:49:27.748891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7128 06:49:27.752798 ===================================
7129 06:49:27.755804 data_rate = 3200,PCW = 0X7600
7130 06:49:27.758992 ===================================
7131 06:49:27.762514 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7132 06:49:27.765733 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7133 06:49:27.772291 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7134 06:49:27.775674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7135 06:49:27.778905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7136 06:49:27.782339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7137 06:49:27.785583 [ANA_INIT] flow start
7138 06:49:27.788660 [ANA_INIT] PLL >>>>>>>>
7139 06:49:27.788743 [ANA_INIT] PLL <<<<<<<<
7140 06:49:27.792254 [ANA_INIT] MIDPI >>>>>>>>
7141 06:49:27.795289 [ANA_INIT] MIDPI <<<<<<<<
7142 06:49:27.795376 [ANA_INIT] DLL >>>>>>>>
7143 06:49:27.798778 [ANA_INIT] DLL <<<<<<<<
7144 06:49:27.801946 [ANA_INIT] flow end
7145 06:49:27.805535 ============ LP4 DIFF to SE enter ============
7146 06:49:27.808590 ============ LP4 DIFF to SE exit ============
7147 06:49:27.812053 [ANA_INIT] <<<<<<<<<<<<<
7148 06:49:27.815543 [Flow] Enable top DCM control >>>>>
7149 06:49:27.818485 [Flow] Enable top DCM control <<<<<
7150 06:49:27.822119 Enable DLL master slave shuffle
7151 06:49:27.825458 ==============================================================
7152 06:49:27.828390 Gating Mode config
7153 06:49:27.835061 ==============================================================
7154 06:49:27.835145 Config description:
7155 06:49:27.845239 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7156 06:49:27.852061 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7157 06:49:27.855371 SELPH_MODE 0: By rank 1: By Phase
7158 06:49:27.862461 ==============================================================
7159 06:49:27.865388 GAT_TRACK_EN = 1
7160 06:49:27.868830 RX_GATING_MODE = 2
7161 06:49:27.872304 RX_GATING_TRACK_MODE = 2
7162 06:49:27.875644 SELPH_MODE = 1
7163 06:49:27.879304 PICG_EARLY_EN = 1
7164 06:49:27.882414 VALID_LAT_VALUE = 1
7165 06:49:27.885672 ==============================================================
7166 06:49:27.888747 Enter into Gating configuration >>>>
7167 06:49:27.891914 Exit from Gating configuration <<<<
7168 06:49:27.895537 Enter into DVFS_PRE_config >>>>>
7169 06:49:27.908905 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7170 06:49:27.908995 Exit from DVFS_PRE_config <<<<<
7171 06:49:27.911997 Enter into PICG configuration >>>>
7172 06:49:27.915082 Exit from PICG configuration <<<<
7173 06:49:27.918593 [RX_INPUT] configuration >>>>>
7174 06:49:27.922115 [RX_INPUT] configuration <<<<<
7175 06:49:27.928490 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7176 06:49:27.931728 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7177 06:49:27.938434 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7178 06:49:27.944910 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7179 06:49:27.951863 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7180 06:49:27.958302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7181 06:49:27.961841 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7182 06:49:27.965103 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7183 06:49:27.968521 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7184 06:49:27.975160 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7185 06:49:27.978903 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7186 06:49:27.981511 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7187 06:49:27.985162 ===================================
7188 06:49:27.988050 LPDDR4 DRAM CONFIGURATION
7189 06:49:27.991506 ===================================
7190 06:49:27.991586 EX_ROW_EN[0] = 0x0
7191 06:49:27.994661 EX_ROW_EN[1] = 0x0
7192 06:49:27.998112 LP4Y_EN = 0x0
7193 06:49:27.998218 WORK_FSP = 0x1
7194 06:49:28.001441 WL = 0x5
7195 06:49:28.001516 RL = 0x5
7196 06:49:28.005385 BL = 0x2
7197 06:49:28.005488 RPST = 0x0
7198 06:49:28.008448 RD_PRE = 0x0
7199 06:49:28.008529 WR_PRE = 0x1
7200 06:49:28.011417 WR_PST = 0x1
7201 06:49:28.011494 DBI_WR = 0x0
7202 06:49:28.015102 DBI_RD = 0x0
7203 06:49:28.015184 OTF = 0x1
7204 06:49:28.018327 ===================================
7205 06:49:28.021511 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7206 06:49:28.028945 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7207 06:49:28.031515 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7208 06:49:28.034726 ===================================
7209 06:49:28.038301 LPDDR4 DRAM CONFIGURATION
7210 06:49:28.041291 ===================================
7211 06:49:28.041367 EX_ROW_EN[0] = 0x10
7212 06:49:28.044858 EX_ROW_EN[1] = 0x0
7213 06:49:28.044962 LP4Y_EN = 0x0
7214 06:49:28.048239 WORK_FSP = 0x1
7215 06:49:28.051551 WL = 0x5
7216 06:49:28.051653 RL = 0x5
7217 06:49:28.054796 BL = 0x2
7218 06:49:28.054883 RPST = 0x0
7219 06:49:28.058350 RD_PRE = 0x0
7220 06:49:28.058437 WR_PRE = 0x1
7221 06:49:28.061501 WR_PST = 0x1
7222 06:49:28.061587 DBI_WR = 0x0
7223 06:49:28.064959 DBI_RD = 0x0
7224 06:49:28.065045 OTF = 0x1
7225 06:49:28.068051 ===================================
7226 06:49:28.074763 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7227 06:49:28.074846 ==
7228 06:49:28.077957 Dram Type= 6, Freq= 0, CH_0, rank 0
7229 06:49:28.081685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7230 06:49:28.081764 ==
7231 06:49:28.084485 [Duty_Offset_Calibration]
7232 06:49:28.088274 B0:2 B1:0 CA:1
7233 06:49:28.088359
7234 06:49:28.091425 [DutyScan_Calibration_Flow] k_type=0
7235 06:49:28.098815
7236 06:49:28.098901 ==CLK 0==
7237 06:49:28.102228 Final CLK duty delay cell = -4
7238 06:49:28.105727 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7239 06:49:28.108909 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7240 06:49:28.112137 [-4] AVG Duty = 4922%(X100)
7241 06:49:28.112222
7242 06:49:28.115526 CH0 CLK Duty spec in!! Max-Min= 218%
7243 06:49:28.118896 [DutyScan_Calibration_Flow] ====Done====
7244 06:49:28.118983
7245 06:49:28.122175 [DutyScan_Calibration_Flow] k_type=1
7246 06:49:28.138651
7247 06:49:28.138761 ==DQS 0 ==
7248 06:49:28.141731 Final DQS duty delay cell = 0
7249 06:49:28.145020 [0] MAX Duty = 5249%(X100), DQS PI = 32
7250 06:49:28.148375 [0] MIN Duty = 4969%(X100), DQS PI = 2
7251 06:49:28.151604 [0] AVG Duty = 5109%(X100)
7252 06:49:28.151691
7253 06:49:28.151760 ==DQS 1 ==
7254 06:49:28.154937 Final DQS duty delay cell = -4
7255 06:49:28.158749 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7256 06:49:28.161581 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7257 06:49:28.164747 [-4] AVG Duty = 5000%(X100)
7258 06:49:28.164825
7259 06:49:28.168365 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7260 06:49:28.168439
7261 06:49:28.171573 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7262 06:49:28.174924 [DutyScan_Calibration_Flow] ====Done====
7263 06:49:28.174995
7264 06:49:28.178208 [DutyScan_Calibration_Flow] k_type=3
7265 06:49:28.194959
7266 06:49:28.195061 ==DQM 0 ==
7267 06:49:28.198599 Final DQM duty delay cell = 0
7268 06:49:28.201513 [0] MAX Duty = 5093%(X100), DQS PI = 26
7269 06:49:28.204882 [0] MIN Duty = 4813%(X100), DQS PI = 50
7270 06:49:28.208174 [0] AVG Duty = 4953%(X100)
7271 06:49:28.208259
7272 06:49:28.208325 ==DQM 1 ==
7273 06:49:28.211762 Final DQM duty delay cell = -4
7274 06:49:28.215204 [-4] MAX Duty = 5031%(X100), DQS PI = 46
7275 06:49:28.218412 [-4] MIN Duty = 4751%(X100), DQS PI = 18
7276 06:49:28.222061 [-4] AVG Duty = 4891%(X100)
7277 06:49:28.222180
7278 06:49:28.225089 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7279 06:49:28.225195
7280 06:49:28.228226 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7281 06:49:28.231769 [DutyScan_Calibration_Flow] ====Done====
7282 06:49:28.231873
7283 06:49:28.234974 [DutyScan_Calibration_Flow] k_type=2
7284 06:49:28.252485
7285 06:49:28.252601 ==DQ 0 ==
7286 06:49:28.255800 Final DQ duty delay cell = 0
7287 06:49:28.259058 [0] MAX Duty = 5124%(X100), DQS PI = 32
7288 06:49:28.262684 [0] MIN Duty = 5000%(X100), DQS PI = 0
7289 06:49:28.262786 [0] AVG Duty = 5062%(X100)
7290 06:49:28.262881
7291 06:49:28.266025 ==DQ 1 ==
7292 06:49:28.268935 Final DQ duty delay cell = 0
7293 06:49:28.272640 [0] MAX Duty = 4969%(X100), DQS PI = 42
7294 06:49:28.275910 [0] MIN Duty = 4875%(X100), DQS PI = 12
7295 06:49:28.276011 [0] AVG Duty = 4922%(X100)
7296 06:49:28.276102
7297 06:49:28.279221 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7298 06:49:28.282489
7299 06:49:28.285586 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7300 06:49:28.289415 [DutyScan_Calibration_Flow] ====Done====
7301 06:49:28.289491 ==
7302 06:49:28.292505 Dram Type= 6, Freq= 0, CH_1, rank 0
7303 06:49:28.295681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7304 06:49:28.295782 ==
7305 06:49:28.298769 [Duty_Offset_Calibration]
7306 06:49:28.298870 B0:0 B1:-1 CA:2
7307 06:49:28.298962
7308 06:49:28.302146 [DutyScan_Calibration_Flow] k_type=0
7309 06:49:28.312639
7310 06:49:28.312746 ==CLK 0==
7311 06:49:28.315943 Final CLK duty delay cell = 0
7312 06:49:28.319407 [0] MAX Duty = 5156%(X100), DQS PI = 8
7313 06:49:28.322484 [0] MIN Duty = 4906%(X100), DQS PI = 46
7314 06:49:28.322583 [0] AVG Duty = 5031%(X100)
7315 06:49:28.326011
7316 06:49:28.329534 CH1 CLK Duty spec in!! Max-Min= 250%
7317 06:49:28.332372 [DutyScan_Calibration_Flow] ====Done====
7318 06:49:28.332473
7319 06:49:28.335977 [DutyScan_Calibration_Flow] k_type=1
7320 06:49:28.352103
7321 06:49:28.352194 ==DQS 0 ==
7322 06:49:28.355997 Final DQS duty delay cell = 0
7323 06:49:28.358864 [0] MAX Duty = 5124%(X100), DQS PI = 26
7324 06:49:28.362522 [0] MIN Duty = 5000%(X100), DQS PI = 0
7325 06:49:28.362601 [0] AVG Duty = 5062%(X100)
7326 06:49:28.365858
7327 06:49:28.365978 ==DQS 1 ==
7328 06:49:28.369131 Final DQS duty delay cell = 0
7329 06:49:28.372523 [0] MAX Duty = 5187%(X100), DQS PI = 0
7330 06:49:28.375581 [0] MIN Duty = 4844%(X100), DQS PI = 32
7331 06:49:28.375667 [0] AVG Duty = 5015%(X100)
7332 06:49:28.378854
7333 06:49:28.382346 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7334 06:49:28.382425
7335 06:49:28.385498 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7336 06:49:28.389012 [DutyScan_Calibration_Flow] ====Done====
7337 06:49:28.389116
7338 06:49:28.391900 [DutyScan_Calibration_Flow] k_type=3
7339 06:49:28.409957
7340 06:49:28.410045 ==DQM 0 ==
7341 06:49:28.413369 Final DQM duty delay cell = 4
7342 06:49:28.416733 [4] MAX Duty = 5125%(X100), DQS PI = 6
7343 06:49:28.419844 [4] MIN Duty = 5000%(X100), DQS PI = 32
7344 06:49:28.419923 [4] AVG Duty = 5062%(X100)
7345 06:49:28.423251
7346 06:49:28.423326 ==DQM 1 ==
7347 06:49:28.426444 Final DQM duty delay cell = 0
7348 06:49:28.429698 [0] MAX Duty = 5281%(X100), DQS PI = 58
7349 06:49:28.433085 [0] MIN Duty = 4876%(X100), DQS PI = 34
7350 06:49:28.436300 [0] AVG Duty = 5078%(X100)
7351 06:49:28.436383
7352 06:49:28.439895 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7353 06:49:28.439971
7354 06:49:28.442815 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7355 06:49:28.446445 [DutyScan_Calibration_Flow] ====Done====
7356 06:49:28.446523
7357 06:49:28.449430 [DutyScan_Calibration_Flow] k_type=2
7358 06:49:28.466859
7359 06:49:28.466952 ==DQ 0 ==
7360 06:49:28.470123 Final DQ duty delay cell = 0
7361 06:49:28.473560 [0] MAX Duty = 5062%(X100), DQS PI = 18
7362 06:49:28.476682 [0] MIN Duty = 4969%(X100), DQS PI = 32
7363 06:49:28.476754 [0] AVG Duty = 5015%(X100)
7364 06:49:28.476824
7365 06:49:28.479976 ==DQ 1 ==
7366 06:49:28.483672 Final DQ duty delay cell = 0
7367 06:49:28.486926 [0] MAX Duty = 5062%(X100), DQS PI = 0
7368 06:49:28.490096 [0] MIN Duty = 4813%(X100), DQS PI = 34
7369 06:49:28.490173 [0] AVG Duty = 4937%(X100)
7370 06:49:28.490237
7371 06:49:28.493510 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7372 06:49:28.493588
7373 06:49:28.496936 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7374 06:49:28.503146 [DutyScan_Calibration_Flow] ====Done====
7375 06:49:28.506320 nWR fixed to 30
7376 06:49:28.506398 [ModeRegInit_LP4] CH0 RK0
7377 06:49:28.509844 [ModeRegInit_LP4] CH0 RK1
7378 06:49:28.513151 [ModeRegInit_LP4] CH1 RK0
7379 06:49:28.513225 [ModeRegInit_LP4] CH1 RK1
7380 06:49:28.516232 match AC timing 5
7381 06:49:28.519883 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7382 06:49:28.523450 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7383 06:49:28.529593 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7384 06:49:28.533491 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7385 06:49:28.539761 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7386 06:49:28.539839 [MiockJmeterHQA]
7387 06:49:28.539904
7388 06:49:28.543126 [DramcMiockJmeter] u1RxGatingPI = 0
7389 06:49:28.547006 0 : 4365, 4138
7390 06:49:28.547089 4 : 4257, 4029
7391 06:49:28.547155 8 : 4253, 4027
7392 06:49:28.549710 12 : 4253, 4027
7393 06:49:28.549784 16 : 4252, 4026
7394 06:49:28.553431 20 : 4363, 4138
7395 06:49:28.553516 24 : 4252, 4027
7396 06:49:28.556495 28 : 4363, 4137
7397 06:49:28.556573 32 : 4258, 4030
7398 06:49:28.559993 36 : 4252, 4027
7399 06:49:28.560068 40 : 4252, 4027
7400 06:49:28.560133 44 : 4255, 4029
7401 06:49:28.563263 48 : 4363, 4138
7402 06:49:28.563337 52 : 4253, 4027
7403 06:49:28.566234 56 : 4363, 4137
7404 06:49:28.566315 60 : 4363, 4137
7405 06:49:28.569748 64 : 4253, 4029
7406 06:49:28.569828 68 : 4253, 4029
7407 06:49:28.569893 72 : 4360, 4138
7408 06:49:28.573122 76 : 4250, 4026
7409 06:49:28.573195 80 : 4363, 4140
7410 06:49:28.576435 84 : 4255, 4030
7411 06:49:28.576505 88 : 4250, 3598
7412 06:49:28.579660 92 : 4250, 0
7413 06:49:28.579733 96 : 4363, 0
7414 06:49:28.579797 100 : 4250, 0
7415 06:49:28.583334 104 : 4252, 0
7416 06:49:28.583413 108 : 4250, 0
7417 06:49:28.586516 112 : 4250, 0
7418 06:49:28.586591 116 : 4252, 0
7419 06:49:28.586654 120 : 4361, 0
7420 06:49:28.589976 124 : 4252, 0
7421 06:49:28.590056 128 : 4250, 0
7422 06:49:28.590120 132 : 4257, 0
7423 06:49:28.593066 136 : 4360, 0
7424 06:49:28.593138 140 : 4250, 0
7425 06:49:28.596497 144 : 4250, 0
7426 06:49:28.596573 148 : 4250, 0
7427 06:49:28.596645 152 : 4250, 0
7428 06:49:28.599862 156 : 4253, 0
7429 06:49:28.599939 160 : 4250, 0
7430 06:49:28.603193 164 : 4250, 0
7431 06:49:28.603271 168 : 4255, 0
7432 06:49:28.603333 172 : 4360, 0
7433 06:49:28.606278 176 : 4250, 0
7434 06:49:28.606353 180 : 4250, 0
7435 06:49:28.606416 184 : 4252, 0
7436 06:49:28.609868 188 : 4360, 0
7437 06:49:28.609950 192 : 4250, 0
7438 06:49:28.612915 196 : 4250, 0
7439 06:49:28.613002 200 : 4250, 4
7440 06:49:28.613070 204 : 4361, 2468
7441 06:49:28.616426 208 : 4360, 4137
7442 06:49:28.616500 212 : 4360, 4138
7443 06:49:28.620008 216 : 4248, 4024
7444 06:49:28.620096 220 : 4250, 4026
7445 06:49:28.623114 224 : 4360, 4138
7446 06:49:28.623192 228 : 4360, 4138
7447 06:49:28.626198 232 : 4250, 4027
7448 06:49:28.626281 236 : 4250, 4027
7449 06:49:28.629457 240 : 4250, 4027
7450 06:49:28.629536 244 : 4250, 4027
7451 06:49:28.633412 248 : 4250, 4027
7452 06:49:28.633494 252 : 4252, 4029
7453 06:49:28.636230 256 : 4250, 4027
7454 06:49:28.636304 260 : 4360, 4137
7455 06:49:28.639769 264 : 4250, 4027
7456 06:49:28.639844 268 : 4250, 4027
7457 06:49:28.639907 272 : 4250, 4026
7458 06:49:28.643145 276 : 4360, 4138
7459 06:49:28.643216 280 : 4363, 4138
7460 06:49:28.646565 284 : 4250, 4027
7461 06:49:28.646638 288 : 4363, 4140
7462 06:49:28.649751 292 : 4250, 4027
7463 06:49:28.649836 296 : 4250, 4027
7464 06:49:28.652998 300 : 4250, 4027
7465 06:49:28.653084 304 : 4252, 4029
7466 06:49:28.656339 308 : 4250, 4027
7467 06:49:28.656425 312 : 4360, 4028
7468 06:49:28.659571 316 : 4250, 2076
7469 06:49:28.659658
7470 06:49:28.659725 MIOCK jitter meter ch=0
7471 06:49:28.659785
7472 06:49:28.662893 1T = (316-92) = 224 dly cells
7473 06:49:28.669411 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7474 06:49:28.669503 ==
7475 06:49:28.672760 Dram Type= 6, Freq= 0, CH_0, rank 0
7476 06:49:28.676186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7477 06:49:28.676267 ==
7478 06:49:28.682472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7479 06:49:28.686249 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7480 06:49:28.689338 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7481 06:49:28.695795 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7482 06:49:28.705730 [CA 0] Center 42 (12~72) winsize 61
7483 06:49:28.708958 [CA 1] Center 42 (12~72) winsize 61
7484 06:49:28.712319 [CA 2] Center 37 (7~67) winsize 61
7485 06:49:28.715961 [CA 3] Center 37 (7~67) winsize 61
7486 06:49:28.718930 [CA 4] Center 35 (5~66) winsize 62
7487 06:49:28.722126 [CA 5] Center 35 (5~65) winsize 61
7488 06:49:28.722240
7489 06:49:28.725467 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7490 06:49:28.725568
7491 06:49:28.728828 [CATrainingPosCal] consider 1 rank data
7492 06:49:28.731988 u2DelayCellTimex100 = 290/100 ps
7493 06:49:28.735534 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7494 06:49:28.742294 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7495 06:49:28.745605 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7496 06:49:28.748721 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7497 06:49:28.752032 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7498 06:49:28.755982 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7499 06:49:28.756086
7500 06:49:28.758916 CA PerBit enable=1, Macro0, CA PI delay=35
7501 06:49:28.759026
7502 06:49:28.762076 [CBTSetCACLKResult] CA Dly = 35
7503 06:49:28.762179 CS Dly: 9 (0~40)
7504 06:49:28.768602 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7505 06:49:28.772135 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7506 06:49:28.772217 ==
7507 06:49:28.775380 Dram Type= 6, Freq= 0, CH_0, rank 1
7508 06:49:28.778706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 06:49:28.778787 ==
7510 06:49:28.785419 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 06:49:28.788482 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 06:49:28.795045 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 06:49:28.798504 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 06:49:28.808773 [CA 0] Center 43 (13~73) winsize 61
7515 06:49:28.812074 [CA 1] Center 43 (13~73) winsize 61
7516 06:49:28.815524 [CA 2] Center 37 (8~67) winsize 60
7517 06:49:28.818706 [CA 3] Center 38 (8~68) winsize 61
7518 06:49:28.821969 [CA 4] Center 36 (6~66) winsize 61
7519 06:49:28.825242 [CA 5] Center 36 (6~66) winsize 61
7520 06:49:28.825329
7521 06:49:28.828612 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7522 06:49:28.828697
7523 06:49:28.831840 [CATrainingPosCal] consider 2 rank data
7524 06:49:28.835309 u2DelayCellTimex100 = 290/100 ps
7525 06:49:28.838516 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7526 06:49:28.845347 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7527 06:49:28.848364 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7528 06:49:28.852101 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7529 06:49:28.855058 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7530 06:49:28.858415 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7531 06:49:28.858500
7532 06:49:28.861730 CA PerBit enable=1, Macro0, CA PI delay=35
7533 06:49:28.861814
7534 06:49:28.865417 [CBTSetCACLKResult] CA Dly = 35
7535 06:49:28.868603 CS Dly: 11 (0~44)
7536 06:49:28.871771 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 06:49:28.875327 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 06:49:28.875425
7539 06:49:28.878858 ----->DramcWriteLeveling(PI) begin...
7540 06:49:28.878943 ==
7541 06:49:28.881769 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 06:49:28.885117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 06:49:28.888524 ==
7544 06:49:28.888602 Write leveling (Byte 0): 34 => 34
7545 06:49:28.891792 Write leveling (Byte 1): 30 => 30
7546 06:49:28.895431 DramcWriteLeveling(PI) end<-----
7547 06:49:28.895514
7548 06:49:28.895580 ==
7549 06:49:28.898423 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 06:49:28.905073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 06:49:28.905162 ==
7552 06:49:28.905247 [Gating] SW mode calibration
7553 06:49:28.915041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7554 06:49:28.918268 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7555 06:49:28.925304 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 06:49:28.928446 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 06:49:28.931808 1 4 8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7558 06:49:28.935631 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7559 06:49:28.941698 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7560 06:49:28.945281 1 4 20 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7561 06:49:28.948502 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 06:49:28.955310 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 06:49:28.958709 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7564 06:49:28.962170 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7565 06:49:28.968226 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
7566 06:49:28.971885 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7567 06:49:28.974880 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7568 06:49:28.981669 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
7569 06:49:28.985197 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7570 06:49:28.988511 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 06:49:28.994935 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 06:49:28.998363 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 06:49:29.001714 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7574 06:49:29.008148 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7575 06:49:29.011504 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7576 06:49:29.015119 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7577 06:49:29.022058 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 06:49:29.024976 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 06:49:29.028388 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 06:49:29.034816 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 06:49:29.038248 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 06:49:29.041381 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7583 06:49:29.044853 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7584 06:49:29.051543 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7585 06:49:29.054755 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 06:49:29.058561 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 06:49:29.064949 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 06:49:29.068568 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 06:49:29.071764 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 06:49:29.078127 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 06:49:29.081955 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 06:49:29.084992 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 06:49:29.091571 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 06:49:29.094975 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 06:49:29.098333 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 06:49:29.104734 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 06:49:29.107959 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7598 06:49:29.111641 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7599 06:49:29.118243 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7600 06:49:29.118335 Total UI for P1: 0, mck2ui 16
7601 06:49:29.124755 best dqsien dly found for B0: ( 1, 9, 10)
7602 06:49:29.127894 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7603 06:49:29.131322 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 06:49:29.134558 Total UI for P1: 0, mck2ui 16
7605 06:49:29.137747 best dqsien dly found for B1: ( 1, 9, 20)
7606 06:49:29.141092 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7607 06:49:29.144441 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7608 06:49:29.144543
7609 06:49:29.151201 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7610 06:49:29.154587 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7611 06:49:29.154666 [Gating] SW calibration Done
7612 06:49:29.157892 ==
7613 06:49:29.161037 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 06:49:29.164831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 06:49:29.164933 ==
7616 06:49:29.165049 RX Vref Scan: 0
7617 06:49:29.165206
7618 06:49:29.168161 RX Vref 0 -> 0, step: 1
7619 06:49:29.168257
7620 06:49:29.171082 RX Delay 0 -> 252, step: 8
7621 06:49:29.174605 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7622 06:49:29.177836 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7623 06:49:29.181289 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7624 06:49:29.187908 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7625 06:49:29.191065 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7626 06:49:29.194505 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7627 06:49:29.197890 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7628 06:49:29.201094 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7629 06:49:29.207927 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7630 06:49:29.210874 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7631 06:49:29.214568 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7632 06:49:29.217698 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7633 06:49:29.220863 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7634 06:49:29.227794 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7635 06:49:29.230853 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7636 06:49:29.234483 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7637 06:49:29.234562 ==
7638 06:49:29.237714 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 06:49:29.240705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 06:49:29.240781 ==
7641 06:49:29.244216 DQS Delay:
7642 06:49:29.244290 DQS0 = 0, DQS1 = 0
7643 06:49:29.247789 DQM Delay:
7644 06:49:29.247874 DQM0 = 138, DQM1 = 126
7645 06:49:29.247942 DQ Delay:
7646 06:49:29.250832 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7647 06:49:29.257356 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7648 06:49:29.260709 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7649 06:49:29.264347 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7650 06:49:29.264429
7651 06:49:29.264493
7652 06:49:29.264555 ==
7653 06:49:29.267648 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 06:49:29.270944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 06:49:29.271020 ==
7656 06:49:29.271083
7657 06:49:29.271151
7658 06:49:29.274159 TX Vref Scan disable
7659 06:49:29.277486 == TX Byte 0 ==
7660 06:49:29.280961 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7661 06:49:29.284208 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7662 06:49:29.287429 == TX Byte 1 ==
7663 06:49:29.290723 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7664 06:49:29.294286 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7665 06:49:29.294367 ==
7666 06:49:29.297346 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 06:49:29.300975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 06:49:29.301050 ==
7669 06:49:29.315414
7670 06:49:29.318754 TX Vref early break, caculate TX vref
7671 06:49:29.321784 TX Vref=16, minBit 5, minWin=22, winSum=374
7672 06:49:29.325255 TX Vref=18, minBit 8, minWin=23, winSum=389
7673 06:49:29.328935 TX Vref=20, minBit 12, minWin=23, winSum=397
7674 06:49:29.331972 TX Vref=22, minBit 5, minWin=24, winSum=411
7675 06:49:29.335163 TX Vref=24, minBit 8, minWin=24, winSum=413
7676 06:49:29.341765 TX Vref=26, minBit 12, minWin=25, winSum=422
7677 06:49:29.345389 TX Vref=28, minBit 1, minWin=26, winSum=431
7678 06:49:29.348705 TX Vref=30, minBit 0, minWin=26, winSum=426
7679 06:49:29.351948 TX Vref=32, minBit 2, minWin=25, winSum=418
7680 06:49:29.355741 TX Vref=34, minBit 1, minWin=24, winSum=405
7681 06:49:29.362280 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
7682 06:49:29.362374
7683 06:49:29.365435 Final TX Range 0 Vref 28
7684 06:49:29.365542
7685 06:49:29.365643 ==
7686 06:49:29.368654 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 06:49:29.371835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 06:49:29.371914 ==
7689 06:49:29.371980
7690 06:49:29.372052
7691 06:49:29.375184 TX Vref Scan disable
7692 06:49:29.381791 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7693 06:49:29.381902 == TX Byte 0 ==
7694 06:49:29.385421 u2DelayCellOfst[0]=13 cells (4 PI)
7695 06:49:29.388553 u2DelayCellOfst[1]=16 cells (5 PI)
7696 06:49:29.391855 u2DelayCellOfst[2]=13 cells (4 PI)
7697 06:49:29.395205 u2DelayCellOfst[3]=13 cells (4 PI)
7698 06:49:29.398673 u2DelayCellOfst[4]=10 cells (3 PI)
7699 06:49:29.402085 u2DelayCellOfst[5]=0 cells (0 PI)
7700 06:49:29.405267 u2DelayCellOfst[6]=16 cells (5 PI)
7701 06:49:29.405373 u2DelayCellOfst[7]=16 cells (5 PI)
7702 06:49:29.412126 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7703 06:49:29.415134 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7704 06:49:29.415216 == TX Byte 1 ==
7705 06:49:29.418720 u2DelayCellOfst[8]=0 cells (0 PI)
7706 06:49:29.421904 u2DelayCellOfst[9]=0 cells (0 PI)
7707 06:49:29.425190 u2DelayCellOfst[10]=6 cells (2 PI)
7708 06:49:29.429036 u2DelayCellOfst[11]=3 cells (1 PI)
7709 06:49:29.431868 u2DelayCellOfst[12]=13 cells (4 PI)
7710 06:49:29.435295 u2DelayCellOfst[13]=10 cells (3 PI)
7711 06:49:29.438490 u2DelayCellOfst[14]=13 cells (4 PI)
7712 06:49:29.442124 u2DelayCellOfst[15]=10 cells (3 PI)
7713 06:49:29.445362 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7714 06:49:29.448618 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7715 06:49:29.452082 DramC Write-DBI on
7716 06:49:29.452159 ==
7717 06:49:29.455348 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 06:49:29.458529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 06:49:29.458604 ==
7720 06:49:29.458669
7721 06:49:29.462043
7722 06:49:29.462141 TX Vref Scan disable
7723 06:49:29.465248 == TX Byte 0 ==
7724 06:49:29.468315 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7725 06:49:29.472058 == TX Byte 1 ==
7726 06:49:29.475114 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7727 06:49:29.475190 DramC Write-DBI off
7728 06:49:29.475257
7729 06:49:29.478756 [DATLAT]
7730 06:49:29.478830 Freq=1600, CH0 RK0
7731 06:49:29.478893
7732 06:49:29.482125 DATLAT Default: 0xf
7733 06:49:29.482196 0, 0xFFFF, sum = 0
7734 06:49:29.485073 1, 0xFFFF, sum = 0
7735 06:49:29.485142 2, 0xFFFF, sum = 0
7736 06:49:29.488570 3, 0xFFFF, sum = 0
7737 06:49:29.488644 4, 0xFFFF, sum = 0
7738 06:49:29.491769 5, 0xFFFF, sum = 0
7739 06:49:29.491838 6, 0xFFFF, sum = 0
7740 06:49:29.494999 7, 0xFFFF, sum = 0
7741 06:49:29.498604 8, 0xFFFF, sum = 0
7742 06:49:29.498682 9, 0xFFFF, sum = 0
7743 06:49:29.501885 10, 0xFFFF, sum = 0
7744 06:49:29.501978 11, 0xFFFF, sum = 0
7745 06:49:29.505008 12, 0xFFFF, sum = 0
7746 06:49:29.505097 13, 0xFFFF, sum = 0
7747 06:49:29.508354 14, 0x0, sum = 1
7748 06:49:29.508468 15, 0x0, sum = 2
7749 06:49:29.511957 16, 0x0, sum = 3
7750 06:49:29.512065 17, 0x0, sum = 4
7751 06:49:29.512177 best_step = 15
7752 06:49:29.514995
7753 06:49:29.515093 ==
7754 06:49:29.518321 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 06:49:29.522007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 06:49:29.522116 ==
7757 06:49:29.522220 RX Vref Scan: 1
7758 06:49:29.522313
7759 06:49:29.525099 Set Vref Range= 24 -> 127
7760 06:49:29.525186
7761 06:49:29.528333 RX Vref 24 -> 127, step: 1
7762 06:49:29.528419
7763 06:49:29.531793 RX Delay 19 -> 252, step: 4
7764 06:49:29.531879
7765 06:49:29.534996 Set Vref, RX VrefLevel [Byte0]: 24
7766 06:49:29.538678 [Byte1]: 24
7767 06:49:29.538765
7768 06:49:29.541841 Set Vref, RX VrefLevel [Byte0]: 25
7769 06:49:29.545244 [Byte1]: 25
7770 06:49:29.545330
7771 06:49:29.548535 Set Vref, RX VrefLevel [Byte0]: 26
7772 06:49:29.551813 [Byte1]: 26
7773 06:49:29.555225
7774 06:49:29.555311 Set Vref, RX VrefLevel [Byte0]: 27
7775 06:49:29.558333 [Byte1]: 27
7776 06:49:29.562902
7777 06:49:29.562988 Set Vref, RX VrefLevel [Byte0]: 28
7778 06:49:29.566159 [Byte1]: 28
7779 06:49:29.570246
7780 06:49:29.570332 Set Vref, RX VrefLevel [Byte0]: 29
7781 06:49:29.573525 [Byte1]: 29
7782 06:49:29.577805
7783 06:49:29.577918 Set Vref, RX VrefLevel [Byte0]: 30
7784 06:49:29.581330 [Byte1]: 30
7785 06:49:29.585428
7786 06:49:29.585513 Set Vref, RX VrefLevel [Byte0]: 31
7787 06:49:29.588726 [Byte1]: 31
7788 06:49:29.593172
7789 06:49:29.593271 Set Vref, RX VrefLevel [Byte0]: 32
7790 06:49:29.596277 [Byte1]: 32
7791 06:49:29.600545
7792 06:49:29.600629 Set Vref, RX VrefLevel [Byte0]: 33
7793 06:49:29.603852 [Byte1]: 33
7794 06:49:29.608415
7795 06:49:29.608514 Set Vref, RX VrefLevel [Byte0]: 34
7796 06:49:29.611291 [Byte1]: 34
7797 06:49:29.615769
7798 06:49:29.615855 Set Vref, RX VrefLevel [Byte0]: 35
7799 06:49:29.619227 [Byte1]: 35
7800 06:49:29.623120
7801 06:49:29.623235 Set Vref, RX VrefLevel [Byte0]: 36
7802 06:49:29.626555 [Byte1]: 36
7803 06:49:29.630825
7804 06:49:29.630906 Set Vref, RX VrefLevel [Byte0]: 37
7805 06:49:29.634198 [Byte1]: 37
7806 06:49:29.638498
7807 06:49:29.638582 Set Vref, RX VrefLevel [Byte0]: 38
7808 06:49:29.641677 [Byte1]: 38
7809 06:49:29.646187
7810 06:49:29.646272 Set Vref, RX VrefLevel [Byte0]: 39
7811 06:49:29.649445 [Byte1]: 39
7812 06:49:29.653396
7813 06:49:29.653472 Set Vref, RX VrefLevel [Byte0]: 40
7814 06:49:29.657044 [Byte1]: 40
7815 06:49:29.661190
7816 06:49:29.661270 Set Vref, RX VrefLevel [Byte0]: 41
7817 06:49:29.664676 [Byte1]: 41
7818 06:49:29.668704
7819 06:49:29.668830 Set Vref, RX VrefLevel [Byte0]: 42
7820 06:49:29.672337 [Byte1]: 42
7821 06:49:29.676444
7822 06:49:29.676523 Set Vref, RX VrefLevel [Byte0]: 43
7823 06:49:29.679531 [Byte1]: 43
7824 06:49:29.683678
7825 06:49:29.683763 Set Vref, RX VrefLevel [Byte0]: 44
7826 06:49:29.687201 [Byte1]: 44
7827 06:49:29.691408
7828 06:49:29.691491 Set Vref, RX VrefLevel [Byte0]: 45
7829 06:49:29.694746 [Byte1]: 45
7830 06:49:29.698989
7831 06:49:29.699070 Set Vref, RX VrefLevel [Byte0]: 46
7832 06:49:29.702458 [Byte1]: 46
7833 06:49:29.706974
7834 06:49:29.707052 Set Vref, RX VrefLevel [Byte0]: 47
7835 06:49:29.710028 [Byte1]: 47
7836 06:49:29.713865
7837 06:49:29.713977 Set Vref, RX VrefLevel [Byte0]: 48
7838 06:49:29.717279 [Byte1]: 48
7839 06:49:29.721555
7840 06:49:29.721666 Set Vref, RX VrefLevel [Byte0]: 49
7841 06:49:29.725201 [Byte1]: 49
7842 06:49:29.729471
7843 06:49:29.729552 Set Vref, RX VrefLevel [Byte0]: 50
7844 06:49:29.732530 [Byte1]: 50
7845 06:49:29.736978
7846 06:49:29.737084 Set Vref, RX VrefLevel [Byte0]: 51
7847 06:49:29.740398 [Byte1]: 51
7848 06:49:29.744399
7849 06:49:29.744486 Set Vref, RX VrefLevel [Byte0]: 52
7850 06:49:29.747821 [Byte1]: 52
7851 06:49:29.751875
7852 06:49:29.751961 Set Vref, RX VrefLevel [Byte0]: 53
7853 06:49:29.755316 [Byte1]: 53
7854 06:49:29.759372
7855 06:49:29.759450 Set Vref, RX VrefLevel [Byte0]: 54
7856 06:49:29.762782 [Byte1]: 54
7857 06:49:29.767456
7858 06:49:29.767531 Set Vref, RX VrefLevel [Byte0]: 55
7859 06:49:29.770279 [Byte1]: 55
7860 06:49:29.774664
7861 06:49:29.774736 Set Vref, RX VrefLevel [Byte0]: 56
7862 06:49:29.778018 [Byte1]: 56
7863 06:49:29.782292
7864 06:49:29.782365 Set Vref, RX VrefLevel [Byte0]: 57
7865 06:49:29.785752 [Byte1]: 57
7866 06:49:29.789861
7867 06:49:29.789932 Set Vref, RX VrefLevel [Byte0]: 58
7868 06:49:29.793419 [Byte1]: 58
7869 06:49:29.797268
7870 06:49:29.797347 Set Vref, RX VrefLevel [Byte0]: 59
7871 06:49:29.800624 [Byte1]: 59
7872 06:49:29.804817
7873 06:49:29.804928 Set Vref, RX VrefLevel [Byte0]: 60
7874 06:49:29.808699 [Byte1]: 60
7875 06:49:29.812635
7876 06:49:29.812737 Set Vref, RX VrefLevel [Byte0]: 61
7877 06:49:29.815877 [Byte1]: 61
7878 06:49:29.820337
7879 06:49:29.820430 Set Vref, RX VrefLevel [Byte0]: 62
7880 06:49:29.823607 [Byte1]: 62
7881 06:49:29.827617
7882 06:49:29.827706 Set Vref, RX VrefLevel [Byte0]: 63
7883 06:49:29.831239 [Byte1]: 63
7884 06:49:29.835079
7885 06:49:29.835165 Set Vref, RX VrefLevel [Byte0]: 64
7886 06:49:29.838974 [Byte1]: 64
7887 06:49:29.842841
7888 06:49:29.842927 Set Vref, RX VrefLevel [Byte0]: 65
7889 06:49:29.846245 [Byte1]: 65
7890 06:49:29.850679
7891 06:49:29.850763 Set Vref, RX VrefLevel [Byte0]: 66
7892 06:49:29.853861 [Byte1]: 66
7893 06:49:29.857913
7894 06:49:29.858007 Set Vref, RX VrefLevel [Byte0]: 67
7895 06:49:29.861725 [Byte1]: 67
7896 06:49:29.865604
7897 06:49:29.865690 Set Vref, RX VrefLevel [Byte0]: 68
7898 06:49:29.869079 [Byte1]: 68
7899 06:49:29.873250
7900 06:49:29.873328 Set Vref, RX VrefLevel [Byte0]: 69
7901 06:49:29.876501 [Byte1]: 69
7902 06:49:29.880925
7903 06:49:29.881004 Set Vref, RX VrefLevel [Byte0]: 70
7904 06:49:29.884212 [Byte1]: 70
7905 06:49:29.888285
7906 06:49:29.888364 Set Vref, RX VrefLevel [Byte0]: 71
7907 06:49:29.891720 [Byte1]: 71
7908 06:49:29.895769
7909 06:49:29.899135 Set Vref, RX VrefLevel [Byte0]: 72
7910 06:49:29.899214 [Byte1]: 72
7911 06:49:29.903304
7912 06:49:29.903384 Set Vref, RX VrefLevel [Byte0]: 73
7913 06:49:29.906572 [Byte1]: 73
7914 06:49:29.911408
7915 06:49:29.911486 Set Vref, RX VrefLevel [Byte0]: 74
7916 06:49:29.914229 [Byte1]: 74
7917 06:49:29.918427
7918 06:49:29.918507 Set Vref, RX VrefLevel [Byte0]: 75
7919 06:49:29.922056 [Byte1]: 75
7920 06:49:29.926325
7921 06:49:29.926407 Set Vref, RX VrefLevel [Byte0]: 76
7922 06:49:29.929363 [Byte1]: 76
7923 06:49:29.933833
7924 06:49:29.933911 Set Vref, RX VrefLevel [Byte0]: 77
7925 06:49:29.937037 [Byte1]: 77
7926 06:49:29.941241
7927 06:49:29.941348 Set Vref, RX VrefLevel [Byte0]: 78
7928 06:49:29.944873 [Byte1]: 78
7929 06:49:29.948831
7930 06:49:29.948915 Set Vref, RX VrefLevel [Byte0]: 79
7931 06:49:29.952126 [Byte1]: 79
7932 06:49:29.956237
7933 06:49:29.956317 Set Vref, RX VrefLevel [Byte0]: 80
7934 06:49:29.959762 [Byte1]: 80
7935 06:49:29.963882
7936 06:49:29.963971 Final RX Vref Byte 0 = 60 to rank0
7937 06:49:29.967509 Final RX Vref Byte 1 = 62 to rank0
7938 06:49:29.970752 Final RX Vref Byte 0 = 60 to rank1
7939 06:49:29.973817 Final RX Vref Byte 1 = 62 to rank1==
7940 06:49:29.977341 Dram Type= 6, Freq= 0, CH_0, rank 0
7941 06:49:29.984221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7942 06:49:29.984304 ==
7943 06:49:29.984369 DQS Delay:
7944 06:49:29.987358 DQS0 = 0, DQS1 = 0
7945 06:49:29.987432 DQM Delay:
7946 06:49:29.987499 DQM0 = 136, DQM1 = 124
7947 06:49:29.990520 DQ Delay:
7948 06:49:29.993723 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
7949 06:49:29.997306 DQ4 =140, DQ5 =126, DQ6 =142, DQ7 =144
7950 06:49:30.000461 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7951 06:49:30.003788 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =134
7952 06:49:30.003860
7953 06:49:30.003923
7954 06:49:30.004028
7955 06:49:30.007091 [DramC_TX_OE_Calibration] TA2
7956 06:49:30.010532 Original DQ_B0 (3 6) =30, OEN = 27
7957 06:49:30.013744 Original DQ_B1 (3 6) =30, OEN = 27
7958 06:49:30.017274 24, 0x0, End_B0=24 End_B1=24
7959 06:49:30.017360 25, 0x0, End_B0=25 End_B1=25
7960 06:49:30.020778 26, 0x0, End_B0=26 End_B1=26
7961 06:49:30.024072 27, 0x0, End_B0=27 End_B1=27
7962 06:49:30.027536 28, 0x0, End_B0=28 End_B1=28
7963 06:49:30.027623 29, 0x0, End_B0=29 End_B1=29
7964 06:49:30.030704 30, 0x0, End_B0=30 End_B1=30
7965 06:49:30.033877 31, 0x4141, End_B0=30 End_B1=30
7966 06:49:30.037276 Byte0 end_step=30 best_step=27
7967 06:49:30.040719 Byte1 end_step=30 best_step=27
7968 06:49:30.043966 Byte0 TX OE(2T, 0.5T) = (3, 3)
7969 06:49:30.044040 Byte1 TX OE(2T, 0.5T) = (3, 3)
7970 06:49:30.044136
7971 06:49:30.047392
7972 06:49:30.054011 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7973 06:49:30.057578 CH0 RK0: MR19=303, MR18=1D1C
7974 06:49:30.063745 CH0_RK0: MR19=0x303, MR18=0x1D1C, DQSOSC=395, MR23=63, INC=23, DEC=15
7975 06:49:30.063825
7976 06:49:30.067270 ----->DramcWriteLeveling(PI) begin...
7977 06:49:30.067376 ==
7978 06:49:30.070657 Dram Type= 6, Freq= 0, CH_0, rank 1
7979 06:49:30.073581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7980 06:49:30.073691 ==
7981 06:49:30.077084 Write leveling (Byte 0): 38 => 38
7982 06:49:30.080377 Write leveling (Byte 1): 29 => 29
7983 06:49:30.083787 DramcWriteLeveling(PI) end<-----
7984 06:49:30.083872
7985 06:49:30.083938 ==
7986 06:49:30.086955 Dram Type= 6, Freq= 0, CH_0, rank 1
7987 06:49:30.090396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 06:49:30.090472 ==
7989 06:49:30.093928 [Gating] SW mode calibration
7990 06:49:30.100550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7991 06:49:30.106774 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7992 06:49:30.110074 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 06:49:30.113928 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 06:49:30.120460 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 06:49:30.123689 1 4 12 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
7996 06:49:30.126802 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 06:49:30.133512 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 06:49:30.136703 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 06:49:30.140143 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 06:49:30.146485 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 06:49:30.150259 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 06:49:30.153639 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8003 06:49:30.160197 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
8004 06:49:30.163510 1 5 16 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)
8005 06:49:30.166838 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 06:49:30.173398 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 06:49:30.176538 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 06:49:30.179857 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 06:49:30.186572 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 06:49:30.190315 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
8011 06:49:30.193326 1 6 12 | B1->B0 | 2f2f 4343 | 0 0 | (0 0) (0 0)
8012 06:49:30.200020 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 06:49:30.203206 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 06:49:30.206584 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 06:49:30.213546 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 06:49:30.216473 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 06:49:30.219978 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 06:49:30.222942 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 06:49:30.229779 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8020 06:49:30.233163 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8021 06:49:30.236382 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 06:49:30.242923 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 06:49:30.246502 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 06:49:30.249698 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 06:49:30.256632 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 06:49:30.259781 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 06:49:30.263154 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 06:49:30.269833 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 06:49:30.272944 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 06:49:30.276143 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 06:49:30.282699 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 06:49:30.286190 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 06:49:30.289837 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 06:49:30.296674 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8035 06:49:30.299334 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8036 06:49:30.302962 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8037 06:49:30.306760 Total UI for P1: 0, mck2ui 16
8038 06:49:30.309185 best dqsien dly found for B0: ( 1, 9, 10)
8039 06:49:30.316069 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 06:49:30.316146 Total UI for P1: 0, mck2ui 16
8041 06:49:30.322689 best dqsien dly found for B1: ( 1, 9, 14)
8042 06:49:30.325811 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8043 06:49:30.329038 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8044 06:49:30.329124
8045 06:49:30.333021 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8046 06:49:30.336019 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8047 06:49:30.339057 [Gating] SW calibration Done
8048 06:49:30.339135 ==
8049 06:49:30.342513 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 06:49:30.345819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 06:49:30.345925 ==
8052 06:49:30.349022 RX Vref Scan: 0
8053 06:49:30.349092
8054 06:49:30.349154 RX Vref 0 -> 0, step: 1
8055 06:49:30.349222
8056 06:49:30.352587 RX Delay 0 -> 252, step: 8
8057 06:49:30.355822 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8058 06:49:30.362356 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8059 06:49:30.365595 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8060 06:49:30.369047 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8061 06:49:30.372197 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8062 06:49:30.375562 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8063 06:49:30.382687 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8064 06:49:30.385656 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8065 06:49:30.388989 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8066 06:49:30.392130 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8067 06:49:30.395450 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8068 06:49:30.402114 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8069 06:49:30.405670 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8070 06:49:30.408852 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8071 06:49:30.412247 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8072 06:49:30.415852 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8073 06:49:30.418675 ==
8074 06:49:30.422225 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 06:49:30.425509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 06:49:30.425609 ==
8077 06:49:30.425677 DQS Delay:
8078 06:49:30.428828 DQS0 = 0, DQS1 = 0
8079 06:49:30.428915 DQM Delay:
8080 06:49:30.432278 DQM0 = 136, DQM1 = 125
8081 06:49:30.432365 DQ Delay:
8082 06:49:30.435616 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8083 06:49:30.438666 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8084 06:49:30.442366 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =123
8085 06:49:30.445743 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8086 06:49:30.445828
8087 06:49:30.445894
8088 06:49:30.445999 ==
8089 06:49:30.448785 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 06:49:30.455247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 06:49:30.455333 ==
8092 06:49:30.455399
8093 06:49:30.455464
8094 06:49:30.455526 TX Vref Scan disable
8095 06:49:30.459332 == TX Byte 0 ==
8096 06:49:30.462623 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8097 06:49:30.469140 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8098 06:49:30.469226 == TX Byte 1 ==
8099 06:49:30.472478 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8100 06:49:30.479325 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8101 06:49:30.479428 ==
8102 06:49:30.482316 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 06:49:30.485443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 06:49:30.485573 ==
8105 06:49:30.500170
8106 06:49:30.503860 TX Vref early break, caculate TX vref
8107 06:49:30.506956 TX Vref=16, minBit 8, minWin=22, winSum=388
8108 06:49:30.510171 TX Vref=18, minBit 0, minWin=24, winSum=396
8109 06:49:30.513507 TX Vref=20, minBit 8, minWin=24, winSum=407
8110 06:49:30.516786 TX Vref=22, minBit 8, minWin=24, winSum=412
8111 06:49:30.520034 TX Vref=24, minBit 2, minWin=25, winSum=422
8112 06:49:30.527263 TX Vref=26, minBit 0, minWin=26, winSum=432
8113 06:49:30.530084 TX Vref=28, minBit 0, minWin=26, winSum=432
8114 06:49:30.533772 TX Vref=30, minBit 0, minWin=26, winSum=431
8115 06:49:30.536715 TX Vref=32, minBit 2, minWin=25, winSum=419
8116 06:49:30.540262 TX Vref=34, minBit 0, minWin=25, winSum=410
8117 06:49:30.543326 TX Vref=36, minBit 2, minWin=24, winSum=403
8118 06:49:30.550107 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 26
8119 06:49:30.550193
8120 06:49:30.553346 Final TX Range 0 Vref 26
8121 06:49:30.553448
8122 06:49:30.553548 ==
8123 06:49:30.556567 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 06:49:30.559795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 06:49:30.559881 ==
8126 06:49:30.559947
8127 06:49:30.560009
8128 06:49:30.563323 TX Vref Scan disable
8129 06:49:30.570063 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8130 06:49:30.570148 == TX Byte 0 ==
8131 06:49:30.573225 u2DelayCellOfst[0]=13 cells (4 PI)
8132 06:49:30.576557 u2DelayCellOfst[1]=20 cells (6 PI)
8133 06:49:30.580441 u2DelayCellOfst[2]=13 cells (4 PI)
8134 06:49:30.583347 u2DelayCellOfst[3]=13 cells (4 PI)
8135 06:49:30.586629 u2DelayCellOfst[4]=10 cells (3 PI)
8136 06:49:30.590188 u2DelayCellOfst[5]=0 cells (0 PI)
8137 06:49:30.593408 u2DelayCellOfst[6]=20 cells (6 PI)
8138 06:49:30.596548 u2DelayCellOfst[7]=20 cells (6 PI)
8139 06:49:30.599944 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8140 06:49:30.603147 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8141 06:49:30.606470 == TX Byte 1 ==
8142 06:49:30.609840 u2DelayCellOfst[8]=0 cells (0 PI)
8143 06:49:30.612994 u2DelayCellOfst[9]=0 cells (0 PI)
8144 06:49:30.616274 u2DelayCellOfst[10]=6 cells (2 PI)
8145 06:49:30.616380 u2DelayCellOfst[11]=3 cells (1 PI)
8146 06:49:30.619850 u2DelayCellOfst[12]=13 cells (4 PI)
8147 06:49:30.622926 u2DelayCellOfst[13]=10 cells (3 PI)
8148 06:49:30.626382 u2DelayCellOfst[14]=16 cells (5 PI)
8149 06:49:30.629748 u2DelayCellOfst[15]=10 cells (3 PI)
8150 06:49:30.636200 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8151 06:49:30.639733 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8152 06:49:30.639807 DramC Write-DBI on
8153 06:49:30.639874 ==
8154 06:49:30.643258 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 06:49:30.649636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 06:49:30.649741 ==
8157 06:49:30.649839
8158 06:49:30.649971
8159 06:49:30.650055 TX Vref Scan disable
8160 06:49:30.654060 == TX Byte 0 ==
8161 06:49:30.657159 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8162 06:49:30.660450 == TX Byte 1 ==
8163 06:49:30.663838 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8164 06:49:30.666874 DramC Write-DBI off
8165 06:49:30.666951
8166 06:49:30.667044 [DATLAT]
8167 06:49:30.667133 Freq=1600, CH0 RK1
8168 06:49:30.667200
8169 06:49:30.670382 DATLAT Default: 0xf
8170 06:49:30.670455 0, 0xFFFF, sum = 0
8171 06:49:30.673663 1, 0xFFFF, sum = 0
8172 06:49:30.677144 2, 0xFFFF, sum = 0
8173 06:49:30.677262 3, 0xFFFF, sum = 0
8174 06:49:30.680096 4, 0xFFFF, sum = 0
8175 06:49:30.680197 5, 0xFFFF, sum = 0
8176 06:49:30.683520 6, 0xFFFF, sum = 0
8177 06:49:30.683621 7, 0xFFFF, sum = 0
8178 06:49:30.687002 8, 0xFFFF, sum = 0
8179 06:49:30.687103 9, 0xFFFF, sum = 0
8180 06:49:30.690101 10, 0xFFFF, sum = 0
8181 06:49:30.690180 11, 0xFFFF, sum = 0
8182 06:49:30.693729 12, 0xFFFF, sum = 0
8183 06:49:30.693846 13, 0xFFFF, sum = 0
8184 06:49:30.696868 14, 0x0, sum = 1
8185 06:49:30.696971 15, 0x0, sum = 2
8186 06:49:30.700261 16, 0x0, sum = 3
8187 06:49:30.700362 17, 0x0, sum = 4
8188 06:49:30.703646 best_step = 15
8189 06:49:30.703749
8190 06:49:30.703845 ==
8191 06:49:30.707046 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 06:49:30.710122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 06:49:30.710226 ==
8194 06:49:30.713612 RX Vref Scan: 0
8195 06:49:30.713712
8196 06:49:30.713806 RX Vref 0 -> 0, step: 1
8197 06:49:30.713900
8198 06:49:30.716892 RX Delay 19 -> 252, step: 4
8199 06:49:30.720101 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8200 06:49:30.727001 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8201 06:49:30.730220 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8202 06:49:30.733766 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8203 06:49:30.736794 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8204 06:49:30.740044 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8205 06:49:30.743664 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8206 06:49:30.750580 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8207 06:49:30.753573 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8208 06:49:30.757167 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8209 06:49:30.760234 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8210 06:49:30.763915 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8211 06:49:30.770149 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8212 06:49:30.773713 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8213 06:49:30.776853 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8214 06:49:30.780487 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8215 06:49:30.780594 ==
8216 06:49:30.783462 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 06:49:30.790178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 06:49:30.790263 ==
8219 06:49:30.790330 DQS Delay:
8220 06:49:30.793853 DQS0 = 0, DQS1 = 0
8221 06:49:30.793984 DQM Delay:
8222 06:49:30.794100 DQM0 = 133, DQM1 = 123
8223 06:49:30.796806 DQ Delay:
8224 06:49:30.800112 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8225 06:49:30.803869 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8226 06:49:30.806881 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8227 06:49:30.810111 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8228 06:49:30.810194
8229 06:49:30.810259
8230 06:49:30.810319
8231 06:49:30.814195 [DramC_TX_OE_Calibration] TA2
8232 06:49:30.816935 Original DQ_B0 (3 6) =30, OEN = 27
8233 06:49:30.819917 Original DQ_B1 (3 6) =30, OEN = 27
8234 06:49:30.823826 24, 0x0, End_B0=24 End_B1=24
8235 06:49:30.823939 25, 0x0, End_B0=25 End_B1=25
8236 06:49:30.826784 26, 0x0, End_B0=26 End_B1=26
8237 06:49:30.830142 27, 0x0, End_B0=27 End_B1=27
8238 06:49:30.833668 28, 0x0, End_B0=28 End_B1=28
8239 06:49:30.837180 29, 0x0, End_B0=29 End_B1=29
8240 06:49:30.837299 30, 0x0, End_B0=30 End_B1=30
8241 06:49:30.840541 31, 0x4141, End_B0=30 End_B1=30
8242 06:49:30.843459 Byte0 end_step=30 best_step=27
8243 06:49:30.847023 Byte1 end_step=30 best_step=27
8244 06:49:30.850292 Byte0 TX OE(2T, 0.5T) = (3, 3)
8245 06:49:30.853417 Byte1 TX OE(2T, 0.5T) = (3, 3)
8246 06:49:30.853505
8247 06:49:30.853596
8248 06:49:30.860444 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8249 06:49:30.863178 CH0 RK1: MR19=303, MR18=220F
8250 06:49:30.870289 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8251 06:49:30.873572 [RxdqsGatingPostProcess] freq 1600
8252 06:49:30.876955 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8253 06:49:30.880121 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 06:49:30.883257 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 06:49:30.886512 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 06:49:30.889858 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 06:49:30.893484 best DQS0 dly(2T, 0.5T) = (1, 1)
8258 06:49:30.896755 best DQS1 dly(2T, 0.5T) = (1, 1)
8259 06:49:30.900202 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8260 06:49:30.903362 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8261 06:49:30.906410 Pre-setting of DQS Precalculation
8262 06:49:30.910150 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8263 06:49:30.910234 ==
8264 06:49:30.913269 Dram Type= 6, Freq= 0, CH_1, rank 0
8265 06:49:30.916618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 06:49:30.919816 ==
8267 06:49:30.923347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 06:49:30.926795 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 06:49:30.933129 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 06:49:30.936559 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 06:49:30.946902 [CA 0] Center 40 (11~70) winsize 60
8272 06:49:30.950097 [CA 1] Center 41 (11~71) winsize 61
8273 06:49:30.953492 [CA 2] Center 36 (7~66) winsize 60
8274 06:49:30.956582 [CA 3] Center 36 (7~66) winsize 60
8275 06:49:30.960197 [CA 4] Center 36 (6~66) winsize 61
8276 06:49:30.963070 [CA 5] Center 36 (6~66) winsize 61
8277 06:49:30.963154
8278 06:49:30.966629 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8279 06:49:30.966714
8280 06:49:30.969911 [CATrainingPosCal] consider 1 rank data
8281 06:49:30.973370 u2DelayCellTimex100 = 290/100 ps
8282 06:49:30.976449 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8283 06:49:30.983536 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8284 06:49:30.986439 CA2 delay=36 (7~66),Diff = 0 PI (0 cell)
8285 06:49:30.989848 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8286 06:49:30.993262 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
8287 06:49:30.996367 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8288 06:49:30.996452
8289 06:49:31.000298 CA PerBit enable=1, Macro0, CA PI delay=36
8290 06:49:31.000385
8291 06:49:31.003357 [CBTSetCACLKResult] CA Dly = 36
8292 06:49:31.006395 CS Dly: 8 (0~39)
8293 06:49:31.009849 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 06:49:31.012964 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 06:49:31.013051 ==
8296 06:49:31.016992 Dram Type= 6, Freq= 0, CH_1, rank 1
8297 06:49:31.019821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 06:49:31.019908 ==
8299 06:49:31.026508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8300 06:49:31.029441 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8301 06:49:31.036174 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8302 06:49:31.039456 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8303 06:49:31.050128 [CA 0] Center 42 (13~72) winsize 60
8304 06:49:31.053458 [CA 1] Center 42 (12~72) winsize 61
8305 06:49:31.056567 [CA 2] Center 38 (9~68) winsize 60
8306 06:49:31.059917 [CA 3] Center 37 (8~67) winsize 60
8307 06:49:31.063197 [CA 4] Center 38 (9~68) winsize 60
8308 06:49:31.066809 [CA 5] Center 37 (8~67) winsize 60
8309 06:49:31.066891
8310 06:49:31.069747 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8311 06:49:31.069828
8312 06:49:31.073348 [CATrainingPosCal] consider 2 rank data
8313 06:49:31.076888 u2DelayCellTimex100 = 290/100 ps
8314 06:49:31.080130 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8315 06:49:31.086781 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8316 06:49:31.089601 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8317 06:49:31.093177 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8318 06:49:31.096746 CA4 delay=37 (9~66),Diff = 0 PI (0 cell)
8319 06:49:31.099614 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8320 06:49:31.099688
8321 06:49:31.103203 CA PerBit enable=1, Macro0, CA PI delay=37
8322 06:49:31.103272
8323 06:49:31.106295 [CBTSetCACLKResult] CA Dly = 37
8324 06:49:31.106394 CS Dly: 9 (0~42)
8325 06:49:31.113123 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8326 06:49:31.116210 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8327 06:49:31.116347
8328 06:49:31.119585 ----->DramcWriteLeveling(PI) begin...
8329 06:49:31.119661 ==
8330 06:49:31.122893 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 06:49:31.126904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 06:49:31.129387 ==
8333 06:49:31.129490 Write leveling (Byte 0): 25 => 25
8334 06:49:31.132694 Write leveling (Byte 1): 28 => 28
8335 06:49:31.136330 DramcWriteLeveling(PI) end<-----
8336 06:49:31.136428
8337 06:49:31.136518 ==
8338 06:49:31.139721 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 06:49:31.146162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 06:49:31.146254 ==
8341 06:49:31.146317 [Gating] SW mode calibration
8342 06:49:31.156337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8343 06:49:31.159541 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8344 06:49:31.162739 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 06:49:31.169303 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 06:49:31.172652 1 4 8 | B1->B0 | 2424 2a2a | 1 1 | (1 1) (1 1)
8347 06:49:31.176171 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 06:49:31.183177 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 06:49:31.186186 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 06:49:31.189552 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 06:49:31.196288 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 06:49:31.199491 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 06:49:31.202810 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8354 06:49:31.209523 1 5 8 | B1->B0 | 3232 3131 | 0 0 | (0 1) (1 0)
8355 06:49:31.213018 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 06:49:31.216061 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 06:49:31.222716 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 06:49:31.226053 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 06:49:31.229169 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 06:49:31.236209 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 06:49:31.239246 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 06:49:31.242568 1 6 8 | B1->B0 | 3838 4343 | 0 1 | (0 0) (0 0)
8363 06:49:31.248929 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 06:49:31.252309 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 06:49:31.255893 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 06:49:31.262262 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 06:49:31.265599 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 06:49:31.269274 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 06:49:31.275857 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8370 06:49:31.279021 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8371 06:49:31.282879 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8372 06:49:31.288844 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 06:49:31.292241 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 06:49:31.295301 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 06:49:31.302222 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 06:49:31.305478 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 06:49:31.308756 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 06:49:31.315093 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 06:49:31.318563 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 06:49:31.321703 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 06:49:31.328889 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 06:49:31.331880 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 06:49:31.335045 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 06:49:31.341863 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 06:49:31.344903 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8386 06:49:31.348124 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8387 06:49:31.354953 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8388 06:49:31.358243 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 06:49:31.361585 Total UI for P1: 0, mck2ui 16
8390 06:49:31.364763 best dqsien dly found for B0: ( 1, 9, 8)
8391 06:49:31.368461 Total UI for P1: 0, mck2ui 16
8392 06:49:31.371898 best dqsien dly found for B1: ( 1, 9, 10)
8393 06:49:31.375250 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8394 06:49:31.378189 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8395 06:49:31.378273
8396 06:49:31.381380 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8397 06:49:31.384904 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8398 06:49:31.388352 [Gating] SW calibration Done
8399 06:49:31.388436 ==
8400 06:49:31.391449 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 06:49:31.394480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 06:49:31.394568 ==
8403 06:49:31.398419 RX Vref Scan: 0
8404 06:49:31.398502
8405 06:49:31.401561 RX Vref 0 -> 0, step: 1
8406 06:49:31.401644
8407 06:49:31.401710 RX Delay 0 -> 252, step: 8
8408 06:49:31.408091 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8409 06:49:31.411341 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8410 06:49:31.414570 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8411 06:49:31.417697 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8412 06:49:31.421063 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8413 06:49:31.427749 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8414 06:49:31.431180 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8415 06:49:31.434471 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8416 06:49:31.437699 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8417 06:49:31.441147 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8418 06:49:31.444899 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8419 06:49:31.450874 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8420 06:49:31.454299 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8421 06:49:31.457749 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8422 06:49:31.460864 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8423 06:49:31.467416 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8424 06:49:31.467501 ==
8425 06:49:31.470799 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 06:49:31.474308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 06:49:31.474393 ==
8428 06:49:31.474459 DQS Delay:
8429 06:49:31.477619 DQS0 = 0, DQS1 = 0
8430 06:49:31.477702 DQM Delay:
8431 06:49:31.480850 DQM0 = 137, DQM1 = 130
8432 06:49:31.480933 DQ Delay:
8433 06:49:31.484072 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8434 06:49:31.487302 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8435 06:49:31.490871 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8436 06:49:31.493989 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8437 06:49:31.494073
8438 06:49:31.497108
8439 06:49:31.497190 ==
8440 06:49:31.500722 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 06:49:31.504113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 06:49:31.504196 ==
8443 06:49:31.504262
8444 06:49:31.504321
8445 06:49:31.507335 TX Vref Scan disable
8446 06:49:31.507418 == TX Byte 0 ==
8447 06:49:31.510740 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8448 06:49:31.517482 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8449 06:49:31.517565 == TX Byte 1 ==
8450 06:49:31.523883 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8451 06:49:31.527200 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8452 06:49:31.527285 ==
8453 06:49:31.530421 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 06:49:31.533476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 06:49:31.533560 ==
8456 06:49:31.546824
8457 06:49:31.550124 TX Vref early break, caculate TX vref
8458 06:49:31.553331 TX Vref=16, minBit 10, minWin=21, winSum=364
8459 06:49:31.556791 TX Vref=18, minBit 10, minWin=22, winSum=377
8460 06:49:31.560122 TX Vref=20, minBit 9, minWin=23, winSum=390
8461 06:49:31.563259 TX Vref=22, minBit 8, minWin=23, winSum=398
8462 06:49:31.566802 TX Vref=24, minBit 9, minWin=24, winSum=409
8463 06:49:31.573315 TX Vref=26, minBit 10, minWin=24, winSum=415
8464 06:49:31.576674 TX Vref=28, minBit 12, minWin=25, winSum=419
8465 06:49:31.580240 TX Vref=30, minBit 10, minWin=24, winSum=414
8466 06:49:31.583091 TX Vref=32, minBit 8, minWin=24, winSum=405
8467 06:49:31.586844 TX Vref=34, minBit 9, minWin=23, winSum=390
8468 06:49:31.593094 [TxChooseVref] Worse bit 12, Min win 25, Win sum 419, Final Vref 28
8469 06:49:31.593178
8470 06:49:31.596815 Final TX Range 0 Vref 28
8471 06:49:31.596899
8472 06:49:31.596964 ==
8473 06:49:31.600262 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 06:49:31.603166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 06:49:31.603249 ==
8476 06:49:31.603315
8477 06:49:31.603376
8478 06:49:31.606598 TX Vref Scan disable
8479 06:49:31.613254 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8480 06:49:31.613337 == TX Byte 0 ==
8481 06:49:31.616266 u2DelayCellOfst[0]=16 cells (5 PI)
8482 06:49:31.619648 u2DelayCellOfst[1]=10 cells (3 PI)
8483 06:49:31.623321 u2DelayCellOfst[2]=0 cells (0 PI)
8484 06:49:31.626641 u2DelayCellOfst[3]=6 cells (2 PI)
8485 06:49:31.629499 u2DelayCellOfst[4]=6 cells (2 PI)
8486 06:49:31.632948 u2DelayCellOfst[5]=16 cells (5 PI)
8487 06:49:31.636131 u2DelayCellOfst[6]=16 cells (5 PI)
8488 06:49:31.639785 u2DelayCellOfst[7]=6 cells (2 PI)
8489 06:49:31.643057 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8490 06:49:31.645847 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8491 06:49:31.649186 == TX Byte 1 ==
8492 06:49:31.653134 u2DelayCellOfst[8]=0 cells (0 PI)
8493 06:49:31.655929 u2DelayCellOfst[9]=3 cells (1 PI)
8494 06:49:31.656002 u2DelayCellOfst[10]=10 cells (3 PI)
8495 06:49:31.659221 u2DelayCellOfst[11]=3 cells (1 PI)
8496 06:49:31.662691 u2DelayCellOfst[12]=16 cells (5 PI)
8497 06:49:31.665783 u2DelayCellOfst[13]=16 cells (5 PI)
8498 06:49:31.669332 u2DelayCellOfst[14]=20 cells (6 PI)
8499 06:49:31.672727 u2DelayCellOfst[15]=16 cells (5 PI)
8500 06:49:31.679007 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8501 06:49:31.682553 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8502 06:49:31.682629 DramC Write-DBI on
8503 06:49:31.682692 ==
8504 06:49:31.685873 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 06:49:31.692564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 06:49:31.692665 ==
8507 06:49:31.692755
8508 06:49:31.692850
8509 06:49:31.692937 TX Vref Scan disable
8510 06:49:31.696578 == TX Byte 0 ==
8511 06:49:31.699991 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8512 06:49:31.702928 == TX Byte 1 ==
8513 06:49:31.706467 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8514 06:49:31.709466 DramC Write-DBI off
8515 06:49:31.709574
8516 06:49:31.709666 [DATLAT]
8517 06:49:31.709754 Freq=1600, CH1 RK0
8518 06:49:31.709850
8519 06:49:31.713308 DATLAT Default: 0xf
8520 06:49:31.713379 0, 0xFFFF, sum = 0
8521 06:49:31.716269 1, 0xFFFF, sum = 0
8522 06:49:31.719625 2, 0xFFFF, sum = 0
8523 06:49:31.719742 3, 0xFFFF, sum = 0
8524 06:49:31.722902 4, 0xFFFF, sum = 0
8525 06:49:31.722987 5, 0xFFFF, sum = 0
8526 06:49:31.726453 6, 0xFFFF, sum = 0
8527 06:49:31.726539 7, 0xFFFF, sum = 0
8528 06:49:31.729775 8, 0xFFFF, sum = 0
8529 06:49:31.729861 9, 0xFFFF, sum = 0
8530 06:49:31.733050 10, 0xFFFF, sum = 0
8531 06:49:31.733135 11, 0xFFFF, sum = 0
8532 06:49:31.736358 12, 0xFFFF, sum = 0
8533 06:49:31.736444 13, 0xFFFF, sum = 0
8534 06:49:31.740158 14, 0x0, sum = 1
8535 06:49:31.740267 15, 0x0, sum = 2
8536 06:49:31.743067 16, 0x0, sum = 3
8537 06:49:31.743153 17, 0x0, sum = 4
8538 06:49:31.746236 best_step = 15
8539 06:49:31.746320
8540 06:49:31.746387 ==
8541 06:49:31.749320 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 06:49:31.752805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 06:49:31.752889 ==
8544 06:49:31.756344 RX Vref Scan: 1
8545 06:49:31.756428
8546 06:49:31.756494 Set Vref Range= 24 -> 127
8547 06:49:31.756557
8548 06:49:31.759275 RX Vref 24 -> 127, step: 1
8549 06:49:31.759394
8550 06:49:31.762698 RX Delay 19 -> 252, step: 4
8551 06:49:31.762782
8552 06:49:31.766403 Set Vref, RX VrefLevel [Byte0]: 24
8553 06:49:31.769491 [Byte1]: 24
8554 06:49:31.769583
8555 06:49:31.772810 Set Vref, RX VrefLevel [Byte0]: 25
8556 06:49:31.775875 [Byte1]: 25
8557 06:49:31.775961
8558 06:49:31.779403 Set Vref, RX VrefLevel [Byte0]: 26
8559 06:49:31.782335 [Byte1]: 26
8560 06:49:31.786701
8561 06:49:31.786777 Set Vref, RX VrefLevel [Byte0]: 27
8562 06:49:31.789896 [Byte1]: 27
8563 06:49:31.794259
8564 06:49:31.794350 Set Vref, RX VrefLevel [Byte0]: 28
8565 06:49:31.797339 [Byte1]: 28
8566 06:49:31.802018
8567 06:49:31.802097 Set Vref, RX VrefLevel [Byte0]: 29
8568 06:49:31.805251 [Byte1]: 29
8569 06:49:31.809345
8570 06:49:31.809421 Set Vref, RX VrefLevel [Byte0]: 30
8571 06:49:31.812696 [Byte1]: 30
8572 06:49:31.817034
8573 06:49:31.817119 Set Vref, RX VrefLevel [Byte0]: 31
8574 06:49:31.820278 [Byte1]: 31
8575 06:49:31.824762
8576 06:49:31.824884 Set Vref, RX VrefLevel [Byte0]: 32
8577 06:49:31.827933 [Byte1]: 32
8578 06:49:31.832084
8579 06:49:31.832173 Set Vref, RX VrefLevel [Byte0]: 33
8580 06:49:31.835549 [Byte1]: 33
8581 06:49:31.839805
8582 06:49:31.839894 Set Vref, RX VrefLevel [Byte0]: 34
8583 06:49:31.842850 [Byte1]: 34
8584 06:49:31.847448
8585 06:49:31.847531 Set Vref, RX VrefLevel [Byte0]: 35
8586 06:49:31.850812 [Byte1]: 35
8587 06:49:31.854705
8588 06:49:31.854789 Set Vref, RX VrefLevel [Byte0]: 36
8589 06:49:31.858108 [Byte1]: 36
8590 06:49:31.862609
8591 06:49:31.862693 Set Vref, RX VrefLevel [Byte0]: 37
8592 06:49:31.865550 [Byte1]: 37
8593 06:49:31.870092
8594 06:49:31.870177 Set Vref, RX VrefLevel [Byte0]: 38
8595 06:49:31.873359 [Byte1]: 38
8596 06:49:31.877652
8597 06:49:31.877737 Set Vref, RX VrefLevel [Byte0]: 39
8598 06:49:31.880679 [Byte1]: 39
8599 06:49:31.885122
8600 06:49:31.885206 Set Vref, RX VrefLevel [Byte0]: 40
8601 06:49:31.888828 [Byte1]: 40
8602 06:49:31.892718
8603 06:49:31.892820 Set Vref, RX VrefLevel [Byte0]: 41
8604 06:49:31.895850 [Byte1]: 41
8605 06:49:31.900215
8606 06:49:31.900316 Set Vref, RX VrefLevel [Byte0]: 42
8607 06:49:31.903481 [Byte1]: 42
8608 06:49:31.908018
8609 06:49:31.908121 Set Vref, RX VrefLevel [Byte0]: 43
8610 06:49:31.911167 [Byte1]: 43
8611 06:49:31.915611
8612 06:49:31.915686 Set Vref, RX VrefLevel [Byte0]: 44
8613 06:49:31.918820 [Byte1]: 44
8614 06:49:31.922910
8615 06:49:31.923011 Set Vref, RX VrefLevel [Byte0]: 45
8616 06:49:31.926355 [Byte1]: 45
8617 06:49:31.930867
8618 06:49:31.930950 Set Vref, RX VrefLevel [Byte0]: 46
8619 06:49:31.934006 [Byte1]: 46
8620 06:49:31.937921
8621 06:49:31.938006 Set Vref, RX VrefLevel [Byte0]: 47
8622 06:49:31.941472 [Byte1]: 47
8623 06:49:31.945646
8624 06:49:31.945748 Set Vref, RX VrefLevel [Byte0]: 48
8625 06:49:31.948759 [Byte1]: 48
8626 06:49:31.953129
8627 06:49:31.953230 Set Vref, RX VrefLevel [Byte0]: 49
8628 06:49:31.956695 [Byte1]: 49
8629 06:49:31.961063
8630 06:49:31.961142 Set Vref, RX VrefLevel [Byte0]: 50
8631 06:49:31.963962 [Byte1]: 50
8632 06:49:31.968529
8633 06:49:31.968631 Set Vref, RX VrefLevel [Byte0]: 51
8634 06:49:31.971830 [Byte1]: 51
8635 06:49:31.975983
8636 06:49:31.976056 Set Vref, RX VrefLevel [Byte0]: 52
8637 06:49:31.979419 [Byte1]: 52
8638 06:49:31.983833
8639 06:49:31.983909 Set Vref, RX VrefLevel [Byte0]: 53
8640 06:49:31.987028 [Byte1]: 53
8641 06:49:31.991035
8642 06:49:31.991114 Set Vref, RX VrefLevel [Byte0]: 54
8643 06:49:31.994383 [Byte1]: 54
8644 06:49:31.998506
8645 06:49:31.998581 Set Vref, RX VrefLevel [Byte0]: 55
8646 06:49:32.001999 [Byte1]: 55
8647 06:49:32.006298
8648 06:49:32.006402 Set Vref, RX VrefLevel [Byte0]: 56
8649 06:49:32.009330 [Byte1]: 56
8650 06:49:32.013884
8651 06:49:32.014015 Set Vref, RX VrefLevel [Byte0]: 57
8652 06:49:32.016964 [Byte1]: 57
8653 06:49:32.021691
8654 06:49:32.021792 Set Vref, RX VrefLevel [Byte0]: 58
8655 06:49:32.024698 [Byte1]: 58
8656 06:49:32.029195
8657 06:49:32.029313 Set Vref, RX VrefLevel [Byte0]: 59
8658 06:49:32.032450 [Byte1]: 59
8659 06:49:32.036628
8660 06:49:32.036732 Set Vref, RX VrefLevel [Byte0]: 60
8661 06:49:32.039769 [Byte1]: 60
8662 06:49:32.044038
8663 06:49:32.044144 Set Vref, RX VrefLevel [Byte0]: 61
8664 06:49:32.047326 [Byte1]: 61
8665 06:49:32.051745
8666 06:49:32.051828 Set Vref, RX VrefLevel [Byte0]: 62
8667 06:49:32.055244 [Byte1]: 62
8668 06:49:32.059379
8669 06:49:32.059451 Set Vref, RX VrefLevel [Byte0]: 63
8670 06:49:32.062581 [Byte1]: 63
8671 06:49:32.067130
8672 06:49:32.067203 Set Vref, RX VrefLevel [Byte0]: 64
8673 06:49:32.070431 [Byte1]: 64
8674 06:49:32.074455
8675 06:49:32.074556 Set Vref, RX VrefLevel [Byte0]: 65
8676 06:49:32.077870 [Byte1]: 65
8677 06:49:32.082034
8678 06:49:32.082133 Set Vref, RX VrefLevel [Byte0]: 66
8679 06:49:32.085196 [Byte1]: 66
8680 06:49:32.089707
8681 06:49:32.089805 Set Vref, RX VrefLevel [Byte0]: 67
8682 06:49:32.092794 [Byte1]: 67
8683 06:49:32.097304
8684 06:49:32.097404 Set Vref, RX VrefLevel [Byte0]: 68
8685 06:49:32.100243 [Byte1]: 68
8686 06:49:32.104713
8687 06:49:32.104814 Set Vref, RX VrefLevel [Byte0]: 69
8688 06:49:32.107928 [Byte1]: 69
8689 06:49:32.112299
8690 06:49:32.112403 Set Vref, RX VrefLevel [Byte0]: 70
8691 06:49:32.115604 [Byte1]: 70
8692 06:49:32.119831
8693 06:49:32.119903 Set Vref, RX VrefLevel [Byte0]: 71
8694 06:49:32.123369 [Byte1]: 71
8695 06:49:32.127639
8696 06:49:32.127741 Set Vref, RX VrefLevel [Byte0]: 72
8697 06:49:32.130697 [Byte1]: 72
8698 06:49:32.134907
8699 06:49:32.134992 Set Vref, RX VrefLevel [Byte0]: 73
8700 06:49:32.138397 [Byte1]: 73
8701 06:49:32.142781
8702 06:49:32.142858 Set Vref, RX VrefLevel [Byte0]: 74
8703 06:49:32.145893 [Byte1]: 74
8704 06:49:32.150035
8705 06:49:32.150115 Set Vref, RX VrefLevel [Byte0]: 75
8706 06:49:32.153661 [Byte1]: 75
8707 06:49:32.157614
8708 06:49:32.157719 Set Vref, RX VrefLevel [Byte0]: 76
8709 06:49:32.161259 [Byte1]: 76
8710 06:49:32.165570
8711 06:49:32.165674 Set Vref, RX VrefLevel [Byte0]: 77
8712 06:49:32.168816 [Byte1]: 77
8713 06:49:32.172687
8714 06:49:32.172761 Final RX Vref Byte 0 = 57 to rank0
8715 06:49:32.176258 Final RX Vref Byte 1 = 63 to rank0
8716 06:49:32.179873 Final RX Vref Byte 0 = 57 to rank1
8717 06:49:32.182988 Final RX Vref Byte 1 = 63 to rank1==
8718 06:49:32.186290 Dram Type= 6, Freq= 0, CH_1, rank 0
8719 06:49:32.193002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8720 06:49:32.193090 ==
8721 06:49:32.193157 DQS Delay:
8722 06:49:32.193253 DQS0 = 0, DQS1 = 0
8723 06:49:32.196218 DQM Delay:
8724 06:49:32.196302 DQM0 = 133, DQM1 = 129
8725 06:49:32.199772 DQ Delay:
8726 06:49:32.202729 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8727 06:49:32.206340 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
8728 06:49:32.209761 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122
8729 06:49:32.213287 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =136
8730 06:49:32.213372
8731 06:49:32.213460
8732 06:49:32.213571
8733 06:49:32.216449 [DramC_TX_OE_Calibration] TA2
8734 06:49:32.219271 Original DQ_B0 (3 6) =30, OEN = 27
8735 06:49:32.222683 Original DQ_B1 (3 6) =30, OEN = 27
8736 06:49:32.225888 24, 0x0, End_B0=24 End_B1=24
8737 06:49:32.226001 25, 0x0, End_B0=25 End_B1=25
8738 06:49:32.229637 26, 0x0, End_B0=26 End_B1=26
8739 06:49:32.232758 27, 0x0, End_B0=27 End_B1=27
8740 06:49:32.236493 28, 0x0, End_B0=28 End_B1=28
8741 06:49:32.236579 29, 0x0, End_B0=29 End_B1=29
8742 06:49:32.239318 30, 0x0, End_B0=30 End_B1=30
8743 06:49:32.242857 31, 0x5151, End_B0=30 End_B1=30
8744 06:49:32.246324 Byte0 end_step=30 best_step=27
8745 06:49:32.249369 Byte1 end_step=30 best_step=27
8746 06:49:32.252776 Byte0 TX OE(2T, 0.5T) = (3, 3)
8747 06:49:32.252861 Byte1 TX OE(2T, 0.5T) = (3, 3)
8748 06:49:32.256130
8749 06:49:32.256214
8750 06:49:32.262790 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8751 06:49:32.266355 CH1 RK0: MR19=303, MR18=1A28
8752 06:49:32.272961 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8753 06:49:32.273039
8754 06:49:32.276290 ----->DramcWriteLeveling(PI) begin...
8755 06:49:32.276373 ==
8756 06:49:32.279518 Dram Type= 6, Freq= 0, CH_1, rank 1
8757 06:49:32.282451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 06:49:32.282525 ==
8759 06:49:32.285893 Write leveling (Byte 0): 24 => 24
8760 06:49:32.289286 Write leveling (Byte 1): 29 => 29
8761 06:49:32.293232 DramcWriteLeveling(PI) end<-----
8762 06:49:32.293334
8763 06:49:32.293435 ==
8764 06:49:32.296025 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 06:49:32.299347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 06:49:32.299424 ==
8767 06:49:32.302610 [Gating] SW mode calibration
8768 06:49:32.309329 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8769 06:49:32.316125 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8770 06:49:32.319557 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 06:49:32.322884 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 06:49:32.329338 1 4 8 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
8773 06:49:32.332688 1 4 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 1)
8774 06:49:32.336224 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 06:49:32.342524 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 06:49:32.345780 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 06:49:32.349146 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 06:49:32.355795 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 06:49:32.358920 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8780 06:49:32.362409 1 5 8 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
8781 06:49:32.369146 1 5 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
8782 06:49:32.372355 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 06:49:32.375846 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 06:49:32.382229 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 06:49:32.385442 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 06:49:32.388991 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 06:49:32.395248 1 6 4 | B1->B0 | 2524 2323 | 1 0 | (1 1) (0 0)
8788 06:49:32.398781 1 6 8 | B1->B0 | 4343 2323 | 0 0 | (0 0) (0 0)
8789 06:49:32.402076 1 6 12 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
8790 06:49:32.408736 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 06:49:32.412310 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 06:49:32.415680 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 06:49:32.418756 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 06:49:32.425786 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 06:49:32.428669 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 06:49:32.432154 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8797 06:49:32.438761 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8798 06:49:32.442149 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 06:49:32.445700 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 06:49:32.452015 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 06:49:32.455338 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 06:49:32.458640 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 06:49:32.465217 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 06:49:32.468735 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 06:49:32.472382 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 06:49:32.478489 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 06:49:32.481920 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 06:49:32.485346 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 06:49:32.492202 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 06:49:32.495133 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 06:49:32.498586 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 06:49:32.504953 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8813 06:49:32.508459 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 06:49:32.511880 Total UI for P1: 0, mck2ui 16
8815 06:49:32.515184 best dqsien dly found for B0: ( 1, 9, 8)
8816 06:49:32.518233 Total UI for P1: 0, mck2ui 16
8817 06:49:32.521509 best dqsien dly found for B1: ( 1, 9, 8)
8818 06:49:32.524884 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8819 06:49:32.528124 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8820 06:49:32.528207
8821 06:49:32.531568 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8822 06:49:32.535037 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8823 06:49:32.538501 [Gating] SW calibration Done
8824 06:49:32.538583 ==
8825 06:49:32.542078 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 06:49:32.544821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 06:49:32.544904 ==
8828 06:49:32.548143 RX Vref Scan: 0
8829 06:49:32.548225
8830 06:49:32.551584 RX Vref 0 -> 0, step: 1
8831 06:49:32.551692
8832 06:49:32.551786 RX Delay 0 -> 252, step: 8
8833 06:49:32.558105 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8834 06:49:32.561736 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8835 06:49:32.564790 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8836 06:49:32.568127 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8837 06:49:32.571495 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8838 06:49:32.578038 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8839 06:49:32.581435 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8840 06:49:32.584738 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8841 06:49:32.587982 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8842 06:49:32.591282 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8843 06:49:32.598067 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8844 06:49:32.601315 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8845 06:49:32.604972 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8846 06:49:32.608190 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8847 06:49:32.611198 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8848 06:49:32.617926 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8849 06:49:32.618047 ==
8850 06:49:32.621216 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 06:49:32.624581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 06:49:32.624665 ==
8853 06:49:32.624736 DQS Delay:
8854 06:49:32.627811 DQS0 = 0, DQS1 = 0
8855 06:49:32.627899 DQM Delay:
8856 06:49:32.631052 DQM0 = 135, DQM1 = 132
8857 06:49:32.631135 DQ Delay:
8858 06:49:32.634484 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8859 06:49:32.637787 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8860 06:49:32.640947 DQ8 =115, DQ9 =123, DQ10 =131, DQ11 =127
8861 06:49:32.644626 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =143
8862 06:49:32.648133
8863 06:49:32.648221
8864 06:49:32.648287 ==
8865 06:49:32.650888 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 06:49:32.654255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 06:49:32.654340 ==
8868 06:49:32.654407
8869 06:49:32.654469
8870 06:49:32.657811 TX Vref Scan disable
8871 06:49:32.657895 == TX Byte 0 ==
8872 06:49:32.664613 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8873 06:49:32.667625 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8874 06:49:32.667710 == TX Byte 1 ==
8875 06:49:32.673865 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8876 06:49:32.677481 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8877 06:49:32.677566 ==
8878 06:49:32.680722 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 06:49:32.683934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 06:49:32.684032 ==
8881 06:49:32.697802
8882 06:49:32.701247 TX Vref early break, caculate TX vref
8883 06:49:32.704587 TX Vref=16, minBit 9, minWin=21, winSum=378
8884 06:49:32.707805 TX Vref=18, minBit 10, minWin=22, winSum=385
8885 06:49:32.711472 TX Vref=20, minBit 9, minWin=23, winSum=395
8886 06:49:32.714963 TX Vref=22, minBit 8, minWin=23, winSum=402
8887 06:49:32.718468 TX Vref=24, minBit 9, minWin=24, winSum=411
8888 06:49:32.724735 TX Vref=26, minBit 10, minWin=24, winSum=413
8889 06:49:32.727867 TX Vref=28, minBit 8, minWin=25, winSum=420
8890 06:49:32.731461 TX Vref=30, minBit 10, minWin=24, winSum=413
8891 06:49:32.734458 TX Vref=32, minBit 0, minWin=24, winSum=403
8892 06:49:32.737963 TX Vref=34, minBit 0, minWin=24, winSum=398
8893 06:49:32.744392 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 28
8894 06:49:32.744482
8895 06:49:32.748233 Final TX Range 0 Vref 28
8896 06:49:32.748317
8897 06:49:32.748384 ==
8898 06:49:32.750985 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 06:49:32.754594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 06:49:32.754684 ==
8901 06:49:32.754750
8902 06:49:32.754810
8903 06:49:32.757900 TX Vref Scan disable
8904 06:49:32.764536 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8905 06:49:32.764624 == TX Byte 0 ==
8906 06:49:32.767817 u2DelayCellOfst[0]=16 cells (5 PI)
8907 06:49:32.771191 u2DelayCellOfst[1]=13 cells (4 PI)
8908 06:49:32.774575 u2DelayCellOfst[2]=0 cells (0 PI)
8909 06:49:32.777827 u2DelayCellOfst[3]=6 cells (2 PI)
8910 06:49:32.781335 u2DelayCellOfst[4]=10 cells (3 PI)
8911 06:49:32.784840 u2DelayCellOfst[5]=20 cells (6 PI)
8912 06:49:32.787716 u2DelayCellOfst[6]=20 cells (6 PI)
8913 06:49:32.791303 u2DelayCellOfst[7]=6 cells (2 PI)
8914 06:49:32.794764 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8915 06:49:32.797785 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8916 06:49:32.797868 == TX Byte 1 ==
8917 06:49:32.801158 u2DelayCellOfst[8]=0 cells (0 PI)
8918 06:49:32.804795 u2DelayCellOfst[9]=3 cells (1 PI)
8919 06:49:32.807710 u2DelayCellOfst[10]=10 cells (3 PI)
8920 06:49:32.811168 u2DelayCellOfst[11]=3 cells (1 PI)
8921 06:49:32.814604 u2DelayCellOfst[12]=13 cells (4 PI)
8922 06:49:32.817822 u2DelayCellOfst[13]=13 cells (4 PI)
8923 06:49:32.821324 u2DelayCellOfst[14]=20 cells (6 PI)
8924 06:49:32.824403 u2DelayCellOfst[15]=16 cells (5 PI)
8925 06:49:32.827977 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8926 06:49:32.834354 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8927 06:49:32.834439 DramC Write-DBI on
8928 06:49:32.834505 ==
8929 06:49:32.837407 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 06:49:32.840795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 06:49:32.844255 ==
8932 06:49:32.844338
8933 06:49:32.844404
8934 06:49:32.844466 TX Vref Scan disable
8935 06:49:32.847818 == TX Byte 0 ==
8936 06:49:32.850743 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8937 06:49:32.854421 == TX Byte 1 ==
8938 06:49:32.857374 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8939 06:49:32.860847 DramC Write-DBI off
8940 06:49:32.860930
8941 06:49:32.860996 [DATLAT]
8942 06:49:32.861058 Freq=1600, CH1 RK1
8943 06:49:32.861118
8944 06:49:32.864288 DATLAT Default: 0xf
8945 06:49:32.864371 0, 0xFFFF, sum = 0
8946 06:49:32.867436 1, 0xFFFF, sum = 0
8947 06:49:32.870803 2, 0xFFFF, sum = 0
8948 06:49:32.870887 3, 0xFFFF, sum = 0
8949 06:49:32.874047 4, 0xFFFF, sum = 0
8950 06:49:32.874131 5, 0xFFFF, sum = 0
8951 06:49:32.877510 6, 0xFFFF, sum = 0
8952 06:49:32.877595 7, 0xFFFF, sum = 0
8953 06:49:32.880704 8, 0xFFFF, sum = 0
8954 06:49:32.880789 9, 0xFFFF, sum = 0
8955 06:49:32.884002 10, 0xFFFF, sum = 0
8956 06:49:32.884086 11, 0xFFFF, sum = 0
8957 06:49:32.887249 12, 0xFFFF, sum = 0
8958 06:49:32.887333 13, 0xFFFF, sum = 0
8959 06:49:32.890679 14, 0x0, sum = 1
8960 06:49:32.890764 15, 0x0, sum = 2
8961 06:49:32.894085 16, 0x0, sum = 3
8962 06:49:32.894168 17, 0x0, sum = 4
8963 06:49:32.897070 best_step = 15
8964 06:49:32.897153
8965 06:49:32.897219 ==
8966 06:49:32.900794 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 06:49:32.903765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 06:49:32.903850 ==
8969 06:49:32.907342 RX Vref Scan: 0
8970 06:49:32.907424
8971 06:49:32.907490 RX Vref 0 -> 0, step: 1
8972 06:49:32.907552
8973 06:49:32.910553 RX Delay 19 -> 252, step: 4
8974 06:49:32.913644 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8975 06:49:32.920509 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8976 06:49:32.923715 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8977 06:49:32.927229 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8978 06:49:32.930408 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8979 06:49:32.933494 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8980 06:49:32.940444 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8981 06:49:32.943858 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8982 06:49:32.947001 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
8983 06:49:32.950250 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8984 06:49:32.953598 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8985 06:49:32.959992 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8986 06:49:32.963937 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8987 06:49:32.966827 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8988 06:49:32.970125 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8989 06:49:32.973573 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8990 06:49:32.973657 ==
8991 06:49:32.976963 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 06:49:32.983731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 06:49:32.983816 ==
8994 06:49:32.983882 DQS Delay:
8995 06:49:32.986979 DQS0 = 0, DQS1 = 0
8996 06:49:32.987063 DQM Delay:
8997 06:49:32.989959 DQM0 = 133, DQM1 = 130
8998 06:49:32.990057 DQ Delay:
8999 06:49:32.993672 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9000 06:49:32.996702 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9001 06:49:32.999969 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =126
9002 06:49:33.003455 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =142
9003 06:49:33.003538
9004 06:49:33.003604
9005 06:49:33.003665
9006 06:49:33.006618 [DramC_TX_OE_Calibration] TA2
9007 06:49:33.009884 Original DQ_B0 (3 6) =30, OEN = 27
9008 06:49:33.013486 Original DQ_B1 (3 6) =30, OEN = 27
9009 06:49:33.016937 24, 0x0, End_B0=24 End_B1=24
9010 06:49:33.019804 25, 0x0, End_B0=25 End_B1=25
9011 06:49:33.019888 26, 0x0, End_B0=26 End_B1=26
9012 06:49:33.023018 27, 0x0, End_B0=27 End_B1=27
9013 06:49:33.026574 28, 0x0, End_B0=28 End_B1=28
9014 06:49:33.030154 29, 0x0, End_B0=29 End_B1=29
9015 06:49:33.030239 30, 0x0, End_B0=30 End_B1=30
9016 06:49:33.033310 31, 0x4141, End_B0=30 End_B1=30
9017 06:49:33.036342 Byte0 end_step=30 best_step=27
9018 06:49:33.040045 Byte1 end_step=30 best_step=27
9019 06:49:33.043070 Byte0 TX OE(2T, 0.5T) = (3, 3)
9020 06:49:33.046584 Byte1 TX OE(2T, 0.5T) = (3, 3)
9021 06:49:33.046668
9022 06:49:33.046733
9023 06:49:33.053001 [DQSOSCAuto] RK1, (LSB)MR18= 0x1905, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 397 ps
9024 06:49:33.056325 CH1 RK1: MR19=303, MR18=1905
9025 06:49:33.063069 CH1_RK1: MR19=0x303, MR18=0x1905, DQSOSC=397, MR23=63, INC=23, DEC=15
9026 06:49:33.066430 [RxdqsGatingPostProcess] freq 1600
9027 06:49:33.069829 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9028 06:49:33.072950 best DQS0 dly(2T, 0.5T) = (1, 1)
9029 06:49:33.076412 best DQS1 dly(2T, 0.5T) = (1, 1)
9030 06:49:33.079584 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9031 06:49:33.082916 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9032 06:49:33.086121 best DQS0 dly(2T, 0.5T) = (1, 1)
9033 06:49:33.089476 best DQS1 dly(2T, 0.5T) = (1, 1)
9034 06:49:33.093077 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9035 06:49:33.096441 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9036 06:49:33.099419 Pre-setting of DQS Precalculation
9037 06:49:33.102751 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9038 06:49:33.109701 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9039 06:49:33.119736 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9040 06:49:33.119868
9041 06:49:33.119935
9042 06:49:33.123092 [Calibration Summary] 3200 Mbps
9043 06:49:33.123175 CH 0, Rank 0
9044 06:49:33.125860 SW Impedance : PASS
9045 06:49:33.125989 DUTY Scan : NO K
9046 06:49:33.129287 ZQ Calibration : PASS
9047 06:49:33.132929 Jitter Meter : NO K
9048 06:49:33.133010 CBT Training : PASS
9049 06:49:33.136200 Write leveling : PASS
9050 06:49:33.136285 RX DQS gating : PASS
9051 06:49:33.139380 RX DQ/DQS(RDDQC) : PASS
9052 06:49:33.143024 TX DQ/DQS : PASS
9053 06:49:33.143108 RX DATLAT : PASS
9054 06:49:33.146382 RX DQ/DQS(Engine): PASS
9055 06:49:33.149178 TX OE : PASS
9056 06:49:33.149287 All Pass.
9057 06:49:33.149386
9058 06:49:33.149476 CH 0, Rank 1
9059 06:49:33.152858 SW Impedance : PASS
9060 06:49:33.155810 DUTY Scan : NO K
9061 06:49:33.155894 ZQ Calibration : PASS
9062 06:49:33.159432 Jitter Meter : NO K
9063 06:49:33.162650 CBT Training : PASS
9064 06:49:33.162733 Write leveling : PASS
9065 06:49:33.166250 RX DQS gating : PASS
9066 06:49:33.169513 RX DQ/DQS(RDDQC) : PASS
9067 06:49:33.169683 TX DQ/DQS : PASS
9068 06:49:33.172874 RX DATLAT : PASS
9069 06:49:33.175996 RX DQ/DQS(Engine): PASS
9070 06:49:33.176069 TX OE : PASS
9071 06:49:33.176132 All Pass.
9072 06:49:33.179452
9073 06:49:33.179537 CH 1, Rank 0
9074 06:49:33.182494 SW Impedance : PASS
9075 06:49:33.182580 DUTY Scan : NO K
9076 06:49:33.185947 ZQ Calibration : PASS
9077 06:49:33.186033 Jitter Meter : NO K
9078 06:49:33.189683 CBT Training : PASS
9079 06:49:33.192396 Write leveling : PASS
9080 06:49:33.192512 RX DQS gating : PASS
9081 06:49:33.195910 RX DQ/DQS(RDDQC) : PASS
9082 06:49:33.199075 TX DQ/DQS : PASS
9083 06:49:33.199201 RX DATLAT : PASS
9084 06:49:33.202834 RX DQ/DQS(Engine): PASS
9085 06:49:33.205876 TX OE : PASS
9086 06:49:33.205981 All Pass.
9087 06:49:33.206048
9088 06:49:33.206138 CH 1, Rank 1
9089 06:49:33.209308 SW Impedance : PASS
9090 06:49:33.212318 DUTY Scan : NO K
9091 06:49:33.212422 ZQ Calibration : PASS
9092 06:49:33.215997 Jitter Meter : NO K
9093 06:49:33.219021 CBT Training : PASS
9094 06:49:33.219107 Write leveling : PASS
9095 06:49:33.222491 RX DQS gating : PASS
9096 06:49:33.225355 RX DQ/DQS(RDDQC) : PASS
9097 06:49:33.225466 TX DQ/DQS : PASS
9098 06:49:33.229139 RX DATLAT : PASS
9099 06:49:33.232845 RX DQ/DQS(Engine): PASS
9100 06:49:33.232932 TX OE : PASS
9101 06:49:33.232999 All Pass.
9102 06:49:33.235871
9103 06:49:33.235956 DramC Write-DBI on
9104 06:49:33.239008 PER_BANK_REFRESH: Hybrid Mode
9105 06:49:33.239093 TX_TRACKING: ON
9106 06:49:33.248735 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9107 06:49:33.255658 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9108 06:49:33.265445 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9109 06:49:33.268734 [FAST_K] Save calibration result to emmc
9110 06:49:33.271883 sync common calibartion params.
9111 06:49:33.271963 sync cbt_mode0:1, 1:1
9112 06:49:33.275181 dram_init: ddr_geometry: 2
9113 06:49:33.279059 dram_init: ddr_geometry: 2
9114 06:49:33.279139 dram_init: ddr_geometry: 2
9115 06:49:33.282152 0:dram_rank_size:100000000
9116 06:49:33.285152 1:dram_rank_size:100000000
9117 06:49:33.288843 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9118 06:49:33.291840 DFS_SHUFFLE_HW_MODE: ON
9119 06:49:33.295421 dramc_set_vcore_voltage set vcore to 725000
9120 06:49:33.298600 Read voltage for 1600, 0
9121 06:49:33.298676 Vio18 = 0
9122 06:49:33.302036 Vcore = 725000
9123 06:49:33.302111 Vdram = 0
9124 06:49:33.302174 Vddq = 0
9125 06:49:33.305051 Vmddr = 0
9126 06:49:33.305161 switch to 3200 Mbps bootup
9127 06:49:33.308295 [DramcRunTimeConfig]
9128 06:49:33.308370 PHYPLL
9129 06:49:33.311653 DPM_CONTROL_AFTERK: ON
9130 06:49:33.311760 PER_BANK_REFRESH: ON
9131 06:49:33.315091 REFRESH_OVERHEAD_REDUCTION: ON
9132 06:49:33.318153 CMD_PICG_NEW_MODE: OFF
9133 06:49:33.318234 XRTWTW_NEW_MODE: ON
9134 06:49:33.321556 XRTRTR_NEW_MODE: ON
9135 06:49:33.321627 TX_TRACKING: ON
9136 06:49:33.325155 RDSEL_TRACKING: OFF
9137 06:49:33.328408 DQS Precalculation for DVFS: ON
9138 06:49:33.328494 RX_TRACKING: OFF
9139 06:49:33.331599 HW_GATING DBG: ON
9140 06:49:33.331686 ZQCS_ENABLE_LP4: ON
9141 06:49:33.335065 RX_PICG_NEW_MODE: ON
9142 06:49:33.335151 TX_PICG_NEW_MODE: ON
9143 06:49:33.338569 ENABLE_RX_DCM_DPHY: ON
9144 06:49:33.341479 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9145 06:49:33.344889 DUMMY_READ_FOR_TRACKING: OFF
9146 06:49:33.344991 !!! SPM_CONTROL_AFTERK: OFF
9147 06:49:33.348125 !!! SPM could not control APHY
9148 06:49:33.352186 IMPEDANCE_TRACKING: ON
9149 06:49:33.352265 TEMP_SENSOR: ON
9150 06:49:33.354783 HW_SAVE_FOR_SR: OFF
9151 06:49:33.358136 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9152 06:49:33.361726 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9153 06:49:33.361807 Read ODT Tracking: ON
9154 06:49:33.364743 Refresh Rate DeBounce: ON
9155 06:49:33.368140 DFS_NO_QUEUE_FLUSH: ON
9156 06:49:33.371719 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9157 06:49:33.371800 ENABLE_DFS_RUNTIME_MRW: OFF
9158 06:49:33.374854 DDR_RESERVE_NEW_MODE: ON
9159 06:49:33.377995 MR_CBT_SWITCH_FREQ: ON
9160 06:49:33.378072 =========================
9161 06:49:33.398504 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9162 06:49:33.402088 dram_init: ddr_geometry: 2
9163 06:49:33.420152 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9164 06:49:33.423241 dram_init: dram init end (result: 0)
9165 06:49:33.429711 DRAM-K: Full calibration passed in 24516 msecs
9166 06:49:33.433310 MRC: failed to locate region type 0.
9167 06:49:33.433424 DRAM rank0 size:0x100000000,
9168 06:49:33.436527 DRAM rank1 size=0x100000000
9169 06:49:33.446336 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9170 06:49:33.453251 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9171 06:49:33.459670 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9172 06:49:33.466654 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9173 06:49:33.469881 DRAM rank0 size:0x100000000,
9174 06:49:33.473179 DRAM rank1 size=0x100000000
9175 06:49:33.473265 CBMEM:
9176 06:49:33.476384 IMD: root @ 0xfffff000 254 entries.
9177 06:49:33.479962 IMD: root @ 0xffffec00 62 entries.
9178 06:49:33.483183 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9179 06:49:33.486619 WARNING: RO_VPD is uninitialized or empty.
9180 06:49:33.492992 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9181 06:49:33.499885 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9182 06:49:33.512741 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9183 06:49:33.524044 BS: romstage times (exec / console): total (unknown) / 24011 ms
9184 06:49:33.524161
9185 06:49:33.524264
9186 06:49:33.534294 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9187 06:49:33.537960 ARM64: Exception handlers installed.
9188 06:49:33.540641 ARM64: Testing exception
9189 06:49:33.543921 ARM64: Done test exception
9190 06:49:33.544006 Enumerating buses...
9191 06:49:33.547457 Show all devs... Before device enumeration.
9192 06:49:33.550936 Root Device: enabled 1
9193 06:49:33.554415 CPU_CLUSTER: 0: enabled 1
9194 06:49:33.554495 CPU: 00: enabled 1
9195 06:49:33.557441 Compare with tree...
9196 06:49:33.557514 Root Device: enabled 1
9197 06:49:33.560998 CPU_CLUSTER: 0: enabled 1
9198 06:49:33.564001 CPU: 00: enabled 1
9199 06:49:33.564106 Root Device scanning...
9200 06:49:33.567367 scan_static_bus for Root Device
9201 06:49:33.570827 CPU_CLUSTER: 0 enabled
9202 06:49:33.574174 scan_static_bus for Root Device done
9203 06:49:33.577316 scan_bus: bus Root Device finished in 8 msecs
9204 06:49:33.577394 done
9205 06:49:33.584057 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9206 06:49:33.587179 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9207 06:49:33.593645 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9208 06:49:33.597504 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9209 06:49:33.600450 Allocating resources...
9210 06:49:33.603880 Reading resources...
9211 06:49:33.607171 Root Device read_resources bus 0 link: 0
9212 06:49:33.607254 DRAM rank0 size:0x100000000,
9213 06:49:33.610558 DRAM rank1 size=0x100000000
9214 06:49:33.613665 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9215 06:49:33.617158 CPU: 00 missing read_resources
9216 06:49:33.620271 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9217 06:49:33.626681 Root Device read_resources bus 0 link: 0 done
9218 06:49:33.626763 Done reading resources.
9219 06:49:33.633583 Show resources in subtree (Root Device)...After reading.
9220 06:49:33.636563 Root Device child on link 0 CPU_CLUSTER: 0
9221 06:49:33.639884 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 06:49:33.650137 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 06:49:33.650220 CPU: 00
9224 06:49:33.653322 Root Device assign_resources, bus 0 link: 0
9225 06:49:33.656878 CPU_CLUSTER: 0 missing set_resources
9226 06:49:33.663632 Root Device assign_resources, bus 0 link: 0 done
9227 06:49:33.663716 Done setting resources.
9228 06:49:33.669828 Show resources in subtree (Root Device)...After assigning values.
9229 06:49:33.673515 Root Device child on link 0 CPU_CLUSTER: 0
9230 06:49:33.676767 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 06:49:33.686850 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 06:49:33.686935 CPU: 00
9233 06:49:33.690284 Done allocating resources.
9234 06:49:33.693396 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9235 06:49:33.696453 Enabling resources...
9236 06:49:33.696530 done.
9237 06:49:33.703440 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9238 06:49:33.703545 Initializing devices...
9239 06:49:33.706652 Root Device init
9240 06:49:33.706729 init hardware done!
9241 06:49:33.709805 0x00000018: ctrlr->caps
9242 06:49:33.713164 52.000 MHz: ctrlr->f_max
9243 06:49:33.713251 0.400 MHz: ctrlr->f_min
9244 06:49:33.716321 0x40ff8080: ctrlr->voltages
9245 06:49:33.716404 sclk: 390625
9246 06:49:33.719701 Bus Width = 1
9247 06:49:33.719786 sclk: 390625
9248 06:49:33.722906 Bus Width = 1
9249 06:49:33.722983 Early init status = 3
9250 06:49:33.729614 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9251 06:49:33.733260 in-header: 03 fc 00 00 01 00 00 00
9252 06:49:33.733346 in-data: 00
9253 06:49:33.739634 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9254 06:49:33.743016 in-header: 03 fd 00 00 00 00 00 00
9255 06:49:33.746506 in-data:
9256 06:49:33.749579 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9257 06:49:33.753652 in-header: 03 fc 00 00 01 00 00 00
9258 06:49:33.756705 in-data: 00
9259 06:49:33.760121 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9260 06:49:33.765625 in-header: 03 fd 00 00 00 00 00 00
9261 06:49:33.769266 in-data:
9262 06:49:33.772231 [SSUSB] Setting up USB HOST controller...
9263 06:49:33.775970 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9264 06:49:33.778937 [SSUSB] phy power-on done.
9265 06:49:33.782480 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9266 06:49:33.788868 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9267 06:49:33.792385 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9268 06:49:33.799011 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9269 06:49:33.805780 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9270 06:49:33.812167 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9271 06:49:33.818556 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9272 06:49:33.825499 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9273 06:49:33.828545 SPM: binary array size = 0x9dc
9274 06:49:33.831799 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9275 06:49:33.838662 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9276 06:49:33.845034 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9277 06:49:33.851702 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9278 06:49:33.855303 configure_display: Starting display init
9279 06:49:33.888949 anx7625_power_on_init: Init interface.
9280 06:49:33.892179 anx7625_disable_pd_protocol: Disabled PD feature.
9281 06:49:33.895422 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9282 06:49:33.923517 anx7625_start_dp_work: Secure OCM version=00
9283 06:49:33.926493 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9284 06:49:33.941416 sp_tx_get_edid_block: EDID Block = 1
9285 06:49:34.043841 Extracted contents:
9286 06:49:34.047044 header: 00 ff ff ff ff ff ff 00
9287 06:49:34.051072 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9288 06:49:34.053961 version: 01 04
9289 06:49:34.057807 basic params: 95 1f 11 78 0a
9290 06:49:34.060750 chroma info: 76 90 94 55 54 90 27 21 50 54
9291 06:49:34.063886 established: 00 00 00
9292 06:49:34.070484 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9293 06:49:34.073798 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9294 06:49:34.080302 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9295 06:49:34.087185 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9296 06:49:34.093584 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9297 06:49:34.097346 extensions: 00
9298 06:49:34.097432 checksum: fb
9299 06:49:34.097499
9300 06:49:34.100411 Manufacturer: IVO Model 57d Serial Number 0
9301 06:49:34.104102 Made week 0 of 2020
9302 06:49:34.104183 EDID version: 1.4
9303 06:49:34.106867 Digital display
9304 06:49:34.110497 6 bits per primary color channel
9305 06:49:34.110586 DisplayPort interface
9306 06:49:34.114020 Maximum image size: 31 cm x 17 cm
9307 06:49:34.116996 Gamma: 220%
9308 06:49:34.117081 Check DPMS levels
9309 06:49:34.120018 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9310 06:49:34.123633 First detailed timing is preferred timing
9311 06:49:34.127174 Established timings supported:
9312 06:49:34.130151 Standard timings supported:
9313 06:49:34.133442 Detailed timings
9314 06:49:34.136840 Hex of detail: 383680a07038204018303c0035ae10000019
9315 06:49:34.140197 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9316 06:49:34.147019 0780 0798 07c8 0820 hborder 0
9317 06:49:34.149930 0438 043b 0447 0458 vborder 0
9318 06:49:34.153433 -hsync -vsync
9319 06:49:34.153528 Did detailed timing
9320 06:49:34.159861 Hex of detail: 000000000000000000000000000000000000
9321 06:49:34.159962 Manufacturer-specified data, tag 0
9322 06:49:34.166582 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9323 06:49:34.170060 ASCII string: InfoVision
9324 06:49:34.173624 Hex of detail: 000000fe00523134304e574635205248200a
9325 06:49:34.176710 ASCII string: R140NWF5 RH
9326 06:49:34.176830 Checksum
9327 06:49:34.180177 Checksum: 0xfb (valid)
9328 06:49:34.183419 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9329 06:49:34.186452 DSI data_rate: 832800000 bps
9330 06:49:34.190063 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9331 06:49:34.196959 anx7625_parse_edid: pixelclock(138800).
9332 06:49:34.200100 hactive(1920), hsync(48), hfp(24), hbp(88)
9333 06:49:34.203385 vactive(1080), vsync(12), vfp(3), vbp(17)
9334 06:49:34.206803 anx7625_dsi_config: config dsi.
9335 06:49:34.213334 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9336 06:49:34.226158 anx7625_dsi_config: success to config DSI
9337 06:49:34.229187 anx7625_dp_start: MIPI phy setup OK.
9338 06:49:34.232923 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9339 06:49:34.236035 mtk_ddp_mode_set invalid vrefresh 60
9340 06:49:34.239267 main_disp_path_setup
9341 06:49:34.239365 ovl_layer_smi_id_en
9342 06:49:34.242806 ovl_layer_smi_id_en
9343 06:49:34.242898 ccorr_config
9344 06:49:34.242966 aal_config
9345 06:49:34.246290 gamma_config
9346 06:49:34.246380 postmask_config
9347 06:49:34.249153 dither_config
9348 06:49:34.252585 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9349 06:49:34.259426 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9350 06:49:34.262479 Root Device init finished in 553 msecs
9351 06:49:34.262582 CPU_CLUSTER: 0 init
9352 06:49:34.272887 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9353 06:49:34.275714 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9354 06:49:34.279208 APU_MBOX 0x190000b0 = 0x10001
9355 06:49:34.282670 APU_MBOX 0x190001b0 = 0x10001
9356 06:49:34.285898 APU_MBOX 0x190005b0 = 0x10001
9357 06:49:34.289123 APU_MBOX 0x190006b0 = 0x10001
9358 06:49:34.292372 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9359 06:49:34.304974 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9360 06:49:34.317610 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9361 06:49:34.324144 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9362 06:49:34.335790 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9363 06:49:34.344866 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9364 06:49:34.348124 CPU_CLUSTER: 0 init finished in 81 msecs
9365 06:49:34.351267 Devices initialized
9366 06:49:34.354917 Show all devs... After init.
9367 06:49:34.355003 Root Device: enabled 1
9368 06:49:34.358218 CPU_CLUSTER: 0: enabled 1
9369 06:49:34.361473 CPU: 00: enabled 1
9370 06:49:34.364724 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9371 06:49:34.368011 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9372 06:49:34.371274 ELOG: NV offset 0x57f000 size 0x1000
9373 06:49:34.378070 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9374 06:49:34.384632 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9375 06:49:34.388003 ELOG: Event(17) added with size 13 at 2024-02-03 06:49:00 UTC
9376 06:49:34.391378 out: cmd=0x121: 03 db 21 01 00 00 00 00
9377 06:49:34.395246 in-header: 03 27 00 00 2c 00 00 00
9378 06:49:34.408396 in-data: 38 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9379 06:49:34.415369 ELOG: Event(A1) added with size 10 at 2024-02-03 06:49:00 UTC
9380 06:49:34.421654 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9381 06:49:34.428326 ELOG: Event(A0) added with size 9 at 2024-02-03 06:49:00 UTC
9382 06:49:34.432079 elog_add_boot_reason: Logged dev mode boot
9383 06:49:34.434841 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9384 06:49:34.438222 Finalize devices...
9385 06:49:34.438312 Devices finalized
9386 06:49:34.445153 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9387 06:49:34.448255 Writing coreboot table at 0xffe64000
9388 06:49:34.451876 0. 000000000010a000-0000000000113fff: RAMSTAGE
9389 06:49:34.455292 1. 0000000040000000-00000000400fffff: RAM
9390 06:49:34.458692 2. 0000000040100000-000000004032afff: RAMSTAGE
9391 06:49:34.464690 3. 000000004032b000-00000000545fffff: RAM
9392 06:49:34.468207 4. 0000000054600000-000000005465ffff: BL31
9393 06:49:34.471435 5. 0000000054660000-00000000ffe63fff: RAM
9394 06:49:34.474664 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9395 06:49:34.481796 7. 0000000100000000-000000023fffffff: RAM
9396 06:49:34.481911 Passing 5 GPIOs to payload:
9397 06:49:34.488383 NAME | PORT | POLARITY | VALUE
9398 06:49:34.491681 EC in RW | 0x000000aa | low | undefined
9399 06:49:34.498165 EC interrupt | 0x00000005 | low | undefined
9400 06:49:34.501292 TPM interrupt | 0x000000ab | high | undefined
9401 06:49:34.504522 SD card detect | 0x00000011 | high | undefined
9402 06:49:34.512213 speaker enable | 0x00000093 | high | undefined
9403 06:49:34.514992 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9404 06:49:34.518049 in-header: 03 f9 00 00 02 00 00 00
9405 06:49:34.518150 in-data: 02 00
9406 06:49:34.521403 ADC[4]: Raw value=901032 ID=7
9407 06:49:34.524845 ADC[3]: Raw value=213179 ID=1
9408 06:49:34.524941 RAM Code: 0x71
9409 06:49:34.528203 ADC[6]: Raw value=74502 ID=0
9410 06:49:34.531555 ADC[5]: Raw value=211703 ID=1
9411 06:49:34.531694 SKU Code: 0x1
9412 06:49:34.538203 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3234
9413 06:49:34.541152 coreboot table: 964 bytes.
9414 06:49:34.544843 IMD ROOT 0. 0xfffff000 0x00001000
9415 06:49:34.547783 IMD SMALL 1. 0xffffe000 0x00001000
9416 06:49:34.551484 RO MCACHE 2. 0xffffc000 0x00001104
9417 06:49:34.554935 CONSOLE 3. 0xfff7c000 0x00080000
9418 06:49:34.558096 FMAP 4. 0xfff7b000 0x00000452
9419 06:49:34.561373 TIME STAMP 5. 0xfff7a000 0x00000910
9420 06:49:34.564504 VBOOT WORK 6. 0xfff66000 0x00014000
9421 06:49:34.568027 RAMOOPS 7. 0xffe66000 0x00100000
9422 06:49:34.571512 COREBOOT 8. 0xffe64000 0x00002000
9423 06:49:34.571600 IMD small region:
9424 06:49:34.574963 IMD ROOT 0. 0xffffec00 0x00000400
9425 06:49:34.577800 VPD 1. 0xffffeb80 0x0000006c
9426 06:49:34.581433 MMC STATUS 2. 0xffffeb60 0x00000004
9427 06:49:34.587716 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9428 06:49:34.587831 Probing TPM: done!
9429 06:49:34.594878 Connected to device vid:did:rid of 1ae0:0028:00
9430 06:49:34.604654 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9431 06:49:34.608773 Initialized TPM device CR50 revision 0
9432 06:49:34.608863 Checking cr50 for pending updates
9433 06:49:34.614543 Reading cr50 TPM mode
9434 06:49:34.623231 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9435 06:49:34.629738 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9436 06:49:34.669945 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9437 06:49:34.673327 Checking segment from ROM address 0x40100000
9438 06:49:34.676736 Checking segment from ROM address 0x4010001c
9439 06:49:34.683527 Loading segment from ROM address 0x40100000
9440 06:49:34.683619 code (compression=0)
9441 06:49:34.690217 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9442 06:49:34.699992 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9443 06:49:34.700087 it's not compressed!
9444 06:49:34.706671 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9445 06:49:34.709908 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9446 06:49:34.730415 Loading segment from ROM address 0x4010001c
9447 06:49:34.730526 Entry Point 0x80000000
9448 06:49:34.733483 Loaded segments
9449 06:49:34.737186 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9450 06:49:34.743484 Jumping to boot code at 0x80000000(0xffe64000)
9451 06:49:34.750406 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9452 06:49:34.757385 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9453 06:49:34.764697 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9454 06:49:34.767924 Checking segment from ROM address 0x40100000
9455 06:49:34.771387 Checking segment from ROM address 0x4010001c
9456 06:49:34.777985 Loading segment from ROM address 0x40100000
9457 06:49:34.778071 code (compression=1)
9458 06:49:34.784882 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9459 06:49:34.794663 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9460 06:49:34.794750 using LZMA
9461 06:49:34.803288 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9462 06:49:34.809973 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9463 06:49:34.813218 Loading segment from ROM address 0x4010001c
9464 06:49:34.813303 Entry Point 0x54601000
9465 06:49:34.816357 Loaded segments
9466 06:49:34.819591 NOTICE: MT8192 bl31_setup
9467 06:49:34.826651 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9468 06:49:34.829978 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9469 06:49:34.833435 WARNING: region 0:
9470 06:49:34.836685 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 06:49:34.836771 WARNING: region 1:
9472 06:49:34.843574 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9473 06:49:34.846929 WARNING: region 2:
9474 06:49:34.850004 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9475 06:49:34.853484 WARNING: region 3:
9476 06:49:34.856470 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 06:49:34.859819 WARNING: region 4:
9478 06:49:34.866742 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 06:49:34.866850 WARNING: region 5:
9480 06:49:34.870106 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 06:49:34.873197 WARNING: region 6:
9482 06:49:34.876665 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 06:49:34.880084 WARNING: region 7:
9484 06:49:34.883142 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 06:49:34.889742 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9486 06:49:34.893246 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9487 06:49:34.896627 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9488 06:49:34.903114 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9489 06:49:34.906709 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9490 06:49:34.909877 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9491 06:49:34.916765 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9492 06:49:34.920056 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9493 06:49:34.926608 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9494 06:49:34.930220 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9495 06:49:34.933419 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9496 06:49:34.939939 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9497 06:49:34.943205 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9498 06:49:34.947288 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9499 06:49:34.953142 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9500 06:49:34.957085 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9501 06:49:34.963166 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9502 06:49:34.966364 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9503 06:49:34.969829 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9504 06:49:34.976569 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9505 06:49:34.980034 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9506 06:49:34.982982 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9507 06:49:34.989667 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9508 06:49:34.993103 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9509 06:49:34.999841 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9510 06:49:35.003376 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9511 06:49:35.006625 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9512 06:49:35.013554 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9513 06:49:35.016905 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9514 06:49:35.019948 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9515 06:49:35.026969 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9516 06:49:35.029847 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9517 06:49:35.036658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9518 06:49:35.040270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9519 06:49:35.043585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9520 06:49:35.046904 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9521 06:49:35.049925 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9522 06:49:35.056840 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9523 06:49:35.060059 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9524 06:49:35.063206 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9525 06:49:35.066428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9526 06:49:35.073288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9527 06:49:35.076430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9528 06:49:35.080139 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9529 06:49:35.086550 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9530 06:49:35.089975 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9531 06:49:35.093426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9532 06:49:35.096770 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9533 06:49:35.103064 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9534 06:49:35.106763 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9535 06:49:35.113317 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9536 06:49:35.116743 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9537 06:49:35.119773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9538 06:49:35.126299 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9539 06:49:35.129798 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9540 06:49:35.136309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9541 06:49:35.139811 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9542 06:49:35.146549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9543 06:49:35.149961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9544 06:49:35.153154 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9545 06:49:35.160081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9546 06:49:35.163260 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9547 06:49:35.169907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9548 06:49:35.173481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9549 06:49:35.179918 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9550 06:49:35.183202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9551 06:49:35.186815 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9552 06:49:35.193298 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9553 06:49:35.197006 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9554 06:49:35.203378 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9555 06:49:35.206619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9556 06:49:35.213762 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9557 06:49:35.216641 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9558 06:49:35.220198 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9559 06:49:35.227061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9560 06:49:35.230005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9561 06:49:35.236798 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9562 06:49:35.240300 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9563 06:49:35.246931 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9564 06:49:35.250458 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9565 06:49:35.253364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9566 06:49:35.260367 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9567 06:49:35.263503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9568 06:49:35.270092 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9569 06:49:35.273476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9570 06:49:35.280055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9571 06:49:35.283406 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9572 06:49:35.286903 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9573 06:49:35.293732 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9574 06:49:35.297187 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9575 06:49:35.303373 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9576 06:49:35.307000 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9577 06:49:35.313719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9578 06:49:35.316936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9579 06:49:35.323654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9580 06:49:35.326874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9581 06:49:35.330096 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9582 06:49:35.333619 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9583 06:49:35.340154 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9584 06:49:35.343423 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9585 06:49:35.346848 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9586 06:49:35.353673 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9587 06:49:35.356687 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9588 06:49:35.360443 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9589 06:49:35.366693 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9590 06:49:35.370289 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9591 06:49:35.376641 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9592 06:49:35.379979 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9593 06:49:35.383175 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9594 06:49:35.389741 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9595 06:49:35.393299 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9596 06:49:35.399869 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9597 06:49:35.403178 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9598 06:49:35.406771 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9599 06:49:35.413400 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9600 06:49:35.416751 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9601 06:49:35.419933 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9602 06:49:35.426502 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9603 06:49:35.429964 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9604 06:49:35.433553 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9605 06:49:35.436965 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9606 06:49:35.443580 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9607 06:49:35.446519 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9608 06:49:35.450108 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9609 06:49:35.456574 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9610 06:49:35.460277 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9611 06:49:35.463557 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9612 06:49:35.469887 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9613 06:49:35.473565 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9614 06:49:35.480011 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9615 06:49:35.483497 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9616 06:49:35.486674 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9617 06:49:35.493936 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9618 06:49:35.497106 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9619 06:49:35.500131 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9620 06:49:35.507387 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9621 06:49:35.510380 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9622 06:49:35.517160 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9623 06:49:35.520180 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9624 06:49:35.523590 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9625 06:49:35.530223 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9626 06:49:35.533788 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9627 06:49:35.540385 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9628 06:49:35.543405 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9629 06:49:35.546735 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9630 06:49:35.553691 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9631 06:49:35.556768 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9632 06:49:35.560098 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9633 06:49:35.567034 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9634 06:49:35.570218 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9635 06:49:35.577088 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9636 06:49:35.580374 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9637 06:49:35.583928 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9638 06:49:35.590000 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9639 06:49:35.593880 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9640 06:49:35.600404 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9641 06:49:35.603892 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9642 06:49:35.606861 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9643 06:49:35.613573 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9644 06:49:35.616708 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9645 06:49:35.620148 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9646 06:49:35.627019 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9647 06:49:35.629997 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9648 06:49:35.637183 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9649 06:49:35.640232 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9650 06:49:35.643743 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9651 06:49:35.650125 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9652 06:49:35.653617 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9653 06:49:35.660058 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9654 06:49:35.663383 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9655 06:49:35.667100 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9656 06:49:35.673612 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9657 06:49:35.676457 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9658 06:49:35.683469 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9659 06:49:35.686576 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9660 06:49:35.690182 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9661 06:49:35.696810 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9662 06:49:35.699896 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9663 06:49:35.706823 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9664 06:49:35.709881 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9665 06:49:35.713491 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9666 06:49:35.719907 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9667 06:49:35.723207 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9668 06:49:35.726231 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9669 06:49:35.733142 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9670 06:49:35.736421 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9671 06:49:35.743134 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9672 06:49:35.746233 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9673 06:49:35.749477 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9674 06:49:35.756218 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9675 06:49:35.759614 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9676 06:49:35.766302 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9677 06:49:35.769746 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9678 06:49:35.775946 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9679 06:49:35.779411 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9680 06:49:35.782764 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9681 06:49:35.789449 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9682 06:49:35.792655 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9683 06:49:35.799462 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9684 06:49:35.802818 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9685 06:49:35.808915 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9686 06:49:35.812515 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9687 06:49:35.815784 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9688 06:49:35.822601 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9689 06:49:35.825659 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9690 06:49:35.832268 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9691 06:49:35.835780 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9692 06:49:35.838715 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9693 06:49:35.845410 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9694 06:49:35.848756 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9695 06:49:35.855253 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9696 06:49:35.858726 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9697 06:49:35.865292 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9698 06:49:35.868501 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9699 06:49:35.872117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9700 06:49:35.878653 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9701 06:49:35.882211 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9702 06:49:35.888340 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9703 06:49:35.891885 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9704 06:49:35.898679 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9705 06:49:35.901753 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9706 06:49:35.904788 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9707 06:49:35.911622 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9708 06:49:35.914913 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9709 06:49:35.921534 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9710 06:49:35.924945 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9711 06:49:35.931608 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9712 06:49:35.935008 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9713 06:49:35.938226 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9714 06:49:35.944881 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9715 06:49:35.948037 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9716 06:49:35.951317 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9717 06:49:35.954544 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9718 06:49:35.958101 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9719 06:49:35.964730 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9720 06:49:35.968189 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9721 06:49:35.974741 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9722 06:49:35.977658 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9723 06:49:35.981108 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9724 06:49:35.987955 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9725 06:49:35.991096 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9726 06:49:35.994391 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9727 06:49:36.000934 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9728 06:49:36.004193 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9729 06:49:36.011099 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9730 06:49:36.014345 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9731 06:49:36.017737 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9732 06:49:36.024113 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9733 06:49:36.027283 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9734 06:49:36.031124 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9735 06:49:36.037431 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9736 06:49:36.040613 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9737 06:49:36.047320 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9738 06:49:36.050727 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9739 06:49:36.053819 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9740 06:49:36.060571 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9741 06:49:36.063895 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9742 06:49:36.067199 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9743 06:49:36.073778 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9744 06:49:36.077175 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9745 06:49:36.080593 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9746 06:49:36.087117 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9747 06:49:36.090199 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9748 06:49:36.097352 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9749 06:49:36.100072 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9750 06:49:36.103536 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9751 06:49:36.110030 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9752 06:49:36.113436 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9753 06:49:36.116779 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9754 06:49:36.123493 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9755 06:49:36.126961 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9756 06:49:36.129936 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9757 06:49:36.133083 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9758 06:49:36.136349 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9759 06:49:36.143059 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9760 06:49:36.146353 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9761 06:49:36.149505 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9762 06:49:36.156708 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9763 06:49:36.159885 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9764 06:49:36.163040 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9765 06:49:36.166293 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9766 06:49:36.172968 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9767 06:49:36.176353 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9768 06:49:36.179870 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9769 06:49:36.186552 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9770 06:49:36.189494 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9771 06:49:36.196318 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9772 06:49:36.199924 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9773 06:49:36.206133 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9774 06:49:36.209683 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9775 06:49:36.212922 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9776 06:49:36.219487 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9777 06:49:36.222742 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9778 06:49:36.229388 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9779 06:49:36.232482 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9780 06:49:36.236149 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9781 06:49:36.242681 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9782 06:49:36.245839 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9783 06:49:36.252682 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9784 06:49:36.255972 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9785 06:49:36.262252 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9786 06:49:36.265861 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9787 06:49:36.268932 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9788 06:49:36.275411 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9789 06:49:36.279036 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9790 06:49:36.285692 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9791 06:49:36.288938 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9792 06:49:36.292292 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9793 06:49:36.299031 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9794 06:49:36.302149 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9795 06:49:36.308732 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9796 06:49:36.312055 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9797 06:49:36.318519 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9798 06:49:36.322050 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9799 06:49:36.325473 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9800 06:49:36.332476 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9801 06:49:36.335540 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9802 06:49:36.338928 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9803 06:49:36.345241 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9804 06:49:36.348566 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9805 06:49:36.355090 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9806 06:49:36.358747 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9807 06:49:36.361962 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9808 06:49:36.368869 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9809 06:49:36.371892 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9810 06:49:36.378537 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9811 06:49:36.381799 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9812 06:49:36.388635 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9813 06:49:36.391691 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9814 06:49:36.395290 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9815 06:49:36.401786 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9816 06:49:36.405310 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9817 06:49:36.411633 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9818 06:49:36.415205 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9819 06:49:36.418591 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9820 06:49:36.425205 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9821 06:49:36.428542 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9822 06:49:36.435177 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9823 06:49:36.438063 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9824 06:49:36.441682 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9825 06:49:36.448266 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9826 06:49:36.451862 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9827 06:49:36.458373 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9828 06:49:36.461255 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9829 06:49:36.467953 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9830 06:49:36.471852 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9831 06:49:36.474841 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9832 06:49:36.481473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9833 06:49:36.484845 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9834 06:49:36.491565 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9835 06:49:36.494811 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9836 06:49:36.498447 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9837 06:49:36.504892 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9838 06:49:36.508085 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9839 06:49:36.514863 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9840 06:49:36.517899 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9841 06:49:36.521383 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9842 06:49:36.528046 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9843 06:49:36.531499 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9844 06:49:36.538140 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9845 06:49:36.541305 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9846 06:49:36.548380 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9847 06:49:36.551234 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9848 06:49:36.554793 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9849 06:49:36.561383 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9850 06:49:36.564847 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9851 06:49:36.571258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9852 06:49:36.574318 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9853 06:49:36.581183 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9854 06:49:36.584700 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9855 06:49:36.588125 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9856 06:49:36.594741 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9857 06:49:36.598064 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9858 06:49:36.604778 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9859 06:49:36.607817 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9860 06:49:36.614708 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9861 06:49:36.617726 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9862 06:49:36.620974 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9863 06:49:36.628032 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9864 06:49:36.631382 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9865 06:49:36.637667 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9866 06:49:36.640960 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9867 06:49:36.647914 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9868 06:49:36.650869 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9869 06:49:36.657774 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9870 06:49:36.660800 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9871 06:49:36.664204 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9872 06:49:36.670989 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9873 06:49:36.674250 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9874 06:49:36.680718 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9875 06:49:36.684508 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9876 06:49:36.690645 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9877 06:49:36.694180 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9878 06:49:36.697562 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9879 06:49:36.704245 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9880 06:49:36.707097 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9881 06:49:36.713731 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9882 06:49:36.717316 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9883 06:49:36.723947 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9884 06:49:36.726905 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9885 06:49:36.733712 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9886 06:49:36.736871 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9887 06:49:36.740444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9888 06:49:36.747189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9889 06:49:36.750069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9890 06:49:36.756886 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9891 06:49:36.760613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9892 06:49:36.767013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9893 06:49:36.769854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9894 06:49:36.776617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9895 06:49:36.780089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9896 06:49:36.786851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9897 06:49:36.789957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9898 06:49:36.796321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9899 06:49:36.799758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9900 06:49:36.806233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9901 06:49:36.809838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9902 06:49:36.816519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9903 06:49:36.819738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9904 06:49:36.823082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9905 06:49:36.829714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9906 06:49:36.832983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9907 06:49:36.839688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9908 06:49:36.842903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9909 06:49:36.849657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9910 06:49:36.852723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9911 06:49:36.859459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9912 06:49:36.862921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9913 06:49:36.869579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9914 06:49:36.875816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9915 06:49:36.879545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9916 06:49:36.882862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9917 06:49:36.889400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9918 06:49:36.892453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9919 06:49:36.899073 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9920 06:49:36.899153 INFO: [APUAPC] vio 0
9921 06:49:36.906406 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9922 06:49:36.909821 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9923 06:49:36.913167 INFO: [APUAPC] D0_APC_0: 0x400510
9924 06:49:36.916850 INFO: [APUAPC] D0_APC_1: 0x0
9925 06:49:36.919942 INFO: [APUAPC] D0_APC_2: 0x1540
9926 06:49:36.923280 INFO: [APUAPC] D0_APC_3: 0x0
9927 06:49:36.926352 INFO: [APUAPC] D1_APC_0: 0xffffffff
9928 06:49:36.929818 INFO: [APUAPC] D1_APC_1: 0xffffffff
9929 06:49:36.933095 INFO: [APUAPC] D1_APC_2: 0x3fffff
9930 06:49:36.936484 INFO: [APUAPC] D1_APC_3: 0x0
9931 06:49:36.939765 INFO: [APUAPC] D2_APC_0: 0xffffffff
9932 06:49:36.942918 INFO: [APUAPC] D2_APC_1: 0xffffffff
9933 06:49:36.946326 INFO: [APUAPC] D2_APC_2: 0x3fffff
9934 06:49:36.949671 INFO: [APUAPC] D2_APC_3: 0x0
9935 06:49:36.952778 INFO: [APUAPC] D3_APC_0: 0xffffffff
9936 06:49:36.956631 INFO: [APUAPC] D3_APC_1: 0xffffffff
9937 06:49:36.959287 INFO: [APUAPC] D3_APC_2: 0x3fffff
9938 06:49:36.962683 INFO: [APUAPC] D3_APC_3: 0x0
9939 06:49:36.966118 INFO: [APUAPC] D4_APC_0: 0xffffffff
9940 06:49:36.969416 INFO: [APUAPC] D4_APC_1: 0xffffffff
9941 06:49:36.972430 INFO: [APUAPC] D4_APC_2: 0x3fffff
9942 06:49:36.975778 INFO: [APUAPC] D4_APC_3: 0x0
9943 06:49:36.979487 INFO: [APUAPC] D5_APC_0: 0xffffffff
9944 06:49:36.982568 INFO: [APUAPC] D5_APC_1: 0xffffffff
9945 06:49:36.986125 INFO: [APUAPC] D5_APC_2: 0x3fffff
9946 06:49:36.986234 INFO: [APUAPC] D5_APC_3: 0x0
9947 06:49:36.989620 INFO: [APUAPC] D6_APC_0: 0xffffffff
9948 06:49:36.992807 INFO: [APUAPC] D6_APC_1: 0xffffffff
9949 06:49:36.996086 INFO: [APUAPC] D6_APC_2: 0x3fffff
9950 06:49:36.999107 INFO: [APUAPC] D6_APC_3: 0x0
9951 06:49:37.003042 INFO: [APUAPC] D7_APC_0: 0xffffffff
9952 06:49:37.006158 INFO: [APUAPC] D7_APC_1: 0xffffffff
9953 06:49:37.009346 INFO: [APUAPC] D7_APC_2: 0x3fffff
9954 06:49:37.012697 INFO: [APUAPC] D7_APC_3: 0x0
9955 06:49:37.016386 INFO: [APUAPC] D8_APC_0: 0xffffffff
9956 06:49:37.019255 INFO: [APUAPC] D8_APC_1: 0xffffffff
9957 06:49:37.022645 INFO: [APUAPC] D8_APC_2: 0x3fffff
9958 06:49:37.025793 INFO: [APUAPC] D8_APC_3: 0x0
9959 06:49:37.028996 INFO: [APUAPC] D9_APC_0: 0xffffffff
9960 06:49:37.032507 INFO: [APUAPC] D9_APC_1: 0xffffffff
9961 06:49:37.035528 INFO: [APUAPC] D9_APC_2: 0x3fffff
9962 06:49:37.039134 INFO: [APUAPC] D9_APC_3: 0x0
9963 06:49:37.042393 INFO: [APUAPC] D10_APC_0: 0xffffffff
9964 06:49:37.045910 INFO: [APUAPC] D10_APC_1: 0xffffffff
9965 06:49:37.048949 INFO: [APUAPC] D10_APC_2: 0x3fffff
9966 06:49:37.052704 INFO: [APUAPC] D10_APC_3: 0x0
9967 06:49:37.055655 INFO: [APUAPC] D11_APC_0: 0xffffffff
9968 06:49:37.059108 INFO: [APUAPC] D11_APC_1: 0xffffffff
9969 06:49:37.062304 INFO: [APUAPC] D11_APC_2: 0x3fffff
9970 06:49:37.065679 INFO: [APUAPC] D11_APC_3: 0x0
9971 06:49:37.068782 INFO: [APUAPC] D12_APC_0: 0xffffffff
9972 06:49:37.072051 INFO: [APUAPC] D12_APC_1: 0xffffffff
9973 06:49:37.075552 INFO: [APUAPC] D12_APC_2: 0x3fffff
9974 06:49:37.078673 INFO: [APUAPC] D12_APC_3: 0x0
9975 06:49:37.081931 INFO: [APUAPC] D13_APC_0: 0xffffffff
9976 06:49:37.085305 INFO: [APUAPC] D13_APC_1: 0xffffffff
9977 06:49:37.089170 INFO: [APUAPC] D13_APC_2: 0x3fffff
9978 06:49:37.092326 INFO: [APUAPC] D13_APC_3: 0x0
9979 06:49:37.095631 INFO: [APUAPC] D14_APC_0: 0xffffffff
9980 06:49:37.098778 INFO: [APUAPC] D14_APC_1: 0xffffffff
9981 06:49:37.101968 INFO: [APUAPC] D14_APC_2: 0x3fffff
9982 06:49:37.105555 INFO: [APUAPC] D14_APC_3: 0x0
9983 06:49:37.108653 INFO: [APUAPC] D15_APC_0: 0xffffffff
9984 06:49:37.111852 INFO: [APUAPC] D15_APC_1: 0xffffffff
9985 06:49:37.115566 INFO: [APUAPC] D15_APC_2: 0x3fffff
9986 06:49:37.118613 INFO: [APUAPC] D15_APC_3: 0x0
9987 06:49:37.122239 INFO: [APUAPC] APC_CON: 0x4
9988 06:49:37.125643 INFO: [NOCDAPC] D0_APC_0: 0x0
9989 06:49:37.129167 INFO: [NOCDAPC] D0_APC_1: 0x0
9990 06:49:37.131736 INFO: [NOCDAPC] D1_APC_0: 0x0
9991 06:49:37.135397 INFO: [NOCDAPC] D1_APC_1: 0xfff
9992 06:49:37.138869 INFO: [NOCDAPC] D2_APC_0: 0x0
9993 06:49:37.141787 INFO: [NOCDAPC] D2_APC_1: 0xfff
9994 06:49:37.141895 INFO: [NOCDAPC] D3_APC_0: 0x0
9995 06:49:37.145043 INFO: [NOCDAPC] D3_APC_1: 0xfff
9996 06:49:37.148258 INFO: [NOCDAPC] D4_APC_0: 0x0
9997 06:49:37.151726 INFO: [NOCDAPC] D4_APC_1: 0xfff
9998 06:49:37.155262 INFO: [NOCDAPC] D5_APC_0: 0x0
9999 06:49:37.158209 INFO: [NOCDAPC] D5_APC_1: 0xfff
10000 06:49:37.161852 INFO: [NOCDAPC] D6_APC_0: 0x0
10001 06:49:37.164878 INFO: [NOCDAPC] D6_APC_1: 0xfff
10002 06:49:37.168470 INFO: [NOCDAPC] D7_APC_0: 0x0
10003 06:49:37.171481 INFO: [NOCDAPC] D7_APC_1: 0xfff
10004 06:49:37.175288 INFO: [NOCDAPC] D8_APC_0: 0x0
10005 06:49:37.175371 INFO: [NOCDAPC] D8_APC_1: 0xfff
10006 06:49:37.178503 INFO: [NOCDAPC] D9_APC_0: 0x0
10007 06:49:37.181721 INFO: [NOCDAPC] D9_APC_1: 0xfff
10008 06:49:37.184839 INFO: [NOCDAPC] D10_APC_0: 0x0
10009 06:49:37.187949 INFO: [NOCDAPC] D10_APC_1: 0xfff
10010 06:49:37.191823 INFO: [NOCDAPC] D11_APC_0: 0x0
10011 06:49:37.194934 INFO: [NOCDAPC] D11_APC_1: 0xfff
10012 06:49:37.197847 INFO: [NOCDAPC] D12_APC_0: 0x0
10013 06:49:37.201240 INFO: [NOCDAPC] D12_APC_1: 0xfff
10014 06:49:37.204496 INFO: [NOCDAPC] D13_APC_0: 0x0
10015 06:49:37.208169 INFO: [NOCDAPC] D13_APC_1: 0xfff
10016 06:49:37.211219 INFO: [NOCDAPC] D14_APC_0: 0x0
10017 06:49:37.214767 INFO: [NOCDAPC] D14_APC_1: 0xfff
10018 06:49:37.217907 INFO: [NOCDAPC] D15_APC_0: 0x0
10019 06:49:37.221262 INFO: [NOCDAPC] D15_APC_1: 0xfff
10020 06:49:37.221365 INFO: [NOCDAPC] APC_CON: 0x4
10021 06:49:37.224650 INFO: [APUAPC] set_apusys_apc done
10022 06:49:37.228249 INFO: [DEVAPC] devapc_init done
10023 06:49:37.234767 INFO: GICv3 without legacy support detected.
10024 06:49:37.237840 INFO: ARM GICv3 driver initialized in EL3
10025 06:49:37.241335 INFO: Maximum SPI INTID supported: 639
10026 06:49:37.244730 INFO: BL31: Initializing runtime services
10027 06:49:37.251049 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10028 06:49:37.254598 INFO: SPM: enable CPC mode
10029 06:49:37.258020 INFO: mcdi ready for mcusys-off-idle and system suspend
10030 06:49:37.264757 INFO: BL31: Preparing for EL3 exit to normal world
10031 06:49:37.267991 INFO: Entry point address = 0x80000000
10032 06:49:37.268063 INFO: SPSR = 0x8
10033 06:49:37.274348
10034 06:49:37.274420
10035 06:49:37.274482
10036 06:49:37.278134 Starting depthcharge on Spherion...
10037 06:49:37.278206
10038 06:49:37.278268 Wipe memory regions:
10039 06:49:37.278332
10040 06:49:37.278935 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10041 06:49:37.279037 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10042 06:49:37.279125 Setting prompt string to ['asurada:']
10043 06:49:37.279205 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10044 06:49:37.281031 [0x00000040000000, 0x00000054600000)
10045 06:49:37.403643
10046 06:49:37.403762 [0x00000054660000, 0x00000080000000)
10047 06:49:37.664325
10048 06:49:37.664485 [0x000000821a7280, 0x000000ffe64000)
10049 06:49:38.409091
10050 06:49:38.409231 [0x00000100000000, 0x00000240000000)
10051 06:49:40.299512
10052 06:49:40.302352 Initializing XHCI USB controller at 0x11200000.
10053 06:49:41.341121
10054 06:49:41.344471 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10055 06:49:41.344718
10056 06:49:41.344905
10057 06:49:41.345079
10058 06:49:41.345562 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 06:49:41.446243 asurada: tftpboot 192.168.201.1 12694799/tftp-deploy-zve8fp0e/kernel/image.itb 12694799/tftp-deploy-zve8fp0e/kernel/cmdline
10061 06:49:41.446389 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 06:49:41.446485 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10063 06:49:41.450685 tftpboot 192.168.201.1 12694799/tftp-deploy-zve8fp0e/kernel/image.itp-deploy-zve8fp0e/kernel/cmdline
10064 06:49:41.450772
10065 06:49:41.450839 Waiting for link
10066 06:49:41.609593
10067 06:49:41.610046 R8152: Initializing
10068 06:49:41.610304
10069 06:49:41.612804 Version 9 (ocp_data = 6010)
10070 06:49:41.613139
10071 06:49:41.615654 R8152: Done initializing
10072 06:49:41.615956
10073 06:49:41.616188 Adding net device
10074 06:49:43.488900
10075 06:49:43.489057 done.
10076 06:49:43.489128
10077 06:49:43.489191 MAC: 00:e0:4c:72:2d:d6
10078 06:49:43.489252
10079 06:49:43.492385 Sending DHCP discover... done.
10080 06:49:43.492471
10081 06:49:43.495541 Waiting for reply... done.
10082 06:49:43.495638
10083 06:49:43.498940 Sending DHCP request... done.
10084 06:49:43.499024
10085 06:49:43.502547 Waiting for reply... done.
10086 06:49:43.502631
10087 06:49:43.502698 My ip is 192.168.201.21
10088 06:49:43.502760
10089 06:49:43.505637 The DHCP server ip is 192.168.201.1
10090 06:49:43.505721
10091 06:49:43.512100 TFTP server IP predefined by user: 192.168.201.1
10092 06:49:43.512184
10093 06:49:43.519065 Bootfile predefined by user: 12694799/tftp-deploy-zve8fp0e/kernel/image.itb
10094 06:49:43.519150
10095 06:49:43.519216 Sending tftp read request... done.
10096 06:49:43.522449
10097 06:49:43.522543 Waiting for the transfer...
10098 06:49:43.525520
10099 06:49:43.804278 00000000 ################################################################
10100 06:49:43.804416
10101 06:49:44.068351 00080000 ################################################################
10102 06:49:44.068489
10103 06:49:44.320391 00100000 ################################################################
10104 06:49:44.320524
10105 06:49:44.580970 00180000 ################################################################
10106 06:49:44.581107
10107 06:49:44.862021 00200000 ################################################################
10108 06:49:44.862160
10109 06:49:45.132513 00280000 ################################################################
10110 06:49:45.132679
10111 06:49:45.382284 00300000 ################################################################
10112 06:49:45.382424
10113 06:49:45.659556 00380000 ################################################################
10114 06:49:45.659691
10115 06:49:45.941391 00400000 ################################################################
10116 06:49:45.941523
10117 06:49:46.237236 00480000 ################################################################
10118 06:49:46.237367
10119 06:49:46.516939 00500000 ################################################################
10120 06:49:46.517089
10121 06:49:46.766142 00580000 ################################################################
10122 06:49:46.766284
10123 06:49:47.032192 00600000 ################################################################
10124 06:49:47.032329
10125 06:49:47.287592 00680000 ################################################################
10126 06:49:47.287729
10127 06:49:47.570490 00700000 ################################################################
10128 06:49:47.570635
10129 06:49:47.859642 00780000 ################################################################
10130 06:49:47.859782
10131 06:49:48.151613 00800000 ################################################################
10132 06:49:48.151749
10133 06:49:48.451422 00880000 ################################################################
10134 06:49:48.451562
10135 06:49:48.740424 00900000 ################################################################
10136 06:49:48.740595
10137 06:49:49.036328 00980000 ################################################################
10138 06:49:49.036468
10139 06:49:49.328901 00a00000 ################################################################
10140 06:49:49.329049
10141 06:49:49.625097 00a80000 ################################################################
10142 06:49:49.625260
10143 06:49:49.885037 00b00000 ################################################################
10144 06:49:49.885175
10145 06:49:50.144719 00b80000 ################################################################
10146 06:49:50.144869
10147 06:49:50.394123 00c00000 ################################################################
10148 06:49:50.394269
10149 06:49:50.660621 00c80000 ################################################################
10150 06:49:50.660789
10151 06:49:50.948338 00d00000 ################################################################
10152 06:49:50.948493
10153 06:49:51.225138 00d80000 ################################################################
10154 06:49:51.225296
10155 06:49:51.511731 00e00000 ################################################################
10156 06:49:51.511879
10157 06:49:51.801035 00e80000 ################################################################
10158 06:49:51.801214
10159 06:49:52.081958 00f00000 ################################################################
10160 06:49:52.082155
10161 06:49:52.371872 00f80000 ################################################################
10162 06:49:52.372006
10163 06:49:52.657438 01000000 ################################################################
10164 06:49:52.657580
10165 06:49:52.936832 01080000 ################################################################
10166 06:49:52.936981
10167 06:49:53.219924 01100000 ################################################################
10168 06:49:53.220055
10169 06:49:53.509222 01180000 ################################################################
10170 06:49:53.509409
10171 06:49:53.789745 01200000 ################################################################
10172 06:49:53.789907
10173 06:49:54.061888 01280000 ################################################################
10174 06:49:54.062075
10175 06:49:54.359428 01300000 ################################################################
10176 06:49:54.359555
10177 06:49:54.627971 01380000 ################################################################
10178 06:49:54.628097
10179 06:49:54.887761 01400000 ################################################################
10180 06:49:54.887898
10181 06:49:55.151364 01480000 ################################################################
10182 06:49:55.151492
10183 06:49:55.428984 01500000 ################################################################
10184 06:49:55.429114
10185 06:49:55.701513 01580000 ################################################################
10186 06:49:55.701698
10187 06:49:55.952596 01600000 ################################################################
10188 06:49:55.952752
10189 06:49:56.212875 01680000 ################################################################
10190 06:49:56.213032
10191 06:49:56.485336 01700000 ################################################################
10192 06:49:56.485468
10193 06:49:56.741013 01780000 ################################################################
10194 06:49:56.741172
10195 06:49:56.993176 01800000 ################################################################
10196 06:49:56.993314
10197 06:49:57.278365 01880000 ################################################################
10198 06:49:57.278507
10199 06:49:57.532390 01900000 ################################################################
10200 06:49:57.532528
10201 06:49:57.773755 01980000 ################################################################
10202 06:49:57.773893
10203 06:49:58.017844 01a00000 ################################################################
10204 06:49:58.018005
10205 06:49:58.269919 01a80000 ################################################################
10206 06:49:58.270088
10207 06:49:58.524076 01b00000 ################################################################
10208 06:49:58.524220
10209 06:49:58.796657 01b80000 ################################################################
10210 06:49:58.796788
10211 06:49:59.071504 01c00000 ################################################################
10212 06:49:59.071633
10213 06:49:59.366240 01c80000 ################################################################
10214 06:49:59.366383
10215 06:49:59.659477 01d00000 ################################################################
10216 06:49:59.659617
10217 06:49:59.951976 01d80000 ################################################################
10218 06:49:59.952135
10219 06:50:00.238619 01e00000 ################################################################
10220 06:50:00.238750
10221 06:50:00.531228 01e80000 ################################################################
10222 06:50:00.531361
10223 06:50:00.827283 01f00000 ################################################################
10224 06:50:00.827440
10225 06:50:01.110654 01f80000 ################################################################
10226 06:50:01.110787
10227 06:50:01.362612 02000000 ################################################################
10228 06:50:01.362742
10229 06:50:01.636827 02080000 ################################################################
10230 06:50:01.636955
10231 06:50:01.911968 02100000 ################################################################
10232 06:50:01.912101
10233 06:50:02.171413 02180000 ################################################################
10234 06:50:02.171548
10235 06:50:02.458089 02200000 ################################################################
10236 06:50:02.458214
10237 06:50:02.745853 02280000 ################################################################
10238 06:50:02.746047
10239 06:50:03.040616 02300000 ################################################################
10240 06:50:03.040756
10241 06:50:03.338664 02380000 ################################################################
10242 06:50:03.338796
10243 06:50:03.639073 02400000 ################################################################
10244 06:50:03.639208
10245 06:50:03.921674 02480000 ################################################################
10246 06:50:03.921839
10247 06:50:04.189345 02500000 ################################################################
10248 06:50:04.189488
10249 06:50:04.462740 02580000 ################################################################
10250 06:50:04.462883
10251 06:50:04.734960 02600000 ################################################################
10252 06:50:04.735096
10253 06:50:05.001431 02680000 ################################################################
10254 06:50:05.001577
10255 06:50:05.268109 02700000 ################################################################
10256 06:50:05.268246
10257 06:50:05.543643 02780000 ################################################################
10258 06:50:05.543783
10259 06:50:05.811594 02800000 ################################################################
10260 06:50:05.811744
10261 06:50:06.064884 02880000 ################################################################
10262 06:50:06.065036
10263 06:50:06.328199 02900000 ################################################################
10264 06:50:06.328348
10265 06:50:06.612874 02980000 ################################################################
10266 06:50:06.613033
10267 06:50:06.897219 02a00000 ################################################################
10268 06:50:06.897353
10269 06:50:07.166566 02a80000 ################################################################
10270 06:50:07.166707
10271 06:50:07.417788 02b00000 ################################################################
10272 06:50:07.417925
10273 06:50:07.671579 02b80000 ################################################################
10274 06:50:07.671710
10275 06:50:07.935258 02c00000 ################################################################
10276 06:50:07.935395
10277 06:50:08.186334 02c80000 ################################################################
10278 06:50:08.186481
10279 06:50:08.428460 02d00000 ################################################################
10280 06:50:08.428619
10281 06:50:08.685459 02d80000 ################################################################
10282 06:50:08.685632
10283 06:50:08.949086 02e00000 ################################################################
10284 06:50:08.949232
10285 06:50:09.202034 02e80000 ################################################################
10286 06:50:09.202183
10287 06:50:09.457097 02f00000 ################################################################
10288 06:50:09.457252
10289 06:50:09.730697 02f80000 ################################################################
10290 06:50:09.730836
10291 06:50:09.987460 03000000 ################################################################
10292 06:50:09.987596
10293 06:50:10.245027 03080000 ################################################################
10294 06:50:10.245170
10295 06:50:10.500263 03100000 ################################################################
10296 06:50:10.500424
10297 06:50:10.768470 03180000 ################################################################
10298 06:50:10.768615
10299 06:50:11.035126 03200000 ################################################################
10300 06:50:11.035262
10301 06:50:11.305362 03280000 ################################################################
10302 06:50:11.305503
10303 06:50:11.569475 03300000 ################################################################
10304 06:50:11.569625
10305 06:50:11.830652 03380000 ################################################################
10306 06:50:11.830839
10307 06:50:12.090979 03400000 ################################################################
10308 06:50:12.091126
10309 06:50:12.347733 03480000 ################################################################
10310 06:50:12.347877
10311 06:50:12.597688 03500000 ################################################################
10312 06:50:12.597832
10313 06:50:12.860953 03580000 ################################################################
10314 06:50:12.861089
10315 06:50:13.122906 03600000 ################################################################
10316 06:50:13.123039
10317 06:50:13.386511 03680000 ################################################################
10318 06:50:13.386681
10319 06:50:13.635522 03700000 ################################################################
10320 06:50:13.635660
10321 06:50:13.894857 03780000 ################################################################
10322 06:50:13.895006
10323 06:50:14.147974 03800000 ################################################################
10324 06:50:14.148117
10325 06:50:14.394741 03880000 ################################################################
10326 06:50:14.394894
10327 06:50:14.645616 03900000 ################################################################
10328 06:50:14.645755
10329 06:50:14.896820 03980000 ################################################################
10330 06:50:14.896955
10331 06:50:15.156076 03a00000 ################################################################
10332 06:50:15.156209
10333 06:50:15.431893 03a80000 ################################################################
10334 06:50:15.432038
10335 06:50:15.738842 03b00000 ################################################################
10336 06:50:15.738977
10337 06:50:16.007783 03b80000 ################################################################
10338 06:50:16.007929
10339 06:50:16.267247 03c00000 ################################################################
10340 06:50:16.267409
10341 06:50:16.528657 03c80000 ################################################################
10342 06:50:16.528793
10343 06:50:16.804672 03d00000 ################################################################
10344 06:50:16.804801
10345 06:50:17.100005 03d80000 ################################################################
10346 06:50:17.100138
10347 06:50:17.363102 03e00000 ################################################################
10348 06:50:17.363233
10349 06:50:17.613935 03e80000 ################################################################
10350 06:50:17.614095
10351 06:50:17.885364 03f00000 ################################################################
10352 06:50:17.885499
10353 06:50:18.158885 03f80000 ################################################################
10354 06:50:18.159019
10355 06:50:18.442300 04000000 ################################################################
10356 06:50:18.442433
10357 06:50:18.724256 04080000 ################################################################
10358 06:50:18.724418
10359 06:50:19.010380 04100000 ################################################################
10360 06:50:19.010521
10361 06:50:19.267832 04180000 ################################################################
10362 06:50:19.267967
10363 06:50:19.520990 04200000 ################################################################
10364 06:50:19.521124
10365 06:50:19.782375 04280000 ################################################################
10366 06:50:19.782511
10367 06:50:20.057922 04300000 ################################################################
10368 06:50:20.058097
10369 06:50:20.326418 04380000 ################################################################
10370 06:50:20.326554
10371 06:50:20.597573 04400000 ################################################################
10372 06:50:20.597757
10373 06:50:20.872956 04480000 ################################################################
10374 06:50:20.873102
10375 06:50:21.162123 04500000 ################################################################
10376 06:50:21.162269
10377 06:50:21.451875 04580000 ################################################################
10378 06:50:21.452022
10379 06:50:21.718404 04600000 ################################################################
10380 06:50:21.718538
10381 06:50:21.986339 04680000 ################################################################
10382 06:50:21.986485
10383 06:50:22.237110 04700000 ################################################################
10384 06:50:22.237248
10385 06:50:22.496927 04780000 ################################################################
10386 06:50:22.497078
10387 06:50:22.766719 04800000 ################################################################
10388 06:50:22.766897
10389 06:50:23.046564 04880000 ################################################################
10390 06:50:23.046710
10391 06:50:23.326203 04900000 ################################################################
10392 06:50:23.326348
10393 06:50:23.614358 04980000 ################################################################
10394 06:50:23.614503
10395 06:50:23.872085 04a00000 ################################################################
10396 06:50:23.872233
10397 06:50:24.121030 04a80000 ################################################################
10398 06:50:24.121188
10399 06:50:24.379992 04b00000 ################################################################
10400 06:50:24.380145
10401 06:50:24.631665 04b80000 ################################################################
10402 06:50:24.631804
10403 06:50:24.886071 04c00000 ################################################################
10404 06:50:24.886209
10405 06:50:25.150316 04c80000 ################################################################
10406 06:50:25.150466
10407 06:50:25.437492 04d00000 ################################################################
10408 06:50:25.437674
10409 06:50:25.726054 04d80000 ################################################################
10410 06:50:25.726192
10411 06:50:26.016296 04e00000 ################################################################
10412 06:50:26.016446
10413 06:50:26.277495 04e80000 ################################################################
10414 06:50:26.277673
10415 06:50:26.551966 04f00000 ################################################################
10416 06:50:26.552107
10417 06:50:26.832287 04f80000 ################################################################
10418 06:50:26.832420
10419 06:50:27.113434 05000000 ################################################################
10420 06:50:27.113674
10421 06:50:27.388323 05080000 ################################################################
10422 06:50:27.388498
10423 06:50:27.667731 05100000 ################################################################
10424 06:50:27.667871
10425 06:50:27.920186 05180000 ################################################################
10426 06:50:27.920355
10427 06:50:28.176450 05200000 ################################################################
10428 06:50:28.176614
10429 06:50:28.450044 05280000 ################################################################
10430 06:50:28.450199
10431 06:50:28.704308 05300000 ################################################################
10432 06:50:28.704480
10433 06:50:28.951319 05380000 ################################################################
10434 06:50:28.951463
10435 06:50:29.226944 05400000 ################################################################
10436 06:50:29.227100
10437 06:50:29.493201 05480000 ################################################################
10438 06:50:29.493384
10439 06:50:29.765072 05500000 ################################################################
10440 06:50:29.765223
10441 06:50:30.042616 05580000 ################################################################
10442 06:50:30.042750
10443 06:50:30.344564 05600000 ################################################################
10444 06:50:30.344715
10445 06:50:30.616071 05680000 ################################################################
10446 06:50:30.616219
10447 06:50:30.875396 05700000 ################################################################
10448 06:50:30.875531
10449 06:50:31.127181 05780000 ################################################################
10450 06:50:31.127330
10451 06:50:31.399369 05800000 ################################################################
10452 06:50:31.399505
10453 06:50:31.687918 05880000 ################################################################
10454 06:50:31.688050
10455 06:50:31.980411 05900000 ################################################################
10456 06:50:31.980547
10457 06:50:32.248613 05980000 ################################################################
10458 06:50:32.248749
10459 06:50:32.518217 05a00000 ################################################################
10460 06:50:32.518359
10461 06:50:32.796834 05a80000 ################################################################
10462 06:50:32.796980
10463 06:50:33.075850 05b00000 ################################################################
10464 06:50:33.075999
10465 06:50:33.356039 05b80000 ################################################################
10466 06:50:33.356206
10467 06:50:33.629075 05c00000 ################################################################
10468 06:50:33.629221
10469 06:50:33.909986 05c80000 ################################################################
10470 06:50:33.910128
10471 06:50:34.202838 05d00000 ################################################################
10472 06:50:34.202988
10473 06:50:34.464770 05d80000 ################################################################
10474 06:50:34.464917
10475 06:50:34.722226 05e00000 ################################################################
10476 06:50:34.722376
10477 06:50:35.012017 05e80000 ################################################################
10478 06:50:35.012171
10479 06:50:35.294828 05f00000 ################################################################
10480 06:50:35.294982
10481 06:50:35.567804 05f80000 ################################################################
10482 06:50:35.567953
10483 06:50:35.848828 06000000 ################################################################
10484 06:50:35.848982
10485 06:50:36.128624 06080000 ################################################################
10486 06:50:36.128779
10487 06:50:36.414808 06100000 ################################################################
10488 06:50:36.414969
10489 06:50:36.694865 06180000 ################################################################
10490 06:50:36.695025
10491 06:50:36.979525 06200000 ################################################################
10492 06:50:36.979733
10493 06:50:37.268198 06280000 ################################################################
10494 06:50:37.268357
10495 06:50:37.562954 06300000 ################################################################
10496 06:50:37.563114
10497 06:50:37.860865 06380000 ################################################################
10498 06:50:37.861053
10499 06:50:38.153451 06400000 ################################################################
10500 06:50:38.153660
10501 06:50:38.446769 06480000 ################################################################
10502 06:50:38.446949
10503 06:50:38.731955 06500000 ################################################################
10504 06:50:38.732106
10505 06:50:39.027487 06580000 ################################################################
10506 06:50:39.027638
10507 06:50:39.322529 06600000 ################################################################
10508 06:50:39.322709
10509 06:50:39.621079 06680000 ################################################################
10510 06:50:39.621260
10511 06:50:39.925973 06700000 ################################################################
10512 06:50:39.926138
10513 06:50:40.219757 06780000 ################################################################
10514 06:50:40.219912
10515 06:50:40.515565 06800000 ################################################################
10516 06:50:40.515722
10517 06:50:40.780672 06880000 ################################################################
10518 06:50:40.780827
10519 06:50:40.988685 06900000 ############################################# done.
10520 06:50:40.988847
10521 06:50:40.992466 The bootfile was 110467654 bytes long.
10522 06:50:40.992562
10523 06:50:40.995682 Sending tftp read request... done.
10524 06:50:40.995773
10525 06:50:40.995839 Waiting for the transfer...
10526 06:50:40.995899
10527 06:50:40.998629 00000000 # done.
10528 06:50:40.998716
10529 06:50:41.005488 Command line loaded dynamically from TFTP file: 12694799/tftp-deploy-zve8fp0e/kernel/cmdline
10530 06:50:41.005592
10531 06:50:41.018565 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10532 06:50:41.018708
10533 06:50:41.022266 Loading FIT.
10534 06:50:41.022356
10535 06:50:41.025315 Image ramdisk-1 has 98367757 bytes.
10536 06:50:41.025408
10537 06:50:41.025475 Image fdt-1 has 47278 bytes.
10538 06:50:41.025537
10539 06:50:41.028742 Image kernel-1 has 12050581 bytes.
10540 06:50:41.028835
10541 06:50:41.038531 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10542 06:50:41.038653
10543 06:50:41.055576 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10544 06:50:41.055732
10545 06:50:41.061928 Choosing best match conf-1 for compat google,spherion-rev2.
10546 06:50:41.065735
10547 06:50:41.070445 Connected to device vid:did:rid of 1ae0:0028:00
10548 06:50:41.078645
10549 06:50:41.081746 tpm_get_response: command 0x17b, return code 0x0
10550 06:50:41.081884
10551 06:50:41.084944 ec_init: CrosEC protocol v3 supported (256, 248)
10552 06:50:41.088957
10553 06:50:41.092459 tpm_cleanup: add release locality here.
10554 06:50:41.092547
10555 06:50:41.092613 Shutting down all USB controllers.
10556 06:50:41.095865
10557 06:50:41.095949 Removing current net device
10558 06:50:41.096016
10559 06:50:41.102487 Exiting depthcharge with code 4 at timestamp: 93139363
10560 06:50:41.102572
10561 06:50:41.106298 LZMA decompressing kernel-1 to 0x821a6718
10562 06:50:41.106382
10563 06:50:41.109321 LZMA decompressing kernel-1 to 0x40000000
10564 06:50:42.608415
10565 06:50:42.608611 jumping to kernel
10566 06:50:42.609178 end: 2.2.4 bootloader-commands (duration 00:01:05) [common]
10567 06:50:42.609277 start: 2.2.5 auto-login-action (timeout 00:03:20) [common]
10568 06:50:42.609352 Setting prompt string to ['Linux version [0-9]']
10569 06:50:42.609418 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10570 06:50:42.609483 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10571 06:50:42.689882
10572 06:50:42.693199 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10573 06:50:42.696407 start: 2.2.5.1 login-action (timeout 00:03:20) [common]
10574 06:50:42.696501 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10575 06:50:42.696571 Setting prompt string to []
10576 06:50:42.696650 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10577 06:50:42.696723 Using line separator: #'\n'#
10578 06:50:42.696781 No login prompt set.
10579 06:50:42.696842 Parsing kernel messages
10580 06:50:42.696897 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10581 06:50:42.696997 [login-action] Waiting for messages, (timeout 00:03:20)
10582 06:50:42.716295 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10583 06:50:42.719444 [ 0.000000] random: crng init done
10584 06:50:42.726513 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10585 06:50:42.729712 [ 0.000000] efi: UEFI not found.
10586 06:50:42.736253 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10587 06:50:42.743036 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10588 06:50:42.752642 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10589 06:50:42.762760 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10590 06:50:42.769371 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10591 06:50:42.775983 [ 0.000000] printk: bootconsole [mtk8250] enabled
10592 06:50:42.782433 [ 0.000000] NUMA: No NUMA configuration found
10593 06:50:42.789244 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10594 06:50:42.792459 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10595 06:50:42.795689 [ 0.000000] Zone ranges:
10596 06:50:42.802257 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10597 06:50:42.805613 [ 0.000000] DMA32 empty
10598 06:50:42.812488 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10599 06:50:42.815646 [ 0.000000] Movable zone start for each node
10600 06:50:42.818925 [ 0.000000] Early memory node ranges
10601 06:50:42.825921 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10602 06:50:42.832209 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10603 06:50:42.838741 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10604 06:50:42.845364 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10605 06:50:42.848752 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10606 06:50:42.858591 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10607 06:50:42.914332 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10608 06:50:42.921455 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10609 06:50:42.927517 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10610 06:50:42.931169 [ 0.000000] psci: probing for conduit method from DT.
10611 06:50:42.937695 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10612 06:50:42.940880 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10613 06:50:42.947678 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10614 06:50:42.950788 [ 0.000000] psci: SMC Calling Convention v1.2
10615 06:50:42.957708 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10616 06:50:42.960891 [ 0.000000] Detected VIPT I-cache on CPU0
10617 06:50:42.967441 [ 0.000000] CPU features: detected: GIC system register CPU interface
10618 06:50:42.973886 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10619 06:50:42.980642 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10620 06:50:42.987195 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10621 06:50:42.994191 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10622 06:50:43.003663 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10623 06:50:43.007149 [ 0.000000] alternatives: applying boot alternatives
10624 06:50:43.013562 [ 0.000000] Fallback order for Node 0: 0
10625 06:50:43.020316 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10626 06:50:43.023915 [ 0.000000] Policy zone: Normal
10627 06:50:43.036747 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10628 06:50:43.046999 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10629 06:50:43.058744 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10630 06:50:43.068647 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10631 06:50:43.075348 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10632 06:50:43.078781 <6>[ 0.000000] software IO TLB: area num 8.
10633 06:50:43.135719 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10634 06:50:43.284029 <6>[ 0.000000] Memory: 7871192K/8385536K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 481576K reserved, 32768K cma-reserved)
10635 06:50:43.290847 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10636 06:50:43.297514 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10637 06:50:43.300904 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10638 06:50:43.307329 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10639 06:50:43.314062 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10640 06:50:43.317257 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10641 06:50:43.327688 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10642 06:50:43.333857 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10643 06:50:43.337082 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10644 06:50:43.345060 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10645 06:50:43.348431 <6>[ 0.000000] GICv3: 608 SPIs implemented
10646 06:50:43.355345 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10647 06:50:43.358658 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10648 06:50:43.362407 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10649 06:50:43.372043 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10650 06:50:43.381758 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10651 06:50:43.394938 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10652 06:50:43.401515 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10653 06:50:43.410866 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10654 06:50:43.423843 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10655 06:50:43.430729 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10656 06:50:43.437157 <6>[ 0.009181] Console: colour dummy device 80x25
10657 06:50:43.447119 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10658 06:50:43.453714 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10659 06:50:43.456965 <6>[ 0.029251] LSM: Security Framework initializing
10660 06:50:43.464272 <6>[ 0.034191] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10661 06:50:43.473854 <6>[ 0.042053] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10662 06:50:43.480400 <6>[ 0.051472] cblist_init_generic: Setting adjustable number of callback queues.
10663 06:50:43.487144 <6>[ 0.058916] cblist_init_generic: Setting shift to 3 and lim to 1.
10664 06:50:43.496865 <6>[ 0.065294] cblist_init_generic: Setting adjustable number of callback queues.
10665 06:50:43.500393 <6>[ 0.072721] cblist_init_generic: Setting shift to 3 and lim to 1.
10666 06:50:43.506933 <6>[ 0.079123] rcu: Hierarchical SRCU implementation.
10667 06:50:43.513591 <6>[ 0.084139] rcu: Max phase no-delay instances is 1000.
10668 06:50:43.520524 <6>[ 0.091164] EFI services will not be available.
10669 06:50:43.523706 <6>[ 0.096147] smp: Bringing up secondary CPUs ...
10670 06:50:43.531539 <6>[ 0.101203] Detected VIPT I-cache on CPU1
10671 06:50:43.537898 <6>[ 0.101270] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10672 06:50:43.544518 <6>[ 0.101301] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10673 06:50:43.548281 <6>[ 0.101637] Detected VIPT I-cache on CPU2
10674 06:50:43.554584 <6>[ 0.101686] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10675 06:50:43.564730 <6>[ 0.101703] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10676 06:50:43.568054 <6>[ 0.101960] Detected VIPT I-cache on CPU3
10677 06:50:43.574651 <6>[ 0.102007] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10678 06:50:43.581117 <6>[ 0.102021] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10679 06:50:43.584464 <6>[ 0.102322] CPU features: detected: Spectre-v4
10680 06:50:43.591132 <6>[ 0.102329] CPU features: detected: Spectre-BHB
10681 06:50:43.594183 <6>[ 0.102333] Detected PIPT I-cache on CPU4
10682 06:50:43.601274 <6>[ 0.102390] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10683 06:50:43.607853 <6>[ 0.102407] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10684 06:50:43.614714 <6>[ 0.102698] Detected PIPT I-cache on CPU5
10685 06:50:43.620958 <6>[ 0.102760] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10686 06:50:43.627456 <6>[ 0.102777] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10687 06:50:43.630855 <6>[ 0.103058] Detected PIPT I-cache on CPU6
10688 06:50:43.637458 <6>[ 0.103115] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10689 06:50:43.644284 <6>[ 0.103131] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10690 06:50:43.650805 <6>[ 0.103415] Detected PIPT I-cache on CPU7
10691 06:50:43.657316 <6>[ 0.103473] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10692 06:50:43.663785 <6>[ 0.103489] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10693 06:50:43.667075 <6>[ 0.103535] smp: Brought up 1 node, 8 CPUs
10694 06:50:43.673610 <6>[ 0.244980] SMP: Total of 8 processors activated.
10695 06:50:43.677041 <6>[ 0.249901] CPU features: detected: 32-bit EL0 Support
10696 06:50:43.687039 <6>[ 0.255263] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10697 06:50:43.693927 <6>[ 0.264064] CPU features: detected: Common not Private translations
10698 06:50:43.700523 <6>[ 0.270540] CPU features: detected: CRC32 instructions
10699 06:50:43.703831 <6>[ 0.275891] CPU features: detected: RCpc load-acquire (LDAPR)
10700 06:50:43.710413 <6>[ 0.281851] CPU features: detected: LSE atomic instructions
10701 06:50:43.717053 <6>[ 0.287633] CPU features: detected: Privileged Access Never
10702 06:50:43.723435 <6>[ 0.293412] CPU features: detected: RAS Extension Support
10703 06:50:43.730155 <6>[ 0.299021] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10704 06:50:43.733839 <6>[ 0.306241] CPU: All CPU(s) started at EL2
10705 06:50:43.740256 <6>[ 0.310558] alternatives: applying system-wide alternatives
10706 06:50:43.748862 <6>[ 0.321234] devtmpfs: initialized
10707 06:50:43.761696 <6>[ 0.330171] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10708 06:50:43.771515 <6>[ 0.340127] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10709 06:50:43.777854 <6>[ 0.348357] pinctrl core: initialized pinctrl subsystem
10710 06:50:43.781462 <6>[ 0.354985] DMI not present or invalid.
10711 06:50:43.787719 <6>[ 0.359395] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10712 06:50:43.797750 <6>[ 0.366266] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10713 06:50:43.804930 <6>[ 0.373849] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10714 06:50:43.814389 <6>[ 0.382073] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10715 06:50:43.817886 <6>[ 0.390312] audit: initializing netlink subsys (disabled)
10716 06:50:43.827666 <5>[ 0.396006] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10717 06:50:43.834460 <6>[ 0.396702] thermal_sys: Registered thermal governor 'step_wise'
10718 06:50:43.840854 <6>[ 0.403972] thermal_sys: Registered thermal governor 'power_allocator'
10719 06:50:43.844417 <6>[ 0.410226] cpuidle: using governor menu
10720 06:50:43.850959 <6>[ 0.421183] NET: Registered PF_QIPCRTR protocol family
10721 06:50:43.857306 <6>[ 0.426655] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10722 06:50:43.860992 <6>[ 0.433755] ASID allocator initialised with 32768 entries
10723 06:50:43.868044 <6>[ 0.440320] Serial: AMBA PL011 UART driver
10724 06:50:43.877009 <4>[ 0.449098] Trying to register duplicate clock ID: 134
10725 06:50:43.930770 <6>[ 0.506151] KASLR enabled
10726 06:50:43.945009 <6>[ 0.513759] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10727 06:50:43.951613 <6>[ 0.520773] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10728 06:50:43.958401 <6>[ 0.527260] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10729 06:50:43.964868 <6>[ 0.534264] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10730 06:50:43.971570 <6>[ 0.540749] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10731 06:50:43.977888 <6>[ 0.547755] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10732 06:50:43.984612 <6>[ 0.554242] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10733 06:50:43.991111 <6>[ 0.561247] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10734 06:50:43.994810 <6>[ 0.568700] ACPI: Interpreter disabled.
10735 06:50:44.002962 <6>[ 0.575138] iommu: Default domain type: Translated
10736 06:50:44.009428 <6>[ 0.580250] iommu: DMA domain TLB invalidation policy: strict mode
10737 06:50:44.013173 <5>[ 0.586913] SCSI subsystem initialized
10738 06:50:44.019460 <6>[ 0.591157] usbcore: registered new interface driver usbfs
10739 06:50:44.026222 <6>[ 0.596889] usbcore: registered new interface driver hub
10740 06:50:44.029095 <6>[ 0.602443] usbcore: registered new device driver usb
10741 06:50:44.036462 <6>[ 0.608558] pps_core: LinuxPPS API ver. 1 registered
10742 06:50:44.046425 <6>[ 0.613751] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10743 06:50:44.049847 <6>[ 0.623092] PTP clock support registered
10744 06:50:44.053232 <6>[ 0.627330] EDAC MC: Ver: 3.0.0
10745 06:50:44.060703 <6>[ 0.632522] FPGA manager framework
10746 06:50:44.063931 <6>[ 0.636198] Advanced Linux Sound Architecture Driver Initialized.
10747 06:50:44.067633 <6>[ 0.642960] vgaarb: loaded
10748 06:50:44.074310 <6>[ 0.646096] clocksource: Switched to clocksource arch_sys_counter
10749 06:50:44.080645 <5>[ 0.652538] VFS: Disk quotas dquot_6.6.0
10750 06:50:44.087572 <6>[ 0.656726] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10751 06:50:44.090435 <6>[ 0.663919] pnp: PnP ACPI: disabled
10752 06:50:44.098380 <6>[ 0.670580] NET: Registered PF_INET protocol family
10753 06:50:44.108109 <6>[ 0.676169] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10754 06:50:44.119784 <6>[ 0.688479] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10755 06:50:44.129887 <6>[ 0.697296] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10756 06:50:44.136428 <6>[ 0.705268] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10757 06:50:44.142910 <6>[ 0.713965] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10758 06:50:44.154795 <6>[ 0.723687] TCP: Hash tables configured (established 65536 bind 65536)
10759 06:50:44.161301 <6>[ 0.730556] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10760 06:50:44.168023 <6>[ 0.737758] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10761 06:50:44.174932 <6>[ 0.745468] NET: Registered PF_UNIX/PF_LOCAL protocol family
10762 06:50:44.181448 <6>[ 0.751615] RPC: Registered named UNIX socket transport module.
10763 06:50:44.184651 <6>[ 0.757767] RPC: Registered udp transport module.
10764 06:50:44.191391 <6>[ 0.762697] RPC: Registered tcp transport module.
10765 06:50:44.197819 <6>[ 0.767630] RPC: Registered tcp NFSv4.1 backchannel transport module.
10766 06:50:44.201425 <6>[ 0.774295] PCI: CLS 0 bytes, default 64
10767 06:50:44.204314 <6>[ 0.778647] Unpacking initramfs...
10768 06:50:44.229534 <6>[ 0.798205] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10769 06:50:44.239353 <6>[ 0.806842] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10770 06:50:44.242379 <6>[ 0.815689] kvm [1]: IPA Size Limit: 40 bits
10771 06:50:44.249511 <6>[ 0.820214] kvm [1]: GICv3: no GICV resource entry
10772 06:50:44.252454 <6>[ 0.825232] kvm [1]: disabling GICv2 emulation
10773 06:50:44.259303 <6>[ 0.829915] kvm [1]: GIC system register CPU interface enabled
10774 06:50:44.262402 <6>[ 0.836072] kvm [1]: vgic interrupt IRQ18
10775 06:50:44.268992 <6>[ 0.840419] kvm [1]: VHE mode initialized successfully
10776 06:50:44.275536 <5>[ 0.846816] Initialise system trusted keyrings
10777 06:50:44.282110 <6>[ 0.851612] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10778 06:50:44.289359 <6>[ 0.861659] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10779 06:50:44.296269 <5>[ 0.868105] NFS: Registering the id_resolver key type
10780 06:50:44.299805 <5>[ 0.873415] Key type id_resolver registered
10781 06:50:44.305890 <5>[ 0.877830] Key type id_legacy registered
10782 06:50:44.312902 <6>[ 0.882116] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10783 06:50:44.319274 <6>[ 0.889036] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10784 06:50:44.325800 <6>[ 0.896804] 9p: Installing v9fs 9p2000 file system support
10785 06:50:44.362685 <5>[ 0.934777] Key type asymmetric registered
10786 06:50:44.365920 <5>[ 0.939107] Asymmetric key parser 'x509' registered
10787 06:50:44.375948 <6>[ 0.944244] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10788 06:50:44.379314 <6>[ 0.951859] io scheduler mq-deadline registered
10789 06:50:44.382326 <6>[ 0.956618] io scheduler kyber registered
10790 06:50:44.401344 <6>[ 0.973632] EINJ: ACPI disabled.
10791 06:50:44.433280 <4>[ 0.998986] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10792 06:50:44.443711 <4>[ 1.009610] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10793 06:50:44.458637 <6>[ 1.030756] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10794 06:50:44.466778 <6>[ 1.038811] printk: console [ttyS0] disabled
10795 06:50:44.494657 <6>[ 1.063458] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10796 06:50:44.501378 <6>[ 1.072935] printk: console [ttyS0] enabled
10797 06:50:44.504936 <6>[ 1.072935] printk: console [ttyS0] enabled
10798 06:50:44.511298 <6>[ 1.081829] printk: bootconsole [mtk8250] disabled
10799 06:50:44.514288 <6>[ 1.081829] printk: bootconsole [mtk8250] disabled
10800 06:50:44.521642 <6>[ 1.092909] SuperH (H)SCI(F) driver initialized
10801 06:50:44.524357 <6>[ 1.098194] msm_serial: driver initialized
10802 06:50:44.538279 <6>[ 1.107158] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10803 06:50:44.548189 <6>[ 1.115704] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10804 06:50:44.554813 <6>[ 1.124247] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10805 06:50:44.564899 <6>[ 1.132876] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10806 06:50:44.574882 <6>[ 1.141582] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10807 06:50:44.581210 <6>[ 1.150302] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10808 06:50:44.591584 <6>[ 1.158843] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10809 06:50:44.597825 <6>[ 1.167647] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10810 06:50:44.607944 <6>[ 1.176190] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10811 06:50:44.619709 <6>[ 1.191983] loop: module loaded
10812 06:50:44.626352 <6>[ 1.197958] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10813 06:50:44.648956 <4>[ 1.221212] mtk-pmic-keys: Failed to locate of_node [id: -1]
10814 06:50:44.655793 <6>[ 1.228100] megasas: 07.719.03.00-rc1
10815 06:50:44.665458 <6>[ 1.237734] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10816 06:50:44.673537 <6>[ 1.245473] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10817 06:50:44.690042 <6>[ 1.262160] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10818 06:50:44.745963 <6>[ 1.311744] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10819 06:50:48.209095 <6>[ 4.781249] Freeing initrd memory: 96060K
10820 06:50:48.219500 <6>[ 4.791761] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10821 06:50:48.231073 <6>[ 4.802885] tun: Universal TUN/TAP device driver, 1.6
10822 06:50:48.233879 <6>[ 4.808958] thunder_xcv, ver 1.0
10823 06:50:48.237164 <6>[ 4.812463] thunder_bgx, ver 1.0
10824 06:50:48.240334 <6>[ 4.815957] nicpf, ver 1.0
10825 06:50:48.250817 <6>[ 4.819979] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10826 06:50:48.254666 <6>[ 4.827455] hns3: Copyright (c) 2017 Huawei Corporation.
10827 06:50:48.261208 <6>[ 4.833042] hclge is initializing
10828 06:50:48.264281 <6>[ 4.836625] e1000: Intel(R) PRO/1000 Network Driver
10829 06:50:48.270721 <6>[ 4.841754] e1000: Copyright (c) 1999-2006 Intel Corporation.
10830 06:50:48.274077 <6>[ 4.847772] e1000e: Intel(R) PRO/1000 Network Driver
10831 06:50:48.280883 <6>[ 4.852988] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10832 06:50:48.287348 <6>[ 4.859175] igb: Intel(R) Gigabit Ethernet Network Driver
10833 06:50:48.294361 <6>[ 4.864824] igb: Copyright (c) 2007-2014 Intel Corporation.
10834 06:50:48.300983 <6>[ 4.870661] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10835 06:50:48.307315 <6>[ 4.877179] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10836 06:50:48.310971 <6>[ 4.883643] sky2: driver version 1.30
10837 06:50:48.317324 <6>[ 4.888642] VFIO - User Level meta-driver version: 0.3
10838 06:50:48.324556 <6>[ 4.896889] usbcore: registered new interface driver usb-storage
10839 06:50:48.331324 <6>[ 4.903337] usbcore: registered new device driver onboard-usb-hub
10840 06:50:48.340728 <6>[ 4.912494] mt6397-rtc mt6359-rtc: registered as rtc0
10841 06:50:48.350252 <6>[ 4.917956] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:50:14 UTC (1706943014)
10842 06:50:48.353410 <6>[ 4.927525] i2c_dev: i2c /dev entries driver
10843 06:50:48.370366 <6>[ 4.939287] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10844 06:50:48.390141 <6>[ 4.962304] cpu cpu0: EM: created perf domain
10845 06:50:48.393980 <6>[ 4.967248] cpu cpu4: EM: created perf domain
10846 06:50:48.400778 <6>[ 4.972867] sdhci: Secure Digital Host Controller Interface driver
10847 06:50:48.407628 <6>[ 4.979301] sdhci: Copyright(c) Pierre Ossman
10848 06:50:48.413974 <6>[ 4.984255] Synopsys Designware Multimedia Card Interface Driver
10849 06:50:48.420786 <6>[ 4.990893] sdhci-pltfm: SDHCI platform and OF driver helper
10850 06:50:48.424062 <6>[ 4.990947] mmc0: CQHCI version 5.10
10851 06:50:48.430561 <6>[ 5.001218] ledtrig-cpu: registered to indicate activity on CPUs
10852 06:50:48.436972 <6>[ 5.008335] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10853 06:50:48.443674 <6>[ 5.015405] usbcore: registered new interface driver usbhid
10854 06:50:48.447344 <6>[ 5.021227] usbhid: USB HID core driver
10855 06:50:48.453851 <6>[ 5.025421] spi_master spi0: will run message pump with realtime priority
10856 06:50:48.497990 <6>[ 5.063271] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10857 06:50:48.516389 <6>[ 5.078354] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10858 06:50:48.523758 <6>[ 5.093238] cros-ec-spi spi0.0: Chrome EC device registered
10859 06:50:48.526845 <6>[ 5.099301] mmc0: Command Queue Engine enabled
10860 06:50:48.533552 <6>[ 5.104069] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10861 06:50:48.539799 <6>[ 5.111694] mmcblk0: mmc0:0001 DA4128 116 GiB
10862 06:50:48.550068 <6>[ 5.122122] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10863 06:50:48.559901 <6>[ 5.126654] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10864 06:50:48.566449 <6>[ 5.129364] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10865 06:50:48.570562 <6>[ 5.138619] NET: Registered PF_PACKET protocol family
10866 06:50:48.576520 <6>[ 5.143271] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10867 06:50:48.579840 <6>[ 5.147945] 9pnet: Installing 9P2000 support
10868 06:50:48.586249 <6>[ 5.153816] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10869 06:50:48.593045 <5>[ 5.157638] Key type dns_resolver registered
10870 06:50:48.596855 <6>[ 5.169106] registered taskstats version 1
10871 06:50:48.602649 <5>[ 5.173489] Loading compiled-in X.509 certificates
10872 06:50:48.631228 <4>[ 5.196243] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10873 06:50:48.641017 <4>[ 5.206985] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10874 06:50:48.647212 <3>[ 5.217537] debugfs: File 'uA_load' in directory '/' already present!
10875 06:50:48.654052 <3>[ 5.224256] debugfs: File 'min_uV' in directory '/' already present!
10876 06:50:48.660648 <3>[ 5.231048] debugfs: File 'max_uV' in directory '/' already present!
10877 06:50:48.667635 <3>[ 5.237669] debugfs: File 'constraint_flags' in directory '/' already present!
10878 06:50:48.678190 <3>[ 5.247147] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10879 06:50:48.687700 <6>[ 5.259812] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10880 06:50:48.694667 <6>[ 5.266734] xhci-mtk 11200000.usb: xHCI Host Controller
10881 06:50:48.701093 <6>[ 5.272237] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10882 06:50:48.711141 <6>[ 5.280085] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10883 06:50:48.717933 <6>[ 5.289508] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10884 06:50:48.724731 <6>[ 5.295572] xhci-mtk 11200000.usb: xHCI Host Controller
10885 06:50:48.731166 <6>[ 5.301048] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10886 06:50:48.737856 <6>[ 5.308693] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10887 06:50:48.745022 <6>[ 5.316297] hub 1-0:1.0: USB hub found
10888 06:50:48.747933 <6>[ 5.320305] hub 1-0:1.0: 1 port detected
10889 06:50:48.754630 <6>[ 5.324572] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10890 06:50:48.761009 <6>[ 5.333126] hub 2-0:1.0: USB hub found
10891 06:50:48.764277 <6>[ 5.337130] hub 2-0:1.0: 1 port detected
10892 06:50:48.772920 <6>[ 5.345117] mtk-msdc 11f70000.mmc: Got CD GPIO
10893 06:50:48.783025 <6>[ 5.352121] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10894 06:50:48.789690 <6>[ 5.360153] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10895 06:50:48.799869 <4>[ 5.368141] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10896 06:50:48.809392 <6>[ 5.377669] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10897 06:50:48.816380 <6>[ 5.385765] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10898 06:50:48.822981 <6>[ 5.393770] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10899 06:50:48.832960 <6>[ 5.401700] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10900 06:50:48.839422 <6>[ 5.409518] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10901 06:50:48.849313 <6>[ 5.417347] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10902 06:50:48.859283 <6>[ 5.427730] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10903 06:50:48.866190 <6>[ 5.436112] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10904 06:50:48.875919 <6>[ 5.444455] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10905 06:50:48.882565 <6>[ 5.452809] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10906 06:50:48.893196 <6>[ 5.461149] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10907 06:50:48.899123 <6>[ 5.469499] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10908 06:50:48.909426 <6>[ 5.477840] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10909 06:50:48.916163 <6>[ 5.486195] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10910 06:50:48.925654 <6>[ 5.494535] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10911 06:50:48.932705 <6>[ 5.502882] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10912 06:50:48.942425 <6>[ 5.511221] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10913 06:50:48.952172 <6>[ 5.519563] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10914 06:50:48.958606 <6>[ 5.527902] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10915 06:50:48.968825 <6>[ 5.536241] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10916 06:50:48.975396 <6>[ 5.544580] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10917 06:50:48.982201 <6>[ 5.553337] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10918 06:50:48.988771 <6>[ 5.560496] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10919 06:50:48.994857 <6>[ 5.567263] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10920 06:50:49.005238 <6>[ 5.574019] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10921 06:50:49.011555 <6>[ 5.580952] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10922 06:50:49.018094 <6>[ 5.587787] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10923 06:50:49.027776 <6>[ 5.596915] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10924 06:50:49.038073 <6>[ 5.606035] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10925 06:50:49.047844 <6>[ 5.615348] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10926 06:50:49.057875 <6>[ 5.624819] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10927 06:50:49.067709 <6>[ 5.634285] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10928 06:50:49.074682 <6>[ 5.643404] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10929 06:50:49.083905 <6>[ 5.652870] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10930 06:50:49.094269 <6>[ 5.661988] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10931 06:50:49.104220 <6>[ 5.671282] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10932 06:50:49.114093 <6>[ 5.681442] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10933 06:50:49.124525 <6>[ 5.693524] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10934 06:50:49.153476 <6>[ 5.722594] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10935 06:50:49.181298 <6>[ 5.753347] hub 2-1:1.0: USB hub found
10936 06:50:49.184624 <6>[ 5.757784] hub 2-1:1.0: 3 ports detected
10937 06:50:49.193035 <6>[ 5.764745] hub 2-1:1.0: USB hub found
10938 06:50:49.196005 <6>[ 5.769215] hub 2-1:1.0: 3 ports detected
10939 06:50:49.305275 <6>[ 5.874390] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10940 06:50:49.460536 <6>[ 6.032520] hub 1-1:1.0: USB hub found
10941 06:50:49.463513 <6>[ 6.037023] hub 1-1:1.0: 4 ports detected
10942 06:50:49.473153 <6>[ 6.045182] hub 1-1:1.0: USB hub found
10943 06:50:49.476327 <6>[ 6.049633] hub 1-1:1.0: 4 ports detected
10944 06:50:49.545613 <6>[ 6.114498] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10945 06:50:49.797169 <6>[ 6.366419] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10946 06:50:49.929699 <6>[ 6.501815] hub 1-1.4:1.0: USB hub found
10947 06:50:49.932825 <6>[ 6.506358] hub 1-1.4:1.0: 2 ports detected
10948 06:50:49.942439 <6>[ 6.514180] hub 1-1.4:1.0: USB hub found
10949 06:50:49.945189 <6>[ 6.518787] hub 1-1.4:1.0: 2 ports detected
10950 06:50:50.241532 <6>[ 6.810394] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10951 06:50:50.433388 <6>[ 7.002485] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10952 06:51:01.422381 <6>[ 17.999474] ALSA device list:
10953 06:51:01.428671 <6>[ 18.002779] No soundcards found.
10954 06:51:01.437042 <6>[ 18.010922] Freeing unused kernel memory: 8448K
10955 06:51:01.440604 <6>[ 18.015956] Run /init as init process
10956 06:51:01.493990 <6>[ 18.067481] NET: Registered PF_INET6 protocol family
10957 06:51:01.500795 <6>[ 18.073750] Segment Routing with IPv6
10958 06:51:01.503844 <6>[ 18.077688] In-situ OAM (IOAM) with IPv6
10959 06:51:01.538673 <30>[ 18.092398] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10960 06:51:01.541726 <30>[ 18.116238] systemd[1]: Detected architecture arm64.
10961 06:51:01.542248
10962 06:51:01.547980 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10963 06:51:01.548457
10964 06:51:01.560489 <30>[ 18.134310] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10965 06:51:01.686050 <30>[ 18.256502] systemd[1]: Queued start job for default target Graphical Interface.
10966 06:51:01.729665 <30>[ 18.303308] systemd[1]: Created slice system-getty.slice.
10967 06:51:01.736101 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10968 06:51:01.753459 <30>[ 18.327035] systemd[1]: Created slice system-modprobe.slice.
10969 06:51:01.759877 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10970 06:51:01.777322 <30>[ 18.350820] systemd[1]: Created slice system-serial\x2dgetty.slice.
10971 06:51:01.787034 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10972 06:51:01.801081 <30>[ 18.374624] systemd[1]: Created slice User and Session Slice.
10973 06:51:01.807771 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10974 06:51:01.828575 <30>[ 18.398950] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10975 06:51:01.838476 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10976 06:51:01.856374 <30>[ 18.427020] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10977 06:51:01.863015 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10978 06:51:01.887521 <30>[ 18.454528] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10979 06:51:01.894435 <30>[ 18.466709] systemd[1]: Reached target Local Encrypted Volumes.
10980 06:51:01.900895 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10981 06:51:01.916934 <30>[ 18.490968] systemd[1]: Reached target Paths.
10982 06:51:01.923499 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10983 06:51:01.936736 <30>[ 18.510395] systemd[1]: Reached target Remote File Systems.
10984 06:51:01.943107 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10985 06:51:01.960688 <30>[ 18.534770] systemd[1]: Reached target Slices.
10986 06:51:01.967023 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10987 06:51:01.981027 <30>[ 18.554461] systemd[1]: Reached target Swap.
10988 06:51:01.984120 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10989 06:51:02.004570 <30>[ 18.574922] systemd[1]: Listening on initctl Compatibility Named Pipe.
10990 06:51:02.010975 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10991 06:51:02.017666 <30>[ 18.590302] systemd[1]: Listening on Journal Audit Socket.
10992 06:51:02.024370 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10993 06:51:02.037305 <30>[ 18.610947] systemd[1]: Listening on Journal Socket (/dev/log).
10994 06:51:02.044168 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10995 06:51:02.062318 <30>[ 18.635730] systemd[1]: Listening on Journal Socket.
10996 06:51:02.068547 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10997 06:51:02.081169 <30>[ 18.655040] systemd[1]: Listening on udev Control Socket.
10998 06:51:02.087869 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10999 06:51:02.106004 <30>[ 18.679499] systemd[1]: Listening on udev Kernel Socket.
11000 06:51:02.112822 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
11001 06:51:02.164475 <30>[ 18.738614] systemd[1]: Mounting Huge Pages File System...
11002 06:51:02.171577 Mounting [0;1;39mHuge Pages File System[0m...
11003 06:51:02.189246 <30>[ 18.762821] systemd[1]: Mounting POSIX Message Queue File System...
11004 06:51:02.195568 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11005 06:51:02.216774 <30>[ 18.790611] systemd[1]: Mounting Kernel Debug File System...
11006 06:51:02.223159 Mounting [0;1;39mKernel Debug File System[0m...
11007 06:51:02.240129 <30>[ 18.810861] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11008 06:51:02.288348 <30>[ 18.858903] systemd[1]: Starting Create list of static device nodes for the current kernel...
11009 06:51:02.294762 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11010 06:51:02.317113 <30>[ 18.891138] systemd[1]: Starting Load Kernel Module configfs...
11011 06:51:02.323741 Starting [0;1;39mLoad Kernel Module configfs[0m...
11012 06:51:02.338760 <30>[ 18.912668] systemd[1]: Starting Load Kernel Module drm...
11013 06:51:02.345297 Starting [0;1;39mLoad Kernel Module drm[0m...
11014 06:51:02.364128 <30>[ 18.934837] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11015 06:51:02.400905 <30>[ 18.974782] systemd[1]: Starting Journal Service...
11016 06:51:02.404376 Starting [0;1;39mJournal Service[0m...
11017 06:51:02.423463 <30>[ 18.997248] systemd[1]: Starting Load Kernel Modules...
11018 06:51:02.429800 Starting [0;1;39mLoad Kernel Modules[0m...
11019 06:51:02.450308 <30>[ 19.021134] systemd[1]: Starting Remount Root and Kernel File Systems...
11020 06:51:02.456709 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11021 06:51:02.471171 <30>[ 19.045155] systemd[1]: Starting Coldplug All udev Devices...
11022 06:51:02.477719 Starting [0;1;39mColdplug All udev Devices[0m...
11023 06:51:02.495673 <30>[ 19.069494] systemd[1]: Started Journal Service.
11024 06:51:02.501969 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11025 06:51:02.519803 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11026 06:51:02.537323 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11027 06:51:02.553826 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11028 06:51:02.573682 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11029 06:51:02.591212 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11030 06:51:02.610995 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11031 06:51:02.629426 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11032 06:51:02.649345 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11033 06:51:02.664391 See 'systemctl status systemd-remount-fs.service' for details.
11034 06:51:02.701579 Mounting [0;1;39mKernel Configuration File System[0m...
11035 06:51:02.719306 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11036 06:51:02.731993 <46>[ 19.303152] systemd-journald[180]: Received client request to flush runtime journal.
11037 06:51:02.743818 Starting [0;1;39mLoad/Save Random Seed[0m...
11038 06:51:02.764432 Starting [0;1;39mApply Kernel Variables[0m...
11039 06:51:02.789168 Starting [0;1;39mCreate System Users[0m...
11040 06:51:02.813878 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11041 06:51:02.832924 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11042 06:51:02.853054 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11043 06:51:02.866195 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11044 06:51:02.881970 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11045 06:51:02.898174 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11046 06:51:02.937133 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11047 06:51:02.959852 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11048 06:51:02.972326 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11049 06:51:02.987941 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11050 06:51:03.032653 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11051 06:51:03.056779 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11052 06:51:03.077433 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11053 06:51:03.101450 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11054 06:51:03.194979 Starting [0;1;39mNetwork Time Synchronization[0m...
11055 06:51:03.201631 <6>[ 19.775339] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11056 06:51:03.221574 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11057 06:51:03.235624 <6>[ 19.806854] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11058 06:51:03.245824 <6>[ 19.817007] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11059 06:51:03.255850 <6>[ 19.825946] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11060 06:51:03.263395 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11061 06:51:03.273061 <3>[ 19.842833] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11062 06:51:03.279754 <3>[ 19.850959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11063 06:51:03.286177 <3>[ 19.859234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11064 06:51:03.293307 <6>[ 19.859426] remoteproc remoteproc0: scp is available
11065 06:51:03.300128 <6>[ 19.873628] remoteproc remoteproc0: powering up scp
11066 06:51:03.306701 <6>[ 19.878818] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11067 06:51:03.313489 <6>[ 19.881213] usbcore: registered new device driver r8152-cfgselector
11068 06:51:03.319912 <6>[ 19.887605] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11069 06:51:03.329690 <3>[ 19.899288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11070 06:51:03.336388 <3>[ 19.908527] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11071 06:51:03.346327 [[0;32m OK [<3>[ 19.917388] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11072 06:51:03.356143 0m] Created slic<3>[ 19.926753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11073 06:51:03.366189 e [0;1;39msyste<3>[ 19.936103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11074 06:51:03.376369 m-systemd\x2dbac<6>[ 19.937498] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11075 06:51:03.379667 klight.slice[0m<6>[ 19.947843] mc: Linux media interface: v0.10
11076 06:51:03.389276 <4>[ 19.948271] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11077 06:51:03.396003 <4>[ 19.948394] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11078 06:51:03.396088 .
11079 06:51:03.402738 <3>[ 19.951330] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11080 06:51:03.412640 <3>[ 19.951401] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11081 06:51:03.419198 <3>[ 19.951405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11082 06:51:03.429388 <3>[ 19.951408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11083 06:51:03.435983 <3>[ 19.951468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11084 06:51:03.445906 <3>[ 19.951473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11085 06:51:03.452343 <3>[ 19.951478] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11086 06:51:03.459270 <3>[ 19.951486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11087 06:51:03.469069 <3>[ 19.951488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11088 06:51:03.476084 <3>[ 19.951505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11089 06:51:03.482610 <6>[ 19.972590] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11090 06:51:03.492859 <6>[ 20.023251] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11091 06:51:03.499605 <6>[ 20.024626] pci_bus 0000:00: root bus resource [bus 00-ff]
11092 06:51:03.509646 <6>[ 20.025105] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11093 06:51:03.515936 <6>[ 20.025113] remoteproc remoteproc0: remote processor scp is now up
11094 06:51:03.522708 <6>[ 20.025113] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11095 06:51:03.529548 <6>[ 20.032265] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11096 06:51:03.539216 <6>[ 20.033384] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11097 06:51:03.545798 <6>[ 20.035895] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11098 06:51:03.555875 <6>[ 20.040049] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11099 06:51:03.565685 <6>[ 20.040055] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11100 06:51:03.569373 <6>[ 20.040096] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11101 06:51:03.578740 <4>[ 20.041575] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11102 06:51:03.585753 <4>[ 20.041575] Fallback method does not support PEC.
11103 06:51:03.592017 <6>[ 20.042764] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11104 06:51:03.602304 <6>[ 20.052911] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11105 06:51:03.608542 <6>[ 20.056978] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11106 06:51:03.618777 <3>[ 20.067742] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11107 06:51:03.621746 <6>[ 20.073532] pci 0000:00:00.0: supports D1 D2
11108 06:51:03.628661 <6>[ 20.075662] videodev: Linux video capture interface: v2.00
11109 06:51:03.638692 <4>[ 20.081883] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11110 06:51:03.644779 <6>[ 20.087686] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11111 06:51:03.652472 <6>[ 20.090033] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11112 06:51:03.662177 <4>[ 20.094232] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11113 06:51:03.665392 <6>[ 20.094895] Bluetooth: Core ver 2.22
11114 06:51:03.668698 <6>[ 20.094971] NET: Registered PF_BLUETOOTH protocol family
11115 06:51:03.675257 <6>[ 20.094973] Bluetooth: HCI device and connection manager initialized
11116 06:51:03.682438 <6>[ 20.094991] Bluetooth: HCI socket layer initialized
11117 06:51:03.685896 <6>[ 20.095001] Bluetooth: L2CAP socket layer initialized
11118 06:51:03.693176 <6>[ 20.095010] Bluetooth: SCO socket layer initialized
11119 06:51:03.700188 <6>[ 20.101486] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11120 06:51:03.703968 <6>[ 20.145187] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11121 06:51:03.710970 <6>[ 20.145287] usbcore: registered new interface driver btusb
11122 06:51:03.721342 <4>[ 20.146269] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11123 06:51:03.728243 <3>[ 20.146283] Bluetooth: hci0: Failed to load firmware file (-2)
11124 06:51:03.735352 <3>[ 20.146286] Bluetooth: hci0: Failed to set up firmware (-2)
11125 06:51:03.744909 <4>[ 20.146289] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11126 06:51:03.751730 <6>[ 20.150128] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11127 06:51:03.765746 <6>[ 20.165433] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11128 06:51:03.772446 <6>[ 20.172092] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11129 06:51:03.775480 <6>[ 20.174223] r8152 2-1.3:1.0 eth0: v1.12.13
11130 06:51:03.782286 <6>[ 20.174265] usbcore: registered new interface driver r8152
11131 06:51:03.789137 <6>[ 20.181580] usbcore: registered new interface driver uvcvideo
11132 06:51:03.792693 <6>[ 20.181964] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11133 06:51:03.799976 <6>[ 20.188874] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11134 06:51:03.806742 <6>[ 20.202732] usbcore: registered new interface driver cdc_ether
11135 06:51:03.813015 <6>[ 20.208000] pci 0000:01:00.0: supports D1 D2
11136 06:51:03.820130 <6>[ 20.232205] usbcore: registered new interface driver r8153_ecm
11137 06:51:03.826671 <6>[ 20.240116] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11138 06:51:03.830442 <6>[ 20.250324] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11139 06:51:03.837045 <6>[ 20.266853] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
11140 06:51:03.846794 <6>[ 20.271693] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11141 06:51:03.853655 <3>[ 20.279868] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11142 06:51:03.863812 <3>[ 20.280559] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11143 06:51:03.870500 <6>[ 20.284969] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11144 06:51:03.880299 <6>[ 20.284978] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11145 06:51:03.887096 <6>[ 20.284991] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11146 06:51:03.896822 <3>[ 20.288927] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11147 06:51:03.903714 <3>[ 20.291576] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11148 06:51:03.914273 <6>[ 20.301239] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11149 06:51:03.917691 <6>[ 20.301255] pci 0000:00:00.0: PCI bridge to [bus 01]
11150 06:51:03.927841 <3>[ 20.312359] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11151 06:51:03.934702 <6>[ 20.313151] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11152 06:51:03.944475 <3>[ 20.345007] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11153 06:51:03.951450 <6>[ 20.351140] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11154 06:51:03.958234 <3>[ 20.375345] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11155 06:51:03.964935 <6>[ 20.381540] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11156 06:51:03.975659 <3>[ 20.406837] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11157 06:51:03.978527 <6>[ 20.412056] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11158 06:51:03.988725 <3>[ 20.437441] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11159 06:51:03.995402 <5>[ 20.461362] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11160 06:51:04.005367 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11161 06:51:04.018694 <5>[ 20.589582] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11162 06:51:04.025201 <5>[ 20.596692] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11163 06:51:04.035224 <4>[ 20.605105] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11164 06:51:04.038771 <6>[ 20.605113] cfg80211: failed to load regulatory.db
11165 06:51:04.045375 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11166 06:51:04.080844 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m<6>[ 20.651641] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11167 06:51:04.080985 .
11168 06:51:04.087769 <6>[ 20.660135] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11169 06:51:04.101780 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11170 06:51:04.112671 <6>[ 20.687046] mt7921e 0000:01:00.0: ASIC revision: 79610010
11171 06:51:04.214270 <6>[ 20.785505] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11172 06:51:04.217510 <6>[ 20.785505]
11173 06:51:04.268578 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11174 06:51:04.284172 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11175 06:51:04.303157 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11176 06:51:04.315926 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11177 06:51:04.335700 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11178 06:51:04.359763 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11179 06:51:04.372369 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11180 06:51:04.395710 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11181 06:51:04.411891 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11182 06:51:04.427945 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11183 06:51:04.447626 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11184 06:51:04.482067 <6>[ 21.053112] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11185 06:51:04.488373 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11186 06:51:04.515791 Starting [0;1;39mUser Login Management[0m...
11187 06:51:04.536580 Starting [0;1;39mPermit User Sessions[0m...
11188 06:51:04.556491 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11189 06:51:04.572927 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11190 06:51:04.593160 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11191 06:51:04.608203 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11192 06:51:04.628825 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11193 06:51:04.646455 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11194 06:51:04.665262 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11195 06:51:04.682461 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11196 06:51:04.700924 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11197 06:51:04.754124 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11198 06:51:04.796923 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11199 06:51:04.845772
11200 06:51:04.845882
11201 06:51:04.848988 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11202 06:51:04.849073
11203 06:51:04.852508 debian-bullseye-arm64 login: root (automatic login)
11204 06:51:04.852593
11205 06:51:04.852659
11206 06:51:04.879417 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
11207 06:51:04.879513
11208 06:51:04.885690 The programs included with the Debian GNU/Linux system are free software;
11209 06:51:04.892517 the exact distribution terms for each program are described in the
11210 06:51:04.895584 individual files in /usr/share/doc/*/copyright.
11211 06:51:04.895669
11212 06:51:04.902127 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11213 06:51:04.905440 permitted by applicable law.
11214 06:51:04.905819 Matched prompt #10: / #
11216 06:51:04.906034 Setting prompt string to ['/ #']
11217 06:51:04.906127 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11219 06:51:04.906321 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11220 06:51:04.906409 start: 2.2.6 expect-shell-connection (timeout 00:02:58) [common]
11221 06:51:04.906478 Setting prompt string to ['/ #']
11222 06:51:04.906539 Forcing a shell prompt, looking for ['/ #']
11224 06:51:04.956750 / #
11225 06:51:04.956854 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11226 06:51:04.956930 Waiting using forced prompt support (timeout 00:02:30)
11227 06:51:04.962132
11228 06:51:04.962403 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11229 06:51:04.962497 start: 2.2.7 export-device-env (timeout 00:02:58) [common]
11230 06:51:04.962592 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11231 06:51:04.962683 end: 2.2 depthcharge-retry (duration 00:02:02) [common]
11232 06:51:04.962771 end: 2 depthcharge-action (duration 00:02:02) [common]
11233 06:51:04.962859 start: 3 lava-test-retry (timeout 00:05:00) [common]
11234 06:51:04.962946 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11235 06:51:04.963021 Using namespace: common
11237 06:51:05.063348 / # #
11238 06:51:05.063458 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11239 06:51:05.068489 #
11240 06:51:05.068759 Using /lava-12694799
11242 06:51:05.169110 / # export SHELL=/bin/sh
11243 06:51:05.174459 export SHELL=/bin/sh
11245 06:51:05.275022 / # . /lava-12694799/environment
11246 06:51:05.280476 . /lava-12694799/environment
11248 06:51:05.381062 / # /lava-12694799/bin/lava-test-runner /lava-12694799/0
11249 06:51:05.381254 Test shell timeout: 10s (minimum of the action and connection timeout)
11250 06:51:05.381617 <6>[ 21.902902] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11251 06:51:05.388507 /lava-12694799/bin/lava-test-runner /lava-12694799/0
11252 06:51:05.430118 + export TESTRUN_ID=0_sleep
11253 06:51:05.430255 + cd /lava-12694799/0/tests/0_sleep
11254 06:51:05.430327 + cat uuid
11255 06:51:05.430391 + UUID=12694799_1.5.2.3.1
11256 06:51:05.430453 + set +x
11257 06:51:05.430513 <LAVA_SIGNAL_STARTRUN 0_sleep 12694799_1.5.2.3.1>
11258 06:51:05.430572 + ./config/lava/sleep/sleep.sh mem
11259 06:51:05.430817 Received signal: <STARTRUN> 0_sleep 12694799_1.5.2.3.1
11260 06:51:05.430886 Starting test lava.0_sleep (12694799_1.5.2.3.1)
11261 06:51:05.430969 Skipping test definition patterns.
11262 06:51:05.432418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11263 06:51:05.432685 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11265 06:51:05.438544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11266 06:51:05.438801 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11268 06:51:05.441883 rtcwake: assuming RTC uses UTC ...
11269 06:51:05.448760 rtcwake: wakeup from "mem" using rtc0 at Sat Feb 3 06:50:37 2024
11270 06:51:05.451871 <6>[ 22.028627] PM: suspend entry (deep)
11271 06:51:05.458359 <6>[ 22.032633] Filesystems sync: 0.000 seconds
11272 06:51:05.461576 <6>[ 22.038450] Freezing user space processes
11273 06:51:05.472951 <6>[ 22.044343] Freezing user space processes completed (elapsed 0.001 seconds)
11274 06:51:05.476149 <6>[ 22.051560] OOM killer disabled.
11275 06:51:05.479330 <6>[ 22.055039] Freezing remaining freezable tasks
11276 06:51:05.489478 <6>[ 22.060983] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11277 06:51:05.496298 <6>[ 22.068647] printk: Suspending console(s) (use no_console_suspend to debug)
11278 06:51:11.573276 <6>[ 22.217589] Disabling non-boot CPUs ...
11279 06:51:11.576587 <4>[ 22.218740] IRQ283: set affinity failed(-22).
11280 06:51:11.583097 <4>[ 22.218759] IRQ284: set affinity failed(-22).
11281 06:51:11.586428 <6>[ 22.219850] psci: CPU1 killed (polled 0 ms)
11282 06:51:11.590097 <4>[ 22.221158] IRQ283: set affinity failed(-22).
11283 06:51:11.596793 <4>[ 22.221171] IRQ284: set affinity failed(-22).
11284 06:51:11.600283 <6>[ 22.222131] psci: CPU2 killed (polled 4 ms)
11285 06:51:11.603521 <4>[ 22.223661] IRQ283: set affinity failed(-22).
11286 06:51:11.610115 <4>[ 22.223674] IRQ284: set affinity failed(-22).
11287 06:51:11.613329 <6>[ 22.224746] psci: CPU3 killed (polled 0 ms)
11288 06:51:11.616478 <4>[ 22.225646] IRQ283: set affinity failed(-22).
11289 06:51:11.623387 <4>[ 22.225650] IRQ284: set affinity failed(-22).
11290 06:51:11.626575 <6>[ 22.225688] psci: CPU4 killed (polled 0 ms)
11291 06:51:11.633590 <4>[ 22.226768] IRQ283: set affinity failed(-22).
11292 06:51:11.636495 <4>[ 22.226775] IRQ284: set affinity failed(-22).
11293 06:51:11.640008 <6>[ 22.226813] psci: CPU5 killed (polled 0 ms)
11294 06:51:11.646651 <6>[ 22.227757] psci: CPU6 killed (polled 0 ms)
11295 06:51:11.650220 <6>[ 22.228728] psci: CPU7 killed (polled 0 ms)
11296 06:51:11.653295 <6>[ 22.229445] Enabling non-boot CPUs ...
11297 06:51:11.656459 <6>[ 22.229702] Detected VIPT I-cache on CPU1
11298 06:51:11.666385 <6>[ 22.229797] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11299 06:51:11.673342 <6>[ 22.229866] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11300 06:51:11.673427 <6>[ 22.230540] CPU1 is up
11301 06:51:11.679958 <6>[ 22.230703] Detected VIPT I-cache on CPU2
11302 06:51:11.686350 <6>[ 22.230768] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11303 06:51:11.692966 <6>[ 22.230813] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11304 06:51:11.696386 <6>[ 22.231356] CPU2 is up
11305 06:51:11.700022 <6>[ 22.231513] Detected VIPT I-cache on CPU3
11306 06:51:11.706487 <6>[ 22.231578] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11307 06:51:11.713271 <6>[ 22.231622] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11308 06:51:11.716396 <6>[ 22.232190] CPU3 is up
11309 06:51:11.722819 <6>[ 22.232316] CPU features: detected: Hardware dirty bit management
11310 06:51:11.726316 <6>[ 22.232335] Detected PIPT I-cache on CPU4
11311 06:51:11.733414 <6>[ 22.232360] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11312 06:51:11.739847 <6>[ 22.232378] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11313 06:51:11.742862 <6>[ 22.232701] CPU4 is up
11314 06:51:11.746427 <6>[ 22.232853] Detected PIPT I-cache on CPU5
11315 06:51:11.756719 <6>[ 22.232881] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11316 06:51:11.763288 <6>[ 22.232899] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11317 06:51:11.763374 <6>[ 22.233177] CPU5 is up
11318 06:51:11.769891 <6>[ 22.233317] Detected PIPT I-cache on CPU6
11319 06:51:11.776223 <6>[ 22.233345] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11320 06:51:11.783314 <6>[ 22.233363] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11321 06:51:11.786502 <6>[ 22.233648] CPU6 is up
11322 06:51:11.789705 <6>[ 22.233784] Detected PIPT I-cache on CPU7
11323 06:51:11.796166 <6>[ 22.233813] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11324 06:51:11.802681 <6>[ 22.233831] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11325 06:51:11.806402 <6>[ 22.234149] CPU7 is up
11326 06:51:11.812939 <4>[ 22.375127] typec port0-partner: PM: parent port0 should not be sleeping
11327 06:51:11.816283 <6>[ 22.837901] OOM killer enabled.
11328 06:51:11.822814 <6>[ 22.841292] Restarting tasks ... done.
11329 06:51:11.825840 <5>[ 22.845677] random: crng reseeded on system resumption
11330 06:51:11.829491 <6>[ 22.851995] PM: suspend exit
11331 06:51:11.841032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>
11332 06:51:11.841292 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=pass
11334 06:51:11.844388 rtcwake: assuming RTC uses UTC ...
11335 06:51:11.851003 rtcwake: wakeup from "mem" using rtc0 at Sat Feb 3 06:50:43 2024
11336 06:51:11.864375 <6>[ 22.883509] PM: suspend entry (deep)
11337 06:51:11.867492 <6>[ 22.887401] Filesystems sync: 0.000 seconds
11338 06:51:11.870876 <6>[ 22.892167] Freezing user space processes
11339 06:51:11.881777 <6>[ 22.897827] Freezing user space processes completed (elapsed 0.001 seconds)
11340 06:51:11.885202 <6>[ 22.905046] OOM killer disabled.
11341 06:51:11.888348 <6>[ 22.908526] Freezing remaining freezable tasks
11342 06:51:11.898329 <6>[ 22.914078] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11343 06:51:11.905053 <6>[ 22.921731] printk: Suspending console(s) (use no_console_suspend to debug)
11344 06:51:17.576615 <6>[ 23.016860] Disabling non-boot CPUs ...
11345 06:51:17.579964 <6>[ 23.017933] psci: CPU1 killed (polled 0 ms)
11346 06:51:17.583251 <6>[ 23.020323] psci: CPU2 killed (polled 0 ms)
11347 06:51:17.590137 <6>[ 23.022091] psci: CPU3 killed (polled 4 ms)
11348 06:51:17.593292 <6>[ 23.022677] psci: CPU4 killed (polled 0 ms)
11349 06:51:17.596408 <6>[ 23.023280] psci: CPU5 killed (polled 0 ms)
11350 06:51:17.603162 <6>[ 23.023897] psci: CPU6 killed (polled 0 ms)
11351 06:51:17.606350 <6>[ 23.024543] psci: CPU7 killed (polled 0 ms)
11352 06:51:17.609639 <6>[ 23.024866] Enabling non-boot CPUs ...
11353 06:51:17.616643 <6>[ 23.025112] Detected VIPT I-cache on CPU1
11354 06:51:17.623054 <6>[ 23.025204] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11355 06:51:17.629715 <6>[ 23.025271] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11356 06:51:17.633429 <6>[ 23.025991] CPU1 is up
11357 06:51:17.636584 <6>[ 23.026193] Detected VIPT I-cache on CPU2
11358 06:51:17.643401 <6>[ 23.026256] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11359 06:51:17.649797 <6>[ 23.026299] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11360 06:51:17.653183 <6>[ 23.026891] CPU2 is up
11361 06:51:17.656518 <6>[ 23.027044] Detected VIPT I-cache on CPU3
11362 06:51:17.663149 <6>[ 23.027107] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11363 06:51:17.669639 <6>[ 23.027150] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11364 06:51:17.672936 <6>[ 23.027749] CPU3 is up
11365 06:51:17.679562 <6>[ 23.027883] Detected PIPT I-cache on CPU4
11366 06:51:17.686386 <6>[ 23.027906] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11367 06:51:17.693140 <6>[ 23.027921] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11368 06:51:17.696050 <6>[ 23.028212] CPU4 is up
11369 06:51:17.699526 <6>[ 23.028340] Detected PIPT I-cache on CPU5
11370 06:51:17.706707 <6>[ 23.028363] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11371 06:51:17.712856 <6>[ 23.028377] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11372 06:51:17.716081 <6>[ 23.028615] CPU5 is up
11373 06:51:17.719308 <6>[ 23.028744] Detected PIPT I-cache on CPU6
11374 06:51:17.725915 <6>[ 23.028767] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11375 06:51:17.732539 <6>[ 23.028782] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11376 06:51:17.736064 <6>[ 23.029034] CPU6 is up
11377 06:51:17.739477 <6>[ 23.029162] Detected PIPT I-cache on CPU7
11378 06:51:17.749472 <6>[ 23.029191] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11379 06:51:17.755966 <6>[ 23.029206] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11380 06:51:17.756089 <6>[ 23.029466] CPU7 is up
11381 06:51:17.762514 <6>[ 23.578228] OOM killer enabled.
11382 06:51:17.765893 <6>[ 23.581618] Restarting tasks ... done.
11383 06:51:17.769042 <5>[ 23.586006] random: crng reseeded on system resumption
11384 06:51:17.773207 <6>[ 23.592240] PM: suspend exit
11385 06:51:17.783850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>
11386 06:51:17.784173 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=pass
11388 06:51:17.786943 rtcwake: assuming RTC uses UTC ...
11389 06:51:17.793707 rtcwake: wakeup from "mem" using rtc0 at Sat Feb 3 06:50:49 2024
11390 06:51:17.806190 <6>[ 23.621565] PM: suspend entry (deep)
11391 06:51:17.809361 <6>[ 23.625431] Filesystems sync: 0.000 seconds
11392 06:51:17.812638 <6>[ 23.630178] Freezing user space processes
11393 06:51:17.823613 <6>[ 23.635881] Freezing user space processes completed (elapsed 0.001 seconds)
11394 06:51:17.826618 <6>[ 23.643105] OOM killer disabled.
11395 06:51:17.829901 <6>[ 23.646586] Freezing remaining freezable tasks
11396 06:51:17.840317 <6>[ 23.652483] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11397 06:51:17.846805 <6>[ 23.660152] printk: Suspending console(s) (use no_console_suspend to debug)
11398 06:51:23.573035 <6>[ 23.734260] Disabling non-boot CPUs ...
11399 06:51:23.576634 <6>[ 23.736318] psci: CPU1 killed (polled 0 ms)
11400 06:51:23.579933 <6>[ 23.738040] psci: CPU2 killed (polled 4 ms)
11401 06:51:23.586634 <6>[ 23.740555] psci: CPU3 killed (polled 0 ms)
11402 06:51:23.589934 <6>[ 23.741163] psci: CPU4 killed (polled 0 ms)
11403 06:51:23.593337 <6>[ 23.741814] psci: CPU5 killed (polled 0 ms)
11404 06:51:23.600466 <6>[ 23.742611] psci: CPU6 killed (polled 0 ms)
11405 06:51:23.603343 <6>[ 23.743187] psci: CPU7 killed (polled 0 ms)
11406 06:51:23.606754 <6>[ 23.743581] Enabling non-boot CPUs ...
11407 06:51:23.613377 <6>[ 23.743825] Detected VIPT I-cache on CPU1
11408 06:51:23.619946 <6>[ 23.743918] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11409 06:51:23.626559 <6>[ 23.743984] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11410 06:51:23.629809 <6>[ 23.744704] CPU1 is up
11411 06:51:23.633372 <6>[ 23.744857] Detected VIPT I-cache on CPU2
11412 06:51:23.639947 <6>[ 23.744920] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11413 06:51:23.646966 <6>[ 23.744963] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11414 06:51:23.650414 <6>[ 23.745555] CPU2 is up
11415 06:51:23.653356 <6>[ 23.745706] Detected VIPT I-cache on CPU3
11416 06:51:23.659962 <6>[ 23.745770] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11417 06:51:23.666932 <6>[ 23.745811] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11418 06:51:23.669960 <6>[ 23.746426] CPU3 is up
11419 06:51:23.673427 <6>[ 23.746560] Detected PIPT I-cache on CPU4
11420 06:51:23.683553 <6>[ 23.746582] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11421 06:51:23.689982 <6>[ 23.746596] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11422 06:51:23.690093 <6>[ 23.746895] CPU4 is up
11423 06:51:23.696574 <6>[ 23.747035] Detected PIPT I-cache on CPU5
11424 06:51:23.703264 <6>[ 23.747057] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11425 06:51:23.710159 <6>[ 23.747071] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11426 06:51:23.713070 <6>[ 23.747311] CPU5 is up
11427 06:51:23.716534 <6>[ 23.747442] Detected PIPT I-cache on CPU6
11428 06:51:23.723030 <6>[ 23.747464] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11429 06:51:23.729766 <6>[ 23.747478] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11430 06:51:23.733203 <6>[ 23.747718] CPU6 is up
11431 06:51:23.736727 <6>[ 23.747846] Detected PIPT I-cache on CPU7
11432 06:51:23.743673 <6>[ 23.747875] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11433 06:51:23.752866 <6>[ 23.747888] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11434 06:51:23.752989 <6>[ 23.748143] CPU7 is up
11435 06:51:23.756410 <6>[ 24.294456] OOM killer enabled.
11436 06:51:23.763411 <6>[ 24.297846] Restarting tasks ... done.
11437 06:51:23.766372 <5>[ 24.302225] random: crng reseeded on system resumption
11438 06:51:23.770240 <6>[ 24.309026] PM: suspend exit
11439 06:51:23.781164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>
11440 06:51:23.781482 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=pass
11442 06:51:23.784311 rtcwake: assuming RTC uses UTC ...
11443 06:51:23.790977 rtcwake: wakeup from "mem" using rtc0 at Sat Feb 3 06:50:55 2024
11444 06:51:23.803961 <6>[ 24.338928] PM: suspend entry (deep)
11445 06:51:23.807524 <6>[ 24.342790] Filesystems sync: 0.000 seconds
11446 06:51:23.810314 <6>[ 24.347525] Freezing user space processes
11447 06:51:23.821231 <6>[ 24.353172] Freezing user space processes completed (elapsed 0.001 seconds)
11448 06:51:23.824802 <6>[ 24.360403] OOM killer disabled.
11449 06:51:23.827874 <6>[ 24.363913] Freezing remaining freezable tasks
11450 06:51:23.838243 <6>[ 24.369863] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11451 06:51:23.844372 <6>[ 24.377538] printk: Suspending console(s) (use no_console_suspend to debug)
11452 06:51:29.569451 <6>[ 24.458174] Disabling non-boot CPUs ...
11453 06:51:29.572921 <6>[ 24.459283] psci: CPU1 killed (polled 0 ms)
11454 06:51:29.576343 <6>[ 24.461439] psci: CPU2 killed (polled 0 ms)
11455 06:51:29.582951 <6>[ 24.463472] psci: CPU3 killed (polled 0 ms)
11456 06:51:29.586155 <6>[ 24.464151] psci: CPU4 killed (polled 0 ms)
11457 06:51:29.589436 <6>[ 24.464841] psci: CPU5 killed (polled 0 ms)
11458 06:51:29.596186 <6>[ 24.465451] psci: CPU6 killed (polled 0 ms)
11459 06:51:29.599346 <6>[ 24.466099] psci: CPU7 killed (polled 0 ms)
11460 06:51:29.602724 <6>[ 24.466498] Enabling non-boot CPUs ...
11461 06:51:29.609671 <6>[ 24.466745] Detected VIPT I-cache on CPU1
11462 06:51:29.616018 <6>[ 24.466840] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11463 06:51:29.622721 <6>[ 24.466904] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11464 06:51:29.626205 <6>[ 24.467632] CPU1 is up
11465 06:51:29.629093 <6>[ 24.467788] Detected VIPT I-cache on CPU2
11466 06:51:29.635965 <6>[ 24.467852] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11467 06:51:29.642453 <6>[ 24.467894] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11468 06:51:29.645947 <6>[ 24.468481] CPU2 is up
11469 06:51:29.649359 <6>[ 24.468631] Detected VIPT I-cache on CPU3
11470 06:51:29.655783 <6>[ 24.468694] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11471 06:51:29.662606 <6>[ 24.468737] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11472 06:51:29.665751 <6>[ 24.469330] CPU3 is up
11473 06:51:29.672378 <6>[ 24.469463] Detected PIPT I-cache on CPU4
11474 06:51:29.678995 <6>[ 24.469485] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11475 06:51:29.685553 <6>[ 24.469500] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11476 06:51:29.689403 <6>[ 24.469793] CPU4 is up
11477 06:51:29.692686 <6>[ 24.469921] Detected PIPT I-cache on CPU5
11478 06:51:29.698790 <6>[ 24.469944] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11479 06:51:29.705863 <6>[ 24.469958] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11480 06:51:29.709257 <6>[ 24.470213] CPU5 is up
11481 06:51:29.712529 <6>[ 24.470356] Detected PIPT I-cache on CPU6
11482 06:51:29.719338 <6>[ 24.470379] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11483 06:51:29.725818 <6>[ 24.470393] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11484 06:51:29.728782 <6>[ 24.470647] CPU6 is up
11485 06:51:29.732021 <6>[ 24.470777] Detected PIPT I-cache on CPU7
11486 06:51:29.742156 <6>[ 24.470806] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11487 06:51:29.748813 <6>[ 24.470821] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11488 06:51:29.748899 <6>[ 24.471101] CPU7 is up
11489 06:51:29.752419 <6>[ 25.014380] OOM killer enabled.
11490 06:51:29.759394 <6>[ 25.017770] Restarting tasks ... done.
11491 06:51:29.762448 <5>[ 25.022167] random: crng reseeded on system resumption
11492 06:51:29.765813 <6>[ 25.028440] PM: suspend exit
11493 06:51:29.775896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>
11494 06:51:29.776166 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11496 06:51:29.779425 rtcwake: assuming RTC uses UTC ...
11497 06:51:29.786342 rtcwake: wakeup from "mem" using rtc0 at Sat Feb 3 06:51:01 2024
11498 06:51:29.798233 <6>[ 25.057357] PM: suspend entry (deep)
11499 06:51:29.801613 <6>[ 25.061225] Filesystems sync: 0.000 seconds
11500 06:51:29.804849 <6>[ 25.065982] Freezing user space processes
11501 06:51:29.815996 <6>[ 25.071648] Freezing user space processes completed (elapsed 0.001 seconds)
11502 06:51:29.819341 <6>[ 25.078879] OOM killer disabled.
11503 06:51:29.822752 <6>[ 25.082366] Freezing remaining freezable tasks
11504 06:51:29.832939 <6>[ 25.088286] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11505 06:51:29.839724 <6>[ 25.095952] printk: Suspending console(s) (use no_console_suspend to debug)
11506 06:51:35.566528 <6>[ 25.169019] Disabling non-boot CPUs ...
11507 06:51:35.569572 <6>[ 25.170892] psci: CPU1 killed (polled 4 ms)
11508 06:51:35.573041 <6>[ 25.172858] psci: CPU2 killed (polled 0 ms)
11509 06:51:35.579496 <6>[ 25.173936] psci: CPU3 killed (polled 4 ms)
11510 06:51:35.582854 <6>[ 25.174437] psci: CPU4 killed (polled 0 ms)
11511 06:51:35.586220 <6>[ 25.175026] psci: CPU5 killed (polled 0 ms)
11512 06:51:35.592699 <6>[ 25.175660] psci: CPU6 killed (polled 0 ms)
11513 06:51:35.596533 <6>[ 25.176188] psci: CPU7 killed (polled 0 ms)
11514 06:51:35.599365 <6>[ 25.176499] Enabling non-boot CPUs ...
11515 06:51:35.605980 <6>[ 25.176717] Detected VIPT I-cache on CPU1
11516 06:51:35.612607 <6>[ 25.176796] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11517 06:51:35.619282 <6>[ 25.176852] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11518 06:51:35.623067 <6>[ 25.177446] CPU1 is up
11519 06:51:35.626349 <6>[ 25.177575] Detected VIPT I-cache on CPU2
11520 06:51:35.633163 <6>[ 25.177625] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11521 06:51:35.639431 <6>[ 25.177659] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11522 06:51:35.642902 <6>[ 25.178181] CPU2 is up
11523 06:51:35.646269 <6>[ 25.178306] Detected VIPT I-cache on CPU3
11524 06:51:35.652913 <6>[ 25.178355] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11525 06:51:35.659585 <6>[ 25.178389] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11526 06:51:35.662914 <6>[ 25.178858] CPU3 is up
11527 06:51:35.665997 <6>[ 25.178977] Detected PIPT I-cache on CPU4
11528 06:51:35.676389 <6>[ 25.178998] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11529 06:51:35.682838 <6>[ 25.179012] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11530 06:51:35.686140 <6>[ 25.179292] CPU4 is up
11531 06:51:35.689249 <6>[ 25.179418] Detected PIPT I-cache on CPU5
11532 06:51:35.695750 <6>[ 25.179440] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11533 06:51:35.702701 <6>[ 25.179454] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11534 06:51:35.705838 <6>[ 25.179684] CPU5 is up
11535 06:51:35.709166 <6>[ 25.179799] Detected PIPT I-cache on CPU6
11536 06:51:35.715803 <6>[ 25.179821] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11537 06:51:35.722516 <6>[ 25.179835] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11538 06:51:35.725670 <6>[ 25.180078] CPU6 is up
11539 06:51:35.728957 <6>[ 25.180191] Detected PIPT I-cache on CPU7
11540 06:51:35.739210 <6>[ 25.180219] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11541 06:51:35.746059 <6>[ 25.180233] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11542 06:51:35.746163 <6>[ 25.180481] CPU7 is up
11543 06:51:35.748945 <6>[ 25.722098] OOM killer enabled.
11544 06:51:35.755705 <6>[ 25.725488] Restarting tasks ... done.
11545 06:51:35.759053 <5>[ 25.729854] random: crng reseeded on system resumption
11546 06:51:35.764057 <6>[ 25.737072] PM: suspend exit
11547 06:51:35.774248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>
11548 06:51:35.774524 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11550 06:51:35.777883 rtcwake: assuming RTC uses UTC ...
11551 06:51:35.784329 rtcwake: wakeup from "mem" using rtc0 at Sat Feb 3 06:51:07 2024
11552 06:51:35.797062 <6>[ 25.766945] PM: suspend entry (deep)
11553 06:51:35.800495 <6>[ 25.770837] Filesystems sync: 0.000 seconds
11554 06:51:35.803596 <6>[ 25.775839] Freezing user space processes
11555 06:51:35.815326 <6>[ 25.781908] Freezing user space processes completed (elapsed 0.001 seconds)
11556 06:51:35.818856 <6>[ 25.789133] OOM killer disabled.
11557 06:51:35.822152 <6>[ 25.792615] Freezing remaining freezable tasks
11558 06:51:35.832162 <6>[ 25.798665] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11559 06:51:35.838758 <6>[ 25.806335] printk: Suspending console(s) (use no_console_suspend to debug)
11560 06:51:41.563630 <6>[ 25.882412] Disabling non-boot CPUs ...
11561 06:51:41.567076 <6>[ 25.883128] psci: CPU1 killed (polled 0 ms)
11562 06:51:41.569985 <6>[ 25.883816] psci: CPU2 killed (polled 0 ms)
11563 06:51:41.576522 <6>[ 25.884541] psci: CPU3 killed (polled 0 ms)
11564 06:51:41.579907 <6>[ 25.885883] psci: CPU4 killed (polled 4 ms)
11565 06:51:41.583321 <6>[ 25.887491] psci: CPU5 killed (polled 0 ms)
11566 06:51:41.590045 <6>[ 25.889014] psci: CPU6 killed (polled 0 ms)
11567 06:51:41.593243 <6>[ 25.889892] psci: CPU7 killed (polled 4 ms)
11568 06:51:41.596612 <6>[ 25.890140] Enabling non-boot CPUs ...
11569 06:51:41.603226 <6>[ 25.890321] Detected VIPT I-cache on CPU1
11570 06:51:41.609648 <6>[ 25.890384] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11571 06:51:41.616481 <6>[ 25.890429] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11572 06:51:41.620073 <6>[ 25.890875] CPU1 is up
11573 06:51:41.623348 <6>[ 25.890970] Detected VIPT I-cache on CPU2
11574 06:51:41.629761 <6>[ 25.891003] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11575 06:51:41.636561 <6>[ 25.891026] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11576 06:51:41.639668 <6>[ 25.891331] CPU2 is up
11577 06:51:41.643262 <6>[ 25.891423] Detected VIPT I-cache on CPU3
11578 06:51:41.649804 <6>[ 25.891455] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11579 06:51:41.656260 <6>[ 25.891478] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11580 06:51:41.659373 <6>[ 25.891790] CPU3 is up
11581 06:51:41.666171 <6>[ 25.891903] Detected PIPT I-cache on CPU4
11582 06:51:41.673102 <6>[ 25.891933] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11583 06:51:41.679845 <6>[ 25.891953] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11584 06:51:41.679931 <6>[ 25.892296] CPU4 is up
11585 06:51:41.686385 <6>[ 25.892414] Detected PIPT I-cache on CPU5
11586 06:51:41.693133 <6>[ 25.892446] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11587 06:51:41.699756 <6>[ 25.892466] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11588 06:51:41.703220 <6>[ 25.892754] CPU5 is up
11589 06:51:41.706498 <6>[ 25.892882] Detected PIPT I-cache on CPU6
11590 06:51:41.712998 <6>[ 25.892913] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11591 06:51:41.719544 <6>[ 25.892933] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11592 06:51:41.723077 <6>[ 25.893248] CPU6 is up
11593 06:51:41.726298 <6>[ 25.893359] Detected PIPT I-cache on CPU7
11594 06:51:41.736324 <6>[ 25.893397] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11595 06:51:41.742956 <6>[ 25.893416] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11596 06:51:41.743082 <6>[ 25.893730] CPU7 is up
11597 06:51:41.745994 <6>[ 26.433616] OOM killer enabled.
11598 06:51:41.752959 <6>[ 26.437007] Restarting tasks ... done.
11599 06:51:41.756178 <5>[ 26.441412] random: crng reseeded on system resumption
11600 06:51:41.759919 <6>[ 26.447693] PM: suspend exit
11601 06:51:41.771135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>
11602 06:51:41.771453 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11604 06:51:41.774181 rtcwake: assuming RTC uses UTC ...
11605 06:51:41.781040 rtcwake: wakeup from "mem" using rtc0 at Sat Feb 3 06:51:13 2024
11606 06:51:41.793898 <6>[ 26.478079] PM: suspend entry (deep)
11607 06:51:41.796787 <6>[ 26.481943] Filesystems sync: 0.000 seconds
11608 06:51:41.800065 <6>[ 26.486684] Freezing user space processes
11609 06:51:41.811174 <6>[ 26.492346] Freezing user space processes completed (elapsed 0.001 seconds)
11610 06:51:41.814421 <6>[ 26.499597] OOM killer disabled.
11611 06:51:41.817842 <6>[ 26.503078] Freezing remaining freezable tasks
11612 06:51:41.828624 <6>[ 26.508989] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11613 06:51:41.835087 <6>[ 26.516653] printk: Suspending console(s) (use no_console_suspend to debug)
11614 06:51:47.568651 <6>[ 26.589708] Disabling non-boot CPUs ...
11615 06:51:47.571812 <6>[ 26.590835] psci: CPU1 killed (polled 0 ms)
11616 06:51:47.575488 <6>[ 26.591987] psci: CPU2 killed (polled 0 ms)
11617 06:51:47.582159 <6>[ 26.594166] psci: CPU3 killed (polled 4 ms)
11618 06:51:47.585633 <6>[ 26.594685] psci: CPU4 killed (polled 0 ms)
11619 06:51:47.588890 <6>[ 26.595339] psci: CPU5 killed (polled 0 ms)
11620 06:51:47.595260 <6>[ 26.595939] psci: CPU6 killed (polled 0 ms)
11621 06:51:47.598557 <6>[ 26.596524] psci: CPU7 killed (polled 0 ms)
11622 06:51:47.601875 <6>[ 26.596844] Enabling non-boot CPUs ...
11623 06:51:47.608753 <6>[ 26.597090] Detected VIPT I-cache on CPU1
11624 06:51:47.615457 <6>[ 26.597182] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11625 06:51:47.621875 <6>[ 26.597248] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11626 06:51:47.625255 <6>[ 26.598003] CPU1 is up
11627 06:51:47.628705 <6>[ 26.598162] Detected VIPT I-cache on CPU2
11628 06:51:47.635712 <6>[ 26.598226] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11629 06:51:47.642150 <6>[ 26.598268] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11630 06:51:47.645509 <6>[ 26.598855] CPU2 is up
11631 06:51:47.648869 <6>[ 26.599004] Detected VIPT I-cache on CPU3
11632 06:51:47.655215 <6>[ 26.599067] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11633 06:51:47.661901 <6>[ 26.599109] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11634 06:51:47.665278 <6>[ 26.599705] CPU3 is up
11635 06:51:47.668339 <6>[ 26.599836] Detected PIPT I-cache on CPU4
11636 06:51:47.678886 <6>[ 26.599857] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11637 06:51:47.685362 <6>[ 26.599871] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11638 06:51:47.685794 <6>[ 26.600155] CPU4 is up
11639 06:51:47.691797 <6>[ 26.600296] Detected PIPT I-cache on CPU5
11640 06:51:47.698704 <6>[ 26.600318] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11641 06:51:47.705249 <6>[ 26.600331] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11642 06:51:47.708763 <6>[ 26.600568] CPU5 is up
11643 06:51:47.711783 <6>[ 26.600696] Detected PIPT I-cache on CPU6
11644 06:51:47.718757 <6>[ 26.600716] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11645 06:51:47.725173 <6>[ 26.600730] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11646 06:51:47.728510 <6>[ 26.600969] CPU6 is up
11647 06:51:47.731896 <6>[ 26.601096] Detected PIPT I-cache on CPU7
11648 06:51:47.738841 <6>[ 26.601124] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11649 06:51:47.745237 <6>[ 26.601137] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11650 06:51:47.748471 <6>[ 26.601392] CPU7 is up
11651 06:51:47.751904 <6>[ 27.146208] OOM killer enabled.
11652 06:51:47.758494 <6>[ 27.149598] Restarting tasks ... done.
11653 06:51:47.762037 <5>[ 27.153960] random: crng reseeded on system resumption
11654 06:51:47.765599 <6>[ 27.160362] PM: suspend exit
11655 06:51:47.776135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>
11656 06:51:47.776871 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=pass
11658 06:51:47.779507 rtcwake: assuming RTC uses UTC ...
11659 06:51:47.786019 rtcwake: wakeup from "mem" using rtc0 at Sat Feb 3 06:51:19 2024
11660 06:51:47.798457 <6>[ 27.190180] PM: suspend entry (deep)
11661 06:51:47.801929 <6>[ 27.194042] Filesystems sync: 0.000 seconds
11662 06:51:47.805242 <6>[ 27.198800] Freezing user space processes
11663 06:51:47.816279 <6>[ 27.204488] Freezing user space processes completed (elapsed 0.001 seconds)
11664 06:51:47.819559 <6>[ 27.211720] OOM killer disabled.
11665 06:51:47.822734 <6>[ 27.215205] Freezing remaining freezable tasks
11666 06:51:47.832887 <6>[ 27.221121] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11667 06:51:47.839688 <6>[ 27.228787] printk: Suspending console(s) (use no_console_suspend to debug)
11668 06:51:53.558124 <6>[ 27.301235] Disabling non-boot CPUs ...
11669 06:51:53.561456 <4>[ 27.302080] migrate_one_irq: 88 callbacks suppressed
11670 06:51:53.568047 <4>[ 27.302091] IRQ283: set affinity failed(-22).
11671 06:51:53.571106 <4>[ 27.302100] IRQ284: set affinity failed(-22).
11672 06:51:53.574543 <6>[ 27.303174] psci: CPU1 killed (polled 0 ms)
11673 06:51:53.581081 <4>[ 27.304061] IRQ283: set affinity failed(-22).
11674 06:51:53.584613 <4>[ 27.304072] IRQ284: set affinity failed(-22).
11675 06:51:53.591156 <6>[ 27.305141] psci: CPU2 killed (polled 0 ms)
11676 06:51:53.594492 <4>[ 27.306121] IRQ283: set affinity failed(-22).
11677 06:51:53.597840 <4>[ 27.306131] IRQ284: set affinity failed(-22).
11678 06:51:53.604584 <6>[ 27.307185] psci: CPU3 killed (polled 0 ms)
11679 06:51:53.607940 <4>[ 27.307737] IRQ283: set affinity failed(-22).
11680 06:51:53.611618 <4>[ 27.307741] IRQ284: set affinity failed(-22).
11681 06:51:53.618092 <6>[ 27.307770] psci: CPU4 killed (polled 0 ms)
11682 06:51:53.621491 <4>[ 27.308308] IRQ283: set affinity failed(-22).
11683 06:51:53.624554 <4>[ 27.308313] IRQ284: set affinity failed(-22).
11684 06:51:53.631297 <6>[ 27.308344] psci: CPU5 killed (polled 0 ms)
11685 06:51:53.634760 <6>[ 27.308858] psci: CPU6 killed (polled 0 ms)
11686 06:51:53.638153 <6>[ 27.309353] psci: CPU7 killed (polled 0 ms)
11687 06:51:53.644534 <6>[ 27.309657] Enabling non-boot CPUs ...
11688 06:51:53.647818 <6>[ 27.309912] Detected VIPT I-cache on CPU1
11689 06:51:53.654613 <6>[ 27.309991] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11690 06:51:53.661182 <6>[ 27.310046] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11691 06:51:53.664582 <6>[ 27.310645] CPU1 is up
11692 06:51:53.667565 <6>[ 27.310774] Detected VIPT I-cache on CPU2
11693 06:51:53.677790 <6>[ 27.310825] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11694 06:51:53.684459 <6>[ 27.310858] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11695 06:51:53.684537 <6>[ 27.311313] CPU2 is up
11696 06:51:53.690986 <6>[ 27.311438] Detected VIPT I-cache on CPU3
11697 06:51:53.697810 <6>[ 27.311488] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11698 06:51:53.704338 <6>[ 27.311521] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11699 06:51:53.707940 <6>[ 27.311986] CPU3 is up
11700 06:51:53.711496 <6>[ 27.312102] Detected PIPT I-cache on CPU4
11701 06:51:53.717786 <6>[ 27.312123] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11702 06:51:53.724184 <6>[ 27.312137] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11703 06:51:53.727871 <6>[ 27.312402] CPU4 is up
11704 06:51:53.730782 <6>[ 27.312524] Detected PIPT I-cache on CPU5
11705 06:51:53.737614 <6>[ 27.312547] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11706 06:51:53.744387 <6>[ 27.312561] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11707 06:51:53.747236 <6>[ 27.312785] CPU5 is up
11708 06:51:53.754216 <6>[ 27.312900] Detected PIPT I-cache on CPU6
11709 06:51:53.760772 <6>[ 27.312921] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11710 06:51:53.767781 <6>[ 27.312935] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11711 06:51:53.770881 <6>[ 27.313175] CPU6 is up
11712 06:51:53.774473 <6>[ 27.313289] Detected PIPT I-cache on CPU7
11713 06:51:53.781057 <6>[ 27.313318] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11714 06:51:53.787770 <6>[ 27.313332] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11715 06:51:53.790958 <6>[ 27.313586] CPU7 is up
11716 06:51:53.794370 <6>[ 27.901025] OOM killer enabled.
11717 06:51:53.797268 <6>[ 27.904416] Restarting tasks ... done.
11718 06:51:53.803953 <5>[ 27.908798] random: crng reseeded on system resumption
11719 06:51:53.807349 <6>[ 27.915190] PM: suspend exit
11720 06:51:53.817050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>
11721 06:51:53.817315 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=pass
11723 06:51:53.819909 rtcwake: assuming RTC uses UTC ...
11724 06:51:53.826861 rtcwake: wakeup from "mem" using rtc0 at Sat Feb 3 06:51:25 2024
11725 06:51:53.839469 <6>[ 27.945189] PM: suspend entry (deep)
11726 06:51:53.842971 <6>[ 27.949063] Filesystems sync: 0.000 seconds
11727 06:51:53.845839 <6>[ 27.953834] Freezing user space processes
11728 06:51:53.857148 <6>[ 27.959524] Freezing user space processes completed (elapsed 0.001 seconds)
11729 06:51:53.860333 <6>[ 27.966753] OOM killer disabled.
11730 06:51:53.863756 <6>[ 27.970233] Freezing remaining freezable tasks
11731 06:51:53.873968 <6>[ 27.976154] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11732 06:51:53.880285 <6>[ 27.983822] printk: Suspending console(s) (use no_console_suspend to debug)
11733 06:51:59.584433 <6>[ 28.058721] Disabling non-boot CPUs ...
11734 06:51:59.587724 <6>[ 28.059811] psci: CPU1 killed (polled 0 ms)
11735 06:51:59.590978 <6>[ 28.061955] psci: CPU2 killed (polled 4 ms)
11736 06:51:59.597358 <6>[ 28.064047] psci: CPU3 killed (polled 0 ms)
11737 06:51:59.600885 <6>[ 28.064734] psci: CPU4 killed (polled 0 ms)
11738 06:51:59.604455 <6>[ 28.065362] psci: CPU5 killed (polled 0 ms)
11739 06:51:59.610752 <6>[ 28.065931] psci: CPU6 killed (polled 0 ms)
11740 06:51:59.614302 <6>[ 28.066530] psci: CPU7 killed (polled 0 ms)
11741 06:51:59.617498 <6>[ 28.066903] Enabling non-boot CPUs ...
11742 06:51:59.624286 <6>[ 28.067152] Detected VIPT I-cache on CPU1
11743 06:51:59.631049 <6>[ 28.067245] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11744 06:51:59.637614 <6>[ 28.067311] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11745 06:51:59.641258 <6>[ 28.068052] CPU1 is up
11746 06:51:59.644216 <6>[ 28.068205] Detected VIPT I-cache on CPU2
11747 06:51:59.650869 <6>[ 28.068268] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11748 06:51:59.657716 <6>[ 28.068311] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11749 06:51:59.660774 <6>[ 28.068899] CPU2 is up
11750 06:51:59.664436 <6>[ 28.069049] Detected VIPT I-cache on CPU3
11751 06:51:59.670902 <6>[ 28.069113] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11752 06:51:59.677497 <6>[ 28.069155] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11753 06:51:59.681252 <6>[ 28.069788] CPU3 is up
11754 06:51:59.684338 <6>[ 28.069924] Detected PIPT I-cache on CPU4
11755 06:51:59.694325 <6>[ 28.069946] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11756 06:51:59.700802 <6>[ 28.069961] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11757 06:51:59.700889 <6>[ 28.070265] CPU4 is up
11758 06:51:59.707592 <6>[ 28.070410] Detected PIPT I-cache on CPU5
11759 06:51:59.714313 <6>[ 28.070433] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11760 06:51:59.720859 <6>[ 28.070447] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11761 06:51:59.724161 <6>[ 28.070690] CPU5 is up
11762 06:51:59.727535 <6>[ 28.070843] Detected PIPT I-cache on CPU6
11763 06:51:59.734352 <6>[ 28.070866] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11764 06:51:59.740958 <6>[ 28.070881] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11765 06:51:59.744378 <6>[ 28.071137] CPU6 is up
11766 06:51:59.747659 <6>[ 28.071266] Detected PIPT I-cache on CPU7
11767 06:51:59.754079 <6>[ 28.071295] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11768 06:51:59.764029 <6>[ 28.071309] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11769 06:51:59.764115 <6>[ 28.071574] CPU7 is up
11770 06:51:59.767315 <6>[ 28.634068] OOM killer enabled.
11771 06:51:59.773813 <6>[ 28.637458] Restarting tasks ... done.
11772 06:51:59.777189 <5>[ 28.641867] random: crng reseeded on system resumption
11773 06:51:59.780922 <6>[ 28.648147] PM: suspend exit
11774 06:51:59.791604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>
11775 06:51:59.791871 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=pass
11777 06:51:59.794861 rtcwake: assuming RTC uses UTC ...
11778 06:51:59.801436 rtcwake: wakeup from "mem" using rtc0 at Sat Feb 3 06:51:31 2024
11779 06:51:59.813928 <6>[ 28.677941] PM: suspend entry (deep)
11780 06:51:59.817342 <6>[ 28.681802] Filesystems sync: 0.000 seconds
11781 06:51:59.820659 <6>[ 28.686568] Freezing user space processes
11782 06:51:59.831641 <6>[ 28.692249] Freezing user space processes completed (elapsed 0.001 seconds)
11783 06:51:59.835043 <6>[ 28.699478] OOM killer disabled.
11784 06:51:59.838610 <6>[ 28.702960] Freezing remaining freezable tasks
11785 06:51:59.848354 <6>[ 28.708886] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11786 06:51:59.854659 <6>[ 28.716552] printk: Suspending console(s) (use no_console_suspend to debug)
11787 06:52:05.562862 <6>[ 28.788116] Disabling non-boot CPUs ...
11788 06:52:05.566363 <6>[ 28.788920] psci: CPU1 killed (polled 0 ms)
11789 06:52:05.569264 <6>[ 28.790908] psci: CPU2 killed (polled 0 ms)
11790 06:52:05.576179 <6>[ 28.792703] psci: CPU3 killed (polled 0 ms)
11791 06:52:05.579511 <6>[ 28.793211] psci: CPU4 killed (polled 0 ms)
11792 06:52:05.582742 <6>[ 28.793817] psci: CPU5 killed (polled 0 ms)
11793 06:52:05.589633 <6>[ 28.794347] psci: CPU6 killed (polled 0 ms)
11794 06:52:05.592507 <6>[ 28.794913] psci: CPU7 killed (polled 0 ms)
11795 06:52:05.595900 <6>[ 28.795217] Enabling non-boot CPUs ...
11796 06:52:05.602721 <6>[ 28.795429] Detected VIPT I-cache on CPU1
11797 06:52:05.609090 <6>[ 28.795504] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11798 06:52:05.615785 <6>[ 28.795557] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11799 06:52:05.619252 <6>[ 28.796117] CPU1 is up
11800 06:52:05.622368 <6>[ 28.796239] Detected VIPT I-cache on CPU2
11801 06:52:05.628954 <6>[ 28.796285] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11802 06:52:05.635716 <6>[ 28.796316] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11803 06:52:05.639375 <6>[ 28.796741] CPU2 is up
11804 06:52:05.642712 <6>[ 28.796856] Detected VIPT I-cache on CPU3
11805 06:52:05.649204 <6>[ 28.796902] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11806 06:52:05.656217 <6>[ 28.796932] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11807 06:52:05.659356 <6>[ 28.797355] CPU3 is up
11808 06:52:05.662658 <6>[ 28.797467] Detected PIPT I-cache on CPU4
11809 06:52:05.672927 <6>[ 28.797489] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11810 06:52:05.679223 <6>[ 28.797503] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11811 06:52:05.679309 <6>[ 28.797778] CPU4 is up
11812 06:52:05.685839 <6>[ 28.797897] Detected PIPT I-cache on CPU5
11813 06:52:05.692694 <6>[ 28.797919] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11814 06:52:05.699141 <6>[ 28.797933] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11815 06:52:05.702615 <6>[ 28.798164] CPU5 is up
11816 06:52:05.706227 <6>[ 28.798274] Detected PIPT I-cache on CPU6
11817 06:52:05.712504 <6>[ 28.798295] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11818 06:52:05.719383 <6>[ 28.798309] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11819 06:52:05.722691 <6>[ 28.798542] CPU6 is up
11820 06:52:05.726071 <6>[ 28.798652] Detected PIPT I-cache on CPU7
11821 06:52:05.735796 <6>[ 28.798679] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11822 06:52:05.742436 <6>[ 28.798693] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11823 06:52:05.742522 <6>[ 28.798939] CPU7 is up
11824 06:52:05.745696 <6>[ 29.341825] OOM killer enabled.
11825 06:52:05.752761 <6>[ 29.345215] Restarting tasks ... done.
11826 06:52:05.755515 <5>[ 29.349617] random: crng reseeded on system resumption
11827 06:52:05.759837 <6>[ 29.356210] PM: suspend exit
11828 06:52:05.770147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>
11829 06:52:05.770232 + set +x
11830 06:52:05.770501 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11832 06:52:05.776782 <LAVA_SIGNAL_ENDRUN 0_sleep 12694799_1.5.2.3.1>
11833 06:52:05.776868 <LAVA_TEST_RUNNER EXIT>
11834 06:52:05.777124 Received signal: <ENDRUN> 0_sleep 12694799_1.5.2.3.1
11835 06:52:05.777216 Ending use of test pattern.
11836 06:52:05.777289 Ending test lava.0_sleep (12694799_1.5.2.3.1), duration 60.35
11838 06:52:05.777555 ok: lava_test_shell seems to have completed
11839 06:52:05.777736 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-1: pass
rtcwake-mem-10: pass
rtcwake-mem-2: pass
rtcwake-mem-3: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-7: pass
rtcwake-mem-8: pass
rtcwake-mem-9: pass
11840 06:52:05.777841 end: 3.1 lava-test-shell (duration 00:01:01) [common]
11841 06:52:05.777970 end: 3 lava-test-retry (duration 00:01:01) [common]
11842 06:52:05.778074 start: 4 finalize (timeout 00:06:13) [common]
11843 06:52:05.778179 start: 4.1 power-off (timeout 00:00:30) [common]
11844 06:52:05.778369 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11845 06:52:05.852887 >> Command sent successfully.
11846 06:52:05.855632 Returned 0 in 0 seconds
11847 06:52:05.956091 end: 4.1 power-off (duration 00:00:00) [common]
11849 06:52:05.956457 start: 4.2 read-feedback (timeout 00:06:13) [common]
11850 06:52:05.956713 Listened to connection for namespace 'common' for up to 1s
11851 06:52:06.957673 Finalising connection for namespace 'common'
11852 06:52:06.957843 Disconnecting from shell: Finalise
11853 06:52:06.957926 / #
11854 06:52:07.058286 end: 4.2 read-feedback (duration 00:00:01) [common]
11855 06:52:07.058440 end: 4 finalize (duration 00:00:01) [common]
11856 06:52:07.058555 Cleaning after the job
11857 06:52:07.058655 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/ramdisk
11858 06:52:07.069149 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/kernel
11859 06:52:07.087750 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/dtb
11860 06:52:07.087964 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694799/tftp-deploy-zve8fp0e/modules
11861 06:52:07.093695 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694799
11862 06:52:07.240474 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694799
11863 06:52:07.240653 Job finished correctly