Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 16
- Kernel Errors: 35
1 06:52:44.300303 lava-dispatcher, installed at version: 2023.10
2 06:52:44.300505 start: 0 validate
3 06:52:44.300635 Start time: 2024-02-03 06:52:44.300627+00:00 (UTC)
4 06:52:44.300759 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:52:44.300888 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 06:52:44.560895 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:52:44.561065 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:52:44.827278 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:52:44.828087 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:52:45.090444 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:52:45.091122 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 06:52:45.366240 validate duration: 1.07
14 06:52:45.367584 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:52:45.368130 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:52:45.368640 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:52:45.369240 Not decompressing ramdisk as can be used compressed.
18 06:52:45.369705 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 06:52:45.370106 saving as /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/ramdisk/rootfs.cpio.gz
20 06:52:45.370475 total size: 26246609 (25 MB)
21 06:52:45.375659 progress 0 % (0 MB)
22 06:52:45.402433 progress 5 % (1 MB)
23 06:52:45.414513 progress 10 % (2 MB)
24 06:52:45.423482 progress 15 % (3 MB)
25 06:52:45.431022 progress 20 % (5 MB)
26 06:52:45.437701 progress 25 % (6 MB)
27 06:52:45.444521 progress 30 % (7 MB)
28 06:52:45.451456 progress 35 % (8 MB)
29 06:52:45.458131 progress 40 % (10 MB)
30 06:52:45.464773 progress 45 % (11 MB)
31 06:52:45.471449 progress 50 % (12 MB)
32 06:52:45.478137 progress 55 % (13 MB)
33 06:52:45.485480 progress 60 % (15 MB)
34 06:52:45.492700 progress 65 % (16 MB)
35 06:52:45.499840 progress 70 % (17 MB)
36 06:52:45.507196 progress 75 % (18 MB)
37 06:52:45.514254 progress 80 % (20 MB)
38 06:52:45.521655 progress 85 % (21 MB)
39 06:52:45.528571 progress 90 % (22 MB)
40 06:52:45.535708 progress 95 % (23 MB)
41 06:52:45.542467 progress 100 % (25 MB)
42 06:52:45.542732 25 MB downloaded in 0.17 s (145.29 MB/s)
43 06:52:45.542899 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:52:45.543144 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:52:45.543233 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:52:45.543318 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:52:45.543443 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 06:52:45.543513 saving as /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/kernel/Image
50 06:52:45.543577 total size: 51532288 (49 MB)
51 06:52:45.543641 No compression specified
52 06:52:45.544769 progress 0 % (0 MB)
53 06:52:45.557682 progress 5 % (2 MB)
54 06:52:45.570714 progress 10 % (4 MB)
55 06:52:45.583682 progress 15 % (7 MB)
56 06:52:45.596880 progress 20 % (9 MB)
57 06:52:45.610109 progress 25 % (12 MB)
58 06:52:45.623197 progress 30 % (14 MB)
59 06:52:45.636477 progress 35 % (17 MB)
60 06:52:45.649793 progress 40 % (19 MB)
61 06:52:45.662846 progress 45 % (22 MB)
62 06:52:45.676083 progress 50 % (24 MB)
63 06:52:45.688948 progress 55 % (27 MB)
64 06:52:45.702375 progress 60 % (29 MB)
65 06:52:45.715828 progress 65 % (31 MB)
66 06:52:45.728696 progress 70 % (34 MB)
67 06:52:45.741692 progress 75 % (36 MB)
68 06:52:45.754634 progress 80 % (39 MB)
69 06:52:45.767361 progress 85 % (41 MB)
70 06:52:45.780209 progress 90 % (44 MB)
71 06:52:45.792972 progress 95 % (46 MB)
72 06:52:45.805545 progress 100 % (49 MB)
73 06:52:45.805748 49 MB downloaded in 0.26 s (187.46 MB/s)
74 06:52:45.805900 end: 1.2.1 http-download (duration 00:00:00) [common]
76 06:52:45.806148 end: 1.2 download-retry (duration 00:00:00) [common]
77 06:52:45.806239 start: 1.3 download-retry (timeout 00:10:00) [common]
78 06:52:45.806326 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 06:52:45.806462 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 06:52:45.806535 saving as /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/dtb/mt8192-asurada-spherion-r0.dtb
81 06:52:45.806598 total size: 47278 (0 MB)
82 06:52:45.806660 No compression specified
83 06:52:45.807773 progress 69 % (0 MB)
84 06:52:45.808046 progress 100 % (0 MB)
85 06:52:45.808226 0 MB downloaded in 0.00 s (27.76 MB/s)
86 06:52:45.808363 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:52:45.808588 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:52:45.808674 start: 1.4 download-retry (timeout 00:10:00) [common]
90 06:52:45.808762 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 06:52:45.808876 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 06:52:45.808946 saving as /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/modules/modules.tar
93 06:52:45.809008 total size: 8624064 (8 MB)
94 06:52:45.809072 Using unxz to decompress xz
95 06:52:45.812760 progress 0 % (0 MB)
96 06:52:45.833992 progress 5 % (0 MB)
97 06:52:45.857141 progress 10 % (0 MB)
98 06:52:45.880185 progress 15 % (1 MB)
99 06:52:45.903275 progress 20 % (1 MB)
100 06:52:45.927196 progress 25 % (2 MB)
101 06:52:45.952335 progress 30 % (2 MB)
102 06:52:45.977945 progress 35 % (2 MB)
103 06:52:46.000979 progress 40 % (3 MB)
104 06:52:46.025377 progress 45 % (3 MB)
105 06:52:46.051003 progress 50 % (4 MB)
106 06:52:46.075061 progress 55 % (4 MB)
107 06:52:46.099352 progress 60 % (4 MB)
108 06:52:46.126651 progress 65 % (5 MB)
109 06:52:46.151593 progress 70 % (5 MB)
110 06:52:46.174751 progress 75 % (6 MB)
111 06:52:46.201342 progress 80 % (6 MB)
112 06:52:46.227391 progress 85 % (7 MB)
113 06:52:46.252075 progress 90 % (7 MB)
114 06:52:46.282658 progress 95 % (7 MB)
115 06:52:46.309848 progress 100 % (8 MB)
116 06:52:46.314805 8 MB downloaded in 0.51 s (16.26 MB/s)
117 06:52:46.315055 end: 1.4.1 http-download (duration 00:00:01) [common]
119 06:52:46.315315 end: 1.4 download-retry (duration 00:00:01) [common]
120 06:52:46.315409 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 06:52:46.315508 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 06:52:46.315590 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:52:46.315679 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 06:52:46.315894 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a
125 06:52:46.316028 makedir: /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin
126 06:52:46.316133 makedir: /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/tests
127 06:52:46.316230 makedir: /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/results
128 06:52:46.316346 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-add-keys
129 06:52:46.316493 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-add-sources
130 06:52:46.316622 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-background-process-start
131 06:52:46.316750 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-background-process-stop
132 06:52:46.316876 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-common-functions
133 06:52:46.316999 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-echo-ipv4
134 06:52:46.317121 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-install-packages
135 06:52:46.317245 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-installed-packages
136 06:52:46.317367 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-os-build
137 06:52:46.317489 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-probe-channel
138 06:52:46.317610 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-probe-ip
139 06:52:46.317732 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-target-ip
140 06:52:46.317852 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-target-mac
141 06:52:46.318014 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-target-storage
142 06:52:46.318141 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-test-case
143 06:52:46.318267 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-test-event
144 06:52:46.318389 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-test-feedback
145 06:52:46.318512 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-test-raise
146 06:52:46.318634 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-test-reference
147 06:52:46.318756 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-test-runner
148 06:52:46.318876 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-test-set
149 06:52:46.319002 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-test-shell
150 06:52:46.319129 Updating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-install-packages (oe)
151 06:52:46.319278 Updating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/bin/lava-installed-packages (oe)
152 06:52:46.319403 Creating /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/environment
153 06:52:46.319503 LAVA metadata
154 06:52:46.319580 - LAVA_JOB_ID=12694845
155 06:52:46.319647 - LAVA_DISPATCHER_IP=192.168.201.1
156 06:52:46.319751 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 06:52:46.319819 skipped lava-vland-overlay
158 06:52:46.319895 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 06:52:46.319977 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 06:52:46.320045 skipped lava-multinode-overlay
161 06:52:46.320121 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 06:52:46.320203 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 06:52:46.320276 Loading test definitions
164 06:52:46.320374 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 06:52:46.320453 Using /lava-12694845 at stage 0
166 06:52:46.320752 uuid=12694845_1.5.2.3.1 testdef=None
167 06:52:46.320843 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 06:52:46.320928 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 06:52:46.321471 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 06:52:46.321827 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 06:52:46.322624 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 06:52:46.322855 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 06:52:46.323434 runner path: /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/0/tests/0_v4l2-compliance-uvc test_uuid 12694845_1.5.2.3.1
176 06:52:46.323590 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 06:52:46.323800 Creating lava-test-runner.conf files
179 06:52:46.323864 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694845/lava-overlay-87zodf9a/lava-12694845/0 for stage 0
180 06:52:46.323952 - 0_v4l2-compliance-uvc
181 06:52:46.324047 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 06:52:46.324132 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 06:52:46.330735 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 06:52:46.330844 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 06:52:46.330936 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 06:52:46.331026 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 06:52:46.331117 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 06:52:46.999121 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 06:52:46.999525 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 06:52:46.999666 extracting modules file /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694845/extract-overlay-ramdisk-c5ya2dcz/ramdisk
191 06:52:47.219009 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 06:52:47.219171 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 06:52:47.219269 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694845/compress-overlay-fdzpytfp/overlay-1.5.2.4.tar.gz to ramdisk
194 06:52:47.219343 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694845/compress-overlay-fdzpytfp/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694845/extract-overlay-ramdisk-c5ya2dcz/ramdisk
195 06:52:47.225702 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 06:52:47.225818 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 06:52:47.225995 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 06:52:47.226097 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 06:52:47.226181 Building ramdisk /var/lib/lava/dispatcher/tmp/12694845/extract-overlay-ramdisk-c5ya2dcz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694845/extract-overlay-ramdisk-c5ya2dcz/ramdisk
200 06:52:47.809507 >> 228458 blocks
201 06:52:51.642702 rename /var/lib/lava/dispatcher/tmp/12694845/extract-overlay-ramdisk-c5ya2dcz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/ramdisk/ramdisk.cpio.gz
202 06:52:51.643123 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 06:52:51.643244 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 06:52:51.643343 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 06:52:51.643451 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/kernel/Image'
206 06:53:03.867152 Returned 0 in 12 seconds
207 06:53:03.968093 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/kernel/image.itb
208 06:53:04.615233 output: FIT description: Kernel Image image with one or more FDT blobs
209 06:53:04.615584 output: Created: Sat Feb 3 06:53:04 2024
210 06:53:04.615690 output: Image 0 (kernel-1)
211 06:53:04.615759 output: Description:
212 06:53:04.615839 output: Created: Sat Feb 3 06:53:04 2024
213 06:53:04.615920 output: Type: Kernel Image
214 06:53:04.615981 output: Compression: lzma compressed
215 06:53:04.616040 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
216 06:53:04.616102 output: Architecture: AArch64
217 06:53:04.616160 output: OS: Linux
218 06:53:04.616215 output: Load Address: 0x00000000
219 06:53:04.616271 output: Entry Point: 0x00000000
220 06:53:04.616326 output: Hash algo: crc32
221 06:53:04.616380 output: Hash value: 380e7c3c
222 06:53:04.616436 output: Image 1 (fdt-1)
223 06:53:04.616492 output: Description: mt8192-asurada-spherion-r0
224 06:53:04.616545 output: Created: Sat Feb 3 06:53:04 2024
225 06:53:04.616598 output: Type: Flat Device Tree
226 06:53:04.616651 output: Compression: uncompressed
227 06:53:04.616705 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 06:53:04.616758 output: Architecture: AArch64
229 06:53:04.616811 output: Hash algo: crc32
230 06:53:04.616864 output: Hash value: cc4352de
231 06:53:04.616917 output: Image 2 (ramdisk-1)
232 06:53:04.616970 output: Description: unavailable
233 06:53:04.617022 output: Created: Sat Feb 3 06:53:04 2024
234 06:53:04.617075 output: Type: RAMDisk Image
235 06:53:04.617128 output: Compression: Unknown Compression
236 06:53:04.617181 output: Data Size: 39375623 Bytes = 38452.76 KiB = 37.55 MiB
237 06:53:04.617235 output: Architecture: AArch64
238 06:53:04.617288 output: OS: Linux
239 06:53:04.617341 output: Load Address: unavailable
240 06:53:04.617394 output: Entry Point: unavailable
241 06:53:04.617449 output: Hash algo: crc32
242 06:53:04.617517 output: Hash value: b2cb03be
243 06:53:04.617571 output: Default Configuration: 'conf-1'
244 06:53:04.617673 output: Configuration 0 (conf-1)
245 06:53:04.617754 output: Description: mt8192-asurada-spherion-r0
246 06:53:04.617820 output: Kernel: kernel-1
247 06:53:04.617874 output: Init Ramdisk: ramdisk-1
248 06:53:04.617927 output: FDT: fdt-1
249 06:53:04.618044 output: Loadables: kernel-1
250 06:53:04.618127 output:
251 06:53:04.618350 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 06:53:04.618451 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 06:53:04.618550 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 06:53:04.618639 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 06:53:04.618755 No LXC device requested
256 06:53:04.618834 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 06:53:04.618915 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 06:53:04.618993 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 06:53:04.619062 Checking files for TFTP limit of 4294967296 bytes.
260 06:53:04.619544 end: 1 tftp-deploy (duration 00:00:19) [common]
261 06:53:04.619686 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 06:53:04.619810 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 06:53:04.619933 substitutions:
264 06:53:04.619999 - {DTB}: 12694845/tftp-deploy-6d7lb4s1/dtb/mt8192-asurada-spherion-r0.dtb
265 06:53:04.620063 - {INITRD}: 12694845/tftp-deploy-6d7lb4s1/ramdisk/ramdisk.cpio.gz
266 06:53:04.620122 - {KERNEL}: 12694845/tftp-deploy-6d7lb4s1/kernel/Image
267 06:53:04.620180 - {LAVA_MAC}: None
268 06:53:04.620236 - {PRESEED_CONFIG}: None
269 06:53:04.620292 - {PRESEED_LOCAL}: None
270 06:53:04.620347 - {RAMDISK}: 12694845/tftp-deploy-6d7lb4s1/ramdisk/ramdisk.cpio.gz
271 06:53:04.620403 - {ROOT_PART}: None
272 06:53:04.620457 - {ROOT}: None
273 06:53:04.620513 - {SERVER_IP}: 192.168.201.1
274 06:53:04.620568 - {TEE}: None
275 06:53:04.620623 Parsed boot commands:
276 06:53:04.620677 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 06:53:04.620850 Parsed boot commands: tftpboot 192.168.201.1 12694845/tftp-deploy-6d7lb4s1/kernel/image.itb 12694845/tftp-deploy-6d7lb4s1/kernel/cmdline
278 06:53:04.620939 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 06:53:04.621025 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 06:53:04.621118 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 06:53:04.621200 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 06:53:04.621271 Not connected, no need to disconnect.
283 06:53:04.621345 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 06:53:04.621421 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 06:53:04.621488 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 06:53:04.625022 Setting prompt string to ['lava-test: # ']
287 06:53:04.625344 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 06:53:04.625451 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 06:53:04.625564 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 06:53:04.625772 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 06:53:04.626027 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 06:53:09.776063 >> Command sent successfully.
293 06:53:09.786214 Returned 0 in 5 seconds
294 06:53:09.887419 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 06:53:09.888832 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 06:53:09.889321 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 06:53:09.889744 Setting prompt string to 'Starting depthcharge on Spherion...'
299 06:53:09.890153 Changing prompt to 'Starting depthcharge on Spherion...'
300 06:53:09.890502 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 06:53:09.891643 [Enter `^Ec?' for help]
302 06:53:10.055321
303 06:53:10.055919
304 06:53:10.056321 F0: 102B 0000
305 06:53:10.056694
306 06:53:10.057035 F3: 1001 0000 [0200]
307 06:53:10.058290
308 06:53:10.058731 F3: 1001 0000
309 06:53:10.059078
310 06:53:10.059397 F7: 102D 0000
311 06:53:10.059707
312 06:53:10.062205 F1: 0000 0000
313 06:53:10.062741
314 06:53:10.063088 V0: 0000 0000 [0001]
315 06:53:10.063408
316 06:53:10.065075 00: 0007 8000
317 06:53:10.065639
318 06:53:10.066017 01: 0000 0000
319 06:53:10.066355
320 06:53:10.068073 BP: 0C00 0209 [0000]
321 06:53:10.068503
322 06:53:10.068916 G0: 1182 0000
323 06:53:10.069249
324 06:53:10.071698 EC: 0000 0021 [4000]
325 06:53:10.072130
326 06:53:10.072473 S7: 0000 0000 [0000]
327 06:53:10.072795
328 06:53:10.075417 CC: 0000 0000 [0001]
329 06:53:10.075852
330 06:53:10.076198 T0: 0000 0040 [010F]
331 06:53:10.076537
332 06:53:10.076974 Jump to BL
333 06:53:10.077298
334 06:53:10.102360
335 06:53:10.102806
336 06:53:10.103153
337 06:53:10.109546 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 06:53:10.113191 ARM64: Exception handlers installed.
339 06:53:10.116503 ARM64: Testing exception
340 06:53:10.120067 ARM64: Done test exception
341 06:53:10.126831 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 06:53:10.137075 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 06:53:10.143471 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 06:53:10.153515 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 06:53:10.160211 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 06:53:10.166762 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 06:53:10.179105 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 06:53:10.185641 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 06:53:10.204906 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 06:53:10.207849 WDT: Last reset was cold boot
351 06:53:10.211343 SPI1(PAD0) initialized at 2873684 Hz
352 06:53:10.214469 SPI5(PAD0) initialized at 992727 Hz
353 06:53:10.217875 VBOOT: Loading verstage.
354 06:53:10.224906 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 06:53:10.227912 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 06:53:10.231402 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 06:53:10.234862 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 06:53:10.242228 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 06:53:10.249283 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 06:53:10.260556 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 06:53:10.261143
362 06:53:10.261525
363 06:53:10.270111 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 06:53:10.273792 ARM64: Exception handlers installed.
365 06:53:10.276980 ARM64: Testing exception
366 06:53:10.277475 ARM64: Done test exception
367 06:53:10.283647 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 06:53:10.286766 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 06:53:10.300714 Probing TPM: . done!
370 06:53:10.301244 TPM ready after 0 ms
371 06:53:10.307747 Connected to device vid:did:rid of 1ae0:0028:00
372 06:53:10.314905 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 06:53:10.318399 Initialized TPM device CR50 revision 0
374 06:53:10.383027 tlcl_send_startup: Startup return code is 0
375 06:53:10.383164 TPM: setup succeeded
376 06:53:10.394998 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 06:53:10.403437 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 06:53:10.413483 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 06:53:10.423178 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 06:53:10.426669 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 06:53:10.432601 in-header: 03 07 00 00 08 00 00 00
382 06:53:10.436251 in-data: aa e4 47 04 13 02 00 00
383 06:53:10.439602 Chrome EC: UHEPI supported
384 06:53:10.446911 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 06:53:10.450702 in-header: 03 ad 00 00 08 00 00 00
386 06:53:10.454194 in-data: 00 20 20 08 00 00 00 00
387 06:53:10.454308 Phase 1
388 06:53:10.458261 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 06:53:10.465278 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 06:53:10.469047 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 06:53:10.473150 Recovery requested (1009000e)
392 06:53:10.482738 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 06:53:10.488611 tlcl_extend: response is 0
394 06:53:10.497289 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 06:53:10.503278 tlcl_extend: response is 0
396 06:53:10.509974 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 06:53:10.530354 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 06:53:10.537624 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 06:53:10.538073
400 06:53:10.538407
401 06:53:10.547344 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 06:53:10.550392 ARM64: Exception handlers installed.
403 06:53:10.550477 ARM64: Testing exception
404 06:53:10.553856 ARM64: Done test exception
405 06:53:10.575840 pmic_efuse_setting: Set efuses in 11 msecs
406 06:53:10.579129 pmwrap_interface_init: Select PMIF_VLD_RDY
407 06:53:10.585863 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 06:53:10.589545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 06:53:10.592715 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 06:53:10.599515 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 06:53:10.603202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 06:53:10.610462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 06:53:10.614275 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 06:53:10.618011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 06:53:10.622001 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 06:53:10.629432 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 06:53:10.632987 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 06:53:10.636835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 06:53:10.639928 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 06:53:10.647092 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 06:53:10.653927 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 06:53:10.661263 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 06:53:10.665147 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 06:53:10.671864 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 06:53:10.675520 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 06:53:10.682102 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 06:53:10.685248 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 06:53:10.692392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 06:53:10.699313 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 06:53:10.702594 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 06:53:10.709537 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 06:53:10.715683 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 06:53:10.719251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 06:53:10.725861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 06:53:10.729486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 06:53:10.733212 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 06:53:10.739580 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 06:53:10.743219 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 06:53:10.749882 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 06:53:10.753147 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 06:53:10.759802 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 06:53:10.763153 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 06:53:10.770191 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 06:53:10.773467 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 06:53:10.780104 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 06:53:10.783915 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 06:53:10.787712 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 06:53:10.791352 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 06:53:10.798600 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 06:53:10.801595 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 06:53:10.805018 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 06:53:10.808771 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 06:53:10.815387 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 06:53:10.818838 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 06:53:10.822640 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 06:53:10.826750 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 06:53:10.830133 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 06:53:10.837681 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 06:53:10.849212 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 06:53:10.852680 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 06:53:10.859771 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 06:53:10.867252 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 06:53:10.874124 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 06:53:10.877314 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 06:53:10.881042 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 06:53:10.888442 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1f
467 06:53:10.895492 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 06:53:10.898643 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 06:53:10.902218 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 06:53:10.913155 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 06:53:10.923071 [RTC]rtc_get_frequency_meter,154: input=23, output=959
472 06:53:10.932528 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 06:53:10.942242 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 06:53:10.952096 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 06:53:10.955181 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 06:53:10.958325 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 06:53:10.965708 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 06:53:10.968594 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 06:53:10.972012 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 06:53:10.975185 ADC[4]: Raw value=902876 ID=7
481 06:53:10.978431 ADC[3]: Raw value=213179 ID=1
482 06:53:10.978911 RAM Code: 0x71
483 06:53:10.985638 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 06:53:10.988966 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 06:53:10.998858 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 06:53:11.005533 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 06:53:11.009111 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 06:53:11.012354 in-header: 03 07 00 00 08 00 00 00
489 06:53:11.015585 in-data: aa e4 47 04 13 02 00 00
490 06:53:11.019116 Chrome EC: UHEPI supported
491 06:53:11.025783 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 06:53:11.029118 in-header: 03 ed 00 00 08 00 00 00
493 06:53:11.032361 in-data: 80 20 60 08 00 00 00 00
494 06:53:11.035599 MRC: failed to locate region type 0.
495 06:53:11.039101 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 06:53:11.042299 DRAM-K: Running full calibration
497 06:53:11.048970 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 06:53:11.052416 header.status = 0x0
499 06:53:11.055922 header.version = 0x6 (expected: 0x6)
500 06:53:11.059179 header.size = 0xd00 (expected: 0xd00)
501 06:53:11.059653 header.flags = 0x0
502 06:53:11.065692 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 06:53:11.083968 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
504 06:53:11.091025 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 06:53:11.093975 dram_init: ddr_geometry: 2
506 06:53:11.094468 [EMI] MDL number = 2
507 06:53:11.097432 [EMI] Get MDL freq = 0
508 06:53:11.100663 dram_init: ddr_type: 0
509 06:53:11.101241 is_discrete_lpddr4: 1
510 06:53:11.104349 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 06:53:11.104927
512 06:53:11.105306
513 06:53:11.107025 [Bian_co] ETT version 0.0.0.1
514 06:53:11.114377 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 06:53:11.114955
516 06:53:11.117565 dramc_set_vcore_voltage set vcore to 650000
517 06:53:11.118180 Read voltage for 800, 4
518 06:53:11.121293 Vio18 = 0
519 06:53:11.121863 Vcore = 650000
520 06:53:11.122279 Vdram = 0
521 06:53:11.123677 Vddq = 0
522 06:53:11.124196 Vmddr = 0
523 06:53:11.127480 dram_init: config_dvfs: 1
524 06:53:11.130467 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 06:53:11.136926 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 06:53:11.140815 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
527 06:53:11.143931 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
528 06:53:11.147515 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 06:53:11.150957 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 06:53:11.153563 MEM_TYPE=3, freq_sel=18
531 06:53:11.157284 sv_algorithm_assistance_LP4_1600
532 06:53:11.160390 ============ PULL DRAM RESETB DOWN ============
533 06:53:11.164016 ========== PULL DRAM RESETB DOWN end =========
534 06:53:11.170347 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 06:53:11.173821 ===================================
536 06:53:11.176890 LPDDR4 DRAM CONFIGURATION
537 06:53:11.180516 ===================================
538 06:53:11.180988 EX_ROW_EN[0] = 0x0
539 06:53:11.183760 EX_ROW_EN[1] = 0x0
540 06:53:11.184227 LP4Y_EN = 0x0
541 06:53:11.187091 WORK_FSP = 0x0
542 06:53:11.187565 WL = 0x2
543 06:53:11.190490 RL = 0x2
544 06:53:11.190967 BL = 0x2
545 06:53:11.193781 RPST = 0x0
546 06:53:11.194305 RD_PRE = 0x0
547 06:53:11.197157 WR_PRE = 0x1
548 06:53:11.197629 WR_PST = 0x0
549 06:53:11.200404 DBI_WR = 0x0
550 06:53:11.200931 DBI_RD = 0x0
551 06:53:11.203761 OTF = 0x1
552 06:53:11.207028 ===================================
553 06:53:11.210667 ===================================
554 06:53:11.211245 ANA top config
555 06:53:11.214113 ===================================
556 06:53:11.217500 DLL_ASYNC_EN = 0
557 06:53:11.220746 ALL_SLAVE_EN = 1
558 06:53:11.223972 NEW_RANK_MODE = 1
559 06:53:11.224452 DLL_IDLE_MODE = 1
560 06:53:11.227083 LP45_APHY_COMB_EN = 1
561 06:53:11.230339 TX_ODT_DIS = 1
562 06:53:11.233871 NEW_8X_MODE = 1
563 06:53:11.237222 ===================================
564 06:53:11.240797 ===================================
565 06:53:11.244219 data_rate = 1600
566 06:53:11.244792 CKR = 1
567 06:53:11.247864 DQ_P2S_RATIO = 8
568 06:53:11.251279 ===================================
569 06:53:11.255943 CA_P2S_RATIO = 8
570 06:53:11.256520 DQ_CA_OPEN = 0
571 06:53:11.258818 DQ_SEMI_OPEN = 0
572 06:53:11.262526 CA_SEMI_OPEN = 0
573 06:53:11.266330 CA_FULL_RATE = 0
574 06:53:11.266952 DQ_CKDIV4_EN = 1
575 06:53:11.270033 CA_CKDIV4_EN = 1
576 06:53:11.274282 CA_PREDIV_EN = 0
577 06:53:11.277258 PH8_DLY = 0
578 06:53:11.277732 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 06:53:11.280928 DQ_AAMCK_DIV = 4
580 06:53:11.284655 CA_AAMCK_DIV = 4
581 06:53:11.288563 CA_ADMCK_DIV = 4
582 06:53:11.289159 DQ_TRACK_CA_EN = 0
583 06:53:11.291941 CA_PICK = 800
584 06:53:11.295851 CA_MCKIO = 800
585 06:53:11.300092 MCKIO_SEMI = 0
586 06:53:11.300691 PLL_FREQ = 3068
587 06:53:11.303840 DQ_UI_PI_RATIO = 32
588 06:53:11.307418 CA_UI_PI_RATIO = 0
589 06:53:11.311170 ===================================
590 06:53:11.314834 ===================================
591 06:53:11.315261 memory_type:LPDDR4
592 06:53:11.318513 GP_NUM : 10
593 06:53:11.319097 SRAM_EN : 1
594 06:53:11.322407 MD32_EN : 0
595 06:53:11.325658 ===================================
596 06:53:11.329842 [ANA_INIT] >>>>>>>>>>>>>>
597 06:53:11.330509 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 06:53:11.333059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 06:53:11.336897 ===================================
600 06:53:11.340747 data_rate = 1600,PCW = 0X7600
601 06:53:11.344566 ===================================
602 06:53:11.348093 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 06:53:11.352140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 06:53:11.359187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 06:53:11.363003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 06:53:11.366709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 06:53:11.370316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 06:53:11.370933 [ANA_INIT] flow start
609 06:53:11.373682 [ANA_INIT] PLL >>>>>>>>
610 06:53:11.374212 [ANA_INIT] PLL <<<<<<<<
611 06:53:11.377763 [ANA_INIT] MIDPI >>>>>>>>
612 06:53:11.381001 [ANA_INIT] MIDPI <<<<<<<<
613 06:53:11.381497 [ANA_INIT] DLL >>>>>>>>
614 06:53:11.384892 [ANA_INIT] flow end
615 06:53:11.388743 ============ LP4 DIFF to SE enter ============
616 06:53:11.392403 ============ LP4 DIFF to SE exit ============
617 06:53:11.396234 [ANA_INIT] <<<<<<<<<<<<<
618 06:53:11.400021 [Flow] Enable top DCM control >>>>>
619 06:53:11.403814 [Flow] Enable top DCM control <<<<<
620 06:53:11.404294 Enable DLL master slave shuffle
621 06:53:11.411376 ==============================================================
622 06:53:11.411857 Gating Mode config
623 06:53:11.419006 ==============================================================
624 06:53:11.419490 Config description:
625 06:53:11.429770 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 06:53:11.437376 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 06:53:11.441134 SELPH_MODE 0: By rank 1: By Phase
628 06:53:11.444738 ==============================================================
629 06:53:11.448757 GAT_TRACK_EN = 1
630 06:53:11.452410 RX_GATING_MODE = 2
631 06:53:11.455829 RX_GATING_TRACK_MODE = 2
632 06:53:11.459573 SELPH_MODE = 1
633 06:53:11.463466 PICG_EARLY_EN = 1
634 06:53:11.464045 VALID_LAT_VALUE = 1
635 06:53:11.470686 ==============================================================
636 06:53:11.474687 Enter into Gating configuration >>>>
637 06:53:11.478294 Exit from Gating configuration <<<<
638 06:53:11.479025 Enter into DVFS_PRE_config >>>>>
639 06:53:11.489165 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 06:53:11.493201 Exit from DVFS_PRE_config <<<<<
641 06:53:11.496926 Enter into PICG configuration >>>>
642 06:53:11.500838 Exit from PICG configuration <<<<
643 06:53:11.505306 [RX_INPUT] configuration >>>>>
644 06:53:11.505741 [RX_INPUT] configuration <<<<<
645 06:53:11.512411 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 06:53:11.515783 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 06:53:11.523336 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 06:53:11.526946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 06:53:11.534293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 06:53:11.541802 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 06:53:11.545355 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 06:53:11.549274 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 06:53:11.552635 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 06:53:11.556879 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 06:53:11.560006 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 06:53:11.567565 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 06:53:11.568144 ===================================
658 06:53:11.571374 LPDDR4 DRAM CONFIGURATION
659 06:53:11.574984 ===================================
660 06:53:11.575555 EX_ROW_EN[0] = 0x0
661 06:53:11.578575 EX_ROW_EN[1] = 0x0
662 06:53:11.582184 LP4Y_EN = 0x0
663 06:53:11.582654 WORK_FSP = 0x0
664 06:53:11.583043 WL = 0x2
665 06:53:11.585856 RL = 0x2
666 06:53:11.586386 BL = 0x2
667 06:53:11.589594 RPST = 0x0
668 06:53:11.590101 RD_PRE = 0x0
669 06:53:11.593169 WR_PRE = 0x1
670 06:53:11.593755 WR_PST = 0x0
671 06:53:11.596301 DBI_WR = 0x0
672 06:53:11.596782 DBI_RD = 0x0
673 06:53:11.600174 OTF = 0x1
674 06:53:11.603238 ===================================
675 06:53:11.606473 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 06:53:11.609846 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 06:53:11.616297 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 06:53:11.619684 ===================================
679 06:53:11.620276 LPDDR4 DRAM CONFIGURATION
680 06:53:11.623418 ===================================
681 06:53:11.626543 EX_ROW_EN[0] = 0x10
682 06:53:11.630106 EX_ROW_EN[1] = 0x0
683 06:53:11.630677 LP4Y_EN = 0x0
684 06:53:11.632987 WORK_FSP = 0x0
685 06:53:11.633507 WL = 0x2
686 06:53:11.636682 RL = 0x2
687 06:53:11.637252 BL = 0x2
688 06:53:11.639687 RPST = 0x0
689 06:53:11.640252 RD_PRE = 0x0
690 06:53:11.643075 WR_PRE = 0x1
691 06:53:11.643564 WR_PST = 0x0
692 06:53:11.646598 DBI_WR = 0x0
693 06:53:11.647165 DBI_RD = 0x0
694 06:53:11.650074 OTF = 0x1
695 06:53:11.653267 ===================================
696 06:53:11.659694 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 06:53:11.663318 nWR fixed to 40
698 06:53:11.663882 [ModeRegInit_LP4] CH0 RK0
699 06:53:11.666711 [ModeRegInit_LP4] CH0 RK1
700 06:53:11.669830 [ModeRegInit_LP4] CH1 RK0
701 06:53:11.670446 [ModeRegInit_LP4] CH1 RK1
702 06:53:11.673244 match AC timing 13
703 06:53:11.676695 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 06:53:11.679739 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 06:53:11.686776 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 06:53:11.690043 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 06:53:11.696423 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 06:53:11.697138 [EMI DOE] emi_dcm 0
709 06:53:11.700076 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 06:53:11.703244 ==
711 06:53:11.706422 Dram Type= 6, Freq= 0, CH_0, rank 0
712 06:53:11.709504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 06:53:11.710012 ==
714 06:53:11.712888 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 06:53:11.719883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 06:53:11.729730 [CA 0] Center 38 (7~69) winsize 63
717 06:53:11.733230 [CA 1] Center 38 (7~69) winsize 63
718 06:53:11.736764 [CA 2] Center 35 (5~66) winsize 62
719 06:53:11.739954 [CA 3] Center 35 (5~66) winsize 62
720 06:53:11.743123 [CA 4] Center 34 (4~65) winsize 62
721 06:53:11.746387 [CA 5] Center 33 (3~64) winsize 62
722 06:53:11.746965
723 06:53:11.749983 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 06:53:11.750561
725 06:53:11.752793 [CATrainingPosCal] consider 1 rank data
726 06:53:11.756318 u2DelayCellTimex100 = 270/100 ps
727 06:53:11.759769 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 06:53:11.763292 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 06:53:11.769691 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 06:53:11.773087 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 06:53:11.776810 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 06:53:11.779851 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 06:53:11.780427
734 06:53:11.782838 CA PerBit enable=1, Macro0, CA PI delay=33
735 06:53:11.783403
736 06:53:11.786427 [CBTSetCACLKResult] CA Dly = 33
737 06:53:11.786897 CS Dly: 6 (0~37)
738 06:53:11.790113 ==
739 06:53:11.790683 Dram Type= 6, Freq= 0, CH_0, rank 1
740 06:53:11.796443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 06:53:11.797071 ==
742 06:53:11.799836 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 06:53:11.806317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 06:53:11.816188 [CA 0] Center 38 (7~69) winsize 63
745 06:53:11.819777 [CA 1] Center 38 (7~69) winsize 63
746 06:53:11.822896 [CA 2] Center 36 (6~66) winsize 61
747 06:53:11.826330 [CA 3] Center 35 (5~66) winsize 62
748 06:53:11.829689 [CA 4] Center 35 (4~66) winsize 63
749 06:53:11.832992 [CA 5] Center 34 (4~65) winsize 62
750 06:53:11.833464
751 06:53:11.836442 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 06:53:11.837042
753 06:53:11.839562 [CATrainingPosCal] consider 2 rank data
754 06:53:11.842988 u2DelayCellTimex100 = 270/100 ps
755 06:53:11.846083 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 06:53:11.849900 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 06:53:11.856483 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 06:53:11.859723 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 06:53:11.863114 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 06:53:11.866295 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 06:53:11.866875
762 06:53:11.870097 CA PerBit enable=1, Macro0, CA PI delay=34
763 06:53:11.870678
764 06:53:11.873118 [CBTSetCACLKResult] CA Dly = 34
765 06:53:11.873591 CS Dly: 6 (0~38)
766 06:53:11.874053
767 06:53:11.876801 ----->DramcWriteLeveling(PI) begin...
768 06:53:11.880041 ==
769 06:53:11.880624 Dram Type= 6, Freq= 0, CH_0, rank 0
770 06:53:11.886110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 06:53:11.886610 ==
772 06:53:11.889910 Write leveling (Byte 0): 29 => 29
773 06:53:11.893075 Write leveling (Byte 1): 32 => 32
774 06:53:11.896859 DramcWriteLeveling(PI) end<-----
775 06:53:11.897440
776 06:53:11.897823 ==
777 06:53:11.899871 Dram Type= 6, Freq= 0, CH_0, rank 0
778 06:53:11.902813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 06:53:11.903306 ==
780 06:53:11.906588 [Gating] SW mode calibration
781 06:53:11.914149 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 06:53:11.917874 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 06:53:11.921610 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 06:53:11.925175 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 06:53:11.932319 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 06:53:11.935471 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 06:53:11.938775 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 06:53:11.942652 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 06:53:11.949180 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 06:53:11.952767 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 06:53:11.955932 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 06:53:11.962952 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 06:53:11.965798 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 06:53:11.969430 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 06:53:11.976223 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 06:53:11.979378 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 06:53:11.982614 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 06:53:11.989368 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 06:53:11.992691 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 06:53:11.995740 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
801 06:53:12.002676 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
802 06:53:12.005900 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 06:53:12.009063 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 06:53:12.015830 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 06:53:12.019055 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 06:53:12.022432 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 06:53:12.025656 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 06:53:12.032304 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
809 06:53:12.036145 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 06:53:12.039274 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
811 06:53:12.045995 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 06:53:12.049247 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 06:53:12.053133 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 06:53:12.059990 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 06:53:12.062478 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
816 06:53:12.066190 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
817 06:53:12.072523 0 10 8 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
818 06:53:12.076260 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
819 06:53:12.079224 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 06:53:12.085690 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 06:53:12.089299 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 06:53:12.092557 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 06:53:12.098756 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 06:53:12.102808 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
825 06:53:12.105918 0 11 8 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
826 06:53:12.112717 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
827 06:53:12.115924 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 06:53:12.119503 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 06:53:12.122744 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 06:53:12.129708 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 06:53:12.132485 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 06:53:12.135709 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 06:53:12.142638 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 06:53:12.146639 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 06:53:12.149357 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 06:53:12.156009 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 06:53:12.159377 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 06:53:12.162701 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 06:53:12.169491 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 06:53:12.173194 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 06:53:12.175981 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 06:53:12.182890 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 06:53:12.185908 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 06:53:12.189693 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 06:53:12.196048 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 06:53:12.199170 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 06:53:12.202912 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 06:53:12.206224 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 06:53:12.212811 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 06:53:12.216326 Total UI for P1: 0, mck2ui 16
851 06:53:12.219499 best dqsien dly found for B0: ( 0, 14, 4)
852 06:53:12.223153 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 06:53:12.225919 Total UI for P1: 0, mck2ui 16
854 06:53:12.229448 best dqsien dly found for B1: ( 0, 14, 8)
855 06:53:12.233043 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
856 06:53:12.236501 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
857 06:53:12.237098
858 06:53:12.239759 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 06:53:12.242546 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
860 06:53:12.246073 [Gating] SW calibration Done
861 06:53:12.246674 ==
862 06:53:12.249710 Dram Type= 6, Freq= 0, CH_0, rank 0
863 06:53:12.252791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 06:53:12.256308 ==
865 06:53:12.256896 RX Vref Scan: 0
866 06:53:12.257278
867 06:53:12.259726 RX Vref 0 -> 0, step: 1
868 06:53:12.260204
869 06:53:12.262936 RX Delay -130 -> 252, step: 16
870 06:53:12.266295 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
871 06:53:12.269914 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 06:53:12.273126 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 06:53:12.276009 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 06:53:12.283031 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
875 06:53:12.285979 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 06:53:12.289542 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 06:53:12.292994 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 06:53:12.296199 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 06:53:12.303044 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 06:53:12.306349 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 06:53:12.309501 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 06:53:12.313257 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
883 06:53:12.316403 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 06:53:12.323158 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 06:53:12.326366 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
886 06:53:12.326943 ==
887 06:53:12.329459 Dram Type= 6, Freq= 0, CH_0, rank 0
888 06:53:12.333161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 06:53:12.333745 ==
890 06:53:12.336127 DQS Delay:
891 06:53:12.336618 DQS0 = 0, DQS1 = 0
892 06:53:12.336997 DQM Delay:
893 06:53:12.339473 DQM0 = 91, DQM1 = 81
894 06:53:12.339975 DQ Delay:
895 06:53:12.343358 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
896 06:53:12.346060 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
897 06:53:12.349448 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
898 06:53:12.352905 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
899 06:53:12.353462
900 06:53:12.353838
901 06:53:12.354245 ==
902 06:53:12.355961 Dram Type= 6, Freq= 0, CH_0, rank 0
903 06:53:12.362596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 06:53:12.363228 ==
905 06:53:12.363611
906 06:53:12.363960
907 06:53:12.364291 TX Vref Scan disable
908 06:53:12.366133 == TX Byte 0 ==
909 06:53:12.369531 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
910 06:53:12.372904 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
911 06:53:12.375988 == TX Byte 1 ==
912 06:53:12.379701 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 06:53:12.382595 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 06:53:12.386330 ==
915 06:53:12.389709 Dram Type= 6, Freq= 0, CH_0, rank 0
916 06:53:12.393147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 06:53:12.393723 ==
918 06:53:12.405318 TX Vref=22, minBit 1, minWin=27, winSum=439
919 06:53:12.408432 TX Vref=24, minBit 5, minWin=27, winSum=442
920 06:53:12.412164 TX Vref=26, minBit 5, minWin=27, winSum=444
921 06:53:12.415230 TX Vref=28, minBit 8, minWin=27, winSum=450
922 06:53:12.418812 TX Vref=30, minBit 8, minWin=27, winSum=454
923 06:53:12.421857 TX Vref=32, minBit 5, minWin=28, winSum=453
924 06:53:12.428853 [TxChooseVref] Worse bit 5, Min win 28, Win sum 453, Final Vref 32
925 06:53:12.429431
926 06:53:12.432055 Final TX Range 1 Vref 32
927 06:53:12.432634
928 06:53:12.433013 ==
929 06:53:12.435596 Dram Type= 6, Freq= 0, CH_0, rank 0
930 06:53:12.438744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 06:53:12.439225 ==
932 06:53:12.439606
933 06:53:12.439956
934 06:53:12.441876 TX Vref Scan disable
935 06:53:12.445465 == TX Byte 0 ==
936 06:53:12.448794 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
937 06:53:12.452044 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
938 06:53:12.455548 == TX Byte 1 ==
939 06:53:12.458609 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 06:53:12.461902 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 06:53:12.462436
942 06:53:12.465155 [DATLAT]
943 06:53:12.465699 Freq=800, CH0 RK0
944 06:53:12.466119
945 06:53:12.468669 DATLAT Default: 0xa
946 06:53:12.469139 0, 0xFFFF, sum = 0
947 06:53:12.472005 1, 0xFFFF, sum = 0
948 06:53:12.472481 2, 0xFFFF, sum = 0
949 06:53:12.475277 3, 0xFFFF, sum = 0
950 06:53:12.475998 4, 0xFFFF, sum = 0
951 06:53:12.478778 5, 0xFFFF, sum = 0
952 06:53:12.479211 6, 0xFFFF, sum = 0
953 06:53:12.481919 7, 0xFFFF, sum = 0
954 06:53:12.482381 8, 0xFFFF, sum = 0
955 06:53:12.485289 9, 0x0, sum = 1
956 06:53:12.485720 10, 0x0, sum = 2
957 06:53:12.488849 11, 0x0, sum = 3
958 06:53:12.489279 12, 0x0, sum = 4
959 06:53:12.492558 best_step = 10
960 06:53:12.493082
961 06:53:12.493424 ==
962 06:53:12.495331 Dram Type= 6, Freq= 0, CH_0, rank 0
963 06:53:12.498919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 06:53:12.499349 ==
965 06:53:12.502003 RX Vref Scan: 1
966 06:53:12.502429
967 06:53:12.502768 Set Vref Range= 32 -> 127
968 06:53:12.503085
969 06:53:12.505335 RX Vref 32 -> 127, step: 1
970 06:53:12.505764
971 06:53:12.508990 RX Delay -95 -> 252, step: 8
972 06:53:12.509441
973 06:53:12.512354 Set Vref, RX VrefLevel [Byte0]: 32
974 06:53:12.515580 [Byte1]: 32
975 06:53:12.516110
976 06:53:12.518573 Set Vref, RX VrefLevel [Byte0]: 33
977 06:53:12.522304 [Byte1]: 33
978 06:53:12.522830
979 06:53:12.525381 Set Vref, RX VrefLevel [Byte0]: 34
980 06:53:12.528796 [Byte1]: 34
981 06:53:12.533020
982 06:53:12.533545 Set Vref, RX VrefLevel [Byte0]: 35
983 06:53:12.536598 [Byte1]: 35
984 06:53:12.540732
985 06:53:12.541253 Set Vref, RX VrefLevel [Byte0]: 36
986 06:53:12.543752 [Byte1]: 36
987 06:53:12.548201
988 06:53:12.548745 Set Vref, RX VrefLevel [Byte0]: 37
989 06:53:12.551935 [Byte1]: 37
990 06:53:12.555861
991 06:53:12.556438 Set Vref, RX VrefLevel [Byte0]: 38
992 06:53:12.559439 [Byte1]: 38
993 06:53:12.563143
994 06:53:12.563670 Set Vref, RX VrefLevel [Byte0]: 39
995 06:53:12.566927 [Byte1]: 39
996 06:53:12.571251
997 06:53:12.571781 Set Vref, RX VrefLevel [Byte0]: 40
998 06:53:12.574015 [Byte1]: 40
999 06:53:12.578811
1000 06:53:12.579332 Set Vref, RX VrefLevel [Byte0]: 41
1001 06:53:12.581917 [Byte1]: 41
1002 06:53:12.586386
1003 06:53:12.586830 Set Vref, RX VrefLevel [Byte0]: 42
1004 06:53:12.589740 [Byte1]: 42
1005 06:53:12.594201
1006 06:53:12.594717 Set Vref, RX VrefLevel [Byte0]: 43
1007 06:53:12.597558 [Byte1]: 43
1008 06:53:12.601674
1009 06:53:12.602131 Set Vref, RX VrefLevel [Byte0]: 44
1010 06:53:12.605319 [Byte1]: 44
1011 06:53:12.609201
1012 06:53:12.609751 Set Vref, RX VrefLevel [Byte0]: 45
1013 06:53:12.612694 [Byte1]: 45
1014 06:53:12.616784
1015 06:53:12.617309 Set Vref, RX VrefLevel [Byte0]: 46
1016 06:53:12.619959 [Byte1]: 46
1017 06:53:12.624192
1018 06:53:12.624722 Set Vref, RX VrefLevel [Byte0]: 47
1019 06:53:12.627277 [Byte1]: 47
1020 06:53:12.631702
1021 06:53:12.632229 Set Vref, RX VrefLevel [Byte0]: 48
1022 06:53:12.634698 [Byte1]: 48
1023 06:53:12.639176
1024 06:53:12.639702 Set Vref, RX VrefLevel [Byte0]: 49
1025 06:53:12.642806 [Byte1]: 49
1026 06:53:12.646825
1027 06:53:12.647368 Set Vref, RX VrefLevel [Byte0]: 50
1028 06:53:12.649909 [Byte1]: 50
1029 06:53:12.654372
1030 06:53:12.654792 Set Vref, RX VrefLevel [Byte0]: 51
1031 06:53:12.657587 [Byte1]: 51
1032 06:53:12.661991
1033 06:53:12.662512 Set Vref, RX VrefLevel [Byte0]: 52
1034 06:53:12.665291 [Byte1]: 52
1035 06:53:12.669772
1036 06:53:12.670355 Set Vref, RX VrefLevel [Byte0]: 53
1037 06:53:12.672803 [Byte1]: 53
1038 06:53:12.677622
1039 06:53:12.678194 Set Vref, RX VrefLevel [Byte0]: 54
1040 06:53:12.680635 [Byte1]: 54
1041 06:53:12.685292
1042 06:53:12.685812 Set Vref, RX VrefLevel [Byte0]: 55
1043 06:53:12.687994 [Byte1]: 55
1044 06:53:12.692661
1045 06:53:12.693180 Set Vref, RX VrefLevel [Byte0]: 56
1046 06:53:12.695811 [Byte1]: 56
1047 06:53:12.699901
1048 06:53:12.700361 Set Vref, RX VrefLevel [Byte0]: 57
1049 06:53:12.703065 [Byte1]: 57
1050 06:53:12.708057
1051 06:53:12.708615 Set Vref, RX VrefLevel [Byte0]: 58
1052 06:53:12.710975 [Byte1]: 58
1053 06:53:12.715121
1054 06:53:12.715596 Set Vref, RX VrefLevel [Byte0]: 59
1055 06:53:12.718718 [Byte1]: 59
1056 06:53:12.723037
1057 06:53:12.723612 Set Vref, RX VrefLevel [Byte0]: 60
1058 06:53:12.726258 [Byte1]: 60
1059 06:53:12.730645
1060 06:53:12.731220 Set Vref, RX VrefLevel [Byte0]: 61
1061 06:53:12.733917 [Byte1]: 61
1062 06:53:12.738225
1063 06:53:12.738793 Set Vref, RX VrefLevel [Byte0]: 62
1064 06:53:12.741534 [Byte1]: 62
1065 06:53:12.746088
1066 06:53:12.746662 Set Vref, RX VrefLevel [Byte0]: 63
1067 06:53:12.748868 [Byte1]: 63
1068 06:53:12.753337
1069 06:53:12.753907 Set Vref, RX VrefLevel [Byte0]: 64
1070 06:53:12.756840 [Byte1]: 64
1071 06:53:12.760596
1072 06:53:12.761158 Set Vref, RX VrefLevel [Byte0]: 65
1073 06:53:12.764208 [Byte1]: 65
1074 06:53:12.768114
1075 06:53:12.768582 Set Vref, RX VrefLevel [Byte0]: 66
1076 06:53:12.771553 [Byte1]: 66
1077 06:53:12.775840
1078 06:53:12.776303 Set Vref, RX VrefLevel [Byte0]: 67
1079 06:53:12.779115 [Byte1]: 67
1080 06:53:12.783648
1081 06:53:12.784227 Set Vref, RX VrefLevel [Byte0]: 68
1082 06:53:12.786976 [Byte1]: 68
1083 06:53:12.790977
1084 06:53:12.791440 Set Vref, RX VrefLevel [Byte0]: 69
1085 06:53:12.794429 [Byte1]: 69
1086 06:53:12.798645
1087 06:53:12.799109 Set Vref, RX VrefLevel [Byte0]: 70
1088 06:53:12.802080 [Byte1]: 70
1089 06:53:12.806486
1090 06:53:12.806950 Set Vref, RX VrefLevel [Byte0]: 71
1091 06:53:12.809625 [Byte1]: 71
1092 06:53:12.813880
1093 06:53:12.814367 Set Vref, RX VrefLevel [Byte0]: 72
1094 06:53:12.816830 [Byte1]: 72
1095 06:53:12.821466
1096 06:53:12.821892 Set Vref, RX VrefLevel [Byte0]: 73
1097 06:53:12.824634 [Byte1]: 73
1098 06:53:12.828726
1099 06:53:12.829152 Set Vref, RX VrefLevel [Byte0]: 74
1100 06:53:12.832772 [Byte1]: 74
1101 06:53:12.836160
1102 06:53:12.836243 Set Vref, RX VrefLevel [Byte0]: 75
1103 06:53:12.839395 [Byte1]: 75
1104 06:53:12.843796
1105 06:53:12.843879 Set Vref, RX VrefLevel [Byte0]: 76
1106 06:53:12.847137 [Byte1]: 76
1107 06:53:12.851517
1108 06:53:12.851599 Final RX Vref Byte 0 = 60 to rank0
1109 06:53:12.854717 Final RX Vref Byte 1 = 52 to rank0
1110 06:53:12.858192 Final RX Vref Byte 0 = 60 to rank1
1111 06:53:12.861324 Final RX Vref Byte 1 = 52 to rank1==
1112 06:53:12.864933 Dram Type= 6, Freq= 0, CH_0, rank 0
1113 06:53:12.871761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1114 06:53:12.871887 ==
1115 06:53:12.871976 DQS Delay:
1116 06:53:12.872061 DQS0 = 0, DQS1 = 0
1117 06:53:12.874828 DQM Delay:
1118 06:53:12.874940 DQM0 = 92, DQM1 = 81
1119 06:53:12.878348 DQ Delay:
1120 06:53:12.881359 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1121 06:53:12.884669 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1122 06:53:12.888330 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1123 06:53:12.891607 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1124 06:53:12.891780
1125 06:53:12.891919
1126 06:53:12.898399 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1127 06:53:12.901791 CH0 RK0: MR19=606, MR18=3D39
1128 06:53:12.908584 CH0_RK0: MR19=0x606, MR18=0x3D39, DQSOSC=394, MR23=63, INC=95, DEC=63
1129 06:53:12.908893
1130 06:53:12.911718 ----->DramcWriteLeveling(PI) begin...
1131 06:53:12.912125 ==
1132 06:53:12.914940 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 06:53:12.918671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 06:53:12.919111 ==
1135 06:53:12.921650 Write leveling (Byte 0): 29 => 29
1136 06:53:12.924945 Write leveling (Byte 1): 27 => 27
1137 06:53:12.928408 DramcWriteLeveling(PI) end<-----
1138 06:53:12.928833
1139 06:53:12.929168 ==
1140 06:53:12.931690 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 06:53:12.935349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 06:53:12.935781 ==
1143 06:53:12.938754 [Gating] SW mode calibration
1144 06:53:12.945011 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1145 06:53:12.951611 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1146 06:53:12.955035 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1147 06:53:12.958190 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1148 06:53:12.965564 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 06:53:12.968528 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 06:53:12.971812 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 06:53:12.978229 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 06:53:12.981738 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 06:53:13.025860 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 06:53:13.026386 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 06:53:13.027060 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 06:53:13.027404 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 06:53:13.027712 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 06:53:13.028015 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 06:53:13.028308 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 06:53:13.028598 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 06:53:13.028887 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 06:53:13.029172 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 06:53:13.069630 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1164 06:53:13.070103 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 06:53:13.070763 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 06:53:13.071108 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 06:53:13.071419 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 06:53:13.071736 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 06:53:13.072220 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 06:53:13.072589 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 06:53:13.072992 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 06:53:13.073468 0 9 8 | B1->B0 | 2b2b 3232 | 0 1 | (0 0) (1 1)
1173 06:53:13.083183 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 06:53:13.083935 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 06:53:13.087022 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 06:53:13.087457 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 06:53:13.090690 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 06:53:13.096810 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 06:53:13.100365 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
1180 06:53:13.103948 0 10 8 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
1181 06:53:13.110042 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 06:53:13.113663 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 06:53:13.116745 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 06:53:13.123619 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 06:53:13.126933 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 06:53:13.130237 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 06:53:13.136951 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1188 06:53:13.140145 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1189 06:53:13.143208 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 06:53:13.149691 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 06:53:13.153282 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 06:53:13.156605 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 06:53:13.160344 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 06:53:13.164362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 06:53:13.172081 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1196 06:53:13.175359 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1197 06:53:13.178667 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 06:53:13.185118 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 06:53:13.189423 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 06:53:13.192408 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 06:53:13.195617 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 06:53:13.202303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 06:53:13.206214 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 06:53:13.209262 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 06:53:13.216421 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 06:53:13.219755 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 06:53:13.223166 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 06:53:13.229885 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 06:53:13.232800 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 06:53:13.236015 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 06:53:13.239742 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 06:53:13.246455 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 06:53:13.249252 Total UI for P1: 0, mck2ui 16
1214 06:53:13.252769 best dqsien dly found for B0: ( 0, 14, 6)
1215 06:53:13.256177 Total UI for P1: 0, mck2ui 16
1216 06:53:13.259773 best dqsien dly found for B1: ( 0, 14, 6)
1217 06:53:13.262660 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1218 06:53:13.266162 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1219 06:53:13.266719
1220 06:53:13.269791 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1221 06:53:13.273380 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1222 06:53:13.276519 [Gating] SW calibration Done
1223 06:53:13.276990 ==
1224 06:53:13.279670 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 06:53:13.283097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 06:53:13.283667 ==
1227 06:53:13.286649 RX Vref Scan: 0
1228 06:53:13.287208
1229 06:53:13.287579 RX Vref 0 -> 0, step: 1
1230 06:53:13.287926
1231 06:53:13.289505 RX Delay -130 -> 252, step: 16
1232 06:53:13.293036 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1233 06:53:13.299792 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1234 06:53:13.302817 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1235 06:53:13.306526 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1236 06:53:13.309647 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1237 06:53:13.312836 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1238 06:53:13.319589 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1239 06:53:13.322757 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1240 06:53:13.326495 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1241 06:53:13.329586 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1242 06:53:13.333084 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1243 06:53:13.339480 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1244 06:53:13.342993 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1245 06:53:13.346588 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1246 06:53:13.349931 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1247 06:53:13.353003 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1248 06:53:13.356200 ==
1249 06:53:13.356671 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 06:53:13.362967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1251 06:53:13.363532 ==
1252 06:53:13.363909 DQS Delay:
1253 06:53:13.366779 DQS0 = 0, DQS1 = 0
1254 06:53:13.367341 DQM Delay:
1255 06:53:13.369726 DQM0 = 92, DQM1 = 79
1256 06:53:13.370387 DQ Delay:
1257 06:53:13.373053 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =85
1258 06:53:13.376181 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
1259 06:53:13.379878 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1260 06:53:13.382854 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1261 06:53:13.383417
1262 06:53:13.383788
1263 06:53:13.384130 ==
1264 06:53:13.386470 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 06:53:13.389740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 06:53:13.390251 ==
1267 06:53:13.390637
1268 06:53:13.391219
1269 06:53:13.392985 TX Vref Scan disable
1270 06:53:13.396537 == TX Byte 0 ==
1271 06:53:13.399919 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1272 06:53:13.402867 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1273 06:53:13.406232 == TX Byte 1 ==
1274 06:53:13.409480 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1275 06:53:13.413355 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1276 06:53:13.413920 ==
1277 06:53:13.416400 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 06:53:13.419592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 06:53:13.422898 ==
1280 06:53:13.434289 TX Vref=22, minBit 8, minWin=27, winSum=443
1281 06:53:13.437518 TX Vref=24, minBit 13, minWin=27, winSum=447
1282 06:53:13.440862 TX Vref=26, minBit 1, minWin=28, winSum=452
1283 06:53:13.444314 TX Vref=28, minBit 1, minWin=28, winSum=452
1284 06:53:13.447702 TX Vref=30, minBit 1, minWin=28, winSum=453
1285 06:53:13.454447 TX Vref=32, minBit 1, minWin=28, winSum=456
1286 06:53:13.458035 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 32
1287 06:53:13.458594
1288 06:53:13.461338 Final TX Range 1 Vref 32
1289 06:53:13.461900
1290 06:53:13.462327 ==
1291 06:53:13.464329 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 06:53:13.467786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 06:53:13.468245 ==
1294 06:53:13.468602
1295 06:53:13.471019
1296 06:53:13.471470 TX Vref Scan disable
1297 06:53:13.474039 == TX Byte 0 ==
1298 06:53:13.477230 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1299 06:53:13.484147 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1300 06:53:13.484599 == TX Byte 1 ==
1301 06:53:13.487301 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1302 06:53:13.494075 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1303 06:53:13.494557
1304 06:53:13.494913 [DATLAT]
1305 06:53:13.495245 Freq=800, CH0 RK1
1306 06:53:13.495573
1307 06:53:13.497373 DATLAT Default: 0xa
1308 06:53:13.497822 0, 0xFFFF, sum = 0
1309 06:53:13.500702 1, 0xFFFF, sum = 0
1310 06:53:13.501159 2, 0xFFFF, sum = 0
1311 06:53:13.504235 3, 0xFFFF, sum = 0
1312 06:53:13.504901 4, 0xFFFF, sum = 0
1313 06:53:13.507143 5, 0xFFFF, sum = 0
1314 06:53:13.510641 6, 0xFFFF, sum = 0
1315 06:53:13.511111 7, 0xFFFF, sum = 0
1316 06:53:13.514091 8, 0xFFFF, sum = 0
1317 06:53:13.514505 9, 0x0, sum = 1
1318 06:53:13.514836 10, 0x0, sum = 2
1319 06:53:13.517425 11, 0x0, sum = 3
1320 06:53:13.517843 12, 0x0, sum = 4
1321 06:53:13.520603 best_step = 10
1322 06:53:13.521008
1323 06:53:13.521327 ==
1324 06:53:13.524137 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 06:53:13.527392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 06:53:13.527856 ==
1327 06:53:13.530683 RX Vref Scan: 0
1328 06:53:13.531089
1329 06:53:13.531413 RX Vref 0 -> 0, step: 1
1330 06:53:13.531909
1331 06:53:13.533915 RX Delay -95 -> 252, step: 8
1332 06:53:13.540902 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1333 06:53:13.544450 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1334 06:53:13.547672 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1335 06:53:13.551200 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1336 06:53:13.554526 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1337 06:53:13.560942 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1338 06:53:13.564320 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1339 06:53:13.568036 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1340 06:53:13.571381 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1341 06:53:13.574456 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1342 06:53:13.581197 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1343 06:53:13.584437 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1344 06:53:13.587940 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1345 06:53:13.591202 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1346 06:53:13.594312 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1347 06:53:13.601333 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1348 06:53:13.601894 ==
1349 06:53:13.604654 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 06:53:13.607984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 06:53:13.608543 ==
1352 06:53:13.608909 DQS Delay:
1353 06:53:13.611388 DQS0 = 0, DQS1 = 0
1354 06:53:13.611839 DQM Delay:
1355 06:53:13.614257 DQM0 = 91, DQM1 = 83
1356 06:53:13.614708 DQ Delay:
1357 06:53:13.617900 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =84
1358 06:53:13.621287 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1359 06:53:13.624609 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1360 06:53:13.627717 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1361 06:53:13.628171
1362 06:53:13.628528
1363 06:53:13.634734 [DQSOSCAuto] RK1, (LSB)MR18= 0x421c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1364 06:53:13.638026 CH0 RK1: MR19=606, MR18=421C
1365 06:53:13.644714 CH0_RK1: MR19=0x606, MR18=0x421C, DQSOSC=393, MR23=63, INC=95, DEC=63
1366 06:53:13.648149 [RxdqsGatingPostProcess] freq 800
1367 06:53:13.654775 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1368 06:53:13.655342 Pre-setting of DQS Precalculation
1369 06:53:13.661823 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1370 06:53:13.662416 ==
1371 06:53:13.664967 Dram Type= 6, Freq= 0, CH_1, rank 0
1372 06:53:13.668275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 06:53:13.668832 ==
1374 06:53:13.675403 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1375 06:53:13.681592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1376 06:53:13.689584 [CA 0] Center 36 (6~67) winsize 62
1377 06:53:13.692887 [CA 1] Center 36 (6~67) winsize 62
1378 06:53:13.696489 [CA 2] Center 34 (4~65) winsize 62
1379 06:53:13.699532 [CA 3] Center 34 (3~65) winsize 63
1380 06:53:13.702712 [CA 4] Center 34 (4~65) winsize 62
1381 06:53:13.706294 [CA 5] Center 33 (3~64) winsize 62
1382 06:53:13.706867
1383 06:53:13.709173 [CmdBusTrainingLP45] Vref(ca) range 1: 28
1384 06:53:13.709636
1385 06:53:13.712990 [CATrainingPosCal] consider 1 rank data
1386 06:53:13.716340 u2DelayCellTimex100 = 270/100 ps
1387 06:53:13.719511 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1388 06:53:13.722997 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1389 06:53:13.729303 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1390 06:53:13.732617 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1391 06:53:13.735917 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1392 06:53:13.739403 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1393 06:53:13.739885
1394 06:53:13.742949 CA PerBit enable=1, Macro0, CA PI delay=33
1395 06:53:13.743536
1396 06:53:13.746396 [CBTSetCACLKResult] CA Dly = 33
1397 06:53:13.746967 CS Dly: 5 (0~36)
1398 06:53:13.747353 ==
1399 06:53:13.750048 Dram Type= 6, Freq= 0, CH_1, rank 1
1400 06:53:13.756107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 06:53:13.756683 ==
1402 06:53:13.759627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1403 06:53:13.766198 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1404 06:53:13.775792 [CA 0] Center 36 (6~67) winsize 62
1405 06:53:13.779003 [CA 1] Center 36 (6~67) winsize 62
1406 06:53:13.782166 [CA 2] Center 35 (5~66) winsize 62
1407 06:53:13.785674 [CA 3] Center 34 (4~65) winsize 62
1408 06:53:13.789105 [CA 4] Center 34 (4~65) winsize 62
1409 06:53:13.792116 [CA 5] Center 33 (3~64) winsize 62
1410 06:53:13.792687
1411 06:53:13.795609 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1412 06:53:13.796180
1413 06:53:13.798650 [CATrainingPosCal] consider 2 rank data
1414 06:53:13.802548 u2DelayCellTimex100 = 270/100 ps
1415 06:53:13.805484 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1416 06:53:13.809007 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1417 06:53:13.815876 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1418 06:53:13.818904 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1419 06:53:13.822457 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1420 06:53:13.825823 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1421 06:53:13.826447
1422 06:53:13.829463 CA PerBit enable=1, Macro0, CA PI delay=33
1423 06:53:13.829927
1424 06:53:13.832999 [CBTSetCACLKResult] CA Dly = 33
1425 06:53:13.833569 CS Dly: 6 (0~38)
1426 06:53:13.833996
1427 06:53:13.836848 ----->DramcWriteLeveling(PI) begin...
1428 06:53:13.837359 ==
1429 06:53:13.840219 Dram Type= 6, Freq= 0, CH_1, rank 0
1430 06:53:13.843975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1431 06:53:13.844483 ==
1432 06:53:13.847743 Write leveling (Byte 0): 28 => 28
1433 06:53:13.851452 Write leveling (Byte 1): 28 => 28
1434 06:53:13.855427 DramcWriteLeveling(PI) end<-----
1435 06:53:13.856005
1436 06:53:13.856380 ==
1437 06:53:13.858501 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 06:53:13.861913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 06:53:13.862411 ==
1440 06:53:13.865438 [Gating] SW mode calibration
1441 06:53:13.872551 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1442 06:53:13.875515 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1443 06:53:13.882324 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1444 06:53:13.885913 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1445 06:53:13.888985 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 06:53:13.895831 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 06:53:13.899017 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 06:53:13.902261 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 06:53:13.909020 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 06:53:13.912375 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 06:53:13.915414 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 06:53:13.922576 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 06:53:13.925738 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 06:53:13.929492 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 06:53:13.935966 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 06:53:13.939351 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 06:53:13.942727 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 06:53:13.949249 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 06:53:13.952248 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1460 06:53:13.955579 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1461 06:53:13.959035 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 06:53:13.965650 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 06:53:13.968830 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 06:53:13.972431 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 06:53:13.978822 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 06:53:13.982532 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 06:53:13.985744 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 06:53:13.992243 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1469 06:53:13.995314 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1470 06:53:13.999098 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 06:53:14.005614 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 06:53:14.008909 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 06:53:14.012502 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 06:53:14.018962 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 06:53:14.022309 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1476 06:53:14.025789 0 10 4 | B1->B0 | 2828 2727 | 0 0 | (1 0) (0 0)
1477 06:53:14.032205 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 06:53:14.035292 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 06:53:14.038500 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 06:53:14.045598 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 06:53:14.048621 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 06:53:14.052179 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 06:53:14.055303 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 06:53:14.062463 0 11 4 | B1->B0 | 3131 3535 | 0 0 | (0 0) (0 0)
1485 06:53:14.065716 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 06:53:14.068978 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 06:53:14.075617 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 06:53:14.078775 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 06:53:14.082701 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 06:53:14.088921 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 06:53:14.092405 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1492 06:53:14.095768 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1493 06:53:14.102634 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1494 06:53:14.105803 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 06:53:14.109209 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 06:53:14.116090 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 06:53:14.119011 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 06:53:14.122832 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 06:53:14.126035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 06:53:14.132625 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 06:53:14.136030 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 06:53:14.139262 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 06:53:14.146379 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 06:53:14.149499 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 06:53:14.152611 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 06:53:14.159166 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 06:53:14.162652 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1508 06:53:14.166054 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1509 06:53:14.172556 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 06:53:14.173118 Total UI for P1: 0, mck2ui 16
1511 06:53:14.179846 best dqsien dly found for B0: ( 0, 14, 2)
1512 06:53:14.180408 Total UI for P1: 0, mck2ui 16
1513 06:53:14.183148 best dqsien dly found for B1: ( 0, 14, 4)
1514 06:53:14.189731 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1515 06:53:14.192721 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1516 06:53:14.193188
1517 06:53:14.196216 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1518 06:53:14.199677 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1519 06:53:14.202825 [Gating] SW calibration Done
1520 06:53:14.203302 ==
1521 06:53:14.206689 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 06:53:14.209614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 06:53:14.210123 ==
1524 06:53:14.210505 RX Vref Scan: 0
1525 06:53:14.210853
1526 06:53:14.212752 RX Vref 0 -> 0, step: 1
1527 06:53:14.213214
1528 06:53:14.216381 RX Delay -130 -> 252, step: 16
1529 06:53:14.219591 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1530 06:53:14.223204 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1531 06:53:14.230003 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1532 06:53:14.233224 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1533 06:53:14.236752 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1534 06:53:14.240009 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1535 06:53:14.243265 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1536 06:53:14.250041 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1537 06:53:14.253308 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1538 06:53:14.256505 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1539 06:53:14.259747 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1540 06:53:14.263421 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1541 06:53:14.269868 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1542 06:53:14.273091 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1543 06:53:14.276429 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1544 06:53:14.279869 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1545 06:53:14.280337 ==
1546 06:53:14.282898 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 06:53:14.289646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1548 06:53:14.290237 ==
1549 06:53:14.290617 DQS Delay:
1550 06:53:14.290964 DQS0 = 0, DQS1 = 0
1551 06:53:14.292971 DQM Delay:
1552 06:53:14.293430 DQM0 = 91, DQM1 = 86
1553 06:53:14.296118 DQ Delay:
1554 06:53:14.299536 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1555 06:53:14.303409 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93
1556 06:53:14.303974 DQ8 =69, DQ9 =77, DQ10 =93, DQ11 =77
1557 06:53:14.309605 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1558 06:53:14.310214
1559 06:53:14.310593
1560 06:53:14.310940 ==
1561 06:53:14.313026 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 06:53:14.316628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 06:53:14.317209 ==
1564 06:53:14.317589
1565 06:53:14.317934
1566 06:53:14.319528 TX Vref Scan disable
1567 06:53:14.319990 == TX Byte 0 ==
1568 06:53:14.326735 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1569 06:53:14.329563 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1570 06:53:14.330291 == TX Byte 1 ==
1571 06:53:14.336616 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1572 06:53:14.339878 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1573 06:53:14.340452 ==
1574 06:53:14.342782 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 06:53:14.346321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 06:53:14.346890 ==
1577 06:53:14.360044 TX Vref=22, minBit 8, minWin=27, winSum=448
1578 06:53:14.363336 TX Vref=24, minBit 8, minWin=27, winSum=449
1579 06:53:14.367047 TX Vref=26, minBit 15, minWin=27, winSum=454
1580 06:53:14.370054 TX Vref=28, minBit 15, minWin=27, winSum=458
1581 06:53:14.373288 TX Vref=30, minBit 8, minWin=28, winSum=458
1582 06:53:14.376968 TX Vref=32, minBit 9, minWin=27, winSum=455
1583 06:53:14.383242 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
1584 06:53:14.383830
1585 06:53:14.386564 Final TX Range 1 Vref 30
1586 06:53:14.387128
1587 06:53:14.387498 ==
1588 06:53:14.390233 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 06:53:14.393520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 06:53:14.394121 ==
1591 06:53:14.394496
1592 06:53:14.396766
1593 06:53:14.397280 TX Vref Scan disable
1594 06:53:14.399781 == TX Byte 0 ==
1595 06:53:14.403799 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1596 06:53:14.407220 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1597 06:53:14.410699 == TX Byte 1 ==
1598 06:53:14.413904 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1599 06:53:14.417633 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1600 06:53:14.418285
1601 06:53:14.420709 [DATLAT]
1602 06:53:14.421270 Freq=800, CH1 RK0
1603 06:53:14.421759
1604 06:53:14.424076 DATLAT Default: 0xa
1605 06:53:14.424647 0, 0xFFFF, sum = 0
1606 06:53:14.427120 1, 0xFFFF, sum = 0
1607 06:53:14.427594 2, 0xFFFF, sum = 0
1608 06:53:14.430694 3, 0xFFFF, sum = 0
1609 06:53:14.431163 4, 0xFFFF, sum = 0
1610 06:53:14.433794 5, 0xFFFF, sum = 0
1611 06:53:14.434312 6, 0xFFFF, sum = 0
1612 06:53:14.437383 7, 0xFFFF, sum = 0
1613 06:53:14.437853 8, 0xFFFF, sum = 0
1614 06:53:14.440832 9, 0x0, sum = 1
1615 06:53:14.441401 10, 0x0, sum = 2
1616 06:53:14.443985 11, 0x0, sum = 3
1617 06:53:14.444553 12, 0x0, sum = 4
1618 06:53:14.447765 best_step = 10
1619 06:53:14.448324
1620 06:53:14.448691 ==
1621 06:53:14.450569 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 06:53:14.454179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 06:53:14.454749 ==
1624 06:53:14.455119 RX Vref Scan: 1
1625 06:53:14.455461
1626 06:53:14.457640 Set Vref Range= 32 -> 127
1627 06:53:14.458267
1628 06:53:14.460879 RX Vref 32 -> 127, step: 1
1629 06:53:14.461443
1630 06:53:14.463817 RX Delay -95 -> 252, step: 8
1631 06:53:14.464280
1632 06:53:14.467116 Set Vref, RX VrefLevel [Byte0]: 32
1633 06:53:14.470739 [Byte1]: 32
1634 06:53:14.471304
1635 06:53:14.474309 Set Vref, RX VrefLevel [Byte0]: 33
1636 06:53:14.477840 [Byte1]: 33
1637 06:53:14.478451
1638 06:53:14.480352 Set Vref, RX VrefLevel [Byte0]: 34
1639 06:53:14.483809 [Byte1]: 34
1640 06:53:14.487722
1641 06:53:14.488189 Set Vref, RX VrefLevel [Byte0]: 35
1642 06:53:14.491150 [Byte1]: 35
1643 06:53:14.495211
1644 06:53:14.495767 Set Vref, RX VrefLevel [Byte0]: 36
1645 06:53:14.498770 [Byte1]: 36
1646 06:53:14.503174
1647 06:53:14.503642 Set Vref, RX VrefLevel [Byte0]: 37
1648 06:53:14.506384 [Byte1]: 37
1649 06:53:14.510480
1650 06:53:14.511062 Set Vref, RX VrefLevel [Byte0]: 38
1651 06:53:14.513653 [Byte1]: 38
1652 06:53:14.518340
1653 06:53:14.518908 Set Vref, RX VrefLevel [Byte0]: 39
1654 06:53:14.521543 [Byte1]: 39
1655 06:53:14.525665
1656 06:53:14.526171 Set Vref, RX VrefLevel [Byte0]: 40
1657 06:53:14.528958 [Byte1]: 40
1658 06:53:14.533208
1659 06:53:14.533676 Set Vref, RX VrefLevel [Byte0]: 41
1660 06:53:14.536416 [Byte1]: 41
1661 06:53:14.540739
1662 06:53:14.541204 Set Vref, RX VrefLevel [Byte0]: 42
1663 06:53:14.544245 [Byte1]: 42
1664 06:53:14.548357
1665 06:53:14.548824 Set Vref, RX VrefLevel [Byte0]: 43
1666 06:53:14.552233 [Byte1]: 43
1667 06:53:14.556386
1668 06:53:14.556959 Set Vref, RX VrefLevel [Byte0]: 44
1669 06:53:14.559724 [Byte1]: 44
1670 06:53:14.563942
1671 06:53:14.564513 Set Vref, RX VrefLevel [Byte0]: 45
1672 06:53:14.567056 [Byte1]: 45
1673 06:53:14.571807
1674 06:53:14.572375 Set Vref, RX VrefLevel [Byte0]: 46
1675 06:53:14.575075 [Byte1]: 46
1676 06:53:14.578962
1677 06:53:14.579539 Set Vref, RX VrefLevel [Byte0]: 47
1678 06:53:14.582514 [Byte1]: 47
1679 06:53:14.586566
1680 06:53:14.587135 Set Vref, RX VrefLevel [Byte0]: 48
1681 06:53:14.589783 [Byte1]: 48
1682 06:53:14.594072
1683 06:53:14.594680 Set Vref, RX VrefLevel [Byte0]: 49
1684 06:53:14.597775 [Byte1]: 49
1685 06:53:14.601795
1686 06:53:14.602423 Set Vref, RX VrefLevel [Byte0]: 50
1687 06:53:14.605030 [Byte1]: 50
1688 06:53:14.609232
1689 06:53:14.609807 Set Vref, RX VrefLevel [Byte0]: 51
1690 06:53:14.612425 [Byte1]: 51
1691 06:53:14.616891
1692 06:53:14.617464 Set Vref, RX VrefLevel [Byte0]: 52
1693 06:53:14.620202 [Byte1]: 52
1694 06:53:14.624613
1695 06:53:14.625354 Set Vref, RX VrefLevel [Byte0]: 53
1696 06:53:14.627947 [Byte1]: 53
1697 06:53:14.631987
1698 06:53:14.632549 Set Vref, RX VrefLevel [Byte0]: 54
1699 06:53:14.635258 [Byte1]: 54
1700 06:53:14.639783
1701 06:53:14.640249 Set Vref, RX VrefLevel [Byte0]: 55
1702 06:53:14.643136 [Byte1]: 55
1703 06:53:14.647344
1704 06:53:14.647919 Set Vref, RX VrefLevel [Byte0]: 56
1705 06:53:14.650870 [Byte1]: 56
1706 06:53:14.655115
1707 06:53:14.655676 Set Vref, RX VrefLevel [Byte0]: 57
1708 06:53:14.658364 [Byte1]: 57
1709 06:53:14.662775
1710 06:53:14.663343 Set Vref, RX VrefLevel [Byte0]: 58
1711 06:53:14.666250 [Byte1]: 58
1712 06:53:14.670325
1713 06:53:14.670887 Set Vref, RX VrefLevel [Byte0]: 59
1714 06:53:14.673307 [Byte1]: 59
1715 06:53:14.677879
1716 06:53:14.678498 Set Vref, RX VrefLevel [Byte0]: 60
1717 06:53:14.681122 [Byte1]: 60
1718 06:53:14.685518
1719 06:53:14.686126 Set Vref, RX VrefLevel [Byte0]: 61
1720 06:53:14.689033 [Byte1]: 61
1721 06:53:14.692920
1722 06:53:14.693459 Set Vref, RX VrefLevel [Byte0]: 62
1723 06:53:14.696048 [Byte1]: 62
1724 06:53:14.700195
1725 06:53:14.700664 Set Vref, RX VrefLevel [Byte0]: 63
1726 06:53:14.704151 [Byte1]: 63
1727 06:53:14.708081
1728 06:53:14.708664 Set Vref, RX VrefLevel [Byte0]: 64
1729 06:53:14.711528 [Byte1]: 64
1730 06:53:14.715407
1731 06:53:14.715874 Set Vref, RX VrefLevel [Byte0]: 65
1732 06:53:14.718689 [Byte1]: 65
1733 06:53:14.723434
1734 06:53:14.724008 Set Vref, RX VrefLevel [Byte0]: 66
1735 06:53:14.726425 [Byte1]: 66
1736 06:53:14.730941
1737 06:53:14.731507 Set Vref, RX VrefLevel [Byte0]: 67
1738 06:53:14.734072 [Byte1]: 67
1739 06:53:14.738574
1740 06:53:14.739043 Set Vref, RX VrefLevel [Byte0]: 68
1741 06:53:14.741431 [Byte1]: 68
1742 06:53:14.746216
1743 06:53:14.746783 Set Vref, RX VrefLevel [Byte0]: 69
1744 06:53:14.749206 [Byte1]: 69
1745 06:53:14.754031
1746 06:53:14.754595 Set Vref, RX VrefLevel [Byte0]: 70
1747 06:53:14.756988 [Byte1]: 70
1748 06:53:14.760972
1749 06:53:14.761442 Set Vref, RX VrefLevel [Byte0]: 71
1750 06:53:14.764631 [Byte1]: 71
1751 06:53:14.769018
1752 06:53:14.769652 Set Vref, RX VrefLevel [Byte0]: 72
1753 06:53:14.772191 [Byte1]: 72
1754 06:53:14.776705
1755 06:53:14.777268 Set Vref, RX VrefLevel [Byte0]: 73
1756 06:53:14.779875 [Byte1]: 73
1757 06:53:14.784084
1758 06:53:14.784648 Set Vref, RX VrefLevel [Byte0]: 74
1759 06:53:14.787440 [Byte1]: 74
1760 06:53:14.791943
1761 06:53:14.792513 Set Vref, RX VrefLevel [Byte0]: 75
1762 06:53:14.794831 [Byte1]: 75
1763 06:53:14.799236
1764 06:53:14.799799 Set Vref, RX VrefLevel [Byte0]: 76
1765 06:53:14.802489 [Byte1]: 76
1766 06:53:14.806845
1767 06:53:14.807406 Set Vref, RX VrefLevel [Byte0]: 77
1768 06:53:14.810198 [Byte1]: 77
1769 06:53:14.814506
1770 06:53:14.815065 Set Vref, RX VrefLevel [Byte0]: 78
1771 06:53:14.817466 [Byte1]: 78
1772 06:53:14.822114
1773 06:53:14.822697 Set Vref, RX VrefLevel [Byte0]: 79
1774 06:53:14.825299 [Byte1]: 79
1775 06:53:14.829728
1776 06:53:14.830376 Final RX Vref Byte 0 = 51 to rank0
1777 06:53:14.833089 Final RX Vref Byte 1 = 60 to rank0
1778 06:53:14.836741 Final RX Vref Byte 0 = 51 to rank1
1779 06:53:14.839736 Final RX Vref Byte 1 = 60 to rank1==
1780 06:53:14.842925 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 06:53:14.850016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 06:53:14.850601 ==
1783 06:53:14.850981 DQS Delay:
1784 06:53:14.851329 DQS0 = 0, DQS1 = 0
1785 06:53:14.853196 DQM Delay:
1786 06:53:14.853764 DQM0 = 93, DQM1 = 82
1787 06:53:14.856902 DQ Delay:
1788 06:53:14.857479 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1789 06:53:14.860021 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1790 06:53:14.863198 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1791 06:53:14.866857 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1792 06:53:14.870040
1793 06:53:14.870611
1794 06:53:14.876967 [DQSOSCAuto] RK0, (LSB)MR18= 0x3350, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1795 06:53:14.880333 CH1 RK0: MR19=606, MR18=3350
1796 06:53:14.886978 CH1_RK0: MR19=0x606, MR18=0x3350, DQSOSC=389, MR23=63, INC=97, DEC=65
1797 06:53:14.887555
1798 06:53:14.890330 ----->DramcWriteLeveling(PI) begin...
1799 06:53:14.890910 ==
1800 06:53:14.893447 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 06:53:14.896893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 06:53:14.897468 ==
1803 06:53:14.900248 Write leveling (Byte 0): 28 => 28
1804 06:53:14.903579 Write leveling (Byte 1): 31 => 31
1805 06:53:14.906694 DramcWriteLeveling(PI) end<-----
1806 06:53:14.907281
1807 06:53:14.907659 ==
1808 06:53:14.909723 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 06:53:14.913543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 06:53:14.914160 ==
1811 06:53:14.916877 [Gating] SW mode calibration
1812 06:53:14.923276 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 06:53:14.930012 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 06:53:14.933636 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1815 06:53:14.937140 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1816 06:53:14.943470 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 06:53:14.946495 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 06:53:14.950512 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 06:53:14.956556 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 06:53:14.960210 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 06:53:14.963178 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 06:53:14.966761 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 06:53:14.974100 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 06:53:14.976851 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 06:53:14.980468 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 06:53:14.986972 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 06:53:14.989970 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 06:53:14.993726 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 06:53:15.000582 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 06:53:15.003626 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1831 06:53:15.006835 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1832 06:53:15.013617 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 06:53:15.016974 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 06:53:15.020150 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 06:53:15.026910 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 06:53:15.030606 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 06:53:15.033754 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 06:53:15.040230 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 06:53:15.043313 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 06:53:15.046689 0 9 8 | B1->B0 | 3131 3232 | 1 0 | (1 1) (0 0)
1841 06:53:15.050495 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 06:53:15.056677 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 06:53:15.060252 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 06:53:15.063589 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 06:53:15.069882 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 06:53:15.073832 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
1847 06:53:15.077186 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
1848 06:53:15.083767 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 06:53:15.087090 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 06:53:15.090133 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 06:53:15.096485 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 06:53:15.100021 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 06:53:15.103616 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 06:53:15.110375 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 06:53:15.113419 0 11 4 | B1->B0 | 3030 3030 | 1 1 | (0 0) (0 0)
1856 06:53:15.116440 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 06:53:15.123419 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 06:53:15.126917 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 06:53:15.129890 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 06:53:15.137140 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 06:53:15.140185 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 06:53:15.143317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 06:53:15.147067 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1864 06:53:15.153581 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 06:53:15.157182 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 06:53:15.160374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 06:53:15.167161 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 06:53:15.170602 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 06:53:15.174244 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 06:53:15.180580 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 06:53:15.183858 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 06:53:15.187209 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 06:53:15.193934 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 06:53:15.197330 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 06:53:15.200654 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 06:53:15.207345 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 06:53:15.210864 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 06:53:15.213697 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 06:53:15.217595 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1880 06:53:15.224244 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1881 06:53:15.227405 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 06:53:15.230251 Total UI for P1: 0, mck2ui 16
1883 06:53:15.233732 best dqsien dly found for B0: ( 0, 14, 6)
1884 06:53:15.237201 Total UI for P1: 0, mck2ui 16
1885 06:53:15.240617 best dqsien dly found for B1: ( 0, 14, 6)
1886 06:53:15.243732 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1887 06:53:15.247261 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1888 06:53:15.247834
1889 06:53:15.250781 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1890 06:53:15.253463 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1891 06:53:15.257217 [Gating] SW calibration Done
1892 06:53:15.257789 ==
1893 06:53:15.260235 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 06:53:15.263758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 06:53:15.266824 ==
1896 06:53:15.267293 RX Vref Scan: 0
1897 06:53:15.267669
1898 06:53:15.270143 RX Vref 0 -> 0, step: 1
1899 06:53:15.270634
1900 06:53:15.273805 RX Delay -130 -> 252, step: 16
1901 06:53:15.276801 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1902 06:53:15.280279 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1903 06:53:15.283596 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1904 06:53:15.286940 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1905 06:53:15.294043 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1906 06:53:15.297049 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1907 06:53:15.300391 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1908 06:53:15.304042 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1909 06:53:15.307330 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1910 06:53:15.310847 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1911 06:53:15.317130 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1912 06:53:15.320692 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1913 06:53:15.323931 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1914 06:53:15.327323 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1915 06:53:15.333529 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1916 06:53:15.336981 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1917 06:53:15.337064 ==
1918 06:53:15.340427 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 06:53:15.343624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 06:53:15.343708 ==
1921 06:53:15.343791 DQS Delay:
1922 06:53:15.346911 DQS0 = 0, DQS1 = 0
1923 06:53:15.347048 DQM Delay:
1924 06:53:15.350162 DQM0 = 89, DQM1 = 81
1925 06:53:15.350246 DQ Delay:
1926 06:53:15.354205 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1927 06:53:15.357083 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1928 06:53:15.360476 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1929 06:53:15.363879 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1930 06:53:15.363962
1931 06:53:15.364027
1932 06:53:15.364088 ==
1933 06:53:15.367038 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 06:53:15.370279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 06:53:15.370368 ==
1936 06:53:15.373810
1937 06:53:15.373898
1938 06:53:15.373984 TX Vref Scan disable
1939 06:53:15.377153 == TX Byte 0 ==
1940 06:53:15.380358 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1941 06:53:15.383584 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1942 06:53:15.386951 == TX Byte 1 ==
1943 06:53:15.390470 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1944 06:53:15.393951 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1945 06:53:15.394047 ==
1946 06:53:15.397220 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 06:53:15.403751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 06:53:15.403838 ==
1949 06:53:15.415825 TX Vref=22, minBit 9, minWin=27, winSum=449
1950 06:53:15.419178 TX Vref=24, minBit 13, minWin=27, winSum=454
1951 06:53:15.422169 TX Vref=26, minBit 9, minWin=27, winSum=455
1952 06:53:15.425809 TX Vref=28, minBit 8, minWin=28, winSum=461
1953 06:53:15.428815 TX Vref=30, minBit 13, minWin=27, winSum=456
1954 06:53:15.435878 TX Vref=32, minBit 8, minWin=28, winSum=457
1955 06:53:15.438751 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 28
1956 06:53:15.438827
1957 06:53:15.442419 Final TX Range 1 Vref 28
1958 06:53:15.442518
1959 06:53:15.442608 ==
1960 06:53:15.445520 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 06:53:15.448966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 06:53:15.449040 ==
1963 06:53:15.452154
1964 06:53:15.452250
1965 06:53:15.452339 TX Vref Scan disable
1966 06:53:15.455628 == TX Byte 0 ==
1967 06:53:15.459249 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1968 06:53:15.462301 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1969 06:53:15.465536 == TX Byte 1 ==
1970 06:53:15.468863 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1971 06:53:15.472468 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1972 06:53:15.475655
1973 06:53:15.475742 [DATLAT]
1974 06:53:15.475811 Freq=800, CH1 RK1
1975 06:53:15.475875
1976 06:53:15.479164 DATLAT Default: 0xa
1977 06:53:15.479251 0, 0xFFFF, sum = 0
1978 06:53:15.482572 1, 0xFFFF, sum = 0
1979 06:53:15.482742 2, 0xFFFF, sum = 0
1980 06:53:15.486232 3, 0xFFFF, sum = 0
1981 06:53:15.486411 4, 0xFFFF, sum = 0
1982 06:53:15.489177 5, 0xFFFF, sum = 0
1983 06:53:15.489353 6, 0xFFFF, sum = 0
1984 06:53:15.492677 7, 0xFFFF, sum = 0
1985 06:53:15.492825 8, 0xFFFF, sum = 0
1986 06:53:15.496085 9, 0x0, sum = 1
1987 06:53:15.496246 10, 0x0, sum = 2
1988 06:53:15.499373 11, 0x0, sum = 3
1989 06:53:15.499541 12, 0x0, sum = 4
1990 06:53:15.502978 best_step = 10
1991 06:53:15.503102
1992 06:53:15.503206 ==
1993 06:53:15.505904 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 06:53:15.509185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 06:53:15.509337 ==
1996 06:53:15.512771 RX Vref Scan: 0
1997 06:53:15.512942
1998 06:53:15.513079 RX Vref 0 -> 0, step: 1
1999 06:53:15.513208
2000 06:53:15.516105 RX Delay -95 -> 252, step: 8
2001 06:53:15.522950 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2002 06:53:15.526317 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2003 06:53:15.530000 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2004 06:53:15.533017 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2005 06:53:15.536181 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2006 06:53:15.539490 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2007 06:53:15.546202 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2008 06:53:15.549814 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2009 06:53:15.552882 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2010 06:53:15.556242 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2011 06:53:15.559400 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2012 06:53:15.566211 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2013 06:53:15.569642 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2014 06:53:15.572800 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2015 06:53:15.576422 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2016 06:53:15.583109 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2017 06:53:15.583566 ==
2018 06:53:15.586022 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 06:53:15.589537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 06:53:15.590001 ==
2021 06:53:15.590345 DQS Delay:
2022 06:53:15.592991 DQS0 = 0, DQS1 = 0
2023 06:53:15.593411 DQM Delay:
2024 06:53:15.596146 DQM0 = 90, DQM1 = 83
2025 06:53:15.596568 DQ Delay:
2026 06:53:15.599719 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2027 06:53:15.603091 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2028 06:53:15.606591 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2029 06:53:15.609836 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =96
2030 06:53:15.610316
2031 06:53:15.610688
2032 06:53:15.616471 [DQSOSCAuto] RK1, (LSB)MR18= 0x350b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
2033 06:53:15.619711 CH1 RK1: MR19=606, MR18=350B
2034 06:53:15.626231 CH1_RK1: MR19=0x606, MR18=0x350B, DQSOSC=396, MR23=63, INC=94, DEC=62
2035 06:53:15.629738 [RxdqsGatingPostProcess] freq 800
2036 06:53:15.636446 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2037 06:53:15.636901 Pre-setting of DQS Precalculation
2038 06:53:15.643169 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2039 06:53:15.649569 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2040 06:53:15.656571 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2041 06:53:15.657028
2042 06:53:15.657400
2043 06:53:15.659814 [Calibration Summary] 1600 Mbps
2044 06:53:15.662901 CH 0, Rank 0
2045 06:53:15.663331 SW Impedance : PASS
2046 06:53:15.666325 DUTY Scan : NO K
2047 06:53:15.666758 ZQ Calibration : PASS
2048 06:53:15.669559 Jitter Meter : NO K
2049 06:53:15.672904 CBT Training : PASS
2050 06:53:15.673331 Write leveling : PASS
2051 06:53:15.676349 RX DQS gating : PASS
2052 06:53:15.679879 RX DQ/DQS(RDDQC) : PASS
2053 06:53:15.680307 TX DQ/DQS : PASS
2054 06:53:15.683171 RX DATLAT : PASS
2055 06:53:15.686582 RX DQ/DQS(Engine): PASS
2056 06:53:15.687009 TX OE : NO K
2057 06:53:15.689873 All Pass.
2058 06:53:15.690205
2059 06:53:15.690451 CH 0, Rank 1
2060 06:53:15.693084 SW Impedance : PASS
2061 06:53:15.693389 DUTY Scan : NO K
2062 06:53:15.696304 ZQ Calibration : PASS
2063 06:53:15.699341 Jitter Meter : NO K
2064 06:53:15.699570 CBT Training : PASS
2065 06:53:15.702876 Write leveling : PASS
2066 06:53:15.706388 RX DQS gating : PASS
2067 06:53:15.706618 RX DQ/DQS(RDDQC) : PASS
2068 06:53:15.709507 TX DQ/DQS : PASS
2069 06:53:15.709739 RX DATLAT : PASS
2070 06:53:15.712664 RX DQ/DQS(Engine): PASS
2071 06:53:15.716146 TX OE : NO K
2072 06:53:15.716375 All Pass.
2073 06:53:15.716561
2074 06:53:15.716729 CH 1, Rank 0
2075 06:53:15.719385 SW Impedance : PASS
2076 06:53:15.723216 DUTY Scan : NO K
2077 06:53:15.723299 ZQ Calibration : PASS
2078 06:53:15.726095 Jitter Meter : NO K
2079 06:53:15.729817 CBT Training : PASS
2080 06:53:15.730001 Write leveling : PASS
2081 06:53:15.733334 RX DQS gating : PASS
2082 06:53:15.736657 RX DQ/DQS(RDDQC) : PASS
2083 06:53:15.736835 TX DQ/DQS : PASS
2084 06:53:15.739626 RX DATLAT : PASS
2085 06:53:15.743192 RX DQ/DQS(Engine): PASS
2086 06:53:15.743380 TX OE : NO K
2087 06:53:15.743471 All Pass.
2088 06:53:15.743554
2089 06:53:15.746677 CH 1, Rank 1
2090 06:53:15.746869 SW Impedance : PASS
2091 06:53:15.750157 DUTY Scan : NO K
2092 06:53:15.753403 ZQ Calibration : PASS
2093 06:53:15.753608 Jitter Meter : NO K
2094 06:53:15.756448 CBT Training : PASS
2095 06:53:15.759668 Write leveling : PASS
2096 06:53:15.759944 RX DQS gating : PASS
2097 06:53:15.762996 RX DQ/DQS(RDDQC) : PASS
2098 06:53:15.766251 TX DQ/DQS : PASS
2099 06:53:15.766428 RX DATLAT : PASS
2100 06:53:15.769470 RX DQ/DQS(Engine): PASS
2101 06:53:15.773069 TX OE : NO K
2102 06:53:15.773362 All Pass.
2103 06:53:15.773540
2104 06:53:15.776575 DramC Write-DBI off
2105 06:53:15.776911 PER_BANK_REFRESH: Hybrid Mode
2106 06:53:15.779459 TX_TRACKING: ON
2107 06:53:15.783337 [GetDramInforAfterCalByMRR] Vendor 6.
2108 06:53:15.786521 [GetDramInforAfterCalByMRR] Revision 606.
2109 06:53:15.790227 [GetDramInforAfterCalByMRR] Revision 2 0.
2110 06:53:15.790800 MR0 0x3b3b
2111 06:53:15.793148 MR8 0x5151
2112 06:53:15.796990 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 06:53:15.797561
2114 06:53:15.797936 MR0 0x3b3b
2115 06:53:15.798359 MR8 0x5151
2116 06:53:15.803317 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 06:53:15.803789
2118 06:53:15.810309 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2119 06:53:15.813400 [FAST_K] Save calibration result to emmc
2120 06:53:15.816566 [FAST_K] Save calibration result to emmc
2121 06:53:15.820340 dram_init: config_dvfs: 1
2122 06:53:15.823270 dramc_set_vcore_voltage set vcore to 662500
2123 06:53:15.826653 Read voltage for 1200, 2
2124 06:53:15.827218 Vio18 = 0
2125 06:53:15.830343 Vcore = 662500
2126 06:53:15.830905 Vdram = 0
2127 06:53:15.831285 Vddq = 0
2128 06:53:15.831630 Vmddr = 0
2129 06:53:15.836976 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2130 06:53:15.843498 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2131 06:53:15.844063 MEM_TYPE=3, freq_sel=15
2132 06:53:15.846715 sv_algorithm_assistance_LP4_1600
2133 06:53:15.850030 ============ PULL DRAM RESETB DOWN ============
2134 06:53:15.856916 ========== PULL DRAM RESETB DOWN end =========
2135 06:53:15.859941 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2136 06:53:15.863517 ===================================
2137 06:53:15.866584 LPDDR4 DRAM CONFIGURATION
2138 06:53:15.869550 ===================================
2139 06:53:15.870137 EX_ROW_EN[0] = 0x0
2140 06:53:15.873578 EX_ROW_EN[1] = 0x0
2141 06:53:15.874184 LP4Y_EN = 0x0
2142 06:53:15.876417 WORK_FSP = 0x0
2143 06:53:15.876885 WL = 0x4
2144 06:53:15.879873 RL = 0x4
2145 06:53:15.880339 BL = 0x2
2146 06:53:15.883234 RPST = 0x0
2147 06:53:15.886855 RD_PRE = 0x0
2148 06:53:15.887431 WR_PRE = 0x1
2149 06:53:15.890121 WR_PST = 0x0
2150 06:53:15.890857 DBI_WR = 0x0
2151 06:53:15.893465 DBI_RD = 0x0
2152 06:53:15.894080 OTF = 0x1
2153 06:53:15.896636 ===================================
2154 06:53:15.900167 ===================================
2155 06:53:15.900754 ANA top config
2156 06:53:15.903053 ===================================
2157 06:53:15.906580 DLL_ASYNC_EN = 0
2158 06:53:15.910093 ALL_SLAVE_EN = 0
2159 06:53:15.913556 NEW_RANK_MODE = 1
2160 06:53:15.916335 DLL_IDLE_MODE = 1
2161 06:53:15.916803 LP45_APHY_COMB_EN = 1
2162 06:53:15.919895 TX_ODT_DIS = 1
2163 06:53:15.922984 NEW_8X_MODE = 1
2164 06:53:15.926858 ===================================
2165 06:53:15.930159 ===================================
2166 06:53:15.933350 data_rate = 2400
2167 06:53:15.936927 CKR = 1
2168 06:53:15.937496 DQ_P2S_RATIO = 8
2169 06:53:15.940439 ===================================
2170 06:53:15.943460 CA_P2S_RATIO = 8
2171 06:53:15.946630 DQ_CA_OPEN = 0
2172 06:53:15.950100 DQ_SEMI_OPEN = 0
2173 06:53:15.953460 CA_SEMI_OPEN = 0
2174 06:53:15.954072 CA_FULL_RATE = 0
2175 06:53:15.956748 DQ_CKDIV4_EN = 0
2176 06:53:15.960503 CA_CKDIV4_EN = 0
2177 06:53:15.963667 CA_PREDIV_EN = 0
2178 06:53:15.966836 PH8_DLY = 17
2179 06:53:15.970558 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2180 06:53:15.971132 DQ_AAMCK_DIV = 4
2181 06:53:15.973604 CA_AAMCK_DIV = 4
2182 06:53:15.976886 CA_ADMCK_DIV = 4
2183 06:53:15.980056 DQ_TRACK_CA_EN = 0
2184 06:53:15.983317 CA_PICK = 1200
2185 06:53:15.986825 CA_MCKIO = 1200
2186 06:53:15.990034 MCKIO_SEMI = 0
2187 06:53:15.993560 PLL_FREQ = 2366
2188 06:53:15.994165 DQ_UI_PI_RATIO = 32
2189 06:53:15.996309 CA_UI_PI_RATIO = 0
2190 06:53:15.999871 ===================================
2191 06:53:16.003307 ===================================
2192 06:53:16.006349 memory_type:LPDDR4
2193 06:53:16.009711 GP_NUM : 10
2194 06:53:16.010282 SRAM_EN : 1
2195 06:53:16.013141 MD32_EN : 0
2196 06:53:16.016272 ===================================
2197 06:53:16.016744 [ANA_INIT] >>>>>>>>>>>>>>
2198 06:53:16.019947 <<<<<< [CONFIGURE PHASE]: ANA_TX
2199 06:53:16.023060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2200 06:53:16.026430 ===================================
2201 06:53:16.029926 data_rate = 2400,PCW = 0X5b00
2202 06:53:16.032976 ===================================
2203 06:53:16.036633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2204 06:53:16.043515 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 06:53:16.050117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 06:53:16.053132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2207 06:53:16.056533 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2208 06:53:16.059717 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2209 06:53:16.063078 [ANA_INIT] flow start
2210 06:53:16.063551 [ANA_INIT] PLL >>>>>>>>
2211 06:53:16.066543 [ANA_INIT] PLL <<<<<<<<
2212 06:53:16.070026 [ANA_INIT] MIDPI >>>>>>>>
2213 06:53:16.070605 [ANA_INIT] MIDPI <<<<<<<<
2214 06:53:16.073098 [ANA_INIT] DLL >>>>>>>>
2215 06:53:16.076365 [ANA_INIT] DLL <<<<<<<<
2216 06:53:16.076938 [ANA_INIT] flow end
2217 06:53:16.083214 ============ LP4 DIFF to SE enter ============
2218 06:53:16.086804 ============ LP4 DIFF to SE exit ============
2219 06:53:16.087386 [ANA_INIT] <<<<<<<<<<<<<
2220 06:53:16.090284 [Flow] Enable top DCM control >>>>>
2221 06:53:16.092966 [Flow] Enable top DCM control <<<<<
2222 06:53:16.096298 Enable DLL master slave shuffle
2223 06:53:16.102993 ==============================================================
2224 06:53:16.103556 Gating Mode config
2225 06:53:16.110048 ==============================================================
2226 06:53:16.112936 Config description:
2227 06:53:16.122920 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2228 06:53:16.129801 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2229 06:53:16.133392 SELPH_MODE 0: By rank 1: By Phase
2230 06:53:16.139662 ==============================================================
2231 06:53:16.142974 GAT_TRACK_EN = 1
2232 06:53:16.146481 RX_GATING_MODE = 2
2233 06:53:16.147055 RX_GATING_TRACK_MODE = 2
2234 06:53:16.150010 SELPH_MODE = 1
2235 06:53:16.153155 PICG_EARLY_EN = 1
2236 06:53:16.156613 VALID_LAT_VALUE = 1
2237 06:53:16.163304 ==============================================================
2238 06:53:16.166701 Enter into Gating configuration >>>>
2239 06:53:16.170095 Exit from Gating configuration <<<<
2240 06:53:16.173432 Enter into DVFS_PRE_config >>>>>
2241 06:53:16.183344 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2242 06:53:16.186693 Exit from DVFS_PRE_config <<<<<
2243 06:53:16.189834 Enter into PICG configuration >>>>
2244 06:53:16.193262 Exit from PICG configuration <<<<
2245 06:53:16.196220 [RX_INPUT] configuration >>>>>
2246 06:53:16.199830 [RX_INPUT] configuration <<<<<
2247 06:53:16.203042 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2248 06:53:16.209888 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2249 06:53:16.216158 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 06:53:16.219987 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 06:53:16.226559 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 06:53:16.232963 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 06:53:16.236610 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2254 06:53:16.239630 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2255 06:53:16.246401 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2256 06:53:16.249931 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2257 06:53:16.253117 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2258 06:53:16.260216 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 06:53:16.263121 ===================================
2260 06:53:16.263593 LPDDR4 DRAM CONFIGURATION
2261 06:53:16.266632 ===================================
2262 06:53:16.269916 EX_ROW_EN[0] = 0x0
2263 06:53:16.270537 EX_ROW_EN[1] = 0x0
2264 06:53:16.273205 LP4Y_EN = 0x0
2265 06:53:16.273772 WORK_FSP = 0x0
2266 06:53:16.277065 WL = 0x4
2267 06:53:16.277630 RL = 0x4
2268 06:53:16.280111 BL = 0x2
2269 06:53:16.283210 RPST = 0x0
2270 06:53:16.283782 RD_PRE = 0x0
2271 06:53:16.286643 WR_PRE = 0x1
2272 06:53:16.287205 WR_PST = 0x0
2273 06:53:16.290152 DBI_WR = 0x0
2274 06:53:16.290719 DBI_RD = 0x0
2275 06:53:16.293159 OTF = 0x1
2276 06:53:16.296624 ===================================
2277 06:53:16.300148 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2278 06:53:16.303248 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2279 06:53:16.306188 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2280 06:53:16.309766 ===================================
2281 06:53:16.313597 LPDDR4 DRAM CONFIGURATION
2282 06:53:16.316603 ===================================
2283 06:53:16.320700 EX_ROW_EN[0] = 0x10
2284 06:53:16.321273 EX_ROW_EN[1] = 0x0
2285 06:53:16.323052 LP4Y_EN = 0x0
2286 06:53:16.323522 WORK_FSP = 0x0
2287 06:53:16.326897 WL = 0x4
2288 06:53:16.327470 RL = 0x4
2289 06:53:16.330111 BL = 0x2
2290 06:53:16.330716 RPST = 0x0
2291 06:53:16.333048 RD_PRE = 0x0
2292 06:53:16.333514 WR_PRE = 0x1
2293 06:53:16.336651 WR_PST = 0x0
2294 06:53:16.337107 DBI_WR = 0x0
2295 06:53:16.339862 DBI_RD = 0x0
2296 06:53:16.340316 OTF = 0x1
2297 06:53:16.343060 ===================================
2298 06:53:16.349969 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2299 06:53:16.350428 ==
2300 06:53:16.353317 Dram Type= 6, Freq= 0, CH_0, rank 0
2301 06:53:16.360192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2302 06:53:16.360615 ==
2303 06:53:16.360880 [Duty_Offset_Calibration]
2304 06:53:16.363632 B0:2 B1:0 CA:1
2305 06:53:16.364056
2306 06:53:16.366730 [DutyScan_Calibration_Flow] k_type=0
2307 06:53:16.374723
2308 06:53:16.375145 ==CLK 0==
2309 06:53:16.377864 Final CLK duty delay cell = -4
2310 06:53:16.381254 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2311 06:53:16.384735 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2312 06:53:16.387970 [-4] AVG Duty = 4953%(X100)
2313 06:53:16.388491
2314 06:53:16.391242 CH0 CLK Duty spec in!! Max-Min= 156%
2315 06:53:16.394462 [DutyScan_Calibration_Flow] ====Done====
2316 06:53:16.394920
2317 06:53:16.398012 [DutyScan_Calibration_Flow] k_type=1
2318 06:53:16.413571
2319 06:53:16.414176 ==DQS 0 ==
2320 06:53:16.416530 Final DQS duty delay cell = 0
2321 06:53:16.420001 [0] MAX Duty = 5187%(X100), DQS PI = 32
2322 06:53:16.423369 [0] MIN Duty = 4938%(X100), DQS PI = 0
2323 06:53:16.423871 [0] AVG Duty = 5062%(X100)
2324 06:53:16.426772
2325 06:53:16.427229 ==DQS 1 ==
2326 06:53:16.430181 Final DQS duty delay cell = -4
2327 06:53:16.433857 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2328 06:53:16.437232 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2329 06:53:16.440124 [-4] AVG Duty = 5015%(X100)
2330 06:53:16.440583
2331 06:53:16.443806 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2332 06:53:16.444265
2333 06:53:16.446727 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2334 06:53:16.450153 [DutyScan_Calibration_Flow] ====Done====
2335 06:53:16.450711
2336 06:53:16.453196 [DutyScan_Calibration_Flow] k_type=3
2337 06:53:16.470857
2338 06:53:16.471403 ==DQM 0 ==
2339 06:53:16.473604 Final DQM duty delay cell = 0
2340 06:53:16.477358 [0] MAX Duty = 5062%(X100), DQS PI = 24
2341 06:53:16.480293 [0] MIN Duty = 4813%(X100), DQS PI = 0
2342 06:53:16.480846 [0] AVG Duty = 4937%(X100)
2343 06:53:16.483793
2344 06:53:16.484347 ==DQM 1 ==
2345 06:53:16.487400 Final DQM duty delay cell = 0
2346 06:53:16.490509 [0] MAX Duty = 5187%(X100), DQS PI = 46
2347 06:53:16.493630 [0] MIN Duty = 5000%(X100), DQS PI = 14
2348 06:53:16.494130 [0] AVG Duty = 5093%(X100)
2349 06:53:16.496893
2350 06:53:16.500849 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2351 06:53:16.501406
2352 06:53:16.503658 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2353 06:53:16.507346 [DutyScan_Calibration_Flow] ====Done====
2354 06:53:16.507931
2355 06:53:16.510320 [DutyScan_Calibration_Flow] k_type=2
2356 06:53:16.526868
2357 06:53:16.527438 ==DQ 0 ==
2358 06:53:16.530286 Final DQ duty delay cell = -4
2359 06:53:16.533438 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2360 06:53:16.536859 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2361 06:53:16.540917 [-4] AVG Duty = 4968%(X100)
2362 06:53:16.541543
2363 06:53:16.541927 ==DQ 1 ==
2364 06:53:16.543381 Final DQ duty delay cell = 4
2365 06:53:16.546766 [4] MAX Duty = 5093%(X100), DQS PI = 4
2366 06:53:16.550298 [4] MIN Duty = 5031%(X100), DQS PI = 14
2367 06:53:16.553328 [4] AVG Duty = 5062%(X100)
2368 06:53:16.553801
2369 06:53:16.556883 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2370 06:53:16.557456
2371 06:53:16.560044 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2372 06:53:16.563650 [DutyScan_Calibration_Flow] ====Done====
2373 06:53:16.564227 ==
2374 06:53:16.566786 Dram Type= 6, Freq= 0, CH_1, rank 0
2375 06:53:16.570439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 06:53:16.571014 ==
2377 06:53:16.573454 [Duty_Offset_Calibration]
2378 06:53:16.574067 B0:0 B1:-1 CA:2
2379 06:53:16.574452
2380 06:53:16.576963 [DutyScan_Calibration_Flow] k_type=0
2381 06:53:16.587608
2382 06:53:16.588180 ==CLK 0==
2383 06:53:16.590470 Final CLK duty delay cell = 0
2384 06:53:16.593817 [0] MAX Duty = 5156%(X100), DQS PI = 16
2385 06:53:16.596847 [0] MIN Duty = 4938%(X100), DQS PI = 44
2386 06:53:16.597319 [0] AVG Duty = 5047%(X100)
2387 06:53:16.600805
2388 06:53:16.601376 CH1 CLK Duty spec in!! Max-Min= 218%
2389 06:53:16.607256 [DutyScan_Calibration_Flow] ====Done====
2390 06:53:16.607860
2391 06:53:16.610152 [DutyScan_Calibration_Flow] k_type=1
2392 06:53:16.626289
2393 06:53:16.626757 ==DQS 0 ==
2394 06:53:16.629560 Final DQS duty delay cell = 0
2395 06:53:16.632906 [0] MAX Duty = 5062%(X100), DQS PI = 22
2396 06:53:16.636541 [0] MIN Duty = 4969%(X100), DQS PI = 0
2397 06:53:16.637034 [0] AVG Duty = 5015%(X100)
2398 06:53:16.639791
2399 06:53:16.640258 ==DQS 1 ==
2400 06:53:16.642828 Final DQS duty delay cell = 0
2401 06:53:16.646399 [0] MAX Duty = 5156%(X100), DQS PI = 0
2402 06:53:16.649754 [0] MIN Duty = 4844%(X100), DQS PI = 34
2403 06:53:16.650272 [0] AVG Duty = 5000%(X100)
2404 06:53:16.652911
2405 06:53:16.656481 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2406 06:53:16.657064
2407 06:53:16.659739 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2408 06:53:16.663031 [DutyScan_Calibration_Flow] ====Done====
2409 06:53:16.663527
2410 06:53:16.666507 [DutyScan_Calibration_Flow] k_type=3
2411 06:53:16.682795
2412 06:53:16.683362 ==DQM 0 ==
2413 06:53:16.685800 Final DQM duty delay cell = 4
2414 06:53:16.689600 [4] MAX Duty = 5093%(X100), DQS PI = 20
2415 06:53:16.692806 [4] MIN Duty = 4938%(X100), DQS PI = 48
2416 06:53:16.695813 [4] AVG Duty = 5015%(X100)
2417 06:53:16.696284
2418 06:53:16.696677 ==DQM 1 ==
2419 06:53:16.699518 Final DQM duty delay cell = -4
2420 06:53:16.702525 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2421 06:53:16.706395 [-4] MIN Duty = 4751%(X100), DQS PI = 34
2422 06:53:16.709627 [-4] AVG Duty = 4875%(X100)
2423 06:53:16.710129
2424 06:53:16.712842 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2425 06:53:16.713311
2426 06:53:16.716040 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2427 06:53:16.719443 [DutyScan_Calibration_Flow] ====Done====
2428 06:53:16.719908
2429 06:53:16.722752 [DutyScan_Calibration_Flow] k_type=2
2430 06:53:16.739737
2431 06:53:16.740310 ==DQ 0 ==
2432 06:53:16.742819 Final DQ duty delay cell = 0
2433 06:53:16.746251 [0] MAX Duty = 5062%(X100), DQS PI = 20
2434 06:53:16.749935 [0] MIN Duty = 4938%(X100), DQS PI = 0
2435 06:53:16.750442 [0] AVG Duty = 5000%(X100)
2436 06:53:16.750817
2437 06:53:16.753387 ==DQ 1 ==
2438 06:53:16.754019 Final DQ duty delay cell = 0
2439 06:53:16.759626 [0] MAX Duty = 5031%(X100), DQS PI = 2
2440 06:53:16.762807 [0] MIN Duty = 4813%(X100), DQS PI = 34
2441 06:53:16.763281 [0] AVG Duty = 4922%(X100)
2442 06:53:16.763654
2443 06:53:16.766371 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2444 06:53:16.766936
2445 06:53:16.770142 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2446 06:53:16.776308 [DutyScan_Calibration_Flow] ====Done====
2447 06:53:16.779766 nWR fixed to 30
2448 06:53:16.780338 [ModeRegInit_LP4] CH0 RK0
2449 06:53:16.782766 [ModeRegInit_LP4] CH0 RK1
2450 06:53:16.786266 [ModeRegInit_LP4] CH1 RK0
2451 06:53:16.786735 [ModeRegInit_LP4] CH1 RK1
2452 06:53:16.789926 match AC timing 7
2453 06:53:16.793361 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2454 06:53:16.796470 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2455 06:53:16.803188 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2456 06:53:16.806428 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2457 06:53:16.813082 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2458 06:53:16.813555 ==
2459 06:53:16.816455 Dram Type= 6, Freq= 0, CH_0, rank 0
2460 06:53:16.819627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 06:53:16.820101 ==
2462 06:53:16.826531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2463 06:53:16.829491 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2464 06:53:16.839322 [CA 0] Center 38 (7~69) winsize 63
2465 06:53:16.842406 [CA 1] Center 38 (7~69) winsize 63
2466 06:53:16.846254 [CA 2] Center 34 (4~65) winsize 62
2467 06:53:16.849324 [CA 3] Center 34 (4~65) winsize 62
2468 06:53:16.852826 [CA 4] Center 33 (3~64) winsize 62
2469 06:53:16.856321 [CA 5] Center 32 (2~63) winsize 62
2470 06:53:16.856790
2471 06:53:16.859194 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2472 06:53:16.859661
2473 06:53:16.862882 [CATrainingPosCal] consider 1 rank data
2474 06:53:16.865862 u2DelayCellTimex100 = 270/100 ps
2475 06:53:16.869319 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2476 06:53:16.872680 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2477 06:53:16.879118 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2478 06:53:16.882887 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2479 06:53:16.885830 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2480 06:53:16.889296 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2481 06:53:16.889918
2482 06:53:16.892546 CA PerBit enable=1, Macro0, CA PI delay=32
2483 06:53:16.893132
2484 06:53:16.895880 [CBTSetCACLKResult] CA Dly = 32
2485 06:53:16.896690 CS Dly: 6 (0~37)
2486 06:53:16.897434 ==
2487 06:53:16.899184 Dram Type= 6, Freq= 0, CH_0, rank 1
2488 06:53:16.905904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 06:53:16.906458 ==
2490 06:53:16.909250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 06:53:16.916221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2492 06:53:16.925046 [CA 0] Center 38 (7~69) winsize 63
2493 06:53:16.928336 [CA 1] Center 38 (8~69) winsize 62
2494 06:53:16.931273 [CA 2] Center 35 (5~66) winsize 62
2495 06:53:16.934673 [CA 3] Center 35 (4~66) winsize 63
2496 06:53:16.938176 [CA 4] Center 34 (3~65) winsize 63
2497 06:53:16.941352 [CA 5] Center 33 (3~63) winsize 61
2498 06:53:16.941973
2499 06:53:16.944752 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2500 06:53:16.945262
2501 06:53:16.948425 [CATrainingPosCal] consider 2 rank data
2502 06:53:16.951575 u2DelayCellTimex100 = 270/100 ps
2503 06:53:16.954928 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2504 06:53:16.958151 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2505 06:53:16.964824 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2506 06:53:16.968482 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2507 06:53:16.971862 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2508 06:53:16.974966 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2509 06:53:16.975562
2510 06:53:16.978405 CA PerBit enable=1, Macro0, CA PI delay=33
2511 06:53:16.978873
2512 06:53:16.981467 [CBTSetCACLKResult] CA Dly = 33
2513 06:53:16.981937 CS Dly: 7 (0~39)
2514 06:53:16.982342
2515 06:53:16.985161 ----->DramcWriteLeveling(PI) begin...
2516 06:53:16.985634 ==
2517 06:53:16.988556 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 06:53:16.995152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 06:53:16.995735 ==
2520 06:53:16.998232 Write leveling (Byte 0): 34 => 34
2521 06:53:17.001875 Write leveling (Byte 1): 32 => 32
2522 06:53:17.005126 DramcWriteLeveling(PI) end<-----
2523 06:53:17.005675
2524 06:53:17.006104 ==
2525 06:53:17.008274 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 06:53:17.011766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 06:53:17.012239 ==
2528 06:53:17.015359 [Gating] SW mode calibration
2529 06:53:17.021799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2530 06:53:17.024880 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2531 06:53:17.032062 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2532 06:53:17.035124 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2533 06:53:17.038527 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 06:53:17.045034 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 06:53:17.048589 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 06:53:17.051830 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 06:53:17.058702 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2538 06:53:17.062098 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2539 06:53:17.065400 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2540 06:53:17.072083 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 06:53:17.075347 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 06:53:17.079044 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 06:53:17.081920 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 06:53:17.088960 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 06:53:17.091994 1 0 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2546 06:53:17.095726 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2547 06:53:17.102178 1 1 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
2548 06:53:17.105923 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 06:53:17.109101 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 06:53:17.115652 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 06:53:17.118656 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 06:53:17.122019 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 06:53:17.129074 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 06:53:17.132029 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2555 06:53:17.135503 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2556 06:53:17.142114 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 06:53:17.145809 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 06:53:17.148993 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 06:53:17.152745 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 06:53:17.158913 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 06:53:17.162563 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 06:53:17.165783 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 06:53:17.172310 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 06:53:17.175731 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 06:53:17.178599 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 06:53:17.185594 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 06:53:17.188813 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 06:53:17.192179 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 06:53:17.198617 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 06:53:17.202607 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2571 06:53:17.205826 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2572 06:53:17.209045 Total UI for P1: 0, mck2ui 16
2573 06:53:17.212341 best dqsien dly found for B0: ( 1, 3, 28)
2574 06:53:17.218866 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 06:53:17.219451 Total UI for P1: 0, mck2ui 16
2576 06:53:17.225839 best dqsien dly found for B1: ( 1, 3, 30)
2577 06:53:17.229146 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2578 06:53:17.232016 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2579 06:53:17.232489
2580 06:53:17.235554 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2581 06:53:17.238652 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2582 06:53:17.242202 [Gating] SW calibration Done
2583 06:53:17.242929 ==
2584 06:53:17.245674 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 06:53:17.248560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 06:53:17.249036 ==
2587 06:53:17.252321 RX Vref Scan: 0
2588 06:53:17.252890
2589 06:53:17.253266 RX Vref 0 -> 0, step: 1
2590 06:53:17.253613
2591 06:53:17.255465 RX Delay -40 -> 252, step: 8
2592 06:53:17.259353 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2593 06:53:17.265647 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2594 06:53:17.269174 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2595 06:53:17.272336 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2596 06:53:17.276029 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2597 06:53:17.278874 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2598 06:53:17.282385 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2599 06:53:17.288818 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2600 06:53:17.292273 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2601 06:53:17.295386 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2602 06:53:17.298834 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2603 06:53:17.302359 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2604 06:53:17.309099 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2605 06:53:17.312390 iDelay=208, Bit 13, Center 111 (48 ~ 175) 128
2606 06:53:17.315527 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2607 06:53:17.319031 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2608 06:53:17.319608 ==
2609 06:53:17.322058 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 06:53:17.328952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 06:53:17.329528 ==
2612 06:53:17.329904 DQS Delay:
2613 06:53:17.332535 DQS0 = 0, DQS1 = 0
2614 06:53:17.333107 DQM Delay:
2615 06:53:17.335274 DQM0 = 123, DQM1 = 110
2616 06:53:17.335797 DQ Delay:
2617 06:53:17.338728 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2618 06:53:17.342300 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2619 06:53:17.345388 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2620 06:53:17.348479 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =115
2621 06:53:17.348946
2622 06:53:17.349315
2623 06:53:17.349659 ==
2624 06:53:17.352182 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 06:53:17.355797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 06:53:17.358862 ==
2627 06:53:17.359439
2628 06:53:17.359812
2629 06:53:17.360161 TX Vref Scan disable
2630 06:53:17.362171 == TX Byte 0 ==
2631 06:53:17.365392 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2632 06:53:17.368980 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2633 06:53:17.372171 == TX Byte 1 ==
2634 06:53:17.375358 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2635 06:53:17.378633 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2636 06:53:17.381994 ==
2637 06:53:17.382566 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 06:53:17.388895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 06:53:17.389480 ==
2640 06:53:17.399448 TX Vref=22, minBit 7, minWin=22, winSum=390
2641 06:53:17.403210 TX Vref=24, minBit 3, minWin=23, winSum=402
2642 06:53:17.406124 TX Vref=26, minBit 2, minWin=24, winSum=408
2643 06:53:17.409640 TX Vref=28, minBit 4, minWin=24, winSum=410
2644 06:53:17.412874 TX Vref=30, minBit 1, minWin=25, winSum=412
2645 06:53:17.416298 TX Vref=32, minBit 0, minWin=25, winSum=408
2646 06:53:17.423247 [TxChooseVref] Worse bit 1, Min win 25, Win sum 412, Final Vref 30
2647 06:53:17.423820
2648 06:53:17.426333 Final TX Range 1 Vref 30
2649 06:53:17.426912
2650 06:53:17.427288 ==
2651 06:53:17.430060 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 06:53:17.433162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 06:53:17.433741 ==
2654 06:53:17.434207
2655 06:53:17.434567
2656 06:53:17.436271 TX Vref Scan disable
2657 06:53:17.440013 == TX Byte 0 ==
2658 06:53:17.443276 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2659 06:53:17.446578 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2660 06:53:17.450062 == TX Byte 1 ==
2661 06:53:17.453309 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2662 06:53:17.456593 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2663 06:53:17.457169
2664 06:53:17.459943 [DATLAT]
2665 06:53:17.460514 Freq=1200, CH0 RK0
2666 06:53:17.460891
2667 06:53:17.463189 DATLAT Default: 0xd
2668 06:53:17.463761 0, 0xFFFF, sum = 0
2669 06:53:17.466724 1, 0xFFFF, sum = 0
2670 06:53:17.467300 2, 0xFFFF, sum = 0
2671 06:53:17.470409 3, 0xFFFF, sum = 0
2672 06:53:17.471001 4, 0xFFFF, sum = 0
2673 06:53:17.473274 5, 0xFFFF, sum = 0
2674 06:53:17.473748 6, 0xFFFF, sum = 0
2675 06:53:17.476765 7, 0xFFFF, sum = 0
2676 06:53:17.477353 8, 0xFFFF, sum = 0
2677 06:53:17.479764 9, 0xFFFF, sum = 0
2678 06:53:17.480281 10, 0xFFFF, sum = 0
2679 06:53:17.482997 11, 0xFFFF, sum = 0
2680 06:53:17.483561 12, 0x0, sum = 1
2681 06:53:17.486433 13, 0x0, sum = 2
2682 06:53:17.487007 14, 0x0, sum = 3
2683 06:53:17.489973 15, 0x0, sum = 4
2684 06:53:17.490555 best_step = 13
2685 06:53:17.490933
2686 06:53:17.491284 ==
2687 06:53:17.493000 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 06:53:17.499579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 06:53:17.500096 ==
2690 06:53:17.500476 RX Vref Scan: 1
2691 06:53:17.500827
2692 06:53:17.502880 Set Vref Range= 32 -> 127
2693 06:53:17.503353
2694 06:53:17.506445 RX Vref 32 -> 127, step: 1
2695 06:53:17.506915
2696 06:53:17.509906 RX Delay -13 -> 252, step: 4
2697 06:53:17.510558
2698 06:53:17.512634 Set Vref, RX VrefLevel [Byte0]: 32
2699 06:53:17.516513 [Byte1]: 32
2700 06:53:17.517083
2701 06:53:17.519339 Set Vref, RX VrefLevel [Byte0]: 33
2702 06:53:17.522750 [Byte1]: 33
2703 06:53:17.523221
2704 06:53:17.526556 Set Vref, RX VrefLevel [Byte0]: 34
2705 06:53:17.530121 [Byte1]: 34
2706 06:53:17.533967
2707 06:53:17.534556 Set Vref, RX VrefLevel [Byte0]: 35
2708 06:53:17.536731 [Byte1]: 35
2709 06:53:17.541482
2710 06:53:17.542089 Set Vref, RX VrefLevel [Byte0]: 36
2711 06:53:17.545039 [Byte1]: 36
2712 06:53:17.549303
2713 06:53:17.549876 Set Vref, RX VrefLevel [Byte0]: 37
2714 06:53:17.553149 [Byte1]: 37
2715 06:53:17.557030
2716 06:53:17.557498 Set Vref, RX VrefLevel [Byte0]: 38
2717 06:53:17.560663 [Byte1]: 38
2718 06:53:17.565056
2719 06:53:17.565632 Set Vref, RX VrefLevel [Byte0]: 39
2720 06:53:17.568627 [Byte1]: 39
2721 06:53:17.573122
2722 06:53:17.573691 Set Vref, RX VrefLevel [Byte0]: 40
2723 06:53:17.576643 [Byte1]: 40
2724 06:53:17.581192
2725 06:53:17.581764 Set Vref, RX VrefLevel [Byte0]: 41
2726 06:53:17.584178 [Byte1]: 41
2727 06:53:17.589071
2728 06:53:17.589640 Set Vref, RX VrefLevel [Byte0]: 42
2729 06:53:17.592043 [Byte1]: 42
2730 06:53:17.596496
2731 06:53:17.596963 Set Vref, RX VrefLevel [Byte0]: 43
2732 06:53:17.599902 [Byte1]: 43
2733 06:53:17.604680
2734 06:53:17.605145 Set Vref, RX VrefLevel [Byte0]: 44
2735 06:53:17.607703 [Byte1]: 44
2736 06:53:17.612726
2737 06:53:17.613478 Set Vref, RX VrefLevel [Byte0]: 45
2738 06:53:17.615906 [Byte1]: 45
2739 06:53:17.620224
2740 06:53:17.620692 Set Vref, RX VrefLevel [Byte0]: 46
2741 06:53:17.623574 [Byte1]: 46
2742 06:53:17.628573
2743 06:53:17.629141 Set Vref, RX VrefLevel [Byte0]: 47
2744 06:53:17.631930 [Byte1]: 47
2745 06:53:17.636183
2746 06:53:17.636655 Set Vref, RX VrefLevel [Byte0]: 48
2747 06:53:17.639402 [Byte1]: 48
2748 06:53:17.644313
2749 06:53:17.644900 Set Vref, RX VrefLevel [Byte0]: 49
2750 06:53:17.647724 [Byte1]: 49
2751 06:53:17.651986
2752 06:53:17.652553 Set Vref, RX VrefLevel [Byte0]: 50
2753 06:53:17.655138 [Byte1]: 50
2754 06:53:17.659578
2755 06:53:17.660046 Set Vref, RX VrefLevel [Byte0]: 51
2756 06:53:17.662903 [Byte1]: 51
2757 06:53:17.667595
2758 06:53:17.668060 Set Vref, RX VrefLevel [Byte0]: 52
2759 06:53:17.671022 [Byte1]: 52
2760 06:53:17.675328
2761 06:53:17.675794 Set Vref, RX VrefLevel [Byte0]: 53
2762 06:53:17.678475 [Byte1]: 53
2763 06:53:17.683653
2764 06:53:17.684117 Set Vref, RX VrefLevel [Byte0]: 54
2765 06:53:17.686921 [Byte1]: 54
2766 06:53:17.691312
2767 06:53:17.691881 Set Vref, RX VrefLevel [Byte0]: 55
2768 06:53:17.694673 [Byte1]: 55
2769 06:53:17.699361
2770 06:53:17.699867 Set Vref, RX VrefLevel [Byte0]: 56
2771 06:53:17.702392 [Byte1]: 56
2772 06:53:17.707187
2773 06:53:17.707754 Set Vref, RX VrefLevel [Byte0]: 57
2774 06:53:17.710559 [Byte1]: 57
2775 06:53:17.715695
2776 06:53:17.716272 Set Vref, RX VrefLevel [Byte0]: 58
2777 06:53:17.718222 [Byte1]: 58
2778 06:53:17.723066
2779 06:53:17.723632 Set Vref, RX VrefLevel [Byte0]: 59
2780 06:53:17.726208 [Byte1]: 59
2781 06:53:17.731114
2782 06:53:17.731682 Set Vref, RX VrefLevel [Byte0]: 60
2783 06:53:17.734243 [Byte1]: 60
2784 06:53:17.738859
2785 06:53:17.739432 Set Vref, RX VrefLevel [Byte0]: 61
2786 06:53:17.742537 [Byte1]: 61
2787 06:53:17.746521
2788 06:53:17.747091 Set Vref, RX VrefLevel [Byte0]: 62
2789 06:53:17.749841 [Byte1]: 62
2790 06:53:17.754844
2791 06:53:17.755415 Set Vref, RX VrefLevel [Byte0]: 63
2792 06:53:17.757576 [Byte1]: 63
2793 06:53:17.762354
2794 06:53:17.762819 Set Vref, RX VrefLevel [Byte0]: 64
2795 06:53:17.765921 [Byte1]: 64
2796 06:53:17.770544
2797 06:53:17.771113 Set Vref, RX VrefLevel [Byte0]: 65
2798 06:53:17.773099 [Byte1]: 65
2799 06:53:17.778250
2800 06:53:17.778719 Set Vref, RX VrefLevel [Byte0]: 66
2801 06:53:17.781179 [Byte1]: 66
2802 06:53:17.785823
2803 06:53:17.786319 Set Vref, RX VrefLevel [Byte0]: 67
2804 06:53:17.789335 [Byte1]: 67
2805 06:53:17.793858
2806 06:53:17.794357 Set Vref, RX VrefLevel [Byte0]: 68
2807 06:53:17.797416 [Byte1]: 68
2808 06:53:17.801823
2809 06:53:17.802316 Set Vref, RX VrefLevel [Byte0]: 69
2810 06:53:17.805174 [Byte1]: 69
2811 06:53:17.810102
2812 06:53:17.810666 Set Vref, RX VrefLevel [Byte0]: 70
2813 06:53:17.812955 [Byte1]: 70
2814 06:53:17.817620
2815 06:53:17.818121 Final RX Vref Byte 0 = 60 to rank0
2816 06:53:17.820692 Final RX Vref Byte 1 = 50 to rank0
2817 06:53:17.824388 Final RX Vref Byte 0 = 60 to rank1
2818 06:53:17.827232 Final RX Vref Byte 1 = 50 to rank1==
2819 06:53:17.830860 Dram Type= 6, Freq= 0, CH_0, rank 0
2820 06:53:17.837209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2821 06:53:17.837769 ==
2822 06:53:17.838204 DQS Delay:
2823 06:53:17.838565 DQS0 = 0, DQS1 = 0
2824 06:53:17.841065 DQM Delay:
2825 06:53:17.841638 DQM0 = 123, DQM1 = 109
2826 06:53:17.844181 DQ Delay:
2827 06:53:17.847176 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2828 06:53:17.850861 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2829 06:53:17.854186 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2830 06:53:17.857404 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2831 06:53:17.858019
2832 06:53:17.858407
2833 06:53:17.864395 [DQSOSCAuto] RK0, (LSB)MR18= 0xa07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2834 06:53:17.867643 CH0 RK0: MR19=404, MR18=A07
2835 06:53:17.873996 CH0_RK0: MR19=0x404, MR18=0xA07, DQSOSC=406, MR23=63, INC=39, DEC=26
2836 06:53:17.874570
2837 06:53:17.877545 ----->DramcWriteLeveling(PI) begin...
2838 06:53:17.878148 ==
2839 06:53:17.881034 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 06:53:17.883882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 06:53:17.887741 ==
2842 06:53:17.888318 Write leveling (Byte 0): 37 => 37
2843 06:53:17.891099 Write leveling (Byte 1): 31 => 31
2844 06:53:17.893905 DramcWriteLeveling(PI) end<-----
2845 06:53:17.894508
2846 06:53:17.894880 ==
2847 06:53:17.897384 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 06:53:17.904266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 06:53:17.904852 ==
2850 06:53:17.905232 [Gating] SW mode calibration
2851 06:53:17.913988 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2852 06:53:17.917484 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2853 06:53:17.920657 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2854 06:53:17.927525 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 06:53:17.930709 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 06:53:17.934289 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 06:53:17.941167 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 06:53:17.943983 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 06:53:17.947888 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 06:53:17.954598 0 15 28 | B1->B0 | 2e2e 2a2a | 0 0 | (0 1) (0 0)
2861 06:53:17.957312 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 06:53:17.960765 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 06:53:17.967612 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 06:53:17.971292 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 06:53:17.974536 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 06:53:17.977874 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 06:53:17.984747 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2868 06:53:17.987922 1 0 28 | B1->B0 | 3c3c 4140 | 0 1 | (0 0) (0 0)
2869 06:53:17.991387 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 06:53:17.997758 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 06:53:18.001166 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 06:53:18.004721 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 06:53:18.010697 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 06:53:18.013981 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 06:53:18.017561 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 06:53:18.024441 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2877 06:53:18.027524 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 06:53:18.030972 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 06:53:18.037012 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 06:53:18.040375 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 06:53:18.043574 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 06:53:18.050276 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 06:53:18.053844 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 06:53:18.056964 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 06:53:18.063940 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 06:53:18.067354 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 06:53:18.070366 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 06:53:18.077358 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 06:53:18.080231 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 06:53:18.083764 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 06:53:18.087044 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 06:53:18.093661 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2893 06:53:18.097152 Total UI for P1: 0, mck2ui 16
2894 06:53:18.100648 best dqsien dly found for B0: ( 1, 3, 26)
2895 06:53:18.103916 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 06:53:18.107289 Total UI for P1: 0, mck2ui 16
2897 06:53:18.110566 best dqsien dly found for B1: ( 1, 3, 28)
2898 06:53:18.113881 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2899 06:53:18.117133 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2900 06:53:18.117237
2901 06:53:18.120304 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2902 06:53:18.123710 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2903 06:53:18.126960 [Gating] SW calibration Done
2904 06:53:18.127068 ==
2905 06:53:18.130313 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 06:53:18.137493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 06:53:18.137597 ==
2908 06:53:18.137689 RX Vref Scan: 0
2909 06:53:18.137778
2910 06:53:18.140183 RX Vref 0 -> 0, step: 1
2911 06:53:18.140256
2912 06:53:18.144097 RX Delay -40 -> 252, step: 8
2913 06:53:18.146955 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2914 06:53:18.150352 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2915 06:53:18.153978 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2916 06:53:18.156945 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2917 06:53:18.164402 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2918 06:53:18.167231 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2919 06:53:18.170512 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2920 06:53:18.174113 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2921 06:53:18.177156 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2922 06:53:18.180372 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2923 06:53:18.187270 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2924 06:53:18.190605 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2925 06:53:18.193613 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2926 06:53:18.197317 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2927 06:53:18.204015 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2928 06:53:18.207584 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2929 06:53:18.207718 ==
2930 06:53:18.211099 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 06:53:18.214096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 06:53:18.214242 ==
2933 06:53:18.214327 DQS Delay:
2934 06:53:18.217238 DQS0 = 0, DQS1 = 0
2935 06:53:18.217365 DQM Delay:
2936 06:53:18.220570 DQM0 = 120, DQM1 = 108
2937 06:53:18.220701 DQ Delay:
2938 06:53:18.224127 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2939 06:53:18.227193 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2940 06:53:18.230686 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2941 06:53:18.233890 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2942 06:53:18.234063
2943 06:53:18.234183
2944 06:53:18.237447 ==
2945 06:53:18.240906 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 06:53:18.243978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 06:53:18.244180 ==
2948 06:53:18.244338
2949 06:53:18.244493
2950 06:53:18.247762 TX Vref Scan disable
2951 06:53:18.248088 == TX Byte 0 ==
2952 06:53:18.250798 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2953 06:53:18.257779 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2954 06:53:18.258242 == TX Byte 1 ==
2955 06:53:18.261008 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2956 06:53:18.267863 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2957 06:53:18.268284 ==
2958 06:53:18.270917 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 06:53:18.274635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 06:53:18.275055 ==
2961 06:53:18.286551 TX Vref=22, minBit 3, minWin=25, winSum=413
2962 06:53:18.289838 TX Vref=24, minBit 5, minWin=25, winSum=421
2963 06:53:18.293553 TX Vref=26, minBit 1, minWin=26, winSum=425
2964 06:53:18.297032 TX Vref=28, minBit 1, minWin=26, winSum=424
2965 06:53:18.299874 TX Vref=30, minBit 13, minWin=26, winSum=432
2966 06:53:18.306488 TX Vref=32, minBit 10, minWin=26, winSum=432
2967 06:53:18.310001 [TxChooseVref] Worse bit 13, Min win 26, Win sum 432, Final Vref 30
2968 06:53:18.310558
2969 06:53:18.313584 Final TX Range 1 Vref 30
2970 06:53:18.314199
2971 06:53:18.314731 ==
2972 06:53:18.316710 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 06:53:18.319998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 06:53:18.320493 ==
2975 06:53:18.323294
2976 06:53:18.323834
2977 06:53:18.324351 TX Vref Scan disable
2978 06:53:18.327002 == TX Byte 0 ==
2979 06:53:18.330185 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2980 06:53:18.333273 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2981 06:53:18.336968 == TX Byte 1 ==
2982 06:53:18.340268 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2983 06:53:18.343459 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2984 06:53:18.346679
2985 06:53:18.347258 [DATLAT]
2986 06:53:18.347762 Freq=1200, CH0 RK1
2987 06:53:18.348244
2988 06:53:18.350069 DATLAT Default: 0xd
2989 06:53:18.350618 0, 0xFFFF, sum = 0
2990 06:53:18.353365 1, 0xFFFF, sum = 0
2991 06:53:18.353972 2, 0xFFFF, sum = 0
2992 06:53:18.356848 3, 0xFFFF, sum = 0
2993 06:53:18.356959 4, 0xFFFF, sum = 0
2994 06:53:18.359987 5, 0xFFFF, sum = 0
2995 06:53:18.363247 6, 0xFFFF, sum = 0
2996 06:53:18.363334 7, 0xFFFF, sum = 0
2997 06:53:18.366498 8, 0xFFFF, sum = 0
2998 06:53:18.366580 9, 0xFFFF, sum = 0
2999 06:53:18.370042 10, 0xFFFF, sum = 0
3000 06:53:18.370124 11, 0xFFFF, sum = 0
3001 06:53:18.373236 12, 0x0, sum = 1
3002 06:53:18.373318 13, 0x0, sum = 2
3003 06:53:18.376587 14, 0x0, sum = 3
3004 06:53:18.376672 15, 0x0, sum = 4
3005 06:53:18.376757 best_step = 13
3006 06:53:18.376836
3007 06:53:18.379832 ==
3008 06:53:18.383042 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 06:53:18.386763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 06:53:18.386849 ==
3011 06:53:18.386940 RX Vref Scan: 0
3012 06:53:18.387033
3013 06:53:18.389794 RX Vref 0 -> 0, step: 1
3014 06:53:18.389914
3015 06:53:18.393670 RX Delay -21 -> 252, step: 4
3016 06:53:18.396767 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3017 06:53:18.403191 iDelay=199, Bit 1, Center 122 (55 ~ 190) 136
3018 06:53:18.406472 iDelay=199, Bit 2, Center 118 (51 ~ 186) 136
3019 06:53:18.410437 iDelay=199, Bit 3, Center 114 (47 ~ 182) 136
3020 06:53:18.413649 iDelay=199, Bit 4, Center 120 (55 ~ 186) 132
3021 06:53:18.417530 iDelay=199, Bit 5, Center 114 (51 ~ 178) 128
3022 06:53:18.420929 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3023 06:53:18.427233 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3024 06:53:18.430384 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3025 06:53:18.433776 iDelay=199, Bit 9, Center 96 (31 ~ 162) 132
3026 06:53:18.437373 iDelay=199, Bit 10, Center 110 (47 ~ 174) 128
3027 06:53:18.440699 iDelay=199, Bit 11, Center 104 (43 ~ 166) 124
3028 06:53:18.447331 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
3029 06:53:18.450398 iDelay=199, Bit 13, Center 110 (47 ~ 174) 128
3030 06:53:18.454065 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3031 06:53:18.457398 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
3032 06:53:18.457865 ==
3033 06:53:18.460350 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 06:53:18.467323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 06:53:18.467792 ==
3036 06:53:18.468164 DQS Delay:
3037 06:53:18.468511 DQS0 = 0, DQS1 = 0
3038 06:53:18.470867 DQM Delay:
3039 06:53:18.471328 DQM0 = 119, DQM1 = 108
3040 06:53:18.474222 DQ Delay:
3041 06:53:18.477298 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3042 06:53:18.480826 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =124
3043 06:53:18.484261 DQ8 =98, DQ9 =96, DQ10 =110, DQ11 =104
3044 06:53:18.487449 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3045 06:53:18.488019
3046 06:53:18.488386
3047 06:53:18.493761 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3048 06:53:18.497659 CH0 RK1: MR19=403, MR18=11F8
3049 06:53:18.504139 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3050 06:53:18.507564 [RxdqsGatingPostProcess] freq 1200
3051 06:53:18.514270 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3052 06:53:18.517574 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 06:53:18.518098 best DQS1 dly(2T, 0.5T) = (0, 11)
3054 06:53:18.520617 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 06:53:18.524292 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3056 06:53:18.527219 best DQS0 dly(2T, 0.5T) = (0, 11)
3057 06:53:18.530770 best DQS1 dly(2T, 0.5T) = (0, 11)
3058 06:53:18.534053 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3059 06:53:18.537231 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3060 06:53:18.541012 Pre-setting of DQS Precalculation
3061 06:53:18.547447 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3062 06:53:18.548054 ==
3063 06:53:18.550719 Dram Type= 6, Freq= 0, CH_1, rank 0
3064 06:53:18.553720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 06:53:18.554221 ==
3066 06:53:18.560727 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3067 06:53:18.564608 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=23, u1VrefScanEnd=33
3068 06:53:18.573747 [CA 0] Center 37 (7~67) winsize 61
3069 06:53:18.576849 [CA 1] Center 37 (7~68) winsize 62
3070 06:53:18.580222 [CA 2] Center 35 (5~65) winsize 61
3071 06:53:18.583505 [CA 3] Center 33 (3~64) winsize 62
3072 06:53:18.586665 [CA 4] Center 33 (3~64) winsize 62
3073 06:53:18.590047 [CA 5] Center 33 (3~64) winsize 62
3074 06:53:18.590626
3075 06:53:18.593845 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3076 06:53:18.594460
3077 06:53:18.596977 [CATrainingPosCal] consider 1 rank data
3078 06:53:18.599900 u2DelayCellTimex100 = 270/100 ps
3079 06:53:18.603539 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3080 06:53:18.606829 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3081 06:53:18.614171 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3082 06:53:18.617000 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3083 06:53:18.620245 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3084 06:53:18.623309 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3085 06:53:18.623776
3086 06:53:18.627146 CA PerBit enable=1, Macro0, CA PI delay=33
3087 06:53:18.627743
3088 06:53:18.630129 [CBTSetCACLKResult] CA Dly = 33
3089 06:53:18.630599 CS Dly: 4 (0~35)
3090 06:53:18.631012 ==
3091 06:53:18.633237 Dram Type= 6, Freq= 0, CH_1, rank 1
3092 06:53:18.640182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 06:53:18.640759 ==
3094 06:53:18.643429 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 06:53:18.649906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3096 06:53:18.659050 [CA 0] Center 38 (8~68) winsize 61
3097 06:53:18.662611 [CA 1] Center 37 (7~68) winsize 62
3098 06:53:18.666345 [CA 2] Center 35 (4~66) winsize 63
3099 06:53:18.669222 [CA 3] Center 34 (4~64) winsize 61
3100 06:53:18.672460 [CA 4] Center 34 (4~64) winsize 61
3101 06:53:18.675866 [CA 5] Center 33 (3~64) winsize 62
3102 06:53:18.676442
3103 06:53:18.679212 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3104 06:53:18.679684
3105 06:53:18.682392 [CATrainingPosCal] consider 2 rank data
3106 06:53:18.685833 u2DelayCellTimex100 = 270/100 ps
3107 06:53:18.689326 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3108 06:53:18.692737 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3109 06:53:18.695705 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3110 06:53:18.702410 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3111 06:53:18.706205 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 06:53:18.709305 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3113 06:53:18.709775
3114 06:53:18.713185 CA PerBit enable=1, Macro0, CA PI delay=33
3115 06:53:18.713763
3116 06:53:18.716376 [CBTSetCACLKResult] CA Dly = 33
3117 06:53:18.716950 CS Dly: 5 (0~38)
3118 06:53:18.717333
3119 06:53:18.719245 ----->DramcWriteLeveling(PI) begin...
3120 06:53:18.719722 ==
3121 06:53:18.722805 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 06:53:18.729445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 06:53:18.730080 ==
3124 06:53:18.732842 Write leveling (Byte 0): 27 => 27
3125 06:53:18.736142 Write leveling (Byte 1): 29 => 29
3126 06:53:18.736718 DramcWriteLeveling(PI) end<-----
3127 06:53:18.737096
3128 06:53:18.739529 ==
3129 06:53:18.742868 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 06:53:18.746250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 06:53:18.746724 ==
3132 06:53:18.749610 [Gating] SW mode calibration
3133 06:53:18.756625 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3134 06:53:18.759561 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3135 06:53:18.766229 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 06:53:18.769338 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 06:53:18.772748 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 06:53:18.779139 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 06:53:18.782867 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 06:53:18.786196 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3141 06:53:18.792731 0 15 24 | B1->B0 | 2f2f 2828 | 1 0 | (1 0) (0 0)
3142 06:53:18.796121 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3143 06:53:18.799335 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 06:53:18.802857 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 06:53:18.809813 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 06:53:18.813286 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 06:53:18.816244 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 06:53:18.823063 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3149 06:53:18.826593 1 0 24 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
3150 06:53:18.829613 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 06:53:18.836574 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 06:53:18.839889 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 06:53:18.843254 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 06:53:18.849901 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 06:53:18.853210 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 06:53:18.856336 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 06:53:18.863070 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3158 06:53:18.866398 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3159 06:53:18.870191 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 06:53:18.873087 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 06:53:18.879744 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 06:53:18.883133 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 06:53:18.886370 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 06:53:18.893614 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 06:53:18.896677 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 06:53:18.899874 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 06:53:18.906707 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 06:53:18.910110 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 06:53:18.913601 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 06:53:18.920142 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 06:53:18.923277 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 06:53:18.926859 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 06:53:18.933491 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3174 06:53:18.936720 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3175 06:53:18.939919 Total UI for P1: 0, mck2ui 16
3176 06:53:18.943511 best dqsien dly found for B0: ( 1, 3, 24)
3177 06:53:18.946632 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 06:53:18.949872 Total UI for P1: 0, mck2ui 16
3179 06:53:18.953219 best dqsien dly found for B1: ( 1, 3, 26)
3180 06:53:18.956676 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3181 06:53:18.960133 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3182 06:53:18.960691
3183 06:53:18.963401 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3184 06:53:18.970221 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3185 06:53:18.970801 [Gating] SW calibration Done
3186 06:53:18.971180 ==
3187 06:53:18.973134 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 06:53:18.979790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 06:53:18.980346 ==
3190 06:53:18.980717 RX Vref Scan: 0
3191 06:53:18.981064
3192 06:53:18.983635 RX Vref 0 -> 0, step: 1
3193 06:53:18.984222
3194 06:53:18.986884 RX Delay -40 -> 252, step: 8
3195 06:53:18.989887 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3196 06:53:18.993154 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3197 06:53:18.996915 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3198 06:53:18.999776 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3199 06:53:19.006811 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3200 06:53:19.009935 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3201 06:53:19.013749 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3202 06:53:19.016588 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3203 06:53:19.020151 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3204 06:53:19.026715 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3205 06:53:19.029848 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3206 06:53:19.033283 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3207 06:53:19.037138 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3208 06:53:19.040003 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3209 06:53:19.046923 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3210 06:53:19.049981 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3211 06:53:19.050562 ==
3212 06:53:19.053400 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 06:53:19.056624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 06:53:19.057197 ==
3215 06:53:19.060349 DQS Delay:
3216 06:53:19.060920 DQS0 = 0, DQS1 = 0
3217 06:53:19.061404 DQM Delay:
3218 06:53:19.063378 DQM0 = 119, DQM1 = 112
3219 06:53:19.063852 DQ Delay:
3220 06:53:19.066802 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3221 06:53:19.070509 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3222 06:53:19.073330 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3223 06:53:19.080016 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3224 06:53:19.080575
3225 06:53:19.081081
3226 06:53:19.081529 ==
3227 06:53:19.083893 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 06:53:19.086541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 06:53:19.087038 ==
3230 06:53:19.087518
3231 06:53:19.087957
3232 06:53:19.089850 TX Vref Scan disable
3233 06:53:19.090394 == TX Byte 0 ==
3234 06:53:19.096533 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3235 06:53:19.100049 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3236 06:53:19.100617 == TX Byte 1 ==
3237 06:53:19.106408 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3238 06:53:19.110181 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3239 06:53:19.110758 ==
3240 06:53:19.113668 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 06:53:19.116843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 06:53:19.117423 ==
3243 06:53:19.128912 TX Vref=22, minBit 9, minWin=23, winSum=398
3244 06:53:19.132361 TX Vref=24, minBit 11, minWin=24, winSum=405
3245 06:53:19.135542 TX Vref=26, minBit 1, minWin=24, winSum=407
3246 06:53:19.138825 TX Vref=28, minBit 3, minWin=25, winSum=413
3247 06:53:19.142425 TX Vref=30, minBit 8, minWin=25, winSum=418
3248 06:53:19.148899 TX Vref=32, minBit 9, minWin=25, winSum=421
3249 06:53:19.152104 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 32
3250 06:53:19.152582
3251 06:53:19.155674 Final TX Range 1 Vref 32
3252 06:53:19.156252
3253 06:53:19.156734 ==
3254 06:53:19.158984 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 06:53:19.162397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 06:53:19.162971 ==
3257 06:53:19.163459
3258 06:53:19.165868
3259 06:53:19.166484 TX Vref Scan disable
3260 06:53:19.169239 == TX Byte 0 ==
3261 06:53:19.172311 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3262 06:53:19.175813 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3263 06:53:19.178684 == TX Byte 1 ==
3264 06:53:19.182688 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3265 06:53:19.185657 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3266 06:53:19.186178
3267 06:53:19.188959 [DATLAT]
3268 06:53:19.189415 Freq=1200, CH1 RK0
3269 06:53:19.189783
3270 06:53:19.192367 DATLAT Default: 0xd
3271 06:53:19.192968 0, 0xFFFF, sum = 0
3272 06:53:19.195807 1, 0xFFFF, sum = 0
3273 06:53:19.196391 2, 0xFFFF, sum = 0
3274 06:53:19.199036 3, 0xFFFF, sum = 0
3275 06:53:19.199608 4, 0xFFFF, sum = 0
3276 06:53:19.202460 5, 0xFFFF, sum = 0
3277 06:53:19.202929 6, 0xFFFF, sum = 0
3278 06:53:19.205812 7, 0xFFFF, sum = 0
3279 06:53:19.206323 8, 0xFFFF, sum = 0
3280 06:53:19.209422 9, 0xFFFF, sum = 0
3281 06:53:19.212887 10, 0xFFFF, sum = 0
3282 06:53:19.213464 11, 0xFFFF, sum = 0
3283 06:53:19.215709 12, 0x0, sum = 1
3284 06:53:19.216178 13, 0x0, sum = 2
3285 06:53:19.216550 14, 0x0, sum = 3
3286 06:53:19.219001 15, 0x0, sum = 4
3287 06:53:19.219472 best_step = 13
3288 06:53:19.219837
3289 06:53:19.220205 ==
3290 06:53:19.222294 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 06:53:19.229266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 06:53:19.229860 ==
3293 06:53:19.230464 RX Vref Scan: 1
3294 06:53:19.230994
3295 06:53:19.232459 Set Vref Range= 32 -> 127
3296 06:53:19.232905
3297 06:53:19.235757 RX Vref 32 -> 127, step: 1
3298 06:53:19.236205
3299 06:53:19.239406 RX Delay -13 -> 252, step: 4
3300 06:53:19.239851
3301 06:53:19.242153 Set Vref, RX VrefLevel [Byte0]: 32
3302 06:53:19.245486 [Byte1]: 32
3303 06:53:19.245930
3304 06:53:19.249097 Set Vref, RX VrefLevel [Byte0]: 33
3305 06:53:19.252298 [Byte1]: 33
3306 06:53:19.252586
3307 06:53:19.255912 Set Vref, RX VrefLevel [Byte0]: 34
3308 06:53:19.259185 [Byte1]: 34
3309 06:53:19.262616
3310 06:53:19.263000 Set Vref, RX VrefLevel [Byte0]: 35
3311 06:53:19.266399 [Byte1]: 35
3312 06:53:19.270969
3313 06:53:19.271360 Set Vref, RX VrefLevel [Byte0]: 36
3314 06:53:19.273985 [Byte1]: 36
3315 06:53:19.278749
3316 06:53:19.279249 Set Vref, RX VrefLevel [Byte0]: 37
3317 06:53:19.281897 [Byte1]: 37
3318 06:53:19.286403
3319 06:53:19.286851 Set Vref, RX VrefLevel [Byte0]: 38
3320 06:53:19.289801 [Byte1]: 38
3321 06:53:19.294225
3322 06:53:19.294621 Set Vref, RX VrefLevel [Byte0]: 39
3323 06:53:19.298029 [Byte1]: 39
3324 06:53:19.302402
3325 06:53:19.302878 Set Vref, RX VrefLevel [Byte0]: 40
3326 06:53:19.305607 [Byte1]: 40
3327 06:53:19.310381
3328 06:53:19.310829 Set Vref, RX VrefLevel [Byte0]: 41
3329 06:53:19.313575 [Byte1]: 41
3330 06:53:19.318525
3331 06:53:19.319080 Set Vref, RX VrefLevel [Byte0]: 42
3332 06:53:19.321109 [Byte1]: 42
3333 06:53:19.326133
3334 06:53:19.326533 Set Vref, RX VrefLevel [Byte0]: 43
3335 06:53:19.329384 [Byte1]: 43
3336 06:53:19.334248
3337 06:53:19.334803 Set Vref, RX VrefLevel [Byte0]: 44
3338 06:53:19.337491 [Byte1]: 44
3339 06:53:19.342215
3340 06:53:19.342764 Set Vref, RX VrefLevel [Byte0]: 45
3341 06:53:19.345378 [Byte1]: 45
3342 06:53:19.349726
3343 06:53:19.350335 Set Vref, RX VrefLevel [Byte0]: 46
3344 06:53:19.353306 [Byte1]: 46
3345 06:53:19.357900
3346 06:53:19.358525 Set Vref, RX VrefLevel [Byte0]: 47
3347 06:53:19.360686 [Byte1]: 47
3348 06:53:19.365575
3349 06:53:19.366169 Set Vref, RX VrefLevel [Byte0]: 48
3350 06:53:19.369034 [Byte1]: 48
3351 06:53:19.373707
3352 06:53:19.374302 Set Vref, RX VrefLevel [Byte0]: 49
3353 06:53:19.376995 [Byte1]: 49
3354 06:53:19.381426
3355 06:53:19.382014 Set Vref, RX VrefLevel [Byte0]: 50
3356 06:53:19.384631 [Byte1]: 50
3357 06:53:19.389508
3358 06:53:19.390097 Set Vref, RX VrefLevel [Byte0]: 51
3359 06:53:19.392309 [Byte1]: 51
3360 06:53:19.397479
3361 06:53:19.398081 Set Vref, RX VrefLevel [Byte0]: 52
3362 06:53:19.399966 [Byte1]: 52
3363 06:53:19.404882
3364 06:53:19.405336 Set Vref, RX VrefLevel [Byte0]: 53
3365 06:53:19.408211 [Byte1]: 53
3366 06:53:19.412924
3367 06:53:19.413483 Set Vref, RX VrefLevel [Byte0]: 54
3368 06:53:19.416250 [Byte1]: 54
3369 06:53:19.420901
3370 06:53:19.421483 Set Vref, RX VrefLevel [Byte0]: 55
3371 06:53:19.427392 [Byte1]: 55
3372 06:53:19.427869
3373 06:53:19.430567 Set Vref, RX VrefLevel [Byte0]: 56
3374 06:53:19.433412 [Byte1]: 56
3375 06:53:19.433880
3376 06:53:19.436938 Set Vref, RX VrefLevel [Byte0]: 57
3377 06:53:19.440542 [Byte1]: 57
3378 06:53:19.444630
3379 06:53:19.445202 Set Vref, RX VrefLevel [Byte0]: 58
3380 06:53:19.447529 [Byte1]: 58
3381 06:53:19.452319
3382 06:53:19.452889 Set Vref, RX VrefLevel [Byte0]: 59
3383 06:53:19.455637 [Byte1]: 59
3384 06:53:19.460199
3385 06:53:19.460773 Set Vref, RX VrefLevel [Byte0]: 60
3386 06:53:19.463647 [Byte1]: 60
3387 06:53:19.468194
3388 06:53:19.468767 Set Vref, RX VrefLevel [Byte0]: 61
3389 06:53:19.471394 [Byte1]: 61
3390 06:53:19.476077
3391 06:53:19.476645 Set Vref, RX VrefLevel [Byte0]: 62
3392 06:53:19.479239 [Byte1]: 62
3393 06:53:19.483944
3394 06:53:19.484517 Set Vref, RX VrefLevel [Byte0]: 63
3395 06:53:19.487155 [Byte1]: 63
3396 06:53:19.491753
3397 06:53:19.492328 Set Vref, RX VrefLevel [Byte0]: 64
3398 06:53:19.494900 [Byte1]: 64
3399 06:53:19.499642
3400 06:53:19.500216 Set Vref, RX VrefLevel [Byte0]: 65
3401 06:53:19.502711 [Byte1]: 65
3402 06:53:19.507508
3403 06:53:19.508076 Set Vref, RX VrefLevel [Byte0]: 66
3404 06:53:19.511162 [Byte1]: 66
3405 06:53:19.515470
3406 06:53:19.516062 Set Vref, RX VrefLevel [Byte0]: 67
3407 06:53:19.518599 [Byte1]: 67
3408 06:53:19.523411
3409 06:53:19.523965 Final RX Vref Byte 0 = 53 to rank0
3410 06:53:19.526408 Final RX Vref Byte 1 = 49 to rank0
3411 06:53:19.529888 Final RX Vref Byte 0 = 53 to rank1
3412 06:53:19.533444 Final RX Vref Byte 1 = 49 to rank1==
3413 06:53:19.536639 Dram Type= 6, Freq= 0, CH_1, rank 0
3414 06:53:19.539850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3415 06:53:19.543320 ==
3416 06:53:19.543951 DQS Delay:
3417 06:53:19.544337 DQS0 = 0, DQS1 = 0
3418 06:53:19.546697 DQM Delay:
3419 06:53:19.547293 DQM0 = 118, DQM1 = 111
3420 06:53:19.549866 DQ Delay:
3421 06:53:19.553598 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3422 06:53:19.556877 DQ4 =118, DQ5 =126, DQ6 =128, DQ7 =116
3423 06:53:19.560022 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104
3424 06:53:19.563423 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3425 06:53:19.563997
3426 06:53:19.564375
3427 06:53:19.569936 [DQSOSCAuto] RK0, (LSB)MR18= 0x115, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3428 06:53:19.573348 CH1 RK0: MR19=404, MR18=115
3429 06:53:19.580171 CH1_RK0: MR19=0x404, MR18=0x115, DQSOSC=401, MR23=63, INC=40, DEC=27
3430 06:53:19.580749
3431 06:53:19.583519 ----->DramcWriteLeveling(PI) begin...
3432 06:53:19.584099 ==
3433 06:53:19.586360 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 06:53:19.590198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 06:53:19.590776 ==
3436 06:53:19.593566 Write leveling (Byte 0): 25 => 25
3437 06:53:19.596816 Write leveling (Byte 1): 30 => 30
3438 06:53:19.600353 DramcWriteLeveling(PI) end<-----
3439 06:53:19.600930
3440 06:53:19.601309 ==
3441 06:53:19.603542 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 06:53:19.606650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 06:53:19.610009 ==
3444 06:53:19.610577 [Gating] SW mode calibration
3445 06:53:19.620267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3446 06:53:19.623313 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3447 06:53:19.626648 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 06:53:19.633209 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 06:53:19.636679 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 06:53:19.640466 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 06:53:19.646618 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 06:53:19.649980 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 06:53:19.653679 0 15 24 | B1->B0 | 2727 3131 | 1 1 | (1 0) (1 0)
3454 06:53:19.660285 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (0 0)
3455 06:53:19.663483 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 06:53:19.666791 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 06:53:19.673554 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 06:53:19.676819 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 06:53:19.680069 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 06:53:19.683111 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3461 06:53:19.689911 1 0 24 | B1->B0 | 3e3e 2e2d | 1 1 | (0 0) (0 0)
3462 06:53:19.693156 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3463 06:53:19.696311 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 06:53:19.703143 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 06:53:19.706678 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 06:53:19.710174 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 06:53:19.716586 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 06:53:19.719525 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 06:53:19.723186 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3470 06:53:19.729820 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 06:53:19.733112 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 06:53:19.736443 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 06:53:19.743207 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 06:53:19.746251 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 06:53:19.749934 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 06:53:19.755740 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 06:53:19.759164 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 06:53:19.762405 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 06:53:19.769021 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 06:53:19.772336 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 06:53:19.775652 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 06:53:19.782329 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 06:53:19.785541 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 06:53:19.789113 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 06:53:19.795703 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3486 06:53:19.798825 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3487 06:53:19.801928 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 06:53:19.805342 Total UI for P1: 0, mck2ui 16
3489 06:53:19.808641 best dqsien dly found for B0: ( 1, 3, 26)
3490 06:53:19.811922 Total UI for P1: 0, mck2ui 16
3491 06:53:19.815182 best dqsien dly found for B1: ( 1, 3, 26)
3492 06:53:19.818952 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3493 06:53:19.822162 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3494 06:53:19.822259
3495 06:53:19.828719 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3496 06:53:19.831792 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3497 06:53:19.831895 [Gating] SW calibration Done
3498 06:53:19.835415 ==
3499 06:53:19.838633 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 06:53:19.842351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 06:53:19.842433 ==
3502 06:53:19.842498 RX Vref Scan: 0
3503 06:53:19.842559
3504 06:53:19.845040 RX Vref 0 -> 0, step: 1
3505 06:53:19.845121
3506 06:53:19.848608 RX Delay -40 -> 252, step: 8
3507 06:53:19.852034 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3508 06:53:19.855556 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3509 06:53:19.858835 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3510 06:53:19.865115 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3511 06:53:19.868873 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3512 06:53:19.871861 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3513 06:53:19.875144 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3514 06:53:19.878496 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3515 06:53:19.885224 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3516 06:53:19.888462 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3517 06:53:19.891663 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3518 06:53:19.895182 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3519 06:53:19.898354 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3520 06:53:19.904797 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3521 06:53:19.908914 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3522 06:53:19.912138 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3523 06:53:19.912221 ==
3524 06:53:19.915053 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 06:53:19.918406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 06:53:19.921859 ==
3527 06:53:19.921966 DQS Delay:
3528 06:53:19.922048 DQS0 = 0, DQS1 = 0
3529 06:53:19.925352 DQM Delay:
3530 06:53:19.925435 DQM0 = 120, DQM1 = 112
3531 06:53:19.928167 DQ Delay:
3532 06:53:19.931558 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3533 06:53:19.934851 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3534 06:53:19.938151 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3535 06:53:19.941461 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3536 06:53:19.941544
3537 06:53:19.941610
3538 06:53:19.941671 ==
3539 06:53:19.944885 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 06:53:19.948038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 06:53:19.948122 ==
3542 06:53:19.948187
3543 06:53:19.948249
3544 06:53:19.951570 TX Vref Scan disable
3545 06:53:19.954978 == TX Byte 0 ==
3546 06:53:19.958160 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3547 06:53:19.961896 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3548 06:53:19.964991 == TX Byte 1 ==
3549 06:53:19.968241 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3550 06:53:19.971405 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3551 06:53:19.971488 ==
3552 06:53:19.974719 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 06:53:19.981132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 06:53:19.981215 ==
3555 06:53:19.992159 TX Vref=22, minBit 1, minWin=25, winSum=413
3556 06:53:19.995441 TX Vref=24, minBit 1, minWin=25, winSum=416
3557 06:53:19.998597 TX Vref=26, minBit 1, minWin=25, winSum=420
3558 06:53:20.001886 TX Vref=28, minBit 1, minWin=26, winSum=422
3559 06:53:20.005374 TX Vref=30, minBit 9, minWin=25, winSum=425
3560 06:53:20.011902 TX Vref=32, minBit 9, minWin=25, winSum=423
3561 06:53:20.015403 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 28
3562 06:53:20.015486
3563 06:53:20.018465 Final TX Range 1 Vref 28
3564 06:53:20.018548
3565 06:53:20.018613 ==
3566 06:53:20.021674 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 06:53:20.025008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 06:53:20.025091 ==
3569 06:53:20.028599
3570 06:53:20.028681
3571 06:53:20.028748 TX Vref Scan disable
3572 06:53:20.032110 == TX Byte 0 ==
3573 06:53:20.035356 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3574 06:53:20.038638 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3575 06:53:20.042168 == TX Byte 1 ==
3576 06:53:20.045558 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3577 06:53:20.051740 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3578 06:53:20.051948
3579 06:53:20.052062 [DATLAT]
3580 06:53:20.052159 Freq=1200, CH1 RK1
3581 06:53:20.052252
3582 06:53:20.055309 DATLAT Default: 0xd
3583 06:53:20.055515 0, 0xFFFF, sum = 0
3584 06:53:20.058354 1, 0xFFFF, sum = 0
3585 06:53:20.058533 2, 0xFFFF, sum = 0
3586 06:53:20.061723 3, 0xFFFF, sum = 0
3587 06:53:20.065230 4, 0xFFFF, sum = 0
3588 06:53:20.065472 5, 0xFFFF, sum = 0
3589 06:53:20.068767 6, 0xFFFF, sum = 0
3590 06:53:20.069029 7, 0xFFFF, sum = 0
3591 06:53:20.071825 8, 0xFFFF, sum = 0
3592 06:53:20.072116 9, 0xFFFF, sum = 0
3593 06:53:20.075368 10, 0xFFFF, sum = 0
3594 06:53:20.075672 11, 0xFFFF, sum = 0
3595 06:53:20.078543 12, 0x0, sum = 1
3596 06:53:20.078877 13, 0x0, sum = 2
3597 06:53:20.082165 14, 0x0, sum = 3
3598 06:53:20.082565 15, 0x0, sum = 4
3599 06:53:20.085563 best_step = 13
3600 06:53:20.086073
3601 06:53:20.086395 ==
3602 06:53:20.089051 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 06:53:20.092342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 06:53:20.092912 ==
3605 06:53:20.093286 RX Vref Scan: 0
3606 06:53:20.093628
3607 06:53:20.095507 RX Vref 0 -> 0, step: 1
3608 06:53:20.096066
3609 06:53:20.098774 RX Delay -13 -> 252, step: 4
3610 06:53:20.102395 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3611 06:53:20.108850 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3612 06:53:20.112011 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3613 06:53:20.115537 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3614 06:53:20.118829 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3615 06:53:20.122105 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3616 06:53:20.128706 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3617 06:53:20.132016 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3618 06:53:20.135110 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3619 06:53:20.138161 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3620 06:53:20.141762 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3621 06:53:20.148336 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3622 06:53:20.152100 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3623 06:53:20.154909 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3624 06:53:20.158355 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3625 06:53:20.162049 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3626 06:53:20.165342 ==
3627 06:53:20.168562 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 06:53:20.171433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 06:53:20.171975 ==
3630 06:53:20.172350 DQS Delay:
3631 06:53:20.175335 DQS0 = 0, DQS1 = 0
3632 06:53:20.175794 DQM Delay:
3633 06:53:20.178589 DQM0 = 119, DQM1 = 113
3634 06:53:20.179151 DQ Delay:
3635 06:53:20.181918 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3636 06:53:20.185325 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3637 06:53:20.188287 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3638 06:53:20.191695 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3639 06:53:20.192259
3640 06:53:20.192627
3641 06:53:20.201654 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 406 ps
3642 06:53:20.202260 CH1 RK1: MR19=403, MR18=8EC
3643 06:53:20.208546 CH1_RK1: MR19=0x403, MR18=0x8EC, DQSOSC=406, MR23=63, INC=39, DEC=26
3644 06:53:20.211888 [RxdqsGatingPostProcess] freq 1200
3645 06:53:20.218728 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3646 06:53:20.223654 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 06:53:20.224732 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 06:53:20.228047 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 06:53:20.231576 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 06:53:20.234613 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 06:53:20.235091 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 06:53:20.238063 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 06:53:20.241762 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 06:53:20.245085 Pre-setting of DQS Precalculation
3655 06:53:20.251748 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3656 06:53:20.258317 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3657 06:53:20.265049 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3658 06:53:20.265604
3659 06:53:20.266037
3660 06:53:20.268452 [Calibration Summary] 2400 Mbps
3661 06:53:20.271597 CH 0, Rank 0
3662 06:53:20.272061 SW Impedance : PASS
3663 06:53:20.274620 DUTY Scan : NO K
3664 06:53:20.275095 ZQ Calibration : PASS
3665 06:53:20.278608 Jitter Meter : NO K
3666 06:53:20.281473 CBT Training : PASS
3667 06:53:20.282071 Write leveling : PASS
3668 06:53:20.285336 RX DQS gating : PASS
3669 06:53:20.288307 RX DQ/DQS(RDDQC) : PASS
3670 06:53:20.288879 TX DQ/DQS : PASS
3671 06:53:20.291573 RX DATLAT : PASS
3672 06:53:20.294866 RX DQ/DQS(Engine): PASS
3673 06:53:20.295408 TX OE : NO K
3674 06:53:20.298603 All Pass.
3675 06:53:20.299155
3676 06:53:20.299524 CH 0, Rank 1
3677 06:53:20.301742 SW Impedance : PASS
3678 06:53:20.302454 DUTY Scan : NO K
3679 06:53:20.305105 ZQ Calibration : PASS
3680 06:53:20.308196 Jitter Meter : NO K
3681 06:53:20.308662 CBT Training : PASS
3682 06:53:20.312011 Write leveling : PASS
3683 06:53:20.314733 RX DQS gating : PASS
3684 06:53:20.315199 RX DQ/DQS(RDDQC) : PASS
3685 06:53:20.318330 TX DQ/DQS : PASS
3686 06:53:20.318904 RX DATLAT : PASS
3687 06:53:20.321485 RX DQ/DQS(Engine): PASS
3688 06:53:20.324479 TX OE : NO K
3689 06:53:20.324971 All Pass.
3690 06:53:20.325341
3691 06:53:20.325778 CH 1, Rank 0
3692 06:53:20.327769 SW Impedance : PASS
3693 06:53:20.331622 DUTY Scan : NO K
3694 06:53:20.332199 ZQ Calibration : PASS
3695 06:53:20.334595 Jitter Meter : NO K
3696 06:53:20.337981 CBT Training : PASS
3697 06:53:20.338552 Write leveling : PASS
3698 06:53:20.341504 RX DQS gating : PASS
3699 06:53:20.344740 RX DQ/DQS(RDDQC) : PASS
3700 06:53:20.345306 TX DQ/DQS : PASS
3701 06:53:20.348230 RX DATLAT : PASS
3702 06:53:20.351300 RX DQ/DQS(Engine): PASS
3703 06:53:20.351768 TX OE : NO K
3704 06:53:20.354423 All Pass.
3705 06:53:20.354962
3706 06:53:20.355522 CH 1, Rank 1
3707 06:53:20.358049 SW Impedance : PASS
3708 06:53:20.358618 DUTY Scan : NO K
3709 06:53:20.361095 ZQ Calibration : PASS
3710 06:53:20.364963 Jitter Meter : NO K
3711 06:53:20.365527 CBT Training : PASS
3712 06:53:20.368134 Write leveling : PASS
3713 06:53:20.368698 RX DQS gating : PASS
3714 06:53:20.371393 RX DQ/DQS(RDDQC) : PASS
3715 06:53:20.374466 TX DQ/DQS : PASS
3716 06:53:20.374936 RX DATLAT : PASS
3717 06:53:20.377854 RX DQ/DQS(Engine): PASS
3718 06:53:20.381366 TX OE : NO K
3719 06:53:20.381983 All Pass.
3720 06:53:20.382385
3721 06:53:20.384853 DramC Write-DBI off
3722 06:53:20.385419 PER_BANK_REFRESH: Hybrid Mode
3723 06:53:20.387679 TX_TRACKING: ON
3724 06:53:20.397811 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3725 06:53:20.401384 [FAST_K] Save calibration result to emmc
3726 06:53:20.404466 dramc_set_vcore_voltage set vcore to 650000
3727 06:53:20.404937 Read voltage for 600, 5
3728 06:53:20.407539 Vio18 = 0
3729 06:53:20.408007 Vcore = 650000
3730 06:53:20.408379 Vdram = 0
3731 06:53:20.411094 Vddq = 0
3732 06:53:20.411653 Vmddr = 0
3733 06:53:20.414264 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3734 06:53:20.421743 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3735 06:53:20.424663 MEM_TYPE=3, freq_sel=19
3736 06:53:20.428143 sv_algorithm_assistance_LP4_1600
3737 06:53:20.431382 ============ PULL DRAM RESETB DOWN ============
3738 06:53:20.434774 ========== PULL DRAM RESETB DOWN end =========
3739 06:53:20.438107 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3740 06:53:20.441354 ===================================
3741 06:53:20.444772 LPDDR4 DRAM CONFIGURATION
3742 06:53:20.448195 ===================================
3743 06:53:20.451545 EX_ROW_EN[0] = 0x0
3744 06:53:20.452106 EX_ROW_EN[1] = 0x0
3745 06:53:20.454722 LP4Y_EN = 0x0
3746 06:53:20.455180 WORK_FSP = 0x0
3747 06:53:20.457967 WL = 0x2
3748 06:53:20.458525 RL = 0x2
3749 06:53:20.461534 BL = 0x2
3750 06:53:20.462128 RPST = 0x0
3751 06:53:20.464912 RD_PRE = 0x0
3752 06:53:20.465481 WR_PRE = 0x1
3753 06:53:20.467916 WR_PST = 0x0
3754 06:53:20.471102 DBI_WR = 0x0
3755 06:53:20.471777 DBI_RD = 0x0
3756 06:53:20.474290 OTF = 0x1
3757 06:53:20.477777 ===================================
3758 06:53:20.480961 ===================================
3759 06:53:20.481463 ANA top config
3760 06:53:20.484364 ===================================
3761 06:53:20.487739 DLL_ASYNC_EN = 0
3762 06:53:20.488201 ALL_SLAVE_EN = 1
3763 06:53:20.490975 NEW_RANK_MODE = 1
3764 06:53:20.494046 DLL_IDLE_MODE = 1
3765 06:53:20.497596 LP45_APHY_COMB_EN = 1
3766 06:53:20.501447 TX_ODT_DIS = 1
3767 06:53:20.502065 NEW_8X_MODE = 1
3768 06:53:20.504326 ===================================
3769 06:53:20.507386 ===================================
3770 06:53:20.510717 data_rate = 1200
3771 06:53:20.514451 CKR = 1
3772 06:53:20.517810 DQ_P2S_RATIO = 8
3773 06:53:20.521484 ===================================
3774 06:53:20.524086 CA_P2S_RATIO = 8
3775 06:53:20.527482 DQ_CA_OPEN = 0
3776 06:53:20.527944 DQ_SEMI_OPEN = 0
3777 06:53:20.531037 CA_SEMI_OPEN = 0
3778 06:53:20.534202 CA_FULL_RATE = 0
3779 06:53:20.537428 DQ_CKDIV4_EN = 1
3780 06:53:20.540927 CA_CKDIV4_EN = 1
3781 06:53:20.544404 CA_PREDIV_EN = 0
3782 06:53:20.544964 PH8_DLY = 0
3783 06:53:20.547683 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3784 06:53:20.551095 DQ_AAMCK_DIV = 4
3785 06:53:20.554543 CA_AAMCK_DIV = 4
3786 06:53:20.557512 CA_ADMCK_DIV = 4
3787 06:53:20.561288 DQ_TRACK_CA_EN = 0
3788 06:53:20.561847 CA_PICK = 600
3789 06:53:20.564589 CA_MCKIO = 600
3790 06:53:20.567263 MCKIO_SEMI = 0
3791 06:53:20.571023 PLL_FREQ = 2288
3792 06:53:20.574081 DQ_UI_PI_RATIO = 32
3793 06:53:20.577300 CA_UI_PI_RATIO = 0
3794 06:53:20.580804 ===================================
3795 06:53:20.584201 ===================================
3796 06:53:20.584767 memory_type:LPDDR4
3797 06:53:20.587201 GP_NUM : 10
3798 06:53:20.590461 SRAM_EN : 1
3799 06:53:20.590928 MD32_EN : 0
3800 06:53:20.593987 ===================================
3801 06:53:20.597628 [ANA_INIT] >>>>>>>>>>>>>>
3802 06:53:20.600560 <<<<<< [CONFIGURE PHASE]: ANA_TX
3803 06:53:20.603695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3804 06:53:20.607125 ===================================
3805 06:53:20.610490 data_rate = 1200,PCW = 0X5800
3806 06:53:20.614081 ===================================
3807 06:53:20.617129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3808 06:53:20.620509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 06:53:20.627126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3810 06:53:20.630489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3811 06:53:20.636984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3812 06:53:20.640151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3813 06:53:20.640617 [ANA_INIT] flow start
3814 06:53:20.643969 [ANA_INIT] PLL >>>>>>>>
3815 06:53:20.647116 [ANA_INIT] PLL <<<<<<<<
3816 06:53:20.647691 [ANA_INIT] MIDPI >>>>>>>>
3817 06:53:20.650111 [ANA_INIT] MIDPI <<<<<<<<
3818 06:53:20.653199 [ANA_INIT] DLL >>>>>>>>
3819 06:53:20.653670 [ANA_INIT] flow end
3820 06:53:20.656555 ============ LP4 DIFF to SE enter ============
3821 06:53:20.663842 ============ LP4 DIFF to SE exit ============
3822 06:53:20.664420 [ANA_INIT] <<<<<<<<<<<<<
3823 06:53:20.666827 [Flow] Enable top DCM control >>>>>
3824 06:53:20.670106 [Flow] Enable top DCM control <<<<<
3825 06:53:20.673874 Enable DLL master slave shuffle
3826 06:53:20.680501 ==============================================================
3827 06:53:20.683356 Gating Mode config
3828 06:53:20.686591 ==============================================================
3829 06:53:20.690811 Config description:
3830 06:53:20.700225 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3831 06:53:20.706807 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3832 06:53:20.710296 SELPH_MODE 0: By rank 1: By Phase
3833 06:53:20.716569 ==============================================================
3834 06:53:20.720122 GAT_TRACK_EN = 1
3835 06:53:20.720721 RX_GATING_MODE = 2
3836 06:53:20.723457 RX_GATING_TRACK_MODE = 2
3837 06:53:20.726590 SELPH_MODE = 1
3838 06:53:20.729849 PICG_EARLY_EN = 1
3839 06:53:20.733111 VALID_LAT_VALUE = 1
3840 06:53:20.739766 ==============================================================
3841 06:53:20.743117 Enter into Gating configuration >>>>
3842 06:53:20.746744 Exit from Gating configuration <<<<
3843 06:53:20.750025 Enter into DVFS_PRE_config >>>>>
3844 06:53:20.759745 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3845 06:53:20.763089 Exit from DVFS_PRE_config <<<<<
3846 06:53:20.766708 Enter into PICG configuration >>>>
3847 06:53:20.769988 Exit from PICG configuration <<<<
3848 06:53:20.773063 [RX_INPUT] configuration >>>>>
3849 06:53:20.776600 [RX_INPUT] configuration <<<<<
3850 06:53:20.779716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3851 06:53:20.786289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3852 06:53:20.792886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 06:53:20.796115 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 06:53:20.802851 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 06:53:20.809445 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 06:53:20.812903 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3857 06:53:20.819205 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3858 06:53:20.822708 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3859 06:53:20.825643 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3860 06:53:20.829172 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3861 06:53:20.835819 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 06:53:20.839012 ===================================
3863 06:53:20.839095 LPDDR4 DRAM CONFIGURATION
3864 06:53:20.842483 ===================================
3865 06:53:20.846027 EX_ROW_EN[0] = 0x0
3866 06:53:20.849487 EX_ROW_EN[1] = 0x0
3867 06:53:20.849929 LP4Y_EN = 0x0
3868 06:53:20.852891 WORK_FSP = 0x0
3869 06:53:20.853309 WL = 0x2
3870 06:53:20.856177 RL = 0x2
3871 06:53:20.856647 BL = 0x2
3872 06:53:20.859929 RPST = 0x0
3873 06:53:20.860456 RD_PRE = 0x0
3874 06:53:20.862974 WR_PRE = 0x1
3875 06:53:20.863396 WR_PST = 0x0
3876 06:53:20.866366 DBI_WR = 0x0
3877 06:53:20.866788 DBI_RD = 0x0
3878 06:53:20.869230 OTF = 0x1
3879 06:53:20.872784 ===================================
3880 06:53:20.875714 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3881 06:53:20.879316 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3882 06:53:20.885737 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3883 06:53:20.889252 ===================================
3884 06:53:20.889676 LPDDR4 DRAM CONFIGURATION
3885 06:53:20.892498 ===================================
3886 06:53:20.896354 EX_ROW_EN[0] = 0x10
3887 06:53:20.899551 EX_ROW_EN[1] = 0x0
3888 06:53:20.900071 LP4Y_EN = 0x0
3889 06:53:20.902749 WORK_FSP = 0x0
3890 06:53:20.903174 WL = 0x2
3891 06:53:20.906199 RL = 0x2
3892 06:53:20.906644 BL = 0x2
3893 06:53:20.908906 RPST = 0x0
3894 06:53:20.909329 RD_PRE = 0x0
3895 06:53:20.912391 WR_PRE = 0x1
3896 06:53:20.912937 WR_PST = 0x0
3897 06:53:20.915537 DBI_WR = 0x0
3898 06:53:20.915999 DBI_RD = 0x0
3899 06:53:20.918739 OTF = 0x1
3900 06:53:20.922131 ===================================
3901 06:53:20.928619 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3902 06:53:20.932194 nWR fixed to 30
3903 06:53:20.932623 [ModeRegInit_LP4] CH0 RK0
3904 06:53:20.935544 [ModeRegInit_LP4] CH0 RK1
3905 06:53:20.938829 [ModeRegInit_LP4] CH1 RK0
3906 06:53:20.941847 [ModeRegInit_LP4] CH1 RK1
3907 06:53:20.942403 match AC timing 17
3908 06:53:20.949071 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3909 06:53:20.951956 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3910 06:53:20.955242 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3911 06:53:20.961785 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3912 06:53:20.965086 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3913 06:53:20.965514 ==
3914 06:53:20.968658 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 06:53:20.971761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3916 06:53:20.971845 ==
3917 06:53:20.978248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3918 06:53:20.984801 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3919 06:53:20.987893 [CA 0] Center 35 (5~66) winsize 62
3920 06:53:20.991423 [CA 1] Center 36 (6~67) winsize 62
3921 06:53:20.994828 [CA 2] Center 34 (4~65) winsize 62
3922 06:53:20.998243 [CA 3] Center 34 (4~65) winsize 62
3923 06:53:21.001486 [CA 4] Center 33 (3~64) winsize 62
3924 06:53:21.004581 [CA 5] Center 33 (2~64) winsize 63
3925 06:53:21.004676
3926 06:53:21.008083 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3927 06:53:21.008187
3928 06:53:21.011661 [CATrainingPosCal] consider 1 rank data
3929 06:53:21.014488 u2DelayCellTimex100 = 270/100 ps
3930 06:53:21.018020 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3931 06:53:21.021149 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3932 06:53:21.024702 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3933 06:53:21.027688 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3934 06:53:21.031310 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3935 06:53:21.034632 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3936 06:53:21.034726
3937 06:53:21.041354 CA PerBit enable=1, Macro0, CA PI delay=33
3938 06:53:21.041460
3939 06:53:21.044745 [CBTSetCACLKResult] CA Dly = 33
3940 06:53:21.044851 CS Dly: 5 (0~36)
3941 06:53:21.044939 ==
3942 06:53:21.047726 Dram Type= 6, Freq= 0, CH_0, rank 1
3943 06:53:21.051380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 06:53:21.051505 ==
3945 06:53:21.057598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3946 06:53:21.064189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3947 06:53:21.067712 [CA 0] Center 36 (6~67) winsize 62
3948 06:53:21.071251 [CA 1] Center 36 (6~67) winsize 62
3949 06:53:21.074591 [CA 2] Center 34 (4~65) winsize 62
3950 06:53:21.078040 [CA 3] Center 34 (4~65) winsize 62
3951 06:53:21.081102 [CA 4] Center 34 (3~65) winsize 63
3952 06:53:21.084488 [CA 5] Center 33 (3~64) winsize 62
3953 06:53:21.084915
3954 06:53:21.087688 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3955 06:53:21.088200
3956 06:53:21.091253 [CATrainingPosCal] consider 2 rank data
3957 06:53:21.094761 u2DelayCellTimex100 = 270/100 ps
3958 06:53:21.097855 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3959 06:53:21.101402 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3960 06:53:21.104310 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3961 06:53:21.107981 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3962 06:53:21.111194 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 06:53:21.118025 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3964 06:53:21.118489
3965 06:53:21.121186 CA PerBit enable=1, Macro0, CA PI delay=33
3966 06:53:21.121611
3967 06:53:21.124275 [CBTSetCACLKResult] CA Dly = 33
3968 06:53:21.124772 CS Dly: 5 (0~36)
3969 06:53:21.125114
3970 06:53:21.127541 ----->DramcWriteLeveling(PI) begin...
3971 06:53:21.127972 ==
3972 06:53:21.131149 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 06:53:21.137613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 06:53:21.138123 ==
3975 06:53:21.140985 Write leveling (Byte 0): 33 => 33
3976 06:53:21.141405 Write leveling (Byte 1): 27 => 27
3977 06:53:21.144548 DramcWriteLeveling(PI) end<-----
3978 06:53:21.144966
3979 06:53:21.145299 ==
3980 06:53:21.147773 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 06:53:21.154245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 06:53:21.154663 ==
3983 06:53:21.158231 [Gating] SW mode calibration
3984 06:53:21.164200 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3985 06:53:21.168018 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3986 06:53:21.174829 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 06:53:21.178005 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 06:53:21.181030 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 06:53:21.187679 0 9 12 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
3990 06:53:21.191104 0 9 16 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (0 0)
3991 06:53:21.194217 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 06:53:21.197617 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 06:53:21.204194 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 06:53:21.207442 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 06:53:21.210787 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 06:53:21.217545 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3997 06:53:21.221226 0 10 12 | B1->B0 | 2626 4040 | 0 0 | (1 1) (0 0)
3998 06:53:21.223999 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3999 06:53:21.230728 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 06:53:21.234244 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 06:53:21.237685 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 06:53:21.244282 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 06:53:21.247387 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 06:53:21.250789 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 06:53:21.257453 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4006 06:53:21.260780 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 06:53:21.263930 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 06:53:21.270603 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 06:53:21.274171 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 06:53:21.277071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 06:53:21.283938 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 06:53:21.287330 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 06:53:21.290455 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 06:53:21.296731 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 06:53:21.300658 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 06:53:21.303505 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 06:53:21.307210 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 06:53:21.313753 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 06:53:21.317031 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 06:53:21.320306 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4021 06:53:21.326877 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4022 06:53:21.330267 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 06:53:21.333512 Total UI for P1: 0, mck2ui 16
4024 06:53:21.336936 best dqsien dly found for B0: ( 0, 13, 10)
4025 06:53:21.340628 Total UI for P1: 0, mck2ui 16
4026 06:53:21.343604 best dqsien dly found for B1: ( 0, 13, 12)
4027 06:53:21.347127 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4028 06:53:21.350367 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4029 06:53:21.350576
4030 06:53:21.353653 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4031 06:53:21.360607 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4032 06:53:21.360803 [Gating] SW calibration Done
4033 06:53:21.361012 ==
4034 06:53:21.363651 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 06:53:21.369976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 06:53:21.370189 ==
4037 06:53:21.370394 RX Vref Scan: 0
4038 06:53:21.370566
4039 06:53:21.373613 RX Vref 0 -> 0, step: 1
4040 06:53:21.373924
4041 06:53:21.377377 RX Delay -230 -> 252, step: 16
4042 06:53:21.380920 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4043 06:53:21.384299 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4044 06:53:21.387496 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4045 06:53:21.393653 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4046 06:53:21.396918 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4047 06:53:21.400354 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4048 06:53:21.403694 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4049 06:53:21.410337 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4050 06:53:21.413808 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4051 06:53:21.417011 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4052 06:53:21.420345 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4053 06:53:21.423703 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4054 06:53:21.430333 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4055 06:53:21.433554 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4056 06:53:21.436925 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4057 06:53:21.440099 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4058 06:53:21.443663 ==
4059 06:53:21.444309 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 06:53:21.450239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 06:53:21.450799 ==
4062 06:53:21.451299 DQS Delay:
4063 06:53:21.453674 DQS0 = 0, DQS1 = 0
4064 06:53:21.454281 DQM Delay:
4065 06:53:21.456891 DQM0 = 51, DQM1 = 39
4066 06:53:21.457383 DQ Delay:
4067 06:53:21.460788 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4068 06:53:21.463785 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4069 06:53:21.467071 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4070 06:53:21.470061 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4071 06:53:21.470480
4072 06:53:21.470808
4073 06:53:21.471118 ==
4074 06:53:21.473288 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 06:53:21.476847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 06:53:21.477282 ==
4077 06:53:21.477614
4078 06:53:21.477922
4079 06:53:21.479773 TX Vref Scan disable
4080 06:53:21.483658 == TX Byte 0 ==
4081 06:53:21.486812 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4082 06:53:21.490233 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4083 06:53:21.493653 == TX Byte 1 ==
4084 06:53:21.496640 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4085 06:53:21.499680 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4086 06:53:21.500100 ==
4087 06:53:21.502980 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 06:53:21.510005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 06:53:21.510460 ==
4090 06:53:21.510800
4091 06:53:21.511142
4092 06:53:21.511448 TX Vref Scan disable
4093 06:53:21.514412 == TX Byte 0 ==
4094 06:53:21.517472 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4095 06:53:21.524110 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4096 06:53:21.524695 == TX Byte 1 ==
4097 06:53:21.527313 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4098 06:53:21.533914 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4099 06:53:21.534554
4100 06:53:21.534986 [DATLAT]
4101 06:53:21.535459 Freq=600, CH0 RK0
4102 06:53:21.535943
4103 06:53:21.537265 DATLAT Default: 0x9
4104 06:53:21.537818 0, 0xFFFF, sum = 0
4105 06:53:21.540540 1, 0xFFFF, sum = 0
4106 06:53:21.543605 2, 0xFFFF, sum = 0
4107 06:53:21.544068 3, 0xFFFF, sum = 0
4108 06:53:21.547248 4, 0xFFFF, sum = 0
4109 06:53:21.547871 5, 0xFFFF, sum = 0
4110 06:53:21.550357 6, 0xFFFF, sum = 0
4111 06:53:21.550937 7, 0xFFFF, sum = 0
4112 06:53:21.553794 8, 0x0, sum = 1
4113 06:53:21.554439 9, 0x0, sum = 2
4114 06:53:21.555010 10, 0x0, sum = 3
4115 06:53:21.556986 11, 0x0, sum = 4
4116 06:53:21.557528 best_step = 9
4117 06:53:21.558030
4118 06:53:21.558487 ==
4119 06:53:21.560250 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 06:53:21.567081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 06:53:21.567700 ==
4122 06:53:21.568269 RX Vref Scan: 1
4123 06:53:21.568810
4124 06:53:21.570364 RX Vref 0 -> 0, step: 1
4125 06:53:21.570929
4126 06:53:21.573975 RX Delay -179 -> 252, step: 8
4127 06:53:21.574526
4128 06:53:21.576891 Set Vref, RX VrefLevel [Byte0]: 60
4129 06:53:21.580176 [Byte1]: 50
4130 06:53:21.580762
4131 06:53:21.583903 Final RX Vref Byte 0 = 60 to rank0
4132 06:53:21.587078 Final RX Vref Byte 1 = 50 to rank0
4133 06:53:21.590159 Final RX Vref Byte 0 = 60 to rank1
4134 06:53:21.593603 Final RX Vref Byte 1 = 50 to rank1==
4135 06:53:21.596928 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 06:53:21.600744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 06:53:21.601270 ==
4138 06:53:21.603891 DQS Delay:
4139 06:53:21.604412 DQS0 = 0, DQS1 = 0
4140 06:53:21.607436 DQM Delay:
4141 06:53:21.607883 DQM0 = 49, DQM1 = 37
4142 06:53:21.608217 DQ Delay:
4143 06:53:21.610333 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4144 06:53:21.614100 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4145 06:53:21.617216 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4146 06:53:21.620464 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4147 06:53:21.621006
4148 06:53:21.621399
4149 06:53:21.630023 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e59, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4150 06:53:21.633485 CH0 RK0: MR19=808, MR18=5E59
4151 06:53:21.639986 CH0_RK0: MR19=0x808, MR18=0x5E59, DQSOSC=392, MR23=63, INC=170, DEC=113
4152 06:53:21.640412
4153 06:53:21.643905 ----->DramcWriteLeveling(PI) begin...
4154 06:53:21.644337 ==
4155 06:53:21.646914 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 06:53:21.649905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 06:53:21.650477 ==
4158 06:53:21.653286 Write leveling (Byte 0): 32 => 32
4159 06:53:21.656679 Write leveling (Byte 1): 32 => 32
4160 06:53:21.660097 DramcWriteLeveling(PI) end<-----
4161 06:53:21.660645
4162 06:53:21.661200 ==
4163 06:53:21.663336 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 06:53:21.666700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 06:53:21.667301 ==
4166 06:53:21.669993 [Gating] SW mode calibration
4167 06:53:21.676691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4168 06:53:21.683091 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4169 06:53:21.686447 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 06:53:21.689928 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 06:53:21.696297 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 06:53:21.699801 0 9 12 | B1->B0 | 3232 3434 | 1 0 | (1 0) (0 1)
4173 06:53:21.703258 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4174 06:53:21.709673 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 06:53:21.712874 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 06:53:21.716428 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 06:53:21.722903 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 06:53:21.726357 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 06:53:21.729429 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 06:53:21.736106 0 10 12 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
4181 06:53:21.739739 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4182 06:53:21.742926 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 06:53:21.746249 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 06:53:21.753194 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 06:53:21.756009 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 06:53:21.759508 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 06:53:21.766035 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 06:53:21.769691 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4189 06:53:21.772642 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 06:53:21.779967 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 06:53:21.783080 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 06:53:21.786157 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 06:53:21.792621 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 06:53:21.796175 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 06:53:21.799322 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 06:53:21.805856 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 06:53:21.809572 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 06:53:21.812667 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 06:53:21.819669 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 06:53:21.822603 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 06:53:21.826196 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 06:53:21.832675 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 06:53:21.836199 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 06:53:21.839736 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4205 06:53:21.842632 Total UI for P1: 0, mck2ui 16
4206 06:53:21.846363 best dqsien dly found for B1: ( 0, 13, 10)
4207 06:53:21.853322 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 06:53:21.853897 Total UI for P1: 0, mck2ui 16
4209 06:53:21.856302 best dqsien dly found for B0: ( 0, 13, 12)
4210 06:53:21.862579 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4211 06:53:21.866343 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4212 06:53:21.866931
4213 06:53:21.869249 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4214 06:53:21.872359 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4215 06:53:21.876202 [Gating] SW calibration Done
4216 06:53:21.876671 ==
4217 06:53:21.879001 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 06:53:21.882946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 06:53:21.883521 ==
4220 06:53:21.886255 RX Vref Scan: 0
4221 06:53:21.886724
4222 06:53:21.887093 RX Vref 0 -> 0, step: 1
4223 06:53:21.887440
4224 06:53:21.889417 RX Delay -230 -> 252, step: 16
4225 06:53:21.892803 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4226 06:53:21.899463 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4227 06:53:21.902834 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4228 06:53:21.906135 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4229 06:53:21.909202 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4230 06:53:21.916056 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4231 06:53:21.919863 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4232 06:53:21.922789 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4233 06:53:21.926380 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4234 06:53:21.929515 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4235 06:53:21.935656 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4236 06:53:21.939199 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4237 06:53:21.942440 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4238 06:53:21.946139 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4239 06:53:21.952337 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4240 06:53:21.955531 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4241 06:53:21.956063 ==
4242 06:53:21.959005 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 06:53:21.962846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 06:53:21.963313 ==
4245 06:53:21.965920 DQS Delay:
4246 06:53:21.966414 DQS0 = 0, DQS1 = 0
4247 06:53:21.966784 DQM Delay:
4248 06:53:21.968912 DQM0 = 49, DQM1 = 41
4249 06:53:21.969436 DQ Delay:
4250 06:53:21.972197 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4251 06:53:21.975097 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4252 06:53:21.978940 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4253 06:53:21.981857 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4254 06:53:21.982535
4255 06:53:21.983157
4256 06:53:21.983528 ==
4257 06:53:21.985811 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 06:53:21.991690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 06:53:21.992260 ==
4260 06:53:21.992783
4261 06:53:21.993257
4262 06:53:21.993765 TX Vref Scan disable
4263 06:53:21.995630 == TX Byte 0 ==
4264 06:53:21.999038 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4265 06:53:22.005702 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4266 06:53:22.006354 == TX Byte 1 ==
4267 06:53:22.008842 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4268 06:53:22.015815 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4269 06:53:22.016339 ==
4270 06:53:22.018634 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 06:53:22.022164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 06:53:22.022683 ==
4273 06:53:22.023150
4274 06:53:22.023597
4275 06:53:22.025807 TX Vref Scan disable
4276 06:53:22.028761 == TX Byte 0 ==
4277 06:53:22.032441 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4278 06:53:22.035893 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4279 06:53:22.039238 == TX Byte 1 ==
4280 06:53:22.042703 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4281 06:53:22.045595 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4282 06:53:22.046227
4283 06:53:22.046606 [DATLAT]
4284 06:53:22.049334 Freq=600, CH0 RK1
4285 06:53:22.049898
4286 06:53:22.050350 DATLAT Default: 0x9
4287 06:53:22.052243 0, 0xFFFF, sum = 0
4288 06:53:22.055645 1, 0xFFFF, sum = 0
4289 06:53:22.056117 2, 0xFFFF, sum = 0
4290 06:53:22.058765 3, 0xFFFF, sum = 0
4291 06:53:22.059234 4, 0xFFFF, sum = 0
4292 06:53:22.062197 5, 0xFFFF, sum = 0
4293 06:53:22.062663 6, 0xFFFF, sum = 0
4294 06:53:22.065501 7, 0xFFFF, sum = 0
4295 06:53:22.065918 8, 0x0, sum = 1
4296 06:53:22.068685 9, 0x0, sum = 2
4297 06:53:22.069097 10, 0x0, sum = 3
4298 06:53:22.069428 11, 0x0, sum = 4
4299 06:53:22.071819 best_step = 9
4300 06:53:22.072226
4301 06:53:22.072549 ==
4302 06:53:22.075717 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 06:53:22.078977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 06:53:22.079386 ==
4305 06:53:22.081760 RX Vref Scan: 0
4306 06:53:22.082211
4307 06:53:22.082535 RX Vref 0 -> 0, step: 1
4308 06:53:22.084951
4309 06:53:22.085354 RX Delay -179 -> 252, step: 8
4310 06:53:22.093127 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4311 06:53:22.096221 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4312 06:53:22.099600 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4313 06:53:22.103150 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4314 06:53:22.106063 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4315 06:53:22.112565 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4316 06:53:22.116124 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4317 06:53:22.119926 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4318 06:53:22.122812 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4319 06:53:22.126494 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4320 06:53:22.132496 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4321 06:53:22.136064 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4322 06:53:22.139846 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4323 06:53:22.142599 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4324 06:53:22.149471 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4325 06:53:22.153101 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4326 06:53:22.153682 ==
4327 06:53:22.155948 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 06:53:22.159329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 06:53:22.159882 ==
4330 06:53:22.162458 DQS Delay:
4331 06:53:22.162906 DQS0 = 0, DQS1 = 0
4332 06:53:22.163259 DQM Delay:
4333 06:53:22.166354 DQM0 = 48, DQM1 = 41
4334 06:53:22.166908 DQ Delay:
4335 06:53:22.169306 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4336 06:53:22.172782 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4337 06:53:22.176027 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4338 06:53:22.179329 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4339 06:53:22.179870
4340 06:53:22.180222
4341 06:53:22.189219 [DQSOSCAuto] RK1, (LSB)MR18= 0x6835, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4342 06:53:22.192277 CH0 RK1: MR19=808, MR18=6835
4343 06:53:22.195566 CH0_RK1: MR19=0x808, MR18=0x6835, DQSOSC=390, MR23=63, INC=172, DEC=114
4344 06:53:22.199181 [RxdqsGatingPostProcess] freq 600
4345 06:53:22.205937 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4346 06:53:22.208785 Pre-setting of DQS Precalculation
4347 06:53:22.212450 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4348 06:53:22.212938 ==
4349 06:53:22.215514 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 06:53:22.222282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 06:53:22.222735 ==
4352 06:53:22.225814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4353 06:53:22.232141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4354 06:53:22.235817 [CA 0] Center 35 (5~66) winsize 62
4355 06:53:22.239035 [CA 1] Center 35 (5~66) winsize 62
4356 06:53:22.241987 [CA 2] Center 34 (4~65) winsize 62
4357 06:53:22.245265 [CA 3] Center 34 (3~65) winsize 63
4358 06:53:22.248728 [CA 4] Center 34 (3~65) winsize 63
4359 06:53:22.251826 [CA 5] Center 33 (3~64) winsize 62
4360 06:53:22.252044
4361 06:53:22.255308 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4362 06:53:22.255502
4363 06:53:22.258480 [CATrainingPosCal] consider 1 rank data
4364 06:53:22.262038 u2DelayCellTimex100 = 270/100 ps
4365 06:53:22.265792 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4366 06:53:22.268969 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4367 06:53:22.275853 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4368 06:53:22.278751 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4369 06:53:22.282441 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4370 06:53:22.285733 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4371 06:53:22.286237
4372 06:53:22.288790 CA PerBit enable=1, Macro0, CA PI delay=33
4373 06:53:22.289259
4374 06:53:22.292346 [CBTSetCACLKResult] CA Dly = 33
4375 06:53:22.292816 CS Dly: 5 (0~36)
4376 06:53:22.293181 ==
4377 06:53:22.295658 Dram Type= 6, Freq= 0, CH_1, rank 1
4378 06:53:22.302502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 06:53:22.303066 ==
4380 06:53:22.305334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 06:53:22.312065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4382 06:53:22.315821 [CA 0] Center 36 (6~66) winsize 61
4383 06:53:22.318840 [CA 1] Center 35 (5~66) winsize 62
4384 06:53:22.322458 [CA 2] Center 34 (4~65) winsize 62
4385 06:53:22.325823 [CA 3] Center 34 (4~65) winsize 62
4386 06:53:22.328644 [CA 4] Center 34 (4~65) winsize 62
4387 06:53:22.331871 [CA 5] Center 34 (3~65) winsize 63
4388 06:53:22.332339
4389 06:53:22.335217 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4390 06:53:22.335687
4391 06:53:22.338670 [CATrainingPosCal] consider 2 rank data
4392 06:53:22.342226 u2DelayCellTimex100 = 270/100 ps
4393 06:53:22.345150 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4394 06:53:22.351917 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4395 06:53:22.355167 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4396 06:53:22.358915 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4397 06:53:22.362085 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 06:53:22.365438 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 06:53:22.365906
4400 06:53:22.368823 CA PerBit enable=1, Macro0, CA PI delay=33
4401 06:53:22.369381
4402 06:53:22.372096 [CBTSetCACLKResult] CA Dly = 33
4403 06:53:22.375366 CS Dly: 5 (0~36)
4404 06:53:22.375927
4405 06:53:22.378514 ----->DramcWriteLeveling(PI) begin...
4406 06:53:22.379085 ==
4407 06:53:22.382311 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 06:53:22.385309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 06:53:22.385874 ==
4410 06:53:22.388677 Write leveling (Byte 0): 29 => 29
4411 06:53:22.391921 Write leveling (Byte 1): 29 => 29
4412 06:53:22.394820 DramcWriteLeveling(PI) end<-----
4413 06:53:22.395384
4414 06:53:22.395762 ==
4415 06:53:22.398469 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 06:53:22.401556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 06:53:22.402171 ==
4418 06:53:22.404780 [Gating] SW mode calibration
4419 06:53:22.411505 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4420 06:53:22.418284 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4421 06:53:22.421566 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 06:53:22.424884 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 06:53:22.431114 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 06:53:22.434374 0 9 12 | B1->B0 | 2c2c 2727 | 1 0 | (1 0) (0 0)
4425 06:53:22.437646 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 06:53:22.444710 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 06:53:22.448030 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 06:53:22.451406 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 06:53:22.457845 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 06:53:22.461073 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 06:53:22.464348 0 10 8 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
4432 06:53:22.470959 0 10 12 | B1->B0 | 3a3a 3c3c | 0 0 | (0 0) (0 0)
4433 06:53:22.474602 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 06:53:22.477416 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 06:53:22.484543 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 06:53:22.487649 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 06:53:22.490851 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 06:53:22.497803 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 06:53:22.501307 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 06:53:22.504330 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4441 06:53:22.510863 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 06:53:22.514395 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 06:53:22.517511 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 06:53:22.524035 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 06:53:22.527298 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 06:53:22.530670 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 06:53:22.537386 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 06:53:22.540668 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 06:53:22.544442 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 06:53:22.547104 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 06:53:22.554108 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 06:53:22.557716 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 06:53:22.561265 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 06:53:22.567598 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 06:53:22.570860 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4456 06:53:22.574572 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4457 06:53:22.580939 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 06:53:22.581503 Total UI for P1: 0, mck2ui 16
4459 06:53:22.587635 best dqsien dly found for B0: ( 0, 13, 10)
4460 06:53:22.588201 Total UI for P1: 0, mck2ui 16
4461 06:53:22.594465 best dqsien dly found for B1: ( 0, 13, 12)
4462 06:53:22.597652 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4463 06:53:22.600543 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4464 06:53:22.601108
4465 06:53:22.604038 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4466 06:53:22.607490 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4467 06:53:22.610661 [Gating] SW calibration Done
4468 06:53:22.611222 ==
4469 06:53:22.613741 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 06:53:22.617148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 06:53:22.617727 ==
4472 06:53:22.620477 RX Vref Scan: 0
4473 06:53:22.621043
4474 06:53:22.621409 RX Vref 0 -> 0, step: 1
4475 06:53:22.621749
4476 06:53:22.624124 RX Delay -230 -> 252, step: 16
4477 06:53:22.630513 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4478 06:53:22.633547 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4479 06:53:22.637136 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4480 06:53:22.640814 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4481 06:53:22.643979 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4482 06:53:22.650510 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4483 06:53:22.654029 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4484 06:53:22.657295 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4485 06:53:22.660910 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4486 06:53:22.663674 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4487 06:53:22.670827 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4488 06:53:22.674150 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4489 06:53:22.677124 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4490 06:53:22.680839 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4491 06:53:22.686895 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4492 06:53:22.690626 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4493 06:53:22.691197 ==
4494 06:53:22.693572 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 06:53:22.697069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 06:53:22.697636 ==
4497 06:53:22.700559 DQS Delay:
4498 06:53:22.701118 DQS0 = 0, DQS1 = 0
4499 06:53:22.701493 DQM Delay:
4500 06:53:22.703789 DQM0 = 48, DQM1 = 42
4501 06:53:22.704348 DQ Delay:
4502 06:53:22.706992 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4503 06:53:22.710180 DQ4 =41, DQ5 =57, DQ6 =65, DQ7 =41
4504 06:53:22.713538 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4505 06:53:22.717145 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4506 06:53:22.717714
4507 06:53:22.718184
4508 06:53:22.718545 ==
4509 06:53:22.720556 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 06:53:22.726984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 06:53:22.727549 ==
4512 06:53:22.727922
4513 06:53:22.728267
4514 06:53:22.728591 TX Vref Scan disable
4515 06:53:22.730555 == TX Byte 0 ==
4516 06:53:22.734001 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4517 06:53:22.740356 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4518 06:53:22.740929 == TX Byte 1 ==
4519 06:53:22.744041 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4520 06:53:22.750541 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4521 06:53:22.751006 ==
4522 06:53:22.753786 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 06:53:22.757274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 06:53:22.757843 ==
4525 06:53:22.758276
4526 06:53:22.758619
4527 06:53:22.760565 TX Vref Scan disable
4528 06:53:22.763807 == TX Byte 0 ==
4529 06:53:22.766922 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4530 06:53:22.770453 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4531 06:53:22.770916 == TX Byte 1 ==
4532 06:53:22.777278 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4533 06:53:22.780460 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4534 06:53:22.781031
4535 06:53:22.781403 [DATLAT]
4536 06:53:22.783639 Freq=600, CH1 RK0
4537 06:53:22.784104
4538 06:53:22.784472 DATLAT Default: 0x9
4539 06:53:22.787282 0, 0xFFFF, sum = 0
4540 06:53:22.787751 1, 0xFFFF, sum = 0
4541 06:53:22.790270 2, 0xFFFF, sum = 0
4542 06:53:22.793716 3, 0xFFFF, sum = 0
4543 06:53:22.794475 4, 0xFFFF, sum = 0
4544 06:53:22.796738 5, 0xFFFF, sum = 0
4545 06:53:22.797442 6, 0xFFFF, sum = 0
4546 06:53:22.800310 7, 0xFFFF, sum = 0
4547 06:53:22.800932 8, 0x0, sum = 1
4548 06:53:22.801486 9, 0x0, sum = 2
4549 06:53:22.803340 10, 0x0, sum = 3
4550 06:53:22.803878 11, 0x0, sum = 4
4551 06:53:22.807141 best_step = 9
4552 06:53:22.807602
4553 06:53:22.807968 ==
4554 06:53:22.810329 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 06:53:22.813452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 06:53:22.813918 ==
4557 06:53:22.817017 RX Vref Scan: 1
4558 06:53:22.817573
4559 06:53:22.817979 RX Vref 0 -> 0, step: 1
4560 06:53:22.818336
4561 06:53:22.820560 RX Delay -179 -> 252, step: 8
4562 06:53:22.821117
4563 06:53:22.823849 Set Vref, RX VrefLevel [Byte0]: 53
4564 06:53:22.827001 [Byte1]: 49
4565 06:53:22.830746
4566 06:53:22.831258 Final RX Vref Byte 0 = 53 to rank0
4567 06:53:22.834024 Final RX Vref Byte 1 = 49 to rank0
4568 06:53:22.837515 Final RX Vref Byte 0 = 53 to rank1
4569 06:53:22.841006 Final RX Vref Byte 1 = 49 to rank1==
4570 06:53:22.844280 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 06:53:22.851365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 06:53:22.851939 ==
4573 06:53:22.852310 DQS Delay:
4574 06:53:22.852654 DQS0 = 0, DQS1 = 0
4575 06:53:22.854109 DQM Delay:
4576 06:53:22.854569 DQM0 = 46, DQM1 = 39
4577 06:53:22.857330 DQ Delay:
4578 06:53:22.860573 DQ0 =52, DQ1 =44, DQ2 =32, DQ3 =44
4579 06:53:22.864240 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =40
4580 06:53:22.867288 DQ8 =28, DQ9 =24, DQ10 =44, DQ11 =32
4581 06:53:22.871126 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =44
4582 06:53:22.871696
4583 06:53:22.872071
4584 06:53:22.877412 [DQSOSCAuto] RK0, (LSB)MR18= 0x496f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4585 06:53:22.881201 CH1 RK0: MR19=808, MR18=496F
4586 06:53:22.887250 CH1_RK0: MR19=0x808, MR18=0x496F, DQSOSC=389, MR23=63, INC=173, DEC=115
4587 06:53:22.887831
4588 06:53:22.890520 ----->DramcWriteLeveling(PI) begin...
4589 06:53:22.891101 ==
4590 06:53:22.893974 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 06:53:22.897168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 06:53:22.897757 ==
4593 06:53:22.900612 Write leveling (Byte 0): 29 => 29
4594 06:53:22.903979 Write leveling (Byte 1): 31 => 31
4595 06:53:22.907464 DramcWriteLeveling(PI) end<-----
4596 06:53:22.908037
4597 06:53:22.908411 ==
4598 06:53:22.910308 Dram Type= 6, Freq= 0, CH_1, rank 1
4599 06:53:22.913728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 06:53:22.914229 ==
4601 06:53:22.917183 [Gating] SW mode calibration
4602 06:53:22.923881 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4603 06:53:22.930371 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4604 06:53:22.933707 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4605 06:53:22.940143 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 06:53:22.943692 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
4607 06:53:22.946723 0 9 12 | B1->B0 | 2c2c 3131 | 0 1 | (0 1) (0 0)
4608 06:53:22.954003 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 06:53:22.956956 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 06:53:22.960229 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 06:53:22.966761 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 06:53:22.970220 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 06:53:22.973740 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 06:53:22.977076 0 10 8 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
4615 06:53:22.983596 0 10 12 | B1->B0 | 3e3e 3434 | 0 0 | (0 0) (0 0)
4616 06:53:22.986934 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 06:53:22.990352 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 06:53:22.996741 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 06:53:23.000127 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 06:53:23.003497 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 06:53:23.010376 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 06:53:23.013621 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 06:53:23.016933 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4624 06:53:23.023311 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 06:53:23.026838 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 06:53:23.030329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 06:53:23.036921 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 06:53:23.040368 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 06:53:23.043112 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 06:53:23.049812 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 06:53:23.053267 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 06:53:23.056409 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 06:53:23.063219 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 06:53:23.066351 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 06:53:23.069620 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 06:53:23.076635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 06:53:23.080014 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 06:53:23.082966 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 06:53:23.090046 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4640 06:53:23.093375 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 06:53:23.096527 Total UI for P1: 0, mck2ui 16
4642 06:53:23.099812 best dqsien dly found for B0: ( 0, 13, 12)
4643 06:53:23.103234 Total UI for P1: 0, mck2ui 16
4644 06:53:23.106582 best dqsien dly found for B1: ( 0, 13, 12)
4645 06:53:23.109911 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4646 06:53:23.113135 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4647 06:53:23.113713
4648 06:53:23.116453 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4649 06:53:23.119669 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4650 06:53:23.123255 [Gating] SW calibration Done
4651 06:53:23.123833 ==
4652 06:53:23.126866 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 06:53:23.129704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 06:53:23.130309 ==
4655 06:53:23.133122 RX Vref Scan: 0
4656 06:53:23.133697
4657 06:53:23.136485 RX Vref 0 -> 0, step: 1
4658 06:53:23.137059
4659 06:53:23.139271 RX Delay -230 -> 252, step: 16
4660 06:53:23.143254 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4661 06:53:23.146137 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4662 06:53:23.149272 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4663 06:53:23.152979 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4664 06:53:23.159235 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4665 06:53:23.163262 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4666 06:53:23.166412 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4667 06:53:23.169852 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4668 06:53:23.176021 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4669 06:53:23.179444 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4670 06:53:23.183079 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4671 06:53:23.186338 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4672 06:53:23.189620 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4673 06:53:23.196324 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4674 06:53:23.199372 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4675 06:53:23.202717 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4676 06:53:23.203289 ==
4677 06:53:23.206573 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 06:53:23.213148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 06:53:23.213724 ==
4680 06:53:23.214153 DQS Delay:
4681 06:53:23.214507 DQS0 = 0, DQS1 = 0
4682 06:53:23.215985 DQM Delay:
4683 06:53:23.216516 DQM0 = 46, DQM1 = 44
4684 06:53:23.219388 DQ Delay:
4685 06:53:23.222856 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4686 06:53:23.223429 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4687 06:53:23.226051 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4688 06:53:23.232705 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4689 06:53:23.233265
4690 06:53:23.233638
4691 06:53:23.234024 ==
4692 06:53:23.235868 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 06:53:23.239376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 06:53:23.239857 ==
4695 06:53:23.240231
4696 06:53:23.240576
4697 06:53:23.242601 TX Vref Scan disable
4698 06:53:23.243067 == TX Byte 0 ==
4699 06:53:23.249375 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4700 06:53:23.252458 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4701 06:53:23.253034 == TX Byte 1 ==
4702 06:53:23.259145 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4703 06:53:23.262322 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4704 06:53:23.262797 ==
4705 06:53:23.265490 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 06:53:23.269385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 06:53:23.270019 ==
4708 06:53:23.270410
4709 06:53:23.270759
4710 06:53:23.272719 TX Vref Scan disable
4711 06:53:23.276096 == TX Byte 0 ==
4712 06:53:23.278662 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4713 06:53:23.285498 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4714 06:53:23.286114 == TX Byte 1 ==
4715 06:53:23.288890 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4716 06:53:23.295456 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4717 06:53:23.296033
4718 06:53:23.296410 [DATLAT]
4719 06:53:23.296761 Freq=600, CH1 RK1
4720 06:53:23.297092
4721 06:53:23.298564 DATLAT Default: 0x9
4722 06:53:23.299029 0, 0xFFFF, sum = 0
4723 06:53:23.302499 1, 0xFFFF, sum = 0
4724 06:53:23.303084 2, 0xFFFF, sum = 0
4725 06:53:23.305454 3, 0xFFFF, sum = 0
4726 06:53:23.308858 4, 0xFFFF, sum = 0
4727 06:53:23.309444 5, 0xFFFF, sum = 0
4728 06:53:23.311980 6, 0xFFFF, sum = 0
4729 06:53:23.312462 7, 0xFFFF, sum = 0
4730 06:53:23.312838 8, 0x0, sum = 1
4731 06:53:23.315599 9, 0x0, sum = 2
4732 06:53:23.316180 10, 0x0, sum = 3
4733 06:53:23.319047 11, 0x0, sum = 4
4734 06:53:23.319628 best_step = 9
4735 06:53:23.320006
4736 06:53:23.320446 ==
4737 06:53:23.322526 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 06:53:23.328946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 06:53:23.329525 ==
4740 06:53:23.329905 RX Vref Scan: 0
4741 06:53:23.330289
4742 06:53:23.331773 RX Vref 0 -> 0, step: 1
4743 06:53:23.332242
4744 06:53:23.335508 RX Delay -179 -> 252, step: 8
4745 06:53:23.339115 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4746 06:53:23.345291 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4747 06:53:23.348714 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4748 06:53:23.352131 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4749 06:53:23.355238 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4750 06:53:23.358692 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4751 06:53:23.365346 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4752 06:53:23.368779 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4753 06:53:23.371663 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4754 06:53:23.375463 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4755 06:53:23.378371 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4756 06:53:23.385641 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4757 06:53:23.388535 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4758 06:53:23.392092 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4759 06:53:23.395256 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4760 06:53:23.402147 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4761 06:53:23.402723 ==
4762 06:53:23.405232 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 06:53:23.408831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 06:53:23.409413 ==
4765 06:53:23.409790 DQS Delay:
4766 06:53:23.412237 DQS0 = 0, DQS1 = 0
4767 06:53:23.412727 DQM Delay:
4768 06:53:23.415414 DQM0 = 46, DQM1 = 39
4769 06:53:23.415953 DQ Delay:
4770 06:53:23.418687 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4771 06:53:23.421864 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =44
4772 06:53:23.425126 DQ8 =28, DQ9 =32, DQ10 =40, DQ11 =32
4773 06:53:23.428914 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4774 06:53:23.429488
4775 06:53:23.429862
4776 06:53:23.435157 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4777 06:53:23.438312 CH1 RK1: MR19=808, MR18=5C22
4778 06:53:23.445167 CH1_RK1: MR19=0x808, MR18=0x5C22, DQSOSC=392, MR23=63, INC=170, DEC=113
4779 06:53:23.448282 [RxdqsGatingPostProcess] freq 600
4780 06:53:23.454724 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4781 06:53:23.458386 Pre-setting of DQS Precalculation
4782 06:53:23.461750 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4783 06:53:23.468402 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4784 06:53:23.474670 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4785 06:53:23.475248
4786 06:53:23.475623
4787 06:53:23.478055 [Calibration Summary] 1200 Mbps
4788 06:53:23.481577 CH 0, Rank 0
4789 06:53:23.482180 SW Impedance : PASS
4790 06:53:23.484939 DUTY Scan : NO K
4791 06:53:23.488107 ZQ Calibration : PASS
4792 06:53:23.488670 Jitter Meter : NO K
4793 06:53:23.491443 CBT Training : PASS
4794 06:53:23.494356 Write leveling : PASS
4795 06:53:23.494827 RX DQS gating : PASS
4796 06:53:23.497851 RX DQ/DQS(RDDQC) : PASS
4797 06:53:23.501223 TX DQ/DQS : PASS
4798 06:53:23.501799 RX DATLAT : PASS
4799 06:53:23.504759 RX DQ/DQS(Engine): PASS
4800 06:53:23.507890 TX OE : NO K
4801 06:53:23.508361 All Pass.
4802 06:53:23.508734
4803 06:53:23.509082 CH 0, Rank 1
4804 06:53:23.511043 SW Impedance : PASS
4805 06:53:23.514865 DUTY Scan : NO K
4806 06:53:23.515427 ZQ Calibration : PASS
4807 06:53:23.518070 Jitter Meter : NO K
4808 06:53:23.518626 CBT Training : PASS
4809 06:53:23.521161 Write leveling : PASS
4810 06:53:23.524577 RX DQS gating : PASS
4811 06:53:23.525147 RX DQ/DQS(RDDQC) : PASS
4812 06:53:23.528193 TX DQ/DQS : PASS
4813 06:53:23.531341 RX DATLAT : PASS
4814 06:53:23.531906 RX DQ/DQS(Engine): PASS
4815 06:53:23.534577 TX OE : NO K
4816 06:53:23.535135 All Pass.
4817 06:53:23.535512
4818 06:53:23.537831 CH 1, Rank 0
4819 06:53:23.538440 SW Impedance : PASS
4820 06:53:23.541350 DUTY Scan : NO K
4821 06:53:23.544470 ZQ Calibration : PASS
4822 06:53:23.545035 Jitter Meter : NO K
4823 06:53:23.547630 CBT Training : PASS
4824 06:53:23.551019 Write leveling : PASS
4825 06:53:23.551580 RX DQS gating : PASS
4826 06:53:23.554068 RX DQ/DQS(RDDQC) : PASS
4827 06:53:23.558013 TX DQ/DQS : PASS
4828 06:53:23.558575 RX DATLAT : PASS
4829 06:53:23.561015 RX DQ/DQS(Engine): PASS
4830 06:53:23.564634 TX OE : NO K
4831 06:53:23.565203 All Pass.
4832 06:53:23.565577
4833 06:53:23.566037 CH 1, Rank 1
4834 06:53:23.567640 SW Impedance : PASS
4835 06:53:23.570893 DUTY Scan : NO K
4836 06:53:23.571484 ZQ Calibration : PASS
4837 06:53:23.574210 Jitter Meter : NO K
4838 06:53:23.577346 CBT Training : PASS
4839 06:53:23.577904 Write leveling : PASS
4840 06:53:23.580693 RX DQS gating : PASS
4841 06:53:23.581255 RX DQ/DQS(RDDQC) : PASS
4842 06:53:23.584053 TX DQ/DQS : PASS
4843 06:53:23.587962 RX DATLAT : PASS
4844 06:53:23.588526 RX DQ/DQS(Engine): PASS
4845 06:53:23.590451 TX OE : NO K
4846 06:53:23.590914 All Pass.
4847 06:53:23.591282
4848 06:53:23.593832 DramC Write-DBI off
4849 06:53:23.597216 PER_BANK_REFRESH: Hybrid Mode
4850 06:53:23.597835 TX_TRACKING: ON
4851 06:53:23.607080 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4852 06:53:23.610203 [FAST_K] Save calibration result to emmc
4853 06:53:23.613853 dramc_set_vcore_voltage set vcore to 662500
4854 06:53:23.617167 Read voltage for 933, 3
4855 06:53:23.617722 Vio18 = 0
4856 06:53:23.620106 Vcore = 662500
4857 06:53:23.620566 Vdram = 0
4858 06:53:23.620932 Vddq = 0
4859 06:53:23.621275 Vmddr = 0
4860 06:53:23.626831 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4861 06:53:23.630635 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4862 06:53:23.633723 MEM_TYPE=3, freq_sel=17
4863 06:53:23.636946 sv_algorithm_assistance_LP4_1600
4864 06:53:23.639841 ============ PULL DRAM RESETB DOWN ============
4865 06:53:23.646791 ========== PULL DRAM RESETB DOWN end =========
4866 06:53:23.649901 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4867 06:53:23.653287 ===================================
4868 06:53:23.656298 LPDDR4 DRAM CONFIGURATION
4869 06:53:23.660137 ===================================
4870 06:53:23.660725 EX_ROW_EN[0] = 0x0
4871 06:53:23.663301 EX_ROW_EN[1] = 0x0
4872 06:53:23.663866 LP4Y_EN = 0x0
4873 06:53:23.666650 WORK_FSP = 0x0
4874 06:53:23.667109 WL = 0x3
4875 06:53:23.669731 RL = 0x3
4876 06:53:23.673075 BL = 0x2
4877 06:53:23.673639 RPST = 0x0
4878 06:53:23.676590 RD_PRE = 0x0
4879 06:53:23.677162 WR_PRE = 0x1
4880 06:53:23.680030 WR_PST = 0x0
4881 06:53:23.680612 DBI_WR = 0x0
4882 06:53:23.682760 DBI_RD = 0x0
4883 06:53:23.683224 OTF = 0x1
4884 06:53:23.686449 ===================================
4885 06:53:23.690085 ===================================
4886 06:53:23.693220 ANA top config
4887 06:53:23.696301 ===================================
4888 06:53:23.696882 DLL_ASYNC_EN = 0
4889 06:53:23.699245 ALL_SLAVE_EN = 1
4890 06:53:23.702642 NEW_RANK_MODE = 1
4891 06:53:23.706237 DLL_IDLE_MODE = 1
4892 06:53:23.706937 LP45_APHY_COMB_EN = 1
4893 06:53:23.709503 TX_ODT_DIS = 1
4894 06:53:23.712747 NEW_8X_MODE = 1
4895 06:53:23.716200 ===================================
4896 06:53:23.719301 ===================================
4897 06:53:23.722646 data_rate = 1866
4898 06:53:23.725892 CKR = 1
4899 06:53:23.729561 DQ_P2S_RATIO = 8
4900 06:53:23.732484 ===================================
4901 06:53:23.733063 CA_P2S_RATIO = 8
4902 06:53:23.735726 DQ_CA_OPEN = 0
4903 06:53:23.738938 DQ_SEMI_OPEN = 0
4904 06:53:23.742262 CA_SEMI_OPEN = 0
4905 06:53:23.745992 CA_FULL_RATE = 0
4906 06:53:23.749098 DQ_CKDIV4_EN = 1
4907 06:53:23.749661 CA_CKDIV4_EN = 1
4908 06:53:23.752251 CA_PREDIV_EN = 0
4909 06:53:23.755600 PH8_DLY = 0
4910 06:53:23.758679 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4911 06:53:23.762313 DQ_AAMCK_DIV = 4
4912 06:53:23.765456 CA_AAMCK_DIV = 4
4913 06:53:23.766076 CA_ADMCK_DIV = 4
4914 06:53:23.768791 DQ_TRACK_CA_EN = 0
4915 06:53:23.772301 CA_PICK = 933
4916 06:53:23.775815 CA_MCKIO = 933
4917 06:53:23.778721 MCKIO_SEMI = 0
4918 06:53:23.782246 PLL_FREQ = 3732
4919 06:53:23.785706 DQ_UI_PI_RATIO = 32
4920 06:53:23.786343 CA_UI_PI_RATIO = 0
4921 06:53:23.788951 ===================================
4922 06:53:23.792191 ===================================
4923 06:53:23.795629 memory_type:LPDDR4
4924 06:53:23.798588 GP_NUM : 10
4925 06:53:23.799056 SRAM_EN : 1
4926 06:53:23.802163 MD32_EN : 0
4927 06:53:23.805658 ===================================
4928 06:53:23.809278 [ANA_INIT] >>>>>>>>>>>>>>
4929 06:53:23.812029 <<<<<< [CONFIGURE PHASE]: ANA_TX
4930 06:53:23.815081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4931 06:53:23.818545 ===================================
4932 06:53:23.819017 data_rate = 1866,PCW = 0X8f00
4933 06:53:23.821664 ===================================
4934 06:53:23.825174 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4935 06:53:23.831501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4936 06:53:23.838417 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 06:53:23.842065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4938 06:53:23.845066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4939 06:53:23.848666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4940 06:53:23.851576 [ANA_INIT] flow start
4941 06:53:23.854960 [ANA_INIT] PLL >>>>>>>>
4942 06:53:23.855533 [ANA_INIT] PLL <<<<<<<<
4943 06:53:23.858141 [ANA_INIT] MIDPI >>>>>>>>
4944 06:53:23.861834 [ANA_INIT] MIDPI <<<<<<<<
4945 06:53:23.862462 [ANA_INIT] DLL >>>>>>>>
4946 06:53:23.865294 [ANA_INIT] flow end
4947 06:53:23.868158 ============ LP4 DIFF to SE enter ============
4948 06:53:23.871937 ============ LP4 DIFF to SE exit ============
4949 06:53:23.875049 [ANA_INIT] <<<<<<<<<<<<<
4950 06:53:23.878392 [Flow] Enable top DCM control >>>>>
4951 06:53:23.881446 [Flow] Enable top DCM control <<<<<
4952 06:53:23.884568 Enable DLL master slave shuffle
4953 06:53:23.891625 ==============================================================
4954 06:53:23.892097 Gating Mode config
4955 06:53:23.897968 ==============================================================
4956 06:53:23.898446 Config description:
4957 06:53:23.907932 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4958 06:53:23.914599 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4959 06:53:23.921165 SELPH_MODE 0: By rank 1: By Phase
4960 06:53:23.924608 ==============================================================
4961 06:53:23.927942 GAT_TRACK_EN = 1
4962 06:53:23.931254 RX_GATING_MODE = 2
4963 06:53:23.934585 RX_GATING_TRACK_MODE = 2
4964 06:53:23.937983 SELPH_MODE = 1
4965 06:53:23.941477 PICG_EARLY_EN = 1
4966 06:53:23.944792 VALID_LAT_VALUE = 1
4967 06:53:23.951082 ==============================================================
4968 06:53:23.954638 Enter into Gating configuration >>>>
4969 06:53:23.957656 Exit from Gating configuration <<<<
4970 06:53:23.961124 Enter into DVFS_PRE_config >>>>>
4971 06:53:23.971322 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4972 06:53:23.974479 Exit from DVFS_PRE_config <<<<<
4973 06:53:23.978053 Enter into PICG configuration >>>>
4974 06:53:23.981222 Exit from PICG configuration <<<<
4975 06:53:23.984568 [RX_INPUT] configuration >>>>>
4976 06:53:23.985145 [RX_INPUT] configuration <<<<<
4977 06:53:23.991291 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4978 06:53:23.997978 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4979 06:53:24.001239 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 06:53:24.007494 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 06:53:24.014405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4982 06:53:24.021003 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4983 06:53:24.024686 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4984 06:53:24.028123 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4985 06:53:24.034284 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4986 06:53:24.037641 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4987 06:53:24.040867 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4988 06:53:24.044389 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 06:53:24.047670 ===================================
4990 06:53:24.050787 LPDDR4 DRAM CONFIGURATION
4991 06:53:24.053846 ===================================
4992 06:53:24.057646 EX_ROW_EN[0] = 0x0
4993 06:53:24.058153 EX_ROW_EN[1] = 0x0
4994 06:53:24.060662 LP4Y_EN = 0x0
4995 06:53:24.061130 WORK_FSP = 0x0
4996 06:53:24.064068 WL = 0x3
4997 06:53:24.064564 RL = 0x3
4998 06:53:24.067674 BL = 0x2
4999 06:53:24.068142 RPST = 0x0
5000 06:53:24.071106 RD_PRE = 0x0
5001 06:53:24.071600 WR_PRE = 0x1
5002 06:53:24.074158 WR_PST = 0x0
5003 06:53:24.077271 DBI_WR = 0x0
5004 06:53:24.077732 DBI_RD = 0x0
5005 06:53:24.080629 OTF = 0x1
5006 06:53:24.084077 ===================================
5007 06:53:24.087671 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5008 06:53:24.090953 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5009 06:53:24.094005 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 06:53:24.097695 ===================================
5011 06:53:24.100567 LPDDR4 DRAM CONFIGURATION
5012 06:53:24.104388 ===================================
5013 06:53:24.107500 EX_ROW_EN[0] = 0x10
5014 06:53:24.108060 EX_ROW_EN[1] = 0x0
5015 06:53:24.110614 LP4Y_EN = 0x0
5016 06:53:24.111084 WORK_FSP = 0x0
5017 06:53:24.113829 WL = 0x3
5018 06:53:24.114336 RL = 0x3
5019 06:53:24.117146 BL = 0x2
5020 06:53:24.117609 RPST = 0x0
5021 06:53:24.120998 RD_PRE = 0x0
5022 06:53:24.121560 WR_PRE = 0x1
5023 06:53:24.123800 WR_PST = 0x0
5024 06:53:24.124268 DBI_WR = 0x0
5025 06:53:24.127674 DBI_RD = 0x0
5026 06:53:24.128237 OTF = 0x1
5027 06:53:24.130676 ===================================
5028 06:53:24.137310 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5029 06:53:24.142021 nWR fixed to 30
5030 06:53:24.145531 [ModeRegInit_LP4] CH0 RK0
5031 06:53:24.146067 [ModeRegInit_LP4] CH0 RK1
5032 06:53:24.149080 [ModeRegInit_LP4] CH1 RK0
5033 06:53:24.152009 [ModeRegInit_LP4] CH1 RK1
5034 06:53:24.152573 match AC timing 9
5035 06:53:24.159138 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5036 06:53:24.162004 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5037 06:53:24.165981 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5038 06:53:24.172307 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5039 06:53:24.175322 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5040 06:53:24.175794 ==
5041 06:53:24.178402 Dram Type= 6, Freq= 0, CH_0, rank 0
5042 06:53:24.182099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5043 06:53:24.182572 ==
5044 06:53:24.188753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5045 06:53:24.195309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5046 06:53:24.198650 [CA 0] Center 37 (7~68) winsize 62
5047 06:53:24.201759 [CA 1] Center 38 (7~69) winsize 63
5048 06:53:24.205433 [CA 2] Center 35 (5~65) winsize 61
5049 06:53:24.208830 [CA 3] Center 34 (4~65) winsize 62
5050 06:53:24.211967 [CA 4] Center 34 (4~64) winsize 61
5051 06:53:24.214787 [CA 5] Center 33 (3~64) winsize 62
5052 06:53:24.215254
5053 06:53:24.218763 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5054 06:53:24.219325
5055 06:53:24.221778 [CATrainingPosCal] consider 1 rank data
5056 06:53:24.225286 u2DelayCellTimex100 = 270/100 ps
5057 06:53:24.228250 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5058 06:53:24.231565 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5059 06:53:24.235238 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5060 06:53:24.237977 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5061 06:53:24.241381 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5062 06:53:24.248066 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5063 06:53:24.248540
5064 06:53:24.251318 CA PerBit enable=1, Macro0, CA PI delay=33
5065 06:53:24.251789
5066 06:53:24.254739 [CBTSetCACLKResult] CA Dly = 33
5067 06:53:24.255209 CS Dly: 7 (0~38)
5068 06:53:24.255581 ==
5069 06:53:24.257982 Dram Type= 6, Freq= 0, CH_0, rank 1
5070 06:53:24.261340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5071 06:53:24.264997 ==
5072 06:53:24.268102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5073 06:53:24.275036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5074 06:53:24.277830 [CA 0] Center 38 (7~69) winsize 63
5075 06:53:24.281677 [CA 1] Center 38 (7~69) winsize 63
5076 06:53:24.284829 [CA 2] Center 35 (5~66) winsize 62
5077 06:53:24.288132 [CA 3] Center 35 (5~66) winsize 62
5078 06:53:24.291338 [CA 4] Center 34 (4~65) winsize 62
5079 06:53:24.294862 [CA 5] Center 34 (4~64) winsize 61
5080 06:53:24.295426
5081 06:53:24.297817 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5082 06:53:24.298470
5083 06:53:24.301777 [CATrainingPosCal] consider 2 rank data
5084 06:53:24.304565 u2DelayCellTimex100 = 270/100 ps
5085 06:53:24.307791 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5086 06:53:24.310942 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5087 06:53:24.314614 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5088 06:53:24.321246 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5089 06:53:24.324511 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5090 06:53:24.327630 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5091 06:53:24.328193
5092 06:53:24.331499 CA PerBit enable=1, Macro0, CA PI delay=34
5093 06:53:24.332069
5094 06:53:24.334147 [CBTSetCACLKResult] CA Dly = 34
5095 06:53:24.334610 CS Dly: 7 (0~39)
5096 06:53:24.334981
5097 06:53:24.337448 ----->DramcWriteLeveling(PI) begin...
5098 06:53:24.337922 ==
5099 06:53:24.341455 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 06:53:24.347783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 06:53:24.348256 ==
5102 06:53:24.350845 Write leveling (Byte 0): 33 => 33
5103 06:53:24.354033 Write leveling (Byte 1): 31 => 31
5104 06:53:24.354493 DramcWriteLeveling(PI) end<-----
5105 06:53:24.357395
5106 06:53:24.357883 ==
5107 06:53:24.360963 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 06:53:24.364362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 06:53:24.364935 ==
5110 06:53:24.367699 [Gating] SW mode calibration
5111 06:53:24.374394 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5112 06:53:24.377641 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5113 06:53:24.384335 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5114 06:53:24.387507 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 06:53:24.390785 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 06:53:24.397601 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 06:53:24.400817 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 06:53:24.404067 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 06:53:24.410894 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5120 06:53:24.414133 0 14 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5121 06:53:24.417435 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
5122 06:53:24.423773 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 06:53:24.427430 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 06:53:24.430792 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 06:53:24.437012 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 06:53:24.440548 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 06:53:24.443730 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5128 06:53:24.450308 0 15 28 | B1->B0 | 2d2d 4444 | 0 0 | (0 0) (0 0)
5129 06:53:24.453732 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5130 06:53:24.456828 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 06:53:24.463873 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 06:53:24.466761 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 06:53:24.470406 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 06:53:24.477210 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 06:53:24.480517 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 06:53:24.483517 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5137 06:53:24.490063 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5138 06:53:24.493552 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 06:53:24.496759 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 06:53:24.503301 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 06:53:24.506946 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 06:53:24.509852 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 06:53:24.516519 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 06:53:24.519872 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 06:53:24.523164 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 06:53:24.526785 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 06:53:24.533188 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 06:53:24.536438 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 06:53:24.540290 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 06:53:24.546631 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 06:53:24.549928 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 06:53:24.553405 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5153 06:53:24.556571 Total UI for P1: 0, mck2ui 16
5154 06:53:24.560218 best dqsien dly found for B0: ( 1, 2, 26)
5155 06:53:24.566541 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5156 06:53:24.569866 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 06:53:24.573510 Total UI for P1: 0, mck2ui 16
5158 06:53:24.576690 best dqsien dly found for B1: ( 1, 2, 30)
5159 06:53:24.579911 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5160 06:53:24.583090 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5161 06:53:24.583656
5162 06:53:24.586849 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5163 06:53:24.589819 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5164 06:53:24.593461 [Gating] SW calibration Done
5165 06:53:24.594071 ==
5166 06:53:24.596831 Dram Type= 6, Freq= 0, CH_0, rank 0
5167 06:53:24.599959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5168 06:53:24.602934 ==
5169 06:53:24.603531 RX Vref Scan: 0
5170 06:53:24.603899
5171 06:53:24.606459 RX Vref 0 -> 0, step: 1
5172 06:53:24.607025
5173 06:53:24.609873 RX Delay -80 -> 252, step: 8
5174 06:53:24.613018 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5175 06:53:24.616534 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5176 06:53:24.619548 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5177 06:53:24.622978 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5178 06:53:24.629600 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5179 06:53:24.632911 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5180 06:53:24.636198 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5181 06:53:24.639885 iDelay=208, Bit 7, Center 119 (32 ~ 207) 176
5182 06:53:24.642995 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5183 06:53:24.646157 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5184 06:53:24.652847 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5185 06:53:24.655852 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5186 06:53:24.659056 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5187 06:53:24.662564 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5188 06:53:24.665873 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5189 06:53:24.672781 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5190 06:53:24.673358 ==
5191 06:53:24.675580 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 06:53:24.679231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 06:53:24.679840 ==
5194 06:53:24.680220 DQS Delay:
5195 06:53:24.682468 DQS0 = 0, DQS1 = 0
5196 06:53:24.682927 DQM Delay:
5197 06:53:24.685900 DQM0 = 107, DQM1 = 91
5198 06:53:24.686504 DQ Delay:
5199 06:53:24.689605 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5200 06:53:24.692925 DQ4 =107, DQ5 =95, DQ6 =119, DQ7 =119
5201 06:53:24.696230 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5202 06:53:24.699003 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5203 06:53:24.699570
5204 06:53:24.699938
5205 06:53:24.700276 ==
5206 06:53:24.702752 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 06:53:24.705768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 06:53:24.709585 ==
5209 06:53:24.710200
5210 06:53:24.710577
5211 06:53:24.710917 TX Vref Scan disable
5212 06:53:24.712310 == TX Byte 0 ==
5213 06:53:24.715974 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5214 06:53:24.719016 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5215 06:53:24.722306 == TX Byte 1 ==
5216 06:53:24.726027 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5217 06:53:24.729242 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5218 06:53:24.732550 ==
5219 06:53:24.735651 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 06:53:24.738730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 06:53:24.739288 ==
5222 06:53:24.739660
5223 06:53:24.740003
5224 06:53:24.742080 TX Vref Scan disable
5225 06:53:24.742555 == TX Byte 0 ==
5226 06:53:24.748795 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5227 06:53:24.752765 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5228 06:53:24.753327 == TX Byte 1 ==
5229 06:53:24.758706 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5230 06:53:24.762269 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5231 06:53:24.762891
5232 06:53:24.763271 [DATLAT]
5233 06:53:24.765097 Freq=933, CH0 RK0
5234 06:53:24.765556
5235 06:53:24.766122 DATLAT Default: 0xd
5236 06:53:24.768835 0, 0xFFFF, sum = 0
5237 06:53:24.769403 1, 0xFFFF, sum = 0
5238 06:53:24.771917 2, 0xFFFF, sum = 0
5239 06:53:24.772386 3, 0xFFFF, sum = 0
5240 06:53:24.775539 4, 0xFFFF, sum = 0
5241 06:53:24.776007 5, 0xFFFF, sum = 0
5242 06:53:24.778597 6, 0xFFFF, sum = 0
5243 06:53:24.779084 7, 0xFFFF, sum = 0
5244 06:53:24.782065 8, 0xFFFF, sum = 0
5245 06:53:24.785447 9, 0xFFFF, sum = 0
5246 06:53:24.786071 10, 0x0, sum = 1
5247 06:53:24.786607 11, 0x0, sum = 2
5248 06:53:24.788764 12, 0x0, sum = 3
5249 06:53:24.789379 13, 0x0, sum = 4
5250 06:53:24.792095 best_step = 11
5251 06:53:24.792661
5252 06:53:24.793032 ==
5253 06:53:24.795399 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 06:53:24.798776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 06:53:24.799346 ==
5256 06:53:24.802192 RX Vref Scan: 1
5257 06:53:24.802761
5258 06:53:24.803134 RX Vref 0 -> 0, step: 1
5259 06:53:24.803481
5260 06:53:24.806026 RX Delay -53 -> 252, step: 4
5261 06:53:24.806595
5262 06:53:24.808880 Set Vref, RX VrefLevel [Byte0]: 60
5263 06:53:24.812460 [Byte1]: 50
5264 06:53:24.816025
5265 06:53:24.816490 Final RX Vref Byte 0 = 60 to rank0
5266 06:53:24.819662 Final RX Vref Byte 1 = 50 to rank0
5267 06:53:24.822609 Final RX Vref Byte 0 = 60 to rank1
5268 06:53:24.826452 Final RX Vref Byte 1 = 50 to rank1==
5269 06:53:24.829164 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 06:53:24.836021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 06:53:24.836577 ==
5272 06:53:24.837042 DQS Delay:
5273 06:53:24.837398 DQS0 = 0, DQS1 = 0
5274 06:53:24.839340 DQM Delay:
5275 06:53:24.839806 DQM0 = 108, DQM1 = 92
5276 06:53:24.842401 DQ Delay:
5277 06:53:24.845644 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5278 06:53:24.849060 DQ4 =110, DQ5 =100, DQ6 =120, DQ7 =116
5279 06:53:24.852661 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =92
5280 06:53:24.855880 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =98
5281 06:53:24.856490
5282 06:53:24.857000
5283 06:53:24.862201 [DQSOSCAuto] RK0, (LSB)MR18= 0x211e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5284 06:53:24.865591 CH0 RK0: MR19=505, MR18=211E
5285 06:53:24.872544 CH0_RK0: MR19=0x505, MR18=0x211E, DQSOSC=411, MR23=63, INC=64, DEC=42
5286 06:53:24.873013
5287 06:53:24.876366 ----->DramcWriteLeveling(PI) begin...
5288 06:53:24.877107 ==
5289 06:53:24.879293 Dram Type= 6, Freq= 0, CH_0, rank 1
5290 06:53:24.882337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 06:53:24.882810 ==
5292 06:53:24.885566 Write leveling (Byte 0): 34 => 34
5293 06:53:24.889101 Write leveling (Byte 1): 27 => 27
5294 06:53:24.892169 DramcWriteLeveling(PI) end<-----
5295 06:53:24.892620
5296 06:53:24.892976 ==
5297 06:53:24.895991 Dram Type= 6, Freq= 0, CH_0, rank 1
5298 06:53:24.898788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 06:53:24.902509 ==
5300 06:53:24.902959 [Gating] SW mode calibration
5301 06:53:24.912836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5302 06:53:24.915772 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5303 06:53:24.919065 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 06:53:24.925708 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 06:53:24.928932 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 06:53:24.932703 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 06:53:24.938976 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 06:53:24.942013 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 06:53:24.945799 0 14 24 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 1)
5310 06:53:24.952167 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5311 06:53:24.955453 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 06:53:24.959048 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 06:53:24.965568 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 06:53:24.968953 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 06:53:24.972320 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 06:53:24.978726 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 06:53:24.981912 0 15 24 | B1->B0 | 2828 2d2d | 0 0 | (0 0) (0 0)
5318 06:53:24.985747 0 15 28 | B1->B0 | 3535 4444 | 0 0 | (0 0) (0 0)
5319 06:53:24.992095 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 06:53:24.995107 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 06:53:24.998666 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 06:53:25.005353 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 06:53:25.008628 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 06:53:25.011999 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 06:53:25.018980 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 06:53:25.021731 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5327 06:53:25.025379 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5328 06:53:25.032155 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 06:53:25.035244 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 06:53:25.038270 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 06:53:25.045280 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 06:53:25.048356 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 06:53:25.051531 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 06:53:25.055138 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 06:53:25.061845 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 06:53:25.065100 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 06:53:25.068514 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 06:53:25.074751 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 06:53:25.078307 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 06:53:25.081531 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 06:53:25.088449 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5342 06:53:25.091780 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5343 06:53:25.095057 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 06:53:25.098518 Total UI for P1: 0, mck2ui 16
5345 06:53:25.101763 best dqsien dly found for B0: ( 1, 2, 26)
5346 06:53:25.105159 Total UI for P1: 0, mck2ui 16
5347 06:53:25.108735 best dqsien dly found for B1: ( 1, 2, 26)
5348 06:53:25.111935 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5349 06:53:25.114819 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5350 06:53:25.115366
5351 06:53:25.121632 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5352 06:53:25.125151 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5353 06:53:25.125704 [Gating] SW calibration Done
5354 06:53:25.128486 ==
5355 06:53:25.131284 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 06:53:25.134793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 06:53:25.135356 ==
5358 06:53:25.135722 RX Vref Scan: 0
5359 06:53:25.136060
5360 06:53:25.137801 RX Vref 0 -> 0, step: 1
5361 06:53:25.138399
5362 06:53:25.141613 RX Delay -80 -> 252, step: 8
5363 06:53:25.144778 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5364 06:53:25.147838 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5365 06:53:25.151230 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5366 06:53:25.157686 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5367 06:53:25.161311 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5368 06:53:25.164250 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5369 06:53:25.168353 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5370 06:53:25.171446 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5371 06:53:25.178103 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5372 06:53:25.181473 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5373 06:53:25.184929 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5374 06:53:25.187933 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5375 06:53:25.190772 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5376 06:53:25.194850 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5377 06:53:25.201373 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5378 06:53:25.204298 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5379 06:53:25.204859 ==
5380 06:53:25.207284 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 06:53:25.210825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 06:53:25.211378 ==
5383 06:53:25.214076 DQS Delay:
5384 06:53:25.214620 DQS0 = 0, DQS1 = 0
5385 06:53:25.214981 DQM Delay:
5386 06:53:25.217228 DQM0 = 104, DQM1 = 90
5387 06:53:25.217679 DQ Delay:
5388 06:53:25.221124 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5389 06:53:25.224418 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5390 06:53:25.227719 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5391 06:53:25.230710 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5392 06:53:25.231167
5393 06:53:25.231524
5394 06:53:25.231856 ==
5395 06:53:25.234245 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 06:53:25.241024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 06:53:25.241584 ==
5398 06:53:25.241996
5399 06:53:25.242348
5400 06:53:25.242670 TX Vref Scan disable
5401 06:53:25.244300 == TX Byte 0 ==
5402 06:53:25.248186 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5403 06:53:25.254350 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5404 06:53:25.254808 == TX Byte 1 ==
5405 06:53:25.258082 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5406 06:53:25.261525 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5407 06:53:25.264395 ==
5408 06:53:25.267975 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 06:53:25.271113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 06:53:25.271667 ==
5411 06:53:25.272031
5412 06:53:25.272363
5413 06:53:25.274642 TX Vref Scan disable
5414 06:53:25.275194 == TX Byte 0 ==
5415 06:53:25.281256 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5416 06:53:25.284446 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5417 06:53:25.284996 == TX Byte 1 ==
5418 06:53:25.291286 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5419 06:53:25.294403 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5420 06:53:25.294956
5421 06:53:25.295442 [DATLAT]
5422 06:53:25.298023 Freq=933, CH0 RK1
5423 06:53:25.298571
5424 06:53:25.298936 DATLAT Default: 0xb
5425 06:53:25.301116 0, 0xFFFF, sum = 0
5426 06:53:25.301707 1, 0xFFFF, sum = 0
5427 06:53:25.304235 2, 0xFFFF, sum = 0
5428 06:53:25.304780 3, 0xFFFF, sum = 0
5429 06:53:25.307757 4, 0xFFFF, sum = 0
5430 06:53:25.310969 5, 0xFFFF, sum = 0
5431 06:53:25.311534 6, 0xFFFF, sum = 0
5432 06:53:25.314115 7, 0xFFFF, sum = 0
5433 06:53:25.314577 8, 0xFFFF, sum = 0
5434 06:53:25.317620 9, 0xFFFF, sum = 0
5435 06:53:25.318107 10, 0x0, sum = 1
5436 06:53:25.320559 11, 0x0, sum = 2
5437 06:53:25.321022 12, 0x0, sum = 3
5438 06:53:25.321389 13, 0x0, sum = 4
5439 06:53:25.324317 best_step = 11
5440 06:53:25.325001
5441 06:53:25.325524 ==
5442 06:53:25.327874 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 06:53:25.331225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 06:53:25.331778 ==
5445 06:53:25.333604 RX Vref Scan: 0
5446 06:53:25.334102
5447 06:53:25.337418 RX Vref 0 -> 0, step: 1
5448 06:53:25.338009
5449 06:53:25.338392 RX Delay -53 -> 252, step: 4
5450 06:53:25.345201 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5451 06:53:25.348636 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5452 06:53:25.351281 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5453 06:53:25.354774 iDelay=203, Bit 3, Center 98 (11 ~ 186) 176
5454 06:53:25.358387 iDelay=203, Bit 4, Center 106 (19 ~ 194) 176
5455 06:53:25.364642 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5456 06:53:25.368508 iDelay=203, Bit 6, Center 112 (23 ~ 202) 180
5457 06:53:25.371677 iDelay=203, Bit 7, Center 110 (23 ~ 198) 176
5458 06:53:25.374940 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5459 06:53:25.378186 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5460 06:53:25.385011 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5461 06:53:25.388246 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5462 06:53:25.391593 iDelay=203, Bit 12, Center 98 (15 ~ 182) 168
5463 06:53:25.395115 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5464 06:53:25.398448 iDelay=203, Bit 14, Center 102 (15 ~ 190) 176
5465 06:53:25.401808 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5466 06:53:25.404934 ==
5467 06:53:25.408494 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 06:53:25.411472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 06:53:25.412023 ==
5470 06:53:25.412523 DQS Delay:
5471 06:53:25.414674 DQS0 = 0, DQS1 = 0
5472 06:53:25.415224 DQM Delay:
5473 06:53:25.417686 DQM0 = 104, DQM1 = 92
5474 06:53:25.418172 DQ Delay:
5475 06:53:25.421181 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5476 06:53:25.424855 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5477 06:53:25.428072 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5478 06:53:25.431551 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98
5479 06:53:25.432115
5480 06:53:25.432472
5481 06:53:25.441418 [DQSOSCAuto] RK1, (LSB)MR18= 0x2909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 408 ps
5482 06:53:25.442009 CH0 RK1: MR19=505, MR18=2909
5483 06:53:25.447986 CH0_RK1: MR19=0x505, MR18=0x2909, DQSOSC=408, MR23=63, INC=65, DEC=43
5484 06:53:25.451153 [RxdqsGatingPostProcess] freq 933
5485 06:53:25.458150 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5486 06:53:25.461167 best DQS0 dly(2T, 0.5T) = (0, 10)
5487 06:53:25.464498 best DQS1 dly(2T, 0.5T) = (0, 10)
5488 06:53:25.467845 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5489 06:53:25.471141 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5490 06:53:25.471595 best DQS0 dly(2T, 0.5T) = (0, 10)
5491 06:53:25.474580 best DQS1 dly(2T, 0.5T) = (0, 10)
5492 06:53:25.478370 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5493 06:53:25.481349 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5494 06:53:25.484635 Pre-setting of DQS Precalculation
5495 06:53:25.491555 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5496 06:53:25.492104 ==
5497 06:53:25.494766 Dram Type= 6, Freq= 0, CH_1, rank 0
5498 06:53:25.497876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 06:53:25.498457 ==
5500 06:53:25.504626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5501 06:53:25.507905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5502 06:53:25.512153 [CA 0] Center 37 (7~68) winsize 62
5503 06:53:25.515271 [CA 1] Center 37 (7~68) winsize 62
5504 06:53:25.518643 [CA 2] Center 35 (5~65) winsize 61
5505 06:53:25.522092 [CA 3] Center 34 (4~65) winsize 62
5506 06:53:25.525595 [CA 4] Center 34 (4~65) winsize 62
5507 06:53:25.528920 [CA 5] Center 34 (4~64) winsize 61
5508 06:53:25.529374
5509 06:53:25.531991 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5510 06:53:25.532446
5511 06:53:25.535168 [CATrainingPosCal] consider 1 rank data
5512 06:53:25.538640 u2DelayCellTimex100 = 270/100 ps
5513 06:53:25.542092 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5514 06:53:25.548684 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5515 06:53:25.551727 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5516 06:53:25.555159 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5517 06:53:25.558755 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5518 06:53:25.561650 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5519 06:53:25.562161
5520 06:53:25.564892 CA PerBit enable=1, Macro0, CA PI delay=34
5521 06:53:25.565302
5522 06:53:25.568719 [CBTSetCACLKResult] CA Dly = 34
5523 06:53:25.569243 CS Dly: 6 (0~37)
5524 06:53:25.571816 ==
5525 06:53:25.575050 Dram Type= 6, Freq= 0, CH_1, rank 1
5526 06:53:25.578298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 06:53:25.578712 ==
5528 06:53:25.581700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5529 06:53:25.588674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5530 06:53:25.591957 [CA 0] Center 37 (7~68) winsize 62
5531 06:53:25.595512 [CA 1] Center 37 (7~68) winsize 62
5532 06:53:25.598702 [CA 2] Center 36 (6~66) winsize 61
5533 06:53:25.601839 [CA 3] Center 35 (5~65) winsize 61
5534 06:53:25.605261 [CA 4] Center 35 (5~65) winsize 61
5535 06:53:25.608626 [CA 5] Center 34 (5~64) winsize 60
5536 06:53:25.609080
5537 06:53:25.611775 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5538 06:53:25.612186
5539 06:53:25.615435 [CATrainingPosCal] consider 2 rank data
5540 06:53:25.618241 u2DelayCellTimex100 = 270/100 ps
5541 06:53:25.621797 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5542 06:53:25.625215 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5543 06:53:25.631957 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5544 06:53:25.635423 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5545 06:53:25.638381 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5546 06:53:25.641680 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5547 06:53:25.642133
5548 06:53:25.644988 CA PerBit enable=1, Macro0, CA PI delay=34
5549 06:53:25.645404
5550 06:53:25.648947 [CBTSetCACLKResult] CA Dly = 34
5551 06:53:25.649362 CS Dly: 7 (0~39)
5552 06:53:25.649693
5553 06:53:25.652123 ----->DramcWriteLeveling(PI) begin...
5554 06:53:25.655567 ==
5555 06:53:25.658975 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 06:53:25.661836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 06:53:25.662298 ==
5558 06:53:25.664867 Write leveling (Byte 0): 25 => 25
5559 06:53:25.668631 Write leveling (Byte 1): 28 => 28
5560 06:53:25.671884 DramcWriteLeveling(PI) end<-----
5561 06:53:25.672299
5562 06:53:25.672624 ==
5563 06:53:25.675346 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 06:53:25.678565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 06:53:25.679017 ==
5566 06:53:25.681919 [Gating] SW mode calibration
5567 06:53:25.688683 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5568 06:53:25.694902 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5569 06:53:25.698110 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 06:53:25.701490 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 06:53:25.708676 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 06:53:25.711796 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 06:53:25.714920 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 06:53:25.718349 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5575 06:53:25.724595 0 14 24 | B1->B0 | 3030 3030 | 1 0 | (1 1) (0 1)
5576 06:53:25.728266 0 14 28 | B1->B0 | 2525 2424 | 0 0 | (0 0) (1 0)
5577 06:53:25.731657 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 06:53:25.738210 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 06:53:25.741592 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 06:53:25.745020 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 06:53:25.751341 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 06:53:25.754719 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 06:53:25.758009 0 15 24 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
5584 06:53:25.764751 0 15 28 | B1->B0 | 4444 4545 | 1 0 | (0 0) (0 0)
5585 06:53:25.768144 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 06:53:25.771064 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 06:53:25.777786 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 06:53:25.781361 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 06:53:25.784527 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 06:53:25.791012 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5591 06:53:25.794671 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5592 06:53:25.797838 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 06:53:25.804256 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 06:53:25.807570 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 06:53:25.810810 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 06:53:25.817886 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 06:53:25.821112 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 06:53:25.824332 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 06:53:25.830832 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 06:53:25.834448 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 06:53:25.837507 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 06:53:25.843898 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 06:53:25.847426 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 06:53:25.850875 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 06:53:25.857914 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 06:53:25.860611 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 06:53:25.864119 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5608 06:53:25.867387 Total UI for P1: 0, mck2ui 16
5609 06:53:25.871054 best dqsien dly found for B0: ( 1, 2, 22)
5610 06:53:25.877513 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5611 06:53:25.880675 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 06:53:25.884204 Total UI for P1: 0, mck2ui 16
5613 06:53:25.887164 best dqsien dly found for B1: ( 1, 2, 26)
5614 06:53:25.890402 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5615 06:53:25.894110 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5616 06:53:25.894566
5617 06:53:25.897189 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5618 06:53:25.901035 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5619 06:53:25.904143 [Gating] SW calibration Done
5620 06:53:25.904657 ==
5621 06:53:25.907773 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 06:53:25.910683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 06:53:25.911150 ==
5624 06:53:25.914031 RX Vref Scan: 0
5625 06:53:25.914481
5626 06:53:25.917462 RX Vref 0 -> 0, step: 1
5627 06:53:25.917901
5628 06:53:25.918285 RX Delay -80 -> 252, step: 8
5629 06:53:25.924090 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5630 06:53:25.927400 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5631 06:53:25.931336 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5632 06:53:25.933761 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5633 06:53:25.937112 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5634 06:53:25.944136 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5635 06:53:25.947073 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5636 06:53:25.950487 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5637 06:53:25.953800 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5638 06:53:25.957175 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5639 06:53:25.960259 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5640 06:53:25.966946 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5641 06:53:25.970206 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5642 06:53:25.973741 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5643 06:53:25.977060 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5644 06:53:25.980021 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5645 06:53:25.980470 ==
5646 06:53:25.983880 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 06:53:25.990231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 06:53:25.990656 ==
5649 06:53:25.991022 DQS Delay:
5650 06:53:25.993329 DQS0 = 0, DQS1 = 0
5651 06:53:25.993786 DQM Delay:
5652 06:53:25.994214 DQM0 = 102, DQM1 = 95
5653 06:53:25.996935 DQ Delay:
5654 06:53:26.000347 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =103
5655 06:53:26.003613 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =99
5656 06:53:26.007003 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5657 06:53:26.010918 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5658 06:53:26.011326
5659 06:53:26.011695
5660 06:53:26.012116 ==
5661 06:53:26.013360 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 06:53:26.017047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 06:53:26.017463 ==
5664 06:53:26.017927
5665 06:53:26.018307
5666 06:53:26.020059 TX Vref Scan disable
5667 06:53:26.023268 == TX Byte 0 ==
5668 06:53:26.027122 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5669 06:53:26.030027 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5670 06:53:26.033355 == TX Byte 1 ==
5671 06:53:26.036924 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5672 06:53:26.040014 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5673 06:53:26.040482 ==
5674 06:53:26.043212 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 06:53:26.047123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 06:53:26.050137 ==
5677 06:53:26.050548
5678 06:53:26.050879
5679 06:53:26.051316 TX Vref Scan disable
5680 06:53:26.053392 == TX Byte 0 ==
5681 06:53:26.056827 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5682 06:53:26.063336 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5683 06:53:26.063747 == TX Byte 1 ==
5684 06:53:26.066727 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5685 06:53:26.073600 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5686 06:53:26.074149
5687 06:53:26.074545 [DATLAT]
5688 06:53:26.074857 Freq=933, CH1 RK0
5689 06:53:26.075152
5690 06:53:26.076777 DATLAT Default: 0xd
5691 06:53:26.077182 0, 0xFFFF, sum = 0
5692 06:53:26.080380 1, 0xFFFF, sum = 0
5693 06:53:26.080794 2, 0xFFFF, sum = 0
5694 06:53:26.083523 3, 0xFFFF, sum = 0
5695 06:53:26.086686 4, 0xFFFF, sum = 0
5696 06:53:26.087097 5, 0xFFFF, sum = 0
5697 06:53:26.090074 6, 0xFFFF, sum = 0
5698 06:53:26.090539 7, 0xFFFF, sum = 0
5699 06:53:26.093248 8, 0xFFFF, sum = 0
5700 06:53:26.093711 9, 0xFFFF, sum = 0
5701 06:53:26.096588 10, 0x0, sum = 1
5702 06:53:26.097056 11, 0x0, sum = 2
5703 06:53:26.099810 12, 0x0, sum = 3
5704 06:53:26.100279 13, 0x0, sum = 4
5705 06:53:26.100612 best_step = 11
5706 06:53:26.103383
5707 06:53:26.103789 ==
5708 06:53:26.106428 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 06:53:26.110052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 06:53:26.110462 ==
5711 06:53:26.110833 RX Vref Scan: 1
5712 06:53:26.111177
5713 06:53:26.113019 RX Vref 0 -> 0, step: 1
5714 06:53:26.113424
5715 06:53:26.116467 RX Delay -53 -> 252, step: 4
5716 06:53:26.116928
5717 06:53:26.119877 Set Vref, RX VrefLevel [Byte0]: 53
5718 06:53:26.123269 [Byte1]: 49
5719 06:53:26.123731
5720 06:53:26.126149 Final RX Vref Byte 0 = 53 to rank0
5721 06:53:26.129550 Final RX Vref Byte 1 = 49 to rank0
5722 06:53:26.132907 Final RX Vref Byte 0 = 53 to rank1
5723 06:53:26.136772 Final RX Vref Byte 1 = 49 to rank1==
5724 06:53:26.139890 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 06:53:26.142893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 06:53:26.146555 ==
5727 06:53:26.146962 DQS Delay:
5728 06:53:26.147281 DQS0 = 0, DQS1 = 0
5729 06:53:26.149476 DQM Delay:
5730 06:53:26.149879 DQM0 = 104, DQM1 = 96
5731 06:53:26.152969 DQ Delay:
5732 06:53:26.156285 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5733 06:53:26.159455 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5734 06:53:26.162845 DQ8 =84, DQ9 =86, DQ10 =102, DQ11 =90
5735 06:53:26.166282 DQ12 =106, DQ13 =100, DQ14 =102, DQ15 =104
5736 06:53:26.166688
5737 06:53:26.167011
5738 06:53:26.173039 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5739 06:53:26.176554 CH1 RK0: MR19=505, MR18=1D35
5740 06:53:26.182956 CH1_RK0: MR19=0x505, MR18=0x1D35, DQSOSC=405, MR23=63, INC=66, DEC=44
5741 06:53:26.183512
5742 06:53:26.186463 ----->DramcWriteLeveling(PI) begin...
5743 06:53:26.187027 ==
5744 06:53:26.189684 Dram Type= 6, Freq= 0, CH_1, rank 1
5745 06:53:26.192818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 06:53:26.193369 ==
5747 06:53:26.196500 Write leveling (Byte 0): 26 => 26
5748 06:53:26.199598 Write leveling (Byte 1): 26 => 26
5749 06:53:26.202843 DramcWriteLeveling(PI) end<-----
5750 06:53:26.203393
5751 06:53:26.203750 ==
5752 06:53:26.206319 Dram Type= 6, Freq= 0, CH_1, rank 1
5753 06:53:26.209447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 06:53:26.213022 ==
5755 06:53:26.213575 [Gating] SW mode calibration
5756 06:53:26.222815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5757 06:53:26.226045 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5758 06:53:26.229671 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5759 06:53:26.236015 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 06:53:26.239261 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 06:53:26.242839 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 06:53:26.249363 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 06:53:26.252712 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 06:53:26.255934 0 14 24 | B1->B0 | 2e2e 3333 | 1 1 | (1 1) (1 1)
5765 06:53:26.262553 0 14 28 | B1->B0 | 2626 2e2e | 0 1 | (0 0) (1 0)
5766 06:53:26.265701 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5767 06:53:26.269268 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 06:53:26.276052 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 06:53:26.279201 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 06:53:26.282670 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 06:53:26.289516 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 06:53:26.292343 0 15 24 | B1->B0 | 3030 2828 | 0 0 | (0 0) (0 0)
5773 06:53:26.296072 0 15 28 | B1->B0 | 4040 4040 | 0 0 | (1 1) (0 0)
5774 06:53:26.302552 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5775 06:53:26.306035 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 06:53:26.309249 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 06:53:26.315814 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 06:53:26.318847 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 06:53:26.322311 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 06:53:26.329283 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5781 06:53:26.332316 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5782 06:53:26.335323 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 06:53:26.339108 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 06:53:26.345517 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 06:53:26.348952 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 06:53:26.352748 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 06:53:26.359000 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 06:53:26.361865 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 06:53:26.365507 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 06:53:26.372094 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 06:53:26.375630 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 06:53:26.378885 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 06:53:26.385876 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 06:53:26.388623 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 06:53:26.392361 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 06:53:26.398967 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5797 06:53:26.402315 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 06:53:26.405813 Total UI for P1: 0, mck2ui 16
5799 06:53:26.408912 best dqsien dly found for B0: ( 1, 2, 24)
5800 06:53:26.412598 Total UI for P1: 0, mck2ui 16
5801 06:53:26.415441 best dqsien dly found for B1: ( 1, 2, 26)
5802 06:53:26.418751 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5803 06:53:26.422135 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5804 06:53:26.422688
5805 06:53:26.425467 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5806 06:53:26.428852 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5807 06:53:26.432371 [Gating] SW calibration Done
5808 06:53:26.432934 ==
5809 06:53:26.435523 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 06:53:26.438856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 06:53:26.442046 ==
5812 06:53:26.442506 RX Vref Scan: 0
5813 06:53:26.442872
5814 06:53:26.445266 RX Vref 0 -> 0, step: 1
5815 06:53:26.445721
5816 06:53:26.446113 RX Delay -80 -> 252, step: 8
5817 06:53:26.452128 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5818 06:53:26.455408 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5819 06:53:26.458874 iDelay=208, Bit 2, Center 91 (8 ~ 175) 168
5820 06:53:26.462183 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5821 06:53:26.465692 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5822 06:53:26.468749 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5823 06:53:26.475951 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5824 06:53:26.478535 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5825 06:53:26.482332 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5826 06:53:26.485745 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5827 06:53:26.488989 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5828 06:53:26.492358 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5829 06:53:26.498947 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5830 06:53:26.502255 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5831 06:53:26.505422 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5832 06:53:26.508625 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5833 06:53:26.509197 ==
5834 06:53:26.512492 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 06:53:26.515317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 06:53:26.519014 ==
5837 06:53:26.519586 DQS Delay:
5838 06:53:26.519953 DQS0 = 0, DQS1 = 0
5839 06:53:26.522046 DQM Delay:
5840 06:53:26.522608 DQM0 = 101, DQM1 = 95
5841 06:53:26.525237 DQ Delay:
5842 06:53:26.528368 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5843 06:53:26.532462 DQ4 =99, DQ5 =115, DQ6 =107, DQ7 =99
5844 06:53:26.535606 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5845 06:53:26.538481 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5846 06:53:26.539042
5847 06:53:26.539407
5848 06:53:26.539836 ==
5849 06:53:26.541817 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 06:53:26.545377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 06:53:26.545967 ==
5852 06:53:26.546339
5853 06:53:26.546680
5854 06:53:26.548526 TX Vref Scan disable
5855 06:53:26.549079 == TX Byte 0 ==
5856 06:53:26.555063 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5857 06:53:26.558228 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5858 06:53:26.558683 == TX Byte 1 ==
5859 06:53:26.564988 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5860 06:53:26.568565 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5861 06:53:26.569027 ==
5862 06:53:26.572018 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 06:53:26.575193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 06:53:26.575659 ==
5865 06:53:26.576024
5866 06:53:26.578458
5867 06:53:26.578912 TX Vref Scan disable
5868 06:53:26.581616 == TX Byte 0 ==
5869 06:53:26.585083 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5870 06:53:26.588807 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5871 06:53:26.591937 == TX Byte 1 ==
5872 06:53:26.595303 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5873 06:53:26.598506 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5874 06:53:26.598964
5875 06:53:26.601736 [DATLAT]
5876 06:53:26.602333 Freq=933, CH1 RK1
5877 06:53:26.602706
5878 06:53:26.605436 DATLAT Default: 0xb
5879 06:53:26.606025 0, 0xFFFF, sum = 0
5880 06:53:26.608393 1, 0xFFFF, sum = 0
5881 06:53:26.608855 2, 0xFFFF, sum = 0
5882 06:53:26.612099 3, 0xFFFF, sum = 0
5883 06:53:26.612668 4, 0xFFFF, sum = 0
5884 06:53:26.615267 5, 0xFFFF, sum = 0
5885 06:53:26.615832 6, 0xFFFF, sum = 0
5886 06:53:26.618542 7, 0xFFFF, sum = 0
5887 06:53:26.619109 8, 0xFFFF, sum = 0
5888 06:53:26.621675 9, 0xFFFF, sum = 0
5889 06:53:26.622187 10, 0x0, sum = 1
5890 06:53:26.624890 11, 0x0, sum = 2
5891 06:53:26.625350 12, 0x0, sum = 3
5892 06:53:26.628294 13, 0x0, sum = 4
5893 06:53:26.628760 best_step = 11
5894 06:53:26.629117
5895 06:53:26.629452 ==
5896 06:53:26.632267 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 06:53:26.638485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 06:53:26.639045 ==
5899 06:53:26.639409 RX Vref Scan: 0
5900 06:53:26.639744
5901 06:53:26.641831 RX Vref 0 -> 0, step: 1
5902 06:53:26.642426
5903 06:53:26.645383 RX Delay -53 -> 252, step: 4
5904 06:53:26.648587 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5905 06:53:26.651894 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5906 06:53:26.658471 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5907 06:53:26.661856 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5908 06:53:26.665335 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5909 06:53:26.668274 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5910 06:53:26.671986 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5911 06:53:26.678380 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5912 06:53:26.681620 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5913 06:53:26.685139 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5914 06:53:26.688485 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5915 06:53:26.691467 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5916 06:53:26.698028 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5917 06:53:26.701333 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5918 06:53:34.712746 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5919 06:53:34.712932 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5920 06:53:34.713039 ==
5921 06:53:34.713143 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 06:53:34.713242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 06:53:34.713343 ==
5924 06:53:34.713441 DQS Delay:
5925 06:53:34.713538 DQS0 = 0, DQS1 = 0
5926 06:53:34.713635 DQM Delay:
5927 06:53:34.713732 DQM0 = 105, DQM1 = 97
5928 06:53:34.713828 DQ Delay:
5929 06:53:34.713924 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5930 06:53:34.714083 DQ4 =106, DQ5 =116, DQ6 =114, DQ7 =104
5931 06:53:34.714180 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5932 06:53:34.714275 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =106
5933 06:53:34.714370
5934 06:53:34.714464
5935 06:53:34.714560 [DQSOSCAuto] RK1, (LSB)MR18= 0x2300, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5936 06:53:34.714658 CH1 RK1: MR19=505, MR18=2300
5937 06:53:34.714754 CH1_RK1: MR19=0x505, MR18=0x2300, DQSOSC=410, MR23=63, INC=64, DEC=42
5938 06:53:34.714851 [RxdqsGatingPostProcess] freq 933
5939 06:53:34.714945 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5940 06:53:34.715041 best DQS0 dly(2T, 0.5T) = (0, 10)
5941 06:53:34.715135 best DQS1 dly(2T, 0.5T) = (0, 10)
5942 06:53:34.715229 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5943 06:53:34.715323 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5944 06:53:34.715419 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 06:53:34.715512 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 06:53:34.715607 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 06:53:34.715701 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 06:53:34.715794 Pre-setting of DQS Precalculation
5949 06:53:34.715888 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5950 06:53:34.715983 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5951 06:53:34.716078 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5952 06:53:34.716173
5953 06:53:34.716268
5954 06:53:34.716361 [Calibration Summary] 1866 Mbps
5955 06:53:34.716454 CH 0, Rank 0
5956 06:53:34.716548 SW Impedance : PASS
5957 06:53:34.716643 DUTY Scan : NO K
5958 06:53:34.716736 ZQ Calibration : PASS
5959 06:53:34.716831 Jitter Meter : NO K
5960 06:53:34.716925 CBT Training : PASS
5961 06:53:34.717019 Write leveling : PASS
5962 06:53:34.717112 RX DQS gating : PASS
5963 06:53:34.717206 RX DQ/DQS(RDDQC) : PASS
5964 06:53:34.717299 TX DQ/DQS : PASS
5965 06:53:34.717393 RX DATLAT : PASS
5966 06:53:34.717487 RX DQ/DQS(Engine): PASS
5967 06:53:34.717580 TX OE : NO K
5968 06:53:34.717675 All Pass.
5969 06:53:34.717769
5970 06:53:34.717862 CH 0, Rank 1
5971 06:53:34.717986 SW Impedance : PASS
5972 06:53:34.718110 DUTY Scan : NO K
5973 06:53:34.718205 ZQ Calibration : PASS
5974 06:53:34.718299 Jitter Meter : NO K
5975 06:53:34.718392 CBT Training : PASS
5976 06:53:34.718486 Write leveling : PASS
5977 06:53:34.718579 RX DQS gating : PASS
5978 06:53:34.718673 RX DQ/DQS(RDDQC) : PASS
5979 06:53:34.718766 TX DQ/DQS : PASS
5980 06:53:34.718861 RX DATLAT : PASS
5981 06:53:34.718955 RX DQ/DQS(Engine): PASS
5982 06:53:34.719048 TX OE : NO K
5983 06:53:34.719143 All Pass.
5984 06:53:34.719237
5985 06:53:34.719330 CH 1, Rank 0
5986 06:53:34.719422 SW Impedance : PASS
5987 06:53:34.719516 DUTY Scan : NO K
5988 06:53:34.719611 ZQ Calibration : PASS
5989 06:53:34.719705 Jitter Meter : NO K
5990 06:53:34.719799 CBT Training : PASS
5991 06:53:34.719892 Write leveling : PASS
5992 06:53:34.719985 RX DQS gating : PASS
5993 06:53:34.720078 RX DQ/DQS(RDDQC) : PASS
5994 06:53:34.720170 TX DQ/DQS : PASS
5995 06:53:34.720263 RX DATLAT : PASS
5996 06:53:34.720357 RX DQ/DQS(Engine): PASS
5997 06:53:34.720451 TX OE : NO K
5998 06:53:34.720546 All Pass.
5999 06:53:34.720639
6000 06:53:34.720733 CH 1, Rank 1
6001 06:53:34.720826 SW Impedance : PASS
6002 06:53:34.720918 DUTY Scan : NO K
6003 06:53:34.721012 ZQ Calibration : PASS
6004 06:53:34.721105 Jitter Meter : NO K
6005 06:53:34.721198 CBT Training : PASS
6006 06:53:34.721291 Write leveling : PASS
6007 06:53:34.721384 RX DQS gating : PASS
6008 06:53:34.721478 RX DQ/DQS(RDDQC) : PASS
6009 06:53:34.721571 TX DQ/DQS : PASS
6010 06:53:34.721664 RX DATLAT : PASS
6011 06:53:34.721758 RX DQ/DQS(Engine): PASS
6012 06:53:34.721851 TX OE : NO K
6013 06:53:34.721949 All Pass.
6014 06:53:34.722090
6015 06:53:34.722183 DramC Write-DBI off
6016 06:53:34.722277 PER_BANK_REFRESH: Hybrid Mode
6017 06:53:34.722370 TX_TRACKING: ON
6018 06:53:34.722465 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6019 06:53:34.722561 [FAST_K] Save calibration result to emmc
6020 06:53:34.722656 dramc_set_vcore_voltage set vcore to 650000
6021 06:53:34.722750 Read voltage for 400, 6
6022 06:53:34.722885 Vio18 = 0
6023 06:53:34.722978 Vcore = 650000
6024 06:53:34.723072 Vdram = 0
6025 06:53:34.723163 Vddq = 0
6026 06:53:34.723256 Vmddr = 0
6027 06:53:34.723349 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6028 06:53:34.723444 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6029 06:53:34.723538 MEM_TYPE=3, freq_sel=20
6030 06:53:34.723633 sv_algorithm_assistance_LP4_800
6031 06:53:34.723727 ============ PULL DRAM RESETB DOWN ============
6032 06:53:34.723822 ========== PULL DRAM RESETB DOWN end =========
6033 06:53:34.723917 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6034 06:53:34.724011 ===================================
6035 06:53:34.724105 LPDDR4 DRAM CONFIGURATION
6036 06:53:34.724199 ===================================
6037 06:53:34.724293 EX_ROW_EN[0] = 0x0
6038 06:53:34.724384 EX_ROW_EN[1] = 0x0
6039 06:53:34.724458 LP4Y_EN = 0x0
6040 06:53:34.724531 WORK_FSP = 0x0
6041 06:53:34.724604 WL = 0x2
6042 06:53:34.724675 RL = 0x2
6043 06:53:34.724747 BL = 0x2
6044 06:53:34.724905 RPST = 0x0
6045 06:53:34.725040 RD_PRE = 0x0
6046 06:53:34.725131 WR_PRE = 0x1
6047 06:53:34.725222 WR_PST = 0x0
6048 06:53:34.725312 DBI_WR = 0x0
6049 06:53:34.725403 DBI_RD = 0x0
6050 06:53:34.725493 OTF = 0x1
6051 06:53:34.725584 ===================================
6052 06:53:34.725676 ===================================
6053 06:53:34.725767 ANA top config
6054 06:53:34.725858 ===================================
6055 06:53:34.725954 DLL_ASYNC_EN = 0
6056 06:53:34.726102 ALL_SLAVE_EN = 1
6057 06:53:34.726194 NEW_RANK_MODE = 1
6058 06:53:34.726287 DLL_IDLE_MODE = 1
6059 06:53:34.726378 LP45_APHY_COMB_EN = 1
6060 06:53:34.726469 TX_ODT_DIS = 1
6061 06:53:34.726561 NEW_8X_MODE = 1
6062 06:53:34.726652 ===================================
6063 06:53:34.726744 ===================================
6064 06:53:34.727107 data_rate = 800
6065 06:53:34.727201 CKR = 1
6066 06:53:34.727295 DQ_P2S_RATIO = 4
6067 06:53:34.727388 ===================================
6068 06:53:34.727481 CA_P2S_RATIO = 4
6069 06:53:34.727574 DQ_CA_OPEN = 0
6070 06:53:34.727665 DQ_SEMI_OPEN = 1
6071 06:53:34.727756 CA_SEMI_OPEN = 1
6072 06:53:34.727848 CA_FULL_RATE = 0
6073 06:53:34.727939 DQ_CKDIV4_EN = 0
6074 06:53:34.728030 CA_CKDIV4_EN = 1
6075 06:53:34.728121 CA_PREDIV_EN = 0
6076 06:53:34.728211 PH8_DLY = 0
6077 06:53:34.728302 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6078 06:53:34.728392 DQ_AAMCK_DIV = 0
6079 06:53:34.728482 CA_AAMCK_DIV = 0
6080 06:53:34.728572 CA_ADMCK_DIV = 4
6081 06:53:34.728662 DQ_TRACK_CA_EN = 0
6082 06:53:34.728752 CA_PICK = 800
6083 06:53:34.728843 CA_MCKIO = 400
6084 06:53:34.728934 MCKIO_SEMI = 400
6085 06:53:34.729024 PLL_FREQ = 3016
6086 06:53:34.729115 DQ_UI_PI_RATIO = 32
6087 06:53:34.729205 CA_UI_PI_RATIO = 32
6088 06:53:34.729295 ===================================
6089 06:53:34.729386 ===================================
6090 06:53:34.729477 memory_type:LPDDR4
6091 06:53:34.729567 GP_NUM : 10
6092 06:53:34.729657 SRAM_EN : 1
6093 06:53:34.729747 MD32_EN : 0
6094 06:53:34.729838 ===================================
6095 06:53:34.729929 [ANA_INIT] >>>>>>>>>>>>>>
6096 06:53:34.730064 <<<<<< [CONFIGURE PHASE]: ANA_TX
6097 06:53:34.730157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6098 06:53:34.730248 ===================================
6099 06:53:34.730339 data_rate = 800,PCW = 0X7400
6100 06:53:34.730429 ===================================
6101 06:53:34.730519 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6102 06:53:34.730610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6103 06:53:34.730702 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6104 06:53:34.730826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6105 06:53:34.730917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6106 06:53:34.731008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6107 06:53:34.731099 [ANA_INIT] flow start
6108 06:53:34.731189 [ANA_INIT] PLL >>>>>>>>
6109 06:53:34.731279 [ANA_INIT] PLL <<<<<<<<
6110 06:53:34.731369 [ANA_INIT] MIDPI >>>>>>>>
6111 06:53:34.731460 [ANA_INIT] MIDPI <<<<<<<<
6112 06:53:34.731550 [ANA_INIT] DLL >>>>>>>>
6113 06:53:34.731639 [ANA_INIT] flow end
6114 06:53:34.731729 ============ LP4 DIFF to SE enter ============
6115 06:53:34.731820 ============ LP4 DIFF to SE exit ============
6116 06:53:34.731911 [ANA_INIT] <<<<<<<<<<<<<
6117 06:53:34.732001 [Flow] Enable top DCM control >>>>>
6118 06:53:34.732092 [Flow] Enable top DCM control <<<<<
6119 06:53:34.732182 Enable DLL master slave shuffle
6120 06:53:34.732272 ==============================================================
6121 06:53:34.732363 Gating Mode config
6122 06:53:34.732453 ==============================================================
6123 06:53:34.732544 Config description:
6124 06:53:34.732634 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6125 06:53:34.732725 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6126 06:53:34.732816 SELPH_MODE 0: By rank 1: By Phase
6127 06:53:34.732907 ==============================================================
6128 06:53:34.732998 GAT_TRACK_EN = 0
6129 06:53:34.733088 RX_GATING_MODE = 2
6130 06:53:34.733178 RX_GATING_TRACK_MODE = 2
6131 06:53:34.733268 SELPH_MODE = 1
6132 06:53:34.733358 PICG_EARLY_EN = 1
6133 06:53:34.733448 VALID_LAT_VALUE = 1
6134 06:53:34.733538 ==============================================================
6135 06:53:34.733629 Enter into Gating configuration >>>>
6136 06:53:34.733720 Exit from Gating configuration <<<<
6137 06:53:34.733809 Enter into DVFS_PRE_config >>>>>
6138 06:53:34.733899 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6139 06:53:34.734032 Exit from DVFS_PRE_config <<<<<
6140 06:53:34.734123 Enter into PICG configuration >>>>
6141 06:53:34.734214 Exit from PICG configuration <<<<
6142 06:53:34.734303 [RX_INPUT] configuration >>>>>
6143 06:53:34.734394 [RX_INPUT] configuration <<<<<
6144 06:53:34.734484 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6145 06:53:34.734575 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6146 06:53:34.734666 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 06:53:34.734756 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 06:53:34.734846 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6149 06:53:34.734937 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6150 06:53:34.735027 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6151 06:53:34.735118 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6152 06:53:34.735208 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6153 06:53:34.735299 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6154 06:53:34.735389 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6155 06:53:34.735480 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6156 06:53:34.735570 ===================================
6157 06:53:34.735660 LPDDR4 DRAM CONFIGURATION
6158 06:53:34.735750 ===================================
6159 06:53:34.735840 EX_ROW_EN[0] = 0x0
6160 06:53:34.735930 EX_ROW_EN[1] = 0x0
6161 06:53:34.736019 LP4Y_EN = 0x0
6162 06:53:34.736109 WORK_FSP = 0x0
6163 06:53:34.736199 WL = 0x2
6164 06:53:34.736288 RL = 0x2
6165 06:53:34.736378 BL = 0x2
6166 06:53:34.736663 RPST = 0x0
6167 06:53:34.736780 RD_PRE = 0x0
6168 06:53:34.736933 WR_PRE = 0x1
6169 06:53:34.737066 WR_PST = 0x0
6170 06:53:34.737158 DBI_WR = 0x0
6171 06:53:34.737249 DBI_RD = 0x0
6172 06:53:34.737340 OTF = 0x1
6173 06:53:34.737431 ===================================
6174 06:53:34.737523 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6175 06:53:34.737614 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6176 06:53:34.737706 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 06:53:34.737797 ===================================
6178 06:53:34.737889 LPDDR4 DRAM CONFIGURATION
6179 06:53:34.738039 ===================================
6180 06:53:34.738131 EX_ROW_EN[0] = 0x10
6181 06:53:34.738221 EX_ROW_EN[1] = 0x0
6182 06:53:34.738311 LP4Y_EN = 0x0
6183 06:53:34.738401 WORK_FSP = 0x0
6184 06:53:34.738491 WL = 0x2
6185 06:53:34.738582 RL = 0x2
6186 06:53:34.738671 BL = 0x2
6187 06:53:34.738777 RPST = 0x0
6188 06:53:34.738925 RD_PRE = 0x0
6189 06:53:34.739028 WR_PRE = 0x1
6190 06:53:34.739118 WR_PST = 0x0
6191 06:53:34.739208 DBI_WR = 0x0
6192 06:53:34.739297 DBI_RD = 0x0
6193 06:53:34.739387 OTF = 0x1
6194 06:53:34.739478 ===================================
6195 06:53:34.739568 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6196 06:53:34.739659 nWR fixed to 30
6197 06:53:34.739750 [ModeRegInit_LP4] CH0 RK0
6198 06:53:34.739840 [ModeRegInit_LP4] CH0 RK1
6199 06:53:34.739930 [ModeRegInit_LP4] CH1 RK0
6200 06:53:34.740019 [ModeRegInit_LP4] CH1 RK1
6201 06:53:34.740109 match AC timing 19
6202 06:53:34.740199 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6203 06:53:34.740290 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6204 06:53:34.740380 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6205 06:53:34.740500 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6206 06:53:34.740590 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6207 06:53:34.740681 ==
6208 06:53:34.740771 Dram Type= 6, Freq= 0, CH_0, rank 0
6209 06:53:34.740862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6210 06:53:34.740952 ==
6211 06:53:34.741042 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6212 06:53:34.741133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6213 06:53:34.741225 [CA 0] Center 36 (8~64) winsize 57
6214 06:53:34.741315 [CA 1] Center 36 (8~64) winsize 57
6215 06:53:34.741406 [CA 2] Center 36 (8~64) winsize 57
6216 06:53:34.741496 [CA 3] Center 36 (8~64) winsize 57
6217 06:53:34.741586 [CA 4] Center 36 (8~64) winsize 57
6218 06:53:34.741676 [CA 5] Center 36 (8~64) winsize 57
6219 06:53:34.741766
6220 06:53:34.741856 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6221 06:53:34.741951
6222 06:53:34.742080 [CATrainingPosCal] consider 1 rank data
6223 06:53:34.742171 u2DelayCellTimex100 = 270/100 ps
6224 06:53:34.742261 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 06:53:34.742351 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 06:53:34.742441 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 06:53:34.742530 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 06:53:34.742620 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 06:53:34.742710 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 06:53:34.742799
6231 06:53:34.742889 CA PerBit enable=1, Macro0, CA PI delay=36
6232 06:53:34.742979
6233 06:53:34.743069 [CBTSetCACLKResult] CA Dly = 36
6234 06:53:34.743159 CS Dly: 1 (0~32)
6235 06:53:34.743248 ==
6236 06:53:34.743338 Dram Type= 6, Freq= 0, CH_0, rank 1
6237 06:53:34.743428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 06:53:34.743567 ==
6239 06:53:34.743660 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 06:53:34.743752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6241 06:53:34.743843 [CA 0] Center 36 (8~64) winsize 57
6242 06:53:34.743934 [CA 1] Center 36 (8~64) winsize 57
6243 06:53:34.744025 [CA 2] Center 36 (8~64) winsize 57
6244 06:53:34.744115 [CA 3] Center 36 (8~64) winsize 57
6245 06:53:34.744205 [CA 4] Center 36 (8~64) winsize 57
6246 06:53:34.744295 [CA 5] Center 36 (8~64) winsize 57
6247 06:53:34.744384
6248 06:53:34.744484 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6249 06:53:34.744575
6250 06:53:34.744665 [CATrainingPosCal] consider 2 rank data
6251 06:53:34.744756 u2DelayCellTimex100 = 270/100 ps
6252 06:53:34.744848 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 06:53:34.744939 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 06:53:34.745029 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 06:53:34.745119 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 06:53:34.745209 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 06:53:34.745298 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 06:53:34.745388
6259 06:53:34.745477 CA PerBit enable=1, Macro0, CA PI delay=36
6260 06:53:34.745567
6261 06:53:34.745657 [CBTSetCACLKResult] CA Dly = 36
6262 06:53:34.745747 CS Dly: 1 (0~32)
6263 06:53:34.745836
6264 06:53:34.745926 ----->DramcWriteLeveling(PI) begin...
6265 06:53:34.746062 ==
6266 06:53:34.746153 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 06:53:34.746244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 06:53:34.746336 ==
6269 06:53:34.746426 Write leveling (Byte 0): 40 => 8
6270 06:53:34.746517 Write leveling (Byte 1): 32 => 0
6271 06:53:34.746606 DramcWriteLeveling(PI) end<-----
6272 06:53:34.746696
6273 06:53:34.746808 ==
6274 06:53:34.746912 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 06:53:34.747003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 06:53:34.747093 ==
6277 06:53:34.747184 [Gating] SW mode calibration
6278 06:53:34.747274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6279 06:53:34.747365 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6280 06:53:34.747455 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6281 06:53:34.747546 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6282 06:53:34.747636 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 06:53:34.747726 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 06:53:34.747816 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 06:53:34.747906 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 06:53:34.747996 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 06:53:34.748087 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 06:53:34.748177 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 06:53:34.748267 Total UI for P1: 0, mck2ui 16
6290 06:53:34.748358 best dqsien dly found for B0: ( 0, 14, 24)
6291 06:53:34.748640 Total UI for P1: 0, mck2ui 16
6292 06:53:34.748732 best dqsien dly found for B1: ( 0, 14, 24)
6293 06:53:34.748826 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6294 06:53:34.748922 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6295 06:53:34.749016
6296 06:53:34.749107 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6297 06:53:34.749201 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6298 06:53:34.749288 [Gating] SW calibration Done
6299 06:53:34.749373 ==
6300 06:53:34.749455 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 06:53:34.749536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 06:53:34.749617 ==
6303 06:53:34.749696 RX Vref Scan: 0
6304 06:53:34.749775
6305 06:53:34.749853 RX Vref 0 -> 0, step: 1
6306 06:53:34.749932
6307 06:53:34.750057 RX Delay -410 -> 252, step: 16
6308 06:53:34.750138 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6309 06:53:34.750219 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6310 06:53:34.750298 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6311 06:53:34.750378 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6312 06:53:34.750456 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6313 06:53:34.750535 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6314 06:53:34.750615 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6315 06:53:34.750694 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6316 06:53:34.750772 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6317 06:53:34.750851 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6318 06:53:34.750929 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6319 06:53:34.751007 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6320 06:53:34.751085 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6321 06:53:34.751164 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6322 06:53:34.751242 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6323 06:53:34.751320 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6324 06:53:34.751398 ==
6325 06:53:34.751476 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 06:53:34.751554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 06:53:34.751633 ==
6328 06:53:34.751711 DQS Delay:
6329 06:53:34.751789 DQS0 = 27, DQS1 = 43
6330 06:53:34.751866 DQM Delay:
6331 06:53:34.751944 DQM0 = 12, DQM1 = 13
6332 06:53:34.752021 DQ Delay:
6333 06:53:34.752100 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6334 06:53:34.752179 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6335 06:53:34.752258 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6336 06:53:34.752335 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6337 06:53:34.752414
6338 06:53:34.752492
6339 06:53:34.752569 ==
6340 06:53:34.752647 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 06:53:34.752725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 06:53:34.752841 ==
6343 06:53:34.752919
6344 06:53:34.752996
6345 06:53:34.753073 TX Vref Scan disable
6346 06:53:34.753150 == TX Byte 0 ==
6347 06:53:34.753228 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 06:53:34.753307 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 06:53:34.753385 == TX Byte 1 ==
6350 06:53:34.753463 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6351 06:53:34.753541 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6352 06:53:34.753619 ==
6353 06:53:34.753697 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 06:53:34.753775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 06:53:34.753854 ==
6356 06:53:34.753932
6357 06:53:34.754051
6358 06:53:34.754129 TX Vref Scan disable
6359 06:53:34.754207 == TX Byte 0 ==
6360 06:53:34.754285 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 06:53:34.754363 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 06:53:34.754441 == TX Byte 1 ==
6363 06:53:34.754519 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6364 06:53:34.754603 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6365 06:53:34.754685
6366 06:53:34.754763 [DATLAT]
6367 06:53:34.754875 Freq=400, CH0 RK0
6368 06:53:34.754951
6369 06:53:34.755026 DATLAT Default: 0xf
6370 06:53:34.755102 0, 0xFFFF, sum = 0
6371 06:53:34.755189 1, 0xFFFF, sum = 0
6372 06:53:34.755270 2, 0xFFFF, sum = 0
6373 06:53:34.755349 3, 0xFFFF, sum = 0
6374 06:53:34.755427 4, 0xFFFF, sum = 0
6375 06:53:34.755505 5, 0xFFFF, sum = 0
6376 06:53:34.755585 6, 0xFFFF, sum = 0
6377 06:53:34.755664 7, 0xFFFF, sum = 0
6378 06:53:34.755743 8, 0xFFFF, sum = 0
6379 06:53:34.755824 9, 0xFFFF, sum = 0
6380 06:53:34.755903 10, 0xFFFF, sum = 0
6381 06:53:34.755991 11, 0xFFFF, sum = 0
6382 06:53:34.756084 12, 0xFFFF, sum = 0
6383 06:53:34.756180 13, 0x0, sum = 1
6384 06:53:34.756279 14, 0x0, sum = 2
6385 06:53:34.756375 15, 0x0, sum = 3
6386 06:53:34.756472 16, 0x0, sum = 4
6387 06:53:34.756582 best_step = 14
6388 06:53:34.756675
6389 06:53:34.756782 ==
6390 06:53:34.756879 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 06:53:34.756993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 06:53:34.757075 ==
6393 06:53:34.757156 RX Vref Scan: 1
6394 06:53:34.757237
6395 06:53:34.757317 RX Vref 0 -> 0, step: 1
6396 06:53:34.757397
6397 06:53:34.757477 RX Delay -327 -> 252, step: 8
6398 06:53:34.757557
6399 06:53:34.757638 Set Vref, RX VrefLevel [Byte0]: 60
6400 06:53:34.757718 [Byte1]: 50
6401 06:53:34.757798
6402 06:53:34.757878 Final RX Vref Byte 0 = 60 to rank0
6403 06:53:34.757990 Final RX Vref Byte 1 = 50 to rank0
6404 06:53:34.758085 Final RX Vref Byte 0 = 60 to rank1
6405 06:53:34.758166 Final RX Vref Byte 1 = 50 to rank1==
6406 06:53:34.758247 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 06:53:34.758328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 06:53:34.758408 ==
6409 06:53:34.758488 DQS Delay:
6410 06:53:34.758568 DQS0 = 28, DQS1 = 48
6411 06:53:34.758648 DQM Delay:
6412 06:53:34.758727 DQM0 = 12, DQM1 = 15
6413 06:53:34.758807 DQ Delay:
6414 06:53:34.758887 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6415 06:53:34.758967 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6416 06:53:34.759048 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6417 06:53:34.759128 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6418 06:53:34.759207
6419 06:53:34.759287
6420 06:53:34.759369 [DQSOSCAuto] RK0, (LSB)MR18= 0xaca4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6421 06:53:34.759451 CH0 RK0: MR19=C0C, MR18=ACA4
6422 06:53:34.759532 CH0_RK0: MR19=0xC0C, MR18=0xACA4, DQSOSC=388, MR23=63, INC=392, DEC=261
6423 06:53:34.759612 ==
6424 06:53:34.759693 Dram Type= 6, Freq= 0, CH_0, rank 1
6425 06:53:34.759773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 06:53:34.759853 ==
6427 06:53:34.759933 [Gating] SW mode calibration
6428 06:53:34.760015 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6429 06:53:34.760096 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6430 06:53:34.760177 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 06:53:34.760258 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6432 06:53:34.760339 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 06:53:34.760420 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 06:53:34.760500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 06:53:34.760801 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 06:53:34.760919 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 06:53:34.761016 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 06:53:34.761098 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 06:53:34.761179 Total UI for P1: 0, mck2ui 16
6440 06:53:34.761260 best dqsien dly found for B0: ( 0, 14, 24)
6441 06:53:34.761348 Total UI for P1: 0, mck2ui 16
6442 06:53:34.761469 best dqsien dly found for B1: ( 0, 14, 24)
6443 06:53:34.761551 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6444 06:53:34.761632 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6445 06:53:34.761712
6446 06:53:34.761792 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6447 06:53:34.761874 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6448 06:53:34.761982 [Gating] SW calibration Done
6449 06:53:34.762051 ==
6450 06:53:34.762104 Dram Type= 6, Freq= 0, CH_0, rank 1
6451 06:53:34.762156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 06:53:34.762208 ==
6453 06:53:34.762260 RX Vref Scan: 0
6454 06:53:34.762312
6455 06:53:34.762362 RX Vref 0 -> 0, step: 1
6456 06:53:34.762414
6457 06:53:34.762465 RX Delay -410 -> 252, step: 16
6458 06:53:34.762517 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6459 06:53:34.762570 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6460 06:53:34.762622 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6461 06:53:34.762674 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6462 06:53:34.762726 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6463 06:53:34.762777 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6464 06:53:34.762829 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6465 06:53:34.762881 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6466 06:53:34.762933 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6467 06:53:34.762985 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6468 06:53:34.763064 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6469 06:53:34.763116 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6470 06:53:34.763167 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6471 06:53:34.763219 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6472 06:53:34.763271 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6473 06:53:34.763323 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6474 06:53:34.763374 ==
6475 06:53:34.763425 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 06:53:34.763477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 06:53:34.763530 ==
6478 06:53:34.763581 DQS Delay:
6479 06:53:34.763633 DQS0 = 27, DQS1 = 43
6480 06:53:34.763684 DQM Delay:
6481 06:53:34.763735 DQM0 = 9, DQM1 = 16
6482 06:53:34.763786 DQ Delay:
6483 06:53:34.763837 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6484 06:53:34.763888 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6485 06:53:34.763939 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6486 06:53:34.763990 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6487 06:53:34.764041
6488 06:53:34.764092
6489 06:53:34.764143 ==
6490 06:53:34.764194 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 06:53:34.764245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 06:53:34.764297 ==
6493 06:53:34.764348
6494 06:53:34.764399
6495 06:53:34.764450 TX Vref Scan disable
6496 06:53:34.764501 == TX Byte 0 ==
6497 06:53:34.764552 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6498 06:53:34.764604 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6499 06:53:34.764656 == TX Byte 1 ==
6500 06:53:34.764707 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6501 06:53:34.764759 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6502 06:53:34.764810 ==
6503 06:53:34.764861 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 06:53:34.764913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 06:53:34.764965 ==
6506 06:53:34.765016
6507 06:53:34.765067
6508 06:53:34.765118 TX Vref Scan disable
6509 06:53:34.765169 == TX Byte 0 ==
6510 06:53:34.765220 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6511 06:53:34.765272 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6512 06:53:34.765323 == TX Byte 1 ==
6513 06:53:34.765374 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6514 06:53:34.765426 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6515 06:53:34.765477
6516 06:53:34.765528 [DATLAT]
6517 06:53:34.765579 Freq=400, CH0 RK1
6518 06:53:34.765630
6519 06:53:34.765681 DATLAT Default: 0xe
6520 06:53:34.765732 0, 0xFFFF, sum = 0
6521 06:53:34.765784 1, 0xFFFF, sum = 0
6522 06:53:34.765837 2, 0xFFFF, sum = 0
6523 06:53:34.765889 3, 0xFFFF, sum = 0
6524 06:53:34.765949 4, 0xFFFF, sum = 0
6525 06:53:34.766045 5, 0xFFFF, sum = 0
6526 06:53:34.766097 6, 0xFFFF, sum = 0
6527 06:53:34.766149 7, 0xFFFF, sum = 0
6528 06:53:34.766201 8, 0xFFFF, sum = 0
6529 06:53:34.766254 9, 0xFFFF, sum = 0
6530 06:53:34.766307 10, 0xFFFF, sum = 0
6531 06:53:34.766359 11, 0xFFFF, sum = 0
6532 06:53:34.766411 12, 0xFFFF, sum = 0
6533 06:53:34.766463 13, 0x0, sum = 1
6534 06:53:34.766516 14, 0x0, sum = 2
6535 06:53:34.766568 15, 0x0, sum = 3
6536 06:53:34.766620 16, 0x0, sum = 4
6537 06:53:34.766702 best_step = 14
6538 06:53:34.766753
6539 06:53:34.766805 ==
6540 06:53:34.766856 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 06:53:34.766908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 06:53:34.766961 ==
6543 06:53:34.767013 RX Vref Scan: 0
6544 06:53:34.767064
6545 06:53:34.767115 RX Vref 0 -> 0, step: 1
6546 06:53:34.767166
6547 06:53:34.767217 RX Delay -327 -> 252, step: 8
6548 06:53:34.767269 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6549 06:53:34.767321 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6550 06:53:34.767372 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6551 06:53:34.767424 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6552 06:53:34.767475 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6553 06:53:34.767527 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6554 06:53:34.767579 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6555 06:53:34.767630 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6556 06:53:34.767682 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6557 06:53:34.767734 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6558 06:53:34.767785 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6559 06:53:34.767837 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6560 06:53:34.767888 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6561 06:53:34.767940 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6562 06:53:34.767991 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6563 06:53:34.768043 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6564 06:53:34.768094 ==
6565 06:53:34.768146 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 06:53:34.768197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 06:53:34.768249 ==
6568 06:53:34.768301 DQS Delay:
6569 06:53:34.768353 DQS0 = 28, DQS1 = 40
6570 06:53:34.768404 DQM Delay:
6571 06:53:34.768455 DQM0 = 10, DQM1 = 12
6572 06:53:34.768506 DQ Delay:
6573 06:53:34.768557 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6574 06:53:34.768609 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6575 06:53:34.768852 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6576 06:53:34.768913 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =16
6577 06:53:34.768966
6578 06:53:34.769018
6579 06:53:34.769069 [DQSOSCAuto] RK1, (LSB)MR18= 0xb669, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6580 06:53:34.769122 CH0 RK1: MR19=C0C, MR18=B669
6581 06:53:34.769175 CH0_RK1: MR19=0xC0C, MR18=0xB669, DQSOSC=387, MR23=63, INC=394, DEC=262
6582 06:53:34.769228 [RxdqsGatingPostProcess] freq 400
6583 06:53:34.769280 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6584 06:53:34.769332 best DQS0 dly(2T, 0.5T) = (0, 10)
6585 06:53:34.769383 best DQS1 dly(2T, 0.5T) = (0, 10)
6586 06:53:34.769435 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6587 06:53:34.769486 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6588 06:53:34.769538 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 06:53:34.769590 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 06:53:34.769642 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 06:53:34.769693 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 06:53:34.769744 Pre-setting of DQS Precalculation
6593 06:53:34.769796 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6594 06:53:34.769849 ==
6595 06:53:34.769901 Dram Type= 6, Freq= 0, CH_1, rank 0
6596 06:53:34.769980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 06:53:34.770047 ==
6598 06:53:34.770099 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6599 06:53:34.770151 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6600 06:53:34.770203 [CA 0] Center 36 (8~64) winsize 57
6601 06:53:34.770256 [CA 1] Center 36 (8~64) winsize 57
6602 06:53:34.770307 [CA 2] Center 36 (8~64) winsize 57
6603 06:53:34.770359 [CA 3] Center 36 (8~64) winsize 57
6604 06:53:34.770410 [CA 4] Center 36 (8~64) winsize 57
6605 06:53:34.770462 [CA 5] Center 36 (8~64) winsize 57
6606 06:53:34.770513
6607 06:53:34.770565 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6608 06:53:34.770617
6609 06:53:34.770668 [CATrainingPosCal] consider 1 rank data
6610 06:53:34.770720 u2DelayCellTimex100 = 270/100 ps
6611 06:53:34.770772 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 06:53:34.770824 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 06:53:34.770875 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 06:53:34.770927 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 06:53:34.770980 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 06:53:34.771031 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 06:53:34.771082
6618 06:53:34.771134 CA PerBit enable=1, Macro0, CA PI delay=36
6619 06:53:34.771187
6620 06:53:34.771239 [CBTSetCACLKResult] CA Dly = 36
6621 06:53:34.771291 CS Dly: 1 (0~32)
6622 06:53:34.771342 ==
6623 06:53:34.771394 Dram Type= 6, Freq= 0, CH_1, rank 1
6624 06:53:34.771446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 06:53:34.771498 ==
6626 06:53:34.771550 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 06:53:34.771602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6628 06:53:34.771654 [CA 0] Center 36 (8~64) winsize 57
6629 06:53:34.771706 [CA 1] Center 36 (8~64) winsize 57
6630 06:53:34.771757 [CA 2] Center 36 (8~64) winsize 57
6631 06:53:34.771808 [CA 3] Center 36 (8~64) winsize 57
6632 06:53:34.771860 [CA 4] Center 36 (8~64) winsize 57
6633 06:53:34.771912 [CA 5] Center 36 (8~64) winsize 57
6634 06:53:34.771963
6635 06:53:34.772014 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6636 06:53:34.772066
6637 06:53:34.772117 [CATrainingPosCal] consider 2 rank data
6638 06:53:34.772169 u2DelayCellTimex100 = 270/100 ps
6639 06:53:34.772221 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 06:53:34.772272 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 06:53:34.772324 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 06:53:34.772375 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 06:53:34.772427 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 06:53:34.772479 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 06:53:34.772530
6646 06:53:34.772582 CA PerBit enable=1, Macro0, CA PI delay=36
6647 06:53:34.772634
6648 06:53:34.772684 [CBTSetCACLKResult] CA Dly = 36
6649 06:53:34.772735 CS Dly: 1 (0~32)
6650 06:53:34.772787
6651 06:53:34.772838 ----->DramcWriteLeveling(PI) begin...
6652 06:53:34.772890 ==
6653 06:53:34.772941 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 06:53:34.772993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 06:53:34.773045 ==
6656 06:53:34.773096 Write leveling (Byte 0): 40 => 8
6657 06:53:34.773147 Write leveling (Byte 1): 32 => 0
6658 06:53:34.773199 DramcWriteLeveling(PI) end<-----
6659 06:53:34.773250
6660 06:53:34.773302 ==
6661 06:53:34.773353 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 06:53:34.773404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 06:53:34.773457 ==
6664 06:53:34.773508 [Gating] SW mode calibration
6665 06:53:34.773560 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6666 06:53:34.773612 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6667 06:53:34.773664 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6668 06:53:34.773716 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6669 06:53:34.773768 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 06:53:34.773819 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 06:53:34.773871 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 06:53:34.773923 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 06:53:34.774038 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 06:53:34.774091 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 06:53:34.774143 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 06:53:34.774194 Total UI for P1: 0, mck2ui 16
6677 06:53:34.774246 best dqsien dly found for B0: ( 0, 14, 24)
6678 06:53:34.774298 Total UI for P1: 0, mck2ui 16
6679 06:53:34.774350 best dqsien dly found for B1: ( 0, 14, 24)
6680 06:53:34.774402 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6681 06:53:34.774453 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6682 06:53:34.774505
6683 06:53:34.774556 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6684 06:53:34.774608 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6685 06:53:34.774660 [Gating] SW calibration Done
6686 06:53:34.774712 ==
6687 06:53:34.774764 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 06:53:34.774816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 06:53:34.774868 ==
6690 06:53:34.774920 RX Vref Scan: 0
6691 06:53:34.774972
6692 06:53:34.775023 RX Vref 0 -> 0, step: 1
6693 06:53:34.775075
6694 06:53:34.775126 RX Delay -410 -> 252, step: 16
6695 06:53:34.775367 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6696 06:53:34.775425 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6697 06:53:34.775479 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6698 06:53:34.775532 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6699 06:53:34.775584 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6700 06:53:34.775636 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6701 06:53:34.775689 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6702 06:53:34.775741 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6703 06:53:34.775793 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6704 06:53:34.775844 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6705 06:53:34.775896 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6706 06:53:34.775947 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6707 06:53:34.775998 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6708 06:53:34.776049 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6709 06:53:34.776101 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6710 06:53:34.776152 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6711 06:53:34.776203 ==
6712 06:53:34.776270 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 06:53:34.776336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 06:53:34.776388 ==
6715 06:53:34.776439 DQS Delay:
6716 06:53:34.776490 DQS0 = 27, DQS1 = 43
6717 06:53:34.776541 DQM Delay:
6718 06:53:34.776593 DQM0 = 8, DQM1 = 17
6719 06:53:34.776644 DQ Delay:
6720 06:53:34.776696 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6721 06:53:34.776747 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6722 06:53:34.776799 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6723 06:53:34.776851 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6724 06:53:34.776902
6725 06:53:34.776953
6726 06:53:34.777004 ==
6727 06:53:34.777056 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 06:53:34.777108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 06:53:34.777160 ==
6730 06:53:34.777211
6731 06:53:34.777261
6732 06:53:34.777312 TX Vref Scan disable
6733 06:53:34.777364 == TX Byte 0 ==
6734 06:53:34.777415 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 06:53:34.777467 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 06:53:34.777519 == TX Byte 1 ==
6737 06:53:34.777571 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6738 06:53:34.777622 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6739 06:53:34.777674 ==
6740 06:53:34.777726 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 06:53:34.777819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 06:53:34.777902 ==
6743 06:53:34.777993
6744 06:53:34.778047
6745 06:53:34.778098 TX Vref Scan disable
6746 06:53:34.778151 == TX Byte 0 ==
6747 06:53:34.778203 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 06:53:34.778255 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 06:53:34.778307 == TX Byte 1 ==
6750 06:53:34.778359 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6751 06:53:34.778411 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6752 06:53:34.778462
6753 06:53:34.778514 [DATLAT]
6754 06:53:34.778566 Freq=400, CH1 RK0
6755 06:53:34.778617
6756 06:53:34.778668 DATLAT Default: 0xf
6757 06:53:34.778721 0, 0xFFFF, sum = 0
6758 06:53:34.778773 1, 0xFFFF, sum = 0
6759 06:53:34.778827 2, 0xFFFF, sum = 0
6760 06:53:34.778879 3, 0xFFFF, sum = 0
6761 06:53:34.778931 4, 0xFFFF, sum = 0
6762 06:53:34.778983 5, 0xFFFF, sum = 0
6763 06:53:34.779035 6, 0xFFFF, sum = 0
6764 06:53:34.779088 7, 0xFFFF, sum = 0
6765 06:53:34.779140 8, 0xFFFF, sum = 0
6766 06:53:34.779192 9, 0xFFFF, sum = 0
6767 06:53:34.779245 10, 0xFFFF, sum = 0
6768 06:53:34.779296 11, 0xFFFF, sum = 0
6769 06:53:34.779349 12, 0xFFFF, sum = 0
6770 06:53:34.779401 13, 0x0, sum = 1
6771 06:53:34.779453 14, 0x0, sum = 2
6772 06:53:34.779505 15, 0x0, sum = 3
6773 06:53:34.779558 16, 0x0, sum = 4
6774 06:53:34.779610 best_step = 14
6775 06:53:34.779661
6776 06:53:34.779711 ==
6777 06:53:34.779763 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 06:53:34.779814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 06:53:34.779866 ==
6780 06:53:34.779948 RX Vref Scan: 1
6781 06:53:34.780000
6782 06:53:34.780051 RX Vref 0 -> 0, step: 1
6783 06:53:34.780103
6784 06:53:34.780154 RX Delay -327 -> 252, step: 8
6785 06:53:34.780205
6786 06:53:34.780256 Set Vref, RX VrefLevel [Byte0]: 53
6787 06:53:34.780308 [Byte1]: 49
6788 06:53:34.780360
6789 06:53:34.780410 Final RX Vref Byte 0 = 53 to rank0
6790 06:53:34.780462 Final RX Vref Byte 1 = 49 to rank0
6791 06:53:34.780514 Final RX Vref Byte 0 = 53 to rank1
6792 06:53:34.780566 Final RX Vref Byte 1 = 49 to rank1==
6793 06:53:34.780617 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 06:53:34.780669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 06:53:34.780721 ==
6796 06:53:34.780772 DQS Delay:
6797 06:53:34.780824 DQS0 = 28, DQS1 = 40
6798 06:53:34.780875 DQM Delay:
6799 06:53:34.780927 DQM0 = 7, DQM1 = 12
6800 06:53:34.780978 DQ Delay:
6801 06:53:34.781029 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6802 06:53:34.781081 DQ4 =4, DQ5 =12, DQ6 =16, DQ7 =4
6803 06:53:34.781132 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6804 06:53:34.781184 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6805 06:53:34.781235
6806 06:53:34.781285
6807 06:53:34.781336 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6808 06:53:34.781388 CH1 RK0: MR19=C0C, MR18=8FCA
6809 06:53:34.781440 CH1_RK0: MR19=0xC0C, MR18=0x8FCA, DQSOSC=384, MR23=63, INC=400, DEC=267
6810 06:53:34.781492 ==
6811 06:53:34.781543 Dram Type= 6, Freq= 0, CH_1, rank 1
6812 06:53:34.781595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 06:53:34.781647 ==
6814 06:53:34.781699 [Gating] SW mode calibration
6815 06:53:34.781751 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6816 06:53:34.781803 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6817 06:53:34.781855 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6818 06:53:34.781907 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6819 06:53:34.781989 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 06:53:34.782056 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 06:53:34.782109 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 06:53:34.782161 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 06:53:34.782212 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 06:53:34.782264 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 06:53:34.782316 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 06:53:34.782367 Total UI for P1: 0, mck2ui 16
6827 06:53:34.782419 best dqsien dly found for B0: ( 0, 14, 24)
6828 06:53:34.782471 Total UI for P1: 0, mck2ui 16
6829 06:53:34.782523 best dqsien dly found for B1: ( 0, 14, 24)
6830 06:53:34.782575 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6831 06:53:34.782627 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6832 06:53:34.782678
6833 06:53:34.782729 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6834 06:53:34.782969 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6835 06:53:34.783027 [Gating] SW calibration Done
6836 06:53:34.783080 ==
6837 06:53:34.783132 Dram Type= 6, Freq= 0, CH_1, rank 1
6838 06:53:34.783184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 06:53:34.783237 ==
6840 06:53:34.783289 RX Vref Scan: 0
6841 06:53:34.783371
6842 06:53:34.783422 RX Vref 0 -> 0, step: 1
6843 06:53:34.783474
6844 06:53:34.783525 RX Delay -410 -> 252, step: 16
6845 06:53:34.783605 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6846 06:53:34.783657 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6847 06:53:34.783709 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6848 06:53:34.783806 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6849 06:53:34.783871 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6850 06:53:34.783923 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6851 06:53:34.783975 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6852 06:53:34.784026 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6853 06:53:34.784078 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6854 06:53:34.784129 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6855 06:53:34.784180 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6856 06:53:34.784232 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6857 06:53:34.784282 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6858 06:53:34.784335 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6859 06:53:34.784387 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6860 06:53:34.784439 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6861 06:53:34.784490 ==
6862 06:53:34.784541 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 06:53:34.784592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 06:53:34.784644 ==
6865 06:53:34.784696 DQS Delay:
6866 06:53:34.784747 DQS0 = 35, DQS1 = 35
6867 06:53:34.784798 DQM Delay:
6868 06:53:34.784849 DQM0 = 18, DQM1 = 13
6869 06:53:34.784900 DQ Delay:
6870 06:53:34.784951 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6871 06:53:34.785002 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6872 06:53:34.785053 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6873 06:53:34.785105 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6874 06:53:34.785156
6875 06:53:34.785207
6876 06:53:34.785258 ==
6877 06:53:34.785309 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 06:53:34.785361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 06:53:34.785412 ==
6880 06:53:34.785463
6881 06:53:34.785514
6882 06:53:34.785565 TX Vref Scan disable
6883 06:53:34.785617 == TX Byte 0 ==
6884 06:53:34.785668 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6885 06:53:34.785720 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6886 06:53:34.785771 == TX Byte 1 ==
6887 06:53:34.785823 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6888 06:53:34.785874 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6889 06:53:34.785926 ==
6890 06:53:34.786026 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 06:53:34.786079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 06:53:34.786131 ==
6893 06:53:34.786182
6894 06:53:34.786234
6895 06:53:34.786285 TX Vref Scan disable
6896 06:53:34.786337 == TX Byte 0 ==
6897 06:53:34.786388 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6898 06:53:34.786439 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6899 06:53:34.786492 == TX Byte 1 ==
6900 06:53:34.786544 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6901 06:53:34.786596 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6902 06:53:34.786663
6903 06:53:34.786728 [DATLAT]
6904 06:53:34.786779 Freq=400, CH1 RK1
6905 06:53:34.786830
6906 06:53:34.786881 DATLAT Default: 0xe
6907 06:53:34.786933 0, 0xFFFF, sum = 0
6908 06:53:34.786985 1, 0xFFFF, sum = 0
6909 06:53:34.787038 2, 0xFFFF, sum = 0
6910 06:53:34.787090 3, 0xFFFF, sum = 0
6911 06:53:34.787142 4, 0xFFFF, sum = 0
6912 06:53:34.787195 5, 0xFFFF, sum = 0
6913 06:53:34.787247 6, 0xFFFF, sum = 0
6914 06:53:34.787298 7, 0xFFFF, sum = 0
6915 06:53:34.787351 8, 0xFFFF, sum = 0
6916 06:53:34.787403 9, 0xFFFF, sum = 0
6917 06:53:34.787455 10, 0xFFFF, sum = 0
6918 06:53:34.787507 11, 0xFFFF, sum = 0
6919 06:53:34.787560 12, 0xFFFF, sum = 0
6920 06:53:34.787612 13, 0x0, sum = 1
6921 06:53:34.787665 14, 0x0, sum = 2
6922 06:53:34.787716 15, 0x0, sum = 3
6923 06:53:34.787769 16, 0x0, sum = 4
6924 06:53:34.787820 best_step = 14
6925 06:53:34.787872
6926 06:53:34.787922 ==
6927 06:53:34.787974 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 06:53:34.788026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 06:53:34.788078 ==
6930 06:53:34.788129 RX Vref Scan: 0
6931 06:53:34.788180
6932 06:53:34.788230 RX Vref 0 -> 0, step: 1
6933 06:53:34.788281
6934 06:53:34.788332 RX Delay -311 -> 252, step: 8
6935 06:53:34.788383 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6936 06:53:34.788435 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6937 06:53:34.788487 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6938 06:53:34.788538 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6939 06:53:34.788589 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6940 06:53:34.788641 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6941 06:53:34.788692 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6942 06:53:34.788744 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6943 06:53:34.958226 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6944 06:53:34.959000 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6945 06:53:34.959615 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6946 06:53:34.960200 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6947 06:53:34.960767 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6948 06:53:34.961332 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6949 06:53:34.961902 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6950 06:53:34.962501 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6951 06:53:34.963062 ==
6952 06:53:34.963621 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 06:53:34.964175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 06:53:34.964732 ==
6955 06:53:34.965280 DQS Delay:
6956 06:53:34.965823 DQS0 = 32, DQS1 = 36
6957 06:53:34.966406 DQM Delay:
6958 06:53:34.966952 DQM0 = 14, DQM1 = 12
6959 06:53:34.967501 DQ Delay:
6960 06:53:34.968044 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =16
6961 06:53:34.968589 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =8
6962 06:53:34.969135 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6963 06:53:34.969679 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20
6964 06:53:34.970256
6965 06:53:34.970806
6966 06:53:34.971347 [DQSOSCAuto] RK1, (LSB)MR18= 0xae57, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
6967 06:53:34.971953 CH1 RK1: MR19=C0C, MR18=AE57
6968 06:53:34.972559 CH1_RK1: MR19=0xC0C, MR18=0xAE57, DQSOSC=388, MR23=63, INC=392, DEC=261
6969 06:53:34.973140 [RxdqsGatingPostProcess] freq 400
6970 06:53:34.973702 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6971 06:53:34.974287 best DQS0 dly(2T, 0.5T) = (0, 10)
6972 06:53:34.974843 best DQS1 dly(2T, 0.5T) = (0, 10)
6973 06:53:34.975905 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6974 06:53:34.976514 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6975 06:53:34.977087 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 06:53:34.977647 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 06:53:34.978240 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 06:53:34.978798 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 06:53:34.979352 Pre-setting of DQS Precalculation
6980 06:53:34.979889 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6981 06:53:34.980388 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6982 06:53:34.980890 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6983 06:53:34.981397
6984 06:53:34.981892
6985 06:53:34.982409 [Calibration Summary] 800 Mbps
6986 06:53:34.982905 CH 0, Rank 0
6987 06:53:34.983402 SW Impedance : PASS
6988 06:53:34.983941 DUTY Scan : NO K
6989 06:53:34.984489 ZQ Calibration : PASS
6990 06:53:34.984931 Jitter Meter : NO K
6991 06:53:34.985308 CBT Training : PASS
6992 06:53:34.985694 Write leveling : PASS
6993 06:53:34.986099 RX DQS gating : PASS
6994 06:53:34.986483 RX DQ/DQS(RDDQC) : PASS
6995 06:53:34.986868 TX DQ/DQS : PASS
6996 06:53:34.987254 RX DATLAT : PASS
6997 06:53:34.987634 RX DQ/DQS(Engine): PASS
6998 06:53:34.988015 TX OE : NO K
6999 06:53:34.988401 All Pass.
7000 06:53:34.988782
7001 06:53:34.989165 CH 0, Rank 1
7002 06:53:34.989542 SW Impedance : PASS
7003 06:53:34.989855 DUTY Scan : NO K
7004 06:53:34.990150 ZQ Calibration : PASS
7005 06:53:34.990434 Jitter Meter : NO K
7006 06:53:34.990717 CBT Training : PASS
7007 06:53:34.990998 Write leveling : NO K
7008 06:53:34.991277 RX DQS gating : PASS
7009 06:53:34.991557 RX DQ/DQS(RDDQC) : PASS
7010 06:53:34.991837 TX DQ/DQS : PASS
7011 06:53:34.992120 RX DATLAT : PASS
7012 06:53:34.992398 RX DQ/DQS(Engine): PASS
7013 06:53:34.992682 TX OE : NO K
7014 06:53:34.992965 All Pass.
7015 06:53:34.993243
7016 06:53:34.993525 CH 1, Rank 0
7017 06:53:34.993807 SW Impedance : PASS
7018 06:53:34.994156 DUTY Scan : NO K
7019 06:53:34.994447 ZQ Calibration : PASS
7020 06:53:34.994721 Jitter Meter : NO K
7021 06:53:34.994944 CBT Training : PASS
7022 06:53:34.995167 Write leveling : PASS
7023 06:53:34.995390 RX DQS gating : PASS
7024 06:53:34.995611 RX DQ/DQS(RDDQC) : PASS
7025 06:53:34.995834 TX DQ/DQS : PASS
7026 06:53:34.996059 RX DATLAT : PASS
7027 06:53:34.996281 RX DQ/DQS(Engine): PASS
7028 06:53:34.996502 TX OE : NO K
7029 06:53:34.996727 All Pass.
7030 06:53:34.996951
7031 06:53:34.997172 CH 1, Rank 1
7032 06:53:34.997396 SW Impedance : PASS
7033 06:53:34.997620 DUTY Scan : NO K
7034 06:53:34.997845 ZQ Calibration : PASS
7035 06:53:34.998081 Jitter Meter : NO K
7036 06:53:34.998304 CBT Training : PASS
7037 06:53:34.998525 Write leveling : NO K
7038 06:53:34.998747 RX DQS gating : PASS
7039 06:53:34.998968 RX DQ/DQS(RDDQC) : PASS
7040 06:53:34.999189 TX DQ/DQS : PASS
7041 06:53:34.999410 RX DATLAT : PASS
7042 06:53:34.999644 RX DQ/DQS(Engine): PASS
7043 06:53:34.999828 TX OE : NO K
7044 06:53:35.000013 All Pass.
7045 06:53:35.000211
7046 06:53:35.000400 DramC Write-DBI off
7047 06:53:35.000589 PER_BANK_REFRESH: Hybrid Mode
7048 06:53:35.000774 TX_TRACKING: ON
7049 06:53:35.000961 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7050 06:53:35.001150 [FAST_K] Save calibration result to emmc
7051 06:53:35.001346 dramc_set_vcore_voltage set vcore to 725000
7052 06:53:35.001553 Read voltage for 1600, 0
7053 06:53:35.001757 Vio18 = 0
7054 06:53:35.001968 Vcore = 725000
7055 06:53:35.002115 Vdram = 0
7056 06:53:35.002233 Vddq = 0
7057 06:53:35.002342 Vmddr = 0
7058 06:53:35.002450 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7059 06:53:35.002555 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7060 06:53:35.002662 MEM_TYPE=3, freq_sel=13
7061 06:53:35.002764 sv_algorithm_assistance_LP4_3733
7062 06:53:35.002866 ============ PULL DRAM RESETB DOWN ============
7063 06:53:35.002970 ========== PULL DRAM RESETB DOWN end =========
7064 06:53:35.003082 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7065 06:53:35.003188 ===================================
7066 06:53:35.003295 LPDDR4 DRAM CONFIGURATION
7067 06:53:35.003400 ===================================
7068 06:53:35.003505 EX_ROW_EN[0] = 0x0
7069 06:53:35.003611 EX_ROW_EN[1] = 0x0
7070 06:53:35.003714 LP4Y_EN = 0x0
7071 06:53:35.003887 WORK_FSP = 0x1
7072 06:53:35.004029 WL = 0x5
7073 06:53:35.004139 RL = 0x5
7074 06:53:35.004246 BL = 0x2
7075 06:53:35.004351 RPST = 0x0
7076 06:53:35.004456 RD_PRE = 0x0
7077 06:53:35.004561 WR_PRE = 0x1
7078 06:53:35.004670 WR_PST = 0x1
7079 06:53:35.004760 DBI_WR = 0x0
7080 06:53:35.004849 DBI_RD = 0x0
7081 06:53:35.004938 OTF = 0x1
7082 06:53:35.005028 ===================================
7083 06:53:35.005119 ===================================
7084 06:53:35.005208 ANA top config
7085 06:53:35.005297 ===================================
7086 06:53:35.005386 DLL_ASYNC_EN = 0
7087 06:53:35.005475 ALL_SLAVE_EN = 0
7088 06:53:35.005563 NEW_RANK_MODE = 1
7089 06:53:35.005654 DLL_IDLE_MODE = 1
7090 06:53:35.005743 LP45_APHY_COMB_EN = 1
7091 06:53:35.005833 TX_ODT_DIS = 0
7092 06:53:35.005922 NEW_8X_MODE = 1
7093 06:53:35.006027 ===================================
7094 06:53:35.006119 ===================================
7095 06:53:35.006209 data_rate = 3200
7096 06:53:35.006297 CKR = 1
7097 06:53:35.006387 DQ_P2S_RATIO = 8
7098 06:53:35.006477 ===================================
7099 06:53:35.006567 CA_P2S_RATIO = 8
7100 06:53:35.006656 DQ_CA_OPEN = 0
7101 06:53:35.006746 DQ_SEMI_OPEN = 0
7102 06:53:35.006836 CA_SEMI_OPEN = 0
7103 06:53:35.006927 CA_FULL_RATE = 0
7104 06:53:35.007016 DQ_CKDIV4_EN = 0
7105 06:53:35.007105 CA_CKDIV4_EN = 0
7106 06:53:35.007194 CA_PREDIV_EN = 0
7107 06:53:35.007283 PH8_DLY = 12
7108 06:53:35.007373 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7109 06:53:35.007462 DQ_AAMCK_DIV = 4
7110 06:53:35.007551 CA_AAMCK_DIV = 4
7111 06:53:35.007640 CA_ADMCK_DIV = 4
7112 06:53:35.007729 DQ_TRACK_CA_EN = 0
7113 06:53:35.007818 CA_PICK = 1600
7114 06:53:35.007907 CA_MCKIO = 1600
7115 06:53:35.007997 MCKIO_SEMI = 0
7116 06:53:35.008087 PLL_FREQ = 3068
7117 06:53:35.008177 DQ_UI_PI_RATIO = 32
7118 06:53:35.008265 CA_UI_PI_RATIO = 0
7119 06:53:35.008579 ===================================
7120 06:53:35.008685 ===================================
7121 06:53:35.008779 memory_type:LPDDR4
7122 06:53:35.008869 GP_NUM : 10
7123 06:53:35.008961 SRAM_EN : 1
7124 06:53:35.009052 MD32_EN : 0
7125 06:53:35.009141 ===================================
7126 06:53:35.009231 [ANA_INIT] >>>>>>>>>>>>>>
7127 06:53:35.009323 <<<<<< [CONFIGURE PHASE]: ANA_TX
7128 06:53:35.009413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7129 06:53:35.009504 ===================================
7130 06:53:35.009604 data_rate = 3200,PCW = 0X7600
7131 06:53:35.009683 ===================================
7132 06:53:35.009761 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7133 06:53:35.009840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7134 06:53:35.009918 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7135 06:53:35.010011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7136 06:53:35.010091 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7137 06:53:35.010170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7138 06:53:35.010248 [ANA_INIT] flow start
7139 06:53:35.010327 [ANA_INIT] PLL >>>>>>>>
7140 06:53:35.010405 [ANA_INIT] PLL <<<<<<<<
7141 06:53:35.010483 [ANA_INIT] MIDPI >>>>>>>>
7142 06:53:35.010560 [ANA_INIT] MIDPI <<<<<<<<
7143 06:53:35.010637 [ANA_INIT] DLL >>>>>>>>
7144 06:53:35.010716 [ANA_INIT] DLL <<<<<<<<
7145 06:53:35.010793 [ANA_INIT] flow end
7146 06:53:35.010870 ============ LP4 DIFF to SE enter ============
7147 06:53:35.010948 ============ LP4 DIFF to SE exit ============
7148 06:53:35.011027 [ANA_INIT] <<<<<<<<<<<<<
7149 06:53:35.011105 [Flow] Enable top DCM control >>>>>
7150 06:53:35.011183 [Flow] Enable top DCM control <<<<<
7151 06:53:35.011261 Enable DLL master slave shuffle
7152 06:53:35.011340 ==============================================================
7153 06:53:35.011419 Gating Mode config
7154 06:53:35.011497 ==============================================================
7155 06:53:35.011575 Config description:
7156 06:53:35.011653 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7157 06:53:35.011732 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7158 06:53:35.011811 SELPH_MODE 0: By rank 1: By Phase
7159 06:53:35.011889 ==============================================================
7160 06:53:35.011967 GAT_TRACK_EN = 1
7161 06:53:35.012045 RX_GATING_MODE = 2
7162 06:53:35.012122 RX_GATING_TRACK_MODE = 2
7163 06:53:35.012201 SELPH_MODE = 1
7164 06:53:35.012279 PICG_EARLY_EN = 1
7165 06:53:35.012357 VALID_LAT_VALUE = 1
7166 06:53:35.012435 ==============================================================
7167 06:53:35.012514 Enter into Gating configuration >>>>
7168 06:53:35.012592 Exit from Gating configuration <<<<
7169 06:53:35.012670 Enter into DVFS_PRE_config >>>>>
7170 06:53:35.012748 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7171 06:53:35.012829 Exit from DVFS_PRE_config <<<<<
7172 06:53:35.012907 Enter into PICG configuration >>>>
7173 06:53:35.012985 Exit from PICG configuration <<<<
7174 06:53:35.013063 [RX_INPUT] configuration >>>>>
7175 06:53:35.013141 [RX_INPUT] configuration <<<<<
7176 06:53:35.013219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7177 06:53:35.013298 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7178 06:53:35.013377 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 06:53:35.013456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 06:53:35.013535 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7181 06:53:35.013613 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7182 06:53:35.013691 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7183 06:53:35.013770 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7184 06:53:35.013848 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7185 06:53:35.013926 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7186 06:53:35.014019 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7187 06:53:35.014099 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7188 06:53:35.014178 ===================================
7189 06:53:35.014256 LPDDR4 DRAM CONFIGURATION
7190 06:53:35.014335 ===================================
7191 06:53:35.014413 EX_ROW_EN[0] = 0x0
7192 06:53:35.014492 EX_ROW_EN[1] = 0x0
7193 06:53:35.014570 LP4Y_EN = 0x0
7194 06:53:35.014654 WORK_FSP = 0x1
7195 06:53:35.014723 WL = 0x5
7196 06:53:35.014792 RL = 0x5
7197 06:53:35.014861 BL = 0x2
7198 06:53:35.014930 RPST = 0x0
7199 06:53:35.014999 RD_PRE = 0x0
7200 06:53:35.015067 WR_PRE = 0x1
7201 06:53:35.015136 WR_PST = 0x1
7202 06:53:35.015206 DBI_WR = 0x0
7203 06:53:35.015276 DBI_RD = 0x0
7204 06:53:35.015345 OTF = 0x1
7205 06:53:35.015414 ===================================
7206 06:53:35.015483 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7207 06:53:35.015553 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7208 06:53:35.015623 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 06:53:35.015693 ===================================
7210 06:53:35.015762 LPDDR4 DRAM CONFIGURATION
7211 06:53:35.015831 ===================================
7212 06:53:35.015901 EX_ROW_EN[0] = 0x10
7213 06:53:35.015971 EX_ROW_EN[1] = 0x0
7214 06:53:35.016040 LP4Y_EN = 0x0
7215 06:53:35.016109 WORK_FSP = 0x1
7216 06:53:35.016178 WL = 0x5
7217 06:53:35.016246 RL = 0x5
7218 06:53:35.016315 BL = 0x2
7219 06:53:35.016384 RPST = 0x0
7220 06:53:35.016453 RD_PRE = 0x0
7221 06:53:35.016522 WR_PRE = 0x1
7222 06:53:35.016591 WR_PST = 0x1
7223 06:53:35.016659 DBI_WR = 0x0
7224 06:53:35.016728 DBI_RD = 0x0
7225 06:53:35.016798 OTF = 0x1
7226 06:53:35.016866 ===================================
7227 06:53:35.016936 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7228 06:53:35.017006 ==
7229 06:53:35.017281 Dram Type= 6, Freq= 0, CH_0, rank 0
7230 06:53:35.017366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7231 06:53:35.017485 ==
7232 06:53:35.017605 [Duty_Offset_Calibration]
7233 06:53:35.017726 B0:2 B1:0 CA:1
7234 06:53:35.017844
7235 06:53:35.017971 [DutyScan_Calibration_Flow] k_type=0
7236 06:53:35.018067
7237 06:53:35.018185 ==CLK 0==
7238 06:53:35.018305 Final CLK duty delay cell = -4
7239 06:53:35.018399 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7240 06:53:35.018493 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7241 06:53:35.018611 [-4] AVG Duty = 4922%(X100)
7242 06:53:35.018728
7243 06:53:35.018821 CH0 CLK Duty spec in!! Max-Min= 218%
7244 06:53:35.018939 [DutyScan_Calibration_Flow] ====Done====
7245 06:53:35.019032
7246 06:53:35.019149 [DutyScan_Calibration_Flow] k_type=1
7247 06:53:35.019267
7248 06:53:35.019358 ==DQS 0 ==
7249 06:53:35.019451 Final DQS duty delay cell = 0
7250 06:53:35.019570 [0] MAX Duty = 5249%(X100), DQS PI = 34
7251 06:53:35.019693 [0] MIN Duty = 4938%(X100), DQS PI = 62
7252 06:53:35.019800 [0] AVG Duty = 5093%(X100)
7253 06:53:35.019905
7254 06:53:35.020011 ==DQS 1 ==
7255 06:53:35.020117 Final DQS duty delay cell = -4
7256 06:53:35.020224 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7257 06:53:35.020330 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7258 06:53:35.020435 [-4] AVG Duty = 4984%(X100)
7259 06:53:35.020541
7260 06:53:35.020646 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7261 06:53:35.020751
7262 06:53:35.020856 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7263 06:53:35.020963 [DutyScan_Calibration_Flow] ====Done====
7264 06:53:35.021068
7265 06:53:35.021174 [DutyScan_Calibration_Flow] k_type=3
7266 06:53:35.021279
7267 06:53:35.021384 ==DQM 0 ==
7268 06:53:35.021490 Final DQM duty delay cell = 0
7269 06:53:35.021596 [0] MAX Duty = 5093%(X100), DQS PI = 26
7270 06:53:35.021702 [0] MIN Duty = 4813%(X100), DQS PI = 50
7271 06:53:35.021808 [0] AVG Duty = 4953%(X100)
7272 06:53:35.021913
7273 06:53:35.022007 ==DQM 1 ==
7274 06:53:35.022114 Final DQM duty delay cell = 0
7275 06:53:35.022221 [0] MAX Duty = 5249%(X100), DQS PI = 30
7276 06:53:35.022327 [0] MIN Duty = 5000%(X100), DQS PI = 20
7277 06:53:35.022433 [0] AVG Duty = 5124%(X100)
7278 06:53:35.022538
7279 06:53:35.022643 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7280 06:53:35.022748
7281 06:53:35.022854 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7282 06:53:35.022959 [DutyScan_Calibration_Flow] ====Done====
7283 06:53:35.023065
7284 06:53:35.023170 [DutyScan_Calibration_Flow] k_type=2
7285 06:53:35.023275
7286 06:53:35.023380 ==DQ 0 ==
7287 06:53:35.023485 Final DQ duty delay cell = 0
7288 06:53:35.023591 [0] MAX Duty = 5124%(X100), DQS PI = 34
7289 06:53:35.023697 [0] MIN Duty = 5000%(X100), DQS PI = 0
7290 06:53:35.023803 [0] AVG Duty = 5062%(X100)
7291 06:53:35.023908
7292 06:53:35.024012 ==DQ 1 ==
7293 06:53:35.024118 Final DQ duty delay cell = 0
7294 06:53:35.024227 [0] MAX Duty = 4969%(X100), DQS PI = 50
7295 06:53:35.024336 [0] MIN Duty = 4875%(X100), DQS PI = 10
7296 06:53:35.024444 [0] AVG Duty = 4922%(X100)
7297 06:53:35.024554
7298 06:53:35.024662 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7299 06:53:35.024752
7300 06:53:35.024837 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7301 06:53:35.024924 [DutyScan_Calibration_Flow] ====Done====
7302 06:53:35.025009 ==
7303 06:53:35.025095 Dram Type= 6, Freq= 0, CH_1, rank 0
7304 06:53:35.025180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7305 06:53:35.025265 ==
7306 06:53:35.025348 [Duty_Offset_Calibration]
7307 06:53:35.025432 B0:0 B1:-1 CA:2
7308 06:53:35.025516
7309 06:53:35.025599 [DutyScan_Calibration_Flow] k_type=0
7310 06:53:35.025683
7311 06:53:35.025765 ==CLK 0==
7312 06:53:35.025849 Final CLK duty delay cell = 0
7313 06:53:35.025933 [0] MAX Duty = 5156%(X100), DQS PI = 10
7314 06:53:35.026025 [0] MIN Duty = 4906%(X100), DQS PI = 46
7315 06:53:35.026110 [0] AVG Duty = 5031%(X100)
7316 06:53:35.026194
7317 06:53:35.026278 CH1 CLK Duty spec in!! Max-Min= 250%
7318 06:53:35.026362 [DutyScan_Calibration_Flow] ====Done====
7319 06:53:35.026445
7320 06:53:35.026529 [DutyScan_Calibration_Flow] k_type=1
7321 06:53:35.026612
7322 06:53:35.026694 ==DQS 0 ==
7323 06:53:35.026778 Final DQS duty delay cell = 0
7324 06:53:35.026862 [0] MAX Duty = 5093%(X100), DQS PI = 24
7325 06:53:35.026946 [0] MIN Duty = 4969%(X100), DQS PI = 62
7326 06:53:35.027029 [0] AVG Duty = 5031%(X100)
7327 06:53:35.027112
7328 06:53:35.027195 ==DQS 1 ==
7329 06:53:35.027278 Final DQS duty delay cell = 0
7330 06:53:35.027362 [0] MAX Duty = 5187%(X100), DQS PI = 0
7331 06:53:35.027446 [0] MIN Duty = 4844%(X100), DQS PI = 32
7332 06:53:35.027530 [0] AVG Duty = 5015%(X100)
7333 06:53:35.027613
7334 06:53:35.027697 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7335 06:53:35.027780
7336 06:53:35.027863 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7337 06:53:35.027949 [DutyScan_Calibration_Flow] ====Done====
7338 06:53:35.028033
7339 06:53:35.028115 [DutyScan_Calibration_Flow] k_type=3
7340 06:53:35.028198
7341 06:53:35.028280 ==DQM 0 ==
7342 06:53:35.028363 Final DQM duty delay cell = 4
7343 06:53:35.028447 [4] MAX Duty = 5125%(X100), DQS PI = 8
7344 06:53:35.028531 [4] MIN Duty = 5000%(X100), DQS PI = 30
7345 06:53:35.028615 [4] AVG Duty = 5062%(X100)
7346 06:53:35.028697
7347 06:53:35.028779 ==DQM 1 ==
7348 06:53:35.028862 Final DQM duty delay cell = 0
7349 06:53:35.028946 [0] MAX Duty = 5281%(X100), DQS PI = 58
7350 06:53:35.029030 [0] MIN Duty = 4876%(X100), DQS PI = 34
7351 06:53:35.029112 [0] AVG Duty = 5078%(X100)
7352 06:53:35.029195
7353 06:53:35.029278 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7354 06:53:35.029362
7355 06:53:35.029445 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7356 06:53:35.029528 [DutyScan_Calibration_Flow] ====Done====
7357 06:53:35.029611
7358 06:53:35.029702 [DutyScan_Calibration_Flow] k_type=2
7359 06:53:35.029780
7360 06:53:35.029857 ==DQ 0 ==
7361 06:53:35.029935 Final DQ duty delay cell = 0
7362 06:53:35.030060 [0] MAX Duty = 5093%(X100), DQS PI = 20
7363 06:53:35.030140 [0] MIN Duty = 4969%(X100), DQS PI = 0
7364 06:53:35.030218 [0] AVG Duty = 5031%(X100)
7365 06:53:35.030294
7366 06:53:35.030369 ==DQ 1 ==
7367 06:53:35.030445 Final DQ duty delay cell = 0
7368 06:53:35.030522 [0] MAX Duty = 5062%(X100), DQS PI = 2
7369 06:53:35.030604 [0] MIN Duty = 4813%(X100), DQS PI = 34
7370 06:53:35.030686 [0] AVG Duty = 4937%(X100)
7371 06:53:35.030768
7372 06:53:35.030850 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7373 06:53:35.030931
7374 06:53:35.031007 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7375 06:53:35.031086 [DutyScan_Calibration_Flow] ====Done====
7376 06:53:35.031166 nWR fixed to 30
7377 06:53:35.031246 [ModeRegInit_LP4] CH0 RK0
7378 06:53:35.031326 [ModeRegInit_LP4] CH0 RK1
7379 06:53:35.031420 [ModeRegInit_LP4] CH1 RK0
7380 06:53:35.031514 [ModeRegInit_LP4] CH1 RK1
7381 06:53:35.031609 match AC timing 5
7382 06:53:35.031703 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7383 06:53:35.031797 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7384 06:53:35.031897 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7385 06:53:35.032004 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7386 06:53:35.032098 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7387 06:53:35.032183 [MiockJmeterHQA]
7388 06:53:35.032266
7389 06:53:35.032543 [DramcMiockJmeter] u1RxGatingPI = 0
7390 06:53:35.032665 0 : 4368, 4140
7391 06:53:35.032766 4 : 4368, 4140
7392 06:53:35.032864 8 : 4252, 4027
7393 06:53:35.032976 12 : 4252, 4027
7394 06:53:35.033060 16 : 4368, 4143
7395 06:53:35.033142 20 : 4252, 4027
7396 06:53:35.033225 24 : 4252, 4027
7397 06:53:35.033307 28 : 4363, 4138
7398 06:53:35.033389 32 : 4252, 4027
7399 06:53:35.033471 36 : 4252, 4027
7400 06:53:35.033553 40 : 4252, 4027
7401 06:53:35.033635 44 : 4255, 4029
7402 06:53:35.033717 48 : 4255, 4029
7403 06:53:35.033799 52 : 4363, 4137
7404 06:53:35.033897 56 : 4363, 4138
7405 06:53:35.034035 60 : 4365, 4140
7406 06:53:35.034117 64 : 4252, 4027
7407 06:53:35.034199 68 : 4252, 4029
7408 06:53:35.034281 72 : 4250, 4027
7409 06:53:35.034363 76 : 4250, 4027
7410 06:53:35.034444 80 : 4361, 4137
7411 06:53:35.034526 84 : 4250, 4027
7412 06:53:35.034608 88 : 4250, 3375
7413 06:53:35.034690 92 : 4250, 0
7414 06:53:35.034772 96 : 4250, 0
7415 06:53:35.034854 100 : 4252, 0
7416 06:53:35.034936 104 : 4252, 0
7417 06:53:35.035018 108 : 4252, 0
7418 06:53:35.035100 112 : 4255, 0
7419 06:53:35.035183 116 : 4252, 0
7420 06:53:35.035265 120 : 4250, 0
7421 06:53:35.035347 124 : 4250, 0
7422 06:53:35.035429 128 : 4252, 0
7423 06:53:35.035512 132 : 4363, 0
7424 06:53:35.035594 136 : 4252, 0
7425 06:53:35.035676 140 : 4250, 0
7426 06:53:35.035758 144 : 4255, 0
7427 06:53:35.035840 148 : 4252, 0
7428 06:53:35.035922 152 : 4250, 0
7429 06:53:35.036004 156 : 4252, 0
7430 06:53:35.036086 160 : 4252, 0
7431 06:53:35.036168 164 : 4250, 0
7432 06:53:35.036250 168 : 4252, 0
7433 06:53:35.036332 172 : 4252, 0
7434 06:53:35.036414 176 : 4250, 0
7435 06:53:35.036496 180 : 4250, 0
7436 06:53:35.036578 184 : 4363, 0
7437 06:53:35.036660 188 : 4366, 0
7438 06:53:35.036742 192 : 4363, 0
7439 06:53:35.036824 196 : 4252, 0
7440 06:53:35.036905 200 : 4360, 1
7441 06:53:35.036987 204 : 4250, 2219
7442 06:53:35.037069 208 : 4361, 4137
7443 06:53:35.037151 212 : 4363, 4138
7444 06:53:35.037233 216 : 4252, 4027
7445 06:53:35.037315 220 : 4360, 4137
7446 06:53:35.037397 224 : 4250, 4026
7447 06:53:35.037479 228 : 4250, 4027
7448 06:53:35.037561 232 : 4250, 4027
7449 06:53:35.037643 236 : 4363, 4139
7450 06:53:35.037725 240 : 4250, 4026
7451 06:53:35.037807 244 : 4250, 4027
7452 06:53:35.037889 248 : 4366, 4140
7453 06:53:35.038029 252 : 4250, 4026
7454 06:53:35.038113 256 : 4250, 4026
7455 06:53:35.038195 260 : 4361, 4137
7456 06:53:35.038277 264 : 4361, 4137
7457 06:53:35.038359 268 : 4250, 4026
7458 06:53:35.038441 272 : 4250, 4027
7459 06:53:35.038523 276 : 4250, 4026
7460 06:53:35.038605 280 : 4253, 4027
7461 06:53:35.038687 284 : 4249, 4027
7462 06:53:35.038769 288 : 4363, 4139
7463 06:53:35.038852 292 : 4250, 4027
7464 06:53:35.038933 296 : 4250, 4027
7465 06:53:35.039015 300 : 4363, 4140
7466 06:53:35.039097 304 : 4250, 4026
7467 06:53:35.039180 308 : 4250, 4026
7468 06:53:35.039262 312 : 4361, 4087
7469 06:53:35.039344 316 : 4361, 2223
7470 06:53:35.039426 320 : 4250, 1
7471 06:53:35.039508
7472 06:53:35.039588 MIOCK jitter meter ch=0
7473 06:53:35.039668
7474 06:53:35.039748 1T = (320-92) = 228 dly cells
7475 06:53:35.039832 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7476 06:53:35.039912 ==
7477 06:53:35.039993 Dram Type= 6, Freq= 0, CH_0, rank 0
7478 06:53:35.040074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7479 06:53:35.040154 ==
7480 06:53:35.040236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7481 06:53:35.040317 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7482 06:53:35.040398 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7483 06:53:35.040480 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7484 06:53:35.040561 [CA 0] Center 42 (12~72) winsize 61
7485 06:53:35.040642 [CA 1] Center 42 (12~72) winsize 61
7486 06:53:35.040722 [CA 2] Center 37 (7~67) winsize 61
7487 06:53:35.040803 [CA 3] Center 37 (7~67) winsize 61
7488 06:53:35.040883 [CA 4] Center 35 (5~66) winsize 62
7489 06:53:35.040963 [CA 5] Center 35 (5~65) winsize 61
7490 06:53:35.041043
7491 06:53:35.041124 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7492 06:53:35.041204
7493 06:53:35.041284 [CATrainingPosCal] consider 1 rank data
7494 06:53:35.041364 u2DelayCellTimex100 = 285/100 ps
7495 06:53:35.041445 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7496 06:53:35.041526 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7497 06:53:35.041607 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7498 06:53:35.041687 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7499 06:53:35.041768 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7500 06:53:35.041848 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7501 06:53:35.041928
7502 06:53:35.042045 CA PerBit enable=1, Macro0, CA PI delay=35
7503 06:53:35.042099
7504 06:53:35.042151 [CBTSetCACLKResult] CA Dly = 35
7505 06:53:35.042203 CS Dly: 9 (0~40)
7506 06:53:35.042255 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7507 06:53:35.042308 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7508 06:53:35.042360 ==
7509 06:53:35.042412 Dram Type= 6, Freq= 0, CH_0, rank 1
7510 06:53:35.042465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7511 06:53:35.042518 ==
7512 06:53:35.042571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7513 06:53:35.042623 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7514 06:53:35.042676 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7515 06:53:35.042728 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7516 06:53:35.042780 [CA 0] Center 43 (13~74) winsize 62
7517 06:53:35.042832 [CA 1] Center 43 (13~73) winsize 61
7518 06:53:35.042885 [CA 2] Center 38 (9~68) winsize 60
7519 06:53:35.042937 [CA 3] Center 38 (9~68) winsize 60
7520 06:53:35.042989 [CA 4] Center 37 (7~67) winsize 61
7521 06:53:35.043040 [CA 5] Center 36 (6~66) winsize 61
7522 06:53:35.043092
7523 06:53:35.043143 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7524 06:53:35.043195
7525 06:53:35.043246 [CATrainingPosCal] consider 2 rank data
7526 06:53:35.043297 u2DelayCellTimex100 = 285/100 ps
7527 06:53:35.043348 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7528 06:53:35.043400 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7529 06:53:35.043452 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7530 06:53:35.043503 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7531 06:53:35.043555 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7532 06:53:35.043606 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7533 06:53:35.043657
7534 06:53:35.043708 CA PerBit enable=1, Macro0, CA PI delay=35
7535 06:53:35.043760
7536 06:53:35.043848 [CBTSetCACLKResult] CA Dly = 35
7537 06:53:35.043984 CS Dly: 10 (0~43)
7538 06:53:35.044049 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7539 06:53:35.044101 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7540 06:53:35.044188
7541 06:53:35.044248 ----->DramcWriteLeveling(PI) begin...
7542 06:53:35.044302 ==
7543 06:53:35.044354 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 06:53:35.044407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 06:53:35.044459 ==
7546 06:53:35.044511 Write leveling (Byte 0): 35 => 35
7547 06:53:35.044564 Write leveling (Byte 1): 31 => 31
7548 06:53:35.044615 DramcWriteLeveling(PI) end<-----
7549 06:53:35.044668
7550 06:53:35.044720 ==
7551 06:53:35.044771 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 06:53:35.044822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 06:53:35.044875 ==
7554 06:53:35.044926 [Gating] SW mode calibration
7555 06:53:35.045173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7556 06:53:35.045270 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7557 06:53:35.045324 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 06:53:35.045377 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 06:53:35.045430 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7560 06:53:35.045482 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7561 06:53:35.045534 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
7562 06:53:35.045585 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7563 06:53:35.045637 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7564 06:53:35.045689 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7565 06:53:35.045741 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7566 06:53:35.045792 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 06:53:35.045844 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7568 06:53:35.045895 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7569 06:53:35.045956 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7570 06:53:35.046048 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7571 06:53:35.046100 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7572 06:53:35.046151 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 06:53:35.046203 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 06:53:35.046255 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 06:53:35.046306 1 6 8 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
7576 06:53:35.046358 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7577 06:53:35.046410 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7578 06:53:35.046461 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 06:53:35.046513 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 06:53:35.046564 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 06:53:35.046616 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 06:53:35.046668 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 06:53:35.046720 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7584 06:53:35.046773 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7585 06:53:35.046824 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7586 06:53:35.046876 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7587 06:53:35.046928 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 06:53:35.046979 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 06:53:35.047031 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 06:53:35.047083 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 06:53:35.047134 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 06:53:35.047186 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 06:53:35.047238 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 06:53:35.047289 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 06:53:35.047340 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 06:53:35.047391 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 06:53:35.047443 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 06:53:35.047494 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 06:53:35.047546 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7600 06:53:35.047597 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7601 06:53:35.047649 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7602 06:53:35.047700 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7603 06:53:35.047751 Total UI for P1: 0, mck2ui 16
7604 06:53:35.047803 best dqsien dly found for B0: ( 1, 9, 12)
7605 06:53:35.047855 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 06:53:35.047906 Total UI for P1: 0, mck2ui 16
7607 06:53:35.047958 best dqsien dly found for B1: ( 1, 9, 20)
7608 06:53:35.048009 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7609 06:53:35.048061 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7610 06:53:35.048112
7611 06:53:35.048163 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7612 06:53:35.048215 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7613 06:53:35.048266 [Gating] SW calibration Done
7614 06:53:35.048318 ==
7615 06:53:35.048369 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 06:53:35.048420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 06:53:35.048472 ==
7618 06:53:35.048523 RX Vref Scan: 0
7619 06:53:35.048574
7620 06:53:35.048626 RX Vref 0 -> 0, step: 1
7621 06:53:35.048677
7622 06:53:35.048728 RX Delay 0 -> 252, step: 8
7623 06:53:35.048780 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7624 06:53:35.048831 iDelay=200, Bit 1, Center 143 (96 ~ 191) 96
7625 06:53:35.048882 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7626 06:53:35.048934 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7627 06:53:35.048985 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7628 06:53:35.049036 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7629 06:53:35.049087 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7630 06:53:35.049139 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7631 06:53:35.049190 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7632 06:53:35.049241 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7633 06:53:35.049291 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7634 06:53:35.049343 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7635 06:53:35.049394 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7636 06:53:35.049445 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7637 06:53:35.049496 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7638 06:53:35.049547 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7639 06:53:35.049599 ==
7640 06:53:35.049650 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 06:53:35.049700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 06:53:35.049752 ==
7643 06:53:35.049804 DQS Delay:
7644 06:53:35.049855 DQS0 = 0, DQS1 = 0
7645 06:53:35.049906 DQM Delay:
7646 06:53:35.049987 DQM0 = 138, DQM1 = 126
7647 06:53:35.050055 DQ Delay:
7648 06:53:35.050106 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7649 06:53:35.050158 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7650 06:53:35.050209 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7651 06:53:35.050450 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7652 06:53:35.050526
7653 06:53:35.050594
7654 06:53:35.050646 ==
7655 06:53:35.050713 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 06:53:35.050779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 06:53:35.050831 ==
7658 06:53:35.050883
7659 06:53:35.050934
7660 06:53:35.050986 TX Vref Scan disable
7661 06:53:35.051038 == TX Byte 0 ==
7662 06:53:35.051089 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7663 06:53:35.051157 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7664 06:53:35.051275 == TX Byte 1 ==
7665 06:53:35.051359 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7666 06:53:35.051412 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7667 06:53:35.051464 ==
7668 06:53:35.051529 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 06:53:35.051581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 06:53:35.051633 ==
7671 06:53:35.051684
7672 06:53:35.051734 TX Vref early break, caculate TX vref
7673 06:53:35.051786 TX Vref=16, minBit 6, minWin=23, winSum=382
7674 06:53:35.051838 TX Vref=18, minBit 12, minWin=23, winSum=387
7675 06:53:35.051890 TX Vref=20, minBit 12, minWin=23, winSum=402
7676 06:53:35.051941 TX Vref=22, minBit 0, minWin=25, winSum=410
7677 06:53:35.051993 TX Vref=24, minBit 1, minWin=25, winSum=416
7678 06:53:35.052044 TX Vref=26, minBit 12, minWin=25, winSum=426
7679 06:53:35.052096 TX Vref=28, minBit 7, minWin=25, winSum=423
7680 06:53:35.052147 TX Vref=30, minBit 3, minWin=25, winSum=420
7681 06:53:35.052199 TX Vref=32, minBit 0, minWin=25, winSum=406
7682 06:53:35.052250 TX Vref=34, minBit 0, minWin=24, winSum=397
7683 06:53:35.052302 [TxChooseVref] Worse bit 12, Min win 25, Win sum 426, Final Vref 26
7684 06:53:35.052354
7685 06:53:35.052405 Final TX Range 0 Vref 26
7686 06:53:35.052456
7687 06:53:35.052507 ==
7688 06:53:35.052557 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 06:53:35.052608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 06:53:35.052661 ==
7691 06:53:35.052712
7692 06:53:35.052762
7693 06:53:35.052813 TX Vref Scan disable
7694 06:53:35.052864 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7695 06:53:35.052916 == TX Byte 0 ==
7696 06:53:35.052967 u2DelayCellOfst[0]=13 cells (4 PI)
7697 06:53:35.053017 u2DelayCellOfst[1]=17 cells (5 PI)
7698 06:53:35.053068 u2DelayCellOfst[2]=10 cells (3 PI)
7699 06:53:35.053119 u2DelayCellOfst[3]=13 cells (4 PI)
7700 06:53:35.053209 u2DelayCellOfst[4]=6 cells (2 PI)
7701 06:53:35.053262 u2DelayCellOfst[5]=0 cells (0 PI)
7702 06:53:35.053313 u2DelayCellOfst[6]=17 cells (5 PI)
7703 06:53:35.053365 u2DelayCellOfst[7]=13 cells (4 PI)
7704 06:53:35.053416 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7705 06:53:35.053468 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7706 06:53:35.053519 == TX Byte 1 ==
7707 06:53:35.053570 u2DelayCellOfst[8]=0 cells (0 PI)
7708 06:53:35.053622 u2DelayCellOfst[9]=0 cells (0 PI)
7709 06:53:35.053673 u2DelayCellOfst[10]=6 cells (2 PI)
7710 06:53:35.053724 u2DelayCellOfst[11]=3 cells (1 PI)
7711 06:53:35.053775 u2DelayCellOfst[12]=10 cells (3 PI)
7712 06:53:35.053827 u2DelayCellOfst[13]=13 cells (4 PI)
7713 06:53:35.053878 u2DelayCellOfst[14]=17 cells (5 PI)
7714 06:53:35.053930 u2DelayCellOfst[15]=10 cells (3 PI)
7715 06:53:35.054049 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7716 06:53:35.054100 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7717 06:53:35.054151 DramC Write-DBI on
7718 06:53:35.054203 ==
7719 06:53:35.054254 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 06:53:35.054305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 06:53:35.054357 ==
7722 06:53:35.054408
7723 06:53:35.054458
7724 06:53:35.054509 TX Vref Scan disable
7725 06:53:35.054560 == TX Byte 0 ==
7726 06:53:35.054611 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7727 06:53:35.054663 == TX Byte 1 ==
7728 06:53:35.054713 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7729 06:53:35.054765 DramC Write-DBI off
7730 06:53:35.054816
7731 06:53:35.054867 [DATLAT]
7732 06:53:35.054917 Freq=1600, CH0 RK0
7733 06:53:35.054969
7734 06:53:35.055020 DATLAT Default: 0xf
7735 06:53:35.055071 0, 0xFFFF, sum = 0
7736 06:53:35.055139 1, 0xFFFF, sum = 0
7737 06:53:35.055221 2, 0xFFFF, sum = 0
7738 06:53:35.055302 3, 0xFFFF, sum = 0
7739 06:53:35.055368 4, 0xFFFF, sum = 0
7740 06:53:35.055420 5, 0xFFFF, sum = 0
7741 06:53:35.055472 6, 0xFFFF, sum = 0
7742 06:53:35.055525 7, 0xFFFF, sum = 0
7743 06:53:35.055577 8, 0xFFFF, sum = 0
7744 06:53:35.055629 9, 0xFFFF, sum = 0
7745 06:53:35.055681 10, 0xFFFF, sum = 0
7746 06:53:35.055733 11, 0xFFFF, sum = 0
7747 06:53:35.055786 12, 0xFFFF, sum = 0
7748 06:53:35.055837 13, 0xFFFF, sum = 0
7749 06:53:35.055889 14, 0x0, sum = 1
7750 06:53:35.055942 15, 0x0, sum = 2
7751 06:53:35.055994 16, 0x0, sum = 3
7752 06:53:35.056046 17, 0x0, sum = 4
7753 06:53:35.056098 best_step = 15
7754 06:53:35.056149
7755 06:53:35.056199 ==
7756 06:53:35.056250 Dram Type= 6, Freq= 0, CH_0, rank 0
7757 06:53:35.056301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7758 06:53:35.056352 ==
7759 06:53:35.056403 RX Vref Scan: 1
7760 06:53:35.056454
7761 06:53:35.056505 Set Vref Range= 24 -> 127
7762 06:53:35.056557
7763 06:53:35.056608 RX Vref 24 -> 127, step: 1
7764 06:53:35.056658
7765 06:53:35.056709 RX Delay 19 -> 252, step: 4
7766 06:53:35.056760
7767 06:53:35.056811 Set Vref, RX VrefLevel [Byte0]: 24
7768 06:53:35.056862 [Byte1]: 24
7769 06:53:35.056914
7770 06:53:35.056964 Set Vref, RX VrefLevel [Byte0]: 25
7771 06:53:35.057015 [Byte1]: 25
7772 06:53:35.057067
7773 06:53:35.057118 Set Vref, RX VrefLevel [Byte0]: 26
7774 06:53:35.057200 [Byte1]: 26
7775 06:53:35.057288
7776 06:53:35.057357 Set Vref, RX VrefLevel [Byte0]: 27
7777 06:53:35.057411 [Byte1]: 27
7778 06:53:35.057463
7779 06:53:35.057515 Set Vref, RX VrefLevel [Byte0]: 28
7780 06:53:35.057567 [Byte1]: 28
7781 06:53:35.057618
7782 06:53:35.057670 Set Vref, RX VrefLevel [Byte0]: 29
7783 06:53:35.057722 [Byte1]: 29
7784 06:53:35.057774
7785 06:53:35.057825 Set Vref, RX VrefLevel [Byte0]: 30
7786 06:53:35.057877 [Byte1]: 30
7787 06:53:35.057929
7788 06:53:35.058025 Set Vref, RX VrefLevel [Byte0]: 31
7789 06:53:35.058090 [Byte1]: 31
7790 06:53:35.058141
7791 06:53:35.058192 Set Vref, RX VrefLevel [Byte0]: 32
7792 06:53:35.058243 [Byte1]: 32
7793 06:53:35.058295
7794 06:53:35.058346 Set Vref, RX VrefLevel [Byte0]: 33
7795 06:53:35.058397 [Byte1]: 33
7796 06:53:35.058449
7797 06:53:35.058499 Set Vref, RX VrefLevel [Byte0]: 34
7798 06:53:35.058551 [Byte1]: 34
7799 06:53:35.058601
7800 06:53:35.058652 Set Vref, RX VrefLevel [Byte0]: 35
7801 06:53:35.058704 [Byte1]: 35
7802 06:53:35.058755
7803 06:53:35.058806 Set Vref, RX VrefLevel [Byte0]: 36
7804 06:53:35.058857 [Byte1]: 36
7805 06:53:35.058908
7806 06:53:35.058959 Set Vref, RX VrefLevel [Byte0]: 37
7807 06:53:35.059011 [Byte1]: 37
7808 06:53:35.059061
7809 06:53:35.059303 Set Vref, RX VrefLevel [Byte0]: 38
7810 06:53:35.059389 [Byte1]: 38
7811 06:53:35.059442
7812 06:53:35.059494 Set Vref, RX VrefLevel [Byte0]: 39
7813 06:53:35.059546 [Byte1]: 39
7814 06:53:35.059598
7815 06:53:35.059650 Set Vref, RX VrefLevel [Byte0]: 40
7816 06:53:35.059701 [Byte1]: 40
7817 06:53:35.059752
7818 06:53:35.059804 Set Vref, RX VrefLevel [Byte0]: 41
7819 06:53:35.059855 [Byte1]: 41
7820 06:53:35.059906
7821 06:53:35.059957 Set Vref, RX VrefLevel [Byte0]: 42
7822 06:53:35.060009 [Byte1]: 42
7823 06:53:35.060061
7824 06:53:35.060112 Set Vref, RX VrefLevel [Byte0]: 43
7825 06:53:35.060164 [Byte1]: 43
7826 06:53:35.060216
7827 06:53:35.060267 Set Vref, RX VrefLevel [Byte0]: 44
7828 06:53:35.060319 [Byte1]: 44
7829 06:53:35.060371
7830 06:53:35.060422 Set Vref, RX VrefLevel [Byte0]: 45
7831 06:53:35.060474 [Byte1]: 45
7832 06:53:35.060525
7833 06:53:35.060577 Set Vref, RX VrefLevel [Byte0]: 46
7834 06:53:35.060628 [Byte1]: 46
7835 06:53:35.060680
7836 06:53:35.060731 Set Vref, RX VrefLevel [Byte0]: 47
7837 06:53:35.060782 [Byte1]: 47
7838 06:53:35.060834
7839 06:53:35.060885 Set Vref, RX VrefLevel [Byte0]: 48
7840 06:53:35.060936 [Byte1]: 48
7841 06:53:35.060987
7842 06:53:35.061038 Set Vref, RX VrefLevel [Byte0]: 49
7843 06:53:35.061090 [Byte1]: 49
7844 06:53:35.061141
7845 06:53:35.061192 Set Vref, RX VrefLevel [Byte0]: 50
7846 06:53:35.061243 [Byte1]: 50
7847 06:53:35.061295
7848 06:53:35.061346 Set Vref, RX VrefLevel [Byte0]: 51
7849 06:53:35.061397 [Byte1]: 51
7850 06:53:35.061449
7851 06:53:35.061500 Set Vref, RX VrefLevel [Byte0]: 52
7852 06:53:35.061551 [Byte1]: 52
7853 06:53:35.061602
7854 06:53:35.061654 Set Vref, RX VrefLevel [Byte0]: 53
7855 06:53:35.061705 [Byte1]: 53
7856 06:53:35.061756
7857 06:53:35.061807 Set Vref, RX VrefLevel [Byte0]: 54
7858 06:53:35.061858 [Byte1]: 54
7859 06:53:35.061909
7860 06:53:35.061991 Set Vref, RX VrefLevel [Byte0]: 55
7861 06:53:35.062071 [Byte1]: 55
7862 06:53:35.062122
7863 06:53:35.062174 Set Vref, RX VrefLevel [Byte0]: 56
7864 06:53:35.062225 [Byte1]: 56
7865 06:53:35.062277
7866 06:53:35.062327 Set Vref, RX VrefLevel [Byte0]: 57
7867 06:53:35.062379 [Byte1]: 57
7868 06:53:35.062430
7869 06:53:35.062481 Set Vref, RX VrefLevel [Byte0]: 58
7870 06:53:35.062533 [Byte1]: 58
7871 06:53:35.062584
7872 06:53:35.062635 Set Vref, RX VrefLevel [Byte0]: 59
7873 06:53:35.062686 [Byte1]: 59
7874 06:53:35.062737
7875 06:53:35.062789 Set Vref, RX VrefLevel [Byte0]: 60
7876 06:53:35.062840 [Byte1]: 60
7877 06:53:35.062891
7878 06:53:35.062943 Set Vref, RX VrefLevel [Byte0]: 61
7879 06:53:35.062995 [Byte1]: 61
7880 06:53:35.063046
7881 06:53:35.063098 Set Vref, RX VrefLevel [Byte0]: 62
7882 06:53:35.063173 [Byte1]: 62
7883 06:53:35.063238
7884 06:53:35.063290 Set Vref, RX VrefLevel [Byte0]: 63
7885 06:53:35.063341 [Byte1]: 63
7886 06:53:35.063393
7887 06:53:35.063445 Set Vref, RX VrefLevel [Byte0]: 64
7888 06:53:35.063496 [Byte1]: 64
7889 06:53:35.063548
7890 06:53:35.063599 Set Vref, RX VrefLevel [Byte0]: 65
7891 06:53:35.063650 [Byte1]: 65
7892 06:53:35.063701
7893 06:53:35.063752 Set Vref, RX VrefLevel [Byte0]: 66
7894 06:53:35.063803 [Byte1]: 66
7895 06:53:35.063855
7896 06:53:35.063907 Set Vref, RX VrefLevel [Byte0]: 67
7897 06:53:35.063958 [Byte1]: 67
7898 06:53:35.064009
7899 06:53:35.064061 Set Vref, RX VrefLevel [Byte0]: 68
7900 06:53:35.064113 [Byte1]: 68
7901 06:53:35.064164
7902 06:53:35.064214 Set Vref, RX VrefLevel [Byte0]: 69
7903 06:53:35.064266 [Byte1]: 69
7904 06:53:35.064347
7905 06:53:35.064398 Set Vref, RX VrefLevel [Byte0]: 70
7906 06:53:35.064448 [Byte1]: 70
7907 06:53:35.064500
7908 06:53:35.064551 Set Vref, RX VrefLevel [Byte0]: 71
7909 06:53:35.064603 [Byte1]: 71
7910 06:53:35.064654
7911 06:53:35.064705 Set Vref, RX VrefLevel [Byte0]: 72
7912 06:53:35.064757 [Byte1]: 72
7913 06:53:35.064809
7914 06:53:35.064861 Set Vref, RX VrefLevel [Byte0]: 73
7915 06:53:35.064912 [Byte1]: 73
7916 06:53:35.064964
7917 06:53:35.065015 Set Vref, RX VrefLevel [Byte0]: 74
7918 06:53:35.065067 [Byte1]: 74
7919 06:53:35.065118
7920 06:53:35.065169 Set Vref, RX VrefLevel [Byte0]: 75
7921 06:53:35.065221 [Byte1]: 75
7922 06:53:35.065272
7923 06:53:35.065324 Set Vref, RX VrefLevel [Byte0]: 76
7924 06:53:35.065374 [Byte1]: 76
7925 06:53:35.065426
7926 06:53:35.065477 Set Vref, RX VrefLevel [Byte0]: 77
7927 06:53:35.065528 [Byte1]: 77
7928 06:53:35.065579
7929 06:53:35.065630 Set Vref, RX VrefLevel [Byte0]: 78
7930 06:53:35.065681 [Byte1]: 78
7931 06:53:35.065732
7932 06:53:35.065782 Set Vref, RX VrefLevel [Byte0]: 79
7933 06:53:35.065834 [Byte1]: 79
7934 06:53:35.065885
7935 06:53:35.065936 Set Vref, RX VrefLevel [Byte0]: 80
7936 06:53:35.066049 [Byte1]: 80
7937 06:53:35.066113
7938 06:53:35.066165 Final RX Vref Byte 0 = 62 to rank0
7939 06:53:35.066217 Final RX Vref Byte 1 = 62 to rank0
7940 06:53:35.066269 Final RX Vref Byte 0 = 62 to rank1
7941 06:53:35.066320 Final RX Vref Byte 1 = 62 to rank1==
7942 06:53:35.066372 Dram Type= 6, Freq= 0, CH_0, rank 0
7943 06:53:35.066424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7944 06:53:35.066477 ==
7945 06:53:35.066529 DQS Delay:
7946 06:53:35.066579 DQS0 = 0, DQS1 = 0
7947 06:53:35.066631 DQM Delay:
7948 06:53:35.066682 DQM0 = 135, DQM1 = 123
7949 06:53:35.066733 DQ Delay:
7950 06:53:35.066785 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =132
7951 06:53:35.066836 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =142
7952 06:53:35.066888 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7953 06:53:35.066939 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
7954 06:53:35.195653
7955 06:53:35.196362
7956 06:53:35.196963
7957 06:53:35.197537 [DramC_TX_OE_Calibration] TA2
7958 06:53:35.198105 Original DQ_B0 (3 6) =30, OEN = 27
7959 06:53:35.198651 Original DQ_B1 (3 6) =30, OEN = 27
7960 06:53:35.199217 24, 0x0, End_B0=24 End_B1=24
7961 06:53:35.199796 25, 0x0, End_B0=25 End_B1=25
7962 06:53:35.200315 26, 0x0, End_B0=26 End_B1=26
7963 06:53:35.200834 27, 0x0, End_B0=27 End_B1=27
7964 06:53:35.201344 28, 0x0, End_B0=28 End_B1=28
7965 06:53:35.201856 29, 0x0, End_B0=29 End_B1=29
7966 06:53:35.202401 30, 0x0, End_B0=30 End_B1=30
7967 06:53:35.202914 31, 0x5151, End_B0=30 End_B1=30
7968 06:53:35.203905 Byte0 end_step=30 best_step=27
7969 06:53:35.204464 Byte1 end_step=30 best_step=27
7970 06:53:35.204993 Byte0 TX OE(2T, 0.5T) = (3, 3)
7971 06:53:35.205497 Byte1 TX OE(2T, 0.5T) = (3, 3)
7972 06:53:35.206033
7973 06:53:35.206542
7974 06:53:35.207051 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7975 06:53:35.207567 CH0 RK0: MR19=303, MR18=1D1B
7976 06:53:35.208068 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7977 06:53:35.208573
7978 06:53:35.209070 ----->DramcWriteLeveling(PI) begin...
7979 06:53:35.209582 ==
7980 06:53:35.210101 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 06:53:35.210601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7982 06:53:35.211107 ==
7983 06:53:35.211608 Write leveling (Byte 0): 37 => 37
7984 06:53:35.212108 Write leveling (Byte 1): 30 => 30
7985 06:53:35.212612 DramcWriteLeveling(PI) end<-----
7986 06:53:35.213106
7987 06:53:35.213591 ==
7988 06:53:35.214112 Dram Type= 6, Freq= 0, CH_0, rank 1
7989 06:53:35.214608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 06:53:35.215111 ==
7991 06:53:35.215606 [Gating] SW mode calibration
7992 06:53:35.216098 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7993 06:53:35.216596 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7994 06:53:35.217098 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 06:53:35.217594 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 06:53:35.218113 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 06:53:35.218610 1 4 12 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
7998 06:53:35.219105 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 06:53:35.219600 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 06:53:35.220097 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 06:53:35.220595 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 06:53:35.221090 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 06:53:35.221586 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 06:53:35.222100 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 06:53:35.222603 1 5 12 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
8006 06:53:35.223102 1 5 16 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
8007 06:53:35.223599 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 06:53:35.224095 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 06:53:35.224600 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 06:53:35.224948 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 06:53:35.225297 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 06:53:35.225648 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8013 06:53:35.226017 1 6 12 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
8014 06:53:35.226374 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 06:53:35.226728 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 06:53:35.227082 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 06:53:35.227436 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 06:53:35.227786 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 06:53:35.228137 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 06:53:35.228485 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8021 06:53:35.228835 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8022 06:53:35.229184 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8023 06:53:35.229539 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8024 06:53:35.229838 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 06:53:35.230118 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 06:53:35.230384 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 06:53:35.230648 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 06:53:35.230913 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 06:53:35.231177 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 06:53:35.231442 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 06:53:35.231707 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 06:53:35.231969 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 06:53:35.232231 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 06:53:35.232496 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 06:53:35.232762 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 06:53:35.233024 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 06:53:35.233288 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8038 06:53:35.233554 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8039 06:53:35.233819 Total UI for P1: 0, mck2ui 16
8040 06:53:35.234106 best dqsien dly found for B0: ( 1, 9, 12)
8041 06:53:35.234376 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 06:53:35.234648 Total UI for P1: 0, mck2ui 16
8043 06:53:35.234863 best dqsien dly found for B1: ( 1, 9, 16)
8044 06:53:35.235076 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8045 06:53:35.235288 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8046 06:53:35.235502
8047 06:53:35.235715 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8048 06:53:35.235928 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8049 06:53:35.236140 [Gating] SW calibration Done
8050 06:53:35.236354 ==
8051 06:53:35.236569 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 06:53:35.236782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 06:53:35.236998 ==
8054 06:53:35.237209 RX Vref Scan: 0
8055 06:53:35.237420
8056 06:53:35.237630 RX Vref 0 -> 0, step: 1
8057 06:53:35.237843
8058 06:53:35.238081 RX Delay 0 -> 252, step: 8
8059 06:53:35.238295 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8060 06:53:35.238509 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8061 06:53:35.238722 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8062 06:53:35.238935 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8063 06:53:35.239147 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8064 06:53:35.239360 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8065 06:53:35.239569 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8066 06:53:35.239762 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8067 06:53:35.239936 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8068 06:53:35.240377 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8069 06:53:35.240578 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8070 06:53:35.240764 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8071 06:53:35.240944 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8072 06:53:35.241124 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8073 06:53:35.241305 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8074 06:53:35.241487 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8075 06:53:35.241680 ==
8076 06:53:35.241879 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 06:53:35.242054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 06:53:35.242169 ==
8079 06:53:35.242277 DQS Delay:
8080 06:53:35.242384 DQS0 = 0, DQS1 = 0
8081 06:53:35.242489 DQM Delay:
8082 06:53:35.242591 DQM0 = 136, DQM1 = 125
8083 06:53:35.242694 DQ Delay:
8084 06:53:35.242796 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8085 06:53:35.242899 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8086 06:53:35.243000 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8087 06:53:35.243103 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8088 06:53:35.243204
8089 06:53:35.243305
8090 06:53:35.243405 ==
8091 06:53:35.243505 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 06:53:35.243606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 06:53:35.243709 ==
8094 06:53:35.243811
8095 06:53:35.243911
8096 06:53:35.244011 TX Vref Scan disable
8097 06:53:35.244113 == TX Byte 0 ==
8098 06:53:35.244214 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8099 06:53:35.244316 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8100 06:53:35.244417 == TX Byte 1 ==
8101 06:53:35.244526 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8102 06:53:35.244671 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8103 06:53:35.244791 ==
8104 06:53:35.244909 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 06:53:35.245057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 06:53:35.245206 ==
8107 06:53:35.245322
8108 06:53:35.245438 TX Vref early break, caculate TX vref
8109 06:53:35.245556 TX Vref=16, minBit 0, minWin=23, winSum=389
8110 06:53:35.245704 TX Vref=18, minBit 0, minWin=24, winSum=398
8111 06:53:35.245853 TX Vref=20, minBit 8, minWin=24, winSum=408
8112 06:53:35.246004 TX Vref=22, minBit 8, minWin=24, winSum=414
8113 06:53:35.246124 TX Vref=24, minBit 0, minWin=25, winSum=423
8114 06:53:35.246242 TX Vref=26, minBit 0, minWin=26, winSum=429
8115 06:53:35.246358 TX Vref=28, minBit 0, minWin=25, winSum=427
8116 06:53:35.246475 TX Vref=30, minBit 0, minWin=25, winSum=420
8117 06:53:35.246592 TX Vref=32, minBit 0, minWin=25, winSum=411
8118 06:53:35.246740 TX Vref=34, minBit 2, minWin=24, winSum=404
8119 06:53:35.246888 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 26
8120 06:53:35.247036
8121 06:53:35.247151 Final TX Range 0 Vref 26
8122 06:53:35.247267
8123 06:53:35.247412 ==
8124 06:53:35.247558 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 06:53:35.247705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 06:53:35.247853 ==
8127 06:53:35.247999
8128 06:53:35.248145
8129 06:53:35.248290 TX Vref Scan disable
8130 06:53:35.248436 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8131 06:53:35.248583 == TX Byte 0 ==
8132 06:53:35.248729 u2DelayCellOfst[0]=13 cells (4 PI)
8133 06:53:35.248877 u2DelayCellOfst[1]=20 cells (6 PI)
8134 06:53:35.249023 u2DelayCellOfst[2]=13 cells (4 PI)
8135 06:53:35.249169 u2DelayCellOfst[3]=13 cells (4 PI)
8136 06:53:35.249315 u2DelayCellOfst[4]=10 cells (3 PI)
8137 06:53:35.249461 u2DelayCellOfst[5]=0 cells (0 PI)
8138 06:53:35.249616 u2DelayCellOfst[6]=20 cells (6 PI)
8139 06:53:35.249745 u2DelayCellOfst[7]=17 cells (5 PI)
8140 06:53:35.249873 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8141 06:53:35.250004 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8142 06:53:35.250110 == TX Byte 1 ==
8143 06:53:35.250214 u2DelayCellOfst[8]=0 cells (0 PI)
8144 06:53:35.250318 u2DelayCellOfst[9]=0 cells (0 PI)
8145 06:53:35.250448 u2DelayCellOfst[10]=6 cells (2 PI)
8146 06:53:35.250578 u2DelayCellOfst[11]=3 cells (1 PI)
8147 06:53:35.250708 u2DelayCellOfst[12]=13 cells (4 PI)
8148 06:53:35.250836 u2DelayCellOfst[13]=13 cells (4 PI)
8149 06:53:35.250966 u2DelayCellOfst[14]=13 cells (4 PI)
8150 06:53:35.251094 u2DelayCellOfst[15]=10 cells (3 PI)
8151 06:53:35.251195 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8152 06:53:35.251299 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8153 06:53:35.251403 DramC Write-DBI on
8154 06:53:35.251505 ==
8155 06:53:35.251634 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 06:53:35.251732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 06:53:35.251854 ==
8158 06:53:35.251945
8159 06:53:35.252065
8160 06:53:35.252154 TX Vref Scan disable
8161 06:53:35.252244 == TX Byte 0 ==
8162 06:53:35.252335 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8163 06:53:35.252455 == TX Byte 1 ==
8164 06:53:35.252546 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8165 06:53:35.252663 DramC Write-DBI off
8166 06:53:35.252753
8167 06:53:35.252843 [DATLAT]
8168 06:53:35.252933 Freq=1600, CH0 RK1
8169 06:53:35.253023
8170 06:53:35.253112 DATLAT Default: 0xf
8171 06:53:35.253216 0, 0xFFFF, sum = 0
8172 06:53:35.253350 1, 0xFFFF, sum = 0
8173 06:53:35.253443 2, 0xFFFF, sum = 0
8174 06:53:35.253552 3, 0xFFFF, sum = 0
8175 06:53:35.253656 4, 0xFFFF, sum = 0
8176 06:53:35.253748 5, 0xFFFF, sum = 0
8177 06:53:35.253840 6, 0xFFFF, sum = 0
8178 06:53:35.253970 7, 0xFFFF, sum = 0
8179 06:53:35.254071 8, 0xFFFF, sum = 0
8180 06:53:35.254172 9, 0xFFFF, sum = 0
8181 06:53:35.254245 10, 0xFFFF, sum = 0
8182 06:53:35.254338 11, 0xFFFF, sum = 0
8183 06:53:35.254431 12, 0xFFFF, sum = 0
8184 06:53:35.254524 13, 0xFFFF, sum = 0
8185 06:53:35.254616 14, 0x0, sum = 1
8186 06:53:35.254709 15, 0x0, sum = 2
8187 06:53:35.254831 16, 0x0, sum = 3
8188 06:53:35.254923 17, 0x0, sum = 4
8189 06:53:35.255044 best_step = 15
8190 06:53:35.255134
8191 06:53:35.255240 ==
8192 06:53:35.255344 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 06:53:35.255434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 06:53:35.255525 ==
8195 06:53:35.255615 RX Vref Scan: 0
8196 06:53:35.255706
8197 06:53:35.255795 RX Vref 0 -> 0, step: 1
8198 06:53:35.255885
8199 06:53:35.255975 RX Delay 11 -> 252, step: 4
8200 06:53:35.256065 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8201 06:53:35.256155 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8202 06:53:35.256245 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8203 06:53:35.256336 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8204 06:53:35.256426 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8205 06:53:35.256516 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8206 06:53:35.256605 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8207 06:53:35.256695 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8208 06:53:35.256785 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8209 06:53:35.256947 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8210 06:53:35.257050 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8211 06:53:35.257363 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8212 06:53:35.257509 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8213 06:53:35.257636 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8214 06:53:35.257730 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8215 06:53:35.257839 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8216 06:53:35.257933 ==
8217 06:53:35.258072 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 06:53:35.258177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 06:53:35.258269 ==
8220 06:53:35.258360 DQS Delay:
8221 06:53:35.258480 DQS0 = 0, DQS1 = 0
8222 06:53:35.258584 DQM Delay:
8223 06:53:35.258688 DQM0 = 133, DQM1 = 123
8224 06:53:35.258809 DQ Delay:
8225 06:53:35.258927 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8226 06:53:35.259044 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8227 06:53:35.259135 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8228 06:53:35.259239 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8229 06:53:35.259342
8230 06:53:35.259432
8231 06:53:35.259521
8232 06:53:35.259611 [DramC_TX_OE_Calibration] TA2
8233 06:53:35.259701 Original DQ_B0 (3 6) =30, OEN = 27
8234 06:53:35.259820 Original DQ_B1 (3 6) =30, OEN = 27
8235 06:53:35.259910 24, 0x0, End_B0=24 End_B1=24
8236 06:53:35.260015 25, 0x0, End_B0=25 End_B1=25
8237 06:53:35.260121 26, 0x0, End_B0=26 End_B1=26
8238 06:53:35.260214 27, 0x0, End_B0=27 End_B1=27
8239 06:53:35.260306 28, 0x0, End_B0=28 End_B1=28
8240 06:53:35.260398 29, 0x0, End_B0=29 End_B1=29
8241 06:53:35.260490 30, 0x0, End_B0=30 End_B1=30
8242 06:53:35.260582 31, 0x4545, End_B0=30 End_B1=30
8243 06:53:35.260675 Byte0 end_step=30 best_step=27
8244 06:53:35.260765 Byte1 end_step=30 best_step=27
8245 06:53:35.260855 Byte0 TX OE(2T, 0.5T) = (3, 3)
8246 06:53:35.260945 Byte1 TX OE(2T, 0.5T) = (3, 3)
8247 06:53:35.261035
8248 06:53:35.261125
8249 06:53:35.261215 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
8250 06:53:35.261306 CH0 RK1: MR19=303, MR18=1E0B
8251 06:53:35.261397 CH0_RK1: MR19=0x303, MR18=0x1E0B, DQSOSC=394, MR23=63, INC=23, DEC=15
8252 06:53:35.261487 [RxdqsGatingPostProcess] freq 1600
8253 06:53:35.261578 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8254 06:53:35.261669 best DQS0 dly(2T, 0.5T) = (1, 1)
8255 06:53:35.261759 best DQS1 dly(2T, 0.5T) = (1, 1)
8256 06:53:35.261849 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8257 06:53:35.261945 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8258 06:53:35.262074 best DQS0 dly(2T, 0.5T) = (1, 1)
8259 06:53:35.262166 best DQS1 dly(2T, 0.5T) = (1, 1)
8260 06:53:35.262258 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8261 06:53:35.262349 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8262 06:53:35.262523 Pre-setting of DQS Precalculation
8263 06:53:35.262613 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8264 06:53:35.262703 ==
8265 06:53:35.262794 Dram Type= 6, Freq= 0, CH_1, rank 0
8266 06:53:35.262884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8267 06:53:35.262976 ==
8268 06:53:35.263066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8269 06:53:35.263157 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8270 06:53:35.263247 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8271 06:53:35.263338 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8272 06:53:35.263428 [CA 0] Center 42 (12~72) winsize 61
8273 06:53:35.263547 [CA 1] Center 42 (12~72) winsize 61
8274 06:53:35.263638 [CA 2] Center 38 (9~68) winsize 60
8275 06:53:35.263728 [CA 3] Center 37 (8~67) winsize 60
8276 06:53:35.263818 [CA 4] Center 37 (8~67) winsize 60
8277 06:53:35.263908 [CA 5] Center 37 (7~67) winsize 61
8278 06:53:35.263997
8279 06:53:35.264087 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8280 06:53:35.264177
8281 06:53:35.264267 [CATrainingPosCal] consider 1 rank data
8282 06:53:35.264357 u2DelayCellTimex100 = 285/100 ps
8283 06:53:35.264448 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8284 06:53:35.264567 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8285 06:53:35.264657 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8286 06:53:35.264747 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8287 06:53:35.264837 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8288 06:53:35.264927 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8289 06:53:35.265017
8290 06:53:35.265107 CA PerBit enable=1, Macro0, CA PI delay=37
8291 06:53:35.265197
8292 06:53:35.265286 [CBTSetCACLKResult] CA Dly = 37
8293 06:53:35.265376 CS Dly: 8 (0~39)
8294 06:53:35.265467 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8295 06:53:35.265557 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8296 06:53:35.265647 ==
8297 06:53:35.265741 Dram Type= 6, Freq= 0, CH_1, rank 1
8298 06:53:35.265829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 06:53:35.265915 ==
8300 06:53:35.266058 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8301 06:53:35.266140 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8302 06:53:35.266220 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8303 06:53:35.266301 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8304 06:53:35.266381 [CA 0] Center 43 (14~72) winsize 59
8305 06:53:35.266461 [CA 1] Center 42 (13~72) winsize 60
8306 06:53:35.266605 [CA 2] Center 38 (9~68) winsize 60
8307 06:53:35.266684 [CA 3] Center 37 (8~67) winsize 60
8308 06:53:35.266763 [CA 4] Center 38 (9~68) winsize 60
8309 06:53:35.266842 [CA 5] Center 37 (8~67) winsize 60
8310 06:53:35.266921
8311 06:53:35.266999 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8312 06:53:35.267077
8313 06:53:35.267155 [CATrainingPosCal] consider 2 rank data
8314 06:53:35.267233 u2DelayCellTimex100 = 285/100 ps
8315 06:53:35.267311 CA0 delay=43 (14~72),Diff = 6 PI (20 cell)
8316 06:53:35.267390 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8317 06:53:35.267468 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8318 06:53:35.267546 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8319 06:53:35.267625 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8320 06:53:35.267704 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8321 06:53:35.267782
8322 06:53:35.267859 CA PerBit enable=1, Macro0, CA PI delay=37
8323 06:53:35.267938
8324 06:53:35.268016 [CBTSetCACLKResult] CA Dly = 37
8325 06:53:35.268093 CS Dly: 9 (0~42)
8326 06:53:35.268170 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8327 06:53:35.268249 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8328 06:53:35.268326
8329 06:53:35.268403 ----->DramcWriteLeveling(PI) begin...
8330 06:53:35.268483 ==
8331 06:53:35.268580 Dram Type= 6, Freq= 0, CH_1, rank 0
8332 06:53:35.268702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 06:53:35.268783 ==
8334 06:53:35.269067 Write leveling (Byte 0): 25 => 25
8335 06:53:35.269206 Write leveling (Byte 1): 27 => 27
8336 06:53:35.269290 DramcWriteLeveling(PI) end<-----
8337 06:53:35.269372
8338 06:53:35.269453 ==
8339 06:53:35.269534 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 06:53:35.269616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 06:53:35.269697 ==
8342 06:53:35.269777 [Gating] SW mode calibration
8343 06:53:35.269858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8344 06:53:35.269968 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8345 06:53:35.270074 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 06:53:35.270159 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 06:53:35.270243 1 4 8 | B1->B0 | 3030 3232 | 1 0 | (0 0) (0 0)
8348 06:53:35.270326 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 06:53:35.270408 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 06:53:35.270490 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 06:53:35.270609 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 06:53:35.270692 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 06:53:35.270774 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 06:53:35.270856 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 06:53:35.270938 1 5 8 | B1->B0 | 2c2c 2a2a | 1 0 | (1 0) (1 0)
8356 06:53:35.271020 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8357 06:53:35.271102 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 06:53:35.271184 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 06:53:35.271266 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 06:53:35.271348 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 06:53:35.271430 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 06:53:35.271512 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 06:53:35.271594 1 6 8 | B1->B0 | 3737 4343 | 0 0 | (0 0) (0 0)
8364 06:53:35.271676 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 06:53:35.271758 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 06:53:35.271858 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 06:53:35.271955 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 06:53:35.272109 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 06:53:35.272190 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 06:53:35.272299 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8371 06:53:35.272379 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8372 06:53:35.272505 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8373 06:53:35.272587 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 06:53:35.272669 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 06:53:35.272765 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 06:53:35.272875 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 06:53:35.272956 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 06:53:35.273065 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 06:53:35.273145 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 06:53:35.273255 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 06:53:35.273365 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 06:53:35.273446 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 06:53:35.273526 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 06:53:35.273607 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 06:53:35.273687 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 06:53:35.273768 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 06:53:35.273848 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8388 06:53:35.273928 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8389 06:53:35.274067 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 06:53:35.274148 Total UI for P1: 0, mck2ui 16
8391 06:53:35.274229 best dqsien dly found for B0: ( 1, 9, 10)
8392 06:53:35.274310 Total UI for P1: 0, mck2ui 16
8393 06:53:35.274391 best dqsien dly found for B1: ( 1, 9, 10)
8394 06:53:35.274472 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8395 06:53:35.274557 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8396 06:53:35.274629
8397 06:53:35.274704 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8398 06:53:35.274759 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8399 06:53:35.274812 [Gating] SW calibration Done
8400 06:53:35.274864 ==
8401 06:53:35.274931 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 06:53:35.274984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 06:53:35.275039 ==
8404 06:53:35.275091 RX Vref Scan: 0
8405 06:53:35.275143
8406 06:53:35.275195 RX Vref 0 -> 0, step: 1
8407 06:53:35.275248
8408 06:53:35.275300 RX Delay 0 -> 252, step: 8
8409 06:53:35.275353 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8410 06:53:35.275406 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8411 06:53:35.275459 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8412 06:53:35.275512 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8413 06:53:35.275564 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8414 06:53:35.275617 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8415 06:53:35.275669 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8416 06:53:35.275721 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8417 06:53:35.275773 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8418 06:53:35.275825 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8419 06:53:35.275877 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8420 06:53:35.275930 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8421 06:53:35.275983 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8422 06:53:35.276035 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8423 06:53:35.276088 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8424 06:53:35.276140 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8425 06:53:35.276193 ==
8426 06:53:35.276244 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 06:53:35.276297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 06:53:35.276350 ==
8429 06:53:35.276403 DQS Delay:
8430 06:53:35.276455 DQS0 = 0, DQS1 = 0
8431 06:53:35.276507 DQM Delay:
8432 06:53:35.276560 DQM0 = 136, DQM1 = 130
8433 06:53:35.276805 DQ Delay:
8434 06:53:35.276864 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8435 06:53:35.276918 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8436 06:53:35.276971 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8437 06:53:35.277025 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8438 06:53:35.277077
8439 06:53:35.277130
8440 06:53:35.277182 ==
8441 06:53:35.277234 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 06:53:35.277287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 06:53:35.277341 ==
8444 06:53:35.277394
8445 06:53:35.277446
8446 06:53:35.277498 TX Vref Scan disable
8447 06:53:35.277550 == TX Byte 0 ==
8448 06:53:35.277603 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8449 06:53:35.277656 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8450 06:53:35.277709 == TX Byte 1 ==
8451 06:53:35.277760 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8452 06:53:35.277813 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8453 06:53:35.277866 ==
8454 06:53:35.277918 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 06:53:35.278021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 06:53:35.278074 ==
8457 06:53:35.278127
8458 06:53:35.278179 TX Vref early break, caculate TX vref
8459 06:53:35.278232 TX Vref=16, minBit 10, minWin=21, winSum=371
8460 06:53:35.278284 TX Vref=18, minBit 15, minWin=22, winSum=381
8461 06:53:35.278337 TX Vref=20, minBit 10, minWin=23, winSum=394
8462 06:53:35.278391 TX Vref=22, minBit 10, minWin=23, winSum=401
8463 06:53:35.278444 TX Vref=24, minBit 1, minWin=25, winSum=413
8464 06:53:35.278497 TX Vref=26, minBit 0, minWin=25, winSum=420
8465 06:53:35.278584 TX Vref=28, minBit 14, minWin=25, winSum=423
8466 06:53:35.278637 TX Vref=30, minBit 13, minWin=24, winSum=410
8467 06:53:35.278690 TX Vref=32, minBit 9, minWin=24, winSum=403
8468 06:53:35.278742 TX Vref=34, minBit 12, minWin=23, winSum=391
8469 06:53:35.278795 [TxChooseVref] Worse bit 14, Min win 25, Win sum 423, Final Vref 28
8470 06:53:35.278847
8471 06:53:35.278899 Final TX Range 0 Vref 28
8472 06:53:35.278952
8473 06:53:35.279003 ==
8474 06:53:35.279055 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 06:53:35.279108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 06:53:35.279161 ==
8477 06:53:35.279213
8478 06:53:35.279265
8479 06:53:35.279316 TX Vref Scan disable
8480 06:53:35.279369 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8481 06:53:35.279421 == TX Byte 0 ==
8482 06:53:35.279473 u2DelayCellOfst[0]=17 cells (5 PI)
8483 06:53:35.279526 u2DelayCellOfst[1]=10 cells (3 PI)
8484 06:53:35.279579 u2DelayCellOfst[2]=0 cells (0 PI)
8485 06:53:35.279631 u2DelayCellOfst[3]=6 cells (2 PI)
8486 06:53:35.279683 u2DelayCellOfst[4]=6 cells (2 PI)
8487 06:53:35.279735 u2DelayCellOfst[5]=17 cells (5 PI)
8488 06:53:35.279788 u2DelayCellOfst[6]=17 cells (5 PI)
8489 06:53:35.279840 u2DelayCellOfst[7]=6 cells (2 PI)
8490 06:53:35.279892 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8491 06:53:35.279945 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8492 06:53:35.279997 == TX Byte 1 ==
8493 06:53:35.280050 u2DelayCellOfst[8]=0 cells (0 PI)
8494 06:53:35.280102 u2DelayCellOfst[9]=3 cells (1 PI)
8495 06:53:35.280155 u2DelayCellOfst[10]=10 cells (3 PI)
8496 06:53:35.280207 u2DelayCellOfst[11]=3 cells (1 PI)
8497 06:53:35.280259 u2DelayCellOfst[12]=17 cells (5 PI)
8498 06:53:35.280311 u2DelayCellOfst[13]=20 cells (6 PI)
8499 06:53:35.280363 u2DelayCellOfst[14]=20 cells (6 PI)
8500 06:53:35.280416 u2DelayCellOfst[15]=17 cells (5 PI)
8501 06:53:35.280468 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8502 06:53:35.280521 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8503 06:53:35.280574 DramC Write-DBI on
8504 06:53:35.280626 ==
8505 06:53:35.280679 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 06:53:35.280731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 06:53:35.280784 ==
8508 06:53:35.280835
8509 06:53:35.280887
8510 06:53:35.280940 TX Vref Scan disable
8511 06:53:35.280992 == TX Byte 0 ==
8512 06:53:35.281044 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8513 06:53:35.281097 == TX Byte 1 ==
8514 06:53:35.281149 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8515 06:53:35.281202 DramC Write-DBI off
8516 06:53:35.281254
8517 06:53:35.281305 [DATLAT]
8518 06:53:35.281357 Freq=1600, CH1 RK0
8519 06:53:35.281410
8520 06:53:35.281461 DATLAT Default: 0xf
8521 06:53:35.281513 0, 0xFFFF, sum = 0
8522 06:53:35.281567 1, 0xFFFF, sum = 0
8523 06:53:35.281620 2, 0xFFFF, sum = 0
8524 06:53:35.281673 3, 0xFFFF, sum = 0
8525 06:53:35.281727 4, 0xFFFF, sum = 0
8526 06:53:35.281779 5, 0xFFFF, sum = 0
8527 06:53:35.281832 6, 0xFFFF, sum = 0
8528 06:53:35.281885 7, 0xFFFF, sum = 0
8529 06:53:35.281942 8, 0xFFFF, sum = 0
8530 06:53:35.282038 9, 0xFFFF, sum = 0
8531 06:53:35.282092 10, 0xFFFF, sum = 0
8532 06:53:35.282146 11, 0xFFFF, sum = 0
8533 06:53:35.282199 12, 0xFFFF, sum = 0
8534 06:53:35.282252 13, 0xFFFF, sum = 0
8535 06:53:35.282306 14, 0x0, sum = 1
8536 06:53:35.282359 15, 0x0, sum = 2
8537 06:53:35.282411 16, 0x0, sum = 3
8538 06:53:35.282464 17, 0x0, sum = 4
8539 06:53:35.282517 best_step = 15
8540 06:53:35.282569
8541 06:53:35.282620 ==
8542 06:53:35.282672 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 06:53:35.282725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 06:53:35.282778 ==
8545 06:53:35.282830 RX Vref Scan: 1
8546 06:53:35.282882
8547 06:53:35.282934 Set Vref Range= 24 -> 127
8548 06:53:35.282986
8549 06:53:35.283038 RX Vref 24 -> 127, step: 1
8550 06:53:35.283090
8551 06:53:35.283142 RX Delay 19 -> 252, step: 4
8552 06:53:35.283195
8553 06:53:35.283247 Set Vref, RX VrefLevel [Byte0]: 24
8554 06:53:35.283299 [Byte1]: 24
8555 06:53:35.283352
8556 06:53:35.283404 Set Vref, RX VrefLevel [Byte0]: 25
8557 06:53:35.283457 [Byte1]: 25
8558 06:53:35.283510
8559 06:53:35.283562 Set Vref, RX VrefLevel [Byte0]: 26
8560 06:53:35.283614 [Byte1]: 26
8561 06:53:35.283667
8562 06:53:35.283719 Set Vref, RX VrefLevel [Byte0]: 27
8563 06:53:35.283772 [Byte1]: 27
8564 06:53:35.283824
8565 06:53:35.283876 Set Vref, RX VrefLevel [Byte0]: 28
8566 06:53:35.283928 [Byte1]: 28
8567 06:53:35.283980
8568 06:53:35.284032 Set Vref, RX VrefLevel [Byte0]: 29
8569 06:53:35.284085 [Byte1]: 29
8570 06:53:35.284137
8571 06:53:35.284188 Set Vref, RX VrefLevel [Byte0]: 30
8572 06:53:35.284241 [Byte1]: 30
8573 06:53:35.284293
8574 06:53:35.284345 Set Vref, RX VrefLevel [Byte0]: 31
8575 06:53:35.284397 [Byte1]: 31
8576 06:53:35.284449
8577 06:53:35.284501 Set Vref, RX VrefLevel [Byte0]: 32
8578 06:53:35.284553 [Byte1]: 32
8579 06:53:35.284606
8580 06:53:35.284657 Set Vref, RX VrefLevel [Byte0]: 33
8581 06:53:35.284709 [Byte1]: 33
8582 06:53:35.284761
8583 06:53:35.284813 Set Vref, RX VrefLevel [Byte0]: 34
8584 06:53:35.284866 [Byte1]: 34
8585 06:53:35.284918
8586 06:53:35.284969 Set Vref, RX VrefLevel [Byte0]: 35
8587 06:53:35.285022 [Byte1]: 35
8588 06:53:35.285074
8589 06:53:35.285126 Set Vref, RX VrefLevel [Byte0]: 36
8590 06:53:35.285369 [Byte1]: 36
8591 06:53:35.285430
8592 06:53:35.285484 Set Vref, RX VrefLevel [Byte0]: 37
8593 06:53:35.285537 [Byte1]: 37
8594 06:53:35.285589
8595 06:53:35.285642 Set Vref, RX VrefLevel [Byte0]: 38
8596 06:53:35.285695 [Byte1]: 38
8597 06:53:35.285747
8598 06:53:35.285799 Set Vref, RX VrefLevel [Byte0]: 39
8599 06:53:35.285852 [Byte1]: 39
8600 06:53:35.285904
8601 06:53:35.286007 Set Vref, RX VrefLevel [Byte0]: 40
8602 06:53:35.286091 [Byte1]: 40
8603 06:53:35.286173
8604 06:53:35.286254 Set Vref, RX VrefLevel [Byte0]: 41
8605 06:53:35.286336 [Byte1]: 41
8606 06:53:35.286417
8607 06:53:35.286499 Set Vref, RX VrefLevel [Byte0]: 42
8608 06:53:35.286581 [Byte1]: 42
8609 06:53:35.286662
8610 06:53:35.286743 Set Vref, RX VrefLevel [Byte0]: 43
8611 06:53:35.286830 [Byte1]: 43
8612 06:53:35.286912
8613 06:53:35.286994 Set Vref, RX VrefLevel [Byte0]: 44
8614 06:53:35.287075 [Byte1]: 44
8615 06:53:35.287156
8616 06:53:35.287237 Set Vref, RX VrefLevel [Byte0]: 45
8617 06:53:35.287319 [Byte1]: 45
8618 06:53:35.287400
8619 06:53:35.287481 Set Vref, RX VrefLevel [Byte0]: 46
8620 06:53:35.287563 [Byte1]: 46
8621 06:53:35.287643
8622 06:53:35.287725 Set Vref, RX VrefLevel [Byte0]: 47
8623 06:53:35.287807 [Byte1]: 47
8624 06:53:35.287888
8625 06:53:35.287969 Set Vref, RX VrefLevel [Byte0]: 48
8626 06:53:35.288050 [Byte1]: 48
8627 06:53:35.288131
8628 06:53:35.288212 Set Vref, RX VrefLevel [Byte0]: 49
8629 06:53:35.288294 [Byte1]: 49
8630 06:53:35.288374
8631 06:53:35.288456 Set Vref, RX VrefLevel [Byte0]: 50
8632 06:53:35.288537 [Byte1]: 50
8633 06:53:35.288618
8634 06:53:35.288699 Set Vref, RX VrefLevel [Byte0]: 51
8635 06:53:35.288781 [Byte1]: 51
8636 06:53:35.288862
8637 06:53:35.288943 Set Vref, RX VrefLevel [Byte0]: 52
8638 06:53:35.289025 [Byte1]: 52
8639 06:53:35.289106
8640 06:53:35.289187 Set Vref, RX VrefLevel [Byte0]: 53
8641 06:53:35.289269 [Byte1]: 53
8642 06:53:35.289350
8643 06:53:35.289431 Set Vref, RX VrefLevel [Byte0]: 54
8644 06:53:35.289513 [Byte1]: 54
8645 06:53:35.289593
8646 06:53:35.289675 Set Vref, RX VrefLevel [Byte0]: 55
8647 06:53:35.289757 [Byte1]: 55
8648 06:53:35.289838
8649 06:53:35.289919 Set Vref, RX VrefLevel [Byte0]: 56
8650 06:53:35.290018 [Byte1]: 56
8651 06:53:35.290072
8652 06:53:35.290125 Set Vref, RX VrefLevel [Byte0]: 57
8653 06:53:35.290179 [Byte1]: 57
8654 06:53:35.290232
8655 06:53:35.290284 Set Vref, RX VrefLevel [Byte0]: 58
8656 06:53:35.290337 [Byte1]: 58
8657 06:53:35.290389
8658 06:53:35.290442 Set Vref, RX VrefLevel [Byte0]: 59
8659 06:53:35.290494 [Byte1]: 59
8660 06:53:35.290546
8661 06:53:35.290599 Set Vref, RX VrefLevel [Byte0]: 60
8662 06:53:35.290651 [Byte1]: 60
8663 06:53:35.290704
8664 06:53:35.290756 Set Vref, RX VrefLevel [Byte0]: 61
8665 06:53:35.290808 [Byte1]: 61
8666 06:53:35.290861
8667 06:53:35.290913 Set Vref, RX VrefLevel [Byte0]: 62
8668 06:53:35.290965 [Byte1]: 62
8669 06:53:35.291017
8670 06:53:35.291070 Set Vref, RX VrefLevel [Byte0]: 63
8671 06:53:35.291123 [Byte1]: 63
8672 06:53:35.291175
8673 06:53:35.291226 Set Vref, RX VrefLevel [Byte0]: 64
8674 06:53:35.291279 [Byte1]: 64
8675 06:53:35.291331
8676 06:53:35.291383 Set Vref, RX VrefLevel [Byte0]: 65
8677 06:53:35.291434 [Byte1]: 65
8678 06:53:35.291486
8679 06:53:35.291539 Set Vref, RX VrefLevel [Byte0]: 66
8680 06:53:35.291591 [Byte1]: 66
8681 06:53:35.291643
8682 06:53:35.291695 Set Vref, RX VrefLevel [Byte0]: 67
8683 06:53:35.291747 [Byte1]: 67
8684 06:53:35.291800
8685 06:53:35.291852 Set Vref, RX VrefLevel [Byte0]: 68
8686 06:53:35.291904 [Byte1]: 68
8687 06:53:35.291957
8688 06:53:35.292009 Set Vref, RX VrefLevel [Byte0]: 69
8689 06:53:35.292062 [Byte1]: 69
8690 06:53:35.292113
8691 06:53:35.292165 Set Vref, RX VrefLevel [Byte0]: 70
8692 06:53:35.292217 [Byte1]: 70
8693 06:53:35.292269
8694 06:53:35.292321 Set Vref, RX VrefLevel [Byte0]: 71
8695 06:53:35.292374 [Byte1]: 71
8696 06:53:35.292427
8697 06:53:35.292479 Set Vref, RX VrefLevel [Byte0]: 72
8698 06:53:35.292532 [Byte1]: 72
8699 06:53:35.292584
8700 06:53:35.292636 Set Vref, RX VrefLevel [Byte0]: 73
8701 06:53:35.292689 [Byte1]: 73
8702 06:53:35.292741
8703 06:53:35.292793 Set Vref, RX VrefLevel [Byte0]: 74
8704 06:53:35.292845 [Byte1]: 74
8705 06:53:35.292898
8706 06:53:35.292949 Set Vref, RX VrefLevel [Byte0]: 75
8707 06:53:35.293002 [Byte1]: 75
8708 06:53:35.293053
8709 06:53:35.293105 Set Vref, RX VrefLevel [Byte0]: 76
8710 06:53:35.293158 [Byte1]: 76
8711 06:53:35.293210
8712 06:53:35.293261 Set Vref, RX VrefLevel [Byte0]: 77
8713 06:53:35.293314 [Byte1]: 77
8714 06:53:35.293366
8715 06:53:35.293418 Final RX Vref Byte 0 = 57 to rank0
8716 06:53:35.293471 Final RX Vref Byte 1 = 62 to rank0
8717 06:53:35.293523 Final RX Vref Byte 0 = 57 to rank1
8718 06:53:35.293575 Final RX Vref Byte 1 = 62 to rank1==
8719 06:53:35.293629 Dram Type= 6, Freq= 0, CH_1, rank 0
8720 06:53:35.293682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8721 06:53:35.293735 ==
8722 06:53:35.293787 DQS Delay:
8723 06:53:35.293839 DQS0 = 0, DQS1 = 0
8724 06:53:35.293892 DQM Delay:
8725 06:53:35.293948 DQM0 = 133, DQM1 = 129
8726 06:53:35.294042 DQ Delay:
8727 06:53:35.294094 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8728 06:53:35.294147 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
8729 06:53:35.294199 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =124
8730 06:53:35.294252 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8731 06:53:35.294304
8732 06:53:35.294356
8733 06:53:35.294409
8734 06:53:35.294461 [DramC_TX_OE_Calibration] TA2
8735 06:53:35.294513 Original DQ_B0 (3 6) =30, OEN = 27
8736 06:53:35.294565 Original DQ_B1 (3 6) =30, OEN = 27
8737 06:53:35.294619 24, 0x0, End_B0=24 End_B1=24
8738 06:53:35.294672 25, 0x0, End_B0=25 End_B1=25
8739 06:53:35.294726 26, 0x0, End_B0=26 End_B1=26
8740 06:53:35.294780 27, 0x0, End_B0=27 End_B1=27
8741 06:53:35.294833 28, 0x0, End_B0=28 End_B1=28
8742 06:53:35.294887 29, 0x0, End_B0=29 End_B1=29
8743 06:53:35.294940 30, 0x0, End_B0=30 End_B1=30
8744 06:53:35.294993 31, 0x4141, End_B0=30 End_B1=30
8745 06:53:35.295046 Byte0 end_step=30 best_step=27
8746 06:53:35.295098 Byte1 end_step=30 best_step=27
8747 06:53:35.295150 Byte0 TX OE(2T, 0.5T) = (3, 3)
8748 06:53:35.295406 Byte1 TX OE(2T, 0.5T) = (3, 3)
8749 06:53:35.295465
8750 06:53:35.295519
8751 06:53:35.295572 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8752 06:53:35.295626 CH1 RK0: MR19=303, MR18=1927
8753 06:53:35.295680 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8754 06:53:35.295734
8755 06:53:35.295786 ----->DramcWriteLeveling(PI) begin...
8756 06:53:35.295840 ==
8757 06:53:35.295893 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 06:53:35.295945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 06:53:35.295998 ==
8760 06:53:35.296051 Write leveling (Byte 0): 25 => 25
8761 06:53:35.296103 Write leveling (Byte 1): 29 => 29
8762 06:53:35.296155 DramcWriteLeveling(PI) end<-----
8763 06:53:35.296208
8764 06:53:35.296260 ==
8765 06:53:35.296312 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 06:53:35.296364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 06:53:35.296417 ==
8768 06:53:35.296469 [Gating] SW mode calibration
8769 06:53:35.296522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8770 06:53:35.296575 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8771 06:53:35.296628 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 06:53:35.296681 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 06:53:35.296734 1 4 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8774 06:53:35.296787 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8775 06:53:35.296839 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 06:53:35.296892 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 06:53:35.296945 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 06:53:35.296997 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 06:53:35.297050 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 06:53:35.297102 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8781 06:53:35.297154 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 0)
8782 06:53:35.297207 1 5 12 | B1->B0 | 2323 3333 | 0 1 | (1 0) (1 0)
8783 06:53:35.297260 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 06:53:35.297312 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 06:53:35.297364 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 06:53:35.297417 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 06:53:35.297469 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 06:53:35.297522 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8789 06:53:35.297574 1 6 8 | B1->B0 | 4242 2626 | 0 0 | (0 0) (0 0)
8790 06:53:35.297627 1 6 12 | B1->B0 | 4646 3d3d | 0 1 | (0 0) (0 0)
8791 06:53:35.297680 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 06:53:35.297732 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 06:53:35.297784 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 06:53:35.297837 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 06:53:35.297889 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 06:53:35.297948 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8797 06:53:35.298044 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8798 06:53:35.298096 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8799 06:53:35.298150 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 06:53:35.298202 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 06:53:35.298255 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 06:53:35.298308 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 06:53:35.298361 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 06:53:35.298413 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 06:53:35.298466 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 06:53:35.298517 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 06:53:35.298570 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 06:53:35.298623 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 06:53:35.298676 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 06:53:35.298728 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 06:53:35.298780 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 06:53:35.298832 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8813 06:53:35.298885 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8814 06:53:35.298938 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8815 06:53:35.298990 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 06:53:35.299043 Total UI for P1: 0, mck2ui 16
8817 06:53:35.299097 best dqsien dly found for B0: ( 1, 9, 10)
8818 06:53:35.299149 Total UI for P1: 0, mck2ui 16
8819 06:53:35.299202 best dqsien dly found for B1: ( 1, 9, 8)
8820 06:53:35.299254 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8821 06:53:35.299307 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8822 06:53:35.299359
8823 06:53:35.299411 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8824 06:53:35.299463 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8825 06:53:35.299516 [Gating] SW calibration Done
8826 06:53:35.299568 ==
8827 06:53:35.299619 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 06:53:35.299672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 06:53:35.299726 ==
8830 06:53:35.299778 RX Vref Scan: 0
8831 06:53:35.299830
8832 06:53:35.299882 RX Vref 0 -> 0, step: 1
8833 06:53:35.299935
8834 06:53:35.299987 RX Delay 0 -> 252, step: 8
8835 06:53:35.300039 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8836 06:53:35.300092 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8837 06:53:35.300144 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8838 06:53:35.300197 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8839 06:53:35.300249 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8840 06:53:35.300301 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8841 06:53:35.300354 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8842 06:53:35.300407 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8843 06:53:35.300459 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8844 06:53:35.300512 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8845 06:53:35.300564 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8846 06:53:35.300617 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8847 06:53:35.300858 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8848 06:53:35.300917 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8849 06:53:35.300971 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8850 06:53:35.301024 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8851 06:53:35.301076 ==
8852 06:53:35.301128 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 06:53:35.301181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 06:53:35.301234 ==
8855 06:53:35.301287 DQS Delay:
8856 06:53:35.301339 DQS0 = 0, DQS1 = 0
8857 06:53:35.301391 DQM Delay:
8858 06:53:35.301444 DQM0 = 135, DQM1 = 132
8859 06:53:35.301496 DQ Delay:
8860 06:53:35.301548 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8861 06:53:35.301599 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8862 06:53:35.301652 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8863 06:53:35.301704 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =143
8864 06:53:35.301757
8865 06:53:35.301809
8866 06:53:35.301860 ==
8867 06:53:35.301913 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 06:53:35.302003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 06:53:35.302071 ==
8870 06:53:35.302123
8871 06:53:35.302175
8872 06:53:35.302226 TX Vref Scan disable
8873 06:53:35.302279 == TX Byte 0 ==
8874 06:53:35.302331 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8875 06:53:35.302384 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8876 06:53:35.302436 == TX Byte 1 ==
8877 06:53:35.302488 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8878 06:53:35.302541 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8879 06:53:35.302593 ==
8880 06:53:35.302646 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 06:53:35.302699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 06:53:35.302751 ==
8883 06:53:35.302803
8884 06:53:35.302855 TX Vref early break, caculate TX vref
8885 06:53:35.302909 TX Vref=16, minBit 8, minWin=22, winSum=381
8886 06:53:35.302962 TX Vref=18, minBit 13, minWin=22, winSum=387
8887 06:53:35.303015 TX Vref=20, minBit 8, minWin=23, winSum=397
8888 06:53:35.303068 TX Vref=22, minBit 9, minWin=23, winSum=406
8889 06:53:35.303121 TX Vref=24, minBit 11, minWin=23, winSum=413
8890 06:53:35.303174 TX Vref=26, minBit 8, minWin=25, winSum=417
8891 06:53:35.303227 TX Vref=28, minBit 10, minWin=24, winSum=414
8892 06:53:35.303280 TX Vref=30, minBit 9, minWin=24, winSum=410
8893 06:53:35.303333 TX Vref=32, minBit 0, minWin=24, winSum=398
8894 06:53:35.303386 TX Vref=34, minBit 8, minWin=22, winSum=387
8895 06:53:35.303438 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 26
8896 06:53:35.303491
8897 06:53:35.303543 Final TX Range 0 Vref 26
8898 06:53:35.303596
8899 06:53:35.303648 ==
8900 06:53:35.303700 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 06:53:35.303752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 06:53:35.303805 ==
8903 06:53:35.303857
8904 06:53:35.303909
8905 06:53:35.303961 TX Vref Scan disable
8906 06:53:35.304013 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8907 06:53:35.304066 == TX Byte 0 ==
8908 06:53:35.304119 u2DelayCellOfst[0]=13 cells (4 PI)
8909 06:53:35.304171 u2DelayCellOfst[1]=10 cells (3 PI)
8910 06:53:35.304224 u2DelayCellOfst[2]=0 cells (0 PI)
8911 06:53:35.304276 u2DelayCellOfst[3]=3 cells (1 PI)
8912 06:53:35.304328 u2DelayCellOfst[4]=6 cells (2 PI)
8913 06:53:35.304381 u2DelayCellOfst[5]=17 cells (5 PI)
8914 06:53:35.304432 u2DelayCellOfst[6]=13 cells (4 PI)
8915 06:53:35.304485 u2DelayCellOfst[7]=6 cells (2 PI)
8916 06:53:35.304537 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8917 06:53:35.304590 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8918 06:53:35.304643 == TX Byte 1 ==
8919 06:53:35.304696 u2DelayCellOfst[8]=0 cells (0 PI)
8920 06:53:35.304749 u2DelayCellOfst[9]=6 cells (2 PI)
8921 06:53:35.304801 u2DelayCellOfst[10]=13 cells (4 PI)
8922 06:53:35.304854 u2DelayCellOfst[11]=6 cells (2 PI)
8923 06:53:35.304906 u2DelayCellOfst[12]=17 cells (5 PI)
8924 06:53:35.304959 u2DelayCellOfst[13]=17 cells (5 PI)
8925 06:53:35.305012 u2DelayCellOfst[14]=20 cells (6 PI)
8926 06:53:35.305064 u2DelayCellOfst[15]=20 cells (6 PI)
8927 06:53:35.872993 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8928 06:53:35.873532 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8929 06:53:35.873896 DramC Write-DBI on
8930 06:53:35.874253 ==
8931 06:53:35.874576 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 06:53:35.874894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 06:53:35.875209 ==
8934 06:53:35.875513
8935 06:53:35.875810
8936 06:53:35.876111 TX Vref Scan disable
8937 06:53:35.876412 == TX Byte 0 ==
8938 06:53:35.876710 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8939 06:53:35.877011 == TX Byte 1 ==
8940 06:53:35.877308 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8941 06:53:35.877608 DramC Write-DBI off
8942 06:53:35.877904
8943 06:53:35.878232 [DATLAT]
8944 06:53:35.878526 Freq=1600, CH1 RK1
8945 06:53:35.878822
8946 06:53:35.879114 DATLAT Default: 0xf
8947 06:53:35.879408 0, 0xFFFF, sum = 0
8948 06:53:35.879710 1, 0xFFFF, sum = 0
8949 06:53:35.880013 2, 0xFFFF, sum = 0
8950 06:53:35.880312 3, 0xFFFF, sum = 0
8951 06:53:35.880611 4, 0xFFFF, sum = 0
8952 06:53:35.880906 5, 0xFFFF, sum = 0
8953 06:53:35.881207 6, 0xFFFF, sum = 0
8954 06:53:35.881503 7, 0xFFFF, sum = 0
8955 06:53:35.881802 8, 0xFFFF, sum = 0
8956 06:53:35.882133 9, 0xFFFF, sum = 0
8957 06:53:35.882435 10, 0xFFFF, sum = 0
8958 06:53:35.882735 11, 0xFFFF, sum = 0
8959 06:53:35.883033 12, 0xFFFF, sum = 0
8960 06:53:35.883330 13, 0xFFFF, sum = 0
8961 06:53:35.883631 14, 0x0, sum = 1
8962 06:53:35.883930 15, 0x0, sum = 2
8963 06:53:35.884231 16, 0x0, sum = 3
8964 06:53:35.884531 17, 0x0, sum = 4
8965 06:53:35.884831 best_step = 15
8966 06:53:35.885125
8967 06:53:35.885417 ==
8968 06:53:35.885711 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 06:53:35.886028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 06:53:35.886331 ==
8971 06:53:35.886628 RX Vref Scan: 0
8972 06:53:35.886921
8973 06:53:35.887214 RX Vref 0 -> 0, step: 1
8974 06:53:35.887507
8975 06:53:35.887799 RX Delay 19 -> 252, step: 4
8976 06:53:35.888093 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8977 06:53:35.888390 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8978 06:53:35.888687 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8979 06:53:35.888982 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8980 06:53:35.889277 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8981 06:53:35.889571 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8982 06:53:35.889868 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
8983 06:53:35.890185 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8984 06:53:35.890481 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8985 06:53:35.890773 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8986 06:53:35.891067 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8987 06:53:35.891362 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8988 06:53:35.891655 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8989 06:53:35.891948 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8990 06:53:35.892642 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8991 06:53:35.892977 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8992 06:53:35.893282 ==
8993 06:53:35.893581 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 06:53:35.893882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 06:53:35.894212 ==
8996 06:53:35.894554 DQS Delay:
8997 06:53:35.894911 DQS0 = 0, DQS1 = 0
8998 06:53:35.895214 DQM Delay:
8999 06:53:35.895511 DQM0 = 133, DQM1 = 130
9000 06:53:35.895808 DQ Delay:
9001 06:53:35.896102 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9002 06:53:35.896405 DQ4 =134, DQ5 =144, DQ6 =140, DQ7 =130
9003 06:53:35.896707 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
9004 06:53:35.897007 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =142
9005 06:53:35.897306
9006 06:53:35.897600
9007 06:53:35.897893
9008 06:53:35.898210 [DramC_TX_OE_Calibration] TA2
9009 06:53:35.898509 Original DQ_B0 (3 6) =30, OEN = 27
9010 06:53:35.898804 Original DQ_B1 (3 6) =30, OEN = 27
9011 06:53:35.899102 24, 0x0, End_B0=24 End_B1=24
9012 06:53:35.899406 25, 0x0, End_B0=25 End_B1=25
9013 06:53:35.899695 26, 0x0, End_B0=26 End_B1=26
9014 06:53:35.899909 27, 0x0, End_B0=27 End_B1=27
9015 06:53:35.900123 28, 0x0, End_B0=28 End_B1=28
9016 06:53:35.900339 29, 0x0, End_B0=29 End_B1=29
9017 06:53:35.900553 30, 0x0, End_B0=30 End_B1=30
9018 06:53:35.900767 31, 0x4545, End_B0=30 End_B1=30
9019 06:53:35.900982 Byte0 end_step=30 best_step=27
9020 06:53:35.901192 Byte1 end_step=30 best_step=27
9021 06:53:35.901402 Byte0 TX OE(2T, 0.5T) = (3, 3)
9022 06:53:35.901613 Byte1 TX OE(2T, 0.5T) = (3, 3)
9023 06:53:35.901824
9024 06:53:35.902047
9025 06:53:35.902257 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
9026 06:53:35.902470 CH1 RK1: MR19=303, MR18=1D08
9027 06:53:35.902682 CH1_RK1: MR19=0x303, MR18=0x1D08, DQSOSC=395, MR23=63, INC=23, DEC=15
9028 06:53:35.902896 [RxdqsGatingPostProcess] freq 1600
9029 06:53:35.903111 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9030 06:53:35.903325 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 06:53:35.903537 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 06:53:35.903751 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 06:53:35.903974 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 06:53:35.904193 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 06:53:35.904411 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 06:53:35.904636 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 06:53:35.904796 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 06:53:35.904957 Pre-setting of DQS Precalculation
9039 06:53:35.905118 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9040 06:53:35.905281 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9041 06:53:35.905443 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9042 06:53:35.905604
9043 06:53:35.905763
9044 06:53:35.906045 [Calibration Summary] 3200 Mbps
9045 06:53:35.906282 CH 0, Rank 0
9046 06:53:35.906450 SW Impedance : PASS
9047 06:53:35.906614 DUTY Scan : NO K
9048 06:53:35.906775 ZQ Calibration : PASS
9049 06:53:35.906937 Jitter Meter : NO K
9050 06:53:35.907097 CBT Training : PASS
9051 06:53:35.907258 Write leveling : PASS
9052 06:53:35.907417 RX DQS gating : PASS
9053 06:53:35.907601 RX DQ/DQS(RDDQC) : PASS
9054 06:53:35.907882 TX DQ/DQS : PASS
9055 06:53:35.908059 RX DATLAT : PASS
9056 06:53:35.908222 RX DQ/DQS(Engine): PASS
9057 06:53:35.908384 TX OE : PASS
9058 06:53:35.908548 All Pass.
9059 06:53:35.908711
9060 06:53:35.908872 CH 0, Rank 1
9061 06:53:35.909034 SW Impedance : PASS
9062 06:53:35.909194 DUTY Scan : NO K
9063 06:53:35.909358 ZQ Calibration : PASS
9064 06:53:35.909518 Jitter Meter : NO K
9065 06:53:35.909675 CBT Training : PASS
9066 06:53:35.909802 Write leveling : PASS
9067 06:53:35.909930 RX DQS gating : PASS
9068 06:53:35.910079 RX DQ/DQS(RDDQC) : PASS
9069 06:53:35.910207 TX DQ/DQS : PASS
9070 06:53:35.910334 RX DATLAT : PASS
9071 06:53:35.910460 RX DQ/DQS(Engine): PASS
9072 06:53:35.910586 TX OE : PASS
9073 06:53:35.910714 All Pass.
9074 06:53:35.910840
9075 06:53:35.910966 CH 1, Rank 0
9076 06:53:35.911094 SW Impedance : PASS
9077 06:53:35.911221 DUTY Scan : NO K
9078 06:53:35.911349 ZQ Calibration : PASS
9079 06:53:35.911476 Jitter Meter : NO K
9080 06:53:35.911602 CBT Training : PASS
9081 06:53:35.911729 Write leveling : PASS
9082 06:53:35.911856 RX DQS gating : PASS
9083 06:53:35.911983 RX DQ/DQS(RDDQC) : PASS
9084 06:53:35.912109 TX DQ/DQS : PASS
9085 06:53:35.912236 RX DATLAT : PASS
9086 06:53:35.912360 RX DQ/DQS(Engine): PASS
9087 06:53:35.912486 TX OE : PASS
9088 06:53:35.912613 All Pass.
9089 06:53:35.912740
9090 06:53:35.912865 CH 1, Rank 1
9091 06:53:35.912991 SW Impedance : PASS
9092 06:53:35.913117 DUTY Scan : NO K
9093 06:53:35.913245 ZQ Calibration : PASS
9094 06:53:35.913372 Jitter Meter : NO K
9095 06:53:35.913498 CBT Training : PASS
9096 06:53:35.913624 Write leveling : PASS
9097 06:53:35.913750 RX DQS gating : PASS
9098 06:53:35.913875 RX DQ/DQS(RDDQC) : PASS
9099 06:53:35.914023 TX DQ/DQS : PASS
9100 06:53:35.914154 RX DATLAT : PASS
9101 06:53:35.914280 RX DQ/DQS(Engine): PASS
9102 06:53:35.914407 TX OE : PASS
9103 06:53:35.914535 All Pass.
9104 06:53:35.914673
9105 06:53:35.914775 DramC Write-DBI on
9106 06:53:35.914879 PER_BANK_REFRESH: Hybrid Mode
9107 06:53:35.914984 TX_TRACKING: ON
9108 06:53:35.915089 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9109 06:53:35.915197 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9110 06:53:35.915304 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9111 06:53:35.915410 [FAST_K] Save calibration result to emmc
9112 06:53:35.915516 sync common calibartion params.
9113 06:53:35.915621 sync cbt_mode0:1, 1:1
9114 06:53:35.915726 dram_init: ddr_geometry: 2
9115 06:53:35.915832 dram_init: ddr_geometry: 2
9116 06:53:35.915936 dram_init: ddr_geometry: 2
9117 06:53:35.916040 0:dram_rank_size:100000000
9118 06:53:35.916147 1:dram_rank_size:100000000
9119 06:53:35.916256 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9120 06:53:35.916361 DFS_SHUFFLE_HW_MODE: ON
9121 06:53:35.916466 dramc_set_vcore_voltage set vcore to 725000
9122 06:53:35.916570 Read voltage for 1600, 0
9123 06:53:35.916676 Vio18 = 0
9124 06:53:35.916781 Vcore = 725000
9125 06:53:35.916885 Vdram = 0
9126 06:53:35.916989 Vddq = 0
9127 06:53:35.917093 Vmddr = 0
9128 06:53:35.917197 switch to 3200 Mbps bootup
9129 06:53:35.917302 [DramcRunTimeConfig]
9130 06:53:35.917406 PHYPLL
9131 06:53:35.917509 DPM_CONTROL_AFTERK: ON
9132 06:53:35.917614 PER_BANK_REFRESH: ON
9133 06:53:35.917718 REFRESH_OVERHEAD_REDUCTION: ON
9134 06:53:35.917824 CMD_PICG_NEW_MODE: OFF
9135 06:53:35.917927 XRTWTW_NEW_MODE: ON
9136 06:53:35.918047 XRTRTR_NEW_MODE: ON
9137 06:53:35.918380 TX_TRACKING: ON
9138 06:53:35.918497 RDSEL_TRACKING: OFF
9139 06:53:35.918605 DQS Precalculation for DVFS: ON
9140 06:53:35.918711 RX_TRACKING: OFF
9141 06:53:35.918816 HW_GATING DBG: ON
9142 06:53:35.918922 ZQCS_ENABLE_LP4: ON
9143 06:53:35.919027 RX_PICG_NEW_MODE: ON
9144 06:53:35.919133 TX_PICG_NEW_MODE: ON
9145 06:53:35.919238 ENABLE_RX_DCM_DPHY: ON
9146 06:53:35.919343 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9147 06:53:35.919448 DUMMY_READ_FOR_TRACKING: OFF
9148 06:53:35.919553 !!! SPM_CONTROL_AFTERK: OFF
9149 06:53:35.919673 !!! SPM could not control APHY
9150 06:53:35.919764 IMPEDANCE_TRACKING: ON
9151 06:53:35.919853 TEMP_SENSOR: ON
9152 06:53:35.919941 HW_SAVE_FOR_SR: OFF
9153 06:53:35.920032 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9154 06:53:35.920121 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9155 06:53:35.920211 Read ODT Tracking: ON
9156 06:53:35.920299 Refresh Rate DeBounce: ON
9157 06:53:35.920390 DFS_NO_QUEUE_FLUSH: ON
9158 06:53:35.920479 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9159 06:53:35.920568 ENABLE_DFS_RUNTIME_MRW: OFF
9160 06:53:35.920656 DDR_RESERVE_NEW_MODE: ON
9161 06:53:35.920745 MR_CBT_SWITCH_FREQ: ON
9162 06:53:35.920834 =========================
9163 06:53:35.920923 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9164 06:53:35.921014 dram_init: ddr_geometry: 2
9165 06:53:35.921104 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9166 06:53:35.921195 dram_init: dram init end (result: 0)
9167 06:53:35.921285 DRAM-K: Full calibration passed in 24542 msecs
9168 06:53:35.921375 MRC: failed to locate region type 0.
9169 06:53:35.921465 DRAM rank0 size:0x100000000,
9170 06:53:35.921554 DRAM rank1 size=0x100000000
9171 06:53:35.921644 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9172 06:53:35.921735 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9173 06:53:35.921825 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9174 06:53:35.921915 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9175 06:53:35.922025 DRAM rank0 size:0x100000000,
9176 06:53:35.922115 DRAM rank1 size=0x100000000
9177 06:53:35.922204 CBMEM:
9178 06:53:35.922293 IMD: root @ 0xfffff000 254 entries.
9179 06:53:35.922385 IMD: root @ 0xffffec00 62 entries.
9180 06:53:35.922475 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9181 06:53:35.922566 WARNING: RO_VPD is uninitialized or empty.
9182 06:53:35.922656 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9183 06:53:35.922747 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9184 06:53:35.922838 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9185 06:53:35.922929 BS: romstage times (exec / console): total (unknown) / 24036 ms
9186 06:53:35.923018
9187 06:53:35.923108
9188 06:53:35.923198 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9189 06:53:35.923289 ARM64: Exception handlers installed.
9190 06:53:35.923378 ARM64: Testing exception
9191 06:53:35.923479 ARM64: Done test exception
9192 06:53:35.923570 Enumerating buses...
9193 06:53:35.923660 Show all devs... Before device enumeration.
9194 06:53:35.923751 Root Device: enabled 1
9195 06:53:35.923840 CPU_CLUSTER: 0: enabled 1
9196 06:53:35.923929 CPU: 00: enabled 1
9197 06:53:35.924018 Compare with tree...
9198 06:53:35.924106 Root Device: enabled 1
9199 06:53:35.924196 CPU_CLUSTER: 0: enabled 1
9200 06:53:35.924285 CPU: 00: enabled 1
9201 06:53:35.924374 Root Device scanning...
9202 06:53:35.924464 scan_static_bus for Root Device
9203 06:53:35.924553 CPU_CLUSTER: 0 enabled
9204 06:53:35.924647 scan_static_bus for Root Device done
9205 06:53:35.924726 scan_bus: bus Root Device finished in 8 msecs
9206 06:53:35.924803 done
9207 06:53:35.924880 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9208 06:53:35.924959 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9209 06:53:35.925038 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9210 06:53:35.925117 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9211 06:53:35.925196 Allocating resources...
9212 06:53:35.925273 Reading resources...
9213 06:53:35.925352 Root Device read_resources bus 0 link: 0
9214 06:53:35.925430 DRAM rank0 size:0x100000000,
9215 06:53:35.925507 DRAM rank1 size=0x100000000
9216 06:53:35.925585 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9217 06:53:35.925663 CPU: 00 missing read_resources
9218 06:53:35.925741 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9219 06:53:35.925819 Root Device read_resources bus 0 link: 0 done
9220 06:53:35.925896 Done reading resources.
9221 06:53:35.925988 Show resources in subtree (Root Device)...After reading.
9222 06:53:35.926069 Root Device child on link 0 CPU_CLUSTER: 0
9223 06:53:35.926149 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 06:53:35.926227 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 06:53:35.926306 CPU: 00
9226 06:53:35.926384 Root Device assign_resources, bus 0 link: 0
9227 06:53:35.926463 CPU_CLUSTER: 0 missing set_resources
9228 06:53:35.926541 Root Device assign_resources, bus 0 link: 0 done
9229 06:53:35.926619 Done setting resources.
9230 06:53:35.926697 Show resources in subtree (Root Device)...After assigning values.
9231 06:53:35.926775 Root Device child on link 0 CPU_CLUSTER: 0
9232 06:53:35.926854 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 06:53:35.926934 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 06:53:35.927013 CPU: 00
9235 06:53:35.927091 Done allocating resources.
9236 06:53:35.927169 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9237 06:53:35.927248 Enabling resources...
9238 06:53:35.927326 done.
9239 06:53:35.927403 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9240 06:53:35.927510 Initializing devices...
9241 06:53:35.927637 Root Device init
9242 06:53:35.927722 init hardware done!
9243 06:53:35.927802 0x00000018: ctrlr->caps
9244 06:53:35.927883 52.000 MHz: ctrlr->f_max
9245 06:53:35.927965 0.400 MHz: ctrlr->f_min
9246 06:53:35.928045 0x40ff8080: ctrlr->voltages
9247 06:53:35.928327 sclk: 390625
9248 06:53:35.928413 Bus Width = 1
9249 06:53:35.928493 sclk: 390625
9250 06:53:35.928571 Bus Width = 1
9251 06:53:35.928648 Early init status = 3
9252 06:53:35.928726 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9253 06:53:35.928807 in-header: 03 fc 00 00 01 00 00 00
9254 06:53:35.928886 in-data: 00
9255 06:53:35.928963 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9256 06:53:35.929043 in-header: 03 fd 00 00 00 00 00 00
9257 06:53:35.929122 in-data:
9258 06:53:35.929199 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9259 06:53:35.929278 in-header: 03 fc 00 00 01 00 00 00
9260 06:53:35.929355 in-data: 00
9261 06:53:35.929449 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9262 06:53:35.934761 in-header: 03 fd 00 00 00 00 00 00
9263 06:53:35.938308 in-data:
9264 06:53:35.941324 [SSUSB] Setting up USB HOST controller...
9265 06:53:35.944825 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9266 06:53:35.948036 [SSUSB] phy power-on done.
9267 06:53:35.951472 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9268 06:53:35.958189 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9269 06:53:35.961241 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9270 06:53:35.968156 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9271 06:53:35.974847 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9272 06:53:35.981227 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9273 06:53:35.988042 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9274 06:53:35.994569 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9275 06:53:35.998060 SPM: binary array size = 0x9dc
9276 06:53:36.001119 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9277 06:53:36.007686 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9278 06:53:36.014644 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9279 06:53:36.021298 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9280 06:53:36.024704 configure_display: Starting display init
9281 06:53:36.058552 anx7625_power_on_init: Init interface.
9282 06:53:36.061643 anx7625_disable_pd_protocol: Disabled PD feature.
9283 06:53:36.064899 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9284 06:53:36.093162 anx7625_start_dp_work: Secure OCM version=00
9285 06:53:36.096221 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9286 06:53:36.110747 sp_tx_get_edid_block: EDID Block = 1
9287 06:53:36.213852 Extracted contents:
9288 06:53:36.217121 header: 00 ff ff ff ff ff ff 00
9289 06:53:36.220293 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9290 06:53:36.223458 version: 01 04
9291 06:53:36.226917 basic params: 95 1f 11 78 0a
9292 06:53:36.230316 chroma info: 76 90 94 55 54 90 27 21 50 54
9293 06:53:36.233228 established: 00 00 00
9294 06:53:36.239990 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9295 06:53:36.243312 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9296 06:53:36.249719 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9297 06:53:36.256340 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9298 06:53:36.262889 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9299 06:53:36.266212 extensions: 00
9300 06:53:36.266506 checksum: fb
9301 06:53:36.266740
9302 06:53:36.269932 Manufacturer: IVO Model 57d Serial Number 0
9303 06:53:36.273400 Made week 0 of 2020
9304 06:53:36.273798 EDID version: 1.4
9305 06:53:36.276459 Digital display
9306 06:53:36.279631 6 bits per primary color channel
9307 06:53:36.279940 DisplayPort interface
9308 06:53:36.283252 Maximum image size: 31 cm x 17 cm
9309 06:53:36.286381 Gamma: 220%
9310 06:53:36.286681 Check DPMS levels
9311 06:53:36.290365 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9312 06:53:36.293162 First detailed timing is preferred timing
9313 06:53:36.296911 Established timings supported:
9314 06:53:36.300201 Standard timings supported:
9315 06:53:36.303119 Detailed timings
9316 06:53:36.306834 Hex of detail: 383680a07038204018303c0035ae10000019
9317 06:53:36.309623 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9318 06:53:36.316204 0780 0798 07c8 0820 hborder 0
9319 06:53:36.319858 0438 043b 0447 0458 vborder 0
9320 06:53:36.323257 -hsync -vsync
9321 06:53:36.323818 Did detailed timing
9322 06:53:36.326867 Hex of detail: 000000000000000000000000000000000000
9323 06:53:36.330009 Manufacturer-specified data, tag 0
9324 06:53:36.336554 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9325 06:53:36.337116 ASCII string: InfoVision
9326 06:53:36.343190 Hex of detail: 000000fe00523134304e574635205248200a
9327 06:53:36.346171 ASCII string: R140NWF5 RH
9328 06:53:36.346625 Checksum
9329 06:53:36.346986 Checksum: 0xfb (valid)
9330 06:53:36.353375 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9331 06:53:36.356459 DSI data_rate: 832800000 bps
9332 06:53:36.359547 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9333 06:53:36.366191 anx7625_parse_edid: pixelclock(138800).
9334 06:53:36.369639 hactive(1920), hsync(48), hfp(24), hbp(88)
9335 06:53:36.373088 vactive(1080), vsync(12), vfp(3), vbp(17)
9336 06:53:36.376088 anx7625_dsi_config: config dsi.
9337 06:53:36.382556 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9338 06:53:36.395803 anx7625_dsi_config: success to config DSI
9339 06:53:36.399130 anx7625_dp_start: MIPI phy setup OK.
9340 06:53:36.402642 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9341 06:53:36.405799 mtk_ddp_mode_set invalid vrefresh 60
9342 06:53:36.408977 main_disp_path_setup
9343 06:53:36.409588 ovl_layer_smi_id_en
9344 06:53:36.412472 ovl_layer_smi_id_en
9345 06:53:36.413032 ccorr_config
9346 06:53:36.413393 aal_config
9347 06:53:36.415478 gamma_config
9348 06:53:36.415933 postmask_config
9349 06:53:36.418597 dither_config
9350 06:53:36.422780 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9351 06:53:36.428993 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9352 06:53:36.432247 Root Device init finished in 555 msecs
9353 06:53:36.432811 CPU_CLUSTER: 0 init
9354 06:53:36.442607 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9355 06:53:36.446008 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9356 06:53:36.448702 APU_MBOX 0x190000b0 = 0x10001
9357 06:53:36.452250 APU_MBOX 0x190001b0 = 0x10001
9358 06:53:36.455759 APU_MBOX 0x190005b0 = 0x10001
9359 06:53:36.458843 APU_MBOX 0x190006b0 = 0x10001
9360 06:53:36.461865 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9361 06:53:36.475178 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9362 06:53:36.487026 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9363 06:53:36.493597 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9364 06:53:36.505315 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9365 06:53:36.514299 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9366 06:53:36.517868 CPU_CLUSTER: 0 init finished in 81 msecs
9367 06:53:36.521486 Devices initialized
9368 06:53:36.524213 Show all devs... After init.
9369 06:53:36.524674 Root Device: enabled 1
9370 06:53:36.527800 CPU_CLUSTER: 0: enabled 1
9371 06:53:36.531386 CPU: 00: enabled 1
9372 06:53:36.534870 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9373 06:53:36.537861 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9374 06:53:36.540740 ELOG: NV offset 0x57f000 size 0x1000
9375 06:53:36.547884 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9376 06:53:36.554504 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9377 06:53:36.557673 ELOG: Event(17) added with size 13 at 2024-02-03 06:53:02 UTC
9378 06:53:36.560799 out: cmd=0x121: 03 db 21 01 00 00 00 00
9379 06:53:36.565014 in-header: 03 07 00 00 2c 00 00 00
9380 06:53:36.577906 in-data: 58 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9381 06:53:36.585403 ELOG: Event(A1) added with size 10 at 2024-02-03 06:53:02 UTC
9382 06:53:36.591542 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9383 06:53:36.598464 ELOG: Event(A0) added with size 9 at 2024-02-03 06:53:02 UTC
9384 06:53:36.601481 elog_add_boot_reason: Logged dev mode boot
9385 06:53:36.604590 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9386 06:53:36.608104 Finalize devices...
9387 06:53:36.608564 Devices finalized
9388 06:53:36.614526 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9389 06:53:36.617765 Writing coreboot table at 0xffe64000
9390 06:53:36.621445 0. 000000000010a000-0000000000113fff: RAMSTAGE
9391 06:53:36.624881 1. 0000000040000000-00000000400fffff: RAM
9392 06:53:36.628224 2. 0000000040100000-000000004032afff: RAMSTAGE
9393 06:53:36.634564 3. 000000004032b000-00000000545fffff: RAM
9394 06:53:36.637917 4. 0000000054600000-000000005465ffff: BL31
9395 06:53:36.640998 5. 0000000054660000-00000000ffe63fff: RAM
9396 06:53:36.644922 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9397 06:53:36.651195 7. 0000000100000000-000000023fffffff: RAM
9398 06:53:36.651768 Passing 5 GPIOs to payload:
9399 06:53:36.658061 NAME | PORT | POLARITY | VALUE
9400 06:53:36.661362 EC in RW | 0x000000aa | low | undefined
9401 06:53:36.668125 EC interrupt | 0x00000005 | low | undefined
9402 06:53:36.671206 TPM interrupt | 0x000000ab | high | undefined
9403 06:53:36.674898 SD card detect | 0x00000011 | high | undefined
9404 06:53:36.681125 speaker enable | 0x00000093 | high | undefined
9405 06:53:36.684429 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9406 06:53:36.688236 in-header: 03 f9 00 00 02 00 00 00
9407 06:53:36.688709 in-data: 02 00
9408 06:53:36.691258 ADC[4]: Raw value=901032 ID=7
9409 06:53:36.694718 ADC[3]: Raw value=212810 ID=1
9410 06:53:36.695285 RAM Code: 0x71
9411 06:53:36.697576 ADC[6]: Raw value=74502 ID=0
9412 06:53:36.701326 ADC[5]: Raw value=212072 ID=1
9413 06:53:36.701894 SKU Code: 0x1
9414 06:53:36.707989 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3234
9415 06:53:36.711086 coreboot table: 964 bytes.
9416 06:53:36.713920 IMD ROOT 0. 0xfffff000 0x00001000
9417 06:53:36.717326 IMD SMALL 1. 0xffffe000 0x00001000
9418 06:53:36.720726 RO MCACHE 2. 0xffffc000 0x00001104
9419 06:53:36.724091 CONSOLE 3. 0xfff7c000 0x00080000
9420 06:53:36.727598 FMAP 4. 0xfff7b000 0x00000452
9421 06:53:36.730942 TIME STAMP 5. 0xfff7a000 0x00000910
9422 06:53:36.733987 VBOOT WORK 6. 0xfff66000 0x00014000
9423 06:53:36.737396 RAMOOPS 7. 0xffe66000 0x00100000
9424 06:53:36.740844 COREBOOT 8. 0xffe64000 0x00002000
9425 06:53:36.741406 IMD small region:
9426 06:53:36.744055 IMD ROOT 0. 0xffffec00 0x00000400
9427 06:53:36.747388 VPD 1. 0xffffeb80 0x0000006c
9428 06:53:36.750591 MMC STATUS 2. 0xffffeb60 0x00000004
9429 06:53:36.757769 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9430 06:53:36.758372 Probing TPM: done!
9431 06:53:36.764412 Connected to device vid:did:rid of 1ae0:0028:00
9432 06:53:36.771003 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9433 06:53:36.778624 Initialized TPM device CR50 revision 0
9434 06:53:36.779203 Checking cr50 for pending updates
9435 06:53:36.784010 Reading cr50 TPM mode
9436 06:53:36.792514 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9437 06:53:36.799197 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9438 06:53:36.839715 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9439 06:53:36.842567 Checking segment from ROM address 0x40100000
9440 06:53:36.846074 Checking segment from ROM address 0x4010001c
9441 06:53:36.852898 Loading segment from ROM address 0x40100000
9442 06:53:36.853462 code (compression=0)
9443 06:53:36.862772 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9444 06:53:36.869544 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9445 06:53:36.870147 it's not compressed!
9446 06:53:36.876367 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9447 06:53:36.879212 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9448 06:53:36.899898 Loading segment from ROM address 0x4010001c
9449 06:53:36.900464 Entry Point 0x80000000
9450 06:53:36.902958 Loaded segments
9451 06:53:36.906576 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9452 06:53:36.913241 Jumping to boot code at 0x80000000(0xffe64000)
9453 06:53:36.919831 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9454 06:53:36.926560 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9455 06:53:36.934369 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9456 06:53:36.937519 Checking segment from ROM address 0x40100000
9457 06:53:36.940761 Checking segment from ROM address 0x4010001c
9458 06:53:36.947288 Loading segment from ROM address 0x40100000
9459 06:53:36.947757 code (compression=1)
9460 06:53:36.954373 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9461 06:53:36.964214 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9462 06:53:36.964784 using LZMA
9463 06:53:36.972871 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9464 06:53:36.979112 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9465 06:53:36.982825 Loading segment from ROM address 0x4010001c
9466 06:53:36.983390 Entry Point 0x54601000
9467 06:53:36.986028 Loaded segments
9468 06:53:36.989315 NOTICE: MT8192 bl31_setup
9469 06:53:36.996134 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9470 06:53:36.999582 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9471 06:53:37.002726 WARNING: region 0:
9472 06:53:37.006318 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 06:53:37.006896 WARNING: region 1:
9474 06:53:37.012962 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9475 06:53:37.016399 WARNING: region 2:
9476 06:53:37.019766 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9477 06:53:37.022629 WARNING: region 3:
9478 06:53:37.026223 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 06:53:37.029676 WARNING: region 4:
9480 06:53:37.036371 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 06:53:37.036953 WARNING: region 5:
9482 06:53:37.039405 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 06:53:37.042802 WARNING: region 6:
9484 06:53:37.046168 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 06:53:37.049397 WARNING: region 7:
9486 06:53:37.053030 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 06:53:37.059818 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9488 06:53:37.062925 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9489 06:53:37.066469 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9490 06:53:37.073343 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9491 06:53:37.076759 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9492 06:53:37.079734 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9493 06:53:37.086360 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9494 06:53:37.089473 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9495 06:53:37.093048 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9496 06:53:37.099744 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9497 06:53:37.103378 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9498 06:53:37.110086 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9499 06:53:37.112947 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9500 06:53:37.116164 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9501 06:53:37.123367 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9502 06:53:37.126456 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9503 06:53:37.129866 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9504 06:53:37.136990 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9505 06:53:37.139604 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9506 06:53:37.143085 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9507 06:53:37.149606 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9508 06:53:37.152891 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9509 06:53:37.159785 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9510 06:53:37.163582 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9511 06:53:37.166313 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9512 06:53:37.173458 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9513 06:53:37.176254 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9514 06:53:37.183192 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9515 06:53:37.186863 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9516 06:53:37.189988 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9517 06:53:37.196803 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9518 06:53:37.200282 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9519 06:53:37.203749 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9520 06:53:37.209870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9521 06:53:37.213101 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9522 06:53:37.216692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9523 06:53:37.220281 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9524 06:53:37.226630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9525 06:53:37.229652 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9526 06:53:37.233106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9527 06:53:37.236565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9528 06:53:37.243100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9529 06:53:37.246315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9530 06:53:37.249931 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9531 06:53:37.253388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9532 06:53:37.260008 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9533 06:53:37.262989 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9534 06:53:37.266054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9535 06:53:37.273389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9536 06:53:37.276649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9537 06:53:37.279912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9538 06:53:37.286549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9539 06:53:37.289901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9540 06:53:37.296734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9541 06:53:37.299976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9542 06:53:37.306726 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9543 06:53:37.310403 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9544 06:53:37.314035 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9545 06:53:37.320437 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9546 06:53:37.323491 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9547 06:53:37.330305 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9548 06:53:37.333651 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9549 06:53:37.340214 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9550 06:53:37.343396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9551 06:53:37.346797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9552 06:53:37.353548 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9553 06:53:37.356659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9554 06:53:37.363506 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9555 06:53:37.366713 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9556 06:53:37.373642 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9557 06:53:37.376534 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9558 06:53:37.380166 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9559 06:53:37.386982 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9560 06:53:37.390064 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9561 06:53:37.397013 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9562 06:53:37.400309 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9563 06:53:37.407221 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9564 06:53:37.410418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9565 06:53:37.413617 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9566 06:53:37.420464 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9567 06:53:37.423683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9568 06:53:37.430795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9569 06:53:37.433614 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9570 06:53:37.440657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9571 06:53:37.443452 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9572 06:53:37.446769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9573 06:53:37.453689 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9574 06:53:37.457276 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9575 06:53:37.463385 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9576 06:53:37.466800 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9577 06:53:37.473688 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9578 06:53:37.477026 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9579 06:53:37.480099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9580 06:53:37.486943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9581 06:53:37.490544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9582 06:53:37.497346 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9583 06:53:37.500221 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9584 06:53:37.503517 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9585 06:53:37.506938 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9586 06:53:37.513847 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9587 06:53:37.516896 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9588 06:53:37.520579 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9589 06:53:37.526734 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9590 06:53:37.530630 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9591 06:53:37.537342 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9592 06:53:37.540507 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9593 06:53:37.544078 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9594 06:53:37.550515 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9595 06:53:37.553716 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9596 06:53:37.560610 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9597 06:53:37.563737 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9598 06:53:37.567182 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9599 06:53:37.573892 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9600 06:53:37.576867 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9601 06:53:37.584062 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9602 06:53:37.587191 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9603 06:53:37.590605 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9604 06:53:37.593816 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9605 06:53:37.600687 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9606 06:53:37.604104 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9607 06:53:37.607357 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9608 06:53:37.610963 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9609 06:53:37.617331 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9610 06:53:37.621003 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9611 06:53:37.623916 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9612 06:53:37.630739 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9613 06:53:37.634465 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9614 06:53:37.637834 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9615 06:53:37.644154 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9616 06:53:37.647749 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9617 06:53:37.654165 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9618 06:53:37.657704 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9619 06:53:37.660676 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9620 06:53:37.667360 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9621 06:53:37.670792 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9622 06:53:37.677291 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9623 06:53:37.680779 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9624 06:53:37.684140 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9625 06:53:37.690977 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9626 06:53:37.694399 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9627 06:53:37.697661 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9628 06:53:37.704538 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9629 06:53:37.707633 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9630 06:53:37.714463 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9631 06:53:37.717836 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9632 06:53:37.721339 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9633 06:53:37.727706 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9634 06:53:37.730950 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9635 06:53:37.734480 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9636 06:53:37.741332 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9637 06:53:37.744395 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9638 06:53:37.751176 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9639 06:53:37.754531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9640 06:53:37.757865 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9641 06:53:37.764531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9642 06:53:37.768217 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9643 06:53:37.774289 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9644 06:53:37.777653 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9645 06:53:37.780907 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9646 06:53:37.787903 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9647 06:53:37.790965 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9648 06:53:37.794502 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9649 06:53:37.800797 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9650 06:53:37.804042 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9651 06:53:37.810877 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9652 06:53:37.813992 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9653 06:53:37.817372 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9654 06:53:37.824033 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9655 06:53:37.827154 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9656 06:53:37.833784 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9657 06:53:37.837645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9658 06:53:37.840445 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9659 06:53:37.847283 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9660 06:53:37.850251 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9661 06:53:37.857055 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9662 06:53:37.860253 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9663 06:53:37.863567 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9664 06:53:37.870375 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9665 06:53:37.873459 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9666 06:53:37.876577 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9667 06:53:37.883418 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9668 06:53:37.886550 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9669 06:53:37.893179 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9670 06:53:37.896743 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9671 06:53:37.900159 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9672 06:53:37.906831 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9673 06:53:37.910219 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9674 06:53:37.916487 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9675 06:53:37.919712 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9676 06:53:37.923429 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9677 06:53:37.929914 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9678 06:53:37.933571 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9679 06:53:37.940243 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9680 06:53:37.943621 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9681 06:53:37.950111 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9682 06:53:37.953490 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9683 06:53:37.956830 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9684 06:53:37.963731 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9685 06:53:37.966817 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9686 06:53:37.973573 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9687 06:53:37.976503 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9688 06:53:37.980346 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9689 06:53:37.987070 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9690 06:53:37.990222 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9691 06:53:37.997228 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9692 06:53:38.000086 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9693 06:53:38.007208 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9694 06:53:38.010444 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9695 06:53:38.013433 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9696 06:53:38.020495 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9697 06:53:38.023809 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9698 06:53:38.030623 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9699 06:53:38.033773 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9700 06:53:38.037312 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9701 06:53:38.043637 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9702 06:53:38.047315 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9703 06:53:38.053972 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9704 06:53:38.056899 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9705 06:53:38.060612 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9706 06:53:38.066830 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9707 06:53:38.070087 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9708 06:53:38.076946 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9709 06:53:38.080146 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9710 06:53:38.086543 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9711 06:53:38.090098 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9712 06:53:38.093675 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9713 06:53:38.100043 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9714 06:53:38.103236 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9715 06:53:38.109970 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9716 06:53:38.113109 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9717 06:53:38.116477 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9718 06:53:38.120157 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9719 06:53:38.123326 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9720 06:53:38.130082 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9721 06:53:38.133484 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9722 06:53:38.139563 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9723 06:53:38.143300 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9724 06:53:38.146814 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9725 06:53:38.153328 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9726 06:53:38.156593 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9727 06:53:38.160155 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9728 06:53:38.166543 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9729 06:53:38.169552 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9730 06:53:38.173059 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9731 06:53:38.179614 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9732 06:53:38.183364 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9733 06:53:38.189451 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9734 06:53:38.192779 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9735 06:53:38.196188 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9736 06:53:38.202452 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9737 06:53:38.206046 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9738 06:53:38.209373 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9739 06:53:38.216347 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9740 06:53:38.219328 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9741 06:53:38.222596 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9742 06:53:38.228974 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9743 06:53:38.232571 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9744 06:53:38.239422 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9745 06:53:38.242793 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9746 06:53:38.246063 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9747 06:53:38.252392 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9748 06:53:38.255842 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9749 06:53:38.259339 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9750 06:53:38.266069 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9751 06:53:38.269436 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9752 06:53:38.272768 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9753 06:53:38.279163 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9754 06:53:38.282678 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9755 06:53:38.285848 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9756 06:53:38.292724 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9757 06:53:38.295770 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9758 06:53:38.298968 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9759 06:53:38.302032 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9760 06:53:38.305657 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9761 06:53:38.311885 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9762 06:53:38.315527 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9763 06:53:38.319040 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9764 06:53:38.325703 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9765 06:53:38.328701 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9766 06:53:38.332496 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9767 06:53:38.335428 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9768 06:53:38.342094 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9769 06:53:38.345190 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9770 06:53:38.351919 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9771 06:53:38.354998 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9772 06:53:38.358435 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9773 06:53:38.364862 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9774 06:53:38.368470 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9775 06:53:38.375056 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9776 06:53:38.378804 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9777 06:53:38.381561 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9778 06:53:38.388288 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9779 06:53:38.391436 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9780 06:53:38.398366 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9781 06:53:38.401573 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9782 06:53:38.408874 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9783 06:53:38.411796 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9784 06:53:38.415187 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9785 06:53:38.421573 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9786 06:53:38.425341 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9787 06:53:38.431541 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9788 06:53:38.434678 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9789 06:53:38.438344 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9790 06:53:38.445123 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9791 06:53:38.448493 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9792 06:53:38.455032 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9793 06:53:38.458452 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9794 06:53:38.462377 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9795 06:53:38.468486 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9796 06:53:38.471673 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9797 06:53:38.477890 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9798 06:53:38.481474 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9799 06:53:38.488282 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9800 06:53:38.491292 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9801 06:53:38.494610 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9802 06:53:38.500988 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9803 06:53:38.504674 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9804 06:53:38.511109 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9805 06:53:38.514390 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9806 06:53:38.517624 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9807 06:53:38.524176 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9808 06:53:38.527871 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9809 06:53:38.534384 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9810 06:53:38.537677 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9811 06:53:38.540992 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9812 06:53:38.547407 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9813 06:53:38.551025 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9814 06:53:38.558023 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9815 06:53:38.561247 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9816 06:53:38.564476 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9817 06:53:38.571370 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9818 06:53:38.574340 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9819 06:53:38.581220 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9820 06:53:38.584299 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9821 06:53:38.590809 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9822 06:53:38.594068 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9823 06:53:38.597717 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9824 06:53:38.604201 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9825 06:53:38.607985 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9826 06:53:38.614081 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9827 06:53:38.617752 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9828 06:53:38.620491 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9829 06:53:38.627481 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9830 06:53:38.630537 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9831 06:53:38.637533 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9832 06:53:38.640350 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9833 06:53:38.643879 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9834 06:53:38.650349 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9835 06:53:38.653983 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9836 06:53:38.660494 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9837 06:53:38.663830 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9838 06:53:38.670414 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9839 06:53:38.673505 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9840 06:53:38.677443 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9841 06:53:38.683783 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9842 06:53:38.687374 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9843 06:53:38.694088 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9844 06:53:38.697191 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9845 06:53:38.703676 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9846 06:53:38.706839 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9847 06:53:38.710641 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9848 06:53:38.716928 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9849 06:53:38.719800 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9850 06:53:38.726657 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9851 06:53:38.729691 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9852 06:53:38.736647 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9853 06:53:38.739309 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9854 06:53:38.746133 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9855 06:53:38.749473 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9856 06:53:38.752992 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9857 06:53:38.759580 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9858 06:53:38.762817 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9859 06:53:38.769654 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9860 06:53:38.772837 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9861 06:53:38.776467 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9862 06:53:38.782865 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9863 06:53:38.786522 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9864 06:53:38.793148 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9865 06:53:38.796416 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9866 06:53:38.803319 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9867 06:53:38.806515 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9868 06:53:38.813414 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9869 06:53:38.816574 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9870 06:53:38.819793 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9871 06:53:38.826385 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9872 06:53:38.829285 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9873 06:53:38.836009 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9874 06:53:38.839294 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9875 06:53:38.845929 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9876 06:53:38.849291 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9877 06:53:38.856123 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9878 06:53:38.859345 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9879 06:53:38.862617 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9880 06:53:38.869118 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9881 06:53:38.872289 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9882 06:53:38.879043 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9883 06:53:38.882502 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9884 06:53:38.888962 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9885 06:53:38.892573 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9886 06:53:38.895875 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9887 06:53:38.902567 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9888 06:53:38.905838 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9889 06:53:38.912307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9890 06:53:38.915597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9891 06:53:38.919122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9892 06:53:38.925683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9893 06:53:38.928983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9894 06:53:38.935638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9895 06:53:38.938738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9896 06:53:38.945728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9897 06:53:38.949435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9898 06:53:38.955619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9899 06:53:38.959022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9900 06:53:38.965847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9901 06:53:38.969181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9902 06:53:38.975570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9903 06:53:38.979002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9904 06:53:38.985600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9905 06:53:38.989348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9906 06:53:38.995941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9907 06:53:38.999155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9908 06:53:39.002406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9909 06:53:39.009099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9910 06:53:39.012392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9911 06:53:39.018889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9912 06:53:39.025779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9913 06:53:39.029019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9914 06:53:39.035870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9915 06:53:39.038760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9916 06:53:39.045510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9917 06:53:39.048643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9918 06:53:39.055602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9919 06:53:39.058757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9920 06:53:39.065205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9921 06:53:39.068857 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9922 06:53:39.069409 INFO: [APUAPC] vio 0
9923 06:53:39.075923 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9924 06:53:39.079267 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9925 06:53:39.082593 INFO: [APUAPC] D0_APC_0: 0x400510
9926 06:53:39.086245 INFO: [APUAPC] D0_APC_1: 0x0
9927 06:53:39.089296 INFO: [APUAPC] D0_APC_2: 0x1540
9928 06:53:39.092487 INFO: [APUAPC] D0_APC_3: 0x0
9929 06:53:39.096097 INFO: [APUAPC] D1_APC_0: 0xffffffff
9930 06:53:39.099316 INFO: [APUAPC] D1_APC_1: 0xffffffff
9931 06:53:39.102513 INFO: [APUAPC] D1_APC_2: 0x3fffff
9932 06:53:39.105873 INFO: [APUAPC] D1_APC_3: 0x0
9933 06:53:39.109566 INFO: [APUAPC] D2_APC_0: 0xffffffff
9934 06:53:39.112763 INFO: [APUAPC] D2_APC_1: 0xffffffff
9935 06:53:39.115718 INFO: [APUAPC] D2_APC_2: 0x3fffff
9936 06:53:39.119077 INFO: [APUAPC] D2_APC_3: 0x0
9937 06:53:39.122838 INFO: [APUAPC] D3_APC_0: 0xffffffff
9938 06:53:39.125675 INFO: [APUAPC] D3_APC_1: 0xffffffff
9939 06:53:39.129098 INFO: [APUAPC] D3_APC_2: 0x3fffff
9940 06:53:39.132256 INFO: [APUAPC] D3_APC_3: 0x0
9941 06:53:39.135876 INFO: [APUAPC] D4_APC_0: 0xffffffff
9942 06:53:39.138742 INFO: [APUAPC] D4_APC_1: 0xffffffff
9943 06:53:39.142670 INFO: [APUAPC] D4_APC_2: 0x3fffff
9944 06:53:39.145801 INFO: [APUAPC] D4_APC_3: 0x0
9945 06:53:39.148948 INFO: [APUAPC] D5_APC_0: 0xffffffff
9946 06:53:39.152448 INFO: [APUAPC] D5_APC_1: 0xffffffff
9947 06:53:39.156182 INFO: [APUAPC] D5_APC_2: 0x3fffff
9948 06:53:39.156778 INFO: [APUAPC] D5_APC_3: 0x0
9949 06:53:39.158768 INFO: [APUAPC] D6_APC_0: 0xffffffff
9950 06:53:39.162233 INFO: [APUAPC] D6_APC_1: 0xffffffff
9951 06:53:39.165740 INFO: [APUAPC] D6_APC_2: 0x3fffff
9952 06:53:39.169200 INFO: [APUAPC] D6_APC_3: 0x0
9953 06:53:39.172228 INFO: [APUAPC] D7_APC_0: 0xffffffff
9954 06:53:39.175703 INFO: [APUAPC] D7_APC_1: 0xffffffff
9955 06:53:39.178857 INFO: [APUAPC] D7_APC_2: 0x3fffff
9956 06:53:39.182431 INFO: [APUAPC] D7_APC_3: 0x0
9957 06:53:39.185389 INFO: [APUAPC] D8_APC_0: 0xffffffff
9958 06:53:39.188874 INFO: [APUAPC] D8_APC_1: 0xffffffff
9959 06:53:39.191977 INFO: [APUAPC] D8_APC_2: 0x3fffff
9960 06:53:39.195522 INFO: [APUAPC] D8_APC_3: 0x0
9961 06:53:39.198750 INFO: [APUAPC] D9_APC_0: 0xffffffff
9962 06:53:39.202007 INFO: [APUAPC] D9_APC_1: 0xffffffff
9963 06:53:39.205507 INFO: [APUAPC] D9_APC_2: 0x3fffff
9964 06:53:39.208958 INFO: [APUAPC] D9_APC_3: 0x0
9965 06:53:39.212103 INFO: [APUAPC] D10_APC_0: 0xffffffff
9966 06:53:39.215778 INFO: [APUAPC] D10_APC_1: 0xffffffff
9967 06:53:39.218764 INFO: [APUAPC] D10_APC_2: 0x3fffff
9968 06:53:39.222323 INFO: [APUAPC] D10_APC_3: 0x0
9969 06:53:39.225247 INFO: [APUAPC] D11_APC_0: 0xffffffff
9970 06:53:39.228633 INFO: [APUAPC] D11_APC_1: 0xffffffff
9971 06:53:39.231905 INFO: [APUAPC] D11_APC_2: 0x3fffff
9972 06:53:39.235566 INFO: [APUAPC] D11_APC_3: 0x0
9973 06:53:39.238617 INFO: [APUAPC] D12_APC_0: 0xffffffff
9974 06:53:39.241636 INFO: [APUAPC] D12_APC_1: 0xffffffff
9975 06:53:39.245502 INFO: [APUAPC] D12_APC_2: 0x3fffff
9976 06:53:39.248515 INFO: [APUAPC] D12_APC_3: 0x0
9977 06:53:39.251494 INFO: [APUAPC] D13_APC_0: 0xffffffff
9978 06:53:39.255333 INFO: [APUAPC] D13_APC_1: 0xffffffff
9979 06:53:39.258561 INFO: [APUAPC] D13_APC_2: 0x3fffff
9980 06:53:39.261768 INFO: [APUAPC] D13_APC_3: 0x0
9981 06:53:39.265028 INFO: [APUAPC] D14_APC_0: 0xffffffff
9982 06:53:39.268586 INFO: [APUAPC] D14_APC_1: 0xffffffff
9983 06:53:39.271834 INFO: [APUAPC] D14_APC_2: 0x3fffff
9984 06:53:39.274989 INFO: [APUAPC] D14_APC_3: 0x0
9985 06:53:39.278249 INFO: [APUAPC] D15_APC_0: 0xffffffff
9986 06:53:39.282287 INFO: [APUAPC] D15_APC_1: 0xffffffff
9987 06:53:39.285271 INFO: [APUAPC] D15_APC_2: 0x3fffff
9988 06:53:39.288757 INFO: [APUAPC] D15_APC_3: 0x0
9989 06:53:39.291521 INFO: [APUAPC] APC_CON: 0x4
9990 06:53:39.295148 INFO: [NOCDAPC] D0_APC_0: 0x0
9991 06:53:39.298448 INFO: [NOCDAPC] D0_APC_1: 0x0
9992 06:53:39.301771 INFO: [NOCDAPC] D1_APC_0: 0x0
9993 06:53:39.305083 INFO: [NOCDAPC] D1_APC_1: 0xfff
9994 06:53:39.308280 INFO: [NOCDAPC] D2_APC_0: 0x0
9995 06:53:39.308775 INFO: [NOCDAPC] D2_APC_1: 0xfff
9996 06:53:39.311576 INFO: [NOCDAPC] D3_APC_0: 0x0
9997 06:53:39.314534 INFO: [NOCDAPC] D3_APC_1: 0xfff
9998 06:53:39.318144 INFO: [NOCDAPC] D4_APC_0: 0x0
9999 06:53:39.321465 INFO: [NOCDAPC] D4_APC_1: 0xfff
10000 06:53:39.324747 INFO: [NOCDAPC] D5_APC_0: 0x0
10001 06:53:39.327982 INFO: [NOCDAPC] D5_APC_1: 0xfff
10002 06:53:39.331231 INFO: [NOCDAPC] D6_APC_0: 0x0
10003 06:53:39.335281 INFO: [NOCDAPC] D6_APC_1: 0xfff
10004 06:53:39.338353 INFO: [NOCDAPC] D7_APC_0: 0x0
10005 06:53:39.341907 INFO: [NOCDAPC] D7_APC_1: 0xfff
10006 06:53:39.342524 INFO: [NOCDAPC] D8_APC_0: 0x0
10007 06:53:39.344892 INFO: [NOCDAPC] D8_APC_1: 0xfff
10008 06:53:39.348715 INFO: [NOCDAPC] D9_APC_0: 0x0
10009 06:53:39.352009 INFO: [NOCDAPC] D9_APC_1: 0xfff
10010 06:53:39.354615 INFO: [NOCDAPC] D10_APC_0: 0x0
10011 06:53:39.358407 INFO: [NOCDAPC] D10_APC_1: 0xfff
10012 06:53:39.361848 INFO: [NOCDAPC] D11_APC_0: 0x0
10013 06:53:39.365158 INFO: [NOCDAPC] D11_APC_1: 0xfff
10014 06:53:39.368169 INFO: [NOCDAPC] D12_APC_0: 0x0
10015 06:53:39.371498 INFO: [NOCDAPC] D12_APC_1: 0xfff
10016 06:53:39.375098 INFO: [NOCDAPC] D13_APC_0: 0x0
10017 06:53:39.378646 INFO: [NOCDAPC] D13_APC_1: 0xfff
10018 06:53:39.379116 INFO: [NOCDAPC] D14_APC_0: 0x0
10019 06:53:39.381649 INFO: [NOCDAPC] D14_APC_1: 0xfff
10020 06:53:39.384871 INFO: [NOCDAPC] D15_APC_0: 0x0
10021 06:53:39.387844 INFO: [NOCDAPC] D15_APC_1: 0xfff
10022 06:53:39.391372 INFO: [NOCDAPC] APC_CON: 0x4
10023 06:53:39.394810 INFO: [APUAPC] set_apusys_apc done
10024 06:53:39.398008 INFO: [DEVAPC] devapc_init done
10025 06:53:39.401070 INFO: GICv3 without legacy support detected.
10026 06:53:39.408190 INFO: ARM GICv3 driver initialized in EL3
10027 06:53:39.411549 INFO: Maximum SPI INTID supported: 639
10028 06:53:39.414699 INFO: BL31: Initializing runtime services
10029 06:53:39.421866 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10030 06:53:39.424539 INFO: SPM: enable CPC mode
10031 06:53:39.428277 INFO: mcdi ready for mcusys-off-idle and system suspend
10032 06:53:39.434545 INFO: BL31: Preparing for EL3 exit to normal world
10033 06:53:39.437629 INFO: Entry point address = 0x80000000
10034 06:53:39.438242 INFO: SPSR = 0x8
10035 06:53:39.444172
10036 06:53:39.444727
10037 06:53:39.445103
10038 06:53:39.447876 Starting depthcharge on Spherion...
10039 06:53:39.448440
10040 06:53:39.448814 Wipe memory regions:
10041 06:53:39.449168
10042 06:53:39.451531 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10043 06:53:39.452081 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10044 06:53:39.452531 Setting prompt string to ['asurada:']
10045 06:53:39.453076 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10046 06:53:39.453814 [0x00000040000000, 0x00000054600000)
10047 06:53:39.573321
10048 06:53:39.573883 [0x00000054660000, 0x00000080000000)
10049 06:53:39.833988
10050 06:53:39.834630 [0x000000821a7280, 0x000000ffe64000)
10051 06:53:40.578688
10052 06:53:40.579247 [0x00000100000000, 0x00000240000000)
10053 06:53:42.469421
10054 06:53:42.472396 Initializing XHCI USB controller at 0x11200000.
10055 06:53:43.510588
10056 06:53:43.514096 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10057 06:53:43.514657
10058 06:53:43.515029
10059 06:53:43.515377
10060 06:53:43.516154 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 06:53:43.617407 asurada: tftpboot 192.168.201.1 12694845/tftp-deploy-6d7lb4s1/kernel/image.itb 12694845/tftp-deploy-6d7lb4s1/kernel/cmdline
10063 06:53:43.618092 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10064 06:53:43.618572 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10065 06:53:43.623013 tftpboot 192.168.201.1 12694845/tftp-deploy-6d7lb4s1/kernel/image.ittp-deploy-6d7lb4s1/kernel/cmdline
10066 06:53:43.623495
10067 06:53:43.623864 Waiting for link
10068 06:53:43.783390
10069 06:53:43.783949 R8152: Initializing
10070 06:53:43.784326
10071 06:53:43.786811 Version 9 (ocp_data = 6010)
10072 06:53:43.787284
10073 06:53:43.790052 R8152: Done initializing
10074 06:53:43.790519
10075 06:53:43.790892 Adding net device
10076 06:53:45.669277
10077 06:53:45.669835 done.
10078 06:53:45.670251
10079 06:53:45.670599 MAC: 00:e0:4c:72:2d:d6
10080 06:53:45.670937
10081 06:53:45.672503 Sending DHCP discover... done.
10082 06:53:45.672976
10083 06:53:52.651770 Waiting for reply... done.
10084 06:53:52.652443
10085 06:53:52.652854 Sending DHCP request... done.
10086 06:53:52.654871
10087 06:53:52.655329 Waiting for reply... done.
10088 06:53:52.655698
10089 06:53:52.658306 My ip is 192.168.201.21
10090 06:53:52.658765
10091 06:53:52.661222 The DHCP server ip is 192.168.201.1
10092 06:53:52.661685
10093 06:53:52.664814 TFTP server IP predefined by user: 192.168.201.1
10094 06:53:52.665278
10095 06:53:52.671246 Bootfile predefined by user: 12694845/tftp-deploy-6d7lb4s1/kernel/image.itb
10096 06:53:52.671813
10097 06:53:52.674595 Sending tftp read request... done.
10098 06:53:52.675078
10099 06:53:52.681263 Waiting for the transfer...
10100 06:53:52.681727
10101 06:53:52.971834 00000000 ################################################################
10102 06:53:52.971973
10103 06:53:53.233067 00080000 ################################################################
10104 06:53:53.233190
10105 06:53:53.524237 00100000 ################################################################
10106 06:53:53.524381
10107 06:53:53.808597 00180000 ################################################################
10108 06:53:53.808767
10109 06:53:54.068672 00200000 ################################################################
10110 06:53:54.068799
10111 06:53:54.347488 00280000 ################################################################
10112 06:53:54.347621
10113 06:53:54.616385 00300000 ################################################################
10114 06:53:54.616551
10115 06:53:54.873078 00380000 ################################################################
10116 06:53:54.873243
10117 06:53:55.156134 00400000 ################################################################
10118 06:53:55.156264
10119 06:53:55.410632 00480000 ################################################################
10120 06:53:55.410759
10121 06:53:55.682983 00500000 ################################################################
10122 06:53:55.683112
10123 06:53:55.931901 00580000 ################################################################
10124 06:53:55.932046
10125 06:53:56.187413 00600000 ################################################################
10126 06:53:56.187539
10127 06:53:56.440791 00680000 ################################################################
10128 06:53:56.440930
10129 06:53:56.691305 00700000 ################################################################
10130 06:53:56.691438
10131 06:53:56.943713 00780000 ################################################################
10132 06:53:56.943846
10133 06:53:57.197812 00800000 ################################################################
10134 06:53:57.197975
10135 06:53:57.447175 00880000 ################################################################
10136 06:53:57.447328
10137 06:53:57.695890 00900000 ################################################################
10138 06:53:57.696051
10139 06:53:57.945368 00980000 ################################################################
10140 06:53:57.945530
10141 06:53:58.198119 00a00000 ################################################################
10142 06:53:58.198268
10143 06:53:58.452136 00a80000 ################################################################
10144 06:53:58.452289
10145 06:53:58.703560 00b00000 ################################################################
10146 06:53:58.703687
10147 06:53:58.953918 00b80000 ################################################################
10148 06:53:58.954067
10149 06:53:59.222630 00c00000 ################################################################
10150 06:53:59.222785
10151 06:53:59.480811 00c80000 ################################################################
10152 06:53:59.480937
10153 06:53:59.742481 00d00000 ################################################################
10154 06:53:59.742648
10155 06:54:00.017601 00d80000 ################################################################
10156 06:54:00.017795
10157 06:54:00.281714 00e00000 ################################################################
10158 06:54:00.281869
10159 06:54:00.564850 00e80000 ################################################################
10160 06:54:00.565005
10161 06:54:00.833351 00f00000 ################################################################
10162 06:54:00.833512
10163 06:54:01.082378 00f80000 ################################################################
10164 06:54:01.082507
10165 06:54:01.330398 01000000 ################################################################
10166 06:54:01.330581
10167 06:54:01.578621 01080000 ################################################################
10168 06:54:01.578777
10169 06:54:01.827244 01100000 ################################################################
10170 06:54:01.827401
10171 06:54:02.074398 01180000 ################################################################
10172 06:54:02.074548
10173 06:54:02.322247 01200000 ################################################################
10174 06:54:02.322374
10175 06:54:02.572310 01280000 ################################################################
10176 06:54:02.572434
10177 06:54:02.839557 01300000 ################################################################
10178 06:54:02.839682
10179 06:54:03.094631 01380000 ################################################################
10180 06:54:03.094755
10181 06:54:03.347526 01400000 ################################################################
10182 06:54:03.347654
10183 06:54:03.597025 01480000 ################################################################
10184 06:54:03.597151
10185 06:54:03.846589 01500000 ################################################################
10186 06:54:03.846753
10187 06:54:04.119099 01580000 ################################################################
10188 06:54:04.119239
10189 06:54:04.375719 01600000 ################################################################
10190 06:54:04.375845
10191 06:54:04.642117 01680000 ################################################################
10192 06:54:04.642248
10193 06:54:04.906952 01700000 ################################################################
10194 06:54:04.907074
10195 06:54:05.156090 01780000 ################################################################
10196 06:54:05.156233
10197 06:54:05.411469 01800000 ################################################################
10198 06:54:05.411600
10199 06:54:05.676631 01880000 ################################################################
10200 06:54:05.676779
10201 06:54:05.929956 01900000 ################################################################
10202 06:54:05.930091
10203 06:54:06.196198 01980000 ################################################################
10204 06:54:06.196333
10205 06:54:06.452058 01a00000 ################################################################
10206 06:54:06.452188
10207 06:54:06.701498 01a80000 ################################################################
10208 06:54:06.701646
10209 06:54:06.950928 01b00000 ################################################################
10210 06:54:06.951105
10211 06:54:07.212898 01b80000 ################################################################
10212 06:54:07.213027
10213 06:54:07.474163 01c00000 ################################################################
10214 06:54:07.474287
10215 06:54:07.732184 01c80000 ################################################################
10216 06:54:07.732311
10217 06:54:07.999477 01d00000 ################################################################
10218 06:54:07.999600
10219 06:54:08.266662 01d80000 ################################################################
10220 06:54:08.266790
10221 06:54:08.516460 01e00000 ################################################################
10222 06:54:08.516587
10223 06:54:08.767555 01e80000 ################################################################
10224 06:54:08.767707
10225 06:54:09.016181 01f00000 ################################################################
10226 06:54:09.016340
10227 06:54:09.271929 01f80000 ################################################################
10228 06:54:09.272092
10229 06:54:09.521538 02000000 ################################################################
10230 06:54:09.521689
10231 06:54:09.770562 02080000 ################################################################
10232 06:54:09.770692
10233 06:54:10.037681 02100000 ################################################################
10234 06:54:10.037813
10235 06:54:10.302916 02180000 ################################################################
10236 06:54:10.303050
10237 06:54:10.564819 02200000 ################################################################
10238 06:54:10.564974
10239 06:54:10.828741 02280000 ################################################################
10240 06:54:10.828865
10241 06:54:11.091689 02300000 ################################################################
10242 06:54:11.091812
10243 06:54:11.341445 02380000 ################################################################
10244 06:54:11.341601
10245 06:54:11.599184 02400000 ################################################################
10246 06:54:11.599313
10247 06:54:11.865715 02480000 ################################################################
10248 06:54:11.865917
10249 06:54:12.124498 02500000 ################################################################
10250 06:54:12.124651
10251 06:54:12.373933 02580000 ################################################################
10252 06:54:12.374094
10253 06:54:12.623530 02600000 ################################################################
10254 06:54:12.623659
10255 06:54:12.877635 02680000 ################################################################
10256 06:54:12.877761
10257 06:54:13.140041 02700000 ################################################################
10258 06:54:13.140195
10259 06:54:13.405571 02780000 ################################################################
10260 06:54:13.405701
10261 06:54:13.658399 02800000 ################################################################
10262 06:54:13.658528
10263 06:54:13.913279 02880000 ################################################################
10264 06:54:13.913434
10265 06:54:14.163787 02900000 ################################################################
10266 06:54:14.163942
10267 06:54:14.415068 02980000 ################################################################
10268 06:54:14.415209
10269 06:54:14.664667 02a00000 ################################################################
10270 06:54:14.664826
10271 06:54:14.917044 02a80000 ################################################################
10272 06:54:14.917196
10273 06:54:15.173597 02b00000 ################################################################
10274 06:54:15.173731
10275 06:54:15.432793 02b80000 ################################################################
10276 06:54:15.432930
10277 06:54:15.682177 02c00000 ################################################################
10278 06:54:15.682310
10279 06:54:15.931541 02c80000 ################################################################
10280 06:54:15.931670
10281 06:54:16.181688 02d00000 ################################################################
10282 06:54:16.181838
10283 06:54:16.435390 02d80000 ################################################################
10284 06:54:16.435515
10285 06:54:16.704776 02e00000 ################################################################
10286 06:54:16.704937
10287 06:54:16.956971 02e80000 ################################################################
10288 06:54:16.957099
10289 06:54:17.215717 02f00000 ################################################################
10290 06:54:17.215855
10291 06:54:17.477090 02f80000 ################################################################
10292 06:54:17.477219
10293 06:54:17.725770 03000000 ################################################################
10294 06:54:17.725927
10295 06:54:17.976755 03080000 ################################################################
10296 06:54:17.976878
10297 06:54:18.020110 03100000 ############ done.
10298 06:54:18.020202
10299 06:54:18.023648 The bootfile was 51475518 bytes long.
10300 06:54:18.023732
10301 06:54:18.026901 Sending tftp read request... done.
10302 06:54:18.026992
10303 06:54:18.030616 Waiting for the transfer...
10304 06:54:18.030713
10305 06:54:18.033804 00000000 # done.
10306 06:54:18.033902
10307 06:54:18.040550 Command line loaded dynamically from TFTP file: 12694845/tftp-deploy-6d7lb4s1/kernel/cmdline
10308 06:54:18.040664
10309 06:54:18.053661 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10310 06:54:18.053802
10311 06:54:18.053911 Loading FIT.
10312 06:54:18.057066
10313 06:54:18.057219 Image ramdisk-1 has 39375623 bytes.
10314 06:54:18.057342
10315 06:54:18.060377 Image fdt-1 has 47278 bytes.
10316 06:54:18.060554
10317 06:54:18.063835 Image kernel-1 has 12050581 bytes.
10318 06:54:18.064098
10319 06:54:18.073503 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10320 06:54:18.073828
10321 06:54:18.090524 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10322 06:54:18.091047
10323 06:54:18.097337 Choosing best match conf-1 for compat google,spherion-rev2.
10324 06:54:18.097798
10325 06:54:18.105010 Connected to device vid:did:rid of 1ae0:0028:00
10326 06:54:18.113060
10327 06:54:18.116709 tpm_get_response: command 0x17b, return code 0x0
10328 06:54:18.117178
10329 06:54:18.119862 ec_init: CrosEC protocol v3 supported (256, 248)
10330 06:54:18.124086
10331 06:54:18.124546 tpm_cleanup: add release locality here.
10332 06:54:18.126956
10333 06:54:18.127412 Shutting down all USB controllers.
10334 06:54:18.127777
10335 06:54:18.130265 Removing current net device
10336 06:54:18.130727
10337 06:54:18.137074 Exiting depthcharge with code 4 at timestamp: 68031560
10338 06:54:18.137536
10339 06:54:18.140743 LZMA decompressing kernel-1 to 0x821a6718
10340 06:54:18.141207
10341 06:54:18.143663 LZMA decompressing kernel-1 to 0x40000000
10342 06:54:19.641886
10343 06:54:19.642054 jumping to kernel
10344 06:54:19.642556 end: 2.2.4 bootloader-commands (duration 00:00:40) [common]
10345 06:54:19.642656 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10346 06:54:19.642734 Setting prompt string to ['Linux version [0-9]']
10347 06:54:19.642803 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10348 06:54:19.642876 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10349 06:54:19.723871
10350 06:54:19.727472 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10351 06:54:19.730588 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10352 06:54:19.730678 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10353 06:54:19.730748 Setting prompt string to []
10354 06:54:19.730825 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10355 06:54:19.730899 Using line separator: #'\n'#
10356 06:54:19.730958 No login prompt set.
10357 06:54:19.731019 Parsing kernel messages
10358 06:54:19.731074 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10359 06:54:19.731177 [login-action] Waiting for messages, (timeout 00:03:45)
10360 06:54:19.750600 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10361 06:54:19.753913 [ 0.000000] random: crng init done
10362 06:54:19.760488 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10363 06:54:19.763726 [ 0.000000] efi: UEFI not found.
10364 06:54:19.770214 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10365 06:54:19.776791 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10366 06:54:19.786622 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10367 06:54:19.796528 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10368 06:54:19.803384 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10369 06:54:19.810004 [ 0.000000] printk: bootconsole [mtk8250] enabled
10370 06:54:19.816516 [ 0.000000] NUMA: No NUMA configuration found
10371 06:54:19.822974 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10372 06:54:19.826678 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10373 06:54:19.829848 [ 0.000000] Zone ranges:
10374 06:54:19.836246 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10375 06:54:19.839617 [ 0.000000] DMA32 empty
10376 06:54:19.846376 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10377 06:54:19.849650 [ 0.000000] Movable zone start for each node
10378 06:54:19.852780 [ 0.000000] Early memory node ranges
10379 06:54:19.859641 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10380 06:54:19.866317 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10381 06:54:19.872641 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10382 06:54:19.879485 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10383 06:54:19.882847 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10384 06:54:19.892520 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10385 06:54:19.948589 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10386 06:54:19.955025 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10387 06:54:19.961777 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10388 06:54:19.965197 [ 0.000000] psci: probing for conduit method from DT.
10389 06:54:19.971739 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10390 06:54:19.974866 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10391 06:54:19.981658 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10392 06:54:19.984958 [ 0.000000] psci: SMC Calling Convention v1.2
10393 06:54:19.991384 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10394 06:54:19.994589 [ 0.000000] Detected VIPT I-cache on CPU0
10395 06:54:20.001328 [ 0.000000] CPU features: detected: GIC system register CPU interface
10396 06:54:20.007894 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10397 06:54:20.014553 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10398 06:54:20.021410 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10399 06:54:20.027688 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10400 06:54:20.034867 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10401 06:54:20.041462 [ 0.000000] alternatives: applying boot alternatives
10402 06:54:20.044505 [ 0.000000] Fallback order for Node 0: 0
10403 06:54:20.054520 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10404 06:54:20.054631 [ 0.000000] Policy zone: Normal
10405 06:54:20.071164 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10406 06:54:20.081030 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10407 06:54:20.092582 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10408 06:54:20.102415 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10409 06:54:20.109346 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10410 06:54:20.112636 <6>[ 0.000000] software IO TLB: area num 8.
10411 06:54:20.169157 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10412 06:54:20.318457 <6>[ 0.000000] Memory: 7928804K/8385536K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 423964K reserved, 32768K cma-reserved)
10413 06:54:20.325359 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10414 06:54:20.332088 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10415 06:54:20.334970 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10416 06:54:20.342121 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10417 06:54:20.348379 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10418 06:54:20.351437 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10419 06:54:20.361625 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10420 06:54:20.368201 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10421 06:54:20.374542 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10422 06:54:20.381437 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10423 06:54:20.385417 <6>[ 0.000000] GICv3: 608 SPIs implemented
10424 06:54:20.388681 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10425 06:54:20.394590 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10426 06:54:20.397648 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10427 06:54:20.404560 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10428 06:54:20.417702 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10429 06:54:20.427709 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10430 06:54:20.437444 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10431 06:54:20.444537 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10432 06:54:20.457931 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10433 06:54:20.464864 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10434 06:54:20.471842 <6>[ 0.009184] Console: colour dummy device 80x25
10435 06:54:20.481378 <6>[ 0.013939] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10436 06:54:20.484784 <6>[ 0.024381] pid_max: default: 32768 minimum: 301
10437 06:54:20.491329 <6>[ 0.029251] LSM: Security Framework initializing
10438 06:54:20.498360 <6>[ 0.034191] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10439 06:54:20.508555 <6>[ 0.042004] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10440 06:54:20.515219 <6>[ 0.051421] cblist_init_generic: Setting adjustable number of callback queues.
10441 06:54:20.521704 <6>[ 0.058864] cblist_init_generic: Setting shift to 3 and lim to 1.
10442 06:54:20.528281 <6>[ 0.065202] cblist_init_generic: Setting adjustable number of callback queues.
10443 06:54:20.534872 <6>[ 0.072630] cblist_init_generic: Setting shift to 3 and lim to 1.
10444 06:54:20.541600 <6>[ 0.079070] rcu: Hierarchical SRCU implementation.
10445 06:54:20.548196 <6>[ 0.084085] rcu: Max phase no-delay instances is 1000.
10446 06:54:20.551647 <6>[ 0.091146] EFI services will not be available.
10447 06:54:20.558173 <6>[ 0.096104] smp: Bringing up secondary CPUs ...
10448 06:54:20.565496 <6>[ 0.101159] Detected VIPT I-cache on CPU1
10449 06:54:20.572103 <6>[ 0.101228] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10450 06:54:20.578874 <6>[ 0.101261] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10451 06:54:20.581852 <6>[ 0.101598] Detected VIPT I-cache on CPU2
10452 06:54:20.588255 <6>[ 0.101650] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10453 06:54:20.595236 <6>[ 0.101669] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10454 06:54:20.601681 <6>[ 0.101928] Detected VIPT I-cache on CPU3
10455 06:54:20.608599 <6>[ 0.101974] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10456 06:54:20.615000 <6>[ 0.101988] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10457 06:54:20.618281 <6>[ 0.102289] CPU features: detected: Spectre-v4
10458 06:54:20.625152 <6>[ 0.102296] CPU features: detected: Spectre-BHB
10459 06:54:20.628322 <6>[ 0.102300] Detected PIPT I-cache on CPU4
10460 06:54:20.634617 <6>[ 0.102359] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10461 06:54:20.641686 <6>[ 0.102375] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10462 06:54:20.647972 <6>[ 0.102666] Detected PIPT I-cache on CPU5
10463 06:54:20.654683 <6>[ 0.102727] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10464 06:54:20.661339 <6>[ 0.102743] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10465 06:54:20.664668 <6>[ 0.103022] Detected PIPT I-cache on CPU6
10466 06:54:20.671361 <6>[ 0.103079] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10467 06:54:20.677846 <6>[ 0.103096] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10468 06:54:20.684412 <6>[ 0.103380] Detected PIPT I-cache on CPU7
10469 06:54:20.691083 <6>[ 0.103444] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10470 06:54:20.697697 <6>[ 0.103460] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10471 06:54:20.701299 <6>[ 0.103508] smp: Brought up 1 node, 8 CPUs
10472 06:54:20.707902 <6>[ 0.244827] SMP: Total of 8 processors activated.
10473 06:54:20.711081 <6>[ 0.249748] CPU features: detected: 32-bit EL0 Support
10474 06:54:20.721120 <6>[ 0.255139] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10475 06:54:20.727682 <6>[ 0.263994] CPU features: detected: Common not Private translations
10476 06:54:20.730933 <6>[ 0.270470] CPU features: detected: CRC32 instructions
10477 06:54:20.737659 <6>[ 0.275822] CPU features: detected: RCpc load-acquire (LDAPR)
10478 06:54:20.744405 <6>[ 0.281782] CPU features: detected: LSE atomic instructions
10479 06:54:20.751004 <6>[ 0.287563] CPU features: detected: Privileged Access Never
10480 06:54:20.754000 <6>[ 0.293343] CPU features: detected: RAS Extension Support
10481 06:54:20.764382 <6>[ 0.298951] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10482 06:54:20.767345 <6>[ 0.306170] CPU: All CPU(s) started at EL2
10483 06:54:20.774090 <6>[ 0.310514] alternatives: applying system-wide alternatives
10484 06:54:20.782996 <6>[ 0.321177] devtmpfs: initialized
10485 06:54:20.798548 <6>[ 0.330238] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10486 06:54:20.805179 <6>[ 0.340199] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10487 06:54:20.811926 <6>[ 0.348425] pinctrl core: initialized pinctrl subsystem
10488 06:54:20.814965 <6>[ 0.355089] DMI not present or invalid.
10489 06:54:20.821822 <6>[ 0.359506] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10490 06:54:20.831930 <6>[ 0.366394] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10491 06:54:20.838303 <6>[ 0.373979] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10492 06:54:20.847959 <6>[ 0.382207] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10493 06:54:20.851454 <6>[ 0.390448] audit: initializing netlink subsys (disabled)
10494 06:54:20.861354 <5>[ 0.396139] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10495 06:54:20.867918 <6>[ 0.396843] thermal_sys: Registered thermal governor 'step_wise'
10496 06:54:20.874531 <6>[ 0.404104] thermal_sys: Registered thermal governor 'power_allocator'
10497 06:54:20.877856 <6>[ 0.410358] cpuidle: using governor menu
10498 06:54:20.884440 <6>[ 0.421321] NET: Registered PF_QIPCRTR protocol family
10499 06:54:20.891228 <6>[ 0.426795] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10500 06:54:20.897859 <6>[ 0.433897] ASID allocator initialised with 32768 entries
10501 06:54:20.901238 <6>[ 0.440471] Serial: AMBA PL011 UART driver
10502 06:54:20.911114 <4>[ 0.449244] Trying to register duplicate clock ID: 134
10503 06:54:20.966961 <6>[ 0.508297] KASLR enabled
10504 06:54:20.981116 <6>[ 0.515950] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10505 06:54:20.988125 <6>[ 0.522963] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10506 06:54:20.994386 <6>[ 0.529451] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10507 06:54:21.001095 <6>[ 0.536455] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10508 06:54:21.007996 <6>[ 0.542943] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10509 06:54:21.014303 <6>[ 0.549947] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10510 06:54:21.021005 <6>[ 0.556434] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10511 06:54:21.027704 <6>[ 0.563437] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10512 06:54:21.030992 <6>[ 0.570906] ACPI: Interpreter disabled.
10513 06:54:21.039780 <6>[ 0.577340] iommu: Default domain type: Translated
10514 06:54:21.046239 <6>[ 0.582490] iommu: DMA domain TLB invalidation policy: strict mode
10515 06:54:21.049400 <5>[ 0.589120] SCSI subsystem initialized
10516 06:54:21.056305 <6>[ 0.593371] usbcore: registered new interface driver usbfs
10517 06:54:21.062964 <6>[ 0.599100] usbcore: registered new interface driver hub
10518 06:54:21.066189 <6>[ 0.604653] usbcore: registered new device driver usb
10519 06:54:21.072778 <6>[ 0.610778] pps_core: LinuxPPS API ver. 1 registered
10520 06:54:21.083077 <6>[ 0.615971] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10521 06:54:21.086151 <6>[ 0.625314] PTP clock support registered
10522 06:54:21.089529 <6>[ 0.629552] EDAC MC: Ver: 3.0.0
10523 06:54:21.096832 <6>[ 0.634747] FPGA manager framework
10524 06:54:21.100150 <6>[ 0.638423] Advanced Linux Sound Architecture Driver Initialized.
10525 06:54:21.104009 <6>[ 0.645196] vgaarb: loaded
10526 06:54:21.110838 <6>[ 0.648349] clocksource: Switched to clocksource arch_sys_counter
10527 06:54:21.117028 <5>[ 0.654794] VFS: Disk quotas dquot_6.6.0
10528 06:54:21.123624 <6>[ 0.658980] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10529 06:54:21.127076 <6>[ 0.666174] pnp: PnP ACPI: disabled
10530 06:54:21.135321 <6>[ 0.672841] NET: Registered PF_INET protocol family
10531 06:54:21.144548 <6>[ 0.678424] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10532 06:54:21.156125 <6>[ 0.690737] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10533 06:54:21.165733 <6>[ 0.699553] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10534 06:54:21.172450 <6>[ 0.707525] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10535 06:54:21.182279 <6>[ 0.716226] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10536 06:54:21.189244 <6>[ 0.725970] TCP: Hash tables configured (established 65536 bind 65536)
10537 06:54:21.195472 <6>[ 0.732833] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10538 06:54:21.205364 <6>[ 0.740028] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10539 06:54:21.212120 <6>[ 0.747733] NET: Registered PF_UNIX/PF_LOCAL protocol family
10540 06:54:21.215307 <6>[ 0.753905] RPC: Registered named UNIX socket transport module.
10541 06:54:21.222116 <6>[ 0.760058] RPC: Registered udp transport module.
10542 06:54:21.225410 <6>[ 0.764992] RPC: Registered tcp transport module.
10543 06:54:21.231854 <6>[ 0.769925] RPC: Registered tcp NFSv4.1 backchannel transport module.
10544 06:54:21.238802 <6>[ 0.776596] PCI: CLS 0 bytes, default 64
10545 06:54:21.241865 <6>[ 0.781021] Unpacking initramfs...
10546 06:54:21.248721 <6>[ 0.784766] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10547 06:54:21.258694 <6>[ 0.793418] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10548 06:54:21.265291 <6>[ 0.802263] kvm [1]: IPA Size Limit: 40 bits
10549 06:54:21.268672 <6>[ 0.806790] kvm [1]: GICv3: no GICV resource entry
10550 06:54:21.272409 <6>[ 0.811809] kvm [1]: disabling GICv2 emulation
10551 06:54:21.279151 <6>[ 0.816496] kvm [1]: GIC system register CPU interface enabled
10552 06:54:21.285315 <6>[ 0.822669] kvm [1]: vgic interrupt IRQ18
10553 06:54:21.292064 <6>[ 0.828423] kvm [1]: VHE mode initialized successfully
10554 06:54:21.295253 <5>[ 0.834843] Initialise system trusted keyrings
10555 06:54:21.302142 <6>[ 0.839641] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10556 06:54:21.311535 <6>[ 0.849641] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10557 06:54:21.318242 <5>[ 0.856007] NFS: Registering the id_resolver key type
10558 06:54:21.321274 <5>[ 0.861305] Key type id_resolver registered
10559 06:54:21.327999 <5>[ 0.865720] Key type id_legacy registered
10560 06:54:21.334637 <6>[ 0.869997] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10561 06:54:21.341159 <6>[ 0.876916] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10562 06:54:21.348116 <6>[ 0.884629] 9p: Installing v9fs 9p2000 file system support
10563 06:54:21.384863 <5>[ 0.923265] Key type asymmetric registered
10564 06:54:21.388554 <5>[ 0.927594] Asymmetric key parser 'x509' registered
10565 06:54:21.398648 <6>[ 0.932727] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10566 06:54:21.401534 <6>[ 0.940340] io scheduler mq-deadline registered
10567 06:54:21.404767 <6>[ 0.945103] io scheduler kyber registered
10568 06:54:21.423907 <6>[ 0.962020] EINJ: ACPI disabled.
10569 06:54:21.456096 <4>[ 0.987548] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10570 06:54:21.466178 <4>[ 0.998180] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 06:54:21.480635 <6>[ 1.018834] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10572 06:54:21.489122 <6>[ 1.026892] printk: console [ttyS0] disabled
10573 06:54:21.516726 <6>[ 1.051524] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10574 06:54:21.523087 <6>[ 1.061002] printk: console [ttyS0] enabled
10575 06:54:21.526462 <6>[ 1.061002] printk: console [ttyS0] enabled
10576 06:54:21.533079 <6>[ 1.069918] printk: bootconsole [mtk8250] disabled
10577 06:54:21.536305 <6>[ 1.069918] printk: bootconsole [mtk8250] disabled
10578 06:54:21.543303 <6>[ 1.081016] SuperH (H)SCI(F) driver initialized
10579 06:54:21.546457 <6>[ 1.086293] msm_serial: driver initialized
10580 06:54:21.560507 <6>[ 1.095207] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10581 06:54:21.570542 <6>[ 1.103753] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10582 06:54:21.577058 <6>[ 1.112294] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10583 06:54:21.586766 <6>[ 1.120922] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10584 06:54:21.593633 <6>[ 1.129629] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10585 06:54:21.603329 <6>[ 1.138342] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10586 06:54:21.613654 <6>[ 1.146882] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10587 06:54:21.620201 <6>[ 1.155672] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10588 06:54:21.630273 <6>[ 1.164215] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10589 06:54:21.642163 <6>[ 1.179730] loop: module loaded
10590 06:54:21.648234 <6>[ 1.185616] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10591 06:54:21.670460 <4>[ 1.208916] mtk-pmic-keys: Failed to locate of_node [id: -1]
10592 06:54:21.677472 <6>[ 1.215715] megasas: 07.719.03.00-rc1
10593 06:54:21.687215 <6>[ 1.225405] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10594 06:54:21.697960 <6>[ 1.235730] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10595 06:54:21.713638 <6>[ 1.251663] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10596 06:54:21.769115 <6>[ 1.300744] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10597 06:54:22.836914 <6>[ 2.374971] Freeing initrd memory: 38448K
10598 06:54:22.847052 <6>[ 2.385227] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10599 06:54:22.857906 <6>[ 2.396203] tun: Universal TUN/TAP device driver, 1.6
10600 06:54:22.861168 <6>[ 2.402271] thunder_xcv, ver 1.0
10601 06:54:22.864573 <6>[ 2.405779] thunder_bgx, ver 1.0
10602 06:54:22.868250 <6>[ 2.409272] nicpf, ver 1.0
10603 06:54:22.878214 <6>[ 2.413301] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10604 06:54:22.881863 <6>[ 2.420779] hns3: Copyright (c) 2017 Huawei Corporation.
10605 06:54:22.888799 <6>[ 2.426369] hclge is initializing
10606 06:54:22.891787 <6>[ 2.429946] e1000: Intel(R) PRO/1000 Network Driver
10607 06:54:22.898348 <6>[ 2.435075] e1000: Copyright (c) 1999-2006 Intel Corporation.
10608 06:54:22.901524 <6>[ 2.441086] e1000e: Intel(R) PRO/1000 Network Driver
10609 06:54:22.908307 <6>[ 2.446302] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10610 06:54:22.915331 <6>[ 2.452488] igb: Intel(R) Gigabit Ethernet Network Driver
10611 06:54:22.921536 <6>[ 2.458137] igb: Copyright (c) 2007-2014 Intel Corporation.
10612 06:54:22.927976 <6>[ 2.463977] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10613 06:54:22.934848 <6>[ 2.470494] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10614 06:54:22.938450 <6>[ 2.476956] sky2: driver version 1.30
10615 06:54:22.944741 <6>[ 2.481968] VFIO - User Level meta-driver version: 0.3
10616 06:54:22.952028 <6>[ 2.490216] usbcore: registered new interface driver usb-storage
10617 06:54:22.958525 <6>[ 2.496667] usbcore: registered new device driver onboard-usb-hub
10618 06:54:22.967531 <6>[ 2.505855] mt6397-rtc mt6359-rtc: registered as rtc0
10619 06:54:22.977567 <6>[ 2.511322] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:53:48 UTC (1706943228)
10620 06:54:22.980686 <6>[ 2.520897] i2c_dev: i2c /dev entries driver
10621 06:54:22.997652 <6>[ 2.532773] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10622 06:54:23.018669 <6>[ 2.556775] cpu cpu0: EM: created perf domain
10623 06:54:23.021815 <6>[ 2.561715] cpu cpu4: EM: created perf domain
10624 06:54:23.028394 <6>[ 2.567017] sdhci: Secure Digital Host Controller Interface driver
10625 06:54:23.035186 <6>[ 2.573452] sdhci: Copyright(c) Pierre Ossman
10626 06:54:23.041736 <6>[ 2.578414] Synopsys Designware Multimedia Card Interface Driver
10627 06:54:23.048679 <6>[ 2.585061] sdhci-pltfm: SDHCI platform and OF driver helper
10628 06:54:23.051713 <6>[ 2.585187] mmc0: CQHCI version 5.10
10629 06:54:23.058718 <6>[ 2.595062] ledtrig-cpu: registered to indicate activity on CPUs
10630 06:54:23.065069 <6>[ 2.602074] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10631 06:54:23.071688 <6>[ 2.609126] usbcore: registered new interface driver usbhid
10632 06:54:23.074974 <6>[ 2.614947] usbhid: USB HID core driver
10633 06:54:23.081556 <6>[ 2.619153] spi_master spi0: will run message pump with realtime priority
10634 06:54:23.128894 <6>[ 2.660519] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10635 06:54:23.148001 <6>[ 2.676761] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10636 06:54:23.151868 <6>[ 2.690334] mmc0: Command Queue Engine enabled
10637 06:54:23.158516 <6>[ 2.695090] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10638 06:54:23.165268 <6>[ 2.702234] cros-ec-spi spi0.0: Chrome EC device registered
10639 06:54:23.168303 <6>[ 2.702464] mmcblk0: mmc0:0001 DA4128 116 GiB
10640 06:54:23.181206 <6>[ 2.719469] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10641 06:54:23.188981 <6>[ 2.727215] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10642 06:54:23.195625 <6>[ 2.733354] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10643 06:54:23.205641 <6>[ 2.737563] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10644 06:54:23.211853 <6>[ 2.739520] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10645 06:54:23.215194 <6>[ 2.749060] NET: Registered PF_PACKET protocol family
10646 06:54:23.222252 <6>[ 2.759822] 9pnet: Installing 9P2000 support
10647 06:54:23.225532 <5>[ 2.764413] Key type dns_resolver registered
10648 06:54:23.231914 <6>[ 2.769520] registered taskstats version 1
10649 06:54:23.235458 <5>[ 2.773907] Loading compiled-in X.509 certificates
10650 06:54:23.263395 <4>[ 2.795362] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10651 06:54:23.273404 <4>[ 2.806112] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 06:54:23.280075 <3>[ 2.816703] debugfs: File 'uA_load' in directory '/' already present!
10653 06:54:23.287028 <3>[ 2.823415] debugfs: File 'min_uV' in directory '/' already present!
10654 06:54:23.293787 <3>[ 2.830030] debugfs: File 'max_uV' in directory '/' already present!
10655 06:54:23.299981 <3>[ 2.836641] debugfs: File 'constraint_flags' in directory '/' already present!
10656 06:54:23.312391 <3>[ 2.847462] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10657 06:54:23.323108 <6>[ 2.861708] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10658 06:54:23.330166 <6>[ 2.868390] xhci-mtk 11200000.usb: xHCI Host Controller
10659 06:54:23.336548 <6>[ 2.873874] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10660 06:54:23.346566 <6>[ 2.881700] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10661 06:54:23.353302 <6>[ 2.891112] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10662 06:54:23.360068 <6>[ 2.897171] xhci-mtk 11200000.usb: xHCI Host Controller
10663 06:54:23.366360 <6>[ 2.902661] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10664 06:54:23.373004 <6>[ 2.910307] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10665 06:54:23.379912 <6>[ 2.917944] hub 1-0:1.0: USB hub found
10666 06:54:23.383116 <6>[ 2.921953] hub 1-0:1.0: 1 port detected
10667 06:54:23.392717 <6>[ 2.926211] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10668 06:54:23.395915 <6>[ 2.934851] hub 2-0:1.0: USB hub found
10669 06:54:23.399122 <6>[ 2.938879] hub 2-0:1.0: 1 port detected
10670 06:54:23.407314 <6>[ 2.945880] mtk-msdc 11f70000.mmc: Got CD GPIO
10671 06:54:23.419558 <6>[ 2.954244] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10672 06:54:23.425696 <6>[ 2.962264] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10673 06:54:23.435824 <4>[ 2.970161] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10674 06:54:23.446006 <6>[ 2.979686] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10675 06:54:23.452203 <6>[ 2.987765] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10676 06:54:23.458947 <6>[ 2.995780] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10677 06:54:23.468807 <6>[ 3.003696] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10678 06:54:23.475347 <6>[ 3.011513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10679 06:54:23.485333 <6>[ 3.019330] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10680 06:54:23.495308 <6>[ 3.029661] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10681 06:54:23.501909 <6>[ 3.038024] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10682 06:54:23.511705 <6>[ 3.046367] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10683 06:54:23.518455 <6>[ 3.054707] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10684 06:54:23.528124 <6>[ 3.063045] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10685 06:54:23.535221 <6>[ 3.071385] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10686 06:54:23.544858 <6>[ 3.079724] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10687 06:54:23.551339 <6>[ 3.088063] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10688 06:54:23.561499 <6>[ 3.096403] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10689 06:54:23.571579 <6>[ 3.104743] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10690 06:54:23.578294 <6>[ 3.113084] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10691 06:54:23.587681 <6>[ 3.121424] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10692 06:54:23.594569 <6>[ 3.129763] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10693 06:54:23.604175 <6>[ 3.138102] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10694 06:54:23.611025 <6>[ 3.146441] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10695 06:54:23.617600 <6>[ 3.155191] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10696 06:54:23.623978 <6>[ 3.162372] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10697 06:54:23.633906 <6>[ 3.169134] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10698 06:54:23.640266 <6>[ 3.175890] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10699 06:54:23.647214 <6>[ 3.182818] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10700 06:54:23.656969 <6>[ 3.189710] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10701 06:54:23.663474 <6>[ 3.198840] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10702 06:54:23.673429 <6>[ 3.207959] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10703 06:54:23.683586 <6>[ 3.217252] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10704 06:54:23.693514 <6>[ 3.226721] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10705 06:54:23.703066 <6>[ 3.236189] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10706 06:54:23.710298 <6>[ 3.245307] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10707 06:54:23.719737 <6>[ 3.254795] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10708 06:54:23.729899 <6>[ 3.263915] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10709 06:54:23.739800 <6>[ 3.273209] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10710 06:54:23.749496 <6>[ 3.283369] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10711 06:54:23.759696 <6>[ 3.294945] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10712 06:54:23.789374 <6>[ 3.324883] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10713 06:54:23.818036 <6>[ 3.356189] hub 2-1:1.0: USB hub found
10714 06:54:23.821715 <6>[ 3.360668] hub 2-1:1.0: 3 ports detected
10715 06:54:23.829566 <6>[ 3.367924] hub 2-1:1.0: USB hub found
10716 06:54:23.832668 <6>[ 3.372246] hub 2-1:1.0: 3 ports detected
10717 06:54:23.941448 <6>[ 3.476561] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10718 06:54:24.096171 <6>[ 3.634738] hub 1-1:1.0: USB hub found
10719 06:54:24.099415 <6>[ 3.639217] hub 1-1:1.0: 4 ports detected
10720 06:54:24.109228 <6>[ 3.647691] hub 1-1:1.0: USB hub found
10721 06:54:24.112249 <6>[ 3.652184] hub 1-1:1.0: 4 ports detected
10722 06:54:24.181609 <6>[ 3.716872] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10723 06:54:24.433519 <6>[ 3.968708] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10724 06:54:24.566294 <6>[ 4.104624] hub 1-1.4:1.0: USB hub found
10725 06:54:24.569402 <6>[ 4.109303] hub 1-1.4:1.0: 2 ports detected
10726 06:54:24.579148 <6>[ 4.117448] hub 1-1.4:1.0: USB hub found
10727 06:54:24.581884 <6>[ 4.121951] hub 1-1.4:1.0: 2 ports detected
10728 06:54:24.877639 <6>[ 4.412647] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10729 06:54:25.069791 <6>[ 4.604646] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10730 06:54:36.062797 <6>[ 15.605581] ALSA device list:
10731 06:54:36.069379 <6>[ 15.608870] No soundcards found.
10732 06:54:36.077230 <6>[ 15.616125] Freeing unused kernel memory: 8448K
10733 06:54:36.079962 <6>[ 15.621172] Run /init as init process
10734 06:54:36.125805 <6>[ 15.664826] NET: Registered PF_INET6 protocol family
10735 06:54:36.129098 <6>[ 15.670835] Segment Routing with IPv6
10736 06:54:36.135381 <6>[ 15.674799] In-situ OAM (IOAM) with IPv6
10737 06:54:36.170667 <30>[ 15.690312] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10738 06:54:36.174363 <30>[ 15.714263] systemd[1]: Detected architecture arm64.
10739 06:54:36.174934
10740 06:54:36.180516 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10741 06:54:36.180978
10742 06:54:36.197370 <30>[ 15.736582] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10743 06:54:36.334309 <30>[ 15.870321] systemd[1]: Queued start job for default target Graphical Interface.
10744 06:54:36.382098 <30>[ 15.921076] systemd[1]: Created slice system-getty.slice.
10745 06:54:36.388232 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10746 06:54:36.405763 <30>[ 15.944840] systemd[1]: Created slice system-modprobe.slice.
10747 06:54:36.412208 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10748 06:54:36.434307 <30>[ 15.973318] systemd[1]: Created slice system-serial\x2dgetty.slice.
10749 06:54:36.444243 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10750 06:54:36.458870 <30>[ 15.997742] systemd[1]: Created slice User and Session Slice.
10751 06:54:36.465021 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10752 06:54:36.485539 <30>[ 16.021203] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10753 06:54:36.494789 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10754 06:54:36.513442 <30>[ 16.049285] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10755 06:54:36.519755 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10756 06:54:36.544564 <30>[ 16.077047] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10757 06:54:36.550566 <30>[ 16.089308] systemd[1]: Reached target Local Encrypted Volumes.
10758 06:54:36.557923 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10759 06:54:36.574007 <30>[ 16.113091] systemd[1]: Reached target Paths.
10760 06:54:36.577248 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10761 06:54:36.593306 <30>[ 16.132640] systemd[1]: Reached target Remote File Systems.
10762 06:54:36.599870 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10763 06:54:36.617411 <30>[ 16.156925] systemd[1]: Reached target Slices.
10764 06:54:36.624160 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10765 06:54:36.637293 <30>[ 16.176650] systemd[1]: Reached target Swap.
10766 06:54:36.640753 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10767 06:54:36.660837 <30>[ 16.197110] systemd[1]: Listening on initctl Compatibility Named Pipe.
10768 06:54:36.667413 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10769 06:54:36.674795 <30>[ 16.212237] systemd[1]: Listening on Journal Audit Socket.
10770 06:54:36.680781 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10771 06:54:36.694084 <30>[ 16.233124] systemd[1]: Listening on Journal Socket (/dev/log).
10772 06:54:36.700700 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10773 06:54:36.718394 <30>[ 16.257747] systemd[1]: Listening on Journal Socket.
10774 06:54:36.724880 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10775 06:54:36.741449 <30>[ 16.277321] systemd[1]: Listening on Network Service Netlink Socket.
10776 06:54:36.747883 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10777 06:54:36.761799 <30>[ 16.301194] systemd[1]: Listening on udev Control Socket.
10778 06:54:36.768423 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10779 06:54:36.785971 <30>[ 16.325606] systemd[1]: Listening on udev Kernel Socket.
10780 06:54:36.793004 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10781 06:54:36.849395 <30>[ 16.388804] systemd[1]: Mounting Huge Pages File System...
10782 06:54:36.856000 Mounting [0;1;39mHuge Pages File System[0m...
10783 06:54:36.871868 <30>[ 16.411124] systemd[1]: Mounting POSIX Message Queue File System...
10784 06:54:36.878519 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10785 06:54:36.894824 <30>[ 16.434250] systemd[1]: Mounting Kernel Debug File System...
10786 06:54:36.901163 Mounting [0;1;39mKernel Debug File System[0m...
10787 06:54:36.920436 <30>[ 16.456714] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10788 06:54:36.931744 <30>[ 16.467989] systemd[1]: Starting Create list of static device nodes for the current kernel...
10789 06:54:36.938503 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10790 06:54:36.957346 <30>[ 16.496870] systemd[1]: Starting Load Kernel Module configfs...
10791 06:54:36.963820 Starting [0;1;39mLoad Kernel Module configfs[0m...
10792 06:54:36.981539 <30>[ 16.520792] systemd[1]: Starting Load Kernel Module drm...
10793 06:54:36.988319 Starting [0;1;39mLoad Kernel Module drm[0m...
10794 06:54:37.004651 <30>[ 16.540958] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10795 06:54:37.018922 <30>[ 16.558326] systemd[1]: Starting Journal Service...
10796 06:54:37.022217 Starting [0;1;39mJournal Service[0m...
10797 06:54:37.041462 <30>[ 16.580904] systemd[1]: Starting Load Kernel Modules...
10798 06:54:37.048613 Starting [0;1;39mLoad Kernel Modules[0m...
10799 06:54:37.068170 <30>[ 16.604425] systemd[1]: Starting Remount Root and Kernel File Systems...
10800 06:54:37.074690 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10801 06:54:37.092987 <30>[ 16.632327] systemd[1]: Starting Coldplug All udev Devices...
10802 06:54:37.099425 Starting [0;1;39mColdplug All udev Devices[0m...
10803 06:54:37.116006 <30>[ 16.655405] systemd[1]: Started Journal Service.
10804 06:54:37.122378 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10805 06:54:37.139321 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10806 06:54:37.153876 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10807 06:54:37.169674 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10808 06:54:37.190030 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10809 06:54:37.207730 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10810 06:54:37.227555 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10811 06:54:37.247382 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10812 06:54:37.267012 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10813 06:54:37.281796 See 'systemctl status systemd-remount-fs.service' for details.
10814 06:54:37.332445 Mounting [0;1;39mKernel Configuration File System[0m...
10815 06:54:37.351292 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10816 06:54:37.361629 <46>[ 16.897780] systemd-journald[176]: Received client request to flush runtime journal.
10817 06:54:37.368890 Starting [0;1;39mLoad/Save Random Seed[0m...
10818 06:54:37.392128 Starting [0;1;39mApply Kernel Variables[0m...
10819 06:54:37.413306 Starting [0;1;39mCreate System Users[0m...
10820 06:54:37.438474 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10821 06:54:37.458284 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10822 06:54:37.478567 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10823 06:54:37.494974 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10824 06:54:37.511051 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10825 06:54:37.527346 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10826 06:54:37.565799 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10827 06:54:37.586242 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10828 06:54:37.597331 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10829 06:54:37.613008 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10830 06:54:37.649857 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10831 06:54:37.677695 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10832 06:54:37.697860 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10833 06:54:37.716414 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10834 06:54:37.745547 Starting [0;1;39mNetwork Service[0m...
10835 06:54:37.764398 Starting [0;1;39mNetwork Time Synchronization[0m...
10836 06:54:37.782190 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10837 06:54:37.801362 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10838 06:54:37.813286 <6>[ 17.349295] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10839 06:54:37.819786 <6>[ 17.357050] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10840 06:54:37.829600 <3>[ 17.360259] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10841 06:54:37.836368 <6>[ 17.365318] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10842 06:54:37.846326 <6>[ 17.365961] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10843 06:54:37.853062 <3>[ 17.373844] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10844 06:54:37.862761 <3>[ 17.373848] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10845 06:54:37.869447 <3>[ 17.374808] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10846 06:54:37.875998 <6>[ 17.378303] remoteproc remoteproc0: scp is available
10847 06:54:37.878787 <6>[ 17.378369] remoteproc remoteproc0: powering up scp
10848 06:54:37.888877 <6>[ 17.378378] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10849 06:54:37.892378 <6>[ 17.378395] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10850 06:54:37.902528 <4>[ 17.425584] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10851 06:54:37.908832 <3>[ 17.433118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10852 06:54:37.915608 <4>[ 17.443320] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10853 06:54:37.925571 <3>[ 17.445859] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 06:54:37.931870 <6>[ 17.447760] usbcore: registered new device driver r8152-cfgselector
10855 06:54:37.938572 <6>[ 17.458955] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10856 06:54:37.945769 <3>[ 17.461214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 06:54:37.955316 <3>[ 17.461218] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 06:54:37.962554 <3>[ 17.463254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 06:54:37.969262 <6>[ 17.463818] mc: Linux media interface: v0.10
10860 06:54:37.975905 <4>[ 17.481267] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10861 06:54:37.982745 <4>[ 17.481267] Fallback method does not support PEC.
10862 06:54:37.989923 <3>[ 17.483512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10863 06:54:37.996580 <6>[ 17.504060] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10864 06:54:38.003346 <6>[ 17.504064] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10865 06:54:38.014127 <6>[ 17.505560] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10866 06:54:38.017425 <6>[ 17.505564] pci_bus 0000:00: root bus resource [bus 00-ff]
10867 06:54:38.023935 <6>[ 17.505567] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10868 06:54:38.034150 <6>[ 17.505570] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10869 06:54:38.040772 <6>[ 17.505586] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10870 06:54:38.046935 <6>[ 17.505598] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10871 06:54:38.053735 <6>[ 17.505652] pci 0000:00:00.0: supports D1 D2
10872 06:54:38.060623 <6>[ 17.505654] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10873 06:54:38.067601 <6>[ 17.506385] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10874 06:54:38.073816 <6>[ 17.506461] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10875 06:54:38.080828 <6>[ 17.506485] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10876 06:54:38.090300 <6>[ 17.506502] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10877 06:54:38.097584 <6>[ 17.506516] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10878 06:54:38.101404 <6>[ 17.506620] pci 0000:01:00.0: supports D1 D2
10879 06:54:38.106855 <6>[ 17.506621] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10880 06:54:38.116881 <3>[ 17.507710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 06:54:38.123280 <3>[ 17.507712] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 06:54:38.133535 <3>[ 17.507742] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 06:54:38.139863 <3>[ 17.508014] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 06:54:38.146669 <6>[ 17.512253] remoteproc remoteproc0: remote processor scp is now up
10885 06:54:38.156779 <6>[ 17.516102] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10886 06:54:38.166253 <6>[ 17.516355] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10887 06:54:38.172959 <6>[ 17.520398] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10888 06:54:38.179988 <6>[ 17.520414] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10889 06:54:38.190978 <6>[ 17.520416] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10890 06:54:38.198199 <6>[ 17.520424] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10891 06:54:38.205129 <6>[ 17.520436] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10892 06:54:38.214950 <6>[ 17.520449] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10893 06:54:38.218554 <6>[ 17.520461] pci 0000:00:00.0: PCI bridge to [bus 01]
10894 06:54:38.228540 <6>[ 17.520466] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10895 06:54:38.231713 <6>[ 17.520547] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10896 06:54:38.238147 <6>[ 17.520912] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10897 06:54:38.244776 <6>[ 17.521179] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10898 06:54:38.254535 <3>[ 17.525876] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10899 06:54:38.261296 <3>[ 17.525879] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10900 06:54:38.270993 <3>[ 17.538966] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 06:54:38.277899 <3>[ 17.539767] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10902 06:54:38.287837 <3>[ 17.542469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10903 06:54:38.294541 <3>[ 17.542471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10904 06:54:38.304327 <6>[ 17.556476] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10905 06:54:38.311255 <6>[ 17.558775] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10906 06:54:38.320902 <3>[ 17.562368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10907 06:54:38.327422 <6>[ 17.569969] videodev: Linux video capture interface: v2.00
10908 06:54:38.331202 <6>[ 17.579607] Bluetooth: Core ver 2.22
10909 06:54:38.337302 <3>[ 17.585605] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 06:54:38.347272 <6>[ 17.586597] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10911 06:54:38.353787 <5>[ 17.587217] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10912 06:54:38.364004 <6>[ 17.588437] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10913 06:54:38.371151 <4>[ 17.592824] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10914 06:54:38.380996 <4>[ 17.592830] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10915 06:54:38.387646 <6>[ 17.593526] NET: Registered PF_BLUETOOTH protocol family
10916 06:54:38.394206 <5>[ 17.596205] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10917 06:54:38.400421 <5>[ 17.596521] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10918 06:54:38.410828 <4>[ 17.596597] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10919 06:54:38.413921 <6>[ 17.596601] cfg80211: failed to load regulatory.db
10920 06:54:38.420420 <6>[ 17.646624] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10921 06:54:38.426963 <6>[ 17.652651] Bluetooth: HCI device and connection manager initialized
10922 06:54:38.433667 <6>[ 17.652659] Bluetooth: HCI socket layer initialized
10923 06:54:38.437238 <6>[ 17.652771] r8152 2-1.3:1.0 eth0: v1.12.13
10924 06:54:38.443625 <6>[ 17.652832] usbcore: registered new interface driver r8152
10925 06:54:38.457183 <6>[ 17.662028] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10926 06:54:38.460276 <6>[ 17.668816] Bluetooth: L2CAP socket layer initialized
10927 06:54:38.467049 <6>[ 17.668823] Bluetooth: SCO socket layer initialized
10928 06:54:38.473636 <6>[ 17.677024] usbcore: registered new interface driver uvcvideo
10929 06:54:38.480298 <6>[ 17.677525] usbcore: registered new interface driver cdc_ether
10930 06:54:38.486713 <6>[ 17.685265] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10931 06:54:38.493267 <6>[ 17.685339] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10932 06:54:38.500122 <6>[ 17.692214] usbcore: registered new interface driver r8153_ecm
10933 06:54:38.506456 <6>[ 17.692631] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10934 06:54:38.509877 <6>[ 17.711279] mt7921e 0000:01:00.0: ASIC revision: 79610010
10935 06:54:38.516563 <6>[ 17.734468] usbcore: registered new interface driver btusb
10936 06:54:38.526770 <4>[ 17.734992] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10937 06:54:38.533066 <3>[ 17.734997] Bluetooth: hci0: Failed to load firmware file (-2)
10938 06:54:38.539188 <3>[ 17.734999] Bluetooth: hci0: Failed to set up firmware (-2)
10939 06:54:38.549195 <4>[ 17.735000] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10940 06:54:38.559047 <3>[ 17.739365] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10941 06:54:38.562440 <6>[ 17.745444] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10942 06:54:38.572419 <6>[ 17.826101] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10943 06:54:38.575764 <6>[ 17.826101]
10944 06:54:38.582728 <3>[ 17.837036] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 06:54:38.592287 <6>[ 18.108877] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10946 06:54:38.598739 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10947 06:54:38.618357 <3>[ 18.155061] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 06:54:38.629999 <3>[ 18.166176] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10949 06:54:38.653303 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10950 06:54:38.677611 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10951 06:54:38.688238 <3>[ 18.221490] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 06:54:38.694511 <3>[ 18.222177] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10953 06:54:38.821680 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10954 06:54:38.837296 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10955 06:54:38.853366 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10956 06:54:38.869600 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10957 06:54:38.888541 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10958 06:54:38.928790 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10959 06:54:38.947594 Starting [0;1;39mNetwork Name Resolution[0m...
10960 06:54:38.966392 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10961 06:54:38.981727 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10962 06:54:39.000807 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10963 06:54:39.016544 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10964 06:54:39.029540 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10965 06:54:39.048318 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10966 06:54:39.061130 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10967 06:54:39.080840 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10968 06:54:39.121464 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10969 06:54:39.153075 Starting [0;1;39mUser Login Management[0m...
10970 06:54:39.173284 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10971 06:54:39.190347 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10972 06:54:39.201796 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10973 06:54:39.221563 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10974 06:54:39.244634 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10975 06:54:39.277440 Starting [0;1;39mPermit User Sessions[0m...
10976 06:54:39.295265 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10977 06:54:39.313916 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10978 06:54:39.370800 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10979 06:54:39.390766 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10980 06:54:39.405926 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10981 06:54:39.421846 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10982 06:54:39.435999 <6>[ 18.975778] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10983 06:54:39.442988 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10984 06:54:39.509738 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10985 06:54:39.559057 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10986 06:54:39.602270
10987 06:54:39.602834
10988 06:54:39.605431 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10989 06:54:39.606023
10990 06:54:39.608579 debian-bullseye-arm64 login: root (automatic login)
10991 06:54:39.609144
10992 06:54:39.609516
10993 06:54:39.627784 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024 aarch64
10994 06:54:39.628381
10995 06:54:39.634259 The programs included with the Debian GNU/Linux system are free software;
10996 06:54:39.640729 the exact distribution terms for each program are described in the
10997 06:54:39.644229 individual files in /usr/share/doc/*/copyright.
10998 06:54:39.644787
10999 06:54:39.650660 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11000 06:54:39.654128 permitted by applicable law.
11001 06:54:39.655503 Matched prompt #10: / #
11003 06:54:39.656671 Setting prompt string to ['/ #']
11004 06:54:39.657142 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11006 06:54:39.658261 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11007 06:54:39.658919 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
11008 06:54:39.659310 Setting prompt string to ['/ #']
11009 06:54:39.659653 Forcing a shell prompt, looking for ['/ #']
11011 06:54:39.710580 / #
11012 06:54:39.711230 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11013 06:54:39.711682 Waiting using forced prompt support (timeout 00:02:30)
11014 06:54:39.717165
11015 06:54:39.718120 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11016 06:54:39.718647 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
11017 06:54:39.719185 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11018 06:54:39.719664 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
11019 06:54:39.720124 end: 2 depthcharge-action (duration 00:01:35) [common]
11020 06:54:39.720602 start: 3 lava-test-retry (timeout 00:08:06) [common]
11021 06:54:39.721077 start: 3.1 lava-test-shell (timeout 00:08:06) [common]
11022 06:54:39.721474 Using namespace: common
11024 06:54:39.822833 / # #
11025 06:54:39.823497 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11026 06:54:39.824096 <6>[ 19.307791] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11027 06:54:39.824485 <6>[ 19.315771] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11028 06:54:39.829101 #
11029 06:54:39.830088 Using /lava-12694845
11031 06:54:39.931573 / # export SHELL=/bin/sh
11032 06:54:39.938160 export SHELL=/bin/sh
11034 06:54:40.040006 / # . /lava-12694845/environment
11035 06:54:40.046631 . /lava-12694845/environment
11037 06:54:40.148457 / # /lava-12694845/bin/lava-test-runner /lava-12694845/0
11038 06:54:40.149114 Test shell timeout: 10s (minimum of the action and connection timeout)
11039 06:54:40.155104 /lava-12694845/bin/lava-test-runner /lava-12694845/0
11040 06:54:40.174461 + export TESTRUN_ID=0_v4l2-compliance-uvc
11041 06:54:40.177816 + cd /lava-12694845/0/tests/0_v4l2-compliance-uvc
11042 06:54:40.178447 + cat uuid
11043 06:54:40.181007 + UUID=12694845_1.5.2.3.1
11044 06:54:40.181575 + set +x
11045 06:54:40.187717 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12694845_1.5.2.3.1>
11046 06:54:40.188523 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12694845_1.5.2.3.1
11047 06:54:40.188972 Starting test lava.0_v4l2-compliance-uvc (12694845_1.5.2.3.1)
11048 06:54:40.189431 Skipping test definition patterns.
11049 06:54:40.190970 + /usr/bin/v4l2-parser.sh -d uvcvideo
11050 06:54:40.197623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11051 06:54:40.198248 device: /dev/video0
11052 06:54:40.198890 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11054 06:54:46.672237 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11055 06:54:46.682595 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11056 06:54:46.690567
11057 06:54:46.707049 Compliance test for uvcvideo device /dev/video0:
11058 06:54:46.712840
11059 06:54:46.721830 Driver Info:
11060 06:54:46.736823 Driver name : uvcvideo
11061 06:54:46.750280 Card type : HD User Facing: HD User Facing
11062 06:54:46.761007 Bus info : usb-11200000.usb-1.4.1
11063 06:54:46.770857 Driver version : 6.1.75
11064 06:54:46.782847 Capabilities : 0x84a00001
11065 06:54:46.797778 Metadata Capture
11066 06:54:46.807548 Streaming
11067 06:54:46.819644 Extended Pix Format
11068 06:54:46.833429 Device Capabilities
11069 06:54:46.842809 Device Caps : 0x04200001
11070 06:54:46.857318 Streaming
11071 06:54:46.866788 Extended Pix Format
11072 06:54:46.877473 Media Driver Info:
11073 06:54:46.889120 Driver name : uvcvideo
11074 06:54:46.901436 Model : HD User Facing: HD User Facing
11075 06:54:46.907217 Serial : 200901010001
11076 06:54:46.922499 Bus info : usb-11200000.usb-1.4.1
11077 06:54:46.934146 Media version : 6.1.75
11078 06:54:46.947228 Hardware revision: 0x00009758 (38744)
11079 06:54:46.953521 Driver version : 6.1.75
11080 06:54:46.965775 Interface Info:
11081 06:54:46.983426 <LAVA_SIGNAL_TESTSET START Interface-Info>
11082 06:54:46.983992 ID : 0x03000002
11083 06:54:46.984638 Received signal: <TESTSET> START Interface-Info
11084 06:54:46.985241 Starting test_set Interface-Info
11085 06:54:46.994078 Type : V4L Video
11086 06:54:47.002848 Entity Info:
11087 06:54:47.009986 <LAVA_SIGNAL_TESTSET STOP>
11088 06:54:47.010827 Received signal: <TESTSET> STOP
11089 06:54:47.011225 Closing test_set Interface-Info
11090 06:54:47.018904 <LAVA_SIGNAL_TESTSET START Entity-Info>
11091 06:54:47.019736 Received signal: <TESTSET> START Entity-Info
11092 06:54:47.020132 Starting test_set Entity-Info
11093 06:54:47.022074 ID : 0x00000001 (1)
11094 06:54:47.030883 Name : HD User Facing: HD User Facing
11095 06:54:47.038218 Function : V4L2 I/O
11096 06:54:47.048941 Flags : default
11097 06:54:47.062146 Pad 0x01000007 : 0: Sink
11098 06:54:47.081719 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11099 06:54:47.082316
11100 06:54:47.092322 Required ioctls:
11101 06:54:47.098511 <LAVA_SIGNAL_TESTSET STOP>
11102 06:54:47.099347 Received signal: <TESTSET> STOP
11103 06:54:47.099732 Closing test_set Entity-Info
11104 06:54:47.107210 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11105 06:54:47.107936 Received signal: <TESTSET> START Required-ioctls
11106 06:54:47.108383 Starting test_set Required-ioctls
11107 06:54:47.110075 test MC information (see 'Media Driver Info' above): OK
11108 06:54:47.131936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11109 06:54:47.132769 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11111 06:54:47.135426 test VIDIOC_QUERYCAP: OK
11112 06:54:47.151798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11113 06:54:47.152630 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11115 06:54:47.154518 test invalid ioctls: OK
11116 06:54:47.174071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11117 06:54:47.174651
11118 06:54:47.175292 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11120 06:54:47.182853 Allow for multiple opens:
11121 06:54:47.189896 <LAVA_SIGNAL_TESTSET STOP>
11122 06:54:47.190771 Received signal: <TESTSET> STOP
11123 06:54:47.191163 Closing test_set Required-ioctls
11124 06:54:47.198867 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11125 06:54:47.199704 Received signal: <TESTSET> START Allow-for-multiple-opens
11126 06:54:47.200098 Starting test_set Allow-for-multiple-opens
11127 06:54:47.201828 test second /dev/video0 open: OK
11128 06:54:47.221532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11129 06:54:47.222413 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11131 06:54:47.224848 test VIDIOC_QUERYCAP: OK
11132 06:54:47.241792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11133 06:54:47.242691 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11135 06:54:47.245218 test VIDIOC_G/S_PRIORITY: OK
11136 06:54:47.265246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11137 06:54:47.266153 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11139 06:54:47.267813 test for unlimited opens: OK
11140 06:54:47.292687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11141 06:54:47.293266
11142 06:54:47.293913 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11144 06:54:47.302130 Debug ioctls:
11145 06:54:47.309731 <LAVA_SIGNAL_TESTSET STOP>
11146 06:54:47.310623 Received signal: <TESTSET> STOP
11147 06:54:47.311215 Closing test_set Allow-for-multiple-opens
11148 06:54:47.319108 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11149 06:54:47.319947 Received signal: <TESTSET> START Debug-ioctls
11150 06:54:47.320343 Starting test_set Debug-ioctls
11151 06:54:47.322381 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11152 06:54:47.342622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11153 06:54:47.343614 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11155 06:54:47.349392 test VIDIOC_LOG_STATUS: OK (Not Supported)
11156 06:54:47.364194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11157 06:54:47.364746
11158 06:54:47.365684 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11160 06:54:47.373866 Input ioctls:
11161 06:54:47.379547 <LAVA_SIGNAL_TESTSET STOP>
11162 06:54:47.380395 Received signal: <TESTSET> STOP
11163 06:54:47.380785 Closing test_set Debug-ioctls
11164 06:54:47.387835 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11165 06:54:47.388769 Received signal: <TESTSET> START Input-ioctls
11166 06:54:47.389339 Starting test_set Input-ioctls
11167 06:54:47.391122 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11168 06:54:47.414022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11169 06:54:47.414880 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11171 06:54:47.417495 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11172 06:54:47.434083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11173 06:54:47.434918 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11175 06:54:47.440405 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11176 06:54:47.457269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11177 06:54:47.458076 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11179 06:54:47.463773 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11180 06:54:47.480372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11181 06:54:47.481186 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11183 06:54:47.483859 test VIDIOC_G/S/ENUMINPUT: OK
11184 06:54:47.503571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11185 06:54:47.504408 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11187 06:54:47.506605 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11188 06:54:47.526286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11189 06:54:47.527120 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11191 06:54:47.529743 Inputs: 1 Audio Inputs: 0 Tuners: 0
11192 06:54:47.538845
11193 06:54:47.555464 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11194 06:54:47.577559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11195 06:54:47.578432 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11197 06:54:47.584057 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11198 06:54:47.602214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11199 06:54:47.603035 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11201 06:54:47.607955 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11202 06:54:47.623528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11203 06:54:47.624359 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11205 06:54:47.629857 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11206 06:54:47.645269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11207 06:54:47.646119 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11209 06:54:47.651622 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11210 06:54:47.667527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11211 06:54:47.668368 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11213 06:54:47.671686
11214 06:54:47.691065 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11215 06:54:47.710499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11216 06:54:47.711373 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11218 06:54:47.716981 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11219 06:54:47.741524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11220 06:54:47.742430 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11222 06:54:47.744420 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11223 06:54:47.760910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11224 06:54:47.761775 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11226 06:54:47.764798 test VIDIOC_G/S_EDID: OK (Not Supported)
11227 06:54:47.782596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11228 06:54:47.783171
11229 06:54:47.783923 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11231 06:54:47.798454 Control ioctls (Input 0):
11232 06:54:47.806578 <LAVA_SIGNAL_TESTSET STOP>
11233 06:54:47.807449 Received signal: <TESTSET> STOP
11234 06:54:47.807876 Closing test_set Input-ioctls
11235 06:54:47.815329 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11236 06:54:47.816198 Received signal: <TESTSET> START Control-ioctls-Input-0
11237 06:54:47.816655 Starting test_set Control-ioctls-Input-0
11238 06:54:47.818425 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11239 06:54:47.842442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11240 06:54:47.843023 test VIDIOC_QUERYCTRL: OK
11241 06:54:47.843786 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11243 06:54:47.861196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11244 06:54:47.862089 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11246 06:54:47.864831 test VIDIOC_G/S_CTRL: OK
11247 06:54:47.883407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11248 06:54:47.884286 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11250 06:54:47.886564 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11251 06:54:47.905287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11252 06:54:47.906165 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11254 06:54:47.912025 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11255 06:54:47.931957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11256 06:54:47.932709 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11258 06:54:47.934782 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11259 06:54:47.956798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11260 06:54:47.957658 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11262 06:54:47.960442 Standard Controls: 16 Private Controls: 0
11263 06:54:47.968675
11264 06:54:47.979280 Format ioctls (Input 0):
11265 06:54:47.986294 <LAVA_SIGNAL_TESTSET STOP>
11266 06:54:47.987149 Received signal: <TESTSET> STOP
11267 06:54:47.987558 Closing test_set Control-ioctls-Input-0
11268 06:54:47.994088 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11269 06:54:47.994913 Received signal: <TESTSET> START Format-ioctls-Input-0
11270 06:54:47.995311 Starting test_set Format-ioctls-Input-0
11271 06:54:47.997638 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11272 06:54:48.021216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11273 06:54:48.022084 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11275 06:54:48.024132 test VIDIOC_G/S_PARM: OK
11276 06:54:48.037512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11277 06:54:48.038420 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11279 06:54:48.040354 test VIDIOC_G_FBUF: OK (Not Supported)
11280 06:54:48.062072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11281 06:54:48.062920 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11283 06:54:48.065355 test VIDIOC_G_FMT: OK
11284 06:54:48.086104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11285 06:54:48.086963 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11287 06:54:48.088882 test VIDIOC_TRY_FMT: OK
11288 06:54:48.108479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11289 06:54:48.109345 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11291 06:54:48.115120 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11292 06:54:48.120065 test VIDIOC_S_FMT: OK
11293 06:54:48.148291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11294 06:54:48.149126 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11296 06:54:48.151882 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11297 06:54:48.170309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11298 06:54:48.171152 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11300 06:54:48.173466 test Cropping: OK (Not Supported)
11301 06:54:48.193857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11302 06:54:48.195022 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11304 06:54:48.196846 test Composing: OK (Not Supported)
11305 06:54:48.220830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11306 06:54:48.221679 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11308 06:54:48.223970 test Scaling: OK (Not Supported)
11309 06:54:48.241814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11310 06:54:48.242416
11311 06:54:48.243064 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11313 06:54:48.250765 Codec ioctls (Input 0):
11314 06:54:48.257652 <LAVA_SIGNAL_TESTSET STOP>
11315 06:54:48.258540 Received signal: <TESTSET> STOP
11316 06:54:48.258935 Closing test_set Format-ioctls-Input-0
11317 06:54:48.267072 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11318 06:54:48.267925 Received signal: <TESTSET> START Codec-ioctls-Input-0
11319 06:54:48.268325 Starting test_set Codec-ioctls-Input-0
11320 06:54:48.270005 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11321 06:54:48.293377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11322 06:54:48.294267 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11324 06:54:48.300034 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11325 06:54:48.314586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11326 06:54:48.315439 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11328 06:54:48.320541 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11329 06:54:48.338162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11330 06:54:48.338739
11331 06:54:48.339371 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11333 06:54:48.349240 Buffer ioctls (Input 0):
11334 06:54:48.355808 <LAVA_SIGNAL_TESTSET STOP>
11335 06:54:48.356635 Received signal: <TESTSET> STOP
11336 06:54:48.357032 Closing test_set Codec-ioctls-Input-0
11337 06:54:48.364754 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11338 06:54:48.365600 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11339 06:54:48.366058 Starting test_set Buffer-ioctls-Input-0
11340 06:54:48.367876 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11341 06:54:48.392583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11342 06:54:48.393534 test VIDIOC_EXPBUF: OK
11343 06:54:48.394336 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11345 06:54:48.413015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11346 06:54:48.413830 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11348 06:54:48.416102 test Requests: OK (Not Supported)
11349 06:54:48.435256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11350 06:54:48.435845
11351 06:54:48.436486 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11353 06:54:48.446060 Test input 0:
11354 06:54:48.460017
11355 06:54:48.470606 Streaming ioctls:
11356 06:54:48.478061 <LAVA_SIGNAL_TESTSET STOP>
11357 06:54:48.478891 Received signal: <TESTSET> STOP
11358 06:54:48.479294 Closing test_set Buffer-ioctls-Input-0
11359 06:54:48.486453 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11360 06:54:48.487279 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11361 06:54:48.487672 Starting test_set Streaming-ioctls_Test-input-0
11362 06:54:48.489462 test read/write: OK (Not Supported)
11363 06:54:48.514594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11364 06:54:48.515435 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11366 06:54:48.517832 test blocking wait: OK
11367 06:54:48.541715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11368 06:54:48.542683 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11370 06:54:48.551869 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11371 06:54:48.554334 test MMAP (no poll): FAIL
11372 06:54:48.574297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11373 06:54:48.575126 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11375 06:54:48.583911 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11376 06:54:48.587237 test MMAP (select): FAIL
11377 06:54:48.608010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11378 06:54:48.608853 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11380 06:54:48.617647 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11381 06:54:48.618262 test MMAP (epoll): FAIL
11382 06:54:48.652754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11383 06:54:48.653324
11384 06:54:48.654024 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11386 06:54:48.669285
11387 06:54:48.841494
11388 06:54:48.851637 test USERPTR (no poll): OK
11389 06:54:48.880234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11390 06:54:48.881004
11391 06:54:48.881660 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11393 06:54:48.893193
11394 06:54:49.073808
11395 06:54:49.080426 test USERPTR (select): OK
11396 06:54:49.107344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11397 06:54:49.108142 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11399 06:54:49.114293 test DMABUF: Cannot test, specify --expbuf-device
11400 06:54:49.119694
11401 06:54:49.135177 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11402 06:54:49.142975 <LAVA_TEST_RUNNER EXIT>
11403 06:54:49.143800 ok: lava_test_shell seems to have completed
11404 06:54:49.144211 Marking unfinished test run as failed
11406 06:54:49.149349 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11407 06:54:49.150035 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11408 06:54:49.150528 end: 3 lava-test-retry (duration 00:00:09) [common]
11409 06:54:49.151009 start: 4 finalize (timeout 00:07:56) [common]
11410 06:54:49.151506 start: 4.1 power-off (timeout 00:00:30) [common]
11411 06:54:49.152304 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11412 06:54:49.235887 >> Command sent successfully.
11413 06:54:49.240528 Returned 0 in 0 seconds
11414 06:54:49.341487 end: 4.1 power-off (duration 00:00:00) [common]
11416 06:54:49.343083 start: 4.2 read-feedback (timeout 00:07:56) [common]
11417 06:54:49.344381 Listened to connection for namespace 'common' for up to 1s
11418 06:54:50.345048 Finalising connection for namespace 'common'
11419 06:54:50.345756 Disconnecting from shell: Finalise
11420 06:54:50.346263 / #
11421 06:54:50.447248 end: 4.2 read-feedback (duration 00:00:01) [common]
11422 06:54:50.448028 end: 4 finalize (duration 00:00:01) [common]
11423 06:54:50.448625 Cleaning after the job
11424 06:54:50.449139 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/ramdisk
11425 06:54:50.471485 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/kernel
11426 06:54:50.497710 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/dtb
11427 06:54:50.498045 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694845/tftp-deploy-6d7lb4s1/modules
11428 06:54:50.505093 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694845
11429 06:54:50.560667 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694845
11430 06:54:50.560843 Job finished correctly