Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 33
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 15
1 11:09:47.977558 lava-dispatcher, installed at version: 2024.01
2 11:09:47.977760 start: 0 validate
3 11:09:47.977890 Start time: 2024-03-03 11:09:47.977882+00:00 (UTC)
4 11:09:47.978006 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:09:47.978135 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:09:48.249002 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:09:48.249699 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:09:48.511678 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:09:48.512345 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:09:48.781665 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:09:48.782384 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:09:49.057607 validate duration: 1.08
14 11:09:49.057901 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:09:49.058009 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:09:49.058097 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:09:49.058223 Not decompressing ramdisk as can be used compressed.
18 11:09:49.058306 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 11:09:49.058370 saving as /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/ramdisk/rootfs.cpio.gz
20 11:09:49.058435 total size: 34390042 (32 MB)
21 11:09:49.059457 progress 0 % (0 MB)
22 11:09:49.068333 progress 5 % (1 MB)
23 11:09:49.077012 progress 10 % (3 MB)
24 11:09:49.085954 progress 15 % (4 MB)
25 11:09:49.094682 progress 20 % (6 MB)
26 11:09:49.103519 progress 25 % (8 MB)
27 11:09:49.112288 progress 30 % (9 MB)
28 11:09:49.121375 progress 35 % (11 MB)
29 11:09:49.130242 progress 40 % (13 MB)
30 11:09:49.139222 progress 45 % (14 MB)
31 11:09:49.148176 progress 50 % (16 MB)
32 11:09:49.157447 progress 55 % (18 MB)
33 11:09:49.166241 progress 60 % (19 MB)
34 11:09:49.175126 progress 65 % (21 MB)
35 11:09:49.183803 progress 70 % (22 MB)
36 11:09:49.192728 progress 75 % (24 MB)
37 11:09:49.201405 progress 80 % (26 MB)
38 11:09:49.210286 progress 85 % (27 MB)
39 11:09:49.218949 progress 90 % (29 MB)
40 11:09:49.227734 progress 95 % (31 MB)
41 11:09:49.236406 progress 100 % (32 MB)
42 11:09:49.236585 32 MB downloaded in 0.18 s (184.10 MB/s)
43 11:09:49.236742 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:09:49.237018 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:09:49.237104 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:09:49.237188 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:09:49.237323 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:09:49.237392 saving as /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/kernel/Image
50 11:09:49.237452 total size: 51599872 (49 MB)
51 11:09:49.237549 No compression specified
52 11:09:49.238650 progress 0 % (0 MB)
53 11:09:49.252203 progress 5 % (2 MB)
54 11:09:49.265760 progress 10 % (4 MB)
55 11:09:49.279454 progress 15 % (7 MB)
56 11:09:49.292758 progress 20 % (9 MB)
57 11:09:49.306027 progress 25 % (12 MB)
58 11:09:49.319260 progress 30 % (14 MB)
59 11:09:49.332626 progress 35 % (17 MB)
60 11:09:49.345896 progress 40 % (19 MB)
61 11:09:49.359405 progress 45 % (22 MB)
62 11:09:49.372866 progress 50 % (24 MB)
63 11:09:49.386615 progress 55 % (27 MB)
64 11:09:49.400086 progress 60 % (29 MB)
65 11:09:49.414426 progress 65 % (32 MB)
66 11:09:49.427687 progress 70 % (34 MB)
67 11:09:49.440889 progress 75 % (36 MB)
68 11:09:49.454013 progress 80 % (39 MB)
69 11:09:49.467193 progress 85 % (41 MB)
70 11:09:49.480538 progress 90 % (44 MB)
71 11:09:49.493760 progress 95 % (46 MB)
72 11:09:49.506796 progress 100 % (49 MB)
73 11:09:49.507016 49 MB downloaded in 0.27 s (182.56 MB/s)
74 11:09:49.507164 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:09:49.507435 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:09:49.507560 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:09:49.507650 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:09:49.507790 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:09:49.507859 saving as /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/dtb/mt8192-asurada-spherion-r0.dtb
81 11:09:49.507920 total size: 47278 (0 MB)
82 11:09:49.507982 No compression specified
83 11:09:49.509105 progress 69 % (0 MB)
84 11:09:49.509380 progress 100 % (0 MB)
85 11:09:49.509596 0 MB downloaded in 0.00 s (26.95 MB/s)
86 11:09:49.509719 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:09:49.509942 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:09:49.510026 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:09:49.510107 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:09:49.510218 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:09:49.510286 saving as /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/modules/modules.tar
93 11:09:49.510347 total size: 8628476 (8 MB)
94 11:09:49.510407 Using unxz to decompress xz
95 11:09:49.514562 progress 0 % (0 MB)
96 11:09:49.535546 progress 5 % (0 MB)
97 11:09:49.559699 progress 10 % (0 MB)
98 11:09:49.584166 progress 15 % (1 MB)
99 11:09:49.606546 progress 20 % (1 MB)
100 11:09:49.630456 progress 25 % (2 MB)
101 11:09:49.654483 progress 30 % (2 MB)
102 11:09:49.682408 progress 35 % (2 MB)
103 11:09:49.707131 progress 40 % (3 MB)
104 11:09:49.730928 progress 45 % (3 MB)
105 11:09:49.755478 progress 50 % (4 MB)
106 11:09:49.779796 progress 55 % (4 MB)
107 11:09:49.802677 progress 60 % (4 MB)
108 11:09:49.828225 progress 65 % (5 MB)
109 11:09:49.852748 progress 70 % (5 MB)
110 11:09:49.877723 progress 75 % (6 MB)
111 11:09:49.903700 progress 80 % (6 MB)
112 11:09:49.928010 progress 85 % (7 MB)
113 11:09:49.952546 progress 90 % (7 MB)
114 11:09:49.982523 progress 95 % (7 MB)
115 11:09:50.011160 progress 100 % (8 MB)
116 11:09:50.016119 8 MB downloaded in 0.51 s (16.27 MB/s)
117 11:09:50.016364 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:09:50.016619 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:09:50.016711 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:09:50.016808 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:09:50.016887 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:09:50.016977 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:09:50.017201 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0
125 11:09:50.017339 makedir: /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin
126 11:09:50.017444 makedir: /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/tests
127 11:09:50.017591 makedir: /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/results
128 11:09:50.017707 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-add-keys
129 11:09:50.017908 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-add-sources
130 11:09:50.018072 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-background-process-start
131 11:09:50.018205 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-background-process-stop
132 11:09:50.018330 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-common-functions
133 11:09:50.018454 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-echo-ipv4
134 11:09:50.018579 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-install-packages
135 11:09:50.018705 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-installed-packages
136 11:09:50.018830 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-os-build
137 11:09:50.018954 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-probe-channel
138 11:09:50.019078 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-probe-ip
139 11:09:50.019201 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-target-ip
140 11:09:50.019323 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-target-mac
141 11:09:50.019446 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-target-storage
142 11:09:50.019574 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-test-case
143 11:09:50.019701 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-test-event
144 11:09:50.019825 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-test-feedback
145 11:09:50.019949 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-test-raise
146 11:09:50.020076 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-test-reference
147 11:09:50.020199 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-test-runner
148 11:09:50.020322 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-test-set
149 11:09:50.020448 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-test-shell
150 11:09:50.020575 Updating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-install-packages (oe)
151 11:09:50.020727 Updating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/bin/lava-installed-packages (oe)
152 11:09:50.020851 Creating /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/environment
153 11:09:50.020952 LAVA metadata
154 11:09:50.021030 - LAVA_JOB_ID=12925679
155 11:09:50.021094 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:09:50.021196 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:09:50.021261 skipped lava-vland-overlay
158 11:09:50.021334 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:09:50.021429 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:09:50.021542 skipped lava-multinode-overlay
161 11:09:50.021622 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:09:50.021727 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:09:50.021819 Loading test definitions
164 11:09:50.021921 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:09:50.022075 Using /lava-12925679 at stage 0
166 11:09:50.022407 uuid=12925679_1.5.2.3.1 testdef=None
167 11:09:50.022495 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:09:50.022577 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:09:50.023086 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:09:50.023343 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:09:50.024042 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:09:50.024266 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:09:50.024859 runner path: /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/0/tests/0_cros-ec test_uuid 12925679_1.5.2.3.1
176 11:09:50.025017 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:09:50.025216 Creating lava-test-runner.conf files
179 11:09:50.025278 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925679/lava-overlay-jxqstmy0/lava-12925679/0 for stage 0
180 11:09:50.025367 - 0_cros-ec
181 11:09:50.025465 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:09:50.025609 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:09:50.032879 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:09:50.032982 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:09:50.033067 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:09:50.033150 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:09:50.033235 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:09:51.018678 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:09:51.019128 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:09:51.019278 extracting modules file /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925679/extract-overlay-ramdisk-aflh2fo2/ramdisk
191 11:09:51.268534 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:09:51.268712 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:09:51.268814 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925679/compress-overlay-em_vywwq/overlay-1.5.2.4.tar.gz to ramdisk
194 11:09:51.268888 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925679/compress-overlay-em_vywwq/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925679/extract-overlay-ramdisk-aflh2fo2/ramdisk
195 11:09:51.275574 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:09:51.275685 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:09:51.275776 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:09:51.275865 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:09:51.275943 Building ramdisk /var/lib/lava/dispatcher/tmp/12925679/extract-overlay-ramdisk-aflh2fo2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925679/extract-overlay-ramdisk-aflh2fo2/ramdisk
200 11:09:51.976396 >> 271118 blocks
201 11:09:56.732813 rename /var/lib/lava/dispatcher/tmp/12925679/extract-overlay-ramdisk-aflh2fo2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/ramdisk/ramdisk.cpio.gz
202 11:09:56.733279 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:09:56.733407 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 11:09:56.733549 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 11:09:56.733670 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/kernel/Image'
206 11:10:09.195064 Returned 0 in 12 seconds
207 11:10:09.295706 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/kernel/image.itb
208 11:10:10.098516 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:10:10.098913 output: Created: Sun Mar 3 11:10:09 2024
210 11:10:10.098990 output: Image 0 (kernel-1)
211 11:10:10.099057 output: Description:
212 11:10:10.099121 output: Created: Sun Mar 3 11:10:09 2024
213 11:10:10.099181 output: Type: Kernel Image
214 11:10:10.099243 output: Compression: lzma compressed
215 11:10:10.099303 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
216 11:10:10.099358 output: Architecture: AArch64
217 11:10:10.099412 output: OS: Linux
218 11:10:10.099465 output: Load Address: 0x00000000
219 11:10:10.099521 output: Entry Point: 0x00000000
220 11:10:10.099574 output: Hash algo: crc32
221 11:10:10.099631 output: Hash value: cf43f4f3
222 11:10:10.099686 output: Image 1 (fdt-1)
223 11:10:10.099744 output: Description: mt8192-asurada-spherion-r0
224 11:10:10.099798 output: Created: Sun Mar 3 11:10:09 2024
225 11:10:10.099851 output: Type: Flat Device Tree
226 11:10:10.099903 output: Compression: uncompressed
227 11:10:10.099956 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:10:10.100009 output: Architecture: AArch64
229 11:10:10.100061 output: Hash algo: crc32
230 11:10:10.100114 output: Hash value: cc4352de
231 11:10:10.100166 output: Image 2 (ramdisk-1)
232 11:10:10.100219 output: Description: unavailable
233 11:10:10.100272 output: Created: Sun Mar 3 11:10:09 2024
234 11:10:10.100324 output: Type: RAMDisk Image
235 11:10:10.100377 output: Compression: Unknown Compression
236 11:10:10.100429 output: Data Size: 47529709 Bytes = 46415.73 KiB = 45.33 MiB
237 11:10:10.100482 output: Architecture: AArch64
238 11:10:10.100534 output: OS: Linux
239 11:10:10.100586 output: Load Address: unavailable
240 11:10:10.100638 output: Entry Point: unavailable
241 11:10:10.100690 output: Hash algo: crc32
242 11:10:10.100742 output: Hash value: b2358cd6
243 11:10:10.100794 output: Default Configuration: 'conf-1'
244 11:10:10.100846 output: Configuration 0 (conf-1)
245 11:10:10.100898 output: Description: mt8192-asurada-spherion-r0
246 11:10:10.100950 output: Kernel: kernel-1
247 11:10:10.101002 output: Init Ramdisk: ramdisk-1
248 11:10:10.101054 output: FDT: fdt-1
249 11:10:10.101106 output: Loadables: kernel-1
250 11:10:10.101158 output:
251 11:10:10.101365 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 11:10:10.101465 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 11:10:10.101613 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 11:10:10.101714 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 11:10:10.101796 No LXC device requested
256 11:10:10.101876 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:10:10.101963 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 11:10:10.102040 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:10:10.102109 Checking files for TFTP limit of 4294967296 bytes.
260 11:10:10.102603 end: 1 tftp-deploy (duration 00:00:21) [common]
261 11:10:10.102709 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:10:10.102806 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:10:10.102934 substitutions:
264 11:10:10.103001 - {DTB}: 12925679/tftp-deploy-y7s_h0a2/dtb/mt8192-asurada-spherion-r0.dtb
265 11:10:10.103065 - {INITRD}: 12925679/tftp-deploy-y7s_h0a2/ramdisk/ramdisk.cpio.gz
266 11:10:10.103125 - {KERNEL}: 12925679/tftp-deploy-y7s_h0a2/kernel/Image
267 11:10:10.103181 - {LAVA_MAC}: None
268 11:10:10.103237 - {PRESEED_CONFIG}: None
269 11:10:10.103292 - {PRESEED_LOCAL}: None
270 11:10:10.103346 - {RAMDISK}: 12925679/tftp-deploy-y7s_h0a2/ramdisk/ramdisk.cpio.gz
271 11:10:10.103401 - {ROOT_PART}: None
272 11:10:10.103454 - {ROOT}: None
273 11:10:10.103508 - {SERVER_IP}: 192.168.201.1
274 11:10:10.103562 - {TEE}: None
275 11:10:10.103618 Parsed boot commands:
276 11:10:10.103671 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:10:10.103849 Parsed boot commands: tftpboot 192.168.201.1 12925679/tftp-deploy-y7s_h0a2/kernel/image.itb 12925679/tftp-deploy-y7s_h0a2/kernel/cmdline
278 11:10:10.103939 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:10:10.104029 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:10:10.104120 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:10:10.104205 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:10:10.104276 Not connected, no need to disconnect.
283 11:10:10.104350 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:10:10.104428 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:10:10.104496 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 11:10:10.108539 Setting prompt string to ['lava-test: # ']
287 11:10:10.108905 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:10:10.109015 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:10:10.109114 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:10:10.109205 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:10:10.109427 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 11:10:15.243745 >> Command sent successfully.
293 11:10:15.250926 Returned 0 in 5 seconds
294 11:10:15.351859 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:10:15.352180 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:10:15.352285 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:10:15.352373 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:10:15.352445 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:10:15.352514 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:10:15.352794 [Enter `^Ec?' for help]
302 11:10:15.520284
303 11:10:15.520518
304 11:10:15.520659 F0: 102B 0000
305 11:10:15.520789
306 11:10:15.520903 F3: 1001 0000 [0200]
307 11:10:15.521019
308 11:10:15.523809 F3: 1001 0000
309 11:10:15.523963
310 11:10:15.524082 F7: 102D 0000
311 11:10:15.524194
312 11:10:15.524301 F1: 0000 0000
313 11:10:15.527407
314 11:10:15.527825 V0: 0000 0000 [0001]
315 11:10:15.528172
316 11:10:15.528482 00: 0007 8000
317 11:10:15.528797
318 11:10:15.531047 01: 0000 0000
319 11:10:15.531491
320 11:10:15.531828 BP: 0C00 0209 [0000]
321 11:10:15.532143
322 11:10:15.534582 G0: 1182 0000
323 11:10:15.535069
324 11:10:15.535410 EC: 0000 0021 [4000]
325 11:10:15.535777
326 11:10:15.538193 S7: 0000 0000 [0000]
327 11:10:15.538774
328 11:10:15.539138 CC: 0000 0000 [0001]
329 11:10:15.539461
330 11:10:15.541471 T0: 0000 0040 [010F]
331 11:10:15.541944
332 11:10:15.542279 Jump to BL
333 11:10:15.542605
334 11:10:15.567095
335 11:10:15.567509
336 11:10:15.567871
337 11:10:15.574153 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:10:15.577985 ARM64: Exception handlers installed.
339 11:10:15.581219 ARM64: Testing exception
340 11:10:15.585281 ARM64: Done test exception
341 11:10:15.592433 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:10:15.599548 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:10:15.607177 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:10:15.617613 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:10:15.624242 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:10:15.634370 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:10:15.645041 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:10:15.651422 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:10:15.669790 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:10:15.672835 WDT: Last reset was cold boot
351 11:10:15.676433 SPI1(PAD0) initialized at 2873684 Hz
352 11:10:15.679614 SPI5(PAD0) initialized at 992727 Hz
353 11:10:15.682847 VBOOT: Loading verstage.
354 11:10:15.689412 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:10:15.693123 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:10:15.696057 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:10:15.699425 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:10:15.707052 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:10:15.713561 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:10:15.724501 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 11:10:15.724614
362 11:10:15.724711
363 11:10:15.734419 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:10:15.737683 ARM64: Exception handlers installed.
365 11:10:15.741296 ARM64: Testing exception
366 11:10:15.741426 ARM64: Done test exception
367 11:10:15.747837 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:10:15.751138 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:10:15.765563 Probing TPM: . done!
370 11:10:15.765675 TPM ready after 0 ms
371 11:10:15.772343 Connected to device vid:did:rid of 1ae0:0028:00
372 11:10:15.779461 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 11:10:15.819503 Initialized TPM device CR50 revision 0
374 11:10:15.831202 tlcl_send_startup: Startup return code is 0
375 11:10:15.831341 TPM: setup succeeded
376 11:10:15.842841 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:10:15.851363 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:10:15.863714 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:10:15.872335 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:10:15.875641 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:10:15.879540 in-header: 03 07 00 00 08 00 00 00
382 11:10:15.883003 in-data: aa e4 47 04 13 02 00 00
383 11:10:15.886218 Chrome EC: UHEPI supported
384 11:10:15.892967 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:10:15.896961 in-header: 03 9d 00 00 08 00 00 00
386 11:10:15.900517 in-data: 10 20 20 08 00 00 00 00
387 11:10:15.900722 Phase 1
388 11:10:15.907736 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:10:15.911630 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:10:15.919258 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:10:15.919342 Recovery requested (1009000e)
392 11:10:15.927534 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:10:15.933652 tlcl_extend: response is 0
394 11:10:15.944179 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:10:15.947421 tlcl_extend: response is 0
396 11:10:15.953872 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:10:15.974918 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 11:10:15.982344 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:10:15.982767
400 11:10:15.983108
401 11:10:15.989501 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:10:15.993308 ARM64: Exception handlers installed.
403 11:10:15.997002 ARM64: Testing exception
404 11:10:16.000147 ARM64: Done test exception
405 11:10:16.019681 pmic_efuse_setting: Set efuses in 11 msecs
406 11:10:16.023402 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:10:16.027118 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:10:16.033648 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:10:16.037110 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:10:16.044407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:10:16.048211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:10:16.051831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:10:16.059506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:10:16.063208 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:10:16.066677 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:10:16.073155 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:10:16.076744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:10:16.080021 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:10:16.086732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:10:16.093382 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:10:16.096354 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:10:16.103298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:10:16.109809 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:10:16.113185 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:10:16.120089 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:10:16.127572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:10:16.131255 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:10:16.138367 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:10:16.141465 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:10:16.148659 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:10:16.152577 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:10:16.159344 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:10:16.162302 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:10:16.168980 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:10:16.172246 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:10:16.179149 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:10:16.183078 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:10:16.190185 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:10:16.194143 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:10:16.197911 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:10:16.201722 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:10:16.209163 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:10:16.212923 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:10:16.219758 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:10:16.222867 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:10:16.226128 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:10:16.233165 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:10:16.236601 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:10:16.239994 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:10:16.242965 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:10:16.249611 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:10:16.253021 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:10:16.256109 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:10:16.263037 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:10:16.266407 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:10:16.269422 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:10:16.273076 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:10:16.283029 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:10:16.289443 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:10:16.296156 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:10:16.302548 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:10:16.312451 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:10:16.316180 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:10:16.319074 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:10:16.325764 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:10:16.332551 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 11:10:16.339336 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:10:16.343204 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 11:10:16.346253 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:10:16.357158 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 11:10:16.360181 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 11:10:16.367001 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 11:10:16.370163 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 11:10:16.373137 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 11:10:16.376334 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 11:10:16.379807 ADC[4]: Raw value=898150 ID=7
477 11:10:16.383148 ADC[3]: Raw value=213440 ID=1
478 11:10:16.386454 RAM Code: 0x71
479 11:10:16.389908 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 11:10:16.393281 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 11:10:16.403987 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 11:10:16.411097 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 11:10:16.414621 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 11:10:16.424046 in-header: 03 07 00 00 08 00 00 00
485 11:10:16.427998 in-data: aa e4 47 04 13 02 00 00
486 11:10:16.431386 Chrome EC: UHEPI supported
487 11:10:16.438984 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 11:10:16.442421 in-header: 03 15 00 00 08 00 00 00
489 11:10:16.445821 in-data: 98 20 20 08 00 00 00 00
490 11:10:16.449805 MRC: failed to locate region type 0.
491 11:10:16.453601 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 11:10:16.457273 DRAM-K: Running full calibration
493 11:10:16.464173 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 11:10:16.464260 header.status = 0x0
495 11:10:16.467992 header.version = 0x6 (expected: 0x6)
496 11:10:16.471490 header.size = 0xd00 (expected: 0xd00)
497 11:10:16.475661 header.flags = 0x0
498 11:10:16.479194 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 11:10:16.498302 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 11:10:16.506109 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 11:10:16.506764 dram_init: ddr_geometry: 2
502 11:10:16.509714 [EMI] MDL number = 2
503 11:10:16.513261 [EMI] Get MDL freq = 0
504 11:10:16.513995 dram_init: ddr_type: 0
505 11:10:16.517365 is_discrete_lpddr4: 1
506 11:10:16.520556 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 11:10:16.521087
508 11:10:16.521645
509 11:10:16.522078 [Bian_co] ETT version 0.0.0.1
510 11:10:16.528792 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 11:10:16.529381
512 11:10:16.532645 dramc_set_vcore_voltage set vcore to 650000
513 11:10:16.533063 Read voltage for 800, 4
514 11:10:16.533392 Vio18 = 0
515 11:10:16.536012 Vcore = 650000
516 11:10:16.536534 Vdram = 0
517 11:10:16.536867 Vddq = 0
518 11:10:16.539144 Vmddr = 0
519 11:10:16.539561 dram_init: config_dvfs: 1
520 11:10:16.545592 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 11:10:16.549344 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 11:10:16.552267 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 11:10:16.559120 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 11:10:16.562121 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 11:10:16.565767 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 11:10:16.569036 MEM_TYPE=3, freq_sel=18
527 11:10:16.572190 sv_algorithm_assistance_LP4_1600
528 11:10:16.575303 ============ PULL DRAM RESETB DOWN ============
529 11:10:16.578654 ========== PULL DRAM RESETB DOWN end =========
530 11:10:16.581968 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 11:10:16.585602 ===================================
532 11:10:16.588911 LPDDR4 DRAM CONFIGURATION
533 11:10:16.592508 ===================================
534 11:10:16.595314 EX_ROW_EN[0] = 0x0
535 11:10:16.595755 EX_ROW_EN[1] = 0x0
536 11:10:16.598923 LP4Y_EN = 0x0
537 11:10:16.599147 WORK_FSP = 0x0
538 11:10:16.602163 WL = 0x2
539 11:10:16.602410 RL = 0x2
540 11:10:16.605282 BL = 0x2
541 11:10:16.605598 RPST = 0x0
542 11:10:16.609065 RD_PRE = 0x0
543 11:10:16.609316 WR_PRE = 0x1
544 11:10:16.612153 WR_PST = 0x0
545 11:10:16.612391 DBI_WR = 0x0
546 11:10:16.615650 DBI_RD = 0x0
547 11:10:16.615813 OTF = 0x1
548 11:10:16.619015 ===================================
549 11:10:16.621991 ===================================
550 11:10:16.625453 ANA top config
551 11:10:16.628945 ===================================
552 11:10:16.632431 DLL_ASYNC_EN = 0
553 11:10:16.632670 ALL_SLAVE_EN = 1
554 11:10:16.635748 NEW_RANK_MODE = 1
555 11:10:16.639121 DLL_IDLE_MODE = 1
556 11:10:16.642147 LP45_APHY_COMB_EN = 1
557 11:10:16.642374 TX_ODT_DIS = 1
558 11:10:16.646067 NEW_8X_MODE = 1
559 11:10:16.649188 ===================================
560 11:10:16.652634 ===================================
561 11:10:16.656081 data_rate = 1600
562 11:10:16.659211 CKR = 1
563 11:10:16.662746 DQ_P2S_RATIO = 8
564 11:10:16.665609 ===================================
565 11:10:16.669202 CA_P2S_RATIO = 8
566 11:10:16.669596 DQ_CA_OPEN = 0
567 11:10:16.672386 DQ_SEMI_OPEN = 0
568 11:10:16.676139 CA_SEMI_OPEN = 0
569 11:10:16.679302 CA_FULL_RATE = 0
570 11:10:16.682173 DQ_CKDIV4_EN = 1
571 11:10:16.685864 CA_CKDIV4_EN = 1
572 11:10:16.686452 CA_PREDIV_EN = 0
573 11:10:16.688968 PH8_DLY = 0
574 11:10:16.692492 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 11:10:16.695906 DQ_AAMCK_DIV = 4
576 11:10:16.698843 CA_AAMCK_DIV = 4
577 11:10:16.702333 CA_ADMCK_DIV = 4
578 11:10:16.702854 DQ_TRACK_CA_EN = 0
579 11:10:16.705663 CA_PICK = 800
580 11:10:16.708820 CA_MCKIO = 800
581 11:10:16.712703 MCKIO_SEMI = 0
582 11:10:16.715785 PLL_FREQ = 3068
583 11:10:16.718840 DQ_UI_PI_RATIO = 32
584 11:10:16.722191 CA_UI_PI_RATIO = 0
585 11:10:16.725736 ===================================
586 11:10:16.729076 ===================================
587 11:10:16.729631 memory_type:LPDDR4
588 11:10:16.732142 GP_NUM : 10
589 11:10:16.732564 SRAM_EN : 1
590 11:10:16.735900 MD32_EN : 0
591 11:10:16.738975 ===================================
592 11:10:16.742542 [ANA_INIT] >>>>>>>>>>>>>>
593 11:10:16.745760 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 11:10:16.749289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 11:10:16.752354 ===================================
596 11:10:16.755922 data_rate = 1600,PCW = 0X7600
597 11:10:16.756453 ===================================
598 11:10:16.762411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 11:10:16.765958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 11:10:16.772769 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 11:10:16.776544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 11:10:16.779344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 11:10:16.783096 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 11:10:16.786811 [ANA_INIT] flow start
605 11:10:16.787233 [ANA_INIT] PLL >>>>>>>>
606 11:10:16.790410 [ANA_INIT] PLL <<<<<<<<
607 11:10:16.791010 [ANA_INIT] MIDPI >>>>>>>>
608 11:10:16.794153 [ANA_INIT] MIDPI <<<<<<<<
609 11:10:16.797586 [ANA_INIT] DLL >>>>>>>>
610 11:10:16.798010 [ANA_INIT] flow end
611 11:10:16.801355 ============ LP4 DIFF to SE enter ============
612 11:10:16.805442 ============ LP4 DIFF to SE exit ============
613 11:10:16.808818 [ANA_INIT] <<<<<<<<<<<<<
614 11:10:16.812269 [Flow] Enable top DCM control >>>>>
615 11:10:16.815886 [Flow] Enable top DCM control <<<<<
616 11:10:16.819162 Enable DLL master slave shuffle
617 11:10:16.822852 ==============================================================
618 11:10:16.826140 Gating Mode config
619 11:10:16.832694 ==============================================================
620 11:10:16.833265 Config description:
621 11:10:16.843895 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 11:10:16.851383 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 11:10:16.855081 SELPH_MODE 0: By rank 1: By Phase
624 11:10:16.858541 ==============================================================
625 11:10:16.861995 GAT_TRACK_EN = 1
626 11:10:16.865880 RX_GATING_MODE = 2
627 11:10:16.869250 RX_GATING_TRACK_MODE = 2
628 11:10:16.873146 SELPH_MODE = 1
629 11:10:16.873344 PICG_EARLY_EN = 1
630 11:10:16.877125 VALID_LAT_VALUE = 1
631 11:10:16.884455 ==============================================================
632 11:10:16.888144 Enter into Gating configuration >>>>
633 11:10:16.892078 Exit from Gating configuration <<<<
634 11:10:16.892221 Enter into DVFS_PRE_config >>>>>
635 11:10:16.902857 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 11:10:16.906648 Exit from DVFS_PRE_config <<<<<
637 11:10:16.910382 Enter into PICG configuration >>>>
638 11:10:16.914320 Exit from PICG configuration <<<<
639 11:10:16.917827 [RX_INPUT] configuration >>>>>
640 11:10:16.917941 [RX_INPUT] configuration <<<<<
641 11:10:16.925153 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 11:10:16.928680 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 11:10:16.936245 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 11:10:16.943558 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 11:10:16.947195 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 11:10:16.954892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 11:10:16.958649 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 11:10:16.962285 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 11:10:16.965949 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 11:10:16.969971 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 11:10:16.973719 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 11:10:16.980898 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 11:10:16.984865 ===================================
654 11:10:16.985423 LPDDR4 DRAM CONFIGURATION
655 11:10:16.988329 ===================================
656 11:10:16.992259 EX_ROW_EN[0] = 0x0
657 11:10:16.992693 EX_ROW_EN[1] = 0x0
658 11:10:16.996085 LP4Y_EN = 0x0
659 11:10:16.996627 WORK_FSP = 0x0
660 11:10:16.999774 WL = 0x2
661 11:10:17.000231 RL = 0x2
662 11:10:17.000593 BL = 0x2
663 11:10:17.003299 RPST = 0x0
664 11:10:17.003718 RD_PRE = 0x0
665 11:10:17.006732 WR_PRE = 0x1
666 11:10:17.007156 WR_PST = 0x0
667 11:10:17.010506 DBI_WR = 0x0
668 11:10:17.010928 DBI_RD = 0x0
669 11:10:17.014452 OTF = 0x1
670 11:10:17.017932 ===================================
671 11:10:17.022045 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 11:10:17.025728 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 11:10:17.029469 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 11:10:17.033305 ===================================
675 11:10:17.033760 LPDDR4 DRAM CONFIGURATION
676 11:10:17.036838 ===================================
677 11:10:17.040771 EX_ROW_EN[0] = 0x10
678 11:10:17.041191 EX_ROW_EN[1] = 0x0
679 11:10:17.044574 LP4Y_EN = 0x0
680 11:10:17.045087 WORK_FSP = 0x0
681 11:10:17.047949 WL = 0x2
682 11:10:17.048569 RL = 0x2
683 11:10:17.051230 BL = 0x2
684 11:10:17.051675 RPST = 0x0
685 11:10:17.055409 RD_PRE = 0x0
686 11:10:17.055827 WR_PRE = 0x1
687 11:10:17.058627 WR_PST = 0x0
688 11:10:17.059045 DBI_WR = 0x0
689 11:10:17.062202 DBI_RD = 0x0
690 11:10:17.062784 OTF = 0x1
691 11:10:17.065957 ===================================
692 11:10:17.073166 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 11:10:17.076871 nWR fixed to 40
694 11:10:17.077460 [ModeRegInit_LP4] CH0 RK0
695 11:10:17.080615 [ModeRegInit_LP4] CH0 RK1
696 11:10:17.084473 [ModeRegInit_LP4] CH1 RK0
697 11:10:17.084901 [ModeRegInit_LP4] CH1 RK1
698 11:10:17.087908 match AC timing 13
699 11:10:17.091434 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 11:10:17.095405 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 11:10:17.099298 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 11:10:17.106589 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 11:10:17.110041 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 11:10:17.110468 [EMI DOE] emi_dcm 0
705 11:10:17.114076 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 11:10:17.114382 ==
707 11:10:17.117264 Dram Type= 6, Freq= 0, CH_0, rank 0
708 11:10:17.121190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 11:10:17.124603 ==
710 11:10:17.128423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 11:10:17.135215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 11:10:17.143136 [CA 0] Center 38 (7~69) winsize 63
713 11:10:17.146339 [CA 1] Center 37 (7~68) winsize 62
714 11:10:17.149710 [CA 2] Center 35 (5~66) winsize 62
715 11:10:17.153013 [CA 3] Center 35 (5~66) winsize 62
716 11:10:17.156530 [CA 4] Center 34 (4~65) winsize 62
717 11:10:17.159743 [CA 5] Center 34 (3~65) winsize 63
718 11:10:17.159875
719 11:10:17.163001 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 11:10:17.163133
721 11:10:17.166165 [CATrainingPosCal] consider 1 rank data
722 11:10:17.169562 u2DelayCellTimex100 = 270/100 ps
723 11:10:17.172971 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 11:10:17.176589 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 11:10:17.183133 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 11:10:17.186605 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 11:10:17.189769 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 11:10:17.193189 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
729 11:10:17.193362
730 11:10:17.196708 CA PerBit enable=1, Macro0, CA PI delay=34
731 11:10:17.196848
732 11:10:17.199708 [CBTSetCACLKResult] CA Dly = 34
733 11:10:17.199839 CS Dly: 6 (0~37)
734 11:10:17.199942 ==
735 11:10:17.203270 Dram Type= 6, Freq= 0, CH_0, rank 1
736 11:10:17.209725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 11:10:17.209858 ==
738 11:10:17.213210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 11:10:17.219619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 11:10:17.229526 [CA 0] Center 38 (7~69) winsize 63
741 11:10:17.233224 [CA 1] Center 37 (7~68) winsize 62
742 11:10:17.236240 [CA 2] Center 35 (5~66) winsize 62
743 11:10:17.239382 [CA 3] Center 35 (5~66) winsize 62
744 11:10:17.242617 [CA 4] Center 34 (4~65) winsize 62
745 11:10:17.246040 [CA 5] Center 34 (4~65) winsize 62
746 11:10:17.246171
747 11:10:17.249506 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 11:10:17.249638
749 11:10:17.252636 [CATrainingPosCal] consider 2 rank data
750 11:10:17.256663 u2DelayCellTimex100 = 270/100 ps
751 11:10:17.259753 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 11:10:17.262838 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 11:10:17.269838 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 11:10:17.273231 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 11:10:17.276196 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 11:10:17.279582 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 11:10:17.279715
758 11:10:17.282701 CA PerBit enable=1, Macro0, CA PI delay=34
759 11:10:17.282834
760 11:10:17.286292 [CBTSetCACLKResult] CA Dly = 34
761 11:10:17.286425 CS Dly: 6 (0~37)
762 11:10:17.286529
763 11:10:17.289297 ----->DramcWriteLeveling(PI) begin...
764 11:10:17.292576 ==
765 11:10:17.296225 Dram Type= 6, Freq= 0, CH_0, rank 0
766 11:10:17.299434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 11:10:17.299568 ==
768 11:10:17.302636 Write leveling (Byte 0): 31 => 31
769 11:10:17.305979 Write leveling (Byte 1): 31 => 31
770 11:10:17.309442 DramcWriteLeveling(PI) end<-----
771 11:10:17.309648
772 11:10:17.309799 ==
773 11:10:17.312833 Dram Type= 6, Freq= 0, CH_0, rank 0
774 11:10:17.315959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 11:10:17.316081 ==
776 11:10:17.319157 [Gating] SW mode calibration
777 11:10:17.325850 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 11:10:17.329329 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 11:10:17.335808 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 11:10:17.339171 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 11:10:17.342719 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 11:10:17.349454 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 11:10:17.352826 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 11:10:17.356033 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 11:10:17.363366 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 11:10:17.366810 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 11:10:17.370588 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 11:10:17.374324 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:10:17.377627 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:10:17.384331 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:10:17.388265 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:10:17.392038 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:10:17.395040 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:10:17.401938 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:10:17.405488 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:10:17.408957 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:10:17.415818 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
798 11:10:17.418951 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
799 11:10:17.422198 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:10:17.429082 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:10:17.432423 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:10:17.435680 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:10:17.442602 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:10:17.446105 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:10:17.449509 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:10:17.456050 0 9 12 | B1->B0 | 2525 3131 | 1 0 | (1 1) (0 0)
807 11:10:17.459444 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 11:10:17.462723 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 11:10:17.466316 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 11:10:17.473160 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 11:10:17.476326 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 11:10:17.479726 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 11:10:17.486182 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
814 11:10:17.489534 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
815 11:10:17.492540 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:10:17.499270 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:10:17.502331 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:10:17.506356 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 11:10:17.512547 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 11:10:17.515984 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 11:10:17.519446 0 11 8 | B1->B0 | 2626 3030 | 0 0 | (0 0) (0 0)
822 11:10:17.526093 0 11 12 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
823 11:10:17.529322 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 11:10:17.532447 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 11:10:17.539559 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 11:10:17.542780 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 11:10:17.546085 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 11:10:17.552690 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 11:10:17.556166 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
830 11:10:17.559593 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 11:10:17.562931 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 11:10:17.569290 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 11:10:17.572845 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 11:10:17.575896 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 11:10:17.582671 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 11:10:17.585804 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 11:10:17.589640 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:10:17.595801 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:10:17.599313 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:10:17.602561 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:10:17.609052 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:10:17.612841 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:10:17.616236 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:10:17.622448 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:10:17.625666 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 11:10:17.629251 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 11:10:17.632451 Total UI for P1: 0, mck2ui 16
848 11:10:17.635983 best dqsien dly found for B0: ( 0, 14, 8)
849 11:10:17.642676 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 11:10:17.643211 Total UI for P1: 0, mck2ui 16
851 11:10:17.645993 best dqsien dly found for B1: ( 0, 14, 12)
852 11:10:17.652524 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
853 11:10:17.655838 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 11:10:17.656367
855 11:10:17.659348 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 11:10:17.662556 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 11:10:17.666142 [Gating] SW calibration Done
858 11:10:17.666678 ==
859 11:10:17.669259 Dram Type= 6, Freq= 0, CH_0, rank 0
860 11:10:17.672664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 11:10:17.673200 ==
862 11:10:17.676321 RX Vref Scan: 0
863 11:10:17.676853
864 11:10:17.677195 RX Vref 0 -> 0, step: 1
865 11:10:17.677548
866 11:10:17.678961 RX Delay -130 -> 252, step: 16
867 11:10:17.682462 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 11:10:17.689224 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 11:10:17.692603 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 11:10:17.695650 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
871 11:10:17.699132 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 11:10:17.702944 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 11:10:17.706047 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 11:10:17.712445 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 11:10:17.716349 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 11:10:17.719377 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 11:10:17.722589 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 11:10:17.726141 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 11:10:17.732681 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 11:10:17.735530 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 11:10:17.738616 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 11:10:17.742406 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 11:10:17.742986 ==
884 11:10:17.745125 Dram Type= 6, Freq= 0, CH_0, rank 0
885 11:10:17.751948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 11:10:17.752041 ==
887 11:10:17.752108 DQS Delay:
888 11:10:17.754930 DQS0 = 0, DQS1 = 0
889 11:10:17.755012 DQM Delay:
890 11:10:17.755079 DQM0 = 80, DQM1 = 69
891 11:10:17.758628 DQ Delay:
892 11:10:17.762582 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
893 11:10:17.765822 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 11:10:17.769619 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 11:10:17.770047 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 11:10:17.770391
897 11:10:17.772860
898 11:10:17.773290 ==
899 11:10:17.776196 Dram Type= 6, Freq= 0, CH_0, rank 0
900 11:10:17.779568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 11:10:17.779997 ==
902 11:10:17.780334
903 11:10:17.780644
904 11:10:17.783107 TX Vref Scan disable
905 11:10:17.783628 == TX Byte 0 ==
906 11:10:17.789544 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
907 11:10:17.793032 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
908 11:10:17.793451 == TX Byte 1 ==
909 11:10:17.800068 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
910 11:10:17.803250 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
911 11:10:17.803770 ==
912 11:10:17.806270 Dram Type= 6, Freq= 0, CH_0, rank 0
913 11:10:17.809504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 11:10:17.809983 ==
915 11:10:17.822787 TX Vref=22, minBit 14, minWin=26, winSum=434
916 11:10:17.826220 TX Vref=24, minBit 14, minWin=26, winSum=439
917 11:10:17.829456 TX Vref=26, minBit 8, minWin=27, winSum=442
918 11:10:17.832585 TX Vref=28, minBit 9, minWin=26, winSum=443
919 11:10:17.836050 TX Vref=30, minBit 9, minWin=26, winSum=438
920 11:10:17.842717 TX Vref=32, minBit 9, minWin=26, winSum=436
921 11:10:17.846285 [TxChooseVref] Worse bit 8, Min win 27, Win sum 442, Final Vref 26
922 11:10:17.846706
923 11:10:17.849615 Final TX Range 1 Vref 26
924 11:10:17.849915
925 11:10:17.850150 ==
926 11:10:17.852626 Dram Type= 6, Freq= 0, CH_0, rank 0
927 11:10:17.855736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 11:10:17.855961 ==
929 11:10:17.859280
930 11:10:17.859459
931 11:10:17.859600 TX Vref Scan disable
932 11:10:17.862736 == TX Byte 0 ==
933 11:10:17.865725 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
934 11:10:17.872438 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
935 11:10:17.872519 == TX Byte 1 ==
936 11:10:17.875820 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
937 11:10:17.882377 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
938 11:10:17.882458
939 11:10:17.882522 [DATLAT]
940 11:10:17.882582 Freq=800, CH0 RK0
941 11:10:17.882639
942 11:10:17.885875 DATLAT Default: 0xa
943 11:10:17.885959 0, 0xFFFF, sum = 0
944 11:10:17.888938 1, 0xFFFF, sum = 0
945 11:10:17.889023 2, 0xFFFF, sum = 0
946 11:10:17.892469 3, 0xFFFF, sum = 0
947 11:10:17.895473 4, 0xFFFF, sum = 0
948 11:10:17.895556 5, 0xFFFF, sum = 0
949 11:10:17.898930 6, 0xFFFF, sum = 0
950 11:10:17.899014 7, 0xFFFF, sum = 0
951 11:10:17.902198 8, 0xFFFF, sum = 0
952 11:10:17.902281 9, 0x0, sum = 1
953 11:10:17.902348 10, 0x0, sum = 2
954 11:10:17.905737 11, 0x0, sum = 3
955 11:10:17.905821 12, 0x0, sum = 4
956 11:10:17.908974 best_step = 10
957 11:10:17.909057
958 11:10:17.909121 ==
959 11:10:17.912471 Dram Type= 6, Freq= 0, CH_0, rank 0
960 11:10:17.915973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 11:10:17.916056 ==
962 11:10:17.918815 RX Vref Scan: 1
963 11:10:17.918897
964 11:10:17.918961 Set Vref Range= 32 -> 127
965 11:10:17.922575
966 11:10:17.922657 RX Vref 32 -> 127, step: 1
967 11:10:17.922723
968 11:10:17.925783 RX Delay -111 -> 252, step: 8
969 11:10:17.925865
970 11:10:17.929113 Set Vref, RX VrefLevel [Byte0]: 32
971 11:10:17.932439 [Byte1]: 32
972 11:10:17.932548
973 11:10:17.935429 Set Vref, RX VrefLevel [Byte0]: 33
974 11:10:17.938811 [Byte1]: 33
975 11:10:17.942860
976 11:10:17.942937 Set Vref, RX VrefLevel [Byte0]: 34
977 11:10:17.946398 [Byte1]: 34
978 11:10:17.950422
979 11:10:17.950495 Set Vref, RX VrefLevel [Byte0]: 35
980 11:10:17.953980 [Byte1]: 35
981 11:10:17.958287
982 11:10:17.958399 Set Vref, RX VrefLevel [Byte0]: 36
983 11:10:17.961582 [Byte1]: 36
984 11:10:17.966069
985 11:10:17.966146 Set Vref, RX VrefLevel [Byte0]: 37
986 11:10:17.969336 [Byte1]: 37
987 11:10:17.973437
988 11:10:17.973545 Set Vref, RX VrefLevel [Byte0]: 38
989 11:10:17.976624 [Byte1]: 38
990 11:10:17.981124
991 11:10:17.981225 Set Vref, RX VrefLevel [Byte0]: 39
992 11:10:17.984364 [Byte1]: 39
993 11:10:17.988993
994 11:10:17.989155 Set Vref, RX VrefLevel [Byte0]: 40
995 11:10:17.992277 [Byte1]: 40
996 11:10:17.996252
997 11:10:17.996326 Set Vref, RX VrefLevel [Byte0]: 41
998 11:10:17.999875 [Byte1]: 41
999 11:10:18.004048
1000 11:10:18.004130 Set Vref, RX VrefLevel [Byte0]: 42
1001 11:10:18.007450 [Byte1]: 42
1002 11:10:18.011863
1003 11:10:18.011958 Set Vref, RX VrefLevel [Byte0]: 43
1004 11:10:18.015243 [Byte1]: 43
1005 11:10:18.019284
1006 11:10:18.019386 Set Vref, RX VrefLevel [Byte0]: 44
1007 11:10:18.023190 [Byte1]: 44
1008 11:10:18.027418
1009 11:10:18.027520 Set Vref, RX VrefLevel [Byte0]: 45
1010 11:10:18.030588 [Byte1]: 45
1011 11:10:18.034919
1012 11:10:18.035021 Set Vref, RX VrefLevel [Byte0]: 46
1013 11:10:18.038435 [Byte1]: 46
1014 11:10:18.042352
1015 11:10:18.042453 Set Vref, RX VrefLevel [Byte0]: 47
1016 11:10:18.046081 [Byte1]: 47
1017 11:10:18.050482
1018 11:10:18.050593 Set Vref, RX VrefLevel [Byte0]: 48
1019 11:10:18.053370 [Byte1]: 48
1020 11:10:18.058191
1021 11:10:18.058313 Set Vref, RX VrefLevel [Byte0]: 49
1022 11:10:18.061180 [Byte1]: 49
1023 11:10:18.065393
1024 11:10:18.065582 Set Vref, RX VrefLevel [Byte0]: 50
1025 11:10:18.068991 [Byte1]: 50
1026 11:10:18.073438
1027 11:10:18.073731 Set Vref, RX VrefLevel [Byte0]: 51
1028 11:10:18.076798 [Byte1]: 51
1029 11:10:18.081239
1030 11:10:18.081605 Set Vref, RX VrefLevel [Byte0]: 52
1031 11:10:18.083947 [Byte1]: 52
1032 11:10:18.088945
1033 11:10:18.089341 Set Vref, RX VrefLevel [Byte0]: 53
1034 11:10:18.092130 [Byte1]: 53
1035 11:10:18.096575
1036 11:10:18.097098 Set Vref, RX VrefLevel [Byte0]: 54
1037 11:10:18.099898 [Byte1]: 54
1038 11:10:18.104213
1039 11:10:18.104733 Set Vref, RX VrefLevel [Byte0]: 55
1040 11:10:18.107714 [Byte1]: 55
1041 11:10:18.111634
1042 11:10:18.112054 Set Vref, RX VrefLevel [Byte0]: 56
1043 11:10:18.114826 [Byte1]: 56
1044 11:10:18.119372
1045 11:10:18.119893 Set Vref, RX VrefLevel [Byte0]: 57
1046 11:10:18.122513 [Byte1]: 57
1047 11:10:18.126549
1048 11:10:18.126976 Set Vref, RX VrefLevel [Byte0]: 58
1049 11:10:18.130133 [Byte1]: 58
1050 11:10:18.134494
1051 11:10:18.134914 Set Vref, RX VrefLevel [Byte0]: 59
1052 11:10:18.137550 [Byte1]: 59
1053 11:10:18.142073
1054 11:10:18.142493 Set Vref, RX VrefLevel [Byte0]: 60
1055 11:10:18.145218 [Byte1]: 60
1056 11:10:18.149751
1057 11:10:18.150166 Set Vref, RX VrefLevel [Byte0]: 61
1058 11:10:18.152917 [Byte1]: 61
1059 11:10:18.157153
1060 11:10:18.157627 Set Vref, RX VrefLevel [Byte0]: 62
1061 11:10:18.160501 [Byte1]: 62
1062 11:10:18.164715
1063 11:10:18.165011 Set Vref, RX VrefLevel [Byte0]: 63
1064 11:10:18.171549 [Byte1]: 63
1065 11:10:18.171791
1066 11:10:18.174423 Set Vref, RX VrefLevel [Byte0]: 64
1067 11:10:18.177924 [Byte1]: 64
1068 11:10:18.178104
1069 11:10:18.181036 Set Vref, RX VrefLevel [Byte0]: 65
1070 11:10:18.184497 [Byte1]: 65
1071 11:10:18.184680
1072 11:10:18.187835 Set Vref, RX VrefLevel [Byte0]: 66
1073 11:10:18.190987 [Byte1]: 66
1074 11:10:18.195337
1075 11:10:18.195517 Set Vref, RX VrefLevel [Byte0]: 67
1076 11:10:18.198396 [Byte1]: 67
1077 11:10:18.203099
1078 11:10:18.203278 Set Vref, RX VrefLevel [Byte0]: 68
1079 11:10:18.206462 [Byte1]: 68
1080 11:10:18.210737
1081 11:10:18.210915 Set Vref, RX VrefLevel [Byte0]: 69
1082 11:10:18.213959 [Byte1]: 69
1083 11:10:18.218126
1084 11:10:18.218305 Set Vref, RX VrefLevel [Byte0]: 70
1085 11:10:18.221355 [Byte1]: 70
1086 11:10:18.225843
1087 11:10:18.226021 Set Vref, RX VrefLevel [Byte0]: 71
1088 11:10:18.229229 [Byte1]: 71
1089 11:10:18.233487
1090 11:10:18.233669 Set Vref, RX VrefLevel [Byte0]: 72
1091 11:10:18.237144 [Byte1]: 72
1092 11:10:18.241243
1093 11:10:18.241515 Set Vref, RX VrefLevel [Byte0]: 73
1094 11:10:18.244579 [Byte1]: 73
1095 11:10:18.248724
1096 11:10:18.248976 Set Vref, RX VrefLevel [Byte0]: 74
1097 11:10:18.251958 [Byte1]: 74
1098 11:10:18.256296
1099 11:10:18.256545 Set Vref, RX VrefLevel [Byte0]: 75
1100 11:10:18.259877 [Byte1]: 75
1101 11:10:18.263834
1102 11:10:18.263942 Set Vref, RX VrefLevel [Byte0]: 76
1103 11:10:18.267387 [Byte1]: 76
1104 11:10:18.271926
1105 11:10:18.272037 Set Vref, RX VrefLevel [Byte0]: 77
1106 11:10:18.275004 [Byte1]: 77
1107 11:10:18.279273
1108 11:10:18.279384 Set Vref, RX VrefLevel [Byte0]: 78
1109 11:10:18.282635 [Byte1]: 78
1110 11:10:18.286853
1111 11:10:18.286983 Set Vref, RX VrefLevel [Byte0]: 79
1112 11:10:18.290235 [Byte1]: 79
1113 11:10:18.294471
1114 11:10:18.294553 Final RX Vref Byte 0 = 60 to rank0
1115 11:10:18.298272 Final RX Vref Byte 1 = 59 to rank0
1116 11:10:18.301355 Final RX Vref Byte 0 = 60 to rank1
1117 11:10:18.304526 Final RX Vref Byte 1 = 59 to rank1==
1118 11:10:18.307943 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 11:10:18.314533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 11:10:18.314615 ==
1121 11:10:18.314680 DQS Delay:
1122 11:10:18.314740 DQS0 = 0, DQS1 = 0
1123 11:10:18.318238 DQM Delay:
1124 11:10:18.318319 DQM0 = 82, DQM1 = 67
1125 11:10:18.321218 DQ Delay:
1126 11:10:18.324817 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1127 11:10:18.324898 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1128 11:10:18.327937 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1129 11:10:18.331574 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1130 11:10:18.334838
1131 11:10:18.334981
1132 11:10:18.341470 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1133 11:10:18.344846 CH0 RK0: MR19=606, MR18=2424
1134 11:10:18.351609 CH0_RK0: MR19=0x606, MR18=0x2424, DQSOSC=400, MR23=63, INC=92, DEC=61
1135 11:10:18.351812
1136 11:10:18.354995 ----->DramcWriteLeveling(PI) begin...
1137 11:10:18.355210 ==
1138 11:10:18.358513 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 11:10:18.361990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 11:10:18.362228 ==
1141 11:10:18.364903 Write leveling (Byte 0): 30 => 30
1142 11:10:18.368740 Write leveling (Byte 1): 30 => 30
1143 11:10:18.372161 DramcWriteLeveling(PI) end<-----
1144 11:10:18.372450
1145 11:10:18.372622 ==
1146 11:10:18.375141 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 11:10:18.378586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 11:10:18.378919 ==
1149 11:10:18.381597 [Gating] SW mode calibration
1150 11:10:18.387993 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 11:10:18.394965 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 11:10:18.398270 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 11:10:18.401710 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 11:10:18.408753 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 11:10:18.411671 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:10:18.415620 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:10:18.422118 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:10:18.425361 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:10:18.428328 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:10:18.435347 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:10:18.438512 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:10:18.441599 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:10:18.485978 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:10:18.486499 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:10:18.486865 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:10:18.487211 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:10:18.487913 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:10:18.488243 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:10:18.488546 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1170 11:10:18.488835 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1171 11:10:18.489120 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:10:18.489468 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:10:18.530243 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:10:18.531186 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:10:18.531588 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:10:18.531941 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:10:18.532305 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:10:18.532698 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1179 11:10:18.533022 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1180 11:10:18.533309 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 11:10:18.533629 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 11:10:18.533915 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 11:10:18.534934 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 11:10:18.538434 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1185 11:10:18.544714 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1186 11:10:18.548205 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
1187 11:10:18.552114 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1188 11:10:18.558461 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:10:18.561687 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:10:18.565386 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:10:18.568320 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:10:18.575252 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:10:18.578401 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1194 11:10:18.581264 0 11 8 | B1->B0 | 2a2a 3838 | 0 0 | (0 0) (0 0)
1195 11:10:18.588269 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1196 11:10:18.591344 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 11:10:18.594799 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:10:18.601779 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:10:18.605623 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:10:18.609345 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:10:18.613315 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 11:10:18.617064 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 11:10:18.623508 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:10:18.626630 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:10:18.630788 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:10:18.634010 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:10:18.640915 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:10:18.643754 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:10:18.647745 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:10:18.654402 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:10:18.657234 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:10:18.660263 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:10:18.666966 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:10:18.670437 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:10:18.673642 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:10:18.680387 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:10:18.683795 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 11:10:18.686903 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 11:10:18.693883 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 11:10:18.694305 Total UI for P1: 0, mck2ui 16
1221 11:10:18.700490 best dqsien dly found for B0: ( 0, 14, 6)
1222 11:10:18.701013 Total UI for P1: 0, mck2ui 16
1223 11:10:18.706928 best dqsien dly found for B1: ( 0, 14, 6)
1224 11:10:18.710177 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1225 11:10:18.713777 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1226 11:10:18.714216
1227 11:10:18.717159 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1228 11:10:18.720516 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1229 11:10:18.723756 [Gating] SW calibration Done
1230 11:10:18.724285 ==
1231 11:10:18.727140 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 11:10:18.730184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 11:10:18.730608 ==
1234 11:10:18.733860 RX Vref Scan: 0
1235 11:10:18.734386
1236 11:10:18.734727 RX Vref 0 -> 0, step: 1
1237 11:10:18.735037
1238 11:10:18.736986 RX Delay -130 -> 252, step: 16
1239 11:10:18.740629 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1240 11:10:18.747022 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1241 11:10:18.750617 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1242 11:10:18.753707 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1243 11:10:18.757439 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1244 11:10:18.760778 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1245 11:10:18.767425 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1246 11:10:18.770441 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1247 11:10:18.773936 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1248 11:10:18.777375 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1249 11:10:18.780347 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1250 11:10:18.786817 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1251 11:10:18.790270 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1252 11:10:18.793595 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1253 11:10:18.797081 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1254 11:10:18.800568 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1255 11:10:18.803800 ==
1256 11:10:18.807026 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 11:10:18.810065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 11:10:18.810489 ==
1259 11:10:18.810825 DQS Delay:
1260 11:10:18.813778 DQS0 = 0, DQS1 = 0
1261 11:10:18.814290 DQM Delay:
1262 11:10:18.816988 DQM0 = 76, DQM1 = 69
1263 11:10:18.817526 DQ Delay:
1264 11:10:18.820299 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1265 11:10:18.823727 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1266 11:10:18.826727 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1267 11:10:18.830065 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1268 11:10:18.830484
1269 11:10:18.830816
1270 11:10:18.831122 ==
1271 11:10:18.833566 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 11:10:18.837218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 11:10:18.837770 ==
1274 11:10:18.838111
1275 11:10:18.838418
1276 11:10:18.840018 TX Vref Scan disable
1277 11:10:18.843558 == TX Byte 0 ==
1278 11:10:18.847096 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1279 11:10:18.850284 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1280 11:10:18.853646 == TX Byte 1 ==
1281 11:10:18.856939 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1282 11:10:18.859952 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1283 11:10:18.860378 ==
1284 11:10:18.863700 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 11:10:18.867194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 11:10:18.870190 ==
1287 11:10:18.881457 TX Vref=22, minBit 9, minWin=26, winSum=436
1288 11:10:18.884806 TX Vref=24, minBit 0, minWin=27, winSum=440
1289 11:10:18.887647 TX Vref=26, minBit 0, minWin=27, winSum=439
1290 11:10:18.891364 TX Vref=28, minBit 9, minWin=27, winSum=446
1291 11:10:18.894407 TX Vref=30, minBit 1, minWin=27, winSum=444
1292 11:10:18.897804 TX Vref=32, minBit 1, minWin=27, winSum=442
1293 11:10:18.904183 [TxChooseVref] Worse bit 9, Min win 27, Win sum 446, Final Vref 28
1294 11:10:18.904601
1295 11:10:18.907583 Final TX Range 1 Vref 28
1296 11:10:18.908000
1297 11:10:18.908328 ==
1298 11:10:18.910978 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 11:10:18.914580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 11:10:18.915060 ==
1301 11:10:18.915396
1302 11:10:18.917461
1303 11:10:18.917926 TX Vref Scan disable
1304 11:10:18.921322 == TX Byte 0 ==
1305 11:10:18.924492 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1306 11:10:18.927519 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1307 11:10:18.930803 == TX Byte 1 ==
1308 11:10:18.934104 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1309 11:10:18.940821 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1310 11:10:18.941342
1311 11:10:18.941716 [DATLAT]
1312 11:10:18.942031 Freq=800, CH0 RK1
1313 11:10:18.942330
1314 11:10:18.944429 DATLAT Default: 0xa
1315 11:10:18.944844 0, 0xFFFF, sum = 0
1316 11:10:18.947682 1, 0xFFFF, sum = 0
1317 11:10:18.948376 2, 0xFFFF, sum = 0
1318 11:10:18.950796 3, 0xFFFF, sum = 0
1319 11:10:18.951218 4, 0xFFFF, sum = 0
1320 11:10:18.954180 5, 0xFFFF, sum = 0
1321 11:10:18.957927 6, 0xFFFF, sum = 0
1322 11:10:18.958449 7, 0xFFFF, sum = 0
1323 11:10:18.960565 8, 0xFFFF, sum = 0
1324 11:10:18.960991 9, 0x0, sum = 1
1325 11:10:18.964304 10, 0x0, sum = 2
1326 11:10:18.964830 11, 0x0, sum = 3
1327 11:10:18.965170 12, 0x0, sum = 4
1328 11:10:18.967591 best_step = 10
1329 11:10:18.968054
1330 11:10:18.968383 ==
1331 11:10:18.971073 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 11:10:18.974194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 11:10:18.974725 ==
1334 11:10:18.977421 RX Vref Scan: 0
1335 11:10:18.977980
1336 11:10:18.978313 RX Vref 0 -> 0, step: 1
1337 11:10:18.980345
1338 11:10:18.980787 RX Delay -111 -> 252, step: 8
1339 11:10:18.987623 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1340 11:10:18.990924 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1341 11:10:18.994390 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1342 11:10:18.997592 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1343 11:10:19.001257 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1344 11:10:19.007652 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1345 11:10:19.010918 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1346 11:10:19.014330 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1347 11:10:19.017728 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1348 11:10:19.021521 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1349 11:10:19.027755 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1350 11:10:19.031115 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1351 11:10:19.034529 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1352 11:10:19.037682 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1353 11:10:19.041174 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1354 11:10:19.047922 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1355 11:10:19.048452 ==
1356 11:10:19.051002 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 11:10:19.054446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 11:10:19.054994 ==
1359 11:10:19.055333 DQS Delay:
1360 11:10:19.057545 DQS0 = 0, DQS1 = 0
1361 11:10:19.057961 DQM Delay:
1362 11:10:19.060730 DQM0 = 79, DQM1 = 69
1363 11:10:19.061293 DQ Delay:
1364 11:10:19.064426 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1365 11:10:19.067567 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =92
1366 11:10:19.070816 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1367 11:10:19.074220 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =76
1368 11:10:19.074637
1369 11:10:19.074967
1370 11:10:19.084182 [DQSOSCAuto] RK1, (LSB)MR18= 0x441e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1371 11:10:19.084693 CH0 RK1: MR19=606, MR18=441E
1372 11:10:19.090927 CH0_RK1: MR19=0x606, MR18=0x441E, DQSOSC=392, MR23=63, INC=96, DEC=64
1373 11:10:19.094186 [RxdqsGatingPostProcess] freq 800
1374 11:10:19.101190 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 11:10:19.104116 Pre-setting of DQS Precalculation
1376 11:10:19.107332 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 11:10:19.107755 ==
1378 11:10:19.110718 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 11:10:19.113856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 11:10:19.117587 ==
1381 11:10:19.120743 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 11:10:19.127697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 11:10:19.136007 [CA 0] Center 36 (6~66) winsize 61
1384 11:10:19.139281 [CA 1] Center 36 (6~67) winsize 62
1385 11:10:19.142651 [CA 2] Center 34 (4~65) winsize 62
1386 11:10:19.145997 [CA 3] Center 34 (4~65) winsize 62
1387 11:10:19.149400 [CA 4] Center 34 (4~65) winsize 62
1388 11:10:19.153077 [CA 5] Center 34 (4~64) winsize 61
1389 11:10:19.153663
1390 11:10:19.156227 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 11:10:19.156800
1392 11:10:19.159652 [CATrainingPosCal] consider 1 rank data
1393 11:10:19.162682 u2DelayCellTimex100 = 270/100 ps
1394 11:10:19.166086 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1395 11:10:19.169732 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 11:10:19.176329 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 11:10:19.179610 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 11:10:19.182767 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 11:10:19.185946 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 11:10:19.186371
1401 11:10:19.189324 CA PerBit enable=1, Macro0, CA PI delay=34
1402 11:10:19.189847
1403 11:10:19.193033 [CBTSetCACLKResult] CA Dly = 34
1404 11:10:19.193616 CS Dly: 5 (0~36)
1405 11:10:19.193983 ==
1406 11:10:19.196134 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 11:10:19.202808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 11:10:19.203328 ==
1409 11:10:19.205928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 11:10:19.212371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 11:10:19.222125 [CA 0] Center 37 (7~67) winsize 61
1412 11:10:19.225511 [CA 1] Center 36 (6~67) winsize 62
1413 11:10:19.228516 [CA 2] Center 35 (5~65) winsize 61
1414 11:10:19.232344 [CA 3] Center 33 (3~64) winsize 62
1415 11:10:19.235527 [CA 4] Center 34 (4~65) winsize 62
1416 11:10:19.238910 [CA 5] Center 33 (3~64) winsize 62
1417 11:10:19.239432
1418 11:10:19.242451 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 11:10:19.242972
1420 11:10:19.245677 [CATrainingPosCal] consider 2 rank data
1421 11:10:19.249081 u2DelayCellTimex100 = 270/100 ps
1422 11:10:19.252365 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1423 11:10:19.255880 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 11:10:19.262438 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 11:10:19.266455 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 11:10:19.270403 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 11:10:19.273594 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 11:10:19.274126
1429 11:10:19.277070 CA PerBit enable=1, Macro0, CA PI delay=34
1430 11:10:19.277654
1431 11:10:19.278004 [CBTSetCACLKResult] CA Dly = 34
1432 11:10:19.280661 CS Dly: 6 (0~38)
1433 11:10:19.281196
1434 11:10:19.284297 ----->DramcWriteLeveling(PI) begin...
1435 11:10:19.284722 ==
1436 11:10:19.287905 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 11:10:19.291469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 11:10:19.292034 ==
1439 11:10:19.295379 Write leveling (Byte 0): 29 => 29
1440 11:10:19.298619 Write leveling (Byte 1): 29 => 29
1441 11:10:19.302229 DramcWriteLeveling(PI) end<-----
1442 11:10:19.302650
1443 11:10:19.302980 ==
1444 11:10:19.305330 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 11:10:19.308837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 11:10:19.309364 ==
1447 11:10:19.312225 [Gating] SW mode calibration
1448 11:10:19.318650 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 11:10:19.322188 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 11:10:19.329076 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 11:10:19.332090 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 11:10:19.335279 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1453 11:10:19.342022 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:10:19.345693 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:10:19.348983 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:10:19.355615 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:10:19.358720 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:10:19.362439 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:10:19.368988 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:10:19.371801 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:10:19.375573 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:10:19.382470 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:10:19.385419 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:10:19.389021 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:10:19.395121 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:10:19.398729 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:10:19.402169 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:10:19.409048 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:10:19.411951 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:10:19.415175 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:10:19.418456 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:10:19.425919 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:10:19.428704 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:10:19.432037 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:10:19.438909 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:10:19.442068 0 9 8 | B1->B0 | 2828 2827 | 0 1 | (0 0) (1 1)
1477 11:10:19.445823 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 11:10:19.452120 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 11:10:19.456025 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 11:10:19.458964 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:10:19.465251 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 11:10:19.468312 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 11:10:19.471852 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1484 11:10:19.477871 0 10 8 | B1->B0 | 2a2a 2e2e | 0 0 | (1 0) (0 1)
1485 11:10:19.481120 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:10:19.484577 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:10:19.491214 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:10:19.494591 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:10:19.497698 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:10:19.504850 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:10:19.508295 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:10:19.511568 0 11 8 | B1->B0 | 3939 3b3a | 0 1 | (0 0) (0 0)
1493 11:10:19.518347 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 11:10:19.521353 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 11:10:19.524899 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 11:10:19.528238 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:10:19.535213 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 11:10:19.538372 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 11:10:19.541661 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:10:19.548801 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1501 11:10:19.551790 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:10:19.554936 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:10:19.561788 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:10:19.565344 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:10:19.568561 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:10:19.575174 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:10:19.578217 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:10:19.581923 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:10:19.588256 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:10:19.591551 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:10:19.594934 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:10:19.601754 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:10:19.605200 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:10:19.608648 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:10:19.615394 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1516 11:10:19.618198 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1517 11:10:19.621991 Total UI for P1: 0, mck2ui 16
1518 11:10:19.625271 best dqsien dly found for B0: ( 0, 14, 4)
1519 11:10:19.628598 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 11:10:19.631341 Total UI for P1: 0, mck2ui 16
1521 11:10:19.634693 best dqsien dly found for B1: ( 0, 14, 8)
1522 11:10:19.638254 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1523 11:10:19.641402 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1524 11:10:19.641866
1525 11:10:19.644908 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 11:10:19.648477 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1527 11:10:19.652042 [Gating] SW calibration Done
1528 11:10:19.652563 ==
1529 11:10:19.655231 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 11:10:19.661766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 11:10:19.662290 ==
1532 11:10:19.662622 RX Vref Scan: 0
1533 11:10:19.662935
1534 11:10:19.665076 RX Vref 0 -> 0, step: 1
1535 11:10:19.665631
1536 11:10:19.668749 RX Delay -130 -> 252, step: 16
1537 11:10:19.672191 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1538 11:10:19.674923 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1539 11:10:19.678549 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1540 11:10:19.681632 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1541 11:10:19.688472 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1542 11:10:19.691859 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1543 11:10:19.694669 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1544 11:10:19.698276 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1545 11:10:19.701708 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1546 11:10:19.708639 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1547 11:10:19.711965 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1548 11:10:19.715289 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1549 11:10:19.718461 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1550 11:10:19.722050 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1551 11:10:19.728511 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1552 11:10:19.732049 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1553 11:10:19.732566 ==
1554 11:10:19.734899 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 11:10:19.738354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 11:10:19.738864 ==
1557 11:10:19.742030 DQS Delay:
1558 11:10:19.742535 DQS0 = 0, DQS1 = 0
1559 11:10:19.742867 DQM Delay:
1560 11:10:19.745083 DQM0 = 81, DQM1 = 71
1561 11:10:19.745634 DQ Delay:
1562 11:10:19.748661 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1563 11:10:19.751674 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1564 11:10:19.755311 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1565 11:10:19.758288 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1566 11:10:19.758704
1567 11:10:19.759027
1568 11:10:19.759327 ==
1569 11:10:19.761922 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 11:10:19.768604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 11:10:19.769116 ==
1572 11:10:19.769453
1573 11:10:19.769824
1574 11:10:19.770119 TX Vref Scan disable
1575 11:10:19.771532 == TX Byte 0 ==
1576 11:10:19.775052 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1577 11:10:19.781898 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1578 11:10:19.782420 == TX Byte 1 ==
1579 11:10:19.785329 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1580 11:10:19.791743 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1581 11:10:19.792250 ==
1582 11:10:19.794911 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 11:10:19.798218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 11:10:19.798640 ==
1585 11:10:19.810642 TX Vref=22, minBit 1, minWin=26, winSum=438
1586 11:10:19.813806 TX Vref=24, minBit 1, minWin=27, winSum=441
1587 11:10:19.817458 TX Vref=26, minBit 2, minWin=27, winSum=444
1588 11:10:19.820755 TX Vref=28, minBit 4, minWin=27, winSum=447
1589 11:10:19.824252 TX Vref=30, minBit 4, minWin=27, winSum=448
1590 11:10:19.827191 TX Vref=32, minBit 0, minWin=27, winSum=446
1591 11:10:19.834286 [TxChooseVref] Worse bit 4, Min win 27, Win sum 448, Final Vref 30
1592 11:10:19.834797
1593 11:10:19.837706 Final TX Range 1 Vref 30
1594 11:10:19.838221
1595 11:10:19.838558 ==
1596 11:10:19.841203 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 11:10:19.844830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 11:10:19.845255 ==
1599 11:10:19.845618
1600 11:10:19.845921
1601 11:10:19.848490 TX Vref Scan disable
1602 11:10:19.851691 == TX Byte 0 ==
1603 11:10:19.855072 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1604 11:10:19.858040 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1605 11:10:19.861329 == TX Byte 1 ==
1606 11:10:19.864912 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 11:10:19.868375 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 11:10:19.868886
1609 11:10:19.871408 [DATLAT]
1610 11:10:19.871918 Freq=800, CH1 RK0
1611 11:10:19.872249
1612 11:10:19.874483 DATLAT Default: 0xa
1613 11:10:19.874894 0, 0xFFFF, sum = 0
1614 11:10:19.877934 1, 0xFFFF, sum = 0
1615 11:10:19.878452 2, 0xFFFF, sum = 0
1616 11:10:19.881668 3, 0xFFFF, sum = 0
1617 11:10:19.882323 4, 0xFFFF, sum = 0
1618 11:10:19.884540 5, 0xFFFF, sum = 0
1619 11:10:19.885263 6, 0xFFFF, sum = 0
1620 11:10:19.887590 7, 0xFFFF, sum = 0
1621 11:10:19.888007 8, 0xFFFF, sum = 0
1622 11:10:19.891238 9, 0x0, sum = 1
1623 11:10:19.891656 10, 0x0, sum = 2
1624 11:10:19.894672 11, 0x0, sum = 3
1625 11:10:19.895106 12, 0x0, sum = 4
1626 11:10:19.897833 best_step = 10
1627 11:10:19.898284
1628 11:10:19.898610 ==
1629 11:10:19.901216 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 11:10:19.904840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 11:10:19.905349 ==
1632 11:10:19.905734 RX Vref Scan: 1
1633 11:10:19.908179
1634 11:10:19.908687 Set Vref Range= 32 -> 127
1635 11:10:19.909015
1636 11:10:19.911437 RX Vref 32 -> 127, step: 1
1637 11:10:19.911949
1638 11:10:19.914630 RX Delay -111 -> 252, step: 8
1639 11:10:19.915128
1640 11:10:19.917955 Set Vref, RX VrefLevel [Byte0]: 32
1641 11:10:19.921440 [Byte1]: 32
1642 11:10:19.922003
1643 11:10:19.924583 Set Vref, RX VrefLevel [Byte0]: 33
1644 11:10:19.927980 [Byte1]: 33
1645 11:10:19.928394
1646 11:10:19.931253 Set Vref, RX VrefLevel [Byte0]: 34
1647 11:10:19.934938 [Byte1]: 34
1648 11:10:19.938680
1649 11:10:19.939090 Set Vref, RX VrefLevel [Byte0]: 35
1650 11:10:19.942420 [Byte1]: 35
1651 11:10:19.946403
1652 11:10:19.946915 Set Vref, RX VrefLevel [Byte0]: 36
1653 11:10:19.950100 [Byte1]: 36
1654 11:10:19.954323
1655 11:10:19.954830 Set Vref, RX VrefLevel [Byte0]: 37
1656 11:10:19.957683 [Byte1]: 37
1657 11:10:19.961980
1658 11:10:19.962490 Set Vref, RX VrefLevel [Byte0]: 38
1659 11:10:19.965102 [Byte1]: 38
1660 11:10:19.969713
1661 11:10:19.970241 Set Vref, RX VrefLevel [Byte0]: 39
1662 11:10:19.972867 [Byte1]: 39
1663 11:10:19.977171
1664 11:10:19.977720 Set Vref, RX VrefLevel [Byte0]: 40
1665 11:10:19.980495 [Byte1]: 40
1666 11:10:19.984700
1667 11:10:19.987894 Set Vref, RX VrefLevel [Byte0]: 41
1668 11:10:19.991119 [Byte1]: 41
1669 11:10:19.991556
1670 11:10:19.994226 Set Vref, RX VrefLevel [Byte0]: 42
1671 11:10:19.997534 [Byte1]: 42
1672 11:10:19.997946
1673 11:10:20.001174 Set Vref, RX VrefLevel [Byte0]: 43
1674 11:10:20.004090 [Byte1]: 43
1675 11:10:20.007421
1676 11:10:20.007832 Set Vref, RX VrefLevel [Byte0]: 44
1677 11:10:20.010973 [Byte1]: 44
1678 11:10:20.015394
1679 11:10:20.015940 Set Vref, RX VrefLevel [Byte0]: 45
1680 11:10:20.018566 [Byte1]: 45
1681 11:10:20.023003
1682 11:10:20.023514 Set Vref, RX VrefLevel [Byte0]: 46
1683 11:10:20.026385 [Byte1]: 46
1684 11:10:20.030174
1685 11:10:20.030587 Set Vref, RX VrefLevel [Byte0]: 47
1686 11:10:20.033857 [Byte1]: 47
1687 11:10:20.038176
1688 11:10:20.038615 Set Vref, RX VrefLevel [Byte0]: 48
1689 11:10:20.041616 [Byte1]: 48
1690 11:10:20.045713
1691 11:10:20.046219 Set Vref, RX VrefLevel [Byte0]: 49
1692 11:10:20.048913 [Byte1]: 49
1693 11:10:20.053615
1694 11:10:20.054132 Set Vref, RX VrefLevel [Byte0]: 50
1695 11:10:20.056957 [Byte1]: 50
1696 11:10:20.061269
1697 11:10:20.061860 Set Vref, RX VrefLevel [Byte0]: 51
1698 11:10:20.064670 [Byte1]: 51
1699 11:10:20.068777
1700 11:10:20.069291 Set Vref, RX VrefLevel [Byte0]: 52
1701 11:10:20.072293 [Byte1]: 52
1702 11:10:20.076551
1703 11:10:20.077064 Set Vref, RX VrefLevel [Byte0]: 53
1704 11:10:20.079772 [Byte1]: 53
1705 11:10:20.084386
1706 11:10:20.084900 Set Vref, RX VrefLevel [Byte0]: 54
1707 11:10:20.087427 [Byte1]: 54
1708 11:10:20.091977
1709 11:10:20.092489 Set Vref, RX VrefLevel [Byte0]: 55
1710 11:10:20.094937 [Byte1]: 55
1711 11:10:20.099321
1712 11:10:20.099733 Set Vref, RX VrefLevel [Byte0]: 56
1713 11:10:20.102918 [Byte1]: 56
1714 11:10:20.106817
1715 11:10:20.107229 Set Vref, RX VrefLevel [Byte0]: 57
1716 11:10:20.110017 [Byte1]: 57
1717 11:10:20.114720
1718 11:10:20.115237 Set Vref, RX VrefLevel [Byte0]: 58
1719 11:10:20.117926 [Byte1]: 58
1720 11:10:20.122363
1721 11:10:20.122880 Set Vref, RX VrefLevel [Byte0]: 59
1722 11:10:20.125637 [Byte1]: 59
1723 11:10:20.129961
1724 11:10:20.130371 Set Vref, RX VrefLevel [Byte0]: 60
1725 11:10:20.133574 [Byte1]: 60
1726 11:10:20.137832
1727 11:10:20.138345 Set Vref, RX VrefLevel [Byte0]: 61
1728 11:10:20.140926 [Byte1]: 61
1729 11:10:20.145285
1730 11:10:20.145735 Set Vref, RX VrefLevel [Byte0]: 62
1731 11:10:20.148415 [Byte1]: 62
1732 11:10:20.152938
1733 11:10:20.153349 Set Vref, RX VrefLevel [Byte0]: 63
1734 11:10:20.156047 [Byte1]: 63
1735 11:10:20.160452
1736 11:10:20.160923 Set Vref, RX VrefLevel [Byte0]: 64
1737 11:10:20.163557 [Byte1]: 64
1738 11:10:20.168080
1739 11:10:20.168492 Set Vref, RX VrefLevel [Byte0]: 65
1740 11:10:20.171302 [Byte1]: 65
1741 11:10:20.175718
1742 11:10:20.176125 Set Vref, RX VrefLevel [Byte0]: 66
1743 11:10:20.178827 [Byte1]: 66
1744 11:10:20.183254
1745 11:10:20.183663 Set Vref, RX VrefLevel [Byte0]: 67
1746 11:10:20.186551 [Byte1]: 67
1747 11:10:20.190775
1748 11:10:20.191187 Set Vref, RX VrefLevel [Byte0]: 68
1749 11:10:20.194221 [Byte1]: 68
1750 11:10:20.198804
1751 11:10:20.199225 Set Vref, RX VrefLevel [Byte0]: 69
1752 11:10:20.201649 [Byte1]: 69
1753 11:10:20.206236
1754 11:10:20.206653 Set Vref, RX VrefLevel [Byte0]: 70
1755 11:10:20.209473 [Byte1]: 70
1756 11:10:20.213893
1757 11:10:20.214491 Set Vref, RX VrefLevel [Byte0]: 71
1758 11:10:20.217015 [Byte1]: 71
1759 11:10:20.221653
1760 11:10:20.222070 Set Vref, RX VrefLevel [Byte0]: 72
1761 11:10:20.224960 [Byte1]: 72
1762 11:10:20.229012
1763 11:10:20.229527 Set Vref, RX VrefLevel [Byte0]: 73
1764 11:10:20.232608 [Byte1]: 73
1765 11:10:20.236786
1766 11:10:20.237249 Set Vref, RX VrefLevel [Byte0]: 74
1767 11:10:20.240064 [Byte1]: 74
1768 11:10:20.244887
1769 11:10:20.245393 Set Vref, RX VrefLevel [Byte0]: 75
1770 11:10:20.251059 [Byte1]: 75
1771 11:10:20.251560
1772 11:10:20.254395 Set Vref, RX VrefLevel [Byte0]: 76
1773 11:10:20.257713 [Byte1]: 76
1774 11:10:20.258234
1775 11:10:20.260942 Final RX Vref Byte 0 = 57 to rank0
1776 11:10:20.264704 Final RX Vref Byte 1 = 52 to rank0
1777 11:10:20.267825 Final RX Vref Byte 0 = 57 to rank1
1778 11:10:20.270969 Final RX Vref Byte 1 = 52 to rank1==
1779 11:10:20.274174 Dram Type= 6, Freq= 0, CH_1, rank 0
1780 11:10:20.278108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 11:10:20.278635 ==
1782 11:10:20.280797 DQS Delay:
1783 11:10:20.281317 DQS0 = 0, DQS1 = 0
1784 11:10:20.281792 DQM Delay:
1785 11:10:20.284339 DQM0 = 81, DQM1 = 71
1786 11:10:20.285038 DQ Delay:
1787 11:10:20.287474 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1788 11:10:20.290696 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1789 11:10:20.294207 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1790 11:10:20.297396 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1791 11:10:20.297861
1792 11:10:20.298190
1793 11:10:20.307425 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1794 11:10:20.307926 CH1 RK0: MR19=606, MR18=E18
1795 11:10:20.314011 CH1_RK0: MR19=0x606, MR18=0xE18, DQSOSC=403, MR23=63, INC=90, DEC=60
1796 11:10:20.314528
1797 11:10:20.317325 ----->DramcWriteLeveling(PI) begin...
1798 11:10:20.321053 ==
1799 11:10:20.321614 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 11:10:20.327184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 11:10:20.327700 ==
1802 11:10:20.330702 Write leveling (Byte 0): 26 => 26
1803 11:10:20.334122 Write leveling (Byte 1): 32 => 32
1804 11:10:20.337561 DramcWriteLeveling(PI) end<-----
1805 11:10:20.338095
1806 11:10:20.338434 ==
1807 11:10:20.340584 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 11:10:20.344306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 11:10:20.344827 ==
1810 11:10:20.347115 [Gating] SW mode calibration
1811 11:10:20.353941 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1812 11:10:20.357614 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1813 11:10:20.363791 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1814 11:10:20.367353 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1815 11:10:20.370189 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1816 11:10:20.377459 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:10:20.380669 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:10:20.383822 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:10:20.390330 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:10:20.393722 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:10:20.396750 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:10:20.403677 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:10:20.406858 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:10:20.409981 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:10:20.417185 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:10:20.420471 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:10:20.423612 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:10:20.430259 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:10:20.433709 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1830 11:10:20.437264 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1831 11:10:20.443745 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:10:20.446930 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:10:20.450155 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:10:20.457012 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:10:20.460348 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:10:20.463964 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:10:20.466963 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:10:20.473924 0 9 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1839 11:10:20.476995 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1840 11:10:20.480148 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 11:10:20.486924 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 11:10:20.490306 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 11:10:20.493470 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 11:10:20.499954 0 9 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1845 11:10:20.503697 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1846 11:10:20.506953 0 10 4 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (0 0)
1847 11:10:20.513751 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1848 11:10:20.516960 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:10:20.520100 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:10:20.526489 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:10:20.529848 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:10:20.533294 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:10:20.540100 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:10:20.543612 0 11 4 | B1->B0 | 2525 3a3a | 0 0 | (0 0) (0 0)
1855 11:10:20.546773 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1856 11:10:20.553656 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 11:10:20.557099 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 11:10:20.560123 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 11:10:20.566965 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 11:10:20.570210 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 11:10:20.573205 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 11:10:20.580035 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1863 11:10:20.583063 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:10:20.586387 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:10:20.589831 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:10:20.596456 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:10:20.599937 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:10:20.603602 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:10:20.609874 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:10:20.613232 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:10:20.616843 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:10:20.623027 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:10:20.626519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:10:20.629748 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:10:20.636909 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 11:10:20.639848 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 11:10:20.643661 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 11:10:20.650071 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1879 11:10:20.653219 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1880 11:10:20.657027 Total UI for P1: 0, mck2ui 16
1881 11:10:20.660259 best dqsien dly found for B0: ( 0, 14, 4)
1882 11:10:20.663514 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 11:10:20.666809 Total UI for P1: 0, mck2ui 16
1884 11:10:20.669733 best dqsien dly found for B1: ( 0, 14, 8)
1885 11:10:20.673210 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1886 11:10:20.676604 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1887 11:10:20.677113
1888 11:10:20.679874 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1889 11:10:20.686680 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1890 11:10:20.687210 [Gating] SW calibration Done
1891 11:10:20.687546 ==
1892 11:10:20.689979 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 11:10:20.696136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 11:10:20.696555 ==
1895 11:10:20.696884 RX Vref Scan: 0
1896 11:10:20.697186
1897 11:10:20.699762 RX Vref 0 -> 0, step: 1
1898 11:10:20.700174
1899 11:10:20.703064 RX Delay -130 -> 252, step: 16
1900 11:10:20.706418 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1901 11:10:20.709935 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1902 11:10:20.713356 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1903 11:10:20.719610 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1904 11:10:20.723399 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1905 11:10:20.726754 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1906 11:10:20.729846 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1907 11:10:20.732961 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1908 11:10:20.736687 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1909 11:10:20.743239 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1910 11:10:20.746530 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1911 11:10:20.750067 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1912 11:10:20.753118 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1913 11:10:20.759948 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1914 11:10:20.762909 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1915 11:10:20.766446 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1916 11:10:20.766971 ==
1917 11:10:20.770107 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 11:10:20.773150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 11:10:20.773706 ==
1920 11:10:20.776564 DQS Delay:
1921 11:10:20.777085 DQS0 = 0, DQS1 = 0
1922 11:10:20.779710 DQM Delay:
1923 11:10:20.780136 DQM0 = 77, DQM1 = 72
1924 11:10:20.780570 DQ Delay:
1925 11:10:20.783405 DQ0 =77, DQ1 =69, DQ2 =61, DQ3 =77
1926 11:10:20.786495 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1927 11:10:20.789929 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1928 11:10:20.793500 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1929 11:10:20.794028
1930 11:10:20.794470
1931 11:10:20.794874 ==
1932 11:10:20.796629 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 11:10:20.803044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 11:10:20.803476 ==
1935 11:10:20.803913
1936 11:10:20.804321
1937 11:10:20.804720 TX Vref Scan disable
1938 11:10:20.806612 == TX Byte 0 ==
1939 11:10:20.809989 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1940 11:10:20.816801 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1941 11:10:20.817321 == TX Byte 1 ==
1942 11:10:20.820473 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1943 11:10:20.827078 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1944 11:10:20.827604 ==
1945 11:10:20.830138 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 11:10:20.833170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 11:10:20.833641 ==
1948 11:10:20.846439 TX Vref=22, minBit 9, minWin=27, winSum=453
1949 11:10:20.850059 TX Vref=24, minBit 0, minWin=28, winSum=456
1950 11:10:20.853383 TX Vref=26, minBit 1, minWin=28, winSum=458
1951 11:10:20.856903 TX Vref=28, minBit 1, minWin=28, winSum=461
1952 11:10:20.859916 TX Vref=30, minBit 1, minWin=28, winSum=463
1953 11:10:20.863191 TX Vref=32, minBit 5, minWin=27, winSum=461
1954 11:10:20.870025 [TxChooseVref] Worse bit 1, Min win 28, Win sum 463, Final Vref 30
1955 11:10:20.870598
1956 11:10:20.873005 Final TX Range 1 Vref 30
1957 11:10:20.873417
1958 11:10:20.873795 ==
1959 11:10:20.876817 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 11:10:20.879626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 11:10:20.880138 ==
1962 11:10:20.880464
1963 11:10:20.883399
1964 11:10:20.883903 TX Vref Scan disable
1965 11:10:20.886745 == TX Byte 0 ==
1966 11:10:20.890302 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1967 11:10:20.893014 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1968 11:10:20.896762 == TX Byte 1 ==
1969 11:10:20.899905 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1970 11:10:20.903202 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1971 11:10:20.906520
1972 11:10:20.906925 [DATLAT]
1973 11:10:20.907249 Freq=800, CH1 RK1
1974 11:10:20.907550
1975 11:10:20.909672 DATLAT Default: 0xa
1976 11:10:20.910084 0, 0xFFFF, sum = 0
1977 11:10:20.913087 1, 0xFFFF, sum = 0
1978 11:10:20.913542 2, 0xFFFF, sum = 0
1979 11:10:20.916394 3, 0xFFFF, sum = 0
1980 11:10:20.916812 4, 0xFFFF, sum = 0
1981 11:10:20.919736 5, 0xFFFF, sum = 0
1982 11:10:20.923046 6, 0xFFFF, sum = 0
1983 11:10:20.923464 7, 0xFFFF, sum = 0
1984 11:10:20.926814 8, 0xFFFF, sum = 0
1985 11:10:20.927328 9, 0x0, sum = 1
1986 11:10:20.927664 10, 0x0, sum = 2
1987 11:10:20.929694 11, 0x0, sum = 3
1988 11:10:20.930113 12, 0x0, sum = 4
1989 11:10:20.933210 best_step = 10
1990 11:10:20.933663
1991 11:10:20.933994 ==
1992 11:10:20.936526 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 11:10:20.939609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 11:10:20.940027 ==
1995 11:10:20.943241 RX Vref Scan: 0
1996 11:10:20.943747
1997 11:10:20.944077 RX Vref 0 -> 0, step: 1
1998 11:10:20.944380
1999 11:10:20.946353 RX Delay -111 -> 252, step: 8
2000 11:10:20.953848 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2001 11:10:20.956845 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2002 11:10:20.960236 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2003 11:10:20.963249 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2004 11:10:20.966450 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2005 11:10:20.973347 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2006 11:10:20.976939 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2007 11:10:20.979609 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2008 11:10:20.983359 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2009 11:10:20.986401 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2010 11:10:20.992875 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2011 11:10:20.996415 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2012 11:10:20.999540 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2013 11:10:21.003047 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2014 11:10:21.009867 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2015 11:10:21.013177 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2016 11:10:21.013756 ==
2017 11:10:21.016306 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 11:10:21.019645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 11:10:21.020101 ==
2020 11:10:21.020530 DQS Delay:
2021 11:10:21.022967 DQS0 = 0, DQS1 = 0
2022 11:10:21.023392 DQM Delay:
2023 11:10:21.026108 DQM0 = 77, DQM1 = 74
2024 11:10:21.026523 DQ Delay:
2025 11:10:21.030002 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2026 11:10:21.032802 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2027 11:10:21.036535 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =64
2028 11:10:21.039351 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2029 11:10:21.039768
2030 11:10:21.040093
2031 11:10:21.050036 [DQSOSCAuto] RK1, (LSB)MR18= 0x2138, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2032 11:10:21.050553 CH1 RK1: MR19=606, MR18=2138
2033 11:10:21.056626 CH1_RK1: MR19=0x606, MR18=0x2138, DQSOSC=395, MR23=63, INC=94, DEC=63
2034 11:10:21.059628 [RxdqsGatingPostProcess] freq 800
2035 11:10:21.066356 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 11:10:21.069568 Pre-setting of DQS Precalculation
2037 11:10:21.072921 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 11:10:21.079167 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 11:10:21.089238 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 11:10:21.089785
2041 11:10:21.090117
2042 11:10:21.090437 [Calibration Summary] 1600 Mbps
2043 11:10:21.092422 CH 0, Rank 0
2044 11:10:21.095919 SW Impedance : PASS
2045 11:10:21.096340 DUTY Scan : NO K
2046 11:10:21.099389 ZQ Calibration : PASS
2047 11:10:21.099806 Jitter Meter : NO K
2048 11:10:21.103029 CBT Training : PASS
2049 11:10:21.105816 Write leveling : PASS
2050 11:10:21.106238 RX DQS gating : PASS
2051 11:10:21.109545 RX DQ/DQS(RDDQC) : PASS
2052 11:10:21.112955 TX DQ/DQS : PASS
2053 11:10:21.113523 RX DATLAT : PASS
2054 11:10:21.115998 RX DQ/DQS(Engine): PASS
2055 11:10:21.118965 TX OE : NO K
2056 11:10:21.119388 All Pass.
2057 11:10:21.119734
2058 11:10:21.120091 CH 0, Rank 1
2059 11:10:21.122576 SW Impedance : PASS
2060 11:10:21.125788 DUTY Scan : NO K
2061 11:10:21.126207 ZQ Calibration : PASS
2062 11:10:21.129324 Jitter Meter : NO K
2063 11:10:21.132541 CBT Training : PASS
2064 11:10:21.132959 Write leveling : PASS
2065 11:10:21.135675 RX DQS gating : PASS
2066 11:10:21.139231 RX DQ/DQS(RDDQC) : PASS
2067 11:10:21.139683 TX DQ/DQS : PASS
2068 11:10:21.142704 RX DATLAT : PASS
2069 11:10:21.143221 RX DQ/DQS(Engine): PASS
2070 11:10:21.146065 TX OE : NO K
2071 11:10:21.146591 All Pass.
2072 11:10:21.146982
2073 11:10:21.149287 CH 1, Rank 0
2074 11:10:21.149839 SW Impedance : PASS
2075 11:10:21.152513 DUTY Scan : NO K
2076 11:10:21.155823 ZQ Calibration : PASS
2077 11:10:21.156340 Jitter Meter : NO K
2078 11:10:21.159343 CBT Training : PASS
2079 11:10:21.162514 Write leveling : PASS
2080 11:10:21.163039 RX DQS gating : PASS
2081 11:10:21.165613 RX DQ/DQS(RDDQC) : PASS
2082 11:10:21.169229 TX DQ/DQS : PASS
2083 11:10:21.169811 RX DATLAT : PASS
2084 11:10:21.172708 RX DQ/DQS(Engine): PASS
2085 11:10:21.175907 TX OE : NO K
2086 11:10:21.176430 All Pass.
2087 11:10:21.176764
2088 11:10:21.177067 CH 1, Rank 1
2089 11:10:21.178934 SW Impedance : PASS
2090 11:10:21.182286 DUTY Scan : NO K
2091 11:10:21.182801 ZQ Calibration : PASS
2092 11:10:21.185923 Jitter Meter : NO K
2093 11:10:21.189383 CBT Training : PASS
2094 11:10:21.189954 Write leveling : PASS
2095 11:10:21.192344 RX DQS gating : PASS
2096 11:10:21.192763 RX DQ/DQS(RDDQC) : PASS
2097 11:10:21.195817 TX DQ/DQS : PASS
2098 11:10:21.199027 RX DATLAT : PASS
2099 11:10:21.199454 RX DQ/DQS(Engine): PASS
2100 11:10:21.202337 TX OE : NO K
2101 11:10:21.202758 All Pass.
2102 11:10:21.203086
2103 11:10:21.205470 DramC Write-DBI off
2104 11:10:21.209264 PER_BANK_REFRESH: Hybrid Mode
2105 11:10:21.209869 TX_TRACKING: ON
2106 11:10:21.212700 [GetDramInforAfterCalByMRR] Vendor 6.
2107 11:10:21.215822 [GetDramInforAfterCalByMRR] Revision 606.
2108 11:10:21.219376 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 11:10:21.222240 MR0 0x3b3b
2110 11:10:21.222658 MR8 0x5151
2111 11:10:21.225863 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 11:10:21.226384
2113 11:10:21.229214 MR0 0x3b3b
2114 11:10:21.229783 MR8 0x5151
2115 11:10:21.232193 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 11:10:21.232614
2117 11:10:21.242183 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 11:10:21.246127 [FAST_K] Save calibration result to emmc
2119 11:10:21.248884 [FAST_K] Save calibration result to emmc
2120 11:10:21.252596 dram_init: config_dvfs: 1
2121 11:10:21.255328 dramc_set_vcore_voltage set vcore to 662500
2122 11:10:21.255763 Read voltage for 1200, 2
2123 11:10:21.259305 Vio18 = 0
2124 11:10:21.259853 Vcore = 662500
2125 11:10:21.260193 Vdram = 0
2126 11:10:21.262005 Vddq = 0
2127 11:10:21.262421 Vmddr = 0
2128 11:10:21.265327 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 11:10:21.271990 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 11:10:21.275393 MEM_TYPE=3, freq_sel=15
2131 11:10:21.278867 sv_algorithm_assistance_LP4_1600
2132 11:10:21.282245 ============ PULL DRAM RESETB DOWN ============
2133 11:10:21.285557 ========== PULL DRAM RESETB DOWN end =========
2134 11:10:21.292465 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 11:10:21.295651 ===================================
2136 11:10:21.296175 LPDDR4 DRAM CONFIGURATION
2137 11:10:21.298696 ===================================
2138 11:10:21.302201 EX_ROW_EN[0] = 0x0
2139 11:10:21.302618 EX_ROW_EN[1] = 0x0
2140 11:10:21.305532 LP4Y_EN = 0x0
2141 11:10:21.305953 WORK_FSP = 0x0
2142 11:10:21.308652 WL = 0x4
2143 11:10:21.309070 RL = 0x4
2144 11:10:21.312029 BL = 0x2
2145 11:10:21.312456 RPST = 0x0
2146 11:10:21.315338 RD_PRE = 0x0
2147 11:10:21.318514 WR_PRE = 0x1
2148 11:10:21.318933 WR_PST = 0x0
2149 11:10:21.321936 DBI_WR = 0x0
2150 11:10:21.322352 DBI_RD = 0x0
2151 11:10:21.325397 OTF = 0x1
2152 11:10:21.328743 ===================================
2153 11:10:21.331964 ===================================
2154 11:10:21.332383 ANA top config
2155 11:10:21.335484 ===================================
2156 11:10:21.338985 DLL_ASYNC_EN = 0
2157 11:10:21.339404 ALL_SLAVE_EN = 0
2158 11:10:21.342056 NEW_RANK_MODE = 1
2159 11:10:21.345405 DLL_IDLE_MODE = 1
2160 11:10:21.348958 LP45_APHY_COMB_EN = 1
2161 11:10:21.352151 TX_ODT_DIS = 1
2162 11:10:21.352676 NEW_8X_MODE = 1
2163 11:10:21.355830 ===================================
2164 11:10:21.358924 ===================================
2165 11:10:21.362234 data_rate = 2400
2166 11:10:21.365639 CKR = 1
2167 11:10:21.368854 DQ_P2S_RATIO = 8
2168 11:10:21.372274 ===================================
2169 11:10:21.375605 CA_P2S_RATIO = 8
2170 11:10:21.378969 DQ_CA_OPEN = 0
2171 11:10:21.379495 DQ_SEMI_OPEN = 0
2172 11:10:21.382164 CA_SEMI_OPEN = 0
2173 11:10:21.385652 CA_FULL_RATE = 0
2174 11:10:21.388911 DQ_CKDIV4_EN = 0
2175 11:10:21.392317 CA_CKDIV4_EN = 0
2176 11:10:21.392737 CA_PREDIV_EN = 0
2177 11:10:21.395580 PH8_DLY = 17
2178 11:10:21.398538 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 11:10:21.402115 DQ_AAMCK_DIV = 4
2180 11:10:21.405356 CA_AAMCK_DIV = 4
2181 11:10:21.408727 CA_ADMCK_DIV = 4
2182 11:10:21.409141 DQ_TRACK_CA_EN = 0
2183 11:10:21.412449 CA_PICK = 1200
2184 11:10:21.415824 CA_MCKIO = 1200
2185 11:10:21.418995 MCKIO_SEMI = 0
2186 11:10:21.422020 PLL_FREQ = 2366
2187 11:10:21.425794 DQ_UI_PI_RATIO = 32
2188 11:10:21.428852 CA_UI_PI_RATIO = 0
2189 11:10:21.432461 ===================================
2190 11:10:21.435387 ===================================
2191 11:10:21.435908 memory_type:LPDDR4
2192 11:10:21.438916 GP_NUM : 10
2193 11:10:21.441800 SRAM_EN : 1
2194 11:10:21.442220 MD32_EN : 0
2195 11:10:21.445264 ===================================
2196 11:10:21.448590 [ANA_INIT] >>>>>>>>>>>>>>
2197 11:10:21.452321 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 11:10:21.455660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 11:10:21.458959 ===================================
2200 11:10:21.462334 data_rate = 2400,PCW = 0X5b00
2201 11:10:21.465624 ===================================
2202 11:10:21.468999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 11:10:21.472071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 11:10:21.478868 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 11:10:21.482063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 11:10:21.485565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 11:10:21.488615 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 11:10:21.491648 [ANA_INIT] flow start
2209 11:10:21.494965 [ANA_INIT] PLL >>>>>>>>
2210 11:10:21.495383 [ANA_INIT] PLL <<<<<<<<
2211 11:10:21.498376 [ANA_INIT] MIDPI >>>>>>>>
2212 11:10:21.501552 [ANA_INIT] MIDPI <<<<<<<<
2213 11:10:21.504829 [ANA_INIT] DLL >>>>>>>>
2214 11:10:21.505248 [ANA_INIT] DLL <<<<<<<<
2215 11:10:21.508138 [ANA_INIT] flow end
2216 11:10:21.511756 ============ LP4 DIFF to SE enter ============
2217 11:10:21.515271 ============ LP4 DIFF to SE exit ============
2218 11:10:21.518174 [ANA_INIT] <<<<<<<<<<<<<
2219 11:10:21.521708 [Flow] Enable top DCM control >>>>>
2220 11:10:21.525042 [Flow] Enable top DCM control <<<<<
2221 11:10:21.528327 Enable DLL master slave shuffle
2222 11:10:21.535468 ==============================================================
2223 11:10:21.535979 Gating Mode config
2224 11:10:21.541966 ==============================================================
2225 11:10:21.542477 Config description:
2226 11:10:21.551674 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 11:10:21.558143 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 11:10:21.565225 SELPH_MODE 0: By rank 1: By Phase
2229 11:10:21.568418 ==============================================================
2230 11:10:21.571750 GAT_TRACK_EN = 1
2231 11:10:21.574906 RX_GATING_MODE = 2
2232 11:10:21.578414 RX_GATING_TRACK_MODE = 2
2233 11:10:21.581644 SELPH_MODE = 1
2234 11:10:21.585184 PICG_EARLY_EN = 1
2235 11:10:21.588550 VALID_LAT_VALUE = 1
2236 11:10:21.591588 ==============================================================
2237 11:10:21.594851 Enter into Gating configuration >>>>
2238 11:10:21.597957 Exit from Gating configuration <<<<
2239 11:10:21.601667 Enter into DVFS_PRE_config >>>>>
2240 11:10:21.615085 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 11:10:21.618293 Exit from DVFS_PRE_config <<<<<
2242 11:10:21.621263 Enter into PICG configuration >>>>
2243 11:10:21.621721 Exit from PICG configuration <<<<
2244 11:10:21.625316 [RX_INPUT] configuration >>>>>
2245 11:10:21.628628 [RX_INPUT] configuration <<<<<
2246 11:10:21.634746 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 11:10:21.638198 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 11:10:21.645108 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 11:10:21.651909 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 11:10:21.658546 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 11:10:21.664931 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 11:10:21.668073 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 11:10:21.671811 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 11:10:21.674621 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 11:10:21.681678 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 11:10:21.684684 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 11:10:21.688230 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 11:10:21.691397 ===================================
2259 11:10:21.694601 LPDDR4 DRAM CONFIGURATION
2260 11:10:21.698135 ===================================
2261 11:10:21.701148 EX_ROW_EN[0] = 0x0
2262 11:10:21.701615 EX_ROW_EN[1] = 0x0
2263 11:10:21.704493 LP4Y_EN = 0x0
2264 11:10:21.704908 WORK_FSP = 0x0
2265 11:10:21.708178 WL = 0x4
2266 11:10:21.708690 RL = 0x4
2267 11:10:21.711668 BL = 0x2
2268 11:10:21.712184 RPST = 0x0
2269 11:10:21.714763 RD_PRE = 0x0
2270 11:10:21.715181 WR_PRE = 0x1
2271 11:10:21.718130 WR_PST = 0x0
2272 11:10:21.718546 DBI_WR = 0x0
2273 11:10:21.721243 DBI_RD = 0x0
2274 11:10:21.721806 OTF = 0x1
2275 11:10:21.724941 ===================================
2276 11:10:21.728285 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 11:10:21.734699 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 11:10:21.738413 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 11:10:21.741715 ===================================
2280 11:10:21.744933 LPDDR4 DRAM CONFIGURATION
2281 11:10:21.748105 ===================================
2282 11:10:21.748617 EX_ROW_EN[0] = 0x10
2283 11:10:21.751695 EX_ROW_EN[1] = 0x0
2284 11:10:21.754960 LP4Y_EN = 0x0
2285 11:10:21.755472 WORK_FSP = 0x0
2286 11:10:21.758128 WL = 0x4
2287 11:10:21.758647 RL = 0x4
2288 11:10:21.761146 BL = 0x2
2289 11:10:21.761605 RPST = 0x0
2290 11:10:21.765017 RD_PRE = 0x0
2291 11:10:21.765576 WR_PRE = 0x1
2292 11:10:21.767832 WR_PST = 0x0
2293 11:10:21.768429 DBI_WR = 0x0
2294 11:10:21.771149 DBI_RD = 0x0
2295 11:10:21.771671 OTF = 0x1
2296 11:10:21.774522 ===================================
2297 11:10:21.781314 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 11:10:21.781811 ==
2299 11:10:21.784777 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 11:10:21.788157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 11:10:21.788575 ==
2302 11:10:21.791191 [Duty_Offset_Calibration]
2303 11:10:21.794541 B0:2 B1:0 CA:3
2304 11:10:21.794833
2305 11:10:21.797727 [DutyScan_Calibration_Flow] k_type=0
2306 11:10:21.805796
2307 11:10:21.806092 ==CLK 0==
2308 11:10:21.809000 Final CLK duty delay cell = 0
2309 11:10:21.812526 [0] MAX Duty = 5031%(X100), DQS PI = 12
2310 11:10:21.816051 [0] MIN Duty = 4906%(X100), DQS PI = 54
2311 11:10:21.816552 [0] AVG Duty = 4968%(X100)
2312 11:10:21.819434
2313 11:10:21.819846 CH0 CLK Duty spec in!! Max-Min= 125%
2314 11:10:21.825942 [DutyScan_Calibration_Flow] ====Done====
2315 11:10:21.826454
2316 11:10:21.829333 [DutyScan_Calibration_Flow] k_type=1
2317 11:10:21.844559
2318 11:10:21.845060 ==DQS 0 ==
2319 11:10:21.847940 Final DQS duty delay cell = 0
2320 11:10:21.851491 [0] MAX Duty = 5062%(X100), DQS PI = 12
2321 11:10:21.854587 [0] MIN Duty = 4907%(X100), DQS PI = 0
2322 11:10:21.855005 [0] AVG Duty = 4984%(X100)
2323 11:10:21.857683
2324 11:10:21.858180 ==DQS 1 ==
2325 11:10:21.861045 Final DQS duty delay cell = -4
2326 11:10:21.864626 [-4] MAX Duty = 4969%(X100), DQS PI = 8
2327 11:10:21.868109 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2328 11:10:21.870737 [-4] AVG Duty = 4938%(X100)
2329 11:10:21.871156
2330 11:10:21.874208 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2331 11:10:21.874622
2332 11:10:21.877937 CH0 DQS 1 Duty spec in!! Max-Min= 62%
2333 11:10:21.881361 [DutyScan_Calibration_Flow] ====Done====
2334 11:10:21.881914
2335 11:10:21.884716 [DutyScan_Calibration_Flow] k_type=3
2336 11:10:21.901520
2337 11:10:21.902021 ==DQM 0 ==
2338 11:10:21.904731 Final DQM duty delay cell = 0
2339 11:10:21.908551 [0] MAX Duty = 5124%(X100), DQS PI = 12
2340 11:10:21.911825 [0] MIN Duty = 4876%(X100), DQS PI = 0
2341 11:10:21.912331 [0] AVG Duty = 5000%(X100)
2342 11:10:21.914962
2343 11:10:21.915375 ==DQM 1 ==
2344 11:10:21.918203 Final DQM duty delay cell = 4
2345 11:10:21.921650 [4] MAX Duty = 5124%(X100), DQS PI = 50
2346 11:10:21.925247 [4] MIN Duty = 5000%(X100), DQS PI = 14
2347 11:10:21.928294 [4] AVG Duty = 5062%(X100)
2348 11:10:21.928797
2349 11:10:21.931971 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2350 11:10:21.932478
2351 11:10:21.934676 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2352 11:10:21.938403 [DutyScan_Calibration_Flow] ====Done====
2353 11:10:21.938912
2354 11:10:21.941436 [DutyScan_Calibration_Flow] k_type=2
2355 11:10:21.957103
2356 11:10:21.957658 ==DQ 0 ==
2357 11:10:21.960137 Final DQ duty delay cell = -4
2358 11:10:21.963508 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2359 11:10:21.966744 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2360 11:10:21.970409 [-4] AVG Duty = 4953%(X100)
2361 11:10:21.970913
2362 11:10:21.971242 ==DQ 1 ==
2363 11:10:21.973357 Final DQ duty delay cell = -4
2364 11:10:21.976915 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2365 11:10:21.979982 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2366 11:10:21.983177 [-4] AVG Duty = 4922%(X100)
2367 11:10:21.983679
2368 11:10:21.986720 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2369 11:10:21.987232
2370 11:10:21.989948 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2371 11:10:21.993247 [DutyScan_Calibration_Flow] ====Done====
2372 11:10:21.993865 ==
2373 11:10:21.996770 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 11:10:21.999858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 11:10:22.000279 ==
2376 11:10:22.003471 [Duty_Offset_Calibration]
2377 11:10:22.003886 B0:1 B1:-2 CA:0
2378 11:10:22.004218
2379 11:10:22.006384 [DutyScan_Calibration_Flow] k_type=0
2380 11:10:22.017336
2381 11:10:22.017969 ==CLK 0==
2382 11:10:22.020290 Final CLK duty delay cell = 0
2383 11:10:22.023466 [0] MAX Duty = 5031%(X100), DQS PI = 16
2384 11:10:22.026975 [0] MIN Duty = 4876%(X100), DQS PI = 2
2385 11:10:22.027388 [0] AVG Duty = 4953%(X100)
2386 11:10:22.030265
2387 11:10:22.030675 CH1 CLK Duty spec in!! Max-Min= 155%
2388 11:10:22.037269 [DutyScan_Calibration_Flow] ====Done====
2389 11:10:22.037856
2390 11:10:22.039887 [DutyScan_Calibration_Flow] k_type=1
2391 11:10:22.055608
2392 11:10:22.056112 ==DQS 0 ==
2393 11:10:22.059030 Final DQS duty delay cell = -4
2394 11:10:22.062173 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2395 11:10:22.065618 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2396 11:10:22.068710 [-4] AVG Duty = 4969%(X100)
2397 11:10:22.069220
2398 11:10:22.069622 ==DQS 1 ==
2399 11:10:22.071691 Final DQS duty delay cell = 0
2400 11:10:22.075428 [0] MAX Duty = 5093%(X100), DQS PI = 0
2401 11:10:22.078472 [0] MIN Duty = 4875%(X100), DQS PI = 26
2402 11:10:22.082046 [0] AVG Duty = 4984%(X100)
2403 11:10:22.082560
2404 11:10:22.085201 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2405 11:10:22.085732
2406 11:10:22.088755 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2407 11:10:22.092160 [DutyScan_Calibration_Flow] ====Done====
2408 11:10:22.092670
2409 11:10:22.094913 [DutyScan_Calibration_Flow] k_type=3
2410 11:10:22.112476
2411 11:10:22.112985 ==DQM 0 ==
2412 11:10:22.115396 Final DQM duty delay cell = 0
2413 11:10:22.118920 [0] MAX Duty = 5000%(X100), DQS PI = 22
2414 11:10:22.122211 [0] MIN Duty = 4844%(X100), DQS PI = 52
2415 11:10:22.125732 [0] AVG Duty = 4922%(X100)
2416 11:10:22.126238
2417 11:10:22.126622 ==DQM 1 ==
2418 11:10:22.128784 Final DQM duty delay cell = 0
2419 11:10:22.132127 [0] MAX Duty = 5031%(X100), DQS PI = 34
2420 11:10:22.135456 [0] MIN Duty = 4907%(X100), DQS PI = 2
2421 11:10:22.135877 [0] AVG Duty = 4969%(X100)
2422 11:10:22.138773
2423 11:10:22.142027 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2424 11:10:22.142451
2425 11:10:22.145413 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2426 11:10:22.148929 [DutyScan_Calibration_Flow] ====Done====
2427 11:10:22.149439
2428 11:10:22.152081 [DutyScan_Calibration_Flow] k_type=2
2429 11:10:22.168920
2430 11:10:22.169439 ==DQ 0 ==
2431 11:10:22.172025 Final DQ duty delay cell = 0
2432 11:10:22.175664 [0] MAX Duty = 5062%(X100), DQS PI = 18
2433 11:10:22.178778 [0] MIN Duty = 4938%(X100), DQS PI = 54
2434 11:10:22.179285 [0] AVG Duty = 5000%(X100)
2435 11:10:22.179614
2436 11:10:22.182116 ==DQ 1 ==
2437 11:10:22.185715 Final DQ duty delay cell = 0
2438 11:10:22.188628 [0] MAX Duty = 5093%(X100), DQS PI = 20
2439 11:10:22.192059 [0] MIN Duty = 4969%(X100), DQS PI = 26
2440 11:10:22.192479 [0] AVG Duty = 5031%(X100)
2441 11:10:22.192811
2442 11:10:22.195191 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2443 11:10:22.195612
2444 11:10:22.198818 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2445 11:10:22.205316 [DutyScan_Calibration_Flow] ====Done====
2446 11:10:22.208940 nWR fixed to 30
2447 11:10:22.209465 [ModeRegInit_LP4] CH0 RK0
2448 11:10:22.212329 [ModeRegInit_LP4] CH0 RK1
2449 11:10:22.215399 [ModeRegInit_LP4] CH1 RK0
2450 11:10:22.215819 [ModeRegInit_LP4] CH1 RK1
2451 11:10:22.218563 match AC timing 7
2452 11:10:22.221638 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 11:10:22.225120 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 11:10:22.231998 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 11:10:22.235175 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 11:10:22.241672 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 11:10:22.242099 ==
2458 11:10:22.245107 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 11:10:22.248556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 11:10:22.248979 ==
2461 11:10:22.255445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 11:10:22.258332 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2463 11:10:22.268598 [CA 0] Center 40 (10~71) winsize 62
2464 11:10:22.271683 [CA 1] Center 39 (9~70) winsize 62
2465 11:10:22.275101 [CA 2] Center 36 (6~66) winsize 61
2466 11:10:22.278136 [CA 3] Center 35 (5~66) winsize 62
2467 11:10:22.281919 [CA 4] Center 34 (4~65) winsize 62
2468 11:10:22.285142 [CA 5] Center 33 (3~64) winsize 62
2469 11:10:22.285599
2470 11:10:22.288557 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2471 11:10:22.288882
2472 11:10:22.291812 [CATrainingPosCal] consider 1 rank data
2473 11:10:22.295211 u2DelayCellTimex100 = 270/100 ps
2474 11:10:22.298190 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2475 11:10:22.301544 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2476 11:10:22.308122 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2477 11:10:22.311431 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2478 11:10:22.315137 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2479 11:10:22.318520 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2480 11:10:22.318726
2481 11:10:22.321802 CA PerBit enable=1, Macro0, CA PI delay=33
2482 11:10:22.322019
2483 11:10:22.325366 [CBTSetCACLKResult] CA Dly = 33
2484 11:10:22.325603 CS Dly: 7 (0~38)
2485 11:10:22.325728 ==
2486 11:10:22.328763 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 11:10:22.335459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 11:10:22.335689 ==
2489 11:10:22.338488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 11:10:22.345573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2491 11:10:22.354710 [CA 0] Center 40 (10~70) winsize 61
2492 11:10:22.358029 [CA 1] Center 39 (9~70) winsize 62
2493 11:10:22.361535 [CA 2] Center 35 (5~66) winsize 62
2494 11:10:22.364622 [CA 3] Center 35 (5~66) winsize 62
2495 11:10:22.367883 [CA 4] Center 34 (4~65) winsize 62
2496 11:10:22.371335 [CA 5] Center 33 (3~64) winsize 62
2497 11:10:22.371769
2498 11:10:22.374600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2499 11:10:22.375022
2500 11:10:22.378018 [CATrainingPosCal] consider 2 rank data
2501 11:10:22.381340 u2DelayCellTimex100 = 270/100 ps
2502 11:10:22.384596 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2503 11:10:22.387788 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2504 11:10:22.394499 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2505 11:10:22.397948 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 11:10:22.401333 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2507 11:10:22.404797 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2508 11:10:22.405213
2509 11:10:22.407760 CA PerBit enable=1, Macro0, CA PI delay=33
2510 11:10:22.408182
2511 11:10:22.411247 [CBTSetCACLKResult] CA Dly = 33
2512 11:10:22.411664 CS Dly: 8 (0~40)
2513 11:10:22.411994
2514 11:10:22.414544 ----->DramcWriteLeveling(PI) begin...
2515 11:10:22.417858 ==
2516 11:10:22.421023 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 11:10:22.424321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 11:10:22.424547 ==
2519 11:10:22.427574 Write leveling (Byte 0): 31 => 31
2520 11:10:22.431171 Write leveling (Byte 1): 31 => 31
2521 11:10:22.434270 DramcWriteLeveling(PI) end<-----
2522 11:10:22.434422
2523 11:10:22.434541 ==
2524 11:10:22.437874 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 11:10:22.441317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 11:10:22.441681 ==
2527 11:10:22.444606 [Gating] SW mode calibration
2528 11:10:22.451448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 11:10:22.454642 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 11:10:22.461297 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 11:10:22.464534 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
2532 11:10:22.467860 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 11:10:22.474852 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 11:10:22.477800 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 11:10:22.481388 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 11:10:22.488306 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 11:10:22.491581 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2538 11:10:22.494785 1 0 0 | B1->B0 | 3232 2c2c | 1 0 | (1 0) (0 0)
2539 11:10:22.501448 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 11:10:22.504918 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 11:10:22.507981 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 11:10:22.514785 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 11:10:22.518271 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 11:10:22.521024 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 11:10:22.527949 1 0 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2546 11:10:22.531097 1 1 0 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
2547 11:10:22.534516 1 1 4 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2548 11:10:22.540890 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 11:10:22.544485 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 11:10:22.548044 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 11:10:22.554184 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 11:10:22.557793 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 11:10:22.561301 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2554 11:10:22.567711 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2555 11:10:22.571478 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:10:22.574553 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:10:22.581153 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:10:22.584380 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:10:22.587776 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:10:22.591087 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:10:22.597752 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:10:22.600860 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:10:22.604046 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:10:22.610820 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:10:22.614173 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 11:10:22.617295 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 11:10:22.624340 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 11:10:22.627591 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 11:10:22.631132 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 11:10:22.637580 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2571 11:10:22.641017 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2572 11:10:22.644377 Total UI for P1: 0, mck2ui 16
2573 11:10:22.648001 best dqsien dly found for B0: ( 1, 3, 30)
2574 11:10:22.651074 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 11:10:22.654640 Total UI for P1: 0, mck2ui 16
2576 11:10:22.658061 best dqsien dly found for B1: ( 1, 4, 4)
2577 11:10:22.661025 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2578 11:10:22.664551 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2579 11:10:22.665070
2580 11:10:22.667709 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2581 11:10:22.674614 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2582 11:10:22.675139 [Gating] SW calibration Done
2583 11:10:22.675479 ==
2584 11:10:22.678081 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 11:10:22.684463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 11:10:22.684997 ==
2587 11:10:22.685332 RX Vref Scan: 0
2588 11:10:22.685684
2589 11:10:22.687676 RX Vref 0 -> 0, step: 1
2590 11:10:22.688091
2591 11:10:22.690850 RX Delay -40 -> 252, step: 8
2592 11:10:22.694136 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2593 11:10:22.697834 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2594 11:10:22.700826 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2595 11:10:22.707848 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2596 11:10:22.711083 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2597 11:10:22.714053 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2598 11:10:22.717789 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2599 11:10:22.721031 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2600 11:10:22.724394 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2601 11:10:22.730915 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2602 11:10:22.734017 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2603 11:10:22.737841 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2604 11:10:22.740741 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2605 11:10:22.744251 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2606 11:10:22.750963 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2607 11:10:22.754106 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2608 11:10:22.754522 ==
2609 11:10:22.757521 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 11:10:22.760759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 11:10:22.761271 ==
2612 11:10:22.764109 DQS Delay:
2613 11:10:22.764525 DQS0 = 0, DQS1 = 0
2614 11:10:22.764853 DQM Delay:
2615 11:10:22.767297 DQM0 = 112, DQM1 = 101
2616 11:10:22.767725 DQ Delay:
2617 11:10:22.770705 DQ0 =111, DQ1 =115, DQ2 =111, DQ3 =107
2618 11:10:22.774069 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2619 11:10:22.777347 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2620 11:10:22.783918 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =111
2621 11:10:22.784435
2622 11:10:22.784766
2623 11:10:22.785072 ==
2624 11:10:22.787084 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 11:10:22.790808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 11:10:22.791321 ==
2627 11:10:22.791653
2628 11:10:22.791957
2629 11:10:22.793695 TX Vref Scan disable
2630 11:10:22.794105 == TX Byte 0 ==
2631 11:10:22.800510 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2632 11:10:22.803593 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2633 11:10:22.804007 == TX Byte 1 ==
2634 11:10:22.810492 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2635 11:10:22.813572 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2636 11:10:22.814010 ==
2637 11:10:22.816919 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 11:10:22.820502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 11:10:22.821141 ==
2640 11:10:22.833347 TX Vref=22, minBit 12, minWin=25, winSum=417
2641 11:10:22.836436 TX Vref=24, minBit 1, minWin=26, winSum=425
2642 11:10:22.839557 TX Vref=26, minBit 4, minWin=26, winSum=431
2643 11:10:22.842935 TX Vref=28, minBit 5, minWin=26, winSum=434
2644 11:10:22.846537 TX Vref=30, minBit 12, minWin=26, winSum=437
2645 11:10:22.853217 TX Vref=32, minBit 2, minWin=26, winSum=430
2646 11:10:22.856470 [TxChooseVref] Worse bit 12, Min win 26, Win sum 437, Final Vref 30
2647 11:10:22.856975
2648 11:10:22.859570 Final TX Range 1 Vref 30
2649 11:10:22.860116
2650 11:10:22.860582 ==
2651 11:10:22.863172 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 11:10:22.866314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 11:10:22.869219 ==
2654 11:10:22.869718
2655 11:10:22.870042
2656 11:10:22.870341 TX Vref Scan disable
2657 11:10:22.872861 == TX Byte 0 ==
2658 11:10:22.876206 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2659 11:10:22.879455 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2660 11:10:22.883154 == TX Byte 1 ==
2661 11:10:22.886449 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2662 11:10:22.892923 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2663 11:10:22.893588
2664 11:10:22.894062 [DATLAT]
2665 11:10:22.894506 Freq=1200, CH0 RK0
2666 11:10:22.894942
2667 11:10:22.896208 DATLAT Default: 0xd
2668 11:10:22.896621 0, 0xFFFF, sum = 0
2669 11:10:22.899650 1, 0xFFFF, sum = 0
2670 11:10:22.900208 2, 0xFFFF, sum = 0
2671 11:10:22.902837 3, 0xFFFF, sum = 0
2672 11:10:22.906189 4, 0xFFFF, sum = 0
2673 11:10:22.906608 5, 0xFFFF, sum = 0
2674 11:10:22.909275 6, 0xFFFF, sum = 0
2675 11:10:22.909763 7, 0xFFFF, sum = 0
2676 11:10:22.912798 8, 0xFFFF, sum = 0
2677 11:10:22.913321 9, 0xFFFF, sum = 0
2678 11:10:22.916086 10, 0xFFFF, sum = 0
2679 11:10:22.916609 11, 0xFFFF, sum = 0
2680 11:10:22.919466 12, 0x0, sum = 1
2681 11:10:22.920021 13, 0x0, sum = 2
2682 11:10:22.922885 14, 0x0, sum = 3
2683 11:10:22.923536 15, 0x0, sum = 4
2684 11:10:22.924130 best_step = 13
2685 11:10:22.926268
2686 11:10:22.926678 ==
2687 11:10:22.929452 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 11:10:22.932836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 11:10:22.933344 ==
2690 11:10:22.933738 RX Vref Scan: 1
2691 11:10:22.934049
2692 11:10:22.936250 Set Vref Range= 32 -> 127
2693 11:10:22.936753
2694 11:10:22.939658 RX Vref 32 -> 127, step: 1
2695 11:10:22.940204
2696 11:10:22.943028 RX Delay -37 -> 252, step: 4
2697 11:10:22.943591
2698 11:10:22.946082 Set Vref, RX VrefLevel [Byte0]: 32
2699 11:10:22.949680 [Byte1]: 32
2700 11:10:22.950182
2701 11:10:22.953043 Set Vref, RX VrefLevel [Byte0]: 33
2702 11:10:22.956320 [Byte1]: 33
2703 11:10:22.959714
2704 11:10:22.960143 Set Vref, RX VrefLevel [Byte0]: 34
2705 11:10:22.963323 [Byte1]: 34
2706 11:10:22.967724
2707 11:10:22.968359 Set Vref, RX VrefLevel [Byte0]: 35
2708 11:10:22.971146 [Byte1]: 35
2709 11:10:22.975937
2710 11:10:22.976721 Set Vref, RX VrefLevel [Byte0]: 36
2711 11:10:22.979256 [Byte1]: 36
2712 11:10:22.983816
2713 11:10:22.984335 Set Vref, RX VrefLevel [Byte0]: 37
2714 11:10:22.986966 [Byte1]: 37
2715 11:10:22.991627
2716 11:10:22.992039 Set Vref, RX VrefLevel [Byte0]: 38
2717 11:10:22.995017 [Byte1]: 38
2718 11:10:22.999664
2719 11:10:23.000306 Set Vref, RX VrefLevel [Byte0]: 39
2720 11:10:23.002783 [Byte1]: 39
2721 11:10:23.007688
2722 11:10:23.008236 Set Vref, RX VrefLevel [Byte0]: 40
2723 11:10:23.010599 [Byte1]: 40
2724 11:10:23.015742
2725 11:10:23.016304 Set Vref, RX VrefLevel [Byte0]: 41
2726 11:10:23.018728 [Byte1]: 41
2727 11:10:23.023653
2728 11:10:23.024065 Set Vref, RX VrefLevel [Byte0]: 42
2729 11:10:23.026975 [Byte1]: 42
2730 11:10:23.031815
2731 11:10:23.032322 Set Vref, RX VrefLevel [Byte0]: 43
2732 11:10:23.035175 [Byte1]: 43
2733 11:10:23.039674
2734 11:10:23.040085 Set Vref, RX VrefLevel [Byte0]: 44
2735 11:10:23.042786 [Byte1]: 44
2736 11:10:23.047868
2737 11:10:23.048367 Set Vref, RX VrefLevel [Byte0]: 45
2738 11:10:23.050775 [Byte1]: 45
2739 11:10:23.055800
2740 11:10:23.056208 Set Vref, RX VrefLevel [Byte0]: 46
2741 11:10:23.059103 [Byte1]: 46
2742 11:10:23.063913
2743 11:10:23.064422 Set Vref, RX VrefLevel [Byte0]: 47
2744 11:10:23.067402 [Byte1]: 47
2745 11:10:23.072084
2746 11:10:23.072589 Set Vref, RX VrefLevel [Byte0]: 48
2747 11:10:23.075033 [Byte1]: 48
2748 11:10:23.079700
2749 11:10:23.080202 Set Vref, RX VrefLevel [Byte0]: 49
2750 11:10:23.083030 [Byte1]: 49
2751 11:10:23.087835
2752 11:10:23.088341 Set Vref, RX VrefLevel [Byte0]: 50
2753 11:10:23.090949 [Byte1]: 50
2754 11:10:23.095738
2755 11:10:23.096243 Set Vref, RX VrefLevel [Byte0]: 51
2756 11:10:23.098738 [Byte1]: 51
2757 11:10:23.103549
2758 11:10:23.103959 Set Vref, RX VrefLevel [Byte0]: 52
2759 11:10:23.107173 [Byte1]: 52
2760 11:10:23.111805
2761 11:10:23.112299 Set Vref, RX VrefLevel [Byte0]: 53
2762 11:10:23.114855 [Byte1]: 53
2763 11:10:23.119519
2764 11:10:23.119949 Set Vref, RX VrefLevel [Byte0]: 54
2765 11:10:23.122889 [Byte1]: 54
2766 11:10:23.127738
2767 11:10:23.128258 Set Vref, RX VrefLevel [Byte0]: 55
2768 11:10:23.130943 [Byte1]: 55
2769 11:10:23.135517
2770 11:10:23.136044 Set Vref, RX VrefLevel [Byte0]: 56
2771 11:10:23.138816 [Byte1]: 56
2772 11:10:23.143834
2773 11:10:23.144471 Set Vref, RX VrefLevel [Byte0]: 57
2774 11:10:23.146733 [Byte1]: 57
2775 11:10:23.151690
2776 11:10:23.152327 Set Vref, RX VrefLevel [Byte0]: 58
2777 11:10:23.155021 [Byte1]: 58
2778 11:10:23.159687
2779 11:10:23.160230 Set Vref, RX VrefLevel [Byte0]: 59
2780 11:10:23.162918 [Byte1]: 59
2781 11:10:23.167704
2782 11:10:23.168205 Set Vref, RX VrefLevel [Byte0]: 60
2783 11:10:23.170994 [Byte1]: 60
2784 11:10:23.175799
2785 11:10:23.176300 Set Vref, RX VrefLevel [Byte0]: 61
2786 11:10:23.178958 [Byte1]: 61
2787 11:10:23.183779
2788 11:10:23.184280 Set Vref, RX VrefLevel [Byte0]: 62
2789 11:10:23.186724 [Byte1]: 62
2790 11:10:23.191843
2791 11:10:23.192372 Set Vref, RX VrefLevel [Byte0]: 63
2792 11:10:23.194889 [Byte1]: 63
2793 11:10:23.199895
2794 11:10:23.200623 Set Vref, RX VrefLevel [Byte0]: 64
2795 11:10:23.202905 [Byte1]: 64
2796 11:10:23.207776
2797 11:10:23.208292 Set Vref, RX VrefLevel [Byte0]: 65
2798 11:10:23.210882 [Byte1]: 65
2799 11:10:23.215811
2800 11:10:23.216221 Set Vref, RX VrefLevel [Byte0]: 66
2801 11:10:23.219145 [Byte1]: 66
2802 11:10:23.223869
2803 11:10:23.224408 Set Vref, RX VrefLevel [Byte0]: 67
2804 11:10:23.226866 [Byte1]: 67
2805 11:10:23.231764
2806 11:10:23.232265 Set Vref, RX VrefLevel [Byte0]: 68
2807 11:10:23.234934 [Byte1]: 68
2808 11:10:23.239655
2809 11:10:23.240085 Set Vref, RX VrefLevel [Byte0]: 69
2810 11:10:23.242975 [Byte1]: 69
2811 11:10:23.247797
2812 11:10:23.248302 Set Vref, RX VrefLevel [Byte0]: 70
2813 11:10:23.250813 [Byte1]: 70
2814 11:10:23.255867
2815 11:10:23.256419 Set Vref, RX VrefLevel [Byte0]: 71
2816 11:10:23.258822 [Byte1]: 71
2817 11:10:23.263671
2818 11:10:23.264319 Set Vref, RX VrefLevel [Byte0]: 72
2819 11:10:23.266690 [Byte1]: 72
2820 11:10:23.271642
2821 11:10:23.272321 Set Vref, RX VrefLevel [Byte0]: 73
2822 11:10:23.274779 [Byte1]: 73
2823 11:10:23.279598
2824 11:10:23.280145 Set Vref, RX VrefLevel [Byte0]: 74
2825 11:10:23.283157 [Byte1]: 74
2826 11:10:23.287563
2827 11:10:23.288110 Set Vref, RX VrefLevel [Byte0]: 75
2828 11:10:23.290989 [Byte1]: 75
2829 11:10:23.295647
2830 11:10:23.296192 Final RX Vref Byte 0 = 61 to rank0
2831 11:10:23.299000 Final RX Vref Byte 1 = 48 to rank0
2832 11:10:23.302135 Final RX Vref Byte 0 = 61 to rank1
2833 11:10:23.305845 Final RX Vref Byte 1 = 48 to rank1==
2834 11:10:23.308782 Dram Type= 6, Freq= 0, CH_0, rank 0
2835 11:10:23.315292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 11:10:23.315842 ==
2837 11:10:23.316311 DQS Delay:
2838 11:10:23.318694 DQS0 = 0, DQS1 = 0
2839 11:10:23.319304 DQM Delay:
2840 11:10:23.319777 DQM0 = 112, DQM1 = 98
2841 11:10:23.322156 DQ Delay:
2842 11:10:23.325167 DQ0 =110, DQ1 =114, DQ2 =110, DQ3 =108
2843 11:10:23.328696 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2844 11:10:23.332203 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =92
2845 11:10:23.335126 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2846 11:10:23.335672
2847 11:10:23.336139
2848 11:10:23.342124 [DQSOSCAuto] RK0, (LSB)MR18= 0xfafa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2849 11:10:23.345412 CH0 RK0: MR19=303, MR18=FAFA
2850 11:10:23.352045 CH0_RK0: MR19=0x303, MR18=0xFAFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2851 11:10:23.352667
2852 11:10:23.355455 ----->DramcWriteLeveling(PI) begin...
2853 11:10:23.356097 ==
2854 11:10:23.358630 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 11:10:23.362119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2856 11:10:23.365393 ==
2857 11:10:23.365941 Write leveling (Byte 0): 34 => 34
2858 11:10:23.368641 Write leveling (Byte 1): 32 => 32
2859 11:10:23.372056 DramcWriteLeveling(PI) end<-----
2860 11:10:23.372689
2861 11:10:23.373157 ==
2862 11:10:23.375610 Dram Type= 6, Freq= 0, CH_0, rank 1
2863 11:10:23.382781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2864 11:10:23.383290 ==
2865 11:10:23.383629 [Gating] SW mode calibration
2866 11:10:23.392108 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2867 11:10:23.395442 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2868 11:10:23.399165 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2869 11:10:23.405693 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 11:10:23.409399 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 11:10:23.411996 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 11:10:23.418984 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 11:10:23.422513 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2874 11:10:23.425167 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2875 11:10:23.431917 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2876 11:10:23.435368 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2877 11:10:23.438698 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 11:10:23.445427 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 11:10:23.448540 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 11:10:23.451874 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 11:10:23.458660 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 11:10:23.461647 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2883 11:10:23.464966 1 0 28 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
2884 11:10:23.471759 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2885 11:10:23.474869 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 11:10:23.478373 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 11:10:23.481550 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 11:10:23.488304 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 11:10:23.491678 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 11:10:23.495037 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 11:10:23.501407 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2892 11:10:23.504786 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2893 11:10:23.508034 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 11:10:23.514828 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 11:10:23.518284 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 11:10:23.521382 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 11:10:23.528453 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 11:10:23.531348 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 11:10:23.534777 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 11:10:23.541487 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 11:10:23.544998 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 11:10:23.548344 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 11:10:23.555068 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 11:10:23.558286 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 11:10:23.561838 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 11:10:23.568348 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 11:10:23.571810 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2908 11:10:23.575218 Total UI for P1: 0, mck2ui 16
2909 11:10:23.577952 best dqsien dly found for B0: ( 1, 3, 26)
2910 11:10:23.581726 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2911 11:10:23.584874 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 11:10:23.588288 Total UI for P1: 0, mck2ui 16
2913 11:10:23.591871 best dqsien dly found for B1: ( 1, 4, 0)
2914 11:10:23.598312 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2915 11:10:23.602016 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2916 11:10:23.602264
2917 11:10:23.604911 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2918 11:10:23.608257 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2919 11:10:23.612084 [Gating] SW calibration Done
2920 11:10:23.612417 ==
2921 11:10:23.615314 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 11:10:23.618428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 11:10:23.618741 ==
2924 11:10:23.618977 RX Vref Scan: 0
2925 11:10:23.621685
2926 11:10:23.621978 RX Vref 0 -> 0, step: 1
2927 11:10:23.622390
2928 11:10:23.625114 RX Delay -40 -> 252, step: 8
2929 11:10:23.628478 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2930 11:10:23.631904 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2931 11:10:23.638675 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2932 11:10:23.642122 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2933 11:10:23.645108 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2934 11:10:23.648393 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2935 11:10:23.651888 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2936 11:10:23.658321 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2937 11:10:23.661535 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2938 11:10:23.665088 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2939 11:10:23.668681 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2940 11:10:23.671830 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2941 11:10:23.678381 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2942 11:10:23.681728 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2943 11:10:23.685120 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2944 11:10:23.688416 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2945 11:10:23.688941 ==
2946 11:10:23.691632 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 11:10:23.697955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 11:10:23.698457 ==
2949 11:10:23.698786 DQS Delay:
2950 11:10:23.699084 DQS0 = 0, DQS1 = 0
2951 11:10:23.701419 DQM Delay:
2952 11:10:23.701868 DQM0 = 112, DQM1 = 100
2953 11:10:23.705147 DQ Delay:
2954 11:10:23.707965 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2955 11:10:23.711788 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2956 11:10:23.714784 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =95
2957 11:10:23.717851 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =107
2958 11:10:23.718268
2959 11:10:23.718598
2960 11:10:23.718901 ==
2961 11:10:23.721146 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 11:10:23.724827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 11:10:23.725353 ==
2964 11:10:23.727845
2965 11:10:23.728346
2966 11:10:23.728674 TX Vref Scan disable
2967 11:10:23.731148 == TX Byte 0 ==
2968 11:10:23.734713 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2969 11:10:23.738144 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2970 11:10:23.741127 == TX Byte 1 ==
2971 11:10:23.744918 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2972 11:10:23.748170 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2973 11:10:23.748595 ==
2974 11:10:23.751384 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 11:10:23.758140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 11:10:23.758653 ==
2977 11:10:23.769022 TX Vref=22, minBit 1, minWin=25, winSum=426
2978 11:10:23.772172 TX Vref=24, minBit 1, minWin=25, winSum=429
2979 11:10:23.775327 TX Vref=26, minBit 7, minWin=26, winSum=436
2980 11:10:23.778943 TX Vref=28, minBit 7, minWin=26, winSum=438
2981 11:10:23.782395 TX Vref=30, minBit 13, minWin=25, winSum=440
2982 11:10:23.789079 TX Vref=32, minBit 1, minWin=27, winSum=438
2983 11:10:23.791636 [TxChooseVref] Worse bit 1, Min win 27, Win sum 438, Final Vref 32
2984 11:10:23.792054
2985 11:10:23.795473 Final TX Range 1 Vref 32
2986 11:10:23.795998
2987 11:10:23.796332 ==
2988 11:10:23.798352 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 11:10:23.802260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 11:10:23.802841 ==
2991 11:10:23.805148
2992 11:10:23.805788
2993 11:10:23.806127 TX Vref Scan disable
2994 11:10:23.808901 == TX Byte 0 ==
2995 11:10:23.811857 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2996 11:10:23.818457 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2997 11:10:23.818973 == TX Byte 1 ==
2998 11:10:23.821559 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2999 11:10:23.828837 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3000 11:10:23.829356
3001 11:10:23.829729 [DATLAT]
3002 11:10:23.830037 Freq=1200, CH0 RK1
3003 11:10:23.830336
3004 11:10:23.832199 DATLAT Default: 0xd
3005 11:10:23.832710 0, 0xFFFF, sum = 0
3006 11:10:23.835044 1, 0xFFFF, sum = 0
3007 11:10:23.835620 2, 0xFFFF, sum = 0
3008 11:10:23.838386 3, 0xFFFF, sum = 0
3009 11:10:23.842031 4, 0xFFFF, sum = 0
3010 11:10:23.842548 5, 0xFFFF, sum = 0
3011 11:10:23.845380 6, 0xFFFF, sum = 0
3012 11:10:23.845932 7, 0xFFFF, sum = 0
3013 11:10:23.848416 8, 0xFFFF, sum = 0
3014 11:10:23.848933 9, 0xFFFF, sum = 0
3015 11:10:23.851672 10, 0xFFFF, sum = 0
3016 11:10:23.852190 11, 0xFFFF, sum = 0
3017 11:10:23.854866 12, 0x0, sum = 1
3018 11:10:23.855290 13, 0x0, sum = 2
3019 11:10:23.858455 14, 0x0, sum = 3
3020 11:10:23.858973 15, 0x0, sum = 4
3021 11:10:23.859311 best_step = 13
3022 11:10:23.862132
3023 11:10:23.862648 ==
3024 11:10:23.865031 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 11:10:23.868591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 11:10:23.869100 ==
3027 11:10:23.869434 RX Vref Scan: 0
3028 11:10:23.869853
3029 11:10:23.871529 RX Vref 0 -> 0, step: 1
3030 11:10:23.871945
3031 11:10:23.874872 RX Delay -37 -> 252, step: 4
3032 11:10:23.878377 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3033 11:10:23.885024 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3034 11:10:23.888389 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3035 11:10:23.891939 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3036 11:10:23.895235 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3037 11:10:23.898407 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3038 11:10:23.904927 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3039 11:10:23.908454 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3040 11:10:23.911890 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3041 11:10:23.914741 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3042 11:10:23.918210 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3043 11:10:23.921924 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3044 11:10:23.928192 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3045 11:10:23.931578 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3046 11:10:23.935060 iDelay=195, Bit 14, Center 112 (43 ~ 182) 140
3047 11:10:23.938004 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3048 11:10:23.938419 ==
3049 11:10:23.941974 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 11:10:23.948115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 11:10:23.948637 ==
3052 11:10:23.948970 DQS Delay:
3053 11:10:23.951728 DQS0 = 0, DQS1 = 0
3054 11:10:23.952235 DQM Delay:
3055 11:10:23.954944 DQM0 = 111, DQM1 = 100
3056 11:10:23.955359 DQ Delay:
3057 11:10:23.958256 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3058 11:10:23.961503 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =120
3059 11:10:23.965233 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =92
3060 11:10:23.968385 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3061 11:10:23.968889
3062 11:10:23.969214
3063 11:10:23.978286 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3064 11:10:23.978797 CH0 RK1: MR19=403, MR18=10F8
3065 11:10:23.984692 CH0_RK1: MR19=0x403, MR18=0x10F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3066 11:10:23.988299 [RxdqsGatingPostProcess] freq 1200
3067 11:10:23.994905 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3068 11:10:23.997977 best DQS0 dly(2T, 0.5T) = (0, 11)
3069 11:10:24.001202 best DQS1 dly(2T, 0.5T) = (0, 12)
3070 11:10:24.004754 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3071 11:10:24.008263 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3072 11:10:24.008774 best DQS0 dly(2T, 0.5T) = (0, 11)
3073 11:10:24.011455 best DQS1 dly(2T, 0.5T) = (0, 12)
3074 11:10:24.014567 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3075 11:10:24.017982 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3076 11:10:24.021344 Pre-setting of DQS Precalculation
3077 11:10:24.028449 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3078 11:10:24.028960 ==
3079 11:10:24.031822 Dram Type= 6, Freq= 0, CH_1, rank 0
3080 11:10:24.034537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 11:10:24.034955 ==
3082 11:10:24.041225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3083 11:10:24.044842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3084 11:10:24.054688 [CA 0] Center 37 (7~67) winsize 61
3085 11:10:24.058127 [CA 1] Center 37 (7~68) winsize 62
3086 11:10:24.061370 [CA 2] Center 34 (4~64) winsize 61
3087 11:10:24.064667 [CA 3] Center 34 (4~64) winsize 61
3088 11:10:24.068005 [CA 4] Center 34 (4~64) winsize 61
3089 11:10:24.071305 [CA 5] Center 33 (3~63) winsize 61
3090 11:10:24.071818
3091 11:10:24.074498 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3092 11:10:24.075005
3093 11:10:24.077907 [CATrainingPosCal] consider 1 rank data
3094 11:10:24.081202 u2DelayCellTimex100 = 270/100 ps
3095 11:10:24.084689 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3096 11:10:24.091503 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3097 11:10:24.094442 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 11:10:24.097632 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3099 11:10:24.101048 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 11:10:24.104472 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3101 11:10:24.104895
3102 11:10:24.107730 CA PerBit enable=1, Macro0, CA PI delay=33
3103 11:10:24.108261
3104 11:10:24.110924 [CBTSetCACLKResult] CA Dly = 33
3105 11:10:24.111348 CS Dly: 5 (0~36)
3106 11:10:24.114794 ==
3107 11:10:24.115306 Dram Type= 6, Freq= 0, CH_1, rank 1
3108 11:10:24.120924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 11:10:24.121344 ==
3110 11:10:24.124409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3111 11:10:24.130895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3112 11:10:24.140358 [CA 0] Center 37 (7~67) winsize 61
3113 11:10:24.143922 [CA 1] Center 37 (7~68) winsize 62
3114 11:10:24.147023 [CA 2] Center 34 (4~65) winsize 62
3115 11:10:24.150402 [CA 3] Center 33 (3~64) winsize 62
3116 11:10:24.153698 [CA 4] Center 34 (4~65) winsize 62
3117 11:10:24.157038 [CA 5] Center 33 (3~63) winsize 61
3118 11:10:24.157607
3119 11:10:24.160282 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3120 11:10:24.160806
3121 11:10:24.163642 [CATrainingPosCal] consider 2 rank data
3122 11:10:24.166539 u2DelayCellTimex100 = 270/100 ps
3123 11:10:24.170182 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3124 11:10:24.173557 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3125 11:10:24.180263 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 11:10:24.183734 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 11:10:24.186813 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3128 11:10:24.190322 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3129 11:10:24.190841
3130 11:10:24.193857 CA PerBit enable=1, Macro0, CA PI delay=33
3131 11:10:24.194380
3132 11:10:24.196540 [CBTSetCACLKResult] CA Dly = 33
3133 11:10:24.196958 CS Dly: 7 (0~40)
3134 11:10:24.197287
3135 11:10:24.200151 ----->DramcWriteLeveling(PI) begin...
3136 11:10:24.203239 ==
3137 11:10:24.206545 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 11:10:24.210298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 11:10:24.210823 ==
3140 11:10:24.213246 Write leveling (Byte 0): 28 => 28
3141 11:10:24.216590 Write leveling (Byte 1): 28 => 28
3142 11:10:24.220101 DramcWriteLeveling(PI) end<-----
3143 11:10:24.220520
3144 11:10:24.220849 ==
3145 11:10:24.223407 Dram Type= 6, Freq= 0, CH_1, rank 0
3146 11:10:24.226640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3147 11:10:24.227059 ==
3148 11:10:24.229930 [Gating] SW mode calibration
3149 11:10:24.236851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3150 11:10:24.243637 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3151 11:10:24.246593 0 15 0 | B1->B0 | 2d2d 2727 | 0 0 | (0 0) (0 0)
3152 11:10:24.249756 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 11:10:24.253191 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 11:10:24.260143 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 11:10:24.263498 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 11:10:24.266652 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3157 11:10:24.273040 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3158 11:10:24.276904 0 15 28 | B1->B0 | 2b2b 3131 | 0 1 | (0 1) (1 0)
3159 11:10:24.279932 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 1)
3160 11:10:24.286879 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 11:10:24.290367 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 11:10:24.293100 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 11:10:24.299971 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 11:10:24.303486 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 11:10:24.306634 1 0 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3166 11:10:24.313411 1 0 28 | B1->B0 | 3c3c 3737 | 0 0 | (0 0) (1 1)
3167 11:10:24.317082 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3168 11:10:24.319796 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 11:10:24.326749 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 11:10:24.330051 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 11:10:24.333290 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 11:10:24.340265 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 11:10:24.343276 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 11:10:24.346403 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3175 11:10:24.349767 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3176 11:10:24.356393 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 11:10:24.359856 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 11:10:24.363061 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 11:10:24.369852 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 11:10:24.372947 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 11:10:24.376421 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 11:10:24.383109 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 11:10:24.386302 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 11:10:24.389743 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 11:10:24.396618 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 11:10:24.399790 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 11:10:24.403348 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 11:10:24.410047 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 11:10:24.412750 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 11:10:24.416703 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3191 11:10:24.423023 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3192 11:10:24.423455 Total UI for P1: 0, mck2ui 16
3193 11:10:24.429702 best dqsien dly found for B1: ( 1, 3, 28)
3194 11:10:24.433544 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 11:10:24.436451 Total UI for P1: 0, mck2ui 16
3196 11:10:24.439559 best dqsien dly found for B0: ( 1, 3, 30)
3197 11:10:24.443148 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3198 11:10:24.446164 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3199 11:10:24.446580
3200 11:10:24.449871 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3201 11:10:24.452994 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3202 11:10:24.456461 [Gating] SW calibration Done
3203 11:10:24.456971 ==
3204 11:10:24.459912 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 11:10:24.462936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 11:10:24.463450 ==
3207 11:10:24.466366 RX Vref Scan: 0
3208 11:10:24.466874
3209 11:10:24.469379 RX Vref 0 -> 0, step: 1
3210 11:10:24.469925
3211 11:10:24.470257 RX Delay -40 -> 252, step: 8
3212 11:10:24.476444 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3213 11:10:24.480178 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3214 11:10:24.483145 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3215 11:10:24.486304 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3216 11:10:24.489574 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3217 11:10:24.496605 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3218 11:10:24.500119 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3219 11:10:24.502812 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3220 11:10:24.506044 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3221 11:10:24.509322 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3222 11:10:24.516135 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3223 11:10:24.519622 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3224 11:10:24.522935 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3225 11:10:24.526150 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3226 11:10:24.529391 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3227 11:10:24.536207 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3228 11:10:24.536679 ==
3229 11:10:24.539299 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 11:10:24.542771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 11:10:24.543219 ==
3232 11:10:24.543555 DQS Delay:
3233 11:10:24.546063 DQS0 = 0, DQS1 = 0
3234 11:10:24.546510 DQM Delay:
3235 11:10:24.549466 DQM0 = 112, DQM1 = 105
3236 11:10:24.549914 DQ Delay:
3237 11:10:24.552935 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =107
3238 11:10:24.556066 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =107
3239 11:10:24.559689 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3240 11:10:24.562645 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3241 11:10:24.563062
3242 11:10:24.563385
3243 11:10:24.566365 ==
3244 11:10:24.566873 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 11:10:24.572496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 11:10:24.572917 ==
3247 11:10:24.573248
3248 11:10:24.573600
3249 11:10:24.575848 TX Vref Scan disable
3250 11:10:24.576313 == TX Byte 0 ==
3251 11:10:24.579587 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3252 11:10:24.586158 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3253 11:10:24.586670 == TX Byte 1 ==
3254 11:10:24.589617 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3255 11:10:24.596215 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3256 11:10:24.596737 ==
3257 11:10:24.599033 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 11:10:24.602423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 11:10:24.602927 ==
3260 11:10:24.614729 TX Vref=22, minBit 8, minWin=24, winSum=409
3261 11:10:24.617966 TX Vref=24, minBit 8, minWin=24, winSum=411
3262 11:10:24.621071 TX Vref=26, minBit 9, minWin=25, winSum=419
3263 11:10:24.624494 TX Vref=28, minBit 9, minWin=25, winSum=420
3264 11:10:24.627804 TX Vref=30, minBit 9, minWin=24, winSum=421
3265 11:10:24.634524 TX Vref=32, minBit 9, minWin=25, winSum=418
3266 11:10:24.637701 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 28
3267 11:10:24.638126
3268 11:10:24.640970 Final TX Range 1 Vref 28
3269 11:10:24.641386
3270 11:10:24.641770 ==
3271 11:10:24.644409 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 11:10:24.647680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 11:10:24.648106 ==
3274 11:10:24.651141
3275 11:10:24.651554
3276 11:10:24.651949 TX Vref Scan disable
3277 11:10:24.654176 == TX Byte 0 ==
3278 11:10:24.658048 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3279 11:10:24.661355 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3280 11:10:24.664717 == TX Byte 1 ==
3281 11:10:24.667835 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3282 11:10:24.671361 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3283 11:10:24.674398
3284 11:10:24.674904 [DATLAT]
3285 11:10:24.675235 Freq=1200, CH1 RK0
3286 11:10:24.675542
3287 11:10:24.677677 DATLAT Default: 0xd
3288 11:10:24.678094 0, 0xFFFF, sum = 0
3289 11:10:24.680918 1, 0xFFFF, sum = 0
3290 11:10:24.681436 2, 0xFFFF, sum = 0
3291 11:10:24.684403 3, 0xFFFF, sum = 0
3292 11:10:24.687537 4, 0xFFFF, sum = 0
3293 11:10:24.687959 5, 0xFFFF, sum = 0
3294 11:10:24.690940 6, 0xFFFF, sum = 0
3295 11:10:24.691359 7, 0xFFFF, sum = 0
3296 11:10:24.694025 8, 0xFFFF, sum = 0
3297 11:10:24.694443 9, 0xFFFF, sum = 0
3298 11:10:24.697378 10, 0xFFFF, sum = 0
3299 11:10:24.697832 11, 0xFFFF, sum = 0
3300 11:10:24.701066 12, 0x0, sum = 1
3301 11:10:24.701516 13, 0x0, sum = 2
3302 11:10:24.704043 14, 0x0, sum = 3
3303 11:10:24.704456 15, 0x0, sum = 4
3304 11:10:24.704850 best_step = 13
3305 11:10:24.705158
3306 11:10:24.707467 ==
3307 11:10:24.710815 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 11:10:24.714471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 11:10:24.714982 ==
3310 11:10:24.715305 RX Vref Scan: 1
3311 11:10:24.715607
3312 11:10:24.718019 Set Vref Range= 32 -> 127
3313 11:10:24.718530
3314 11:10:24.720881 RX Vref 32 -> 127, step: 1
3315 11:10:24.721466
3316 11:10:24.724184 RX Delay -21 -> 252, step: 4
3317 11:10:24.724618
3318 11:10:24.727765 Set Vref, RX VrefLevel [Byte0]: 32
3319 11:10:24.730887 [Byte1]: 32
3320 11:10:24.731554
3321 11:10:24.734144 Set Vref, RX VrefLevel [Byte0]: 33
3322 11:10:24.737873 [Byte1]: 33
3323 11:10:24.740981
3324 11:10:24.741730 Set Vref, RX VrefLevel [Byte0]: 34
3325 11:10:24.744211 [Byte1]: 34
3326 11:10:24.748610
3327 11:10:24.749020 Set Vref, RX VrefLevel [Byte0]: 35
3328 11:10:24.752169 [Byte1]: 35
3329 11:10:24.756550
3330 11:10:24.757182 Set Vref, RX VrefLevel [Byte0]: 36
3331 11:10:24.759783 [Byte1]: 36
3332 11:10:24.764535
3333 11:10:24.764946 Set Vref, RX VrefLevel [Byte0]: 37
3334 11:10:24.768234 [Byte1]: 37
3335 11:10:24.772499
3336 11:10:24.773038 Set Vref, RX VrefLevel [Byte0]: 38
3337 11:10:24.776233 [Byte1]: 38
3338 11:10:24.780810
3339 11:10:24.781524 Set Vref, RX VrefLevel [Byte0]: 39
3340 11:10:24.784028 [Byte1]: 39
3341 11:10:24.788638
3342 11:10:24.789142 Set Vref, RX VrefLevel [Byte0]: 40
3343 11:10:24.791964 [Byte1]: 40
3344 11:10:24.796714
3345 11:10:24.797217 Set Vref, RX VrefLevel [Byte0]: 41
3346 11:10:24.799676 [Byte1]: 41
3347 11:10:24.804318
3348 11:10:24.804857 Set Vref, RX VrefLevel [Byte0]: 42
3349 11:10:24.807667 [Byte1]: 42
3350 11:10:24.812169
3351 11:10:24.812707 Set Vref, RX VrefLevel [Byte0]: 43
3352 11:10:24.815299 [Byte1]: 43
3353 11:10:24.820243
3354 11:10:24.820888 Set Vref, RX VrefLevel [Byte0]: 44
3355 11:10:24.823634 [Byte1]: 44
3356 11:10:24.827692
3357 11:10:24.828101 Set Vref, RX VrefLevel [Byte0]: 45
3358 11:10:24.831520 [Byte1]: 45
3359 11:10:24.835778
3360 11:10:24.836275 Set Vref, RX VrefLevel [Byte0]: 46
3361 11:10:24.839011 [Byte1]: 46
3362 11:10:24.843977
3363 11:10:24.844483 Set Vref, RX VrefLevel [Byte0]: 47
3364 11:10:24.847078 [Byte1]: 47
3365 11:10:24.851924
3366 11:10:24.852429 Set Vref, RX VrefLevel [Byte0]: 48
3367 11:10:24.854998 [Byte1]: 48
3368 11:10:24.859962
3369 11:10:24.860461 Set Vref, RX VrefLevel [Byte0]: 49
3370 11:10:24.862792 [Byte1]: 49
3371 11:10:24.867499
3372 11:10:24.867988 Set Vref, RX VrefLevel [Byte0]: 50
3373 11:10:24.870933 [Byte1]: 50
3374 11:10:24.875781
3375 11:10:24.876291 Set Vref, RX VrefLevel [Byte0]: 51
3376 11:10:24.879079 [Byte1]: 51
3377 11:10:24.883918
3378 11:10:24.884424 Set Vref, RX VrefLevel [Byte0]: 52
3379 11:10:24.886769 [Byte1]: 52
3380 11:10:24.891286
3381 11:10:24.891779 Set Vref, RX VrefLevel [Byte0]: 53
3382 11:10:24.894499 [Byte1]: 53
3383 11:10:24.899324
3384 11:10:24.899740 Set Vref, RX VrefLevel [Byte0]: 54
3385 11:10:24.902339 [Byte1]: 54
3386 11:10:24.907012
3387 11:10:24.907426 Set Vref, RX VrefLevel [Byte0]: 55
3388 11:10:24.910565 [Byte1]: 55
3389 11:10:24.915118
3390 11:10:24.915667 Set Vref, RX VrefLevel [Byte0]: 56
3391 11:10:24.918462 [Byte1]: 56
3392 11:10:24.922885
3393 11:10:24.923299 Set Vref, RX VrefLevel [Byte0]: 57
3394 11:10:24.926260 [Byte1]: 57
3395 11:10:24.931076
3396 11:10:24.931582 Set Vref, RX VrefLevel [Byte0]: 58
3397 11:10:24.934233 [Byte1]: 58
3398 11:10:24.938729
3399 11:10:24.939236 Set Vref, RX VrefLevel [Byte0]: 59
3400 11:10:24.941993 [Byte1]: 59
3401 11:10:24.946736
3402 11:10:24.947242 Set Vref, RX VrefLevel [Byte0]: 60
3403 11:10:24.949827 [Byte1]: 60
3404 11:10:24.954595
3405 11:10:24.955102 Set Vref, RX VrefLevel [Byte0]: 61
3406 11:10:24.957877 [Byte1]: 61
3407 11:10:24.962728
3408 11:10:24.963240 Set Vref, RX VrefLevel [Byte0]: 62
3409 11:10:24.966219 [Byte1]: 62
3410 11:10:24.970548
3411 11:10:24.971050 Set Vref, RX VrefLevel [Byte0]: 63
3412 11:10:24.973990 [Byte1]: 63
3413 11:10:24.978433
3414 11:10:24.978940 Set Vref, RX VrefLevel [Byte0]: 64
3415 11:10:24.982095 [Byte1]: 64
3416 11:10:24.986408
3417 11:10:24.986913 Set Vref, RX VrefLevel [Byte0]: 65
3418 11:10:24.990037 [Byte1]: 65
3419 11:10:24.994488
3420 11:10:24.995002 Set Vref, RX VrefLevel [Byte0]: 66
3421 11:10:24.998075 [Byte1]: 66
3422 11:10:25.002418
3423 11:10:25.002926 Final RX Vref Byte 0 = 57 to rank0
3424 11:10:25.005458 Final RX Vref Byte 1 = 51 to rank0
3425 11:10:25.008844 Final RX Vref Byte 0 = 57 to rank1
3426 11:10:25.012329 Final RX Vref Byte 1 = 51 to rank1==
3427 11:10:25.015261 Dram Type= 6, Freq= 0, CH_1, rank 0
3428 11:10:25.022083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 11:10:25.022641 ==
3430 11:10:25.022973 DQS Delay:
3431 11:10:25.023279 DQS0 = 0, DQS1 = 0
3432 11:10:25.025503 DQM Delay:
3433 11:10:25.025923 DQM0 = 114, DQM1 = 105
3434 11:10:25.028622 DQ Delay:
3435 11:10:25.032390 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =112
3436 11:10:25.035477 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3437 11:10:25.039048 DQ8 =94, DQ9 =100, DQ10 =104, DQ11 =100
3438 11:10:25.042251 DQ12 =114, DQ13 =110, DQ14 =112, DQ15 =112
3439 11:10:25.042760
3440 11:10:25.043089
3441 11:10:25.048697 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3442 11:10:25.052290 CH1 RK0: MR19=303, MR18=ECF3
3443 11:10:25.059130 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3444 11:10:25.059644
3445 11:10:25.062122 ----->DramcWriteLeveling(PI) begin...
3446 11:10:25.062543 ==
3447 11:10:25.065961 Dram Type= 6, Freq= 0, CH_1, rank 1
3448 11:10:25.069054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 11:10:25.072379 ==
3450 11:10:25.072890 Write leveling (Byte 0): 23 => 23
3451 11:10:25.075654 Write leveling (Byte 1): 28 => 28
3452 11:10:25.078978 DramcWriteLeveling(PI) end<-----
3453 11:10:25.079497
3454 11:10:25.079831 ==
3455 11:10:25.082434 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 11:10:25.088991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 11:10:25.089525 ==
3458 11:10:25.089859 [Gating] SW mode calibration
3459 11:10:25.099001 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3460 11:10:25.102412 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3461 11:10:25.108618 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 11:10:25.112257 0 15 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
3463 11:10:25.115663 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 11:10:25.118835 0 15 12 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
3465 11:10:25.125196 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 11:10:25.128567 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 11:10:25.132359 0 15 24 | B1->B0 | 3232 2525 | 1 0 | (1 0) (0 0)
3468 11:10:25.138631 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3469 11:10:25.141767 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3470 11:10:25.145553 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 11:10:25.151850 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 11:10:25.154908 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 11:10:25.158387 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 11:10:25.165221 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3475 11:10:25.168549 1 0 24 | B1->B0 | 2727 4444 | 0 0 | (0 0) (0 0)
3476 11:10:25.171451 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3477 11:10:25.178092 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 11:10:25.181800 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 11:10:25.184782 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 11:10:25.191606 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 11:10:25.194982 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 11:10:25.198352 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 11:10:25.204519 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3484 11:10:25.208176 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3485 11:10:25.211288 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 11:10:25.217815 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 11:10:25.221405 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 11:10:25.224199 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 11:10:25.231080 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 11:10:25.234199 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 11:10:25.237837 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 11:10:25.244387 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 11:10:25.248041 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 11:10:25.250820 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 11:10:25.257333 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 11:10:25.261028 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 11:10:25.264134 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 11:10:25.271106 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3499 11:10:25.274060 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3500 11:10:25.277395 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 11:10:25.280778 Total UI for P1: 0, mck2ui 16
3502 11:10:25.284295 best dqsien dly found for B0: ( 1, 3, 22)
3503 11:10:25.287734 Total UI for P1: 0, mck2ui 16
3504 11:10:25.290480 best dqsien dly found for B1: ( 1, 3, 26)
3505 11:10:25.293976 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3506 11:10:25.297673 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3507 11:10:25.298187
3508 11:10:25.304044 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3509 11:10:25.307136 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3510 11:10:25.307553 [Gating] SW calibration Done
3511 11:10:25.310405 ==
3512 11:10:25.313915 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 11:10:25.317204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 11:10:25.317754 ==
3515 11:10:25.318096 RX Vref Scan: 0
3516 11:10:25.318404
3517 11:10:25.320425 RX Vref 0 -> 0, step: 1
3518 11:10:25.320934
3519 11:10:25.323756 RX Delay -40 -> 252, step: 8
3520 11:10:25.327413 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3521 11:10:25.330676 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3522 11:10:25.334088 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3523 11:10:25.340860 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3524 11:10:25.344008 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3525 11:10:25.347441 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3526 11:10:25.350751 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3527 11:10:25.354011 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3528 11:10:25.360352 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3529 11:10:25.363884 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3530 11:10:25.366782 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3531 11:10:25.370416 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3532 11:10:25.373534 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3533 11:10:25.380343 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3534 11:10:25.383492 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3535 11:10:25.386812 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3536 11:10:25.387321 ==
3537 11:10:25.390055 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 11:10:25.393529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 11:10:25.396936 ==
3540 11:10:25.397444 DQS Delay:
3541 11:10:25.397813 DQS0 = 0, DQS1 = 0
3542 11:10:25.400052 DQM Delay:
3543 11:10:25.400467 DQM0 = 111, DQM1 = 107
3544 11:10:25.403118 DQ Delay:
3545 11:10:25.406740 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3546 11:10:25.409915 DQ4 =107, DQ5 =123, DQ6 =119, DQ7 =111
3547 11:10:25.413521 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3548 11:10:25.416511 DQ12 =115, DQ13 =119, DQ14 =111, DQ15 =111
3549 11:10:25.417068
3550 11:10:25.417404
3551 11:10:25.417773 ==
3552 11:10:25.419738 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 11:10:25.423005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 11:10:25.423519 ==
3555 11:10:25.423851
3556 11:10:25.424239
3557 11:10:25.426143 TX Vref Scan disable
3558 11:10:25.429589 == TX Byte 0 ==
3559 11:10:25.433278 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3560 11:10:25.436414 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3561 11:10:25.439814 == TX Byte 1 ==
3562 11:10:25.443104 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3563 11:10:25.446236 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3564 11:10:25.446656 ==
3565 11:10:25.449591 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 11:10:25.456210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 11:10:25.456724 ==
3568 11:10:25.467054 TX Vref=22, minBit 3, minWin=25, winSum=419
3569 11:10:25.470159 TX Vref=24, minBit 9, minWin=25, winSum=428
3570 11:10:25.473689 TX Vref=26, minBit 8, minWin=26, winSum=434
3571 11:10:25.477285 TX Vref=28, minBit 9, minWin=26, winSum=433
3572 11:10:25.480476 TX Vref=30, minBit 8, minWin=26, winSum=435
3573 11:10:25.487105 TX Vref=32, minBit 8, minWin=25, winSum=429
3574 11:10:25.490194 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
3575 11:10:25.490703
3576 11:10:25.493631 Final TX Range 1 Vref 30
3577 11:10:25.494138
3578 11:10:25.494468 ==
3579 11:10:25.496458 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 11:10:25.500154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 11:10:25.500575 ==
3582 11:10:25.503397
3583 11:10:25.503840
3584 11:10:25.504169 TX Vref Scan disable
3585 11:10:25.506653 == TX Byte 0 ==
3586 11:10:25.509942 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3587 11:10:25.516310 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3588 11:10:25.516810 == TX Byte 1 ==
3589 11:10:25.519628 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3590 11:10:25.526649 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3591 11:10:25.527070
3592 11:10:25.527455 [DATLAT]
3593 11:10:25.527767 Freq=1200, CH1 RK1
3594 11:10:25.528067
3595 11:10:25.529852 DATLAT Default: 0xd
3596 11:10:25.533104 0, 0xFFFF, sum = 0
3597 11:10:25.533770 1, 0xFFFF, sum = 0
3598 11:10:25.536340 2, 0xFFFF, sum = 0
3599 11:10:25.536855 3, 0xFFFF, sum = 0
3600 11:10:25.539423 4, 0xFFFF, sum = 0
3601 11:10:25.539847 5, 0xFFFF, sum = 0
3602 11:10:25.543086 6, 0xFFFF, sum = 0
3603 11:10:25.543507 7, 0xFFFF, sum = 0
3604 11:10:25.546029 8, 0xFFFF, sum = 0
3605 11:10:25.546453 9, 0xFFFF, sum = 0
3606 11:10:25.549404 10, 0xFFFF, sum = 0
3607 11:10:25.549883 11, 0xFFFF, sum = 0
3608 11:10:25.553153 12, 0x0, sum = 1
3609 11:10:25.553706 13, 0x0, sum = 2
3610 11:10:25.556243 14, 0x0, sum = 3
3611 11:10:25.556760 15, 0x0, sum = 4
3612 11:10:25.559806 best_step = 13
3613 11:10:25.560315
3614 11:10:25.560645 ==
3615 11:10:25.562941 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 11:10:25.566358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 11:10:25.566870 ==
3618 11:10:25.567203 RX Vref Scan: 0
3619 11:10:25.569981
3620 11:10:25.570491 RX Vref 0 -> 0, step: 1
3621 11:10:25.570827
3622 11:10:25.572696 RX Delay -21 -> 252, step: 4
3623 11:10:25.579656 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3624 11:10:25.583089 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3625 11:10:25.585844 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3626 11:10:25.589012 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3627 11:10:25.592578 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3628 11:10:25.599202 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3629 11:10:25.602344 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3630 11:10:25.605655 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3631 11:10:25.608782 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3632 11:10:25.612652 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3633 11:10:25.619297 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3634 11:10:25.622207 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3635 11:10:25.625802 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3636 11:10:25.628518 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3637 11:10:25.631850 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3638 11:10:25.638674 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3639 11:10:25.639170 ==
3640 11:10:25.642005 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 11:10:25.645542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 11:10:25.645961 ==
3643 11:10:25.646291 DQS Delay:
3644 11:10:25.648643 DQS0 = 0, DQS1 = 0
3645 11:10:25.649153 DQM Delay:
3646 11:10:25.651926 DQM0 = 111, DQM1 = 110
3647 11:10:25.652336 DQ Delay:
3648 11:10:25.655251 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =108
3649 11:10:25.658346 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =110
3650 11:10:25.661848 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =102
3651 11:10:25.665130 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3652 11:10:25.668594
3653 11:10:25.669005
3654 11:10:25.675308 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3655 11:10:25.678333 CH1 RK1: MR19=304, MR18=FB0B
3656 11:10:25.685416 CH1_RK1: MR19=0x304, MR18=0xFB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3657 11:10:25.688845 [RxdqsGatingPostProcess] freq 1200
3658 11:10:25.691888 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3659 11:10:25.695086 best DQS0 dly(2T, 0.5T) = (0, 11)
3660 11:10:25.698448 best DQS1 dly(2T, 0.5T) = (0, 11)
3661 11:10:25.701695 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3662 11:10:25.705132 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3663 11:10:25.708001 best DQS0 dly(2T, 0.5T) = (0, 11)
3664 11:10:25.711790 best DQS1 dly(2T, 0.5T) = (0, 11)
3665 11:10:25.714681 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3666 11:10:25.718236 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3667 11:10:25.721646 Pre-setting of DQS Precalculation
3668 11:10:25.724921 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3669 11:10:25.734492 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3670 11:10:25.741179 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3671 11:10:25.741739
3672 11:10:25.742074
3673 11:10:25.744725 [Calibration Summary] 2400 Mbps
3674 11:10:25.745138 CH 0, Rank 0
3675 11:10:25.748254 SW Impedance : PASS
3676 11:10:25.748797 DUTY Scan : NO K
3677 11:10:25.751190 ZQ Calibration : PASS
3678 11:10:25.754580 Jitter Meter : NO K
3679 11:10:25.755090 CBT Training : PASS
3680 11:10:25.757990 Write leveling : PASS
3681 11:10:25.761461 RX DQS gating : PASS
3682 11:10:25.762011 RX DQ/DQS(RDDQC) : PASS
3683 11:10:25.764535 TX DQ/DQS : PASS
3684 11:10:25.767912 RX DATLAT : PASS
3685 11:10:25.768467 RX DQ/DQS(Engine): PASS
3686 11:10:25.771106 TX OE : NO K
3687 11:10:25.771623 All Pass.
3688 11:10:25.771947
3689 11:10:25.774254 CH 0, Rank 1
3690 11:10:25.774800 SW Impedance : PASS
3691 11:10:25.777842 DUTY Scan : NO K
3692 11:10:25.778351 ZQ Calibration : PASS
3693 11:10:25.781301 Jitter Meter : NO K
3694 11:10:25.784557 CBT Training : PASS
3695 11:10:25.785064 Write leveling : PASS
3696 11:10:25.787609 RX DQS gating : PASS
3697 11:10:25.791016 RX DQ/DQS(RDDQC) : PASS
3698 11:10:25.791524 TX DQ/DQS : PASS
3699 11:10:25.794398 RX DATLAT : PASS
3700 11:10:25.797405 RX DQ/DQS(Engine): PASS
3701 11:10:25.797958 TX OE : NO K
3702 11:10:25.800775 All Pass.
3703 11:10:25.801209
3704 11:10:25.801577 CH 1, Rank 0
3705 11:10:25.803876 SW Impedance : PASS
3706 11:10:25.804284 DUTY Scan : NO K
3707 11:10:25.807247 ZQ Calibration : PASS
3708 11:10:25.810716 Jitter Meter : NO K
3709 11:10:25.811167 CBT Training : PASS
3710 11:10:25.814140 Write leveling : PASS
3711 11:10:25.817209 RX DQS gating : PASS
3712 11:10:25.817750 RX DQ/DQS(RDDQC) : PASS
3713 11:10:25.820614 TX DQ/DQS : PASS
3714 11:10:25.823935 RX DATLAT : PASS
3715 11:10:25.824348 RX DQ/DQS(Engine): PASS
3716 11:10:25.827088 TX OE : NO K
3717 11:10:25.827506 All Pass.
3718 11:10:25.827833
3719 11:10:25.830412 CH 1, Rank 1
3720 11:10:25.830823 SW Impedance : PASS
3721 11:10:25.833856 DUTY Scan : NO K
3722 11:10:25.837342 ZQ Calibration : PASS
3723 11:10:25.837917 Jitter Meter : NO K
3724 11:10:25.840670 CBT Training : PASS
3725 11:10:25.841084 Write leveling : PASS
3726 11:10:25.843934 RX DQS gating : PASS
3727 11:10:25.847458 RX DQ/DQS(RDDQC) : PASS
3728 11:10:25.847972 TX DQ/DQS : PASS
3729 11:10:25.850641 RX DATLAT : PASS
3730 11:10:25.853937 RX DQ/DQS(Engine): PASS
3731 11:10:25.854349 TX OE : NO K
3732 11:10:25.857383 All Pass.
3733 11:10:25.857956
3734 11:10:25.858288 DramC Write-DBI off
3735 11:10:25.860659 PER_BANK_REFRESH: Hybrid Mode
3736 11:10:25.863827 TX_TRACKING: ON
3737 11:10:25.870357 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3738 11:10:25.873833 [FAST_K] Save calibration result to emmc
3739 11:10:25.877072 dramc_set_vcore_voltage set vcore to 650000
3740 11:10:25.879962 Read voltage for 600, 5
3741 11:10:25.880374 Vio18 = 0
3742 11:10:25.883898 Vcore = 650000
3743 11:10:25.884411 Vdram = 0
3744 11:10:25.884741 Vddq = 0
3745 11:10:25.887249 Vmddr = 0
3746 11:10:25.890418 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3747 11:10:25.897374 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3748 11:10:25.897944 MEM_TYPE=3, freq_sel=19
3749 11:10:25.900139 sv_algorithm_assistance_LP4_1600
3750 11:10:25.906491 ============ PULL DRAM RESETB DOWN ============
3751 11:10:25.909943 ========== PULL DRAM RESETB DOWN end =========
3752 11:10:25.913268 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3753 11:10:25.916921 ===================================
3754 11:10:25.920270 LPDDR4 DRAM CONFIGURATION
3755 11:10:25.923604 ===================================
3756 11:10:25.926524 EX_ROW_EN[0] = 0x0
3757 11:10:25.926985 EX_ROW_EN[1] = 0x0
3758 11:10:25.929969 LP4Y_EN = 0x0
3759 11:10:25.930528 WORK_FSP = 0x0
3760 11:10:25.933129 WL = 0x2
3761 11:10:25.933596 RL = 0x2
3762 11:10:25.937059 BL = 0x2
3763 11:10:25.937625 RPST = 0x0
3764 11:10:25.939767 RD_PRE = 0x0
3765 11:10:25.940179 WR_PRE = 0x1
3766 11:10:25.943179 WR_PST = 0x0
3767 11:10:25.943590 DBI_WR = 0x0
3768 11:10:25.946855 DBI_RD = 0x0
3769 11:10:25.947371 OTF = 0x1
3770 11:10:25.949850 ===================================
3771 11:10:25.953574 ===================================
3772 11:10:25.956548 ANA top config
3773 11:10:25.959919 ===================================
3774 11:10:25.963373 DLL_ASYNC_EN = 0
3775 11:10:25.963897 ALL_SLAVE_EN = 1
3776 11:10:25.966286 NEW_RANK_MODE = 1
3777 11:10:25.969854 DLL_IDLE_MODE = 1
3778 11:10:25.972969 LP45_APHY_COMB_EN = 1
3779 11:10:25.973521 TX_ODT_DIS = 1
3780 11:10:25.976627 NEW_8X_MODE = 1
3781 11:10:25.979477 ===================================
3782 11:10:25.983181 ===================================
3783 11:10:25.986257 data_rate = 1200
3784 11:10:25.989924 CKR = 1
3785 11:10:25.992972 DQ_P2S_RATIO = 8
3786 11:10:25.996568 ===================================
3787 11:10:25.999573 CA_P2S_RATIO = 8
3788 11:10:25.999988 DQ_CA_OPEN = 0
3789 11:10:26.002901 DQ_SEMI_OPEN = 0
3790 11:10:26.006603 CA_SEMI_OPEN = 0
3791 11:10:26.010168 CA_FULL_RATE = 0
3792 11:10:26.013048 DQ_CKDIV4_EN = 1
3793 11:10:26.016088 CA_CKDIV4_EN = 1
3794 11:10:26.016502 CA_PREDIV_EN = 0
3795 11:10:26.019476 PH8_DLY = 0
3796 11:10:26.023256 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3797 11:10:26.026435 DQ_AAMCK_DIV = 4
3798 11:10:26.029613 CA_AAMCK_DIV = 4
3799 11:10:26.032655 CA_ADMCK_DIV = 4
3800 11:10:26.033068 DQ_TRACK_CA_EN = 0
3801 11:10:26.036055 CA_PICK = 600
3802 11:10:26.039443 CA_MCKIO = 600
3803 11:10:26.042608 MCKIO_SEMI = 0
3804 11:10:26.046362 PLL_FREQ = 2288
3805 11:10:26.049765 DQ_UI_PI_RATIO = 32
3806 11:10:26.052625 CA_UI_PI_RATIO = 0
3807 11:10:26.056357 ===================================
3808 11:10:26.059308 ===================================
3809 11:10:26.059821 memory_type:LPDDR4
3810 11:10:26.062503 GP_NUM : 10
3811 11:10:26.065812 SRAM_EN : 1
3812 11:10:26.066227 MD32_EN : 0
3813 11:10:26.069533 ===================================
3814 11:10:26.072780 [ANA_INIT] >>>>>>>>>>>>>>
3815 11:10:26.076171 <<<<<< [CONFIGURE PHASE]: ANA_TX
3816 11:10:26.079305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3817 11:10:26.082699 ===================================
3818 11:10:26.086179 data_rate = 1200,PCW = 0X5800
3819 11:10:26.089268 ===================================
3820 11:10:26.092458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3821 11:10:26.096166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 11:10:26.102067 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3823 11:10:26.105981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3824 11:10:26.108981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3825 11:10:26.112017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3826 11:10:26.115639 [ANA_INIT] flow start
3827 11:10:26.118847 [ANA_INIT] PLL >>>>>>>>
3828 11:10:26.119259 [ANA_INIT] PLL <<<<<<<<
3829 11:10:26.122199 [ANA_INIT] MIDPI >>>>>>>>
3830 11:10:26.125644 [ANA_INIT] MIDPI <<<<<<<<
3831 11:10:26.128703 [ANA_INIT] DLL >>>>>>>>
3832 11:10:26.129117 [ANA_INIT] flow end
3833 11:10:26.131942 ============ LP4 DIFF to SE enter ============
3834 11:10:26.138363 ============ LP4 DIFF to SE exit ============
3835 11:10:26.138862 [ANA_INIT] <<<<<<<<<<<<<
3836 11:10:26.142020 [Flow] Enable top DCM control >>>>>
3837 11:10:26.145558 [Flow] Enable top DCM control <<<<<
3838 11:10:26.148322 Enable DLL master slave shuffle
3839 11:10:26.155450 ==============================================================
3840 11:10:26.155958 Gating Mode config
3841 11:10:26.161647 ==============================================================
3842 11:10:26.165398 Config description:
3843 11:10:26.174895 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3844 11:10:26.181849 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3845 11:10:26.185033 SELPH_MODE 0: By rank 1: By Phase
3846 11:10:26.191219 ==============================================================
3847 11:10:26.194922 GAT_TRACK_EN = 1
3848 11:10:26.198445 RX_GATING_MODE = 2
3849 11:10:26.198962 RX_GATING_TRACK_MODE = 2
3850 11:10:26.201222 SELPH_MODE = 1
3851 11:10:26.204666 PICG_EARLY_EN = 1
3852 11:10:26.208079 VALID_LAT_VALUE = 1
3853 11:10:26.214441 ==============================================================
3854 11:10:26.217946 Enter into Gating configuration >>>>
3855 11:10:26.221299 Exit from Gating configuration <<<<
3856 11:10:26.224676 Enter into DVFS_PRE_config >>>>>
3857 11:10:26.234269 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3858 11:10:26.237803 Exit from DVFS_PRE_config <<<<<
3859 11:10:26.240767 Enter into PICG configuration >>>>
3860 11:10:26.244603 Exit from PICG configuration <<<<
3861 11:10:26.247923 [RX_INPUT] configuration >>>>>
3862 11:10:26.250935 [RX_INPUT] configuration <<<<<
3863 11:10:26.254163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3864 11:10:26.260794 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3865 11:10:26.267362 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 11:10:26.274171 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 11:10:26.280943 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 11:10:26.283959 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 11:10:26.290616 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3870 11:10:26.293969 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3871 11:10:26.297193 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3872 11:10:26.300608 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3873 11:10:26.307140 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3874 11:10:26.310286 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3875 11:10:26.314126 ===================================
3876 11:10:26.316972 LPDDR4 DRAM CONFIGURATION
3877 11:10:26.320117 ===================================
3878 11:10:26.320604 EX_ROW_EN[0] = 0x0
3879 11:10:26.323537 EX_ROW_EN[1] = 0x0
3880 11:10:26.324043 LP4Y_EN = 0x0
3881 11:10:26.326817 WORK_FSP = 0x0
3882 11:10:26.327266 WL = 0x2
3883 11:10:26.329971 RL = 0x2
3884 11:10:26.330382 BL = 0x2
3885 11:10:26.333396 RPST = 0x0
3886 11:10:26.333854 RD_PRE = 0x0
3887 11:10:26.336796 WR_PRE = 0x1
3888 11:10:26.340020 WR_PST = 0x0
3889 11:10:26.340525 DBI_WR = 0x0
3890 11:10:26.343179 DBI_RD = 0x0
3891 11:10:26.343624 OTF = 0x1
3892 11:10:26.347010 ===================================
3893 11:10:26.349804 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3894 11:10:26.353335 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3895 11:10:26.360348 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 11:10:26.363421 ===================================
3897 11:10:26.366585 LPDDR4 DRAM CONFIGURATION
3898 11:10:26.369906 ===================================
3899 11:10:26.370322 EX_ROW_EN[0] = 0x10
3900 11:10:26.373236 EX_ROW_EN[1] = 0x0
3901 11:10:26.373678 LP4Y_EN = 0x0
3902 11:10:26.376269 WORK_FSP = 0x0
3903 11:10:26.376681 WL = 0x2
3904 11:10:26.380011 RL = 0x2
3905 11:10:26.380517 BL = 0x2
3906 11:10:26.383287 RPST = 0x0
3907 11:10:26.383797 RD_PRE = 0x0
3908 11:10:26.386543 WR_PRE = 0x1
3909 11:10:26.387050 WR_PST = 0x0
3910 11:10:26.390140 DBI_WR = 0x0
3911 11:10:26.393532 DBI_RD = 0x0
3912 11:10:26.394048 OTF = 0x1
3913 11:10:26.396799 ===================================
3914 11:10:26.402857 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3915 11:10:26.406257 nWR fixed to 30
3916 11:10:26.409601 [ModeRegInit_LP4] CH0 RK0
3917 11:10:26.410015 [ModeRegInit_LP4] CH0 RK1
3918 11:10:26.413345 [ModeRegInit_LP4] CH1 RK0
3919 11:10:26.416566 [ModeRegInit_LP4] CH1 RK1
3920 11:10:26.417072 match AC timing 17
3921 11:10:26.423064 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3922 11:10:26.426157 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3923 11:10:26.429861 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3924 11:10:26.436368 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3925 11:10:26.439446 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3926 11:10:26.439992 ==
3927 11:10:26.442723 Dram Type= 6, Freq= 0, CH_0, rank 0
3928 11:10:26.446157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3929 11:10:26.446704 ==
3930 11:10:26.452684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3931 11:10:26.459099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3932 11:10:26.462458 [CA 0] Center 37 (7~67) winsize 61
3933 11:10:26.465864 [CA 1] Center 36 (6~66) winsize 61
3934 11:10:26.469096 [CA 2] Center 35 (5~65) winsize 61
3935 11:10:26.472136 [CA 3] Center 35 (5~65) winsize 61
3936 11:10:26.475869 [CA 4] Center 34 (4~65) winsize 62
3937 11:10:26.479148 [CA 5] Center 34 (4~64) winsize 61
3938 11:10:26.479790
3939 11:10:26.482398 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3940 11:10:26.482906
3941 11:10:26.485570 [CATrainingPosCal] consider 1 rank data
3942 11:10:26.488920 u2DelayCellTimex100 = 270/100 ps
3943 11:10:26.492351 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3944 11:10:26.495678 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
3945 11:10:26.499206 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3946 11:10:26.505585 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3947 11:10:26.508713 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3948 11:10:26.511790 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3949 11:10:26.512218
3950 11:10:26.515429 CA PerBit enable=1, Macro0, CA PI delay=34
3951 11:10:26.515937
3952 11:10:26.518680 [CBTSetCACLKResult] CA Dly = 34
3953 11:10:26.519097 CS Dly: 5 (0~36)
3954 11:10:26.519424 ==
3955 11:10:26.522197 Dram Type= 6, Freq= 0, CH_0, rank 1
3956 11:10:26.528826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 11:10:26.529344 ==
3958 11:10:26.531976 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3959 11:10:26.538755 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3960 11:10:26.541760 [CA 0] Center 37 (7~67) winsize 61
3961 11:10:26.545239 [CA 1] Center 36 (6~67) winsize 62
3962 11:10:26.548914 [CA 2] Center 35 (5~65) winsize 61
3963 11:10:26.551817 [CA 3] Center 34 (4~65) winsize 62
3964 11:10:26.555090 [CA 4] Center 34 (4~64) winsize 61
3965 11:10:26.558336 [CA 5] Center 33 (3~64) winsize 62
3966 11:10:26.558842
3967 11:10:26.561876 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3968 11:10:26.562387
3969 11:10:26.565302 [CATrainingPosCal] consider 2 rank data
3970 11:10:26.568317 u2DelayCellTimex100 = 270/100 ps
3971 11:10:26.572174 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3972 11:10:26.578174 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
3973 11:10:26.581696 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3974 11:10:26.585000 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3975 11:10:26.588256 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3976 11:10:26.591883 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3977 11:10:26.592404
3978 11:10:26.594723 CA PerBit enable=1, Macro0, CA PI delay=34
3979 11:10:26.595143
3980 11:10:26.598501 [CBTSetCACLKResult] CA Dly = 34
3981 11:10:26.601514 CS Dly: 6 (0~38)
3982 11:10:26.602023
3983 11:10:26.604545 ----->DramcWriteLeveling(PI) begin...
3984 11:10:26.604980 ==
3985 11:10:26.607899 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 11:10:26.611519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 11:10:26.611937 ==
3988 11:10:26.614928 Write leveling (Byte 0): 32 => 32
3989 11:10:26.618080 Write leveling (Byte 1): 29 => 29
3990 11:10:26.621390 DramcWriteLeveling(PI) end<-----
3991 11:10:26.621942
3992 11:10:26.622271 ==
3993 11:10:26.624530 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 11:10:26.627932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 11:10:26.628443 ==
3996 11:10:26.631144 [Gating] SW mode calibration
3997 11:10:26.637970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3998 11:10:26.644552 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3999 11:10:26.648186 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 11:10:26.650945 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 11:10:26.657366 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 11:10:26.661172 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4003 11:10:26.664359 0 9 16 | B1->B0 | 3232 2e2e | 0 0 | (0 1) (0 0)
4004 11:10:26.670740 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 11:10:26.674127 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 11:10:26.677183 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 11:10:26.684212 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 11:10:26.687329 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 11:10:26.690211 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 11:10:26.697120 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4011 11:10:26.700275 0 10 16 | B1->B0 | 3232 3939 | 1 0 | (0 0) (0 0)
4012 11:10:26.703519 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 11:10:26.710176 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 11:10:26.713631 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 11:10:26.717056 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 11:10:26.723353 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 11:10:26.726847 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 11:10:26.730132 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4019 11:10:26.736546 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4020 11:10:26.740106 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 11:10:26.743173 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 11:10:26.749949 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 11:10:26.753372 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 11:10:26.756561 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 11:10:26.763302 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 11:10:26.766607 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 11:10:26.769676 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 11:10:26.776935 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 11:10:26.779919 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 11:10:26.783322 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 11:10:26.789873 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 11:10:26.793217 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 11:10:26.796607 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 11:10:26.803063 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 11:10:26.806197 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4036 11:10:26.809643 Total UI for P1: 0, mck2ui 16
4037 11:10:26.813295 best dqsien dly found for B0: ( 0, 13, 14)
4038 11:10:26.816069 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 11:10:26.819721 Total UI for P1: 0, mck2ui 16
4040 11:10:26.822859 best dqsien dly found for B1: ( 0, 13, 18)
4041 11:10:26.826422 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4042 11:10:26.830027 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4043 11:10:26.830539
4044 11:10:26.832746 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4045 11:10:26.839996 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4046 11:10:26.840542 [Gating] SW calibration Done
4047 11:10:26.840882 ==
4048 11:10:26.842941 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 11:10:26.849307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 11:10:26.849873 ==
4051 11:10:26.850209 RX Vref Scan: 0
4052 11:10:26.850513
4053 11:10:26.852644 RX Vref 0 -> 0, step: 1
4054 11:10:26.853054
4055 11:10:26.855971 RX Delay -230 -> 252, step: 16
4056 11:10:26.859661 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4057 11:10:26.862797 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4058 11:10:26.869608 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4059 11:10:26.872650 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4060 11:10:26.876147 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4061 11:10:26.879253 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4062 11:10:26.882509 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4063 11:10:26.889106 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4064 11:10:26.892905 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4065 11:10:26.895900 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4066 11:10:26.899243 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4067 11:10:26.905870 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4068 11:10:26.908787 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4069 11:10:26.911969 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4070 11:10:26.915518 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4071 11:10:26.922113 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4072 11:10:26.922633 ==
4073 11:10:26.925575 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 11:10:26.928735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 11:10:26.929254 ==
4076 11:10:26.929646 DQS Delay:
4077 11:10:26.932140 DQS0 = 0, DQS1 = 0
4078 11:10:26.932551 DQM Delay:
4079 11:10:26.935182 DQM0 = 39, DQM1 = 30
4080 11:10:26.935591 DQ Delay:
4081 11:10:26.939000 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4082 11:10:26.942037 DQ4 =41, DQ5 =25, DQ6 =57, DQ7 =49
4083 11:10:26.945461 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4084 11:10:26.948827 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4085 11:10:26.949358
4086 11:10:26.949786
4087 11:10:26.950096 ==
4088 11:10:26.951973 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 11:10:26.955364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 11:10:26.958389 ==
4091 11:10:26.958806
4092 11:10:26.959135
4093 11:10:26.959443 TX Vref Scan disable
4094 11:10:26.961911 == TX Byte 0 ==
4095 11:10:26.965434 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4096 11:10:26.968445 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4097 11:10:26.971952 == TX Byte 1 ==
4098 11:10:26.974982 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4099 11:10:26.981913 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4100 11:10:26.982431 ==
4101 11:10:26.985376 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 11:10:26.988630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 11:10:26.989145 ==
4104 11:10:26.989512
4105 11:10:26.989827
4106 11:10:26.991842 TX Vref Scan disable
4107 11:10:26.994954 == TX Byte 0 ==
4108 11:10:26.997902 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4109 11:10:27.001572 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4110 11:10:27.004936 == TX Byte 1 ==
4111 11:10:27.007780 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4112 11:10:27.011065 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4113 11:10:27.011485
4114 11:10:27.011815 [DATLAT]
4115 11:10:27.014632 Freq=600, CH0 RK0
4116 11:10:27.015147
4117 11:10:27.017997 DATLAT Default: 0x9
4118 11:10:27.018685 0, 0xFFFF, sum = 0
4119 11:10:27.021517 1, 0xFFFF, sum = 0
4120 11:10:27.022036 2, 0xFFFF, sum = 0
4121 11:10:27.024594 3, 0xFFFF, sum = 0
4122 11:10:27.025110 4, 0xFFFF, sum = 0
4123 11:10:27.027980 5, 0xFFFF, sum = 0
4124 11:10:27.028527 6, 0xFFFF, sum = 0
4125 11:10:27.031195 7, 0xFFFF, sum = 0
4126 11:10:27.031616 8, 0x0, sum = 1
4127 11:10:27.034119 9, 0x0, sum = 2
4128 11:10:27.034589 10, 0x0, sum = 3
4129 11:10:27.037785 11, 0x0, sum = 4
4130 11:10:27.038207 best_step = 9
4131 11:10:27.038569
4132 11:10:27.039053 ==
4133 11:10:27.040766 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 11:10:27.044325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 11:10:27.044840 ==
4136 11:10:27.047828 RX Vref Scan: 1
4137 11:10:27.048335
4138 11:10:27.051171 RX Vref 0 -> 0, step: 1
4139 11:10:27.051682
4140 11:10:27.052013 RX Delay -195 -> 252, step: 8
4141 11:10:27.052321
4142 11:10:27.054521 Set Vref, RX VrefLevel [Byte0]: 61
4143 11:10:27.057596 [Byte1]: 48
4144 11:10:27.062037
4145 11:10:27.062453 Final RX Vref Byte 0 = 61 to rank0
4146 11:10:27.065857 Final RX Vref Byte 1 = 48 to rank0
4147 11:10:27.068759 Final RX Vref Byte 0 = 61 to rank1
4148 11:10:27.072240 Final RX Vref Byte 1 = 48 to rank1==
4149 11:10:27.075594 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 11:10:27.082082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 11:10:27.082594 ==
4152 11:10:27.082928 DQS Delay:
4153 11:10:27.085571 DQS0 = 0, DQS1 = 0
4154 11:10:27.086080 DQM Delay:
4155 11:10:27.086415 DQM0 = 34, DQM1 = 29
4156 11:10:27.089047 DQ Delay:
4157 11:10:27.092265 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4158 11:10:27.095344 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4159 11:10:27.098588 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4160 11:10:27.102100 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4161 11:10:27.102611
4162 11:10:27.102941
4163 11:10:27.108023 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4164 11:10:27.111349 CH0 RK0: MR19=808, MR18=3B3A
4165 11:10:27.118245 CH0_RK0: MR19=0x808, MR18=0x3B3A, DQSOSC=398, MR23=63, INC=165, DEC=110
4166 11:10:27.118787
4167 11:10:27.121518 ----->DramcWriteLeveling(PI) begin...
4168 11:10:27.122039 ==
4169 11:10:27.124740 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 11:10:27.128248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 11:10:27.128761 ==
4172 11:10:27.131459 Write leveling (Byte 0): 34 => 34
4173 11:10:27.134680 Write leveling (Byte 1): 30 => 30
4174 11:10:27.137847 DramcWriteLeveling(PI) end<-----
4175 11:10:27.138264
4176 11:10:27.138591 ==
4177 11:10:27.141125 Dram Type= 6, Freq= 0, CH_0, rank 1
4178 11:10:27.144523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 11:10:27.148000 ==
4180 11:10:27.148514 [Gating] SW mode calibration
4181 11:10:27.157813 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4182 11:10:27.160808 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4183 11:10:27.164576 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 11:10:27.170987 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 11:10:27.174015 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 11:10:27.177904 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4187 11:10:27.184216 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4188 11:10:27.187753 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 11:10:27.191073 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 11:10:27.197251 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 11:10:27.201084 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 11:10:27.204099 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 11:10:27.210279 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 11:10:27.214152 0 10 12 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
4195 11:10:27.217401 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4196 11:10:27.224081 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 11:10:27.227180 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 11:10:27.230145 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 11:10:27.237069 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 11:10:27.240179 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 11:10:27.243471 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 11:10:27.250172 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 11:10:27.253723 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4204 11:10:27.257178 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 11:10:27.263916 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 11:10:27.266639 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 11:10:27.270264 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 11:10:27.276973 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 11:10:27.280428 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 11:10:27.283428 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 11:10:27.290417 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 11:10:27.293405 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 11:10:27.296538 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 11:10:27.303766 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 11:10:27.306736 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 11:10:27.309787 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 11:10:27.316637 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 11:10:27.319961 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4219 11:10:27.322947 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4220 11:10:27.326242 Total UI for P1: 0, mck2ui 16
4221 11:10:27.330106 best dqsien dly found for B0: ( 0, 13, 12)
4222 11:10:27.336323 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 11:10:27.336823 Total UI for P1: 0, mck2ui 16
4224 11:10:27.342734 best dqsien dly found for B1: ( 0, 13, 16)
4225 11:10:27.346085 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4226 11:10:27.349575 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4227 11:10:27.350086
4228 11:10:27.353037 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4229 11:10:27.356331 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4230 11:10:27.359550 [Gating] SW calibration Done
4231 11:10:27.360063 ==
4232 11:10:27.362950 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 11:10:27.366116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 11:10:27.366677 ==
4235 11:10:27.369370 RX Vref Scan: 0
4236 11:10:27.369910
4237 11:10:27.370245 RX Vref 0 -> 0, step: 1
4238 11:10:27.370554
4239 11:10:27.372900 RX Delay -230 -> 252, step: 16
4240 11:10:27.379375 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4241 11:10:27.382523 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4242 11:10:27.385840 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4243 11:10:27.389295 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4244 11:10:27.392839 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4245 11:10:27.399341 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4246 11:10:27.402454 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4247 11:10:27.405735 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4248 11:10:27.408670 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4249 11:10:27.415943 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4250 11:10:27.418863 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4251 11:10:27.422486 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4252 11:10:27.425640 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4253 11:10:27.431906 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4254 11:10:27.435457 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4255 11:10:27.438697 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4256 11:10:27.439118 ==
4257 11:10:27.442184 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 11:10:27.445286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 11:10:27.445755 ==
4260 11:10:27.448998 DQS Delay:
4261 11:10:27.449556 DQS0 = 0, DQS1 = 0
4262 11:10:27.452430 DQM Delay:
4263 11:10:27.452938 DQM0 = 36, DQM1 = 29
4264 11:10:27.453269 DQ Delay:
4265 11:10:27.455202 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4266 11:10:27.458992 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4267 11:10:27.462167 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4268 11:10:27.465716 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4269 11:10:27.466226
4270 11:10:27.466558
4271 11:10:27.466863 ==
4272 11:10:27.468839 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 11:10:27.475524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 11:10:27.476041 ==
4275 11:10:27.476377
4276 11:10:27.476681
4277 11:10:27.479007 TX Vref Scan disable
4278 11:10:27.479513 == TX Byte 0 ==
4279 11:10:27.482108 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4280 11:10:27.488445 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4281 11:10:27.488959 == TX Byte 1 ==
4282 11:10:27.492062 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4283 11:10:27.498416 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4284 11:10:27.498928 ==
4285 11:10:27.501676 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 11:10:27.505409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 11:10:27.505965 ==
4288 11:10:27.506301
4289 11:10:27.506611
4290 11:10:27.508512 TX Vref Scan disable
4291 11:10:27.511632 == TX Byte 0 ==
4292 11:10:27.514793 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4293 11:10:27.518071 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4294 11:10:27.521504 == TX Byte 1 ==
4295 11:10:27.524716 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4296 11:10:27.528172 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4297 11:10:27.528585
4298 11:10:27.531473 [DATLAT]
4299 11:10:27.531886 Freq=600, CH0 RK1
4300 11:10:27.532211
4301 11:10:27.534885 DATLAT Default: 0x9
4302 11:10:27.535294 0, 0xFFFF, sum = 0
4303 11:10:27.538007 1, 0xFFFF, sum = 0
4304 11:10:27.538345 2, 0xFFFF, sum = 0
4305 11:10:27.541327 3, 0xFFFF, sum = 0
4306 11:10:27.541664 4, 0xFFFF, sum = 0
4307 11:10:27.544821 5, 0xFFFF, sum = 0
4308 11:10:27.545210 6, 0xFFFF, sum = 0
4309 11:10:27.548110 7, 0xFFFF, sum = 0
4310 11:10:27.548496 8, 0x0, sum = 1
4311 11:10:27.551599 9, 0x0, sum = 2
4312 11:10:27.551986 10, 0x0, sum = 3
4313 11:10:27.554747 11, 0x0, sum = 4
4314 11:10:27.555092 best_step = 9
4315 11:10:27.555327
4316 11:10:27.555543 ==
4317 11:10:27.558065 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 11:10:27.561107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 11:10:27.564453 ==
4320 11:10:27.564746 RX Vref Scan: 0
4321 11:10:27.564979
4322 11:10:27.568351 RX Vref 0 -> 0, step: 1
4323 11:10:27.568732
4324 11:10:27.570960 RX Delay -195 -> 252, step: 8
4325 11:10:27.574526 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4326 11:10:27.581282 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4327 11:10:27.584707 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4328 11:10:27.587848 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4329 11:10:27.591126 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4330 11:10:27.594217 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4331 11:10:27.600791 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4332 11:10:27.604177 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4333 11:10:27.607451 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4334 11:10:27.610666 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4335 11:10:27.618046 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4336 11:10:27.621080 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4337 11:10:27.623860 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4338 11:10:27.627788 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4339 11:10:27.634121 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4340 11:10:27.637243 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4341 11:10:27.637727 ==
4342 11:10:27.640743 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 11:10:27.643985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 11:10:27.644505 ==
4345 11:10:27.647214 DQS Delay:
4346 11:10:27.647624 DQS0 = 0, DQS1 = 0
4347 11:10:27.647946 DQM Delay:
4348 11:10:27.650721 DQM0 = 33, DQM1 = 28
4349 11:10:27.651247 DQ Delay:
4350 11:10:27.654015 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4351 11:10:27.657618 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4352 11:10:27.660687 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4353 11:10:27.664322 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4354 11:10:27.664836
4355 11:10:27.665161
4356 11:10:27.674024 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4357 11:10:27.674507 CH0 RK1: MR19=808, MR18=6A38
4358 11:10:27.680673 CH0_RK1: MR19=0x808, MR18=0x6A38, DQSOSC=389, MR23=63, INC=173, DEC=115
4359 11:10:27.683947 [RxdqsGatingPostProcess] freq 600
4360 11:10:27.690882 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4361 11:10:27.693923 Pre-setting of DQS Precalculation
4362 11:10:27.697390 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4363 11:10:27.697939 ==
4364 11:10:27.700337 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 11:10:27.706902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 11:10:27.707415 ==
4367 11:10:27.710015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4368 11:10:27.717019 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4369 11:10:27.720014 [CA 0] Center 35 (5~66) winsize 62
4370 11:10:27.723641 [CA 1] Center 36 (6~66) winsize 61
4371 11:10:27.727022 [CA 2] Center 34 (4~65) winsize 62
4372 11:10:27.730433 [CA 3] Center 34 (4~65) winsize 62
4373 11:10:27.733526 [CA 4] Center 34 (4~65) winsize 62
4374 11:10:27.736555 [CA 5] Center 33 (3~64) winsize 62
4375 11:10:27.736990
4376 11:10:27.739947 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4377 11:10:27.740359
4378 11:10:27.743478 [CATrainingPosCal] consider 1 rank data
4379 11:10:27.746681 u2DelayCellTimex100 = 270/100 ps
4380 11:10:27.749745 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4381 11:10:27.756473 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4382 11:10:27.759564 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 11:10:27.762848 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4384 11:10:27.766462 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4385 11:10:27.769792 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4386 11:10:27.770218
4387 11:10:27.773013 CA PerBit enable=1, Macro0, CA PI delay=33
4388 11:10:27.773438
4389 11:10:27.776034 [CBTSetCACLKResult] CA Dly = 33
4390 11:10:27.779517 CS Dly: 4 (0~35)
4391 11:10:27.779806 ==
4392 11:10:27.782805 Dram Type= 6, Freq= 0, CH_1, rank 1
4393 11:10:27.785933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 11:10:27.786153 ==
4395 11:10:27.792315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4396 11:10:27.795599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4397 11:10:27.799639 [CA 0] Center 36 (6~66) winsize 61
4398 11:10:27.803119 [CA 1] Center 36 (6~67) winsize 62
4399 11:10:27.806507 [CA 2] Center 34 (4~65) winsize 62
4400 11:10:27.809811 [CA 3] Center 34 (3~65) winsize 63
4401 11:10:27.813057 [CA 4] Center 34 (4~65) winsize 62
4402 11:10:27.816427 [CA 5] Center 33 (3~64) winsize 62
4403 11:10:27.816519
4404 11:10:27.819563 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4405 11:10:27.819647
4406 11:10:27.823069 [CATrainingPosCal] consider 2 rank data
4407 11:10:27.826411 u2DelayCellTimex100 = 270/100 ps
4408 11:10:27.829552 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4409 11:10:27.832907 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4410 11:10:27.839571 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 11:10:27.842857 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4412 11:10:27.846127 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4413 11:10:27.849627 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 11:10:27.849710
4415 11:10:27.852703 CA PerBit enable=1, Macro0, CA PI delay=33
4416 11:10:27.852784
4417 11:10:27.856239 [CBTSetCACLKResult] CA Dly = 33
4418 11:10:27.856322 CS Dly: 5 (0~37)
4419 11:10:27.859515
4420 11:10:27.862772 ----->DramcWriteLeveling(PI) begin...
4421 11:10:27.862857 ==
4422 11:10:27.865897 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 11:10:27.869280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 11:10:27.869366 ==
4425 11:10:27.872567 Write leveling (Byte 0): 29 => 29
4426 11:10:27.875722 Write leveling (Byte 1): 28 => 28
4427 11:10:27.879114 DramcWriteLeveling(PI) end<-----
4428 11:10:27.879203
4429 11:10:27.879268 ==
4430 11:10:27.882454 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 11:10:27.885823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 11:10:27.885907 ==
4433 11:10:27.889188 [Gating] SW mode calibration
4434 11:10:27.895731 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4435 11:10:27.902153 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4436 11:10:27.905740 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 11:10:27.908888 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 11:10:27.915506 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 11:10:27.918784 0 9 12 | B1->B0 | 3232 3232 | 0 1 | (0 1) (1 1)
4440 11:10:27.922334 0 9 16 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
4441 11:10:27.928935 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 11:10:27.931873 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 11:10:27.935244 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 11:10:27.941933 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 11:10:27.945312 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 11:10:27.948588 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 11:10:27.955106 0 10 12 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 0)
4448 11:10:27.958491 0 10 16 | B1->B0 | 3f3f 4040 | 0 0 | (0 0) (0 0)
4449 11:10:27.961827 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 11:10:27.968354 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 11:10:27.971534 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 11:10:27.974753 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 11:10:27.981665 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 11:10:27.984992 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 11:10:27.988323 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 11:10:27.995063 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 11:10:27.998339 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 11:10:28.001582 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 11:10:28.008278 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 11:10:28.011177 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 11:10:28.014903 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 11:10:28.021403 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 11:10:28.024553 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 11:10:28.027911 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 11:10:28.034584 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 11:10:28.037833 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 11:10:28.040918 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 11:10:28.047562 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 11:10:28.050788 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 11:10:28.053912 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 11:10:28.061095 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4472 11:10:28.061327 Total UI for P1: 0, mck2ui 16
4473 11:10:28.067560 best dqsien dly found for B0: ( 0, 13, 10)
4474 11:10:28.070780 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4475 11:10:28.074166 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 11:10:28.077880 Total UI for P1: 0, mck2ui 16
4477 11:10:28.081043 best dqsien dly found for B1: ( 0, 13, 14)
4478 11:10:28.084217 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4479 11:10:28.087789 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4480 11:10:28.088269
4481 11:10:28.094393 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4482 11:10:28.097655 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4483 11:10:28.098168 [Gating] SW calibration Done
4484 11:10:28.100643 ==
4485 11:10:28.104318 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 11:10:28.107282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 11:10:28.107701 ==
4488 11:10:28.108032 RX Vref Scan: 0
4489 11:10:28.108339
4490 11:10:28.110420 RX Vref 0 -> 0, step: 1
4491 11:10:28.110834
4492 11:10:28.114069 RX Delay -230 -> 252, step: 16
4493 11:10:28.117194 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4494 11:10:28.120890 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4495 11:10:28.127301 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4496 11:10:28.130249 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4497 11:10:28.133595 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4498 11:10:28.137015 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4499 11:10:28.143484 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4500 11:10:28.146845 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4501 11:10:28.150095 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4502 11:10:28.153592 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4503 11:10:28.156678 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4504 11:10:28.163827 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4505 11:10:28.167124 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4506 11:10:28.169990 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4507 11:10:28.177070 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4508 11:10:28.180195 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4509 11:10:28.180699 ==
4510 11:10:28.183658 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 11:10:28.186758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 11:10:28.187267 ==
4513 11:10:28.187598 DQS Delay:
4514 11:10:28.190052 DQS0 = 0, DQS1 = 0
4515 11:10:28.190463 DQM Delay:
4516 11:10:28.193129 DQM0 = 37, DQM1 = 28
4517 11:10:28.193599 DQ Delay:
4518 11:10:28.196810 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4519 11:10:28.200044 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4520 11:10:28.203506 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4521 11:10:28.206671 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4522 11:10:28.207217
4523 11:10:28.207549
4524 11:10:28.207851 ==
4525 11:10:28.209980 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 11:10:28.216366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 11:10:28.216881 ==
4528 11:10:28.217209
4529 11:10:28.217563
4530 11:10:28.217865 TX Vref Scan disable
4531 11:10:28.219736 == TX Byte 0 ==
4532 11:10:28.223218 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4533 11:10:28.229948 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4534 11:10:28.230450 == TX Byte 1 ==
4535 11:10:28.233153 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4536 11:10:28.239686 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4537 11:10:28.240103 ==
4538 11:10:28.243342 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 11:10:28.246339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 11:10:28.246764 ==
4541 11:10:28.247092
4542 11:10:28.247394
4543 11:10:28.249373 TX Vref Scan disable
4544 11:10:28.252938 == TX Byte 0 ==
4545 11:10:28.256296 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 11:10:28.259531 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 11:10:28.262659 == TX Byte 1 ==
4548 11:10:28.266279 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4549 11:10:28.269846 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4550 11:10:28.270354
4551 11:10:28.270750 [DATLAT]
4552 11:10:28.272832 Freq=600, CH1 RK0
4553 11:10:28.273344
4554 11:10:28.276311 DATLAT Default: 0x9
4555 11:10:28.276820 0, 0xFFFF, sum = 0
4556 11:10:28.279394 1, 0xFFFF, sum = 0
4557 11:10:28.279910 2, 0xFFFF, sum = 0
4558 11:10:28.282587 3, 0xFFFF, sum = 0
4559 11:10:28.283101 4, 0xFFFF, sum = 0
4560 11:10:28.286109 5, 0xFFFF, sum = 0
4561 11:10:28.286627 6, 0xFFFF, sum = 0
4562 11:10:28.289453 7, 0xFFFF, sum = 0
4563 11:10:28.290010 8, 0x0, sum = 1
4564 11:10:28.292880 9, 0x0, sum = 2
4565 11:10:28.293395 10, 0x0, sum = 3
4566 11:10:28.296448 11, 0x0, sum = 4
4567 11:10:28.296958 best_step = 9
4568 11:10:28.297284
4569 11:10:28.297624 ==
4570 11:10:28.299222 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 11:10:28.302259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 11:10:28.302668 ==
4573 11:10:28.305975 RX Vref Scan: 1
4574 11:10:28.306477
4575 11:10:28.309064 RX Vref 0 -> 0, step: 1
4576 11:10:28.309620
4577 11:10:28.309960 RX Delay -195 -> 252, step: 8
4578 11:10:28.310269
4579 11:10:28.312158 Set Vref, RX VrefLevel [Byte0]: 57
4580 11:10:28.315523 [Byte1]: 51
4581 11:10:28.320635
4582 11:10:28.321144 Final RX Vref Byte 0 = 57 to rank0
4583 11:10:28.324048 Final RX Vref Byte 1 = 51 to rank0
4584 11:10:28.326989 Final RX Vref Byte 0 = 57 to rank1
4585 11:10:28.330718 Final RX Vref Byte 1 = 51 to rank1==
4586 11:10:28.333590 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 11:10:28.340279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 11:10:28.340778 ==
4589 11:10:28.341112 DQS Delay:
4590 11:10:28.343603 DQS0 = 0, DQS1 = 0
4591 11:10:28.344113 DQM Delay:
4592 11:10:28.344464 DQM0 = 40, DQM1 = 28
4593 11:10:28.346601 DQ Delay:
4594 11:10:28.349999 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4595 11:10:28.353429 DQ4 =36, DQ5 =52, DQ6 =52, DQ7 =36
4596 11:10:28.356707 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4597 11:10:28.360252 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4598 11:10:28.360761
4599 11:10:28.361096
4600 11:10:28.366625 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f2c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
4601 11:10:28.370349 CH1 RK0: MR19=808, MR18=1F2C
4602 11:10:28.377141 CH1_RK0: MR19=0x808, MR18=0x1F2C, DQSOSC=401, MR23=63, INC=163, DEC=108
4603 11:10:28.377684
4604 11:10:28.380108 ----->DramcWriteLeveling(PI) begin...
4605 11:10:28.380626 ==
4606 11:10:28.383589 Dram Type= 6, Freq= 0, CH_1, rank 1
4607 11:10:28.386785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 11:10:28.387297 ==
4609 11:10:28.390220 Write leveling (Byte 0): 31 => 31
4610 11:10:28.393313 Write leveling (Byte 1): 28 => 28
4611 11:10:28.396941 DramcWriteLeveling(PI) end<-----
4612 11:10:28.397449
4613 11:10:28.397847 ==
4614 11:10:28.399933 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 11:10:28.403496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 11:10:28.406306 ==
4617 11:10:28.406819 [Gating] SW mode calibration
4618 11:10:28.412683 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4619 11:10:28.419632 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4620 11:10:28.422699 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4621 11:10:28.429621 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 11:10:28.433000 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4623 11:10:28.436064 0 9 12 | B1->B0 | 3030 2a2a | 1 0 | (0 1) (0 0)
4624 11:10:28.443020 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4625 11:10:28.445972 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 11:10:28.449268 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 11:10:28.456022 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 11:10:28.459131 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 11:10:28.462458 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 11:10:28.469189 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4631 11:10:28.472614 0 10 12 | B1->B0 | 3333 3a3a | 0 0 | (0 0) (0 0)
4632 11:10:28.475943 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4633 11:10:28.482150 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 11:10:28.485822 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 11:10:28.488752 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 11:10:28.495995 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 11:10:28.498990 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 11:10:28.502382 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 11:10:28.508610 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4640 11:10:28.511970 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 11:10:28.515122 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 11:10:28.522082 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 11:10:28.525279 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 11:10:28.528311 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 11:10:28.535323 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 11:10:28.538213 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 11:10:28.541624 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 11:10:28.548456 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 11:10:28.551943 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 11:10:28.555349 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 11:10:28.561831 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 11:10:28.565131 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 11:10:28.568391 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 11:10:28.574719 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4655 11:10:28.578135 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4656 11:10:28.581627 Total UI for P1: 0, mck2ui 16
4657 11:10:28.584876 best dqsien dly found for B0: ( 0, 13, 8)
4658 11:10:28.588428 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 11:10:28.591622 Total UI for P1: 0, mck2ui 16
4660 11:10:28.594620 best dqsien dly found for B1: ( 0, 13, 14)
4661 11:10:28.597724 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4662 11:10:28.601550 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4663 11:10:28.602061
4664 11:10:28.604657 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4665 11:10:28.610904 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4666 11:10:28.611402 [Gating] SW calibration Done
4667 11:10:28.614186 ==
4668 11:10:28.614629 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 11:10:28.621262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 11:10:28.621814 ==
4671 11:10:28.622141 RX Vref Scan: 0
4672 11:10:28.622442
4673 11:10:28.624298 RX Vref 0 -> 0, step: 1
4674 11:10:28.624708
4675 11:10:28.628133 RX Delay -230 -> 252, step: 16
4676 11:10:28.630864 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4677 11:10:28.634375 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4678 11:10:28.641021 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4679 11:10:28.644225 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4680 11:10:28.647488 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4681 11:10:28.650731 iDelay=218, Bit 5, Center 41 (-134 ~ 217) 352
4682 11:10:28.654143 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4683 11:10:28.660893 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4684 11:10:28.664405 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4685 11:10:28.667107 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4686 11:10:28.670703 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4687 11:10:28.677716 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4688 11:10:28.680644 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4689 11:10:28.684341 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4690 11:10:28.687019 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4691 11:10:28.693723 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4692 11:10:28.694338 ==
4693 11:10:28.696896 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 11:10:28.700427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 11:10:28.700943 ==
4696 11:10:28.701278 DQS Delay:
4697 11:10:28.704054 DQS0 = 0, DQS1 = 0
4698 11:10:28.704563 DQM Delay:
4699 11:10:28.706756 DQM0 = 35, DQM1 = 30
4700 11:10:28.707171 DQ Delay:
4701 11:10:28.710339 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4702 11:10:28.713424 DQ4 =33, DQ5 =41, DQ6 =41, DQ7 =33
4703 11:10:28.716706 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4704 11:10:28.720560 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4705 11:10:28.721075
4706 11:10:28.721407
4707 11:10:28.721773 ==
4708 11:10:28.723485 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 11:10:28.726612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 11:10:28.730210 ==
4711 11:10:28.730733
4712 11:10:28.731065
4713 11:10:28.731370 TX Vref Scan disable
4714 11:10:28.733437 == TX Byte 0 ==
4715 11:10:28.736715 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4716 11:10:28.743255 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4717 11:10:28.743762 == TX Byte 1 ==
4718 11:10:28.746287 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4719 11:10:28.753412 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4720 11:10:28.753962 ==
4721 11:10:28.756534 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 11:10:28.759734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 11:10:28.760250 ==
4724 11:10:28.760583
4725 11:10:28.760890
4726 11:10:28.763056 TX Vref Scan disable
4727 11:10:28.766233 == TX Byte 0 ==
4728 11:10:28.769636 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4729 11:10:28.772933 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4730 11:10:28.776547 == TX Byte 1 ==
4731 11:10:28.779933 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4732 11:10:28.783283 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4733 11:10:28.783796
4734 11:10:28.784124 [DATLAT]
4735 11:10:28.786068 Freq=600, CH1 RK1
4736 11:10:28.786477
4737 11:10:28.789769 DATLAT Default: 0x9
4738 11:10:28.790282 0, 0xFFFF, sum = 0
4739 11:10:28.793117 1, 0xFFFF, sum = 0
4740 11:10:28.793671 2, 0xFFFF, sum = 0
4741 11:10:28.796046 3, 0xFFFF, sum = 0
4742 11:10:28.796458 4, 0xFFFF, sum = 0
4743 11:10:28.799747 5, 0xFFFF, sum = 0
4744 11:10:28.800311 6, 0xFFFF, sum = 0
4745 11:10:28.802735 7, 0xFFFF, sum = 0
4746 11:10:28.803246 8, 0x0, sum = 1
4747 11:10:28.805866 9, 0x0, sum = 2
4748 11:10:28.806385 10, 0x0, sum = 3
4749 11:10:28.809212 11, 0x0, sum = 4
4750 11:10:28.809778 best_step = 9
4751 11:10:28.810107
4752 11:10:28.810407 ==
4753 11:10:28.812712 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 11:10:28.815680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 11:10:28.816093 ==
4756 11:10:28.819166 RX Vref Scan: 0
4757 11:10:28.819576
4758 11:10:28.822568 RX Vref 0 -> 0, step: 1
4759 11:10:28.822976
4760 11:10:28.823296 RX Delay -195 -> 252, step: 8
4761 11:10:28.830625 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4762 11:10:28.834113 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4763 11:10:28.837147 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4764 11:10:28.840489 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4765 11:10:28.847091 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4766 11:10:28.850159 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4767 11:10:28.853982 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4768 11:10:28.856924 iDelay=205, Bit 7, Center 32 (-131 ~ 196) 328
4769 11:10:28.863591 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4770 11:10:28.866593 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4771 11:10:28.870022 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4772 11:10:28.873347 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4773 11:10:28.876572 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4774 11:10:28.883450 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4775 11:10:28.886700 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4776 11:10:28.890181 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4777 11:10:28.890795 ==
4778 11:10:28.893204 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 11:10:28.899631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 11:10:28.900175 ==
4781 11:10:28.900640 DQS Delay:
4782 11:10:28.903410 DQS0 = 0, DQS1 = 0
4783 11:10:28.904016 DQM Delay:
4784 11:10:28.904358 DQM0 = 36, DQM1 = 30
4785 11:10:28.906259 DQ Delay:
4786 11:10:28.909509 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4787 11:10:28.912951 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4788 11:10:28.915919 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =20
4789 11:10:28.919536 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4790 11:10:28.919945
4791 11:10:28.920264
4792 11:10:28.926130 [DQSOSCAuto] RK1, (LSB)MR18= 0x3051, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4793 11:10:28.929283 CH1 RK1: MR19=808, MR18=3051
4794 11:10:28.935919 CH1_RK1: MR19=0x808, MR18=0x3051, DQSOSC=394, MR23=63, INC=168, DEC=112
4795 11:10:28.939113 [RxdqsGatingPostProcess] freq 600
4796 11:10:28.942739 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4797 11:10:28.945898 Pre-setting of DQS Precalculation
4798 11:10:28.952379 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4799 11:10:28.959081 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4800 11:10:28.966010 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4801 11:10:28.966523
4802 11:10:28.966845
4803 11:10:28.969460 [Calibration Summary] 1200 Mbps
4804 11:10:28.970033 CH 0, Rank 0
4805 11:10:28.972578 SW Impedance : PASS
4806 11:10:28.976084 DUTY Scan : NO K
4807 11:10:28.976592 ZQ Calibration : PASS
4808 11:10:28.979442 Jitter Meter : NO K
4809 11:10:28.982721 CBT Training : PASS
4810 11:10:28.983230 Write leveling : PASS
4811 11:10:28.986098 RX DQS gating : PASS
4812 11:10:28.989116 RX DQ/DQS(RDDQC) : PASS
4813 11:10:28.989674 TX DQ/DQS : PASS
4814 11:10:28.992590 RX DATLAT : PASS
4815 11:10:28.996194 RX DQ/DQS(Engine): PASS
4816 11:10:28.996733 TX OE : NO K
4817 11:10:28.999118 All Pass.
4818 11:10:28.999622
4819 11:10:28.999953 CH 0, Rank 1
4820 11:10:29.002072 SW Impedance : PASS
4821 11:10:29.002482 DUTY Scan : NO K
4822 11:10:29.005873 ZQ Calibration : PASS
4823 11:10:29.009210 Jitter Meter : NO K
4824 11:10:29.009781 CBT Training : PASS
4825 11:10:29.012386 Write leveling : PASS
4826 11:10:29.015348 RX DQS gating : PASS
4827 11:10:29.015759 RX DQ/DQS(RDDQC) : PASS
4828 11:10:29.018891 TX DQ/DQS : PASS
4829 11:10:29.019456 RX DATLAT : PASS
4830 11:10:29.022138 RX DQ/DQS(Engine): PASS
4831 11:10:29.025875 TX OE : NO K
4832 11:10:29.026450 All Pass.
4833 11:10:29.026784
4834 11:10:29.027086 CH 1, Rank 0
4835 11:10:29.028559 SW Impedance : PASS
4836 11:10:29.032031 DUTY Scan : NO K
4837 11:10:29.032555 ZQ Calibration : PASS
4838 11:10:29.035036 Jitter Meter : NO K
4839 11:10:29.038725 CBT Training : PASS
4840 11:10:29.039235 Write leveling : PASS
4841 11:10:29.042109 RX DQS gating : PASS
4842 11:10:29.044958 RX DQ/DQS(RDDQC) : PASS
4843 11:10:29.045369 TX DQ/DQS : PASS
4844 11:10:29.048402 RX DATLAT : PASS
4845 11:10:29.051895 RX DQ/DQS(Engine): PASS
4846 11:10:29.052303 TX OE : NO K
4847 11:10:29.054967 All Pass.
4848 11:10:29.055373
4849 11:10:29.055692 CH 1, Rank 1
4850 11:10:29.058492 SW Impedance : PASS
4851 11:10:29.058897 DUTY Scan : NO K
4852 11:10:29.062013 ZQ Calibration : PASS
4853 11:10:29.064817 Jitter Meter : NO K
4854 11:10:29.065317 CBT Training : PASS
4855 11:10:29.068657 Write leveling : PASS
4856 11:10:29.071924 RX DQS gating : PASS
4857 11:10:29.072474 RX DQ/DQS(RDDQC) : PASS
4858 11:10:29.075283 TX DQ/DQS : PASS
4859 11:10:29.078362 RX DATLAT : PASS
4860 11:10:29.078774 RX DQ/DQS(Engine): PASS
4861 11:10:29.081849 TX OE : NO K
4862 11:10:29.082360 All Pass.
4863 11:10:29.082685
4864 11:10:29.085252 DramC Write-DBI off
4865 11:10:29.088424 PER_BANK_REFRESH: Hybrid Mode
4866 11:10:29.088967 TX_TRACKING: ON
4867 11:10:29.098104 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4868 11:10:29.101528 [FAST_K] Save calibration result to emmc
4869 11:10:29.104799 dramc_set_vcore_voltage set vcore to 662500
4870 11:10:29.107862 Read voltage for 933, 3
4871 11:10:29.108276 Vio18 = 0
4872 11:10:29.108599 Vcore = 662500
4873 11:10:29.111391 Vdram = 0
4874 11:10:29.111801 Vddq = 0
4875 11:10:29.112121 Vmddr = 0
4876 11:10:29.118008 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4877 11:10:29.121614 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4878 11:10:29.124386 MEM_TYPE=3, freq_sel=17
4879 11:10:29.127830 sv_algorithm_assistance_LP4_1600
4880 11:10:29.131356 ============ PULL DRAM RESETB DOWN ============
4881 11:10:29.134493 ========== PULL DRAM RESETB DOWN end =========
4882 11:10:29.141209 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4883 11:10:29.144288 ===================================
4884 11:10:29.144787 LPDDR4 DRAM CONFIGURATION
4885 11:10:29.147625 ===================================
4886 11:10:29.151018 EX_ROW_EN[0] = 0x0
4887 11:10:29.154102 EX_ROW_EN[1] = 0x0
4888 11:10:29.154510 LP4Y_EN = 0x0
4889 11:10:29.157704 WORK_FSP = 0x0
4890 11:10:29.158220 WL = 0x3
4891 11:10:29.160900 RL = 0x3
4892 11:10:29.161436 BL = 0x2
4893 11:10:29.164358 RPST = 0x0
4894 11:10:29.164870 RD_PRE = 0x0
4895 11:10:29.167640 WR_PRE = 0x1
4896 11:10:29.168151 WR_PST = 0x0
4897 11:10:29.170960 DBI_WR = 0x0
4898 11:10:29.171477 DBI_RD = 0x0
4899 11:10:29.174164 OTF = 0x1
4900 11:10:29.177349 ===================================
4901 11:10:29.180697 ===================================
4902 11:10:29.181116 ANA top config
4903 11:10:29.183890 ===================================
4904 11:10:29.187307 DLL_ASYNC_EN = 0
4905 11:10:29.190356 ALL_SLAVE_EN = 1
4906 11:10:29.193919 NEW_RANK_MODE = 1
4907 11:10:29.194339 DLL_IDLE_MODE = 1
4908 11:10:29.197014 LP45_APHY_COMB_EN = 1
4909 11:10:29.200436 TX_ODT_DIS = 1
4910 11:10:29.203502 NEW_8X_MODE = 1
4911 11:10:29.206891 ===================================
4912 11:10:29.210041 ===================================
4913 11:10:29.213403 data_rate = 1866
4914 11:10:29.213621 CKR = 1
4915 11:10:29.216595 DQ_P2S_RATIO = 8
4916 11:10:29.220273 ===================================
4917 11:10:29.223282 CA_P2S_RATIO = 8
4918 11:10:29.226657 DQ_CA_OPEN = 0
4919 11:10:29.229873 DQ_SEMI_OPEN = 0
4920 11:10:29.233368 CA_SEMI_OPEN = 0
4921 11:10:29.233470 CA_FULL_RATE = 0
4922 11:10:29.236639 DQ_CKDIV4_EN = 1
4923 11:10:29.239967 CA_CKDIV4_EN = 1
4924 11:10:29.243186 CA_PREDIV_EN = 0
4925 11:10:29.246339 PH8_DLY = 0
4926 11:10:29.249622 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4927 11:10:29.249706 DQ_AAMCK_DIV = 4
4928 11:10:29.253203 CA_AAMCK_DIV = 4
4929 11:10:29.256281 CA_ADMCK_DIV = 4
4930 11:10:29.259633 DQ_TRACK_CA_EN = 0
4931 11:10:29.263174 CA_PICK = 933
4932 11:10:29.266383 CA_MCKIO = 933
4933 11:10:29.269739 MCKIO_SEMI = 0
4934 11:10:29.269822 PLL_FREQ = 3732
4935 11:10:29.272889 DQ_UI_PI_RATIO = 32
4936 11:10:29.276249 CA_UI_PI_RATIO = 0
4937 11:10:29.279517 ===================================
4938 11:10:29.282743 ===================================
4939 11:10:29.285972 memory_type:LPDDR4
4940 11:10:29.289350 GP_NUM : 10
4941 11:10:29.289431 SRAM_EN : 1
4942 11:10:29.292827 MD32_EN : 0
4943 11:10:29.295880 ===================================
4944 11:10:29.295961 [ANA_INIT] >>>>>>>>>>>>>>
4945 11:10:29.299515 <<<<<< [CONFIGURE PHASE]: ANA_TX
4946 11:10:29.302611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4947 11:10:29.305988 ===================================
4948 11:10:29.309332 data_rate = 1866,PCW = 0X8f00
4949 11:10:29.312565 ===================================
4950 11:10:29.315904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4951 11:10:29.322190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4952 11:10:29.328936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4953 11:10:29.332363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4954 11:10:29.335445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4955 11:10:29.338894 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4956 11:10:29.342347 [ANA_INIT] flow start
4957 11:10:29.342429 [ANA_INIT] PLL >>>>>>>>
4958 11:10:29.345594 [ANA_INIT] PLL <<<<<<<<
4959 11:10:29.349079 [ANA_INIT] MIDPI >>>>>>>>
4960 11:10:29.349161 [ANA_INIT] MIDPI <<<<<<<<
4961 11:10:29.352292 [ANA_INIT] DLL >>>>>>>>
4962 11:10:29.355505 [ANA_INIT] flow end
4963 11:10:29.358881 ============ LP4 DIFF to SE enter ============
4964 11:10:29.361932 ============ LP4 DIFF to SE exit ============
4965 11:10:29.365331 [ANA_INIT] <<<<<<<<<<<<<
4966 11:10:29.368859 [Flow] Enable top DCM control >>>>>
4967 11:10:29.372242 [Flow] Enable top DCM control <<<<<
4968 11:10:29.375551 Enable DLL master slave shuffle
4969 11:10:29.378646 ==============================================================
4970 11:10:29.381952 Gating Mode config
4971 11:10:29.388416 ==============================================================
4972 11:10:29.388499 Config description:
4973 11:10:29.398652 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4974 11:10:29.405223 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4975 11:10:29.411670 SELPH_MODE 0: By rank 1: By Phase
4976 11:10:29.415087 ==============================================================
4977 11:10:29.418484 GAT_TRACK_EN = 1
4978 11:10:29.421518 RX_GATING_MODE = 2
4979 11:10:29.424869 RX_GATING_TRACK_MODE = 2
4980 11:10:29.428245 SELPH_MODE = 1
4981 11:10:29.431659 PICG_EARLY_EN = 1
4982 11:10:29.434857 VALID_LAT_VALUE = 1
4983 11:10:29.438205 ==============================================================
4984 11:10:29.441464 Enter into Gating configuration >>>>
4985 11:10:29.444899 Exit from Gating configuration <<<<
4986 11:10:29.448314 Enter into DVFS_PRE_config >>>>>
4987 11:10:29.461357 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4988 11:10:29.464717 Exit from DVFS_PRE_config <<<<<
4989 11:10:29.467780 Enter into PICG configuration >>>>
4990 11:10:29.471310 Exit from PICG configuration <<<<
4991 11:10:29.471391 [RX_INPUT] configuration >>>>>
4992 11:10:29.474692 [RX_INPUT] configuration <<<<<
4993 11:10:29.481281 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4994 11:10:29.484731 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4995 11:10:29.490866 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 11:10:29.497721 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 11:10:29.504240 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4998 11:10:29.511081 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4999 11:10:29.514458 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5000 11:10:29.517796 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5001 11:10:29.524094 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5002 11:10:29.527595 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5003 11:10:29.531158 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5004 11:10:29.534263 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 11:10:29.537598 ===================================
5006 11:10:29.540769 LPDDR4 DRAM CONFIGURATION
5007 11:10:29.544223 ===================================
5008 11:10:29.547324 EX_ROW_EN[0] = 0x0
5009 11:10:29.547407 EX_ROW_EN[1] = 0x0
5010 11:10:29.550577 LP4Y_EN = 0x0
5011 11:10:29.550656 WORK_FSP = 0x0
5012 11:10:29.553990 WL = 0x3
5013 11:10:29.554070 RL = 0x3
5014 11:10:29.557511 BL = 0x2
5015 11:10:29.557605 RPST = 0x0
5016 11:10:29.560484 RD_PRE = 0x0
5017 11:10:29.563712 WR_PRE = 0x1
5018 11:10:29.563791 WR_PST = 0x0
5019 11:10:29.567284 DBI_WR = 0x0
5020 11:10:29.567364 DBI_RD = 0x0
5021 11:10:29.570408 OTF = 0x1
5022 11:10:29.573745 ===================================
5023 11:10:29.577174 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5024 11:10:29.580570 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5025 11:10:29.583562 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 11:10:29.587312 ===================================
5027 11:10:29.590458 LPDDR4 DRAM CONFIGURATION
5028 11:10:29.593634 ===================================
5029 11:10:29.597130 EX_ROW_EN[0] = 0x10
5030 11:10:29.597209 EX_ROW_EN[1] = 0x0
5031 11:10:29.600178 LP4Y_EN = 0x0
5032 11:10:29.600258 WORK_FSP = 0x0
5033 11:10:29.603490 WL = 0x3
5034 11:10:29.603569 RL = 0x3
5035 11:10:29.606831 BL = 0x2
5036 11:10:29.606910 RPST = 0x0
5037 11:10:29.610230 RD_PRE = 0x0
5038 11:10:29.610310 WR_PRE = 0x1
5039 11:10:29.613257 WR_PST = 0x0
5040 11:10:29.617080 DBI_WR = 0x0
5041 11:10:29.617160 DBI_RD = 0x0
5042 11:10:29.620030 OTF = 0x1
5043 11:10:29.623215 ===================================
5044 11:10:29.626554 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5045 11:10:29.632225 nWR fixed to 30
5046 11:10:29.635497 [ModeRegInit_LP4] CH0 RK0
5047 11:10:29.635616 [ModeRegInit_LP4] CH0 RK1
5048 11:10:29.638936 [ModeRegInit_LP4] CH1 RK0
5049 11:10:29.642421 [ModeRegInit_LP4] CH1 RK1
5050 11:10:29.642580 match AC timing 9
5051 11:10:29.648724 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5052 11:10:29.652270 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5053 11:10:29.655265 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5054 11:10:29.662311 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5055 11:10:29.665393 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5056 11:10:29.665599 ==
5057 11:10:29.668503 Dram Type= 6, Freq= 0, CH_0, rank 0
5058 11:10:29.672041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 11:10:29.672213 ==
5060 11:10:29.678477 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 11:10:29.685051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 11:10:29.688350 [CA 0] Center 38 (8~69) winsize 62
5063 11:10:29.691770 [CA 1] Center 38 (8~68) winsize 61
5064 11:10:29.695002 [CA 2] Center 35 (5~66) winsize 62
5065 11:10:29.698238 [CA 3] Center 35 (5~66) winsize 62
5066 11:10:29.701506 [CA 4] Center 34 (4~64) winsize 61
5067 11:10:29.704830 [CA 5] Center 33 (3~64) winsize 62
5068 11:10:29.704909
5069 11:10:29.708167 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 11:10:29.708246
5071 11:10:29.711742 [CATrainingPosCal] consider 1 rank data
5072 11:10:29.714870 u2DelayCellTimex100 = 270/100 ps
5073 11:10:29.718065 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5074 11:10:29.721424 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5075 11:10:29.724576 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5076 11:10:29.728167 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5077 11:10:29.731331 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5078 11:10:29.738075 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5079 11:10:29.738158
5080 11:10:29.741396 CA PerBit enable=1, Macro0, CA PI delay=33
5081 11:10:29.741539
5082 11:10:29.744609 [CBTSetCACLKResult] CA Dly = 33
5083 11:10:29.744688 CS Dly: 7 (0~38)
5084 11:10:29.744749 ==
5085 11:10:29.748082 Dram Type= 6, Freq= 0, CH_0, rank 1
5086 11:10:29.751404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 11:10:29.754552 ==
5088 11:10:29.758174 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5089 11:10:29.764765 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5090 11:10:29.767811 [CA 0] Center 38 (8~69) winsize 62
5091 11:10:29.771287 [CA 1] Center 38 (8~69) winsize 62
5092 11:10:29.774506 [CA 2] Center 35 (5~66) winsize 62
5093 11:10:29.777649 [CA 3] Center 35 (5~66) winsize 62
5094 11:10:29.781193 [CA 4] Center 34 (4~65) winsize 62
5095 11:10:29.784623 [CA 5] Center 33 (3~64) winsize 62
5096 11:10:29.784704
5097 11:10:29.787931 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5098 11:10:29.788011
5099 11:10:29.791120 [CATrainingPosCal] consider 2 rank data
5100 11:10:29.794454 u2DelayCellTimex100 = 270/100 ps
5101 11:10:29.797651 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5102 11:10:29.801065 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5103 11:10:29.804300 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5104 11:10:29.811156 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5105 11:10:29.814281 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5106 11:10:29.817597 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5107 11:10:29.817677
5108 11:10:29.820900 CA PerBit enable=1, Macro0, CA PI delay=33
5109 11:10:29.820980
5110 11:10:29.824198 [CBTSetCACLKResult] CA Dly = 33
5111 11:10:29.824277 CS Dly: 7 (0~39)
5112 11:10:29.824340
5113 11:10:29.827486 ----->DramcWriteLeveling(PI) begin...
5114 11:10:29.827567 ==
5115 11:10:29.831057 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 11:10:29.837422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 11:10:29.837561 ==
5118 11:10:29.840957 Write leveling (Byte 0): 30 => 30
5119 11:10:29.844253 Write leveling (Byte 1): 28 => 28
5120 11:10:29.847532 DramcWriteLeveling(PI) end<-----
5121 11:10:29.847615
5122 11:10:29.847678 ==
5123 11:10:29.850705 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 11:10:29.854120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 11:10:29.854200 ==
5126 11:10:29.857299 [Gating] SW mode calibration
5127 11:10:29.863954 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5128 11:10:29.867200 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5129 11:10:29.873882 0 14 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5130 11:10:29.876919 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5131 11:10:29.883535 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 11:10:29.886882 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 11:10:29.890271 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 11:10:29.896766 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 11:10:29.900185 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 11:10:29.903427 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5137 11:10:29.910310 0 15 0 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
5138 11:10:29.913418 0 15 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5139 11:10:29.916521 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 11:10:29.923290 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 11:10:29.926473 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 11:10:29.929946 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 11:10:29.933240 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 11:10:29.939650 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5145 11:10:29.943063 1 0 0 | B1->B0 | 2626 3b3b | 1 1 | (0 0) (0 0)
5146 11:10:29.946202 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5147 11:10:29.952902 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 11:10:29.956231 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 11:10:29.959650 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 11:10:29.966107 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 11:10:29.969565 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 11:10:29.972720 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 11:10:29.979245 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5154 11:10:29.982379 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 11:10:29.989049 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 11:10:29.992411 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 11:10:29.995825 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 11:10:29.998914 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 11:10:30.005567 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 11:10:30.008683 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 11:10:30.015624 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 11:10:30.018777 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 11:10:30.022217 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 11:10:30.028578 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 11:10:30.032104 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 11:10:30.035401 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 11:10:30.038646 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 11:10:30.045323 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5169 11:10:30.048689 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5170 11:10:30.051805 Total UI for P1: 0, mck2ui 16
5171 11:10:30.055156 best dqsien dly found for B0: ( 1, 2, 28)
5172 11:10:30.058530 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5173 11:10:30.064925 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 11:10:30.068326 Total UI for P1: 0, mck2ui 16
5175 11:10:30.071681 best dqsien dly found for B1: ( 1, 3, 4)
5176 11:10:30.074717 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5177 11:10:30.078159 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5178 11:10:30.078240
5179 11:10:30.081426 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5180 11:10:30.084834 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5181 11:10:30.088273 [Gating] SW calibration Done
5182 11:10:30.088353 ==
5183 11:10:30.091592 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 11:10:30.094868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 11:10:30.094949 ==
5186 11:10:30.098099 RX Vref Scan: 0
5187 11:10:30.098178
5188 11:10:30.098241 RX Vref 0 -> 0, step: 1
5189 11:10:30.101303
5190 11:10:30.101382 RX Delay -80 -> 252, step: 8
5191 11:10:30.107983 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5192 11:10:30.111261 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5193 11:10:30.114494 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5194 11:10:30.117742 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5195 11:10:30.121170 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5196 11:10:30.124153 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5197 11:10:30.130893 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5198 11:10:30.134253 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5199 11:10:30.137419 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5200 11:10:30.140934 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5201 11:10:30.144228 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5202 11:10:30.150797 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5203 11:10:30.153958 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5204 11:10:30.157257 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5205 11:10:30.160829 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5206 11:10:30.167320 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5207 11:10:30.167405 ==
5208 11:10:30.170705 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 11:10:30.173661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 11:10:30.173742 ==
5211 11:10:30.173805 DQS Delay:
5212 11:10:30.177058 DQS0 = 0, DQS1 = 0
5213 11:10:30.177138 DQM Delay:
5214 11:10:30.180502 DQM0 = 95, DQM1 = 82
5215 11:10:30.180581 DQ Delay:
5216 11:10:30.183841 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5217 11:10:30.186969 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =111
5218 11:10:30.190390 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5219 11:10:30.193783 DQ12 =83, DQ13 =91, DQ14 =91, DQ15 =91
5220 11:10:30.193864
5221 11:10:30.193927
5222 11:10:30.193984 ==
5223 11:10:30.197074 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 11:10:30.200334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 11:10:30.200415 ==
5226 11:10:30.203723
5227 11:10:30.203804
5228 11:10:30.203867 TX Vref Scan disable
5229 11:10:30.206685 == TX Byte 0 ==
5230 11:10:30.210181 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5231 11:10:30.213458 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5232 11:10:30.216821 == TX Byte 1 ==
5233 11:10:30.220090 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5234 11:10:30.223407 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5235 11:10:30.226575 ==
5236 11:10:30.226654 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 11:10:30.233275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 11:10:30.233356 ==
5239 11:10:30.233419
5240 11:10:30.233485
5241 11:10:30.236628 TX Vref Scan disable
5242 11:10:30.236708 == TX Byte 0 ==
5243 11:10:30.243449 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5244 11:10:30.246458 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5245 11:10:30.246565 == TX Byte 1 ==
5246 11:10:30.253160 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5247 11:10:30.256496 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5248 11:10:30.256579
5249 11:10:30.256643 [DATLAT]
5250 11:10:30.259621 Freq=933, CH0 RK0
5251 11:10:30.259700
5252 11:10:30.259762 DATLAT Default: 0xd
5253 11:10:30.262901 0, 0xFFFF, sum = 0
5254 11:10:30.262982 1, 0xFFFF, sum = 0
5255 11:10:30.266307 2, 0xFFFF, sum = 0
5256 11:10:30.266389 3, 0xFFFF, sum = 0
5257 11:10:30.269728 4, 0xFFFF, sum = 0
5258 11:10:30.269809 5, 0xFFFF, sum = 0
5259 11:10:30.272853 6, 0xFFFF, sum = 0
5260 11:10:30.275922 7, 0xFFFF, sum = 0
5261 11:10:30.276003 8, 0xFFFF, sum = 0
5262 11:10:30.279259 9, 0xFFFF, sum = 0
5263 11:10:30.279367 10, 0x0, sum = 1
5264 11:10:30.282776 11, 0x0, sum = 2
5265 11:10:30.282856 12, 0x0, sum = 3
5266 11:10:30.282919 13, 0x0, sum = 4
5267 11:10:30.285899 best_step = 11
5268 11:10:30.285978
5269 11:10:30.286042 ==
5270 11:10:30.289144 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 11:10:30.292715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 11:10:30.292795 ==
5273 11:10:30.295884 RX Vref Scan: 1
5274 11:10:30.295963
5275 11:10:30.296026 RX Vref 0 -> 0, step: 1
5276 11:10:30.299134
5277 11:10:30.299212 RX Delay -77 -> 252, step: 4
5278 11:10:30.299276
5279 11:10:30.302528 Set Vref, RX VrefLevel [Byte0]: 61
5280 11:10:30.305468 [Byte1]: 48
5281 11:10:30.310335
5282 11:10:30.310414 Final RX Vref Byte 0 = 61 to rank0
5283 11:10:30.313648 Final RX Vref Byte 1 = 48 to rank0
5284 11:10:30.317240 Final RX Vref Byte 0 = 61 to rank1
5285 11:10:30.320307 Final RX Vref Byte 1 = 48 to rank1==
5286 11:10:30.323470 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 11:10:30.330096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 11:10:30.330176 ==
5289 11:10:30.330238 DQS Delay:
5290 11:10:30.333469 DQS0 = 0, DQS1 = 0
5291 11:10:30.333558 DQM Delay:
5292 11:10:30.333654 DQM0 = 95, DQM1 = 81
5293 11:10:30.336575 DQ Delay:
5294 11:10:30.340222 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5295 11:10:30.343454 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5296 11:10:30.346890 DQ8 =74, DQ9 =68, DQ10 =84, DQ11 =74
5297 11:10:30.350258 DQ12 =86, DQ13 =86, DQ14 =94, DQ15 =88
5298 11:10:30.350337
5299 11:10:30.350399
5300 11:10:30.356471 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 417 ps
5301 11:10:30.359866 CH0 RK0: MR19=505, MR18=F0F
5302 11:10:30.366572 CH0_RK0: MR19=0x505, MR18=0xF0F, DQSOSC=417, MR23=63, INC=62, DEC=41
5303 11:10:30.366652
5304 11:10:30.369959 ----->DramcWriteLeveling(PI) begin...
5305 11:10:30.370040 ==
5306 11:10:30.373114 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 11:10:30.376547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 11:10:30.376632 ==
5309 11:10:30.379923 Write leveling (Byte 0): 30 => 30
5310 11:10:30.383135 Write leveling (Byte 1): 28 => 28
5311 11:10:30.386436 DramcWriteLeveling(PI) end<-----
5312 11:10:30.386540
5313 11:10:30.386630 ==
5314 11:10:30.389831 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 11:10:30.393343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 11:10:30.393429 ==
5317 11:10:30.396410 [Gating] SW mode calibration
5318 11:10:30.403131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5319 11:10:30.409728 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5320 11:10:30.412932 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5321 11:10:30.419605 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 11:10:30.423115 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 11:10:30.426398 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 11:10:30.432807 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 11:10:30.436422 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 11:10:30.439785 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 11:10:30.443003 0 14 28 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
5328 11:10:30.449411 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
5329 11:10:30.453022 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 11:10:30.456158 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 11:10:30.462628 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 11:10:30.466161 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 11:10:30.469365 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 11:10:30.475824 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5335 11:10:30.479224 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5336 11:10:30.482583 1 0 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
5337 11:10:30.489170 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 11:10:30.492420 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 11:10:30.495876 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 11:10:30.502279 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 11:10:30.505885 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 11:10:30.508802 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 11:10:30.515584 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5344 11:10:30.518682 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5345 11:10:30.522168 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5346 11:10:30.528635 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 11:10:30.532099 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 11:10:30.535408 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 11:10:30.542158 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 11:10:30.545574 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 11:10:30.548430 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 11:10:30.555282 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 11:10:30.558684 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 11:10:30.561698 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 11:10:30.568357 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 11:10:30.571808 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 11:10:30.575064 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 11:10:30.581678 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5359 11:10:30.584980 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5360 11:10:30.588352 Total UI for P1: 0, mck2ui 16
5361 11:10:30.591647 best dqsien dly found for B0: ( 1, 2, 24)
5362 11:10:30.594979 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5363 11:10:30.601791 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 11:10:30.601872 Total UI for P1: 0, mck2ui 16
5365 11:10:30.607964 best dqsien dly found for B1: ( 1, 2, 30)
5366 11:10:30.611616 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5367 11:10:30.614837 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5368 11:10:30.614919
5369 11:10:30.618145 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5370 11:10:30.621456 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5371 11:10:30.624786 [Gating] SW calibration Done
5372 11:10:30.624866 ==
5373 11:10:30.628227 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 11:10:30.631272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 11:10:30.631353 ==
5376 11:10:30.634679 RX Vref Scan: 0
5377 11:10:30.634759
5378 11:10:30.634821 RX Vref 0 -> 0, step: 1
5379 11:10:30.634880
5380 11:10:30.638169 RX Delay -80 -> 252, step: 8
5381 11:10:30.641269 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5382 11:10:30.647901 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5383 11:10:30.651102 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5384 11:10:30.654751 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5385 11:10:30.658158 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5386 11:10:30.661190 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5387 11:10:30.667814 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5388 11:10:30.671302 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5389 11:10:30.674298 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5390 11:10:30.677756 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5391 11:10:30.680920 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5392 11:10:30.687644 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5393 11:10:30.691217 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5394 11:10:30.694277 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5395 11:10:30.697322 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5396 11:10:30.700710 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5397 11:10:30.700789 ==
5398 11:10:30.704325 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 11:10:30.710619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 11:10:30.710698 ==
5401 11:10:30.710761 DQS Delay:
5402 11:10:30.714026 DQS0 = 0, DQS1 = 0
5403 11:10:30.714104 DQM Delay:
5404 11:10:30.714167 DQM0 = 91, DQM1 = 82
5405 11:10:30.717297 DQ Delay:
5406 11:10:30.720602 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5407 11:10:30.724175 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5408 11:10:30.727408 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =71
5409 11:10:30.730722 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5410 11:10:30.730801
5411 11:10:30.730862
5412 11:10:30.730918 ==
5413 11:10:30.733977 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 11:10:30.737343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 11:10:30.737424 ==
5416 11:10:30.737512
5417 11:10:30.737604
5418 11:10:30.740560 TX Vref Scan disable
5419 11:10:30.743825 == TX Byte 0 ==
5420 11:10:30.747518 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5421 11:10:30.750613 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5422 11:10:30.753911 == TX Byte 1 ==
5423 11:10:30.757092 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5424 11:10:30.760448 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5425 11:10:30.760541 ==
5426 11:10:30.763698 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 11:10:30.767112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 11:10:30.770197 ==
5429 11:10:30.770276
5430 11:10:30.770338
5431 11:10:30.770396 TX Vref Scan disable
5432 11:10:30.773873 == TX Byte 0 ==
5433 11:10:30.777316 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5434 11:10:30.784015 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5435 11:10:30.784095 == TX Byte 1 ==
5436 11:10:30.787191 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5437 11:10:30.793916 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5438 11:10:30.793997
5439 11:10:30.794060 [DATLAT]
5440 11:10:30.794118 Freq=933, CH0 RK1
5441 11:10:30.794174
5442 11:10:30.797046 DATLAT Default: 0xb
5443 11:10:30.797125 0, 0xFFFF, sum = 0
5444 11:10:30.800204 1, 0xFFFF, sum = 0
5445 11:10:30.803599 2, 0xFFFF, sum = 0
5446 11:10:30.803680 3, 0xFFFF, sum = 0
5447 11:10:30.807025 4, 0xFFFF, sum = 0
5448 11:10:30.807105 5, 0xFFFF, sum = 0
5449 11:10:30.810349 6, 0xFFFF, sum = 0
5450 11:10:30.810430 7, 0xFFFF, sum = 0
5451 11:10:30.813649 8, 0xFFFF, sum = 0
5452 11:10:30.813730 9, 0xFFFF, sum = 0
5453 11:10:30.816878 10, 0x0, sum = 1
5454 11:10:30.816959 11, 0x0, sum = 2
5455 11:10:30.820302 12, 0x0, sum = 3
5456 11:10:30.820383 13, 0x0, sum = 4
5457 11:10:30.820446 best_step = 11
5458 11:10:30.823422
5459 11:10:30.823501 ==
5460 11:10:30.826824 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 11:10:30.830105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 11:10:30.830217 ==
5463 11:10:30.830283 RX Vref Scan: 0
5464 11:10:30.830342
5465 11:10:30.833403 RX Vref 0 -> 0, step: 1
5466 11:10:30.833491
5467 11:10:30.836553 RX Delay -69 -> 252, step: 4
5468 11:10:30.843473 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5469 11:10:30.846479 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5470 11:10:30.849881 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5471 11:10:30.853248 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5472 11:10:30.856596 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5473 11:10:30.859826 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5474 11:10:30.866447 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5475 11:10:30.869753 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5476 11:10:30.873067 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5477 11:10:30.876223 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5478 11:10:30.879720 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5479 11:10:30.886246 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5480 11:10:30.889472 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5481 11:10:30.893048 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5482 11:10:30.896241 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5483 11:10:30.899296 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5484 11:10:30.902505 ==
5485 11:10:30.905891 Dram Type= 6, Freq= 0, CH_0, rank 1
5486 11:10:30.909098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 11:10:30.909178 ==
5488 11:10:30.909241 DQS Delay:
5489 11:10:30.912617 DQS0 = 0, DQS1 = 0
5490 11:10:30.912696 DQM Delay:
5491 11:10:30.915795 DQM0 = 92, DQM1 = 83
5492 11:10:30.915900 DQ Delay:
5493 11:10:30.919204 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5494 11:10:30.922282 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5495 11:10:30.925800 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5496 11:10:30.929192 DQ12 =88, DQ13 =90, DQ14 =92, DQ15 =90
5497 11:10:30.929272
5498 11:10:30.929335
5499 11:10:30.935856 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5500 11:10:30.938982 CH0 RK1: MR19=505, MR18=2E10
5501 11:10:30.945797 CH0_RK1: MR19=0x505, MR18=0x2E10, DQSOSC=407, MR23=63, INC=65, DEC=43
5502 11:10:30.949198 [RxdqsGatingPostProcess] freq 933
5503 11:10:30.955800 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5504 11:10:30.959204 best DQS0 dly(2T, 0.5T) = (0, 10)
5505 11:10:30.959286 best DQS1 dly(2T, 0.5T) = (0, 11)
5506 11:10:30.962417 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5507 11:10:30.965764 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5508 11:10:30.968734 best DQS0 dly(2T, 0.5T) = (0, 10)
5509 11:10:30.972353 best DQS1 dly(2T, 0.5T) = (0, 10)
5510 11:10:30.975827 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5511 11:10:30.978757 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5512 11:10:30.982424 Pre-setting of DQS Precalculation
5513 11:10:30.988575 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5514 11:10:30.988714 ==
5515 11:10:30.992060 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 11:10:30.995470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 11:10:30.995578 ==
5518 11:10:31.001750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 11:10:31.005624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5520 11:10:31.009696 [CA 0] Center 37 (7~67) winsize 61
5521 11:10:31.013045 [CA 1] Center 37 (7~68) winsize 62
5522 11:10:31.016163 [CA 2] Center 34 (5~64) winsize 60
5523 11:10:31.019723 [CA 3] Center 34 (5~64) winsize 60
5524 11:10:31.022868 [CA 4] Center 34 (5~64) winsize 60
5525 11:10:31.026103 [CA 5] Center 33 (4~63) winsize 60
5526 11:10:31.026181
5527 11:10:31.029444 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5528 11:10:31.029605
5529 11:10:31.032748 [CATrainingPosCal] consider 1 rank data
5530 11:10:31.036216 u2DelayCellTimex100 = 270/100 ps
5531 11:10:31.039502 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5532 11:10:31.046100 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5533 11:10:31.049345 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5534 11:10:31.052578 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5535 11:10:31.056053 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5536 11:10:31.059268 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5537 11:10:31.059348
5538 11:10:31.062730 CA PerBit enable=1, Macro0, CA PI delay=33
5539 11:10:31.062809
5540 11:10:31.065875 [CBTSetCACLKResult] CA Dly = 33
5541 11:10:31.065955 CS Dly: 6 (0~37)
5542 11:10:31.069267 ==
5543 11:10:31.072347 Dram Type= 6, Freq= 0, CH_1, rank 1
5544 11:10:31.075799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 11:10:31.075881 ==
5546 11:10:31.079172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 11:10:31.085699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5548 11:10:31.089436 [CA 0] Center 38 (8~68) winsize 61
5549 11:10:31.092766 [CA 1] Center 37 (7~68) winsize 62
5550 11:10:31.096191 [CA 2] Center 35 (5~65) winsize 61
5551 11:10:31.099467 [CA 3] Center 34 (4~64) winsize 61
5552 11:10:31.102758 [CA 4] Center 35 (5~65) winsize 61
5553 11:10:31.106396 [CA 5] Center 34 (4~64) winsize 61
5554 11:10:31.106476
5555 11:10:31.109399 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5556 11:10:31.109543
5557 11:10:31.112799 [CATrainingPosCal] consider 2 rank data
5558 11:10:31.115766 u2DelayCellTimex100 = 270/100 ps
5559 11:10:31.119484 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5560 11:10:31.126047 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5561 11:10:31.129216 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5562 11:10:31.132723 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5563 11:10:31.135820 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5564 11:10:31.138880 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5565 11:10:31.138966
5566 11:10:31.142644 CA PerBit enable=1, Macro0, CA PI delay=33
5567 11:10:31.142729
5568 11:10:31.145756 [CBTSetCACLKResult] CA Dly = 33
5569 11:10:31.149033 CS Dly: 7 (0~39)
5570 11:10:31.149141
5571 11:10:31.152262 ----->DramcWriteLeveling(PI) begin...
5572 11:10:31.152343 ==
5573 11:10:31.155536 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 11:10:31.158825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 11:10:31.158906 ==
5576 11:10:31.162146 Write leveling (Byte 0): 27 => 27
5577 11:10:31.165575 Write leveling (Byte 1): 29 => 29
5578 11:10:31.168934 DramcWriteLeveling(PI) end<-----
5579 11:10:31.169015
5580 11:10:31.169078 ==
5581 11:10:31.172165 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 11:10:31.175312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 11:10:31.175397 ==
5584 11:10:31.178863 [Gating] SW mode calibration
5585 11:10:31.185207 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5586 11:10:31.192019 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5587 11:10:31.195444 0 14 0 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)
5588 11:10:31.198867 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 11:10:31.205328 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 11:10:31.208654 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 11:10:31.211972 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 11:10:31.218624 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 11:10:31.221864 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 11:10:31.225190 0 14 28 | B1->B0 | 3030 2f2f | 1 1 | (1 0) (1 0)
5595 11:10:31.231546 0 15 0 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
5596 11:10:31.235083 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 11:10:31.238220 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 11:10:31.244881 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 11:10:31.248089 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 11:10:31.251723 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 11:10:31.258396 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 11:10:31.261421 0 15 28 | B1->B0 | 2a2a 3333 | 1 1 | (0 0) (1 1)
5603 11:10:31.264831 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 11:10:31.271504 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 11:10:31.274771 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 11:10:31.278225 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 11:10:31.284782 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 11:10:31.288144 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 11:10:31.291218 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 11:10:31.297713 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5611 11:10:31.301193 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5612 11:10:31.304323 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 11:10:31.311166 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 11:10:31.314134 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 11:10:31.317570 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 11:10:31.324136 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 11:10:31.327306 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 11:10:31.330665 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 11:10:31.337291 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 11:10:31.340520 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 11:10:31.344097 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 11:10:31.350374 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 11:10:31.353793 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 11:10:31.357217 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 11:10:31.363655 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 11:10:31.367100 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5627 11:10:31.370197 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 11:10:31.373469 Total UI for P1: 0, mck2ui 16
5629 11:10:31.376704 best dqsien dly found for B0: ( 1, 2, 28)
5630 11:10:31.380221 Total UI for P1: 0, mck2ui 16
5631 11:10:31.383551 best dqsien dly found for B1: ( 1, 2, 28)
5632 11:10:31.386651 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5633 11:10:31.390085 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5634 11:10:31.390165
5635 11:10:31.396471 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5636 11:10:31.399930 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5637 11:10:31.400011 [Gating] SW calibration Done
5638 11:10:31.403195 ==
5639 11:10:31.406596 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 11:10:31.409617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 11:10:31.409697 ==
5642 11:10:31.409760 RX Vref Scan: 0
5643 11:10:31.409819
5644 11:10:31.413119 RX Vref 0 -> 0, step: 1
5645 11:10:31.413198
5646 11:10:31.416198 RX Delay -80 -> 252, step: 8
5647 11:10:31.419622 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5648 11:10:31.422768 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5649 11:10:31.429622 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5650 11:10:31.432621 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5651 11:10:31.436017 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5652 11:10:31.439391 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5653 11:10:31.442784 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5654 11:10:31.446015 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5655 11:10:31.452857 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5656 11:10:31.456126 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5657 11:10:31.459182 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5658 11:10:31.462509 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5659 11:10:31.465723 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5660 11:10:31.472374 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5661 11:10:31.475906 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5662 11:10:31.479320 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5663 11:10:31.479426 ==
5664 11:10:31.482211 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 11:10:31.485715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 11:10:31.485796 ==
5667 11:10:31.489048 DQS Delay:
5668 11:10:31.489127 DQS0 = 0, DQS1 = 0
5669 11:10:31.492224 DQM Delay:
5670 11:10:31.492303 DQM0 = 94, DQM1 = 87
5671 11:10:31.492366 DQ Delay:
5672 11:10:31.495536 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5673 11:10:31.498844 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5674 11:10:31.502108 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5675 11:10:31.505453 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5676 11:10:31.505586
5677 11:10:31.508712
5678 11:10:31.508810 ==
5679 11:10:31.512174 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 11:10:31.515222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 11:10:31.515306 ==
5682 11:10:31.515369
5683 11:10:31.515426
5684 11:10:31.518596 TX Vref Scan disable
5685 11:10:31.518675 == TX Byte 0 ==
5686 11:10:31.525176 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5687 11:10:31.528661 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5688 11:10:31.528741 == TX Byte 1 ==
5689 11:10:31.534896 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5690 11:10:31.538439 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5691 11:10:31.538518 ==
5692 11:10:31.541791 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 11:10:31.545139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 11:10:31.545220 ==
5695 11:10:31.545282
5696 11:10:31.545341
5697 11:10:31.548564 TX Vref Scan disable
5698 11:10:31.551756 == TX Byte 0 ==
5699 11:10:31.555189 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5700 11:10:31.558348 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5701 11:10:31.561394 == TX Byte 1 ==
5702 11:10:31.564846 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5703 11:10:31.568054 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5704 11:10:31.568135
5705 11:10:31.571442 [DATLAT]
5706 11:10:31.571523 Freq=933, CH1 RK0
5707 11:10:31.571586
5708 11:10:31.574650 DATLAT Default: 0xd
5709 11:10:31.574731 0, 0xFFFF, sum = 0
5710 11:10:31.578058 1, 0xFFFF, sum = 0
5711 11:10:31.578140 2, 0xFFFF, sum = 0
5712 11:10:31.581418 3, 0xFFFF, sum = 0
5713 11:10:31.581526 4, 0xFFFF, sum = 0
5714 11:10:31.584500 5, 0xFFFF, sum = 0
5715 11:10:31.584581 6, 0xFFFF, sum = 0
5716 11:10:31.588045 7, 0xFFFF, sum = 0
5717 11:10:31.588126 8, 0xFFFF, sum = 0
5718 11:10:31.591149 9, 0xFFFF, sum = 0
5719 11:10:31.591231 10, 0x0, sum = 1
5720 11:10:31.594503 11, 0x0, sum = 2
5721 11:10:31.594584 12, 0x0, sum = 3
5722 11:10:31.597950 13, 0x0, sum = 4
5723 11:10:31.598031 best_step = 11
5724 11:10:31.598093
5725 11:10:31.598152 ==
5726 11:10:31.601113 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 11:10:31.607741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 11:10:31.607831 ==
5729 11:10:31.607895 RX Vref Scan: 1
5730 11:10:31.607953
5731 11:10:31.611358 RX Vref 0 -> 0, step: 1
5732 11:10:31.611437
5733 11:10:31.614497 RX Delay -69 -> 252, step: 4
5734 11:10:31.614576
5735 11:10:31.617650 Set Vref, RX VrefLevel [Byte0]: 57
5736 11:10:31.621079 [Byte1]: 51
5737 11:10:31.621159
5738 11:10:31.624236 Final RX Vref Byte 0 = 57 to rank0
5739 11:10:31.627482 Final RX Vref Byte 1 = 51 to rank0
5740 11:10:31.630951 Final RX Vref Byte 0 = 57 to rank1
5741 11:10:31.634407 Final RX Vref Byte 1 = 51 to rank1==
5742 11:10:31.637630 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 11:10:31.640893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 11:10:31.640973 ==
5745 11:10:31.644399 DQS Delay:
5746 11:10:31.644479 DQS0 = 0, DQS1 = 0
5747 11:10:31.647359 DQM Delay:
5748 11:10:31.647438 DQM0 = 96, DQM1 = 88
5749 11:10:31.647502 DQ Delay:
5750 11:10:31.650817 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =92
5751 11:10:31.654241 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5752 11:10:31.657398 DQ8 =76, DQ9 =82, DQ10 =86, DQ11 =80
5753 11:10:31.660707 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5754 11:10:31.660790
5755 11:10:31.664146
5756 11:10:31.670627 [DQSOSCAuto] RK0, (LSB)MR18= 0xfd06, (MSB)MR19= 0x405, tDQSOscB0 = 420 ps tDQSOscB1 = 423 ps
5757 11:10:31.673872 CH1 RK0: MR19=405, MR18=FD06
5758 11:10:31.680579 CH1_RK0: MR19=0x405, MR18=0xFD06, DQSOSC=420, MR23=63, INC=61, DEC=40
5759 11:10:31.680660
5760 11:10:31.683929 ----->DramcWriteLeveling(PI) begin...
5761 11:10:31.684010 ==
5762 11:10:31.687282 Dram Type= 6, Freq= 0, CH_1, rank 1
5763 11:10:31.690625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 11:10:31.690705 ==
5765 11:10:31.693833 Write leveling (Byte 0): 25 => 25
5766 11:10:31.697328 Write leveling (Byte 1): 29 => 29
5767 11:10:31.700400 DramcWriteLeveling(PI) end<-----
5768 11:10:31.700480
5769 11:10:31.700544 ==
5770 11:10:31.703896 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 11:10:31.707076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 11:10:31.707156 ==
5773 11:10:31.710533 [Gating] SW mode calibration
5774 11:10:31.717007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5775 11:10:31.723800 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5776 11:10:31.726848 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5777 11:10:31.730388 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 11:10:31.736742 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 11:10:31.740153 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 11:10:31.743455 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 11:10:31.750115 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 11:10:31.753665 0 14 24 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 1)
5783 11:10:31.756713 0 14 28 | B1->B0 | 2828 2323 | 1 0 | (1 0) (1 0)
5784 11:10:31.763523 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5785 11:10:31.766598 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 11:10:31.769918 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 11:10:31.776989 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 11:10:31.780344 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 11:10:31.783615 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 11:10:31.789901 0 15 24 | B1->B0 | 2626 3232 | 1 0 | (0 0) (0 0)
5791 11:10:31.792949 0 15 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5792 11:10:31.796546 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5793 11:10:31.803249 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 11:10:31.806199 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 11:10:31.809718 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 11:10:31.816373 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 11:10:31.819639 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 11:10:31.823129 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5799 11:10:31.829889 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 11:10:31.833254 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 11:10:31.836372 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 11:10:31.842901 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 11:10:31.846119 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 11:10:31.849568 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 11:10:31.856211 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 11:10:31.859320 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 11:10:31.862706 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 11:10:31.869167 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 11:10:31.872357 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 11:10:31.875883 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 11:10:31.882708 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 11:10:31.885815 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 11:10:31.889183 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 11:10:31.895716 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5815 11:10:31.899215 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5816 11:10:31.902256 Total UI for P1: 0, mck2ui 16
5817 11:10:31.905673 best dqsien dly found for B0: ( 1, 2, 24)
5818 11:10:31.909066 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 11:10:31.912106 Total UI for P1: 0, mck2ui 16
5820 11:10:31.915524 best dqsien dly found for B1: ( 1, 2, 26)
5821 11:10:31.919103 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5822 11:10:31.922072 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5823 11:10:31.922152
5824 11:10:31.925446 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5825 11:10:31.932278 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5826 11:10:31.932358 [Gating] SW calibration Done
5827 11:10:31.932420 ==
5828 11:10:31.935501 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 11:10:31.942176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 11:10:31.942282 ==
5831 11:10:31.942347 RX Vref Scan: 0
5832 11:10:31.942406
5833 11:10:31.945650 RX Vref 0 -> 0, step: 1
5834 11:10:31.945729
5835 11:10:31.948767 RX Delay -80 -> 252, step: 8
5836 11:10:31.952196 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5837 11:10:31.955152 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5838 11:10:31.958525 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5839 11:10:31.965127 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5840 11:10:31.968554 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5841 11:10:31.971886 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5842 11:10:31.975324 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5843 11:10:31.978450 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5844 11:10:31.981655 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5845 11:10:31.988201 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5846 11:10:31.991501 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5847 11:10:31.994804 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5848 11:10:31.998167 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5849 11:10:32.001594 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5850 11:10:32.008154 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5851 11:10:32.011404 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5852 11:10:32.011483 ==
5853 11:10:32.014893 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 11:10:32.018313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 11:10:32.018393 ==
5856 11:10:32.021458 DQS Delay:
5857 11:10:32.021547 DQS0 = 0, DQS1 = 0
5858 11:10:32.021610 DQM Delay:
5859 11:10:32.024840 DQM0 = 93, DQM1 = 86
5860 11:10:32.024911 DQ Delay:
5861 11:10:32.027973 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5862 11:10:32.031418 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5863 11:10:32.034803 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5864 11:10:32.038276 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =91
5865 11:10:32.038355
5866 11:10:32.038417
5867 11:10:32.038475 ==
5868 11:10:32.041470 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 11:10:32.047973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 11:10:32.048053 ==
5871 11:10:32.048116
5872 11:10:32.048173
5873 11:10:32.048228 TX Vref Scan disable
5874 11:10:32.051607 == TX Byte 0 ==
5875 11:10:32.055238 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5876 11:10:32.061634 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5877 11:10:32.061737 == TX Byte 1 ==
5878 11:10:32.065099 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5879 11:10:32.071519 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5880 11:10:32.071599 ==
5881 11:10:32.075087 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 11:10:32.078123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 11:10:32.078207 ==
5884 11:10:32.078271
5885 11:10:32.078329
5886 11:10:32.081574 TX Vref Scan disable
5887 11:10:32.081653 == TX Byte 0 ==
5888 11:10:32.088106 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5889 11:10:32.091535 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5890 11:10:32.091614 == TX Byte 1 ==
5891 11:10:32.098230 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5892 11:10:32.101605 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5893 11:10:32.101685
5894 11:10:32.101747 [DATLAT]
5895 11:10:32.104829 Freq=933, CH1 RK1
5896 11:10:32.104909
5897 11:10:32.104971 DATLAT Default: 0xb
5898 11:10:32.107999 0, 0xFFFF, sum = 0
5899 11:10:32.108080 1, 0xFFFF, sum = 0
5900 11:10:32.111266 2, 0xFFFF, sum = 0
5901 11:10:32.114528 3, 0xFFFF, sum = 0
5902 11:10:32.114635 4, 0xFFFF, sum = 0
5903 11:10:32.118060 5, 0xFFFF, sum = 0
5904 11:10:32.118134 6, 0xFFFF, sum = 0
5905 11:10:32.121064 7, 0xFFFF, sum = 0
5906 11:10:32.121175 8, 0xFFFF, sum = 0
5907 11:10:32.124592 9, 0xFFFF, sum = 0
5908 11:10:32.124673 10, 0x0, sum = 1
5909 11:10:32.127951 11, 0x0, sum = 2
5910 11:10:32.128058 12, 0x0, sum = 3
5911 11:10:32.131202 13, 0x0, sum = 4
5912 11:10:32.131309 best_step = 11
5913 11:10:32.131399
5914 11:10:32.131485 ==
5915 11:10:32.134241 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 11:10:32.137433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 11:10:32.137548 ==
5918 11:10:32.140915 RX Vref Scan: 0
5919 11:10:32.140989
5920 11:10:32.144187 RX Vref 0 -> 0, step: 1
5921 11:10:32.144266
5922 11:10:32.144328 RX Delay -69 -> 252, step: 4
5923 11:10:32.152308 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5924 11:10:32.155489 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5925 11:10:32.158976 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5926 11:10:32.162066 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5927 11:10:32.165417 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5928 11:10:32.171830 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5929 11:10:32.175253 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5930 11:10:32.178514 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5931 11:10:32.182200 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5932 11:10:32.185330 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5933 11:10:32.188715 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5934 11:10:32.195493 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5935 11:10:32.198600 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5936 11:10:32.201855 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5937 11:10:32.205145 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5938 11:10:32.208453 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5939 11:10:32.208533 ==
5940 11:10:32.212007 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 11:10:32.218274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 11:10:32.218381 ==
5943 11:10:32.218472 DQS Delay:
5944 11:10:32.221866 DQS0 = 0, DQS1 = 0
5945 11:10:32.221946 DQM Delay:
5946 11:10:32.225148 DQM0 = 91, DQM1 = 90
5947 11:10:32.225228 DQ Delay:
5948 11:10:32.228392 DQ0 =96, DQ1 =86, DQ2 =80, DQ3 =88
5949 11:10:32.231768 DQ4 =90, DQ5 =100, DQ6 =106, DQ7 =88
5950 11:10:32.235274 DQ8 =76, DQ9 =82, DQ10 =94, DQ11 =86
5951 11:10:32.238547 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
5952 11:10:32.238626
5953 11:10:32.238689
5954 11:10:32.244859 [DQSOSCAuto] RK1, (LSB)MR18= 0xc20, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5955 11:10:32.248353 CH1 RK1: MR19=505, MR18=C20
5956 11:10:32.254894 CH1_RK1: MR19=0x505, MR18=0xC20, DQSOSC=411, MR23=63, INC=64, DEC=42
5957 11:10:32.257973 [RxdqsGatingPostProcess] freq 933
5958 11:10:32.261316 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5959 11:10:32.264979 best DQS0 dly(2T, 0.5T) = (0, 10)
5960 11:10:32.268098 best DQS1 dly(2T, 0.5T) = (0, 10)
5961 11:10:32.271557 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5962 11:10:32.274681 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5963 11:10:32.278146 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 11:10:32.281201 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 11:10:32.284427 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 11:10:32.287849 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 11:10:32.291526 Pre-setting of DQS Precalculation
5968 11:10:32.294535 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5969 11:10:32.304562 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5970 11:10:32.311167 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5971 11:10:32.311249
5972 11:10:32.311312
5973 11:10:32.314235 [Calibration Summary] 1866 Mbps
5974 11:10:32.314315 CH 0, Rank 0
5975 11:10:32.317640 SW Impedance : PASS
5976 11:10:32.317751 DUTY Scan : NO K
5977 11:10:32.321161 ZQ Calibration : PASS
5978 11:10:32.324178 Jitter Meter : NO K
5979 11:10:32.324286 CBT Training : PASS
5980 11:10:32.327844 Write leveling : PASS
5981 11:10:32.331268 RX DQS gating : PASS
5982 11:10:32.331367 RX DQ/DQS(RDDQC) : PASS
5983 11:10:32.334571 TX DQ/DQS : PASS
5984 11:10:32.337794 RX DATLAT : PASS
5985 11:10:32.338014 RX DQ/DQS(Engine): PASS
5986 11:10:32.340783 TX OE : NO K
5987 11:10:32.340890 All Pass.
5988 11:10:32.340982
5989 11:10:32.344233 CH 0, Rank 1
5990 11:10:32.344324 SW Impedance : PASS
5991 11:10:32.347402 DUTY Scan : NO K
5992 11:10:32.350960 ZQ Calibration : PASS
5993 11:10:32.351059 Jitter Meter : NO K
5994 11:10:32.354162 CBT Training : PASS
5995 11:10:32.357643 Write leveling : PASS
5996 11:10:32.357722 RX DQS gating : PASS
5997 11:10:32.361150 RX DQ/DQS(RDDQC) : PASS
5998 11:10:32.364739 TX DQ/DQS : PASS
5999 11:10:32.364819 RX DATLAT : PASS
6000 11:10:32.367712 RX DQ/DQS(Engine): PASS
6001 11:10:32.370773 TX OE : NO K
6002 11:10:32.370868 All Pass.
6003 11:10:32.370932
6004 11:10:32.371007 CH 1, Rank 0
6005 11:10:32.374064 SW Impedance : PASS
6006 11:10:32.377628 DUTY Scan : NO K
6007 11:10:32.377708 ZQ Calibration : PASS
6008 11:10:32.380695 Jitter Meter : NO K
6009 11:10:32.380776 CBT Training : PASS
6010 11:10:32.384163 Write leveling : PASS
6011 11:10:32.387210 RX DQS gating : PASS
6012 11:10:32.387292 RX DQ/DQS(RDDQC) : PASS
6013 11:10:32.390669 TX DQ/DQS : PASS
6014 11:10:32.393824 RX DATLAT : PASS
6015 11:10:32.393920 RX DQ/DQS(Engine): PASS
6016 11:10:32.397247 TX OE : NO K
6017 11:10:32.397327 All Pass.
6018 11:10:32.397391
6019 11:10:32.400569 CH 1, Rank 1
6020 11:10:32.400650 SW Impedance : PASS
6021 11:10:32.403716 DUTY Scan : NO K
6022 11:10:32.407344 ZQ Calibration : PASS
6023 11:10:32.407445 Jitter Meter : NO K
6024 11:10:32.410453 CBT Training : PASS
6025 11:10:32.413626 Write leveling : PASS
6026 11:10:32.413707 RX DQS gating : PASS
6027 11:10:32.417087 RX DQ/DQS(RDDQC) : PASS
6028 11:10:32.420073 TX DQ/DQS : PASS
6029 11:10:32.420155 RX DATLAT : PASS
6030 11:10:32.423538 RX DQ/DQS(Engine): PASS
6031 11:10:32.427036 TX OE : NO K
6032 11:10:32.427117 All Pass.
6033 11:10:32.427181
6034 11:10:32.427239 DramC Write-DBI off
6035 11:10:32.430214 PER_BANK_REFRESH: Hybrid Mode
6036 11:10:32.433699 TX_TRACKING: ON
6037 11:10:32.440277 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6038 11:10:32.443439 [FAST_K] Save calibration result to emmc
6039 11:10:32.450193 dramc_set_vcore_voltage set vcore to 650000
6040 11:10:32.450274 Read voltage for 400, 6
6041 11:10:32.453623 Vio18 = 0
6042 11:10:32.453704 Vcore = 650000
6043 11:10:32.453783 Vdram = 0
6044 11:10:32.453872 Vddq = 0
6045 11:10:32.456846 Vmddr = 0
6046 11:10:32.459973 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6047 11:10:32.466811 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6048 11:10:32.469892 MEM_TYPE=3, freq_sel=20
6049 11:10:32.469973 sv_algorithm_assistance_LP4_800
6050 11:10:32.476453 ============ PULL DRAM RESETB DOWN ============
6051 11:10:32.479970 ========== PULL DRAM RESETB DOWN end =========
6052 11:10:32.483169 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6053 11:10:32.486510 ===================================
6054 11:10:32.489919 LPDDR4 DRAM CONFIGURATION
6055 11:10:32.493202 ===================================
6056 11:10:32.496698 EX_ROW_EN[0] = 0x0
6057 11:10:32.496778 EX_ROW_EN[1] = 0x0
6058 11:10:32.499888 LP4Y_EN = 0x0
6059 11:10:32.499969 WORK_FSP = 0x0
6060 11:10:32.503026 WL = 0x2
6061 11:10:32.503106 RL = 0x2
6062 11:10:32.506264 BL = 0x2
6063 11:10:32.506345 RPST = 0x0
6064 11:10:32.509713 RD_PRE = 0x0
6065 11:10:32.509794 WR_PRE = 0x1
6066 11:10:32.513101 WR_PST = 0x0
6067 11:10:32.516327 DBI_WR = 0x0
6068 11:10:32.516439 DBI_RD = 0x0
6069 11:10:32.519507 OTF = 0x1
6070 11:10:32.523121 ===================================
6071 11:10:32.526073 ===================================
6072 11:10:32.526148 ANA top config
6073 11:10:32.529420 ===================================
6074 11:10:32.532916 DLL_ASYNC_EN = 0
6075 11:10:32.536015 ALL_SLAVE_EN = 1
6076 11:10:32.536115 NEW_RANK_MODE = 1
6077 11:10:32.539618 DLL_IDLE_MODE = 1
6078 11:10:32.542720 LP45_APHY_COMB_EN = 1
6079 11:10:32.545917 TX_ODT_DIS = 1
6080 11:10:32.546014 NEW_8X_MODE = 1
6081 11:10:32.549105 ===================================
6082 11:10:32.552762 ===================================
6083 11:10:32.556054 data_rate = 800
6084 11:10:32.559616 CKR = 1
6085 11:10:32.562787 DQ_P2S_RATIO = 4
6086 11:10:32.565813 ===================================
6087 11:10:32.569244 CA_P2S_RATIO = 4
6088 11:10:32.572552 DQ_CA_OPEN = 0
6089 11:10:32.575649 DQ_SEMI_OPEN = 1
6090 11:10:32.575730 CA_SEMI_OPEN = 1
6091 11:10:32.579086 CA_FULL_RATE = 0
6092 11:10:32.582448 DQ_CKDIV4_EN = 0
6093 11:10:32.585646 CA_CKDIV4_EN = 1
6094 11:10:32.589074 CA_PREDIV_EN = 0
6095 11:10:32.592077 PH8_DLY = 0
6096 11:10:32.592158 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6097 11:10:32.595512 DQ_AAMCK_DIV = 0
6098 11:10:32.598950 CA_AAMCK_DIV = 0
6099 11:10:32.601903 CA_ADMCK_DIV = 4
6100 11:10:32.605363 DQ_TRACK_CA_EN = 0
6101 11:10:32.608602 CA_PICK = 800
6102 11:10:32.608676 CA_MCKIO = 400
6103 11:10:32.611766 MCKIO_SEMI = 400
6104 11:10:32.615022 PLL_FREQ = 3016
6105 11:10:32.618361 DQ_UI_PI_RATIO = 32
6106 11:10:32.621980 CA_UI_PI_RATIO = 32
6107 11:10:32.625109 ===================================
6108 11:10:32.628540 ===================================
6109 11:10:32.631707 memory_type:LPDDR4
6110 11:10:32.631800 GP_NUM : 10
6111 11:10:32.635083 SRAM_EN : 1
6112 11:10:32.638505 MD32_EN : 0
6113 11:10:32.641632 ===================================
6114 11:10:32.641714 [ANA_INIT] >>>>>>>>>>>>>>
6115 11:10:32.645072 <<<<<< [CONFIGURE PHASE]: ANA_TX
6116 11:10:32.648182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6117 11:10:32.651558 ===================================
6118 11:10:32.655210 data_rate = 800,PCW = 0X7400
6119 11:10:32.658158 ===================================
6120 11:10:32.661772 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6121 11:10:32.667989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6122 11:10:32.678298 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6123 11:10:32.684741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6124 11:10:32.688229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6125 11:10:32.691762 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6126 11:10:32.691842 [ANA_INIT] flow start
6127 11:10:32.694647 [ANA_INIT] PLL >>>>>>>>
6128 11:10:32.698199 [ANA_INIT] PLL <<<<<<<<
6129 11:10:32.698279 [ANA_INIT] MIDPI >>>>>>>>
6130 11:10:32.701268 [ANA_INIT] MIDPI <<<<<<<<
6131 11:10:32.704706 [ANA_INIT] DLL >>>>>>>>
6132 11:10:32.704785 [ANA_INIT] flow end
6133 11:10:32.711429 ============ LP4 DIFF to SE enter ============
6134 11:10:32.714599 ============ LP4 DIFF to SE exit ============
6135 11:10:32.714680 [ANA_INIT] <<<<<<<<<<<<<
6136 11:10:32.718101 [Flow] Enable top DCM control >>>>>
6137 11:10:32.721212 [Flow] Enable top DCM control <<<<<
6138 11:10:32.724499 Enable DLL master slave shuffle
6139 11:10:32.731021 ==============================================================
6140 11:10:32.734391 Gating Mode config
6141 11:10:32.737652 ==============================================================
6142 11:10:32.741114 Config description:
6143 11:10:32.750768 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6144 11:10:32.757631 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6145 11:10:32.760972 SELPH_MODE 0: By rank 1: By Phase
6146 11:10:32.767446 ==============================================================
6147 11:10:32.770880 GAT_TRACK_EN = 0
6148 11:10:32.774244 RX_GATING_MODE = 2
6149 11:10:32.777442 RX_GATING_TRACK_MODE = 2
6150 11:10:32.780724 SELPH_MODE = 1
6151 11:10:32.780808 PICG_EARLY_EN = 1
6152 11:10:32.784192 VALID_LAT_VALUE = 1
6153 11:10:32.790808 ==============================================================
6154 11:10:32.794365 Enter into Gating configuration >>>>
6155 11:10:32.797285 Exit from Gating configuration <<<<
6156 11:10:32.800640 Enter into DVFS_PRE_config >>>>>
6157 11:10:32.810704 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6158 11:10:32.813729 Exit from DVFS_PRE_config <<<<<
6159 11:10:32.817032 Enter into PICG configuration >>>>
6160 11:10:32.820299 Exit from PICG configuration <<<<
6161 11:10:32.823911 [RX_INPUT] configuration >>>>>
6162 11:10:32.827026 [RX_INPUT] configuration <<<<<
6163 11:10:32.830341 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6164 11:10:32.836994 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6165 11:10:32.843555 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6166 11:10:32.850220 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6167 11:10:32.856897 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6168 11:10:32.860127 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6169 11:10:32.866636 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6170 11:10:32.869975 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6171 11:10:32.873297 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6172 11:10:32.876618 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6173 11:10:32.883421 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6174 11:10:32.886636 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6175 11:10:32.890017 ===================================
6176 11:10:32.893141 LPDDR4 DRAM CONFIGURATION
6177 11:10:32.896515 ===================================
6178 11:10:32.896597 EX_ROW_EN[0] = 0x0
6179 11:10:32.899689 EX_ROW_EN[1] = 0x0
6180 11:10:32.899772 LP4Y_EN = 0x0
6181 11:10:32.902960 WORK_FSP = 0x0
6182 11:10:32.903045 WL = 0x2
6183 11:10:32.906293 RL = 0x2
6184 11:10:32.909623 BL = 0x2
6185 11:10:32.909704 RPST = 0x0
6186 11:10:32.913090 RD_PRE = 0x0
6187 11:10:32.913171 WR_PRE = 0x1
6188 11:10:32.916438 WR_PST = 0x0
6189 11:10:32.916518 DBI_WR = 0x0
6190 11:10:32.919364 DBI_RD = 0x0
6191 11:10:32.919445 OTF = 0x1
6192 11:10:32.922752 ===================================
6193 11:10:32.926075 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6194 11:10:32.932749 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6195 11:10:32.936247 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6196 11:10:32.939259 ===================================
6197 11:10:32.942710 LPDDR4 DRAM CONFIGURATION
6198 11:10:32.945759 ===================================
6199 11:10:32.945840 EX_ROW_EN[0] = 0x10
6200 11:10:32.949124 EX_ROW_EN[1] = 0x0
6201 11:10:32.949205 LP4Y_EN = 0x0
6202 11:10:32.952347 WORK_FSP = 0x0
6203 11:10:32.955616 WL = 0x2
6204 11:10:32.955696 RL = 0x2
6205 11:10:32.959077 BL = 0x2
6206 11:10:32.959156 RPST = 0x0
6207 11:10:32.962694 RD_PRE = 0x0
6208 11:10:32.962773 WR_PRE = 0x1
6209 11:10:32.965717 WR_PST = 0x0
6210 11:10:32.965796 DBI_WR = 0x0
6211 11:10:32.969042 DBI_RD = 0x0
6212 11:10:32.969121 OTF = 0x1
6213 11:10:32.972384 ===================================
6214 11:10:32.978647 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6215 11:10:32.982843 nWR fixed to 30
6216 11:10:32.986213 [ModeRegInit_LP4] CH0 RK0
6217 11:10:32.986292 [ModeRegInit_LP4] CH0 RK1
6218 11:10:32.989790 [ModeRegInit_LP4] CH1 RK0
6219 11:10:32.993058 [ModeRegInit_LP4] CH1 RK1
6220 11:10:32.993163 match AC timing 19
6221 11:10:32.999673 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6222 11:10:33.002818 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6223 11:10:33.006311 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6224 11:10:33.012804 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6225 11:10:33.016069 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6226 11:10:33.016149 ==
6227 11:10:33.019566 Dram Type= 6, Freq= 0, CH_0, rank 0
6228 11:10:33.022739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6229 11:10:33.022820 ==
6230 11:10:33.029250 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6231 11:10:33.036146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6232 11:10:33.039386 [CA 0] Center 36 (8~64) winsize 57
6233 11:10:33.042410 [CA 1] Center 36 (8~64) winsize 57
6234 11:10:33.046077 [CA 2] Center 36 (8~64) winsize 57
6235 11:10:33.049115 [CA 3] Center 36 (8~64) winsize 57
6236 11:10:33.049188 [CA 4] Center 36 (8~64) winsize 57
6237 11:10:33.052366 [CA 5] Center 36 (8~64) winsize 57
6238 11:10:33.052481
6239 11:10:33.059219 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6240 11:10:33.059299
6241 11:10:33.062599 [CATrainingPosCal] consider 1 rank data
6242 11:10:33.065739 u2DelayCellTimex100 = 270/100 ps
6243 11:10:33.069049 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 11:10:33.072119 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 11:10:33.075551 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 11:10:33.078858 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 11:10:33.082243 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 11:10:33.085613 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 11:10:33.085692
6250 11:10:33.088711 CA PerBit enable=1, Macro0, CA PI delay=36
6251 11:10:33.088790
6252 11:10:33.092150 [CBTSetCACLKResult] CA Dly = 36
6253 11:10:33.095589 CS Dly: 1 (0~32)
6254 11:10:33.095668 ==
6255 11:10:33.099149 Dram Type= 6, Freq= 0, CH_0, rank 1
6256 11:10:33.102324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 11:10:33.102404 ==
6258 11:10:33.108881 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 11:10:33.115234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6260 11:10:33.118547 [CA 0] Center 36 (8~64) winsize 57
6261 11:10:33.118630 [CA 1] Center 36 (8~64) winsize 57
6262 11:10:33.122116 [CA 2] Center 36 (8~64) winsize 57
6263 11:10:33.125408 [CA 3] Center 36 (8~64) winsize 57
6264 11:10:33.128548 [CA 4] Center 36 (8~64) winsize 57
6265 11:10:33.131726 [CA 5] Center 36 (8~64) winsize 57
6266 11:10:33.131807
6267 11:10:33.135296 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6268 11:10:33.135376
6269 11:10:33.141880 [CATrainingPosCal] consider 2 rank data
6270 11:10:33.141961 u2DelayCellTimex100 = 270/100 ps
6271 11:10:33.148306 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 11:10:33.151737 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 11:10:33.155102 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 11:10:33.158489 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 11:10:33.161618 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 11:10:33.164865 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 11:10:33.164946
6278 11:10:33.168445 CA PerBit enable=1, Macro0, CA PI delay=36
6279 11:10:33.168526
6280 11:10:33.171420 [CBTSetCACLKResult] CA Dly = 36
6281 11:10:33.174796 CS Dly: 1 (0~32)
6282 11:10:33.174876
6283 11:10:33.178480 ----->DramcWriteLeveling(PI) begin...
6284 11:10:33.178562 ==
6285 11:10:33.181400 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 11:10:33.184746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 11:10:33.184827 ==
6288 11:10:33.188069 Write leveling (Byte 0): 40 => 8
6289 11:10:33.191201 Write leveling (Byte 1): 40 => 8
6290 11:10:33.194670 DramcWriteLeveling(PI) end<-----
6291 11:10:33.194752
6292 11:10:33.194815 ==
6293 11:10:33.198042 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 11:10:33.201433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 11:10:33.201521 ==
6296 11:10:33.204527 [Gating] SW mode calibration
6297 11:10:33.211251 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6298 11:10:33.217741 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6299 11:10:33.221027 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6300 11:10:33.224247 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6301 11:10:33.231040 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 11:10:33.234277 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 11:10:33.237591 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 11:10:33.244509 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 11:10:33.247498 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 11:10:33.250866 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 11:10:33.257654 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 11:10:33.257735 Total UI for P1: 0, mck2ui 16
6309 11:10:33.264218 best dqsien dly found for B0: ( 0, 14, 24)
6310 11:10:33.264297 Total UI for P1: 0, mck2ui 16
6311 11:10:33.270810 best dqsien dly found for B1: ( 0, 14, 24)
6312 11:10:33.273857 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6313 11:10:33.277532 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6314 11:10:33.277612
6315 11:10:33.280520 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6316 11:10:33.283899 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6317 11:10:33.287382 [Gating] SW calibration Done
6318 11:10:33.287461 ==
6319 11:10:33.290610 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 11:10:33.294206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 11:10:33.294285 ==
6322 11:10:33.297176 RX Vref Scan: 0
6323 11:10:33.297253
6324 11:10:33.297315 RX Vref 0 -> 0, step: 1
6325 11:10:33.297373
6326 11:10:33.300575 RX Delay -410 -> 252, step: 16
6327 11:10:33.307067 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6328 11:10:33.310499 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6329 11:10:33.313860 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6330 11:10:33.317068 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6331 11:10:33.323543 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6332 11:10:33.326887 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6333 11:10:33.330269 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6334 11:10:33.333648 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6335 11:10:33.340250 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6336 11:10:33.343399 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6337 11:10:33.346717 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6338 11:10:33.350180 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6339 11:10:33.356585 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6340 11:10:33.360069 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6341 11:10:33.363575 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6342 11:10:33.370139 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6343 11:10:33.370246 ==
6344 11:10:33.373149 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 11:10:33.376512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 11:10:33.376600 ==
6347 11:10:33.376665 DQS Delay:
6348 11:10:33.380026 DQS0 = 59, DQS1 = 59
6349 11:10:33.380108 DQM Delay:
6350 11:10:33.383446 DQM0 = 18, DQM1 = 10
6351 11:10:33.383527 DQ Delay:
6352 11:10:33.386524 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6353 11:10:33.389915 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6354 11:10:33.393219 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6355 11:10:33.396525 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6356 11:10:33.396606
6357 11:10:33.396670
6358 11:10:33.396728 ==
6359 11:10:33.400040 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 11:10:33.403054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 11:10:33.403135 ==
6362 11:10:33.403199
6363 11:10:33.403258
6364 11:10:33.406554 TX Vref Scan disable
6365 11:10:33.409884 == TX Byte 0 ==
6366 11:10:33.413269 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 11:10:33.416434 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 11:10:33.416515 == TX Byte 1 ==
6369 11:10:33.423217 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 11:10:33.426265 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 11:10:33.426346 ==
6372 11:10:33.429679 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 11:10:33.432927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 11:10:33.433011 ==
6375 11:10:33.433074
6376 11:10:33.436412
6377 11:10:33.436492 TX Vref Scan disable
6378 11:10:33.439499 == TX Byte 0 ==
6379 11:10:33.442894 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6380 11:10:33.446091 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6381 11:10:33.449601 == TX Byte 1 ==
6382 11:10:33.452945 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6383 11:10:33.456279 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6384 11:10:33.456359
6385 11:10:33.456422 [DATLAT]
6386 11:10:33.459425 Freq=400, CH0 RK0
6387 11:10:33.459504
6388 11:10:33.459566 DATLAT Default: 0xf
6389 11:10:33.462850 0, 0xFFFF, sum = 0
6390 11:10:33.466199 1, 0xFFFF, sum = 0
6391 11:10:33.466279 2, 0xFFFF, sum = 0
6392 11:10:33.469261 3, 0xFFFF, sum = 0
6393 11:10:33.469369 4, 0xFFFF, sum = 0
6394 11:10:33.472574 5, 0xFFFF, sum = 0
6395 11:10:33.472655 6, 0xFFFF, sum = 0
6396 11:10:33.475940 7, 0xFFFF, sum = 0
6397 11:10:33.476020 8, 0xFFFF, sum = 0
6398 11:10:33.479322 9, 0xFFFF, sum = 0
6399 11:10:33.479403 10, 0xFFFF, sum = 0
6400 11:10:33.482594 11, 0xFFFF, sum = 0
6401 11:10:33.482675 12, 0xFFFF, sum = 0
6402 11:10:33.486082 13, 0x0, sum = 1
6403 11:10:33.486163 14, 0x0, sum = 2
6404 11:10:33.489225 15, 0x0, sum = 3
6405 11:10:33.489306 16, 0x0, sum = 4
6406 11:10:33.492649 best_step = 14
6407 11:10:33.492728
6408 11:10:33.492791 ==
6409 11:10:33.495867 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 11:10:33.499309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 11:10:33.499389 ==
6412 11:10:33.502695 RX Vref Scan: 1
6413 11:10:33.502775
6414 11:10:33.502838 RX Vref 0 -> 0, step: 1
6415 11:10:33.502896
6416 11:10:33.505694 RX Delay -359 -> 252, step: 8
6417 11:10:33.505773
6418 11:10:33.509167 Set Vref, RX VrefLevel [Byte0]: 61
6419 11:10:33.512250 [Byte1]: 48
6420 11:10:33.516791
6421 11:10:33.516870 Final RX Vref Byte 0 = 61 to rank0
6422 11:10:33.520172 Final RX Vref Byte 1 = 48 to rank0
6423 11:10:33.523279 Final RX Vref Byte 0 = 61 to rank1
6424 11:10:33.526756 Final RX Vref Byte 1 = 48 to rank1==
6425 11:10:33.529820 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 11:10:33.536658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 11:10:33.536738 ==
6428 11:10:33.536801 DQS Delay:
6429 11:10:33.539797 DQS0 = 60, DQS1 = 68
6430 11:10:33.539877 DQM Delay:
6431 11:10:33.539939 DQM0 = 14, DQM1 = 14
6432 11:10:33.543102 DQ Delay:
6433 11:10:33.546614 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6434 11:10:33.549712 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6435 11:10:33.549791 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6436 11:10:33.556647 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6437 11:10:33.556727
6438 11:10:33.556789
6439 11:10:33.563274 [DQSOSCAuto] RK0, (LSB)MR18= 0x8684, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6440 11:10:33.566587 CH0 RK0: MR19=C0C, MR18=8684
6441 11:10:33.573112 CH0_RK0: MR19=0xC0C, MR18=0x8684, DQSOSC=393, MR23=63, INC=382, DEC=254
6442 11:10:33.573192 ==
6443 11:10:33.576203 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 11:10:33.579784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 11:10:33.579869 ==
6446 11:10:33.583011 [Gating] SW mode calibration
6447 11:10:33.589440 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6448 11:10:33.596124 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6449 11:10:33.599624 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6450 11:10:33.602962 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6451 11:10:33.609436 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 11:10:33.612701 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 11:10:33.616192 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 11:10:33.622621 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 11:10:33.626143 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 11:10:33.629244 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 11:10:33.635818 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 11:10:33.635901 Total UI for P1: 0, mck2ui 16
6459 11:10:33.642325 best dqsien dly found for B0: ( 0, 14, 24)
6460 11:10:33.642407 Total UI for P1: 0, mck2ui 16
6461 11:10:33.649183 best dqsien dly found for B1: ( 0, 14, 24)
6462 11:10:33.652558 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6463 11:10:33.655549 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6464 11:10:33.655630
6465 11:10:33.659365 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6466 11:10:33.662373 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6467 11:10:33.665499 [Gating] SW calibration Done
6468 11:10:33.665596 ==
6469 11:10:33.668831 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 11:10:33.672272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 11:10:33.672352 ==
6472 11:10:33.675529 RX Vref Scan: 0
6473 11:10:33.675609
6474 11:10:33.675672 RX Vref 0 -> 0, step: 1
6475 11:10:33.675731
6476 11:10:33.678820 RX Delay -410 -> 252, step: 16
6477 11:10:33.685558 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6478 11:10:33.688862 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6479 11:10:33.691941 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6480 11:10:33.695267 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6481 11:10:33.701882 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6482 11:10:33.705332 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6483 11:10:33.708761 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6484 11:10:33.711862 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6485 11:10:33.718565 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6486 11:10:33.721788 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6487 11:10:33.725151 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6488 11:10:33.728494 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6489 11:10:33.735073 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6490 11:10:33.738500 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6491 11:10:33.741585 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6492 11:10:33.748450 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6493 11:10:33.748530 ==
6494 11:10:33.751713 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 11:10:33.754819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 11:10:33.754900 ==
6497 11:10:33.754963 DQS Delay:
6498 11:10:33.758250 DQS0 = 59, DQS1 = 59
6499 11:10:33.758330 DQM Delay:
6500 11:10:33.761711 DQM0 = 16, DQM1 = 10
6501 11:10:33.761790 DQ Delay:
6502 11:10:33.764609 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6503 11:10:33.768413 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6504 11:10:33.771308 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6505 11:10:33.774537 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6506 11:10:33.774617
6507 11:10:33.774679
6508 11:10:33.774737 ==
6509 11:10:33.778072 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 11:10:33.781450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 11:10:33.781586 ==
6512 11:10:33.781649
6513 11:10:33.781707
6514 11:10:33.784645 TX Vref Scan disable
6515 11:10:33.788025 == TX Byte 0 ==
6516 11:10:33.791362 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6517 11:10:33.794531 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6518 11:10:33.797826 == TX Byte 1 ==
6519 11:10:33.801275 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6520 11:10:33.804471 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6521 11:10:33.804551 ==
6522 11:10:33.807815 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 11:10:33.811157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 11:10:33.811237 ==
6525 11:10:33.811300
6526 11:10:33.814549
6527 11:10:33.814628 TX Vref Scan disable
6528 11:10:33.817650 == TX Byte 0 ==
6529 11:10:33.821054 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6530 11:10:33.824291 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6531 11:10:33.827887 == TX Byte 1 ==
6532 11:10:33.831213 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6533 11:10:33.834343 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6534 11:10:33.834423
6535 11:10:33.834485 [DATLAT]
6536 11:10:33.837740 Freq=400, CH0 RK1
6537 11:10:33.837819
6538 11:10:33.837882 DATLAT Default: 0xe
6539 11:10:33.840943 0, 0xFFFF, sum = 0
6540 11:10:33.844321 1, 0xFFFF, sum = 0
6541 11:10:33.844428 2, 0xFFFF, sum = 0
6542 11:10:33.847708 3, 0xFFFF, sum = 0
6543 11:10:33.847788 4, 0xFFFF, sum = 0
6544 11:10:33.850755 5, 0xFFFF, sum = 0
6545 11:10:33.850836 6, 0xFFFF, sum = 0
6546 11:10:33.854167 7, 0xFFFF, sum = 0
6547 11:10:33.854247 8, 0xFFFF, sum = 0
6548 11:10:33.857745 9, 0xFFFF, sum = 0
6549 11:10:33.857827 10, 0xFFFF, sum = 0
6550 11:10:33.860688 11, 0xFFFF, sum = 0
6551 11:10:33.860769 12, 0xFFFF, sum = 0
6552 11:10:33.864268 13, 0x0, sum = 1
6553 11:10:33.864375 14, 0x0, sum = 2
6554 11:10:33.867628 15, 0x0, sum = 3
6555 11:10:33.867709 16, 0x0, sum = 4
6556 11:10:33.871057 best_step = 14
6557 11:10:33.871137
6558 11:10:33.871200 ==
6559 11:10:33.874198 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 11:10:33.877579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 11:10:33.877660 ==
6562 11:10:33.877724 RX Vref Scan: 0
6563 11:10:33.880638
6564 11:10:33.880718 RX Vref 0 -> 0, step: 1
6565 11:10:33.880781
6566 11:10:33.884164 RX Delay -359 -> 252, step: 8
6567 11:10:33.891575 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6568 11:10:33.894962 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6569 11:10:33.898412 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6570 11:10:33.901734 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6571 11:10:33.908296 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6572 11:10:33.911366 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6573 11:10:33.914848 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6574 11:10:33.921445 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6575 11:10:33.924847 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6576 11:10:33.927894 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6577 11:10:33.931216 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6578 11:10:33.937793 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6579 11:10:33.941188 iDelay=217, Bit 12, Center -52 (-303 ~ 200) 504
6580 11:10:33.944617 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6581 11:10:33.947668 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6582 11:10:33.954721 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6583 11:10:33.954802 ==
6584 11:10:33.957785 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 11:10:33.961294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 11:10:33.961402 ==
6587 11:10:33.961531 DQS Delay:
6588 11:10:33.964270 DQS0 = 60, DQS1 = 72
6589 11:10:33.964351 DQM Delay:
6590 11:10:33.967655 DQM0 = 11, DQM1 = 17
6591 11:10:33.967736 DQ Delay:
6592 11:10:33.971155 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6593 11:10:33.974156 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6594 11:10:33.977471 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6595 11:10:33.980896 DQ12 =20, DQ13 =28, DQ14 =28, DQ15 =24
6596 11:10:33.980977
6597 11:10:33.981040
6598 11:10:33.987314 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6599 11:10:33.990872 CH0 RK1: MR19=C0C, MR18=BD73
6600 11:10:33.997146 CH0_RK1: MR19=0xC0C, MR18=0xBD73, DQSOSC=386, MR23=63, INC=396, DEC=264
6601 11:10:34.000557 [RxdqsGatingPostProcess] freq 400
6602 11:10:34.007305 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6603 11:10:34.010572 best DQS0 dly(2T, 0.5T) = (0, 10)
6604 11:10:34.013949 best DQS1 dly(2T, 0.5T) = (0, 10)
6605 11:10:34.017223 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6606 11:10:34.020649 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6607 11:10:34.020730 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 11:10:34.023949 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 11:10:34.027108 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 11:10:34.030541 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 11:10:34.033676 Pre-setting of DQS Precalculation
6612 11:10:34.040339 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6613 11:10:34.040421 ==
6614 11:10:34.043642 Dram Type= 6, Freq= 0, CH_1, rank 0
6615 11:10:34.046975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 11:10:34.047057 ==
6617 11:10:34.053650 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6618 11:10:34.060085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6619 11:10:34.063781 [CA 0] Center 36 (8~64) winsize 57
6620 11:10:34.063862 [CA 1] Center 36 (8~64) winsize 57
6621 11:10:34.066827 [CA 2] Center 36 (8~64) winsize 57
6622 11:10:34.070211 [CA 3] Center 36 (8~64) winsize 57
6623 11:10:34.073681 [CA 4] Center 36 (8~64) winsize 57
6624 11:10:34.076651 [CA 5] Center 36 (8~64) winsize 57
6625 11:10:34.076732
6626 11:10:34.080130 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6627 11:10:34.080211
6628 11:10:34.083318 [CATrainingPosCal] consider 1 rank data
6629 11:10:34.086742 u2DelayCellTimex100 = 270/100 ps
6630 11:10:34.089812 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 11:10:34.096654 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 11:10:34.100031 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 11:10:34.103420 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 11:10:34.106641 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 11:10:34.110095 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 11:10:34.110176
6637 11:10:34.113226 CA PerBit enable=1, Macro0, CA PI delay=36
6638 11:10:34.113307
6639 11:10:34.116594 [CBTSetCACLKResult] CA Dly = 36
6640 11:10:34.116674 CS Dly: 1 (0~32)
6641 11:10:34.119870 ==
6642 11:10:34.123264 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 11:10:34.126491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 11:10:34.126573 ==
6645 11:10:34.132774 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 11:10:34.136386 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6647 11:10:34.139509 [CA 0] Center 36 (8~64) winsize 57
6648 11:10:34.142917 [CA 1] Center 36 (8~64) winsize 57
6649 11:10:34.146219 [CA 2] Center 36 (8~64) winsize 57
6650 11:10:34.149706 [CA 3] Center 36 (8~64) winsize 57
6651 11:10:34.152587 [CA 4] Center 36 (8~64) winsize 57
6652 11:10:34.156097 [CA 5] Center 36 (8~64) winsize 57
6653 11:10:34.156179
6654 11:10:34.159680 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6655 11:10:34.159762
6656 11:10:34.162584 [CATrainingPosCal] consider 2 rank data
6657 11:10:34.165992 u2DelayCellTimex100 = 270/100 ps
6658 11:10:34.169331 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 11:10:34.172448 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 11:10:34.175875 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 11:10:34.182651 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 11:10:34.185785 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 11:10:34.189324 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 11:10:34.189405
6665 11:10:34.192505 CA PerBit enable=1, Macro0, CA PI delay=36
6666 11:10:34.192587
6667 11:10:34.195768 [CBTSetCACLKResult] CA Dly = 36
6668 11:10:34.195866 CS Dly: 1 (0~32)
6669 11:10:34.195930
6670 11:10:34.199022 ----->DramcWriteLeveling(PI) begin...
6671 11:10:34.202377 ==
6672 11:10:34.202456 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 11:10:34.209116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 11:10:34.209196 ==
6675 11:10:34.212274 Write leveling (Byte 0): 40 => 8
6676 11:10:34.215629 Write leveling (Byte 1): 40 => 8
6677 11:10:34.215715 DramcWriteLeveling(PI) end<-----
6678 11:10:34.218731
6679 11:10:34.218810 ==
6680 11:10:34.222180 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 11:10:34.225552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 11:10:34.225634 ==
6683 11:10:34.228534 [Gating] SW mode calibration
6684 11:10:34.235167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6685 11:10:34.242015 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6686 11:10:34.245259 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6687 11:10:34.248584 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6688 11:10:34.255203 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 11:10:34.258445 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 11:10:34.261873 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 11:10:34.268122 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 11:10:34.271545 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 11:10:34.274646 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 11:10:34.281449 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 11:10:34.281535 Total UI for P1: 0, mck2ui 16
6696 11:10:34.284541 best dqsien dly found for B0: ( 0, 14, 24)
6697 11:10:34.288165 Total UI for P1: 0, mck2ui 16
6698 11:10:34.291272 best dqsien dly found for B1: ( 0, 14, 24)
6699 11:10:34.298063 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6700 11:10:34.301082 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6701 11:10:34.301161
6702 11:10:34.304589 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6703 11:10:34.307963 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6704 11:10:34.311360 [Gating] SW calibration Done
6705 11:10:34.311440 ==
6706 11:10:34.314653 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 11:10:34.317844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 11:10:34.317927 ==
6709 11:10:34.321062 RX Vref Scan: 0
6710 11:10:34.321143
6711 11:10:34.321206 RX Vref 0 -> 0, step: 1
6712 11:10:34.321265
6713 11:10:34.324581 RX Delay -410 -> 252, step: 16
6714 11:10:34.330789 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6715 11:10:34.334069 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6716 11:10:34.337332 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6717 11:10:34.340821 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6718 11:10:34.347306 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6719 11:10:34.350659 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6720 11:10:34.353967 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6721 11:10:34.357306 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6722 11:10:34.363825 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6723 11:10:34.367318 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6724 11:10:34.370604 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6725 11:10:34.373919 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6726 11:10:34.380667 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6727 11:10:34.383752 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6728 11:10:34.386889 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6729 11:10:34.390306 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6730 11:10:34.393585 ==
6731 11:10:34.397006 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 11:10:34.400202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 11:10:34.400277 ==
6734 11:10:34.400338 DQS Delay:
6735 11:10:34.403720 DQS0 = 51, DQS1 = 67
6736 11:10:34.403801 DQM Delay:
6737 11:10:34.406681 DQM0 = 12, DQM1 = 19
6738 11:10:34.406761 DQ Delay:
6739 11:10:34.409895 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6740 11:10:34.413258 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6741 11:10:34.416564 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6742 11:10:34.420134 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6743 11:10:34.420215
6744 11:10:34.420279
6745 11:10:34.420339 ==
6746 11:10:34.423058 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 11:10:34.426518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 11:10:34.426604 ==
6749 11:10:34.426669
6750 11:10:34.426728
6751 11:10:34.430025 TX Vref Scan disable
6752 11:10:34.430106 == TX Byte 0 ==
6753 11:10:34.436566 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 11:10:34.439670 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 11:10:34.439777 == TX Byte 1 ==
6756 11:10:34.446247 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 11:10:34.449702 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 11:10:34.449809 ==
6759 11:10:34.452863 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 11:10:34.456153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 11:10:34.456260 ==
6762 11:10:34.456328
6763 11:10:34.459458
6764 11:10:34.459538 TX Vref Scan disable
6765 11:10:34.462732 == TX Byte 0 ==
6766 11:10:34.466181 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 11:10:34.469501 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 11:10:34.472787 == TX Byte 1 ==
6769 11:10:34.475846 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 11:10:34.479663 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 11:10:34.479744
6772 11:10:34.479808 [DATLAT]
6773 11:10:34.482787 Freq=400, CH1 RK0
6774 11:10:34.482868
6775 11:10:34.485884 DATLAT Default: 0xf
6776 11:10:34.485965 0, 0xFFFF, sum = 0
6777 11:10:34.489206 1, 0xFFFF, sum = 0
6778 11:10:34.489312 2, 0xFFFF, sum = 0
6779 11:10:34.492295 3, 0xFFFF, sum = 0
6780 11:10:34.492377 4, 0xFFFF, sum = 0
6781 11:10:34.495799 5, 0xFFFF, sum = 0
6782 11:10:34.495897 6, 0xFFFF, sum = 0
6783 11:10:34.498885 7, 0xFFFF, sum = 0
6784 11:10:34.498984 8, 0xFFFF, sum = 0
6785 11:10:34.502215 9, 0xFFFF, sum = 0
6786 11:10:34.502334 10, 0xFFFF, sum = 0
6787 11:10:34.505622 11, 0xFFFF, sum = 0
6788 11:10:34.505705 12, 0xFFFF, sum = 0
6789 11:10:34.509153 13, 0x0, sum = 1
6790 11:10:34.509235 14, 0x0, sum = 2
6791 11:10:34.512556 15, 0x0, sum = 3
6792 11:10:34.512637 16, 0x0, sum = 4
6793 11:10:34.515826 best_step = 14
6794 11:10:34.515907
6795 11:10:34.515980 ==
6796 11:10:34.518981 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 11:10:34.522090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 11:10:34.522265 ==
6799 11:10:34.525872 RX Vref Scan: 1
6800 11:10:34.526028
6801 11:10:34.526168 RX Vref 0 -> 0, step: 1
6802 11:10:34.526303
6803 11:10:34.528809 RX Delay -375 -> 252, step: 8
6804 11:10:34.528977
6805 11:10:34.532193 Set Vref, RX VrefLevel [Byte0]: 57
6806 11:10:34.535277 [Byte1]: 51
6807 11:10:34.540074
6808 11:10:34.540228 Final RX Vref Byte 0 = 57 to rank0
6809 11:10:34.543292 Final RX Vref Byte 1 = 51 to rank0
6810 11:10:34.546683 Final RX Vref Byte 0 = 57 to rank1
6811 11:10:34.550054 Final RX Vref Byte 1 = 51 to rank1==
6812 11:10:34.553468 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 11:10:34.560033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 11:10:34.560231 ==
6815 11:10:34.560373 DQS Delay:
6816 11:10:34.563686 DQS0 = 56, DQS1 = 64
6817 11:10:34.563840 DQM Delay:
6818 11:10:34.563977 DQM0 = 13, DQM1 = 10
6819 11:10:34.566570 DQ Delay:
6820 11:10:34.569934 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6821 11:10:34.570086 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6822 11:10:34.573345 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6823 11:10:34.576514 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6824 11:10:34.576668
6825 11:10:34.579925
6826 11:10:34.586497 [DQSOSCAuto] RK0, (LSB)MR18= 0x5165, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
6827 11:10:34.590013 CH1 RK0: MR19=C0C, MR18=5165
6828 11:10:34.596742 CH1_RK0: MR19=0xC0C, MR18=0x5165, DQSOSC=397, MR23=63, INC=374, DEC=249
6829 11:10:34.596908 ==
6830 11:10:34.599945 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 11:10:34.603311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 11:10:34.603466 ==
6833 11:10:34.606568 [Gating] SW mode calibration
6834 11:10:34.613284 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6835 11:10:34.619744 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6836 11:10:34.622963 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6837 11:10:34.626453 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6838 11:10:34.633089 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 11:10:34.636138 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 11:10:34.639643 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 11:10:34.646249 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 11:10:34.649312 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 11:10:34.652735 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 11:10:34.659300 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 11:10:34.659408 Total UI for P1: 0, mck2ui 16
6846 11:10:34.665757 best dqsien dly found for B0: ( 0, 14, 24)
6847 11:10:34.665839 Total UI for P1: 0, mck2ui 16
6848 11:10:34.669273 best dqsien dly found for B1: ( 0, 14, 24)
6849 11:10:34.675911 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6850 11:10:34.679334 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6851 11:10:34.679416
6852 11:10:34.682221 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6853 11:10:34.685931 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6854 11:10:34.689061 [Gating] SW calibration Done
6855 11:10:34.689142 ==
6856 11:10:34.692280 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 11:10:34.695441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 11:10:34.695523 ==
6859 11:10:34.698808 RX Vref Scan: 0
6860 11:10:34.698889
6861 11:10:34.698953 RX Vref 0 -> 0, step: 1
6862 11:10:34.699012
6863 11:10:34.702237 RX Delay -410 -> 252, step: 16
6864 11:10:34.709063 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6865 11:10:34.712247 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6866 11:10:34.715365 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6867 11:10:34.718715 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6868 11:10:34.725337 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6869 11:10:34.728837 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6870 11:10:34.732233 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6871 11:10:34.735341 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6872 11:10:34.742115 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6873 11:10:34.745137 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6874 11:10:34.748727 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6875 11:10:34.752030 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6876 11:10:34.758501 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6877 11:10:34.761860 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6878 11:10:34.765062 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6879 11:10:34.771636 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6880 11:10:34.771716 ==
6881 11:10:34.775154 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 11:10:34.778266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 11:10:34.778346 ==
6884 11:10:34.778409 DQS Delay:
6885 11:10:34.781512 DQS0 = 59, DQS1 = 67
6886 11:10:34.781605 DQM Delay:
6887 11:10:34.785056 DQM0 = 19, DQM1 = 21
6888 11:10:34.785135 DQ Delay:
6889 11:10:34.788485 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6890 11:10:34.791573 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6891 11:10:34.794799 DQ8 =0, DQ9 =16, DQ10 =24, DQ11 =16
6892 11:10:34.798148 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6893 11:10:34.798227
6894 11:10:34.798290
6895 11:10:34.798347 ==
6896 11:10:34.801645 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 11:10:34.804760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 11:10:34.804841 ==
6899 11:10:34.804904
6900 11:10:34.804962
6901 11:10:34.808177 TX Vref Scan disable
6902 11:10:34.811562 == TX Byte 0 ==
6903 11:10:34.814920 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6904 11:10:34.818411 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6905 11:10:34.818484 == TX Byte 1 ==
6906 11:10:34.824643 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6907 11:10:34.828186 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6908 11:10:34.828258 ==
6909 11:10:34.831461 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 11:10:34.834587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 11:10:34.834662 ==
6912 11:10:34.834723
6913 11:10:34.837903
6914 11:10:34.837971 TX Vref Scan disable
6915 11:10:34.841144 == TX Byte 0 ==
6916 11:10:34.844688 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6917 11:10:34.848064 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6918 11:10:34.851092 == TX Byte 1 ==
6919 11:10:34.854563 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6920 11:10:34.857637 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6921 11:10:34.857713
6922 11:10:34.857774 [DATLAT]
6923 11:10:34.861058 Freq=400, CH1 RK1
6924 11:10:34.861129
6925 11:10:34.861189 DATLAT Default: 0xe
6926 11:10:34.864402 0, 0xFFFF, sum = 0
6927 11:10:34.864474 1, 0xFFFF, sum = 0
6928 11:10:34.867912 2, 0xFFFF, sum = 0
6929 11:10:34.871146 3, 0xFFFF, sum = 0
6930 11:10:34.871219 4, 0xFFFF, sum = 0
6931 11:10:34.874507 5, 0xFFFF, sum = 0
6932 11:10:34.874579 6, 0xFFFF, sum = 0
6933 11:10:34.877744 7, 0xFFFF, sum = 0
6934 11:10:34.877818 8, 0xFFFF, sum = 0
6935 11:10:34.881160 9, 0xFFFF, sum = 0
6936 11:10:34.881236 10, 0xFFFF, sum = 0
6937 11:10:34.884365 11, 0xFFFF, sum = 0
6938 11:10:34.884435 12, 0xFFFF, sum = 0
6939 11:10:34.887841 13, 0x0, sum = 1
6940 11:10:34.887910 14, 0x0, sum = 2
6941 11:10:34.890916 15, 0x0, sum = 3
6942 11:10:34.890983 16, 0x0, sum = 4
6943 11:10:34.894255 best_step = 14
6944 11:10:34.894327
6945 11:10:34.894387 ==
6946 11:10:34.897678 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 11:10:34.900854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 11:10:34.900923 ==
6949 11:10:34.900989 RX Vref Scan: 0
6950 11:10:34.904090
6951 11:10:34.904158 RX Vref 0 -> 0, step: 1
6952 11:10:34.904215
6953 11:10:34.907749 RX Delay -375 -> 252, step: 8
6954 11:10:34.914967 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6955 11:10:34.918223 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6956 11:10:34.921623 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6957 11:10:34.928034 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6958 11:10:34.931486 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6959 11:10:34.934633 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6960 11:10:34.937891 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6961 11:10:34.944625 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6962 11:10:34.947813 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6963 11:10:34.951187 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6964 11:10:34.954655 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6965 11:10:34.961179 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6966 11:10:34.964519 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6967 11:10:34.967676 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6968 11:10:34.971031 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6969 11:10:34.977794 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6970 11:10:34.977876 ==
6971 11:10:34.980913 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 11:10:34.984297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 11:10:34.984379 ==
6974 11:10:34.984444 DQS Delay:
6975 11:10:34.987599 DQS0 = 60, DQS1 = 64
6976 11:10:34.987709 DQM Delay:
6977 11:10:34.990813 DQM0 = 13, DQM1 = 10
6978 11:10:34.990894 DQ Delay:
6979 11:10:34.994176 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6980 11:10:34.997516 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6981 11:10:35.000789 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6982 11:10:35.004206 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6983 11:10:35.004287
6984 11:10:35.004355
6985 11:10:35.010831 [DQSOSCAuto] RK1, (LSB)MR18= 0x79aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6986 11:10:35.014043 CH1 RK1: MR19=C0C, MR18=79AA
6987 11:10:35.021010 CH1_RK1: MR19=0xC0C, MR18=0x79AA, DQSOSC=388, MR23=63, INC=392, DEC=261
6988 11:10:35.024188 [RxdqsGatingPostProcess] freq 400
6989 11:10:35.030795 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6990 11:10:35.033801 best DQS0 dly(2T, 0.5T) = (0, 10)
6991 11:10:35.037281 best DQS1 dly(2T, 0.5T) = (0, 10)
6992 11:10:35.040537 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6993 11:10:35.043991 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6994 11:10:35.044072 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 11:10:35.047206 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 11:10:35.050445 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 11:10:35.053710 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 11:10:35.057186 Pre-setting of DQS Precalculation
6999 11:10:35.063600 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7000 11:10:35.070525 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7001 11:10:35.077197 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7002 11:10:35.077304
7003 11:10:35.077396
7004 11:10:35.080197 [Calibration Summary] 800 Mbps
7005 11:10:35.080305 CH 0, Rank 0
7006 11:10:35.083658 SW Impedance : PASS
7007 11:10:35.086806 DUTY Scan : NO K
7008 11:10:35.086887 ZQ Calibration : PASS
7009 11:10:35.090182 Jitter Meter : NO K
7010 11:10:35.093495 CBT Training : PASS
7011 11:10:35.093589 Write leveling : PASS
7012 11:10:35.097004 RX DQS gating : PASS
7013 11:10:35.100067 RX DQ/DQS(RDDQC) : PASS
7014 11:10:35.100148 TX DQ/DQS : PASS
7015 11:10:35.103657 RX DATLAT : PASS
7016 11:10:35.106783 RX DQ/DQS(Engine): PASS
7017 11:10:35.106863 TX OE : NO K
7018 11:10:35.110119 All Pass.
7019 11:10:35.110200
7020 11:10:35.110264 CH 0, Rank 1
7021 11:10:35.113362 SW Impedance : PASS
7022 11:10:35.113472 DUTY Scan : NO K
7023 11:10:35.116528 ZQ Calibration : PASS
7024 11:10:35.119773 Jitter Meter : NO K
7025 11:10:35.119870 CBT Training : PASS
7026 11:10:35.123449 Write leveling : NO K
7027 11:10:35.126484 RX DQS gating : PASS
7028 11:10:35.126559 RX DQ/DQS(RDDQC) : PASS
7029 11:10:35.129971 TX DQ/DQS : PASS
7030 11:10:35.130052 RX DATLAT : PASS
7031 11:10:35.133391 RX DQ/DQS(Engine): PASS
7032 11:10:35.136389 TX OE : NO K
7033 11:10:35.136473 All Pass.
7034 11:10:35.136537
7035 11:10:35.136596 CH 1, Rank 0
7036 11:10:35.139758 SW Impedance : PASS
7037 11:10:35.143115 DUTY Scan : NO K
7038 11:10:35.143195 ZQ Calibration : PASS
7039 11:10:35.146582 Jitter Meter : NO K
7040 11:10:35.149983 CBT Training : PASS
7041 11:10:35.150068 Write leveling : PASS
7042 11:10:35.153020 RX DQS gating : PASS
7043 11:10:35.156191 RX DQ/DQS(RDDQC) : PASS
7044 11:10:35.156273 TX DQ/DQS : PASS
7045 11:10:35.159755 RX DATLAT : PASS
7046 11:10:35.162716 RX DQ/DQS(Engine): PASS
7047 11:10:35.162797 TX OE : NO K
7048 11:10:35.166159 All Pass.
7049 11:10:35.166254
7050 11:10:35.166319 CH 1, Rank 1
7051 11:10:35.169753 SW Impedance : PASS
7052 11:10:35.169835 DUTY Scan : NO K
7053 11:10:35.173069 ZQ Calibration : PASS
7054 11:10:35.176244 Jitter Meter : NO K
7055 11:10:35.176325 CBT Training : PASS
7056 11:10:35.179516 Write leveling : NO K
7057 11:10:35.183022 RX DQS gating : PASS
7058 11:10:35.183103 RX DQ/DQS(RDDQC) : PASS
7059 11:10:35.186020 TX DQ/DQS : PASS
7060 11:10:35.186101 RX DATLAT : PASS
7061 11:10:35.189330 RX DQ/DQS(Engine): PASS
7062 11:10:35.192738 TX OE : NO K
7063 11:10:35.192822 All Pass.
7064 11:10:35.192886
7065 11:10:35.196275 DramC Write-DBI off
7066 11:10:35.196356 PER_BANK_REFRESH: Hybrid Mode
7067 11:10:35.199632 TX_TRACKING: ON
7068 11:10:35.209447 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7069 11:10:35.212894 [FAST_K] Save calibration result to emmc
7070 11:10:35.215892 dramc_set_vcore_voltage set vcore to 725000
7071 11:10:35.219133 Read voltage for 1600, 0
7072 11:10:35.219214 Vio18 = 0
7073 11:10:35.219278 Vcore = 725000
7074 11:10:35.222660 Vdram = 0
7075 11:10:35.222741 Vddq = 0
7076 11:10:35.222805 Vmddr = 0
7077 11:10:35.229154 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7078 11:10:35.232493 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7079 11:10:35.236025 MEM_TYPE=3, freq_sel=13
7080 11:10:35.238950 sv_algorithm_assistance_LP4_3733
7081 11:10:35.242461 ============ PULL DRAM RESETB DOWN ============
7082 11:10:35.245773 ========== PULL DRAM RESETB DOWN end =========
7083 11:10:35.252263 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7084 11:10:35.255732 ===================================
7085 11:10:35.255832 LPDDR4 DRAM CONFIGURATION
7086 11:10:35.258853 ===================================
7087 11:10:35.262354 EX_ROW_EN[0] = 0x0
7088 11:10:35.265537 EX_ROW_EN[1] = 0x0
7089 11:10:35.265619 LP4Y_EN = 0x0
7090 11:10:35.269184 WORK_FSP = 0x1
7091 11:10:35.269290 WL = 0x5
7092 11:10:35.272178 RL = 0x5
7093 11:10:35.272286 BL = 0x2
7094 11:10:35.275566 RPST = 0x0
7095 11:10:35.275674 RD_PRE = 0x0
7096 11:10:35.279056 WR_PRE = 0x1
7097 11:10:35.279128 WR_PST = 0x1
7098 11:10:35.282275 DBI_WR = 0x0
7099 11:10:35.282345 DBI_RD = 0x0
7100 11:10:35.285490 OTF = 0x1
7101 11:10:35.289047 ===================================
7102 11:10:35.292223 ===================================
7103 11:10:35.292320 ANA top config
7104 11:10:35.295725 ===================================
7105 11:10:35.298695 DLL_ASYNC_EN = 0
7106 11:10:35.302142 ALL_SLAVE_EN = 0
7107 11:10:35.305591 NEW_RANK_MODE = 1
7108 11:10:35.305677 DLL_IDLE_MODE = 1
7109 11:10:35.308600 LP45_APHY_COMB_EN = 1
7110 11:10:35.311973 TX_ODT_DIS = 0
7111 11:10:35.315583 NEW_8X_MODE = 1
7112 11:10:35.318553 ===================================
7113 11:10:35.322226 ===================================
7114 11:10:35.325243 data_rate = 3200
7115 11:10:35.325322 CKR = 1
7116 11:10:35.328510 DQ_P2S_RATIO = 8
7117 11:10:35.331963 ===================================
7118 11:10:35.335067 CA_P2S_RATIO = 8
7119 11:10:35.338286 DQ_CA_OPEN = 0
7120 11:10:35.342053 DQ_SEMI_OPEN = 0
7121 11:10:35.345088 CA_SEMI_OPEN = 0
7122 11:10:35.345161 CA_FULL_RATE = 0
7123 11:10:35.348226 DQ_CKDIV4_EN = 0
7124 11:10:35.351518 CA_CKDIV4_EN = 0
7125 11:10:35.355129 CA_PREDIV_EN = 0
7126 11:10:35.358223 PH8_DLY = 12
7127 11:10:35.361302 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7128 11:10:35.361382 DQ_AAMCK_DIV = 4
7129 11:10:35.364958 CA_AAMCK_DIV = 4
7130 11:10:35.368076 CA_ADMCK_DIV = 4
7131 11:10:35.371480 DQ_TRACK_CA_EN = 0
7132 11:10:35.374399 CA_PICK = 1600
7133 11:10:35.377934 CA_MCKIO = 1600
7134 11:10:35.381172 MCKIO_SEMI = 0
7135 11:10:35.384406 PLL_FREQ = 3068
7136 11:10:35.384487 DQ_UI_PI_RATIO = 32
7137 11:10:35.387821 CA_UI_PI_RATIO = 0
7138 11:10:35.390863 ===================================
7139 11:10:35.394239 ===================================
7140 11:10:35.397744 memory_type:LPDDR4
7141 11:10:35.400865 GP_NUM : 10
7142 11:10:35.400945 SRAM_EN : 1
7143 11:10:35.404344 MD32_EN : 0
7144 11:10:35.407369 ===================================
7145 11:10:35.411123 [ANA_INIT] >>>>>>>>>>>>>>
7146 11:10:35.411203 <<<<<< [CONFIGURE PHASE]: ANA_TX
7147 11:10:35.417607 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7148 11:10:35.420596 ===================================
7149 11:10:35.420676 data_rate = 3200,PCW = 0X7600
7150 11:10:35.424037 ===================================
7151 11:10:35.427452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7152 11:10:35.434034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7153 11:10:35.440654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7154 11:10:35.444022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7155 11:10:35.447410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7156 11:10:35.450470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7157 11:10:35.454045 [ANA_INIT] flow start
7158 11:10:35.454125 [ANA_INIT] PLL >>>>>>>>
7159 11:10:35.457184 [ANA_INIT] PLL <<<<<<<<
7160 11:10:35.460680 [ANA_INIT] MIDPI >>>>>>>>
7161 11:10:35.463782 [ANA_INIT] MIDPI <<<<<<<<
7162 11:10:35.463862 [ANA_INIT] DLL >>>>>>>>
7163 11:10:35.467246 [ANA_INIT] DLL <<<<<<<<
7164 11:10:35.467326 [ANA_INIT] flow end
7165 11:10:35.473638 ============ LP4 DIFF to SE enter ============
7166 11:10:35.477157 ============ LP4 DIFF to SE exit ============
7167 11:10:35.480388 [ANA_INIT] <<<<<<<<<<<<<
7168 11:10:35.483815 [Flow] Enable top DCM control >>>>>
7169 11:10:35.487124 [Flow] Enable top DCM control <<<<<
7170 11:10:35.490554 Enable DLL master slave shuffle
7171 11:10:35.493912 ==============================================================
7172 11:10:35.497138 Gating Mode config
7173 11:10:35.500128 ==============================================================
7174 11:10:35.503540 Config description:
7175 11:10:35.513527 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7176 11:10:35.520154 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7177 11:10:35.523441 SELPH_MODE 0: By rank 1: By Phase
7178 11:10:35.530184 ==============================================================
7179 11:10:35.533407 GAT_TRACK_EN = 1
7180 11:10:35.536642 RX_GATING_MODE = 2
7181 11:10:35.540076 RX_GATING_TRACK_MODE = 2
7182 11:10:35.543216 SELPH_MODE = 1
7183 11:10:35.546556 PICG_EARLY_EN = 1
7184 11:10:35.549883 VALID_LAT_VALUE = 1
7185 11:10:35.553338 ==============================================================
7186 11:10:35.556452 Enter into Gating configuration >>>>
7187 11:10:35.559931 Exit from Gating configuration <<<<
7188 11:10:35.563105 Enter into DVFS_PRE_config >>>>>
7189 11:10:35.576543 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7190 11:10:35.576625 Exit from DVFS_PRE_config <<<<<
7191 11:10:35.579721 Enter into PICG configuration >>>>
7192 11:10:35.582881 Exit from PICG configuration <<<<
7193 11:10:35.586233 [RX_INPUT] configuration >>>>>
7194 11:10:35.589438 [RX_INPUT] configuration <<<<<
7195 11:10:35.595942 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7196 11:10:35.599464 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7197 11:10:35.606170 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7198 11:10:35.612524 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7199 11:10:35.619320 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7200 11:10:35.625740 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7201 11:10:35.629173 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7202 11:10:35.632499 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7203 11:10:35.635875 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7204 11:10:35.642643 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7205 11:10:35.645640 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7206 11:10:35.649063 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7207 11:10:35.652294 ===================================
7208 11:10:35.655762 LPDDR4 DRAM CONFIGURATION
7209 11:10:35.659119 ===================================
7210 11:10:35.662418 EX_ROW_EN[0] = 0x0
7211 11:10:35.662498 EX_ROW_EN[1] = 0x0
7212 11:10:35.665402 LP4Y_EN = 0x0
7213 11:10:35.665539 WORK_FSP = 0x1
7214 11:10:35.668804 WL = 0x5
7215 11:10:35.668884 RL = 0x5
7216 11:10:35.672193 BL = 0x2
7217 11:10:35.672273 RPST = 0x0
7218 11:10:35.675301 RD_PRE = 0x0
7219 11:10:35.675381 WR_PRE = 0x1
7220 11:10:35.678750 WR_PST = 0x1
7221 11:10:35.678829 DBI_WR = 0x0
7222 11:10:35.682040 DBI_RD = 0x0
7223 11:10:35.682120 OTF = 0x1
7224 11:10:35.685369 ===================================
7225 11:10:35.692106 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7226 11:10:35.695292 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7227 11:10:35.698457 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7228 11:10:35.701700 ===================================
7229 11:10:35.705133 LPDDR4 DRAM CONFIGURATION
7230 11:10:35.708671 ===================================
7231 11:10:35.712179 EX_ROW_EN[0] = 0x10
7232 11:10:35.712259 EX_ROW_EN[1] = 0x0
7233 11:10:35.714965 LP4Y_EN = 0x0
7234 11:10:35.715044 WORK_FSP = 0x1
7235 11:10:35.718484 WL = 0x5
7236 11:10:35.718564 RL = 0x5
7237 11:10:35.721866 BL = 0x2
7238 11:10:35.721945 RPST = 0x0
7239 11:10:35.725093 RD_PRE = 0x0
7240 11:10:35.725172 WR_PRE = 0x1
7241 11:10:35.728119 WR_PST = 0x1
7242 11:10:35.728229 DBI_WR = 0x0
7243 11:10:35.731575 DBI_RD = 0x0
7244 11:10:35.731657 OTF = 0x1
7245 11:10:35.734909 ===================================
7246 11:10:35.741415 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7247 11:10:35.741522 ==
7248 11:10:35.744611 Dram Type= 6, Freq= 0, CH_0, rank 0
7249 11:10:35.751464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7250 11:10:35.751648 ==
7251 11:10:35.751746 [Duty_Offset_Calibration]
7252 11:10:35.754677 B0:2 B1:0 CA:3
7253 11:10:35.754762
7254 11:10:35.758156 [DutyScan_Calibration_Flow] k_type=0
7255 11:10:35.767237
7256 11:10:35.767397 ==CLK 0==
7257 11:10:35.770582 Final CLK duty delay cell = 0
7258 11:10:35.774295 [0] MAX Duty = 5031%(X100), DQS PI = 12
7259 11:10:35.777302 [0] MIN Duty = 4907%(X100), DQS PI = 6
7260 11:10:35.777383 [0] AVG Duty = 4969%(X100)
7261 11:10:35.780647
7262 11:10:35.784136 CH0 CLK Duty spec in!! Max-Min= 124%
7263 11:10:35.787090 [DutyScan_Calibration_Flow] ====Done====
7264 11:10:35.787171
7265 11:10:35.790473 [DutyScan_Calibration_Flow] k_type=1
7266 11:10:35.807210
7267 11:10:35.807307 ==DQS 0 ==
7268 11:10:35.810510 Final DQS duty delay cell = 0
7269 11:10:35.814026 [0] MAX Duty = 5094%(X100), DQS PI = 28
7270 11:10:35.817192 [0] MIN Duty = 4875%(X100), DQS PI = 48
7271 11:10:35.820574 [0] AVG Duty = 4984%(X100)
7272 11:10:35.820656
7273 11:10:35.820720 ==DQS 1 ==
7274 11:10:35.823633 Final DQS duty delay cell = 0
7275 11:10:35.827053 [0] MAX Duty = 5156%(X100), DQS PI = 32
7276 11:10:35.830325 [0] MIN Duty = 5062%(X100), DQS PI = 8
7277 11:10:35.833784 [0] AVG Duty = 5109%(X100)
7278 11:10:35.833865
7279 11:10:35.837179 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7280 11:10:35.837259
7281 11:10:35.840405 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7282 11:10:35.843701 [DutyScan_Calibration_Flow] ====Done====
7283 11:10:35.843846
7284 11:10:35.846725 [DutyScan_Calibration_Flow] k_type=3
7285 11:10:35.865312
7286 11:10:35.865488 ==DQM 0 ==
7287 11:10:35.868523 Final DQM duty delay cell = 0
7288 11:10:35.871974 [0] MAX Duty = 5156%(X100), DQS PI = 30
7289 11:10:35.875107 [0] MIN Duty = 4875%(X100), DQS PI = 0
7290 11:10:35.875190 [0] AVG Duty = 5015%(X100)
7291 11:10:35.878485
7292 11:10:35.878565 ==DQM 1 ==
7293 11:10:35.881711 Final DQM duty delay cell = 4
7294 11:10:35.884944 [4] MAX Duty = 5187%(X100), DQS PI = 60
7295 11:10:35.888365 [4] MIN Duty = 5000%(X100), DQS PI = 14
7296 11:10:35.891492 [4] AVG Duty = 5093%(X100)
7297 11:10:35.891574
7298 11:10:35.895084 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7299 11:10:35.895164
7300 11:10:35.898071 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7301 11:10:35.901389 [DutyScan_Calibration_Flow] ====Done====
7302 11:10:35.901518
7303 11:10:35.904457 [DutyScan_Calibration_Flow] k_type=2
7304 11:10:35.921662
7305 11:10:35.921785 ==DQ 0 ==
7306 11:10:35.924878 Final DQ duty delay cell = -4
7307 11:10:35.928331 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7308 11:10:35.931362 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7309 11:10:35.934785 [-4] AVG Duty = 4938%(X100)
7310 11:10:35.934867
7311 11:10:35.934931 ==DQ 1 ==
7312 11:10:35.938439 Final DQ duty delay cell = 0
7313 11:10:35.941451 [0] MAX Duty = 5156%(X100), DQS PI = 58
7314 11:10:35.945007 [0] MIN Duty = 5000%(X100), DQS PI = 14
7315 11:10:35.948051 [0] AVG Duty = 5078%(X100)
7316 11:10:35.948133
7317 11:10:35.951293 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7318 11:10:35.951374
7319 11:10:35.954662 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7320 11:10:35.957879 [DutyScan_Calibration_Flow] ====Done====
7321 11:10:35.957966 ==
7322 11:10:35.961154 Dram Type= 6, Freq= 0, CH_1, rank 0
7323 11:10:35.964627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7324 11:10:35.964709 ==
7325 11:10:35.967814 [Duty_Offset_Calibration]
7326 11:10:35.967908 B0:1 B1:-2 CA:0
7327 11:10:35.967973
7328 11:10:35.971072 [DutyScan_Calibration_Flow] k_type=0
7329 11:10:35.982185
7330 11:10:35.982288 ==CLK 0==
7331 11:10:35.985256 Final CLK duty delay cell = 0
7332 11:10:35.988664 [0] MAX Duty = 5093%(X100), DQS PI = 22
7333 11:10:35.992092 [0] MIN Duty = 4844%(X100), DQS PI = 2
7334 11:10:35.995071 [0] AVG Duty = 4968%(X100)
7335 11:10:35.995158
7336 11:10:35.998604 CH1 CLK Duty spec in!! Max-Min= 249%
7337 11:10:36.002137 [DutyScan_Calibration_Flow] ====Done====
7338 11:10:36.002219
7339 11:10:36.005128 [DutyScan_Calibration_Flow] k_type=1
7340 11:10:36.021594
7341 11:10:36.021805 ==DQS 0 ==
7342 11:10:36.025160 Final DQS duty delay cell = 0
7343 11:10:36.028290 [0] MAX Duty = 5187%(X100), DQS PI = 24
7344 11:10:36.031495 [0] MIN Duty = 5062%(X100), DQS PI = 0
7345 11:10:36.031600 [0] AVG Duty = 5124%(X100)
7346 11:10:36.035050
7347 11:10:36.035127 ==DQS 1 ==
7348 11:10:36.038468 Final DQS duty delay cell = 0
7349 11:10:36.041633 [0] MAX Duty = 5093%(X100), DQS PI = 0
7350 11:10:36.044965 [0] MIN Duty = 4875%(X100), DQS PI = 24
7351 11:10:36.045047 [0] AVG Duty = 4984%(X100)
7352 11:10:36.048531
7353 11:10:36.051612 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7354 11:10:36.051694
7355 11:10:36.055110 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7356 11:10:36.058197 [DutyScan_Calibration_Flow] ====Done====
7357 11:10:36.058284
7358 11:10:36.061490 [DutyScan_Calibration_Flow] k_type=3
7359 11:10:36.078490
7360 11:10:36.078622 ==DQM 0 ==
7361 11:10:36.081795 Final DQM duty delay cell = 0
7362 11:10:36.085177 [0] MAX Duty = 5031%(X100), DQS PI = 24
7363 11:10:36.088411 [0] MIN Duty = 4813%(X100), DQS PI = 54
7364 11:10:36.091797 [0] AVG Duty = 4922%(X100)
7365 11:10:36.091882
7366 11:10:36.091946 ==DQM 1 ==
7367 11:10:36.095109 Final DQM duty delay cell = 0
7368 11:10:36.098180 [0] MAX Duty = 5093%(X100), DQS PI = 36
7369 11:10:36.101751 [0] MIN Duty = 4875%(X100), DQS PI = 24
7370 11:10:36.105068 [0] AVG Duty = 4984%(X100)
7371 11:10:36.105154
7372 11:10:36.108505 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7373 11:10:36.108587
7374 11:10:36.111617 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7375 11:10:36.115093 [DutyScan_Calibration_Flow] ====Done====
7376 11:10:36.115176
7377 11:10:36.118274 [DutyScan_Calibration_Flow] k_type=2
7378 11:10:36.135686
7379 11:10:36.135861 ==DQ 0 ==
7380 11:10:36.138882 Final DQ duty delay cell = 0
7381 11:10:36.142128 [0] MAX Duty = 5093%(X100), DQS PI = 22
7382 11:10:36.145457 [0] MIN Duty = 4907%(X100), DQS PI = 46
7383 11:10:36.145581 [0] AVG Duty = 5000%(X100)
7384 11:10:36.148865
7385 11:10:36.148947 ==DQ 1 ==
7386 11:10:36.152064 Final DQ duty delay cell = 0
7387 11:10:36.155373 [0] MAX Duty = 5125%(X100), DQS PI = 34
7388 11:10:36.158868 [0] MIN Duty = 4969%(X100), DQS PI = 24
7389 11:10:36.158957 [0] AVG Duty = 5047%(X100)
7390 11:10:36.161885
7391 11:10:36.165313 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7392 11:10:36.165398
7393 11:10:36.168758 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7394 11:10:36.172231 [DutyScan_Calibration_Flow] ====Done====
7395 11:10:36.175260 nWR fixed to 30
7396 11:10:36.175344 [ModeRegInit_LP4] CH0 RK0
7397 11:10:36.178673 [ModeRegInit_LP4] CH0 RK1
7398 11:10:36.182176 [ModeRegInit_LP4] CH1 RK0
7399 11:10:36.185022 [ModeRegInit_LP4] CH1 RK1
7400 11:10:36.185106 match AC timing 5
7401 11:10:36.191856 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7402 11:10:36.194921 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7403 11:10:36.198195 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7404 11:10:36.204737 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7405 11:10:36.208078 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7406 11:10:36.208180 [MiockJmeterHQA]
7407 11:10:36.208249
7408 11:10:36.211300 [DramcMiockJmeter] u1RxGatingPI = 0
7409 11:10:36.214729 0 : 4363, 4137
7410 11:10:36.214843 4 : 4252, 4027
7411 11:10:36.218212 8 : 4368, 4140
7412 11:10:36.218318 12 : 4363, 4137
7413 11:10:36.218452 16 : 4363, 4137
7414 11:10:36.221314 20 : 4363, 4137
7415 11:10:36.221414 24 : 4252, 4027
7416 11:10:36.224546 28 : 4253, 4026
7417 11:10:36.224668 32 : 4252, 4027
7418 11:10:36.227987 36 : 4254, 4029
7419 11:10:36.228073 40 : 4363, 4137
7420 11:10:36.231578 44 : 4252, 4027
7421 11:10:36.231664 48 : 4252, 4027
7422 11:10:36.231729 52 : 4252, 4027
7423 11:10:36.234906 56 : 4254, 4029
7424 11:10:36.234989 60 : 4250, 4027
7425 11:10:36.237956 64 : 4360, 4138
7426 11:10:36.238041 68 : 4360, 4137
7427 11:10:36.241343 72 : 4250, 4027
7428 11:10:36.241428 76 : 4250, 4027
7429 11:10:36.244672 80 : 4250, 4026
7430 11:10:36.244756 84 : 4252, 4027
7431 11:10:36.244822 88 : 4252, 4029
7432 11:10:36.247664 92 : 4361, 4137
7433 11:10:36.247749 96 : 4250, 4027
7434 11:10:36.251252 100 : 4250, 4026
7435 11:10:36.251337 104 : 4361, 3780
7436 11:10:36.254493 108 : 4250, 1
7437 11:10:36.254577 112 : 4250, 0
7438 11:10:36.254643 116 : 4250, 0
7439 11:10:36.257586 120 : 4250, 0
7440 11:10:36.257704 124 : 4250, 0
7441 11:10:36.260963 128 : 4250, 0
7442 11:10:36.261048 132 : 4361, 0
7443 11:10:36.261114 136 : 4360, 0
7444 11:10:36.264414 140 : 4363, 0
7445 11:10:36.264498 144 : 4250, 0
7446 11:10:36.267452 148 : 4249, 0
7447 11:10:36.267539 152 : 4250, 0
7448 11:10:36.267619 156 : 4250, 0
7449 11:10:36.270968 160 : 4250, 0
7450 11:10:36.271052 164 : 4250, 0
7451 11:10:36.274334 168 : 4253, 0
7452 11:10:36.274417 172 : 4249, 0
7453 11:10:36.274483 176 : 4250, 0
7454 11:10:36.277385 180 : 4253, 0
7455 11:10:36.277469 184 : 4360, 0
7456 11:10:36.277542 188 : 4250, 0
7457 11:10:36.280808 192 : 4361, 0
7458 11:10:36.280894 196 : 4249, 0
7459 11:10:36.284163 200 : 4250, 0
7460 11:10:36.284249 204 : 4250, 0
7461 11:10:36.284315 208 : 4250, 0
7462 11:10:36.287548 212 : 4250, 0
7463 11:10:36.287632 216 : 4250, 0
7464 11:10:36.290665 220 : 4253, 0
7465 11:10:36.290748 224 : 4360, 0
7466 11:10:36.290813 228 : 4250, 0
7467 11:10:36.294004 232 : 4250, 0
7468 11:10:36.294087 236 : 4249, 1155
7469 11:10:36.297349 240 : 4252, 4029
7470 11:10:36.297433 244 : 4250, 4026
7471 11:10:36.300608 248 : 4250, 4027
7472 11:10:36.300692 252 : 4360, 4138
7473 11:10:36.304265 256 : 4249, 4027
7474 11:10:36.304349 260 : 4250, 4026
7475 11:10:36.307464 264 : 4361, 4137
7476 11:10:36.307547 268 : 4250, 4027
7477 11:10:36.307613 272 : 4249, 4027
7478 11:10:36.310813 276 : 4363, 4140
7479 11:10:36.310898 280 : 4250, 4026
7480 11:10:36.313903 284 : 4252, 4027
7481 11:10:36.313987 288 : 4252, 4027
7482 11:10:36.317187 292 : 4252, 4029
7483 11:10:36.317271 296 : 4250, 4026
7484 11:10:36.320540 300 : 4252, 4027
7485 11:10:36.320635 304 : 4363, 4138
7486 11:10:36.323892 308 : 4250, 4027
7487 11:10:36.323977 312 : 4250, 4026
7488 11:10:36.327364 316 : 4361, 4137
7489 11:10:36.327449 320 : 4252, 4027
7490 11:10:36.330482 324 : 4252, 4027
7491 11:10:36.330567 328 : 4363, 4140
7492 11:10:36.330632 332 : 4250, 4026
7493 11:10:36.334086 336 : 4252, 4027
7494 11:10:36.334170 340 : 4253, 4027
7495 11:10:36.337351 344 : 4252, 4029
7496 11:10:36.337434 348 : 4250, 4026
7497 11:10:36.340397 352 : 4252, 4021
7498 11:10:36.340519 356 : 4363, 3090
7499 11:10:36.343830 360 : 4249, 4
7500 11:10:36.343913
7501 11:10:36.343979 MIOCK jitter meter ch=0
7502 11:10:36.344039
7503 11:10:36.347155 1T = (360-108) = 252 dly cells
7504 11:10:36.353845 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7505 11:10:36.353949 ==
7506 11:10:36.356936 Dram Type= 6, Freq= 0, CH_0, rank 0
7507 11:10:36.360133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7508 11:10:36.360228 ==
7509 11:10:36.366758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7510 11:10:36.370322 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7511 11:10:36.376774 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7512 11:10:36.380151 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7513 11:10:36.390451 [CA 0] Center 43 (13~74) winsize 62
7514 11:10:36.393819 [CA 1] Center 43 (13~74) winsize 62
7515 11:10:36.397297 [CA 2] Center 38 (10~67) winsize 58
7516 11:10:36.400340 [CA 3] Center 38 (9~68) winsize 60
7517 11:10:36.403655 [CA 4] Center 36 (7~66) winsize 60
7518 11:10:36.407120 [CA 5] Center 36 (7~66) winsize 60
7519 11:10:36.407206
7520 11:10:36.410299 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7521 11:10:36.410382
7522 11:10:36.416897 [CATrainingPosCal] consider 1 rank data
7523 11:10:36.417005 u2DelayCellTimex100 = 258/100 ps
7524 11:10:36.423540 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7525 11:10:36.426749 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7526 11:10:36.430055 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7527 11:10:36.433605 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7528 11:10:36.436927 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7529 11:10:36.440182 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7530 11:10:36.440267
7531 11:10:36.443226 CA PerBit enable=1, Macro0, CA PI delay=36
7532 11:10:36.443309
7533 11:10:36.446575 [CBTSetCACLKResult] CA Dly = 36
7534 11:10:36.450222 CS Dly: 11 (0~42)
7535 11:10:36.453181 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7536 11:10:36.456466 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7537 11:10:36.456552 ==
7538 11:10:36.459917 Dram Type= 6, Freq= 0, CH_0, rank 1
7539 11:10:36.466505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 11:10:36.466609 ==
7541 11:10:36.469673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7542 11:10:36.476097 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7543 11:10:36.479547 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7544 11:10:36.486022 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7545 11:10:36.494242 [CA 0] Center 44 (14~75) winsize 62
7546 11:10:36.497332 [CA 1] Center 43 (13~74) winsize 62
7547 11:10:36.500695 [CA 2] Center 39 (10~69) winsize 60
7548 11:10:36.504207 [CA 3] Center 39 (10~69) winsize 60
7549 11:10:36.507208 [CA 4] Center 37 (8~67) winsize 60
7550 11:10:36.510674 [CA 5] Center 37 (7~67) winsize 61
7551 11:10:36.510760
7552 11:10:36.514103 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7553 11:10:36.514188
7554 11:10:36.520716 [CATrainingPosCal] consider 2 rank data
7555 11:10:36.520810 u2DelayCellTimex100 = 258/100 ps
7556 11:10:36.526955 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7557 11:10:36.530307 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7558 11:10:36.534018 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7559 11:10:36.537120 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7560 11:10:36.540456 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7561 11:10:36.543732 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7562 11:10:36.543823
7563 11:10:36.547131 CA PerBit enable=1, Macro0, CA PI delay=36
7564 11:10:36.547215
7565 11:10:36.550373 [CBTSetCACLKResult] CA Dly = 36
7566 11:10:36.553619 CS Dly: 11 (0~43)
7567 11:10:36.557197 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7568 11:10:36.560122 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7569 11:10:36.560220
7570 11:10:36.563440 ----->DramcWriteLeveling(PI) begin...
7571 11:10:36.563525 ==
7572 11:10:36.566732 Dram Type= 6, Freq= 0, CH_0, rank 0
7573 11:10:36.573514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 11:10:36.573624 ==
7575 11:10:36.576782 Write leveling (Byte 0): 36 => 36
7576 11:10:36.580245 Write leveling (Byte 1): 29 => 29
7577 11:10:36.580361 DramcWriteLeveling(PI) end<-----
7578 11:10:36.583600
7579 11:10:36.583685 ==
7580 11:10:36.587196 Dram Type= 6, Freq= 0, CH_0, rank 0
7581 11:10:36.590179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7582 11:10:36.590266 ==
7583 11:10:36.593349 [Gating] SW mode calibration
7584 11:10:36.600031 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7585 11:10:36.603626 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7586 11:10:36.610303 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 11:10:36.613435 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 11:10:36.616908 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 11:10:36.623450 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 11:10:36.626980 1 4 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7591 11:10:36.630131 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7592 11:10:36.636869 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7593 11:10:36.640108 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 11:10:36.643354 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 11:10:36.649961 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 11:10:36.653270 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 11:10:36.656531 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 11:10:36.662931 1 5 16 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7599 11:10:36.666433 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7600 11:10:36.669632 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7601 11:10:36.676323 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 11:10:36.679463 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 11:10:36.682895 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 11:10:36.689437 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 11:10:36.692831 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 11:10:36.696223 1 6 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7607 11:10:36.702642 1 6 20 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
7608 11:10:36.706234 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7609 11:10:36.709277 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 11:10:36.716034 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 11:10:36.719222 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 11:10:36.722536 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 11:10:36.729212 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 11:10:36.732692 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7615 11:10:36.735988 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7616 11:10:36.742390 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7617 11:10:36.745637 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 11:10:36.748949 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 11:10:36.755866 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 11:10:36.758692 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 11:10:36.762208 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 11:10:36.768898 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 11:10:36.772338 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 11:10:36.775493 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 11:10:36.782118 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 11:10:36.785376 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 11:10:36.788793 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 11:10:36.795263 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 11:10:36.798797 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 11:10:36.801847 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7631 11:10:36.808379 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7632 11:10:36.811702 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 11:10:36.814983 Total UI for P1: 0, mck2ui 16
7634 11:10:36.818555 best dqsien dly found for B0: ( 1, 9, 18)
7635 11:10:36.821533 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 11:10:36.824928 Total UI for P1: 0, mck2ui 16
7637 11:10:36.828080 best dqsien dly found for B1: ( 1, 9, 24)
7638 11:10:36.831720 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7639 11:10:36.834857 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7640 11:10:36.834944
7641 11:10:36.841140 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7642 11:10:36.844779 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7643 11:10:36.844870 [Gating] SW calibration Done
7644 11:10:36.847753 ==
7645 11:10:36.851281 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 11:10:36.854455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 11:10:36.854544 ==
7648 11:10:36.854609 RX Vref Scan: 0
7649 11:10:36.854671
7650 11:10:36.857773 RX Vref 0 -> 0, step: 1
7651 11:10:36.857857
7652 11:10:36.861286 RX Delay 0 -> 252, step: 8
7653 11:10:36.864538 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7654 11:10:36.867456 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7655 11:10:36.870918 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7656 11:10:36.877661 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7657 11:10:36.880861 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7658 11:10:36.884070 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7659 11:10:36.887546 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7660 11:10:36.890833 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7661 11:10:36.897649 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7662 11:10:36.900675 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7663 11:10:36.903910 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7664 11:10:36.907028 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7665 11:10:36.913902 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7666 11:10:36.916914 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7667 11:10:36.920321 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7668 11:10:36.924009 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7669 11:10:36.924102 ==
7670 11:10:36.926990 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 11:10:36.933379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 11:10:36.933484 ==
7673 11:10:36.933591 DQS Delay:
7674 11:10:36.936734 DQS0 = 0, DQS1 = 0
7675 11:10:36.936817 DQM Delay:
7676 11:10:36.936882 DQM0 = 127, DQM1 = 124
7677 11:10:36.940287 DQ Delay:
7678 11:10:36.943287 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7679 11:10:36.946808 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7680 11:10:36.950218 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7681 11:10:36.953419 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7682 11:10:36.953545
7683 11:10:36.953611
7684 11:10:36.953671 ==
7685 11:10:36.956718 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 11:10:36.963264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 11:10:36.963415 ==
7688 11:10:36.963483
7689 11:10:36.963543
7690 11:10:36.963599 TX Vref Scan disable
7691 11:10:36.966482 == TX Byte 0 ==
7692 11:10:36.969925 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7693 11:10:36.976597 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7694 11:10:36.976712 == TX Byte 1 ==
7695 11:10:36.979714 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7696 11:10:36.986574 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7697 11:10:36.986668 ==
7698 11:10:36.989767 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 11:10:36.992906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 11:10:36.992990 ==
7701 11:10:37.007408
7702 11:10:37.010869 TX Vref early break, caculate TX vref
7703 11:10:37.014427 TX Vref=16, minBit 0, minWin=22, winSum=360
7704 11:10:37.017341 TX Vref=18, minBit 8, minWin=22, winSum=373
7705 11:10:37.020691 TX Vref=20, minBit 8, minWin=23, winSum=381
7706 11:10:37.024096 TX Vref=22, minBit 8, minWin=23, winSum=399
7707 11:10:37.027254 TX Vref=24, minBit 4, minWin=24, winSum=405
7708 11:10:37.033842 TX Vref=26, minBit 0, minWin=25, winSum=409
7709 11:10:37.037251 TX Vref=28, minBit 4, minWin=25, winSum=413
7710 11:10:37.040734 TX Vref=30, minBit 8, minWin=24, winSum=404
7711 11:10:37.043708 TX Vref=32, minBit 8, minWin=24, winSum=396
7712 11:10:37.047384 TX Vref=34, minBit 9, minWin=23, winSum=395
7713 11:10:37.050365 TX Vref=36, minBit 8, minWin=22, winSum=378
7714 11:10:37.057220 [TxChooseVref] Worse bit 4, Min win 25, Win sum 413, Final Vref 28
7715 11:10:37.057360
7716 11:10:37.060489 Final TX Range 0 Vref 28
7717 11:10:37.060582
7718 11:10:37.060649 ==
7719 11:10:37.063771 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 11:10:37.067234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 11:10:37.067327 ==
7722 11:10:37.067393
7723 11:10:37.070189
7724 11:10:37.070274 TX Vref Scan disable
7725 11:10:37.077050 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7726 11:10:37.077151 == TX Byte 0 ==
7727 11:10:37.080264 u2DelayCellOfst[0]=15 cells (4 PI)
7728 11:10:37.083468 u2DelayCellOfst[1]=18 cells (5 PI)
7729 11:10:37.086736 u2DelayCellOfst[2]=15 cells (4 PI)
7730 11:10:37.090259 u2DelayCellOfst[3]=15 cells (4 PI)
7731 11:10:37.093330 u2DelayCellOfst[4]=11 cells (3 PI)
7732 11:10:37.096849 u2DelayCellOfst[5]=0 cells (0 PI)
7733 11:10:37.100265 u2DelayCellOfst[6]=22 cells (6 PI)
7734 11:10:37.103229 u2DelayCellOfst[7]=18 cells (5 PI)
7735 11:10:37.106797 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7736 11:10:37.110218 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7737 11:10:37.113410 == TX Byte 1 ==
7738 11:10:37.116838 u2DelayCellOfst[8]=0 cells (0 PI)
7739 11:10:37.120274 u2DelayCellOfst[9]=3 cells (1 PI)
7740 11:10:37.123388 u2DelayCellOfst[10]=7 cells (2 PI)
7741 11:10:37.126627 u2DelayCellOfst[11]=3 cells (1 PI)
7742 11:10:37.126723 u2DelayCellOfst[12]=15 cells (4 PI)
7743 11:10:37.129771 u2DelayCellOfst[13]=11 cells (3 PI)
7744 11:10:37.133095 u2DelayCellOfst[14]=18 cells (5 PI)
7745 11:10:37.136732 u2DelayCellOfst[15]=11 cells (3 PI)
7746 11:10:37.142886 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7747 11:10:37.146390 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7748 11:10:37.146478 DramC Write-DBI on
7749 11:10:37.149931 ==
7750 11:10:37.152763 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 11:10:37.156452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 11:10:37.156539 ==
7753 11:10:37.156605
7754 11:10:37.156664
7755 11:10:37.159423 TX Vref Scan disable
7756 11:10:37.159507 == TX Byte 0 ==
7757 11:10:37.166174 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7758 11:10:37.166289 == TX Byte 1 ==
7759 11:10:37.169329 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7760 11:10:37.172634 DramC Write-DBI off
7761 11:10:37.172724
7762 11:10:37.172831 [DATLAT]
7763 11:10:37.176192 Freq=1600, CH0 RK0
7764 11:10:37.176277
7765 11:10:37.176342 DATLAT Default: 0xf
7766 11:10:37.179554 0, 0xFFFF, sum = 0
7767 11:10:37.179640 1, 0xFFFF, sum = 0
7768 11:10:37.182852 2, 0xFFFF, sum = 0
7769 11:10:37.182938 3, 0xFFFF, sum = 0
7770 11:10:37.186160 4, 0xFFFF, sum = 0
7771 11:10:37.189663 5, 0xFFFF, sum = 0
7772 11:10:37.189765 6, 0xFFFF, sum = 0
7773 11:10:37.192644 7, 0xFFFF, sum = 0
7774 11:10:37.192728 8, 0xFFFF, sum = 0
7775 11:10:37.195789 9, 0xFFFF, sum = 0
7776 11:10:37.195876 10, 0xFFFF, sum = 0
7777 11:10:37.199214 11, 0xFFFF, sum = 0
7778 11:10:37.199304 12, 0xFFFF, sum = 0
7779 11:10:37.202463 13, 0xEFFF, sum = 0
7780 11:10:37.202549 14, 0x0, sum = 1
7781 11:10:37.205804 15, 0x0, sum = 2
7782 11:10:37.205890 16, 0x0, sum = 3
7783 11:10:37.209182 17, 0x0, sum = 4
7784 11:10:37.209255 best_step = 15
7785 11:10:37.209316
7786 11:10:37.209375 ==
7787 11:10:37.212295 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 11:10:37.215678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 11:10:37.219071 ==
7790 11:10:37.219159 RX Vref Scan: 1
7791 11:10:37.219226
7792 11:10:37.222463 Set Vref Range= 24 -> 127
7793 11:10:37.222563
7794 11:10:37.225727 RX Vref 24 -> 127, step: 1
7795 11:10:37.225811
7796 11:10:37.225876 RX Delay 11 -> 252, step: 4
7797 11:10:37.225936
7798 11:10:37.228929 Set Vref, RX VrefLevel [Byte0]: 24
7799 11:10:37.232107 [Byte1]: 24
7800 11:10:37.236084
7801 11:10:37.236183 Set Vref, RX VrefLevel [Byte0]: 25
7802 11:10:37.239381 [Byte1]: 25
7803 11:10:37.243715
7804 11:10:37.243843 Set Vref, RX VrefLevel [Byte0]: 26
7805 11:10:37.247062 [Byte1]: 26
7806 11:10:37.251316
7807 11:10:37.251434 Set Vref, RX VrefLevel [Byte0]: 27
7808 11:10:37.254684 [Byte1]: 27
7809 11:10:37.258850
7810 11:10:37.258942 Set Vref, RX VrefLevel [Byte0]: 28
7811 11:10:37.262056 [Byte1]: 28
7812 11:10:37.266660
7813 11:10:37.266757 Set Vref, RX VrefLevel [Byte0]: 29
7814 11:10:37.269841 [Byte1]: 29
7815 11:10:37.274264
7816 11:10:37.274357 Set Vref, RX VrefLevel [Byte0]: 30
7817 11:10:37.277387 [Byte1]: 30
7818 11:10:37.281687
7819 11:10:37.281809 Set Vref, RX VrefLevel [Byte0]: 31
7820 11:10:37.285152 [Byte1]: 31
7821 11:10:37.289537
7822 11:10:37.289628 Set Vref, RX VrefLevel [Byte0]: 32
7823 11:10:37.292757 [Byte1]: 32
7824 11:10:37.296852
7825 11:10:37.296970 Set Vref, RX VrefLevel [Byte0]: 33
7826 11:10:37.300155 [Byte1]: 33
7827 11:10:37.304506
7828 11:10:37.304599 Set Vref, RX VrefLevel [Byte0]: 34
7829 11:10:37.307956 [Byte1]: 34
7830 11:10:37.312236
7831 11:10:37.312327 Set Vref, RX VrefLevel [Byte0]: 35
7832 11:10:37.315647 [Byte1]: 35
7833 11:10:37.319892
7834 11:10:37.319984 Set Vref, RX VrefLevel [Byte0]: 36
7835 11:10:37.323244 [Byte1]: 36
7836 11:10:37.327517
7837 11:10:37.327632 Set Vref, RX VrefLevel [Byte0]: 37
7838 11:10:37.330530 [Byte1]: 37
7839 11:10:37.334791
7840 11:10:37.334878 Set Vref, RX VrefLevel [Byte0]: 38
7841 11:10:37.338370 [Byte1]: 38
7842 11:10:37.342515
7843 11:10:37.342604 Set Vref, RX VrefLevel [Byte0]: 39
7844 11:10:37.345700 [Byte1]: 39
7845 11:10:37.350134
7846 11:10:37.350231 Set Vref, RX VrefLevel [Byte0]: 40
7847 11:10:37.353459 [Byte1]: 40
7848 11:10:37.357749
7849 11:10:37.357841 Set Vref, RX VrefLevel [Byte0]: 41
7850 11:10:37.360994 [Byte1]: 41
7851 11:10:37.365407
7852 11:10:37.365599 Set Vref, RX VrefLevel [Byte0]: 42
7853 11:10:37.368791 [Byte1]: 42
7854 11:10:37.373020
7855 11:10:37.373102 Set Vref, RX VrefLevel [Byte0]: 43
7856 11:10:37.376527 [Byte1]: 43
7857 11:10:37.380558
7858 11:10:37.380656 Set Vref, RX VrefLevel [Byte0]: 44
7859 11:10:37.384145 [Byte1]: 44
7860 11:10:37.388339
7861 11:10:37.388440 Set Vref, RX VrefLevel [Byte0]: 45
7862 11:10:37.391359 [Byte1]: 45
7863 11:10:37.396041
7864 11:10:37.396131 Set Vref, RX VrefLevel [Byte0]: 46
7865 11:10:37.399084 [Byte1]: 46
7866 11:10:37.403357
7867 11:10:37.403448 Set Vref, RX VrefLevel [Byte0]: 47
7868 11:10:37.406961 [Byte1]: 47
7869 11:10:37.411156
7870 11:10:37.411251 Set Vref, RX VrefLevel [Byte0]: 48
7871 11:10:37.414532 [Byte1]: 48
7872 11:10:37.418723
7873 11:10:37.418819 Set Vref, RX VrefLevel [Byte0]: 49
7874 11:10:37.422198 [Byte1]: 49
7875 11:10:37.426409
7876 11:10:37.426499 Set Vref, RX VrefLevel [Byte0]: 50
7877 11:10:37.429901 [Byte1]: 50
7878 11:10:37.433938
7879 11:10:37.434030 Set Vref, RX VrefLevel [Byte0]: 51
7880 11:10:37.437091 [Byte1]: 51
7881 11:10:37.441444
7882 11:10:37.441583 Set Vref, RX VrefLevel [Byte0]: 52
7883 11:10:37.445038 [Byte1]: 52
7884 11:10:37.449199
7885 11:10:37.449294 Set Vref, RX VrefLevel [Byte0]: 53
7886 11:10:37.452625 [Byte1]: 53
7887 11:10:37.456963
7888 11:10:37.457057 Set Vref, RX VrefLevel [Byte0]: 54
7889 11:10:37.460163 [Byte1]: 54
7890 11:10:37.464356
7891 11:10:37.464449 Set Vref, RX VrefLevel [Byte0]: 55
7892 11:10:37.468082 [Byte1]: 55
7893 11:10:37.471999
7894 11:10:37.472120 Set Vref, RX VrefLevel [Byte0]: 56
7895 11:10:37.475361 [Byte1]: 56
7896 11:10:37.479810
7897 11:10:37.479899 Set Vref, RX VrefLevel [Byte0]: 57
7898 11:10:37.483138 [Byte1]: 57
7899 11:10:37.487206
7900 11:10:37.487297 Set Vref, RX VrefLevel [Byte0]: 58
7901 11:10:37.490522 [Byte1]: 58
7902 11:10:37.494800
7903 11:10:37.494890 Set Vref, RX VrefLevel [Byte0]: 59
7904 11:10:37.498235 [Byte1]: 59
7905 11:10:37.502795
7906 11:10:37.502889 Set Vref, RX VrefLevel [Byte0]: 60
7907 11:10:37.505748 [Byte1]: 60
7908 11:10:37.510248
7909 11:10:37.510366 Set Vref, RX VrefLevel [Byte0]: 61
7910 11:10:37.513418 [Byte1]: 61
7911 11:10:37.517889
7912 11:10:37.517978 Set Vref, RX VrefLevel [Byte0]: 62
7913 11:10:37.520869 [Byte1]: 62
7914 11:10:37.525433
7915 11:10:37.525564 Set Vref, RX VrefLevel [Byte0]: 63
7916 11:10:37.528662 [Byte1]: 63
7917 11:10:37.532834
7918 11:10:37.532920 Set Vref, RX VrefLevel [Byte0]: 64
7919 11:10:37.536328 [Byte1]: 64
7920 11:10:37.540361
7921 11:10:37.540485 Set Vref, RX VrefLevel [Byte0]: 65
7922 11:10:37.544006 [Byte1]: 65
7923 11:10:37.548114
7924 11:10:37.548203 Set Vref, RX VrefLevel [Byte0]: 66
7925 11:10:37.551468 [Byte1]: 66
7926 11:10:37.555708
7927 11:10:37.555886 Set Vref, RX VrefLevel [Byte0]: 67
7928 11:10:37.558993 [Byte1]: 67
7929 11:10:37.563438
7930 11:10:37.563539 Set Vref, RX VrefLevel [Byte0]: 68
7931 11:10:37.566659 [Byte1]: 68
7932 11:10:37.571103
7933 11:10:37.571237 Set Vref, RX VrefLevel [Byte0]: 69
7934 11:10:37.574322 [Byte1]: 69
7935 11:10:37.578569
7936 11:10:37.578656 Set Vref, RX VrefLevel [Byte0]: 70
7937 11:10:37.581904 [Byte1]: 70
7938 11:10:37.586065
7939 11:10:37.586175 Set Vref, RX VrefLevel [Byte0]: 71
7940 11:10:37.589368 [Byte1]: 71
7941 11:10:37.593793
7942 11:10:37.593879 Set Vref, RX VrefLevel [Byte0]: 72
7943 11:10:37.597128 [Byte1]: 72
7944 11:10:37.601408
7945 11:10:37.601564 Set Vref, RX VrefLevel [Byte0]: 73
7946 11:10:37.604662 [Byte1]: 73
7947 11:10:37.609089
7948 11:10:37.609178 Set Vref, RX VrefLevel [Byte0]: 74
7949 11:10:37.612439 [Byte1]: 74
7950 11:10:37.616431
7951 11:10:37.616553 Set Vref, RX VrefLevel [Byte0]: 75
7952 11:10:37.619777 [Byte1]: 75
7953 11:10:37.624274
7954 11:10:37.624369 Set Vref, RX VrefLevel [Byte0]: 76
7955 11:10:37.627721 [Byte1]: 76
7956 11:10:37.632137
7957 11:10:37.632228 Set Vref, RX VrefLevel [Byte0]: 77
7958 11:10:37.635243 [Byte1]: 77
7959 11:10:37.639553
7960 11:10:37.639682 Set Vref, RX VrefLevel [Byte0]: 78
7961 11:10:37.642930 [Byte1]: 78
7962 11:10:37.647162
7963 11:10:37.647304 Final RX Vref Byte 0 = 64 to rank0
7964 11:10:37.650263 Final RX Vref Byte 1 = 59 to rank0
7965 11:10:37.653884 Final RX Vref Byte 0 = 64 to rank1
7966 11:10:37.657145 Final RX Vref Byte 1 = 59 to rank1==
7967 11:10:37.660362 Dram Type= 6, Freq= 0, CH_0, rank 0
7968 11:10:37.667243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7969 11:10:37.667402 ==
7970 11:10:37.667507 DQS Delay:
7971 11:10:37.667598 DQS0 = 0, DQS1 = 0
7972 11:10:37.670319 DQM Delay:
7973 11:10:37.670438 DQM0 = 126, DQM1 = 119
7974 11:10:37.673837 DQ Delay:
7975 11:10:37.676947 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7976 11:10:37.680475 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7977 11:10:37.683598 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7978 11:10:37.687082 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7979 11:10:37.687174
7980 11:10:37.687239
7981 11:10:37.687298
7982 11:10:37.690434 [DramC_TX_OE_Calibration] TA2
7983 11:10:37.693832 Original DQ_B0 (3 6) =30, OEN = 27
7984 11:10:37.697284 Original DQ_B1 (3 6) =30, OEN = 27
7985 11:10:37.700590 24, 0x0, End_B0=24 End_B1=24
7986 11:10:37.700678 25, 0x0, End_B0=25 End_B1=25
7987 11:10:37.703831 26, 0x0, End_B0=26 End_B1=26
7988 11:10:37.707203 27, 0x0, End_B0=27 End_B1=27
7989 11:10:37.710165 28, 0x0, End_B0=28 End_B1=28
7990 11:10:37.710254 29, 0x0, End_B0=29 End_B1=29
7991 11:10:37.713443 30, 0x0, End_B0=30 End_B1=30
7992 11:10:37.716933 31, 0x5151, End_B0=30 End_B1=30
7993 11:10:37.720388 Byte0 end_step=30 best_step=27
7994 11:10:37.723756 Byte1 end_step=30 best_step=27
7995 11:10:37.726938 Byte0 TX OE(2T, 0.5T) = (3, 3)
7996 11:10:37.729993 Byte1 TX OE(2T, 0.5T) = (3, 3)
7997 11:10:37.730117
7998 11:10:37.730212
7999 11:10:37.736718 [DQSOSCAuto] RK0, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8000 11:10:37.740233 CH0 RK0: MR19=303, MR18=1312
8001 11:10:37.746919 CH0_RK0: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
8002 11:10:37.747035
8003 11:10:37.750044 ----->DramcWriteLeveling(PI) begin...
8004 11:10:37.750157 ==
8005 11:10:37.753149 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 11:10:37.756498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 11:10:37.756615 ==
8008 11:10:37.759862 Write leveling (Byte 0): 36 => 36
8009 11:10:37.763020 Write leveling (Byte 1): 27 => 27
8010 11:10:37.766648 DramcWriteLeveling(PI) end<-----
8011 11:10:37.766782
8012 11:10:37.766887 ==
8013 11:10:37.769517 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 11:10:37.772900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 11:10:37.773069 ==
8016 11:10:37.776408 [Gating] SW mode calibration
8017 11:10:37.783017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8018 11:10:37.789366 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8019 11:10:37.793131 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 11:10:37.799490 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 11:10:37.803004 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 11:10:37.806241 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8023 11:10:37.812688 1 4 16 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8024 11:10:37.815878 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8025 11:10:37.819230 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 11:10:37.826054 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 11:10:37.829071 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 11:10:37.832433 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 11:10:37.839246 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8030 11:10:37.842554 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8031 11:10:37.845492 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8032 11:10:37.852378 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
8033 11:10:37.855580 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 11:10:37.858960 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 11:10:37.862449 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 11:10:37.868933 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 11:10:37.872282 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8038 11:10:37.875383 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8039 11:10:37.882344 1 6 16 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
8040 11:10:37.885337 1 6 20 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
8041 11:10:37.888820 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 11:10:37.895454 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 11:10:37.898635 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 11:10:37.902136 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 11:10:37.908773 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8046 11:10:37.912072 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 11:10:37.915137 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8048 11:10:37.921771 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8049 11:10:37.925161 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 11:10:37.928134 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 11:10:37.934842 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 11:10:37.938251 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 11:10:37.941627 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 11:10:37.948336 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 11:10:37.951533 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 11:10:37.954797 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 11:10:37.961337 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 11:10:37.965094 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 11:10:37.968096 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 11:10:37.974754 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 11:10:37.978062 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 11:10:37.981352 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8063 11:10:37.984619 Total UI for P1: 0, mck2ui 16
8064 11:10:37.988358 best dqsien dly found for B0: ( 1, 9, 8)
8065 11:10:37.994727 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8066 11:10:37.997821 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8067 11:10:38.001385 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 11:10:38.004339 Total UI for P1: 0, mck2ui 16
8069 11:10:38.007817 best dqsien dly found for B1: ( 1, 9, 18)
8070 11:10:38.010991 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8071 11:10:38.014404 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8072 11:10:38.014512
8073 11:10:38.021084 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8074 11:10:38.024741 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8075 11:10:38.024835 [Gating] SW calibration Done
8076 11:10:38.027757 ==
8077 11:10:38.030966 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 11:10:38.034190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 11:10:38.034285 ==
8080 11:10:38.034351 RX Vref Scan: 0
8081 11:10:38.034412
8082 11:10:38.037406 RX Vref 0 -> 0, step: 1
8083 11:10:38.037518
8084 11:10:38.040737 RX Delay 0 -> 252, step: 8
8085 11:10:38.044247 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8086 11:10:38.047744 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8087 11:10:38.050995 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8088 11:10:38.057448 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8089 11:10:38.060670 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8090 11:10:38.064318 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8091 11:10:38.067584 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8092 11:10:38.070569 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8093 11:10:38.077172 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8094 11:10:38.080590 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8095 11:10:38.083849 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8096 11:10:38.087100 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8097 11:10:38.093680 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8098 11:10:38.097329 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8099 11:10:38.100515 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8100 11:10:38.103618 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8101 11:10:38.103706 ==
8102 11:10:38.107128 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 11:10:38.113567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 11:10:38.113663 ==
8105 11:10:38.113729 DQS Delay:
8106 11:10:38.117066 DQS0 = 0, DQS1 = 0
8107 11:10:38.117151 DQM Delay:
8108 11:10:38.117216 DQM0 = 127, DQM1 = 121
8109 11:10:38.120095 DQ Delay:
8110 11:10:38.123599 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8111 11:10:38.127071 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8112 11:10:38.130053 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8113 11:10:38.133781 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8114 11:10:38.133870
8115 11:10:38.133943
8116 11:10:38.134004 ==
8117 11:10:38.136917 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 11:10:38.139884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 11:10:38.143620 ==
8120 11:10:38.143706
8121 11:10:38.143771
8122 11:10:38.143830 TX Vref Scan disable
8123 11:10:38.146727 == TX Byte 0 ==
8124 11:10:38.149697 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8125 11:10:38.153248 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8126 11:10:38.156629 == TX Byte 1 ==
8127 11:10:38.159845 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8128 11:10:38.163332 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8129 11:10:38.166584 ==
8130 11:10:38.169545 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 11:10:38.173014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 11:10:38.173128 ==
8133 11:10:38.187627
8134 11:10:38.191039 TX Vref early break, caculate TX vref
8135 11:10:38.194262 TX Vref=16, minBit 8, minWin=22, winSum=374
8136 11:10:38.197655 TX Vref=18, minBit 8, minWin=22, winSum=381
8137 11:10:38.200716 TX Vref=20, minBit 8, minWin=22, winSum=384
8138 11:10:38.203991 TX Vref=22, minBit 8, minWin=23, winSum=395
8139 11:10:38.207428 TX Vref=24, minBit 8, minWin=23, winSum=403
8140 11:10:38.214060 TX Vref=26, minBit 8, minWin=24, winSum=412
8141 11:10:38.217509 TX Vref=28, minBit 8, minWin=24, winSum=410
8142 11:10:38.220531 TX Vref=30, minBit 8, minWin=23, winSum=408
8143 11:10:38.224383 TX Vref=32, minBit 8, minWin=23, winSum=401
8144 11:10:38.227187 TX Vref=34, minBit 8, minWin=22, winSum=392
8145 11:10:38.230722 TX Vref=36, minBit 8, minWin=22, winSum=383
8146 11:10:38.237147 [TxChooseVref] Worse bit 8, Min win 24, Win sum 412, Final Vref 26
8147 11:10:38.237244
8148 11:10:38.240588 Final TX Range 0 Vref 26
8149 11:10:38.240669
8150 11:10:38.240731 ==
8151 11:10:38.244048 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 11:10:38.247010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 11:10:38.247099 ==
8154 11:10:38.247165
8155 11:10:38.250405
8156 11:10:38.250489 TX Vref Scan disable
8157 11:10:38.257291 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8158 11:10:38.257406 == TX Byte 0 ==
8159 11:10:38.260414 u2DelayCellOfst[0]=11 cells (3 PI)
8160 11:10:38.263481 u2DelayCellOfst[1]=15 cells (4 PI)
8161 11:10:38.267327 u2DelayCellOfst[2]=11 cells (3 PI)
8162 11:10:38.270472 u2DelayCellOfst[3]=11 cells (3 PI)
8163 11:10:38.273708 u2DelayCellOfst[4]=7 cells (2 PI)
8164 11:10:38.276991 u2DelayCellOfst[5]=0 cells (0 PI)
8165 11:10:38.280105 u2DelayCellOfst[6]=18 cells (5 PI)
8166 11:10:38.283230 u2DelayCellOfst[7]=18 cells (5 PI)
8167 11:10:38.286748 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8168 11:10:38.290249 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8169 11:10:38.293326 == TX Byte 1 ==
8170 11:10:38.296724 u2DelayCellOfst[8]=0 cells (0 PI)
8171 11:10:38.300055 u2DelayCellOfst[9]=0 cells (0 PI)
8172 11:10:38.303409 u2DelayCellOfst[10]=7 cells (2 PI)
8173 11:10:38.306523 u2DelayCellOfst[11]=3 cells (1 PI)
8174 11:10:38.306639 u2DelayCellOfst[12]=15 cells (4 PI)
8175 11:10:38.310118 u2DelayCellOfst[13]=15 cells (4 PI)
8176 11:10:38.313466 u2DelayCellOfst[14]=18 cells (5 PI)
8177 11:10:38.316821 u2DelayCellOfst[15]=11 cells (3 PI)
8178 11:10:38.323243 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8179 11:10:38.326564 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8180 11:10:38.326665 DramC Write-DBI on
8181 11:10:38.330085 ==
8182 11:10:38.330172 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 11:10:38.336678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 11:10:38.336778 ==
8185 11:10:38.336845
8186 11:10:38.336907
8187 11:10:38.339848 TX Vref Scan disable
8188 11:10:38.339920 == TX Byte 0 ==
8189 11:10:38.346733 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8190 11:10:38.346840 == TX Byte 1 ==
8191 11:10:38.349596 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8192 11:10:38.353040 DramC Write-DBI off
8193 11:10:38.353154
8194 11:10:38.353247 [DATLAT]
8195 11:10:38.356163 Freq=1600, CH0 RK1
8196 11:10:38.356248
8197 11:10:38.356313 DATLAT Default: 0xf
8198 11:10:38.359428 0, 0xFFFF, sum = 0
8199 11:10:38.359538 1, 0xFFFF, sum = 0
8200 11:10:38.362835 2, 0xFFFF, sum = 0
8201 11:10:38.362955 3, 0xFFFF, sum = 0
8202 11:10:38.366116 4, 0xFFFF, sum = 0
8203 11:10:38.369450 5, 0xFFFF, sum = 0
8204 11:10:38.369583 6, 0xFFFF, sum = 0
8205 11:10:38.372857 7, 0xFFFF, sum = 0
8206 11:10:38.372974 8, 0xFFFF, sum = 0
8207 11:10:38.375983 9, 0xFFFF, sum = 0
8208 11:10:38.376073 10, 0xFFFF, sum = 0
8209 11:10:38.379564 11, 0xFFFF, sum = 0
8210 11:10:38.379653 12, 0xFFFF, sum = 0
8211 11:10:38.382570 13, 0xCFFF, sum = 0
8212 11:10:38.382657 14, 0x0, sum = 1
8213 11:10:38.386146 15, 0x0, sum = 2
8214 11:10:38.386235 16, 0x0, sum = 3
8215 11:10:38.389306 17, 0x0, sum = 4
8216 11:10:38.389390 best_step = 15
8217 11:10:38.389455
8218 11:10:38.389563 ==
8219 11:10:38.392522 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 11:10:38.396102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 11:10:38.399282 ==
8222 11:10:38.399395 RX Vref Scan: 0
8223 11:10:38.399489
8224 11:10:38.402399 RX Vref 0 -> 0, step: 1
8225 11:10:38.402487
8226 11:10:38.402556 RX Delay 3 -> 252, step: 4
8227 11:10:38.409854 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8228 11:10:38.413195 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8229 11:10:38.416416 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8230 11:10:38.419714 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8231 11:10:38.423033 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8232 11:10:38.429741 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8233 11:10:38.433291 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8234 11:10:38.436502 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8235 11:10:38.439434 iDelay=191, Bit 8, Center 108 (51 ~ 166) 116
8236 11:10:38.443037 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8237 11:10:38.449464 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8238 11:10:38.452643 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8239 11:10:38.456078 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8240 11:10:38.459176 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8241 11:10:38.466032 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8242 11:10:38.469152 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8243 11:10:38.469242 ==
8244 11:10:38.472492 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 11:10:38.475799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 11:10:38.475889 ==
8247 11:10:38.479221 DQS Delay:
8248 11:10:38.479306 DQS0 = 0, DQS1 = 0
8249 11:10:38.479371 DQM Delay:
8250 11:10:38.482607 DQM0 = 124, DQM1 = 117
8251 11:10:38.482693 DQ Delay:
8252 11:10:38.486059 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8253 11:10:38.489225 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8254 11:10:38.495901 DQ8 =108, DQ9 =104, DQ10 =118, DQ11 =112
8255 11:10:38.499097 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8256 11:10:38.499194
8257 11:10:38.499288
8258 11:10:38.499347
8259 11:10:38.502527 [DramC_TX_OE_Calibration] TA2
8260 11:10:38.505613 Original DQ_B0 (3 6) =30, OEN = 27
8261 11:10:38.509037 Original DQ_B1 (3 6) =30, OEN = 27
8262 11:10:38.509124 24, 0x0, End_B0=24 End_B1=24
8263 11:10:38.512385 25, 0x0, End_B0=25 End_B1=25
8264 11:10:38.515737 26, 0x0, End_B0=26 End_B1=26
8265 11:10:38.518908 27, 0x0, End_B0=27 End_B1=27
8266 11:10:38.518997 28, 0x0, End_B0=28 End_B1=28
8267 11:10:38.522472 29, 0x0, End_B0=29 End_B1=29
8268 11:10:38.525810 30, 0x0, End_B0=30 End_B1=30
8269 11:10:38.528859 31, 0x5151, End_B0=30 End_B1=30
8270 11:10:38.532501 Byte0 end_step=30 best_step=27
8271 11:10:38.535630 Byte1 end_step=30 best_step=27
8272 11:10:38.535720 Byte0 TX OE(2T, 0.5T) = (3, 3)
8273 11:10:38.538918 Byte1 TX OE(2T, 0.5T) = (3, 3)
8274 11:10:38.539002
8275 11:10:38.539067
8276 11:10:38.548824 [DQSOSCAuto] RK1, (LSB)MR18= 0x2210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8277 11:10:38.552174 CH0 RK1: MR19=303, MR18=2210
8278 11:10:38.555386 CH0_RK1: MR19=0x303, MR18=0x2210, DQSOSC=392, MR23=63, INC=24, DEC=16
8279 11:10:38.558735 [RxdqsGatingPostProcess] freq 1600
8280 11:10:38.565244 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8281 11:10:38.568847 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 11:10:38.571902 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 11:10:38.575343 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 11:10:38.578580 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 11:10:38.581689 best DQS0 dly(2T, 0.5T) = (1, 1)
8286 11:10:38.581805 best DQS1 dly(2T, 0.5T) = (1, 1)
8287 11:10:38.585123 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8288 11:10:38.588342 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8289 11:10:38.592038 Pre-setting of DQS Precalculation
8290 11:10:38.598449 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8291 11:10:38.598561 ==
8292 11:10:38.601535 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 11:10:38.604864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 11:10:38.604961 ==
8295 11:10:38.611619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 11:10:38.614837 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 11:10:38.618087 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 11:10:38.624588 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 11:10:38.634048 [CA 0] Center 42 (13~71) winsize 59
8300 11:10:38.637283 [CA 1] Center 42 (12~72) winsize 61
8301 11:10:38.640835 [CA 2] Center 38 (9~67) winsize 59
8302 11:10:38.644138 [CA 3] Center 37 (8~66) winsize 59
8303 11:10:38.647694 [CA 4] Center 37 (8~67) winsize 60
8304 11:10:38.650979 [CA 5] Center 36 (7~66) winsize 60
8305 11:10:38.651094
8306 11:10:38.654103 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8307 11:10:38.654188
8308 11:10:38.657613 [CATrainingPosCal] consider 1 rank data
8309 11:10:38.661131 u2DelayCellTimex100 = 258/100 ps
8310 11:10:38.664189 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8311 11:10:38.670902 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8312 11:10:38.673983 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8313 11:10:38.677444 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8314 11:10:38.680396 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8315 11:10:38.683941 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8316 11:10:38.684035
8317 11:10:38.687055 CA PerBit enable=1, Macro0, CA PI delay=36
8318 11:10:38.687140
8319 11:10:38.690480 [CBTSetCACLKResult] CA Dly = 36
8320 11:10:38.694113 CS Dly: 9 (0~40)
8321 11:10:38.697092 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 11:10:38.700459 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 11:10:38.700552 ==
8324 11:10:38.703827 Dram Type= 6, Freq= 0, CH_1, rank 1
8325 11:10:38.707315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 11:10:38.710262 ==
8327 11:10:38.713650 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 11:10:38.717110 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 11:10:38.723591 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 11:10:38.730155 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 11:10:38.737145 [CA 0] Center 42 (13~72) winsize 60
8332 11:10:38.740357 [CA 1] Center 42 (12~72) winsize 61
8333 11:10:38.743750 [CA 2] Center 38 (9~67) winsize 59
8334 11:10:38.747185 [CA 3] Center 36 (7~66) winsize 60
8335 11:10:38.750580 [CA 4] Center 37 (8~67) winsize 60
8336 11:10:38.753832 [CA 5] Center 36 (6~67) winsize 62
8337 11:10:38.753929
8338 11:10:38.756859 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8339 11:10:38.756977
8340 11:10:38.760251 [CATrainingPosCal] consider 2 rank data
8341 11:10:38.763754 u2DelayCellTimex100 = 258/100 ps
8342 11:10:38.770350 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8343 11:10:38.773807 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8344 11:10:38.777005 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8345 11:10:38.780554 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8346 11:10:38.783722 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8347 11:10:38.786822 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8348 11:10:38.786923
8349 11:10:38.789993 CA PerBit enable=1, Macro0, CA PI delay=36
8350 11:10:38.790106
8351 11:10:38.793420 [CBTSetCACLKResult] CA Dly = 36
8352 11:10:38.796927 CS Dly: 10 (0~43)
8353 11:10:38.800284 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 11:10:38.803380 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 11:10:38.803472
8356 11:10:38.806701 ----->DramcWriteLeveling(PI) begin...
8357 11:10:38.806806 ==
8358 11:10:38.810150 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 11:10:38.816618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 11:10:38.816723 ==
8361 11:10:38.820032 Write leveling (Byte 0): 23 => 23
8362 11:10:38.823247 Write leveling (Byte 1): 28 => 28
8363 11:10:38.823338 DramcWriteLeveling(PI) end<-----
8364 11:10:38.823403
8365 11:10:38.826733 ==
8366 11:10:38.829818 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 11:10:38.833275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 11:10:38.833412 ==
8369 11:10:38.836531 [Gating] SW mode calibration
8370 11:10:38.843328 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8371 11:10:38.846680 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8372 11:10:38.853170 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 11:10:38.856456 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 11:10:38.859640 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 11:10:38.866493 1 4 12 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8376 11:10:38.869817 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8377 11:10:38.873233 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 11:10:38.879677 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 11:10:38.883174 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 11:10:38.886150 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 11:10:38.892766 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 11:10:38.896066 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 11:10:38.899321 1 5 12 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 1)
8384 11:10:38.906129 1 5 16 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 0)
8385 11:10:38.909408 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 11:10:38.912838 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 11:10:38.919353 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 11:10:38.922756 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 11:10:38.926162 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 11:10:38.932791 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 11:10:38.935948 1 6 12 | B1->B0 | 2c2c 2626 | 0 0 | (0 0) (0 0)
8392 11:10:38.939268 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8393 11:10:38.946104 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 11:10:38.949092 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 11:10:38.952624 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 11:10:38.959245 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 11:10:38.962360 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 11:10:38.965709 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 11:10:38.969037 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 11:10:38.975819 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8401 11:10:38.979160 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8402 11:10:38.982222 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 11:10:38.989148 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 11:10:38.992513 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 11:10:38.995504 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 11:10:39.002148 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 11:10:39.005578 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 11:10:39.008645 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 11:10:39.015240 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 11:10:39.018569 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 11:10:39.022286 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 11:10:39.028496 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 11:10:39.031795 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 11:10:39.035398 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 11:10:39.042186 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 11:10:39.045346 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8417 11:10:39.048545 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 11:10:39.051920 Total UI for P1: 0, mck2ui 16
8419 11:10:39.055147 best dqsien dly found for B0: ( 1, 9, 16)
8420 11:10:39.058651 Total UI for P1: 0, mck2ui 16
8421 11:10:39.061746 best dqsien dly found for B1: ( 1, 9, 16)
8422 11:10:39.065088 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8423 11:10:39.068247 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8424 11:10:39.068343
8425 11:10:39.075102 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8426 11:10:39.078377 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8427 11:10:39.081405 [Gating] SW calibration Done
8428 11:10:39.081536 ==
8429 11:10:39.084777 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 11:10:39.088231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 11:10:39.088335 ==
8432 11:10:39.088416 RX Vref Scan: 0
8433 11:10:39.091581
8434 11:10:39.091664 RX Vref 0 -> 0, step: 1
8435 11:10:39.091749
8436 11:10:39.094669 RX Delay 0 -> 252, step: 8
8437 11:10:39.098107 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8438 11:10:39.101436 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8439 11:10:39.107787 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8440 11:10:39.111206 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8441 11:10:39.114791 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8442 11:10:39.118031 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8443 11:10:39.121117 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8444 11:10:39.127823 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8445 11:10:39.131348 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8446 11:10:39.134589 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8447 11:10:39.138137 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8448 11:10:39.141229 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8449 11:10:39.147589 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8450 11:10:39.150869 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8451 11:10:39.154354 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8452 11:10:39.157637 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8453 11:10:39.157744 ==
8454 11:10:39.160837 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 11:10:39.167575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 11:10:39.167693 ==
8457 11:10:39.167762 DQS Delay:
8458 11:10:39.170805 DQS0 = 0, DQS1 = 0
8459 11:10:39.170889 DQM Delay:
8460 11:10:39.170954 DQM0 = 132, DQM1 = 126
8461 11:10:39.174212 DQ Delay:
8462 11:10:39.177407 DQ0 =135, DQ1 =127, DQ2 =123, DQ3 =131
8463 11:10:39.180833 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8464 11:10:39.184186 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8465 11:10:39.187493 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8466 11:10:39.187573
8467 11:10:39.187640
8468 11:10:39.187699 ==
8469 11:10:39.190825 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 11:10:39.197404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 11:10:39.197528 ==
8472 11:10:39.197594
8473 11:10:39.197657
8474 11:10:39.197718 TX Vref Scan disable
8475 11:10:39.200420 == TX Byte 0 ==
8476 11:10:39.203800 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8477 11:10:39.207312 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8478 11:10:39.210459 == TX Byte 1 ==
8479 11:10:39.214188 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8480 11:10:39.217055 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8481 11:10:39.220546 ==
8482 11:10:39.223986 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 11:10:39.227050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 11:10:39.227159 ==
8485 11:10:39.239553
8486 11:10:39.242981 TX Vref early break, caculate TX vref
8487 11:10:39.246330 TX Vref=16, minBit 10, minWin=21, winSum=359
8488 11:10:39.249299 TX Vref=18, minBit 5, minWin=22, winSum=370
8489 11:10:39.252764 TX Vref=20, minBit 1, minWin=23, winSum=381
8490 11:10:39.255949 TX Vref=22, minBit 5, minWin=23, winSum=388
8491 11:10:39.259552 TX Vref=24, minBit 1, minWin=24, winSum=399
8492 11:10:39.265967 TX Vref=26, minBit 0, minWin=24, winSum=409
8493 11:10:39.269255 TX Vref=28, minBit 0, minWin=25, winSum=418
8494 11:10:39.272807 TX Vref=30, minBit 0, minWin=24, winSum=411
8495 11:10:39.276039 TX Vref=32, minBit 0, minWin=24, winSum=400
8496 11:10:39.279377 TX Vref=34, minBit 0, minWin=23, winSum=392
8497 11:10:39.286042 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8498 11:10:39.286154
8499 11:10:39.289262 Final TX Range 0 Vref 28
8500 11:10:39.289371
8501 11:10:39.289460 ==
8502 11:10:39.292607 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 11:10:39.296053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 11:10:39.296133 ==
8505 11:10:39.296195
8506 11:10:39.296253
8507 11:10:39.299465 TX Vref Scan disable
8508 11:10:39.306051 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8509 11:10:39.306143 == TX Byte 0 ==
8510 11:10:39.309522 u2DelayCellOfst[0]=18 cells (5 PI)
8511 11:10:39.312531 u2DelayCellOfst[1]=11 cells (3 PI)
8512 11:10:39.315826 u2DelayCellOfst[2]=0 cells (0 PI)
8513 11:10:39.319131 u2DelayCellOfst[3]=3 cells (1 PI)
8514 11:10:39.322663 u2DelayCellOfst[4]=7 cells (2 PI)
8515 11:10:39.325636 u2DelayCellOfst[5]=22 cells (6 PI)
8516 11:10:39.328963 u2DelayCellOfst[6]=18 cells (5 PI)
8517 11:10:39.329079 u2DelayCellOfst[7]=7 cells (2 PI)
8518 11:10:39.335768 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8519 11:10:39.339144 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8520 11:10:39.339232 == TX Byte 1 ==
8521 11:10:39.342303 u2DelayCellOfst[8]=0 cells (0 PI)
8522 11:10:39.345698 u2DelayCellOfst[9]=3 cells (1 PI)
8523 11:10:39.349050 u2DelayCellOfst[10]=11 cells (3 PI)
8524 11:10:39.352129 u2DelayCellOfst[11]=7 cells (2 PI)
8525 11:10:39.355772 u2DelayCellOfst[12]=15 cells (4 PI)
8526 11:10:39.358804 u2DelayCellOfst[13]=18 cells (5 PI)
8527 11:10:39.362235 u2DelayCellOfst[14]=18 cells (5 PI)
8528 11:10:39.365741 u2DelayCellOfst[15]=18 cells (5 PI)
8529 11:10:39.369049 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8530 11:10:39.375492 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8531 11:10:39.375628 DramC Write-DBI on
8532 11:10:39.375722 ==
8533 11:10:39.378827 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 11:10:39.382147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 11:10:39.385360 ==
8536 11:10:39.385468
8537 11:10:39.385559
8538 11:10:39.385618 TX Vref Scan disable
8539 11:10:39.389040 == TX Byte 0 ==
8540 11:10:39.392120 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8541 11:10:39.395414 == TX Byte 1 ==
8542 11:10:39.398825 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8543 11:10:39.402182 DramC Write-DBI off
8544 11:10:39.402270
8545 11:10:39.402335 [DATLAT]
8546 11:10:39.402396 Freq=1600, CH1 RK0
8547 11:10:39.402454
8548 11:10:39.405375 DATLAT Default: 0xf
8549 11:10:39.408796 0, 0xFFFF, sum = 0
8550 11:10:39.408882 1, 0xFFFF, sum = 0
8551 11:10:39.412317 2, 0xFFFF, sum = 0
8552 11:10:39.412402 3, 0xFFFF, sum = 0
8553 11:10:39.415279 4, 0xFFFF, sum = 0
8554 11:10:39.415364 5, 0xFFFF, sum = 0
8555 11:10:39.418663 6, 0xFFFF, sum = 0
8556 11:10:39.418750 7, 0xFFFF, sum = 0
8557 11:10:39.422060 8, 0xFFFF, sum = 0
8558 11:10:39.422146 9, 0xFFFF, sum = 0
8559 11:10:39.425240 10, 0xFFFF, sum = 0
8560 11:10:39.425347 11, 0xFFFF, sum = 0
8561 11:10:39.428626 12, 0xFFFF, sum = 0
8562 11:10:39.428731 13, 0x8FFF, sum = 0
8563 11:10:39.432002 14, 0x0, sum = 1
8564 11:10:39.432084 15, 0x0, sum = 2
8565 11:10:39.435364 16, 0x0, sum = 3
8566 11:10:39.435443 17, 0x0, sum = 4
8567 11:10:39.438590 best_step = 15
8568 11:10:39.438667
8569 11:10:39.438731 ==
8570 11:10:39.441618 Dram Type= 6, Freq= 0, CH_1, rank 0
8571 11:10:39.445223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8572 11:10:39.445331 ==
8573 11:10:39.448243 RX Vref Scan: 1
8574 11:10:39.448328
8575 11:10:39.448422 Set Vref Range= 24 -> 127
8576 11:10:39.448497
8577 11:10:39.451649 RX Vref 24 -> 127, step: 1
8578 11:10:39.451732
8579 11:10:39.455013 RX Delay 11 -> 252, step: 4
8580 11:10:39.455121
8581 11:10:39.458107 Set Vref, RX VrefLevel [Byte0]: 24
8582 11:10:39.461378 [Byte1]: 24
8583 11:10:39.461468
8584 11:10:39.464855 Set Vref, RX VrefLevel [Byte0]: 25
8585 11:10:39.468158 [Byte1]: 25
8586 11:10:39.471634
8587 11:10:39.471740 Set Vref, RX VrefLevel [Byte0]: 26
8588 11:10:39.475033 [Byte1]: 26
8589 11:10:39.479107
8590 11:10:39.479212 Set Vref, RX VrefLevel [Byte0]: 27
8591 11:10:39.482535 [Byte1]: 27
8592 11:10:39.486723
8593 11:10:39.486827 Set Vref, RX VrefLevel [Byte0]: 28
8594 11:10:39.490037 [Byte1]: 28
8595 11:10:39.494721
8596 11:10:39.494816 Set Vref, RX VrefLevel [Byte0]: 29
8597 11:10:39.497730 [Byte1]: 29
8598 11:10:39.501974
8599 11:10:39.502065 Set Vref, RX VrefLevel [Byte0]: 30
8600 11:10:39.505399 [Byte1]: 30
8601 11:10:39.509521
8602 11:10:39.509612 Set Vref, RX VrefLevel [Byte0]: 31
8603 11:10:39.512961 [Byte1]: 31
8604 11:10:39.517311
8605 11:10:39.517411 Set Vref, RX VrefLevel [Byte0]: 32
8606 11:10:39.520549 [Byte1]: 32
8607 11:10:39.524927
8608 11:10:39.525016 Set Vref, RX VrefLevel [Byte0]: 33
8609 11:10:39.528597 [Byte1]: 33
8610 11:10:39.532542
8611 11:10:39.532633 Set Vref, RX VrefLevel [Byte0]: 34
8612 11:10:39.535725 [Byte1]: 34
8613 11:10:39.540151
8614 11:10:39.540241 Set Vref, RX VrefLevel [Byte0]: 35
8615 11:10:39.543490 [Byte1]: 35
8616 11:10:39.547732
8617 11:10:39.547824 Set Vref, RX VrefLevel [Byte0]: 36
8618 11:10:39.550980 [Byte1]: 36
8619 11:10:39.555457
8620 11:10:39.555549 Set Vref, RX VrefLevel [Byte0]: 37
8621 11:10:39.558705 [Byte1]: 37
8622 11:10:39.563178
8623 11:10:39.563285 Set Vref, RX VrefLevel [Byte0]: 38
8624 11:10:39.566187 [Byte1]: 38
8625 11:10:39.570691
8626 11:10:39.570787 Set Vref, RX VrefLevel [Byte0]: 39
8627 11:10:39.573792 [Byte1]: 39
8628 11:10:39.578401
8629 11:10:39.578497 Set Vref, RX VrefLevel [Byte0]: 40
8630 11:10:39.581413 [Byte1]: 40
8631 11:10:39.585967
8632 11:10:39.586059 Set Vref, RX VrefLevel [Byte0]: 41
8633 11:10:39.588971 [Byte1]: 41
8634 11:10:39.593565
8635 11:10:39.593660 Set Vref, RX VrefLevel [Byte0]: 42
8636 11:10:39.596660 [Byte1]: 42
8637 11:10:39.601052
8638 11:10:39.601157 Set Vref, RX VrefLevel [Byte0]: 43
8639 11:10:39.604345 [Byte1]: 43
8640 11:10:39.608783
8641 11:10:39.608871 Set Vref, RX VrefLevel [Byte0]: 44
8642 11:10:39.612156 [Byte1]: 44
8643 11:10:39.616101
8644 11:10:39.616189 Set Vref, RX VrefLevel [Byte0]: 45
8645 11:10:39.619638 [Byte1]: 45
8646 11:10:39.624038
8647 11:10:39.624128 Set Vref, RX VrefLevel [Byte0]: 46
8648 11:10:39.627351 [Byte1]: 46
8649 11:10:39.631513
8650 11:10:39.631654 Set Vref, RX VrefLevel [Byte0]: 47
8651 11:10:39.634644 [Byte1]: 47
8652 11:10:39.639035
8653 11:10:39.639131 Set Vref, RX VrefLevel [Byte0]: 48
8654 11:10:39.642260 [Byte1]: 48
8655 11:10:39.646782
8656 11:10:39.646877 Set Vref, RX VrefLevel [Byte0]: 49
8657 11:10:39.650054 [Byte1]: 49
8658 11:10:39.654349
8659 11:10:39.654449 Set Vref, RX VrefLevel [Byte0]: 50
8660 11:10:39.657652 [Byte1]: 50
8661 11:10:39.661807
8662 11:10:39.661899 Set Vref, RX VrefLevel [Byte0]: 51
8663 11:10:39.665169 [Byte1]: 51
8664 11:10:39.669736
8665 11:10:39.669830 Set Vref, RX VrefLevel [Byte0]: 52
8666 11:10:39.673024 [Byte1]: 52
8667 11:10:39.677299
8668 11:10:39.677410 Set Vref, RX VrefLevel [Byte0]: 53
8669 11:10:39.680525 [Byte1]: 53
8670 11:10:39.685007
8671 11:10:39.685102 Set Vref, RX VrefLevel [Byte0]: 54
8672 11:10:39.688023 [Byte1]: 54
8673 11:10:39.692586
8674 11:10:39.692685 Set Vref, RX VrefLevel [Byte0]: 55
8675 11:10:39.695698 [Byte1]: 55
8676 11:10:39.699973
8677 11:10:39.700061 Set Vref, RX VrefLevel [Byte0]: 56
8678 11:10:39.703212 [Byte1]: 56
8679 11:10:39.707745
8680 11:10:39.707837 Set Vref, RX VrefLevel [Byte0]: 57
8681 11:10:39.710828 [Byte1]: 57
8682 11:10:39.715351
8683 11:10:39.715443 Set Vref, RX VrefLevel [Byte0]: 58
8684 11:10:39.718394 [Byte1]: 58
8685 11:10:39.722745
8686 11:10:39.722834 Set Vref, RX VrefLevel [Byte0]: 59
8687 11:10:39.726177 [Byte1]: 59
8688 11:10:39.730376
8689 11:10:39.730466 Set Vref, RX VrefLevel [Byte0]: 60
8690 11:10:39.733795 [Byte1]: 60
8691 11:10:39.738042
8692 11:10:39.738151 Set Vref, RX VrefLevel [Byte0]: 61
8693 11:10:39.741431 [Byte1]: 61
8694 11:10:39.745626
8695 11:10:39.745721 Set Vref, RX VrefLevel [Byte0]: 62
8696 11:10:39.749271 [Byte1]: 62
8697 11:10:39.753294
8698 11:10:39.753384 Set Vref, RX VrefLevel [Byte0]: 63
8699 11:10:39.756643 [Byte1]: 63
8700 11:10:39.760735
8701 11:10:39.760849 Set Vref, RX VrefLevel [Byte0]: 64
8702 11:10:39.764232 [Byte1]: 64
8703 11:10:39.768542
8704 11:10:39.768668 Set Vref, RX VrefLevel [Byte0]: 65
8705 11:10:39.771947 [Byte1]: 65
8706 11:10:39.776043
8707 11:10:39.776155 Set Vref, RX VrefLevel [Byte0]: 66
8708 11:10:39.779327 [Byte1]: 66
8709 11:10:39.783928
8710 11:10:39.784036 Set Vref, RX VrefLevel [Byte0]: 67
8711 11:10:39.787021 [Byte1]: 67
8712 11:10:39.791496
8713 11:10:39.791612 Set Vref, RX VrefLevel [Byte0]: 68
8714 11:10:39.794836 [Byte1]: 68
8715 11:10:39.798979
8716 11:10:39.799085 Set Vref, RX VrefLevel [Byte0]: 69
8717 11:10:39.802402 [Byte1]: 69
8718 11:10:39.806562
8719 11:10:39.806644 Set Vref, RX VrefLevel [Byte0]: 70
8720 11:10:39.810008 [Byte1]: 70
8721 11:10:39.814200
8722 11:10:39.814289 Set Vref, RX VrefLevel [Byte0]: 71
8723 11:10:39.817396 [Byte1]: 71
8724 11:10:39.821843
8725 11:10:39.821970 Final RX Vref Byte 0 = 60 to rank0
8726 11:10:39.825351 Final RX Vref Byte 1 = 54 to rank0
8727 11:10:39.828289 Final RX Vref Byte 0 = 60 to rank1
8728 11:10:39.831779 Final RX Vref Byte 1 = 54 to rank1==
8729 11:10:39.834850 Dram Type= 6, Freq= 0, CH_1, rank 0
8730 11:10:39.841894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8731 11:10:39.842032 ==
8732 11:10:39.842130 DQS Delay:
8733 11:10:39.844758 DQS0 = 0, DQS1 = 0
8734 11:10:39.844854 DQM Delay:
8735 11:10:39.844942 DQM0 = 131, DQM1 = 123
8736 11:10:39.848207 DQ Delay:
8737 11:10:39.851676 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8738 11:10:39.854827 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8739 11:10:39.858089 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8740 11:10:39.861279 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =132
8741 11:10:39.861388
8742 11:10:39.861502
8743 11:10:39.861608
8744 11:10:39.864853 [DramC_TX_OE_Calibration] TA2
8745 11:10:39.868077 Original DQ_B0 (3 6) =30, OEN = 27
8746 11:10:39.871101 Original DQ_B1 (3 6) =30, OEN = 27
8747 11:10:39.874475 24, 0x0, End_B0=24 End_B1=24
8748 11:10:39.874588 25, 0x0, End_B0=25 End_B1=25
8749 11:10:39.877822 26, 0x0, End_B0=26 End_B1=26
8750 11:10:39.881246 27, 0x0, End_B0=27 End_B1=27
8751 11:10:39.884370 28, 0x0, End_B0=28 End_B1=28
8752 11:10:39.887750 29, 0x0, End_B0=29 End_B1=29
8753 11:10:39.887902 30, 0x0, End_B0=30 End_B1=30
8754 11:10:39.891046 31, 0x4141, End_B0=30 End_B1=30
8755 11:10:39.894604 Byte0 end_step=30 best_step=27
8756 11:10:39.897808 Byte1 end_step=30 best_step=27
8757 11:10:39.900880 Byte0 TX OE(2T, 0.5T) = (3, 3)
8758 11:10:39.904452 Byte1 TX OE(2T, 0.5T) = (3, 3)
8759 11:10:39.904557
8760 11:10:39.904648
8761 11:10:39.910881 [DQSOSCAuto] RK0, (LSB)MR18= 0x90d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8762 11:10:39.914143 CH1 RK0: MR19=303, MR18=90D
8763 11:10:39.920901 CH1_RK0: MR19=0x303, MR18=0x90D, DQSOSC=403, MR23=63, INC=22, DEC=15
8764 11:10:39.921000
8765 11:10:39.924253 ----->DramcWriteLeveling(PI) begin...
8766 11:10:39.924356 ==
8767 11:10:39.927403 Dram Type= 6, Freq= 0, CH_1, rank 1
8768 11:10:39.930708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8769 11:10:39.930794 ==
8770 11:10:39.934080 Write leveling (Byte 0): 24 => 24
8771 11:10:39.937493 Write leveling (Byte 1): 25 => 25
8772 11:10:39.940953 DramcWriteLeveling(PI) end<-----
8773 11:10:39.941040
8774 11:10:39.941104 ==
8775 11:10:39.944147 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 11:10:39.947462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 11:10:39.947548 ==
8778 11:10:39.950595 [Gating] SW mode calibration
8779 11:10:39.957293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8780 11:10:39.963930 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8781 11:10:39.967188 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 11:10:39.974108 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 11:10:39.977175 1 4 8 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
8784 11:10:39.980491 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8785 11:10:39.987091 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 11:10:39.990351 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 11:10:39.994000 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 11:10:40.000429 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 11:10:40.003625 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 11:10:40.006810 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 11:10:40.013352 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
8792 11:10:40.016668 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
8793 11:10:40.020131 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 11:10:40.026649 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 11:10:40.030101 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 11:10:40.033113 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 11:10:40.039558 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 11:10:40.043054 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 11:10:40.046479 1 6 8 | B1->B0 | 2525 4040 | 0 0 | (0 0) (0 0)
8800 11:10:40.053101 1 6 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
8801 11:10:40.056274 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 11:10:40.059470 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 11:10:40.066426 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 11:10:40.069752 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 11:10:40.072824 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 11:10:40.079519 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 11:10:40.083007 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8808 11:10:40.085975 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8809 11:10:40.092560 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8810 11:10:40.095819 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 11:10:40.099332 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 11:10:40.105999 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 11:10:40.109209 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 11:10:40.112742 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 11:10:40.119056 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 11:10:40.122479 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 11:10:40.125859 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 11:10:40.128990 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 11:10:40.135605 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 11:10:40.139030 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 11:10:40.142101 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 11:10:40.149039 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8823 11:10:40.152068 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8824 11:10:40.155401 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8825 11:10:40.162065 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 11:10:40.165362 Total UI for P1: 0, mck2ui 16
8827 11:10:40.168821 best dqsien dly found for B0: ( 1, 9, 8)
8828 11:10:40.172116 Total UI for P1: 0, mck2ui 16
8829 11:10:40.175567 best dqsien dly found for B1: ( 1, 9, 10)
8830 11:10:40.178717 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8831 11:10:40.182056 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8832 11:10:40.182141
8833 11:10:40.185287 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8834 11:10:40.188470 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8835 11:10:40.191785 [Gating] SW calibration Done
8836 11:10:40.191874 ==
8837 11:10:40.195212 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 11:10:40.198745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 11:10:40.198855 ==
8840 11:10:40.201911 RX Vref Scan: 0
8841 11:10:40.202001
8842 11:10:40.205054 RX Vref 0 -> 0, step: 1
8843 11:10:40.205136
8844 11:10:40.205201 RX Delay 0 -> 252, step: 8
8845 11:10:40.212044 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8846 11:10:40.215436 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8847 11:10:40.218357 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8848 11:10:40.221739 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8849 11:10:40.224978 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8850 11:10:40.231911 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8851 11:10:40.235015 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8852 11:10:40.238249 iDelay=200, Bit 7, Center 123 (64 ~ 183) 120
8853 11:10:40.241784 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8854 11:10:40.245390 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8855 11:10:40.248475 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8856 11:10:40.255247 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8857 11:10:40.258126 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8858 11:10:40.261593 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8859 11:10:40.265057 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8860 11:10:40.271598 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8861 11:10:40.271738 ==
8862 11:10:40.274686 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 11:10:40.278047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 11:10:40.278135 ==
8865 11:10:40.278205 DQS Delay:
8866 11:10:40.281468 DQS0 = 0, DQS1 = 0
8867 11:10:40.281574 DQM Delay:
8868 11:10:40.284552 DQM0 = 127, DQM1 = 127
8869 11:10:40.284643 DQ Delay:
8870 11:10:40.288062 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =123
8871 11:10:40.291417 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =123
8872 11:10:40.294686 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8873 11:10:40.298114 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8874 11:10:40.298202
8875 11:10:40.301215
8876 11:10:40.301298 ==
8877 11:10:40.304676 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 11:10:40.308192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 11:10:40.308312 ==
8880 11:10:40.308406
8881 11:10:40.308515
8882 11:10:40.311160 TX Vref Scan disable
8883 11:10:40.311243 == TX Byte 0 ==
8884 11:10:40.318081 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8885 11:10:40.321089 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8886 11:10:40.321179 == TX Byte 1 ==
8887 11:10:40.327959 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8888 11:10:40.331402 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8889 11:10:40.331498 ==
8890 11:10:40.334405 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 11:10:40.337563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 11:10:40.337644 ==
8893 11:10:40.351864
8894 11:10:40.355213 TX Vref early break, caculate TX vref
8895 11:10:40.358359 TX Vref=16, minBit 0, minWin=23, winSum=383
8896 11:10:40.361774 TX Vref=18, minBit 0, minWin=24, winSum=402
8897 11:10:40.365152 TX Vref=20, minBit 0, minWin=23, winSum=404
8898 11:10:40.368535 TX Vref=22, minBit 0, minWin=24, winSum=412
8899 11:10:40.372030 TX Vref=24, minBit 0, minWin=25, winSum=415
8900 11:10:40.378601 TX Vref=26, minBit 0, minWin=25, winSum=425
8901 11:10:40.381700 TX Vref=28, minBit 1, minWin=25, winSum=425
8902 11:10:40.385302 TX Vref=30, minBit 1, minWin=25, winSum=423
8903 11:10:40.388581 TX Vref=32, minBit 1, minWin=24, winSum=418
8904 11:10:40.391770 TX Vref=34, minBit 5, minWin=23, winSum=404
8905 11:10:40.395203 TX Vref=36, minBit 0, minWin=23, winSum=396
8906 11:10:40.401729 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8907 11:10:40.401863
8908 11:10:40.405121 Final TX Range 0 Vref 26
8909 11:10:40.405232
8910 11:10:40.405325 ==
8911 11:10:40.408479 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 11:10:40.411389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 11:10:40.411503 ==
8914 11:10:40.411600
8915 11:10:40.414786
8916 11:10:40.414897 TX Vref Scan disable
8917 11:10:40.421350 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8918 11:10:40.421482 == TX Byte 0 ==
8919 11:10:40.424967 u2DelayCellOfst[0]=18 cells (5 PI)
8920 11:10:40.428259 u2DelayCellOfst[1]=11 cells (3 PI)
8921 11:10:40.431681 u2DelayCellOfst[2]=0 cells (0 PI)
8922 11:10:40.434573 u2DelayCellOfst[3]=3 cells (1 PI)
8923 11:10:40.438013 u2DelayCellOfst[4]=11 cells (3 PI)
8924 11:10:40.441047 u2DelayCellOfst[5]=22 cells (6 PI)
8925 11:10:40.444275 u2DelayCellOfst[6]=18 cells (5 PI)
8926 11:10:40.447825 u2DelayCellOfst[7]=3 cells (1 PI)
8927 11:10:40.451098 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8928 11:10:40.454572 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8929 11:10:40.457710 == TX Byte 1 ==
8930 11:10:40.460885 u2DelayCellOfst[8]=0 cells (0 PI)
8931 11:10:40.464318 u2DelayCellOfst[9]=7 cells (2 PI)
8932 11:10:40.467729 u2DelayCellOfst[10]=15 cells (4 PI)
8933 11:10:40.470753 u2DelayCellOfst[11]=7 cells (2 PI)
8934 11:10:40.470873 u2DelayCellOfst[12]=18 cells (5 PI)
8935 11:10:40.474299 u2DelayCellOfst[13]=18 cells (5 PI)
8936 11:10:40.477344 u2DelayCellOfst[14]=18 cells (5 PI)
8937 11:10:40.480915 u2DelayCellOfst[15]=22 cells (6 PI)
8938 11:10:40.487423 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8939 11:10:40.490748 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8940 11:10:40.490877 DramC Write-DBI on
8941 11:10:40.494103 ==
8942 11:10:40.494184 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 11:10:40.500920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 11:10:40.501008 ==
8945 11:10:40.501070
8946 11:10:40.501128
8947 11:10:40.504135 TX Vref Scan disable
8948 11:10:40.504232 == TX Byte 0 ==
8949 11:10:40.510574 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8950 11:10:40.510675 == TX Byte 1 ==
8951 11:10:40.514230 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8952 11:10:40.517149 DramC Write-DBI off
8953 11:10:40.517226
8954 11:10:40.517290 [DATLAT]
8955 11:10:40.520590 Freq=1600, CH1 RK1
8956 11:10:40.520665
8957 11:10:40.520731 DATLAT Default: 0xf
8958 11:10:40.524059 0, 0xFFFF, sum = 0
8959 11:10:40.524133 1, 0xFFFF, sum = 0
8960 11:10:40.527200 2, 0xFFFF, sum = 0
8961 11:10:40.527298 3, 0xFFFF, sum = 0
8962 11:10:40.530490 4, 0xFFFF, sum = 0
8963 11:10:40.530569 5, 0xFFFF, sum = 0
8964 11:10:40.533921 6, 0xFFFF, sum = 0
8965 11:10:40.533997 7, 0xFFFF, sum = 0
8966 11:10:40.537206 8, 0xFFFF, sum = 0
8967 11:10:40.537305 9, 0xFFFF, sum = 0
8968 11:10:40.540663 10, 0xFFFF, sum = 0
8969 11:10:40.543594 11, 0xFFFF, sum = 0
8970 11:10:40.543665 12, 0xFFFF, sum = 0
8971 11:10:40.547025 13, 0x8FFF, sum = 0
8972 11:10:40.547124 14, 0x0, sum = 1
8973 11:10:40.550495 15, 0x0, sum = 2
8974 11:10:40.550597 16, 0x0, sum = 3
8975 11:10:40.553827 17, 0x0, sum = 4
8976 11:10:40.553919 best_step = 15
8977 11:10:40.553980
8978 11:10:40.554038 ==
8979 11:10:40.557021 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 11:10:40.560159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 11:10:40.563509 ==
8982 11:10:40.563615 RX Vref Scan: 0
8983 11:10:40.563706
8984 11:10:40.566844 RX Vref 0 -> 0, step: 1
8985 11:10:40.566931
8986 11:10:40.566994 RX Delay 3 -> 252, step: 4
8987 11:10:40.573952 iDelay=195, Bit 0, Center 134 (79 ~ 190) 112
8988 11:10:40.577415 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8989 11:10:40.580479 iDelay=195, Bit 2, Center 116 (59 ~ 174) 116
8990 11:10:40.583822 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8991 11:10:40.587145 iDelay=195, Bit 4, Center 122 (67 ~ 178) 112
8992 11:10:40.593793 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8993 11:10:40.597115 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8994 11:10:40.600581 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8995 11:10:40.603888 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8996 11:10:40.607275 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8997 11:10:40.613734 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8998 11:10:40.617141 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8999 11:10:40.620460 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9000 11:10:40.623390 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9001 11:10:40.630191 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9002 11:10:40.633684 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9003 11:10:40.633776 ==
9004 11:10:40.636962 Dram Type= 6, Freq= 0, CH_1, rank 1
9005 11:10:40.639941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9006 11:10:40.640099 ==
9007 11:10:40.643597 DQS Delay:
9008 11:10:40.643712 DQS0 = 0, DQS1 = 0
9009 11:10:40.643805 DQM Delay:
9010 11:10:40.646624 DQM0 = 128, DQM1 = 124
9011 11:10:40.646726 DQ Delay:
9012 11:10:40.650313 DQ0 =134, DQ1 =126, DQ2 =116, DQ3 =126
9013 11:10:40.653660 DQ4 =122, DQ5 =138, DQ6 =138, DQ7 =126
9014 11:10:40.656877 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
9015 11:10:40.663581 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9016 11:10:40.663689
9017 11:10:40.663755
9018 11:10:40.663815
9019 11:10:40.667080 [DramC_TX_OE_Calibration] TA2
9020 11:10:40.667201 Original DQ_B0 (3 6) =30, OEN = 27
9021 11:10:40.670066 Original DQ_B1 (3 6) =30, OEN = 27
9022 11:10:40.673412 24, 0x0, End_B0=24 End_B1=24
9023 11:10:40.676917 25, 0x0, End_B0=25 End_B1=25
9024 11:10:40.680402 26, 0x0, End_B0=26 End_B1=26
9025 11:10:40.683309 27, 0x0, End_B0=27 End_B1=27
9026 11:10:40.683419 28, 0x0, End_B0=28 End_B1=28
9027 11:10:40.686825 29, 0x0, End_B0=29 End_B1=29
9028 11:10:40.690048 30, 0x0, End_B0=30 End_B1=30
9029 11:10:40.693184 31, 0x5151, End_B0=30 End_B1=30
9030 11:10:40.696670 Byte0 end_step=30 best_step=27
9031 11:10:40.696780 Byte1 end_step=30 best_step=27
9032 11:10:40.699957 Byte0 TX OE(2T, 0.5T) = (3, 3)
9033 11:10:40.703416 Byte1 TX OE(2T, 0.5T) = (3, 3)
9034 11:10:40.703495
9035 11:10:40.703558
9036 11:10:40.713130 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9037 11:10:40.713253 CH1 RK1: MR19=303, MR18=D1A
9038 11:10:40.719847 CH1_RK1: MR19=0x303, MR18=0xD1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9039 11:10:40.723099 [RxdqsGatingPostProcess] freq 1600
9040 11:10:40.729835 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9041 11:10:40.733392 best DQS0 dly(2T, 0.5T) = (1, 1)
9042 11:10:40.736276 best DQS1 dly(2T, 0.5T) = (1, 1)
9043 11:10:40.739599 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9044 11:10:40.743111 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9045 11:10:40.743203 best DQS0 dly(2T, 0.5T) = (1, 1)
9046 11:10:40.746456 best DQS1 dly(2T, 0.5T) = (1, 1)
9047 11:10:40.749471 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9048 11:10:40.753089 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9049 11:10:40.756066 Pre-setting of DQS Precalculation
9050 11:10:40.763038 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9051 11:10:40.769641 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9052 11:10:40.776072 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9053 11:10:40.776189
9054 11:10:40.776256
9055 11:10:40.779314 [Calibration Summary] 3200 Mbps
9056 11:10:40.779402 CH 0, Rank 0
9057 11:10:40.782770 SW Impedance : PASS
9058 11:10:40.785841 DUTY Scan : NO K
9059 11:10:40.785927 ZQ Calibration : PASS
9060 11:10:40.789229 Jitter Meter : NO K
9061 11:10:40.792366 CBT Training : PASS
9062 11:10:40.792451 Write leveling : PASS
9063 11:10:40.795676 RX DQS gating : PASS
9064 11:10:40.799095 RX DQ/DQS(RDDQC) : PASS
9065 11:10:40.799182 TX DQ/DQS : PASS
9066 11:10:40.802266 RX DATLAT : PASS
9067 11:10:40.805709 RX DQ/DQS(Engine): PASS
9068 11:10:40.805797 TX OE : PASS
9069 11:10:40.805863 All Pass.
9070 11:10:40.809016
9071 11:10:40.809099 CH 0, Rank 1
9072 11:10:40.812234 SW Impedance : PASS
9073 11:10:40.812345 DUTY Scan : NO K
9074 11:10:40.815582 ZQ Calibration : PASS
9075 11:10:40.819069 Jitter Meter : NO K
9076 11:10:40.819156 CBT Training : PASS
9077 11:10:40.822264 Write leveling : PASS
9078 11:10:40.822350 RX DQS gating : PASS
9079 11:10:40.825469 RX DQ/DQS(RDDQC) : PASS
9080 11:10:40.829064 TX DQ/DQS : PASS
9081 11:10:40.829151 RX DATLAT : PASS
9082 11:10:40.832369 RX DQ/DQS(Engine): PASS
9083 11:10:40.835704 TX OE : PASS
9084 11:10:40.835791 All Pass.
9085 11:10:40.835856
9086 11:10:40.835935 CH 1, Rank 0
9087 11:10:40.838759 SW Impedance : PASS
9088 11:10:40.842141 DUTY Scan : NO K
9089 11:10:40.842226 ZQ Calibration : PASS
9090 11:10:40.845302 Jitter Meter : NO K
9091 11:10:40.848794 CBT Training : PASS
9092 11:10:40.848880 Write leveling : PASS
9093 11:10:40.852104 RX DQS gating : PASS
9094 11:10:40.855490 RX DQ/DQS(RDDQC) : PASS
9095 11:10:40.855576 TX DQ/DQS : PASS
9096 11:10:40.858533 RX DATLAT : PASS
9097 11:10:40.861938 RX DQ/DQS(Engine): PASS
9098 11:10:40.862023 TX OE : PASS
9099 11:10:40.865325 All Pass.
9100 11:10:40.865436
9101 11:10:40.865552 CH 1, Rank 1
9102 11:10:40.868616 SW Impedance : PASS
9103 11:10:40.868703 DUTY Scan : NO K
9104 11:10:40.872077 ZQ Calibration : PASS
9105 11:10:40.875228 Jitter Meter : NO K
9106 11:10:40.875315 CBT Training : PASS
9107 11:10:40.878456 Write leveling : PASS
9108 11:10:40.878538 RX DQS gating : PASS
9109 11:10:40.881893 RX DQ/DQS(RDDQC) : PASS
9110 11:10:40.885344 TX DQ/DQS : PASS
9111 11:10:40.885431 RX DATLAT : PASS
9112 11:10:40.888414 RX DQ/DQS(Engine): PASS
9113 11:10:40.891888 TX OE : PASS
9114 11:10:40.891975 All Pass.
9115 11:10:40.892041
9116 11:10:40.895287 DramC Write-DBI on
9117 11:10:40.895370 PER_BANK_REFRESH: Hybrid Mode
9118 11:10:40.898395 TX_TRACKING: ON
9119 11:10:40.908356 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9120 11:10:40.915308 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9121 11:10:40.921759 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9122 11:10:40.925005 [FAST_K] Save calibration result to emmc
9123 11:10:40.928340 sync common calibartion params.
9124 11:10:40.931548 sync cbt_mode0:1, 1:1
9125 11:10:40.931647 dram_init: ddr_geometry: 2
9126 11:10:40.935010 dram_init: ddr_geometry: 2
9127 11:10:40.938223 dram_init: ddr_geometry: 2
9128 11:10:40.941416 0:dram_rank_size:100000000
9129 11:10:40.941602 1:dram_rank_size:100000000
9130 11:10:40.948270 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9131 11:10:40.951307 DFS_SHUFFLE_HW_MODE: ON
9132 11:10:40.954714 dramc_set_vcore_voltage set vcore to 725000
9133 11:10:40.958286 Read voltage for 1600, 0
9134 11:10:40.958384 Vio18 = 0
9135 11:10:40.958450 Vcore = 725000
9136 11:10:40.958511 Vdram = 0
9137 11:10:40.961308 Vddq = 0
9138 11:10:40.961391 Vmddr = 0
9139 11:10:40.964679 switch to 3200 Mbps bootup
9140 11:10:40.964777 [DramcRunTimeConfig]
9141 11:10:40.967960 PHYPLL
9142 11:10:40.968077 DPM_CONTROL_AFTERK: ON
9143 11:10:40.971281 PER_BANK_REFRESH: ON
9144 11:10:40.974645 REFRESH_OVERHEAD_REDUCTION: ON
9145 11:10:40.974759 CMD_PICG_NEW_MODE: OFF
9146 11:10:40.978052 XRTWTW_NEW_MODE: ON
9147 11:10:40.978127 XRTRTR_NEW_MODE: ON
9148 11:10:40.981205 TX_TRACKING: ON
9149 11:10:40.981322 RDSEL_TRACKING: OFF
9150 11:10:40.984493 DQS Precalculation for DVFS: ON
9151 11:10:40.988012 RX_TRACKING: OFF
9152 11:10:40.988092 HW_GATING DBG: ON
9153 11:10:40.991077 ZQCS_ENABLE_LP4: ON
9154 11:10:40.991163 RX_PICG_NEW_MODE: ON
9155 11:10:40.994464 TX_PICG_NEW_MODE: ON
9156 11:10:40.994544 ENABLE_RX_DCM_DPHY: ON
9157 11:10:40.997846 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9158 11:10:41.001014 DUMMY_READ_FOR_TRACKING: OFF
9159 11:10:41.004426 !!! SPM_CONTROL_AFTERK: OFF
9160 11:10:41.007524 !!! SPM could not control APHY
9161 11:10:41.007614 IMPEDANCE_TRACKING: ON
9162 11:10:41.011008 TEMP_SENSOR: ON
9163 11:10:41.011094 HW_SAVE_FOR_SR: OFF
9164 11:10:41.014231 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9165 11:10:41.017414 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9166 11:10:41.020723 Read ODT Tracking: ON
9167 11:10:41.024388 Refresh Rate DeBounce: ON
9168 11:10:41.024493 DFS_NO_QUEUE_FLUSH: ON
9169 11:10:41.027368 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9170 11:10:41.030731 ENABLE_DFS_RUNTIME_MRW: OFF
9171 11:10:41.033935 DDR_RESERVE_NEW_MODE: ON
9172 11:10:41.034037 MR_CBT_SWITCH_FREQ: ON
9173 11:10:41.037248 =========================
9174 11:10:41.056391 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9175 11:10:41.059568 dram_init: ddr_geometry: 2
9176 11:10:41.077849 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9177 11:10:41.081327 dram_init: dram init end (result: 0)
9178 11:10:41.087907 DRAM-K: Full calibration passed in 24618 msecs
9179 11:10:41.091304 MRC: failed to locate region type 0.
9180 11:10:41.091435 DRAM rank0 size:0x100000000,
9181 11:10:41.094557 DRAM rank1 size=0x100000000
9182 11:10:41.104599 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9183 11:10:41.111231 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9184 11:10:41.117881 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9185 11:10:41.124171 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9186 11:10:41.127539 DRAM rank0 size:0x100000000,
9187 11:10:41.130874 DRAM rank1 size=0x100000000
9188 11:10:41.130987 CBMEM:
9189 11:10:41.134543 IMD: root @ 0xfffff000 254 entries.
9190 11:10:41.137406 IMD: root @ 0xffffec00 62 entries.
9191 11:10:41.141130 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9192 11:10:41.147578 WARNING: RO_VPD is uninitialized or empty.
9193 11:10:41.150386 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9194 11:10:41.157928 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9195 11:10:41.170925 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9196 11:10:41.182151 BS: romstage times (exec / console): total (unknown) / 24075 ms
9197 11:10:41.182293
9198 11:10:41.182360
9199 11:10:41.192008 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9200 11:10:41.195292 ARM64: Exception handlers installed.
9201 11:10:41.198649 ARM64: Testing exception
9202 11:10:41.202138 ARM64: Done test exception
9203 11:10:41.202227 Enumerating buses...
9204 11:10:41.205179 Show all devs... Before device enumeration.
9205 11:10:41.208574 Root Device: enabled 1
9206 11:10:41.211825 CPU_CLUSTER: 0: enabled 1
9207 11:10:41.211904 CPU: 00: enabled 1
9208 11:10:41.215249 Compare with tree...
9209 11:10:41.215325 Root Device: enabled 1
9210 11:10:41.218308 CPU_CLUSTER: 0: enabled 1
9211 11:10:41.221929 CPU: 00: enabled 1
9212 11:10:41.222015 Root Device scanning...
9213 11:10:41.224923 scan_static_bus for Root Device
9214 11:10:41.228417 CPU_CLUSTER: 0 enabled
9215 11:10:41.231572 scan_static_bus for Root Device done
9216 11:10:41.234818 scan_bus: bus Root Device finished in 8 msecs
9217 11:10:41.234904 done
9218 11:10:41.241599 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9219 11:10:41.244955 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9220 11:10:41.251215 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9221 11:10:41.254756 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9222 11:10:41.258028 Allocating resources...
9223 11:10:41.261352 Reading resources...
9224 11:10:41.264772 Root Device read_resources bus 0 link: 0
9225 11:10:41.267963 DRAM rank0 size:0x100000000,
9226 11:10:41.268125 DRAM rank1 size=0x100000000
9227 11:10:41.271474 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9228 11:10:41.274664 CPU: 00 missing read_resources
9229 11:10:41.281286 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9230 11:10:41.284532 Root Device read_resources bus 0 link: 0 done
9231 11:10:41.287827 Done reading resources.
9232 11:10:41.291249 Show resources in subtree (Root Device)...After reading.
9233 11:10:41.294292 Root Device child on link 0 CPU_CLUSTER: 0
9234 11:10:41.297587 CPU_CLUSTER: 0 child on link 0 CPU: 00
9235 11:10:41.307641 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9236 11:10:41.307766 CPU: 00
9237 11:10:41.310748 Root Device assign_resources, bus 0 link: 0
9238 11:10:41.314134 CPU_CLUSTER: 0 missing set_resources
9239 11:10:41.320990 Root Device assign_resources, bus 0 link: 0 done
9240 11:10:41.321124 Done setting resources.
9241 11:10:41.327406 Show resources in subtree (Root Device)...After assigning values.
9242 11:10:41.330723 Root Device child on link 0 CPU_CLUSTER: 0
9243 11:10:41.334113 CPU_CLUSTER: 0 child on link 0 CPU: 00
9244 11:10:41.344047 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9245 11:10:41.344183 CPU: 00
9246 11:10:41.347504 Done allocating resources.
9247 11:10:41.353970 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9248 11:10:41.354092 Enabling resources...
9249 11:10:41.354159 done.
9250 11:10:41.360760 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9251 11:10:41.360891 Initializing devices...
9252 11:10:41.364002 Root Device init
9253 11:10:41.367284 init hardware done!
9254 11:10:41.367379 0x00000018: ctrlr->caps
9255 11:10:41.370761 52.000 MHz: ctrlr->f_max
9256 11:10:41.373783 0.400 MHz: ctrlr->f_min
9257 11:10:41.373895 0x40ff8080: ctrlr->voltages
9258 11:10:41.377247 sclk: 390625
9259 11:10:41.377327 Bus Width = 1
9260 11:10:41.377417 sclk: 390625
9261 11:10:41.380668 Bus Width = 1
9262 11:10:41.380744 Early init status = 3
9263 11:10:41.387261 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9264 11:10:41.390931 in-header: 03 fc 00 00 01 00 00 00
9265 11:10:41.393909 in-data: 00
9266 11:10:41.397272 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9267 11:10:41.403308 in-header: 03 fd 00 00 00 00 00 00
9268 11:10:41.406407 in-data:
9269 11:10:41.409748 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9270 11:10:41.413821 in-header: 03 fc 00 00 01 00 00 00
9271 11:10:41.417114 in-data: 00
9272 11:10:41.420313 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9273 11:10:41.426398 in-header: 03 fd 00 00 00 00 00 00
9274 11:10:41.429231 in-data:
9275 11:10:41.432781 [SSUSB] Setting up USB HOST controller...
9276 11:10:41.436105 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9277 11:10:41.439534 [SSUSB] phy power-on done.
9278 11:10:41.442526 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9279 11:10:41.449358 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9280 11:10:41.452391 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9281 11:10:41.459424 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9282 11:10:41.466079 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9283 11:10:41.472536 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9284 11:10:41.479037 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9285 11:10:41.485600 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9286 11:10:41.489239 SPM: binary array size = 0x9dc
9287 11:10:41.492224 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9288 11:10:41.498904 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9289 11:10:41.505654 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9290 11:10:41.512095 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9291 11:10:41.515351 configure_display: Starting display init
9292 11:10:41.549203 anx7625_power_on_init: Init interface.
9293 11:10:41.552620 anx7625_disable_pd_protocol: Disabled PD feature.
9294 11:10:41.555943 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9295 11:10:41.583787 anx7625_start_dp_work: Secure OCM version=00
9296 11:10:41.587310 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9297 11:10:41.601940 sp_tx_get_edid_block: EDID Block = 1
9298 11:10:41.704445 Extracted contents:
9299 11:10:41.707931 header: 00 ff ff ff ff ff ff 00
9300 11:10:41.710846 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9301 11:10:41.714235 version: 01 04
9302 11:10:41.717740 basic params: 95 1f 11 78 0a
9303 11:10:41.720763 chroma info: 76 90 94 55 54 90 27 21 50 54
9304 11:10:41.724168 established: 00 00 00
9305 11:10:41.730765 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9306 11:10:41.734234 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9307 11:10:41.740654 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9308 11:10:41.747482 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9309 11:10:41.753800 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9310 11:10:41.757105 extensions: 00
9311 11:10:41.757197 checksum: fb
9312 11:10:41.757260
9313 11:10:41.760762 Manufacturer: IVO Model 57d Serial Number 0
9314 11:10:41.763755 Made week 0 of 2020
9315 11:10:41.767134 EDID version: 1.4
9316 11:10:41.767220 Digital display
9317 11:10:41.770290 6 bits per primary color channel
9318 11:10:41.770378 DisplayPort interface
9319 11:10:41.773782 Maximum image size: 31 cm x 17 cm
9320 11:10:41.777104 Gamma: 220%
9321 11:10:41.777189 Check DPMS levels
9322 11:10:41.780513 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9323 11:10:41.787069 First detailed timing is preferred timing
9324 11:10:41.787183 Established timings supported:
9325 11:10:41.790341 Standard timings supported:
9326 11:10:41.793790 Detailed timings
9327 11:10:41.797051 Hex of detail: 383680a07038204018303c0035ae10000019
9328 11:10:41.803547 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9329 11:10:41.806878 0780 0798 07c8 0820 hborder 0
9330 11:10:41.810220 0438 043b 0447 0458 vborder 0
9331 11:10:41.813692 -hsync -vsync
9332 11:10:41.813782 Did detailed timing
9333 11:10:41.820309 Hex of detail: 000000000000000000000000000000000000
9334 11:10:41.823605 Manufacturer-specified data, tag 0
9335 11:10:41.826647 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9336 11:10:41.829910 ASCII string: InfoVision
9337 11:10:41.833491 Hex of detail: 000000fe00523134304e574635205248200a
9338 11:10:41.836542 ASCII string: R140NWF5 RH
9339 11:10:41.836633 Checksum
9340 11:10:41.840159 Checksum: 0xfb (valid)
9341 11:10:41.843023 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9342 11:10:41.846620 DSI data_rate: 832800000 bps
9343 11:10:41.853023 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9344 11:10:41.856549 anx7625_parse_edid: pixelclock(138800).
9345 11:10:41.859479 hactive(1920), hsync(48), hfp(24), hbp(88)
9346 11:10:41.863119 vactive(1080), vsync(12), vfp(3), vbp(17)
9347 11:10:41.866430 anx7625_dsi_config: config dsi.
9348 11:10:41.872949 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9349 11:10:41.886296 anx7625_dsi_config: success to config DSI
9350 11:10:41.889787 anx7625_dp_start: MIPI phy setup OK.
9351 11:10:41.893022 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9352 11:10:41.896374 mtk_ddp_mode_set invalid vrefresh 60
9353 11:10:41.899638 main_disp_path_setup
9354 11:10:41.899734 ovl_layer_smi_id_en
9355 11:10:41.902912 ovl_layer_smi_id_en
9356 11:10:41.903002 ccorr_config
9357 11:10:41.903065 aal_config
9358 11:10:41.906215 gamma_config
9359 11:10:41.906301 postmask_config
9360 11:10:41.909551 dither_config
9361 11:10:41.912777 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9362 11:10:41.919311 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9363 11:10:41.922588 Root Device init finished in 555 msecs
9364 11:10:41.926128 CPU_CLUSTER: 0 init
9365 11:10:41.932905 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9366 11:10:41.939220 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9367 11:10:41.939328 APU_MBOX 0x190000b0 = 0x10001
9368 11:10:41.942700 APU_MBOX 0x190001b0 = 0x10001
9369 11:10:41.946147 APU_MBOX 0x190005b0 = 0x10001
9370 11:10:41.949077 APU_MBOX 0x190006b0 = 0x10001
9371 11:10:41.955859 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9372 11:10:41.965369 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9373 11:10:41.977993 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9374 11:10:41.984771 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9375 11:10:41.995909 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9376 11:10:42.005263 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9377 11:10:42.008422 CPU_CLUSTER: 0 init finished in 81 msecs
9378 11:10:42.011859 Devices initialized
9379 11:10:42.015113 Show all devs... After init.
9380 11:10:42.015225 Root Device: enabled 1
9381 11:10:42.018197 CPU_CLUSTER: 0: enabled 1
9382 11:10:42.021558 CPU: 00: enabled 1
9383 11:10:42.024901 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9384 11:10:42.028086 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9385 11:10:42.031313 ELOG: NV offset 0x57f000 size 0x1000
9386 11:10:42.038292 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9387 11:10:42.045250 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9388 11:10:42.048242 ELOG: Event(17) added with size 13 at 2024-03-03 11:10:42 UTC
9389 11:10:42.055056 out: cmd=0x121: 03 db 21 01 00 00 00 00
9390 11:10:42.058137 in-header: 03 20 00 00 2c 00 00 00
9391 11:10:42.068003 in-data: 3e 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9392 11:10:42.074492 ELOG: Event(A1) added with size 10 at 2024-03-03 11:10:42 UTC
9393 11:10:42.081151 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9394 11:10:42.088126 ELOG: Event(A0) added with size 9 at 2024-03-03 11:10:42 UTC
9395 11:10:42.091031 elog_add_boot_reason: Logged dev mode boot
9396 11:10:42.097826 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9397 11:10:42.097947 Finalize devices...
9398 11:10:42.100783 Devices finalized
9399 11:10:42.104180 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9400 11:10:42.107554 Writing coreboot table at 0xffe64000
9401 11:10:42.111018 0. 000000000010a000-0000000000113fff: RAMSTAGE
9402 11:10:42.117386 1. 0000000040000000-00000000400fffff: RAM
9403 11:10:42.120712 2. 0000000040100000-000000004032afff: RAMSTAGE
9404 11:10:42.124069 3. 000000004032b000-00000000545fffff: RAM
9405 11:10:42.127441 4. 0000000054600000-000000005465ffff: BL31
9406 11:10:42.130721 5. 0000000054660000-00000000ffe63fff: RAM
9407 11:10:42.137131 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9408 11:10:42.140658 7. 0000000100000000-000000023fffffff: RAM
9409 11:10:42.144080 Passing 5 GPIOs to payload:
9410 11:10:42.147207 NAME | PORT | POLARITY | VALUE
9411 11:10:42.154062 EC in RW | 0x000000aa | low | undefined
9412 11:10:42.157181 EC interrupt | 0x00000005 | low | undefined
9413 11:10:42.160715 TPM interrupt | 0x000000ab | high | undefined
9414 11:10:42.167062 SD card detect | 0x00000011 | high | undefined
9415 11:10:42.170588 speaker enable | 0x00000093 | high | undefined
9416 11:10:42.173867 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9417 11:10:42.177067 in-header: 03 f9 00 00 02 00 00 00
9418 11:10:42.180308 in-data: 02 00
9419 11:10:42.183711 ADC[4]: Raw value=892971 ID=7
9420 11:10:42.183803 ADC[3]: Raw value=213070 ID=1
9421 11:10:42.187148 RAM Code: 0x71
9422 11:10:42.190259 ADC[6]: Raw value=74722 ID=0
9423 11:10:42.190350 ADC[5]: Raw value=211960 ID=1
9424 11:10:42.193692 SKU Code: 0x1
9425 11:10:42.200166 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 18ab
9426 11:10:42.200273 coreboot table: 964 bytes.
9427 11:10:42.203402 IMD ROOT 0. 0xfffff000 0x00001000
9428 11:10:42.206716 IMD SMALL 1. 0xffffe000 0x00001000
9429 11:10:42.209973 RO MCACHE 2. 0xffffc000 0x00001104
9430 11:10:42.213315 CONSOLE 3. 0xfff7c000 0x00080000
9431 11:10:42.216792 FMAP 4. 0xfff7b000 0x00000452
9432 11:10:42.220128 TIME STAMP 5. 0xfff7a000 0x00000910
9433 11:10:42.223217 VBOOT WORK 6. 0xfff66000 0x00014000
9434 11:10:42.226469 RAMOOPS 7. 0xffe66000 0x00100000
9435 11:10:42.229944 COREBOOT 8. 0xffe64000 0x00002000
9436 11:10:42.233288 IMD small region:
9437 11:10:42.236469 IMD ROOT 0. 0xffffec00 0x00000400
9438 11:10:42.240038 VPD 1. 0xffffeb80 0x0000006c
9439 11:10:42.243063 MMC STATUS 2. 0xffffeb60 0x00000004
9440 11:10:42.246446 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9441 11:10:42.249775 Probing TPM: done!
9442 11:10:42.253069 Connected to device vid:did:rid of 1ae0:0028:00
9443 11:10:42.264182 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9444 11:10:42.267523 Initialized TPM device CR50 revision 0
9445 11:10:42.271211 Checking cr50 for pending updates
9446 11:10:42.274771 Reading cr50 TPM mode
9447 11:10:42.283633 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9448 11:10:42.290442 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9449 11:10:42.330227 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9450 11:10:42.333442 Checking segment from ROM address 0x40100000
9451 11:10:42.336754 Checking segment from ROM address 0x4010001c
9452 11:10:42.343738 Loading segment from ROM address 0x40100000
9453 11:10:42.343862 code (compression=0)
9454 11:10:42.353707 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9455 11:10:42.360309 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9456 11:10:42.360429 it's not compressed!
9457 11:10:42.366850 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9458 11:10:42.370331 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9459 11:10:42.390570 Loading segment from ROM address 0x4010001c
9460 11:10:42.390757 Entry Point 0x80000000
9461 11:10:42.393901 Loaded segments
9462 11:10:42.397432 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9463 11:10:42.404079 Jumping to boot code at 0x80000000(0xffe64000)
9464 11:10:42.410728 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9465 11:10:42.417098 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9466 11:10:42.425418 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9467 11:10:42.428519 Checking segment from ROM address 0x40100000
9468 11:10:42.432002 Checking segment from ROM address 0x4010001c
9469 11:10:42.438278 Loading segment from ROM address 0x40100000
9470 11:10:42.438387 code (compression=1)
9471 11:10:42.445098 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9472 11:10:42.455275 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9473 11:10:42.455398 using LZMA
9474 11:10:42.463434 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9475 11:10:42.470233 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9476 11:10:42.473796 Loading segment from ROM address 0x4010001c
9477 11:10:42.473907 Entry Point 0x54601000
9478 11:10:42.476812 Loaded segments
9479 11:10:42.480156 NOTICE: MT8192 bl31_setup
9480 11:10:42.487383 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9481 11:10:42.490423 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9482 11:10:42.493843 WARNING: region 0:
9483 11:10:42.497231 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 11:10:42.497319 WARNING: region 1:
9485 11:10:42.503840 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9486 11:10:42.507510 WARNING: region 2:
9487 11:10:42.510391 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9488 11:10:42.513841 WARNING: region 3:
9489 11:10:42.517133 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 11:10:42.520565 WARNING: region 4:
9491 11:10:42.524193 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9492 11:10:42.527151 WARNING: region 5:
9493 11:10:42.530410 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 11:10:42.533788 WARNING: region 6:
9495 11:10:42.537372 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 11:10:42.537471 WARNING: region 7:
9497 11:10:42.543736 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 11:10:42.550650 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9499 11:10:42.554115 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9500 11:10:42.557082 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9501 11:10:42.564014 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9502 11:10:42.567368 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9503 11:10:42.570538 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9504 11:10:42.577068 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9505 11:10:42.580469 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9506 11:10:42.587186 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9507 11:10:42.590394 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9508 11:10:42.593719 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9509 11:10:42.600484 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9510 11:10:42.603710 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9511 11:10:42.607070 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9512 11:10:42.613729 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9513 11:10:42.617113 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9514 11:10:42.620618 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9515 11:10:42.627380 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9516 11:10:42.630494 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9517 11:10:42.637150 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9518 11:10:42.640392 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9519 11:10:42.643777 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9520 11:10:42.650471 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9521 11:10:42.653881 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9522 11:10:42.660557 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9523 11:10:42.663749 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9524 11:10:42.667113 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9525 11:10:42.673696 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9526 11:10:42.676795 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9527 11:10:42.683689 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9528 11:10:42.687136 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9529 11:10:42.690258 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9530 11:10:42.696911 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9531 11:10:42.700117 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9532 11:10:42.703860 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9533 11:10:42.707256 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9534 11:10:42.713695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9535 11:10:42.717075 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9536 11:10:42.720213 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9537 11:10:42.723623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9538 11:10:42.730404 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9539 11:10:42.733884 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9540 11:10:42.736948 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9541 11:10:42.740278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9542 11:10:42.746801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9543 11:10:42.750192 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9544 11:10:42.753451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9545 11:10:42.756821 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9546 11:10:42.763611 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9547 11:10:42.767055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9548 11:10:42.773111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9549 11:10:42.776537 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9550 11:10:42.783184 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9551 11:10:42.786591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9552 11:10:42.790040 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9553 11:10:42.796577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9554 11:10:42.800085 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9555 11:10:42.806652 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9556 11:10:42.809937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9557 11:10:42.816661 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9558 11:10:42.820086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9559 11:10:42.823130 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9560 11:10:42.829838 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9561 11:10:42.833264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9562 11:10:42.839985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9563 11:10:42.843317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9564 11:10:42.849872 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9565 11:10:42.853339 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9566 11:10:42.856457 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9567 11:10:42.863152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9568 11:10:42.866525 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9569 11:10:42.873092 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9570 11:10:42.876465 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9571 11:10:42.883288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9572 11:10:42.886774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9573 11:10:42.889997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9574 11:10:42.896520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9575 11:10:42.899875 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9576 11:10:42.906743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9577 11:10:42.909980 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9578 11:10:42.916218 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9579 11:10:42.919535 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9580 11:10:42.926265 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9581 11:10:42.929438 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9582 11:10:42.932812 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9583 11:10:42.939475 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9584 11:10:42.942790 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9585 11:10:42.949443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9586 11:10:42.952813 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9587 11:10:42.959553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9588 11:10:42.963042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9589 11:10:42.966098 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9590 11:10:42.972828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9591 11:10:42.976300 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9592 11:10:42.982914 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9593 11:10:42.986272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9594 11:10:42.992633 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9595 11:10:42.996049 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9596 11:10:42.999533 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9597 11:10:43.002593 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9598 11:10:43.009339 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9599 11:10:43.012940 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9600 11:10:43.015807 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9601 11:10:43.022567 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9602 11:10:43.025913 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9603 11:10:43.032766 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9604 11:10:43.036078 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9605 11:10:43.039150 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9606 11:10:43.046234 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9607 11:10:43.049383 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9608 11:10:43.052778 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9609 11:10:43.059411 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9610 11:10:43.062694 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9611 11:10:43.069455 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9612 11:10:43.072761 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9613 11:10:43.076044 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9614 11:10:43.082597 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9615 11:10:43.086233 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9616 11:10:43.089393 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9617 11:10:43.096003 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9618 11:10:43.099420 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9619 11:10:43.102623 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9620 11:10:43.106085 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9621 11:10:43.112644 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9622 11:10:43.116186 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9623 11:10:43.119128 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9624 11:10:43.126121 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9625 11:10:43.129511 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9626 11:10:43.135857 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9627 11:10:43.139379 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9628 11:10:43.142417 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9629 11:10:43.149414 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9630 11:10:43.152465 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9631 11:10:43.155920 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9632 11:10:43.162483 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9633 11:10:43.165853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9634 11:10:43.172615 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9635 11:10:43.176020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9636 11:10:43.179072 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9637 11:10:43.185981 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9638 11:10:43.189397 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9639 11:10:43.195780 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9640 11:10:43.199098 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9641 11:10:43.202466 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9642 11:10:43.209231 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9643 11:10:43.212470 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9644 11:10:43.218859 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9645 11:10:43.222536 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9646 11:10:43.225645 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9647 11:10:43.232387 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9648 11:10:43.235474 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9649 11:10:43.238778 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9650 11:10:43.245708 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9651 11:10:43.249040 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9652 11:10:43.255508 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9653 11:10:43.259096 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9654 11:10:43.262289 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9655 11:10:43.268754 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9656 11:10:43.271940 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9657 11:10:43.278526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9658 11:10:43.282263 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9659 11:10:43.285218 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9660 11:10:43.291904 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9661 11:10:43.295389 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9662 11:10:43.301704 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9663 11:10:43.305105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9664 11:10:43.308422 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9665 11:10:43.315269 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9666 11:10:43.318304 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9667 11:10:43.324707 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9668 11:10:43.328102 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9669 11:10:43.334574 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9670 11:10:43.337936 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9671 11:10:43.341293 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9672 11:10:43.347971 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9673 11:10:43.350958 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9674 11:10:43.354421 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9675 11:10:43.360836 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9676 11:10:43.364400 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9677 11:10:43.370608 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9678 11:10:43.373937 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9679 11:10:43.377832 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9680 11:10:43.384119 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9681 11:10:43.387484 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9682 11:10:43.394053 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9683 11:10:43.397248 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9684 11:10:43.400501 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9685 11:10:43.407084 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9686 11:10:43.410464 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9687 11:10:43.417464 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9688 11:10:43.420446 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9689 11:10:43.427168 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9690 11:10:43.430499 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9691 11:10:43.433455 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9692 11:10:43.440323 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9693 11:10:43.443381 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9694 11:10:43.450086 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9695 11:10:43.453496 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9696 11:10:43.460186 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9697 11:10:43.463621 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9698 11:10:43.466759 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9699 11:10:43.473614 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9700 11:10:43.476876 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9701 11:10:43.483354 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9702 11:10:43.486431 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9703 11:10:43.490137 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9704 11:10:43.496509 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9705 11:10:43.499654 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9706 11:10:43.506358 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9707 11:10:43.509739 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9708 11:10:43.516081 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9709 11:10:43.519739 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9710 11:10:43.522966 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9711 11:10:43.529543 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9712 11:10:43.532792 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9713 11:10:43.539323 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9714 11:10:43.542968 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9715 11:10:43.549242 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9716 11:10:43.552763 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9717 11:10:43.556280 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9718 11:10:43.562863 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9719 11:10:43.566131 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9720 11:10:43.572756 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9721 11:10:43.576110 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9722 11:10:43.579065 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9723 11:10:43.585813 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9724 11:10:43.589215 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9725 11:10:43.595877 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9726 11:10:43.598987 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9727 11:10:43.602363 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9728 11:10:43.609131 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9729 11:10:43.612178 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9730 11:10:43.615652 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9731 11:10:43.618783 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9732 11:10:43.625441 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9733 11:10:43.628998 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9734 11:10:43.632013 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9735 11:10:43.639021 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9736 11:10:43.642018 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9737 11:10:43.648847 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9738 11:10:43.652154 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9739 11:10:43.655460 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9740 11:10:43.662016 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9741 11:10:43.665326 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9742 11:10:43.668683 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9743 11:10:43.675073 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9744 11:10:43.678575 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9745 11:10:43.685136 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9746 11:10:43.688211 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9747 11:10:43.691648 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9748 11:10:43.698445 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9749 11:10:43.701437 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9750 11:10:43.705127 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9751 11:10:43.711678 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9752 11:10:43.714862 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9753 11:10:43.718120 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9754 11:10:43.724796 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9755 11:10:43.728140 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9756 11:10:43.731509 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9757 11:10:43.738411 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9758 11:10:43.741432 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9759 11:10:43.748075 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9760 11:10:43.751529 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9761 11:10:43.754576 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9762 11:10:43.761212 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9763 11:10:43.764655 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9764 11:10:43.771105 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9765 11:10:43.774556 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9766 11:10:43.777776 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9767 11:10:43.781046 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9768 11:10:43.787590 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9769 11:10:43.790817 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9770 11:10:43.794245 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9771 11:10:43.797370 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9772 11:10:43.804147 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9773 11:10:43.807547 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9774 11:10:43.810875 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9775 11:10:43.814152 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9776 11:10:43.820757 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9777 11:10:43.823937 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9778 11:10:43.827367 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9779 11:10:43.833876 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9780 11:10:43.837060 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9781 11:10:43.840571 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9782 11:10:43.847170 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9783 11:10:43.850530 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9784 11:10:43.857098 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9785 11:10:43.860446 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9786 11:10:43.867250 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9787 11:10:43.870348 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9788 11:10:43.873685 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9789 11:10:43.880235 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9790 11:10:43.883444 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9791 11:10:43.890172 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9792 11:10:43.893434 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9793 11:10:43.896921 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9794 11:10:43.903869 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9795 11:10:43.906908 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9796 11:10:43.909989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9797 11:10:43.916658 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9798 11:10:43.920026 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9799 11:10:43.926834 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9800 11:10:43.930076 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9801 11:10:43.936848 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9802 11:10:43.940046 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9803 11:10:43.943097 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9804 11:10:43.950016 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9805 11:10:43.953326 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9806 11:10:43.959787 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9807 11:10:43.962896 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9808 11:10:43.969328 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9809 11:10:43.972940 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9810 11:10:43.976040 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9811 11:10:43.983025 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9812 11:10:43.986282 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9813 11:10:43.993018 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9814 11:10:43.996274 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9815 11:10:43.999575 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9816 11:10:44.006302 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9817 11:10:44.009465 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9818 11:10:44.016144 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9819 11:10:44.019431 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9820 11:10:44.022877 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9821 11:10:44.029225 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9822 11:10:44.032690 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9823 11:10:44.039387 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9824 11:10:44.042725 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9825 11:10:44.049332 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9826 11:10:44.052419 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9827 11:10:44.056030 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9828 11:10:44.062220 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9829 11:10:44.065575 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9830 11:10:44.072357 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9831 11:10:44.075491 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9832 11:10:44.078983 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9833 11:10:44.085379 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9834 11:10:44.088751 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9835 11:10:44.095357 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9836 11:10:44.098851 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9837 11:10:44.102309 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9838 11:10:44.108683 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9839 11:10:44.112083 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9840 11:10:44.118838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9841 11:10:44.122089 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9842 11:10:44.128674 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9843 11:10:44.131756 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9844 11:10:44.135296 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9845 11:10:44.141793 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9846 11:10:44.145084 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9847 11:10:44.151628 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9848 11:10:44.154982 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9849 11:10:44.158331 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9850 11:10:44.164742 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9851 11:10:44.168200 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9852 11:10:44.174730 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9853 11:10:44.178174 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9854 11:10:44.184603 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9855 11:10:44.187990 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9856 11:10:44.191290 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9857 11:10:44.197730 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9858 11:10:44.201212 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9859 11:10:44.207868 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9860 11:10:44.211243 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9861 11:10:44.217811 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9862 11:10:44.221286 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9863 11:10:44.227802 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9864 11:10:44.231242 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9865 11:10:44.234214 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9866 11:10:44.241026 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9867 11:10:44.244264 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9868 11:10:44.251070 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9869 11:10:44.254078 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9870 11:10:44.260696 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9871 11:10:44.264068 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9872 11:10:44.270535 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9873 11:10:44.273981 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9874 11:10:44.277280 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9875 11:10:44.283808 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9876 11:10:44.287205 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9877 11:10:44.293973 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9878 11:10:44.297300 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9879 11:10:44.303805 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9880 11:10:44.307218 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9881 11:10:44.310329 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9882 11:10:44.317009 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9883 11:10:44.320428 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9884 11:10:44.326849 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9885 11:10:44.330204 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9886 11:10:44.336791 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9887 11:10:44.339972 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9888 11:10:44.346781 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9889 11:10:44.350164 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9890 11:10:44.353215 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9891 11:10:44.359806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9892 11:10:44.363546 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9893 11:10:44.369944 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9894 11:10:44.373092 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9895 11:10:44.380039 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9896 11:10:44.383090 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9897 11:10:44.386818 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9898 11:10:44.393155 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9899 11:10:44.396651 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9900 11:10:44.403253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9901 11:10:44.406441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9902 11:10:44.409821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9903 11:10:44.416475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9904 11:10:44.419859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9905 11:10:44.426446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9906 11:10:44.429572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9907 11:10:44.436090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9908 11:10:44.439491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9909 11:10:44.446019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9910 11:10:44.449347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9911 11:10:44.456073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9912 11:10:44.459648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9913 11:10:44.466113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9914 11:10:44.469456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9915 11:10:44.475915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9916 11:10:44.479251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9917 11:10:44.485875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9918 11:10:44.489195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9919 11:10:44.495903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9920 11:10:44.499056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9921 11:10:44.505562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9922 11:10:44.508854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9923 11:10:44.515641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9924 11:10:44.518746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9925 11:10:44.525409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9926 11:10:44.528759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9927 11:10:44.535169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9928 11:10:44.538671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9929 11:10:44.545357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9930 11:10:44.548606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9931 11:10:44.555156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9932 11:10:44.558702 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9933 11:10:44.561969 INFO: [APUAPC] vio 0
9934 11:10:44.565303 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9935 11:10:44.571881 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9936 11:10:44.575034 INFO: [APUAPC] D0_APC_0: 0x400510
9937 11:10:44.578431 INFO: [APUAPC] D0_APC_1: 0x0
9938 11:10:44.578509 INFO: [APUAPC] D0_APC_2: 0x1540
9939 11:10:44.581603 INFO: [APUAPC] D0_APC_3: 0x0
9940 11:10:44.585060 INFO: [APUAPC] D1_APC_0: 0xffffffff
9941 11:10:44.588251 INFO: [APUAPC] D1_APC_1: 0xffffffff
9942 11:10:44.591620 INFO: [APUAPC] D1_APC_2: 0x3fffff
9943 11:10:44.595082 INFO: [APUAPC] D1_APC_3: 0x0
9944 11:10:44.598149 INFO: [APUAPC] D2_APC_0: 0xffffffff
9945 11:10:44.601353 INFO: [APUAPC] D2_APC_1: 0xffffffff
9946 11:10:44.604764 INFO: [APUAPC] D2_APC_2: 0x3fffff
9947 11:10:44.608200 INFO: [APUAPC] D2_APC_3: 0x0
9948 11:10:44.611311 INFO: [APUAPC] D3_APC_0: 0xffffffff
9949 11:10:44.614565 INFO: [APUAPC] D3_APC_1: 0xffffffff
9950 11:10:44.617903 INFO: [APUAPC] D3_APC_2: 0x3fffff
9951 11:10:44.621242 INFO: [APUAPC] D3_APC_3: 0x0
9952 11:10:44.624466 INFO: [APUAPC] D4_APC_0: 0xffffffff
9953 11:10:44.627718 INFO: [APUAPC] D4_APC_1: 0xffffffff
9954 11:10:44.631342 INFO: [APUAPC] D4_APC_2: 0x3fffff
9955 11:10:44.634521 INFO: [APUAPC] D4_APC_3: 0x0
9956 11:10:44.637785 INFO: [APUAPC] D5_APC_0: 0xffffffff
9957 11:10:44.641128 INFO: [APUAPC] D5_APC_1: 0xffffffff
9958 11:10:44.644440 INFO: [APUAPC] D5_APC_2: 0x3fffff
9959 11:10:44.647715 INFO: [APUAPC] D5_APC_3: 0x0
9960 11:10:44.650670 INFO: [APUAPC] D6_APC_0: 0xffffffff
9961 11:10:44.654090 INFO: [APUAPC] D6_APC_1: 0xffffffff
9962 11:10:44.657403 INFO: [APUAPC] D6_APC_2: 0x3fffff
9963 11:10:44.660738 INFO: [APUAPC] D6_APC_3: 0x0
9964 11:10:44.664082 INFO: [APUAPC] D7_APC_0: 0xffffffff
9965 11:10:44.667391 INFO: [APUAPC] D7_APC_1: 0xffffffff
9966 11:10:44.670861 INFO: [APUAPC] D7_APC_2: 0x3fffff
9967 11:10:44.674049 INFO: [APUAPC] D7_APC_3: 0x0
9968 11:10:44.677419 INFO: [APUAPC] D8_APC_0: 0xffffffff
9969 11:10:44.680537 INFO: [APUAPC] D8_APC_1: 0xffffffff
9970 11:10:44.684018 INFO: [APUAPC] D8_APC_2: 0x3fffff
9971 11:10:44.687258 INFO: [APUAPC] D8_APC_3: 0x0
9972 11:10:44.690607 INFO: [APUAPC] D9_APC_0: 0xffffffff
9973 11:10:44.693826 INFO: [APUAPC] D9_APC_1: 0xffffffff
9974 11:10:44.697146 INFO: [APUAPC] D9_APC_2: 0x3fffff
9975 11:10:44.700620 INFO: [APUAPC] D9_APC_3: 0x0
9976 11:10:44.703663 INFO: [APUAPC] D10_APC_0: 0xffffffff
9977 11:10:44.706984 INFO: [APUAPC] D10_APC_1: 0xffffffff
9978 11:10:44.710172 INFO: [APUAPC] D10_APC_2: 0x3fffff
9979 11:10:44.713598 INFO: [APUAPC] D10_APC_3: 0x0
9980 11:10:44.716562 INFO: [APUAPC] D11_APC_0: 0xffffffff
9981 11:10:44.720015 INFO: [APUAPC] D11_APC_1: 0xffffffff
9982 11:10:44.723314 INFO: [APUAPC] D11_APC_2: 0x3fffff
9983 11:10:44.726585 INFO: [APUAPC] D11_APC_3: 0x0
9984 11:10:44.730046 INFO: [APUAPC] D12_APC_0: 0xffffffff
9985 11:10:44.733353 INFO: [APUAPC] D12_APC_1: 0xffffffff
9986 11:10:44.736587 INFO: [APUAPC] D12_APC_2: 0x3fffff
9987 11:10:44.739700 INFO: [APUAPC] D12_APC_3: 0x0
9988 11:10:44.743082 INFO: [APUAPC] D13_APC_0: 0xffffffff
9989 11:10:44.746462 INFO: [APUAPC] D13_APC_1: 0xffffffff
9990 11:10:44.749852 INFO: [APUAPC] D13_APC_2: 0x3fffff
9991 11:10:44.753004 INFO: [APUAPC] D13_APC_3: 0x0
9992 11:10:44.756269 INFO: [APUAPC] D14_APC_0: 0xffffffff
9993 11:10:44.759568 INFO: [APUAPC] D14_APC_1: 0xffffffff
9994 11:10:44.762870 INFO: [APUAPC] D14_APC_2: 0x3fffff
9995 11:10:44.766224 INFO: [APUAPC] D14_APC_3: 0x0
9996 11:10:44.769639 INFO: [APUAPC] D15_APC_0: 0xffffffff
9997 11:10:44.772875 INFO: [APUAPC] D15_APC_1: 0xffffffff
9998 11:10:44.776230 INFO: [APUAPC] D15_APC_2: 0x3fffff
9999 11:10:44.779503 INFO: [APUAPC] D15_APC_3: 0x0
10000 11:10:44.782607 INFO: [APUAPC] APC_CON: 0x4
10001 11:10:44.786074 INFO: [NOCDAPC] D0_APC_0: 0x0
10002 11:10:44.789148 INFO: [NOCDAPC] D0_APC_1: 0x0
10003 11:10:44.792684 INFO: [NOCDAPC] D1_APC_0: 0x0
10004 11:10:44.795980 INFO: [NOCDAPC] D1_APC_1: 0xfff
10005 11:10:44.796064 INFO: [NOCDAPC] D2_APC_0: 0x0
10006 11:10:44.799245 INFO: [NOCDAPC] D2_APC_1: 0xfff
10007 11:10:44.802763 INFO: [NOCDAPC] D3_APC_0: 0x0
10008 11:10:44.805894 INFO: [NOCDAPC] D3_APC_1: 0xfff
10009 11:10:44.809114 INFO: [NOCDAPC] D4_APC_0: 0x0
10010 11:10:44.812586 INFO: [NOCDAPC] D4_APC_1: 0xfff
10011 11:10:44.815590 INFO: [NOCDAPC] D5_APC_0: 0x0
10012 11:10:44.819015 INFO: [NOCDAPC] D5_APC_1: 0xfff
10013 11:10:44.822294 INFO: [NOCDAPC] D6_APC_0: 0x0
10014 11:10:44.825442 INFO: [NOCDAPC] D6_APC_1: 0xfff
10015 11:10:44.828993 INFO: [NOCDAPC] D7_APC_0: 0x0
10016 11:10:44.832332 INFO: [NOCDAPC] D7_APC_1: 0xfff
10017 11:10:44.832415 INFO: [NOCDAPC] D8_APC_0: 0x0
10018 11:10:44.835416 INFO: [NOCDAPC] D8_APC_1: 0xfff
10019 11:10:44.838751 INFO: [NOCDAPC] D9_APC_0: 0x0
10020 11:10:44.842025 INFO: [NOCDAPC] D9_APC_1: 0xfff
10021 11:10:44.845341 INFO: [NOCDAPC] D10_APC_0: 0x0
10022 11:10:44.848712 INFO: [NOCDAPC] D10_APC_1: 0xfff
10023 11:10:44.852247 INFO: [NOCDAPC] D11_APC_0: 0x0
10024 11:10:44.855521 INFO: [NOCDAPC] D11_APC_1: 0xfff
10025 11:10:44.858695 INFO: [NOCDAPC] D12_APC_0: 0x0
10026 11:10:44.862008 INFO: [NOCDAPC] D12_APC_1: 0xfff
10027 11:10:44.865081 INFO: [NOCDAPC] D13_APC_0: 0x0
10028 11:10:44.868516 INFO: [NOCDAPC] D13_APC_1: 0xfff
10029 11:10:44.872076 INFO: [NOCDAPC] D14_APC_0: 0x0
10030 11:10:44.875105 INFO: [NOCDAPC] D14_APC_1: 0xfff
10031 11:10:44.878440 INFO: [NOCDAPC] D15_APC_0: 0x0
10032 11:10:44.881636 INFO: [NOCDAPC] D15_APC_1: 0xfff
10033 11:10:44.881718 INFO: [NOCDAPC] APC_CON: 0x4
10034 11:10:44.884667 INFO: [APUAPC] set_apusys_apc done
10035 11:10:44.888342 INFO: [DEVAPC] devapc_init done
10036 11:10:44.894736 INFO: GICv3 without legacy support detected.
10037 11:10:44.898555 INFO: ARM GICv3 driver initialized in EL3
10038 11:10:44.901410 INFO: Maximum SPI INTID supported: 639
10039 11:10:44.904892 INFO: BL31: Initializing runtime services
10040 11:10:44.911514 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10041 11:10:44.915051 INFO: SPM: enable CPC mode
10042 11:10:44.918157 INFO: mcdi ready for mcusys-off-idle and system suspend
10043 11:10:44.924904 INFO: BL31: Preparing for EL3 exit to normal world
10044 11:10:44.927860 INFO: Entry point address = 0x80000000
10045 11:10:44.927947 INFO: SPSR = 0x8
10046 11:10:44.934931
10047 11:10:44.935017
10048 11:10:44.935081
10049 11:10:44.938216 Starting depthcharge on Spherion...
10050 11:10:44.938298
10051 11:10:44.938362 Wipe memory regions:
10052 11:10:44.938422
10053 11:10:44.939142 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10054 11:10:44.939240 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10055 11:10:44.939318 Setting prompt string to ['asurada:']
10056 11:10:44.939396 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10057 11:10:44.941592 [0x00000040000000, 0x00000054600000)
10058 11:10:45.064023
10059 11:10:45.064171 [0x00000054660000, 0x00000080000000)
10060 11:10:45.324704
10061 11:10:45.324861 [0x000000821a7280, 0x000000ffe64000)
10062 11:10:46.069465
10063 11:10:46.069630 [0x00000100000000, 0x00000240000000)
10064 11:10:47.960046
10065 11:10:47.963137 Initializing XHCI USB controller at 0x11200000.
10066 11:10:49.000765
10067 11:10:49.003992 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10068 11:10:49.004094
10069 11:10:49.004160
10070 11:10:49.004220
10071 11:10:49.004498 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 11:10:49.104909 asurada: tftpboot 192.168.201.1 12925679/tftp-deploy-y7s_h0a2/kernel/image.itb 12925679/tftp-deploy-y7s_h0a2/kernel/cmdline
10074 11:10:49.105090 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10075 11:10:49.105197 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10076 11:10:49.109142 tftpboot 192.168.201.1 12925679/tftp-deploy-y7s_h0a2/kernel/image.itbtp-deploy-y7s_h0a2/kernel/cmdline
10077 11:10:49.109228
10078 11:10:49.109292 Waiting for link
10079 11:10:49.269831
10080 11:10:49.269984 R8152: Initializing
10081 11:10:49.270074
10082 11:10:49.272997 Version 6 (ocp_data = 5c30)
10083 11:10:49.273114
10084 11:10:49.276413 R8152: Done initializing
10085 11:10:49.276497
10086 11:10:49.276561 Adding net device
10087 11:10:51.180315
10088 11:10:51.180461 done.
10089 11:10:51.180529
10090 11:10:51.180589 MAC: 00:24:32:30:78:ff
10091 11:10:51.180646
10092 11:10:51.183648 Sending DHCP discover... done.
10093 11:10:51.183731
10094 11:10:51.187060 Waiting for reply... done.
10095 11:10:51.187168
10096 11:10:51.190047 Sending DHCP request... done.
10097 11:10:51.190129
10098 11:10:51.193411 Waiting for reply... done.
10099 11:10:51.193542
10100 11:10:51.193642 My ip is 192.168.201.21
10101 11:10:51.193706
10102 11:10:51.196817 The DHCP server ip is 192.168.201.1
10103 11:10:51.196898
10104 11:10:51.200040 TFTP server IP predefined by user: 192.168.201.1
10105 11:10:51.203361
10106 11:10:51.206695 Bootfile predefined by user: 12925679/tftp-deploy-y7s_h0a2/kernel/image.itb
10107 11:10:51.209805
10108 11:10:51.209886 Sending tftp read request... done.
10109 11:10:51.209951
10110 11:10:51.216517 Waiting for the transfer...
10111 11:10:51.216599
10112 11:10:51.871977 00000000 ################################################################
10113 11:10:51.872511
10114 11:10:52.625872 00080000 ################################################################
10115 11:10:52.626481
10116 11:10:53.362109 00100000 ################################################################
10117 11:10:53.362645
10118 11:10:54.060426 00180000 ################################################################
10119 11:10:54.060571
10120 11:10:54.615247 00200000 ################################################################
10121 11:10:54.615387
10122 11:10:55.147997 00280000 ################################################################
10123 11:10:55.148130
10124 11:10:55.676826 00300000 ################################################################
10125 11:10:55.676972
10126 11:10:56.196103 00380000 ################################################################
10127 11:10:56.196239
10128 11:10:56.718791 00400000 ################################################################
10129 11:10:56.718926
10130 11:10:57.258248 00480000 ################################################################
10131 11:10:57.258417
10132 11:10:57.925544 00500000 ################################################################
10133 11:10:57.926062
10134 11:10:58.487116 00580000 ################################################################
10135 11:10:58.487264
10136 11:10:59.031923 00600000 ################################################################
10137 11:10:59.032074
10138 11:10:59.568820 00680000 ################################################################
10139 11:10:59.568971
10140 11:11:00.109617 00700000 ################################################################
10141 11:11:00.109768
10142 11:11:00.658666 00780000 ################################################################
10143 11:11:00.658810
10144 11:11:01.203248 00800000 ################################################################
10145 11:11:01.203400
10146 11:11:01.828741 00880000 ################################################################
10147 11:11:01.829279
10148 11:11:02.386076 00900000 ################################################################
10149 11:11:02.386220
10150 11:11:02.925096 00980000 ################################################################
10151 11:11:02.925241
10152 11:11:03.463316 00a00000 ################################################################
10153 11:11:03.463459
10154 11:11:04.019331 00a80000 ################################################################
10155 11:11:04.019515
10156 11:11:04.569711 00b00000 ################################################################
10157 11:11:04.569847
10158 11:11:05.101998 00b80000 ################################################################
10159 11:11:05.102142
10160 11:11:05.690954 00c00000 ################################################################
10161 11:11:05.691464
10162 11:11:06.271222 00c80000 ################################################################
10163 11:11:06.271358
10164 11:11:06.816429 00d00000 ################################################################
10165 11:11:06.816578
10166 11:11:07.355601 00d80000 ################################################################
10167 11:11:07.355781
10168 11:11:07.896836 00e00000 ################################################################
10169 11:11:07.896988
10170 11:11:08.442724 00e80000 ################################################################
10171 11:11:08.442865
10172 11:11:08.985469 00f00000 ################################################################
10173 11:11:08.985662
10174 11:11:09.528463 00f80000 ################################################################
10175 11:11:09.528599
10176 11:11:10.068863 01000000 ################################################################
10177 11:11:10.069016
10178 11:11:10.600616 01080000 ################################################################
10179 11:11:10.600775
10180 11:11:11.128233 01100000 ################################################################
10181 11:11:11.128370
10182 11:11:11.667196 01180000 ################################################################
10183 11:11:11.667355
10184 11:11:12.198391 01200000 ################################################################
10185 11:11:12.198581
10186 11:11:12.730209 01280000 ################################################################
10187 11:11:12.730345
10188 11:11:13.271371 01300000 ################################################################
10189 11:11:13.271547
10190 11:11:13.809361 01380000 ################################################################
10191 11:11:13.809548
10192 11:11:14.351224 01400000 ################################################################
10193 11:11:14.351375
10194 11:11:14.891278 01480000 ################################################################
10195 11:11:14.891433
10196 11:11:15.429109 01500000 ################################################################
10197 11:11:15.429271
10198 11:11:15.967859 01580000 ################################################################
10199 11:11:15.967997
10200 11:11:16.509592 01600000 ################################################################
10201 11:11:16.509738
10202 11:11:17.045424 01680000 ################################################################
10203 11:11:17.045600
10204 11:11:17.582592 01700000 ################################################################
10205 11:11:17.582814
10206 11:11:18.119530 01780000 ################################################################
10207 11:11:18.119708
10208 11:11:18.646092 01800000 ################################################################
10209 11:11:18.646244
10210 11:11:19.189619 01880000 ################################################################
10211 11:11:19.189807
10212 11:11:19.711058 01900000 ################################################################
10213 11:11:19.711202
10214 11:11:20.237403 01980000 ################################################################
10215 11:11:20.237577
10216 11:11:20.780144 01a00000 ################################################################
10217 11:11:20.780299
10218 11:11:21.317692 01a80000 ################################################################
10219 11:11:21.317841
10220 11:11:21.871835 01b00000 ################################################################
10221 11:11:21.871978
10222 11:11:22.414024 01b80000 ################################################################
10223 11:11:22.414155
10224 11:11:22.947025 01c00000 ################################################################
10225 11:11:22.947173
10226 11:11:23.492475 01c80000 ################################################################
10227 11:11:23.492616
10228 11:11:24.034083 01d00000 ################################################################
10229 11:11:24.034260
10230 11:11:24.573682 01d80000 ################################################################
10231 11:11:24.573826
10232 11:11:25.107085 01e00000 ################################################################
10233 11:11:25.107251
10234 11:11:25.639925 01e80000 ################################################################
10235 11:11:25.640075
10236 11:11:26.177419 01f00000 ################################################################
10237 11:11:26.177610
10238 11:11:26.726157 01f80000 ################################################################
10239 11:11:26.726299
10240 11:11:27.259338 02000000 ################################################################
10241 11:11:27.259499
10242 11:11:27.802539 02080000 ################################################################
10243 11:11:27.802676
10244 11:11:28.337831 02100000 ################################################################
10245 11:11:28.337980
10246 11:11:28.872339 02180000 ################################################################
10247 11:11:28.872512
10248 11:11:29.423956 02200000 ################################################################
10249 11:11:29.424123
10250 11:11:29.957296 02280000 ################################################################
10251 11:11:29.957480
10252 11:11:30.488645 02300000 ################################################################
10253 11:11:30.488795
10254 11:11:31.028076 02380000 ################################################################
10255 11:11:31.028213
10256 11:11:31.561615 02400000 ################################################################
10257 11:11:31.561752
10258 11:11:32.101932 02480000 ################################################################
10259 11:11:32.102063
10260 11:11:32.637586 02500000 ################################################################
10261 11:11:32.637717
10262 11:11:33.167237 02580000 ################################################################
10263 11:11:33.167388
10264 11:11:33.702413 02600000 ################################################################
10265 11:11:33.702556
10266 11:11:34.245427 02680000 ################################################################
10267 11:11:34.245574
10268 11:11:34.783241 02700000 ################################################################
10269 11:11:34.783394
10270 11:11:35.322003 02780000 ################################################################
10271 11:11:35.322150
10272 11:11:35.861370 02800000 ################################################################
10273 11:11:35.861557
10274 11:11:36.419888 02880000 ################################################################
10275 11:11:36.420030
10276 11:11:36.962673 02900000 ################################################################
10277 11:11:36.962867
10278 11:11:37.505881 02980000 ################################################################
10279 11:11:37.506017
10280 11:11:38.061065 02a00000 ################################################################
10281 11:11:38.061203
10282 11:11:38.603853 02a80000 ################################################################
10283 11:11:38.604000
10284 11:11:39.145903 02b00000 ################################################################
10285 11:11:39.146062
10286 11:11:39.672738 02b80000 ################################################################
10287 11:11:39.672874
10288 11:11:40.189527 02c00000 ################################################################
10289 11:11:40.189662
10290 11:11:40.708441 02c80000 ################################################################
10291 11:11:40.708609
10292 11:11:41.241220 02d00000 ################################################################
10293 11:11:41.241362
10294 11:11:41.791947 02d80000 ################################################################
10295 11:11:41.792472
10296 11:11:42.338613 02e00000 ################################################################
10297 11:11:42.338751
10298 11:11:42.878683 02e80000 ################################################################
10299 11:11:42.878821
10300 11:11:43.426266 02f00000 ################################################################
10301 11:11:43.426418
10302 11:11:43.991045 02f80000 ################################################################
10303 11:11:43.991181
10304 11:11:44.575047 03000000 ################################################################
10305 11:11:44.575191
10306 11:11:45.159551 03080000 ################################################################
10307 11:11:45.159684
10308 11:11:45.743325 03100000 ################################################################
10309 11:11:45.743471
10310 11:11:46.286566 03180000 ################################################################
10311 11:11:46.286710
10312 11:11:46.832560 03200000 ################################################################
10313 11:11:46.832695
10314 11:11:47.385471 03280000 ################################################################
10315 11:11:47.385682
10316 11:11:47.945071 03300000 ################################################################
10317 11:11:47.945225
10318 11:11:48.503435 03380000 ################################################################
10319 11:11:48.503585
10320 11:11:49.060425 03400000 ################################################################
10321 11:11:49.060625
10322 11:11:49.611705 03480000 ################################################################
10323 11:11:49.611850
10324 11:11:50.160303 03500000 ################################################################
10325 11:11:50.160437
10326 11:11:50.723338 03580000 ################################################################
10327 11:11:50.723482
10328 11:11:51.266438 03600000 ################################################################
10329 11:11:51.266588
10330 11:11:51.824967 03680000 ################################################################
10331 11:11:51.825120
10332 11:11:52.384665 03700000 ################################################################
10333 11:11:52.384808
10334 11:11:52.946657 03780000 ################################################################
10335 11:11:52.946801
10336 11:11:53.491244 03800000 ################################################################
10337 11:11:53.491395
10338 11:11:53.918913 03880000 ################################################ done.
10339 11:11:53.919065
10340 11:11:53.922395 The bootfile was 59636722 bytes long.
10341 11:11:53.922486
10342 11:11:53.925428 Sending tftp read request... done.
10343 11:11:53.925531
10344 11:11:53.925607 Waiting for the transfer...
10345 11:11:53.925676
10346 11:11:53.928954 00000000 # done.
10347 11:11:53.929049
10348 11:11:53.935474 Command line loaded dynamically from TFTP file: 12925679/tftp-deploy-y7s_h0a2/kernel/cmdline
10349 11:11:53.935665
10350 11:11:53.948939 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10351 11:11:53.949161
10352 11:11:53.952391 Loading FIT.
10353 11:11:53.952565
10354 11:11:53.955300 Image ramdisk-1 has 47529709 bytes.
10355 11:11:53.955464
10356 11:11:53.955594 Image fdt-1 has 47278 bytes.
10357 11:11:53.958885
10358 11:11:53.959119 Image kernel-1 has 12057697 bytes.
10359 11:11:53.959327
10360 11:11:53.968776 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10361 11:11:53.969005
10362 11:11:53.985510 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10363 11:11:53.985734
10364 11:11:53.991906 Choosing best match conf-1 for compat google,spherion-rev2.
10365 11:11:53.996294
10366 11:11:54.001089 Connected to device vid:did:rid of 1ae0:0028:00
10367 11:11:54.007796
10368 11:11:54.011263 tpm_get_response: command 0x17b, return code 0x0
10369 11:11:54.011675
10370 11:11:54.014526 ec_init: CrosEC protocol v3 supported (256, 248)
10371 11:11:54.018804
10372 11:11:54.021821 tpm_cleanup: add release locality here.
10373 11:11:54.022284
10374 11:11:54.022644 Shutting down all USB controllers.
10375 11:11:54.025379
10376 11:11:54.025892 Removing current net device
10377 11:11:54.026261
10378 11:11:54.032184 Exiting depthcharge with code 4 at timestamp: 98461034
10379 11:11:54.032650
10380 11:11:54.035277 LZMA decompressing kernel-1 to 0x821a6718
10381 11:11:54.035781
10382 11:11:54.038641 LZMA decompressing kernel-1 to 0x40000000
10383 11:11:55.538317
10384 11:11:55.538453 jumping to kernel
10385 11:11:55.538972 end: 2.2.4 bootloader-commands (duration 00:01:11) [common]
10386 11:11:55.539071 start: 2.2.5 auto-login-action (timeout 00:03:15) [common]
10387 11:11:55.539147 Setting prompt string to ['Linux version [0-9]']
10388 11:11:55.539214 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10389 11:11:55.539280 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10390 11:11:55.620126
10391 11:11:55.623429 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10392 11:11:55.626694 start: 2.2.5.1 login-action (timeout 00:03:14) [common]
10393 11:11:55.626840 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10394 11:11:55.626912 Setting prompt string to []
10395 11:11:55.627024 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10396 11:11:55.627098 Using line separator: #'\n'#
10397 11:11:55.627157 No login prompt set.
10398 11:11:55.627220 Parsing kernel messages
10399 11:11:55.627274 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10400 11:11:55.627374 [login-action] Waiting for messages, (timeout 00:03:14)
10401 11:11:55.627438 Waiting using forced prompt support (timeout 00:01:37)
10402 11:11:55.646359 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10403 11:11:55.649670 [ 0.000000] random: crng init done
10404 11:11:55.656273 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10405 11:11:55.659572 [ 0.000000] efi: UEFI not found.
10406 11:11:55.666589 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10407 11:11:55.672839 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10408 11:11:55.682853 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10409 11:11:55.692816 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10410 11:11:55.699331 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10411 11:11:55.705780 [ 0.000000] printk: bootconsole [mtk8250] enabled
10412 11:11:55.712407 [ 0.000000] NUMA: No NUMA configuration found
10413 11:11:55.719141 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10414 11:11:55.722448 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10415 11:11:55.725453 [ 0.000000] Zone ranges:
10416 11:11:55.732140 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10417 11:11:55.735473 [ 0.000000] DMA32 empty
10418 11:11:55.742108 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10419 11:11:55.745447 [ 0.000000] Movable zone start for each node
10420 11:11:55.748683 [ 0.000000] Early memory node ranges
10421 11:11:55.755551 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10422 11:11:55.762114 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10423 11:11:55.768493 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10424 11:11:55.775293 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10425 11:11:55.781669 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10426 11:11:55.788334 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10427 11:11:55.844680 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10428 11:11:55.851035 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10429 11:11:55.857760 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10430 11:11:55.861074 [ 0.000000] psci: probing for conduit method from DT.
10431 11:11:55.867740 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10432 11:11:55.871065 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10433 11:11:55.877999 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10434 11:11:55.881038 [ 0.000000] psci: SMC Calling Convention v1.2
10435 11:11:55.887408 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10436 11:11:55.891069 [ 0.000000] Detected VIPT I-cache on CPU0
10437 11:11:55.897373 [ 0.000000] CPU features: detected: GIC system register CPU interface
10438 11:11:55.904153 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10439 11:11:55.910612 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10440 11:11:55.917432 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10441 11:11:55.924109 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10442 11:11:55.933806 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10443 11:11:55.937225 [ 0.000000] alternatives: applying boot alternatives
10444 11:11:55.943706 [ 0.000000] Fallback order for Node 0: 0
10445 11:11:55.950377 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10446 11:11:55.953831 [ 0.000000] Policy zone: Normal
10447 11:11:55.967173 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10448 11:11:55.977259 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10449 11:11:55.987804 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10450 11:11:55.997625 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10451 11:11:56.004290 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10452 11:11:56.007641 <6>[ 0.000000] software IO TLB: area num 8.
10453 11:11:56.064228 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10454 11:11:56.213315 <6>[ 0.000000] Memory: 7920776K/8385536K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 431992K reserved, 32768K cma-reserved)
10455 11:11:56.220003 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10456 11:11:56.226827 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10457 11:11:56.229864 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10458 11:11:56.236643 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10459 11:11:56.243300 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10460 11:11:56.246259 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10461 11:11:56.256419 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10462 11:11:56.263090 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10463 11:11:56.269481 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10464 11:11:56.276200 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10465 11:11:56.279233 <6>[ 0.000000] GICv3: 608 SPIs implemented
10466 11:11:56.282743 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10467 11:11:56.289212 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10468 11:11:56.292574 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10469 11:11:56.299111 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10470 11:11:56.312397 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10471 11:11:56.325781 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10472 11:11:56.332201 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10473 11:11:56.340011 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10474 11:11:56.353431 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10475 11:11:56.360134 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10476 11:11:56.366667 <6>[ 0.009183] Console: colour dummy device 80x25
10477 11:11:56.376517 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10478 11:11:56.383354 <6>[ 0.024354] pid_max: default: 32768 minimum: 301
10479 11:11:56.386611 <6>[ 0.029249] LSM: Security Framework initializing
10480 11:11:56.393273 <6>[ 0.034187] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10481 11:11:56.403296 <6>[ 0.042002] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10482 11:11:56.409611 <6>[ 0.051427] cblist_init_generic: Setting adjustable number of callback queues.
10483 11:11:56.416257 <6>[ 0.058871] cblist_init_generic: Setting shift to 3 and lim to 1.
10484 11:11:56.426083 <6>[ 0.065211] cblist_init_generic: Setting adjustable number of callback queues.
10485 11:11:56.432904 <6>[ 0.072638] cblist_init_generic: Setting shift to 3 and lim to 1.
10486 11:11:56.436212 <6>[ 0.079038] rcu: Hierarchical SRCU implementation.
10487 11:11:56.442506 <6>[ 0.084054] rcu: Max phase no-delay instances is 1000.
10488 11:11:56.449052 <6>[ 0.091118] EFI services will not be available.
10489 11:11:56.452471 <6>[ 0.096049] smp: Bringing up secondary CPUs ...
10490 11:11:56.460831 <6>[ 0.101101] Detected VIPT I-cache on CPU1
10491 11:11:56.467318 <6>[ 0.101169] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10492 11:11:56.473875 <6>[ 0.101204] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10493 11:11:56.477260 <6>[ 0.101540] Detected VIPT I-cache on CPU2
10494 11:11:56.483777 <6>[ 0.101589] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10495 11:11:56.493835 <6>[ 0.101607] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10496 11:11:56.497247 <6>[ 0.101866] Detected VIPT I-cache on CPU3
10497 11:11:56.503953 <6>[ 0.101913] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10498 11:11:56.510495 <6>[ 0.101927] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10499 11:11:56.513815 <6>[ 0.102234] CPU features: detected: Spectre-v4
10500 11:11:56.520294 <6>[ 0.102240] CPU features: detected: Spectre-BHB
10501 11:11:56.523526 <6>[ 0.102245] Detected PIPT I-cache on CPU4
10502 11:11:56.530187 <6>[ 0.102305] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10503 11:11:56.536684 <6>[ 0.102322] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10504 11:11:56.543293 <6>[ 0.102622] Detected PIPT I-cache on CPU5
10505 11:11:56.550079 <6>[ 0.102684] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10506 11:11:56.556891 <6>[ 0.102700] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10507 11:11:56.559981 <6>[ 0.102983] Detected PIPT I-cache on CPU6
10508 11:11:56.566759 <6>[ 0.103048] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10509 11:11:56.573111 <6>[ 0.103064] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10510 11:11:56.580095 <6>[ 0.103362] Detected PIPT I-cache on CPU7
10511 11:11:56.586460 <6>[ 0.103427] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10512 11:11:56.593074 <6>[ 0.103443] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10513 11:11:56.596546 <6>[ 0.103491] smp: Brought up 1 node, 8 CPUs
10514 11:11:56.603171 <6>[ 0.244821] SMP: Total of 8 processors activated.
10515 11:11:56.606198 <6>[ 0.249742] CPU features: detected: 32-bit EL0 Support
10516 11:11:56.616204 <6>[ 0.255105] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10517 11:11:56.622689 <6>[ 0.263906] CPU features: detected: Common not Private translations
10518 11:11:56.629490 <6>[ 0.270393] CPU features: detected: CRC32 instructions
10519 11:11:56.632741 <6>[ 0.275745] CPU features: detected: RCpc load-acquire (LDAPR)
10520 11:11:56.639413 <6>[ 0.281705] CPU features: detected: LSE atomic instructions
10521 11:11:56.646203 <6>[ 0.287522] CPU features: detected: Privileged Access Never
10522 11:11:56.652688 <6>[ 0.293301] CPU features: detected: RAS Extension Support
10523 11:11:56.659391 <6>[ 0.298910] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10524 11:11:56.662480 <6>[ 0.306174] CPU: All CPU(s) started at EL2
10525 11:11:56.669316 <6>[ 0.310491] alternatives: applying system-wide alternatives
10526 11:11:56.678330 <6>[ 0.321296] devtmpfs: initialized
10527 11:11:56.694330 <6>[ 0.330263] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10528 11:11:56.700576 <6>[ 0.340226] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10529 11:11:56.707183 <6>[ 0.347930] pinctrl core: initialized pinctrl subsystem
10530 11:11:56.710633 <6>[ 0.354605] DMI not present or invalid.
10531 11:11:56.717161 <6>[ 0.359015] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10532 11:11:56.726862 <6>[ 0.365867] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10533 11:11:56.733757 <6>[ 0.373458] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10534 11:11:56.743689 <6>[ 0.381676] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10535 11:11:56.746728 <6>[ 0.389919] audit: initializing netlink subsys (disabled)
10536 11:11:56.756735 <5>[ 0.395612] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10537 11:11:56.763724 <6>[ 0.396324] thermal_sys: Registered thermal governor 'step_wise'
10538 11:11:56.769934 <6>[ 0.403581] thermal_sys: Registered thermal governor 'power_allocator'
10539 11:11:56.773378 <6>[ 0.409840] cpuidle: using governor menu
10540 11:11:56.780254 <6>[ 0.420799] NET: Registered PF_QIPCRTR protocol family
10541 11:11:56.786843 <6>[ 0.426273] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10542 11:11:56.789983 <6>[ 0.433378] ASID allocator initialised with 32768 entries
10543 11:11:56.797308 <6>[ 0.439954] Serial: AMBA PL011 UART driver
10544 11:11:56.805944 <4>[ 0.448719] Trying to register duplicate clock ID: 134
10545 11:11:56.860714 <6>[ 0.506352] KASLR enabled
10546 11:11:56.874916 <6>[ 0.514244] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10547 11:11:56.881597 <6>[ 0.521261] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10548 11:11:56.888296 <6>[ 0.527751] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10549 11:11:56.894980 <6>[ 0.534758] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10550 11:11:56.901382 <6>[ 0.541245] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10551 11:11:56.908227 <6>[ 0.548251] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10552 11:11:56.915045 <6>[ 0.554741] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10553 11:11:56.921586 <6>[ 0.561745] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10554 11:11:56.924800 <6>[ 0.569268] ACPI: Interpreter disabled.
10555 11:11:56.933327 <6>[ 0.575686] iommu: Default domain type: Translated
10556 11:11:56.940096 <6>[ 0.580798] iommu: DMA domain TLB invalidation policy: strict mode
10557 11:11:56.943135 <5>[ 0.587459] SCSI subsystem initialized
10558 11:11:56.949711 <6>[ 0.591627] usbcore: registered new interface driver usbfs
10559 11:11:56.955845 <6>[ 0.597360] usbcore: registered new interface driver hub
10560 11:11:56.959393 <6>[ 0.602914] usbcore: registered new device driver usb
10561 11:11:56.966284 <6>[ 0.609011] pps_core: LinuxPPS API ver. 1 registered
10562 11:11:56.976169 <6>[ 0.614205] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10563 11:11:56.979502 <6>[ 0.623552] PTP clock support registered
10564 11:11:56.982755 <6>[ 0.627795] EDAC MC: Ver: 3.0.0
10565 11:11:56.990228 <6>[ 0.632951] FPGA manager framework
10566 11:11:56.996935 <6>[ 0.636628] Advanced Linux Sound Architecture Driver Initialized.
10567 11:11:57.000081 <6>[ 0.643409] vgaarb: loaded
10568 11:11:57.006560 <6>[ 0.646570] clocksource: Switched to clocksource arch_sys_counter
10569 11:11:57.009844 <5>[ 0.653007] VFS: Disk quotas dquot_6.6.0
10570 11:11:57.016323 <6>[ 0.657195] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10571 11:11:57.019878 <6>[ 0.664386] pnp: PnP ACPI: disabled
10572 11:11:57.028197 <6>[ 0.671065] NET: Registered PF_INET protocol family
10573 11:11:57.038081 <6>[ 0.676653] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10574 11:11:57.049257 <6>[ 0.688927] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10575 11:11:57.059220 <6>[ 0.697741] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10576 11:11:57.065891 <6>[ 0.705711] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10577 11:11:57.075846 <6>[ 0.714411] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10578 11:11:57.082561 <6>[ 0.724161] TCP: Hash tables configured (established 65536 bind 65536)
10579 11:11:57.088850 <6>[ 0.731022] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10580 11:11:57.098776 <6>[ 0.738217] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10581 11:11:57.105362 <6>[ 0.745918] NET: Registered PF_UNIX/PF_LOCAL protocol family
10582 11:11:57.112031 <6>[ 0.752089] RPC: Registered named UNIX socket transport module.
10583 11:11:57.115266 <6>[ 0.758243] RPC: Registered udp transport module.
10584 11:11:57.121856 <6>[ 0.763176] RPC: Registered tcp transport module.
10585 11:11:57.128671 <6>[ 0.768110] RPC: Registered tcp NFSv4.1 backchannel transport module.
10586 11:11:57.131799 <6>[ 0.774781] PCI: CLS 0 bytes, default 64
10587 11:11:57.134857 <6>[ 0.779185] Unpacking initramfs...
10588 11:11:57.152194 <6>[ 0.791236] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10589 11:11:57.161749 <6>[ 0.799885] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10590 11:11:57.164867 <6>[ 0.808739] kvm [1]: IPA Size Limit: 40 bits
10591 11:11:57.171452 <6>[ 0.813266] kvm [1]: GICv3: no GICV resource entry
10592 11:11:57.174788 <6>[ 0.818287] kvm [1]: disabling GICv2 emulation
10593 11:11:57.181286 <6>[ 0.822975] kvm [1]: GIC system register CPU interface enabled
10594 11:11:57.187975 <6>[ 0.830616] kvm [1]: vgic interrupt IRQ18
10595 11:11:57.191220 <6>[ 0.835024] kvm [1]: VHE mode initialized successfully
10596 11:11:57.198775 <5>[ 0.841433] Initialise system trusted keyrings
10597 11:11:57.205014 <6>[ 0.846218] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10598 11:11:57.213885 <6>[ 0.856438] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10599 11:11:57.220236 <5>[ 0.862854] NFS: Registering the id_resolver key type
10600 11:11:57.223724 <5>[ 0.868159] Key type id_resolver registered
10601 11:11:57.230048 <5>[ 0.872575] Key type id_legacy registered
10602 11:11:57.236880 <6>[ 0.876851] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10603 11:11:57.243242 <6>[ 0.883770] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10604 11:11:57.249924 <6>[ 0.891499] 9p: Installing v9fs 9p2000 file system support
10605 11:11:57.285952 <5>[ 0.928797] Key type asymmetric registered
10606 11:11:57.289351 <5>[ 0.933127] Asymmetric key parser 'x509' registered
10607 11:11:57.299313 <6>[ 0.938261] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10608 11:11:57.302542 <6>[ 0.945872] io scheduler mq-deadline registered
10609 11:11:57.305846 <6>[ 0.950651] io scheduler kyber registered
10610 11:11:57.324850 <6>[ 0.967597] EINJ: ACPI disabled.
10611 11:11:57.356644 <4>[ 0.993006] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10612 11:11:57.366836 <4>[ 1.003652] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10613 11:11:57.381221 <6>[ 1.024113] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10614 11:11:57.389260 <6>[ 1.032109] printk: console [ttyS0] disabled
10615 11:11:57.417250 <6>[ 1.056740] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10616 11:11:57.423736 <6>[ 1.066212] printk: console [ttyS0] enabled
10617 11:11:57.427036 <6>[ 1.066212] printk: console [ttyS0] enabled
10618 11:11:57.433926 <6>[ 1.075105] printk: bootconsole [mtk8250] disabled
10619 11:11:57.436910 <6>[ 1.075105] printk: bootconsole [mtk8250] disabled
10620 11:11:57.443904 <6>[ 1.086137] SuperH (H)SCI(F) driver initialized
10621 11:11:57.446903 <6>[ 1.091412] msm_serial: driver initialized
10622 11:11:57.460801 <6>[ 1.100353] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10623 11:11:57.470985 <6>[ 1.108898] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10624 11:11:57.477618 <6>[ 1.117441] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10625 11:11:57.487245 <6>[ 1.126069] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10626 11:11:57.494081 <6>[ 1.134776] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10627 11:11:57.504101 <6>[ 1.143494] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10628 11:11:57.513994 <6>[ 1.152033] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10629 11:11:57.520618 <6>[ 1.160823] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10630 11:11:57.530297 <6>[ 1.169364] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10631 11:11:57.542229 <6>[ 1.184973] loop: module loaded
10632 11:11:57.548717 <6>[ 1.190819] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10633 11:11:57.571213 <4>[ 1.213965] mtk-pmic-keys: Failed to locate of_node [id: -1]
10634 11:11:57.577821 <6>[ 1.220731] megasas: 07.719.03.00-rc1
10635 11:11:57.587557 <6>[ 1.230367] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10636 11:11:57.595081 <6>[ 1.237943] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10637 11:11:57.611792 <6>[ 1.254401] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10638 11:11:57.667230 <6>[ 1.303568] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10639 11:11:59.161945 <6>[ 2.804856] Freeing initrd memory: 46412K
10640 11:11:59.171961 <6>[ 2.814998] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10641 11:11:59.183042 <6>[ 2.826094] tun: Universal TUN/TAP device driver, 1.6
10642 11:11:59.186235 <6>[ 2.832172] thunder_xcv, ver 1.0
10643 11:11:59.189695 <6>[ 2.835677] thunder_bgx, ver 1.0
10644 11:11:59.192881 <6>[ 2.839174] nicpf, ver 1.0
10645 11:11:59.203621 <6>[ 2.843205] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10646 11:11:59.206855 <6>[ 2.850682] hns3: Copyright (c) 2017 Huawei Corporation.
10647 11:11:59.213502 <6>[ 2.856270] hclge is initializing
10648 11:11:59.216765 <6>[ 2.859849] e1000: Intel(R) PRO/1000 Network Driver
10649 11:11:59.223372 <6>[ 2.864978] e1000: Copyright (c) 1999-2006 Intel Corporation.
10650 11:11:59.226743 <6>[ 2.870995] e1000e: Intel(R) PRO/1000 Network Driver
10651 11:11:59.233364 <6>[ 2.876209] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10652 11:11:59.239963 <6>[ 2.882396] igb: Intel(R) Gigabit Ethernet Network Driver
10653 11:11:59.246819 <6>[ 2.888045] igb: Copyright (c) 2007-2014 Intel Corporation.
10654 11:11:59.253363 <6>[ 2.893897] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10655 11:11:59.259765 <6>[ 2.900415] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10656 11:11:59.263142 <6>[ 2.906883] sky2: driver version 1.30
10657 11:11:59.269671 <6>[ 2.911875] VFIO - User Level meta-driver version: 0.3
10658 11:11:59.277018 <6>[ 2.920130] usbcore: registered new interface driver usb-storage
10659 11:11:59.283801 <6>[ 2.926582] usbcore: registered new device driver onboard-usb-hub
10660 11:11:59.292761 <6>[ 2.935804] mt6397-rtc mt6359-rtc: registered as rtc0
10661 11:11:59.302758 <6>[ 2.941299] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:11:59 UTC (1709464319)
10662 11:11:59.305900 <6>[ 2.950925] i2c_dev: i2c /dev entries driver
10663 11:11:59.322785 <6>[ 2.962731] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10664 11:11:59.342743 <6>[ 2.985734] cpu cpu0: EM: created perf domain
10665 11:11:59.346118 <6>[ 2.990680] cpu cpu4: EM: created perf domain
10666 11:11:59.352974 <6>[ 2.996088] sdhci: Secure Digital Host Controller Interface driver
10667 11:11:59.359592 <6>[ 3.002520] sdhci: Copyright(c) Pierre Ossman
10668 11:11:59.366581 <6>[ 3.007489] Synopsys Designware Multimedia Card Interface Driver
10669 11:11:59.373225 <6>[ 3.014124] sdhci-pltfm: SDHCI platform and OF driver helper
10670 11:11:59.376160 <6>[ 3.014148] mmc0: CQHCI version 5.10
10671 11:11:59.382695 <6>[ 3.024164] ledtrig-cpu: registered to indicate activity on CPUs
10672 11:11:59.389668 <6>[ 3.031222] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10673 11:11:59.396150 <6>[ 3.038286] usbcore: registered new interface driver usbhid
10674 11:11:59.399416 <6>[ 3.044109] usbhid: USB HID core driver
10675 11:11:59.406074 <6>[ 3.048309] spi_master spi0: will run message pump with realtime priority
10676 11:11:59.449432 <6>[ 3.085838] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10677 11:11:59.468180 <6>[ 3.100877] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10678 11:11:59.475088 <6>[ 3.115751] cros-ec-spi spi0.0: Chrome EC device registered
10679 11:11:59.478632 <6>[ 3.121814] mmc0: Command Queue Engine enabled
10680 11:11:59.485181 <6>[ 3.126605] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10681 11:11:59.491774 <6>[ 3.134138] mmcblk0: mmc0:0001 DA4128 116 GiB
10682 11:11:59.501579 <6>[ 3.134622] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10683 11:11:59.504720 <6>[ 3.143961] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10684 11:11:59.511464 <6>[ 3.149218] NET: Registered PF_PACKET protocol family
10685 11:11:59.518132 <6>[ 3.155089] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10686 11:11:59.521501 <6>[ 3.159451] 9pnet: Installing 9P2000 support
10687 11:11:59.524525 <6>[ 3.165321] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10688 11:11:59.531226 <5>[ 3.169161] Key type dns_resolver registered
10689 11:11:59.538016 <6>[ 3.175149] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10690 11:11:59.541135 <6>[ 3.179352] registered taskstats version 1
10691 11:11:59.547658 <5>[ 3.189762] Loading compiled-in X.509 certificates
10692 11:11:59.576199 <4>[ 3.212543] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10693 11:11:59.586079 <4>[ 3.223221] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10694 11:11:59.592785 <3>[ 3.233750] debugfs: File 'uA_load' in directory '/' already present!
10695 11:11:59.599343 <3>[ 3.240450] debugfs: File 'min_uV' in directory '/' already present!
10696 11:11:59.605862 <3>[ 3.247113] debugfs: File 'max_uV' in directory '/' already present!
10697 11:11:59.612815 <3>[ 3.253727] debugfs: File 'constraint_flags' in directory '/' already present!
10698 11:11:59.623750 <3>[ 3.263285] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10699 11:11:59.632084 <6>[ 3.275258] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10700 11:11:59.639139 <6>[ 3.282087] xhci-mtk 11200000.usb: xHCI Host Controller
10701 11:11:59.645553 <6>[ 3.287583] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10702 11:11:59.655823 <6>[ 3.295437] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10703 11:11:59.662585 <6>[ 3.304854] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10704 11:11:59.668818 <6>[ 3.310932] xhci-mtk 11200000.usb: xHCI Host Controller
10705 11:11:59.675697 <6>[ 3.316408] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10706 11:11:59.682389 <6>[ 3.324057] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10707 11:11:59.688772 <6>[ 3.331725] hub 1-0:1.0: USB hub found
10708 11:11:59.692121 <6>[ 3.335736] hub 1-0:1.0: 1 port detected
10709 11:11:59.698816 <6>[ 3.339997] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10710 11:11:59.705435 <6>[ 3.348555] hub 2-0:1.0: USB hub found
10711 11:11:59.708569 <6>[ 3.352561] hub 2-0:1.0: 1 port detected
10712 11:11:59.716249 <6>[ 3.359503] mtk-msdc 11f70000.mmc: Got CD GPIO
10713 11:11:59.727649 <6>[ 3.367502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10714 11:11:59.734276 <6>[ 3.375525] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10715 11:11:59.744146 <4>[ 3.383430] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10716 11:11:59.754138 <6>[ 3.392954] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10717 11:11:59.760634 <6>[ 3.401032] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10718 11:11:59.767326 <6>[ 3.409147] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10719 11:11:59.777361 <6>[ 3.417084] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10720 11:11:59.783819 <6>[ 3.424902] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10721 11:11:59.793696 <6>[ 3.432718] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10722 11:11:59.803810 <6>[ 3.443364] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10723 11:11:59.813422 <6>[ 3.451742] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10724 11:11:59.820020 <6>[ 3.460080] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10725 11:11:59.830020 <6>[ 3.468417] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10726 11:11:59.836857 <6>[ 3.476755] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10727 11:11:59.846534 <6>[ 3.485094] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10728 11:11:59.853207 <6>[ 3.493440] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10729 11:11:59.863036 <6>[ 3.501779] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10730 11:11:59.869832 <6>[ 3.510116] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10731 11:11:59.879676 <6>[ 3.518466] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10732 11:11:59.886453 <6>[ 3.526807] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10733 11:11:59.896248 <6>[ 3.535145] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10734 11:11:59.902853 <6>[ 3.543482] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10735 11:11:59.912520 <6>[ 3.551820] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10736 11:11:59.919363 <6>[ 3.560158] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10737 11:11:59.925837 <6>[ 3.568921] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10738 11:11:59.933241 <6>[ 3.576067] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10739 11:11:59.939813 <6>[ 3.582827] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10740 11:11:59.949758 <6>[ 3.589589] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10741 11:11:59.956271 <6>[ 3.596559] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10742 11:11:59.962968 <6>[ 3.603404] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10743 11:11:59.972745 <6>[ 3.612532] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10744 11:11:59.982814 <6>[ 3.621652] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10745 11:11:59.992665 <6>[ 3.630952] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10746 11:12:00.002624 <6>[ 3.640419] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10747 11:12:00.012487 <6>[ 3.649886] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10748 11:12:00.019118 <6>[ 3.659005] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10749 11:12:00.028909 <6>[ 3.668472] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10750 11:12:00.038842 <6>[ 3.677591] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10751 11:12:00.048776 <6>[ 3.686885] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10752 11:12:00.058737 <6>[ 3.697045] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10753 11:12:00.069253 <6>[ 3.708974] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10754 11:12:00.099499 <6>[ 3.739224] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10755 11:12:00.127225 <6>[ 3.770352] hub 2-1:1.0: USB hub found
10756 11:12:00.130401 <6>[ 3.774811] hub 2-1:1.0: 3 ports detected
10757 11:12:00.139005 <6>[ 3.782052] hub 2-1:1.0: USB hub found
10758 11:12:00.142151 <6>[ 3.786432] hub 2-1:1.0: 3 ports detected
10759 11:12:00.251201 <6>[ 3.890844] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10760 11:12:00.405708 <6>[ 4.048818] hub 1-1:1.0: USB hub found
10761 11:12:00.408941 <6>[ 4.053222] hub 1-1:1.0: 4 ports detected
10762 11:12:00.417692 <6>[ 4.060718] hub 1-1:1.0: USB hub found
10763 11:12:00.420753 <6>[ 4.065094] hub 1-1:1.0: 4 ports detected
10764 11:12:00.482831 <6>[ 4.122770] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10765 11:12:00.743118 <6>[ 4.382884] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10766 11:12:00.875674 <6>[ 4.518841] hub 1-1.4:1.0: USB hub found
10767 11:12:00.878804 <6>[ 4.523518] hub 1-1.4:1.0: 2 ports detected
10768 11:12:00.888830 <6>[ 4.531933] hub 1-1.4:1.0: USB hub found
10769 11:12:00.891828 <6>[ 4.536523] hub 1-1.4:1.0: 2 ports detected
10770 11:12:01.190714 <6>[ 4.830859] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10771 11:12:01.382589 <6>[ 5.022837] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10772 11:12:12.368162 <6>[ 16.015880] ALSA device list:
10773 11:12:12.374642 <6>[ 16.019170] No soundcards found.
10774 11:12:12.382664 <6>[ 16.027199] Freeing unused kernel memory: 8448K
10775 11:12:12.386076 <6>[ 16.032578] Run /init as init process
10776 11:12:12.415212 <6>[ 16.059493] NET: Registered PF_INET6 protocol family
10777 11:12:12.421456 <6>[ 16.065893] Segment Routing with IPv6
10778 11:12:12.424927 <6>[ 16.069858] In-situ OAM (IOAM) with IPv6
10779 11:12:12.457641 <30>[ 16.082202] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10780 11:12:12.460658 <30>[ 16.105798] systemd[1]: Detected architecture arm64.
10781 11:12:12.460752
10782 11:12:12.467465 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10783 11:12:12.467542
10784 11:12:12.486459 <30>[ 16.130921] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10785 11:12:12.570757 <30>[ 16.212099] systemd[1]: Queued start job for default target Graphical Interface.
10786 11:12:12.599253 <30>[ 16.243603] systemd[1]: Created slice system-getty.slice.
10787 11:12:12.605868 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10788 11:12:12.622778 <30>[ 16.267290] systemd[1]: Created slice system-modprobe.slice.
10789 11:12:12.629425 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10790 11:12:12.647360 <30>[ 16.291870] systemd[1]: Created slice system-serial\x2dgetty.slice.
10791 11:12:12.657619 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10792 11:12:12.670945 <30>[ 16.315321] systemd[1]: Created slice User and Session Slice.
10793 11:12:12.677370 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10794 11:12:12.698181 <30>[ 16.339458] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10795 11:12:12.708038 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10796 11:12:12.726122 <30>[ 16.367398] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10797 11:12:12.732786 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10798 11:12:12.757256 <30>[ 16.395296] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10799 11:12:12.764234 <30>[ 16.407543] systemd[1]: Reached target Local Encrypted Volumes.
10800 11:12:12.770737 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10801 11:12:12.786901 <30>[ 16.431305] systemd[1]: Reached target Paths.
10802 11:12:12.793211 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10803 11:12:12.806462 <30>[ 16.450874] systemd[1]: Reached target Remote File Systems.
10804 11:12:12.813104 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10805 11:12:12.830807 <30>[ 16.475230] systemd[1]: Reached target Slices.
10806 11:12:12.837227 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10807 11:12:12.850520 <30>[ 16.494925] systemd[1]: Reached target Swap.
10808 11:12:12.853797 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10809 11:12:12.874074 <30>[ 16.515372] systemd[1]: Listening on initctl Compatibility Named Pipe.
10810 11:12:12.880693 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10811 11:12:12.887416 <30>[ 16.530667] systemd[1]: Listening on Journal Audit Socket.
10812 11:12:12.893874 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10813 11:12:12.906854 <30>[ 16.551345] systemd[1]: Listening on Journal Socket (/dev/log).
10814 11:12:12.913432 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10815 11:12:12.931539 <30>[ 16.576105] systemd[1]: Listening on Journal Socket.
10816 11:12:12.938327 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10817 11:12:12.954292 <30>[ 16.595586] systemd[1]: Listening on Network Service Netlink Socket.
10818 11:12:12.960710 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10819 11:12:12.974750 <30>[ 16.619458] systemd[1]: Listening on udev Control Socket.
10820 11:12:12.981348 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10821 11:12:12.999591 <30>[ 16.643932] systemd[1]: Listening on udev Kernel Socket.
10822 11:12:13.006102 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10823 11:12:13.062354 <30>[ 16.707105] systemd[1]: Mounting Huge Pages File System...
10824 11:12:13.068877 Mounting [0;1;39mHuge Pages File System[0m...
10825 11:12:13.087478 <30>[ 16.728815] systemd[1]: Mounting POSIX Message Queue File System...
10826 11:12:13.090448 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10827 11:12:13.108364 <30>[ 16.752837] systemd[1]: Mounting Kernel Debug File System...
10828 11:12:13.114901 Mounting [0;1;39mKernel Debug File System[0m...
10829 11:12:13.133616 <30>[ 16.775150] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10830 11:12:13.145429 <30>[ 16.786891] systemd[1]: Starting Create list of static device nodes for the current kernel...
10831 11:12:13.151982 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10832 11:12:13.174627 <30>[ 16.819153] systemd[1]: Starting Load Kernel Module configfs...
10833 11:12:13.181005 Starting [0;1;39mLoad Kernel Module configfs[0m...
10834 11:12:13.198243 <30>[ 16.842999] systemd[1]: Starting Load Kernel Module drm...
10835 11:12:13.204765 Starting [0;1;39mLoad Kernel Module drm[0m...
10836 11:12:13.221678 <30>[ 16.863084] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10837 11:12:13.236103 <30>[ 16.880784] systemd[1]: Starting Journal Service...
10838 11:12:13.239550 Starting [0;1;39mJournal Service[0m...
10839 11:12:13.261001 <30>[ 16.905482] systemd[1]: Starting Load Kernel Modules...
10840 11:12:13.267436 Starting [0;1;39mLoad Kernel Modules[0m...
10841 11:12:13.289023 <30>[ 16.930362] systemd[1]: Starting Remount Root and Kernel File Systems...
10842 11:12:13.295421 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10843 11:12:13.312920 <30>[ 16.957746] systemd[1]: Starting Coldplug All udev Devices...
10844 11:12:13.319750 Starting [0;1;39mColdplug All udev Devices[0m...
10845 11:12:13.341939 <30>[ 16.985959] systemd[1]: Started Journal Service.
10846 11:12:13.348224 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10847 11:12:13.364921 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10848 11:12:13.383288 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10849 11:12:13.400378 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10850 11:12:13.423565 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10851 11:12:13.445952 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10852 11:12:13.470153 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10853 11:12:13.488524 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10854 11:12:13.508563 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10855 11:12:13.523162 See 'systemctl status systemd-remount-fs.service' for details.
10856 11:12:13.572991 Mounting [0;1;39mKernel Configuration File System[0m...
10857 11:12:13.590095 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10858 11:12:13.603278 <46>[ 17.243998] systemd-journald[178]: Received client request to flush runtime journal.
10859 11:12:13.612317 Starting [0;1;39mLoad/Save Random Seed[0m...
10860 11:12:13.630786 Starting [0;1;39mApply Kernel Variables[0m...
10861 11:12:13.652498 Starting [0;1;39mCreate System Users[0m...
10862 11:12:13.672694 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10863 11:12:13.692121 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10864 11:12:13.715654 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10865 11:12:13.728245 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10866 11:12:13.744374 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10867 11:12:13.760438 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10868 11:12:13.799919 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10869 11:12:13.823361 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10870 11:12:13.838973 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10871 11:12:13.854699 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10872 11:12:13.895542 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10873 11:12:13.922884 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10874 11:12:13.941659 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10875 11:12:13.960378 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10876 11:12:14.012244 Starting [0;1;39mNetwork Service[0m...
10877 11:12:14.041472 Starting [0;1;39mNetwork Time Synchronization[0m...
10878 11:12:14.060296 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10879 11:12:14.098205 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10880 11:12:14.118919 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10881 11:12:14.125334 <6>[ 17.767651] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10882 11:12:14.140224 [[0;32m OK [0m] Started [0;1;39mNetwork Tim<6>[ 17.783287] remoteproc remoteproc0: scp is available
10883 11:12:14.149754 e Synchronizatio<3>[ 17.785186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10884 11:12:14.150249 n[0m.
10885 11:12:14.156338 <6>[ 17.790689] remoteproc remoteproc0: powering up scp
10886 11:12:14.167014 <6>[ 17.807794] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10887 11:12:14.173873 <3>[ 17.810099] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10888 11:12:14.179963 <6>[ 17.816359] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10889 11:12:14.190026 <6>[ 17.819245] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10890 11:12:14.196791 <6>[ 17.819264] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10891 11:12:14.206488 <6>[ 17.819269] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10892 11:12:14.213659 <3>[ 17.824617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10893 11:12:14.220263 <4>[ 17.851116] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10894 11:12:14.230190 <3>[ 17.856219] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10895 11:12:14.236838 <6>[ 17.862315] usbcore: registered new device driver r8152-cfgselector
10896 11:12:14.242970 <4>[ 17.864515] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10897 11:12:14.253217 <3>[ 17.870726] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 11:12:14.255940 <6>[ 17.888584] mc: Linux media interface: v0.10
10899 11:12:14.263184 <3>[ 17.892559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 11:12:14.272834 <3>[ 17.913315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10901 11:12:14.279034 <6>[ 17.919353] videodev: Linux video capture interface: v2.00
10902 11:12:14.286342 <3>[ 17.921639] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10903 11:12:14.292957 <6>[ 17.922873] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10904 11:12:14.299529 <6>[ 17.940061] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10905 11:12:14.309241 [[0;32m OK [<3>[ 17.943179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10906 11:12:14.322539 0m] Found device<6>[ 17.947357] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10907 11:12:14.329259 [0;1;39m/dev/t<6>[ 17.950506] pci_bus 0000:00: root bus resource [bus 00-ff]
10908 11:12:14.329870 tyS0[0m.
10909 11:12:14.338887 <6>[ 17.956938] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10910 11:12:14.345468 <6>[ 17.956942] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10911 11:12:14.352102 <6>[ 17.956946] remoteproc remoteproc0: remote processor scp is now up
10912 11:12:14.362695 <6>[ 17.963514] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10913 11:12:14.369222 <3>[ 17.970388] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10914 11:12:14.375539 <3>[ 17.970410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 11:12:14.385544 <3>[ 17.970414] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 11:12:14.392596 <6>[ 17.971397] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10917 11:12:14.398955 <3>[ 17.971604] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 11:12:14.409189 <3>[ 17.971623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 11:12:14.415519 <3>[ 17.971626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 11:12:14.425267 <3>[ 17.971632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 11:12:14.432213 <3>[ 17.971635] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10922 11:12:14.442354 <3>[ 17.971679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10923 11:12:14.448464 <4>[ 17.984965] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10924 11:12:14.455068 <4>[ 17.984965] Fallback method does not support PEC.
10925 11:12:14.464820 <6>[ 17.987388] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10926 11:12:14.471338 <6>[ 17.987472] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10927 11:12:14.478323 <6>[ 18.003832] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10928 11:12:14.485005 <6>[ 18.010357] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10929 11:12:14.495228 <6>[ 18.011768] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10930 11:12:14.505612 <3>[ 18.018502] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 11:12:14.508716 <6>[ 18.026347] pci 0000:00:00.0: supports D1 D2
10932 11:12:14.516030 <6>[ 18.036037] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10933 11:12:14.522553 <6>[ 18.041488] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10934 11:12:14.532815 <6>[ 18.043109] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10935 11:12:14.543285 <4>[ 18.053693] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10936 11:12:14.549911 <6>[ 18.053996] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10937 11:12:14.556527 <6>[ 18.057911] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10938 11:12:14.559900 <6>[ 18.058965] Bluetooth: Core ver 2.22
10939 11:12:14.566667 <6>[ 18.060107] NET: Registered PF_BLUETOOTH protocol family
10940 11:12:14.573663 <6>[ 18.060111] Bluetooth: HCI device and connection manager initialized
10941 11:12:14.577198 <6>[ 18.060126] Bluetooth: HCI socket layer initialized
10942 11:12:14.583873 <6>[ 18.060130] Bluetooth: L2CAP socket layer initialized
10943 11:12:14.587527 <6>[ 18.060142] Bluetooth: SCO socket layer initialized
10944 11:12:14.597545 <4>[ 18.065858] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10945 11:12:14.604172 <6>[ 18.073952] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10946 11:12:14.611103 <6>[ 18.076268] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10947 11:12:14.624471 <6>[ 18.077778] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10948 11:12:14.627842 <6>[ 18.077889] usbcore: registered new interface driver uvcvideo
10949 11:12:14.634053 <6>[ 18.129493] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10950 11:12:14.641407 <6>[ 18.134768] r8152 2-1.3:1.0 eth0: v1.12.13
10951 11:12:14.644598 <6>[ 18.134838] usbcore: registered new interface driver r8152
10952 11:12:14.651544 <6>[ 18.135696] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10953 11:12:14.658430 <6>[ 18.147109] usbcore: registered new interface driver btusb
10954 11:12:14.668527 <4>[ 18.147529] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10955 11:12:14.675522 <3>[ 18.147542] Bluetooth: hci0: Failed to load firmware file (-2)
10956 11:12:14.681928 <3>[ 18.147546] Bluetooth: hci0: Failed to set up firmware (-2)
10957 11:12:14.692198 <4>[ 18.147549] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10958 11:12:14.699180 <6>[ 18.153778] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10959 11:12:14.702576 <6>[ 18.153899] pci 0000:01:00.0: supports D1 D2
10960 11:12:14.709703 <6>[ 18.154174] usbcore: registered new interface driver cdc_ether
10961 11:12:14.716141 <6>[ 18.167096] usbcore: registered new interface driver r8153_ecm
10962 11:12:14.723467 <3>[ 18.170268] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 11:12:14.733550 <3>[ 18.172737] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10964 11:12:14.740277 <6>[ 18.173435] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10965 11:12:14.749926 <3>[ 18.173470] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 11:12:14.756770 <3>[ 18.174195] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10967 11:12:14.764095 <6>[ 18.186908] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10968 11:12:14.773946 <3>[ 18.193618] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 11:12:14.780370 <6>[ 18.199043] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10970 11:12:14.786997 <6>[ 18.201872] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10971 11:12:14.797040 <3>[ 18.226257] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 11:12:14.803616 <6>[ 18.226399] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10973 11:12:14.813430 <3>[ 18.252413] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 11:12:14.819865 <6>[ 18.259403] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10975 11:12:14.829842 <6>[ 18.259417] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10976 11:12:14.836453 <3>[ 18.291568] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 11:12:14.846582 <6>[ 18.294420] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10978 11:12:14.853352 <3>[ 18.322678] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 11:12:14.859623 <6>[ 18.324203] pci 0000:00:00.0: PCI bridge to [bus 01]
10980 11:12:14.866576 <6>[ 18.508891] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10981 11:12:14.872919 <6>[ 18.509066] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10982 11:12:14.883162 [[0;32m OK [<6>[ 18.524059] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10983 11:12:14.889867 0m] Created slic<6>[ 18.532157] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10984 11:12:14.893034 e [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10985 11:12:14.913583 <5>[ 18.554335] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10986 11:12:14.919793 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10987 11:12:14.935731 <5>[ 18.576802] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10988 11:12:14.942292 <5>[ 18.584244] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10989 11:12:14.952171 [[0;32m OK [<4>[ 18.592838] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10990 11:12:14.959167 <6>[ 18.603027] cfg80211: failed to load regulatory.db
10991 11:12:14.965564 0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10992 11:12:14.986488 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10993 11:12:15.011442 <6>[ 18.652366] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10994 11:12:15.017691 <6>[ 18.659871] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10995 11:12:15.042265 <6>[ 18.686554] mt7921e 0000:01:00.0: ASIC revision: 79610010
10996 11:12:15.052140 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10997 11:12:15.074504 Starting [0;1;39mNetwork Name Resolution[0m...
10998 11:12:15.096668 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10999 11:12:15.148412 <6>[ 18.789096] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11000 11:12:15.151803 <6>[ 18.789096]
11001 11:12:15.155136 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11002 11:12:15.170916 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11003 11:12:15.190289 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11004 11:12:15.206318 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11005 11:12:15.218834 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11006 11:12:15.238826 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11007 11:12:15.250683 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11008 11:12:15.267029 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11009 11:12:15.303042 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11010 11:12:15.335410 Starting [0;1;39mUser Login Management[0m...
11011 11:12:15.353189 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11012 11:12:15.371111 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11013 11:12:15.387646 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11014 11:12:15.405972 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11015 11:12:15.416178 <6>[ 19.057061] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11016 11:12:15.426163 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11017 11:12:15.479352 Starting [0;1;39mPermit User Sessions[0m...
11018 11:12:15.501141 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11019 11:12:15.525167 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11020 11:12:15.593364 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11021 11:12:15.611767 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11022 11:12:15.627612 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11023 11:12:15.643923 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11024 11:12:15.659515 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11025 11:12:15.724618 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11026 11:12:15.763341 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11027 11:12:15.809558
11028 11:12:15.810074
11029 11:12:15.813153 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11030 11:12:15.813726
11031 11:12:15.816296 debian-bullseye-arm64 login: root (automatic login)
11032 11:12:15.816831
11033 11:12:15.817191
11034 11:12:15.845622 Linux debian-bullseye-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
11035 11:12:15.846124
11036 11:12:15.852097 The programs included with the Debian GNU/Linux system are free software;
11037 11:12:15.859082 the exact distribution terms for each program are described in the
11038 11:12:15.862154 individual files in /usr/share/doc/*/copyright.
11039 11:12:15.862572
11040 11:12:15.868834 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11041 11:12:15.871951 permitted by applicable law.
11042 11:12:15.873380 Matched prompt #10: / #
11044 11:12:15.874628 Setting prompt string to ['/ #']
11045 11:12:15.875070 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11047 11:12:15.876163 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11048 11:12:15.876671 start: 2.2.6 expect-shell-connection (timeout 00:02:54) [common]
11049 11:12:15.877088 Setting prompt string to ['/ #']
11050 11:12:15.877400 Forcing a shell prompt, looking for ['/ #']
11052 11:12:15.928267 / #
11053 11:12:15.928871 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11054 11:12:15.929253 Waiting using forced prompt support (timeout 00:02:30)
11055 11:12:15.934349
11056 11:12:15.935209 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11057 11:12:15.935688 start: 2.2.7 export-device-env (timeout 00:02:54) [common]
11058 11:12:15.936141 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11059 11:12:15.936573 end: 2.2 depthcharge-retry (duration 00:02:06) [common]
11060 11:12:15.936995 end: 2 depthcharge-action (duration 00:02:06) [common]
11061 11:12:15.937419 start: 3 lava-test-retry (timeout 00:05:00) [common]
11062 11:12:15.937967 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11063 11:12:15.938341 Using namespace: common
11065 11:12:16.039441 / # #
11066 11:12:16.040047 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11067 11:12:16.045561 #
11068 11:12:16.046230 Using /lava-12925679
11070 11:12:16.147221 / # export SHELL=/bin/sh
11071 11:12:16.147849 <6>[ 19.734653] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11072 11:12:16.148208 <6>[ 19.742430] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11073 11:12:16.153100 export SHELL=/bin/sh
11075 11:12:16.254410 / # . /lava-12925679/environment
11076 11:12:16.259438 . /lava-12925679/environment
11078 11:12:16.363293 / # <6>[ 19.9130/lava-12925679/bin/lava-test-runner /lava-12925679/0
11079 11:12:16.363684 Test shell timeout: 10s (minimum of the action and connection timeout)
11080 11:12:16.364647 23] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11081 11:12:16.368730 /lava-12925679/bin/lava-test-runner /lava-12925679/0
11082 11:12:16.390231 + export TESTRUN_ID=0_cros-ec
11083 11:12:16.397285 + c<8>[ 20.040131] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12925679_1.5.2.3.1>
11084 11:12:16.398138 Received signal: <STARTRUN> 0_cros-ec 12925679_1.5.2.3.1
11085 11:12:16.398527 Starting test lava.0_cros-ec (12925679_1.5.2.3.1)
11086 11:12:16.398916 Skipping test definition patterns.
11087 11:12:16.400204 d /lava-12925679/0/tests/0_cros-ec
11088 11:12:16.403333 + cat uuid
11089 11:12:16.403743 + UUID=12925679_1.5.2.3.1
11090 11:12:16.404071 + set +x
11091 11:12:16.409887 + python3 -m cros.runners.lava_runner -v
11092 11:12:16.787780 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11093 11:12:16.798065 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11094 11:12:16.798576
11095 11:12:16.804362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11096 11:12:16.805147 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11098 11:12:16.811147 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11099 11:12:16.820813 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11100 11:12:16.821327
11101 11:12:16.827487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11102 11:12:16.828259 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11104 11:12:16.834248 test_cros_ec<8>[ 20.476555] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12925679_1.5.2.3.1>
11105 11:12:16.835028 Received signal: <ENDRUN> 0_cros-ec 12925679_1.5.2.3.1
11106 11:12:16.835418 Ending use of test pattern.
11107 11:12:16.835731 Ending test lava.0_cros-ec (12925679_1.5.2.3.1), duration 0.44
11109 11:12:16.837274 _gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11110 11:12:16.844420 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11111 11:12:16.847231
11112 11:12:16.850525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11113 11:12:16.851193 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11115 11:12:16.857025 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11116 11:12:16.864068 Checks the standard ABI for the main Embedded Controller. ... ok
11117 11:12:16.864580
11118 11:12:16.867719 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11120 11:12:16.870143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11121 11:12:16.873747 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11122 11:12:16.880305 Checks the main Embedded controller character device. ... ok
11123 11:12:16.880792
11124 11:12:16.886734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11125 11:12:16.887408 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11127 11:12:16.890364 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11128 11:12:16.896906 Checks basic comunication with the main Embedded controller. ... ok
11129 11:12:16.897424
11130 11:12:16.903410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11131 11:12:16.904212 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11133 11:12:16.906869 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11134 11:12:16.916992 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11135 11:12:16.917537
11136 11:12:16.920051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11137 11:12:16.920731 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11139 11:12:16.926846 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11140 11:12:16.936482 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11141 11:12:16.937001
11142 11:12:16.939598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11143 11:12:16.940266 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11145 11:12:16.946168 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11146 11:12:16.952969 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11147 11:12:16.953508
11148 11:12:16.959352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11149 11:12:16.960171 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11151 11:12:16.963144 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11152 11:12:16.972708 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11153 11:12:16.973227
11154 11:12:16.979349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11155 11:12:16.980132 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11157 11:12:16.982420 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11158 11:12:16.992952 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11159 11:12:16.993496
11160 11:12:16.999380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11161 11:12:17.000170 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11163 11:12:17.002108 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11164 11:12:17.009468 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11165 11:12:17.010023
11166 11:12:17.015970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11167 11:12:17.016754 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11169 11:12:17.022232 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11170 11:12:17.028919 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11171 11:12:17.029436
11172 11:12:17.035478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11173 11:12:17.036428 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11175 11:12:17.042152 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11176 11:12:17.048404 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11177 11:12:17.051773
11178 11:12:17.055330 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11180 11:12:17.058572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11181 11:12:17.061567 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11182 11:12:17.068597 Check the cros battery ABI. ... skipped 'No BAT found'
11183 11:12:17.069101
11184 11:12:17.074761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11185 11:12:17.075452 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11187 11:12:17.081465 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11188 11:12:17.088214 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11189 11:12:17.088633
11190 11:12:17.095062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11191 11:12:17.096014 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11193 11:12:17.101255 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11194 11:12:17.108336 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11195 11:12:17.108860
11196 11:12:17.111434 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11198 11:12:17.114844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11199 11:12:17.121456 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11200 11:12:17.124366 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11201 11:12:17.124973
11202 11:12:17.130793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11203 11:12:17.131209
11204 11:12:17.131806 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11206 11:12:17.138013 ----------------------------------------------------------------------
11207 11:12:17.140991 Ran 18 tests in 0.009s
11208 11:12:17.141518
11209 11:12:17.141859 OK (skipped=15)
11210 11:12:17.144288 + set +x
11211 11:12:17.144986 <LAVA_TEST_RUNNER EXIT>
11212 11:12:17.145629 ok: lava_test_shell seems to have completed
11213 11:12:17.146494 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11214 11:12:17.146947 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11215 11:12:17.147358 end: 3 lava-test-retry (duration 00:00:01) [common]
11216 11:12:17.147801 start: 4 finalize (timeout 00:07:32) [common]
11217 11:12:17.148242 start: 4.1 power-off (timeout 00:00:30) [common]
11218 11:12:17.148989 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11219 11:12:17.272753 >> Command sent successfully.
11220 11:12:17.283495 Returned 0 in 0 seconds
11221 11:12:17.384855 end: 4.1 power-off (duration 00:00:00) [common]
11223 11:12:17.386770 start: 4.2 read-feedback (timeout 00:07:32) [common]
11224 11:12:17.388351 Listened to connection for namespace 'common' for up to 1s
11225 11:12:18.388847 Finalising connection for namespace 'common'
11226 11:12:18.389445 Disconnecting from shell: Finalise
11227 11:12:18.389883 / #
11228 11:12:18.490766 end: 4.2 read-feedback (duration 00:00:01) [common]
11229 11:12:18.491386 end: 4 finalize (duration 00:00:01) [common]
11230 11:12:18.491965 Cleaning after the job
11231 11:12:18.492447 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/ramdisk
11232 11:12:18.520422 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/kernel
11233 11:12:18.538223 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/dtb
11234 11:12:18.538494 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925679/tftp-deploy-y7s_h0a2/modules
11235 11:12:18.548299 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925679
11236 11:12:18.667744 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925679
11237 11:12:18.667907 Job finished correctly