Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 35
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 16
1 11:07:54.796602 lava-dispatcher, installed at version: 2024.01
2 11:07:54.796834 start: 0 validate
3 11:07:54.796977 Start time: 2024-03-03 11:07:54.796967+00:00 (UTC)
4 11:07:54.797106 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:07:54.797241 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240129.0%2Farm64%2Frootfs.cpio.gz exists
6 11:07:55.069134 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:07:55.069310 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:07:55.336391 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:07:55.336662 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:07:55.603891 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:07:55.604207 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:07:55.872574 validate duration: 1.08
14 11:07:55.873036 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:07:55.873214 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:07:55.873366 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:07:55.873566 Not decompressing ramdisk as can be used compressed.
18 11:07:55.873710 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240129.0/arm64/rootfs.cpio.gz
19 11:07:55.873827 saving as /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/ramdisk/rootfs.cpio.gz
20 11:07:55.873944 total size: 47861385 (45 MB)
21 11:07:55.875577 progress 0 % (0 MB)
22 11:07:55.889201 progress 5 % (2 MB)
23 11:07:55.902300 progress 10 % (4 MB)
24 11:07:55.915950 progress 15 % (6 MB)
25 11:07:55.929500 progress 20 % (9 MB)
26 11:07:55.943571 progress 25 % (11 MB)
27 11:07:55.957153 progress 30 % (13 MB)
28 11:07:55.970028 progress 35 % (16 MB)
29 11:07:55.982609 progress 40 % (18 MB)
30 11:07:55.995269 progress 45 % (20 MB)
31 11:07:56.007930 progress 50 % (22 MB)
32 11:07:56.020612 progress 55 % (25 MB)
33 11:07:56.033292 progress 60 % (27 MB)
34 11:07:56.045905 progress 65 % (29 MB)
35 11:07:56.058563 progress 70 % (31 MB)
36 11:07:56.071216 progress 75 % (34 MB)
37 11:07:56.083945 progress 80 % (36 MB)
38 11:07:56.096545 progress 85 % (38 MB)
39 11:07:56.109167 progress 90 % (41 MB)
40 11:07:56.121643 progress 95 % (43 MB)
41 11:07:56.134029 progress 100 % (45 MB)
42 11:07:56.134242 45 MB downloaded in 0.26 s (175.35 MB/s)
43 11:07:56.134406 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:07:56.134652 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:07:56.134741 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:07:56.134827 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:07:56.134969 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:07:56.135040 saving as /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/kernel/Image
50 11:07:56.135103 total size: 51599872 (49 MB)
51 11:07:56.135168 No compression specified
52 11:07:56.136273 progress 0 % (0 MB)
53 11:07:56.149762 progress 5 % (2 MB)
54 11:07:56.163428 progress 10 % (4 MB)
55 11:07:56.177094 progress 15 % (7 MB)
56 11:07:56.190627 progress 20 % (9 MB)
57 11:07:56.204366 progress 25 % (12 MB)
58 11:07:56.218029 progress 30 % (14 MB)
59 11:07:56.231772 progress 35 % (17 MB)
60 11:07:56.245235 progress 40 % (19 MB)
61 11:07:56.258889 progress 45 % (22 MB)
62 11:07:56.272554 progress 50 % (24 MB)
63 11:07:56.286310 progress 55 % (27 MB)
64 11:07:56.299840 progress 60 % (29 MB)
65 11:07:56.313740 progress 65 % (32 MB)
66 11:07:56.327444 progress 70 % (34 MB)
67 11:07:56.341200 progress 75 % (36 MB)
68 11:07:56.354698 progress 80 % (39 MB)
69 11:07:56.368377 progress 85 % (41 MB)
70 11:07:56.382080 progress 90 % (44 MB)
71 11:07:56.395492 progress 95 % (46 MB)
72 11:07:56.408871 progress 100 % (49 MB)
73 11:07:56.409103 49 MB downloaded in 0.27 s (179.60 MB/s)
74 11:07:56.409258 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:07:56.409511 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:07:56.409600 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:07:56.409697 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:07:56.409843 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:07:56.409915 saving as /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/dtb/mt8192-asurada-spherion-r0.dtb
81 11:07:56.409978 total size: 47278 (0 MB)
82 11:07:56.410042 No compression specified
83 11:07:56.411160 progress 69 % (0 MB)
84 11:07:56.411454 progress 100 % (0 MB)
85 11:07:56.411615 0 MB downloaded in 0.00 s (27.58 MB/s)
86 11:07:56.411741 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:07:56.411970 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:07:56.412057 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:07:56.412141 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:07:56.412258 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:07:56.412328 saving as /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/modules/modules.tar
93 11:07:56.412388 total size: 8628476 (8 MB)
94 11:07:56.412450 Using unxz to decompress xz
95 11:07:56.416660 progress 0 % (0 MB)
96 11:07:56.438453 progress 5 % (0 MB)
97 11:07:56.464895 progress 10 % (0 MB)
98 11:07:56.491154 progress 15 % (1 MB)
99 11:07:56.515788 progress 20 % (1 MB)
100 11:07:56.542347 progress 25 % (2 MB)
101 11:07:56.568307 progress 30 % (2 MB)
102 11:07:56.599492 progress 35 % (2 MB)
103 11:07:56.626555 progress 40 % (3 MB)
104 11:07:56.652658 progress 45 % (3 MB)
105 11:07:56.679521 progress 50 % (4 MB)
106 11:07:56.707104 progress 55 % (4 MB)
107 11:07:56.733783 progress 60 % (4 MB)
108 11:07:56.762076 progress 65 % (5 MB)
109 11:07:56.789133 progress 70 % (5 MB)
110 11:07:56.814937 progress 75 % (6 MB)
111 11:07:56.843036 progress 80 % (6 MB)
112 11:07:56.869769 progress 85 % (7 MB)
113 11:07:56.896816 progress 90 % (7 MB)
114 11:07:56.929008 progress 95 % (7 MB)
115 11:07:56.960342 progress 100 % (8 MB)
116 11:07:56.965694 8 MB downloaded in 0.55 s (14.87 MB/s)
117 11:07:56.965945 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:07:56.966206 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:07:56.966299 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:07:56.966394 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:07:56.966475 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:07:56.966571 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:07:56.966794 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a
125 11:07:56.966935 makedir: /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin
126 11:07:56.967040 makedir: /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/tests
127 11:07:56.967141 makedir: /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/results
128 11:07:56.967256 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-add-keys
129 11:07:56.967444 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-add-sources
130 11:07:56.967578 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-background-process-start
131 11:07:56.967713 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-background-process-stop
132 11:07:56.967841 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-common-functions
133 11:07:56.967968 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-echo-ipv4
134 11:07:56.968095 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-install-packages
135 11:07:56.968222 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-installed-packages
136 11:07:56.968349 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-os-build
137 11:07:56.968477 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-probe-channel
138 11:07:56.968603 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-probe-ip
139 11:07:56.968729 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-target-ip
140 11:07:56.968859 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-target-mac
141 11:07:56.968985 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-target-storage
142 11:07:56.969117 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-test-case
143 11:07:56.969245 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-test-event
144 11:07:56.969369 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-test-feedback
145 11:07:56.969495 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-test-raise
146 11:07:56.969624 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-test-reference
147 11:07:56.969751 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-test-runner
148 11:07:56.969877 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-test-set
149 11:07:56.970005 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-test-shell
150 11:07:56.970135 Updating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-install-packages (oe)
151 11:07:56.970295 Updating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/bin/lava-installed-packages (oe)
152 11:07:56.970423 Creating /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/environment
153 11:07:56.970528 LAVA metadata
154 11:07:56.970606 - LAVA_JOB_ID=12925673
155 11:07:56.970670 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:07:56.970775 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:07:56.970842 skipped lava-vland-overlay
158 11:07:56.970916 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:07:56.970997 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:07:56.971057 skipped lava-multinode-overlay
161 11:07:56.971135 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:07:56.971223 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:07:56.971297 Loading test definitions
164 11:07:56.971425 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:07:56.971500 Using /lava-12925673 at stage 0
166 11:07:56.971821 uuid=12925673_1.5.2.3.1 testdef=None
167 11:07:56.971909 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:07:56.971995 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:07:56.972539 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:07:56.972767 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:07:56.973408 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:07:56.973641 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:07:56.974265 runner path: /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/0/tests/0_igt-kms-mediatek test_uuid 12925673_1.5.2.3.1
176 11:07:56.974428 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:07:56.974634 Creating lava-test-runner.conf files
179 11:07:56.974698 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925673/lava-overlay-4j2zx07a/lava-12925673/0 for stage 0
180 11:07:56.974788 - 0_igt-kms-mediatek
181 11:07:56.974887 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:07:56.975010 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:07:56.984064 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:07:56.984206 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:07:56.984338 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:07:56.984459 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:07:56.984579 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:07:58.837461 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 11:07:58.837856 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 11:07:58.837967 extracting modules file /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925673/extract-overlay-ramdisk-2516n1v6/ramdisk
191 11:07:59.069624 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:07:59.069795 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 11:07:59.069890 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925673/compress-overlay-bls_bepl/overlay-1.5.2.4.tar.gz to ramdisk
194 11:07:59.069967 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925673/compress-overlay-bls_bepl/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925673/extract-overlay-ramdisk-2516n1v6/ramdisk
195 11:07:59.077252 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:07:59.077368 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 11:07:59.077465 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:07:59.077555 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 11:07:59.077666 Building ramdisk /var/lib/lava/dispatcher/tmp/12925673/extract-overlay-ramdisk-2516n1v6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925673/extract-overlay-ramdisk-2516n1v6/ramdisk
200 11:08:00.422654 >> 465513 blocks
201 11:08:06.816228 rename /var/lib/lava/dispatcher/tmp/12925673/extract-overlay-ramdisk-2516n1v6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/ramdisk/ramdisk.cpio.gz
202 11:08:06.816688 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 11:08:06.816816 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 11:08:06.816916 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 11:08:06.817028 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/kernel/Image'
206 11:08:19.732699 Returned 0 in 12 seconds
207 11:08:19.833327 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/kernel/image.itb
208 11:08:21.120089 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:08:21.120531 output: Created: Sun Mar 3 11:08:20 2024
210 11:08:21.120645 output: Image 0 (kernel-1)
211 11:08:21.120747 output: Description:
212 11:08:21.120859 output: Created: Sun Mar 3 11:08:20 2024
213 11:08:21.120998 output: Type: Kernel Image
214 11:08:21.121091 output: Compression: lzma compressed
215 11:08:21.121199 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
216 11:08:21.121298 output: Architecture: AArch64
217 11:08:21.121398 output: OS: Linux
218 11:08:21.121489 output: Load Address: 0x00000000
219 11:08:21.121599 output: Entry Point: 0x00000000
220 11:08:21.121687 output: Hash algo: crc32
221 11:08:21.121777 output: Hash value: cf43f4f3
222 11:08:21.121863 output: Image 1 (fdt-1)
223 11:08:21.121962 output: Description: mt8192-asurada-spherion-r0
224 11:08:21.122056 output: Created: Sun Mar 3 11:08:20 2024
225 11:08:21.122159 output: Type: Flat Device Tree
226 11:08:21.122251 output: Compression: uncompressed
227 11:08:21.122336 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:08:21.122423 output: Architecture: AArch64
229 11:08:21.122506 output: Hash algo: crc32
230 11:08:21.122594 output: Hash value: cc4352de
231 11:08:21.122653 output: Image 2 (ramdisk-1)
232 11:08:21.122708 output: Description: unavailable
233 11:08:21.122769 output: Created: Sun Mar 3 11:08:20 2024
234 11:08:21.122824 output: Type: RAMDisk Image
235 11:08:21.122878 output: Compression: Unknown Compression
236 11:08:21.122956 output: Data Size: 61006423 Bytes = 59576.58 KiB = 58.18 MiB
237 11:08:21.123040 output: Architecture: AArch64
238 11:08:21.123135 output: OS: Linux
239 11:08:21.123227 output: Load Address: unavailable
240 11:08:21.123315 output: Entry Point: unavailable
241 11:08:21.123426 output: Hash algo: crc32
242 11:08:21.123482 output: Hash value: 32b3d5b1
243 11:08:21.123569 output: Default Configuration: 'conf-1'
244 11:08:21.123628 output: Configuration 0 (conf-1)
245 11:08:21.123683 output: Description: mt8192-asurada-spherion-r0
246 11:08:21.123737 output: Kernel: kernel-1
247 11:08:21.123822 output: Init Ramdisk: ramdisk-1
248 11:08:21.123880 output: FDT: fdt-1
249 11:08:21.123935 output: Loadables: kernel-1
250 11:08:21.124015 output:
251 11:08:21.124265 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 11:08:21.124407 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 11:08:21.124546 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 11:08:21.124686 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 11:08:21.124800 No LXC device requested
256 11:08:21.124913 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:08:21.125054 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 11:08:21.125167 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:08:21.125316 Checking files for TFTP limit of 4294967296 bytes.
260 11:08:21.126123 end: 1 tftp-deploy (duration 00:00:25) [common]
261 11:08:21.126301 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:08:21.126435 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:08:21.126645 substitutions:
264 11:08:21.126750 - {DTB}: 12925673/tftp-deploy-ldkp6nhv/dtb/mt8192-asurada-spherion-r0.dtb
265 11:08:21.126849 - {INITRD}: 12925673/tftp-deploy-ldkp6nhv/ramdisk/ramdisk.cpio.gz
266 11:08:21.126939 - {KERNEL}: 12925673/tftp-deploy-ldkp6nhv/kernel/Image
267 11:08:21.127075 - {LAVA_MAC}: None
268 11:08:21.127174 - {PRESEED_CONFIG}: None
269 11:08:21.127283 - {PRESEED_LOCAL}: None
270 11:08:21.127384 - {RAMDISK}: 12925673/tftp-deploy-ldkp6nhv/ramdisk/ramdisk.cpio.gz
271 11:08:21.127456 - {ROOT_PART}: None
272 11:08:21.127529 - {ROOT}: None
273 11:08:21.127593 - {SERVER_IP}: 192.168.201.1
274 11:08:21.127710 - {TEE}: None
275 11:08:21.127771 Parsed boot commands:
276 11:08:21.127835 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:08:21.128033 Parsed boot commands: tftpboot 192.168.201.1 12925673/tftp-deploy-ldkp6nhv/kernel/image.itb 12925673/tftp-deploy-ldkp6nhv/kernel/cmdline
278 11:08:21.128154 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:08:21.128319 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:08:21.128495 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:08:21.128621 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:08:21.128725 Not connected, no need to disconnect.
283 11:08:21.128851 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:08:21.128972 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:08:21.129080 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 11:08:21.134014 Setting prompt string to ['lava-test: # ']
287 11:08:21.134524 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:08:21.134716 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:08:21.134863 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:08:21.135005 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:08:21.135387 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 11:08:26.270132 >> Command sent successfully.
293 11:08:26.272685 Returned 0 in 5 seconds
294 11:08:26.373060 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:08:26.373565 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:08:26.373728 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:08:26.373876 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:08:26.374006 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:08:26.374131 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:08:26.374628 [Enter `^Ec?' for help]
302 11:08:26.548822
303 11:08:26.549044
304 11:08:26.549168 F0: 102B 0000
305 11:08:26.549317
306 11:08:26.549431 F3: 1001 0000 [0200]
307 11:08:26.549546
308 11:08:26.552438 F3: 1001 0000
309 11:08:26.552564
310 11:08:26.552681 F7: 102D 0000
311 11:08:26.552796
312 11:08:26.552938 F1: 0000 0000
313 11:08:26.555856
314 11:08:26.555977 V0: 0000 0000 [0001]
315 11:08:26.556097
316 11:08:26.556206 00: 0007 8000
317 11:08:26.556349
318 11:08:26.559799 01: 0000 0000
319 11:08:26.559931
320 11:08:26.560078 BP: 0C00 0209 [0000]
321 11:08:26.560204
322 11:08:26.563490 G0: 1182 0000
323 11:08:26.563611
324 11:08:26.563731 EC: 0000 0021 [4000]
325 11:08:26.563844
326 11:08:26.567136 S7: 0000 0000 [0000]
327 11:08:26.567276
328 11:08:26.567436 CC: 0000 0000 [0001]
329 11:08:26.567594
330 11:08:26.569897 T0: 0000 0040 [010F]
331 11:08:26.570114
332 11:08:26.570225 Jump to BL
333 11:08:26.570350
334 11:08:26.595323
335 11:08:26.595487
336 11:08:26.595618
337 11:08:26.603108 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:08:26.606740 ARM64: Exception handlers installed.
339 11:08:26.610391 ARM64: Testing exception
340 11:08:26.613767 ARM64: Done test exception
341 11:08:26.621374 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:08:26.628730 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:08:26.635594 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:08:26.646278 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:08:26.652901 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:08:26.663334 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:08:26.673403 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:08:26.680083 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:08:26.698593 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:08:26.701754 WDT: Last reset was cold boot
351 11:08:26.705104 SPI1(PAD0) initialized at 2873684 Hz
352 11:08:26.708368 SPI5(PAD0) initialized at 992727 Hz
353 11:08:26.711655 VBOOT: Loading verstage.
354 11:08:26.718204 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:08:26.721406 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:08:26.724941 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:08:26.728448 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:08:26.736053 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:08:26.742394 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:08:26.753141 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 11:08:26.753272
362 11:08:26.753391
363 11:08:26.763276 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:08:26.766482 ARM64: Exception handlers installed.
365 11:08:26.769553 ARM64: Testing exception
366 11:08:26.769681 ARM64: Done test exception
367 11:08:26.776762 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:08:26.780167 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:08:26.794624 Probing TPM: . done!
370 11:08:26.794752 TPM ready after 0 ms
371 11:08:26.801474 Connected to device vid:did:rid of 1ae0:0028:00
372 11:08:26.808912 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 11:08:26.866276 Initialized TPM device CR50 revision 0
374 11:08:26.878331 tlcl_send_startup: Startup return code is 0
375 11:08:26.878468 TPM: setup succeeded
376 11:08:26.889728 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:08:26.898633 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:08:26.909627 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:08:26.919352 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:08:26.922392 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:08:26.930258 in-header: 03 07 00 00 08 00 00 00
382 11:08:26.933963 in-data: aa e4 47 04 13 02 00 00
383 11:08:26.937546 Chrome EC: UHEPI supported
384 11:08:26.944613 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:08:26.948393 in-header: 03 95 00 00 08 00 00 00
386 11:08:26.951841 in-data: 18 20 20 08 00 00 00 00
387 11:08:26.951966 Phase 1
388 11:08:26.956150 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:08:26.959689 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:08:26.966702 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:08:26.970313 Recovery requested (1009000e)
392 11:08:26.978539 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:08:26.983801 tlcl_extend: response is 0
394 11:08:26.993301 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:08:26.999234 tlcl_extend: response is 0
396 11:08:27.006093 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:08:27.026103 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 11:08:27.032698 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:08:27.032828
400 11:08:27.032943
401 11:08:27.042420 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:08:27.045640 ARM64: Exception handlers installed.
403 11:08:27.049218 ARM64: Testing exception
404 11:08:27.049341 ARM64: Done test exception
405 11:08:27.071570 pmic_efuse_setting: Set efuses in 11 msecs
406 11:08:27.074783 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:08:27.081097 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:08:27.084668 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:08:27.091706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:08:27.095141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:08:27.098475 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:08:27.105876 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:08:27.109791 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:08:27.113166 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:08:27.120031 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:08:27.123938 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:08:27.127520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:08:27.131504 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:08:27.138283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:08:27.145582 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:08:27.149838 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:08:27.156631 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:08:27.160212 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:08:27.167870 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:08:27.171500 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:08:27.178527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:08:27.182183 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:08:27.189330 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:08:27.193697 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:08:27.201342 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:08:27.204123 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:08:27.211287 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:08:27.215093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:08:27.222405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:08:27.226188 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:08:27.229619 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:08:27.237101 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:08:27.240790 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:08:27.244252 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:08:27.251324 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:08:27.254657 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:08:27.262172 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:08:27.265565 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:08:27.269056 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:08:27.276269 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:08:27.280182 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:08:27.284045 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:08:27.287611 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:08:27.290647 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:08:27.297892 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:08:27.301764 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:08:27.304999 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:08:27.308742 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:08:27.312460 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:08:27.320279 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:08:27.324191 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:08:27.327473 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:08:27.334273 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:08:27.342151 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:08:27.349202 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:08:27.356701 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:08:27.364251 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:08:27.367275 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:08:27.371476 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:08:27.378304 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:08:27.385827 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x23
467 11:08:27.388942 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:08:27.396964 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 11:08:27.399607 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:08:27.409171 [RTC]rtc_get_frequency_meter,154: input=15, output=852
471 11:08:27.418765 [RTC]rtc_get_frequency_meter,154: input=7, output=725
472 11:08:27.428364 [RTC]rtc_get_frequency_meter,154: input=11, output=789
473 11:08:27.437533 [RTC]rtc_get_frequency_meter,154: input=13, output=820
474 11:08:27.447170 [RTC]rtc_get_frequency_meter,154: input=12, output=805
475 11:08:27.456265 [RTC]rtc_get_frequency_meter,154: input=11, output=788
476 11:08:27.466610 [RTC]rtc_get_frequency_meter,154: input=12, output=804
477 11:08:27.470391 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 11:08:27.473892 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 11:08:27.480588 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:08:27.484766 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 11:08:27.488383 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:08:27.492109 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 11:08:27.495795 ADC[4]: Raw value=903694 ID=7
484 11:08:27.495909 ADC[3]: Raw value=213916 ID=1
485 11:08:27.499322 RAM Code: 0x71
486 11:08:27.503299 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:08:27.510045 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:08:27.517683 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:08:27.525291 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:08:27.529357 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:08:27.532324 in-header: 03 07 00 00 08 00 00 00
492 11:08:27.535831 in-data: aa e4 47 04 13 02 00 00
493 11:08:27.535915 Chrome EC: UHEPI supported
494 11:08:27.542854 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:08:27.546740 in-header: 03 95 00 00 08 00 00 00
496 11:08:27.550336 in-data: 18 20 20 08 00 00 00 00
497 11:08:27.553841 MRC: failed to locate region type 0.
498 11:08:27.558271 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:08:27.562243 DRAM-K: Running full calibration
500 11:08:27.569434 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:08:27.569520 header.status = 0x0
502 11:08:27.572967 header.version = 0x6 (expected: 0x6)
503 11:08:27.576985 header.size = 0xd00 (expected: 0xd00)
504 11:08:27.580361 header.flags = 0x0
505 11:08:27.583649 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:08:27.603176 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 11:08:27.610707 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:08:27.614235 dram_init: ddr_geometry: 2
509 11:08:27.614317 [EMI] MDL number = 2
510 11:08:27.617793 [EMI] Get MDL freq = 0
511 11:08:27.617867 dram_init: ddr_type: 0
512 11:08:27.621578 is_discrete_lpddr4: 1
513 11:08:27.625252 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:08:27.625325
515 11:08:27.625387
516 11:08:27.629038 [Bian_co] ETT version 0.0.0.1
517 11:08:27.632270 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:08:27.632397
519 11:08:27.636232 dramc_set_vcore_voltage set vcore to 650000
520 11:08:27.636333 Read voltage for 800, 4
521 11:08:27.639733 Vio18 = 0
522 11:08:27.639818 Vcore = 650000
523 11:08:27.639886 Vdram = 0
524 11:08:27.643794 Vddq = 0
525 11:08:27.643893 Vmddr = 0
526 11:08:27.643990 dram_init: config_dvfs: 1
527 11:08:27.650426 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:08:27.657122 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:08:27.660729 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:08:27.663895 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:08:27.667097 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:08:27.670693 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:08:27.674582 MEM_TYPE=3, freq_sel=18
534 11:08:27.674663 sv_algorithm_assistance_LP4_1600
535 11:08:27.682151 ============ PULL DRAM RESETB DOWN ============
536 11:08:27.685846 ========== PULL DRAM RESETB DOWN end =========
537 11:08:27.689458 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:08:27.693061 ===================================
539 11:08:27.693166 LPDDR4 DRAM CONFIGURATION
540 11:08:27.696055 ===================================
541 11:08:27.699724 EX_ROW_EN[0] = 0x0
542 11:08:27.703145 EX_ROW_EN[1] = 0x0
543 11:08:27.703238 LP4Y_EN = 0x0
544 11:08:27.706549 WORK_FSP = 0x0
545 11:08:27.706638 WL = 0x2
546 11:08:27.710140 RL = 0x2
547 11:08:27.710246 BL = 0x2
548 11:08:27.713532 RPST = 0x0
549 11:08:27.713612 RD_PRE = 0x0
550 11:08:27.716482 WR_PRE = 0x1
551 11:08:27.716556 WR_PST = 0x0
552 11:08:27.720311 DBI_WR = 0x0
553 11:08:27.720388 DBI_RD = 0x0
554 11:08:27.723302 OTF = 0x1
555 11:08:27.726459 ===================================
556 11:08:27.729567 ===================================
557 11:08:27.729648 ANA top config
558 11:08:27.733295 ===================================
559 11:08:27.736587 DLL_ASYNC_EN = 0
560 11:08:27.739802 ALL_SLAVE_EN = 1
561 11:08:27.739881 NEW_RANK_MODE = 1
562 11:08:27.742912 DLL_IDLE_MODE = 1
563 11:08:27.746224 LP45_APHY_COMB_EN = 1
564 11:08:27.749736 TX_ODT_DIS = 1
565 11:08:27.753312 NEW_8X_MODE = 1
566 11:08:27.756400 ===================================
567 11:08:27.760143 ===================================
568 11:08:27.760216 data_rate = 1600
569 11:08:27.763316 CKR = 1
570 11:08:27.766025 DQ_P2S_RATIO = 8
571 11:08:27.769717 ===================================
572 11:08:27.773520 CA_P2S_RATIO = 8
573 11:08:27.777351 DQ_CA_OPEN = 0
574 11:08:27.777431 DQ_SEMI_OPEN = 0
575 11:08:27.780541 CA_SEMI_OPEN = 0
576 11:08:27.783549 CA_FULL_RATE = 0
577 11:08:27.786720 DQ_CKDIV4_EN = 1
578 11:08:27.790374 CA_CKDIV4_EN = 1
579 11:08:27.793709 CA_PREDIV_EN = 0
580 11:08:27.793794 PH8_DLY = 0
581 11:08:27.797037 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:08:27.800159 DQ_AAMCK_DIV = 4
583 11:08:27.803597 CA_AAMCK_DIV = 4
584 11:08:27.806968 CA_ADMCK_DIV = 4
585 11:08:27.810304 DQ_TRACK_CA_EN = 0
586 11:08:27.810388 CA_PICK = 800
587 11:08:27.813331 CA_MCKIO = 800
588 11:08:27.816991 MCKIO_SEMI = 0
589 11:08:27.820522 PLL_FREQ = 3068
590 11:08:27.824214 DQ_UI_PI_RATIO = 32
591 11:08:27.827629 CA_UI_PI_RATIO = 0
592 11:08:27.827708 ===================================
593 11:08:27.831503 ===================================
594 11:08:27.835444 memory_type:LPDDR4
595 11:08:27.835523 GP_NUM : 10
596 11:08:27.839165 SRAM_EN : 1
597 11:08:27.843114 MD32_EN : 0
598 11:08:27.843199 ===================================
599 11:08:27.846696 [ANA_INIT] >>>>>>>>>>>>>>
600 11:08:27.850372 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:08:27.854167 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:08:27.858080 ===================================
603 11:08:27.858165 data_rate = 1600,PCW = 0X7600
604 11:08:27.861234 ===================================
605 11:08:27.863832 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:08:27.870973 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:08:27.877698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:08:27.880426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:08:27.884027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:08:27.887092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:08:27.890961 [ANA_INIT] flow start
612 11:08:27.894012 [ANA_INIT] PLL >>>>>>>>
613 11:08:27.894097 [ANA_INIT] PLL <<<<<<<<
614 11:08:27.897198 [ANA_INIT] MIDPI >>>>>>>>
615 11:08:27.900461 [ANA_INIT] MIDPI <<<<<<<<
616 11:08:27.900546 [ANA_INIT] DLL >>>>>>>>
617 11:08:27.904041 [ANA_INIT] flow end
618 11:08:27.906886 ============ LP4 DIFF to SE enter ============
619 11:08:27.910495 ============ LP4 DIFF to SE exit ============
620 11:08:27.913768 [ANA_INIT] <<<<<<<<<<<<<
621 11:08:27.917356 [Flow] Enable top DCM control >>>>>
622 11:08:27.920671 [Flow] Enable top DCM control <<<<<
623 11:08:27.924020 Enable DLL master slave shuffle
624 11:08:27.930282 ==============================================================
625 11:08:27.930368 Gating Mode config
626 11:08:27.937123 ==============================================================
627 11:08:27.940062 Config description:
628 11:08:27.946761 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:08:27.953606 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:08:27.960420 SELPH_MODE 0: By rank 1: By Phase
631 11:08:27.963528 ==============================================================
632 11:08:27.966721 GAT_TRACK_EN = 1
633 11:08:27.970293 RX_GATING_MODE = 2
634 11:08:27.973437 RX_GATING_TRACK_MODE = 2
635 11:08:27.976648 SELPH_MODE = 1
636 11:08:27.980086 PICG_EARLY_EN = 1
637 11:08:27.983345 VALID_LAT_VALUE = 1
638 11:08:27.990212 ==============================================================
639 11:08:27.993027 Enter into Gating configuration >>>>
640 11:08:27.996307 Exit from Gating configuration <<<<
641 11:08:27.999932 Enter into DVFS_PRE_config >>>>>
642 11:08:28.009679 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:08:28.012812 Exit from DVFS_PRE_config <<<<<
644 11:08:28.016214 Enter into PICG configuration >>>>
645 11:08:28.019833 Exit from PICG configuration <<<<
646 11:08:28.022955 [RX_INPUT] configuration >>>>>
647 11:08:28.026095 [RX_INPUT] configuration <<<<<
648 11:08:28.029625 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:08:28.035902 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:08:28.042724 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:08:28.046397 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:08:28.052816 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:08:28.059242 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:08:28.062356 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:08:28.065796 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:08:28.072660 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:08:28.076004 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:08:28.079300 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:08:28.086247 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:08:28.089323 ===================================
661 11:08:28.089409 LPDDR4 DRAM CONFIGURATION
662 11:08:28.092577 ===================================
663 11:08:28.095597 EX_ROW_EN[0] = 0x0
664 11:08:28.098973 EX_ROW_EN[1] = 0x0
665 11:08:28.099057 LP4Y_EN = 0x0
666 11:08:28.102599 WORK_FSP = 0x0
667 11:08:28.102684 WL = 0x2
668 11:08:28.105671 RL = 0x2
669 11:08:28.105755 BL = 0x2
670 11:08:28.108873 RPST = 0x0
671 11:08:28.108977 RD_PRE = 0x0
672 11:08:28.112574 WR_PRE = 0x1
673 11:08:28.112659 WR_PST = 0x0
674 11:08:28.115947 DBI_WR = 0x0
675 11:08:28.116031 DBI_RD = 0x0
676 11:08:28.119149 OTF = 0x1
677 11:08:28.122271 ===================================
678 11:08:28.125655 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:08:28.128911 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:08:28.135279 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:08:28.138668 ===================================
682 11:08:28.138752 LPDDR4 DRAM CONFIGURATION
683 11:08:28.141994 ===================================
684 11:08:28.145347 EX_ROW_EN[0] = 0x10
685 11:08:28.148904 EX_ROW_EN[1] = 0x0
686 11:08:28.149023 LP4Y_EN = 0x0
687 11:08:28.151982 WORK_FSP = 0x0
688 11:08:28.152093 WL = 0x2
689 11:08:28.155128 RL = 0x2
690 11:08:28.155212 BL = 0x2
691 11:08:28.158944 RPST = 0x0
692 11:08:28.159029 RD_PRE = 0x0
693 11:08:28.162000 WR_PRE = 0x1
694 11:08:28.162084 WR_PST = 0x0
695 11:08:28.165251 DBI_WR = 0x0
696 11:08:28.165335 DBI_RD = 0x0
697 11:08:28.169383 OTF = 0x1
698 11:08:28.172003 ===================================
699 11:08:28.178358 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:08:28.181973 nWR fixed to 40
701 11:08:28.182057 [ModeRegInit_LP4] CH0 RK0
702 11:08:28.185208 [ModeRegInit_LP4] CH0 RK1
703 11:08:28.188561 [ModeRegInit_LP4] CH1 RK0
704 11:08:28.188644 [ModeRegInit_LP4] CH1 RK1
705 11:08:28.192135 match AC timing 13
706 11:08:28.195223 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:08:28.198492 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:08:28.205538 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:08:28.209019 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:08:28.214962 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:08:28.215046 [EMI DOE] emi_dcm 0
712 11:08:28.221715 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:08:28.221814 ==
714 11:08:28.225324 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:08:28.228544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:08:28.228654 ==
717 11:08:28.234996 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:08:28.238411 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:08:28.248615 [CA 0] Center 37 (7~68) winsize 62
720 11:08:28.252118 [CA 1] Center 37 (6~68) winsize 63
721 11:08:28.255310 [CA 2] Center 34 (4~65) winsize 62
722 11:08:28.258367 [CA 3] Center 34 (4~65) winsize 62
723 11:08:28.261729 [CA 4] Center 33 (3~64) winsize 62
724 11:08:28.265124 [CA 5] Center 33 (3~64) winsize 62
725 11:08:28.265207
726 11:08:28.268847 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:08:28.268951
728 11:08:28.271709 [CATrainingPosCal] consider 1 rank data
729 11:08:28.274862 u2DelayCellTimex100 = 270/100 ps
730 11:08:28.278427 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:08:28.284945 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 11:08:28.288408 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 11:08:28.291562 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 11:08:28.294961 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 11:08:28.298188 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:08:28.298304
737 11:08:28.301480 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:08:28.301563
739 11:08:28.304592 [CBTSetCACLKResult] CA Dly = 33
740 11:08:28.307996 CS Dly: 5 (0~36)
741 11:08:28.308078 ==
742 11:08:28.311216 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:08:28.314606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:08:28.314689 ==
745 11:08:28.321561 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:08:28.324970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:08:28.334949 [CA 0] Center 38 (7~69) winsize 63
748 11:08:28.338196 [CA 1] Center 37 (7~68) winsize 62
749 11:08:28.341265 [CA 2] Center 35 (4~66) winsize 63
750 11:08:28.344925 [CA 3] Center 34 (4~65) winsize 62
751 11:08:28.348238 [CA 4] Center 34 (3~65) winsize 63
752 11:08:28.351349 [CA 5] Center 33 (3~64) winsize 62
753 11:08:28.351454
754 11:08:28.354944 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 11:08:28.355027
756 11:08:28.358453 [CATrainingPosCal] consider 2 rank data
757 11:08:28.361274 u2DelayCellTimex100 = 270/100 ps
758 11:08:28.364991 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:08:28.368189 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:08:28.374952 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 11:08:28.378387 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 11:08:28.381175 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 11:08:28.385004 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:08:28.385102
765 11:08:28.387648 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:08:28.387748
767 11:08:28.391089 [CBTSetCACLKResult] CA Dly = 33
768 11:08:28.391202 CS Dly: 6 (0~38)
769 11:08:28.394985
770 11:08:28.397657 ----->DramcWriteLeveling(PI) begin...
771 11:08:28.397823 ==
772 11:08:28.401490 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:08:28.405265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:08:28.405379 ==
775 11:08:28.408690 Write leveling (Byte 0): 31 => 31
776 11:08:28.408788 Write leveling (Byte 1): 26 => 26
777 11:08:28.412309 DramcWriteLeveling(PI) end<-----
778 11:08:28.412407
779 11:08:28.412501 ==
780 11:08:28.415998 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:08:28.419403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:08:28.422617 ==
783 11:08:28.422731 [Gating] SW mode calibration
784 11:08:28.430047 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:08:28.437006 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:08:28.440070 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:08:28.443566 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 11:08:28.450226 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 11:08:28.453785 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 11:08:28.457676 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:08:28.463376 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:08:28.466674 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:08:28.470396 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:08:28.476710 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:08:28.480382 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:08:28.483531 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:08:28.489905 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:08:28.493123 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:08:28.496742 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:08:28.503604 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:08:28.506514 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:08:28.509998 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 11:08:28.516107 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 11:08:28.519714 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 11:08:28.523141 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:08:28.530060 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:08:28.532904 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:08:28.536779 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:08:28.542682 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:08:28.545983 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:08:28.549311 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:08:28.556109 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
813 11:08:28.559096 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
814 11:08:28.562511 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:08:28.569006 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:08:28.572900 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:08:28.575540 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:08:28.582272 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:08:28.585876 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
820 11:08:28.589113 0 10 8 | B1->B0 | 3232 2828 | 0 0 | (0 1) (0 0)
821 11:08:28.595513 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
822 11:08:28.599326 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:08:28.602260 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:08:28.608880 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:08:28.612232 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:08:28.615333 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:08:28.622135 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
828 11:08:28.625193 0 11 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
829 11:08:28.628503 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
830 11:08:28.635223 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:08:28.638872 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:08:28.642182 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:08:28.648812 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:08:28.652212 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:08:28.655215 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
836 11:08:28.658414 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 11:08:28.665424 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:08:28.668320 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:08:28.671986 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:08:28.678595 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:08:28.682173 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:08:28.685883 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:08:28.691774 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:08:28.695109 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:08:28.698569 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:08:28.704917 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:08:28.708088 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:08:28.711504 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:08:28.717931 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:08:28.721804 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:08:28.725004 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 11:08:28.731689 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 11:08:28.734373 Total UI for P1: 0, mck2ui 16
854 11:08:28.738431 best dqsien dly found for B0: ( 0, 14, 4)
855 11:08:28.741144 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 11:08:28.744867 Total UI for P1: 0, mck2ui 16
857 11:08:28.747787 best dqsien dly found for B1: ( 0, 14, 10)
858 11:08:28.751176 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 11:08:28.754453 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 11:08:28.754532
861 11:08:28.757634 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 11:08:28.760962 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 11:08:28.764591 [Gating] SW calibration Done
864 11:08:28.764702 ==
865 11:08:28.767572 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:08:28.775261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:08:28.775399 ==
868 11:08:28.775494 RX Vref Scan: 0
869 11:08:28.775560
870 11:08:28.778435 RX Vref 0 -> 0, step: 1
871 11:08:28.778557
872 11:08:28.781706 RX Delay -130 -> 252, step: 16
873 11:08:28.785116 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 11:08:28.788497 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 11:08:28.791356 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 11:08:28.795115 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 11:08:28.801736 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 11:08:28.804958 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 11:08:28.807904 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 11:08:28.811572 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 11:08:28.814754 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 11:08:28.821171 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 11:08:28.825182 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 11:08:28.828282 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 11:08:28.831311 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 11:08:28.834776 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 11:08:28.841578 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 11:08:28.845415 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 11:08:28.845522 ==
890 11:08:28.848038 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:08:28.851866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:08:28.851957 ==
893 11:08:28.854629 DQS Delay:
894 11:08:28.854743 DQS0 = 0, DQS1 = 0
895 11:08:28.854842 DQM Delay:
896 11:08:28.858223 DQM0 = 86, DQM1 = 75
897 11:08:28.858337 DQ Delay:
898 11:08:28.861282 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 11:08:28.864641 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
900 11:08:28.868362 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
901 11:08:28.871262 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 11:08:28.871386
903 11:08:28.871485
904 11:08:28.871579 ==
905 11:08:28.874633 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:08:28.881475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:08:28.881589 ==
908 11:08:28.881686
909 11:08:28.881778
910 11:08:28.881869 TX Vref Scan disable
911 11:08:28.884709 == TX Byte 0 ==
912 11:08:28.888386 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 11:08:28.895154 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 11:08:28.895267 == TX Byte 1 ==
915 11:08:28.897953 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
916 11:08:28.901531 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
917 11:08:28.904505 ==
918 11:08:28.908341 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:08:28.911142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:08:28.911253 ==
921 11:08:28.924236 TX Vref=22, minBit 1, minWin=26, winSum=437
922 11:08:28.928037 TX Vref=24, minBit 3, minWin=27, winSum=444
923 11:08:28.930934 TX Vref=26, minBit 2, minWin=27, winSum=444
924 11:08:28.934085 TX Vref=28, minBit 6, minWin=27, winSum=452
925 11:08:28.937456 TX Vref=30, minBit 7, minWin=27, winSum=449
926 11:08:28.944103 TX Vref=32, minBit 2, minWin=27, winSum=449
927 11:08:28.947716 [TxChooseVref] Worse bit 6, Min win 27, Win sum 452, Final Vref 28
928 11:08:28.947821
929 11:08:28.951057 Final TX Range 1 Vref 28
930 11:08:28.951174
931 11:08:28.951269 ==
932 11:08:28.953996 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:08:28.957243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:08:28.957357 ==
935 11:08:28.960882
936 11:08:28.960995
937 11:08:28.961097 TX Vref Scan disable
938 11:08:28.964088 == TX Byte 0 ==
939 11:08:28.968198 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 11:08:28.970974 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 11:08:28.974216 == TX Byte 1 ==
942 11:08:28.977419 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
943 11:08:28.980997 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
944 11:08:28.984268
945 11:08:28.984377 [DATLAT]
946 11:08:28.984472 Freq=800, CH0 RK0
947 11:08:28.984566
948 11:08:28.987734 DATLAT Default: 0xa
949 11:08:28.987843 0, 0xFFFF, sum = 0
950 11:08:28.990838 1, 0xFFFF, sum = 0
951 11:08:28.990941 2, 0xFFFF, sum = 0
952 11:08:28.993822 3, 0xFFFF, sum = 0
953 11:08:28.993908 4, 0xFFFF, sum = 0
954 11:08:28.997673 5, 0xFFFF, sum = 0
955 11:08:29.000893 6, 0xFFFF, sum = 0
956 11:08:29.001000 7, 0xFFFF, sum = 0
957 11:08:29.004073 8, 0xFFFF, sum = 0
958 11:08:29.004166 9, 0x0, sum = 1
959 11:08:29.004236 10, 0x0, sum = 2
960 11:08:29.007321 11, 0x0, sum = 3
961 11:08:29.007471 12, 0x0, sum = 4
962 11:08:29.010681 best_step = 10
963 11:08:29.010772
964 11:08:29.010867 ==
965 11:08:29.013885 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:08:29.017116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:08:29.017226 ==
968 11:08:29.020621 RX Vref Scan: 1
969 11:08:29.020706
970 11:08:29.024087 Set Vref Range= 32 -> 127
971 11:08:29.024172
972 11:08:29.024258 RX Vref 32 -> 127, step: 1
973 11:08:29.024339
974 11:08:29.027117 RX Delay -111 -> 252, step: 8
975 11:08:29.027202
976 11:08:29.030740 Set Vref, RX VrefLevel [Byte0]: 32
977 11:08:29.033779 [Byte1]: 32
978 11:08:29.033864
979 11:08:29.038170 Set Vref, RX VrefLevel [Byte0]: 33
980 11:08:29.040641 [Byte1]: 33
981 11:08:29.044987
982 11:08:29.045073 Set Vref, RX VrefLevel [Byte0]: 34
983 11:08:29.048022 [Byte1]: 34
984 11:08:29.052525
985 11:08:29.052611 Set Vref, RX VrefLevel [Byte0]: 35
986 11:08:29.055664 [Byte1]: 35
987 11:08:29.060103
988 11:08:29.060189 Set Vref, RX VrefLevel [Byte0]: 36
989 11:08:29.063297 [Byte1]: 36
990 11:08:29.068218
991 11:08:29.068302 Set Vref, RX VrefLevel [Byte0]: 37
992 11:08:29.071550 [Byte1]: 37
993 11:08:29.075828
994 11:08:29.075946 Set Vref, RX VrefLevel [Byte0]: 38
995 11:08:29.078884 [Byte1]: 38
996 11:08:29.082777
997 11:08:29.082893 Set Vref, RX VrefLevel [Byte0]: 39
998 11:08:29.086228 [Byte1]: 39
999 11:08:29.090849
1000 11:08:29.090964 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:08:29.094535 [Byte1]: 40
1002 11:08:29.098679
1003 11:08:29.101420 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:08:29.101530 [Byte1]: 41
1005 11:08:29.105749
1006 11:08:29.105857 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:08:29.109241 [Byte1]: 42
1008 11:08:29.113608
1009 11:08:29.113712 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:08:29.116940 [Byte1]: 43
1011 11:08:29.120901
1012 11:08:29.121004 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:08:29.124255 [Byte1]: 44
1014 11:08:29.128950
1015 11:08:29.129060 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:08:29.132083 [Byte1]: 45
1017 11:08:29.136389
1018 11:08:29.136503 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:08:29.139541 [Byte1]: 46
1020 11:08:29.144318
1021 11:08:29.144422 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:08:29.147198 [Byte1]: 47
1023 11:08:29.151731
1024 11:08:29.151808 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:08:29.154973 [Byte1]: 48
1026 11:08:29.159700
1027 11:08:29.159808 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:08:29.162696 [Byte1]: 49
1029 11:08:29.167125
1030 11:08:29.167234 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:08:29.170173 [Byte1]: 50
1032 11:08:29.174525
1033 11:08:29.174607 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:08:29.178007 [Byte1]: 51
1035 11:08:29.182172
1036 11:08:29.182291 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:08:29.185436 [Byte1]: 52
1038 11:08:29.190259
1039 11:08:29.190368 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:08:29.192930 [Byte1]: 53
1041 11:08:29.197517
1042 11:08:29.197602 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:08:29.201649 [Byte1]: 54
1044 11:08:29.205082
1045 11:08:29.205159 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:08:29.208607 [Byte1]: 55
1047 11:08:29.212817
1048 11:08:29.212901 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:08:29.216537 [Byte1]: 56
1050 11:08:29.220535
1051 11:08:29.220617 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:08:29.224181 [Byte1]: 57
1053 11:08:29.228274
1054 11:08:29.228364 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:08:29.231750 [Byte1]: 58
1056 11:08:29.235939
1057 11:08:29.236027 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:08:29.239029 [Byte1]: 59
1059 11:08:29.243249
1060 11:08:29.243337 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:08:29.246597 [Byte1]: 60
1062 11:08:29.251213
1063 11:08:29.251300 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:08:29.254410 [Byte1]: 61
1065 11:08:29.258539
1066 11:08:29.258627 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:08:29.262113 [Byte1]: 62
1068 11:08:29.266492
1069 11:08:29.266584 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:08:29.269773 [Byte1]: 63
1071 11:08:29.274019
1072 11:08:29.274101 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:08:29.277481 [Byte1]: 64
1074 11:08:29.282022
1075 11:08:29.282106 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:08:29.285089 [Byte1]: 65
1077 11:08:29.289317
1078 11:08:29.289399 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:08:29.292689 [Byte1]: 66
1080 11:08:29.296753
1081 11:08:29.296826 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:08:29.300277 [Byte1]: 67
1083 11:08:29.304951
1084 11:08:29.305024 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:08:29.308040 [Byte1]: 68
1086 11:08:29.312021
1087 11:08:29.312108 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:08:29.315837 [Byte1]: 69
1089 11:08:29.319815
1090 11:08:29.319922 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:08:29.322917 [Byte1]: 70
1092 11:08:29.327766
1093 11:08:29.327853 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:08:29.330843 [Byte1]: 71
1095 11:08:29.335325
1096 11:08:29.335438 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:08:29.338486 [Byte1]: 72
1098 11:08:29.342684
1099 11:08:29.342770 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:08:29.345958 [Byte1]: 73
1101 11:08:29.350277
1102 11:08:29.350361 Set Vref, RX VrefLevel [Byte0]: 74
1103 11:08:29.353942 [Byte1]: 74
1104 11:08:29.358289
1105 11:08:29.358372 Final RX Vref Byte 0 = 55 to rank0
1106 11:08:29.361329 Final RX Vref Byte 1 = 60 to rank0
1107 11:08:29.364840 Final RX Vref Byte 0 = 55 to rank1
1108 11:08:29.368006 Final RX Vref Byte 1 = 60 to rank1==
1109 11:08:29.371135 Dram Type= 6, Freq= 0, CH_0, rank 0
1110 11:08:29.378472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1111 11:08:29.378557 ==
1112 11:08:29.378625 DQS Delay:
1113 11:08:29.378689 DQS0 = 0, DQS1 = 0
1114 11:08:29.381225 DQM Delay:
1115 11:08:29.381325 DQM0 = 88, DQM1 = 77
1116 11:08:29.384862 DQ Delay:
1117 11:08:29.387965 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1118 11:08:29.391506 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1119 11:08:29.394712 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1120 11:08:29.397615 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1121 11:08:29.397725
1122 11:08:29.397821
1123 11:08:29.404782 [DQSOSCAuto] RK0, (LSB)MR18= 0x3029, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1124 11:08:29.407844 CH0 RK0: MR19=606, MR18=3029
1125 11:08:29.414233 CH0_RK0: MR19=0x606, MR18=0x3029, DQSOSC=397, MR23=63, INC=93, DEC=62
1126 11:08:29.414331
1127 11:08:29.418110 ----->DramcWriteLeveling(PI) begin...
1128 11:08:29.418215 ==
1129 11:08:29.421063 Dram Type= 6, Freq= 0, CH_0, rank 1
1130 11:08:29.424429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 11:08:29.424533 ==
1132 11:08:29.427767 Write leveling (Byte 0): 30 => 30
1133 11:08:29.431001 Write leveling (Byte 1): 28 => 28
1134 11:08:29.434167 DramcWriteLeveling(PI) end<-----
1135 11:08:29.434280
1136 11:08:29.434387 ==
1137 11:08:29.437483 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 11:08:29.441450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 11:08:29.441562 ==
1140 11:08:29.444570 [Gating] SW mode calibration
1141 11:08:29.450823 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1142 11:08:29.457605 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1143 11:08:29.460742 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1144 11:08:29.504857 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1145 11:08:29.505398 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1146 11:08:29.505708 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 11:08:29.505807 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 11:08:29.506099 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 11:08:29.506384 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 11:08:29.506491 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 11:08:29.506783 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 11:08:29.506877 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:08:29.507165 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:08:29.510740 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:08:29.513526 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:08:29.519717 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:08:29.523137 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:08:29.526312 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:08:29.533152 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:08:29.536151 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1161 11:08:29.539831 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1162 11:08:29.546082 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:08:29.549786 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:08:29.552868 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:08:29.559532 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:08:29.562660 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:08:29.566297 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:08:29.572563 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1169 11:08:29.575823 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
1170 11:08:29.579308 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 11:08:29.586159 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 11:08:29.589064 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 11:08:29.592543 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 11:08:29.599357 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 11:08:29.602295 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1176 11:08:29.605710 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
1177 11:08:29.612241 0 10 8 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
1178 11:08:29.616305 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:08:29.619325 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:08:29.622454 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:08:29.629212 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:08:29.632405 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:08:29.635689 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:08:29.642091 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1185 11:08:29.645221 0 11 8 | B1->B0 | 2f2f 4242 | 0 0 | (0 0) (0 0)
1186 11:08:29.649329 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 11:08:29.656531 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 11:08:29.661117 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 11:08:29.664096 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 11:08:29.667239 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 11:08:29.673829 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1192 11:08:29.677951 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1193 11:08:29.680818 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 11:08:29.684257 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 11:08:29.690970 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 11:08:29.694016 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 11:08:29.697680 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 11:08:29.704451 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 11:08:29.707634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 11:08:29.710815 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:08:29.717833 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:08:29.720858 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:08:29.724108 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:08:29.730944 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:08:29.733776 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:08:29.737104 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:08:29.744069 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:08:29.747323 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1209 11:08:29.750456 Total UI for P1: 0, mck2ui 16
1210 11:08:29.754284 best dqsien dly found for B0: ( 0, 14, 2)
1211 11:08:29.757122 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1212 11:08:29.763804 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 11:08:29.763886 Total UI for P1: 0, mck2ui 16
1214 11:08:29.770124 best dqsien dly found for B1: ( 0, 14, 6)
1215 11:08:29.773690 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1216 11:08:29.776911 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1217 11:08:29.776989
1218 11:08:29.780546 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1219 11:08:29.783553 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1220 11:08:29.787135 [Gating] SW calibration Done
1221 11:08:29.787209 ==
1222 11:08:29.790208 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 11:08:29.793552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 11:08:29.793625 ==
1225 11:08:29.796987 RX Vref Scan: 0
1226 11:08:29.797063
1227 11:08:29.797128 RX Vref 0 -> 0, step: 1
1228 11:08:29.797190
1229 11:08:29.799811 RX Delay -130 -> 252, step: 16
1230 11:08:29.803108 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1231 11:08:29.809676 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1232 11:08:29.813386 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1233 11:08:29.816348 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1234 11:08:29.819699 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1235 11:08:29.823232 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1236 11:08:29.829720 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1237 11:08:29.833097 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1238 11:08:29.836159 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1239 11:08:29.839838 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1240 11:08:29.845999 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1241 11:08:29.849842 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1242 11:08:29.852467 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1243 11:08:29.856069 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1244 11:08:29.859475 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1245 11:08:29.865980 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1246 11:08:29.866114 ==
1247 11:08:29.869239 Dram Type= 6, Freq= 0, CH_0, rank 1
1248 11:08:29.872638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1249 11:08:29.872798 ==
1250 11:08:29.872867 DQS Delay:
1251 11:08:29.875922 DQS0 = 0, DQS1 = 0
1252 11:08:29.876045 DQM Delay:
1253 11:08:29.879192 DQM0 = 88, DQM1 = 78
1254 11:08:29.879275 DQ Delay:
1255 11:08:29.882620 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1256 11:08:29.885719 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1257 11:08:29.889252 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1258 11:08:29.892327 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1259 11:08:29.892411
1260 11:08:29.892477
1261 11:08:29.892539 ==
1262 11:08:29.895976 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 11:08:29.898784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 11:08:29.902325 ==
1265 11:08:29.902407
1266 11:08:29.902474
1267 11:08:29.902534 TX Vref Scan disable
1268 11:08:29.905638 == TX Byte 0 ==
1269 11:08:29.908585 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1270 11:08:29.912557 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1271 11:08:29.915393 == TX Byte 1 ==
1272 11:08:29.918622 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1273 11:08:29.922513 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1274 11:08:29.925146 ==
1275 11:08:29.928880 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 11:08:29.932370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 11:08:29.932506 ==
1278 11:08:29.944243 TX Vref=22, minBit 0, minWin=27, winSum=437
1279 11:08:29.947415 TX Vref=24, minBit 1, minWin=27, winSum=443
1280 11:08:29.950974 TX Vref=26, minBit 2, minWin=27, winSum=446
1281 11:08:29.954137 TX Vref=28, minBit 1, minWin=27, winSum=446
1282 11:08:29.957353 TX Vref=30, minBit 3, minWin=27, winSum=448
1283 11:08:29.964405 TX Vref=32, minBit 1, minWin=27, winSum=447
1284 11:08:29.967736 [TxChooseVref] Worse bit 3, Min win 27, Win sum 448, Final Vref 30
1285 11:08:29.967871
1286 11:08:29.971057 Final TX Range 1 Vref 30
1287 11:08:29.971185
1288 11:08:29.971299 ==
1289 11:08:29.974258 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 11:08:29.977547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 11:08:29.977671 ==
1292 11:08:29.977797
1293 11:08:29.981444
1294 11:08:29.981574 TX Vref Scan disable
1295 11:08:29.984554 == TX Byte 0 ==
1296 11:08:29.987634 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1297 11:08:29.990821 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1298 11:08:29.994307 == TX Byte 1 ==
1299 11:08:29.997373 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1300 11:08:30.001138 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1301 11:08:30.004141
1302 11:08:30.004216 [DATLAT]
1303 11:08:30.004279 Freq=800, CH0 RK1
1304 11:08:30.004342
1305 11:08:30.007926 DATLAT Default: 0xa
1306 11:08:30.007997 0, 0xFFFF, sum = 0
1307 11:08:30.010712 1, 0xFFFF, sum = 0
1308 11:08:30.010783 2, 0xFFFF, sum = 0
1309 11:08:30.014410 3, 0xFFFF, sum = 0
1310 11:08:30.014483 4, 0xFFFF, sum = 0
1311 11:08:30.017229 5, 0xFFFF, sum = 0
1312 11:08:30.020971 6, 0xFFFF, sum = 0
1313 11:08:30.021044 7, 0xFFFF, sum = 0
1314 11:08:30.024001 8, 0xFFFF, sum = 0
1315 11:08:30.024071 9, 0x0, sum = 1
1316 11:08:30.024137 10, 0x0, sum = 2
1317 11:08:30.027495 11, 0x0, sum = 3
1318 11:08:30.027568 12, 0x0, sum = 4
1319 11:08:30.030578 best_step = 10
1320 11:08:30.030652
1321 11:08:30.030716 ==
1322 11:08:30.033958 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 11:08:30.037678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 11:08:30.037776 ==
1325 11:08:30.040534 RX Vref Scan: 0
1326 11:08:30.040612
1327 11:08:30.040677 RX Vref 0 -> 0, step: 1
1328 11:08:30.040740
1329 11:08:30.043770 RX Delay -95 -> 252, step: 8
1330 11:08:30.050987 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1331 11:08:30.054074 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1332 11:08:30.057739 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1333 11:08:30.060779 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1334 11:08:30.064421 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1335 11:08:30.071069 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1336 11:08:30.074342 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1337 11:08:30.078048 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1338 11:08:30.080768 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1339 11:08:30.084096 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1340 11:08:30.091087 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1341 11:08:30.093986 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1342 11:08:30.097279 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1343 11:08:30.100422 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1344 11:08:30.107181 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1345 11:08:30.110859 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1346 11:08:30.110982 ==
1347 11:08:30.114140 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 11:08:30.117206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 11:08:30.117335 ==
1350 11:08:30.120340 DQS Delay:
1351 11:08:30.120469 DQS0 = 0, DQS1 = 0
1352 11:08:30.120582 DQM Delay:
1353 11:08:30.123670 DQM0 = 86, DQM1 = 76
1354 11:08:30.123800 DQ Delay:
1355 11:08:30.126980 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1356 11:08:30.130657 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1357 11:08:30.133698 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1358 11:08:30.136720 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1359 11:08:30.136843
1360 11:08:30.136967
1361 11:08:30.147092 [DQSOSCAuto] RK1, (LSB)MR18= 0x2623, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1362 11:08:30.147216 CH0 RK1: MR19=606, MR18=2623
1363 11:08:30.153479 CH0_RK1: MR19=0x606, MR18=0x2623, DQSOSC=400, MR23=63, INC=92, DEC=61
1364 11:08:30.157309 [RxdqsGatingPostProcess] freq 800
1365 11:08:30.163232 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1366 11:08:30.166469 Pre-setting of DQS Precalculation
1367 11:08:30.170109 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1368 11:08:30.170247 ==
1369 11:08:30.173381 Dram Type= 6, Freq= 0, CH_1, rank 0
1370 11:08:30.179963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 11:08:30.180091 ==
1372 11:08:30.183346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1373 11:08:30.190292 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1374 11:08:30.198963 [CA 0] Center 37 (6~68) winsize 63
1375 11:08:30.202459 [CA 1] Center 37 (6~68) winsize 63
1376 11:08:30.205583 [CA 2] Center 35 (5~66) winsize 62
1377 11:08:30.208781 [CA 3] Center 34 (4~65) winsize 62
1378 11:08:30.212561 [CA 4] Center 34 (4~65) winsize 62
1379 11:08:30.215618 [CA 5] Center 33 (3~64) winsize 62
1380 11:08:30.215756
1381 11:08:30.218820 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1382 11:08:30.218954
1383 11:08:30.222707 [CATrainingPosCal] consider 1 rank data
1384 11:08:30.225280 u2DelayCellTimex100 = 270/100 ps
1385 11:08:30.228534 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1386 11:08:30.235753 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1387 11:08:30.238753 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
1388 11:08:30.242141 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1389 11:08:30.245298 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1390 11:08:30.248516 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1391 11:08:30.248601
1392 11:08:30.252185 CA PerBit enable=1, Macro0, CA PI delay=33
1393 11:08:30.252284
1394 11:08:30.255461 [CBTSetCACLKResult] CA Dly = 33
1395 11:08:30.258656 CS Dly: 4 (0~35)
1396 11:08:30.258796 ==
1397 11:08:30.261789 Dram Type= 6, Freq= 0, CH_1, rank 1
1398 11:08:30.265088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 11:08:30.265251 ==
1400 11:08:30.271903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 11:08:30.275096 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 11:08:30.285720 [CA 0] Center 36 (6~67) winsize 62
1403 11:08:30.288874 [CA 1] Center 36 (6~67) winsize 62
1404 11:08:30.291920 [CA 2] Center 34 (4~65) winsize 62
1405 11:08:30.295312 [CA 3] Center 33 (3~64) winsize 62
1406 11:08:30.298405 [CA 4] Center 34 (4~65) winsize 62
1407 11:08:30.301821 [CA 5] Center 34 (3~65) winsize 63
1408 11:08:30.301940
1409 11:08:30.305036 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1410 11:08:30.305158
1411 11:08:30.308650 [CATrainingPosCal] consider 2 rank data
1412 11:08:30.312549 u2DelayCellTimex100 = 270/100 ps
1413 11:08:30.315611 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1414 11:08:30.319648 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1415 11:08:30.323138 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1416 11:08:30.326693 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1417 11:08:30.330294 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1418 11:08:30.334062 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1419 11:08:30.334196
1420 11:08:30.337571 CA PerBit enable=1, Macro0, CA PI delay=33
1421 11:08:30.337766
1422 11:08:30.341470 [CBTSetCACLKResult] CA Dly = 33
1423 11:08:30.345002 CS Dly: 5 (0~37)
1424 11:08:30.345127
1425 11:08:30.348715 ----->DramcWriteLeveling(PI) begin...
1426 11:08:30.348849 ==
1427 11:08:30.348964 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 11:08:30.355189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 11:08:30.355323 ==
1430 11:08:30.358685 Write leveling (Byte 0): 26 => 26
1431 11:08:30.362127 Write leveling (Byte 1): 27 => 27
1432 11:08:30.362262 DramcWriteLeveling(PI) end<-----
1433 11:08:30.365764
1434 11:08:30.365889 ==
1435 11:08:30.368725 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 11:08:30.372215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 11:08:30.372351 ==
1438 11:08:30.375439 [Gating] SW mode calibration
1439 11:08:30.382078 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1440 11:08:30.385794 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1441 11:08:30.392033 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1442 11:08:30.395355 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1443 11:08:30.398814 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 11:08:30.404876 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 11:08:30.408175 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 11:08:30.411783 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 11:08:30.418077 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 11:08:30.421492 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 11:08:30.424777 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:08:30.431393 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:08:30.434661 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:08:30.438211 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:08:30.444938 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:08:30.447897 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:08:30.451975 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:08:30.457970 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:08:30.461690 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1458 11:08:30.464715 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1459 11:08:30.471565 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:08:30.474592 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:08:30.478230 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:08:30.484579 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:08:30.487767 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:08:30.491446 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:08:30.498021 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:08:30.500934 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:08:30.504289 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1468 11:08:30.511072 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 11:08:30.514313 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 11:08:30.517732 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 11:08:30.524176 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 11:08:30.527941 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 11:08:30.531284 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 11:08:30.537390 0 10 4 | B1->B0 | 3333 3232 | 0 0 | (0 1) (0 1)
1475 11:08:30.540779 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1476 11:08:30.544443 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:08:30.550658 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:08:30.554348 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:08:30.557431 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 11:08:30.564368 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:08:30.567318 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:08:30.570494 0 11 4 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 0)
1483 11:08:30.577153 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1484 11:08:30.580373 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 11:08:30.583666 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 11:08:30.590429 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 11:08:30.594078 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 11:08:30.597148 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 11:08:30.600343 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 11:08:30.607305 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1491 11:08:30.610123 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 11:08:30.614040 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 11:08:30.620270 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 11:08:30.623544 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 11:08:30.627046 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 11:08:30.633842 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 11:08:30.636873 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 11:08:30.640264 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:08:30.646818 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:08:30.650054 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:08:30.653531 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:08:30.660086 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:08:30.663291 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:08:30.666939 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:08:30.673233 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:08:30.677026 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:08:30.680459 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1508 11:08:30.683403 Total UI for P1: 0, mck2ui 16
1509 11:08:30.686790 best dqsien dly found for B0: ( 0, 14, 6)
1510 11:08:30.693107 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 11:08:30.693191 Total UI for P1: 0, mck2ui 16
1512 11:08:30.700179 best dqsien dly found for B1: ( 0, 14, 8)
1513 11:08:30.703219 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1514 11:08:30.706463 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1515 11:08:30.706586
1516 11:08:30.710153 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1517 11:08:30.713447 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1518 11:08:30.716476 [Gating] SW calibration Done
1519 11:08:30.716610 ==
1520 11:08:30.719933 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 11:08:30.723300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1522 11:08:30.723472 ==
1523 11:08:30.726348 RX Vref Scan: 0
1524 11:08:30.726472
1525 11:08:30.726599 RX Vref 0 -> 0, step: 1
1526 11:08:30.726724
1527 11:08:30.730179 RX Delay -130 -> 252, step: 16
1528 11:08:30.733186 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1529 11:08:30.739578 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1530 11:08:30.743473 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1531 11:08:30.746645 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1532 11:08:30.749887 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1533 11:08:30.753085 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1534 11:08:30.759672 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1535 11:08:30.762867 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1536 11:08:30.766589 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1537 11:08:30.769763 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1538 11:08:30.772775 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1539 11:08:30.779567 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1540 11:08:30.782859 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1541 11:08:30.786423 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1542 11:08:30.789488 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1543 11:08:30.796126 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1544 11:08:30.796251 ==
1545 11:08:30.799763 Dram Type= 6, Freq= 0, CH_1, rank 0
1546 11:08:30.803209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1547 11:08:30.803356 ==
1548 11:08:30.803514 DQS Delay:
1549 11:08:30.806134 DQS0 = 0, DQS1 = 0
1550 11:08:30.806257 DQM Delay:
1551 11:08:30.809457 DQM0 = 87, DQM1 = 82
1552 11:08:30.809589 DQ Delay:
1553 11:08:30.812810 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1554 11:08:30.816069 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1555 11:08:30.819232 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1556 11:08:30.822422 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1557 11:08:30.822554
1558 11:08:30.822677
1559 11:08:30.822794 ==
1560 11:08:30.825721 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 11:08:30.829257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1562 11:08:30.829338 ==
1563 11:08:30.832562
1564 11:08:30.832642
1565 11:08:30.832707 TX Vref Scan disable
1566 11:08:30.835859 == TX Byte 0 ==
1567 11:08:30.839290 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1568 11:08:30.842762 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1569 11:08:30.846174 == TX Byte 1 ==
1570 11:08:30.849266 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1571 11:08:30.852338 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1572 11:08:30.852422 ==
1573 11:08:30.855626 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 11:08:30.862386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 11:08:30.862470 ==
1576 11:08:30.874359 TX Vref=22, minBit 1, minWin=27, winSum=443
1577 11:08:30.878607 TX Vref=24, minBit 0, minWin=27, winSum=445
1578 11:08:30.881140 TX Vref=26, minBit 0, minWin=27, winSum=449
1579 11:08:30.884449 TX Vref=28, minBit 2, minWin=27, winSum=454
1580 11:08:30.887901 TX Vref=30, minBit 0, minWin=27, winSum=454
1581 11:08:30.894537 TX Vref=32, minBit 0, minWin=27, winSum=454
1582 11:08:30.898405 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 28
1583 11:08:30.898489
1584 11:08:30.901502 Final TX Range 1 Vref 28
1585 11:08:30.901586
1586 11:08:30.901670 ==
1587 11:08:30.904927 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 11:08:30.908998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 11:08:30.909082 ==
1590 11:08:30.909167
1591 11:08:30.909247
1592 11:08:30.911700 TX Vref Scan disable
1593 11:08:30.914992 == TX Byte 0 ==
1594 11:08:30.918168 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1595 11:08:30.921622 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1596 11:08:30.924731 == TX Byte 1 ==
1597 11:08:30.928132 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1598 11:08:30.931314 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1599 11:08:30.931437
1600 11:08:30.934737 [DATLAT]
1601 11:08:30.934825 Freq=800, CH1 RK0
1602 11:08:30.934911
1603 11:08:30.938333 DATLAT Default: 0xa
1604 11:08:30.938464 0, 0xFFFF, sum = 0
1605 11:08:30.941296 1, 0xFFFF, sum = 0
1606 11:08:30.941381 2, 0xFFFF, sum = 0
1607 11:08:30.945005 3, 0xFFFF, sum = 0
1608 11:08:30.945090 4, 0xFFFF, sum = 0
1609 11:08:30.948415 5, 0xFFFF, sum = 0
1610 11:08:30.948500 6, 0xFFFF, sum = 0
1611 11:08:30.951575 7, 0xFFFF, sum = 0
1612 11:08:30.951660 8, 0xFFFF, sum = 0
1613 11:08:30.954681 9, 0x0, sum = 1
1614 11:08:30.954766 10, 0x0, sum = 2
1615 11:08:30.958170 11, 0x0, sum = 3
1616 11:08:30.958285 12, 0x0, sum = 4
1617 11:08:30.961152 best_step = 10
1618 11:08:30.961236
1619 11:08:30.961322 ==
1620 11:08:30.965046 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 11:08:30.967853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 11:08:30.967938 ==
1623 11:08:30.971427 RX Vref Scan: 1
1624 11:08:30.971524
1625 11:08:30.971608 Set Vref Range= 32 -> 127
1626 11:08:30.971688
1627 11:08:30.974750 RX Vref 32 -> 127, step: 1
1628 11:08:30.974833
1629 11:08:30.977918 RX Delay -95 -> 252, step: 8
1630 11:08:30.978002
1631 11:08:30.981116 Set Vref, RX VrefLevel [Byte0]: 32
1632 11:08:30.984447 [Byte1]: 32
1633 11:08:30.984532
1634 11:08:30.987914 Set Vref, RX VrefLevel [Byte0]: 33
1635 11:08:30.991031 [Byte1]: 33
1636 11:08:30.994767
1637 11:08:30.994850 Set Vref, RX VrefLevel [Byte0]: 34
1638 11:08:30.998152 [Byte1]: 34
1639 11:08:31.002330
1640 11:08:31.002432 Set Vref, RX VrefLevel [Byte0]: 35
1641 11:08:31.005567 [Byte1]: 35
1642 11:08:31.009571
1643 11:08:31.009657 Set Vref, RX VrefLevel [Byte0]: 36
1644 11:08:31.012944 [Byte1]: 36
1645 11:08:31.017938
1646 11:08:31.018023 Set Vref, RX VrefLevel [Byte0]: 37
1647 11:08:31.020588 [Byte1]: 37
1648 11:08:31.024947
1649 11:08:31.025059 Set Vref, RX VrefLevel [Byte0]: 38
1650 11:08:31.028361 [Byte1]: 38
1651 11:08:31.032502
1652 11:08:31.032619 Set Vref, RX VrefLevel [Byte0]: 39
1653 11:08:31.035797 [Byte1]: 39
1654 11:08:31.040172
1655 11:08:31.040255 Set Vref, RX VrefLevel [Byte0]: 40
1656 11:08:31.043311 [Byte1]: 40
1657 11:08:31.047489
1658 11:08:31.047572 Set Vref, RX VrefLevel [Byte0]: 41
1659 11:08:31.050904 [Byte1]: 41
1660 11:08:31.055337
1661 11:08:31.055460 Set Vref, RX VrefLevel [Byte0]: 42
1662 11:08:31.058926 [Byte1]: 42
1663 11:08:31.063123
1664 11:08:31.063208 Set Vref, RX VrefLevel [Byte0]: 43
1665 11:08:31.066208 [Byte1]: 43
1666 11:08:31.070693
1667 11:08:31.070777 Set Vref, RX VrefLevel [Byte0]: 44
1668 11:08:31.073818 [Byte1]: 44
1669 11:08:31.078276
1670 11:08:31.078359 Set Vref, RX VrefLevel [Byte0]: 45
1671 11:08:31.081370 [Byte1]: 45
1672 11:08:31.085444
1673 11:08:31.085519 Set Vref, RX VrefLevel [Byte0]: 46
1674 11:08:31.089252 [Byte1]: 46
1675 11:08:31.093440
1676 11:08:31.093517 Set Vref, RX VrefLevel [Byte0]: 47
1677 11:08:31.096543 [Byte1]: 47
1678 11:08:31.100716
1679 11:08:31.100795 Set Vref, RX VrefLevel [Byte0]: 48
1680 11:08:31.104119 [Byte1]: 48
1681 11:08:31.108377
1682 11:08:31.108463 Set Vref, RX VrefLevel [Byte0]: 49
1683 11:08:31.111607 [Byte1]: 49
1684 11:08:31.116067
1685 11:08:31.116153 Set Vref, RX VrefLevel [Byte0]: 50
1686 11:08:31.119515 [Byte1]: 50
1687 11:08:31.124224
1688 11:08:31.124307 Set Vref, RX VrefLevel [Byte0]: 51
1689 11:08:31.127143 [Byte1]: 51
1690 11:08:31.131056
1691 11:08:31.131139 Set Vref, RX VrefLevel [Byte0]: 52
1692 11:08:31.134539 [Byte1]: 52
1693 11:08:31.138674
1694 11:08:31.138758 Set Vref, RX VrefLevel [Byte0]: 53
1695 11:08:31.142098 [Byte1]: 53
1696 11:08:31.146448
1697 11:08:31.146532 Set Vref, RX VrefLevel [Byte0]: 54
1698 11:08:31.149610 [Byte1]: 54
1699 11:08:31.153939
1700 11:08:31.154046 Set Vref, RX VrefLevel [Byte0]: 55
1701 11:08:31.157503 [Byte1]: 55
1702 11:08:31.161776
1703 11:08:31.161877 Set Vref, RX VrefLevel [Byte0]: 56
1704 11:08:31.164924 [Byte1]: 56
1705 11:08:31.169170
1706 11:08:31.169254 Set Vref, RX VrefLevel [Byte0]: 57
1707 11:08:31.172524 [Byte1]: 57
1708 11:08:31.176900
1709 11:08:31.176984 Set Vref, RX VrefLevel [Byte0]: 58
1710 11:08:31.180577 [Byte1]: 58
1711 11:08:31.184704
1712 11:08:31.184788 Set Vref, RX VrefLevel [Byte0]: 59
1713 11:08:31.187984 [Byte1]: 59
1714 11:08:31.191890
1715 11:08:31.191973 Set Vref, RX VrefLevel [Byte0]: 60
1716 11:08:31.195196 [Byte1]: 60
1717 11:08:31.199449
1718 11:08:31.199546 Set Vref, RX VrefLevel [Byte0]: 61
1719 11:08:31.202683 [Byte1]: 61
1720 11:08:31.207099
1721 11:08:31.207182 Set Vref, RX VrefLevel [Byte0]: 62
1722 11:08:31.210529 [Byte1]: 62
1723 11:08:31.215113
1724 11:08:31.215197 Set Vref, RX VrefLevel [Byte0]: 63
1725 11:08:31.218090 [Byte1]: 63
1726 11:08:31.222284
1727 11:08:31.222382 Set Vref, RX VrefLevel [Byte0]: 64
1728 11:08:31.226251 [Byte1]: 64
1729 11:08:31.230348
1730 11:08:31.230431 Set Vref, RX VrefLevel [Byte0]: 65
1731 11:08:31.233829 [Byte1]: 65
1732 11:08:31.237684
1733 11:08:31.237768 Set Vref, RX VrefLevel [Byte0]: 66
1734 11:08:31.241266 [Byte1]: 66
1735 11:08:31.245065
1736 11:08:31.245148 Set Vref, RX VrefLevel [Byte0]: 67
1737 11:08:31.248623 [Byte1]: 67
1738 11:08:31.252717
1739 11:08:31.252804 Set Vref, RX VrefLevel [Byte0]: 68
1740 11:08:31.256076 [Byte1]: 68
1741 11:08:31.260559
1742 11:08:31.260643 Set Vref, RX VrefLevel [Byte0]: 69
1743 11:08:31.263624 [Byte1]: 69
1744 11:08:31.267966
1745 11:08:31.268049 Set Vref, RX VrefLevel [Byte0]: 70
1746 11:08:31.272057 [Byte1]: 70
1747 11:08:31.275542
1748 11:08:31.275626 Set Vref, RX VrefLevel [Byte0]: 71
1749 11:08:31.278752 [Byte1]: 71
1750 11:08:31.283209
1751 11:08:31.283292 Set Vref, RX VrefLevel [Byte0]: 72
1752 11:08:31.286281 [Byte1]: 72
1753 11:08:31.290550
1754 11:08:31.290633 Set Vref, RX VrefLevel [Byte0]: 73
1755 11:08:31.294296 [Byte1]: 73
1756 11:08:31.298689
1757 11:08:31.298785 Set Vref, RX VrefLevel [Byte0]: 74
1758 11:08:31.301961 [Byte1]: 74
1759 11:08:31.306040
1760 11:08:31.306124 Set Vref, RX VrefLevel [Byte0]: 75
1761 11:08:31.309464 [Byte1]: 75
1762 11:08:31.313923
1763 11:08:31.314037 Final RX Vref Byte 0 = 56 to rank0
1764 11:08:31.317231 Final RX Vref Byte 1 = 59 to rank0
1765 11:08:31.320127 Final RX Vref Byte 0 = 56 to rank1
1766 11:08:31.323603 Final RX Vref Byte 1 = 59 to rank1==
1767 11:08:31.326834 Dram Type= 6, Freq= 0, CH_1, rank 0
1768 11:08:31.333309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1769 11:08:31.333394 ==
1770 11:08:31.333507 DQS Delay:
1771 11:08:31.336895 DQS0 = 0, DQS1 = 0
1772 11:08:31.337008 DQM Delay:
1773 11:08:31.337093 DQM0 = 85, DQM1 = 81
1774 11:08:31.340223 DQ Delay:
1775 11:08:31.343044 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1776 11:08:31.346928 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =84
1777 11:08:31.349905 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1778 11:08:31.353025 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1779 11:08:31.353166
1780 11:08:31.353253
1781 11:08:31.359809 [DQSOSCAuto] RK0, (LSB)MR18= 0x182c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1782 11:08:31.363030 CH1 RK0: MR19=606, MR18=182C
1783 11:08:31.369523 CH1_RK0: MR19=0x606, MR18=0x182C, DQSOSC=398, MR23=63, INC=93, DEC=62
1784 11:08:31.369632
1785 11:08:31.372804 ----->DramcWriteLeveling(PI) begin...
1786 11:08:31.372903 ==
1787 11:08:31.376211 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 11:08:31.379713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 11:08:31.379794 ==
1790 11:08:31.383482 Write leveling (Byte 0): 23 => 23
1791 11:08:31.386835 Write leveling (Byte 1): 29 => 29
1792 11:08:31.389826 DramcWriteLeveling(PI) end<-----
1793 11:08:31.389907
1794 11:08:31.389971 ==
1795 11:08:31.392847 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 11:08:31.396552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 11:08:31.396634 ==
1798 11:08:31.399229 [Gating] SW mode calibration
1799 11:08:31.406147 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1800 11:08:31.413165 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1801 11:08:31.416314 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1802 11:08:31.422874 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1803 11:08:31.425941 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1804 11:08:31.429613 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 11:08:31.436120 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 11:08:31.439204 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 11:08:31.442751 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 11:08:31.449215 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 11:08:31.452504 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:08:31.455915 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:08:31.459608 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:08:31.466353 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:08:31.469157 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:08:31.472789 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:08:31.479216 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:08:31.482879 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:08:31.485902 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1818 11:08:31.492690 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1819 11:08:31.495828 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1820 11:08:31.499218 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:08:31.505978 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:08:31.509149 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:08:31.512239 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:08:31.519010 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:08:31.522212 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:08:31.525373 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1827 11:08:31.532191 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1828 11:08:31.535449 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 11:08:31.538774 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 11:08:31.545379 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 11:08:31.548679 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 11:08:31.551872 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 11:08:31.558923 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1834 11:08:31.562202 0 10 4 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (1 1)
1835 11:08:31.565369 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
1836 11:08:31.572134 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:08:31.575059 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:08:31.578315 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:08:31.585074 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:08:31.588300 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:08:31.591761 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1842 11:08:31.598626 0 11 4 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
1843 11:08:31.601583 0 11 8 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
1844 11:08:31.604772 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 11:08:31.611798 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 11:08:31.615080 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 11:08:31.618300 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 11:08:31.624592 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 11:08:31.628627 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1850 11:08:31.631934 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1851 11:08:31.638120 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1852 11:08:31.641213 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 11:08:31.644541 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 11:08:31.651097 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 11:08:31.654348 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 11:08:31.658107 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 11:08:31.664739 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 11:08:31.668048 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:08:31.671089 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:08:31.677562 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:08:31.680776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:08:31.684572 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:08:31.690972 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:08:31.694331 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:08:31.697732 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1866 11:08:31.704028 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 11:08:31.704110 Total UI for P1: 0, mck2ui 16
1868 11:08:31.707756 best dqsien dly found for B0: ( 0, 14, 0)
1869 11:08:31.711046 Total UI for P1: 0, mck2ui 16
1870 11:08:31.714075 best dqsien dly found for B1: ( 0, 14, 2)
1871 11:08:31.717292 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1872 11:08:31.724170 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1873 11:08:31.724268
1874 11:08:31.727699 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1875 11:08:31.730774 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1876 11:08:31.734186 [Gating] SW calibration Done
1877 11:08:31.734282 ==
1878 11:08:31.737339 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 11:08:31.740396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 11:08:31.740494 ==
1881 11:08:31.740591 RX Vref Scan: 0
1882 11:08:31.743919
1883 11:08:31.744017 RX Vref 0 -> 0, step: 1
1884 11:08:31.744114
1885 11:08:31.747121 RX Delay -130 -> 252, step: 16
1886 11:08:31.750469 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1887 11:08:31.757393 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1888 11:08:31.760622 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1889 11:08:31.763833 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1890 11:08:31.767191 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1891 11:08:31.770780 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1892 11:08:31.773976 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1893 11:08:31.780369 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1894 11:08:31.783649 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1895 11:08:31.787259 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1896 11:08:31.790232 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1897 11:08:31.793675 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1898 11:08:31.800410 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1899 11:08:31.803651 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1900 11:08:31.807021 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1901 11:08:31.810480 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1902 11:08:31.810618 ==
1903 11:08:31.813845 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 11:08:31.820250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 11:08:31.820349 ==
1906 11:08:31.820446 DQS Delay:
1907 11:08:31.823400 DQS0 = 0, DQS1 = 0
1908 11:08:31.823501 DQM Delay:
1909 11:08:31.823654 DQM0 = 84, DQM1 = 80
1910 11:08:31.826619 DQ Delay:
1911 11:08:31.830388 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1912 11:08:31.833905 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1913 11:08:31.837087 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1914 11:08:31.839820 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1915 11:08:31.839901
1916 11:08:31.839999
1917 11:08:31.840090 ==
1918 11:08:31.843628 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 11:08:31.846722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 11:08:31.846821 ==
1921 11:08:31.846917
1922 11:08:31.846992
1923 11:08:31.850457 TX Vref Scan disable
1924 11:08:31.853839 == TX Byte 0 ==
1925 11:08:31.856557 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1926 11:08:31.860124 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1927 11:08:31.862974 == TX Byte 1 ==
1928 11:08:31.866886 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1929 11:08:31.870260 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1930 11:08:31.870357 ==
1931 11:08:31.873193 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 11:08:31.876386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 11:08:31.879878 ==
1934 11:08:31.891728 TX Vref=22, minBit 3, minWin=26, winSum=442
1935 11:08:31.894921 TX Vref=24, minBit 6, minWin=26, winSum=448
1936 11:08:31.898221 TX Vref=26, minBit 1, minWin=27, winSum=451
1937 11:08:31.901718 TX Vref=28, minBit 1, minWin=27, winSum=453
1938 11:08:31.904785 TX Vref=30, minBit 0, minWin=27, winSum=452
1939 11:08:31.912029 TX Vref=32, minBit 1, minWin=27, winSum=449
1940 11:08:31.914688 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 28
1941 11:08:31.914786
1942 11:08:31.918226 Final TX Range 1 Vref 28
1943 11:08:31.918324
1944 11:08:31.918421 ==
1945 11:08:31.921152 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 11:08:31.924694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 11:08:31.927967 ==
1948 11:08:31.928064
1949 11:08:31.928142
1950 11:08:31.928219 TX Vref Scan disable
1951 11:08:31.931494 == TX Byte 0 ==
1952 11:08:31.934706 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1953 11:08:31.941306 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1954 11:08:31.941404 == TX Byte 1 ==
1955 11:08:31.944708 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1956 11:08:31.951375 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1957 11:08:31.951488
1958 11:08:31.951584 [DATLAT]
1959 11:08:31.951660 Freq=800, CH1 RK1
1960 11:08:31.951751
1961 11:08:31.954542 DATLAT Default: 0xa
1962 11:08:31.954625 0, 0xFFFF, sum = 0
1963 11:08:31.958425 1, 0xFFFF, sum = 0
1964 11:08:31.961652 2, 0xFFFF, sum = 0
1965 11:08:31.961751 3, 0xFFFF, sum = 0
1966 11:08:31.964864 4, 0xFFFF, sum = 0
1967 11:08:31.964962 5, 0xFFFF, sum = 0
1968 11:08:31.968169 6, 0xFFFF, sum = 0
1969 11:08:31.968269 7, 0xFFFF, sum = 0
1970 11:08:31.971359 8, 0xFFFF, sum = 0
1971 11:08:31.971479 9, 0x0, sum = 1
1972 11:08:31.974514 10, 0x0, sum = 2
1973 11:08:31.974614 11, 0x0, sum = 3
1974 11:08:31.974711 12, 0x0, sum = 4
1975 11:08:31.977778 best_step = 10
1976 11:08:31.977875
1977 11:08:31.977970 ==
1978 11:08:31.981380 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 11:08:31.984912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 11:08:31.985012 ==
1981 11:08:31.987835 RX Vref Scan: 0
1982 11:08:31.987931
1983 11:08:31.988029 RX Vref 0 -> 0, step: 1
1984 11:08:31.991260
1985 11:08:31.991383 RX Delay -95 -> 252, step: 8
1986 11:08:31.998277 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1987 11:08:32.001683 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1988 11:08:32.005223 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1989 11:08:32.008250 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1990 11:08:32.011715 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1991 11:08:32.018047 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1992 11:08:32.021144 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1993 11:08:32.024488 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1994 11:08:32.028073 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1995 11:08:32.031396 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1996 11:08:32.037799 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
1997 11:08:32.041074 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1998 11:08:32.044365 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1999 11:08:32.047586 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2000 11:08:32.054647 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2001 11:08:32.057876 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2002 11:08:32.057960 ==
2003 11:08:32.061382 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 11:08:32.064314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 11:08:32.064398 ==
2006 11:08:32.067336 DQS Delay:
2007 11:08:32.067444 DQS0 = 0, DQS1 = 0
2008 11:08:32.067530 DQM Delay:
2009 11:08:32.070923 DQM0 = 86, DQM1 = 82
2010 11:08:32.071031 DQ Delay:
2011 11:08:32.074182 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2012 11:08:32.077505 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2013 11:08:32.080646 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2014 11:08:32.083990 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2015 11:08:32.084075
2016 11:08:32.084161
2017 11:08:32.093787 [DQSOSCAuto] RK1, (LSB)MR18= 0x1936, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2018 11:08:32.097368 CH1 RK1: MR19=606, MR18=1936
2019 11:08:32.100958 CH1_RK1: MR19=0x606, MR18=0x1936, DQSOSC=396, MR23=63, INC=94, DEC=62
2020 11:08:32.103782 [RxdqsGatingPostProcess] freq 800
2021 11:08:32.110431 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2022 11:08:32.113989 Pre-setting of DQS Precalculation
2023 11:08:32.117433 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2024 11:08:32.127153 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2025 11:08:32.133836 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2026 11:08:32.133922
2027 11:08:32.134016
2028 11:08:32.136783 [Calibration Summary] 1600 Mbps
2029 11:08:32.136868 CH 0, Rank 0
2030 11:08:32.140132 SW Impedance : PASS
2031 11:08:32.140215 DUTY Scan : NO K
2032 11:08:32.143304 ZQ Calibration : PASS
2033 11:08:32.146610 Jitter Meter : NO K
2034 11:08:32.146693 CBT Training : PASS
2035 11:08:32.149892 Write leveling : PASS
2036 11:08:32.153703 RX DQS gating : PASS
2037 11:08:32.153787 RX DQ/DQS(RDDQC) : PASS
2038 11:08:32.156974 TX DQ/DQS : PASS
2039 11:08:32.160290 RX DATLAT : PASS
2040 11:08:32.160372 RX DQ/DQS(Engine): PASS
2041 11:08:32.164000 TX OE : NO K
2042 11:08:32.164083 All Pass.
2043 11:08:32.164149
2044 11:08:32.167252 CH 0, Rank 1
2045 11:08:32.167366 SW Impedance : PASS
2046 11:08:32.170368 DUTY Scan : NO K
2047 11:08:32.170451 ZQ Calibration : PASS
2048 11:08:32.173728 Jitter Meter : NO K
2049 11:08:32.177137 CBT Training : PASS
2050 11:08:32.177219 Write leveling : PASS
2051 11:08:32.180270 RX DQS gating : PASS
2052 11:08:32.183839 RX DQ/DQS(RDDQC) : PASS
2053 11:08:32.183919 TX DQ/DQS : PASS
2054 11:08:32.187014 RX DATLAT : PASS
2055 11:08:32.190840 RX DQ/DQS(Engine): PASS
2056 11:08:32.190920 TX OE : NO K
2057 11:08:32.194036 All Pass.
2058 11:08:32.194116
2059 11:08:32.194181 CH 1, Rank 0
2060 11:08:32.197252 SW Impedance : PASS
2061 11:08:32.197333 DUTY Scan : NO K
2062 11:08:32.199864 ZQ Calibration : PASS
2063 11:08:32.203551 Jitter Meter : NO K
2064 11:08:32.203628 CBT Training : PASS
2065 11:08:32.206726 Write leveling : PASS
2066 11:08:32.209920 RX DQS gating : PASS
2067 11:08:32.210003 RX DQ/DQS(RDDQC) : PASS
2068 11:08:32.213503 TX DQ/DQS : PASS
2069 11:08:32.216582 RX DATLAT : PASS
2070 11:08:32.216665 RX DQ/DQS(Engine): PASS
2071 11:08:32.220530 TX OE : NO K
2072 11:08:32.220612 All Pass.
2073 11:08:32.220677
2074 11:08:32.223525 CH 1, Rank 1
2075 11:08:32.223620 SW Impedance : PASS
2076 11:08:32.227221 DUTY Scan : NO K
2077 11:08:32.227292 ZQ Calibration : PASS
2078 11:08:32.229774 Jitter Meter : NO K
2079 11:08:32.233175 CBT Training : PASS
2080 11:08:32.233256 Write leveling : PASS
2081 11:08:32.236747 RX DQS gating : PASS
2082 11:08:32.239837 RX DQ/DQS(RDDQC) : PASS
2083 11:08:32.239918 TX DQ/DQS : PASS
2084 11:08:32.243078 RX DATLAT : PASS
2085 11:08:32.246519 RX DQ/DQS(Engine): PASS
2086 11:08:32.246600 TX OE : NO K
2087 11:08:32.250282 All Pass.
2088 11:08:32.250377
2089 11:08:32.250440 DramC Write-DBI off
2090 11:08:32.253043 PER_BANK_REFRESH: Hybrid Mode
2091 11:08:32.256642 TX_TRACKING: ON
2092 11:08:32.259589 [GetDramInforAfterCalByMRR] Vendor 6.
2093 11:08:32.263005 [GetDramInforAfterCalByMRR] Revision 606.
2094 11:08:32.266204 [GetDramInforAfterCalByMRR] Revision 2 0.
2095 11:08:32.266285 MR0 0x3b3b
2096 11:08:32.266349 MR8 0x5151
2097 11:08:32.272662 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 11:08:32.272743
2099 11:08:32.272807 MR0 0x3b3b
2100 11:08:32.272867 MR8 0x5151
2101 11:08:32.275928 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 11:08:32.276009
2103 11:08:32.285836 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2104 11:08:32.289335 [FAST_K] Save calibration result to emmc
2105 11:08:32.292818 [FAST_K] Save calibration result to emmc
2106 11:08:32.295949 dram_init: config_dvfs: 1
2107 11:08:32.299242 dramc_set_vcore_voltage set vcore to 662500
2108 11:08:32.302515 Read voltage for 1200, 2
2109 11:08:32.302596 Vio18 = 0
2110 11:08:32.305926 Vcore = 662500
2111 11:08:32.306010 Vdram = 0
2112 11:08:32.306074 Vddq = 0
2113 11:08:32.306134 Vmddr = 0
2114 11:08:32.313118 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2115 11:08:32.316009 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2116 11:08:32.318882 MEM_TYPE=3, freq_sel=15
2117 11:08:32.322359 sv_algorithm_assistance_LP4_1600
2118 11:08:32.325608 ============ PULL DRAM RESETB DOWN ============
2119 11:08:32.332272 ========== PULL DRAM RESETB DOWN end =========
2120 11:08:32.336006 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2121 11:08:32.338897 ===================================
2122 11:08:32.342512 LPDDR4 DRAM CONFIGURATION
2123 11:08:32.345770 ===================================
2124 11:08:32.345851 EX_ROW_EN[0] = 0x0
2125 11:08:32.348988 EX_ROW_EN[1] = 0x0
2126 11:08:32.349069 LP4Y_EN = 0x0
2127 11:08:32.352149 WORK_FSP = 0x0
2128 11:08:32.352230 WL = 0x4
2129 11:08:32.355670 RL = 0x4
2130 11:08:32.355751 BL = 0x2
2131 11:08:32.358767 RPST = 0x0
2132 11:08:32.358847 RD_PRE = 0x0
2133 11:08:32.362147 WR_PRE = 0x1
2134 11:08:32.365803 WR_PST = 0x0
2135 11:08:32.365883 DBI_WR = 0x0
2136 11:08:32.368632 DBI_RD = 0x0
2137 11:08:32.368714 OTF = 0x1
2138 11:08:32.372019 ===================================
2139 11:08:32.375834 ===================================
2140 11:08:32.375916 ANA top config
2141 11:08:32.378897 ===================================
2142 11:08:32.382330 DLL_ASYNC_EN = 0
2143 11:08:32.385854 ALL_SLAVE_EN = 0
2144 11:08:32.389271 NEW_RANK_MODE = 1
2145 11:08:32.392022 DLL_IDLE_MODE = 1
2146 11:08:32.392103 LP45_APHY_COMB_EN = 1
2147 11:08:32.395352 TX_ODT_DIS = 1
2148 11:08:32.398755 NEW_8X_MODE = 1
2149 11:08:32.401877 ===================================
2150 11:08:32.405498 ===================================
2151 11:08:32.408824 data_rate = 2400
2152 11:08:32.412015 CKR = 1
2153 11:08:32.412098 DQ_P2S_RATIO = 8
2154 11:08:32.415234 ===================================
2155 11:08:32.419103 CA_P2S_RATIO = 8
2156 11:08:32.422673 DQ_CA_OPEN = 0
2157 11:08:32.425656 DQ_SEMI_OPEN = 0
2158 11:08:32.428790 CA_SEMI_OPEN = 0
2159 11:08:32.432010 CA_FULL_RATE = 0
2160 11:08:32.432091 DQ_CKDIV4_EN = 0
2161 11:08:32.435500 CA_CKDIV4_EN = 0
2162 11:08:32.438677 CA_PREDIV_EN = 0
2163 11:08:32.441859 PH8_DLY = 17
2164 11:08:32.445391 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2165 11:08:32.448648 DQ_AAMCK_DIV = 4
2166 11:08:32.448731 CA_AAMCK_DIV = 4
2167 11:08:32.451722 CA_ADMCK_DIV = 4
2168 11:08:32.455575 DQ_TRACK_CA_EN = 0
2169 11:08:32.458316 CA_PICK = 1200
2170 11:08:32.461892 CA_MCKIO = 1200
2171 11:08:32.465075 MCKIO_SEMI = 0
2172 11:08:32.468061 PLL_FREQ = 2366
2173 11:08:32.471602 DQ_UI_PI_RATIO = 32
2174 11:08:32.471722 CA_UI_PI_RATIO = 0
2175 11:08:32.475055 ===================================
2176 11:08:32.478156 ===================================
2177 11:08:32.481403 memory_type:LPDDR4
2178 11:08:32.485314 GP_NUM : 10
2179 11:08:32.485418 SRAM_EN : 1
2180 11:08:32.488285 MD32_EN : 0
2181 11:08:32.491317 ===================================
2182 11:08:32.494786 [ANA_INIT] >>>>>>>>>>>>>>
2183 11:08:32.498318 <<<<<< [CONFIGURE PHASE]: ANA_TX
2184 11:08:32.501586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2185 11:08:32.504832 ===================================
2186 11:08:32.504914 data_rate = 2400,PCW = 0X5b00
2187 11:08:32.507858 ===================================
2188 11:08:32.511439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2189 11:08:32.517911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 11:08:32.524460 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 11:08:32.528108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2192 11:08:32.531141 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2193 11:08:32.534906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2194 11:08:32.537946 [ANA_INIT] flow start
2195 11:08:32.538029 [ANA_INIT] PLL >>>>>>>>
2196 11:08:32.541177 [ANA_INIT] PLL <<<<<<<<
2197 11:08:32.544651 [ANA_INIT] MIDPI >>>>>>>>
2198 11:08:32.548741 [ANA_INIT] MIDPI <<<<<<<<
2199 11:08:32.548823 [ANA_INIT] DLL >>>>>>>>
2200 11:08:32.551126 [ANA_INIT] DLL <<<<<<<<
2201 11:08:32.551254 [ANA_INIT] flow end
2202 11:08:32.557814 ============ LP4 DIFF to SE enter ============
2203 11:08:32.561343 ============ LP4 DIFF to SE exit ============
2204 11:08:32.564633 [ANA_INIT] <<<<<<<<<<<<<
2205 11:08:32.567877 [Flow] Enable top DCM control >>>>>
2206 11:08:32.570900 [Flow] Enable top DCM control <<<<<
2207 11:08:32.574368 Enable DLL master slave shuffle
2208 11:08:32.577675 ==============================================================
2209 11:08:32.581153 Gating Mode config
2210 11:08:32.584258 ==============================================================
2211 11:08:32.587648 Config description:
2212 11:08:32.597619 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2213 11:08:32.604314 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2214 11:08:32.607457 SELPH_MODE 0: By rank 1: By Phase
2215 11:08:32.613843 ==============================================================
2216 11:08:32.617533 GAT_TRACK_EN = 1
2217 11:08:32.620813 RX_GATING_MODE = 2
2218 11:08:32.623879 RX_GATING_TRACK_MODE = 2
2219 11:08:32.627258 SELPH_MODE = 1
2220 11:08:32.630385 PICG_EARLY_EN = 1
2221 11:08:32.634110 VALID_LAT_VALUE = 1
2222 11:08:32.637091 ==============================================================
2223 11:08:32.640676 Enter into Gating configuration >>>>
2224 11:08:32.644062 Exit from Gating configuration <<<<
2225 11:08:32.647730 Enter into DVFS_PRE_config >>>>>
2226 11:08:32.657641 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2227 11:08:32.660314 Exit from DVFS_PRE_config <<<<<
2228 11:08:32.663576 Enter into PICG configuration >>>>
2229 11:08:32.667170 Exit from PICG configuration <<<<
2230 11:08:32.670624 [RX_INPUT] configuration >>>>>
2231 11:08:32.673797 [RX_INPUT] configuration <<<<<
2232 11:08:32.680796 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2233 11:08:32.683332 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2234 11:08:32.690164 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 11:08:32.696795 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 11:08:32.703553 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 11:08:32.709762 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 11:08:32.712942 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2239 11:08:32.716270 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2240 11:08:32.719568 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2241 11:08:32.726504 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2242 11:08:32.729859 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2243 11:08:32.732843 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2244 11:08:32.736220 ===================================
2245 11:08:32.739669 LPDDR4 DRAM CONFIGURATION
2246 11:08:32.742581 ===================================
2247 11:08:32.746491 EX_ROW_EN[0] = 0x0
2248 11:08:32.746576 EX_ROW_EN[1] = 0x0
2249 11:08:32.749872 LP4Y_EN = 0x0
2250 11:08:32.749957 WORK_FSP = 0x0
2251 11:08:32.752971 WL = 0x4
2252 11:08:32.753054 RL = 0x4
2253 11:08:32.756426 BL = 0x2
2254 11:08:32.756538 RPST = 0x0
2255 11:08:32.759333 RD_PRE = 0x0
2256 11:08:32.759450 WR_PRE = 0x1
2257 11:08:32.762720 WR_PST = 0x0
2258 11:08:32.762823 DBI_WR = 0x0
2259 11:08:32.766378 DBI_RD = 0x0
2260 11:08:32.766478 OTF = 0x1
2261 11:08:32.769827 ===================================
2262 11:08:32.776124 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2263 11:08:32.779299 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2264 11:08:32.783088 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 11:08:32.785925 ===================================
2266 11:08:32.789411 LPDDR4 DRAM CONFIGURATION
2267 11:08:32.792424 ===================================
2268 11:08:32.796336 EX_ROW_EN[0] = 0x10
2269 11:08:32.796442 EX_ROW_EN[1] = 0x0
2270 11:08:32.799271 LP4Y_EN = 0x0
2271 11:08:32.799378 WORK_FSP = 0x0
2272 11:08:32.802783 WL = 0x4
2273 11:08:32.802883 RL = 0x4
2274 11:08:32.805868 BL = 0x2
2275 11:08:32.805969 RPST = 0x0
2276 11:08:32.809092 RD_PRE = 0x0
2277 11:08:32.809199 WR_PRE = 0x1
2278 11:08:32.812510 WR_PST = 0x0
2279 11:08:32.812586 DBI_WR = 0x0
2280 11:08:32.815919 DBI_RD = 0x0
2281 11:08:32.815995 OTF = 0x1
2282 11:08:32.819106 ===================================
2283 11:08:32.825690 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2284 11:08:32.825795 ==
2285 11:08:32.829241 Dram Type= 6, Freq= 0, CH_0, rank 0
2286 11:08:32.835613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2287 11:08:32.835736 ==
2288 11:08:32.835851 [Duty_Offset_Calibration]
2289 11:08:32.838948 B0:2 B1:0 CA:4
2290 11:08:32.839077
2291 11:08:32.842035 [DutyScan_Calibration_Flow] k_type=0
2292 11:08:32.850935
2293 11:08:32.851068 ==CLK 0==
2294 11:08:32.854572 Final CLK duty delay cell = 0
2295 11:08:32.857593 [0] MAX Duty = 5156%(X100), DQS PI = 14
2296 11:08:32.860670 [0] MIN Duty = 4969%(X100), DQS PI = 8
2297 11:08:32.860797 [0] AVG Duty = 5062%(X100)
2298 11:08:32.864007
2299 11:08:32.867369 CH0 CLK Duty spec in!! Max-Min= 187%
2300 11:08:32.870653 [DutyScan_Calibration_Flow] ====Done====
2301 11:08:32.870777
2302 11:08:32.873991 [DutyScan_Calibration_Flow] k_type=1
2303 11:08:32.890155
2304 11:08:32.890237 ==DQS 0 ==
2305 11:08:32.893569 Final DQS duty delay cell = 0
2306 11:08:32.897557 [0] MAX Duty = 5156%(X100), DQS PI = 18
2307 11:08:32.900149 [0] MIN Duty = 5093%(X100), DQS PI = 2
2308 11:08:32.900232 [0] AVG Duty = 5124%(X100)
2309 11:08:32.903645
2310 11:08:32.903721 ==DQS 1 ==
2311 11:08:32.906746 Final DQS duty delay cell = 0
2312 11:08:32.910396 [0] MAX Duty = 5125%(X100), DQS PI = 50
2313 11:08:32.913385 [0] MIN Duty = 5000%(X100), DQS PI = 0
2314 11:08:32.916760 [0] AVG Duty = 5062%(X100)
2315 11:08:32.916845
2316 11:08:32.920011 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2317 11:08:32.920092
2318 11:08:32.923619 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2319 11:08:32.926362 [DutyScan_Calibration_Flow] ====Done====
2320 11:08:32.926442
2321 11:08:32.929901 [DutyScan_Calibration_Flow] k_type=3
2322 11:08:32.946406
2323 11:08:32.946530 ==DQM 0 ==
2324 11:08:32.949926 Final DQM duty delay cell = 0
2325 11:08:32.953353 [0] MAX Duty = 5125%(X100), DQS PI = 20
2326 11:08:32.956674 [0] MIN Duty = 4844%(X100), DQS PI = 52
2327 11:08:32.959965 [0] AVG Duty = 4984%(X100)
2328 11:08:32.960045
2329 11:08:32.960108 ==DQM 1 ==
2330 11:08:32.963184 Final DQM duty delay cell = 0
2331 11:08:32.966639 [0] MAX Duty = 5000%(X100), DQS PI = 6
2332 11:08:32.969944 [0] MIN Duty = 4875%(X100), DQS PI = 12
2333 11:08:32.973105 [0] AVG Duty = 4937%(X100)
2334 11:08:32.973186
2335 11:08:32.976213 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2336 11:08:32.976299
2337 11:08:32.979570 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2338 11:08:32.982925 [DutyScan_Calibration_Flow] ====Done====
2339 11:08:32.983006
2340 11:08:32.986190 [DutyScan_Calibration_Flow] k_type=2
2341 11:08:33.003179
2342 11:08:33.003261 ==DQ 0 ==
2343 11:08:33.006394 Final DQ duty delay cell = 0
2344 11:08:33.009672 [0] MAX Duty = 5125%(X100), DQS PI = 18
2345 11:08:33.012905 [0] MIN Duty = 4969%(X100), DQS PI = 56
2346 11:08:33.013056 [0] AVG Duty = 5047%(X100)
2347 11:08:33.016706
2348 11:08:33.016807 ==DQ 1 ==
2349 11:08:33.019712 Final DQ duty delay cell = 0
2350 11:08:33.023012 [0] MAX Duty = 5156%(X100), DQS PI = 6
2351 11:08:33.026207 [0] MIN Duty = 4938%(X100), DQS PI = 16
2352 11:08:33.026288 [0] AVG Duty = 5047%(X100)
2353 11:08:33.026352
2354 11:08:33.030188 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2355 11:08:33.032823
2356 11:08:33.036492 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2357 11:08:33.039749 [DutyScan_Calibration_Flow] ====Done====
2358 11:08:33.039831 ==
2359 11:08:33.042963 Dram Type= 6, Freq= 0, CH_1, rank 0
2360 11:08:33.046711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 11:08:33.046793 ==
2362 11:08:33.050060 [Duty_Offset_Calibration]
2363 11:08:33.050141 B0:0 B1:-1 CA:3
2364 11:08:33.050205
2365 11:08:33.052940 [DutyScan_Calibration_Flow] k_type=0
2366 11:08:33.062222
2367 11:08:33.062302 ==CLK 0==
2368 11:08:33.065713 Final CLK duty delay cell = -4
2369 11:08:33.068873 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2370 11:08:33.072050 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2371 11:08:33.075295 [-4] AVG Duty = 4938%(X100)
2372 11:08:33.075433
2373 11:08:33.078931 CH1 CLK Duty spec in!! Max-Min= 124%
2374 11:08:33.081939 [DutyScan_Calibration_Flow] ====Done====
2375 11:08:33.082020
2376 11:08:33.085446 [DutyScan_Calibration_Flow] k_type=1
2377 11:08:33.101920
2378 11:08:33.102002 ==DQS 0 ==
2379 11:08:33.105068 Final DQS duty delay cell = 0
2380 11:08:33.108368 [0] MAX Duty = 5187%(X100), DQS PI = 18
2381 11:08:33.111516 [0] MIN Duty = 4938%(X100), DQS PI = 38
2382 11:08:33.115634 [0] AVG Duty = 5062%(X100)
2383 11:08:33.115715
2384 11:08:33.115779 ==DQS 1 ==
2385 11:08:33.118863 Final DQS duty delay cell = 0
2386 11:08:33.121657 [0] MAX Duty = 5156%(X100), DQS PI = 8
2387 11:08:33.124716 [0] MIN Duty = 5031%(X100), DQS PI = 24
2388 11:08:33.127914 [0] AVG Duty = 5093%(X100)
2389 11:08:33.128028
2390 11:08:33.131592 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2391 11:08:33.131674
2392 11:08:33.134979 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2393 11:08:33.138220 [DutyScan_Calibration_Flow] ====Done====
2394 11:08:33.138303
2395 11:08:33.141228 [DutyScan_Calibration_Flow] k_type=3
2396 11:08:33.158565
2397 11:08:33.158650 ==DQM 0 ==
2398 11:08:33.161488 Final DQM duty delay cell = 0
2399 11:08:33.165121 [0] MAX Duty = 5031%(X100), DQS PI = 26
2400 11:08:33.168181 [0] MIN Duty = 4813%(X100), DQS PI = 38
2401 11:08:33.171475 [0] AVG Duty = 4922%(X100)
2402 11:08:33.171582
2403 11:08:33.171674 ==DQM 1 ==
2404 11:08:33.174856 Final DQM duty delay cell = 0
2405 11:08:33.178124 [0] MAX Duty = 4969%(X100), DQS PI = 32
2406 11:08:33.181584 [0] MIN Duty = 4844%(X100), DQS PI = 0
2407 11:08:33.184587 [0] AVG Duty = 4906%(X100)
2408 11:08:33.184739
2409 11:08:33.187761 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2410 11:08:33.187866
2411 11:08:33.191284 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2412 11:08:33.195017 [DutyScan_Calibration_Flow] ====Done====
2413 11:08:33.195098
2414 11:08:33.198314 [DutyScan_Calibration_Flow] k_type=2
2415 11:08:33.214008
2416 11:08:33.214089 ==DQ 0 ==
2417 11:08:33.217341 Final DQ duty delay cell = -4
2418 11:08:33.220498 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2419 11:08:33.223912 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2420 11:08:33.227686 [-4] AVG Duty = 4937%(X100)
2421 11:08:33.227779
2422 11:08:33.227844 ==DQ 1 ==
2423 11:08:33.230674 Final DQ duty delay cell = 0
2424 11:08:33.234256 [0] MAX Duty = 5031%(X100), DQS PI = 34
2425 11:08:33.236927 [0] MIN Duty = 4844%(X100), DQS PI = 62
2426 11:08:33.240691 [0] AVG Duty = 4937%(X100)
2427 11:08:33.240774
2428 11:08:33.243885 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2429 11:08:33.243968
2430 11:08:33.246886 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2431 11:08:33.250264 [DutyScan_Calibration_Flow] ====Done====
2432 11:08:33.253640 nWR fixed to 30
2433 11:08:33.257202 [ModeRegInit_LP4] CH0 RK0
2434 11:08:33.257322 [ModeRegInit_LP4] CH0 RK1
2435 11:08:33.260508 [ModeRegInit_LP4] CH1 RK0
2436 11:08:33.263620 [ModeRegInit_LP4] CH1 RK1
2437 11:08:33.263702 match AC timing 7
2438 11:08:33.270585 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2439 11:08:33.273606 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2440 11:08:33.276881 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2441 11:08:33.283605 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2442 11:08:33.287233 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2443 11:08:33.287315 ==
2444 11:08:33.290313 Dram Type= 6, Freq= 0, CH_0, rank 0
2445 11:08:33.293340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 11:08:33.293449 ==
2447 11:08:33.300021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2448 11:08:33.306721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2449 11:08:33.314784 [CA 0] Center 39 (9~70) winsize 62
2450 11:08:33.317732 [CA 1] Center 39 (9~69) winsize 61
2451 11:08:33.321161 [CA 2] Center 35 (5~66) winsize 62
2452 11:08:33.324329 [CA 3] Center 35 (5~66) winsize 62
2453 11:08:33.327712 [CA 4] Center 33 (3~64) winsize 62
2454 11:08:33.331134 [CA 5] Center 33 (3~63) winsize 61
2455 11:08:33.331216
2456 11:08:33.334278 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2457 11:08:33.334387
2458 11:08:33.337276 [CATrainingPosCal] consider 1 rank data
2459 11:08:33.340929 u2DelayCellTimex100 = 270/100 ps
2460 11:08:33.343959 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2461 11:08:33.350774 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2462 11:08:33.353939 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2463 11:08:33.357076 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2464 11:08:33.361153 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2465 11:08:33.363970 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2466 11:08:33.364055
2467 11:08:33.367165 CA PerBit enable=1, Macro0, CA PI delay=33
2468 11:08:33.367274
2469 11:08:33.370419 [CBTSetCACLKResult] CA Dly = 33
2470 11:08:33.370493 CS Dly: 7 (0~38)
2471 11:08:33.373759 ==
2472 11:08:33.377571 Dram Type= 6, Freq= 0, CH_0, rank 1
2473 11:08:33.380534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2474 11:08:33.380633 ==
2475 11:08:33.383849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2476 11:08:33.390781 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2477 11:08:33.399996 [CA 0] Center 39 (9~70) winsize 62
2478 11:08:33.403754 [CA 1] Center 39 (9~70) winsize 62
2479 11:08:33.407019 [CA 2] Center 35 (5~66) winsize 62
2480 11:08:33.410133 [CA 3] Center 35 (5~66) winsize 62
2481 11:08:33.413499 [CA 4] Center 34 (4~65) winsize 62
2482 11:08:33.416622 [CA 5] Center 33 (3~64) winsize 62
2483 11:08:33.416699
2484 11:08:33.419963 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2485 11:08:33.420045
2486 11:08:33.423036 [CATrainingPosCal] consider 2 rank data
2487 11:08:33.427068 u2DelayCellTimex100 = 270/100 ps
2488 11:08:33.429782 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2489 11:08:33.436340 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2490 11:08:33.439636 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2491 11:08:33.443151 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2492 11:08:33.446461 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2493 11:08:33.449510 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2494 11:08:33.449585
2495 11:08:33.453139 CA PerBit enable=1, Macro0, CA PI delay=33
2496 11:08:33.453213
2497 11:08:33.456106 [CBTSetCACLKResult] CA Dly = 33
2498 11:08:33.456185 CS Dly: 8 (0~41)
2499 11:08:33.459577
2500 11:08:33.463034 ----->DramcWriteLeveling(PI) begin...
2501 11:08:33.463132 ==
2502 11:08:33.466003 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 11:08:33.470167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 11:08:33.470252 ==
2505 11:08:33.472971 Write leveling (Byte 0): 29 => 29
2506 11:08:33.476327 Write leveling (Byte 1): 27 => 27
2507 11:08:33.479780 DramcWriteLeveling(PI) end<-----
2508 11:08:33.479852
2509 11:08:33.479912 ==
2510 11:08:33.482682 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 11:08:33.486400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 11:08:33.486472 ==
2513 11:08:33.489481 [Gating] SW mode calibration
2514 11:08:33.496239 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2515 11:08:33.502969 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2516 11:08:33.506154 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2517 11:08:33.509319 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
2518 11:08:33.516067 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 11:08:33.519518 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 11:08:33.522871 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 11:08:33.529464 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 11:08:33.532738 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2523 11:08:33.536461 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
2524 11:08:33.542519 1 0 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
2525 11:08:33.545718 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 11:08:33.549073 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 11:08:33.555703 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 11:08:33.558944 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 11:08:33.562362 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 11:08:33.569268 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2531 11:08:33.572009 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2532 11:08:33.575382 1 1 0 | B1->B0 | 2626 4646 | 1 0 | (0 0) (0 0)
2533 11:08:33.582121 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 11:08:33.585387 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 11:08:33.588482 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 11:08:33.595162 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 11:08:33.598828 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 11:08:33.602092 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2539 11:08:33.605892 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2540 11:08:33.611811 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2541 11:08:33.615700 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 11:08:33.618592 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 11:08:33.625172 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 11:08:33.628267 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 11:08:33.631901 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 11:08:33.638349 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 11:08:33.641942 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 11:08:33.644836 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 11:08:33.651851 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 11:08:33.655066 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 11:08:33.658558 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:08:33.664829 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:08:33.668061 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:08:33.671644 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2555 11:08:33.678236 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2556 11:08:33.681289 Total UI for P1: 0, mck2ui 16
2557 11:08:33.684474 best dqsien dly found for B0: ( 1, 3, 24)
2558 11:08:33.687739 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 11:08:33.690935 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 11:08:33.694514 Total UI for P1: 0, mck2ui 16
2561 11:08:33.697752 best dqsien dly found for B1: ( 1, 4, 0)
2562 11:08:33.701338 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2563 11:08:33.704939 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2564 11:08:33.705059
2565 11:08:33.711479 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2566 11:08:33.714555 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2567 11:08:33.717813 [Gating] SW calibration Done
2568 11:08:33.717947 ==
2569 11:08:33.720893 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 11:08:33.724573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 11:08:33.724691 ==
2572 11:08:33.724803 RX Vref Scan: 0
2573 11:08:33.724912
2574 11:08:33.727731 RX Vref 0 -> 0, step: 1
2575 11:08:33.727849
2576 11:08:33.730898 RX Delay -40 -> 252, step: 8
2577 11:08:33.734260 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2578 11:08:33.737907 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2579 11:08:33.744199 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2580 11:08:33.747515 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2581 11:08:33.751024 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2582 11:08:33.754526 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2583 11:08:33.757849 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2584 11:08:33.764222 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2585 11:08:33.767576 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2586 11:08:33.770793 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2587 11:08:33.774617 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2588 11:08:33.777728 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2589 11:08:33.783853 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2590 11:08:33.787585 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2591 11:08:33.790761 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2592 11:08:33.793989 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2593 11:08:33.794070 ==
2594 11:08:33.797246 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 11:08:33.803763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 11:08:33.803844 ==
2597 11:08:33.803909 DQS Delay:
2598 11:08:33.803968 DQS0 = 0, DQS1 = 0
2599 11:08:33.807265 DQM Delay:
2600 11:08:33.807345 DQM0 = 119, DQM1 = 107
2601 11:08:33.810387 DQ Delay:
2602 11:08:33.813866 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2603 11:08:33.817142 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2604 11:08:33.820544 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2605 11:08:33.823782 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2606 11:08:33.823863
2607 11:08:33.823927
2608 11:08:33.823986 ==
2609 11:08:33.827620 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 11:08:33.830286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 11:08:33.830367 ==
2612 11:08:33.833940
2613 11:08:33.834020
2614 11:08:33.834084 TX Vref Scan disable
2615 11:08:33.837382 == TX Byte 0 ==
2616 11:08:33.840798 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2617 11:08:33.843777 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2618 11:08:33.847226 == TX Byte 1 ==
2619 11:08:33.850277 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2620 11:08:33.853565 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2621 11:08:33.853646 ==
2622 11:08:33.857204 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 11:08:33.863597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 11:08:33.863678 ==
2625 11:08:33.874261 TX Vref=22, minBit 4, minWin=25, winSum=412
2626 11:08:33.878144 TX Vref=24, minBit 10, minWin=24, winSum=413
2627 11:08:33.881406 TX Vref=26, minBit 1, minWin=25, winSum=425
2628 11:08:33.884361 TX Vref=28, minBit 1, minWin=26, winSum=429
2629 11:08:33.888041 TX Vref=30, minBit 10, minWin=26, winSum=429
2630 11:08:33.894260 TX Vref=32, minBit 2, minWin=26, winSum=427
2631 11:08:33.897468 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
2632 11:08:33.897590
2633 11:08:33.901133 Final TX Range 1 Vref 28
2634 11:08:33.901250
2635 11:08:33.901363 ==
2636 11:08:33.904141 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 11:08:33.907467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 11:08:33.907581 ==
2639 11:08:33.911087
2640 11:08:33.911202
2641 11:08:33.911308 TX Vref Scan disable
2642 11:08:33.914107 == TX Byte 0 ==
2643 11:08:33.917571 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2644 11:08:33.920933 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2645 11:08:33.924327 == TX Byte 1 ==
2646 11:08:33.928139 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2647 11:08:33.930608 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2648 11:08:33.934388
2649 11:08:33.934484 [DATLAT]
2650 11:08:33.934563 Freq=1200, CH0 RK0
2651 11:08:33.934657
2652 11:08:33.937595 DATLAT Default: 0xd
2653 11:08:33.937675 0, 0xFFFF, sum = 0
2654 11:08:33.941025 1, 0xFFFF, sum = 0
2655 11:08:33.941110 2, 0xFFFF, sum = 0
2656 11:08:33.944356 3, 0xFFFF, sum = 0
2657 11:08:33.947550 4, 0xFFFF, sum = 0
2658 11:08:33.947632 5, 0xFFFF, sum = 0
2659 11:08:33.950870 6, 0xFFFF, sum = 0
2660 11:08:33.950992 7, 0xFFFF, sum = 0
2661 11:08:33.954123 8, 0xFFFF, sum = 0
2662 11:08:33.954225 9, 0xFFFF, sum = 0
2663 11:08:33.957209 10, 0xFFFF, sum = 0
2664 11:08:33.957308 11, 0xFFFF, sum = 0
2665 11:08:33.961028 12, 0x0, sum = 1
2666 11:08:33.961112 13, 0x0, sum = 2
2667 11:08:33.964148 14, 0x0, sum = 3
2668 11:08:33.964276 15, 0x0, sum = 4
2669 11:08:33.964389 best_step = 13
2670 11:08:33.967175
2671 11:08:33.967296 ==
2672 11:08:33.970705 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 11:08:33.974105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 11:08:33.974223 ==
2675 11:08:33.974336 RX Vref Scan: 1
2676 11:08:33.974439
2677 11:08:33.977510 Set Vref Range= 32 -> 127
2678 11:08:33.977630
2679 11:08:33.980726 RX Vref 32 -> 127, step: 1
2680 11:08:33.980823
2681 11:08:33.984497 RX Delay -21 -> 252, step: 4
2682 11:08:33.984591
2683 11:08:33.987409 Set Vref, RX VrefLevel [Byte0]: 32
2684 11:08:33.990564 [Byte1]: 32
2685 11:08:33.990647
2686 11:08:33.994078 Set Vref, RX VrefLevel [Byte0]: 33
2687 11:08:33.997647 [Byte1]: 33
2688 11:08:34.000694
2689 11:08:34.000819 Set Vref, RX VrefLevel [Byte0]: 34
2690 11:08:34.004100 [Byte1]: 34
2691 11:08:34.009180
2692 11:08:34.011816 Set Vref, RX VrefLevel [Byte0]: 35
2693 11:08:34.015107 [Byte1]: 35
2694 11:08:34.015239
2695 11:08:34.018719 Set Vref, RX VrefLevel [Byte0]: 36
2696 11:08:34.022141 [Byte1]: 36
2697 11:08:34.022256
2698 11:08:34.025486 Set Vref, RX VrefLevel [Byte0]: 37
2699 11:08:34.028175 [Byte1]: 37
2700 11:08:34.032333
2701 11:08:34.032436 Set Vref, RX VrefLevel [Byte0]: 38
2702 11:08:34.035516 [Byte1]: 38
2703 11:08:34.040612
2704 11:08:34.040692 Set Vref, RX VrefLevel [Byte0]: 39
2705 11:08:34.043553 [Byte1]: 39
2706 11:08:34.048228
2707 11:08:34.048308 Set Vref, RX VrefLevel [Byte0]: 40
2708 11:08:34.051303 [Byte1]: 40
2709 11:08:34.056127
2710 11:08:34.056208 Set Vref, RX VrefLevel [Byte0]: 41
2711 11:08:34.059399 [Byte1]: 41
2712 11:08:34.064428
2713 11:08:34.064509 Set Vref, RX VrefLevel [Byte0]: 42
2714 11:08:34.067405 [Byte1]: 42
2715 11:08:34.072048
2716 11:08:34.072129 Set Vref, RX VrefLevel [Byte0]: 43
2717 11:08:34.075498 [Byte1]: 43
2718 11:08:34.079829
2719 11:08:34.079957 Set Vref, RX VrefLevel [Byte0]: 44
2720 11:08:34.083539 [Byte1]: 44
2721 11:08:34.087626
2722 11:08:34.087706 Set Vref, RX VrefLevel [Byte0]: 45
2723 11:08:34.091223 [Byte1]: 45
2724 11:08:34.095635
2725 11:08:34.095720 Set Vref, RX VrefLevel [Byte0]: 46
2726 11:08:34.099001 [Byte1]: 46
2727 11:08:34.103911
2728 11:08:34.103994 Set Vref, RX VrefLevel [Byte0]: 47
2729 11:08:34.107466 [Byte1]: 47
2730 11:08:34.111503
2731 11:08:34.111619 Set Vref, RX VrefLevel [Byte0]: 48
2732 11:08:34.114783 [Byte1]: 48
2733 11:08:34.119628
2734 11:08:34.119748 Set Vref, RX VrefLevel [Byte0]: 49
2735 11:08:34.122857 [Byte1]: 49
2736 11:08:34.127516
2737 11:08:34.127654 Set Vref, RX VrefLevel [Byte0]: 50
2738 11:08:34.131087 [Byte1]: 50
2739 11:08:34.135957
2740 11:08:34.136079 Set Vref, RX VrefLevel [Byte0]: 51
2741 11:08:34.138977 [Byte1]: 51
2742 11:08:34.143540
2743 11:08:34.143659 Set Vref, RX VrefLevel [Byte0]: 52
2744 11:08:34.146493 [Byte1]: 52
2745 11:08:34.151178
2746 11:08:34.151303 Set Vref, RX VrefLevel [Byte0]: 53
2747 11:08:34.154614 [Byte1]: 53
2748 11:08:34.159264
2749 11:08:34.159422 Set Vref, RX VrefLevel [Byte0]: 54
2750 11:08:34.162570 [Byte1]: 54
2751 11:08:34.166895
2752 11:08:34.167012 Set Vref, RX VrefLevel [Byte0]: 55
2753 11:08:34.171277 [Byte1]: 55
2754 11:08:34.175495
2755 11:08:34.175635 Set Vref, RX VrefLevel [Byte0]: 56
2756 11:08:34.178413 [Byte1]: 56
2757 11:08:34.182670
2758 11:08:34.182791 Set Vref, RX VrefLevel [Byte0]: 57
2759 11:08:34.186435 [Byte1]: 57
2760 11:08:34.191078
2761 11:08:34.191199 Set Vref, RX VrefLevel [Byte0]: 58
2762 11:08:34.194452 [Byte1]: 58
2763 11:08:34.198637
2764 11:08:34.198739 Set Vref, RX VrefLevel [Byte0]: 59
2765 11:08:34.202185 [Byte1]: 59
2766 11:08:34.206823
2767 11:08:34.206905 Set Vref, RX VrefLevel [Byte0]: 60
2768 11:08:34.209799 [Byte1]: 60
2769 11:08:34.214845
2770 11:08:34.214926 Set Vref, RX VrefLevel [Byte0]: 61
2771 11:08:34.217780 [Byte1]: 61
2772 11:08:34.222897
2773 11:08:34.222979 Set Vref, RX VrefLevel [Byte0]: 62
2774 11:08:34.225842 [Byte1]: 62
2775 11:08:34.230569
2776 11:08:34.230650 Set Vref, RX VrefLevel [Byte0]: 63
2777 11:08:34.233753 [Byte1]: 63
2778 11:08:34.238434
2779 11:08:34.238516 Set Vref, RX VrefLevel [Byte0]: 64
2780 11:08:34.241763 [Byte1]: 64
2781 11:08:34.246316
2782 11:08:34.246441 Set Vref, RX VrefLevel [Byte0]: 65
2783 11:08:34.249477 [Byte1]: 65
2784 11:08:34.254216
2785 11:08:34.254342 Set Vref, RX VrefLevel [Byte0]: 66
2786 11:08:34.257616 [Byte1]: 66
2787 11:08:34.262094
2788 11:08:34.262221 Set Vref, RX VrefLevel [Byte0]: 67
2789 11:08:34.265579 [Byte1]: 67
2790 11:08:34.270127
2791 11:08:34.270264 Final RX Vref Byte 0 = 56 to rank0
2792 11:08:34.273285 Final RX Vref Byte 1 = 49 to rank0
2793 11:08:34.276684 Final RX Vref Byte 0 = 56 to rank1
2794 11:08:34.280060 Final RX Vref Byte 1 = 49 to rank1==
2795 11:08:34.283561 Dram Type= 6, Freq= 0, CH_0, rank 0
2796 11:08:34.289718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2797 11:08:34.289825 ==
2798 11:08:34.289918 DQS Delay:
2799 11:08:34.293192 DQS0 = 0, DQS1 = 0
2800 11:08:34.293294 DQM Delay:
2801 11:08:34.293385 DQM0 = 119, DQM1 = 105
2802 11:08:34.296596 DQ Delay:
2803 11:08:34.299833 DQ0 =118, DQ1 =116, DQ2 =116, DQ3 =116
2804 11:08:34.303334 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2805 11:08:34.306150 DQ8 =94, DQ9 =92, DQ10 =104, DQ11 =100
2806 11:08:34.309908 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =112
2807 11:08:34.309992
2808 11:08:34.310082
2809 11:08:34.319625 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2810 11:08:34.319708 CH0 RK0: MR19=403, MR18=1FC
2811 11:08:34.326175 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2812 11:08:34.326286
2813 11:08:34.329776 ----->DramcWriteLeveling(PI) begin...
2814 11:08:34.329859 ==
2815 11:08:34.333182 Dram Type= 6, Freq= 0, CH_0, rank 1
2816 11:08:34.336042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 11:08:34.340021 ==
2818 11:08:34.343135 Write leveling (Byte 0): 29 => 29
2819 11:08:34.343260 Write leveling (Byte 1): 27 => 27
2820 11:08:34.346177 DramcWriteLeveling(PI) end<-----
2821 11:08:34.346299
2822 11:08:34.346393 ==
2823 11:08:34.349698 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 11:08:34.356383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 11:08:34.356474 ==
2826 11:08:34.359494 [Gating] SW mode calibration
2827 11:08:34.365919 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2828 11:08:34.369060 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2829 11:08:34.375927 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
2830 11:08:34.379089 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2831 11:08:34.382702 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 11:08:34.389434 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 11:08:34.392582 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 11:08:34.395716 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2835 11:08:34.402493 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2836 11:08:34.405707 0 15 28 | B1->B0 | 3434 2626 | 0 0 | (0 0) (0 0)
2837 11:08:34.409164 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2838 11:08:34.415428 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 11:08:34.419066 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 11:08:34.422341 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 11:08:34.429032 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 11:08:34.432946 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 11:08:34.435733 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2844 11:08:34.441984 1 0 28 | B1->B0 | 2626 4242 | 0 0 | (0 0) (0 0)
2845 11:08:34.445323 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2846 11:08:34.448728 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 11:08:34.455171 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 11:08:34.458987 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 11:08:34.462050 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 11:08:34.468773 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 11:08:34.471755 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2852 11:08:34.475194 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2853 11:08:34.481878 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2854 11:08:34.485291 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 11:08:34.488514 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 11:08:34.494749 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 11:08:34.498205 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 11:08:34.501419 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 11:08:34.508214 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 11:08:34.511345 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 11:08:34.514833 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 11:08:34.520913 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 11:08:34.524305 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 11:08:34.527723 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 11:08:34.534447 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 11:08:34.537485 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2867 11:08:34.540735 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2868 11:08:34.547419 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2869 11:08:34.550912 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2870 11:08:34.554079 Total UI for P1: 0, mck2ui 16
2871 11:08:34.557527 best dqsien dly found for B0: ( 1, 3, 24)
2872 11:08:34.560575 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 11:08:34.564227 Total UI for P1: 0, mck2ui 16
2874 11:08:34.567359 best dqsien dly found for B1: ( 1, 4, 0)
2875 11:08:34.570397 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2876 11:08:34.573814 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2877 11:08:34.573990
2878 11:08:34.577228 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2879 11:08:34.583986 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2880 11:08:34.584069 [Gating] SW calibration Done
2881 11:08:34.584135 ==
2882 11:08:34.587136 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 11:08:34.593789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 11:08:34.593872 ==
2885 11:08:34.593938 RX Vref Scan: 0
2886 11:08:34.593999
2887 11:08:34.596926 RX Vref 0 -> 0, step: 1
2888 11:08:34.597043
2889 11:08:34.600598 RX Delay -40 -> 252, step: 8
2890 11:08:34.603814 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2891 11:08:34.607556 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2892 11:08:34.610433 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2893 11:08:34.617305 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2894 11:08:34.621121 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2895 11:08:34.623804 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2896 11:08:34.626703 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2897 11:08:34.629974 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2898 11:08:34.637131 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2899 11:08:34.640325 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2900 11:08:34.643408 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2901 11:08:34.646505 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2902 11:08:34.650205 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2903 11:08:34.656505 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2904 11:08:34.659588 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2905 11:08:34.663112 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2906 11:08:34.663195 ==
2907 11:08:34.666670 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 11:08:34.669465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 11:08:34.672898 ==
2910 11:08:34.672981 DQS Delay:
2911 11:08:34.673046 DQS0 = 0, DQS1 = 0
2912 11:08:34.676634 DQM Delay:
2913 11:08:34.676716 DQM0 = 118, DQM1 = 106
2914 11:08:34.679857 DQ Delay:
2915 11:08:34.682970 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2916 11:08:34.686864 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2917 11:08:34.689793 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
2918 11:08:34.692902 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =115
2919 11:08:34.693002
2920 11:08:34.693092
2921 11:08:34.693178 ==
2922 11:08:34.696260 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 11:08:34.699825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 11:08:34.699909 ==
2925 11:08:34.699978
2926 11:08:34.700065
2927 11:08:34.703347 TX Vref Scan disable
2928 11:08:34.706431 == TX Byte 0 ==
2929 11:08:34.709882 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2930 11:08:34.712781 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2931 11:08:34.716475 == TX Byte 1 ==
2932 11:08:34.719328 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2933 11:08:34.723205 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2934 11:08:34.723308 ==
2935 11:08:34.726166 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 11:08:34.729476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 11:08:34.732648 ==
2938 11:08:34.743261 TX Vref=22, minBit 0, minWin=25, winSum=411
2939 11:08:34.746457 TX Vref=24, minBit 0, minWin=26, winSum=420
2940 11:08:34.749700 TX Vref=26, minBit 0, minWin=26, winSum=421
2941 11:08:34.753228 TX Vref=28, minBit 15, minWin=25, winSum=426
2942 11:08:34.756550 TX Vref=30, minBit 2, minWin=26, winSum=428
2943 11:08:34.763115 TX Vref=32, minBit 12, minWin=25, winSum=421
2944 11:08:34.766155 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 30
2945 11:08:34.766238
2946 11:08:34.769524 Final TX Range 1 Vref 30
2947 11:08:34.769605
2948 11:08:34.769669 ==
2949 11:08:34.773285 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 11:08:34.776181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 11:08:34.776262 ==
2952 11:08:34.779776
2953 11:08:34.779856
2954 11:08:34.779920 TX Vref Scan disable
2955 11:08:34.782978 == TX Byte 0 ==
2956 11:08:34.786272 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2957 11:08:34.792867 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2958 11:08:34.792950 == TX Byte 1 ==
2959 11:08:34.795869 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2960 11:08:34.802471 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2961 11:08:34.802553
2962 11:08:34.802619 [DATLAT]
2963 11:08:34.802679 Freq=1200, CH0 RK1
2964 11:08:34.802738
2965 11:08:34.805741 DATLAT Default: 0xd
2966 11:08:34.805824 0, 0xFFFF, sum = 0
2967 11:08:34.809720 1, 0xFFFF, sum = 0
2968 11:08:34.812814 2, 0xFFFF, sum = 0
2969 11:08:34.812919 3, 0xFFFF, sum = 0
2970 11:08:34.816299 4, 0xFFFF, sum = 0
2971 11:08:34.816383 5, 0xFFFF, sum = 0
2972 11:08:34.819131 6, 0xFFFF, sum = 0
2973 11:08:34.819241 7, 0xFFFF, sum = 0
2974 11:08:34.822685 8, 0xFFFF, sum = 0
2975 11:08:34.822796 9, 0xFFFF, sum = 0
2976 11:08:34.826003 10, 0xFFFF, sum = 0
2977 11:08:34.826103 11, 0xFFFF, sum = 0
2978 11:08:34.829068 12, 0x0, sum = 1
2979 11:08:34.829152 13, 0x0, sum = 2
2980 11:08:34.832646 14, 0x0, sum = 3
2981 11:08:34.832729 15, 0x0, sum = 4
2982 11:08:34.836307 best_step = 13
2983 11:08:34.836388
2984 11:08:34.836453 ==
2985 11:08:34.839063 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 11:08:34.842545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 11:08:34.842628 ==
2988 11:08:34.842694 RX Vref Scan: 0
2989 11:08:34.842754
2990 11:08:34.846081 RX Vref 0 -> 0, step: 1
2991 11:08:34.846163
2992 11:08:34.849336 RX Delay -21 -> 252, step: 4
2993 11:08:34.855925 iDelay=191, Bit 0, Center 116 (55 ~ 178) 124
2994 11:08:34.859032 iDelay=191, Bit 1, Center 118 (51 ~ 186) 136
2995 11:08:34.862225 iDelay=191, Bit 2, Center 114 (51 ~ 178) 128
2996 11:08:34.865875 iDelay=191, Bit 3, Center 114 (51 ~ 178) 128
2997 11:08:34.869167 iDelay=191, Bit 4, Center 120 (55 ~ 186) 132
2998 11:08:34.872356 iDelay=191, Bit 5, Center 110 (47 ~ 174) 128
2999 11:08:34.879090 iDelay=191, Bit 6, Center 128 (67 ~ 190) 124
3000 11:08:34.882547 iDelay=191, Bit 7, Center 122 (59 ~ 186) 128
3001 11:08:34.885710 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3002 11:08:34.888796 iDelay=191, Bit 9, Center 92 (27 ~ 158) 132
3003 11:08:34.892893 iDelay=191, Bit 10, Center 108 (43 ~ 174) 132
3004 11:08:34.899197 iDelay=191, Bit 11, Center 96 (31 ~ 162) 132
3005 11:08:34.901970 iDelay=191, Bit 12, Center 112 (51 ~ 174) 124
3006 11:08:34.905958 iDelay=191, Bit 13, Center 110 (47 ~ 174) 128
3007 11:08:34.908850 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3008 11:08:34.915232 iDelay=191, Bit 15, Center 114 (51 ~ 178) 128
3009 11:08:34.915312 ==
3010 11:08:34.919076 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 11:08:34.922430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 11:08:34.922511 ==
3013 11:08:34.922575 DQS Delay:
3014 11:08:34.926028 DQS0 = 0, DQS1 = 0
3015 11:08:34.926109 DQM Delay:
3016 11:08:34.928750 DQM0 = 117, DQM1 = 105
3017 11:08:34.928830 DQ Delay:
3018 11:08:34.931849 DQ0 =116, DQ1 =118, DQ2 =114, DQ3 =114
3019 11:08:34.935497 DQ4 =120, DQ5 =110, DQ6 =128, DQ7 =122
3020 11:08:34.938874 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =96
3021 11:08:34.941790 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3022 11:08:34.941872
3023 11:08:34.941935
3024 11:08:34.952085 [DQSOSCAuto] RK1, (LSB)MR18= 0xfcfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3025 11:08:34.955087 CH0 RK1: MR19=303, MR18=FCFA
3026 11:08:34.958608 CH0_RK1: MR19=0x303, MR18=0xFCFA, DQSOSC=411, MR23=63, INC=38, DEC=25
3027 11:08:34.962218 [RxdqsGatingPostProcess] freq 1200
3028 11:08:34.968613 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3029 11:08:34.972016 best DQS0 dly(2T, 0.5T) = (0, 11)
3030 11:08:34.975521 best DQS1 dly(2T, 0.5T) = (0, 12)
3031 11:08:34.978607 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3032 11:08:34.981946 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3033 11:08:34.985241 best DQS0 dly(2T, 0.5T) = (0, 11)
3034 11:08:34.988243 best DQS1 dly(2T, 0.5T) = (0, 12)
3035 11:08:34.992051 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3036 11:08:34.995013 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3037 11:08:34.995094 Pre-setting of DQS Precalculation
3038 11:08:35.001760 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3039 11:08:35.001841 ==
3040 11:08:35.005576 Dram Type= 6, Freq= 0, CH_1, rank 0
3041 11:08:35.008579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 11:08:35.008659 ==
3043 11:08:35.015550 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3044 11:08:35.021526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3045 11:08:35.029422 [CA 0] Center 38 (8~68) winsize 61
3046 11:08:35.032502 [CA 1] Center 37 (7~68) winsize 62
3047 11:08:35.036515 [CA 2] Center 35 (5~65) winsize 61
3048 11:08:35.038857 [CA 3] Center 33 (3~64) winsize 62
3049 11:08:35.042104 [CA 4] Center 34 (4~65) winsize 62
3050 11:08:35.045574 [CA 5] Center 33 (3~64) winsize 62
3051 11:08:35.045655
3052 11:08:35.048990 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3053 11:08:35.049071
3054 11:08:35.052083 [CATrainingPosCal] consider 1 rank data
3055 11:08:35.055786 u2DelayCellTimex100 = 270/100 ps
3056 11:08:35.058626 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3057 11:08:35.065605 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3058 11:08:35.068963 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3059 11:08:35.072259 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3060 11:08:35.075858 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3061 11:08:35.079166 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3062 11:08:35.079247
3063 11:08:35.082540 CA PerBit enable=1, Macro0, CA PI delay=33
3064 11:08:35.082620
3065 11:08:35.085225 [CBTSetCACLKResult] CA Dly = 33
3066 11:08:35.085306 CS Dly: 5 (0~36)
3067 11:08:35.089070 ==
3068 11:08:35.091926 Dram Type= 6, Freq= 0, CH_1, rank 1
3069 11:08:35.095659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 11:08:35.095741 ==
3071 11:08:35.098741 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 11:08:35.105288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3073 11:08:35.114662 [CA 0] Center 37 (7~68) winsize 62
3074 11:08:35.117976 [CA 1] Center 38 (8~68) winsize 61
3075 11:08:35.121296 [CA 2] Center 35 (5~65) winsize 61
3076 11:08:35.124376 [CA 3] Center 33 (3~64) winsize 62
3077 11:08:35.127855 [CA 4] Center 34 (4~64) winsize 61
3078 11:08:35.131627 [CA 5] Center 33 (3~64) winsize 62
3079 11:08:35.131748
3080 11:08:35.134594 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3081 11:08:35.134713
3082 11:08:35.137921 [CATrainingPosCal] consider 2 rank data
3083 11:08:35.141189 u2DelayCellTimex100 = 270/100 ps
3084 11:08:35.145126 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3085 11:08:35.151881 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3086 11:08:35.154666 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3087 11:08:35.158125 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3088 11:08:35.161247 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3089 11:08:35.164313 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3090 11:08:35.164394
3091 11:08:35.167942 CA PerBit enable=1, Macro0, CA PI delay=33
3092 11:08:35.168023
3093 11:08:35.171436 [CBTSetCACLKResult] CA Dly = 33
3094 11:08:35.171543 CS Dly: 6 (0~38)
3095 11:08:35.174129
3096 11:08:35.177652 ----->DramcWriteLeveling(PI) begin...
3097 11:08:35.177735 ==
3098 11:08:35.181049 Dram Type= 6, Freq= 0, CH_1, rank 0
3099 11:08:35.184240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 11:08:35.184321 ==
3101 11:08:35.187256 Write leveling (Byte 0): 26 => 26
3102 11:08:35.190976 Write leveling (Byte 1): 26 => 26
3103 11:08:35.194042 DramcWriteLeveling(PI) end<-----
3104 11:08:35.194123
3105 11:08:35.194187 ==
3106 11:08:35.197336 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 11:08:35.201058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 11:08:35.201140 ==
3109 11:08:35.204344 [Gating] SW mode calibration
3110 11:08:35.210386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3111 11:08:35.217047 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3112 11:08:35.220340 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
3113 11:08:35.224259 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 11:08:35.230289 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 11:08:35.233370 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 11:08:35.237246 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 11:08:35.243290 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 11:08:35.246809 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
3119 11:08:35.250686 0 15 28 | B1->B0 | 2b2b 2424 | 0 0 | (0 1) (0 1)
3120 11:08:35.257018 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3121 11:08:35.260207 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 11:08:35.263467 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 11:08:35.269996 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 11:08:35.273685 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 11:08:35.276553 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 11:08:35.283239 1 0 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
3127 11:08:35.286915 1 0 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
3128 11:08:35.290097 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 11:08:35.296547 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 11:08:35.299963 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 11:08:35.303225 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 11:08:35.309891 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 11:08:35.313256 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 11:08:35.316736 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3135 11:08:35.322938 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3136 11:08:35.326092 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3137 11:08:35.329530 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 11:08:35.336760 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 11:08:35.339888 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 11:08:35.343028 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 11:08:35.350030 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 11:08:35.352879 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 11:08:35.356368 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 11:08:35.359681 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 11:08:35.366370 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 11:08:35.369922 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 11:08:35.372926 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 11:08:35.379401 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 11:08:35.383157 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 11:08:35.386232 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3151 11:08:35.392764 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3152 11:08:35.395965 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 11:08:35.399224 Total UI for P1: 0, mck2ui 16
3154 11:08:35.402746 best dqsien dly found for B0: ( 1, 3, 26)
3155 11:08:35.405919 Total UI for P1: 0, mck2ui 16
3156 11:08:35.409160 best dqsien dly found for B1: ( 1, 3, 28)
3157 11:08:35.412432 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3158 11:08:35.415821 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3159 11:08:35.415904
3160 11:08:35.419222 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3161 11:08:35.422459 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3162 11:08:35.425778 [Gating] SW calibration Done
3163 11:08:35.425858 ==
3164 11:08:35.429593 Dram Type= 6, Freq= 0, CH_1, rank 0
3165 11:08:35.435955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 11:08:35.436051 ==
3167 11:08:35.436115 RX Vref Scan: 0
3168 11:08:35.436175
3169 11:08:35.439050 RX Vref 0 -> 0, step: 1
3170 11:08:35.439156
3171 11:08:35.442551 RX Delay -40 -> 252, step: 8
3172 11:08:35.445767 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3173 11:08:35.448730 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3174 11:08:35.452179 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3175 11:08:35.455485 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3176 11:08:35.462471 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3177 11:08:35.465665 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3178 11:08:35.468781 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3179 11:08:35.472258 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3180 11:08:35.475549 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3181 11:08:35.482315 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3182 11:08:35.485584 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3183 11:08:35.489250 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3184 11:08:35.492161 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3185 11:08:35.498803 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3186 11:08:35.502036 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3187 11:08:35.505269 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3188 11:08:35.505350 ==
3189 11:08:35.508912 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 11:08:35.512161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 11:08:35.512241 ==
3192 11:08:35.515307 DQS Delay:
3193 11:08:35.515423 DQS0 = 0, DQS1 = 0
3194 11:08:35.518881 DQM Delay:
3195 11:08:35.518961 DQM0 = 115, DQM1 = 112
3196 11:08:35.519025 DQ Delay:
3197 11:08:35.521617 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3198 11:08:35.528508 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3199 11:08:35.531937 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3200 11:08:35.535041 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3201 11:08:35.535121
3202 11:08:35.535186
3203 11:08:35.535245 ==
3204 11:08:35.538138 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 11:08:35.541702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 11:08:35.541783 ==
3207 11:08:35.541848
3208 11:08:35.541907
3209 11:08:35.545023 TX Vref Scan disable
3210 11:08:35.548151 == TX Byte 0 ==
3211 11:08:35.551283 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3212 11:08:35.554727 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3213 11:08:35.558244 == TX Byte 1 ==
3214 11:08:35.561446 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3215 11:08:35.564638 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3216 11:08:35.564718 ==
3217 11:08:35.567710 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 11:08:35.574600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 11:08:35.574686 ==
3220 11:08:35.584616 TX Vref=22, minBit 9, minWin=24, winSum=406
3221 11:08:35.587718 TX Vref=24, minBit 11, minWin=24, winSum=415
3222 11:08:35.591562 TX Vref=26, minBit 9, minWin=24, winSum=419
3223 11:08:35.594346 TX Vref=28, minBit 9, minWin=24, winSum=418
3224 11:08:35.597951 TX Vref=30, minBit 9, minWin=24, winSum=423
3225 11:08:35.604720 TX Vref=32, minBit 9, minWin=24, winSum=421
3226 11:08:35.607909 [TxChooseVref] Worse bit 9, Min win 24, Win sum 423, Final Vref 30
3227 11:08:35.608014
3228 11:08:35.611379 Final TX Range 1 Vref 30
3229 11:08:35.611452
3230 11:08:35.611514 ==
3231 11:08:35.614709 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 11:08:35.618199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 11:08:35.618327 ==
3234 11:08:35.621219
3235 11:08:35.621340
3236 11:08:35.621454 TX Vref Scan disable
3237 11:08:35.624309 == TX Byte 0 ==
3238 11:08:35.627705 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3239 11:08:35.631198 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3240 11:08:35.634268 == TX Byte 1 ==
3241 11:08:35.637920 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3242 11:08:35.644663 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3243 11:08:35.644787
3244 11:08:35.644900 [DATLAT]
3245 11:08:35.645010 Freq=1200, CH1 RK0
3246 11:08:35.645121
3247 11:08:35.647733 DATLAT Default: 0xd
3248 11:08:35.647856 0, 0xFFFF, sum = 0
3249 11:08:35.650748 1, 0xFFFF, sum = 0
3250 11:08:35.650871 2, 0xFFFF, sum = 0
3251 11:08:35.654082 3, 0xFFFF, sum = 0
3252 11:08:35.657437 4, 0xFFFF, sum = 0
3253 11:08:35.657560 5, 0xFFFF, sum = 0
3254 11:08:35.660671 6, 0xFFFF, sum = 0
3255 11:08:35.660793 7, 0xFFFF, sum = 0
3256 11:08:35.663934 8, 0xFFFF, sum = 0
3257 11:08:35.664055 9, 0xFFFF, sum = 0
3258 11:08:35.667669 10, 0xFFFF, sum = 0
3259 11:08:35.667791 11, 0xFFFF, sum = 0
3260 11:08:35.671109 12, 0x0, sum = 1
3261 11:08:35.671232 13, 0x0, sum = 2
3262 11:08:35.674565 14, 0x0, sum = 3
3263 11:08:35.674689 15, 0x0, sum = 4
3264 11:08:35.677553 best_step = 13
3265 11:08:35.677673
3266 11:08:35.677786 ==
3267 11:08:35.680722 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 11:08:35.684168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 11:08:35.684288 ==
3270 11:08:35.684402 RX Vref Scan: 1
3271 11:08:35.687285
3272 11:08:35.687390 Set Vref Range= 32 -> 127
3273 11:08:35.687471
3274 11:08:35.690647 RX Vref 32 -> 127, step: 1
3275 11:08:35.690728
3276 11:08:35.693764 RX Delay -13 -> 252, step: 4
3277 11:08:35.693859
3278 11:08:35.697221 Set Vref, RX VrefLevel [Byte0]: 32
3279 11:08:35.700591 [Byte1]: 32
3280 11:08:35.700671
3281 11:08:35.703645 Set Vref, RX VrefLevel [Byte0]: 33
3282 11:08:35.706913 [Byte1]: 33
3283 11:08:35.710593
3284 11:08:35.710716 Set Vref, RX VrefLevel [Byte0]: 34
3285 11:08:35.714486 [Byte1]: 34
3286 11:08:35.718719
3287 11:08:35.718800 Set Vref, RX VrefLevel [Byte0]: 35
3288 11:08:35.722149 [Byte1]: 35
3289 11:08:35.726558
3290 11:08:35.726639 Set Vref, RX VrefLevel [Byte0]: 36
3291 11:08:35.729891 [Byte1]: 36
3292 11:08:35.734407
3293 11:08:35.734517 Set Vref, RX VrefLevel [Byte0]: 37
3294 11:08:35.737839 [Byte1]: 37
3295 11:08:35.742447
3296 11:08:35.742550 Set Vref, RX VrefLevel [Byte0]: 38
3297 11:08:35.745719 [Byte1]: 38
3298 11:08:35.750561
3299 11:08:35.750642 Set Vref, RX VrefLevel [Byte0]: 39
3300 11:08:35.753448 [Byte1]: 39
3301 11:08:35.758111
3302 11:08:35.758231 Set Vref, RX VrefLevel [Byte0]: 40
3303 11:08:35.761156 [Byte1]: 40
3304 11:08:35.766097
3305 11:08:35.766177 Set Vref, RX VrefLevel [Byte0]: 41
3306 11:08:35.769211 [Byte1]: 41
3307 11:08:35.773913
3308 11:08:35.773993 Set Vref, RX VrefLevel [Byte0]: 42
3309 11:08:35.777138 [Byte1]: 42
3310 11:08:35.781939
3311 11:08:35.782042 Set Vref, RX VrefLevel [Byte0]: 43
3312 11:08:35.785241 [Byte1]: 43
3313 11:08:35.789317
3314 11:08:35.789406 Set Vref, RX VrefLevel [Byte0]: 44
3315 11:08:35.792677 [Byte1]: 44
3316 11:08:35.797535
3317 11:08:35.797622 Set Vref, RX VrefLevel [Byte0]: 45
3318 11:08:35.800716 [Byte1]: 45
3319 11:08:35.805988
3320 11:08:35.806070 Set Vref, RX VrefLevel [Byte0]: 46
3321 11:08:35.808422 [Byte1]: 46
3322 11:08:35.812962
3323 11:08:35.813043 Set Vref, RX VrefLevel [Byte0]: 47
3324 11:08:35.816422 [Byte1]: 47
3325 11:08:35.821485
3326 11:08:35.821619 Set Vref, RX VrefLevel [Byte0]: 48
3327 11:08:35.824326 [Byte1]: 48
3328 11:08:35.828819
3329 11:08:35.828994 Set Vref, RX VrefLevel [Byte0]: 49
3330 11:08:35.832137 [Byte1]: 49
3331 11:08:35.836949
3332 11:08:35.837074 Set Vref, RX VrefLevel [Byte0]: 50
3333 11:08:35.840220 [Byte1]: 50
3334 11:08:35.844720
3335 11:08:35.844853 Set Vref, RX VrefLevel [Byte0]: 51
3336 11:08:35.847771 [Byte1]: 51
3337 11:08:35.852508
3338 11:08:35.852629 Set Vref, RX VrefLevel [Byte0]: 52
3339 11:08:35.855727 [Byte1]: 52
3340 11:08:35.860835
3341 11:08:35.860913 Set Vref, RX VrefLevel [Byte0]: 53
3342 11:08:35.863847 [Byte1]: 53
3343 11:08:35.868411
3344 11:08:35.868520 Set Vref, RX VrefLevel [Byte0]: 54
3345 11:08:35.871692 [Byte1]: 54
3346 11:08:35.876208
3347 11:08:35.876290 Set Vref, RX VrefLevel [Byte0]: 55
3348 11:08:35.879558 [Byte1]: 55
3349 11:08:35.884340
3350 11:08:35.884421 Set Vref, RX VrefLevel [Byte0]: 56
3351 11:08:35.887245 [Byte1]: 56
3352 11:08:35.892040
3353 11:08:35.892124 Set Vref, RX VrefLevel [Byte0]: 57
3354 11:08:35.895279 [Byte1]: 57
3355 11:08:35.900051
3356 11:08:35.900131 Set Vref, RX VrefLevel [Byte0]: 58
3357 11:08:35.903314 [Byte1]: 58
3358 11:08:35.907765
3359 11:08:35.907846 Set Vref, RX VrefLevel [Byte0]: 59
3360 11:08:35.910895 [Byte1]: 59
3361 11:08:35.915376
3362 11:08:35.915472 Set Vref, RX VrefLevel [Byte0]: 60
3363 11:08:35.919348 [Byte1]: 60
3364 11:08:35.923367
3365 11:08:35.923504 Set Vref, RX VrefLevel [Byte0]: 61
3366 11:08:35.926542 [Byte1]: 61
3367 11:08:35.931326
3368 11:08:35.931471 Set Vref, RX VrefLevel [Byte0]: 62
3369 11:08:35.934516 [Byte1]: 62
3370 11:08:35.939105
3371 11:08:35.939227 Set Vref, RX VrefLevel [Byte0]: 63
3372 11:08:35.942349 [Byte1]: 63
3373 11:08:35.947165
3374 11:08:35.947287 Set Vref, RX VrefLevel [Byte0]: 64
3375 11:08:35.950642 [Byte1]: 64
3376 11:08:35.954844
3377 11:08:35.954959 Set Vref, RX VrefLevel [Byte0]: 65
3378 11:08:35.958644 [Byte1]: 65
3379 11:08:35.962816
3380 11:08:35.962917 Final RX Vref Byte 0 = 51 to rank0
3381 11:08:35.966124 Final RX Vref Byte 1 = 52 to rank0
3382 11:08:35.969762 Final RX Vref Byte 0 = 51 to rank1
3383 11:08:35.972857 Final RX Vref Byte 1 = 52 to rank1==
3384 11:08:35.976012 Dram Type= 6, Freq= 0, CH_1, rank 0
3385 11:08:35.982603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3386 11:08:35.982723 ==
3387 11:08:35.982824 DQS Delay:
3388 11:08:35.982916 DQS0 = 0, DQS1 = 0
3389 11:08:35.986143 DQM Delay:
3390 11:08:35.986226 DQM0 = 114, DQM1 = 113
3391 11:08:35.989413 DQ Delay:
3392 11:08:35.992843 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3393 11:08:35.996116 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3394 11:08:35.999178 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =108
3395 11:08:36.002560 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3396 11:08:36.002642
3397 11:08:36.002708
3398 11:08:36.012671 [DQSOSCAuto] RK0, (LSB)MR18= 0xf602, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 414 ps
3399 11:08:36.012756 CH1 RK0: MR19=304, MR18=F602
3400 11:08:36.019198 CH1_RK0: MR19=0x304, MR18=0xF602, DQSOSC=409, MR23=63, INC=39, DEC=26
3401 11:08:36.019281
3402 11:08:36.022530 ----->DramcWriteLeveling(PI) begin...
3403 11:08:36.022614 ==
3404 11:08:36.025642 Dram Type= 6, Freq= 0, CH_1, rank 1
3405 11:08:36.032253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3406 11:08:36.032336 ==
3407 11:08:36.035647 Write leveling (Byte 0): 23 => 23
3408 11:08:36.038804 Write leveling (Byte 1): 27 => 27
3409 11:08:36.038888 DramcWriteLeveling(PI) end<-----
3410 11:08:36.038954
3411 11:08:36.042375 ==
3412 11:08:36.045430 Dram Type= 6, Freq= 0, CH_1, rank 1
3413 11:08:36.048560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 11:08:36.048664 ==
3415 11:08:36.051893 [Gating] SW mode calibration
3416 11:08:36.058802 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3417 11:08:36.061860 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3418 11:08:36.068624 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3419 11:08:36.071819 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3420 11:08:36.075042 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3421 11:08:36.081877 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3422 11:08:36.085288 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3423 11:08:36.088289 0 15 20 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3424 11:08:36.094975 0 15 24 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
3425 11:08:36.098534 0 15 28 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
3426 11:08:36.101861 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3427 11:08:36.108302 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3428 11:08:36.111623 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3429 11:08:36.114991 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3430 11:08:36.121377 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3431 11:08:36.124699 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3432 11:08:36.128458 1 0 24 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
3433 11:08:36.135180 1 0 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
3434 11:08:36.138087 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3435 11:08:36.141172 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3436 11:08:36.147842 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3437 11:08:36.151105 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3438 11:08:36.154656 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3439 11:08:36.160911 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3440 11:08:36.164455 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3441 11:08:36.167450 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3442 11:08:36.174472 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3443 11:08:36.178097 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3444 11:08:36.181279 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 11:08:36.187232 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 11:08:36.190759 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 11:08:36.194023 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 11:08:36.200771 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 11:08:36.204173 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 11:08:36.207254 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 11:08:36.213692 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 11:08:36.216856 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 11:08:36.220191 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 11:08:36.226595 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 11:08:36.230340 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3456 11:08:36.233613 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3457 11:08:36.239918 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 11:08:36.243520 Total UI for P1: 0, mck2ui 16
3459 11:08:36.246732 best dqsien dly found for B0: ( 1, 3, 22)
3460 11:08:36.249765 Total UI for P1: 0, mck2ui 16
3461 11:08:36.253003 best dqsien dly found for B1: ( 1, 3, 26)
3462 11:08:36.256175 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3463 11:08:36.259753 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3464 11:08:36.259834
3465 11:08:36.262842 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3466 11:08:36.266045 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3467 11:08:36.269864 [Gating] SW calibration Done
3468 11:08:36.269945 ==
3469 11:08:36.272806 Dram Type= 6, Freq= 0, CH_1, rank 1
3470 11:08:36.276266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 11:08:36.276382 ==
3472 11:08:36.279515 RX Vref Scan: 0
3473 11:08:36.279613
3474 11:08:36.282813 RX Vref 0 -> 0, step: 1
3475 11:08:36.282910
3476 11:08:36.283004 RX Delay -40 -> 252, step: 8
3477 11:08:36.289310 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3478 11:08:36.292611 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3479 11:08:36.295923 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3480 11:08:36.299804 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3481 11:08:36.302774 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3482 11:08:36.308953 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3483 11:08:36.312703 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3484 11:08:36.315680 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3485 11:08:36.318974 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3486 11:08:36.322206 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3487 11:08:36.329184 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3488 11:08:36.332339 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3489 11:08:36.335614 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3490 11:08:36.338775 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3491 11:08:36.345237 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3492 11:08:36.348387 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3493 11:08:36.348468 ==
3494 11:08:36.351652 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 11:08:36.355193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 11:08:36.355314 ==
3497 11:08:36.358208 DQS Delay:
3498 11:08:36.358289 DQS0 = 0, DQS1 = 0
3499 11:08:36.358353 DQM Delay:
3500 11:08:36.361835 DQM0 = 115, DQM1 = 112
3501 11:08:36.361915 DQ Delay:
3502 11:08:36.365494 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3503 11:08:36.368226 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3504 11:08:36.374649 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3505 11:08:36.378287 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3506 11:08:36.378368
3507 11:08:36.378431
3508 11:08:36.378491 ==
3509 11:08:36.381260 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 11:08:36.384599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 11:08:36.384679 ==
3512 11:08:36.384743
3513 11:08:36.384802
3514 11:08:36.388323 TX Vref Scan disable
3515 11:08:36.391693 == TX Byte 0 ==
3516 11:08:36.394695 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3517 11:08:36.397646 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3518 11:08:36.400783 == TX Byte 1 ==
3519 11:08:36.404538 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3520 11:08:36.407515 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3521 11:08:36.407596 ==
3522 11:08:36.411306 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 11:08:36.414180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 11:08:36.417601 ==
3525 11:08:36.427956 TX Vref=22, minBit 2, minWin=25, winSum=418
3526 11:08:36.431268 TX Vref=24, minBit 7, minWin=25, winSum=421
3527 11:08:36.434585 TX Vref=26, minBit 9, minWin=25, winSum=426
3528 11:08:36.437874 TX Vref=28, minBit 9, minWin=25, winSum=431
3529 11:08:36.441070 TX Vref=30, minBit 8, minWin=26, winSum=433
3530 11:08:36.447294 TX Vref=32, minBit 9, minWin=25, winSum=431
3531 11:08:36.450871 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
3532 11:08:36.450981
3533 11:08:36.454422 Final TX Range 1 Vref 30
3534 11:08:36.454503
3535 11:08:36.454567 ==
3536 11:08:36.457424 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 11:08:36.463701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 11:08:36.463783 ==
3539 11:08:36.463847
3540 11:08:36.463907
3541 11:08:36.463965 TX Vref Scan disable
3542 11:08:36.467708 == TX Byte 0 ==
3543 11:08:36.470708 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3544 11:08:36.474320 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3545 11:08:36.477553 == TX Byte 1 ==
3546 11:08:36.481083 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3547 11:08:36.487191 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3548 11:08:36.487316
3549 11:08:36.487472 [DATLAT]
3550 11:08:36.487587 Freq=1200, CH1 RK1
3551 11:08:36.487708
3552 11:08:36.490610 DATLAT Default: 0xd
3553 11:08:36.493752 0, 0xFFFF, sum = 0
3554 11:08:36.493887 1, 0xFFFF, sum = 0
3555 11:08:36.497307 2, 0xFFFF, sum = 0
3556 11:08:36.497485 3, 0xFFFF, sum = 0
3557 11:08:36.500541 4, 0xFFFF, sum = 0
3558 11:08:36.500677 5, 0xFFFF, sum = 0
3559 11:08:36.503688 6, 0xFFFF, sum = 0
3560 11:08:36.503812 7, 0xFFFF, sum = 0
3561 11:08:36.507640 8, 0xFFFF, sum = 0
3562 11:08:36.507784 9, 0xFFFF, sum = 0
3563 11:08:36.510211 10, 0xFFFF, sum = 0
3564 11:08:36.510335 11, 0xFFFF, sum = 0
3565 11:08:36.513938 12, 0x0, sum = 1
3566 11:08:36.514022 13, 0x0, sum = 2
3567 11:08:36.517020 14, 0x0, sum = 3
3568 11:08:36.517103 15, 0x0, sum = 4
3569 11:08:36.520689 best_step = 13
3570 11:08:36.520795
3571 11:08:36.520888 ==
3572 11:08:36.523926 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 11:08:36.527129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 11:08:36.527236 ==
3575 11:08:36.530136 RX Vref Scan: 0
3576 11:08:36.530216
3577 11:08:36.530280 RX Vref 0 -> 0, step: 1
3578 11:08:36.530340
3579 11:08:36.533851 RX Delay -13 -> 252, step: 4
3580 11:08:36.540081 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3581 11:08:36.544070 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3582 11:08:36.546710 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3583 11:08:36.549781 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3584 11:08:36.553154 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3585 11:08:36.559520 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3586 11:08:36.563151 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3587 11:08:36.566265 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3588 11:08:36.569562 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3589 11:08:36.572883 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3590 11:08:36.579269 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3591 11:08:36.583033 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3592 11:08:36.586328 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3593 11:08:36.589276 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3594 11:08:36.596132 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3595 11:08:36.599226 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3596 11:08:36.599341 ==
3597 11:08:36.602855 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 11:08:36.605935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 11:08:36.606021 ==
3600 11:08:36.609166 DQS Delay:
3601 11:08:36.609251 DQS0 = 0, DQS1 = 0
3602 11:08:36.609337 DQM Delay:
3603 11:08:36.612261 DQM0 = 114, DQM1 = 112
3604 11:08:36.612347 DQ Delay:
3605 11:08:36.615988 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3606 11:08:36.619118 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =112
3607 11:08:36.625843 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3608 11:08:36.628877 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3609 11:08:36.628979
3610 11:08:36.629064
3611 11:08:36.635207 [DQSOSCAuto] RK1, (LSB)MR18= 0xf304, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
3612 11:08:36.638571 CH1 RK1: MR19=304, MR18=F304
3613 11:08:36.644963 CH1_RK1: MR19=0x304, MR18=0xF304, DQSOSC=408, MR23=63, INC=39, DEC=26
3614 11:08:36.648681 [RxdqsGatingPostProcess] freq 1200
3615 11:08:36.654882 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3616 11:08:36.658018 best DQS0 dly(2T, 0.5T) = (0, 11)
3617 11:08:36.658099 best DQS1 dly(2T, 0.5T) = (0, 11)
3618 11:08:36.661958 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3619 11:08:36.664573 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3620 11:08:36.667978 best DQS0 dly(2T, 0.5T) = (0, 11)
3621 11:08:36.671626 best DQS1 dly(2T, 0.5T) = (0, 11)
3622 11:08:36.674482 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3623 11:08:36.677862 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3624 11:08:36.681062 Pre-setting of DQS Precalculation
3625 11:08:36.687957 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3626 11:08:36.694136 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3627 11:08:36.700700 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3628 11:08:36.700782
3629 11:08:36.700866
3630 11:08:36.704226 [Calibration Summary] 2400 Mbps
3631 11:08:36.704402 CH 0, Rank 0
3632 11:08:36.707860 SW Impedance : PASS
3633 11:08:36.710923 DUTY Scan : NO K
3634 11:08:36.711021 ZQ Calibration : PASS
3635 11:08:36.714181 Jitter Meter : NO K
3636 11:08:36.717281 CBT Training : PASS
3637 11:08:36.717366 Write leveling : PASS
3638 11:08:36.720959 RX DQS gating : PASS
3639 11:08:36.723803 RX DQ/DQS(RDDQC) : PASS
3640 11:08:36.723905 TX DQ/DQS : PASS
3641 11:08:36.727327 RX DATLAT : PASS
3642 11:08:36.730584 RX DQ/DQS(Engine): PASS
3643 11:08:36.730764 TX OE : NO K
3644 11:08:36.734037 All Pass.
3645 11:08:36.734203
3646 11:08:36.734386 CH 0, Rank 1
3647 11:08:36.737091 SW Impedance : PASS
3648 11:08:36.737231 DUTY Scan : NO K
3649 11:08:36.740684 ZQ Calibration : PASS
3650 11:08:36.744260 Jitter Meter : NO K
3651 11:08:36.744391 CBT Training : PASS
3652 11:08:36.747308 Write leveling : PASS
3653 11:08:36.750312 RX DQS gating : PASS
3654 11:08:36.750430 RX DQ/DQS(RDDQC) : PASS
3655 11:08:36.753766 TX DQ/DQS : PASS
3656 11:08:36.753914 RX DATLAT : PASS
3657 11:08:36.757192 RX DQ/DQS(Engine): PASS
3658 11:08:36.760157 TX OE : NO K
3659 11:08:36.760280 All Pass.
3660 11:08:36.760400
3661 11:08:36.763992 CH 1, Rank 0
3662 11:08:36.764120 SW Impedance : PASS
3663 11:08:36.767142 DUTY Scan : NO K
3664 11:08:36.767275 ZQ Calibration : PASS
3665 11:08:36.770453 Jitter Meter : NO K
3666 11:08:36.773316 CBT Training : PASS
3667 11:08:36.773437 Write leveling : PASS
3668 11:08:36.776926 RX DQS gating : PASS
3669 11:08:36.780040 RX DQ/DQS(RDDQC) : PASS
3670 11:08:36.780175 TX DQ/DQS : PASS
3671 11:08:36.783721 RX DATLAT : PASS
3672 11:08:36.786883 RX DQ/DQS(Engine): PASS
3673 11:08:36.787014 TX OE : NO K
3674 11:08:36.790096 All Pass.
3675 11:08:36.790253
3676 11:08:36.790366 CH 1, Rank 1
3677 11:08:36.793353 SW Impedance : PASS
3678 11:08:36.793479 DUTY Scan : NO K
3679 11:08:36.797004 ZQ Calibration : PASS
3680 11:08:36.800027 Jitter Meter : NO K
3681 11:08:36.800161 CBT Training : PASS
3682 11:08:36.802997 Write leveling : PASS
3683 11:08:36.806945 RX DQS gating : PASS
3684 11:08:36.807075 RX DQ/DQS(RDDQC) : PASS
3685 11:08:36.810020 TX DQ/DQS : PASS
3686 11:08:36.813204 RX DATLAT : PASS
3687 11:08:36.813346 RX DQ/DQS(Engine): PASS
3688 11:08:36.816326 TX OE : NO K
3689 11:08:36.816460 All Pass.
3690 11:08:36.816576
3691 11:08:36.819809 DramC Write-DBI off
3692 11:08:36.823276 PER_BANK_REFRESH: Hybrid Mode
3693 11:08:36.823407 TX_TRACKING: ON
3694 11:08:36.832932 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3695 11:08:36.836261 [FAST_K] Save calibration result to emmc
3696 11:08:36.839111 dramc_set_vcore_voltage set vcore to 650000
3697 11:08:36.842576 Read voltage for 600, 5
3698 11:08:36.842699 Vio18 = 0
3699 11:08:36.842825 Vcore = 650000
3700 11:08:36.845979 Vdram = 0
3701 11:08:36.846101 Vddq = 0
3702 11:08:36.846226 Vmddr = 0
3703 11:08:36.852398 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3704 11:08:36.855993 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3705 11:08:36.858875 MEM_TYPE=3, freq_sel=19
3706 11:08:36.862133 sv_algorithm_assistance_LP4_1600
3707 11:08:36.865515 ============ PULL DRAM RESETB DOWN ============
3708 11:08:36.871794 ========== PULL DRAM RESETB DOWN end =========
3709 11:08:36.875394 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3710 11:08:36.878653 ===================================
3711 11:08:36.881827 LPDDR4 DRAM CONFIGURATION
3712 11:08:36.885003 ===================================
3713 11:08:36.885125 EX_ROW_EN[0] = 0x0
3714 11:08:36.888316 EX_ROW_EN[1] = 0x0
3715 11:08:36.888440 LP4Y_EN = 0x0
3716 11:08:36.891620 WORK_FSP = 0x0
3717 11:08:36.895270 WL = 0x2
3718 11:08:36.895414 RL = 0x2
3719 11:08:36.898489 BL = 0x2
3720 11:08:36.898622 RPST = 0x0
3721 11:08:36.901716 RD_PRE = 0x0
3722 11:08:36.901851 WR_PRE = 0x1
3723 11:08:36.904911 WR_PST = 0x0
3724 11:08:36.905043 DBI_WR = 0x0
3725 11:08:36.909210 DBI_RD = 0x0
3726 11:08:36.909345 OTF = 0x1
3727 11:08:36.912280 ===================================
3728 11:08:36.915086 ===================================
3729 11:08:36.917865 ANA top config
3730 11:08:36.921447 ===================================
3731 11:08:36.921570 DLL_ASYNC_EN = 0
3732 11:08:36.924476 ALL_SLAVE_EN = 1
3733 11:08:36.927740 NEW_RANK_MODE = 1
3734 11:08:36.931448 DLL_IDLE_MODE = 1
3735 11:08:36.934289 LP45_APHY_COMB_EN = 1
3736 11:08:36.934417 TX_ODT_DIS = 1
3737 11:08:36.937640 NEW_8X_MODE = 1
3738 11:08:36.941074 ===================================
3739 11:08:36.944161 ===================================
3740 11:08:36.947435 data_rate = 1200
3741 11:08:36.951702 CKR = 1
3742 11:08:36.954640 DQ_P2S_RATIO = 8
3743 11:08:36.957158 ===================================
3744 11:08:36.960922 CA_P2S_RATIO = 8
3745 11:08:36.961046 DQ_CA_OPEN = 0
3746 11:08:36.963860 DQ_SEMI_OPEN = 0
3747 11:08:36.967149 CA_SEMI_OPEN = 0
3748 11:08:36.970658 CA_FULL_RATE = 0
3749 11:08:36.974061 DQ_CKDIV4_EN = 1
3750 11:08:36.977114 CA_CKDIV4_EN = 1
3751 11:08:36.977235 CA_PREDIV_EN = 0
3752 11:08:36.980534 PH8_DLY = 0
3753 11:08:36.984233 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3754 11:08:36.987441 DQ_AAMCK_DIV = 4
3755 11:08:36.990429 CA_AAMCK_DIV = 4
3756 11:08:36.993524 CA_ADMCK_DIV = 4
3757 11:08:36.993660 DQ_TRACK_CA_EN = 0
3758 11:08:36.996887 CA_PICK = 600
3759 11:08:37.000253 CA_MCKIO = 600
3760 11:08:37.003371 MCKIO_SEMI = 0
3761 11:08:37.006682 PLL_FREQ = 2288
3762 11:08:37.010045 DQ_UI_PI_RATIO = 32
3763 11:08:37.013415 CA_UI_PI_RATIO = 0
3764 11:08:37.016654 ===================================
3765 11:08:37.020530 ===================================
3766 11:08:37.020654 memory_type:LPDDR4
3767 11:08:37.023223 GP_NUM : 10
3768 11:08:37.026594 SRAM_EN : 1
3769 11:08:37.026784 MD32_EN : 0
3770 11:08:37.029609 ===================================
3771 11:08:37.033211 [ANA_INIT] >>>>>>>>>>>>>>
3772 11:08:37.036270 <<<<<< [CONFIGURE PHASE]: ANA_TX
3773 11:08:37.039897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3774 11:08:37.042661 ===================================
3775 11:08:37.046182 data_rate = 1200,PCW = 0X5800
3776 11:08:37.049357 ===================================
3777 11:08:37.053219 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3778 11:08:37.056157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3779 11:08:37.062708 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3780 11:08:37.069247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3781 11:08:37.072803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3782 11:08:37.076048 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3783 11:08:37.076181 [ANA_INIT] flow start
3784 11:08:37.078980 [ANA_INIT] PLL >>>>>>>>
3785 11:08:37.082284 [ANA_INIT] PLL <<<<<<<<
3786 11:08:37.082405 [ANA_INIT] MIDPI >>>>>>>>
3787 11:08:37.086079 [ANA_INIT] MIDPI <<<<<<<<
3788 11:08:37.088767 [ANA_INIT] DLL >>>>>>>>
3789 11:08:37.088891 [ANA_INIT] flow end
3790 11:08:37.095332 ============ LP4 DIFF to SE enter ============
3791 11:08:37.098928 ============ LP4 DIFF to SE exit ============
3792 11:08:37.101925 [ANA_INIT] <<<<<<<<<<<<<
3793 11:08:37.105159 [Flow] Enable top DCM control >>>>>
3794 11:08:37.108920 [Flow] Enable top DCM control <<<<<
3795 11:08:37.109055 Enable DLL master slave shuffle
3796 11:08:37.115184 ==============================================================
3797 11:08:37.118982 Gating Mode config
3798 11:08:37.121807 ==============================================================
3799 11:08:37.125033 Config description:
3800 11:08:37.134767 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3801 11:08:37.141390 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3802 11:08:37.144593 SELPH_MODE 0: By rank 1: By Phase
3803 11:08:37.151645 ==============================================================
3804 11:08:37.154702 GAT_TRACK_EN = 1
3805 11:08:37.157815 RX_GATING_MODE = 2
3806 11:08:37.161155 RX_GATING_TRACK_MODE = 2
3807 11:08:37.164445 SELPH_MODE = 1
3808 11:08:37.167645 PICG_EARLY_EN = 1
3809 11:08:37.171019 VALID_LAT_VALUE = 1
3810 11:08:37.174397 ==============================================================
3811 11:08:37.177689 Enter into Gating configuration >>>>
3812 11:08:37.181142 Exit from Gating configuration <<<<
3813 11:08:37.184355 Enter into DVFS_PRE_config >>>>>
3814 11:08:37.197339 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3815 11:08:37.200922 Exit from DVFS_PRE_config <<<<<
3816 11:08:37.201008 Enter into PICG configuration >>>>
3817 11:08:37.204019 Exit from PICG configuration <<<<
3818 11:08:37.207329 [RX_INPUT] configuration >>>>>
3819 11:08:37.210412 [RX_INPUT] configuration <<<<<
3820 11:08:37.217364 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3821 11:08:37.220285 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3822 11:08:37.227017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3823 11:08:37.233447 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3824 11:08:37.240028 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3825 11:08:37.246417 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3826 11:08:37.250266 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3827 11:08:37.253227 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3828 11:08:37.259684 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3829 11:08:37.263848 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3830 11:08:37.266346 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3831 11:08:37.269657 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3832 11:08:37.273414 ===================================
3833 11:08:37.276565 LPDDR4 DRAM CONFIGURATION
3834 11:08:37.279901 ===================================
3835 11:08:37.282708 EX_ROW_EN[0] = 0x0
3836 11:08:37.282852 EX_ROW_EN[1] = 0x0
3837 11:08:37.286577 LP4Y_EN = 0x0
3838 11:08:37.286662 WORK_FSP = 0x0
3839 11:08:37.289552 WL = 0x2
3840 11:08:37.289637 RL = 0x2
3841 11:08:37.292717 BL = 0x2
3842 11:08:37.292802 RPST = 0x0
3843 11:08:37.295991 RD_PRE = 0x0
3844 11:08:37.299274 WR_PRE = 0x1
3845 11:08:37.299360 WR_PST = 0x0
3846 11:08:37.302598 DBI_WR = 0x0
3847 11:08:37.302682 DBI_RD = 0x0
3848 11:08:37.306589 OTF = 0x1
3849 11:08:37.309344 ===================================
3850 11:08:37.312357 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3851 11:08:37.316155 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3852 11:08:37.322245 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3853 11:08:37.325936 ===================================
3854 11:08:37.326036 LPDDR4 DRAM CONFIGURATION
3855 11:08:37.328691 ===================================
3856 11:08:37.332308 EX_ROW_EN[0] = 0x10
3857 11:08:37.332396 EX_ROW_EN[1] = 0x0
3858 11:08:37.335207 LP4Y_EN = 0x0
3859 11:08:37.339024 WORK_FSP = 0x0
3860 11:08:37.339109 WL = 0x2
3861 11:08:37.342344 RL = 0x2
3862 11:08:37.342429 BL = 0x2
3863 11:08:37.345390 RPST = 0x0
3864 11:08:37.345474 RD_PRE = 0x0
3865 11:08:37.348669 WR_PRE = 0x1
3866 11:08:37.348754 WR_PST = 0x0
3867 11:08:37.351898 DBI_WR = 0x0
3868 11:08:37.351983 DBI_RD = 0x0
3869 11:08:37.355496 OTF = 0x1
3870 11:08:37.358467 ===================================
3871 11:08:37.364822 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3872 11:08:37.368177 nWR fixed to 30
3873 11:08:37.368263 [ModeRegInit_LP4] CH0 RK0
3874 11:08:37.371946 [ModeRegInit_LP4] CH0 RK1
3875 11:08:37.375075 [ModeRegInit_LP4] CH1 RK0
3876 11:08:37.378189 [ModeRegInit_LP4] CH1 RK1
3877 11:08:37.378272 match AC timing 17
3878 11:08:37.384564 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3879 11:08:37.387902 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3880 11:08:37.391073 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3881 11:08:37.398117 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3882 11:08:37.401299 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3883 11:08:37.401425 ==
3884 11:08:37.404431 Dram Type= 6, Freq= 0, CH_0, rank 0
3885 11:08:37.407761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3886 11:08:37.407882 ==
3887 11:08:37.414141 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3888 11:08:37.421004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3889 11:08:37.424155 [CA 0] Center 36 (6~67) winsize 62
3890 11:08:37.427411 [CA 1] Center 36 (6~67) winsize 62
3891 11:08:37.430687 [CA 2] Center 34 (4~65) winsize 62
3892 11:08:37.434136 [CA 3] Center 34 (4~65) winsize 62
3893 11:08:37.437624 [CA 4] Center 33 (3~64) winsize 62
3894 11:08:37.440425 [CA 5] Center 33 (3~64) winsize 62
3895 11:08:37.440548
3896 11:08:37.443889 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3897 11:08:37.444013
3898 11:08:37.447187 [CATrainingPosCal] consider 1 rank data
3899 11:08:37.450545 u2DelayCellTimex100 = 270/100 ps
3900 11:08:37.453973 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3901 11:08:37.457215 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3902 11:08:37.460350 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3903 11:08:37.463665 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3904 11:08:37.469964 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3905 11:08:37.473484 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3906 11:08:37.473560
3907 11:08:37.476812 CA PerBit enable=1, Macro0, CA PI delay=33
3908 11:08:37.476903
3909 11:08:37.479818 [CBTSetCACLKResult] CA Dly = 33
3910 11:08:37.479905 CS Dly: 5 (0~36)
3911 11:08:37.480005 ==
3912 11:08:37.483515 Dram Type= 6, Freq= 0, CH_0, rank 1
3913 11:08:37.489796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3914 11:08:37.489888 ==
3915 11:08:37.493224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3916 11:08:37.499942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3917 11:08:37.503183 [CA 0] Center 36 (6~67) winsize 62
3918 11:08:37.506251 [CA 1] Center 36 (6~67) winsize 62
3919 11:08:37.509976 [CA 2] Center 34 (4~65) winsize 62
3920 11:08:37.512962 [CA 3] Center 34 (4~65) winsize 62
3921 11:08:37.516449 [CA 4] Center 34 (4~64) winsize 61
3922 11:08:37.519625 [CA 5] Center 33 (3~64) winsize 62
3923 11:08:37.519709
3924 11:08:37.522963 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3925 11:08:37.523074
3926 11:08:37.526011 [CATrainingPosCal] consider 2 rank data
3927 11:08:37.529342 u2DelayCellTimex100 = 270/100 ps
3928 11:08:37.532696 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3929 11:08:37.539182 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3930 11:08:37.542377 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3931 11:08:37.546019 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3932 11:08:37.549257 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3933 11:08:37.552250 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3934 11:08:37.552331
3935 11:08:37.555756 CA PerBit enable=1, Macro0, CA PI delay=33
3936 11:08:37.555837
3937 11:08:37.559221 [CBTSetCACLKResult] CA Dly = 33
3938 11:08:37.562708 CS Dly: 5 (0~36)
3939 11:08:37.562788
3940 11:08:37.565629 ----->DramcWriteLeveling(PI) begin...
3941 11:08:37.565711 ==
3942 11:08:37.569008 Dram Type= 6, Freq= 0, CH_0, rank 0
3943 11:08:37.571975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 11:08:37.572056 ==
3945 11:08:37.575629 Write leveling (Byte 0): 31 => 31
3946 11:08:37.579219 Write leveling (Byte 1): 26 => 26
3947 11:08:37.581725 DramcWriteLeveling(PI) end<-----
3948 11:08:37.581805
3949 11:08:37.581869 ==
3950 11:08:37.585135 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 11:08:37.588865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 11:08:37.588946 ==
3953 11:08:37.591597 [Gating] SW mode calibration
3954 11:08:37.598321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3955 11:08:37.605446 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3956 11:08:37.608659 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3957 11:08:37.615106 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3958 11:08:37.618272 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3959 11:08:37.621295 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
3960 11:08:37.627749 0 9 16 | B1->B0 | 2828 2424 | 1 1 | (0 0) (0 0)
3961 11:08:37.631253 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3962 11:08:37.634868 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3963 11:08:37.641122 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3964 11:08:37.644535 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3965 11:08:37.647617 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3966 11:08:37.654541 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 11:08:37.657820 0 10 12 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
3968 11:08:37.661098 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
3969 11:08:37.664480 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3970 11:08:37.670950 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3971 11:08:37.674014 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3972 11:08:37.677349 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3973 11:08:37.685096 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3974 11:08:37.687529 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 11:08:37.693721 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3976 11:08:37.697080 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3977 11:08:37.700229 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3978 11:08:37.707241 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 11:08:37.710166 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 11:08:37.713375 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 11:08:37.720229 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 11:08:37.723641 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 11:08:37.726680 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 11:08:37.733178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 11:08:37.736401 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 11:08:37.739818 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 11:08:37.746397 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 11:08:37.749982 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 11:08:37.752916 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 11:08:37.759632 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 11:08:37.763284 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3992 11:08:37.766298 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3993 11:08:37.769723 Total UI for P1: 0, mck2ui 16
3994 11:08:37.772585 best dqsien dly found for B0: ( 0, 13, 12)
3995 11:08:37.779215 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 11:08:37.779298 Total UI for P1: 0, mck2ui 16
3997 11:08:37.785720 best dqsien dly found for B1: ( 0, 13, 14)
3998 11:08:37.789411 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
3999 11:08:37.792406 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4000 11:08:37.792490
4001 11:08:37.795852 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4002 11:08:37.799096 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4003 11:08:37.802746 [Gating] SW calibration Done
4004 11:08:37.802829 ==
4005 11:08:37.805744 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 11:08:37.809004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 11:08:37.809089 ==
4008 11:08:37.812236 RX Vref Scan: 0
4009 11:08:37.812320
4010 11:08:37.812386 RX Vref 0 -> 0, step: 1
4011 11:08:37.812448
4012 11:08:37.815549 RX Delay -230 -> 252, step: 16
4013 11:08:37.822333 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4014 11:08:37.825508 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4015 11:08:37.828844 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4016 11:08:37.832085 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4017 11:08:37.838490 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4018 11:08:37.841979 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4019 11:08:37.845188 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4020 11:08:37.848517 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4021 11:08:37.851860 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4022 11:08:37.858486 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4023 11:08:37.861694 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4024 11:08:37.864989 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4025 11:08:37.868260 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4026 11:08:37.874678 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4027 11:08:37.878015 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4028 11:08:37.881350 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4029 11:08:37.881432 ==
4030 11:08:37.884604 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 11:08:37.891088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 11:08:37.891169 ==
4033 11:08:37.891234 DQS Delay:
4034 11:08:37.891294 DQS0 = 0, DQS1 = 0
4035 11:08:37.894660 DQM Delay:
4036 11:08:37.894741 DQM0 = 49, DQM1 = 39
4037 11:08:37.898242 DQ Delay:
4038 11:08:37.901304 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4039 11:08:37.904441 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4040 11:08:37.907678 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4041 11:08:37.911281 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4042 11:08:37.911386
4043 11:08:37.911469
4044 11:08:37.911529 ==
4045 11:08:37.914609 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 11:08:37.917749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 11:08:37.917830 ==
4048 11:08:37.917895
4049 11:08:37.917955
4050 11:08:37.921194 TX Vref Scan disable
4051 11:08:37.924104 == TX Byte 0 ==
4052 11:08:37.927266 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4053 11:08:37.930894 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4054 11:08:37.933899 == TX Byte 1 ==
4055 11:08:37.937137 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4056 11:08:37.940961 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4057 11:08:37.941043 ==
4058 11:08:37.944040 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 11:08:37.947257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 11:08:37.950321 ==
4061 11:08:37.950402
4062 11:08:37.950466
4063 11:08:37.950526 TX Vref Scan disable
4064 11:08:37.954557 == TX Byte 0 ==
4065 11:08:37.957463 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4066 11:08:37.964381 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4067 11:08:37.964506 == TX Byte 1 ==
4068 11:08:37.967496 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4069 11:08:37.974508 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4070 11:08:37.974661
4071 11:08:37.974772 [DATLAT]
4072 11:08:37.974885 Freq=600, CH0 RK0
4073 11:08:37.974993
4074 11:08:37.977895 DATLAT Default: 0x9
4075 11:08:37.977998 0, 0xFFFF, sum = 0
4076 11:08:37.981215 1, 0xFFFF, sum = 0
4077 11:08:37.984347 2, 0xFFFF, sum = 0
4078 11:08:37.984444 3, 0xFFFF, sum = 0
4079 11:08:37.987511 4, 0xFFFF, sum = 0
4080 11:08:37.987594 5, 0xFFFF, sum = 0
4081 11:08:37.990951 6, 0xFFFF, sum = 0
4082 11:08:37.991033 7, 0xFFFF, sum = 0
4083 11:08:37.994025 8, 0x0, sum = 1
4084 11:08:37.994108 9, 0x0, sum = 2
4085 11:08:37.994175 10, 0x0, sum = 3
4086 11:08:37.997315 11, 0x0, sum = 4
4087 11:08:37.997398 best_step = 9
4088 11:08:37.997462
4089 11:08:38.001282 ==
4090 11:08:38.001364 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 11:08:38.007477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 11:08:38.007559 ==
4093 11:08:38.007623 RX Vref Scan: 1
4094 11:08:38.007684
4095 11:08:38.010644 RX Vref 0 -> 0, step: 1
4096 11:08:38.010725
4097 11:08:38.014300 RX Delay -179 -> 252, step: 8
4098 11:08:38.014381
4099 11:08:38.017012 Set Vref, RX VrefLevel [Byte0]: 56
4100 11:08:38.020148 [Byte1]: 49
4101 11:08:38.020229
4102 11:08:38.023766 Final RX Vref Byte 0 = 56 to rank0
4103 11:08:38.026927 Final RX Vref Byte 1 = 49 to rank0
4104 11:08:38.030575 Final RX Vref Byte 0 = 56 to rank1
4105 11:08:38.033553 Final RX Vref Byte 1 = 49 to rank1==
4106 11:08:38.037051 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 11:08:38.040287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 11:08:38.043243 ==
4109 11:08:38.043326 DQS Delay:
4110 11:08:38.043418 DQS0 = 0, DQS1 = 0
4111 11:08:38.046460 DQM Delay:
4112 11:08:38.046582 DQM0 = 44, DQM1 = 36
4113 11:08:38.049807 DQ Delay:
4114 11:08:38.053618 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4115 11:08:38.053700 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4116 11:08:38.056543 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4117 11:08:38.063140 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4118 11:08:38.063223
4119 11:08:38.063290
4120 11:08:38.069460 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a41, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4121 11:08:38.073120 CH0 RK0: MR19=808, MR18=4A41
4122 11:08:38.079292 CH0_RK0: MR19=0x808, MR18=0x4A41, DQSOSC=395, MR23=63, INC=168, DEC=112
4123 11:08:38.079397
4124 11:08:38.082963 ----->DramcWriteLeveling(PI) begin...
4125 11:08:38.083046 ==
4126 11:08:38.086277 Dram Type= 6, Freq= 0, CH_0, rank 1
4127 11:08:38.089584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 11:08:38.089666 ==
4129 11:08:38.092909 Write leveling (Byte 0): 35 => 35
4130 11:08:38.096525 Write leveling (Byte 1): 28 => 28
4131 11:08:38.099199 DramcWriteLeveling(PI) end<-----
4132 11:08:38.099309
4133 11:08:38.099417 ==
4134 11:08:38.102915 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 11:08:38.106023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 11:08:38.109285 ==
4137 11:08:38.109365 [Gating] SW mode calibration
4138 11:08:38.116113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4139 11:08:38.122511 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4140 11:08:38.125581 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4141 11:08:38.132047 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4142 11:08:38.135654 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4143 11:08:38.138996 0 9 12 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
4144 11:08:38.145126 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4145 11:08:38.148420 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4146 11:08:38.152189 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4147 11:08:38.158785 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4148 11:08:38.161875 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4149 11:08:38.165675 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4150 11:08:38.171815 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4151 11:08:38.175145 0 10 12 | B1->B0 | 2525 3636 | 0 0 | (0 0) (1 1)
4152 11:08:38.178593 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4153 11:08:38.185129 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4154 11:08:38.188262 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4155 11:08:38.191606 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4156 11:08:38.198501 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4157 11:08:38.201670 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4158 11:08:38.204868 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4159 11:08:38.211286 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4160 11:08:38.214671 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4161 11:08:38.218242 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4162 11:08:38.224712 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 11:08:38.227942 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 11:08:38.231090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 11:08:38.237565 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 11:08:38.241022 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 11:08:38.244212 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 11:08:38.250684 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 11:08:38.254161 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 11:08:38.257456 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 11:08:38.264404 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 11:08:38.267171 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 11:08:38.270525 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 11:08:38.277204 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4175 11:08:38.280456 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 11:08:38.283482 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 11:08:38.287098 Total UI for P1: 0, mck2ui 16
4178 11:08:38.290501 best dqsien dly found for B0: ( 0, 13, 14)
4179 11:08:38.293866 Total UI for P1: 0, mck2ui 16
4180 11:08:38.296665 best dqsien dly found for B1: ( 0, 13, 14)
4181 11:08:38.300137 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4182 11:08:38.306641 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4183 11:08:38.306729
4184 11:08:38.310105 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4185 11:08:38.313452 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4186 11:08:38.316765 [Gating] SW calibration Done
4187 11:08:38.316847 ==
4188 11:08:38.319893 Dram Type= 6, Freq= 0, CH_0, rank 1
4189 11:08:38.323256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 11:08:38.323372 ==
4191 11:08:38.326723 RX Vref Scan: 0
4192 11:08:38.326818
4193 11:08:38.326881 RX Vref 0 -> 0, step: 1
4194 11:08:38.326946
4195 11:08:38.329816 RX Delay -230 -> 252, step: 16
4196 11:08:38.332906 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4197 11:08:38.339662 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4198 11:08:38.342754 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4199 11:08:38.346709 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4200 11:08:38.349654 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4201 11:08:38.356018 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4202 11:08:38.359469 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4203 11:08:38.362934 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4204 11:08:38.365785 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4205 11:08:38.369311 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4206 11:08:38.375722 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4207 11:08:38.378921 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4208 11:08:38.382701 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4209 11:08:38.388964 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4210 11:08:38.392251 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4211 11:08:38.395583 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4212 11:08:38.395663 ==
4213 11:08:38.399043 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 11:08:38.401870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 11:08:38.401952 ==
4216 11:08:38.405270 DQS Delay:
4217 11:08:38.405370 DQS0 = 0, DQS1 = 0
4218 11:08:38.408542 DQM Delay:
4219 11:08:38.408623 DQM0 = 45, DQM1 = 36
4220 11:08:38.408688 DQ Delay:
4221 11:08:38.412047 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4222 11:08:38.415292 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4223 11:08:38.418605 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4224 11:08:38.422176 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4225 11:08:38.422258
4226 11:08:38.425174
4227 11:08:38.425255 ==
4228 11:08:38.429081 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 11:08:38.431772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 11:08:38.431854 ==
4231 11:08:38.431917
4232 11:08:38.431977
4233 11:08:38.435206 TX Vref Scan disable
4234 11:08:38.435287 == TX Byte 0 ==
4235 11:08:38.441638 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4236 11:08:38.445013 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4237 11:08:38.445094 == TX Byte 1 ==
4238 11:08:38.451937 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4239 11:08:38.454850 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4240 11:08:38.455009 ==
4241 11:08:38.458089 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 11:08:38.461732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 11:08:38.461814 ==
4244 11:08:38.461878
4245 11:08:38.461939
4246 11:08:38.464982 TX Vref Scan disable
4247 11:08:38.468066 == TX Byte 0 ==
4248 11:08:38.471760 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4249 11:08:38.478318 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4250 11:08:38.478401 == TX Byte 1 ==
4251 11:08:38.481177 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4252 11:08:38.487983 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4253 11:08:38.488065
4254 11:08:38.488129 [DATLAT]
4255 11:08:38.488189 Freq=600, CH0 RK1
4256 11:08:38.488248
4257 11:08:38.491571 DATLAT Default: 0x9
4258 11:08:38.494519 0, 0xFFFF, sum = 0
4259 11:08:38.494602 1, 0xFFFF, sum = 0
4260 11:08:38.497699 2, 0xFFFF, sum = 0
4261 11:08:38.497789 3, 0xFFFF, sum = 0
4262 11:08:38.500938 4, 0xFFFF, sum = 0
4263 11:08:38.501040 5, 0xFFFF, sum = 0
4264 11:08:38.504304 6, 0xFFFF, sum = 0
4265 11:08:38.504387 7, 0xFFFF, sum = 0
4266 11:08:38.507828 8, 0x0, sum = 1
4267 11:08:38.507911 9, 0x0, sum = 2
4268 11:08:38.511283 10, 0x0, sum = 3
4269 11:08:38.511375 11, 0x0, sum = 4
4270 11:08:38.511445 best_step = 9
4271 11:08:38.511507
4272 11:08:38.514239 ==
4273 11:08:38.517625 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 11:08:38.520972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 11:08:38.521054 ==
4276 11:08:38.521119 RX Vref Scan: 0
4277 11:08:38.521180
4278 11:08:38.524089 RX Vref 0 -> 0, step: 1
4279 11:08:38.524170
4280 11:08:38.527325 RX Delay -179 -> 252, step: 8
4281 11:08:38.533864 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4282 11:08:38.537126 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4283 11:08:38.540736 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4284 11:08:38.543842 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4285 11:08:38.547300 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4286 11:08:38.553886 iDelay=205, Bit 5, Center 36 (-107 ~ 180) 288
4287 11:08:38.556895 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4288 11:08:38.560133 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4289 11:08:38.563600 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4290 11:08:38.570197 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4291 11:08:38.573491 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4292 11:08:38.576793 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4293 11:08:38.579972 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4294 11:08:38.586511 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4295 11:08:38.589947 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4296 11:08:38.593229 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4297 11:08:38.593330 ==
4298 11:08:38.596676 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 11:08:38.600368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 11:08:38.600497 ==
4301 11:08:38.603296 DQS Delay:
4302 11:08:38.603415 DQS0 = 0, DQS1 = 0
4303 11:08:38.606548 DQM Delay:
4304 11:08:38.606628 DQM0 = 44, DQM1 = 36
4305 11:08:38.606691 DQ Delay:
4306 11:08:38.609863 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4307 11:08:38.613281 DQ4 =48, DQ5 =36, DQ6 =56, DQ7 =52
4308 11:08:38.616805 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4309 11:08:38.619726 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4310 11:08:38.619835
4311 11:08:38.619932
4312 11:08:38.630098 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a36, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4313 11:08:38.633063 CH0 RK1: MR19=808, MR18=3A36
4314 11:08:38.639453 CH0_RK1: MR19=0x808, MR18=0x3A36, DQSOSC=398, MR23=63, INC=165, DEC=110
4315 11:08:38.642682 [RxdqsGatingPostProcess] freq 600
4316 11:08:38.646323 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4317 11:08:38.649136 Pre-setting of DQS Precalculation
4318 11:08:38.656220 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4319 11:08:38.656301 ==
4320 11:08:38.659191 Dram Type= 6, Freq= 0, CH_1, rank 0
4321 11:08:38.662727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 11:08:38.662808 ==
4323 11:08:38.668985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4324 11:08:38.672510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4325 11:08:38.677197 [CA 0] Center 35 (5~66) winsize 62
4326 11:08:38.680173 [CA 1] Center 35 (5~66) winsize 62
4327 11:08:38.683522 [CA 2] Center 34 (4~65) winsize 62
4328 11:08:38.687090 [CA 3] Center 34 (3~65) winsize 63
4329 11:08:38.689830 [CA 4] Center 34 (4~65) winsize 62
4330 11:08:38.693097 [CA 5] Center 34 (3~65) winsize 63
4331 11:08:38.693179
4332 11:08:38.696640 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4333 11:08:38.696720
4334 11:08:38.700086 [CATrainingPosCal] consider 1 rank data
4335 11:08:38.702847 u2DelayCellTimex100 = 270/100 ps
4336 11:08:38.706441 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4337 11:08:38.712853 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4338 11:08:38.715977 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4339 11:08:38.719235 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4340 11:08:38.722606 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4341 11:08:38.725773 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4342 11:08:38.725856
4343 11:08:38.729199 CA PerBit enable=1, Macro0, CA PI delay=34
4344 11:08:38.729318
4345 11:08:38.732485 [CBTSetCACLKResult] CA Dly = 34
4346 11:08:38.735869 CS Dly: 5 (0~36)
4347 11:08:38.736036 ==
4348 11:08:38.738963 Dram Type= 6, Freq= 0, CH_1, rank 1
4349 11:08:38.742562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 11:08:38.742645 ==
4351 11:08:38.748728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4352 11:08:38.755148 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4353 11:08:38.758573 [CA 0] Center 35 (5~66) winsize 62
4354 11:08:38.762024 [CA 1] Center 35 (5~66) winsize 62
4355 11:08:38.765034 [CA 2] Center 34 (4~65) winsize 62
4356 11:08:38.768744 [CA 3] Center 34 (3~65) winsize 63
4357 11:08:38.771701 [CA 4] Center 34 (4~65) winsize 62
4358 11:08:38.774796 [CA 5] Center 34 (3~65) winsize 63
4359 11:08:38.774876
4360 11:08:38.778726 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4361 11:08:38.778867
4362 11:08:38.781366 [CATrainingPosCal] consider 2 rank data
4363 11:08:38.785358 u2DelayCellTimex100 = 270/100 ps
4364 11:08:38.788428 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4365 11:08:38.791541 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4366 11:08:38.794738 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4367 11:08:38.798141 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4368 11:08:38.801430 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4369 11:08:38.804514 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4370 11:08:38.804599
4371 11:08:38.811322 CA PerBit enable=1, Macro0, CA PI delay=34
4372 11:08:38.811436
4373 11:08:38.811505 [CBTSetCACLKResult] CA Dly = 34
4374 11:08:38.814423 CS Dly: 4 (0~35)
4375 11:08:38.814532
4376 11:08:38.817944 ----->DramcWriteLeveling(PI) begin...
4377 11:08:38.818028 ==
4378 11:08:38.821296 Dram Type= 6, Freq= 0, CH_1, rank 0
4379 11:08:38.824640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 11:08:38.824744 ==
4381 11:08:38.827725 Write leveling (Byte 0): 30 => 30
4382 11:08:38.831087 Write leveling (Byte 1): 29 => 29
4383 11:08:38.835020 DramcWriteLeveling(PI) end<-----
4384 11:08:38.835103
4385 11:08:38.835168 ==
4386 11:08:38.837738 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 11:08:38.844365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 11:08:38.844449 ==
4389 11:08:38.844515 [Gating] SW mode calibration
4390 11:08:38.854203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4391 11:08:38.857537 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4392 11:08:38.860643 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4393 11:08:38.867660 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4394 11:08:38.870500 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4395 11:08:38.874134 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (1 1)
4396 11:08:38.880483 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4397 11:08:38.884399 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 11:08:38.887643 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 11:08:38.894121 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 11:08:38.896921 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 11:08:38.900643 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 11:08:38.906861 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4403 11:08:38.910072 0 10 12 | B1->B0 | 2f2f 3332 | 1 1 | (0 0) (0 0)
4404 11:08:38.916560 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 11:08:38.920253 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 11:08:38.922963 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 11:08:38.930031 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 11:08:38.932992 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 11:08:38.936386 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 11:08:38.942845 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 11:08:38.946041 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4412 11:08:38.949550 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 11:08:38.956212 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 11:08:38.959405 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 11:08:38.962753 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 11:08:38.969073 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 11:08:38.972476 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 11:08:38.975585 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 11:08:38.982484 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 11:08:38.986014 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 11:08:38.989097 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 11:08:38.995954 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 11:08:38.999211 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 11:08:39.002253 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 11:08:39.008551 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 11:08:39.011704 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 11:08:39.015453 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4428 11:08:39.021721 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 11:08:39.021901 Total UI for P1: 0, mck2ui 16
4430 11:08:39.028583 best dqsien dly found for B0: ( 0, 13, 14)
4431 11:08:39.028665 Total UI for P1: 0, mck2ui 16
4432 11:08:39.034974 best dqsien dly found for B1: ( 0, 13, 12)
4433 11:08:39.038328 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4434 11:08:39.041509 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4435 11:08:39.041591
4436 11:08:39.044692 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4437 11:08:39.048348 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4438 11:08:39.051567 [Gating] SW calibration Done
4439 11:08:39.051648 ==
4440 11:08:39.055183 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 11:08:39.058274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 11:08:39.058356 ==
4443 11:08:39.061315 RX Vref Scan: 0
4444 11:08:39.061434
4445 11:08:39.061531 RX Vref 0 -> 0, step: 1
4446 11:08:39.064696
4447 11:08:39.064778 RX Delay -230 -> 252, step: 16
4448 11:08:39.071071 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4449 11:08:39.074551 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4450 11:08:39.077757 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4451 11:08:39.080959 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4452 11:08:39.087526 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4453 11:08:39.091057 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4454 11:08:39.094701 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4455 11:08:39.097543 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4456 11:08:39.101451 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4457 11:08:39.107615 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4458 11:08:39.110464 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4459 11:08:39.114189 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4460 11:08:39.117207 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4461 11:08:39.123878 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4462 11:08:39.127072 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4463 11:08:39.130405 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4464 11:08:39.130526 ==
4465 11:08:39.133478 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 11:08:39.139954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 11:08:39.140078 ==
4468 11:08:39.140195 DQS Delay:
4469 11:08:39.143317 DQS0 = 0, DQS1 = 0
4470 11:08:39.143442 DQM Delay:
4471 11:08:39.143554 DQM0 = 41, DQM1 = 37
4472 11:08:39.146876 DQ Delay:
4473 11:08:39.150077 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4474 11:08:39.153177 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4475 11:08:39.156773 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4476 11:08:39.159685 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4477 11:08:39.159790
4478 11:08:39.159885
4479 11:08:39.159975 ==
4480 11:08:39.163124 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 11:08:39.166927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 11:08:39.167011 ==
4483 11:08:39.167077
4484 11:08:39.167138
4485 11:08:39.169976 TX Vref Scan disable
4486 11:08:39.173034 == TX Byte 0 ==
4487 11:08:39.176192 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4488 11:08:39.179298 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4489 11:08:39.182571 == TX Byte 1 ==
4490 11:08:39.186075 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4491 11:08:39.189220 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4492 11:08:39.189316 ==
4493 11:08:39.192612 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 11:08:39.199078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 11:08:39.199161 ==
4496 11:08:39.199225
4497 11:08:39.199285
4498 11:08:39.199343 TX Vref Scan disable
4499 11:08:39.203203 == TX Byte 0 ==
4500 11:08:39.206887 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4501 11:08:39.213442 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4502 11:08:39.213525 == TX Byte 1 ==
4503 11:08:39.216714 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4504 11:08:39.222880 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4505 11:08:39.222961
4506 11:08:39.223026 [DATLAT]
4507 11:08:39.223087 Freq=600, CH1 RK0
4508 11:08:39.223145
4509 11:08:39.226524 DATLAT Default: 0x9
4510 11:08:39.229963 0, 0xFFFF, sum = 0
4511 11:08:39.230090 1, 0xFFFF, sum = 0
4512 11:08:39.233155 2, 0xFFFF, sum = 0
4513 11:08:39.233237 3, 0xFFFF, sum = 0
4514 11:08:39.236558 4, 0xFFFF, sum = 0
4515 11:08:39.236655 5, 0xFFFF, sum = 0
4516 11:08:39.239773 6, 0xFFFF, sum = 0
4517 11:08:39.239871 7, 0xFFFF, sum = 0
4518 11:08:39.243013 8, 0x0, sum = 1
4519 11:08:39.243125 9, 0x0, sum = 2
4520 11:08:39.246419 10, 0x0, sum = 3
4521 11:08:39.246504 11, 0x0, sum = 4
4522 11:08:39.246571 best_step = 9
4523 11:08:39.246633
4524 11:08:39.249993 ==
4525 11:08:39.253137 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 11:08:39.256151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 11:08:39.256267 ==
4528 11:08:39.256359 RX Vref Scan: 1
4529 11:08:39.256447
4530 11:08:39.259701 RX Vref 0 -> 0, step: 1
4531 11:08:39.259784
4532 11:08:39.263156 RX Delay -179 -> 252, step: 8
4533 11:08:39.263265
4534 11:08:39.266423 Set Vref, RX VrefLevel [Byte0]: 51
4535 11:08:39.269473 [Byte1]: 52
4536 11:08:39.269580
4537 11:08:39.272633 Final RX Vref Byte 0 = 51 to rank0
4538 11:08:39.275672 Final RX Vref Byte 1 = 52 to rank0
4539 11:08:39.279649 Final RX Vref Byte 0 = 51 to rank1
4540 11:08:39.282738 Final RX Vref Byte 1 = 52 to rank1==
4541 11:08:39.285546 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 11:08:39.289240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 11:08:39.292514 ==
4544 11:08:39.292595 DQS Delay:
4545 11:08:39.292660 DQS0 = 0, DQS1 = 0
4546 11:08:39.295942 DQM Delay:
4547 11:08:39.296023 DQM0 = 41, DQM1 = 32
4548 11:08:39.298873 DQ Delay:
4549 11:08:39.302493 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4550 11:08:39.302575 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4551 11:08:39.305696 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =28
4552 11:08:39.311972 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4553 11:08:39.312070
4554 11:08:39.312212
4555 11:08:39.318610 [DQSOSCAuto] RK0, (LSB)MR18= 0x3049, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 400 ps
4556 11:08:39.321921 CH1 RK0: MR19=808, MR18=3049
4557 11:08:39.328569 CH1_RK0: MR19=0x808, MR18=0x3049, DQSOSC=396, MR23=63, INC=167, DEC=111
4558 11:08:39.328669
4559 11:08:39.331692 ----->DramcWriteLeveling(PI) begin...
4560 11:08:39.331792 ==
4561 11:08:39.335228 Dram Type= 6, Freq= 0, CH_1, rank 1
4562 11:08:39.338964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 11:08:39.339047 ==
4564 11:08:39.341924 Write leveling (Byte 0): 31 => 31
4565 11:08:39.344900 Write leveling (Byte 1): 31 => 31
4566 11:08:39.348118 DramcWriteLeveling(PI) end<-----
4567 11:08:39.348296
4568 11:08:39.348380 ==
4569 11:08:39.351533 Dram Type= 6, Freq= 0, CH_1, rank 1
4570 11:08:39.354977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 11:08:39.355058 ==
4572 11:08:39.358225 [Gating] SW mode calibration
4573 11:08:39.364950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4574 11:08:39.371410 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4575 11:08:39.374551 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4576 11:08:39.381376 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4577 11:08:39.384936 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4578 11:08:39.387645 0 9 12 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (1 0)
4579 11:08:39.394487 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4580 11:08:39.397678 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4581 11:08:39.401366 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4582 11:08:39.407470 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4583 11:08:39.410745 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4584 11:08:39.414084 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4585 11:08:39.420537 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4586 11:08:39.423902 0 10 12 | B1->B0 | 2d2d 3c3c | 1 0 | (0 0) (0 0)
4587 11:08:39.427298 0 10 16 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
4588 11:08:39.434326 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4589 11:08:39.437131 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4590 11:08:39.440435 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4591 11:08:39.447065 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4592 11:08:39.450364 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4593 11:08:39.453405 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4594 11:08:39.460413 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4595 11:08:39.463341 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4596 11:08:39.466526 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 11:08:39.473467 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 11:08:39.476615 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 11:08:39.480143 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 11:08:39.486218 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 11:08:39.489976 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 11:08:39.493012 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 11:08:39.499848 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 11:08:39.502711 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 11:08:39.506455 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 11:08:39.513034 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 11:08:39.516112 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 11:08:39.519474 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 11:08:39.525942 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 11:08:39.529910 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4611 11:08:39.532438 Total UI for P1: 0, mck2ui 16
4612 11:08:39.535877 best dqsien dly found for B0: ( 0, 13, 10)
4613 11:08:39.539507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 11:08:39.542914 Total UI for P1: 0, mck2ui 16
4615 11:08:39.545711 best dqsien dly found for B1: ( 0, 13, 12)
4616 11:08:39.549014 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4617 11:08:39.555706 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4618 11:08:39.555788
4619 11:08:39.558913 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4620 11:08:39.562371 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4621 11:08:39.565301 [Gating] SW calibration Done
4622 11:08:39.565383 ==
4623 11:08:39.568728 Dram Type= 6, Freq= 0, CH_1, rank 1
4624 11:08:39.572488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 11:08:39.572602 ==
4626 11:08:39.575305 RX Vref Scan: 0
4627 11:08:39.575409
4628 11:08:39.575476 RX Vref 0 -> 0, step: 1
4629 11:08:39.575537
4630 11:08:39.578951 RX Delay -230 -> 252, step: 16
4631 11:08:39.581847 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4632 11:08:39.588322 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4633 11:08:39.591565 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4634 11:08:39.595132 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4635 11:08:39.598473 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4636 11:08:39.604634 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4637 11:08:39.608428 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4638 11:08:39.611824 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4639 11:08:39.614651 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4640 11:08:39.621802 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4641 11:08:39.624510 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4642 11:08:39.627978 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4643 11:08:39.631283 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4644 11:08:39.637604 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4645 11:08:39.641128 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4646 11:08:39.643935 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4647 11:08:39.644018 ==
4648 11:08:39.647816 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 11:08:39.650756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 11:08:39.654079 ==
4651 11:08:39.654160 DQS Delay:
4652 11:08:39.654225 DQS0 = 0, DQS1 = 0
4653 11:08:39.657392 DQM Delay:
4654 11:08:39.657472 DQM0 = 41, DQM1 = 38
4655 11:08:39.660457 DQ Delay:
4656 11:08:39.664231 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4657 11:08:39.664312 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4658 11:08:39.666999 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4659 11:08:39.670411 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4660 11:08:39.674100
4661 11:08:39.674181
4662 11:08:39.674245 ==
4663 11:08:39.677375 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 11:08:39.680723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 11:08:39.680848 ==
4666 11:08:39.680946
4667 11:08:39.681022
4668 11:08:39.683904 TX Vref Scan disable
4669 11:08:39.684001 == TX Byte 0 ==
4670 11:08:39.690234 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4671 11:08:39.693367 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4672 11:08:39.693449 == TX Byte 1 ==
4673 11:08:39.699987 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4674 11:08:39.703638 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4675 11:08:39.703720 ==
4676 11:08:39.706802 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 11:08:39.709924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 11:08:39.710006 ==
4679 11:08:39.710071
4680 11:08:39.713751
4681 11:08:39.713864 TX Vref Scan disable
4682 11:08:39.716653 == TX Byte 0 ==
4683 11:08:39.720088 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4684 11:08:39.726846 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4685 11:08:39.726928 == TX Byte 1 ==
4686 11:08:39.729917 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4687 11:08:39.736552 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4688 11:08:39.736697
4689 11:08:39.736864 [DATLAT]
4690 11:08:39.736948 Freq=600, CH1 RK1
4691 11:08:39.737008
4692 11:08:39.740078 DATLAT Default: 0x9
4693 11:08:39.740158 0, 0xFFFF, sum = 0
4694 11:08:39.743224 1, 0xFFFF, sum = 0
4695 11:08:39.746588 2, 0xFFFF, sum = 0
4696 11:08:39.746670 3, 0xFFFF, sum = 0
4697 11:08:39.749911 4, 0xFFFF, sum = 0
4698 11:08:39.749993 5, 0xFFFF, sum = 0
4699 11:08:39.753349 6, 0xFFFF, sum = 0
4700 11:08:39.753508 7, 0xFFFF, sum = 0
4701 11:08:39.756605 8, 0x0, sum = 1
4702 11:08:39.756696 9, 0x0, sum = 2
4703 11:08:39.759695 10, 0x0, sum = 3
4704 11:08:39.759777 11, 0x0, sum = 4
4705 11:08:39.759842 best_step = 9
4706 11:08:39.759901
4707 11:08:39.762846 ==
4708 11:08:39.766510 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 11:08:39.769698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 11:08:39.769781 ==
4711 11:08:39.769846 RX Vref Scan: 0
4712 11:08:39.769906
4713 11:08:39.773145 RX Vref 0 -> 0, step: 1
4714 11:08:39.773230
4715 11:08:39.775804 RX Delay -179 -> 252, step: 8
4716 11:08:39.782657 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4717 11:08:39.785846 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4718 11:08:39.789200 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4719 11:08:39.792445 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4720 11:08:39.795986 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4721 11:08:39.802185 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4722 11:08:39.805479 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4723 11:08:39.808716 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4724 11:08:39.811999 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4725 11:08:39.818789 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4726 11:08:39.821911 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4727 11:08:39.825763 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4728 11:08:39.829003 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4729 11:08:39.835193 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4730 11:08:39.838761 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4731 11:08:39.841922 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4732 11:08:39.842059 ==
4733 11:08:39.845029 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 11:08:39.851739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 11:08:39.851822 ==
4736 11:08:39.851887 DQS Delay:
4737 11:08:39.851947 DQS0 = 0, DQS1 = 0
4738 11:08:39.855018 DQM Delay:
4739 11:08:39.855113 DQM0 = 37, DQM1 = 36
4740 11:08:39.858412 DQ Delay:
4741 11:08:39.861504 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4742 11:08:39.864763 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4743 11:08:39.868241 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4744 11:08:39.871726 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4745 11:08:39.871807
4746 11:08:39.871872
4747 11:08:39.878137 [DQSOSCAuto] RK1, (LSB)MR18= 0x3157, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4748 11:08:39.881316 CH1 RK1: MR19=808, MR18=3157
4749 11:08:39.887534 CH1_RK1: MR19=0x808, MR18=0x3157, DQSOSC=393, MR23=63, INC=169, DEC=113
4750 11:08:39.890952 [RxdqsGatingPostProcess] freq 600
4751 11:08:39.894423 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4752 11:08:39.897449 Pre-setting of DQS Precalculation
4753 11:08:39.904251 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4754 11:08:39.910881 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4755 11:08:39.917243 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4756 11:08:39.917327
4757 11:08:39.917394
4758 11:08:39.920602 [Calibration Summary] 1200 Mbps
4759 11:08:39.923892 CH 0, Rank 0
4760 11:08:39.923975 SW Impedance : PASS
4761 11:08:39.927314 DUTY Scan : NO K
4762 11:08:39.930602 ZQ Calibration : PASS
4763 11:08:39.930685 Jitter Meter : NO K
4764 11:08:39.933669 CBT Training : PASS
4765 11:08:39.933752 Write leveling : PASS
4766 11:08:39.937135 RX DQS gating : PASS
4767 11:08:39.940254 RX DQ/DQS(RDDQC) : PASS
4768 11:08:39.940337 TX DQ/DQS : PASS
4769 11:08:39.944095 RX DATLAT : PASS
4770 11:08:39.946909 RX DQ/DQS(Engine): PASS
4771 11:08:39.946992 TX OE : NO K
4772 11:08:39.950361 All Pass.
4773 11:08:39.950444
4774 11:08:39.950509 CH 0, Rank 1
4775 11:08:39.953529 SW Impedance : PASS
4776 11:08:39.953612 DUTY Scan : NO K
4777 11:08:39.957278 ZQ Calibration : PASS
4778 11:08:39.960128 Jitter Meter : NO K
4779 11:08:39.960212 CBT Training : PASS
4780 11:08:39.963155 Write leveling : PASS
4781 11:08:39.966403 RX DQS gating : PASS
4782 11:08:39.966485 RX DQ/DQS(RDDQC) : PASS
4783 11:08:39.969945 TX DQ/DQS : PASS
4784 11:08:39.973283 RX DATLAT : PASS
4785 11:08:39.973366 RX DQ/DQS(Engine): PASS
4786 11:08:39.976597 TX OE : NO K
4787 11:08:39.976680 All Pass.
4788 11:08:39.976746
4789 11:08:39.979568 CH 1, Rank 0
4790 11:08:39.979651 SW Impedance : PASS
4791 11:08:39.983221 DUTY Scan : NO K
4792 11:08:39.986163 ZQ Calibration : PASS
4793 11:08:39.986246 Jitter Meter : NO K
4794 11:08:39.989471 CBT Training : PASS
4795 11:08:39.993196 Write leveling : PASS
4796 11:08:39.993295 RX DQS gating : PASS
4797 11:08:39.996173 RX DQ/DQS(RDDQC) : PASS
4798 11:08:39.999078 TX DQ/DQS : PASS
4799 11:08:39.999174 RX DATLAT : PASS
4800 11:08:40.002920 RX DQ/DQS(Engine): PASS
4801 11:08:40.006020 TX OE : NO K
4802 11:08:40.006102 All Pass.
4803 11:08:40.006167
4804 11:08:40.006227 CH 1, Rank 1
4805 11:08:40.009309 SW Impedance : PASS
4806 11:08:40.012244 DUTY Scan : NO K
4807 11:08:40.012325 ZQ Calibration : PASS
4808 11:08:40.015593 Jitter Meter : NO K
4809 11:08:40.019721 CBT Training : PASS
4810 11:08:40.019802 Write leveling : PASS
4811 11:08:40.022600 RX DQS gating : PASS
4812 11:08:40.025618 RX DQ/DQS(RDDQC) : PASS
4813 11:08:40.025720 TX DQ/DQS : PASS
4814 11:08:40.029154 RX DATLAT : PASS
4815 11:08:40.032304 RX DQ/DQS(Engine): PASS
4816 11:08:40.032377 TX OE : NO K
4817 11:08:40.032440 All Pass.
4818 11:08:40.032507
4819 11:08:40.035629 DramC Write-DBI off
4820 11:08:40.039049 PER_BANK_REFRESH: Hybrid Mode
4821 11:08:40.039146 TX_TRACKING: ON
4822 11:08:40.048918 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4823 11:08:40.052489 [FAST_K] Save calibration result to emmc
4824 11:08:40.055274 dramc_set_vcore_voltage set vcore to 662500
4825 11:08:40.058550 Read voltage for 933, 3
4826 11:08:40.058675 Vio18 = 0
4827 11:08:40.062176 Vcore = 662500
4828 11:08:40.062291 Vdram = 0
4829 11:08:40.062381 Vddq = 0
4830 11:08:40.062493 Vmddr = 0
4831 11:08:40.068421 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4832 11:08:40.074911 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4833 11:08:40.075087 MEM_TYPE=3, freq_sel=17
4834 11:08:40.078039 sv_algorithm_assistance_LP4_1600
4835 11:08:40.081378 ============ PULL DRAM RESETB DOWN ============
4836 11:08:40.088225 ========== PULL DRAM RESETB DOWN end =========
4837 11:08:40.091683 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4838 11:08:40.094973 ===================================
4839 11:08:40.097922 LPDDR4 DRAM CONFIGURATION
4840 11:08:40.101150 ===================================
4841 11:08:40.101223 EX_ROW_EN[0] = 0x0
4842 11:08:40.104478 EX_ROW_EN[1] = 0x0
4843 11:08:40.108225 LP4Y_EN = 0x0
4844 11:08:40.108301 WORK_FSP = 0x0
4845 11:08:40.111264 WL = 0x3
4846 11:08:40.111369 RL = 0x3
4847 11:08:40.114565 BL = 0x2
4848 11:08:40.114664 RPST = 0x0
4849 11:08:40.117782 RD_PRE = 0x0
4850 11:08:40.117882 WR_PRE = 0x1
4851 11:08:40.120796 WR_PST = 0x0
4852 11:08:40.120870 DBI_WR = 0x0
4853 11:08:40.124402 DBI_RD = 0x0
4854 11:08:40.124474 OTF = 0x1
4855 11:08:40.127377 ===================================
4856 11:08:40.131015 ===================================
4857 11:08:40.134133 ANA top config
4858 11:08:40.137726 ===================================
4859 11:08:40.141085 DLL_ASYNC_EN = 0
4860 11:08:40.141167 ALL_SLAVE_EN = 1
4861 11:08:40.144057 NEW_RANK_MODE = 1
4862 11:08:40.147237 DLL_IDLE_MODE = 1
4863 11:08:40.150564 LP45_APHY_COMB_EN = 1
4864 11:08:40.150646 TX_ODT_DIS = 1
4865 11:08:40.153962 NEW_8X_MODE = 1
4866 11:08:40.156857 ===================================
4867 11:08:40.160751 ===================================
4868 11:08:40.163663 data_rate = 1866
4869 11:08:40.167247 CKR = 1
4870 11:08:40.170141 DQ_P2S_RATIO = 8
4871 11:08:40.173780 ===================================
4872 11:08:40.177167 CA_P2S_RATIO = 8
4873 11:08:40.180549 DQ_CA_OPEN = 0
4874 11:08:40.180672 DQ_SEMI_OPEN = 0
4875 11:08:40.183576 CA_SEMI_OPEN = 0
4876 11:08:40.186517 CA_FULL_RATE = 0
4877 11:08:40.189820 DQ_CKDIV4_EN = 1
4878 11:08:40.193555 CA_CKDIV4_EN = 1
4879 11:08:40.196845 CA_PREDIV_EN = 0
4880 11:08:40.196918 PH8_DLY = 0
4881 11:08:40.200090 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4882 11:08:40.203292 DQ_AAMCK_DIV = 4
4883 11:08:40.206974 CA_AAMCK_DIV = 4
4884 11:08:40.209586 CA_ADMCK_DIV = 4
4885 11:08:40.213425 DQ_TRACK_CA_EN = 0
4886 11:08:40.213510 CA_PICK = 933
4887 11:08:40.216655 CA_MCKIO = 933
4888 11:08:40.219589 MCKIO_SEMI = 0
4889 11:08:40.222818 PLL_FREQ = 3732
4890 11:08:40.226091 DQ_UI_PI_RATIO = 32
4891 11:08:40.229685 CA_UI_PI_RATIO = 0
4892 11:08:40.233147 ===================================
4893 11:08:40.236191 ===================================
4894 11:08:40.239820 memory_type:LPDDR4
4895 11:08:40.239900 GP_NUM : 10
4896 11:08:40.242983 SRAM_EN : 1
4897 11:08:40.243063 MD32_EN : 0
4898 11:08:40.246392 ===================================
4899 11:08:40.249729 [ANA_INIT] >>>>>>>>>>>>>>
4900 11:08:40.252706 <<<<<< [CONFIGURE PHASE]: ANA_TX
4901 11:08:40.255964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4902 11:08:40.259645 ===================================
4903 11:08:40.262334 data_rate = 1866,PCW = 0X8f00
4904 11:08:40.265709 ===================================
4905 11:08:40.269372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4906 11:08:40.275527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4907 11:08:40.278928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4908 11:08:40.285552 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4909 11:08:40.289260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4910 11:08:40.291950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4911 11:08:40.292052 [ANA_INIT] flow start
4912 11:08:40.295468 [ANA_INIT] PLL >>>>>>>>
4913 11:08:40.298467 [ANA_INIT] PLL <<<<<<<<
4914 11:08:40.298565 [ANA_INIT] MIDPI >>>>>>>>
4915 11:08:40.302334 [ANA_INIT] MIDPI <<<<<<<<
4916 11:08:40.305788 [ANA_INIT] DLL >>>>>>>>
4917 11:08:40.305887 [ANA_INIT] flow end
4918 11:08:40.311744 ============ LP4 DIFF to SE enter ============
4919 11:08:40.315264 ============ LP4 DIFF to SE exit ============
4920 11:08:40.318815 [ANA_INIT] <<<<<<<<<<<<<
4921 11:08:40.321884 [Flow] Enable top DCM control >>>>>
4922 11:08:40.325020 [Flow] Enable top DCM control <<<<<
4923 11:08:40.328088 Enable DLL master slave shuffle
4924 11:08:40.332077 ==============================================================
4925 11:08:40.335071 Gating Mode config
4926 11:08:40.338185 ==============================================================
4927 11:08:40.341542 Config description:
4928 11:08:40.351475 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4929 11:08:40.358627 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4930 11:08:40.361658 SELPH_MODE 0: By rank 1: By Phase
4931 11:08:40.368023 ==============================================================
4932 11:08:40.371661 GAT_TRACK_EN = 1
4933 11:08:40.374246 RX_GATING_MODE = 2
4934 11:08:40.377669 RX_GATING_TRACK_MODE = 2
4935 11:08:40.381141 SELPH_MODE = 1
4936 11:08:40.384051 PICG_EARLY_EN = 1
4937 11:08:40.387676 VALID_LAT_VALUE = 1
4938 11:08:40.390554 ==============================================================
4939 11:08:40.394380 Enter into Gating configuration >>>>
4940 11:08:40.397436 Exit from Gating configuration <<<<
4941 11:08:40.400489 Enter into DVFS_PRE_config >>>>>
4942 11:08:40.413651 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4943 11:08:40.417164 Exit from DVFS_PRE_config <<<<<
4944 11:08:40.420303 Enter into PICG configuration >>>>
4945 11:08:40.420386 Exit from PICG configuration <<<<
4946 11:08:40.423501 [RX_INPUT] configuration >>>>>
4947 11:08:40.426973 [RX_INPUT] configuration <<<<<
4948 11:08:40.433674 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4949 11:08:40.436861 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4950 11:08:40.443707 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4951 11:08:40.449788 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4952 11:08:40.456952 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4953 11:08:40.463387 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4954 11:08:40.467155 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4955 11:08:40.469800 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4956 11:08:40.476677 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4957 11:08:40.479550 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4958 11:08:40.482969 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4959 11:08:40.486264 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4960 11:08:40.489789 ===================================
4961 11:08:40.492957 LPDDR4 DRAM CONFIGURATION
4962 11:08:40.496033 ===================================
4963 11:08:40.499458 EX_ROW_EN[0] = 0x0
4964 11:08:40.499568 EX_ROW_EN[1] = 0x0
4965 11:08:40.502722 LP4Y_EN = 0x0
4966 11:08:40.502804 WORK_FSP = 0x0
4967 11:08:40.505904 WL = 0x3
4968 11:08:40.505987 RL = 0x3
4969 11:08:40.509382 BL = 0x2
4970 11:08:40.509464 RPST = 0x0
4971 11:08:40.512766 RD_PRE = 0x0
4972 11:08:40.515870 WR_PRE = 0x1
4973 11:08:40.515953 WR_PST = 0x0
4974 11:08:40.519687 DBI_WR = 0x0
4975 11:08:40.519800 DBI_RD = 0x0
4976 11:08:40.522330 OTF = 0x1
4977 11:08:40.525955 ===================================
4978 11:08:40.529079 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4979 11:08:40.532585 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4980 11:08:40.535635 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4981 11:08:40.538702 ===================================
4982 11:08:40.542212 LPDDR4 DRAM CONFIGURATION
4983 11:08:40.545733 ===================================
4984 11:08:40.549066 EX_ROW_EN[0] = 0x10
4985 11:08:40.549176 EX_ROW_EN[1] = 0x0
4986 11:08:40.552479 LP4Y_EN = 0x0
4987 11:08:40.552583 WORK_FSP = 0x0
4988 11:08:40.556088 WL = 0x3
4989 11:08:40.558855 RL = 0x3
4990 11:08:40.558937 BL = 0x2
4991 11:08:40.561974 RPST = 0x0
4992 11:08:40.562056 RD_PRE = 0x0
4993 11:08:40.565310 WR_PRE = 0x1
4994 11:08:40.565391 WR_PST = 0x0
4995 11:08:40.568819 DBI_WR = 0x0
4996 11:08:40.568929 DBI_RD = 0x0
4997 11:08:40.571911 OTF = 0x1
4998 11:08:40.575420 ===================================
4999 11:08:40.581830 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5000 11:08:40.584873 nWR fixed to 30
5001 11:08:40.584981 [ModeRegInit_LP4] CH0 RK0
5002 11:08:40.588418 [ModeRegInit_LP4] CH0 RK1
5003 11:08:40.591616 [ModeRegInit_LP4] CH1 RK0
5004 11:08:40.594907 [ModeRegInit_LP4] CH1 RK1
5005 11:08:40.594988 match AC timing 9
5006 11:08:40.598414 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5007 11:08:40.605128 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5008 11:08:40.608161 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5009 11:08:40.615194 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5010 11:08:40.618030 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5011 11:08:40.618128 ==
5012 11:08:40.621313 Dram Type= 6, Freq= 0, CH_0, rank 0
5013 11:08:40.624513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5014 11:08:40.624593 ==
5015 11:08:40.630848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5016 11:08:40.637642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5017 11:08:40.640711 [CA 0] Center 38 (7~69) winsize 63
5018 11:08:40.644265 [CA 1] Center 37 (7~68) winsize 62
5019 11:08:40.647503 [CA 2] Center 34 (4~65) winsize 62
5020 11:08:40.650812 [CA 3] Center 34 (4~65) winsize 62
5021 11:08:40.654127 [CA 4] Center 33 (3~63) winsize 61
5022 11:08:40.657483 [CA 5] Center 33 (3~63) winsize 61
5023 11:08:40.657563
5024 11:08:40.660378 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5025 11:08:40.660485
5026 11:08:40.663702 [CATrainingPosCal] consider 1 rank data
5027 11:08:40.667174 u2DelayCellTimex100 = 270/100 ps
5028 11:08:40.670106 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5029 11:08:40.674093 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5030 11:08:40.677661 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5031 11:08:40.680260 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5032 11:08:40.683485 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5033 11:08:40.690264 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5034 11:08:40.690373
5035 11:08:40.693355 CA PerBit enable=1, Macro0, CA PI delay=33
5036 11:08:40.693437
5037 11:08:40.696675 [CBTSetCACLKResult] CA Dly = 33
5038 11:08:40.696756 CS Dly: 6 (0~37)
5039 11:08:40.696822 ==
5040 11:08:40.700274 Dram Type= 6, Freq= 0, CH_0, rank 1
5041 11:08:40.703141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5042 11:08:40.706898 ==
5043 11:08:40.710102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5044 11:08:40.716841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5045 11:08:40.719627 [CA 0] Center 38 (8~69) winsize 62
5046 11:08:40.723476 [CA 1] Center 38 (7~69) winsize 63
5047 11:08:40.726388 [CA 2] Center 35 (5~65) winsize 61
5048 11:08:40.729635 [CA 3] Center 34 (4~65) winsize 62
5049 11:08:40.733178 [CA 4] Center 33 (3~64) winsize 62
5050 11:08:40.736321 [CA 5] Center 33 (3~63) winsize 61
5051 11:08:40.736403
5052 11:08:40.739456 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5053 11:08:40.739539
5054 11:08:40.742637 [CATrainingPosCal] consider 2 rank data
5055 11:08:40.746465 u2DelayCellTimex100 = 270/100 ps
5056 11:08:40.749384 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5057 11:08:40.752779 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5058 11:08:40.759236 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5059 11:08:40.762598 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5060 11:08:40.766293 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5061 11:08:40.769539 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5062 11:08:40.769622
5063 11:08:40.772621 CA PerBit enable=1, Macro0, CA PI delay=33
5064 11:08:40.772703
5065 11:08:40.776013 [CBTSetCACLKResult] CA Dly = 33
5066 11:08:40.776095 CS Dly: 7 (0~39)
5067 11:08:40.776161
5068 11:08:40.782327 ----->DramcWriteLeveling(PI) begin...
5069 11:08:40.782409 ==
5070 11:08:40.785482 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 11:08:40.788798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5072 11:08:40.788879 ==
5073 11:08:40.792197 Write leveling (Byte 0): 32 => 32
5074 11:08:40.795282 Write leveling (Byte 1): 26 => 26
5075 11:08:40.799049 DramcWriteLeveling(PI) end<-----
5076 11:08:40.799129
5077 11:08:40.799193 ==
5078 11:08:40.802341 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 11:08:40.805608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 11:08:40.805690 ==
5081 11:08:40.808516 [Gating] SW mode calibration
5082 11:08:40.815088 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5083 11:08:40.821817 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5084 11:08:40.824976 0 14 0 | B1->B0 | 2525 3333 | 1 1 | (0 0) (1 1)
5085 11:08:40.828599 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5086 11:08:40.834713 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5087 11:08:40.838275 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 11:08:40.841804 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5089 11:08:40.847918 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5090 11:08:40.851521 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5091 11:08:40.854728 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
5092 11:08:40.861618 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5093 11:08:40.864636 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5094 11:08:40.867867 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 11:08:40.874609 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 11:08:40.877853 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 11:08:40.880878 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 11:08:40.887268 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 11:08:40.890984 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5100 11:08:40.894101 1 0 0 | B1->B0 | 2f2f 4444 | 0 0 | (0 0) (0 0)
5101 11:08:40.900584 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 11:08:40.904254 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 11:08:40.907149 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 11:08:40.914153 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 11:08:40.917342 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 11:08:40.920467 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 11:08:40.927429 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5108 11:08:40.930617 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5109 11:08:40.933693 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 11:08:40.940593 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 11:08:40.943695 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 11:08:40.946970 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 11:08:40.953235 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 11:08:40.956734 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 11:08:40.960093 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 11:08:40.966562 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 11:08:40.969688 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 11:08:40.973008 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 11:08:40.979610 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 11:08:40.983117 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 11:08:40.986292 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 11:08:40.993206 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5123 11:08:40.995934 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5124 11:08:40.999567 Total UI for P1: 0, mck2ui 16
5125 11:08:41.002530 best dqsien dly found for B0: ( 1, 2, 24)
5126 11:08:41.006064 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5127 11:08:41.012684 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 11:08:41.015820 Total UI for P1: 0, mck2ui 16
5129 11:08:41.019713 best dqsien dly found for B1: ( 1, 2, 30)
5130 11:08:41.022574 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5131 11:08:41.025657 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5132 11:08:41.025738
5133 11:08:41.028906 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5134 11:08:41.032355 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5135 11:08:41.036010 [Gating] SW calibration Done
5136 11:08:41.036118 ==
5137 11:08:41.038776 Dram Type= 6, Freq= 0, CH_0, rank 0
5138 11:08:41.041843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5139 11:08:41.041943 ==
5140 11:08:41.045439 RX Vref Scan: 0
5141 11:08:41.045541
5142 11:08:41.048747 RX Vref 0 -> 0, step: 1
5143 11:08:41.048850
5144 11:08:41.048945 RX Delay -80 -> 252, step: 8
5145 11:08:41.055191 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5146 11:08:41.059066 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5147 11:08:41.061809 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5148 11:08:41.065555 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5149 11:08:41.068614 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5150 11:08:41.071967 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5151 11:08:41.078422 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5152 11:08:41.081857 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5153 11:08:41.085119 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5154 11:08:41.088504 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5155 11:08:41.094680 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5156 11:08:41.098172 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5157 11:08:41.101360 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5158 11:08:41.104730 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5159 11:08:41.107853 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5160 11:08:41.111117 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5161 11:08:41.114796 ==
5162 11:08:41.117974 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 11:08:41.121257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 11:08:41.121365 ==
5165 11:08:41.121457 DQS Delay:
5166 11:08:41.124892 DQS0 = 0, DQS1 = 0
5167 11:08:41.124973 DQM Delay:
5168 11:08:41.127942 DQM0 = 102, DQM1 = 88
5169 11:08:41.128036 DQ Delay:
5170 11:08:41.130888 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5171 11:08:41.134114 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5172 11:08:41.137698 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5173 11:08:41.140741 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =95
5174 11:08:41.140840
5175 11:08:41.140930
5176 11:08:41.141018 ==
5177 11:08:41.144351 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 11:08:41.147579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 11:08:41.150933 ==
5180 11:08:41.151038
5181 11:08:41.151130
5182 11:08:41.151231 TX Vref Scan disable
5183 11:08:41.153950 == TX Byte 0 ==
5184 11:08:41.157463 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5185 11:08:41.161051 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5186 11:08:41.164185 == TX Byte 1 ==
5187 11:08:41.167824 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5188 11:08:41.171079 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5189 11:08:41.174151 ==
5190 11:08:41.177630 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 11:08:41.180499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 11:08:41.180581 ==
5193 11:08:41.180652
5194 11:08:41.180714
5195 11:08:41.184066 TX Vref Scan disable
5196 11:08:41.184187 == TX Byte 0 ==
5197 11:08:41.190294 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5198 11:08:41.193927 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5199 11:08:41.194053 == TX Byte 1 ==
5200 11:08:41.200501 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5201 11:08:41.203991 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5202 11:08:41.204073
5203 11:08:41.204137 [DATLAT]
5204 11:08:41.207057 Freq=933, CH0 RK0
5205 11:08:41.207139
5206 11:08:41.207203 DATLAT Default: 0xd
5207 11:08:41.209992 0, 0xFFFF, sum = 0
5208 11:08:41.210075 1, 0xFFFF, sum = 0
5209 11:08:41.213321 2, 0xFFFF, sum = 0
5210 11:08:41.216919 3, 0xFFFF, sum = 0
5211 11:08:41.217001 4, 0xFFFF, sum = 0
5212 11:08:41.219915 5, 0xFFFF, sum = 0
5213 11:08:41.219998 6, 0xFFFF, sum = 0
5214 11:08:41.223654 7, 0xFFFF, sum = 0
5215 11:08:41.223736 8, 0xFFFF, sum = 0
5216 11:08:41.226667 9, 0xFFFF, sum = 0
5217 11:08:41.226749 10, 0x0, sum = 1
5218 11:08:41.230070 11, 0x0, sum = 2
5219 11:08:41.230151 12, 0x0, sum = 3
5220 11:08:41.233070 13, 0x0, sum = 4
5221 11:08:41.233152 best_step = 11
5222 11:08:41.233215
5223 11:08:41.233274 ==
5224 11:08:41.236313 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 11:08:41.239700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 11:08:41.239807 ==
5227 11:08:41.243078 RX Vref Scan: 1
5228 11:08:41.243187
5229 11:08:41.246227 RX Vref 0 -> 0, step: 1
5230 11:08:41.246329
5231 11:08:41.246420 RX Delay -69 -> 252, step: 4
5232 11:08:41.246508
5233 11:08:41.249552 Set Vref, RX VrefLevel [Byte0]: 56
5234 11:08:41.253125 [Byte1]: 49
5235 11:08:41.257898
5236 11:08:41.257979 Final RX Vref Byte 0 = 56 to rank0
5237 11:08:41.261038 Final RX Vref Byte 1 = 49 to rank0
5238 11:08:41.264595 Final RX Vref Byte 0 = 56 to rank1
5239 11:08:41.267850 Final RX Vref Byte 1 = 49 to rank1==
5240 11:08:41.271123 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 11:08:41.277813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 11:08:41.277895 ==
5243 11:08:41.277961 DQS Delay:
5244 11:08:41.281197 DQS0 = 0, DQS1 = 0
5245 11:08:41.281278 DQM Delay:
5246 11:08:41.281344 DQM0 = 102, DQM1 = 90
5247 11:08:41.284217 DQ Delay:
5248 11:08:41.287931 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =98
5249 11:08:41.291109 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =108
5250 11:08:41.294020 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5251 11:08:41.297723 DQ12 =98, DQ13 =94, DQ14 =96, DQ15 =98
5252 11:08:41.297805
5253 11:08:41.297871
5254 11:08:41.304226 [DQSOSCAuto] RK0, (LSB)MR18= 0x1710, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5255 11:08:41.307841 CH0 RK0: MR19=505, MR18=1710
5256 11:08:41.314213 CH0_RK0: MR19=0x505, MR18=0x1710, DQSOSC=414, MR23=63, INC=63, DEC=42
5257 11:08:41.314296
5258 11:08:41.317398 ----->DramcWriteLeveling(PI) begin...
5259 11:08:41.317483 ==
5260 11:08:41.320708 Dram Type= 6, Freq= 0, CH_0, rank 1
5261 11:08:41.323700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 11:08:41.323783 ==
5263 11:08:41.326961 Write leveling (Byte 0): 32 => 32
5264 11:08:41.330927 Write leveling (Byte 1): 27 => 27
5265 11:08:41.333646 DramcWriteLeveling(PI) end<-----
5266 11:08:41.333747
5267 11:08:41.333838 ==
5268 11:08:41.337046 Dram Type= 6, Freq= 0, CH_0, rank 1
5269 11:08:41.344126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 11:08:41.344213 ==
5271 11:08:41.344278 [Gating] SW mode calibration
5272 11:08:41.353336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5273 11:08:41.356927 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5274 11:08:41.363037 0 14 0 | B1->B0 | 2525 3232 | 1 1 | (1 1) (1 1)
5275 11:08:41.366454 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5276 11:08:41.370168 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5277 11:08:41.376395 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5278 11:08:41.379501 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5279 11:08:41.383246 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5280 11:08:41.389464 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5281 11:08:41.392852 0 14 28 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
5282 11:08:41.396323 0 15 0 | B1->B0 | 3030 2525 | 0 0 | (1 0) (0 0)
5283 11:08:41.402631 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
5284 11:08:41.406215 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5285 11:08:41.409222 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5286 11:08:41.415975 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5287 11:08:41.419305 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5288 11:08:41.422075 0 15 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
5289 11:08:41.429305 0 15 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
5290 11:08:41.432016 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5291 11:08:41.435279 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5292 11:08:41.442191 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5293 11:08:41.445284 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5294 11:08:41.448519 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5295 11:08:41.455076 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5296 11:08:41.458694 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5297 11:08:41.461902 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5298 11:08:41.468275 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5299 11:08:41.471807 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 11:08:41.474628 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 11:08:41.481498 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 11:08:41.484773 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 11:08:41.488294 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 11:08:41.494845 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 11:08:41.497979 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 11:08:41.501030 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 11:08:41.507899 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 11:08:41.510888 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 11:08:41.514338 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 11:08:41.520721 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 11:08:41.524042 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 11:08:41.527305 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5313 11:08:41.534016 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5314 11:08:41.537525 Total UI for P1: 0, mck2ui 16
5315 11:08:41.540806 best dqsien dly found for B0: ( 1, 2, 24)
5316 11:08:41.543872 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5317 11:08:41.547186 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 11:08:41.550497 Total UI for P1: 0, mck2ui 16
5319 11:08:41.553632 best dqsien dly found for B1: ( 1, 3, 0)
5320 11:08:41.557302 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5321 11:08:41.560213 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5322 11:08:41.563701
5323 11:08:41.567055 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5324 11:08:41.570533 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5325 11:08:41.573670 [Gating] SW calibration Done
5326 11:08:41.573751 ==
5327 11:08:41.576598 Dram Type= 6, Freq= 0, CH_0, rank 1
5328 11:08:41.579828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 11:08:41.579911 ==
5330 11:08:41.583805 RX Vref Scan: 0
5331 11:08:41.583886
5332 11:08:41.583951 RX Vref 0 -> 0, step: 1
5333 11:08:41.584011
5334 11:08:41.586872 RX Delay -80 -> 252, step: 8
5335 11:08:41.590026 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5336 11:08:41.592933 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5337 11:08:41.599590 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5338 11:08:41.602951 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5339 11:08:41.605933 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5340 11:08:41.609495 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5341 11:08:41.612717 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5342 11:08:41.619475 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5343 11:08:41.622654 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5344 11:08:41.626406 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5345 11:08:41.629623 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5346 11:08:41.632554 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5347 11:08:41.636384 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5348 11:08:41.642325 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5349 11:08:41.645956 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5350 11:08:41.649033 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5351 11:08:41.649116 ==
5352 11:08:41.653342 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 11:08:41.656165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 11:08:41.656246 ==
5355 11:08:41.659165 DQS Delay:
5356 11:08:41.659271 DQS0 = 0, DQS1 = 0
5357 11:08:41.662381 DQM Delay:
5358 11:08:41.662462 DQM0 = 101, DQM1 = 87
5359 11:08:41.662526 DQ Delay:
5360 11:08:41.665450 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =99
5361 11:08:41.669021 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5362 11:08:41.672305 DQ8 =79, DQ9 =71, DQ10 =91, DQ11 =83
5363 11:08:41.678574 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =91
5364 11:08:41.678680
5365 11:08:41.678771
5366 11:08:41.678858 ==
5367 11:08:41.681939 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 11:08:41.685263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 11:08:41.685345 ==
5370 11:08:41.685409
5371 11:08:41.685469
5372 11:08:41.688565 TX Vref Scan disable
5373 11:08:41.688646 == TX Byte 0 ==
5374 11:08:41.695000 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5375 11:08:41.698470 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5376 11:08:41.698551 == TX Byte 1 ==
5377 11:08:41.705171 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5378 11:08:41.708309 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5379 11:08:41.708390 ==
5380 11:08:41.711715 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 11:08:41.714999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 11:08:41.715081 ==
5383 11:08:41.715146
5384 11:08:41.718235
5385 11:08:41.718318 TX Vref Scan disable
5386 11:08:41.721602 == TX Byte 0 ==
5387 11:08:41.724552 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5388 11:08:41.731563 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5389 11:08:41.731646 == TX Byte 1 ==
5390 11:08:41.734695 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5391 11:08:41.741468 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5392 11:08:41.741551
5393 11:08:41.741616 [DATLAT]
5394 11:08:41.741677 Freq=933, CH0 RK1
5395 11:08:41.741736
5396 11:08:41.744690 DATLAT Default: 0xb
5397 11:08:41.747883 0, 0xFFFF, sum = 0
5398 11:08:41.747966 1, 0xFFFF, sum = 0
5399 11:08:41.751042 2, 0xFFFF, sum = 0
5400 11:08:41.751152 3, 0xFFFF, sum = 0
5401 11:08:41.754821 4, 0xFFFF, sum = 0
5402 11:08:41.754904 5, 0xFFFF, sum = 0
5403 11:08:41.757484 6, 0xFFFF, sum = 0
5404 11:08:41.757567 7, 0xFFFF, sum = 0
5405 11:08:41.760690 8, 0xFFFF, sum = 0
5406 11:08:41.760773 9, 0xFFFF, sum = 0
5407 11:08:41.764610 10, 0x0, sum = 1
5408 11:08:41.764693 11, 0x0, sum = 2
5409 11:08:41.768098 12, 0x0, sum = 3
5410 11:08:41.768181 13, 0x0, sum = 4
5411 11:08:41.770795 best_step = 11
5412 11:08:41.770876
5413 11:08:41.770941 ==
5414 11:08:41.773827 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 11:08:41.777329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 11:08:41.777412 ==
5417 11:08:41.777477 RX Vref Scan: 0
5418 11:08:41.780953
5419 11:08:41.781060 RX Vref 0 -> 0, step: 1
5420 11:08:41.781156
5421 11:08:41.784055 RX Delay -69 -> 252, step: 4
5422 11:08:41.791065 iDelay=195, Bit 0, Center 100 (19 ~ 182) 164
5423 11:08:41.793768 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5424 11:08:41.797201 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5425 11:08:41.800283 iDelay=195, Bit 3, Center 96 (11 ~ 182) 172
5426 11:08:41.803606 iDelay=195, Bit 4, Center 102 (15 ~ 190) 176
5427 11:08:41.810572 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5428 11:08:41.813905 iDelay=195, Bit 6, Center 112 (31 ~ 194) 164
5429 11:08:41.816987 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5430 11:08:41.820026 iDelay=195, Bit 8, Center 82 (-1 ~ 166) 168
5431 11:08:41.823591 iDelay=195, Bit 9, Center 78 (-5 ~ 162) 168
5432 11:08:41.829997 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5433 11:08:41.833803 iDelay=195, Bit 11, Center 82 (-1 ~ 166) 168
5434 11:08:41.837186 iDelay=195, Bit 12, Center 94 (11 ~ 178) 168
5435 11:08:41.840064 iDelay=195, Bit 13, Center 96 (15 ~ 178) 164
5436 11:08:41.843235 iDelay=195, Bit 14, Center 102 (19 ~ 186) 168
5437 11:08:41.850285 iDelay=195, Bit 15, Center 96 (15 ~ 178) 164
5438 11:08:41.850364 ==
5439 11:08:41.852930 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 11:08:41.856147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 11:08:41.856220 ==
5442 11:08:41.856291 DQS Delay:
5443 11:08:41.859856 DQS0 = 0, DQS1 = 0
5444 11:08:41.859930 DQM Delay:
5445 11:08:41.863182 DQM0 = 101, DQM1 = 90
5446 11:08:41.863256 DQ Delay:
5447 11:08:41.866200 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =96
5448 11:08:41.869428 DQ4 =102, DQ5 =92, DQ6 =112, DQ7 =110
5449 11:08:41.873245 DQ8 =82, DQ9 =78, DQ10 =94, DQ11 =82
5450 11:08:41.876200 DQ12 =94, DQ13 =96, DQ14 =102, DQ15 =96
5451 11:08:41.876269
5452 11:08:41.876330
5453 11:08:41.886131 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 417 ps
5454 11:08:41.886210 CH0 RK1: MR19=505, MR18=E0B
5455 11:08:41.892574 CH0_RK1: MR19=0x505, MR18=0xE0B, DQSOSC=417, MR23=63, INC=62, DEC=41
5456 11:08:41.896312 [RxdqsGatingPostProcess] freq 933
5457 11:08:41.902560 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5458 11:08:41.906015 best DQS0 dly(2T, 0.5T) = (0, 10)
5459 11:08:41.908986 best DQS1 dly(2T, 0.5T) = (0, 10)
5460 11:08:41.912223 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5461 11:08:41.915253 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5462 11:08:41.919010 best DQS0 dly(2T, 0.5T) = (0, 10)
5463 11:08:41.922005 best DQS1 dly(2T, 0.5T) = (0, 11)
5464 11:08:41.925226 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5465 11:08:41.928325 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5466 11:08:41.932176 Pre-setting of DQS Precalculation
5467 11:08:41.935336 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5468 11:08:41.935464 ==
5469 11:08:41.938467 Dram Type= 6, Freq= 0, CH_1, rank 0
5470 11:08:41.941653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 11:08:41.941735 ==
5472 11:08:41.948602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5473 11:08:41.955138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5474 11:08:41.958414 [CA 0] Center 36 (6~67) winsize 62
5475 11:08:41.961688 [CA 1] Center 36 (6~67) winsize 62
5476 11:08:41.965079 [CA 2] Center 35 (5~65) winsize 61
5477 11:08:41.968307 [CA 3] Center 34 (3~65) winsize 63
5478 11:08:41.971529 [CA 4] Center 34 (4~65) winsize 62
5479 11:08:41.974617 [CA 5] Center 33 (3~64) winsize 62
5480 11:08:41.974715
5481 11:08:41.978327 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5482 11:08:41.978409
5483 11:08:41.981968 [CATrainingPosCal] consider 1 rank data
5484 11:08:41.984795 u2DelayCellTimex100 = 270/100 ps
5485 11:08:41.988152 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5486 11:08:41.991147 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5487 11:08:41.994639 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5488 11:08:41.997934 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5489 11:08:42.004599 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5490 11:08:42.007850 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5491 11:08:42.007943
5492 11:08:42.011067 CA PerBit enable=1, Macro0, CA PI delay=33
5493 11:08:42.011172
5494 11:08:42.014158 [CBTSetCACLKResult] CA Dly = 33
5495 11:08:42.014269 CS Dly: 6 (0~37)
5496 11:08:42.014364 ==
5497 11:08:42.017769 Dram Type= 6, Freq= 0, CH_1, rank 1
5498 11:08:42.024110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 11:08:42.024192 ==
5500 11:08:42.027390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5501 11:08:42.033859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5502 11:08:42.037283 [CA 0] Center 37 (6~68) winsize 63
5503 11:08:42.040277 [CA 1] Center 37 (7~67) winsize 61
5504 11:08:42.043662 [CA 2] Center 34 (4~65) winsize 62
5505 11:08:42.047019 [CA 3] Center 33 (3~64) winsize 62
5506 11:08:42.050437 [CA 4] Center 33 (3~64) winsize 62
5507 11:08:42.053497 [CA 5] Center 33 (3~64) winsize 62
5508 11:08:42.053580
5509 11:08:42.057182 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5510 11:08:42.057316
5511 11:08:42.060506 [CATrainingPosCal] consider 2 rank data
5512 11:08:42.063641 u2DelayCellTimex100 = 270/100 ps
5513 11:08:42.067027 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5514 11:08:42.074083 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5515 11:08:42.076975 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5516 11:08:42.080247 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5517 11:08:42.083682 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5518 11:08:42.086651 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5519 11:08:42.086736
5520 11:08:42.089686 CA PerBit enable=1, Macro0, CA PI delay=33
5521 11:08:42.089770
5522 11:08:42.092894 [CBTSetCACLKResult] CA Dly = 33
5523 11:08:42.096141 CS Dly: 7 (0~39)
5524 11:08:42.096225
5525 11:08:42.099967 ----->DramcWriteLeveling(PI) begin...
5526 11:08:42.100053 ==
5527 11:08:42.102879 Dram Type= 6, Freq= 0, CH_1, rank 0
5528 11:08:42.106376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 11:08:42.106461 ==
5530 11:08:42.109457 Write leveling (Byte 0): 26 => 26
5531 11:08:42.112847 Write leveling (Byte 1): 27 => 27
5532 11:08:42.116030 DramcWriteLeveling(PI) end<-----
5533 11:08:42.116163
5534 11:08:42.116279 ==
5535 11:08:42.119116 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 11:08:42.122775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 11:08:42.122927 ==
5538 11:08:42.126096 [Gating] SW mode calibration
5539 11:08:42.132607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5540 11:08:42.139020 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5541 11:08:42.142536 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 11:08:42.148820 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 11:08:42.152322 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 11:08:42.155349 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 11:08:42.161687 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 11:08:42.165063 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 11:08:42.168294 0 14 24 | B1->B0 | 3333 3333 | 1 1 | (1 0) (1 0)
5548 11:08:42.175389 0 14 28 | B1->B0 | 2a2a 2828 | 1 1 | (1 1) (1 1)
5549 11:08:42.178592 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 11:08:42.181583 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 11:08:42.188258 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 11:08:42.191804 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 11:08:42.194904 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 11:08:42.201350 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 11:08:42.204906 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5556 11:08:42.208198 0 15 28 | B1->B0 | 3636 3939 | 1 0 | (0 0) (0 0)
5557 11:08:42.214708 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 11:08:42.217981 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 11:08:42.220916 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 11:08:42.227526 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 11:08:42.231118 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 11:08:42.234414 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 11:08:42.240694 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5564 11:08:42.244272 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5565 11:08:42.247578 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5566 11:08:42.254059 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 11:08:42.257092 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 11:08:42.260573 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 11:08:42.267369 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 11:08:42.270685 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 11:08:42.273984 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 11:08:42.280454 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 11:08:42.283332 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 11:08:42.286932 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 11:08:42.293518 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 11:08:42.296856 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 11:08:42.300146 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 11:08:42.307172 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 11:08:42.309769 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5580 11:08:42.313250 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 11:08:42.316580 Total UI for P1: 0, mck2ui 16
5582 11:08:42.320112 best dqsien dly found for B0: ( 1, 2, 26)
5583 11:08:42.323244 Total UI for P1: 0, mck2ui 16
5584 11:08:42.326472 best dqsien dly found for B1: ( 1, 2, 24)
5585 11:08:42.329690 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5586 11:08:42.333281 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5587 11:08:42.333357
5588 11:08:42.339893 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5589 11:08:42.342715 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5590 11:08:42.346369 [Gating] SW calibration Done
5591 11:08:42.346444 ==
5592 11:08:42.349404 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 11:08:42.352966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 11:08:42.353042 ==
5595 11:08:42.353105 RX Vref Scan: 0
5596 11:08:42.356261
5597 11:08:42.356335 RX Vref 0 -> 0, step: 1
5598 11:08:42.356398
5599 11:08:42.359914 RX Delay -80 -> 252, step: 8
5600 11:08:42.362644 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5601 11:08:42.366120 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5602 11:08:42.372664 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5603 11:08:42.375820 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5604 11:08:42.378832 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5605 11:08:42.382403 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5606 11:08:42.385646 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5607 11:08:42.388668 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5608 11:08:42.395102 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5609 11:08:42.398722 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5610 11:08:42.402030 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5611 11:08:42.405382 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5612 11:08:42.408311 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5613 11:08:42.414814 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5614 11:08:42.418779 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5615 11:08:42.421713 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5616 11:08:42.421794 ==
5617 11:08:42.424888 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 11:08:42.428198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 11:08:42.428299 ==
5620 11:08:42.431077 DQS Delay:
5621 11:08:42.431174 DQS0 = 0, DQS1 = 0
5622 11:08:42.434433 DQM Delay:
5623 11:08:42.434513 DQM0 = 98, DQM1 = 93
5624 11:08:42.438114 DQ Delay:
5625 11:08:42.438195 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5626 11:08:42.441457 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5627 11:08:42.444605 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =87
5628 11:08:42.451097 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5629 11:08:42.451175
5630 11:08:42.451239
5631 11:08:42.451299 ==
5632 11:08:42.454128 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 11:08:42.457705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 11:08:42.457781 ==
5635 11:08:42.457852
5636 11:08:42.457912
5637 11:08:42.461202 TX Vref Scan disable
5638 11:08:42.461275 == TX Byte 0 ==
5639 11:08:42.467920 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5640 11:08:42.470877 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5641 11:08:42.470961 == TX Byte 1 ==
5642 11:08:42.477656 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5643 11:08:42.480662 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5644 11:08:42.480738 ==
5645 11:08:42.484165 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 11:08:42.487589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 11:08:42.487671 ==
5648 11:08:42.487735
5649 11:08:42.487795
5650 11:08:42.490642 TX Vref Scan disable
5651 11:08:42.494784 == TX Byte 0 ==
5652 11:08:42.497353 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5653 11:08:42.500955 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5654 11:08:42.503928 == TX Byte 1 ==
5655 11:08:42.506915 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5656 11:08:42.513583 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5657 11:08:42.513691
5658 11:08:42.513756 [DATLAT]
5659 11:08:42.513854 Freq=933, CH1 RK0
5660 11:08:42.513914
5661 11:08:42.517003 DATLAT Default: 0xd
5662 11:08:42.517074 0, 0xFFFF, sum = 0
5663 11:08:42.520143 1, 0xFFFF, sum = 0
5664 11:08:42.520241 2, 0xFFFF, sum = 0
5665 11:08:42.523358 3, 0xFFFF, sum = 0
5666 11:08:42.526974 4, 0xFFFF, sum = 0
5667 11:08:42.527113 5, 0xFFFF, sum = 0
5668 11:08:42.530742 6, 0xFFFF, sum = 0
5669 11:08:42.530867 7, 0xFFFF, sum = 0
5670 11:08:42.533333 8, 0xFFFF, sum = 0
5671 11:08:42.533469 9, 0xFFFF, sum = 0
5672 11:08:42.536649 10, 0x0, sum = 1
5673 11:08:42.536819 11, 0x0, sum = 2
5674 11:08:42.540019 12, 0x0, sum = 3
5675 11:08:42.540123 13, 0x0, sum = 4
5676 11:08:42.540225 best_step = 11
5677 11:08:42.540312
5678 11:08:42.543220 ==
5679 11:08:42.546789 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 11:08:42.550207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 11:08:42.550328 ==
5682 11:08:42.550433 RX Vref Scan: 1
5683 11:08:42.550559
5684 11:08:42.553261 RX Vref 0 -> 0, step: 1
5685 11:08:42.553344
5686 11:08:42.556755 RX Delay -61 -> 252, step: 4
5687 11:08:42.556836
5688 11:08:42.560051 Set Vref, RX VrefLevel [Byte0]: 51
5689 11:08:42.563198 [Byte1]: 52
5690 11:08:42.563333
5691 11:08:42.566503 Final RX Vref Byte 0 = 51 to rank0
5692 11:08:42.569876 Final RX Vref Byte 1 = 52 to rank0
5693 11:08:42.573136 Final RX Vref Byte 0 = 51 to rank1
5694 11:08:42.576479 Final RX Vref Byte 1 = 52 to rank1==
5695 11:08:42.579701 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 11:08:42.586139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 11:08:42.586272 ==
5698 11:08:42.586385 DQS Delay:
5699 11:08:42.586506 DQS0 = 0, DQS1 = 0
5700 11:08:42.589860 DQM Delay:
5701 11:08:42.589992 DQM0 = 96, DQM1 = 92
5702 11:08:42.592812 DQ Delay:
5703 11:08:42.596565 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =94
5704 11:08:42.599525 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =92
5705 11:08:42.602986 DQ8 =78, DQ9 =82, DQ10 =90, DQ11 =86
5706 11:08:42.606213 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5707 11:08:42.606345
5708 11:08:42.606458
5709 11:08:42.612584 [DQSOSCAuto] RK0, (LSB)MR18= 0x717, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5710 11:08:42.616196 CH1 RK0: MR19=505, MR18=717
5711 11:08:42.623090 CH1_RK0: MR19=0x505, MR18=0x717, DQSOSC=414, MR23=63, INC=63, DEC=42
5712 11:08:42.623224
5713 11:08:42.625691 ----->DramcWriteLeveling(PI) begin...
5714 11:08:42.625814 ==
5715 11:08:42.629221 Dram Type= 6, Freq= 0, CH_1, rank 1
5716 11:08:42.632377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 11:08:42.632501 ==
5718 11:08:42.635583 Write leveling (Byte 0): 25 => 25
5719 11:08:42.639115 Write leveling (Byte 1): 27 => 27
5720 11:08:42.642276 DramcWriteLeveling(PI) end<-----
5721 11:08:42.642398
5722 11:08:42.642517 ==
5723 11:08:42.645594 Dram Type= 6, Freq= 0, CH_1, rank 1
5724 11:08:42.648992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 11:08:42.652042 ==
5726 11:08:42.652147 [Gating] SW mode calibration
5727 11:08:42.662222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5728 11:08:42.665650 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5729 11:08:42.668434 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5730 11:08:42.675094 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5731 11:08:42.678852 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5732 11:08:42.681762 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5733 11:08:42.688513 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5734 11:08:42.691901 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5735 11:08:42.695078 0 14 24 | B1->B0 | 3333 2828 | 1 1 | (1 1) (1 0)
5736 11:08:42.701545 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
5737 11:08:42.704735 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5738 11:08:42.708387 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5739 11:08:42.714690 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5740 11:08:42.718239 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5741 11:08:42.721451 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5742 11:08:42.727801 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5743 11:08:42.731083 0 15 24 | B1->B0 | 2828 3939 | 1 1 | (0 0) (0 0)
5744 11:08:42.734817 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5745 11:08:42.741116 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5746 11:08:42.744667 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5747 11:08:42.747947 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5748 11:08:42.754171 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5749 11:08:42.757527 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5750 11:08:42.761390 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5751 11:08:42.767202 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5752 11:08:42.770502 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5753 11:08:42.773916 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5754 11:08:42.780838 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 11:08:42.784151 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 11:08:42.787065 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 11:08:42.793938 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 11:08:42.796948 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 11:08:42.800974 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 11:08:42.806687 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 11:08:42.810260 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 11:08:42.816770 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 11:08:42.820423 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 11:08:42.823040 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 11:08:42.830063 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 11:08:42.832999 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 11:08:42.836146 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5768 11:08:42.839778 Total UI for P1: 0, mck2ui 16
5769 11:08:42.843042 best dqsien dly found for B0: ( 1, 2, 22)
5770 11:08:42.849826 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5771 11:08:42.852499 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 11:08:42.856021 Total UI for P1: 0, mck2ui 16
5773 11:08:42.859370 best dqsien dly found for B1: ( 1, 2, 28)
5774 11:08:42.862631 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5775 11:08:42.865796 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5776 11:08:42.865879
5777 11:08:42.869327 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5778 11:08:42.872422 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5779 11:08:42.876113 [Gating] SW calibration Done
5780 11:08:42.876197 ==
5781 11:08:42.879089 Dram Type= 6, Freq= 0, CH_1, rank 1
5782 11:08:42.882439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 11:08:42.885612 ==
5784 11:08:42.885696 RX Vref Scan: 0
5785 11:08:42.885764
5786 11:08:42.889186 RX Vref 0 -> 0, step: 1
5787 11:08:42.889270
5788 11:08:42.892323 RX Delay -80 -> 252, step: 8
5789 11:08:42.895495 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5790 11:08:42.898752 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5791 11:08:42.902228 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5792 11:08:42.905476 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5793 11:08:42.908564 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5794 11:08:42.915270 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5795 11:08:42.918301 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5796 11:08:42.921505 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5797 11:08:42.925349 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5798 11:08:42.928505 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5799 11:08:42.934942 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5800 11:08:42.938098 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5801 11:08:42.941962 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5802 11:08:42.945219 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5803 11:08:42.948175 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5804 11:08:42.951502 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5805 11:08:42.954563 ==
5806 11:08:42.957900 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 11:08:42.961180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 11:08:42.961264 ==
5809 11:08:42.961331 DQS Delay:
5810 11:08:42.964737 DQS0 = 0, DQS1 = 0
5811 11:08:42.964821 DQM Delay:
5812 11:08:42.968130 DQM0 = 96, DQM1 = 92
5813 11:08:42.968243 DQ Delay:
5814 11:08:42.971097 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =95
5815 11:08:42.974419 DQ4 =95, DQ5 =107, DQ6 =99, DQ7 =95
5816 11:08:42.978418 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5817 11:08:42.980905 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5818 11:08:42.980989
5819 11:08:42.981055
5820 11:08:42.981117 ==
5821 11:08:42.984055 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 11:08:42.987519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 11:08:42.987603 ==
5824 11:08:42.987674
5825 11:08:42.987736
5826 11:08:42.991158 TX Vref Scan disable
5827 11:08:42.994139 == TX Byte 0 ==
5828 11:08:42.997476 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5829 11:08:43.000935 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5830 11:08:43.004128 == TX Byte 1 ==
5831 11:08:43.007102 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5832 11:08:43.010466 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5833 11:08:43.010551 ==
5834 11:08:43.013933 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 11:08:43.020658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 11:08:43.020783 ==
5837 11:08:43.020863
5838 11:08:43.020927
5839 11:08:43.020988 TX Vref Scan disable
5840 11:08:43.024671 == TX Byte 0 ==
5841 11:08:43.028388 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5842 11:08:43.034895 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5843 11:08:43.035006 == TX Byte 1 ==
5844 11:08:43.038276 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5845 11:08:43.044245 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5846 11:08:43.044330
5847 11:08:43.044396 [DATLAT]
5848 11:08:43.044458 Freq=933, CH1 RK1
5849 11:08:43.044518
5850 11:08:43.047761 DATLAT Default: 0xb
5851 11:08:43.051115 0, 0xFFFF, sum = 0
5852 11:08:43.051228 1, 0xFFFF, sum = 0
5853 11:08:43.054542 2, 0xFFFF, sum = 0
5854 11:08:43.054627 3, 0xFFFF, sum = 0
5855 11:08:43.057666 4, 0xFFFF, sum = 0
5856 11:08:43.057751 5, 0xFFFF, sum = 0
5857 11:08:43.060810 6, 0xFFFF, sum = 0
5858 11:08:43.060899 7, 0xFFFF, sum = 0
5859 11:08:43.063943 8, 0xFFFF, sum = 0
5860 11:08:43.064028 9, 0xFFFF, sum = 0
5861 11:08:43.067426 10, 0x0, sum = 1
5862 11:08:43.067541 11, 0x0, sum = 2
5863 11:08:43.070791 12, 0x0, sum = 3
5864 11:08:43.070900 13, 0x0, sum = 4
5865 11:08:43.073879 best_step = 11
5866 11:08:43.073963
5867 11:08:43.074030 ==
5868 11:08:43.077660 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 11:08:43.080693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 11:08:43.080806 ==
5871 11:08:43.080902 RX Vref Scan: 0
5872 11:08:43.084159
5873 11:08:43.084231 RX Vref 0 -> 0, step: 1
5874 11:08:43.084294
5875 11:08:43.087341 RX Delay -53 -> 252, step: 4
5876 11:08:43.093451 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5877 11:08:43.096840 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5878 11:08:43.100380 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5879 11:08:43.103255 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5880 11:08:43.106599 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5881 11:08:43.113345 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5882 11:08:43.116776 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5883 11:08:43.119910 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5884 11:08:43.122953 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5885 11:08:43.126476 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5886 11:08:43.132885 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5887 11:08:43.136564 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5888 11:08:43.139823 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5889 11:08:43.143195 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5890 11:08:43.146213 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5891 11:08:43.152921 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5892 11:08:43.153005 ==
5893 11:08:43.156332 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 11:08:43.159461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 11:08:43.159546 ==
5896 11:08:43.159613 DQS Delay:
5897 11:08:43.162912 DQS0 = 0, DQS1 = 0
5898 11:08:43.163023 DQM Delay:
5899 11:08:43.166295 DQM0 = 95, DQM1 = 93
5900 11:08:43.166379 DQ Delay:
5901 11:08:43.169325 DQ0 =102, DQ1 =94, DQ2 =84, DQ3 =92
5902 11:08:43.172476 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =92
5903 11:08:43.175688 DQ8 =82, DQ9 =82, DQ10 =92, DQ11 =86
5904 11:08:43.178958 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =100
5905 11:08:43.179065
5906 11:08:43.179159
5907 11:08:43.189303 [DQSOSCAuto] RK1, (LSB)MR18= 0xe25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5908 11:08:43.189444 CH1 RK1: MR19=505, MR18=E25
5909 11:08:43.195565 CH1_RK1: MR19=0x505, MR18=0xE25, DQSOSC=410, MR23=63, INC=64, DEC=42
5910 11:08:43.199102 [RxdqsGatingPostProcess] freq 933
5911 11:08:43.205929 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5912 11:08:43.209040 best DQS0 dly(2T, 0.5T) = (0, 10)
5913 11:08:43.212143 best DQS1 dly(2T, 0.5T) = (0, 10)
5914 11:08:43.215767 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5915 11:08:43.219065 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5916 11:08:43.221750 best DQS0 dly(2T, 0.5T) = (0, 10)
5917 11:08:43.225079 best DQS1 dly(2T, 0.5T) = (0, 10)
5918 11:08:43.228706 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5919 11:08:43.231879 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5920 11:08:43.231976 Pre-setting of DQS Precalculation
5921 11:08:43.238196 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5922 11:08:43.244807 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5923 11:08:43.251888 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5924 11:08:43.251970
5925 11:08:43.254946
5926 11:08:43.255070 [Calibration Summary] 1866 Mbps
5927 11:08:43.258228 CH 0, Rank 0
5928 11:08:43.258310 SW Impedance : PASS
5929 11:08:43.261519 DUTY Scan : NO K
5930 11:08:43.264725 ZQ Calibration : PASS
5931 11:08:43.264837 Jitter Meter : NO K
5932 11:08:43.267952 CBT Training : PASS
5933 11:08:43.270917 Write leveling : PASS
5934 11:08:43.271015 RX DQS gating : PASS
5935 11:08:43.274329 RX DQ/DQS(RDDQC) : PASS
5936 11:08:43.277871 TX DQ/DQS : PASS
5937 11:08:43.278008 RX DATLAT : PASS
5938 11:08:43.281084 RX DQ/DQS(Engine): PASS
5939 11:08:43.284162 TX OE : NO K
5940 11:08:43.284236 All Pass.
5941 11:08:43.284306
5942 11:08:43.284365 CH 0, Rank 1
5943 11:08:43.287576 SW Impedance : PASS
5944 11:08:43.291246 DUTY Scan : NO K
5945 11:08:43.291355 ZQ Calibration : PASS
5946 11:08:43.294176 Jitter Meter : NO K
5947 11:08:43.297504 CBT Training : PASS
5948 11:08:43.297601 Write leveling : PASS
5949 11:08:43.301532 RX DQS gating : PASS
5950 11:08:43.304336 RX DQ/DQS(RDDQC) : PASS
5951 11:08:43.304482 TX DQ/DQS : PASS
5952 11:08:43.307347 RX DATLAT : PASS
5953 11:08:43.307472 RX DQ/DQS(Engine): PASS
5954 11:08:43.310849 TX OE : NO K
5955 11:08:43.310973 All Pass.
5956 11:08:43.311097
5957 11:08:43.314302 CH 1, Rank 0
5958 11:08:43.314384 SW Impedance : PASS
5959 11:08:43.317619 DUTY Scan : NO K
5960 11:08:43.320942 ZQ Calibration : PASS
5961 11:08:43.321080 Jitter Meter : NO K
5962 11:08:43.324309 CBT Training : PASS
5963 11:08:43.327533 Write leveling : PASS
5964 11:08:43.327615 RX DQS gating : PASS
5965 11:08:43.330738 RX DQ/DQS(RDDQC) : PASS
5966 11:08:43.333644 TX DQ/DQS : PASS
5967 11:08:43.333743 RX DATLAT : PASS
5968 11:08:43.337184 RX DQ/DQS(Engine): PASS
5969 11:08:43.340150 TX OE : NO K
5970 11:08:43.340274 All Pass.
5971 11:08:43.340383
5972 11:08:43.340490 CH 1, Rank 1
5973 11:08:43.343544 SW Impedance : PASS
5974 11:08:43.346925 DUTY Scan : NO K
5975 11:08:43.347028 ZQ Calibration : PASS
5976 11:08:43.350424 Jitter Meter : NO K
5977 11:08:43.353902 CBT Training : PASS
5978 11:08:43.353976 Write leveling : PASS
5979 11:08:43.357177 RX DQS gating : PASS
5980 11:08:43.360442 RX DQ/DQS(RDDQC) : PASS
5981 11:08:43.360556 TX DQ/DQS : PASS
5982 11:08:43.363408 RX DATLAT : PASS
5983 11:08:43.366704 RX DQ/DQS(Engine): PASS
5984 11:08:43.366804 TX OE : NO K
5985 11:08:43.370110 All Pass.
5986 11:08:43.370206
5987 11:08:43.370298 DramC Write-DBI off
5988 11:08:43.373413 PER_BANK_REFRESH: Hybrid Mode
5989 11:08:43.373512 TX_TRACKING: ON
5990 11:08:43.383065 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5991 11:08:43.386444 [FAST_K] Save calibration result to emmc
5992 11:08:43.389565 dramc_set_vcore_voltage set vcore to 650000
5993 11:08:43.392742 Read voltage for 400, 6
5994 11:08:43.392870 Vio18 = 0
5995 11:08:43.396214 Vcore = 650000
5996 11:08:43.396336 Vdram = 0
5997 11:08:43.396451 Vddq = 0
5998 11:08:43.399694 Vmddr = 0
5999 11:08:43.402652 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6000 11:08:43.409346 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6001 11:08:43.409469 MEM_TYPE=3, freq_sel=20
6002 11:08:43.412683 sv_algorithm_assistance_LP4_800
6003 11:08:43.419745 ============ PULL DRAM RESETB DOWN ============
6004 11:08:43.422469 ========== PULL DRAM RESETB DOWN end =========
6005 11:08:43.425775 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6006 11:08:43.429954 ===================================
6007 11:08:43.432428 LPDDR4 DRAM CONFIGURATION
6008 11:08:43.435802 ===================================
6009 11:08:43.439147 EX_ROW_EN[0] = 0x0
6010 11:08:43.439266 EX_ROW_EN[1] = 0x0
6011 11:08:43.442656 LP4Y_EN = 0x0
6012 11:08:43.442761 WORK_FSP = 0x0
6013 11:08:43.445543 WL = 0x2
6014 11:08:43.445641 RL = 0x2
6015 11:08:43.448995 BL = 0x2
6016 11:08:43.449077 RPST = 0x0
6017 11:08:43.452472 RD_PRE = 0x0
6018 11:08:43.452555 WR_PRE = 0x1
6019 11:08:43.455132 WR_PST = 0x0
6020 11:08:43.455230 DBI_WR = 0x0
6021 11:08:43.458785 DBI_RD = 0x0
6022 11:08:43.462159 OTF = 0x1
6023 11:08:43.465038 ===================================
6024 11:08:43.468371 ===================================
6025 11:08:43.468453 ANA top config
6026 11:08:43.471717 ===================================
6027 11:08:43.475155 DLL_ASYNC_EN = 0
6028 11:08:43.475253 ALL_SLAVE_EN = 1
6029 11:08:43.478357 NEW_RANK_MODE = 1
6030 11:08:43.481600 DLL_IDLE_MODE = 1
6031 11:08:43.484711 LP45_APHY_COMB_EN = 1
6032 11:08:43.488101 TX_ODT_DIS = 1
6033 11:08:43.488211 NEW_8X_MODE = 1
6034 11:08:43.491740 ===================================
6035 11:08:43.494784 ===================================
6036 11:08:43.498008 data_rate = 800
6037 11:08:43.501121 CKR = 1
6038 11:08:43.504646 DQ_P2S_RATIO = 4
6039 11:08:43.507877 ===================================
6040 11:08:43.510888 CA_P2S_RATIO = 4
6041 11:08:43.514380 DQ_CA_OPEN = 0
6042 11:08:43.517590 DQ_SEMI_OPEN = 1
6043 11:08:43.517675 CA_SEMI_OPEN = 1
6044 11:08:43.521354 CA_FULL_RATE = 0
6045 11:08:43.524632 DQ_CKDIV4_EN = 0
6046 11:08:43.527749 CA_CKDIV4_EN = 1
6047 11:08:43.531271 CA_PREDIV_EN = 0
6048 11:08:43.534510 PH8_DLY = 0
6049 11:08:43.534592 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6050 11:08:43.537965 DQ_AAMCK_DIV = 0
6051 11:08:43.540692 CA_AAMCK_DIV = 0
6052 11:08:43.544405 CA_ADMCK_DIV = 4
6053 11:08:43.547298 DQ_TRACK_CA_EN = 0
6054 11:08:43.551133 CA_PICK = 800
6055 11:08:43.551242 CA_MCKIO = 400
6056 11:08:43.554188 MCKIO_SEMI = 400
6057 11:08:43.557532 PLL_FREQ = 3016
6058 11:08:43.560728 DQ_UI_PI_RATIO = 32
6059 11:08:43.563971 CA_UI_PI_RATIO = 32
6060 11:08:43.566858 ===================================
6061 11:08:43.570872 ===================================
6062 11:08:43.573962 memory_type:LPDDR4
6063 11:08:43.574044 GP_NUM : 10
6064 11:08:43.577010 SRAM_EN : 1
6065 11:08:43.580413 MD32_EN : 0
6066 11:08:43.583558 ===================================
6067 11:08:43.583640 [ANA_INIT] >>>>>>>>>>>>>>
6068 11:08:43.586770 <<<<<< [CONFIGURE PHASE]: ANA_TX
6069 11:08:43.590258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6070 11:08:43.593344 ===================================
6071 11:08:43.597230 data_rate = 800,PCW = 0X7400
6072 11:08:43.600052 ===================================
6073 11:08:43.603195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6074 11:08:43.609671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6075 11:08:43.619818 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6076 11:08:43.626182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6077 11:08:43.629339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6078 11:08:43.633151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6079 11:08:43.633233 [ANA_INIT] flow start
6080 11:08:43.636499 [ANA_INIT] PLL >>>>>>>>
6081 11:08:43.639414 [ANA_INIT] PLL <<<<<<<<
6082 11:08:43.642923 [ANA_INIT] MIDPI >>>>>>>>
6083 11:08:43.643025 [ANA_INIT] MIDPI <<<<<<<<
6084 11:08:43.645872 [ANA_INIT] DLL >>>>>>>>
6085 11:08:43.649462 [ANA_INIT] flow end
6086 11:08:43.652498 ============ LP4 DIFF to SE enter ============
6087 11:08:43.655755 ============ LP4 DIFF to SE exit ============
6088 11:08:43.659154 [ANA_INIT] <<<<<<<<<<<<<
6089 11:08:43.662553 [Flow] Enable top DCM control >>>>>
6090 11:08:43.665826 [Flow] Enable top DCM control <<<<<
6091 11:08:43.669044 Enable DLL master slave shuffle
6092 11:08:43.672525 ==============================================================
6093 11:08:43.675876 Gating Mode config
6094 11:08:43.678948 ==============================================================
6095 11:08:43.682184 Config description:
6096 11:08:43.692383 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6097 11:08:43.698597 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6098 11:08:43.702218 SELPH_MODE 0: By rank 1: By Phase
6099 11:08:43.708872 ==============================================================
6100 11:08:43.711844 GAT_TRACK_EN = 0
6101 11:08:43.715123 RX_GATING_MODE = 2
6102 11:08:43.718326 RX_GATING_TRACK_MODE = 2
6103 11:08:43.721993 SELPH_MODE = 1
6104 11:08:43.724934 PICG_EARLY_EN = 1
6105 11:08:43.728082 VALID_LAT_VALUE = 1
6106 11:08:43.731795 ==============================================================
6107 11:08:43.734600 Enter into Gating configuration >>>>
6108 11:08:43.738091 Exit from Gating configuration <<<<
6109 11:08:43.741743 Enter into DVFS_PRE_config >>>>>
6110 11:08:43.754847 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6111 11:08:43.757964 Exit from DVFS_PRE_config <<<<<
6112 11:08:43.761076 Enter into PICG configuration >>>>
6113 11:08:43.761158 Exit from PICG configuration <<<<
6114 11:08:43.764456 [RX_INPUT] configuration >>>>>
6115 11:08:43.767709 [RX_INPUT] configuration <<<<<
6116 11:08:43.774433 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6117 11:08:43.777877 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6118 11:08:43.784649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6119 11:08:43.791091 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6120 11:08:43.797424 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6121 11:08:43.803926 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6122 11:08:43.807511 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6123 11:08:43.810575 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6124 11:08:43.817309 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6125 11:08:43.820600 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6126 11:08:43.823787 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6127 11:08:43.830149 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6128 11:08:43.833813 ===================================
6129 11:08:43.833910 LPDDR4 DRAM CONFIGURATION
6130 11:08:43.836857 ===================================
6131 11:08:43.840537 EX_ROW_EN[0] = 0x0
6132 11:08:43.840635 EX_ROW_EN[1] = 0x0
6133 11:08:43.843640 LP4Y_EN = 0x0
6134 11:08:43.843752 WORK_FSP = 0x0
6135 11:08:43.846880 WL = 0x2
6136 11:08:43.846979 RL = 0x2
6137 11:08:43.850102 BL = 0x2
6138 11:08:43.853533 RPST = 0x0
6139 11:08:43.853615 RD_PRE = 0x0
6140 11:08:43.856816 WR_PRE = 0x1
6141 11:08:43.856898 WR_PST = 0x0
6142 11:08:43.860673 DBI_WR = 0x0
6143 11:08:43.860770 DBI_RD = 0x0
6144 11:08:43.863839 OTF = 0x1
6145 11:08:43.866597 ===================================
6146 11:08:43.870384 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6147 11:08:43.873166 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6148 11:08:43.879820 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6149 11:08:43.882978 ===================================
6150 11:08:43.883064 LPDDR4 DRAM CONFIGURATION
6151 11:08:43.886650 ===================================
6152 11:08:43.889594 EX_ROW_EN[0] = 0x10
6153 11:08:43.889704 EX_ROW_EN[1] = 0x0
6154 11:08:43.893159 LP4Y_EN = 0x0
6155 11:08:43.893270 WORK_FSP = 0x0
6156 11:08:43.896768 WL = 0x2
6157 11:08:43.899563 RL = 0x2
6158 11:08:43.899647 BL = 0x2
6159 11:08:43.902686 RPST = 0x0
6160 11:08:43.902769 RD_PRE = 0x0
6161 11:08:43.906313 WR_PRE = 0x1
6162 11:08:43.906423 WR_PST = 0x0
6163 11:08:43.909800 DBI_WR = 0x0
6164 11:08:43.909883 DBI_RD = 0x0
6165 11:08:43.913106 OTF = 0x1
6166 11:08:43.916158 ===================================
6167 11:08:43.922653 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6168 11:08:43.925903 nWR fixed to 30
6169 11:08:43.925989 [ModeRegInit_LP4] CH0 RK0
6170 11:08:43.929106 [ModeRegInit_LP4] CH0 RK1
6171 11:08:43.932398 [ModeRegInit_LP4] CH1 RK0
6172 11:08:43.935785 [ModeRegInit_LP4] CH1 RK1
6173 11:08:43.935885 match AC timing 19
6174 11:08:43.942226 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6175 11:08:43.945763 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6176 11:08:43.949102 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6177 11:08:43.955245 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6178 11:08:43.958487 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6179 11:08:43.958568 ==
6180 11:08:43.961868 Dram Type= 6, Freq= 0, CH_0, rank 0
6181 11:08:43.965134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6182 11:08:43.965223 ==
6183 11:08:43.971873 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6184 11:08:43.978596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6185 11:08:43.981959 [CA 0] Center 36 (8~64) winsize 57
6186 11:08:43.985403 [CA 1] Center 36 (8~64) winsize 57
6187 11:08:43.988584 [CA 2] Center 36 (8~64) winsize 57
6188 11:08:43.988697 [CA 3] Center 36 (8~64) winsize 57
6189 11:08:43.992028 [CA 4] Center 36 (8~64) winsize 57
6190 11:08:43.995290 [CA 5] Center 36 (8~64) winsize 57
6191 11:08:43.995403
6192 11:08:44.001675 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6193 11:08:44.001759
6194 11:08:44.005088 [CATrainingPosCal] consider 1 rank data
6195 11:08:44.005200 u2DelayCellTimex100 = 270/100 ps
6196 11:08:44.011573 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6197 11:08:44.015017 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6198 11:08:44.018213 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6199 11:08:44.021286 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6200 11:08:44.024790 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6201 11:08:44.028073 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6202 11:08:44.028184
6203 11:08:44.031646 CA PerBit enable=1, Macro0, CA PI delay=36
6204 11:08:44.031756
6205 11:08:44.034666 [CBTSetCACLKResult] CA Dly = 36
6206 11:08:44.038021 CS Dly: 1 (0~32)
6207 11:08:44.038105 ==
6208 11:08:44.041271 Dram Type= 6, Freq= 0, CH_0, rank 1
6209 11:08:44.045084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6210 11:08:44.045169 ==
6211 11:08:44.051033 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6212 11:08:44.057819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6213 11:08:44.057904 [CA 0] Center 36 (8~64) winsize 57
6214 11:08:44.060905 [CA 1] Center 36 (8~64) winsize 57
6215 11:08:44.064301 [CA 2] Center 36 (8~64) winsize 57
6216 11:08:44.067316 [CA 3] Center 36 (8~64) winsize 57
6217 11:08:44.071136 [CA 4] Center 36 (8~64) winsize 57
6218 11:08:44.074646 [CA 5] Center 36 (8~64) winsize 57
6219 11:08:44.074730
6220 11:08:44.077581 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6221 11:08:44.077665
6222 11:08:44.080842 [CATrainingPosCal] consider 2 rank data
6223 11:08:44.084520 u2DelayCellTimex100 = 270/100 ps
6224 11:08:44.087635 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 11:08:44.093857 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 11:08:44.096970 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 11:08:44.100277 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 11:08:44.103397 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 11:08:44.107187 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 11:08:44.107271
6231 11:08:44.110073 CA PerBit enable=1, Macro0, CA PI delay=36
6232 11:08:44.110158
6233 11:08:44.113575 [CBTSetCACLKResult] CA Dly = 36
6234 11:08:44.116980 CS Dly: 1 (0~32)
6235 11:08:44.117064
6236 11:08:44.120165 ----->DramcWriteLeveling(PI) begin...
6237 11:08:44.120250 ==
6238 11:08:44.123188 Dram Type= 6, Freq= 0, CH_0, rank 0
6239 11:08:44.126869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6240 11:08:44.126979 ==
6241 11:08:44.129686 Write leveling (Byte 0): 40 => 8
6242 11:08:44.133050 Write leveling (Byte 1): 40 => 8
6243 11:08:44.136235 DramcWriteLeveling(PI) end<-----
6244 11:08:44.136318
6245 11:08:44.136384 ==
6246 11:08:44.139618 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 11:08:44.142983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 11:08:44.143093 ==
6249 11:08:44.146329 [Gating] SW mode calibration
6250 11:08:44.152735 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6251 11:08:44.159795 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6252 11:08:44.162804 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6253 11:08:44.169629 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6254 11:08:44.172499 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6255 11:08:44.175964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6256 11:08:44.182629 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6257 11:08:44.186160 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6258 11:08:44.189305 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6259 11:08:44.195728 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6260 11:08:44.199077 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6261 11:08:44.202101 Total UI for P1: 0, mck2ui 16
6262 11:08:44.205807 best dqsien dly found for B0: ( 0, 14, 24)
6263 11:08:44.209097 Total UI for P1: 0, mck2ui 16
6264 11:08:44.212318 best dqsien dly found for B1: ( 0, 14, 24)
6265 11:08:44.215495 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6266 11:08:44.218677 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6267 11:08:44.218790
6268 11:08:44.221964 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6269 11:08:44.225350 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6270 11:08:44.228730 [Gating] SW calibration Done
6271 11:08:44.228854 ==
6272 11:08:44.232023 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 11:08:44.234897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 11:08:44.238033 ==
6275 11:08:44.238184 RX Vref Scan: 0
6276 11:08:44.238295
6277 11:08:44.241495 RX Vref 0 -> 0, step: 1
6278 11:08:44.241619
6279 11:08:44.245016 RX Delay -410 -> 252, step: 16
6280 11:08:44.248205 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6281 11:08:44.251557 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6282 11:08:44.254937 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6283 11:08:44.261424 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6284 11:08:44.264788 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6285 11:08:44.267783 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6286 11:08:44.274372 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6287 11:08:44.277680 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6288 11:08:44.281082 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6289 11:08:44.284422 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6290 11:08:44.290773 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6291 11:08:44.293890 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6292 11:08:44.297657 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6293 11:08:44.301199 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6294 11:08:44.307173 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6295 11:08:44.310982 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6296 11:08:44.311083 ==
6297 11:08:44.314369 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 11:08:44.317083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 11:08:44.317166 ==
6300 11:08:44.320692 DQS Delay:
6301 11:08:44.320773 DQS0 = 35, DQS1 = 51
6302 11:08:44.323805 DQM Delay:
6303 11:08:44.323890 DQM0 = 5, DQM1 = 10
6304 11:08:44.323955 DQ Delay:
6305 11:08:44.327257 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6306 11:08:44.330857 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6307 11:08:44.334030 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6308 11:08:44.336980 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6309 11:08:44.337061
6310 11:08:44.337125
6311 11:08:44.337185 ==
6312 11:08:44.340153 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 11:08:44.347235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 11:08:44.347342 ==
6315 11:08:44.347474
6316 11:08:44.347563
6317 11:08:44.347650 TX Vref Scan disable
6318 11:08:44.349984 == TX Byte 0 ==
6319 11:08:44.353351 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6320 11:08:44.356826 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6321 11:08:44.360072 == TX Byte 1 ==
6322 11:08:44.363910 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6323 11:08:44.366612 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6324 11:08:44.369633 ==
6325 11:08:44.369743 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 11:08:44.376253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 11:08:44.376334 ==
6328 11:08:44.376399
6329 11:08:44.376465
6330 11:08:44.379690 TX Vref Scan disable
6331 11:08:44.379781 == TX Byte 0 ==
6332 11:08:44.382933 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6333 11:08:44.389438 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6334 11:08:44.389514 == TX Byte 1 ==
6335 11:08:44.393125 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 11:08:44.399656 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 11:08:44.399737
6338 11:08:44.399802 [DATLAT]
6339 11:08:44.399862 Freq=400, CH0 RK0
6340 11:08:44.399919
6341 11:08:44.402717 DATLAT Default: 0xf
6342 11:08:44.402784 0, 0xFFFF, sum = 0
6343 11:08:44.406092 1, 0xFFFF, sum = 0
6344 11:08:44.409532 2, 0xFFFF, sum = 0
6345 11:08:44.409631 3, 0xFFFF, sum = 0
6346 11:08:44.412623 4, 0xFFFF, sum = 0
6347 11:08:44.412727 5, 0xFFFF, sum = 0
6348 11:08:44.415805 6, 0xFFFF, sum = 0
6349 11:08:44.415885 7, 0xFFFF, sum = 0
6350 11:08:44.419044 8, 0xFFFF, sum = 0
6351 11:08:44.419147 9, 0xFFFF, sum = 0
6352 11:08:44.422278 10, 0xFFFF, sum = 0
6353 11:08:44.422351 11, 0xFFFF, sum = 0
6354 11:08:44.425693 12, 0xFFFF, sum = 0
6355 11:08:44.425899 13, 0x0, sum = 1
6356 11:08:44.429157 14, 0x0, sum = 2
6357 11:08:44.429301 15, 0x0, sum = 3
6358 11:08:44.432462 16, 0x0, sum = 4
6359 11:08:44.432592 best_step = 14
6360 11:08:44.432703
6361 11:08:44.432811 ==
6362 11:08:44.436047 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 11:08:44.442325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 11:08:44.442462 ==
6365 11:08:44.442576 RX Vref Scan: 1
6366 11:08:44.442698
6367 11:08:44.445493 RX Vref 0 -> 0, step: 1
6368 11:08:44.445630
6369 11:08:44.448965 RX Delay -343 -> 252, step: 8
6370 11:08:44.449098
6371 11:08:44.451855 Set Vref, RX VrefLevel [Byte0]: 56
6372 11:08:44.455084 [Byte1]: 49
6373 11:08:44.455184
6374 11:08:44.458796 Final RX Vref Byte 0 = 56 to rank0
6375 11:08:44.462226 Final RX Vref Byte 1 = 49 to rank0
6376 11:08:44.465348 Final RX Vref Byte 0 = 56 to rank1
6377 11:08:44.468651 Final RX Vref Byte 1 = 49 to rank1==
6378 11:08:44.471678 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 11:08:44.475155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 11:08:44.478089 ==
6381 11:08:44.478203 DQS Delay:
6382 11:08:44.478300 DQS0 = 44, DQS1 = 60
6383 11:08:44.481451 DQM Delay:
6384 11:08:44.481561 DQM0 = 10, DQM1 = 18
6385 11:08:44.484836 DQ Delay:
6386 11:08:44.488518 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6387 11:08:44.488635 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6388 11:08:44.491465 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6389 11:08:44.495052 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6390 11:08:44.498124
6391 11:08:44.498234
6392 11:08:44.504847 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e82, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6393 11:08:44.508054 CH0 RK0: MR19=C0C, MR18=8E82
6394 11:08:44.514295 CH0_RK0: MR19=0xC0C, MR18=0x8E82, DQSOSC=392, MR23=63, INC=384, DEC=256
6395 11:08:44.514407 ==
6396 11:08:44.517931 Dram Type= 6, Freq= 0, CH_0, rank 1
6397 11:08:44.520923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 11:08:44.521004 ==
6399 11:08:44.524432 [Gating] SW mode calibration
6400 11:08:44.531131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6401 11:08:44.537851 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6402 11:08:44.541004 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6403 11:08:44.543961 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6404 11:08:44.550664 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6405 11:08:44.554142 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6406 11:08:44.557773 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 11:08:44.564244 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6408 11:08:44.567288 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6409 11:08:44.570792 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6410 11:08:44.577423 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 11:08:44.580653 Total UI for P1: 0, mck2ui 16
6412 11:08:44.583963 best dqsien dly found for B0: ( 0, 14, 24)
6413 11:08:44.584067 Total UI for P1: 0, mck2ui 16
6414 11:08:44.590035 best dqsien dly found for B1: ( 0, 14, 24)
6415 11:08:44.593957 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6416 11:08:44.596777 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6417 11:08:44.596851
6418 11:08:44.600518 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6419 11:08:44.603162 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6420 11:08:44.606541 [Gating] SW calibration Done
6421 11:08:44.606651 ==
6422 11:08:44.610091 Dram Type= 6, Freq= 0, CH_0, rank 1
6423 11:08:44.613204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 11:08:44.613291 ==
6425 11:08:44.616504 RX Vref Scan: 0
6426 11:08:44.616614
6427 11:08:44.619610 RX Vref 0 -> 0, step: 1
6428 11:08:44.619693
6429 11:08:44.619760 RX Delay -410 -> 252, step: 16
6430 11:08:44.626698 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6431 11:08:44.630160 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6432 11:08:44.633247 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6433 11:08:44.639920 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6434 11:08:44.643020 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6435 11:08:44.645985 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6436 11:08:44.649779 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6437 11:08:44.656125 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6438 11:08:44.659218 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6439 11:08:44.663106 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6440 11:08:44.665713 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6441 11:08:44.672706 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6442 11:08:44.675842 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6443 11:08:44.678989 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6444 11:08:44.685450 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6445 11:08:44.688929 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6446 11:08:44.689018 ==
6447 11:08:44.692304 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 11:08:44.695255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 11:08:44.695381 ==
6450 11:08:44.698622 DQS Delay:
6451 11:08:44.698733 DQS0 = 35, DQS1 = 59
6452 11:08:44.698829 DQM Delay:
6453 11:08:44.702226 DQM0 = 5, DQM1 = 17
6454 11:08:44.702310 DQ Delay:
6455 11:08:44.705584 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6456 11:08:44.708803 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6457 11:08:44.711697 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6458 11:08:44.715215 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6459 11:08:44.715299
6460 11:08:44.715373
6461 11:08:44.715438 ==
6462 11:08:44.718093 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 11:08:44.721899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 11:08:44.725378 ==
6465 11:08:44.725462
6466 11:08:44.725531
6467 11:08:44.725594 TX Vref Scan disable
6468 11:08:44.728114 == TX Byte 0 ==
6469 11:08:44.732020 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6470 11:08:44.735303 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6471 11:08:44.738194 == TX Byte 1 ==
6472 11:08:44.741621 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6473 11:08:44.744748 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6474 11:08:44.744850 ==
6475 11:08:44.748260 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 11:08:44.754912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 11:08:44.755023 ==
6478 11:08:44.755119
6479 11:08:44.755210
6480 11:08:44.755299 TX Vref Scan disable
6481 11:08:44.757893 == TX Byte 0 ==
6482 11:08:44.761442 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6483 11:08:44.765069 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6484 11:08:44.767970 == TX Byte 1 ==
6485 11:08:44.770817 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6486 11:08:44.774751 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6487 11:08:44.774833
6488 11:08:44.777730 [DATLAT]
6489 11:08:44.777823 Freq=400, CH0 RK1
6490 11:08:44.777909
6491 11:08:44.781040 DATLAT Default: 0xe
6492 11:08:44.781154 0, 0xFFFF, sum = 0
6493 11:08:44.784454 1, 0xFFFF, sum = 0
6494 11:08:44.784550 2, 0xFFFF, sum = 0
6495 11:08:44.788043 3, 0xFFFF, sum = 0
6496 11:08:44.788141 4, 0xFFFF, sum = 0
6497 11:08:44.791040 5, 0xFFFF, sum = 0
6498 11:08:44.791120 6, 0xFFFF, sum = 0
6499 11:08:44.793953 7, 0xFFFF, sum = 0
6500 11:08:44.794048 8, 0xFFFF, sum = 0
6501 11:08:44.797640 9, 0xFFFF, sum = 0
6502 11:08:44.800704 10, 0xFFFF, sum = 0
6503 11:08:44.800794 11, 0xFFFF, sum = 0
6504 11:08:44.804437 12, 0xFFFF, sum = 0
6505 11:08:44.804547 13, 0x0, sum = 1
6506 11:08:44.807760 14, 0x0, sum = 2
6507 11:08:44.807847 15, 0x0, sum = 3
6508 11:08:44.810744 16, 0x0, sum = 4
6509 11:08:44.810838 best_step = 14
6510 11:08:44.810924
6511 11:08:44.811032 ==
6512 11:08:44.813887 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 11:08:44.817271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 11:08:44.817351 ==
6515 11:08:44.820326 RX Vref Scan: 0
6516 11:08:44.820403
6517 11:08:44.823525 RX Vref 0 -> 0, step: 1
6518 11:08:44.823613
6519 11:08:44.823680 RX Delay -359 -> 252, step: 8
6520 11:08:44.833221 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6521 11:08:44.835762 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6522 11:08:44.839176 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6523 11:08:44.846030 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6524 11:08:44.849049 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6525 11:08:44.852420 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6526 11:08:44.855927 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6527 11:08:44.862124 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6528 11:08:44.865612 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6529 11:08:44.868541 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6530 11:08:44.871822 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6531 11:08:44.878620 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6532 11:08:44.882241 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6533 11:08:44.885528 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6534 11:08:44.888663 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6535 11:08:44.895222 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6536 11:08:44.895308 ==
6537 11:08:44.898431 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 11:08:44.901933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 11:08:44.902044 ==
6540 11:08:44.905317 DQS Delay:
6541 11:08:44.905391 DQS0 = 44, DQS1 = 60
6542 11:08:44.905454 DQM Delay:
6543 11:08:44.908684 DQM0 = 9, DQM1 = 15
6544 11:08:44.908776 DQ Delay:
6545 11:08:44.911575 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6546 11:08:44.914667 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6547 11:08:44.917918 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6548 11:08:44.921875 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6549 11:08:44.921966
6550 11:08:44.922033
6551 11:08:44.931321 [DQSOSCAuto] RK1, (LSB)MR18= 0x847f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6552 11:08:44.931431 CH0 RK1: MR19=C0C, MR18=847F
6553 11:08:44.937639 CH0_RK1: MR19=0xC0C, MR18=0x847F, DQSOSC=393, MR23=63, INC=382, DEC=254
6554 11:08:44.941292 [RxdqsGatingPostProcess] freq 400
6555 11:08:44.947630 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6556 11:08:44.951104 best DQS0 dly(2T, 0.5T) = (0, 10)
6557 11:08:44.954442 best DQS1 dly(2T, 0.5T) = (0, 10)
6558 11:08:44.957798 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6559 11:08:44.960878 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6560 11:08:44.964009 best DQS0 dly(2T, 0.5T) = (0, 10)
6561 11:08:44.968240 best DQS1 dly(2T, 0.5T) = (0, 10)
6562 11:08:44.970548 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6563 11:08:44.973834 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6564 11:08:44.973938 Pre-setting of DQS Precalculation
6565 11:08:44.980655 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6566 11:08:44.980738 ==
6567 11:08:44.983907 Dram Type= 6, Freq= 0, CH_1, rank 0
6568 11:08:44.987107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 11:08:44.987194 ==
6570 11:08:44.994314 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6571 11:08:45.000486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6572 11:08:45.004151 [CA 0] Center 36 (8~64) winsize 57
6573 11:08:45.006900 [CA 1] Center 36 (8~64) winsize 57
6574 11:08:45.010167 [CA 2] Center 36 (8~64) winsize 57
6575 11:08:45.013336 [CA 3] Center 36 (8~64) winsize 57
6576 11:08:45.016735 [CA 4] Center 36 (8~64) winsize 57
6577 11:08:45.020049 [CA 5] Center 36 (8~64) winsize 57
6578 11:08:45.020136
6579 11:08:45.023110 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6580 11:08:45.023194
6581 11:08:45.026779 [CATrainingPosCal] consider 1 rank data
6582 11:08:45.030304 u2DelayCellTimex100 = 270/100 ps
6583 11:08:45.033535 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6584 11:08:45.036265 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6585 11:08:45.039615 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6586 11:08:45.043379 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6587 11:08:45.046422 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6588 11:08:45.049654 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6589 11:08:45.049754
6590 11:08:45.056307 CA PerBit enable=1, Macro0, CA PI delay=36
6591 11:08:45.056385
6592 11:08:45.056447 [CBTSetCACLKResult] CA Dly = 36
6593 11:08:45.059553 CS Dly: 1 (0~32)
6594 11:08:45.059627 ==
6595 11:08:45.062913 Dram Type= 6, Freq= 0, CH_1, rank 1
6596 11:08:45.065931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 11:08:45.066005 ==
6598 11:08:45.072431 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6599 11:08:45.078915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6600 11:08:45.082553 [CA 0] Center 36 (8~64) winsize 57
6601 11:08:45.085673 [CA 1] Center 36 (8~64) winsize 57
6602 11:08:45.088923 [CA 2] Center 36 (8~64) winsize 57
6603 11:08:45.092401 [CA 3] Center 36 (8~64) winsize 57
6604 11:08:45.095634 [CA 4] Center 36 (8~64) winsize 57
6605 11:08:45.095717 [CA 5] Center 36 (8~64) winsize 57
6606 11:08:45.099569
6607 11:08:45.101995 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6608 11:08:45.102077
6609 11:08:45.105632 [CATrainingPosCal] consider 2 rank data
6610 11:08:45.108808 u2DelayCellTimex100 = 270/100 ps
6611 11:08:45.112382 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 11:08:45.115250 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 11:08:45.118457 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 11:08:45.121888 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 11:08:45.125153 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 11:08:45.128311 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 11:08:45.128410
6618 11:08:45.134728 CA PerBit enable=1, Macro0, CA PI delay=36
6619 11:08:45.134811
6620 11:08:45.134876 [CBTSetCACLKResult] CA Dly = 36
6621 11:08:45.138153 CS Dly: 1 (0~32)
6622 11:08:45.138235
6623 11:08:45.141455 ----->DramcWriteLeveling(PI) begin...
6624 11:08:45.141539 ==
6625 11:08:45.144828 Dram Type= 6, Freq= 0, CH_1, rank 0
6626 11:08:45.147961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 11:08:45.148044 ==
6628 11:08:45.150991 Write leveling (Byte 0): 40 => 8
6629 11:08:45.154461 Write leveling (Byte 1): 40 => 8
6630 11:08:45.157609 DramcWriteLeveling(PI) end<-----
6631 11:08:45.157694
6632 11:08:45.157790 ==
6633 11:08:45.161048 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 11:08:45.167730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 11:08:45.167811 ==
6636 11:08:45.167901 [Gating] SW mode calibration
6637 11:08:45.177587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6638 11:08:45.181031 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6639 11:08:45.187353 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6640 11:08:45.190697 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6641 11:08:45.194040 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6642 11:08:45.200500 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6643 11:08:45.204113 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6644 11:08:45.207289 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6645 11:08:45.213852 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6646 11:08:45.217160 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6647 11:08:45.220325 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6648 11:08:45.224000 Total UI for P1: 0, mck2ui 16
6649 11:08:45.226644 best dqsien dly found for B0: ( 0, 14, 24)
6650 11:08:45.230488 Total UI for P1: 0, mck2ui 16
6651 11:08:45.233445 best dqsien dly found for B1: ( 0, 14, 24)
6652 11:08:45.236750 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6653 11:08:45.240209 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6654 11:08:45.240291
6655 11:08:45.246523 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6656 11:08:45.249747 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6657 11:08:45.249856 [Gating] SW calibration Done
6658 11:08:45.253013 ==
6659 11:08:45.256266 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 11:08:45.259866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 11:08:45.259948 ==
6662 11:08:45.260013 RX Vref Scan: 0
6663 11:08:45.260074
6664 11:08:45.263060 RX Vref 0 -> 0, step: 1
6665 11:08:45.263141
6666 11:08:45.266261 RX Delay -410 -> 252, step: 16
6667 11:08:45.269675 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6668 11:08:45.276442 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6669 11:08:45.279129 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6670 11:08:45.282854 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6671 11:08:45.286082 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6672 11:08:45.292491 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6673 11:08:45.296292 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6674 11:08:45.299149 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6675 11:08:45.302347 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6676 11:08:45.309439 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6677 11:08:45.312869 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6678 11:08:45.315689 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6679 11:08:45.319386 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6680 11:08:45.325861 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6681 11:08:45.328801 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6682 11:08:45.332409 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6683 11:08:45.332490 ==
6684 11:08:45.335683 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 11:08:45.341937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 11:08:45.342082 ==
6687 11:08:45.342194 DQS Delay:
6688 11:08:45.345626 DQS0 = 35, DQS1 = 51
6689 11:08:45.345757 DQM Delay:
6690 11:08:45.345871 DQM0 = 6, DQM1 = 13
6691 11:08:45.348988 DQ Delay:
6692 11:08:45.352588 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6693 11:08:45.352718 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6694 11:08:45.355351 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6695 11:08:45.358353 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6696 11:08:45.358502
6697 11:08:45.362036
6698 11:08:45.362168 ==
6699 11:08:45.365312 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 11:08:45.368769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 11:08:45.368892 ==
6702 11:08:45.369013
6703 11:08:45.369127
6704 11:08:45.372031 TX Vref Scan disable
6705 11:08:45.372182 == TX Byte 0 ==
6706 11:08:45.375374 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6707 11:08:45.381680 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6708 11:08:45.381818 == TX Byte 1 ==
6709 11:08:45.385239 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6710 11:08:45.391485 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6711 11:08:45.391641 ==
6712 11:08:45.394518 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 11:08:45.398910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 11:08:45.399041 ==
6715 11:08:45.399154
6716 11:08:45.399272
6717 11:08:45.401335 TX Vref Scan disable
6718 11:08:45.401515 == TX Byte 0 ==
6719 11:08:45.408255 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6720 11:08:45.411543 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6721 11:08:45.411661 == TX Byte 1 ==
6722 11:08:45.418093 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 11:08:45.421197 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 11:08:45.421323
6725 11:08:45.421437 [DATLAT]
6726 11:08:45.424748 Freq=400, CH1 RK0
6727 11:08:45.424867
6728 11:08:45.424977 DATLAT Default: 0xf
6729 11:08:45.427669 0, 0xFFFF, sum = 0
6730 11:08:45.427795 1, 0xFFFF, sum = 0
6731 11:08:45.431548 2, 0xFFFF, sum = 0
6732 11:08:45.431672 3, 0xFFFF, sum = 0
6733 11:08:45.434430 4, 0xFFFF, sum = 0
6734 11:08:45.434571 5, 0xFFFF, sum = 0
6735 11:08:45.437761 6, 0xFFFF, sum = 0
6736 11:08:45.437886 7, 0xFFFF, sum = 0
6737 11:08:45.441163 8, 0xFFFF, sum = 0
6738 11:08:45.441276 9, 0xFFFF, sum = 0
6739 11:08:45.444192 10, 0xFFFF, sum = 0
6740 11:08:45.447803 11, 0xFFFF, sum = 0
6741 11:08:45.447885 12, 0xFFFF, sum = 0
6742 11:08:45.447951 13, 0x0, sum = 1
6743 11:08:45.451278 14, 0x0, sum = 2
6744 11:08:45.451367 15, 0x0, sum = 3
6745 11:08:45.454458 16, 0x0, sum = 4
6746 11:08:45.454541 best_step = 14
6747 11:08:45.454606
6748 11:08:45.454667 ==
6749 11:08:45.457484 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 11:08:45.464399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 11:08:45.464550 ==
6752 11:08:45.464708 RX Vref Scan: 1
6753 11:08:45.464858
6754 11:08:45.467762 RX Vref 0 -> 0, step: 1
6755 11:08:45.467885
6756 11:08:45.471266 RX Delay -343 -> 252, step: 8
6757 11:08:45.471414
6758 11:08:45.474021 Set Vref, RX VrefLevel [Byte0]: 51
6759 11:08:45.478167 [Byte1]: 52
6760 11:08:45.480658
6761 11:08:45.483958 Final RX Vref Byte 0 = 51 to rank0
6762 11:08:45.484090 Final RX Vref Byte 1 = 52 to rank0
6763 11:08:45.487720 Final RX Vref Byte 0 = 51 to rank1
6764 11:08:45.490794 Final RX Vref Byte 1 = 52 to rank1==
6765 11:08:45.493970 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 11:08:45.500239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 11:08:45.500375 ==
6768 11:08:45.500497 DQS Delay:
6769 11:08:45.503758 DQS0 = 44, DQS1 = 52
6770 11:08:45.503886 DQM Delay:
6771 11:08:45.506866 DQM0 = 10, DQM1 = 11
6772 11:08:45.506997 DQ Delay:
6773 11:08:45.510469 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6774 11:08:45.513885 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6775 11:08:45.514084 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6776 11:08:45.520249 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6777 11:08:45.520382
6778 11:08:45.520495
6779 11:08:45.527054 [DQSOSCAuto] RK0, (LSB)MR18= 0x6b92, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6780 11:08:45.530057 CH1 RK0: MR19=C0C, MR18=6B92
6781 11:08:45.536602 CH1_RK0: MR19=0xC0C, MR18=0x6B92, DQSOSC=391, MR23=63, INC=386, DEC=257
6782 11:08:45.536724 ==
6783 11:08:45.540277 Dram Type= 6, Freq= 0, CH_1, rank 1
6784 11:08:45.543181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 11:08:45.543309 ==
6786 11:08:45.546479 [Gating] SW mode calibration
6787 11:08:45.553127 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6788 11:08:45.559916 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6789 11:08:45.562950 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6790 11:08:45.566148 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6791 11:08:45.573252 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6792 11:08:45.576363 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6793 11:08:45.579761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 11:08:45.585995 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6795 11:08:45.589673 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6796 11:08:45.592574 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6797 11:08:45.599487 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 11:08:45.602397 Total UI for P1: 0, mck2ui 16
6799 11:08:45.605924 best dqsien dly found for B0: ( 0, 14, 24)
6800 11:08:45.609021 Total UI for P1: 0, mck2ui 16
6801 11:08:45.612626 best dqsien dly found for B1: ( 0, 14, 24)
6802 11:08:45.615652 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6803 11:08:45.619449 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6804 11:08:45.619547
6805 11:08:45.622585 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6806 11:08:45.625501 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6807 11:08:45.629047 [Gating] SW calibration Done
6808 11:08:45.629128 ==
6809 11:08:45.632417 Dram Type= 6, Freq= 0, CH_1, rank 1
6810 11:08:45.635648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 11:08:45.635780 ==
6812 11:08:45.639092 RX Vref Scan: 0
6813 11:08:45.639214
6814 11:08:45.642320 RX Vref 0 -> 0, step: 1
6815 11:08:45.642401
6816 11:08:45.642466 RX Delay -410 -> 252, step: 16
6817 11:08:45.648829 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6818 11:08:45.652134 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6819 11:08:45.655220 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6820 11:08:45.661993 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6821 11:08:45.665511 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6822 11:08:45.668673 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6823 11:08:45.672222 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6824 11:08:45.678858 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6825 11:08:45.681752 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6826 11:08:45.684973 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6827 11:08:45.688389 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6828 11:08:45.694904 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6829 11:08:45.698098 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6830 11:08:45.701510 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6831 11:08:45.705119 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6832 11:08:45.711522 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6833 11:08:45.711603 ==
6834 11:08:45.714659 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 11:08:45.718011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 11:08:45.718092 ==
6837 11:08:45.718157 DQS Delay:
6838 11:08:45.721314 DQS0 = 43, DQS1 = 51
6839 11:08:45.721395 DQM Delay:
6840 11:08:45.724883 DQM0 = 9, DQM1 = 15
6841 11:08:45.725008 DQ Delay:
6842 11:08:45.727747 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6843 11:08:45.731325 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6844 11:08:45.734840 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6845 11:08:45.737908 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6846 11:08:45.738040
6847 11:08:45.738154
6848 11:08:45.738272 ==
6849 11:08:45.741118 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 11:08:45.744435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 11:08:45.744559 ==
6852 11:08:45.747415
6853 11:08:45.747563
6854 11:08:45.747706 TX Vref Scan disable
6855 11:08:45.751066 == TX Byte 0 ==
6856 11:08:45.754340 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6857 11:08:45.757441 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6858 11:08:45.760792 == TX Byte 1 ==
6859 11:08:45.764408 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6860 11:08:45.767354 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6861 11:08:45.767514 ==
6862 11:08:45.770720 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 11:08:45.773989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 11:08:45.777178 ==
6865 11:08:45.777301
6866 11:08:45.777420
6867 11:08:45.777533 TX Vref Scan disable
6868 11:08:45.780516 == TX Byte 0 ==
6869 11:08:45.783980 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6870 11:08:45.787249 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6871 11:08:45.790637 == TX Byte 1 ==
6872 11:08:45.793803 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6873 11:08:45.796966 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6874 11:08:45.797088
6875 11:08:45.800179 [DATLAT]
6876 11:08:45.800309 Freq=400, CH1 RK1
6877 11:08:45.800420
6878 11:08:45.803983 DATLAT Default: 0xe
6879 11:08:45.804175 0, 0xFFFF, sum = 0
6880 11:08:45.806682 1, 0xFFFF, sum = 0
6881 11:08:45.806804 2, 0xFFFF, sum = 0
6882 11:08:45.810139 3, 0xFFFF, sum = 0
6883 11:08:45.810271 4, 0xFFFF, sum = 0
6884 11:08:45.813352 5, 0xFFFF, sum = 0
6885 11:08:45.813475 6, 0xFFFF, sum = 0
6886 11:08:45.816694 7, 0xFFFF, sum = 0
6887 11:08:45.816818 8, 0xFFFF, sum = 0
6888 11:08:45.820061 9, 0xFFFF, sum = 0
6889 11:08:45.823281 10, 0xFFFF, sum = 0
6890 11:08:45.823421 11, 0xFFFF, sum = 0
6891 11:08:45.826547 12, 0xFFFF, sum = 0
6892 11:08:45.826764 13, 0x0, sum = 1
6893 11:08:45.830226 14, 0x0, sum = 2
6894 11:08:45.830351 15, 0x0, sum = 3
6895 11:08:45.830469 16, 0x0, sum = 4
6896 11:08:45.832926 best_step = 14
6897 11:08:45.833040
6898 11:08:45.833146 ==
6899 11:08:45.836683 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 11:08:45.840287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 11:08:45.840472 ==
6902 11:08:45.842959 RX Vref Scan: 0
6903 11:08:45.843076
6904 11:08:45.846064 RX Vref 0 -> 0, step: 1
6905 11:08:45.846183
6906 11:08:45.846294 RX Delay -343 -> 252, step: 8
6907 11:08:45.855025 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6908 11:08:45.858174 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6909 11:08:45.861360 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6910 11:08:45.868313 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6911 11:08:45.871632 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6912 11:08:45.874764 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6913 11:08:45.877893 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6914 11:08:45.884589 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6915 11:08:45.887478 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6916 11:08:45.891112 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6917 11:08:45.894584 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6918 11:08:45.901007 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6919 11:08:45.904692 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6920 11:08:45.908022 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6921 11:08:45.911177 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6922 11:08:45.917605 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6923 11:08:45.917688 ==
6924 11:08:45.921116 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 11:08:45.924223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 11:08:45.924306 ==
6927 11:08:45.927214 DQS Delay:
6928 11:08:45.927296 DQS0 = 48, DQS1 = 52
6929 11:08:45.927368 DQM Delay:
6930 11:08:45.930453 DQM0 = 12, DQM1 = 11
6931 11:08:45.930535 DQ Delay:
6932 11:08:45.933708 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6933 11:08:45.937231 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6934 11:08:45.940324 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6935 11:08:45.944090 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6936 11:08:45.944172
6937 11:08:45.944238
6938 11:08:45.953899 [DQSOSCAuto] RK1, (LSB)MR18= 0x73ab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6939 11:08:45.953983 CH1 RK1: MR19=C0C, MR18=73AB
6940 11:08:45.960418 CH1_RK1: MR19=0xC0C, MR18=0x73AB, DQSOSC=388, MR23=63, INC=392, DEC=261
6941 11:08:45.963821 [RxdqsGatingPostProcess] freq 400
6942 11:08:45.969960 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6943 11:08:45.973678 best DQS0 dly(2T, 0.5T) = (0, 10)
6944 11:08:45.976627 best DQS1 dly(2T, 0.5T) = (0, 10)
6945 11:08:45.979833 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6946 11:08:45.983515 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6947 11:08:45.986761 best DQS0 dly(2T, 0.5T) = (0, 10)
6948 11:08:45.989631 best DQS1 dly(2T, 0.5T) = (0, 10)
6949 11:08:45.993154 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6950 11:08:45.996431 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6951 11:08:45.999501 Pre-setting of DQS Precalculation
6952 11:08:46.003235 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6953 11:08:46.009981 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6954 11:08:46.016085 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6955 11:08:46.016212
6956 11:08:46.016327
6957 11:08:46.019824 [Calibration Summary] 800 Mbps
6958 11:08:46.022784 CH 0, Rank 0
6959 11:08:46.022901 SW Impedance : PASS
6960 11:08:46.026276 DUTY Scan : NO K
6961 11:08:46.029565 ZQ Calibration : PASS
6962 11:08:46.029697 Jitter Meter : NO K
6963 11:08:46.032563 CBT Training : PASS
6964 11:08:46.035789 Write leveling : PASS
6965 11:08:46.035912 RX DQS gating : PASS
6966 11:08:46.039132 RX DQ/DQS(RDDQC) : PASS
6967 11:08:46.042397 TX DQ/DQS : PASS
6968 11:08:46.042478 RX DATLAT : PASS
6969 11:08:46.045735 RX DQ/DQS(Engine): PASS
6970 11:08:46.049574 TX OE : NO K
6971 11:08:46.049719 All Pass.
6972 11:08:46.049805
6973 11:08:46.049967 CH 0, Rank 1
6974 11:08:46.052648 SW Impedance : PASS
6975 11:08:46.055854 DUTY Scan : NO K
6976 11:08:46.056068 ZQ Calibration : PASS
6977 11:08:46.059172 Jitter Meter : NO K
6978 11:08:46.062680 CBT Training : PASS
6979 11:08:46.062763 Write leveling : NO K
6980 11:08:46.065375 RX DQS gating : PASS
6981 11:08:46.065457 RX DQ/DQS(RDDQC) : PASS
6982 11:08:46.068731 TX DQ/DQS : PASS
6983 11:08:46.072440 RX DATLAT : PASS
6984 11:08:46.072552 RX DQ/DQS(Engine): PASS
6985 11:08:46.075578 TX OE : NO K
6986 11:08:46.075679 All Pass.
6987 11:08:46.075770
6988 11:08:46.078476 CH 1, Rank 0
6989 11:08:46.078557 SW Impedance : PASS
6990 11:08:46.082059 DUTY Scan : NO K
6991 11:08:46.085004 ZQ Calibration : PASS
6992 11:08:46.085117 Jitter Meter : NO K
6993 11:08:46.088714 CBT Training : PASS
6994 11:08:46.091743 Write leveling : PASS
6995 11:08:46.091826 RX DQS gating : PASS
6996 11:08:46.094908 RX DQ/DQS(RDDQC) : PASS
6997 11:08:46.098239 TX DQ/DQS : PASS
6998 11:08:46.098348 RX DATLAT : PASS
6999 11:08:46.101552 RX DQ/DQS(Engine): PASS
7000 11:08:46.105131 TX OE : NO K
7001 11:08:46.105214 All Pass.
7002 11:08:46.105280
7003 11:08:46.105340 CH 1, Rank 1
7004 11:08:46.108394 SW Impedance : PASS
7005 11:08:46.111849 DUTY Scan : NO K
7006 11:08:46.111931 ZQ Calibration : PASS
7007 11:08:46.114765 Jitter Meter : NO K
7008 11:08:46.117985 CBT Training : PASS
7009 11:08:46.118067 Write leveling : NO K
7010 11:08:46.121288 RX DQS gating : PASS
7011 11:08:46.124452 RX DQ/DQS(RDDQC) : PASS
7012 11:08:46.124526 TX DQ/DQS : PASS
7013 11:08:46.128241 RX DATLAT : PASS
7014 11:08:46.131159 RX DQ/DQS(Engine): PASS
7015 11:08:46.131268 TX OE : NO K
7016 11:08:46.134578 All Pass.
7017 11:08:46.134659
7018 11:08:46.134725 DramC Write-DBI off
7019 11:08:46.137995 PER_BANK_REFRESH: Hybrid Mode
7020 11:08:46.138081 TX_TRACKING: ON
7021 11:08:46.147568 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7022 11:08:46.151029 [FAST_K] Save calibration result to emmc
7023 11:08:46.154499 dramc_set_vcore_voltage set vcore to 725000
7024 11:08:46.157894 Read voltage for 1600, 0
7025 11:08:46.157975 Vio18 = 0
7026 11:08:46.161228 Vcore = 725000
7027 11:08:46.161309 Vdram = 0
7028 11:08:46.161373 Vddq = 0
7029 11:08:46.164320 Vmddr = 0
7030 11:08:46.167281 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7031 11:08:46.173786 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7032 11:08:46.173887 MEM_TYPE=3, freq_sel=13
7033 11:08:46.177580 sv_algorithm_assistance_LP4_3733
7034 11:08:46.184302 ============ PULL DRAM RESETB DOWN ============
7035 11:08:46.186909 ========== PULL DRAM RESETB DOWN end =========
7036 11:08:46.190272 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7037 11:08:46.193530 ===================================
7038 11:08:46.196710 LPDDR4 DRAM CONFIGURATION
7039 11:08:46.200447 ===================================
7040 11:08:46.203480 EX_ROW_EN[0] = 0x0
7041 11:08:46.203555 EX_ROW_EN[1] = 0x0
7042 11:08:46.206622 LP4Y_EN = 0x0
7043 11:08:46.206704 WORK_FSP = 0x1
7044 11:08:46.210215 WL = 0x5
7045 11:08:46.210298 RL = 0x5
7046 11:08:46.213639 BL = 0x2
7047 11:08:46.213720 RPST = 0x0
7048 11:08:46.217211 RD_PRE = 0x0
7049 11:08:46.217291 WR_PRE = 0x1
7050 11:08:46.220081 WR_PST = 0x1
7051 11:08:46.220161 DBI_WR = 0x0
7052 11:08:46.223017 DBI_RD = 0x0
7053 11:08:46.226542 OTF = 0x1
7054 11:08:46.229825 ===================================
7055 11:08:46.232862 ===================================
7056 11:08:46.232943 ANA top config
7057 11:08:46.236427 ===================================
7058 11:08:46.239722 DLL_ASYNC_EN = 0
7059 11:08:46.239803 ALL_SLAVE_EN = 0
7060 11:08:46.242816 NEW_RANK_MODE = 1
7061 11:08:46.246510 DLL_IDLE_MODE = 1
7062 11:08:46.249631 LP45_APHY_COMB_EN = 1
7063 11:08:46.252670 TX_ODT_DIS = 0
7064 11:08:46.252751 NEW_8X_MODE = 1
7065 11:08:46.256361 ===================================
7066 11:08:46.259768 ===================================
7067 11:08:46.262624 data_rate = 3200
7068 11:08:46.265945 CKR = 1
7069 11:08:46.269510 DQ_P2S_RATIO = 8
7070 11:08:46.272658 ===================================
7071 11:08:46.276208 CA_P2S_RATIO = 8
7072 11:08:46.279206 DQ_CA_OPEN = 0
7073 11:08:46.279286 DQ_SEMI_OPEN = 0
7074 11:08:46.283025 CA_SEMI_OPEN = 0
7075 11:08:46.285837 CA_FULL_RATE = 0
7076 11:08:46.289181 DQ_CKDIV4_EN = 0
7077 11:08:46.292565 CA_CKDIV4_EN = 0
7078 11:08:46.296154 CA_PREDIV_EN = 0
7079 11:08:46.296235 PH8_DLY = 12
7080 11:08:46.299229 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7081 11:08:46.302486 DQ_AAMCK_DIV = 4
7082 11:08:46.306263 CA_AAMCK_DIV = 4
7083 11:08:46.309382 CA_ADMCK_DIV = 4
7084 11:08:46.312606 DQ_TRACK_CA_EN = 0
7085 11:08:46.315581 CA_PICK = 1600
7086 11:08:46.315688 CA_MCKIO = 1600
7087 11:08:46.318922 MCKIO_SEMI = 0
7088 11:08:46.322342 PLL_FREQ = 3068
7089 11:08:46.325898 DQ_UI_PI_RATIO = 32
7090 11:08:46.328575 CA_UI_PI_RATIO = 0
7091 11:08:46.332209 ===================================
7092 11:08:46.335669 ===================================
7093 11:08:46.338917 memory_type:LPDDR4
7094 11:08:46.338997 GP_NUM : 10
7095 11:08:46.341793 SRAM_EN : 1
7096 11:08:46.345206 MD32_EN : 0
7097 11:08:46.348855 ===================================
7098 11:08:46.348936 [ANA_INIT] >>>>>>>>>>>>>>
7099 11:08:46.351898 <<<<<< [CONFIGURE PHASE]: ANA_TX
7100 11:08:46.355413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7101 11:08:46.358627 ===================================
7102 11:08:46.361613 data_rate = 3200,PCW = 0X7600
7103 11:08:46.364863 ===================================
7104 11:08:46.368194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7105 11:08:46.374667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7106 11:08:46.377895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7107 11:08:46.384720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7108 11:08:46.387796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7109 11:08:46.391154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7110 11:08:46.394274 [ANA_INIT] flow start
7111 11:08:46.394355 [ANA_INIT] PLL >>>>>>>>
7112 11:08:46.397616 [ANA_INIT] PLL <<<<<<<<
7113 11:08:46.400972 [ANA_INIT] MIDPI >>>>>>>>
7114 11:08:46.401052 [ANA_INIT] MIDPI <<<<<<<<
7115 11:08:46.404534 [ANA_INIT] DLL >>>>>>>>
7116 11:08:46.408137 [ANA_INIT] DLL <<<<<<<<
7117 11:08:46.408234 [ANA_INIT] flow end
7118 11:08:46.413945 ============ LP4 DIFF to SE enter ============
7119 11:08:46.417357 ============ LP4 DIFF to SE exit ============
7120 11:08:46.420794 [ANA_INIT] <<<<<<<<<<<<<
7121 11:08:46.424764 [Flow] Enable top DCM control >>>>>
7122 11:08:46.427496 [Flow] Enable top DCM control <<<<<
7123 11:08:46.427576 Enable DLL master slave shuffle
7124 11:08:46.433935 ==============================================================
7125 11:08:46.437114 Gating Mode config
7126 11:08:46.440334 ==============================================================
7127 11:08:46.444131 Config description:
7128 11:08:46.453503 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7129 11:08:46.460444 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7130 11:08:46.463387 SELPH_MODE 0: By rank 1: By Phase
7131 11:08:46.470623 ==============================================================
7132 11:08:46.473569 GAT_TRACK_EN = 1
7133 11:08:46.476384 RX_GATING_MODE = 2
7134 11:08:46.479977 RX_GATING_TRACK_MODE = 2
7135 11:08:46.483227 SELPH_MODE = 1
7136 11:08:46.486358 PICG_EARLY_EN = 1
7137 11:08:46.489682 VALID_LAT_VALUE = 1
7138 11:08:46.493015 ==============================================================
7139 11:08:46.496365 Enter into Gating configuration >>>>
7140 11:08:46.499333 Exit from Gating configuration <<<<
7141 11:08:46.503272 Enter into DVFS_PRE_config >>>>>
7142 11:08:46.516135 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7143 11:08:46.519193 Exit from DVFS_PRE_config <<<<<
7144 11:08:46.519318 Enter into PICG configuration >>>>
7145 11:08:46.522779 Exit from PICG configuration <<<<
7146 11:08:46.525862 [RX_INPUT] configuration >>>>>
7147 11:08:46.529440 [RX_INPUT] configuration <<<<<
7148 11:08:46.535980 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7149 11:08:46.539185 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7150 11:08:46.545662 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7151 11:08:46.551996 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7152 11:08:46.558640 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7153 11:08:46.565118 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7154 11:08:46.568531 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7155 11:08:46.571894 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7156 11:08:46.578456 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7157 11:08:46.581788 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7158 11:08:46.584820 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7159 11:08:46.588425 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7160 11:08:46.591841 ===================================
7161 11:08:46.595015 LPDDR4 DRAM CONFIGURATION
7162 11:08:46.598766 ===================================
7163 11:08:46.601400 EX_ROW_EN[0] = 0x0
7164 11:08:46.601481 EX_ROW_EN[1] = 0x0
7165 11:08:46.604656 LP4Y_EN = 0x0
7166 11:08:46.604738 WORK_FSP = 0x1
7167 11:08:46.608649 WL = 0x5
7168 11:08:46.608731 RL = 0x5
7169 11:08:46.611147 BL = 0x2
7170 11:08:46.611229 RPST = 0x0
7171 11:08:46.614779 RD_PRE = 0x0
7172 11:08:46.617791 WR_PRE = 0x1
7173 11:08:46.617872 WR_PST = 0x1
7174 11:08:46.621758 DBI_WR = 0x0
7175 11:08:46.621845 DBI_RD = 0x0
7176 11:08:46.624436 OTF = 0x1
7177 11:08:46.627735 ===================================
7178 11:08:46.631406 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7179 11:08:46.634216 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7180 11:08:46.641078 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7181 11:08:46.643974 ===================================
7182 11:08:46.644057 LPDDR4 DRAM CONFIGURATION
7183 11:08:46.647627 ===================================
7184 11:08:46.650805 EX_ROW_EN[0] = 0x10
7185 11:08:46.650888 EX_ROW_EN[1] = 0x0
7186 11:08:46.653903 LP4Y_EN = 0x0
7187 11:08:46.653988 WORK_FSP = 0x1
7188 11:08:46.657207 WL = 0x5
7189 11:08:46.660479 RL = 0x5
7190 11:08:46.660560 BL = 0x2
7191 11:08:46.663474 RPST = 0x0
7192 11:08:46.663554 RD_PRE = 0x0
7193 11:08:46.667024 WR_PRE = 0x1
7194 11:08:46.667104 WR_PST = 0x1
7195 11:08:46.670587 DBI_WR = 0x0
7196 11:08:46.670667 DBI_RD = 0x0
7197 11:08:46.673667 OTF = 0x1
7198 11:08:46.677290 ===================================
7199 11:08:46.683359 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7200 11:08:46.683478 ==
7201 11:08:46.687115 Dram Type= 6, Freq= 0, CH_0, rank 0
7202 11:08:46.690173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7203 11:08:46.690255 ==
7204 11:08:46.693514 [Duty_Offset_Calibration]
7205 11:08:46.693594 B0:2 B1:0 CA:4
7206 11:08:46.693657
7207 11:08:46.696669 [DutyScan_Calibration_Flow] k_type=0
7208 11:08:46.706228
7209 11:08:46.706308 ==CLK 0==
7210 11:08:46.709857 Final CLK duty delay cell = -4
7211 11:08:46.713090 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7212 11:08:46.716142 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7213 11:08:46.719372 [-4] AVG Duty = 4937%(X100)
7214 11:08:46.719470
7215 11:08:46.722807 CH0 CLK Duty spec in!! Max-Min= 187%
7216 11:08:46.726286 [DutyScan_Calibration_Flow] ====Done====
7217 11:08:46.726368
7218 11:08:46.729467 [DutyScan_Calibration_Flow] k_type=1
7219 11:08:46.746800
7220 11:08:46.746882 ==DQS 0 ==
7221 11:08:46.750000 Final DQS duty delay cell = 0
7222 11:08:46.753459 [0] MAX Duty = 5249%(X100), DQS PI = 38
7223 11:08:46.756463 [0] MIN Duty = 5093%(X100), DQS PI = 6
7224 11:08:46.759674 [0] AVG Duty = 5171%(X100)
7225 11:08:46.759756
7226 11:08:46.759821 ==DQS 1 ==
7227 11:08:46.763371 Final DQS duty delay cell = 0
7228 11:08:46.766738 [0] MAX Duty = 5156%(X100), DQS PI = 2
7229 11:08:46.769938 [0] MIN Duty = 4969%(X100), DQS PI = 10
7230 11:08:46.773297 [0] AVG Duty = 5062%(X100)
7231 11:08:46.773379
7232 11:08:46.776283 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7233 11:08:46.776365
7234 11:08:46.779637 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7235 11:08:46.782773 [DutyScan_Calibration_Flow] ====Done====
7236 11:08:46.782855
7237 11:08:46.785910 [DutyScan_Calibration_Flow] k_type=3
7238 11:08:46.803992
7239 11:08:46.804074 ==DQM 0 ==
7240 11:08:46.807233 Final DQM duty delay cell = 0
7241 11:08:46.810431 [0] MAX Duty = 5124%(X100), DQS PI = 22
7242 11:08:46.813975 [0] MIN Duty = 4844%(X100), DQS PI = 56
7243 11:08:46.816718 [0] AVG Duty = 4984%(X100)
7244 11:08:46.816800
7245 11:08:46.816865 ==DQM 1 ==
7246 11:08:46.820189 Final DQM duty delay cell = 0
7247 11:08:46.823344 [0] MAX Duty = 5000%(X100), DQS PI = 2
7248 11:08:46.826458 [0] MIN Duty = 4844%(X100), DQS PI = 14
7249 11:08:46.829782 [0] AVG Duty = 4922%(X100)
7250 11:08:46.829912
7251 11:08:46.833453 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7252 11:08:46.833575
7253 11:08:46.836852 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7254 11:08:46.840240 [DutyScan_Calibration_Flow] ====Done====
7255 11:08:46.840362
7256 11:08:46.842941 [DutyScan_Calibration_Flow] k_type=2
7257 11:08:46.860652
7258 11:08:46.860757 ==DQ 0 ==
7259 11:08:46.864114 Final DQ duty delay cell = 0
7260 11:08:46.867729 [0] MAX Duty = 5124%(X100), DQS PI = 20
7261 11:08:46.870574 [0] MIN Duty = 4938%(X100), DQS PI = 12
7262 11:08:46.873822 [0] AVG Duty = 5031%(X100)
7263 11:08:46.873904
7264 11:08:46.873968 ==DQ 1 ==
7265 11:08:46.877467 Final DQ duty delay cell = 0
7266 11:08:46.880588 [0] MAX Duty = 5187%(X100), DQS PI = 2
7267 11:08:46.884136 [0] MIN Duty = 4938%(X100), DQS PI = 12
7268 11:08:46.884219 [0] AVG Duty = 5062%(X100)
7269 11:08:46.887165
7270 11:08:46.890647 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7271 11:08:46.890777
7272 11:08:46.893762 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7273 11:08:46.897190 [DutyScan_Calibration_Flow] ====Done====
7274 11:08:46.897314 ==
7275 11:08:46.901021 Dram Type= 6, Freq= 0, CH_1, rank 0
7276 11:08:46.903597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7277 11:08:46.903723 ==
7278 11:08:46.907180 [Duty_Offset_Calibration]
7279 11:08:46.907305 B0:0 B1:-1 CA:3
7280 11:08:46.907431
7281 11:08:46.910115 [DutyScan_Calibration_Flow] k_type=0
7282 11:08:46.920533
7283 11:08:46.920657 ==CLK 0==
7284 11:08:46.923512 Final CLK duty delay cell = -4
7285 11:08:46.926728 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7286 11:08:46.929936 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7287 11:08:46.933307 [-4] AVG Duty = 4922%(X100)
7288 11:08:46.933435
7289 11:08:46.936937 CH1 CLK Duty spec in!! Max-Min= 156%
7290 11:08:46.940249 [DutyScan_Calibration_Flow] ====Done====
7291 11:08:46.940374
7292 11:08:46.943079 [DutyScan_Calibration_Flow] k_type=1
7293 11:08:46.959604
7294 11:08:46.959685 ==DQS 0 ==
7295 11:08:46.962525 Final DQS duty delay cell = 0
7296 11:08:46.966112 [0] MAX Duty = 5250%(X100), DQS PI = 30
7297 11:08:46.969563 [0] MIN Duty = 4907%(X100), DQS PI = 56
7298 11:08:46.972698 [0] AVG Duty = 5078%(X100)
7299 11:08:46.972779
7300 11:08:46.972844 ==DQS 1 ==
7301 11:08:46.975998 Final DQS duty delay cell = -4
7302 11:08:46.979504 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7303 11:08:46.982672 [-4] MIN Duty = 4844%(X100), DQS PI = 16
7304 11:08:46.985577 [-4] AVG Duty = 4922%(X100)
7305 11:08:46.985659
7306 11:08:46.988912 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7307 11:08:46.988995
7308 11:08:46.992521 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7309 11:08:46.995643 [DutyScan_Calibration_Flow] ====Done====
7310 11:08:46.995773
7311 11:08:46.998740 [DutyScan_Calibration_Flow] k_type=3
7312 11:08:47.016821
7313 11:08:47.016946 ==DQM 0 ==
7314 11:08:47.020097 Final DQM duty delay cell = 0
7315 11:08:47.023695 [0] MAX Duty = 5062%(X100), DQS PI = 30
7316 11:08:47.026791 [0] MIN Duty = 4782%(X100), DQS PI = 38
7317 11:08:47.029988 [0] AVG Duty = 4922%(X100)
7318 11:08:47.030069
7319 11:08:47.030134 ==DQM 1 ==
7320 11:08:47.033436 Final DQM duty delay cell = 0
7321 11:08:47.036495 [0] MAX Duty = 5000%(X100), DQS PI = 30
7322 11:08:47.039970 [0] MIN Duty = 4813%(X100), DQS PI = 12
7323 11:08:47.043280 [0] AVG Duty = 4906%(X100)
7324 11:08:47.043359
7325 11:08:47.046970 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7326 11:08:47.047050
7327 11:08:47.049590 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7328 11:08:47.052885 [DutyScan_Calibration_Flow] ====Done====
7329 11:08:47.052966
7330 11:08:47.056363 [DutyScan_Calibration_Flow] k_type=2
7331 11:08:47.073156
7332 11:08:47.073236 ==DQ 0 ==
7333 11:08:47.076470 Final DQ duty delay cell = -4
7334 11:08:47.079537 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7335 11:08:47.082752 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7336 11:08:47.086079 [-4] AVG Duty = 4891%(X100)
7337 11:08:47.086159
7338 11:08:47.086223 ==DQ 1 ==
7339 11:08:47.089593 Final DQ duty delay cell = 0
7340 11:08:47.092534 [0] MAX Duty = 5062%(X100), DQS PI = 32
7341 11:08:47.095861 [0] MIN Duty = 4875%(X100), DQS PI = 56
7342 11:08:47.099164 [0] AVG Duty = 4968%(X100)
7343 11:08:47.099244
7344 11:08:47.102425 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7345 11:08:47.102505
7346 11:08:47.106180 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7347 11:08:47.109243 [DutyScan_Calibration_Flow] ====Done====
7348 11:08:47.112385 nWR fixed to 30
7349 11:08:47.115670 [ModeRegInit_LP4] CH0 RK0
7350 11:08:47.115751 [ModeRegInit_LP4] CH0 RK1
7351 11:08:47.119124 [ModeRegInit_LP4] CH1 RK0
7352 11:08:47.122996 [ModeRegInit_LP4] CH1 RK1
7353 11:08:47.123076 match AC timing 5
7354 11:08:47.129259 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7355 11:08:47.132358 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7356 11:08:47.135479 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7357 11:08:47.142031 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7358 11:08:47.145180 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7359 11:08:47.148932 [MiockJmeterHQA]
7360 11:08:47.149015
7361 11:08:47.151845 [DramcMiockJmeter] u1RxGatingPI = 0
7362 11:08:47.151928 0 : 4255, 4027
7363 11:08:47.151995 4 : 4252, 4027
7364 11:08:47.155119 8 : 4363, 4137
7365 11:08:47.155203 12 : 4252, 4027
7366 11:08:47.158430 16 : 4363, 4137
7367 11:08:47.158514 20 : 4252, 4027
7368 11:08:47.161689 24 : 4363, 4137
7369 11:08:47.161778 28 : 4252, 4027
7370 11:08:47.161848 32 : 4252, 4027
7371 11:08:47.164978 36 : 4253, 4026
7372 11:08:47.165061 40 : 4361, 4138
7373 11:08:47.168562 44 : 4363, 4138
7374 11:08:47.168645 48 : 4250, 4027
7375 11:08:47.171519 52 : 4252, 4027
7376 11:08:47.171606 56 : 4253, 4027
7377 11:08:47.175301 60 : 4252, 4027
7378 11:08:47.175410 64 : 4255, 4029
7379 11:08:47.175478 68 : 4361, 4138
7380 11:08:47.178240 72 : 4250, 4027
7381 11:08:47.178323 76 : 4250, 4027
7382 11:08:47.181662 80 : 4250, 4027
7383 11:08:47.181746 84 : 4252, 4029
7384 11:08:47.185065 88 : 4250, 4027
7385 11:08:47.185149 92 : 4361, 4138
7386 11:08:47.188384 96 : 4360, 2536
7387 11:08:47.188467 100 : 4250, 0
7388 11:08:47.188534 104 : 4361, 0
7389 11:08:47.191418 108 : 4252, 0
7390 11:08:47.191502 112 : 4253, 0
7391 11:08:47.194474 116 : 4250, 0
7392 11:08:47.194557 120 : 4252, 0
7393 11:08:47.194624 124 : 4252, 0
7394 11:08:47.197724 128 : 4250, 0
7395 11:08:47.197807 132 : 4253, 0
7396 11:08:47.201076 136 : 4249, 0
7397 11:08:47.201159 140 : 4250, 0
7398 11:08:47.201225 144 : 4363, 0
7399 11:08:47.204770 148 : 4360, 0
7400 11:08:47.204853 152 : 4250, 0
7401 11:08:47.207609 156 : 4361, 0
7402 11:08:47.207702 160 : 4250, 0
7403 11:08:47.207768 164 : 4250, 0
7404 11:08:47.211307 168 : 4250, 0
7405 11:08:47.211430 172 : 4252, 0
7406 11:08:47.211498 176 : 4252, 0
7407 11:08:47.214447 180 : 4250, 0
7408 11:08:47.214530 184 : 4253, 0
7409 11:08:47.217730 188 : 4361, 0
7410 11:08:47.217814 192 : 4250, 0
7411 11:08:47.217880 196 : 4360, 0
7412 11:08:47.220774 200 : 4250, 0
7413 11:08:47.220857 204 : 4250, 0
7414 11:08:47.224076 208 : 4250, 0
7415 11:08:47.224159 212 : 4250, 0
7416 11:08:47.224225 216 : 4249, 0
7417 11:08:47.227278 220 : 4250, 744
7418 11:08:47.227371 224 : 4250, 4022
7419 11:08:47.230578 228 : 4249, 4027
7420 11:08:47.230662 232 : 4360, 4137
7421 11:08:47.234401 236 : 4250, 4027
7422 11:08:47.234484 240 : 4250, 4027
7423 11:08:47.238353 244 : 4252, 4027
7424 11:08:47.238437 248 : 4252, 4029
7425 11:08:47.240666 252 : 4250, 4026
7426 11:08:47.240749 256 : 4250, 4027
7427 11:08:47.243873 260 : 4361, 4138
7428 11:08:47.243956 264 : 4250, 4027
7429 11:08:47.246970 268 : 4250, 4027
7430 11:08:47.247081 272 : 4361, 4137
7431 11:08:47.247177 276 : 4250, 4027
7432 11:08:47.250835 280 : 4250, 4027
7433 11:08:47.250936 284 : 4363, 4140
7434 11:08:47.253865 288 : 4250, 4027
7435 11:08:47.253964 292 : 4250, 4027
7436 11:08:47.257270 296 : 4250, 4027
7437 11:08:47.257353 300 : 4252, 4029
7438 11:08:47.260666 304 : 4250, 4027
7439 11:08:47.260750 308 : 4250, 4027
7440 11:08:47.263396 312 : 4361, 4137
7441 11:08:47.263480 316 : 4250, 4027
7442 11:08:47.267032 320 : 4250, 4027
7443 11:08:47.267114 324 : 4361, 4137
7444 11:08:47.270255 328 : 4250, 4027
7445 11:08:47.270339 332 : 4250, 3912
7446 11:08:47.273732 336 : 4363, 1780
7447 11:08:47.273816
7448 11:08:47.273882 MIOCK jitter meter ch=0
7449 11:08:47.273944
7450 11:08:47.276775 1T = (336-100) = 236 dly cells
7451 11:08:47.283880 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7452 11:08:47.283963 ==
7453 11:08:47.286553 Dram Type= 6, Freq= 0, CH_0, rank 0
7454 11:08:47.290280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7455 11:08:47.290363 ==
7456 11:08:47.296751 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7457 11:08:47.299958 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7458 11:08:47.303703 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7459 11:08:47.309803 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7460 11:08:47.319839 [CA 0] Center 44 (14~74) winsize 61
7461 11:08:47.323121 [CA 1] Center 43 (13~74) winsize 62
7462 11:08:47.326120 [CA 2] Center 39 (10~68) winsize 59
7463 11:08:47.330118 [CA 3] Center 38 (9~68) winsize 60
7464 11:08:47.333438 [CA 4] Center 36 (7~66) winsize 60
7465 11:08:47.336139 [CA 5] Center 36 (6~66) winsize 61
7466 11:08:47.336222
7467 11:08:47.339718 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7468 11:08:47.339801
7469 11:08:47.346171 [CATrainingPosCal] consider 1 rank data
7470 11:08:47.346253 u2DelayCellTimex100 = 275/100 ps
7471 11:08:47.352378 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7472 11:08:47.355947 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7473 11:08:47.358988 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7474 11:08:47.362609 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7475 11:08:47.365627 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7476 11:08:47.369126 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7477 11:08:47.369208
7478 11:08:47.372186 CA PerBit enable=1, Macro0, CA PI delay=36
7479 11:08:47.372268
7480 11:08:47.375346 [CBTSetCACLKResult] CA Dly = 36
7481 11:08:47.378950 CS Dly: 11 (0~42)
7482 11:08:47.382014 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7483 11:08:47.385465 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7484 11:08:47.388657 ==
7485 11:08:47.388743 Dram Type= 6, Freq= 0, CH_0, rank 1
7486 11:08:47.395187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 11:08:47.395310 ==
7488 11:08:47.398297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 11:08:47.404651 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 11:08:47.408572 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 11:08:47.414746 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 11:08:47.423162 [CA 0] Center 43 (13~74) winsize 62
7493 11:08:47.426884 [CA 1] Center 43 (13~73) winsize 61
7494 11:08:47.429797 [CA 2] Center 38 (9~68) winsize 60
7495 11:08:47.433509 [CA 3] Center 38 (9~68) winsize 60
7496 11:08:47.436489 [CA 4] Center 36 (6~67) winsize 62
7497 11:08:47.439790 [CA 5] Center 36 (6~66) winsize 61
7498 11:08:47.439872
7499 11:08:47.442751 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7500 11:08:47.442832
7501 11:08:47.449735 [CATrainingPosCal] consider 2 rank data
7502 11:08:47.449848 u2DelayCellTimex100 = 275/100 ps
7503 11:08:47.456655 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7504 11:08:47.459740 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7505 11:08:47.462466 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7506 11:08:47.465622 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7507 11:08:47.469229 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7508 11:08:47.472385 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7509 11:08:47.472515
7510 11:08:47.476106 CA PerBit enable=1, Macro0, CA PI delay=36
7511 11:08:47.476230
7512 11:08:47.479205 [CBTSetCACLKResult] CA Dly = 36
7513 11:08:47.482713 CS Dly: 12 (0~44)
7514 11:08:47.485424 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 11:08:47.488981 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 11:08:47.489106
7517 11:08:47.492041 ----->DramcWriteLeveling(PI) begin...
7518 11:08:47.495300 ==
7519 11:08:47.498916 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 11:08:47.502070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 11:08:47.502194 ==
7522 11:08:47.505361 Write leveling (Byte 0): 35 => 35
7523 11:08:47.508780 Write leveling (Byte 1): 27 => 27
7524 11:08:47.511860 DramcWriteLeveling(PI) end<-----
7525 11:08:47.511984
7526 11:08:47.512099 ==
7527 11:08:47.515007 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 11:08:47.518364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 11:08:47.518488 ==
7530 11:08:47.521726 [Gating] SW mode calibration
7531 11:08:47.528206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7532 11:08:47.534902 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7533 11:08:47.538169 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7534 11:08:47.541216 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7535 11:08:47.547886 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7536 11:08:47.551309 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
7537 11:08:47.554803 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7538 11:08:47.561150 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
7539 11:08:47.564335 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 11:08:47.567812 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7541 11:08:47.574405 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7542 11:08:47.577756 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7543 11:08:47.580953 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7544 11:08:47.587656 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7545 11:08:47.590964 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7546 11:08:47.594115 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
7547 11:08:47.600521 1 5 24 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
7548 11:08:47.603678 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 11:08:47.607156 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 11:08:47.614024 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 11:08:47.616992 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7552 11:08:47.620651 1 6 12 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
7553 11:08:47.627074 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7554 11:08:47.630201 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7555 11:08:47.633978 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 11:08:47.640269 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 11:08:47.643345 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 11:08:47.647079 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 11:08:47.653433 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 11:08:47.656874 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7561 11:08:47.659745 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7562 11:08:47.666472 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7563 11:08:47.669754 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7564 11:08:47.673075 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 11:08:47.679589 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 11:08:47.682676 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 11:08:47.686383 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 11:08:47.692914 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 11:08:47.696153 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 11:08:47.699121 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 11:08:47.706189 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 11:08:47.709550 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 11:08:47.712564 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 11:08:47.719046 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 11:08:47.722490 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7576 11:08:47.726097 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7577 11:08:47.732206 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7578 11:08:47.735952 Total UI for P1: 0, mck2ui 16
7579 11:08:47.738626 best dqsien dly found for B0: ( 1, 9, 10)
7580 11:08:47.742032 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7581 11:08:47.745219 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7582 11:08:47.752504 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 11:08:47.755335 Total UI for P1: 0, mck2ui 16
7584 11:08:47.758741 best dqsien dly found for B1: ( 1, 9, 20)
7585 11:08:47.761791 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7586 11:08:47.765196 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7587 11:08:47.765277
7588 11:08:47.768443 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7589 11:08:47.771685 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7590 11:08:47.774941 [Gating] SW calibration Done
7591 11:08:47.775022 ==
7592 11:08:47.778564 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 11:08:47.781656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 11:08:47.781738 ==
7595 11:08:47.785166 RX Vref Scan: 0
7596 11:08:47.785247
7597 11:08:47.788350 RX Vref 0 -> 0, step: 1
7598 11:08:47.788430
7599 11:08:47.788495 RX Delay 0 -> 252, step: 8
7600 11:08:47.794571 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7601 11:08:47.798137 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7602 11:08:47.801118 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7603 11:08:47.804666 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7604 11:08:47.807952 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7605 11:08:47.814656 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7606 11:08:47.817861 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7607 11:08:47.821578 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7608 11:08:47.824298 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7609 11:08:47.830978 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7610 11:08:47.834324 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7611 11:08:47.837425 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7612 11:08:47.840875 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7613 11:08:47.844096 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7614 11:08:47.850752 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7615 11:08:47.854200 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7616 11:08:47.854283 ==
7617 11:08:47.857057 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 11:08:47.861172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 11:08:47.861256 ==
7620 11:08:47.863922 DQS Delay:
7621 11:08:47.864004 DQS0 = 0, DQS1 = 0
7622 11:08:47.864070 DQM Delay:
7623 11:08:47.867062 DQM0 = 131, DQM1 = 127
7624 11:08:47.867144 DQ Delay:
7625 11:08:47.870335 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7626 11:08:47.873625 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7627 11:08:47.880708 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7628 11:08:47.883327 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7629 11:08:47.883436
7630 11:08:47.883501
7631 11:08:47.883561 ==
7632 11:08:47.886912 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 11:08:47.890458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 11:08:47.890539 ==
7635 11:08:47.890603
7636 11:08:47.890663
7637 11:08:47.893447 TX Vref Scan disable
7638 11:08:47.896707 == TX Byte 0 ==
7639 11:08:47.900404 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7640 11:08:47.903587 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7641 11:08:47.906428 == TX Byte 1 ==
7642 11:08:47.910034 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7643 11:08:47.913003 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7644 11:08:47.913084 ==
7645 11:08:47.916227 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 11:08:47.923016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 11:08:47.923124 ==
7648 11:08:47.936196
7649 11:08:47.939617 TX Vref early break, caculate TX vref
7650 11:08:47.942844 TX Vref=16, minBit 1, minWin=21, winSum=369
7651 11:08:47.945950 TX Vref=18, minBit 0, minWin=23, winSum=383
7652 11:08:47.949470 TX Vref=20, minBit 1, minWin=23, winSum=391
7653 11:08:47.952742 TX Vref=22, minBit 7, minWin=23, winSum=403
7654 11:08:47.956287 TX Vref=24, minBit 1, minWin=24, winSum=409
7655 11:08:47.962352 TX Vref=26, minBit 1, minWin=25, winSum=417
7656 11:08:47.965699 TX Vref=28, minBit 1, minWin=25, winSum=420
7657 11:08:47.969266 TX Vref=30, minBit 2, minWin=25, winSum=419
7658 11:08:47.972565 TX Vref=32, minBit 2, minWin=24, winSum=409
7659 11:08:47.975676 TX Vref=34, minBit 7, minWin=23, winSum=399
7660 11:08:47.982460 TX Vref=36, minBit 2, minWin=23, winSum=388
7661 11:08:47.985534 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 28
7662 11:08:47.985615
7663 11:08:47.988685 Final TX Range 0 Vref 28
7664 11:08:47.988766
7665 11:08:47.988829 ==
7666 11:08:47.992551 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 11:08:47.995371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 11:08:47.998893 ==
7669 11:08:47.998973
7670 11:08:47.999036
7671 11:08:47.999095 TX Vref Scan disable
7672 11:08:48.005847 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7673 11:08:48.005927 == TX Byte 0 ==
7674 11:08:48.008930 u2DelayCellOfst[0]=10 cells (3 PI)
7675 11:08:48.012439 u2DelayCellOfst[1]=14 cells (4 PI)
7676 11:08:48.015454 u2DelayCellOfst[2]=10 cells (3 PI)
7677 11:08:48.018824 u2DelayCellOfst[3]=10 cells (3 PI)
7678 11:08:48.021797 u2DelayCellOfst[4]=7 cells (2 PI)
7679 11:08:48.024988 u2DelayCellOfst[5]=0 cells (0 PI)
7680 11:08:48.028828 u2DelayCellOfst[6]=14 cells (4 PI)
7681 11:08:48.031803 u2DelayCellOfst[7]=17 cells (5 PI)
7682 11:08:48.034978 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7683 11:08:48.038221 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7684 11:08:48.041847 == TX Byte 1 ==
7685 11:08:48.044929 u2DelayCellOfst[8]=0 cells (0 PI)
7686 11:08:48.048410 u2DelayCellOfst[9]=0 cells (0 PI)
7687 11:08:48.051717 u2DelayCellOfst[10]=7 cells (2 PI)
7688 11:08:48.054810 u2DelayCellOfst[11]=3 cells (1 PI)
7689 11:08:48.057891 u2DelayCellOfst[12]=10 cells (3 PI)
7690 11:08:48.061159 u2DelayCellOfst[13]=10 cells (3 PI)
7691 11:08:48.064497 u2DelayCellOfst[14]=14 cells (4 PI)
7692 11:08:48.069644 u2DelayCellOfst[15]=10 cells (3 PI)
7693 11:08:48.071538 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7694 11:08:48.074869 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7695 11:08:48.077758 DramC Write-DBI on
7696 11:08:48.077839 ==
7697 11:08:48.081219 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 11:08:48.084830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 11:08:48.084911 ==
7700 11:08:48.084976
7701 11:08:48.085036
7702 11:08:48.088230 TX Vref Scan disable
7703 11:08:48.091499 == TX Byte 0 ==
7704 11:08:48.094243 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7705 11:08:48.094323 == TX Byte 1 ==
7706 11:08:48.100953 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7707 11:08:48.101035 DramC Write-DBI off
7708 11:08:48.101098
7709 11:08:48.101158 [DATLAT]
7710 11:08:48.104346 Freq=1600, CH0 RK0
7711 11:08:48.104426
7712 11:08:48.107725 DATLAT Default: 0xf
7713 11:08:48.107805 0, 0xFFFF, sum = 0
7714 11:08:48.111093 1, 0xFFFF, sum = 0
7715 11:08:48.111175 2, 0xFFFF, sum = 0
7716 11:08:48.114279 3, 0xFFFF, sum = 0
7717 11:08:48.114361 4, 0xFFFF, sum = 0
7718 11:08:48.117206 5, 0xFFFF, sum = 0
7719 11:08:48.117288 6, 0xFFFF, sum = 0
7720 11:08:48.120636 7, 0xFFFF, sum = 0
7721 11:08:48.120718 8, 0xFFFF, sum = 0
7722 11:08:48.123830 9, 0xFFFF, sum = 0
7723 11:08:48.123911 10, 0xFFFF, sum = 0
7724 11:08:48.127384 11, 0xFFFF, sum = 0
7725 11:08:48.127480 12, 0xFFFF, sum = 0
7726 11:08:48.130655 13, 0xFFFF, sum = 0
7727 11:08:48.130737 14, 0x0, sum = 1
7728 11:08:48.134182 15, 0x0, sum = 2
7729 11:08:48.134263 16, 0x0, sum = 3
7730 11:08:48.137283 17, 0x0, sum = 4
7731 11:08:48.137365 best_step = 15
7732 11:08:48.137428
7733 11:08:48.137487 ==
7734 11:08:48.140556 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 11:08:48.146778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 11:08:48.146860 ==
7737 11:08:48.146924 RX Vref Scan: 1
7738 11:08:48.146984
7739 11:08:48.150414 Set Vref Range= 24 -> 127
7740 11:08:48.150495
7741 11:08:48.153620 RX Vref 24 -> 127, step: 1
7742 11:08:48.153701
7743 11:08:48.156659 RX Delay 19 -> 252, step: 4
7744 11:08:48.156740
7745 11:08:48.160031 Set Vref, RX VrefLevel [Byte0]: 24
7746 11:08:48.163541 [Byte1]: 24
7747 11:08:48.163622
7748 11:08:48.166800 Set Vref, RX VrefLevel [Byte0]: 25
7749 11:08:48.169898 [Byte1]: 25
7750 11:08:48.169979
7751 11:08:48.173219 Set Vref, RX VrefLevel [Byte0]: 26
7752 11:08:48.177181 [Byte1]: 26
7753 11:08:48.179753
7754 11:08:48.179833 Set Vref, RX VrefLevel [Byte0]: 27
7755 11:08:48.183492 [Byte1]: 27
7756 11:08:48.187340
7757 11:08:48.187464 Set Vref, RX VrefLevel [Byte0]: 28
7758 11:08:48.190858 [Byte1]: 28
7759 11:08:48.195266
7760 11:08:48.195346 Set Vref, RX VrefLevel [Byte0]: 29
7761 11:08:48.198205 [Byte1]: 29
7762 11:08:48.202561
7763 11:08:48.202641 Set Vref, RX VrefLevel [Byte0]: 30
7764 11:08:48.206324 [Byte1]: 30
7765 11:08:48.210104
7766 11:08:48.210183 Set Vref, RX VrefLevel [Byte0]: 31
7767 11:08:48.213474 [Byte1]: 31
7768 11:08:48.218191
7769 11:08:48.218272 Set Vref, RX VrefLevel [Byte0]: 32
7770 11:08:48.221429 [Byte1]: 32
7771 11:08:48.225202
7772 11:08:48.225285 Set Vref, RX VrefLevel [Byte0]: 33
7773 11:08:48.228541 [Byte1]: 33
7774 11:08:48.233485
7775 11:08:48.233565 Set Vref, RX VrefLevel [Byte0]: 34
7776 11:08:48.236497 [Byte1]: 34
7777 11:08:48.240723
7778 11:08:48.240804 Set Vref, RX VrefLevel [Byte0]: 35
7779 11:08:48.243869 [Byte1]: 35
7780 11:08:48.248177
7781 11:08:48.248257 Set Vref, RX VrefLevel [Byte0]: 36
7782 11:08:48.251180 [Byte1]: 36
7783 11:08:48.255784
7784 11:08:48.255864 Set Vref, RX VrefLevel [Byte0]: 37
7785 11:08:48.258974 [Byte1]: 37
7786 11:08:48.263223
7787 11:08:48.263304 Set Vref, RX VrefLevel [Byte0]: 38
7788 11:08:48.267345 [Byte1]: 38
7789 11:08:48.270904
7790 11:08:48.270984 Set Vref, RX VrefLevel [Byte0]: 39
7791 11:08:48.274309 [Byte1]: 39
7792 11:08:48.278692
7793 11:08:48.278772 Set Vref, RX VrefLevel [Byte0]: 40
7794 11:08:48.282417 [Byte1]: 40
7795 11:08:48.285900
7796 11:08:48.285980 Set Vref, RX VrefLevel [Byte0]: 41
7797 11:08:48.289226 [Byte1]: 41
7798 11:08:48.293895
7799 11:08:48.293975 Set Vref, RX VrefLevel [Byte0]: 42
7800 11:08:48.297092 [Byte1]: 42
7801 11:08:48.301113
7802 11:08:48.301195 Set Vref, RX VrefLevel [Byte0]: 43
7803 11:08:48.304738 [Byte1]: 43
7804 11:08:48.308527
7805 11:08:48.308608 Set Vref, RX VrefLevel [Byte0]: 44
7806 11:08:48.311853 [Byte1]: 44
7807 11:08:48.316267
7808 11:08:48.316349 Set Vref, RX VrefLevel [Byte0]: 45
7809 11:08:48.319698 [Byte1]: 45
7810 11:08:48.323776
7811 11:08:48.323858 Set Vref, RX VrefLevel [Byte0]: 46
7812 11:08:48.327105 [Byte1]: 46
7813 11:08:48.331330
7814 11:08:48.331432 Set Vref, RX VrefLevel [Byte0]: 47
7815 11:08:48.334676 [Byte1]: 47
7816 11:08:48.339136
7817 11:08:48.339217 Set Vref, RX VrefLevel [Byte0]: 48
7818 11:08:48.342108 [Byte1]: 48
7819 11:08:48.346398
7820 11:08:48.346483 Set Vref, RX VrefLevel [Byte0]: 49
7821 11:08:48.349839 [Byte1]: 49
7822 11:08:48.353950
7823 11:08:48.354031 Set Vref, RX VrefLevel [Byte0]: 50
7824 11:08:48.357236 [Byte1]: 50
7825 11:08:48.362072
7826 11:08:48.362154 Set Vref, RX VrefLevel [Byte0]: 51
7827 11:08:48.365332 [Byte1]: 51
7828 11:08:48.369542
7829 11:08:48.369624 Set Vref, RX VrefLevel [Byte0]: 52
7830 11:08:48.372696 [Byte1]: 52
7831 11:08:48.377047
7832 11:08:48.377129 Set Vref, RX VrefLevel [Byte0]: 53
7833 11:08:48.380474 [Byte1]: 53
7834 11:08:48.384514
7835 11:08:48.384596 Set Vref, RX VrefLevel [Byte0]: 54
7836 11:08:48.387396 [Byte1]: 54
7837 11:08:48.391892
7838 11:08:48.391974 Set Vref, RX VrefLevel [Byte0]: 55
7839 11:08:48.395055 [Byte1]: 55
7840 11:08:48.399339
7841 11:08:48.399444 Set Vref, RX VrefLevel [Byte0]: 56
7842 11:08:48.402649 [Byte1]: 56
7843 11:08:48.407007
7844 11:08:48.407089 Set Vref, RX VrefLevel [Byte0]: 57
7845 11:08:48.410504 [Byte1]: 57
7846 11:08:48.415031
7847 11:08:48.415112 Set Vref, RX VrefLevel [Byte0]: 58
7848 11:08:48.417893 [Byte1]: 58
7849 11:08:48.422282
7850 11:08:48.422363 Set Vref, RX VrefLevel [Byte0]: 59
7851 11:08:48.426033 [Byte1]: 59
7852 11:08:48.429664
7853 11:08:48.429744 Set Vref, RX VrefLevel [Byte0]: 60
7854 11:08:48.433230 [Byte1]: 60
7855 11:08:48.437163
7856 11:08:48.437243 Set Vref, RX VrefLevel [Byte0]: 61
7857 11:08:48.440792 [Byte1]: 61
7858 11:08:48.444874
7859 11:08:48.444955 Set Vref, RX VrefLevel [Byte0]: 62
7860 11:08:48.448330 [Byte1]: 62
7861 11:08:48.452501
7862 11:08:48.452581 Set Vref, RX VrefLevel [Byte0]: 63
7863 11:08:48.456070 [Byte1]: 63
7864 11:08:48.460215
7865 11:08:48.460295 Set Vref, RX VrefLevel [Byte0]: 64
7866 11:08:48.463640 [Byte1]: 64
7867 11:08:48.467977
7868 11:08:48.468057 Set Vref, RX VrefLevel [Byte0]: 65
7869 11:08:48.470956 [Byte1]: 65
7870 11:08:48.475289
7871 11:08:48.475395 Set Vref, RX VrefLevel [Byte0]: 66
7872 11:08:48.478897 [Byte1]: 66
7873 11:08:48.483008
7874 11:08:48.483088 Set Vref, RX VrefLevel [Byte0]: 67
7875 11:08:48.486398 [Byte1]: 67
7876 11:08:48.490717
7877 11:08:48.490797 Set Vref, RX VrefLevel [Byte0]: 68
7878 11:08:48.493611 [Byte1]: 68
7879 11:08:48.498218
7880 11:08:48.498299 Set Vref, RX VrefLevel [Byte0]: 69
7881 11:08:48.501446 [Byte1]: 69
7882 11:08:48.505592
7883 11:08:48.505676 Set Vref, RX VrefLevel [Byte0]: 70
7884 11:08:48.509123 [Byte1]: 70
7885 11:08:48.513196
7886 11:08:48.513276 Set Vref, RX VrefLevel [Byte0]: 71
7887 11:08:48.516606 [Byte1]: 71
7888 11:08:48.520869
7889 11:08:48.520950 Set Vref, RX VrefLevel [Byte0]: 72
7890 11:08:48.524207 [Byte1]: 72
7891 11:08:48.528706
7892 11:08:48.528787 Set Vref, RX VrefLevel [Byte0]: 73
7893 11:08:48.531607 [Byte1]: 73
7894 11:08:48.536204
7895 11:08:48.536284 Set Vref, RX VrefLevel [Byte0]: 74
7896 11:08:48.539275 [Byte1]: 74
7897 11:08:48.543342
7898 11:08:48.543461 Set Vref, RX VrefLevel [Byte0]: 75
7899 11:08:48.546911 [Byte1]: 75
7900 11:08:48.551174
7901 11:08:48.551255 Set Vref, RX VrefLevel [Byte0]: 76
7902 11:08:48.554171 [Byte1]: 76
7903 11:08:48.558538
7904 11:08:48.558618 Final RX Vref Byte 0 = 56 to rank0
7905 11:08:48.562118 Final RX Vref Byte 1 = 60 to rank0
7906 11:08:48.565250 Final RX Vref Byte 0 = 56 to rank1
7907 11:08:48.568603 Final RX Vref Byte 1 = 60 to rank1==
7908 11:08:48.572051 Dram Type= 6, Freq= 0, CH_0, rank 0
7909 11:08:48.578410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7910 11:08:48.578494 ==
7911 11:08:48.578559 DQS Delay:
7912 11:08:48.581731 DQS0 = 0, DQS1 = 0
7913 11:08:48.581813 DQM Delay:
7914 11:08:48.581878 DQM0 = 129, DQM1 = 123
7915 11:08:48.585188 DQ Delay:
7916 11:08:48.587991 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7917 11:08:48.591196 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =134
7918 11:08:48.594800 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7919 11:08:48.597846 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =130
7920 11:08:48.597928
7921 11:08:48.597993
7922 11:08:48.598053
7923 11:08:48.601318 [DramC_TX_OE_Calibration] TA2
7924 11:08:48.604589 Original DQ_B0 (3 6) =30, OEN = 27
7925 11:08:48.607851 Original DQ_B1 (3 6) =30, OEN = 27
7926 11:08:48.611334 24, 0x0, End_B0=24 End_B1=24
7927 11:08:48.614413 25, 0x0, End_B0=25 End_B1=25
7928 11:08:48.614497 26, 0x0, End_B0=26 End_B1=26
7929 11:08:48.617884 27, 0x0, End_B0=27 End_B1=27
7930 11:08:48.621090 28, 0x0, End_B0=28 End_B1=28
7931 11:08:48.624376 29, 0x0, End_B0=29 End_B1=29
7932 11:08:48.624460 30, 0x0, End_B0=30 End_B1=30
7933 11:08:48.628006 31, 0x4141, End_B0=30 End_B1=30
7934 11:08:48.630860 Byte0 end_step=30 best_step=27
7935 11:08:48.634199 Byte1 end_step=30 best_step=27
7936 11:08:48.637345 Byte0 TX OE(2T, 0.5T) = (3, 3)
7937 11:08:48.640769 Byte1 TX OE(2T, 0.5T) = (3, 3)
7938 11:08:48.640852
7939 11:08:48.640917
7940 11:08:48.646976 [DQSOSCAuto] RK0, (LSB)MR18= 0x1512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
7941 11:08:48.650518 CH0 RK0: MR19=303, MR18=1512
7942 11:08:48.657117 CH0_RK0: MR19=0x303, MR18=0x1512, DQSOSC=399, MR23=63, INC=23, DEC=15
7943 11:08:48.657200
7944 11:08:48.660346 ----->DramcWriteLeveling(PI) begin...
7945 11:08:48.660429 ==
7946 11:08:48.664066 Dram Type= 6, Freq= 0, CH_0, rank 1
7947 11:08:48.667195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7948 11:08:48.669750 ==
7949 11:08:48.669833 Write leveling (Byte 0): 34 => 34
7950 11:08:48.673512 Write leveling (Byte 1): 25 => 25
7951 11:08:48.676803 DramcWriteLeveling(PI) end<-----
7952 11:08:48.676885
7953 11:08:48.676949 ==
7954 11:08:48.679866 Dram Type= 6, Freq= 0, CH_0, rank 1
7955 11:08:48.686199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7956 11:08:48.686283 ==
7957 11:08:48.689830 [Gating] SW mode calibration
7958 11:08:48.696103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7959 11:08:48.699487 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7960 11:08:48.706585 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7961 11:08:48.709268 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7962 11:08:48.713181 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7963 11:08:48.719215 1 4 12 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
7964 11:08:48.722588 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7965 11:08:48.726492 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7966 11:08:48.732644 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7967 11:08:48.736169 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7968 11:08:48.739135 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7969 11:08:48.746026 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7970 11:08:48.749033 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7971 11:08:48.752697 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7972 11:08:48.759148 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7973 11:08:48.762359 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
7974 11:08:48.765399 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7975 11:08:48.771986 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7976 11:08:48.775536 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7977 11:08:48.778947 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7978 11:08:48.785042 1 6 8 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
7979 11:08:48.788660 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7980 11:08:48.791881 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7981 11:08:48.798422 1 6 20 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
7982 11:08:48.801963 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 11:08:48.805004 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 11:08:48.811518 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 11:08:48.814797 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 11:08:48.818062 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7987 11:08:48.824859 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7988 11:08:48.828266 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7989 11:08:48.831837 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7990 11:08:48.837800 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7991 11:08:48.840911 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 11:08:48.844477 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 11:08:48.851184 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 11:08:48.854195 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 11:08:48.857346 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 11:08:48.864285 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 11:08:48.867644 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 11:08:48.870464 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 11:08:48.877522 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 11:08:48.880671 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 11:08:48.883775 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8002 11:08:48.890438 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8003 11:08:48.893867 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8004 11:08:48.896945 Total UI for P1: 0, mck2ui 16
8005 11:08:48.900251 best dqsien dly found for B0: ( 1, 9, 6)
8006 11:08:48.904347 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8007 11:08:48.910373 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8008 11:08:48.913558 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 11:08:48.916976 Total UI for P1: 0, mck2ui 16
8010 11:08:48.920596 best dqsien dly found for B1: ( 1, 9, 20)
8011 11:08:48.923346 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8012 11:08:48.927350 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8013 11:08:48.927466
8014 11:08:48.930037 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8015 11:08:48.933483 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8016 11:08:48.936561 [Gating] SW calibration Done
8017 11:08:48.936643 ==
8018 11:08:48.940626 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 11:08:48.947054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 11:08:48.947137 ==
8021 11:08:48.947202 RX Vref Scan: 0
8022 11:08:48.947263
8023 11:08:48.949566 RX Vref 0 -> 0, step: 1
8024 11:08:48.949673
8025 11:08:48.953136 RX Delay 0 -> 252, step: 8
8026 11:08:48.956580 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8027 11:08:48.959714 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8028 11:08:48.963192 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8029 11:08:48.966553 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8030 11:08:48.973347 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8031 11:08:48.976400 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8032 11:08:48.979894 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8033 11:08:48.982823 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8034 11:08:48.986221 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8035 11:08:48.992791 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8036 11:08:48.995982 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8037 11:08:48.999251 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8038 11:08:49.002676 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8039 11:08:49.009382 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8040 11:08:49.012451 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8041 11:08:49.016516 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8042 11:08:49.016597 ==
8043 11:08:49.018982 Dram Type= 6, Freq= 0, CH_0, rank 1
8044 11:08:49.022202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8045 11:08:49.022298 ==
8046 11:08:49.025492 DQS Delay:
8047 11:08:49.025590 DQS0 = 0, DQS1 = 0
8048 11:08:49.028763 DQM Delay:
8049 11:08:49.028845 DQM0 = 131, DQM1 = 128
8050 11:08:49.032247 DQ Delay:
8051 11:08:49.035656 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8052 11:08:49.038900 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8053 11:08:49.041954 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8054 11:08:49.045391 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8055 11:08:49.045474
8056 11:08:49.045553
8057 11:08:49.045616 ==
8058 11:08:49.048631 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 11:08:49.052036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 11:08:49.052117 ==
8061 11:08:49.055177
8062 11:08:49.055257
8063 11:08:49.055320 TX Vref Scan disable
8064 11:08:49.058781 == TX Byte 0 ==
8065 11:08:49.061871 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8066 11:08:49.065285 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8067 11:08:49.068201 == TX Byte 1 ==
8068 11:08:49.071869 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8069 11:08:49.074803 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8070 11:08:49.078322 ==
8071 11:08:49.078402 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 11:08:49.084559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 11:08:49.084640 ==
8074 11:08:49.099003
8075 11:08:49.102186 TX Vref early break, caculate TX vref
8076 11:08:49.106049 TX Vref=16, minBit 9, minWin=22, winSum=380
8077 11:08:49.108759 TX Vref=18, minBit 14, minWin=23, winSum=388
8078 11:08:49.112460 TX Vref=20, minBit 2, minWin=24, winSum=395
8079 11:08:49.115303 TX Vref=22, minBit 2, minWin=24, winSum=401
8080 11:08:49.122083 TX Vref=24, minBit 3, minWin=25, winSum=413
8081 11:08:49.125159 TX Vref=26, minBit 4, minWin=25, winSum=412
8082 11:08:49.128755 TX Vref=28, minBit 4, minWin=25, winSum=419
8083 11:08:49.131603 TX Vref=30, minBit 1, minWin=25, winSum=409
8084 11:08:49.135128 TX Vref=32, minBit 1, minWin=25, winSum=409
8085 11:08:49.138686 TX Vref=34, minBit 0, minWin=24, winSum=398
8086 11:08:49.144876 TX Vref=36, minBit 0, minWin=24, winSum=385
8087 11:08:49.148354 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 28
8088 11:08:49.148435
8089 11:08:49.151474 Final TX Range 0 Vref 28
8090 11:08:49.151555
8091 11:08:49.151619 ==
8092 11:08:49.154746 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 11:08:49.161535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 11:08:49.161616 ==
8095 11:08:49.161680
8096 11:08:49.161739
8097 11:08:49.161797 TX Vref Scan disable
8098 11:08:49.168462 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8099 11:08:49.168544 == TX Byte 0 ==
8100 11:08:49.172235 u2DelayCellOfst[0]=10 cells (3 PI)
8101 11:08:49.175247 u2DelayCellOfst[1]=14 cells (4 PI)
8102 11:08:49.178836 u2DelayCellOfst[2]=7 cells (2 PI)
8103 11:08:49.181459 u2DelayCellOfst[3]=10 cells (3 PI)
8104 11:08:49.184751 u2DelayCellOfst[4]=7 cells (2 PI)
8105 11:08:49.187887 u2DelayCellOfst[5]=0 cells (0 PI)
8106 11:08:49.191777 u2DelayCellOfst[6]=14 cells (4 PI)
8107 11:08:49.194884 u2DelayCellOfst[7]=14 cells (4 PI)
8108 11:08:49.197997 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8109 11:08:49.201277 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8110 11:08:49.204836 == TX Byte 1 ==
8111 11:08:49.207760 u2DelayCellOfst[8]=0 cells (0 PI)
8112 11:08:49.211211 u2DelayCellOfst[9]=0 cells (0 PI)
8113 11:08:49.214689 u2DelayCellOfst[10]=7 cells (2 PI)
8114 11:08:49.217720 u2DelayCellOfst[11]=3 cells (1 PI)
8115 11:08:49.220917 u2DelayCellOfst[12]=7 cells (2 PI)
8116 11:08:49.223960 u2DelayCellOfst[13]=7 cells (2 PI)
8117 11:08:49.227781 u2DelayCellOfst[14]=14 cells (4 PI)
8118 11:08:49.227862 u2DelayCellOfst[15]=10 cells (3 PI)
8119 11:08:49.234120 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8120 11:08:49.237543 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8121 11:08:49.240390 DramC Write-DBI on
8122 11:08:49.240510 ==
8123 11:08:49.243844 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 11:08:49.247335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 11:08:49.247464 ==
8126 11:08:49.247575
8127 11:08:49.247684
8128 11:08:49.250331 TX Vref Scan disable
8129 11:08:49.250452 == TX Byte 0 ==
8130 11:08:49.256936 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8131 11:08:49.257056 == TX Byte 1 ==
8132 11:08:49.263694 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8133 11:08:49.263815 DramC Write-DBI off
8134 11:08:49.263927
8135 11:08:49.264037 [DATLAT]
8136 11:08:49.267393 Freq=1600, CH0 RK1
8137 11:08:49.267528
8138 11:08:49.270212 DATLAT Default: 0xf
8139 11:08:49.270330 0, 0xFFFF, sum = 0
8140 11:08:49.273769 1, 0xFFFF, sum = 0
8141 11:08:49.273892 2, 0xFFFF, sum = 0
8142 11:08:49.277039 3, 0xFFFF, sum = 0
8143 11:08:49.277163 4, 0xFFFF, sum = 0
8144 11:08:49.280058 5, 0xFFFF, sum = 0
8145 11:08:49.280182 6, 0xFFFF, sum = 0
8146 11:08:49.283510 7, 0xFFFF, sum = 0
8147 11:08:49.283629 8, 0xFFFF, sum = 0
8148 11:08:49.286718 9, 0xFFFF, sum = 0
8149 11:08:49.286842 10, 0xFFFF, sum = 0
8150 11:08:49.289883 11, 0xFFFF, sum = 0
8151 11:08:49.290006 12, 0xFFFF, sum = 0
8152 11:08:49.293472 13, 0xFFFF, sum = 0
8153 11:08:49.293594 14, 0x0, sum = 1
8154 11:08:49.296294 15, 0x0, sum = 2
8155 11:08:49.296424 16, 0x0, sum = 3
8156 11:08:49.299924 17, 0x0, sum = 4
8157 11:08:49.300046 best_step = 15
8158 11:08:49.300154
8159 11:08:49.300263 ==
8160 11:08:49.303680 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 11:08:49.309844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 11:08:49.309931 ==
8163 11:08:49.309997 RX Vref Scan: 0
8164 11:08:49.310057
8165 11:08:49.313228 RX Vref 0 -> 0, step: 1
8166 11:08:49.313310
8167 11:08:49.316405 RX Delay 19 -> 252, step: 4
8168 11:08:49.319787 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8169 11:08:49.323316 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8170 11:08:49.329470 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8171 11:08:49.332543 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8172 11:08:49.335986 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8173 11:08:49.339682 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8174 11:08:49.342722 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8175 11:08:49.349041 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8176 11:08:49.352574 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8177 11:08:49.356124 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8178 11:08:49.359131 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8179 11:08:49.362836 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8180 11:08:49.370959 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8181 11:08:49.372550 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8182 11:08:49.375493 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8183 11:08:49.379515 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8184 11:08:49.379597 ==
8185 11:08:49.382188 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 11:08:49.388785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 11:08:49.388868 ==
8188 11:08:49.388933 DQS Delay:
8189 11:08:49.392016 DQS0 = 0, DQS1 = 0
8190 11:08:49.392098 DQM Delay:
8191 11:08:49.395551 DQM0 = 128, DQM1 = 124
8192 11:08:49.395633 DQ Delay:
8193 11:08:49.399018 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8194 11:08:49.401927 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =134
8195 11:08:49.405258 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8196 11:08:49.408673 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8197 11:08:49.408754
8198 11:08:49.408819
8199 11:08:49.408879
8200 11:08:49.411459 [DramC_TX_OE_Calibration] TA2
8201 11:08:49.414805 Original DQ_B0 (3 6) =30, OEN = 27
8202 11:08:49.418444 Original DQ_B1 (3 6) =30, OEN = 27
8203 11:08:49.421689 24, 0x0, End_B0=24 End_B1=24
8204 11:08:49.424637 25, 0x0, End_B0=25 End_B1=25
8205 11:08:49.424721 26, 0x0, End_B0=26 End_B1=26
8206 11:08:49.427888 27, 0x0, End_B0=27 End_B1=27
8207 11:08:49.431320 28, 0x0, End_B0=28 End_B1=28
8208 11:08:49.434571 29, 0x0, End_B0=29 End_B1=29
8209 11:08:49.438044 30, 0x0, End_B0=30 End_B1=30
8210 11:08:49.438127 31, 0x4141, End_B0=30 End_B1=30
8211 11:08:49.441064 Byte0 end_step=30 best_step=27
8212 11:08:49.444275 Byte1 end_step=30 best_step=27
8213 11:08:49.447641 Byte0 TX OE(2T, 0.5T) = (3, 3)
8214 11:08:49.451358 Byte1 TX OE(2T, 0.5T) = (3, 3)
8215 11:08:49.451504
8216 11:08:49.451597
8217 11:08:49.457988 [DQSOSCAuto] RK1, (LSB)MR18= 0x1311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8218 11:08:49.460766 CH0 RK1: MR19=303, MR18=1311
8219 11:08:49.467351 CH0_RK1: MR19=0x303, MR18=0x1311, DQSOSC=400, MR23=63, INC=23, DEC=15
8220 11:08:49.470589 [RxdqsGatingPostProcess] freq 1600
8221 11:08:49.477444 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8222 11:08:49.480946 best DQS0 dly(2T, 0.5T) = (1, 1)
8223 11:08:49.483826 best DQS1 dly(2T, 0.5T) = (1, 1)
8224 11:08:49.487189 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8225 11:08:49.487270 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8226 11:08:49.490270 best DQS0 dly(2T, 0.5T) = (1, 1)
8227 11:08:49.493537 best DQS1 dly(2T, 0.5T) = (1, 1)
8228 11:08:49.497706 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8229 11:08:49.500677 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8230 11:08:49.503778 Pre-setting of DQS Precalculation
8231 11:08:49.510304 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8232 11:08:49.510385 ==
8233 11:08:49.513381 Dram Type= 6, Freq= 0, CH_1, rank 0
8234 11:08:49.516684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 11:08:49.516765 ==
8236 11:08:49.523260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8237 11:08:49.526486 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8238 11:08:49.530131 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8239 11:08:49.536484 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8240 11:08:49.545994 [CA 0] Center 42 (13~72) winsize 60
8241 11:08:49.548480 [CA 1] Center 42 (12~72) winsize 61
8242 11:08:49.551835 [CA 2] Center 38 (9~67) winsize 59
8243 11:08:49.555289 [CA 3] Center 37 (8~66) winsize 59
8244 11:08:49.558517 [CA 4] Center 38 (8~68) winsize 61
8245 11:08:49.561785 [CA 5] Center 36 (7~66) winsize 60
8246 11:08:49.561866
8247 11:08:49.565120 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8248 11:08:49.565201
8249 11:08:49.572090 [CATrainingPosCal] consider 1 rank data
8250 11:08:49.572171 u2DelayCellTimex100 = 275/100 ps
8251 11:08:49.578466 CA0 delay=42 (13~72),Diff = 6 PI (21 cell)
8252 11:08:49.581917 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8253 11:08:49.584948 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8254 11:08:49.588347 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8255 11:08:49.591282 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8256 11:08:49.594478 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8257 11:08:49.594559
8258 11:08:49.598007 CA PerBit enable=1, Macro0, CA PI delay=36
8259 11:08:49.598088
8260 11:08:49.601224 [CBTSetCACLKResult] CA Dly = 36
8261 11:08:49.604414 CS Dly: 7 (0~38)
8262 11:08:49.607900 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8263 11:08:49.611757 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8264 11:08:49.611838 ==
8265 11:08:49.614347 Dram Type= 6, Freq= 0, CH_1, rank 1
8266 11:08:49.621049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8267 11:08:49.621131 ==
8268 11:08:49.624360 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8269 11:08:49.631119 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8270 11:08:49.634027 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8271 11:08:49.640518 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8272 11:08:49.648485 [CA 0] Center 41 (11~72) winsize 62
8273 11:08:49.651704 [CA 1] Center 42 (13~72) winsize 60
8274 11:08:49.655211 [CA 2] Center 38 (9~68) winsize 60
8275 11:08:49.658517 [CA 3] Center 36 (7~66) winsize 60
8276 11:08:49.662010 [CA 4] Center 37 (7~68) winsize 62
8277 11:08:49.664894 [CA 5] Center 37 (8~66) winsize 59
8278 11:08:49.665007
8279 11:08:49.668680 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8280 11:08:49.668761
8281 11:08:49.671802 [CATrainingPosCal] consider 2 rank data
8282 11:08:49.675271 u2DelayCellTimex100 = 275/100 ps
8283 11:08:49.681296 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8284 11:08:49.684927 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8285 11:08:49.687763 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8286 11:08:49.691495 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8287 11:08:49.694618 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8288 11:08:49.697721 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8289 11:08:49.697830
8290 11:08:49.701067 CA PerBit enable=1, Macro0, CA PI delay=37
8291 11:08:49.701149
8292 11:08:49.704567 [CBTSetCACLKResult] CA Dly = 37
8293 11:08:49.707765 CS Dly: 9 (0~42)
8294 11:08:49.710813 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8295 11:08:49.714088 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8296 11:08:49.714170
8297 11:08:49.717753 ----->DramcWriteLeveling(PI) begin...
8298 11:08:49.717836 ==
8299 11:08:49.720952 Dram Type= 6, Freq= 0, CH_1, rank 0
8300 11:08:49.727684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 11:08:49.727765 ==
8302 11:08:49.730707 Write leveling (Byte 0): 23 => 23
8303 11:08:49.733921 Write leveling (Byte 1): 27 => 27
8304 11:08:49.737464 DramcWriteLeveling(PI) end<-----
8305 11:08:49.737544
8306 11:08:49.737606 ==
8307 11:08:49.740569 Dram Type= 6, Freq= 0, CH_1, rank 0
8308 11:08:49.743933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 11:08:49.744043 ==
8310 11:08:49.747181 [Gating] SW mode calibration
8311 11:08:49.753613 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8312 11:08:49.760210 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8313 11:08:49.763358 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 11:08:49.766962 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8315 11:08:49.773473 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8316 11:08:49.777214 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
8317 11:08:49.779817 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 11:08:49.786496 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 11:08:49.790315 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 11:08:49.793236 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 11:08:49.799967 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 11:08:49.803034 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 11:08:49.806480 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8324 11:08:49.812922 1 5 12 | B1->B0 | 3333 2525 | 1 0 | (1 0) (1 0)
8325 11:08:49.815850 1 5 16 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
8326 11:08:49.819052 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 11:08:49.826146 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 11:08:49.829184 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 11:08:49.832315 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 11:08:49.839079 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 11:08:49.842529 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 11:08:49.845841 1 6 12 | B1->B0 | 2525 4343 | 0 0 | (0 0) (0 0)
8333 11:08:49.852049 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8334 11:08:49.855855 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 11:08:49.859146 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 11:08:49.865340 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 11:08:49.869393 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 11:08:49.872443 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 11:08:49.878923 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 11:08:49.881860 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8341 11:08:49.885383 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8342 11:08:49.892131 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 11:08:49.895765 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 11:08:49.898932 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 11:08:49.904842 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 11:08:49.908323 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 11:08:49.911890 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 11:08:49.917969 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 11:08:49.921607 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 11:08:49.924614 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 11:08:49.931159 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 11:08:49.934817 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 11:08:49.937887 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 11:08:49.944496 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 11:08:49.948483 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8356 11:08:49.951054 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8357 11:08:49.954513 Total UI for P1: 0, mck2ui 16
8358 11:08:49.957620 best dqsien dly found for B0: ( 1, 9, 8)
8359 11:08:49.964499 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8360 11:08:49.967796 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 11:08:49.971126 Total UI for P1: 0, mck2ui 16
8362 11:08:49.974234 best dqsien dly found for B1: ( 1, 9, 14)
8363 11:08:49.977489 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8364 11:08:49.981644 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8365 11:08:49.981726
8366 11:08:49.984190 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8367 11:08:49.987325 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8368 11:08:49.990937 [Gating] SW calibration Done
8369 11:08:49.991044 ==
8370 11:08:49.994222 Dram Type= 6, Freq= 0, CH_1, rank 0
8371 11:08:49.997323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8372 11:08:50.000432 ==
8373 11:08:50.000514 RX Vref Scan: 0
8374 11:08:50.000580
8375 11:08:50.003931 RX Vref 0 -> 0, step: 1
8376 11:08:50.004012
8377 11:08:50.007024 RX Delay 0 -> 252, step: 8
8378 11:08:50.010414 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8379 11:08:50.014041 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8380 11:08:50.017447 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8381 11:08:50.020573 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8382 11:08:50.026882 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8383 11:08:50.030263 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8384 11:08:50.033704 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8385 11:08:50.036660 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8386 11:08:50.040175 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8387 11:08:50.046751 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8388 11:08:50.049862 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8389 11:08:50.053322 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8390 11:08:50.056463 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8391 11:08:50.059623 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8392 11:08:50.066563 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8393 11:08:50.069682 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8394 11:08:50.069765 ==
8395 11:08:50.072801 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 11:08:50.076670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 11:08:50.076753 ==
8398 11:08:50.080002 DQS Delay:
8399 11:08:50.080084 DQS0 = 0, DQS1 = 0
8400 11:08:50.083186 DQM Delay:
8401 11:08:50.083267 DQM0 = 134, DQM1 = 131
8402 11:08:50.083332 DQ Delay:
8403 11:08:50.089336 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8404 11:08:50.092718 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8405 11:08:50.096098 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8406 11:08:50.099712 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8407 11:08:50.099795
8408 11:08:50.099860
8409 11:08:50.099920 ==
8410 11:08:50.102813 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 11:08:50.106054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 11:08:50.106136 ==
8413 11:08:50.106200
8414 11:08:50.106259
8415 11:08:50.109265 TX Vref Scan disable
8416 11:08:50.112573 == TX Byte 0 ==
8417 11:08:50.115831 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8418 11:08:50.118920 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8419 11:08:50.122219 == TX Byte 1 ==
8420 11:08:50.125673 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8421 11:08:50.128798 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8422 11:08:50.128879 ==
8423 11:08:50.132118 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 11:08:50.138791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 11:08:50.138872 ==
8426 11:08:50.151628
8427 11:08:50.154913 TX Vref early break, caculate TX vref
8428 11:08:50.158572 TX Vref=16, minBit 8, minWin=21, winSum=370
8429 11:08:50.161708 TX Vref=18, minBit 8, minWin=22, winSum=378
8430 11:08:50.164675 TX Vref=20, minBit 8, minWin=23, winSum=389
8431 11:08:50.167807 TX Vref=22, minBit 9, minWin=23, winSum=396
8432 11:08:50.171227 TX Vref=24, minBit 8, minWin=24, winSum=407
8433 11:08:50.177530 TX Vref=26, minBit 0, minWin=25, winSum=416
8434 11:08:50.181175 TX Vref=28, minBit 0, minWin=25, winSum=417
8435 11:08:50.184365 TX Vref=30, minBit 0, minWin=25, winSum=416
8436 11:08:50.187686 TX Vref=32, minBit 8, minWin=24, winSum=407
8437 11:08:50.190718 TX Vref=34, minBit 0, minWin=23, winSum=396
8438 11:08:50.197412 TX Vref=36, minBit 9, minWin=22, winSum=381
8439 11:08:50.200812 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8440 11:08:50.200894
8441 11:08:50.204215 Final TX Range 0 Vref 28
8442 11:08:50.204295
8443 11:08:50.204359 ==
8444 11:08:50.207746 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 11:08:50.210767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 11:08:50.213975 ==
8447 11:08:50.214055
8448 11:08:50.214119
8449 11:08:50.214179 TX Vref Scan disable
8450 11:08:50.220700 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8451 11:08:50.220781 == TX Byte 0 ==
8452 11:08:50.224493 u2DelayCellOfst[0]=10 cells (3 PI)
8453 11:08:50.227912 u2DelayCellOfst[1]=10 cells (3 PI)
8454 11:08:50.230939 u2DelayCellOfst[2]=0 cells (0 PI)
8455 11:08:50.234281 u2DelayCellOfst[3]=3 cells (1 PI)
8456 11:08:50.237796 u2DelayCellOfst[4]=7 cells (2 PI)
8457 11:08:50.241032 u2DelayCellOfst[5]=14 cells (4 PI)
8458 11:08:50.244138 u2DelayCellOfst[6]=14 cells (4 PI)
8459 11:08:50.247472 u2DelayCellOfst[7]=3 cells (1 PI)
8460 11:08:50.251245 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8461 11:08:50.253602 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8462 11:08:50.257185 == TX Byte 1 ==
8463 11:08:50.260218 u2DelayCellOfst[8]=0 cells (0 PI)
8464 11:08:50.263545 u2DelayCellOfst[9]=3 cells (1 PI)
8465 11:08:50.267179 u2DelayCellOfst[10]=14 cells (4 PI)
8466 11:08:50.270435 u2DelayCellOfst[11]=3 cells (1 PI)
8467 11:08:50.273507 u2DelayCellOfst[12]=14 cells (4 PI)
8468 11:08:50.276627 u2DelayCellOfst[13]=14 cells (4 PI)
8469 11:08:50.280573 u2DelayCellOfst[14]=17 cells (5 PI)
8470 11:08:50.280655 u2DelayCellOfst[15]=17 cells (5 PI)
8471 11:08:50.286553 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8472 11:08:50.290067 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8473 11:08:50.293060 DramC Write-DBI on
8474 11:08:50.293141 ==
8475 11:08:50.296221 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 11:08:50.299560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 11:08:50.299641 ==
8478 11:08:50.299706
8479 11:08:50.299765
8480 11:08:50.302887 TX Vref Scan disable
8481 11:08:50.302994 == TX Byte 0 ==
8482 11:08:50.309540 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8483 11:08:50.309622 == TX Byte 1 ==
8484 11:08:50.316166 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8485 11:08:50.316247 DramC Write-DBI off
8486 11:08:50.316311
8487 11:08:50.316370 [DATLAT]
8488 11:08:50.319695 Freq=1600, CH1 RK0
8489 11:08:50.319776
8490 11:08:50.323072 DATLAT Default: 0xf
8491 11:08:50.323198 0, 0xFFFF, sum = 0
8492 11:08:50.325992 1, 0xFFFF, sum = 0
8493 11:08:50.326115 2, 0xFFFF, sum = 0
8494 11:08:50.328962 3, 0xFFFF, sum = 0
8495 11:08:50.329087 4, 0xFFFF, sum = 0
8496 11:08:50.332698 5, 0xFFFF, sum = 0
8497 11:08:50.332782 6, 0xFFFF, sum = 0
8498 11:08:50.336658 7, 0xFFFF, sum = 0
8499 11:08:50.336740 8, 0xFFFF, sum = 0
8500 11:08:50.338992 9, 0xFFFF, sum = 0
8501 11:08:50.339073 10, 0xFFFF, sum = 0
8502 11:08:50.342212 11, 0xFFFF, sum = 0
8503 11:08:50.342294 12, 0xFFFF, sum = 0
8504 11:08:50.345473 13, 0xFFFF, sum = 0
8505 11:08:50.345555 14, 0x0, sum = 1
8506 11:08:50.349068 15, 0x0, sum = 2
8507 11:08:50.349149 16, 0x0, sum = 3
8508 11:08:50.352390 17, 0x0, sum = 4
8509 11:08:50.352472 best_step = 15
8510 11:08:50.352536
8511 11:08:50.352595 ==
8512 11:08:50.355466 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 11:08:50.362440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 11:08:50.362524 ==
8515 11:08:50.362589 RX Vref Scan: 1
8516 11:08:50.362648
8517 11:08:50.365572 Set Vref Range= 24 -> 127
8518 11:08:50.365653
8519 11:08:50.368986 RX Vref 24 -> 127, step: 1
8520 11:08:50.369066
8521 11:08:50.372606 RX Delay 19 -> 252, step: 4
8522 11:08:50.372686
8523 11:08:50.375627 Set Vref, RX VrefLevel [Byte0]: 24
8524 11:08:50.379040 [Byte1]: 24
8525 11:08:50.379121
8526 11:08:50.381922 Set Vref, RX VrefLevel [Byte0]: 25
8527 11:08:50.385202 [Byte1]: 25
8528 11:08:50.385283
8529 11:08:50.388603 Set Vref, RX VrefLevel [Byte0]: 26
8530 11:08:50.391793 [Byte1]: 26
8531 11:08:50.391890
8532 11:08:50.395299 Set Vref, RX VrefLevel [Byte0]: 27
8533 11:08:50.398305 [Byte1]: 27
8534 11:08:50.402532
8535 11:08:50.402612 Set Vref, RX VrefLevel [Byte0]: 28
8536 11:08:50.405972 [Byte1]: 28
8537 11:08:50.409985
8538 11:08:50.410100 Set Vref, RX VrefLevel [Byte0]: 29
8539 11:08:50.413599 [Byte1]: 29
8540 11:08:50.418011
8541 11:08:50.418090 Set Vref, RX VrefLevel [Byte0]: 30
8542 11:08:50.421509 [Byte1]: 30
8543 11:08:50.425523
8544 11:08:50.425603 Set Vref, RX VrefLevel [Byte0]: 31
8545 11:08:50.428895 [Byte1]: 31
8546 11:08:50.432617
8547 11:08:50.432724 Set Vref, RX VrefLevel [Byte0]: 32
8548 11:08:50.435899 [Byte1]: 32
8549 11:08:50.440341
8550 11:08:50.440421 Set Vref, RX VrefLevel [Byte0]: 33
8551 11:08:50.443841 [Byte1]: 33
8552 11:08:50.447964
8553 11:08:50.448043 Set Vref, RX VrefLevel [Byte0]: 34
8554 11:08:50.451295 [Byte1]: 34
8555 11:08:50.455666
8556 11:08:50.455747 Set Vref, RX VrefLevel [Byte0]: 35
8557 11:08:50.458770 [Byte1]: 35
8558 11:08:50.463621
8559 11:08:50.463701 Set Vref, RX VrefLevel [Byte0]: 36
8560 11:08:50.466671 [Byte1]: 36
8561 11:08:50.470813
8562 11:08:50.470894 Set Vref, RX VrefLevel [Byte0]: 37
8563 11:08:50.473927 [Byte1]: 37
8564 11:08:50.478114
8565 11:08:50.478194 Set Vref, RX VrefLevel [Byte0]: 38
8566 11:08:50.481908 [Byte1]: 38
8567 11:08:50.486005
8568 11:08:50.486086 Set Vref, RX VrefLevel [Byte0]: 39
8569 11:08:50.489015 [Byte1]: 39
8570 11:08:50.493773
8571 11:08:50.493853 Set Vref, RX VrefLevel [Byte0]: 40
8572 11:08:50.497158 [Byte1]: 40
8573 11:08:50.501209
8574 11:08:50.501289 Set Vref, RX VrefLevel [Byte0]: 41
8575 11:08:50.504597 [Byte1]: 41
8576 11:08:50.508648
8577 11:08:50.508728 Set Vref, RX VrefLevel [Byte0]: 42
8578 11:08:50.511942 [Byte1]: 42
8579 11:08:50.516094
8580 11:08:50.516175 Set Vref, RX VrefLevel [Byte0]: 43
8581 11:08:50.519689 [Byte1]: 43
8582 11:08:50.523783
8583 11:08:50.523864 Set Vref, RX VrefLevel [Byte0]: 44
8584 11:08:50.526876 [Byte1]: 44
8585 11:08:50.531120
8586 11:08:50.531203 Set Vref, RX VrefLevel [Byte0]: 45
8587 11:08:50.535105 [Byte1]: 45
8588 11:08:50.538605
8589 11:08:50.538703 Set Vref, RX VrefLevel [Byte0]: 46
8590 11:08:50.542264 [Byte1]: 46
8591 11:08:50.546809
8592 11:08:50.546889 Set Vref, RX VrefLevel [Byte0]: 47
8593 11:08:50.549814 [Byte1]: 47
8594 11:08:50.553830
8595 11:08:50.553910 Set Vref, RX VrefLevel [Byte0]: 48
8596 11:08:50.557391 [Byte1]: 48
8597 11:08:50.561645
8598 11:08:50.561726 Set Vref, RX VrefLevel [Byte0]: 49
8599 11:08:50.564849 [Byte1]: 49
8600 11:08:50.569036
8601 11:08:50.569116 Set Vref, RX VrefLevel [Byte0]: 50
8602 11:08:50.573220 [Byte1]: 50
8603 11:08:50.576686
8604 11:08:50.576767 Set Vref, RX VrefLevel [Byte0]: 51
8605 11:08:50.580376 [Byte1]: 51
8606 11:08:50.584294
8607 11:08:50.584375 Set Vref, RX VrefLevel [Byte0]: 52
8608 11:08:50.588148 [Byte1]: 52
8609 11:08:50.591705
8610 11:08:50.591786 Set Vref, RX VrefLevel [Byte0]: 53
8611 11:08:50.594981 [Byte1]: 53
8612 11:08:50.599320
8613 11:08:50.599438 Set Vref, RX VrefLevel [Byte0]: 54
8614 11:08:50.602870 [Byte1]: 54
8615 11:08:50.607142
8616 11:08:50.607222 Set Vref, RX VrefLevel [Byte0]: 55
8617 11:08:50.610226 [Byte1]: 55
8618 11:08:50.614585
8619 11:08:50.614665 Set Vref, RX VrefLevel [Byte0]: 56
8620 11:08:50.617992 [Byte1]: 56
8621 11:08:50.622169
8622 11:08:50.622250 Set Vref, RX VrefLevel [Byte0]: 57
8623 11:08:50.625650 [Byte1]: 57
8624 11:08:50.630079
8625 11:08:50.630162 Set Vref, RX VrefLevel [Byte0]: 58
8626 11:08:50.633071 [Byte1]: 58
8627 11:08:50.637325
8628 11:08:50.637406 Set Vref, RX VrefLevel [Byte0]: 59
8629 11:08:50.640491 [Byte1]: 59
8630 11:08:50.645057
8631 11:08:50.645137 Set Vref, RX VrefLevel [Byte0]: 60
8632 11:08:50.648234 [Byte1]: 60
8633 11:08:50.653103
8634 11:08:50.653183 Set Vref, RX VrefLevel [Byte0]: 61
8635 11:08:50.655961 [Byte1]: 61
8636 11:08:50.659973
8637 11:08:50.660054 Set Vref, RX VrefLevel [Byte0]: 62
8638 11:08:50.663643 [Byte1]: 62
8639 11:08:50.667577
8640 11:08:50.667657 Set Vref, RX VrefLevel [Byte0]: 63
8641 11:08:50.670810 [Byte1]: 63
8642 11:08:50.675332
8643 11:08:50.675449 Set Vref, RX VrefLevel [Byte0]: 64
8644 11:08:50.678561 [Byte1]: 64
8645 11:08:50.683290
8646 11:08:50.683408 Set Vref, RX VrefLevel [Byte0]: 65
8647 11:08:50.686742 [Byte1]: 65
8648 11:08:50.690202
8649 11:08:50.690313 Set Vref, RX VrefLevel [Byte0]: 66
8650 11:08:50.693444 [Byte1]: 66
8651 11:08:50.697888
8652 11:08:50.697968 Set Vref, RX VrefLevel [Byte0]: 67
8653 11:08:50.700912 [Byte1]: 67
8654 11:08:50.705581
8655 11:08:50.705662 Set Vref, RX VrefLevel [Byte0]: 68
8656 11:08:50.708565 [Byte1]: 68
8657 11:08:50.713231
8658 11:08:50.713338 Set Vref, RX VrefLevel [Byte0]: 69
8659 11:08:50.716578 [Byte1]: 69
8660 11:08:50.720391
8661 11:08:50.720472 Set Vref, RX VrefLevel [Byte0]: 70
8662 11:08:50.723842 [Byte1]: 70
8663 11:08:50.727993
8664 11:08:50.728154 Set Vref, RX VrefLevel [Byte0]: 71
8665 11:08:50.731283 [Byte1]: 71
8666 11:08:50.735665
8667 11:08:50.735745 Set Vref, RX VrefLevel [Byte0]: 72
8668 11:08:50.739164 [Byte1]: 72
8669 11:08:50.743258
8670 11:08:50.743385 Final RX Vref Byte 0 = 57 to rank0
8671 11:08:50.746554 Final RX Vref Byte 1 = 63 to rank0
8672 11:08:50.750282 Final RX Vref Byte 0 = 57 to rank1
8673 11:08:50.753402 Final RX Vref Byte 1 = 63 to rank1==
8674 11:08:50.756843 Dram Type= 6, Freq= 0, CH_1, rank 0
8675 11:08:50.763088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8676 11:08:50.763170 ==
8677 11:08:50.763234 DQS Delay:
8678 11:08:50.766447 DQS0 = 0, DQS1 = 0
8679 11:08:50.766528 DQM Delay:
8680 11:08:50.766591 DQM0 = 132, DQM1 = 128
8681 11:08:50.770245 DQ Delay:
8682 11:08:50.772760 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =132
8683 11:08:50.776693 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8684 11:08:50.779591 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =120
8685 11:08:50.782510 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8686 11:08:50.782618
8687 11:08:50.782709
8688 11:08:50.782797
8689 11:08:50.786655 [DramC_TX_OE_Calibration] TA2
8690 11:08:50.789303 Original DQ_B0 (3 6) =30, OEN = 27
8691 11:08:50.792580 Original DQ_B1 (3 6) =30, OEN = 27
8692 11:08:50.795852 24, 0x0, End_B0=24 End_B1=24
8693 11:08:50.799408 25, 0x0, End_B0=25 End_B1=25
8694 11:08:50.799491 26, 0x0, End_B0=26 End_B1=26
8695 11:08:50.802305 27, 0x0, End_B0=27 End_B1=27
8696 11:08:50.805582 28, 0x0, End_B0=28 End_B1=28
8697 11:08:50.809752 29, 0x0, End_B0=29 End_B1=29
8698 11:08:50.809834 30, 0x0, End_B0=30 End_B1=30
8699 11:08:50.812673 31, 0x4141, End_B0=30 End_B1=30
8700 11:08:50.815909 Byte0 end_step=30 best_step=27
8701 11:08:50.819190 Byte1 end_step=30 best_step=27
8702 11:08:50.822024 Byte0 TX OE(2T, 0.5T) = (3, 3)
8703 11:08:50.825411 Byte1 TX OE(2T, 0.5T) = (3, 3)
8704 11:08:50.825491
8705 11:08:50.825556
8706 11:08:50.832174 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8707 11:08:50.835949 CH1 RK0: MR19=303, MR18=C16
8708 11:08:50.841988 CH1_RK0: MR19=0x303, MR18=0xC16, DQSOSC=398, MR23=63, INC=23, DEC=15
8709 11:08:50.842069
8710 11:08:50.845439 ----->DramcWriteLeveling(PI) begin...
8711 11:08:50.845521 ==
8712 11:08:50.848497 Dram Type= 6, Freq= 0, CH_1, rank 1
8713 11:08:50.851738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8714 11:08:50.851820 ==
8715 11:08:50.854942 Write leveling (Byte 0): 25 => 25
8716 11:08:50.858284 Write leveling (Byte 1): 27 => 27
8717 11:08:50.861332 DramcWriteLeveling(PI) end<-----
8718 11:08:50.861413
8719 11:08:50.861476 ==
8720 11:08:50.864922 Dram Type= 6, Freq= 0, CH_1, rank 1
8721 11:08:50.871715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8722 11:08:50.871796 ==
8723 11:08:50.871861 [Gating] SW mode calibration
8724 11:08:50.881261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8725 11:08:50.884372 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8726 11:08:50.891788 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8727 11:08:50.894193 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 11:08:50.897688 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8729 11:08:50.904167 1 4 12 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
8730 11:08:50.907766 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8731 11:08:50.910619 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8732 11:08:50.917389 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8733 11:08:50.920610 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 11:08:50.924002 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 11:08:50.930816 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8736 11:08:50.933682 1 5 8 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8737 11:08:50.937247 1 5 12 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
8738 11:08:50.944044 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 11:08:50.946770 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 11:08:50.950433 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 11:08:50.956739 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 11:08:50.960028 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 11:08:50.963246 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8744 11:08:50.970092 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8745 11:08:50.973288 1 6 12 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8746 11:08:50.976467 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8747 11:08:50.983544 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8748 11:08:50.986067 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 11:08:50.989688 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 11:08:50.996480 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 11:08:50.999473 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 11:08:51.002864 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8753 11:08:51.009283 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8754 11:08:51.012633 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 11:08:51.015750 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 11:08:51.022529 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 11:08:51.026092 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 11:08:51.029134 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 11:08:51.035700 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 11:08:51.039148 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 11:08:51.042754 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 11:08:51.048958 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 11:08:51.052414 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 11:08:51.055583 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 11:08:51.062296 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 11:08:51.065842 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 11:08:51.068748 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8768 11:08:51.075602 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8769 11:08:51.079028 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8770 11:08:51.081988 Total UI for P1: 0, mck2ui 16
8771 11:08:51.084914 best dqsien dly found for B0: ( 1, 9, 6)
8772 11:08:51.088252 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 11:08:51.092100 Total UI for P1: 0, mck2ui 16
8774 11:08:51.095030 best dqsien dly found for B1: ( 1, 9, 10)
8775 11:08:51.098844 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8776 11:08:51.101775 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8777 11:08:51.101856
8778 11:08:51.108238 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8779 11:08:51.111609 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8780 11:08:51.115158 [Gating] SW calibration Done
8781 11:08:51.115239 ==
8782 11:08:51.118245 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 11:08:51.121188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 11:08:51.121270 ==
8785 11:08:51.121336 RX Vref Scan: 0
8786 11:08:51.121395
8787 11:08:51.124879 RX Vref 0 -> 0, step: 1
8788 11:08:51.124961
8789 11:08:51.127820 RX Delay 0 -> 252, step: 8
8790 11:08:51.131239 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8791 11:08:51.135411 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8792 11:08:51.138455 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8793 11:08:51.144543 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8794 11:08:51.148453 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8795 11:08:51.151761 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8796 11:08:51.154234 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8797 11:08:51.160995 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8798 11:08:51.164236 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8799 11:08:51.167836 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8800 11:08:51.170703 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8801 11:08:51.174210 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8802 11:08:51.180978 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8803 11:08:51.184459 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8804 11:08:51.187595 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8805 11:08:51.190287 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8806 11:08:51.190401 ==
8807 11:08:51.193642 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 11:08:51.200492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 11:08:51.200575 ==
8810 11:08:51.200640 DQS Delay:
8811 11:08:51.203720 DQS0 = 0, DQS1 = 0
8812 11:08:51.203801 DQM Delay:
8813 11:08:51.207174 DQM0 = 133, DQM1 = 130
8814 11:08:51.207281 DQ Delay:
8815 11:08:51.210778 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8816 11:08:51.213448 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8817 11:08:51.217513 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8818 11:08:51.220271 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8819 11:08:51.220353
8820 11:08:51.220418
8821 11:08:51.220477 ==
8822 11:08:51.223191 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 11:08:51.230145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 11:08:51.230227 ==
8825 11:08:51.230292
8826 11:08:51.230353
8827 11:08:51.230411 TX Vref Scan disable
8828 11:08:51.233883 == TX Byte 0 ==
8829 11:08:51.237140 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8830 11:08:51.243255 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8831 11:08:51.243372 == TX Byte 1 ==
8832 11:08:51.246797 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8833 11:08:51.253344 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8834 11:08:51.253425 ==
8835 11:08:51.256625 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 11:08:51.259990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 11:08:51.260072 ==
8838 11:08:51.274340
8839 11:08:51.277828 TX Vref early break, caculate TX vref
8840 11:08:51.281041 TX Vref=16, minBit 9, minWin=20, winSum=375
8841 11:08:51.284369 TX Vref=18, minBit 9, minWin=22, winSum=385
8842 11:08:51.287882 TX Vref=20, minBit 9, minWin=22, winSum=395
8843 11:08:51.291154 TX Vref=22, minBit 8, minWin=24, winSum=400
8844 11:08:51.294336 TX Vref=24, minBit 9, minWin=24, winSum=402
8845 11:08:51.301137 TX Vref=26, minBit 0, minWin=25, winSum=412
8846 11:08:51.304129 TX Vref=28, minBit 9, minWin=25, winSum=417
8847 11:08:51.307398 TX Vref=30, minBit 9, minWin=24, winSum=415
8848 11:08:51.310363 TX Vref=32, minBit 8, minWin=24, winSum=408
8849 11:08:51.313786 TX Vref=34, minBit 8, minWin=24, winSum=403
8850 11:08:51.320661 TX Vref=36, minBit 8, minWin=23, winSum=396
8851 11:08:51.323696 TX Vref=38, minBit 8, minWin=23, winSum=389
8852 11:08:51.330712 [TxChooseVref] Worse bit 9, Min win 25, Win sum 417, Final Vref 28
8853 11:08:51.330794
8854 11:08:51.330858 Final TX Range 0 Vref 28
8855 11:08:51.330919
8856 11:08:51.330976 ==
8857 11:08:51.334113 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 11:08:51.340109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 11:08:51.340190 ==
8860 11:08:51.340255
8861 11:08:51.340314
8862 11:08:51.340370 TX Vref Scan disable
8863 11:08:51.347963 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8864 11:08:51.348044 == TX Byte 0 ==
8865 11:08:51.350871 u2DelayCellOfst[0]=14 cells (4 PI)
8866 11:08:51.354518 u2DelayCellOfst[1]=10 cells (3 PI)
8867 11:08:51.357757 u2DelayCellOfst[2]=0 cells (0 PI)
8868 11:08:51.360618 u2DelayCellOfst[3]=3 cells (1 PI)
8869 11:08:51.364152 u2DelayCellOfst[4]=7 cells (2 PI)
8870 11:08:51.367337 u2DelayCellOfst[5]=14 cells (4 PI)
8871 11:08:51.370815 u2DelayCellOfst[6]=14 cells (4 PI)
8872 11:08:51.373916 u2DelayCellOfst[7]=7 cells (2 PI)
8873 11:08:51.377188 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8874 11:08:51.380493 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8875 11:08:51.383527 == TX Byte 1 ==
8876 11:08:51.387165 u2DelayCellOfst[8]=0 cells (0 PI)
8877 11:08:51.390083 u2DelayCellOfst[9]=3 cells (1 PI)
8878 11:08:51.393615 u2DelayCellOfst[10]=10 cells (3 PI)
8879 11:08:51.397456 u2DelayCellOfst[11]=7 cells (2 PI)
8880 11:08:51.400840 u2DelayCellOfst[12]=14 cells (4 PI)
8881 11:08:51.403060 u2DelayCellOfst[13]=14 cells (4 PI)
8882 11:08:51.406495 u2DelayCellOfst[14]=17 cells (5 PI)
8883 11:08:51.409841 u2DelayCellOfst[15]=17 cells (5 PI)
8884 11:08:51.412988 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8885 11:08:51.416394 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8886 11:08:51.419944 DramC Write-DBI on
8887 11:08:51.420025 ==
8888 11:08:51.423641 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 11:08:51.426144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 11:08:51.426225 ==
8891 11:08:51.426288
8892 11:08:51.426348
8893 11:08:51.429964 TX Vref Scan disable
8894 11:08:51.432697 == TX Byte 0 ==
8895 11:08:51.436157 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8896 11:08:51.436237 == TX Byte 1 ==
8897 11:08:51.442774 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8898 11:08:51.442881 DramC Write-DBI off
8899 11:08:51.442973
8900 11:08:51.443061 [DATLAT]
8901 11:08:51.446259 Freq=1600, CH1 RK1
8902 11:08:51.446340
8903 11:08:51.449417 DATLAT Default: 0xf
8904 11:08:51.449497 0, 0xFFFF, sum = 0
8905 11:08:51.452935 1, 0xFFFF, sum = 0
8906 11:08:51.453017 2, 0xFFFF, sum = 0
8907 11:08:51.456020 3, 0xFFFF, sum = 0
8908 11:08:51.456102 4, 0xFFFF, sum = 0
8909 11:08:51.459267 5, 0xFFFF, sum = 0
8910 11:08:51.459350 6, 0xFFFF, sum = 0
8911 11:08:51.462578 7, 0xFFFF, sum = 0
8912 11:08:51.462702 8, 0xFFFF, sum = 0
8913 11:08:51.465877 9, 0xFFFF, sum = 0
8914 11:08:51.465994 10, 0xFFFF, sum = 0
8915 11:08:51.468913 11, 0xFFFF, sum = 0
8916 11:08:51.469017 12, 0xFFFF, sum = 0
8917 11:08:51.472272 13, 0xFFFF, sum = 0
8918 11:08:51.475304 14, 0x0, sum = 1
8919 11:08:51.475438 15, 0x0, sum = 2
8920 11:08:51.475533 16, 0x0, sum = 3
8921 11:08:51.478577 17, 0x0, sum = 4
8922 11:08:51.478742 best_step = 15
8923 11:08:51.478833
8924 11:08:51.481904 ==
8925 11:08:51.482000 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 11:08:51.488482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 11:08:51.488564 ==
8928 11:08:51.488627 RX Vref Scan: 0
8929 11:08:51.488688
8930 11:08:51.492194 RX Vref 0 -> 0, step: 1
8931 11:08:51.492275
8932 11:08:51.495097 RX Delay 11 -> 252, step: 4
8933 11:08:51.498567 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8934 11:08:51.501761 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8935 11:08:51.508465 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8936 11:08:51.511656 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8937 11:08:51.514804 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8938 11:08:51.518149 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8939 11:08:51.524721 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8940 11:08:51.528123 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8941 11:08:51.531250 iDelay=195, Bit 8, Center 114 (63 ~ 166) 104
8942 11:08:51.534666 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8943 11:08:51.537955 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8944 11:08:51.544506 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8945 11:08:51.547722 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8946 11:08:51.551037 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8947 11:08:51.554396 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8948 11:08:51.560787 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8949 11:08:51.560868 ==
8950 11:08:51.564194 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 11:08:51.567217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 11:08:51.567336 ==
8953 11:08:51.567510 DQS Delay:
8954 11:08:51.571351 DQS0 = 0, DQS1 = 0
8955 11:08:51.571458 DQM Delay:
8956 11:08:51.573768 DQM0 = 131, DQM1 = 127
8957 11:08:51.573848 DQ Delay:
8958 11:08:51.576937 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =128
8959 11:08:51.580445 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =128
8960 11:08:51.583665 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8961 11:08:51.586906 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8962 11:08:51.586987
8963 11:08:51.590133
8964 11:08:51.590213
8965 11:08:51.590277 [DramC_TX_OE_Calibration] TA2
8966 11:08:51.593343 Original DQ_B0 (3 6) =30, OEN = 27
8967 11:08:51.597531 Original DQ_B1 (3 6) =30, OEN = 27
8968 11:08:51.600376 24, 0x0, End_B0=24 End_B1=24
8969 11:08:51.603636 25, 0x0, End_B0=25 End_B1=25
8970 11:08:51.606952 26, 0x0, End_B0=26 End_B1=26
8971 11:08:51.607036 27, 0x0, End_B0=27 End_B1=27
8972 11:08:51.610200 28, 0x0, End_B0=28 End_B1=28
8973 11:08:51.613671 29, 0x0, End_B0=29 End_B1=29
8974 11:08:51.616998 30, 0x0, End_B0=30 End_B1=30
8975 11:08:51.620472 31, 0x4545, End_B0=30 End_B1=30
8976 11:08:51.623841 Byte0 end_step=30 best_step=27
8977 11:08:51.623923 Byte1 end_step=30 best_step=27
8978 11:08:51.626669 Byte0 TX OE(2T, 0.5T) = (3, 3)
8979 11:08:51.630249 Byte1 TX OE(2T, 0.5T) = (3, 3)
8980 11:08:51.630330
8981 11:08:51.630394
8982 11:08:51.639865 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
8983 11:08:51.639948 CH1 RK1: MR19=303, MR18=C1A
8984 11:08:51.646711 CH1_RK1: MR19=0x303, MR18=0xC1A, DQSOSC=396, MR23=63, INC=23, DEC=15
8985 11:08:51.649586 [RxdqsGatingPostProcess] freq 1600
8986 11:08:51.656281 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8987 11:08:51.659623 best DQS0 dly(2T, 0.5T) = (1, 1)
8988 11:08:51.662790 best DQS1 dly(2T, 0.5T) = (1, 1)
8989 11:08:51.666024 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8990 11:08:51.670424 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8991 11:08:51.670505 best DQS0 dly(2T, 0.5T) = (1, 1)
8992 11:08:51.672799 best DQS1 dly(2T, 0.5T) = (1, 1)
8993 11:08:51.676087 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8994 11:08:51.679582 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8995 11:08:51.682613 Pre-setting of DQS Precalculation
8996 11:08:51.688995 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8997 11:08:51.695640 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8998 11:08:51.702754 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8999 11:08:51.702836
9000 11:08:51.702899
9001 11:08:51.705784 [Calibration Summary] 3200 Mbps
9002 11:08:51.705865 CH 0, Rank 0
9003 11:08:51.709240 SW Impedance : PASS
9004 11:08:51.712224 DUTY Scan : NO K
9005 11:08:51.712305 ZQ Calibration : PASS
9006 11:08:51.715751 Jitter Meter : NO K
9007 11:08:51.718705 CBT Training : PASS
9008 11:08:51.718786 Write leveling : PASS
9009 11:08:51.722434 RX DQS gating : PASS
9010 11:08:51.725847 RX DQ/DQS(RDDQC) : PASS
9011 11:08:51.725927 TX DQ/DQS : PASS
9012 11:08:51.728781 RX DATLAT : PASS
9013 11:08:51.732329 RX DQ/DQS(Engine): PASS
9014 11:08:51.732408 TX OE : PASS
9015 11:08:51.735229 All Pass.
9016 11:08:51.735309
9017 11:08:51.735382 CH 0, Rank 1
9018 11:08:51.739073 SW Impedance : PASS
9019 11:08:51.739153 DUTY Scan : NO K
9020 11:08:51.741822 ZQ Calibration : PASS
9021 11:08:51.745137 Jitter Meter : NO K
9022 11:08:51.745232 CBT Training : PASS
9023 11:08:51.748702 Write leveling : PASS
9024 11:08:51.751789 RX DQS gating : PASS
9025 11:08:51.751869 RX DQ/DQS(RDDQC) : PASS
9026 11:08:51.755234 TX DQ/DQS : PASS
9027 11:08:51.758301 RX DATLAT : PASS
9028 11:08:51.758382 RX DQ/DQS(Engine): PASS
9029 11:08:51.761678 TX OE : PASS
9030 11:08:51.761759 All Pass.
9031 11:08:51.761822
9032 11:08:51.765265 CH 1, Rank 0
9033 11:08:51.765345 SW Impedance : PASS
9034 11:08:51.768321 DUTY Scan : NO K
9035 11:08:51.771519 ZQ Calibration : PASS
9036 11:08:51.771622 Jitter Meter : NO K
9037 11:08:51.774819 CBT Training : PASS
9038 11:08:51.774899 Write leveling : PASS
9039 11:08:51.777913 RX DQS gating : PASS
9040 11:08:51.781608 RX DQ/DQS(RDDQC) : PASS
9041 11:08:51.781688 TX DQ/DQS : PASS
9042 11:08:51.784682 RX DATLAT : PASS
9043 11:08:51.788116 RX DQ/DQS(Engine): PASS
9044 11:08:51.788196 TX OE : PASS
9045 11:08:51.791202 All Pass.
9046 11:08:51.791285
9047 11:08:51.791349 CH 1, Rank 1
9048 11:08:51.795178 SW Impedance : PASS
9049 11:08:51.795259 DUTY Scan : NO K
9050 11:08:51.797663 ZQ Calibration : PASS
9051 11:08:51.801052 Jitter Meter : NO K
9052 11:08:51.801169 CBT Training : PASS
9053 11:08:51.804206 Write leveling : PASS
9054 11:08:51.807587 RX DQS gating : PASS
9055 11:08:51.807670 RX DQ/DQS(RDDQC) : PASS
9056 11:08:51.810839 TX DQ/DQS : PASS
9057 11:08:51.814214 RX DATLAT : PASS
9058 11:08:51.814297 RX DQ/DQS(Engine): PASS
9059 11:08:51.817913 TX OE : PASS
9060 11:08:51.817995 All Pass.
9061 11:08:51.818061
9062 11:08:51.820894 DramC Write-DBI on
9063 11:08:51.824098 PER_BANK_REFRESH: Hybrid Mode
9064 11:08:51.824180 TX_TRACKING: ON
9065 11:08:51.833872 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9066 11:08:51.840498 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9067 11:08:51.847424 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9068 11:08:51.850250 [FAST_K] Save calibration result to emmc
9069 11:08:51.853623 sync common calibartion params.
9070 11:08:51.857140 sync cbt_mode0:1, 1:1
9071 11:08:51.860743 dram_init: ddr_geometry: 2
9072 11:08:51.860824 dram_init: ddr_geometry: 2
9073 11:08:51.863741 dram_init: ddr_geometry: 2
9074 11:08:51.867296 0:dram_rank_size:100000000
9075 11:08:51.870966 1:dram_rank_size:100000000
9076 11:08:51.873374 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9077 11:08:51.876788 DFS_SHUFFLE_HW_MODE: ON
9078 11:08:51.880185 dramc_set_vcore_voltage set vcore to 725000
9079 11:08:51.883218 Read voltage for 1600, 0
9080 11:08:51.883326 Vio18 = 0
9081 11:08:51.886928 Vcore = 725000
9082 11:08:51.887010 Vdram = 0
9083 11:08:51.887074 Vddq = 0
9084 11:08:51.887134 Vmddr = 0
9085 11:08:51.890106 switch to 3200 Mbps bootup
9086 11:08:51.893604 [DramcRunTimeConfig]
9087 11:08:51.893716 PHYPLL
9088 11:08:51.893781 DPM_CONTROL_AFTERK: ON
9089 11:08:51.896986 PER_BANK_REFRESH: ON
9090 11:08:51.899915 REFRESH_OVERHEAD_REDUCTION: ON
9091 11:08:51.903820 CMD_PICG_NEW_MODE: OFF
9092 11:08:51.903901 XRTWTW_NEW_MODE: ON
9093 11:08:51.906729 XRTRTR_NEW_MODE: ON
9094 11:08:51.906810 TX_TRACKING: ON
9095 11:08:51.910113 RDSEL_TRACKING: OFF
9096 11:08:51.910194 DQS Precalculation for DVFS: ON
9097 11:08:51.913545 RX_TRACKING: OFF
9098 11:08:51.913626 HW_GATING DBG: ON
9099 11:08:51.916807 ZQCS_ENABLE_LP4: ON
9100 11:08:51.919806 RX_PICG_NEW_MODE: ON
9101 11:08:51.919887 TX_PICG_NEW_MODE: ON
9102 11:08:51.923273 ENABLE_RX_DCM_DPHY: ON
9103 11:08:51.926536 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9104 11:08:51.926617 DUMMY_READ_FOR_TRACKING: OFF
9105 11:08:51.929909 !!! SPM_CONTROL_AFTERK: OFF
9106 11:08:51.933024 !!! SPM could not control APHY
9107 11:08:51.936312 IMPEDANCE_TRACKING: ON
9108 11:08:51.936393 TEMP_SENSOR: ON
9109 11:08:51.939386 HW_SAVE_FOR_SR: OFF
9110 11:08:51.942801 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9111 11:08:51.946216 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9112 11:08:51.946297 Read ODT Tracking: ON
9113 11:08:51.949493 Refresh Rate DeBounce: ON
9114 11:08:51.952863 DFS_NO_QUEUE_FLUSH: ON
9115 11:08:51.955783 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9116 11:08:51.955890 ENABLE_DFS_RUNTIME_MRW: OFF
9117 11:08:51.959274 DDR_RESERVE_NEW_MODE: ON
9118 11:08:51.962347 MR_CBT_SWITCH_FREQ: ON
9119 11:08:51.962427 =========================
9120 11:08:51.983318 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9121 11:08:51.986100 dram_init: ddr_geometry: 2
9122 11:08:52.004523 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9123 11:08:52.007687 dram_init: dram init end (result: 0)
9124 11:08:52.014560 DRAM-K: Full calibration passed in 24439 msecs
9125 11:08:52.017622 MRC: failed to locate region type 0.
9126 11:08:52.017703 DRAM rank0 size:0x100000000,
9127 11:08:52.020778 DRAM rank1 size=0x100000000
9128 11:08:52.030816 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9129 11:08:52.037138 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9130 11:08:52.047003 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9131 11:08:52.053550 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9132 11:08:52.053672 DRAM rank0 size:0x100000000,
9133 11:08:52.056776 DRAM rank1 size=0x100000000
9134 11:08:52.056872 CBMEM:
9135 11:08:52.059959 IMD: root @ 0xfffff000 254 entries.
9136 11:08:52.063549 IMD: root @ 0xffffec00 62 entries.
9137 11:08:52.070106 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9138 11:08:52.073674 WARNING: RO_VPD is uninitialized or empty.
9139 11:08:52.076474 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9140 11:08:52.084741 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9141 11:08:52.097640 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9142 11:08:52.109098 BS: romstage times (exec / console): total (unknown) / 23965 ms
9143 11:08:52.109181
9144 11:08:52.109244
9145 11:08:52.118789 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9146 11:08:52.121957 ARM64: Exception handlers installed.
9147 11:08:52.124964 ARM64: Testing exception
9148 11:08:52.128272 ARM64: Done test exception
9149 11:08:52.128353 Enumerating buses...
9150 11:08:52.131661 Show all devs... Before device enumeration.
9151 11:08:52.134911 Root Device: enabled 1
9152 11:08:52.137930 CPU_CLUSTER: 0: enabled 1
9153 11:08:52.138051 CPU: 00: enabled 1
9154 11:08:52.141331 Compare with tree...
9155 11:08:52.141441 Root Device: enabled 1
9156 11:08:52.144666 CPU_CLUSTER: 0: enabled 1
9157 11:08:52.148006 CPU: 00: enabled 1
9158 11:08:52.148086 Root Device scanning...
9159 11:08:52.151480 scan_static_bus for Root Device
9160 11:08:52.154660 CPU_CLUSTER: 0 enabled
9161 11:08:52.158162 scan_static_bus for Root Device done
9162 11:08:52.161250 scan_bus: bus Root Device finished in 8 msecs
9163 11:08:52.161330 done
9164 11:08:52.167591 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9165 11:08:52.171133 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9166 11:08:52.177550 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9167 11:08:52.184081 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9168 11:08:52.184162 Allocating resources...
9169 11:08:52.187289 Reading resources...
9170 11:08:52.190781 Root Device read_resources bus 0 link: 0
9171 11:08:52.193989 DRAM rank0 size:0x100000000,
9172 11:08:52.194088 DRAM rank1 size=0x100000000
9173 11:08:52.200535 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9174 11:08:52.200618 CPU: 00 missing read_resources
9175 11:08:52.207066 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9176 11:08:52.210564 Root Device read_resources bus 0 link: 0 done
9177 11:08:52.213622 Done reading resources.
9178 11:08:52.216962 Show resources in subtree (Root Device)...After reading.
9179 11:08:52.220044 Root Device child on link 0 CPU_CLUSTER: 0
9180 11:08:52.223705 CPU_CLUSTER: 0 child on link 0 CPU: 00
9181 11:08:52.233360 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9182 11:08:52.233459 CPU: 00
9183 11:08:52.239977 Root Device assign_resources, bus 0 link: 0
9184 11:08:52.243079 CPU_CLUSTER: 0 missing set_resources
9185 11:08:52.246664 Root Device assign_resources, bus 0 link: 0 done
9186 11:08:52.249645 Done setting resources.
9187 11:08:52.253201 Show resources in subtree (Root Device)...After assigning values.
9188 11:08:52.259949 Root Device child on link 0 CPU_CLUSTER: 0
9189 11:08:52.263305 CPU_CLUSTER: 0 child on link 0 CPU: 00
9190 11:08:52.269274 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9191 11:08:52.272637 CPU: 00
9192 11:08:52.272738 Done allocating resources.
9193 11:08:52.279078 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9194 11:08:52.282760 Enabling resources...
9195 11:08:52.282842 done.
9196 11:08:52.285836 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9197 11:08:52.289595 Initializing devices...
9198 11:08:52.289677 Root Device init
9199 11:08:52.292444 init hardware done!
9200 11:08:52.295668 0x00000018: ctrlr->caps
9201 11:08:52.295788 52.000 MHz: ctrlr->f_max
9202 11:08:52.298996 0.400 MHz: ctrlr->f_min
9203 11:08:52.302437 0x40ff8080: ctrlr->voltages
9204 11:08:52.302539 sclk: 390625
9205 11:08:52.302630 Bus Width = 1
9206 11:08:52.305707 sclk: 390625
9207 11:08:52.305803 Bus Width = 1
9208 11:08:52.309392 Early init status = 3
9209 11:08:52.312263 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9210 11:08:52.317086 in-header: 03 fc 00 00 01 00 00 00
9211 11:08:52.320353 in-data: 00
9212 11:08:52.323451 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9213 11:08:52.329068 in-header: 03 fd 00 00 00 00 00 00
9214 11:08:52.332747 in-data:
9215 11:08:52.336105 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9216 11:08:52.340150 in-header: 03 fc 00 00 01 00 00 00
9217 11:08:52.343240 in-data: 00
9218 11:08:52.346737 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9219 11:08:52.352385 in-header: 03 fd 00 00 00 00 00 00
9220 11:08:52.355831 in-data:
9221 11:08:52.358894 [SSUSB] Setting up USB HOST controller...
9222 11:08:52.362141 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9223 11:08:52.365381 [SSUSB] phy power-on done.
9224 11:08:52.368822 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9225 11:08:52.375657 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9226 11:08:52.378620 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9227 11:08:52.385718 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9228 11:08:52.391975 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9229 11:08:52.399135 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9230 11:08:52.405381 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9231 11:08:52.411504 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9232 11:08:52.415175 SPM: binary array size = 0x9dc
9233 11:08:52.418503 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9234 11:08:52.424744 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9235 11:08:52.431604 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9236 11:08:52.438267 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9237 11:08:52.441337 configure_display: Starting display init
9238 11:08:52.475861 anx7625_power_on_init: Init interface.
9239 11:08:52.479121 anx7625_disable_pd_protocol: Disabled PD feature.
9240 11:08:52.482094 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9241 11:08:52.509888 anx7625_start_dp_work: Secure OCM version=00
9242 11:08:52.513693 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9243 11:08:52.528042 sp_tx_get_edid_block: EDID Block = 1
9244 11:08:52.630842 Extracted contents:
9245 11:08:52.634339 header: 00 ff ff ff ff ff ff 00
9246 11:08:52.637311 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9247 11:08:52.640610 version: 01 04
9248 11:08:52.643874 basic params: 95 1f 11 78 0a
9249 11:08:52.647095 chroma info: 76 90 94 55 54 90 27 21 50 54
9250 11:08:52.650391 established: 00 00 00
9251 11:08:52.657649 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9252 11:08:52.663538 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9253 11:08:52.667183 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9254 11:08:52.673293 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9255 11:08:52.680004 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9256 11:08:52.683616 extensions: 00
9257 11:08:52.683697 checksum: fb
9258 11:08:52.683761
9259 11:08:52.690357 Manufacturer: IVO Model 57d Serial Number 0
9260 11:08:52.690438 Made week 0 of 2020
9261 11:08:52.693439 EDID version: 1.4
9262 11:08:52.693520 Digital display
9263 11:08:52.696518 6 bits per primary color channel
9264 11:08:52.700151 DisplayPort interface
9265 11:08:52.700232 Maximum image size: 31 cm x 17 cm
9266 11:08:52.703166 Gamma: 220%
9267 11:08:52.703247 Check DPMS levels
9268 11:08:52.709676 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9269 11:08:52.713545 First detailed timing is preferred timing
9270 11:08:52.716294 Established timings supported:
9271 11:08:52.716374 Standard timings supported:
9272 11:08:52.719832 Detailed timings
9273 11:08:52.722914 Hex of detail: 383680a07038204018303c0035ae10000019
9274 11:08:52.729344 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9275 11:08:52.732797 0780 0798 07c8 0820 hborder 0
9276 11:08:52.735958 0438 043b 0447 0458 vborder 0
9277 11:08:52.739261 -hsync -vsync
9278 11:08:52.739344 Did detailed timing
9279 11:08:52.745993 Hex of detail: 000000000000000000000000000000000000
9280 11:08:52.749137 Manufacturer-specified data, tag 0
9281 11:08:52.752276 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9282 11:08:52.756050 ASCII string: InfoVision
9283 11:08:52.759154 Hex of detail: 000000fe00523134304e574635205248200a
9284 11:08:52.762296 ASCII string: R140NWF5 RH
9285 11:08:52.762403 Checksum
9286 11:08:52.765652 Checksum: 0xfb (valid)
9287 11:08:52.768930 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9288 11:08:52.772145 DSI data_rate: 832800000 bps
9289 11:08:52.778817 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9290 11:08:52.782088 anx7625_parse_edid: pixelclock(138800).
9291 11:08:52.785679 hactive(1920), hsync(48), hfp(24), hbp(88)
9292 11:08:52.788243 vactive(1080), vsync(12), vfp(3), vbp(17)
9293 11:08:52.791725 anx7625_dsi_config: config dsi.
9294 11:08:52.798563 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9295 11:08:52.813209 anx7625_dsi_config: success to config DSI
9296 11:08:52.816398 anx7625_dp_start: MIPI phy setup OK.
9297 11:08:52.819349 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9298 11:08:52.822790 mtk_ddp_mode_set invalid vrefresh 60
9299 11:08:52.825791 main_disp_path_setup
9300 11:08:52.825871 ovl_layer_smi_id_en
9301 11:08:52.829030 ovl_layer_smi_id_en
9302 11:08:52.829150 ccorr_config
9303 11:08:52.829242 aal_config
9304 11:08:52.832421 gamma_config
9305 11:08:52.832501 postmask_config
9306 11:08:52.835887 dither_config
9307 11:08:52.839437 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9308 11:08:52.845841 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9309 11:08:52.848937 Root Device init finished in 555 msecs
9310 11:08:52.852530 CPU_CLUSTER: 0 init
9311 11:08:52.858649 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9312 11:08:52.865590 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9313 11:08:52.865698 APU_MBOX 0x190000b0 = 0x10001
9314 11:08:52.868956 APU_MBOX 0x190001b0 = 0x10001
9315 11:08:52.872104 APU_MBOX 0x190005b0 = 0x10001
9316 11:08:52.875254 APU_MBOX 0x190006b0 = 0x10001
9317 11:08:52.881987 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9318 11:08:52.891762 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9319 11:08:52.904108 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9320 11:08:52.910748 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9321 11:08:52.923053 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9322 11:08:52.931347 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9323 11:08:52.934674 CPU_CLUSTER: 0 init finished in 81 msecs
9324 11:08:52.937931 Devices initialized
9325 11:08:52.941579 Show all devs... After init.
9326 11:08:52.941674 Root Device: enabled 1
9327 11:08:52.944952 CPU_CLUSTER: 0: enabled 1
9328 11:08:52.947862 CPU: 00: enabled 1
9329 11:08:52.951307 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9330 11:08:52.954398 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9331 11:08:52.957991 ELOG: NV offset 0x57f000 size 0x1000
9332 11:08:52.964705 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9333 11:08:52.971037 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9334 11:08:52.974361 ELOG: Event(17) added with size 13 at 2024-03-03 11:08:52 UTC
9335 11:08:52.980742 out: cmd=0x121: 03 db 21 01 00 00 00 00
9336 11:08:52.984544 in-header: 03 18 00 00 2c 00 00 00
9337 11:08:52.998019 in-data: 47 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9338 11:08:53.000677 ELOG: Event(A1) added with size 10 at 2024-03-03 11:08:53 UTC
9339 11:08:53.007372 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9340 11:08:53.013684 ELOG: Event(A0) added with size 9 at 2024-03-03 11:08:53 UTC
9341 11:08:53.017009 elog_add_boot_reason: Logged dev mode boot
9342 11:08:53.023581 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9343 11:08:53.023665 Finalize devices...
9344 11:08:53.027330 Devices finalized
9345 11:08:53.031158 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9346 11:08:53.033730 Writing coreboot table at 0xffe64000
9347 11:08:53.040194 0. 000000000010a000-0000000000113fff: RAMSTAGE
9348 11:08:53.043523 1. 0000000040000000-00000000400fffff: RAM
9349 11:08:53.047334 2. 0000000040100000-000000004032afff: RAMSTAGE
9350 11:08:53.049905 3. 000000004032b000-00000000545fffff: RAM
9351 11:08:53.053049 4. 0000000054600000-000000005465ffff: BL31
9352 11:08:53.056763 5. 0000000054660000-00000000ffe63fff: RAM
9353 11:08:53.063610 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9354 11:08:53.066614 7. 0000000100000000-000000023fffffff: RAM
9355 11:08:53.069728 Passing 5 GPIOs to payload:
9356 11:08:53.073015 NAME | PORT | POLARITY | VALUE
9357 11:08:53.079979 EC in RW | 0x000000aa | low | undefined
9358 11:08:53.083083 EC interrupt | 0x00000005 | low | undefined
9359 11:08:53.089176 TPM interrupt | 0x000000ab | high | undefined
9360 11:08:53.092508 SD card detect | 0x00000011 | high | undefined
9361 11:08:53.099270 speaker enable | 0x00000093 | high | undefined
9362 11:08:53.102423 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9363 11:08:53.105576 in-header: 03 f9 00 00 02 00 00 00
9364 11:08:53.105659 in-data: 02 00
9365 11:08:53.109881 ADC[4]: Raw value=902955 ID=7
9366 11:08:53.112464 ADC[3]: Raw value=213916 ID=1
9367 11:08:53.112547 RAM Code: 0x71
9368 11:08:53.116017 ADC[6]: Raw value=74630 ID=0
9369 11:08:53.119202 ADC[5]: Raw value=213916 ID=1
9370 11:08:53.119309 SKU Code: 0x1
9371 11:08:53.125458 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7483
9372 11:08:53.128879 coreboot table: 964 bytes.
9373 11:08:53.132142 IMD ROOT 0. 0xfffff000 0x00001000
9374 11:08:53.135251 IMD SMALL 1. 0xffffe000 0x00001000
9375 11:08:53.138851 RO MCACHE 2. 0xffffc000 0x00001104
9376 11:08:53.141862 CONSOLE 3. 0xfff7c000 0x00080000
9377 11:08:53.145553 FMAP 4. 0xfff7b000 0x00000452
9378 11:08:53.148608 TIME STAMP 5. 0xfff7a000 0x00000910
9379 11:08:53.152192 VBOOT WORK 6. 0xfff66000 0x00014000
9380 11:08:53.155400 RAMOOPS 7. 0xffe66000 0x00100000
9381 11:08:53.158716 COREBOOT 8. 0xffe64000 0x00002000
9382 11:08:53.158812 IMD small region:
9383 11:08:53.162049 IMD ROOT 0. 0xffffec00 0x00000400
9384 11:08:53.165027 VPD 1. 0xffffeb80 0x0000006c
9385 11:08:53.168561 MMC STATUS 2. 0xffffeb60 0x00000004
9386 11:08:53.174729 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9387 11:08:53.178382 Probing TPM: done!
9388 11:08:53.182133 Connected to device vid:did:rid of 1ae0:0028:00
9389 11:08:53.191630 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9390 11:08:53.194927 Initialized TPM device CR50 revision 0
9391 11:08:53.198549 Checking cr50 for pending updates
9392 11:08:53.201617 Reading cr50 TPM mode
9393 11:08:53.210493 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9394 11:08:53.217421 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9395 11:08:53.257408 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9396 11:08:53.260810 Checking segment from ROM address 0x40100000
9397 11:08:53.263886 Checking segment from ROM address 0x4010001c
9398 11:08:53.270835 Loading segment from ROM address 0x40100000
9399 11:08:53.270918 code (compression=0)
9400 11:08:53.280523 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9401 11:08:53.287193 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9402 11:08:53.287273 it's not compressed!
9403 11:08:53.294418 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9404 11:08:53.300508 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9405 11:08:53.317712 Loading segment from ROM address 0x4010001c
9406 11:08:53.317794 Entry Point 0x80000000
9407 11:08:53.321244 Loaded segments
9408 11:08:53.325434 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9409 11:08:53.331014 Jumping to boot code at 0x80000000(0xffe64000)
9410 11:08:53.337949 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9411 11:08:53.344114 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9412 11:08:53.352318 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9413 11:08:53.355941 Checking segment from ROM address 0x40100000
9414 11:08:53.358999 Checking segment from ROM address 0x4010001c
9415 11:08:53.365657 Loading segment from ROM address 0x40100000
9416 11:08:53.365770 code (compression=1)
9417 11:08:53.372288 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9418 11:08:53.381868 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9419 11:08:53.381967 using LZMA
9420 11:08:53.391089 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9421 11:08:53.397338 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9422 11:08:53.400793 Loading segment from ROM address 0x4010001c
9423 11:08:53.400877 Entry Point 0x54601000
9424 11:08:53.403792 Loaded segments
9425 11:08:53.406761 NOTICE: MT8192 bl31_setup
9426 11:08:53.414393 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9427 11:08:53.417602 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9428 11:08:53.420833 WARNING: region 0:
9429 11:08:53.424182 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9430 11:08:53.424305 WARNING: region 1:
9431 11:08:53.431085 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9432 11:08:53.434730 WARNING: region 2:
9433 11:08:53.437588 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9434 11:08:53.440574 WARNING: region 3:
9435 11:08:53.443867 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9436 11:08:53.447666 WARNING: region 4:
9437 11:08:53.453819 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9438 11:08:53.453978 WARNING: region 5:
9439 11:08:53.457302 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9440 11:08:53.460888 WARNING: region 6:
9441 11:08:53.464437 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 11:08:53.467641 WARNING: region 7:
9443 11:08:53.470438 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 11:08:53.477185 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9445 11:08:53.480707 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9446 11:08:53.483460 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9447 11:08:53.490589 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9448 11:08:53.493499 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9449 11:08:53.500386 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9450 11:08:53.503338 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9451 11:08:53.507162 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9452 11:08:53.513763 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9453 11:08:53.516797 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9454 11:08:53.520288 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9455 11:08:53.527041 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9456 11:08:53.529850 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9457 11:08:53.536485 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9458 11:08:53.539680 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9459 11:08:53.543202 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9460 11:08:53.549990 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9461 11:08:53.553053 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9462 11:08:53.560124 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9463 11:08:53.563648 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9464 11:08:53.566428 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9465 11:08:53.572988 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9466 11:08:53.576773 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9467 11:08:53.579741 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9468 11:08:53.586324 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9469 11:08:53.589532 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9470 11:08:53.595998 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9471 11:08:53.599514 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9472 11:08:53.605780 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9473 11:08:53.609194 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9474 11:08:53.612613 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9475 11:08:53.618947 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9476 11:08:53.622886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9477 11:08:53.625596 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9478 11:08:53.632128 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9479 11:08:53.635475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9480 11:08:53.638910 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9481 11:08:53.642194 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9482 11:08:53.648525 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9483 11:08:53.652006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9484 11:08:53.655275 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9485 11:08:53.658685 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9486 11:08:53.665119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9487 11:08:53.668573 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9488 11:08:53.671657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9489 11:08:53.675210 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9490 11:08:53.681849 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9491 11:08:53.685018 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9492 11:08:53.688401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9493 11:08:53.695165 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9494 11:08:53.698341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9495 11:08:53.704744 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9496 11:08:53.708338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9497 11:08:53.715150 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9498 11:08:53.718112 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9499 11:08:53.721235 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9500 11:08:53.728005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9501 11:08:53.731711 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9502 11:08:53.738621 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9503 11:08:53.741419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9504 11:08:53.748515 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9505 11:08:53.751552 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9506 11:08:53.758149 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9507 11:08:53.761512 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9508 11:08:53.767741 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9509 11:08:53.771114 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9510 11:08:53.774677 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9511 11:08:53.781902 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9512 11:08:53.784244 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9513 11:08:53.791371 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9514 11:08:53.794556 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9515 11:08:53.800740 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9516 11:08:53.804328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9517 11:08:53.807633 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9518 11:08:53.814176 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9519 11:08:53.817506 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9520 11:08:53.824217 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9521 11:08:53.827460 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9522 11:08:53.834414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9523 11:08:53.838013 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9524 11:08:53.844216 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9525 11:08:53.847232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9526 11:08:53.851042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9527 11:08:53.857438 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9528 11:08:53.860439 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9529 11:08:53.867320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9530 11:08:53.870509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9531 11:08:53.877269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9532 11:08:53.881030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9533 11:08:53.883707 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9534 11:08:53.890339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9535 11:08:53.893362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9536 11:08:53.900113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9537 11:08:53.903493 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9538 11:08:53.910418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9539 11:08:53.914056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9540 11:08:53.916885 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9541 11:08:53.923621 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9542 11:08:53.927299 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9543 11:08:53.930268 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9544 11:08:53.933518 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9545 11:08:53.940471 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9546 11:08:53.943497 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9547 11:08:53.950150 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9548 11:08:53.953947 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9549 11:08:53.956863 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9550 11:08:53.963309 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9551 11:08:53.966345 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9552 11:08:53.973168 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9553 11:08:53.976385 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9554 11:08:53.979720 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9555 11:08:53.986453 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9556 11:08:53.989960 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9557 11:08:53.997002 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9558 11:08:53.999986 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9559 11:08:54.003403 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9560 11:08:54.009985 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9561 11:08:54.012925 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9562 11:08:54.016366 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9563 11:08:54.023152 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9564 11:08:54.026328 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9565 11:08:54.030216 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9566 11:08:54.033075 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9567 11:08:54.039353 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9568 11:08:54.043178 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9569 11:08:54.045968 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9570 11:08:54.052795 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9571 11:08:54.055837 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9572 11:08:54.062530 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9573 11:08:54.066103 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9574 11:08:54.069124 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9575 11:08:54.075932 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9576 11:08:54.079086 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9577 11:08:54.085436 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9578 11:08:54.089063 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9579 11:08:54.095299 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9580 11:08:54.098971 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9581 11:08:54.102209 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9582 11:08:54.108709 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9583 11:08:54.112164 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9584 11:08:54.119020 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9585 11:08:54.121655 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9586 11:08:54.125552 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9587 11:08:54.131843 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9588 11:08:54.134966 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9589 11:08:54.141926 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9590 11:08:54.144757 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9591 11:08:54.148213 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9592 11:08:54.154493 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9593 11:08:54.158039 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9594 11:08:54.164762 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9595 11:08:54.167828 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9596 11:08:54.171040 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9597 11:08:54.177820 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9598 11:08:54.181065 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9599 11:08:54.187773 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9600 11:08:54.191160 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9601 11:08:54.194294 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9602 11:08:54.200860 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9603 11:08:54.204599 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9604 11:08:54.210594 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9605 11:08:54.213978 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9606 11:08:54.217542 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9607 11:08:54.223697 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9608 11:08:54.227066 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9609 11:08:54.233380 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9610 11:08:54.237158 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9611 11:08:54.240485 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9612 11:08:54.246819 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9613 11:08:54.249790 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9614 11:08:54.256582 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9615 11:08:54.260019 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9616 11:08:54.263373 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9617 11:08:54.269388 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9618 11:08:54.273343 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9619 11:08:54.280197 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9620 11:08:54.283503 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9621 11:08:54.289397 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9622 11:08:54.292756 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9623 11:08:54.295940 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9624 11:08:54.302319 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9625 11:08:54.305760 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9626 11:08:54.312594 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9627 11:08:54.315549 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9628 11:08:54.318982 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9629 11:08:54.325634 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9630 11:08:54.328485 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9631 11:08:54.335186 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9632 11:08:54.338677 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9633 11:08:54.341836 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9634 11:08:54.348957 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9635 11:08:54.351906 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9636 11:08:54.358670 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9637 11:08:54.361655 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9638 11:08:54.368233 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9639 11:08:54.372122 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9640 11:08:54.374829 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9641 11:08:54.381655 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9642 11:08:54.384500 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9643 11:08:54.391222 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9644 11:08:54.394309 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9645 11:08:54.401016 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9646 11:08:54.404261 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9647 11:08:54.408094 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9648 11:08:54.414378 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9649 11:08:54.417475 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9650 11:08:54.423787 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9651 11:08:54.427154 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9652 11:08:54.433708 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9653 11:08:54.437030 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9654 11:08:54.443610 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9655 11:08:54.447146 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9656 11:08:54.449980 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9657 11:08:54.456930 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9658 11:08:54.459957 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9659 11:08:54.466759 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9660 11:08:54.470452 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9661 11:08:54.476265 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9662 11:08:54.479715 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9663 11:08:54.483408 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9664 11:08:54.489936 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9665 11:08:54.492848 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9666 11:08:54.499102 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9667 11:08:54.503047 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9668 11:08:54.509053 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9669 11:08:54.512489 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9670 11:08:54.515696 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9671 11:08:54.522480 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9672 11:08:54.526064 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9673 11:08:54.531912 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9674 11:08:54.535354 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9675 11:08:54.539026 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9676 11:08:54.542309 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9677 11:08:54.545383 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9678 11:08:54.551944 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9679 11:08:54.555294 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9680 11:08:54.562081 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9681 11:08:54.564896 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9682 11:08:54.568063 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9683 11:08:54.575605 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9684 11:08:54.578178 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9685 11:08:54.585237 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9686 11:08:54.588268 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9687 11:08:54.591513 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9688 11:08:54.598333 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9689 11:08:54.601814 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9690 11:08:54.607711 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9691 11:08:54.611076 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9692 11:08:54.614320 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9693 11:08:54.620744 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9694 11:08:54.624626 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9695 11:08:54.627337 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9696 11:08:54.633948 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9697 11:08:54.637333 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9698 11:08:54.643664 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9699 11:08:54.647105 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9700 11:08:54.650732 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9701 11:08:54.656886 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9702 11:08:54.660771 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9703 11:08:54.663390 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9704 11:08:54.669863 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9705 11:08:54.673415 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9706 11:08:54.679806 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9707 11:08:54.683090 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9708 11:08:54.686682 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9709 11:08:54.692971 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9710 11:08:54.696685 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9711 11:08:54.703141 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9712 11:08:54.706502 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9713 11:08:54.709697 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9714 11:08:54.713329 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9715 11:08:54.716374 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9716 11:08:54.722616 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9717 11:08:54.726037 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9718 11:08:54.729344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9719 11:08:54.732892 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9720 11:08:54.739538 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9721 11:08:54.742168 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9722 11:08:54.745646 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9723 11:08:54.752348 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9724 11:08:54.755358 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9725 11:08:54.759082 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9726 11:08:54.765935 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9727 11:08:54.768718 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9728 11:08:54.771923 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9729 11:08:54.779265 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9730 11:08:54.781692 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9731 11:08:54.788321 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9732 11:08:54.791507 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9733 11:08:54.798039 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9734 11:08:54.801390 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9735 11:08:54.805420 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9736 11:08:54.811929 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9737 11:08:54.814924 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9738 11:08:54.821151 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9739 11:08:54.824940 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9740 11:08:54.831061 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9741 11:08:54.834540 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9742 11:08:54.838047 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9743 11:08:54.844411 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9744 11:08:54.847632 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9745 11:08:54.854253 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9746 11:08:54.857645 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9747 11:08:54.864023 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9748 11:08:54.867467 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9749 11:08:54.870526 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9750 11:08:54.877021 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9751 11:08:54.880441 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9752 11:08:54.886853 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9753 11:08:54.890369 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9754 11:08:54.896505 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9755 11:08:54.899963 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9756 11:08:54.903331 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9757 11:08:54.909710 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9758 11:08:54.912962 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9759 11:08:54.919627 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9760 11:08:54.923187 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9761 11:08:54.926633 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9762 11:08:54.933094 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9763 11:08:54.936266 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9764 11:08:54.942873 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9765 11:08:54.946051 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9766 11:08:54.952535 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9767 11:08:54.956068 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9768 11:08:54.959349 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9769 11:08:54.965792 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9770 11:08:54.969095 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9771 11:08:54.977079 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9772 11:08:54.979499 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9773 11:08:54.982372 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9774 11:08:54.989170 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9775 11:08:54.992068 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9776 11:08:54.998648 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9777 11:08:55.001685 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9778 11:08:55.008481 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9779 11:08:55.011933 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9780 11:08:55.018239 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9781 11:08:55.021418 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9782 11:08:55.025019 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9783 11:08:55.031399 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9784 11:08:55.034963 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9785 11:08:55.041507 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9786 11:08:55.044536 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9787 11:08:55.047716 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9788 11:08:55.054335 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9789 11:08:55.057841 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9790 11:08:55.064129 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9791 11:08:55.067805 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9792 11:08:55.074404 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9793 11:08:55.077484 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9794 11:08:55.081172 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9795 11:08:55.087873 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9796 11:08:55.090930 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9797 11:08:55.097082 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9798 11:08:55.100504 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9799 11:08:55.107085 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9800 11:08:55.110648 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9801 11:08:55.113650 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9802 11:08:55.120763 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9803 11:08:55.123627 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9804 11:08:55.130940 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9805 11:08:55.134185 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9806 11:08:55.139818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9807 11:08:55.143402 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9808 11:08:55.150202 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9809 11:08:55.153593 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9810 11:08:55.156668 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9811 11:08:55.162898 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9812 11:08:55.166617 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9813 11:08:55.173046 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9814 11:08:55.176580 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9815 11:08:55.183140 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9816 11:08:55.186196 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9817 11:08:55.192816 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9818 11:08:55.196079 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9819 11:08:55.202452 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9820 11:08:55.205677 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9821 11:08:55.209078 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9822 11:08:55.216569 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9823 11:08:55.218761 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9824 11:08:55.225593 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9825 11:08:55.229102 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9826 11:08:55.235694 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9827 11:08:55.238853 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9828 11:08:55.245142 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9829 11:08:55.248298 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9830 11:08:55.251996 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9831 11:08:55.258259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9832 11:08:55.261709 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9833 11:08:55.268320 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9834 11:08:55.271608 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9835 11:08:55.277833 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9836 11:08:55.281310 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9837 11:08:55.284939 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9838 11:08:55.291616 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9839 11:08:55.294846 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9840 11:08:55.301263 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9841 11:08:55.304263 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9842 11:08:55.311038 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9843 11:08:55.314994 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9844 11:08:55.321488 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9845 11:08:55.323909 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9846 11:08:55.327492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9847 11:08:55.334089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9848 11:08:55.337588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9849 11:08:55.344176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9850 11:08:55.347324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9851 11:08:55.353742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9852 11:08:55.357344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9853 11:08:55.363814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9854 11:08:55.366801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9855 11:08:55.373387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9856 11:08:55.376913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9857 11:08:55.383266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9858 11:08:55.386567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9859 11:08:55.392957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9860 11:08:55.396464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9861 11:08:55.403137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9862 11:08:55.406239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9863 11:08:55.412855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9864 11:08:55.416034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9865 11:08:55.423017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9866 11:08:55.426015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9867 11:08:55.432333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9868 11:08:55.435634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9869 11:08:55.442460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9870 11:08:55.445369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9871 11:08:55.452058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9872 11:08:55.455879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9873 11:08:55.462143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9874 11:08:55.465564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9875 11:08:55.471858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9876 11:08:55.478594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9877 11:08:55.481752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9878 11:08:55.484889 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9879 11:08:55.488418 INFO: [APUAPC] vio 0
9880 11:08:55.491844 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9881 11:08:55.498791 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9882 11:08:55.502029 INFO: [APUAPC] D0_APC_0: 0x400510
9883 11:08:55.504915 INFO: [APUAPC] D0_APC_1: 0x0
9884 11:08:55.508182 INFO: [APUAPC] D0_APC_2: 0x1540
9885 11:08:55.508263 INFO: [APUAPC] D0_APC_3: 0x0
9886 11:08:55.514759 INFO: [APUAPC] D1_APC_0: 0xffffffff
9887 11:08:55.518066 INFO: [APUAPC] D1_APC_1: 0xffffffff
9888 11:08:55.521230 INFO: [APUAPC] D1_APC_2: 0x3fffff
9889 11:08:55.521311 INFO: [APUAPC] D1_APC_3: 0x0
9890 11:08:55.528391 INFO: [APUAPC] D2_APC_0: 0xffffffff
9891 11:08:55.531027 INFO: [APUAPC] D2_APC_1: 0xffffffff
9892 11:08:55.534161 INFO: [APUAPC] D2_APC_2: 0x3fffff
9893 11:08:55.534274 INFO: [APUAPC] D2_APC_3: 0x0
9894 11:08:55.541330 INFO: [APUAPC] D3_APC_0: 0xffffffff
9895 11:08:55.544485 INFO: [APUAPC] D3_APC_1: 0xffffffff
9896 11:08:55.547533 INFO: [APUAPC] D3_APC_2: 0x3fffff
9897 11:08:55.547655 INFO: [APUAPC] D3_APC_3: 0x0
9898 11:08:55.550560 INFO: [APUAPC] D4_APC_0: 0xffffffff
9899 11:08:55.557175 INFO: [APUAPC] D4_APC_1: 0xffffffff
9900 11:08:55.560673 INFO: [APUAPC] D4_APC_2: 0x3fffff
9901 11:08:55.560795 INFO: [APUAPC] D4_APC_3: 0x0
9902 11:08:55.563787 INFO: [APUAPC] D5_APC_0: 0xffffffff
9903 11:08:55.567499 INFO: [APUAPC] D5_APC_1: 0xffffffff
9904 11:08:55.570666 INFO: [APUAPC] D5_APC_2: 0x3fffff
9905 11:08:55.573590 INFO: [APUAPC] D5_APC_3: 0x0
9906 11:08:55.577160 INFO: [APUAPC] D6_APC_0: 0xffffffff
9907 11:08:55.580195 INFO: [APUAPC] D6_APC_1: 0xffffffff
9908 11:08:55.583977 INFO: [APUAPC] D6_APC_2: 0x3fffff
9909 11:08:55.586797 INFO: [APUAPC] D6_APC_3: 0x0
9910 11:08:55.590224 INFO: [APUAPC] D7_APC_0: 0xffffffff
9911 11:08:55.593532 INFO: [APUAPC] D7_APC_1: 0xffffffff
9912 11:08:55.596666 INFO: [APUAPC] D7_APC_2: 0x3fffff
9913 11:08:55.600181 INFO: [APUAPC] D7_APC_3: 0x0
9914 11:08:55.603566 INFO: [APUAPC] D8_APC_0: 0xffffffff
9915 11:08:55.606570 INFO: [APUAPC] D8_APC_1: 0xffffffff
9916 11:08:55.610342 INFO: [APUAPC] D8_APC_2: 0x3fffff
9917 11:08:55.613432 INFO: [APUAPC] D8_APC_3: 0x0
9918 11:08:55.616467 INFO: [APUAPC] D9_APC_0: 0xffffffff
9919 11:08:55.619705 INFO: [APUAPC] D9_APC_1: 0xffffffff
9920 11:08:55.622917 INFO: [APUAPC] D9_APC_2: 0x3fffff
9921 11:08:55.626360 INFO: [APUAPC] D9_APC_3: 0x0
9922 11:08:55.629994 INFO: [APUAPC] D10_APC_0: 0xffffffff
9923 11:08:55.632720 INFO: [APUAPC] D10_APC_1: 0xffffffff
9924 11:08:55.636177 INFO: [APUAPC] D10_APC_2: 0x3fffff
9925 11:08:55.639758 INFO: [APUAPC] D10_APC_3: 0x0
9926 11:08:55.643124 INFO: [APUAPC] D11_APC_0: 0xffffffff
9927 11:08:55.646194 INFO: [APUAPC] D11_APC_1: 0xffffffff
9928 11:08:55.649722 INFO: [APUAPC] D11_APC_2: 0x3fffff
9929 11:08:55.652557 INFO: [APUAPC] D11_APC_3: 0x0
9930 11:08:55.655814 INFO: [APUAPC] D12_APC_0: 0xffffffff
9931 11:08:55.659037 INFO: [APUAPC] D12_APC_1: 0xffffffff
9932 11:08:55.665856 INFO: [APUAPC] D12_APC_2: 0x3fffff
9933 11:08:55.665979 INFO: [APUAPC] D12_APC_3: 0x0
9934 11:08:55.668938 INFO: [APUAPC] D13_APC_0: 0xffffffff
9935 11:08:55.675840 INFO: [APUAPC] D13_APC_1: 0xffffffff
9936 11:08:55.678980 INFO: [APUAPC] D13_APC_2: 0x3fffff
9937 11:08:55.679103 INFO: [APUAPC] D13_APC_3: 0x0
9938 11:08:55.682533 INFO: [APUAPC] D14_APC_0: 0xffffffff
9939 11:08:55.688872 INFO: [APUAPC] D14_APC_1: 0xffffffff
9940 11:08:55.692696 INFO: [APUAPC] D14_APC_2: 0x3fffff
9941 11:08:55.692817 INFO: [APUAPC] D14_APC_3: 0x0
9942 11:08:55.698686 INFO: [APUAPC] D15_APC_0: 0xffffffff
9943 11:08:55.702055 INFO: [APUAPC] D15_APC_1: 0xffffffff
9944 11:08:55.705506 INFO: [APUAPC] D15_APC_2: 0x3fffff
9945 11:08:55.708464 INFO: [APUAPC] D15_APC_3: 0x0
9946 11:08:55.708586 INFO: [APUAPC] APC_CON: 0x4
9947 11:08:55.712114 INFO: [NOCDAPC] D0_APC_0: 0x0
9948 11:08:55.715202 INFO: [NOCDAPC] D0_APC_1: 0x0
9949 11:08:55.718914 INFO: [NOCDAPC] D1_APC_0: 0x0
9950 11:08:55.721425 INFO: [NOCDAPC] D1_APC_1: 0xfff
9951 11:08:55.724794 INFO: [NOCDAPC] D2_APC_0: 0x0
9952 11:08:55.728477 INFO: [NOCDAPC] D2_APC_1: 0xfff
9953 11:08:55.731514 INFO: [NOCDAPC] D3_APC_0: 0x0
9954 11:08:55.734838 INFO: [NOCDAPC] D3_APC_1: 0xfff
9955 11:08:55.738215 INFO: [NOCDAPC] D4_APC_0: 0x0
9956 11:08:55.741681 INFO: [NOCDAPC] D4_APC_1: 0xfff
9957 11:08:55.741802 INFO: [NOCDAPC] D5_APC_0: 0x0
9958 11:08:55.745253 INFO: [NOCDAPC] D5_APC_1: 0xfff
9959 11:08:55.748201 INFO: [NOCDAPC] D6_APC_0: 0x0
9960 11:08:55.751241 INFO: [NOCDAPC] D6_APC_1: 0xfff
9961 11:08:55.754395 INFO: [NOCDAPC] D7_APC_0: 0x0
9962 11:08:55.757740 INFO: [NOCDAPC] D7_APC_1: 0xfff
9963 11:08:55.761204 INFO: [NOCDAPC] D8_APC_0: 0x0
9964 11:08:55.764135 INFO: [NOCDAPC] D8_APC_1: 0xfff
9965 11:08:55.767665 INFO: [NOCDAPC] D9_APC_0: 0x0
9966 11:08:55.770983 INFO: [NOCDAPC] D9_APC_1: 0xfff
9967 11:08:55.774329 INFO: [NOCDAPC] D10_APC_0: 0x0
9968 11:08:55.777613 INFO: [NOCDAPC] D10_APC_1: 0xfff
9969 11:08:55.780407 INFO: [NOCDAPC] D11_APC_0: 0x0
9970 11:08:55.784123 INFO: [NOCDAPC] D11_APC_1: 0xfff
9971 11:08:55.784205 INFO: [NOCDAPC] D12_APC_0: 0x0
9972 11:08:55.788023 INFO: [NOCDAPC] D12_APC_1: 0xfff
9973 11:08:55.790533 INFO: [NOCDAPC] D13_APC_0: 0x0
9974 11:08:55.794426 INFO: [NOCDAPC] D13_APC_1: 0xfff
9975 11:08:55.797296 INFO: [NOCDAPC] D14_APC_0: 0x0
9976 11:08:55.800313 INFO: [NOCDAPC] D14_APC_1: 0xfff
9977 11:08:55.804023 INFO: [NOCDAPC] D15_APC_0: 0x0
9978 11:08:55.806980 INFO: [NOCDAPC] D15_APC_1: 0xfff
9979 11:08:55.810234 INFO: [NOCDAPC] APC_CON: 0x4
9980 11:08:55.813604 INFO: [APUAPC] set_apusys_apc done
9981 11:08:55.816828 INFO: [DEVAPC] devapc_init done
9982 11:08:55.820171 INFO: GICv3 without legacy support detected.
9983 11:08:55.823589 INFO: ARM GICv3 driver initialized in EL3
9984 11:08:55.829978 INFO: Maximum SPI INTID supported: 639
9985 11:08:55.833897 INFO: BL31: Initializing runtime services
9986 11:08:55.839883 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9987 11:08:55.839966 INFO: SPM: enable CPC mode
9988 11:08:55.846407 INFO: mcdi ready for mcusys-off-idle and system suspend
9989 11:08:55.849793 INFO: BL31: Preparing for EL3 exit to normal world
9990 11:08:55.852720 INFO: Entry point address = 0x80000000
9991 11:08:55.856417 INFO: SPSR = 0x8
9992 11:08:55.862222
9993 11:08:55.862304
9994 11:08:55.862370
9995 11:08:55.863073 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9996 11:08:55.863176 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9997 11:08:55.863256 Setting prompt string to ['asurada:']
9998 11:08:55.863335 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9999 11:08:55.865635 Starting depthcharge on Spherion...
10000 11:08:55.865718
10001 11:08:55.865784 Wipe memory regions:
10002 11:08:55.865845
10003 11:08:55.868760 [0x00000040000000, 0x00000054600000)
10004 11:08:55.990842
10005 11:08:55.990968 [0x00000054660000, 0x00000080000000)
10006 11:08:56.251812
10007 11:08:56.251963 [0x000000821a7280, 0x000000ffe64000)
10008 11:08:56.996198
10009 11:08:56.996349 [0x00000100000000, 0x00000240000000)
10010 11:08:58.886845
10011 11:08:58.889755 Initializing XHCI USB controller at 0x11200000.
10012 11:08:59.927831
10013 11:08:59.930623 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10014 11:08:59.930710
10015 11:08:59.930775
10016 11:08:59.930836
10017 11:08:59.931116 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10019 11:09:00.031435 asurada: tftpboot 192.168.201.1 12925673/tftp-deploy-ldkp6nhv/kernel/image.itb 12925673/tftp-deploy-ldkp6nhv/kernel/cmdline
10020 11:09:00.031553 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10021 11:09:00.031636 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10022 11:09:00.036938 tftpboot 192.168.201.1 12925673/tftp-deploy-ldkp6nhv/kernel/image.itp-deploy-ldkp6nhv/kernel/cmdline
10023 11:09:00.037021
10024 11:09:00.037086 Waiting for link
10025 11:09:00.196446
10026 11:09:00.196578 R8152: Initializing
10027 11:09:00.196646
10028 11:09:00.199615 Version 6 (ocp_data = 5c30)
10029 11:09:00.199696
10030 11:09:00.203011 R8152: Done initializing
10031 11:09:00.203092
10032 11:09:00.203156 Adding net device
10033 11:09:02.058535
10034 11:09:02.058686 done.
10035 11:09:02.058752
10036 11:09:02.058812 MAC: 00:24:32:30:7c:7b
10037 11:09:02.058870
10038 11:09:02.062411 Sending DHCP discover... done.
10039 11:09:02.062493
10040 11:09:02.065303 Waiting for reply... done.
10041 11:09:02.065386
10042 11:09:02.068599 Sending DHCP request... done.
10043 11:09:02.068680
10044 11:09:02.073924 Waiting for reply... done.
10045 11:09:02.074004
10046 11:09:02.074069 My ip is 192.168.201.14
10047 11:09:02.074128
10048 11:09:02.076910 The DHCP server ip is 192.168.201.1
10049 11:09:02.076991
10050 11:09:02.083969 TFTP server IP predefined by user: 192.168.201.1
10051 11:09:02.084051
10052 11:09:02.090341 Bootfile predefined by user: 12925673/tftp-deploy-ldkp6nhv/kernel/image.itb
10053 11:09:02.090423
10054 11:09:02.093194 Sending tftp read request... done.
10055 11:09:02.093277
10056 11:09:02.097392 Waiting for the transfer...
10057 11:09:02.097480
10058 11:09:02.673871 00000000 ################################################################
10059 11:09:02.674031
10060 11:09:03.250988 00080000 ################################################################
10061 11:09:03.251133
10062 11:09:03.831966 00100000 ################################################################
10063 11:09:03.832180
10064 11:09:04.413868 00180000 ################################################################
10065 11:09:04.414077
10066 11:09:04.995446 00200000 ################################################################
10067 11:09:04.995592
10068 11:09:05.575271 00280000 ################################################################
10069 11:09:05.575452
10070 11:09:06.156198 00300000 ################################################################
10071 11:09:06.156348
10072 11:09:06.709499 00380000 ################################################################
10073 11:09:06.709649
10074 11:09:07.266971 00400000 ################################################################
10075 11:09:07.267119
10076 11:09:07.836853 00480000 ################################################################
10077 11:09:07.837002
10078 11:09:08.400776 00500000 ################################################################
10079 11:09:08.400927
10080 11:09:08.982183 00580000 ################################################################
10081 11:09:08.982396
10082 11:09:09.548669 00600000 ################################################################
10083 11:09:09.548883
10084 11:09:10.120317 00680000 ################################################################
10085 11:09:10.120522
10086 11:09:10.690524 00700000 ################################################################
10087 11:09:10.690701
10088 11:09:11.259960 00780000 ################################################################
10089 11:09:11.260174
10090 11:09:11.833700 00800000 ################################################################
10091 11:09:11.833853
10092 11:09:12.386313 00880000 ################################################################
10093 11:09:12.386463
10094 11:09:12.934416 00900000 ################################################################
10095 11:09:12.934575
10096 11:09:13.512918 00980000 ################################################################
10097 11:09:13.513069
10098 11:09:14.095933 00a00000 ################################################################
10099 11:09:14.096084
10100 11:09:14.665336 00a80000 ################################################################
10101 11:09:14.665541
10102 11:09:15.248242 00b00000 ################################################################
10103 11:09:15.248412
10104 11:09:15.786009 00b80000 ################################################################
10105 11:09:15.786205
10106 11:09:16.328916 00c00000 ################################################################
10107 11:09:16.329117
10108 11:09:16.861812 00c80000 ################################################################
10109 11:09:16.862005
10110 11:09:17.423625 00d00000 ################################################################
10111 11:09:17.423773
10112 11:09:17.997315 00d80000 ################################################################
10113 11:09:17.997502
10114 11:09:18.563796 00e00000 ################################################################
10115 11:09:18.564017
10116 11:09:19.146787 00e80000 ################################################################
10117 11:09:19.146955
10118 11:09:19.726794 00f00000 ################################################################
10119 11:09:19.726948
10120 11:09:20.310007 00f80000 ################################################################
10121 11:09:20.310157
10122 11:09:20.895909 01000000 ################################################################
10123 11:09:20.896087
10124 11:09:21.477624 01080000 ################################################################
10125 11:09:21.477782
10126 11:09:22.062807 01100000 ################################################################
10127 11:09:22.062958
10128 11:09:22.617619 01180000 ################################################################
10129 11:09:22.617839
10130 11:09:23.204628 01200000 ################################################################
10131 11:09:23.204786
10132 11:09:23.787819 01280000 ################################################################
10133 11:09:23.787973
10134 11:09:24.359630 01300000 ################################################################
10135 11:09:24.359785
10136 11:09:24.947398 01380000 ################################################################
10137 11:09:24.947553
10138 11:09:25.528159 01400000 ################################################################
10139 11:09:25.528313
10140 11:09:26.100773 01480000 ################################################################
10141 11:09:26.101005
10142 11:09:26.689812 01500000 ################################################################
10143 11:09:26.690070
10144 11:09:27.282217 01580000 ################################################################
10145 11:09:27.282380
10146 11:09:27.862817 01600000 ################################################################
10147 11:09:27.862984
10148 11:09:28.432779 01680000 ################################################################
10149 11:09:28.432936
10150 11:09:29.019761 01700000 ################################################################
10151 11:09:29.019987
10152 11:09:29.604152 01780000 ################################################################
10153 11:09:29.604372
10154 11:09:30.199404 01800000 ################################################################
10155 11:09:30.199554
10156 11:09:30.787311 01880000 ################################################################
10157 11:09:30.787549
10158 11:09:31.334041 01900000 ################################################################
10159 11:09:31.334237
10160 11:09:31.900968 01980000 ################################################################
10161 11:09:31.901167
10162 11:09:32.465897 01a00000 ################################################################
10163 11:09:32.466095
10164 11:09:33.026511 01a80000 ################################################################
10165 11:09:33.026704
10166 11:09:33.595734 01b00000 ################################################################
10167 11:09:33.595928
10168 11:09:34.169703 01b80000 ################################################################
10169 11:09:34.169901
10170 11:09:34.733976 01c00000 ################################################################
10171 11:09:34.734131
10172 11:09:35.307101 01c80000 ################################################################
10173 11:09:35.307281
10174 11:09:35.861439 01d00000 ################################################################
10175 11:09:35.861656
10176 11:09:36.432228 01d80000 ################################################################
10177 11:09:36.432378
10178 11:09:37.011692 01e00000 ################################################################
10179 11:09:37.011903
10180 11:09:37.586191 01e80000 ################################################################
10181 11:09:37.586400
10182 11:09:38.134090 01f00000 ################################################################
10183 11:09:38.134227
10184 11:09:38.698392 01f80000 ################################################################
10185 11:09:38.698566
10186 11:09:39.255127 02000000 ################################################################
10187 11:09:39.255300
10188 11:09:39.828317 02080000 ################################################################
10189 11:09:39.828468
10190 11:09:40.404126 02100000 ################################################################
10191 11:09:40.404271
10192 11:09:40.969930 02180000 ################################################################
10193 11:09:40.970080
10194 11:09:41.537347 02200000 ################################################################
10195 11:09:41.537505
10196 11:09:42.103189 02280000 ################################################################
10197 11:09:42.103353
10198 11:09:42.676749 02300000 ################################################################
10199 11:09:42.676881
10200 11:09:43.250253 02380000 ################################################################
10201 11:09:43.250389
10202 11:09:43.834903 02400000 ################################################################
10203 11:09:43.835043
10204 11:09:44.419044 02480000 ################################################################
10205 11:09:44.419185
10206 11:09:45.007168 02500000 ################################################################
10207 11:09:45.007312
10208 11:09:45.597045 02580000 ################################################################
10209 11:09:45.597222
10210 11:09:46.144244 02600000 ################################################################
10211 11:09:46.144415
10212 11:09:46.671022 02680000 ################################################################
10213 11:09:46.671194
10214 11:09:47.218554 02700000 ################################################################
10215 11:09:47.218744
10216 11:09:47.749481 02780000 ################################################################
10217 11:09:47.749638
10218 11:09:48.289486 02800000 ################################################################
10219 11:09:48.289695
10220 11:09:48.814988 02880000 ################################################################
10221 11:09:48.815133
10222 11:09:49.341208 02900000 ################################################################
10223 11:09:49.341421
10224 11:09:49.865630 02980000 ################################################################
10225 11:09:49.865838
10226 11:09:50.390813 02a00000 ################################################################
10227 11:09:50.390956
10228 11:09:50.928144 02a80000 ################################################################
10229 11:09:50.928290
10230 11:09:51.465363 02b00000 ################################################################
10231 11:09:51.465544
10232 11:09:51.997654 02b80000 ################################################################
10233 11:09:51.997798
10234 11:09:52.538818 02c00000 ################################################################
10235 11:09:52.538960
10236 11:09:53.085389 02c80000 ################################################################
10237 11:09:53.085572
10238 11:09:53.617963 02d00000 ################################################################
10239 11:09:53.618111
10240 11:09:54.145525 02d80000 ################################################################
10241 11:09:54.145675
10242 11:09:54.683994 02e00000 ################################################################
10243 11:09:54.684143
10244 11:09:55.230957 02e80000 ################################################################
10245 11:09:55.231101
10246 11:09:55.762788 02f00000 ################################################################
10247 11:09:55.762939
10248 11:09:56.294463 02f80000 ################################################################
10249 11:09:56.294614
10250 11:09:56.829384 03000000 ################################################################
10251 11:09:56.829605
10252 11:09:57.359443 03080000 ################################################################
10253 11:09:57.359662
10254 11:09:57.878282 03100000 ################################################################
10255 11:09:57.878459
10256 11:09:58.424817 03180000 ################################################################
10257 11:09:58.424954
10258 11:09:58.959190 03200000 ################################################################
10259 11:09:58.959354
10260 11:09:59.482793 03280000 ################################################################
10261 11:09:59.482958
10262 11:10:00.027215 03300000 ################################################################
10263 11:10:00.027411
10264 11:10:00.555755 03380000 ################################################################
10265 11:10:00.555946
10266 11:10:01.090789 03400000 ################################################################
10267 11:10:01.090932
10268 11:10:01.639765 03480000 ################################################################
10269 11:10:01.639908
10270 11:10:02.168383 03500000 ################################################################
10271 11:10:02.168587
10272 11:10:02.698201 03580000 ################################################################
10273 11:10:02.698403
10274 11:10:03.223796 03600000 ################################################################
10275 11:10:03.223954
10276 11:10:03.753805 03680000 ################################################################
10277 11:10:03.753999
10278 11:10:04.293951 03700000 ################################################################
10279 11:10:04.294124
10280 11:10:04.830031 03780000 ################################################################
10281 11:10:04.830203
10282 11:10:05.356955 03800000 ################################################################
10283 11:10:05.357116
10284 11:10:05.889838 03880000 ################################################################
10285 11:10:05.890029
10286 11:10:06.420336 03900000 ################################################################
10287 11:10:06.420527
10288 11:10:06.960209 03980000 ################################################################
10289 11:10:06.960341
10290 11:10:07.487550 03a00000 ################################################################
10291 11:10:07.487770
10292 11:10:08.015738 03a80000 ################################################################
10293 11:10:08.015915
10294 11:10:08.541389 03b00000 ################################################################
10295 11:10:08.541564
10296 11:10:09.070413 03b80000 ################################################################
10297 11:10:09.070587
10298 11:10:09.597676 03c00000 ################################################################
10299 11:10:09.597886
10300 11:10:10.127463 03c80000 ################################################################
10301 11:10:10.127674
10302 11:10:10.657288 03d00000 ################################################################
10303 11:10:10.657434
10304 11:10:11.199597 03d80000 ################################################################
10305 11:10:11.199759
10306 11:10:11.733719 03e00000 ################################################################
10307 11:10:11.733879
10308 11:10:12.299973 03e80000 ################################################################
10309 11:10:12.300119
10310 11:10:12.898187 03f00000 ################################################################
10311 11:10:12.898364
10312 11:10:13.487859 03f80000 ################################################################
10313 11:10:13.488005
10314 11:10:14.066366 04000000 ################################################################
10315 11:10:14.066526
10316 11:10:14.616367 04080000 ################################################################
10317 11:10:14.616509
10318 11:10:15.164436 04100000 ################################################################
10319 11:10:15.164579
10320 11:10:15.740224 04180000 ################################################################
10321 11:10:15.740368
10322 11:10:16.315336 04200000 ################################################################
10323 11:10:16.315562
10324 11:10:16.880949 04280000 ################################################################
10325 11:10:16.881084
10326 11:10:17.445299 04300000 ################################################################
10327 11:10:17.445435
10328 11:10:18.021567 04380000 ################################################################
10329 11:10:18.021719
10330 11:10:18.610180 04400000 ################################################################
10331 11:10:18.610319
10332 11:10:19.196934 04480000 ################################################################
10333 11:10:19.197084
10334 11:10:19.764233 04500000 ################################################################
10335 11:10:19.764382
10336 11:10:20.026139 04580000 ############################# done.
10337 11:10:20.026281
10338 11:10:20.029546 The bootfile was 73113434 bytes long.
10339 11:10:20.029633
10340 11:10:20.032515 Sending tftp read request... done.
10341 11:10:20.032598
10342 11:10:20.032664 Waiting for the transfer...
10343 11:10:20.032725
10344 11:10:20.036098 00000000 # done.
10345 11:10:20.036184
10346 11:10:20.042464 Command line loaded dynamically from TFTP file: 12925673/tftp-deploy-ldkp6nhv/kernel/cmdline
10347 11:10:20.042549
10348 11:10:20.055695 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10349 11:10:20.055781
10350 11:10:20.059222 Loading FIT.
10351 11:10:20.059304
10352 11:10:20.062419 Image ramdisk-1 has 61006423 bytes.
10353 11:10:20.062502
10354 11:10:20.065708 Image fdt-1 has 47278 bytes.
10355 11:10:20.065790
10356 11:10:20.068799 Image kernel-1 has 12057697 bytes.
10357 11:10:20.068881
10358 11:10:20.075399 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10359 11:10:20.075482
10360 11:10:20.095483 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10361 11:10:20.095571
10362 11:10:20.098843 Choosing best match conf-1 for compat google,spherion-rev2.
10363 11:10:20.103423
10364 11:10:20.107908 Connected to device vid:did:rid of 1ae0:0028:00
10365 11:10:20.114793
10366 11:10:20.118221 tpm_get_response: command 0x17b, return code 0x0
10367 11:10:20.118303
10368 11:10:20.124676 ec_init: CrosEC protocol v3 supported (256, 248)
10369 11:10:20.124758
10370 11:10:20.128102 tpm_cleanup: add release locality here.
10371 11:10:20.128186
10372 11:10:20.131193 Shutting down all USB controllers.
10373 11:10:20.131276
10374 11:10:20.134714 Removing current net device
10375 11:10:20.134796
10376 11:10:20.137820 Exiting depthcharge with code 4 at timestamp: 113541070
10377 11:10:20.137903
10378 11:10:20.144735 LZMA decompressing kernel-1 to 0x821a6718
10379 11:10:20.144824
10380 11:10:20.147893 LZMA decompressing kernel-1 to 0x40000000
10381 11:10:21.648685
10382 11:10:21.648836 jumping to kernel
10383 11:10:21.649372 end: 2.2.4 bootloader-commands (duration 00:01:26) [common]
10384 11:10:21.649469 start: 2.2.5 auto-login-action (timeout 00:02:59) [common]
10385 11:10:21.649545 Setting prompt string to ['Linux version [0-9]']
10386 11:10:21.649614 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10387 11:10:21.649682 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10388 11:10:21.730057
10389 11:10:21.733502 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10390 11:10:21.737099 start: 2.2.5.1 login-action (timeout 00:02:59) [common]
10391 11:10:21.737196 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10392 11:10:21.737268 Setting prompt string to []
10393 11:10:21.737346 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10394 11:10:21.737420 Using line separator: #'\n'#
10395 11:10:21.737481 No login prompt set.
10396 11:10:21.737543 Parsing kernel messages
10397 11:10:21.737599 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10398 11:10:21.737754 [login-action] Waiting for messages, (timeout 00:02:59)
10399 11:10:21.737823 Waiting using forced prompt support (timeout 00:01:30)
10400 11:10:21.756547 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10401 11:10:21.759846 [ 0.000000] random: crng init done
10402 11:10:21.766631 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10403 11:10:21.769559 [ 0.000000] efi: UEFI not found.
10404 11:10:21.776128 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10405 11:10:21.785817 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10406 11:10:21.796020 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10407 11:10:21.802441 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10408 11:10:21.808938 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10409 11:10:21.815996 [ 0.000000] printk: bootconsole [mtk8250] enabled
10410 11:10:21.822381 [ 0.000000] NUMA: No NUMA configuration found
10411 11:10:21.828791 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10412 11:10:21.835280 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10413 11:10:21.835389 [ 0.000000] Zone ranges:
10414 11:10:21.842080 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10415 11:10:21.845108 [ 0.000000] DMA32 empty
10416 11:10:21.851646 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10417 11:10:21.855660 [ 0.000000] Movable zone start for each node
10418 11:10:21.858553 [ 0.000000] Early memory node ranges
10419 11:10:21.865036 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10420 11:10:21.871468 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10421 11:10:21.877921 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10422 11:10:21.884552 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10423 11:10:21.890877 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10424 11:10:21.897765 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10425 11:10:21.954304 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10426 11:10:21.961236 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10427 11:10:21.967809 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10428 11:10:21.971086 [ 0.000000] psci: probing for conduit method from DT.
10429 11:10:21.977728 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10430 11:10:21.981341 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10431 11:10:21.987716 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10432 11:10:21.991001 [ 0.000000] psci: SMC Calling Convention v1.2
10433 11:10:21.997861 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10434 11:10:22.001261 [ 0.000000] Detected VIPT I-cache on CPU0
10435 11:10:22.007121 [ 0.000000] CPU features: detected: GIC system register CPU interface
10436 11:10:22.013928 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10437 11:10:22.020865 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10438 11:10:22.027291 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10439 11:10:22.036854 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10440 11:10:22.043824 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10441 11:10:22.046577 [ 0.000000] alternatives: applying boot alternatives
10442 11:10:22.053273 [ 0.000000] Fallback order for Node 0: 0
10443 11:10:22.059888 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10444 11:10:22.063511 [ 0.000000] Policy zone: Normal
10445 11:10:22.076854 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10446 11:10:22.086100 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10447 11:10:22.098394 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10448 11:10:22.108640 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10449 11:10:22.115111 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10450 11:10:22.118375 <6>[ 0.000000] software IO TLB: area num 8.
10451 11:10:22.174941 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10452 11:10:22.324262 <6>[ 0.000000] Memory: 7907616K/8385536K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 445152K reserved, 32768K cma-reserved)
10453 11:10:22.330518 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10454 11:10:22.337383 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10455 11:10:22.340761 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10456 11:10:22.347711 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10457 11:10:22.353848 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10458 11:10:22.357268 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10459 11:10:22.366791 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10460 11:10:22.373340 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10461 11:10:22.380208 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10462 11:10:22.386923 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10463 11:10:22.389852 <6>[ 0.000000] GICv3: 608 SPIs implemented
10464 11:10:22.393095 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10465 11:10:22.399835 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10466 11:10:22.403192 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10467 11:10:22.409799 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10468 11:10:22.422831 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10469 11:10:22.436315 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10470 11:10:22.442656 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10471 11:10:22.450997 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10472 11:10:22.463978 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10473 11:10:22.470765 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10474 11:10:22.477073 <6>[ 0.009178] Console: colour dummy device 80x25
10475 11:10:22.486821 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10476 11:10:22.494125 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10477 11:10:22.496848 <6>[ 0.029286] LSM: Security Framework initializing
10478 11:10:22.503598 <6>[ 0.034255] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10479 11:10:22.513338 <6>[ 0.042117] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10480 11:10:22.523481 <6>[ 0.051545] cblist_init_generic: Setting adjustable number of callback queues.
10481 11:10:22.529816 <6>[ 0.058989] cblist_init_generic: Setting shift to 3 and lim to 1.
10482 11:10:22.536378 <6>[ 0.065329] cblist_init_generic: Setting adjustable number of callback queues.
10483 11:10:22.542962 <6>[ 0.072757] cblist_init_generic: Setting shift to 3 and lim to 1.
10484 11:10:22.546408 <6>[ 0.079158] rcu: Hierarchical SRCU implementation.
10485 11:10:22.553100 <6>[ 0.084174] rcu: Max phase no-delay instances is 1000.
10486 11:10:22.559851 <6>[ 0.091198] EFI services will not be available.
10487 11:10:22.562858 <6>[ 0.096154] smp: Bringing up secondary CPUs ...
10488 11:10:22.571552 <6>[ 0.101204] Detected VIPT I-cache on CPU1
10489 11:10:22.578769 <6>[ 0.101273] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10490 11:10:22.584769 <6>[ 0.101305] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10491 11:10:22.588392 <6>[ 0.101637] Detected VIPT I-cache on CPU2
10492 11:10:22.594802 <6>[ 0.101684] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10493 11:10:22.604518 <6>[ 0.101700] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10494 11:10:22.607797 <6>[ 0.101961] Detected VIPT I-cache on CPU3
10495 11:10:22.614607 <6>[ 0.102005] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10496 11:10:22.621167 <6>[ 0.102019] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10497 11:10:22.627650 <6>[ 0.102323] CPU features: detected: Spectre-v4
10498 11:10:22.630931 <6>[ 0.102330] CPU features: detected: Spectre-BHB
10499 11:10:22.634412 <6>[ 0.102336] Detected PIPT I-cache on CPU4
10500 11:10:22.640846 <6>[ 0.102393] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10501 11:10:22.650470 <6>[ 0.102409] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10502 11:10:22.653757 <6>[ 0.102705] Detected PIPT I-cache on CPU5
10503 11:10:22.660447 <6>[ 0.102767] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10504 11:10:22.667401 <6>[ 0.102784] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10505 11:10:22.670584 <6>[ 0.103068] Detected PIPT I-cache on CPU6
10506 11:10:22.680608 <6>[ 0.103132] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10507 11:10:22.686762 <6>[ 0.103149] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10508 11:10:22.691119 <6>[ 0.103448] Detected PIPT I-cache on CPU7
10509 11:10:22.696813 <6>[ 0.103514] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10510 11:10:22.703111 <6>[ 0.103530] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10511 11:10:22.706648 <6>[ 0.103577] smp: Brought up 1 node, 8 CPUs
10512 11:10:22.713345 <6>[ 0.245058] SMP: Total of 8 processors activated.
10513 11:10:22.720483 <6>[ 0.249979] CPU features: detected: 32-bit EL0 Support
10514 11:10:22.726355 <6>[ 0.255343] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10515 11:10:22.732778 <6>[ 0.264198] CPU features: detected: Common not Private translations
10516 11:10:22.739508 <6>[ 0.270714] CPU features: detected: CRC32 instructions
10517 11:10:22.746282 <6>[ 0.276065] CPU features: detected: RCpc load-acquire (LDAPR)
10518 11:10:22.749386 <6>[ 0.282025] CPU features: detected: LSE atomic instructions
10519 11:10:22.756051 <6>[ 0.287806] CPU features: detected: Privileged Access Never
10520 11:10:22.762515 <6>[ 0.293586] CPU features: detected: RAS Extension Support
10521 11:10:22.769280 <6>[ 0.299195] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10522 11:10:22.772776 <6>[ 0.306458] CPU: All CPU(s) started at EL2
10523 11:10:22.779085 <6>[ 0.310775] alternatives: applying system-wide alternatives
10524 11:10:22.789874 <6>[ 0.321630] devtmpfs: initialized
10525 11:10:22.805710 <6>[ 0.330660] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10526 11:10:22.812057 <6>[ 0.340619] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10527 11:10:22.818618 <6>[ 0.348648] pinctrl core: initialized pinctrl subsystem
10528 11:10:22.821744 <6>[ 0.355313] DMI not present or invalid.
10529 11:10:22.828284 <6>[ 0.359730] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10530 11:10:22.838453 <6>[ 0.366596] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10531 11:10:22.844761 <6>[ 0.374184] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10532 11:10:22.854862 <6>[ 0.382404] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10533 11:10:22.857875 <6>[ 0.390645] audit: initializing netlink subsys (disabled)
10534 11:10:22.867737 <5>[ 0.396340] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10535 11:10:22.874630 <6>[ 0.397057] thermal_sys: Registered thermal governor 'step_wise'
10536 11:10:22.880782 <6>[ 0.404307] thermal_sys: Registered thermal governor 'power_allocator'
10537 11:10:22.883975 <6>[ 0.410563] cpuidle: using governor menu
10538 11:10:22.890727 <6>[ 0.421528] NET: Registered PF_QIPCRTR protocol family
10539 11:10:22.897259 <6>[ 0.427007] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10540 11:10:22.903845 <6>[ 0.434113] ASID allocator initialised with 32768 entries
10541 11:10:22.907325 <6>[ 0.440689] Serial: AMBA PL011 UART driver
10542 11:10:22.917620 <4>[ 0.449387] Trying to register duplicate clock ID: 134
10543 11:10:22.971648 <6>[ 0.507078] KASLR enabled
10544 11:10:22.986060 <6>[ 0.514820] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10545 11:10:22.992783 <6>[ 0.521834] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10546 11:10:22.999195 <6>[ 0.528323] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10547 11:10:23.006067 <6>[ 0.535331] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10548 11:10:23.012624 <6>[ 0.541820] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10549 11:10:23.019330 <6>[ 0.548824] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10550 11:10:23.026062 <6>[ 0.555310] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10551 11:10:23.032443 <6>[ 0.562313] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10552 11:10:23.035620 <6>[ 0.569835] ACPI: Interpreter disabled.
10553 11:10:23.044100 <6>[ 0.576248] iommu: Default domain type: Translated
10554 11:10:23.051180 <6>[ 0.581360] iommu: DMA domain TLB invalidation policy: strict mode
10555 11:10:23.054123 <5>[ 0.588025] SCSI subsystem initialized
10556 11:10:23.060598 <6>[ 0.592199] usbcore: registered new interface driver usbfs
10557 11:10:23.067210 <6>[ 0.597932] usbcore: registered new interface driver hub
10558 11:10:23.070669 <6>[ 0.603485] usbcore: registered new device driver usb
10559 11:10:23.077776 <6>[ 0.609591] pps_core: LinuxPPS API ver. 1 registered
10560 11:10:23.087946 <6>[ 0.614786] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10561 11:10:23.090807 <6>[ 0.624134] PTP clock support registered
10562 11:10:23.094140 <6>[ 0.628378] EDAC MC: Ver: 3.0.0
10563 11:10:23.101733 <6>[ 0.633542] FPGA manager framework
10564 11:10:23.108134 <6>[ 0.637223] Advanced Linux Sound Architecture Driver Initialized.
10565 11:10:23.111310 <6>[ 0.644000] vgaarb: loaded
10566 11:10:23.117723 <6>[ 0.647155] clocksource: Switched to clocksource arch_sys_counter
10567 11:10:23.121112 <5>[ 0.653597] VFS: Disk quotas dquot_6.6.0
10568 11:10:23.127853 <6>[ 0.657783] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10569 11:10:23.131600 <6>[ 0.664976] pnp: PnP ACPI: disabled
10570 11:10:23.139806 <6>[ 0.671642] NET: Registered PF_INET protocol family
10571 11:10:23.149499 <6>[ 0.677239] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10572 11:10:23.161020 <6>[ 0.689553] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10573 11:10:23.170578 <6>[ 0.698370] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10574 11:10:23.177488 <6>[ 0.706345] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10575 11:10:23.187207 <6>[ 0.715043] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10576 11:10:23.193667 <6>[ 0.724799] TCP: Hash tables configured (established 65536 bind 65536)
10577 11:10:23.200351 <6>[ 0.731662] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10578 11:10:23.210316 <6>[ 0.738863] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10579 11:10:23.216624 <6>[ 0.746563] NET: Registered PF_UNIX/PF_LOCAL protocol family
10580 11:10:23.223642 <6>[ 0.752734] RPC: Registered named UNIX socket transport module.
10581 11:10:23.226656 <6>[ 0.758888] RPC: Registered udp transport module.
10582 11:10:23.233484 <6>[ 0.763820] RPC: Registered tcp transport module.
10583 11:10:23.239837 <6>[ 0.768752] RPC: Registered tcp NFSv4.1 backchannel transport module.
10584 11:10:23.243280 <6>[ 0.775419] PCI: CLS 0 bytes, default 64
10585 11:10:23.246730 <6>[ 0.779788] Unpacking initramfs...
10586 11:10:23.270670 <6>[ 0.799308] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10587 11:10:23.280661 <6>[ 0.807978] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10588 11:10:23.283752 <6>[ 0.816840] kvm [1]: IPA Size Limit: 40 bits
10589 11:10:23.290243 <6>[ 0.821372] kvm [1]: GICv3: no GICV resource entry
10590 11:10:23.293483 <6>[ 0.826390] kvm [1]: disabling GICv2 emulation
10591 11:10:23.300312 <6>[ 0.831080] kvm [1]: GIC system register CPU interface enabled
10592 11:10:23.303791 <6>[ 0.837254] kvm [1]: vgic interrupt IRQ18
10593 11:10:23.310010 <6>[ 0.841611] kvm [1]: VHE mode initialized successfully
10594 11:10:23.316635 <5>[ 0.847975] Initialise system trusted keyrings
10595 11:10:23.323184 <6>[ 0.852785] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10596 11:10:23.330999 <6>[ 0.862895] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10597 11:10:23.337510 <5>[ 0.869291] NFS: Registering the id_resolver key type
10598 11:10:23.340619 <5>[ 0.874589] Key type id_resolver registered
10599 11:10:23.347102 <5>[ 0.879003] Key type id_legacy registered
10600 11:10:23.354195 <6>[ 0.883281] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10601 11:10:23.360440 <6>[ 0.890200] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10602 11:10:23.367024 <6>[ 0.897900] 9p: Installing v9fs 9p2000 file system support
10603 11:10:23.404584 <5>[ 0.935864] Key type asymmetric registered
10604 11:10:23.407079 <5>[ 0.940197] Asymmetric key parser 'x509' registered
10605 11:10:23.417182 <6>[ 0.945339] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10606 11:10:23.420419 <6>[ 0.952956] io scheduler mq-deadline registered
10607 11:10:23.423463 <6>[ 0.957743] io scheduler kyber registered
10608 11:10:23.442684 <6>[ 0.974809] EINJ: ACPI disabled.
10609 11:10:23.475259 <4>[ 1.000556] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 11:10:23.484708 <4>[ 1.011263] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 11:10:23.500404 <6>[ 1.032553] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10612 11:10:23.509098 <6>[ 1.040763] printk: console [ttyS0] disabled
10613 11:10:23.536637 <6>[ 1.065390] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10614 11:10:23.543263 <6>[ 1.074863] printk: console [ttyS0] enabled
10615 11:10:23.546762 <6>[ 1.074863] printk: console [ttyS0] enabled
10616 11:10:23.553536 <6>[ 1.083757] printk: bootconsole [mtk8250] disabled
10617 11:10:23.556906 <6>[ 1.083757] printk: bootconsole [mtk8250] disabled
10618 11:10:23.563302 <6>[ 1.095073] SuperH (H)SCI(F) driver initialized
10619 11:10:23.566832 <6>[ 1.100363] msm_serial: driver initialized
10620 11:10:23.580793 <6>[ 1.109401] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10621 11:10:23.590410 <6>[ 1.117969] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10622 11:10:23.597103 <6>[ 1.126509] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10623 11:10:23.607123 <6>[ 1.135138] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10624 11:10:23.617133 <6>[ 1.143862] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10625 11:10:23.623517 <6>[ 1.152577] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10626 11:10:23.633395 <6>[ 1.161127] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10627 11:10:23.640282 <6>[ 1.169935] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10628 11:10:23.649717 <6>[ 1.178477] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10629 11:10:23.662380 <6>[ 1.194155] loop: module loaded
10630 11:10:23.668420 <6>[ 1.200222] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10631 11:10:23.691998 <4>[ 1.223878] mtk-pmic-keys: Failed to locate of_node [id: -1]
10632 11:10:23.698814 <6>[ 1.230972] megasas: 07.719.03.00-rc1
10633 11:10:23.708348 <6>[ 1.240633] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10634 11:10:23.718504 <6>[ 1.250528] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10635 11:10:23.735085 <6>[ 1.267137] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10636 11:10:23.791371 <6>[ 1.317129] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10637 11:10:25.955256 <6>[ 3.487721] Freeing initrd memory: 59572K
10638 11:10:25.967277 <6>[ 3.499550] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10639 11:10:25.978152 <6>[ 3.510332] tun: Universal TUN/TAP device driver, 1.6
10640 11:10:25.981644 <6>[ 3.516392] thunder_xcv, ver 1.0
10641 11:10:25.984576 <6>[ 3.519895] thunder_bgx, ver 1.0
10642 11:10:25.987824 <6>[ 3.523389] nicpf, ver 1.0
10643 11:10:25.998522 <6>[ 3.527407] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10644 11:10:26.001705 <6>[ 3.534881] hns3: Copyright (c) 2017 Huawei Corporation.
10645 11:10:26.008121 <6>[ 3.540471] hclge is initializing
10646 11:10:26.011976 <6>[ 3.544047] e1000: Intel(R) PRO/1000 Network Driver
10647 11:10:26.018595 <6>[ 3.549176] e1000: Copyright (c) 1999-2006 Intel Corporation.
10648 11:10:26.021832 <6>[ 3.555193] e1000e: Intel(R) PRO/1000 Network Driver
10649 11:10:26.027957 <6>[ 3.560409] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10650 11:10:26.034865 <6>[ 3.566594] igb: Intel(R) Gigabit Ethernet Network Driver
10651 11:10:26.041504 <6>[ 3.572243] igb: Copyright (c) 2007-2014 Intel Corporation.
10652 11:10:26.047990 <6>[ 3.578096] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10653 11:10:26.054758 <6>[ 3.584615] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10654 11:10:26.057838 <6>[ 3.591077] sky2: driver version 1.30
10655 11:10:26.064537 <6>[ 3.596062] VFIO - User Level meta-driver version: 0.3
10656 11:10:26.071836 <6>[ 3.604328] usbcore: registered new interface driver usb-storage
10657 11:10:26.078309 <6>[ 3.610771] usbcore: registered new device driver onboard-usb-hub
10658 11:10:26.087396 <6>[ 3.619957] mt6397-rtc mt6359-rtc: registered as rtc0
10659 11:10:26.097518 <6>[ 3.625423] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:10:26 UTC (1709464226)
10660 11:10:26.100539 <6>[ 3.634985] i2c_dev: i2c /dev entries driver
10661 11:10:26.117875 <6>[ 3.646778] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10662 11:10:26.138560 <6>[ 3.670779] cpu cpu0: EM: created perf domain
10663 11:10:26.141599 <6>[ 3.675693] cpu cpu4: EM: created perf domain
10664 11:10:26.148830 <6>[ 3.681282] sdhci: Secure Digital Host Controller Interface driver
10665 11:10:26.155694 <6>[ 3.687716] sdhci: Copyright(c) Pierre Ossman
10666 11:10:26.161853 <6>[ 3.692674] Synopsys Designware Multimedia Card Interface Driver
10667 11:10:26.168437 <6>[ 3.699321] sdhci-pltfm: SDHCI platform and OF driver helper
10668 11:10:26.171722 <6>[ 3.699384] mmc0: CQHCI version 5.10
10669 11:10:26.178526 <6>[ 3.709624] ledtrig-cpu: registered to indicate activity on CPUs
10670 11:10:26.185153 <6>[ 3.716647] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10671 11:10:26.191923 <6>[ 3.723710] usbcore: registered new interface driver usbhid
10672 11:10:26.195042 <6>[ 3.729533] usbhid: USB HID core driver
10673 11:10:26.205227 <6>[ 3.733745] spi_master spi0: will run message pump with realtime priority
10674 11:10:26.246755 <6>[ 3.772792] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10675 11:10:26.265486 <6>[ 3.787806] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10676 11:10:26.269010 <6>[ 3.802739] mmc0: Command Queue Engine enabled
10677 11:10:26.275560 <6>[ 3.802806] cros-ec-spi spi0.0: Chrome EC device registered
10678 11:10:26.282428 <6>[ 3.807478] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10679 11:10:26.288696 <6>[ 3.820718] mmcblk0: mmc0:0001 DA4128 116 GiB
10680 11:10:26.300732 <6>[ 3.832917] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10681 11:10:26.310463 <6>[ 3.837697] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10682 11:10:26.317304 <6>[ 3.840301] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10683 11:10:26.320166 <6>[ 3.849359] NET: Registered PF_PACKET protocol family
10684 11:10:26.326857 <6>[ 3.854100] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10685 11:10:26.330321 <6>[ 3.858730] 9pnet: Installing 9P2000 support
10686 11:10:26.336822 <6>[ 3.864505] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10687 11:10:26.343287 <5>[ 3.868434] Key type dns_resolver registered
10688 11:10:26.346684 <6>[ 3.879893] registered taskstats version 1
10689 11:10:26.353416 <5>[ 3.884279] Loading compiled-in X.509 certificates
10690 11:10:26.386781 <4>[ 3.912132] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10691 11:10:26.396110 <4>[ 3.923021] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10692 11:10:26.402981 <3>[ 3.933565] debugfs: File 'uA_load' in directory '/' already present!
10693 11:10:26.409564 <3>[ 3.940328] debugfs: File 'min_uV' in directory '/' already present!
10694 11:10:26.415990 <3>[ 3.946958] debugfs: File 'max_uV' in directory '/' already present!
10695 11:10:26.422638 <3>[ 3.953583] debugfs: File 'constraint_flags' in directory '/' already present!
10696 11:10:26.434026 <3>[ 3.963108] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10697 11:10:26.443956 <6>[ 3.976184] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10698 11:10:26.450496 <6>[ 3.983053] xhci-mtk 11200000.usb: xHCI Host Controller
10699 11:10:26.457426 <6>[ 3.988548] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10700 11:10:26.467551 <6>[ 3.996395] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10701 11:10:26.474118 <6>[ 4.005826] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10702 11:10:26.480785 <6>[ 4.011906] xhci-mtk 11200000.usb: xHCI Host Controller
10703 11:10:26.487160 <6>[ 4.017389] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10704 11:10:26.493535 <6>[ 4.025045] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10705 11:10:26.500000 <6>[ 4.032701] hub 1-0:1.0: USB hub found
10706 11:10:26.503304 <6>[ 4.036729] hub 1-0:1.0: 1 port detected
10707 11:10:26.513750 <6>[ 4.041017] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10708 11:10:26.516793 <6>[ 4.049660] hub 2-0:1.0: USB hub found
10709 11:10:26.520286 <6>[ 4.053685] hub 2-0:1.0: 1 port detected
10710 11:10:26.528795 <6>[ 4.061377] mtk-msdc 11f70000.mmc: Got CD GPIO
10711 11:10:26.539156 <6>[ 4.068405] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10712 11:10:26.546046 <6>[ 4.076429] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10713 11:10:26.555718 <4>[ 4.084358] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10714 11:10:26.565488 <6>[ 4.093882] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10715 11:10:26.572242 <6>[ 4.101959] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10716 11:10:26.582705 <6>[ 4.110098] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10717 11:10:26.589063 <6>[ 4.118027] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10718 11:10:26.595246 <6>[ 4.125845] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10719 11:10:26.605042 <6>[ 4.133661] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10720 11:10:26.615166 <6>[ 4.144346] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10721 11:10:26.625319 <6>[ 4.152728] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10722 11:10:26.631538 <6>[ 4.161066] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10723 11:10:26.641770 <6>[ 4.169407] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10724 11:10:26.648053 <6>[ 4.177744] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10725 11:10:26.657987 <6>[ 4.186081] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10726 11:10:26.665130 <6>[ 4.194418] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10727 11:10:26.674853 <6>[ 4.202755] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10728 11:10:26.681231 <6>[ 4.211094] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10729 11:10:26.691274 <6>[ 4.219431] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10730 11:10:26.697742 <6>[ 4.227770] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10731 11:10:26.708241 <6>[ 4.236117] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10732 11:10:26.714215 <6>[ 4.244454] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10733 11:10:26.724142 <6>[ 4.252791] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10734 11:10:26.730843 <6>[ 4.261129] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10735 11:10:26.737828 <6>[ 4.269918] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10736 11:10:26.744413 <6>[ 4.277084] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10737 11:10:26.751233 <6>[ 4.283852] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10738 11:10:26.761457 <6>[ 4.290612] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10739 11:10:26.768492 <6>[ 4.297547] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10740 11:10:26.774927 <6>[ 4.304390] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10741 11:10:26.784747 <6>[ 4.313518] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10742 11:10:26.794829 <6>[ 4.322639] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10743 11:10:26.804369 <6>[ 4.331933] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10744 11:10:26.814838 <6>[ 4.341402] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10745 11:10:26.821075 <6>[ 4.350869] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10746 11:10:26.831003 <6>[ 4.359988] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10747 11:10:26.840493 <6>[ 4.369454] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10748 11:10:26.850861 <6>[ 4.378573] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10749 11:10:26.860812 <6>[ 4.387866] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10750 11:10:26.870473 <6>[ 4.398026] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10751 11:10:26.880954 <6>[ 4.409971] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10752 11:10:26.910259 <6>[ 4.439651] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10753 11:10:26.938762 <6>[ 4.470842] hub 2-1:1.0: USB hub found
10754 11:10:26.941463 <6>[ 4.475300] hub 2-1:1.0: 3 ports detected
10755 11:10:26.950133 <6>[ 4.482627] hub 2-1:1.0: USB hub found
10756 11:10:26.953334 <6>[ 4.486975] hub 2-1:1.0: 3 ports detected
10757 11:10:27.062419 <6>[ 4.591449] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10758 11:10:27.216415 <6>[ 4.749033] hub 1-1:1.0: USB hub found
10759 11:10:27.220400 <6>[ 4.753489] hub 1-1:1.0: 4 ports detected
10760 11:10:27.229183 <6>[ 4.761378] hub 1-1:1.0: USB hub found
10761 11:10:27.232069 <6>[ 4.765726] hub 1-1:1.0: 4 ports detected
10762 11:10:27.302193 <6>[ 4.831555] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10763 11:10:27.554264 <6>[ 5.083453] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10764 11:10:27.686990 <6>[ 5.219205] hub 1-1.4:1.0: USB hub found
10765 11:10:27.689728 <6>[ 5.223849] hub 1-1.4:1.0: 2 ports detected
10766 11:10:27.699514 <6>[ 5.231938] hub 1-1.4:1.0: USB hub found
10767 11:10:27.702721 <6>[ 5.236513] hub 1-1.4:1.0: 2 ports detected
10768 11:10:27.997946 <6>[ 5.527453] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10769 11:10:28.190010 <6>[ 5.719403] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10770 11:10:39.183629 <6>[ 16.720404] ALSA device list:
10771 11:10:39.189709 <6>[ 16.723689] No soundcards found.
10772 11:10:39.198690 <6>[ 16.731969] Freeing unused kernel memory: 8448K
10773 11:10:39.201288 <6>[ 16.736876] Run /init as init process
10774 11:10:39.232611 <6>[ 16.766636] NET: Registered PF_INET6 protocol family
10775 11:10:39.239246 <6>[ 16.773162] Segment Routing with IPv6
10776 11:10:39.242732 <6>[ 16.777106] In-situ OAM (IOAM) with IPv6
10777 11:10:39.285446 <30>[ 16.792809] systemd[1]: systemd 252.19-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10778 11:10:39.291992 <30>[ 16.825953] systemd[1]: Detected architecture arm64.
10779 11:10:39.292076
10780 11:10:39.298457 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10781 11:10:39.298540
10782 11:10:39.313427 <30>[ 16.847526] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10783 11:10:39.415702 <30>[ 16.945971] systemd[1]: Queued start job for default target graphical.target.
10784 11:10:39.478643 <30>[ 17.009415] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10785 11:10:39.485366 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10786 11:10:39.505830 <30>[ 17.036692] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10787 11:10:39.515655 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10788 11:10:39.533336 <30>[ 17.063945] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10789 11:10:39.543183 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10790 11:10:39.561937 <30>[ 17.092653] systemd[1]: Created slice user.slice - User and Session Slice.
10791 11:10:39.568771 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10792 11:10:39.588163 <30>[ 17.115564] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10793 11:10:39.594976 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10794 11:10:39.616734 <30>[ 17.144019] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10795 11:10:39.623550 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10796 11:10:39.650639 <30>[ 17.171530] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10797 11:10:39.660643 <30>[ 17.191403] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10798 11:10:39.667376 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10799 11:10:39.685450 <30>[ 17.215937] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10800 11:10:39.695477 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10801 11:10:39.710037 <30>[ 17.243957] systemd[1]: Reached target paths.target - Path Units.
10802 11:10:39.716799 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10803 11:10:39.737719 <30>[ 17.267911] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10804 11:10:39.744282 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10805 11:10:39.757672 <30>[ 17.291436] systemd[1]: Reached target slices.target - Slice Units.
10806 11:10:39.767580 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10807 11:10:39.782216 <30>[ 17.315969] systemd[1]: Reached target swap.target - Swaps.
10808 11:10:39.788667 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10809 11:10:39.809354 <30>[ 17.339965] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10810 11:10:39.819113 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10811 11:10:39.837862 <30>[ 17.368445] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10812 11:10:39.847653 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10813 11:10:39.867205 <30>[ 17.397656] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10814 11:10:39.876677 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10815 11:10:39.893833 <30>[ 17.424227] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10816 11:10:39.903620 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10817 11:10:39.922510 <30>[ 17.452777] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10818 11:10:39.928517 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10819 11:10:39.949594 <30>[ 17.480125] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10820 11:10:39.959790 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10821 11:10:39.977419 <30>[ 17.507941] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10822 11:10:39.987247 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10823 11:10:40.028739 <30>[ 17.559517] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10824 11:10:40.035138 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10825 11:10:40.054454 <30>[ 17.585162] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10826 11:10:40.061461 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10827 11:10:40.082704 <30>[ 17.613539] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10828 11:10:40.089504 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10829 11:10:40.115341 <30>[ 17.639688] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10830 11:10:40.149446 <30>[ 17.680117] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10831 11:10:40.159283 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10832 11:10:40.181896 <30>[ 17.712829] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10833 11:10:40.188881 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10834 11:10:40.214008 <30>[ 17.744671] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10835 11:10:40.224215 Startin<6>[ 17.754104] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10836 11:10:40.230502 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10837 11:10:40.289226 <30>[ 17.820297] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10838 11:10:40.296329 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10839 11:10:40.310749 <30>[ 17.840932] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10840 11:10:40.320336 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10841 11:10:40.381729 <30>[ 17.912301] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10842 11:10:40.387909 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10843 11:10:40.417865 <30>[ 17.948528] systemd[1]: Starting systemd-journald.service - Journal Service...
10844 11:10:40.424312 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10845 11:10:40.457321 <30>[ 17.987977] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10846 11:10:40.463764 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10847 11:10:40.492410 <30>[ 18.019919] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10848 11:10:40.499041 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10849 11:10:40.519268 <30>[ 18.050444] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10850 11:10:40.529694 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10851 11:10:40.565698 <30>[ 18.096111] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10852 11:10:40.571973 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10853 11:10:40.597008 <30>[ 18.127838] systemd[1]: Started systemd-journald.service - Journal Service.
10854 11:10:40.603790 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10855 11:10:40.623244 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10856 11:10:40.642090 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10857 11:10:40.661324 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10858 11:10:40.677850 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10859 11:10:40.698987 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10860 11:10:40.723214 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10861 11:10:40.747521 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10862 11:10:40.772846 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10863 11:10:40.791612 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10864 11:10:40.811542 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10865 11:10:40.831186 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10866 11:10:40.851264 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10867 11:10:40.865321 See 'systemctl status systemd-remount-fs.service' for details.
10868 11:10:40.886160 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10869 11:10:40.907692 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10870 11:10:40.964872 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10871 11:10:40.987046 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10872 11:10:40.998265 <46>[ 18.528909] systemd-journald[191]: Received client request to flush runtime journal.
10873 11:10:41.010415 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10874 11:10:41.036112 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10875 11:10:41.061956 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10876 11:10:41.089928 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10877 11:10:41.114231 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10878 11:10:41.138449 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10879 11:10:41.158126 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10880 11:10:41.178179 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10881 11:10:41.233394 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10882 11:10:41.256363 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10883 11:10:41.272928 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10884 11:10:41.292679 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10885 11:10:41.346160 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10886 11:10:41.370914 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10887 11:10:41.392499 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10888 11:10:41.417036 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10889 11:10:41.436993 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10890 11:10:41.452042 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10891 11:10:41.495824 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10892 11:10:41.517038 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10893 11:10:41.549610 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10894 11:10:41.658576 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10895 11:10:41.678192 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10896 11:10:41.698206 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10897 11:10:41.718385 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10898 11:10:41.738548 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10899 11:10:41.754968 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10900 11:10:41.761880 <6>[ 19.293999] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10901 11:10:41.768466 <6>[ 19.294108] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10902 11:10:41.775322 <6>[ 19.304347] remoteproc remoteproc0: scp is available
10903 11:10:41.781639 <4>[ 19.309958] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10904 11:10:41.791723 <6>[ 19.310296] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10905 11:10:41.801681 <6>[ 19.310311] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10906 11:10:41.804891 <6>[ 19.315786] mc: Linux media interface: v0.10
10907 11:10:41.808103 <6>[ 19.316017] remoteproc remoteproc0: powering up scp
10908 11:10:41.817685 <6>[ 19.316022] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10909 11:10:41.824280 <6>[ 19.316044] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10910 11:10:41.831507 <4>[ 19.323507] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10911 11:10:41.841043 [[0;32m OK [0m] Reached targ<6>[ 19.372891] videodev: Linux video capture interface: v2.00
10912 11:10:41.847846 et [0;1;39msock<6>[ 19.373062] usbcore: registered new device driver r8152-cfgselector
10913 11:10:41.850734 ets.target[0m - Socket Units.
10914 11:10:41.857590 <3>[ 19.388711] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 11:10:41.867621 <6>[ 19.391597] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10916 11:10:41.874082 <3>[ 19.397746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10917 11:10:41.884196 <3>[ 19.413511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10918 11:10:41.890780 <3>[ 19.413589] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10919 11:10:41.900398 <4>[ 19.421924] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10920 11:10:41.903855 <4>[ 19.421924] Fallback method does not support PEC.
10921 11:10:41.910231 <6>[ 19.428528] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10922 11:10:41.917079 <6>[ 19.428536] pci_bus 0000:00: root bus resource [bus 00-ff]
10923 11:10:41.924326 [[0;32m OK [<6>[ 19.428544] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10924 11:10:41.937575 0m] Reached targ<6>[ 19.428549] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10925 11:10:41.944024 et [0;1;39mbasi<6>[ 19.428582] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10926 11:10:41.954646 c.target[0m - B<6>[ 19.428602] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10927 11:10:41.954732 asic System.
10928 11:10:41.958037 <6>[ 19.428681] pci 0000:00:00.0: supports D1 D2
10929 11:10:41.964820 <6>[ 19.428685] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10930 11:10:41.974428 <3>[ 19.429740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10931 11:10:41.981005 <6>[ 19.430254] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10932 11:10:41.987718 <6>[ 19.430377] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10933 11:10:41.994416 <6>[ 19.430409] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10934 11:10:42.004065 <6>[ 19.430430] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10935 11:10:42.011022 <6>[ 19.430449] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10936 11:10:42.014360 <6>[ 19.430568] pci 0000:01:00.0: supports D1 D2
10937 11:10:42.021051 <6>[ 19.430571] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10938 11:10:42.030657 <6>[ 19.441278] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10939 11:10:42.037126 <6>[ 19.441346] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10940 11:10:42.044979 <6>[ 19.441354] remoteproc remoteproc0: remote processor scp is now up
10941 11:10:42.051529 <6>[ 19.443283] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10942 11:10:42.058471 <6>[ 19.443313] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10943 11:10:42.068312 <6>[ 19.443316] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10944 11:10:42.074834 <6>[ 19.443324] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10945 11:10:42.084880 <6>[ 19.443337] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10946 11:10:42.091922 <3>[ 19.450195] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10947 11:10:42.098462 <3>[ 19.450205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10948 11:10:42.108467 <6>[ 19.455942] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10949 11:10:42.115020 <3>[ 19.462507] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 11:10:42.126019 <3>[ 19.464444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10951 11:10:42.129197 <6>[ 19.475741] pci 0000:00:00.0: PCI bridge to [bus 01]
10952 11:10:42.139048 <6>[ 19.477827] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10953 11:10:42.146022 <3>[ 19.483394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10954 11:10:42.155684 <6>[ 19.483431] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10955 11:10:42.163350 <6>[ 19.492230] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10956 11:10:42.169635 <6>[ 19.492367] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10957 11:10:42.176460 <3>[ 19.498564] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10958 11:10:42.186245 <3>[ 19.502150] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 11:10:42.196298 <6>[ 19.503959] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10960 11:10:42.206087 <6>[ 19.504212] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10961 11:10:42.213509 <6>[ 19.506925] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10962 11:10:42.220231 <3>[ 19.513197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10963 11:10:42.230557 <4>[ 19.514618] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10964 11:10:42.236605 <4>[ 19.514628] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10965 11:10:42.246432 <3>[ 19.521635] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10966 11:10:42.253450 <6>[ 19.522598] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10967 11:10:42.259832 <3>[ 19.527657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10968 11:10:42.266232 <3>[ 19.527977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10969 11:10:42.276215 <6>[ 19.538162] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10970 11:10:42.282818 <3>[ 19.542656] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10971 11:10:42.292652 <3>[ 19.542661] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10972 11:10:42.295982 <6>[ 19.543348] Bluetooth: Core ver 2.22
10973 11:10:42.303102 <6>[ 19.543474] NET: Registered PF_BLUETOOTH protocol family
10974 11:10:42.309367 <6>[ 19.543477] Bluetooth: HCI device and connection manager initialized
10975 11:10:42.312518 <6>[ 19.543500] Bluetooth: HCI socket layer initialized
10976 11:10:42.319227 <6>[ 19.543506] Bluetooth: L2CAP socket layer initialized
10977 11:10:42.322833 <6>[ 19.543519] Bluetooth: SCO socket layer initialized
10978 11:10:42.332305 <5>[ 19.553446] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10979 11:10:42.340021 <6>[ 19.554513] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10980 11:10:42.346680 <3>[ 19.554674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10981 11:10:42.356816 <6>[ 19.562484] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10982 11:10:42.363047 <3>[ 19.568564] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10983 11:10:42.372875 <3>[ 19.568613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10984 11:10:42.380081 <5>[ 19.576379] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10985 11:10:42.386643 <5>[ 19.576877] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10986 11:10:42.395847 <4>[ 19.576974] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10987 11:10:42.399329 <6>[ 19.576982] cfg80211: failed to load regulatory.db
10988 11:10:42.412566 <6>[ 19.578375] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10989 11:10:42.415753 <6>[ 19.583723] r8152 2-1.3:1.0 eth0: v1.12.13
10990 11:10:42.422639 <6>[ 19.590755] usbcore: registered new interface driver uvcvideo
10991 11:10:42.429144 <6>[ 19.598984] usbcore: registered new interface driver r8152
10992 11:10:42.435688 <6>[ 19.608020] usbcore: registered new interface driver btusb
10993 11:10:42.442514 <6>[ 19.608712] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10994 11:10:42.452064 <4>[ 19.608723] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10995 11:10:42.458921 <3>[ 19.608731] Bluetooth: hci0: Failed to load firmware file (-2)
10996 11:10:42.465049 <3>[ 19.608734] Bluetooth: hci0: Failed to set up firmware (-2)
10997 11:10:42.474960 <4>[ 19.608735] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10998 11:10:42.482004 <3>[ 19.632083] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10999 11:10:42.491956 <3>[ 19.633904] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 11:10:42.501259 <3>[ 19.634613] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 11:10:42.504892 <6>[ 19.639529] usbcore: registered new interface driver cdc_ether
11002 11:10:42.514970 <3>[ 19.661933] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 11:10:42.521233 <6>[ 19.674839] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11004 11:10:42.527916 <6>[ 19.678464] usbcore: registered new interface driver r8153_ecm
11005 11:10:42.534371 <6>[ 19.686410] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11006 11:10:42.544387 <3>[ 19.703310] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 11:10:42.550958 <6>[ 19.712181] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
11008 11:10:42.553970 <6>[ 19.727342] mt7921e 0000:01:00.0: ASIC revision: 79610010
11009 11:10:42.564419 <3>[ 19.754946] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 11:10:42.574178 <6>[ 19.853840] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11011 11:10:42.574261 <6>[ 19.853840]
11012 11:10:42.583762 <3>[ 19.879457] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11013 11:10:42.590729 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11014 11:10:42.617034 <6>[ 20.147412] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11015 11:10:42.640944 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11016 11:10:42.660032 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11017 11:10:42.677584 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11018 11:10:42.703007 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11019 11:10:42.762115 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11020 11:10:42.785359 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11021 11:10:42.801601 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11022 11:10:42.834942 [[0;32m OK [<46>[ 20.352897] systemd-journald[191]: Data hash table of /var/log/journal/7511cdbeca2141059c257953b873947e/system.journal has a fill level at 75.1 (1538 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11023 11:10:42.851638 0m] Listening on<46>[ 20.375441] systemd-journald[191]: /var/log/journal/7511cdbeca2141059c257953b873947e/system.journal: Journal header limits reached or header out-of-date, rotating.
11024 11:10:42.858354 [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11025 11:10:42.914304 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11026 11:10:42.935355 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11027 11:10:42.953684 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11028 11:10:42.969743 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11029 11:10:42.989247 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11030 11:10:43.038354 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11031 11:10:43.063287 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11032 11:10:43.088330 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11033 11:10:43.142723 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11034 11:10:43.166239 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11035 11:10:43.190587 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11036 11:10:43.241807
11037 11:10:43.241906
11038 11:10:43.245260 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11039 11:10:43.245341
11040 11:10:43.248239 debian-bookworm-arm64 login: root (automatic login)
11041 11:10:43.248321
11042 11:10:43.248385
11043 11:10:43.261346 Linux debian-bookworm-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
11044 11:10:43.261429
11045 11:10:43.267634 The programs included with the Debian GNU/Linux system are free software;
11046 11:10:43.275055 the exact distribution terms for each program are described in the
11047 11:10:43.278041 individual files in /usr/share/doc/*/copyright.
11048 11:10:43.278122
11049 11:10:43.284823 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11050 11:10:43.288346 permitted by applicable law.
11051 11:10:43.288726 Matched prompt #10: / #
11053 11:10:43.288929 Setting prompt string to ['/ #']
11054 11:10:43.289019 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11056 11:10:43.289210 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11057 11:10:43.289294 start: 2.2.6 expect-shell-connection (timeout 00:02:38) [common]
11058 11:10:43.289365 Setting prompt string to ['/ #']
11059 11:10:43.289425 Forcing a shell prompt, looking for ['/ #']
11061 11:10:43.339629 / #
11062 11:10:43.339731 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11063 11:10:43.339804 Waiting using forced prompt support (timeout 00:02:30)
11064 11:10:43.345044
11065 11:10:43.345310 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11066 11:10:43.345400 start: 2.2.7 export-device-env (timeout 00:02:38) [common]
11067 11:10:43.345489 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11068 11:10:43.345574 end: 2.2 depthcharge-retry (duration 00:02:22) [common]
11069 11:10:43.345656 end: 2 depthcharge-action (duration 00:02:22) [common]
11070 11:10:43.345742 start: 3 lava-test-retry (timeout 00:07:13) [common]
11071 11:10:43.345824 start: 3.1 lava-test-shell (timeout 00:07:13) [common]
11072 11:10:43.345898 Using namespace: common
11074 11:10:43.446225 / # #
11075 11:10:43.446356 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11076 11:10:43.451540 #
11077 11:10:43.451803 Using /lava-12925673
11079 11:10:43.552127 / # export SHELL=/bin/sh
11080 11:10:43.552271 <6>[ 21.019547] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11081 11:10:43.557076 export SHELL=/bin/sh
11083 11:10:43.657558 / # . /lava-12925673/environment
11084 11:10:43.662394 . /lava-12925673/environment
11086 11:10:43.762921 / # /lava-12925673/bin/lava-test-runner /lava-12925673/0
11087 11:10:43.763039 Test shell timeout: 10s (minimum of the action and connection timeout)
11088 11:10:43.768422 /lava-12925673/bin/lava-test-runner /lava-12925673/0
11089 11:10:43.794794 + export TESTRUN_ID=0_igt-kms-medi<8>[ 21.328124] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 12925673_1.5.2.3.1>
11090 11:10:43.795057 Received signal: <STARTRUN> 0_igt-kms-mediatek 12925673_1.5.2.3.1
11091 11:10:43.795131 Starting test lava.0_igt-kms-mediatek (12925673_1.5.2.3.1)
11092 11:10:43.795217 Skipping test definition patterns.
11093 11:10:43.797643 atek
11094 11:10:43.800877 + cd /lava-12925673/0/tests/0_igt-kms-mediatek
11095 11:10:43.800959 + cat uuid
11096 11:10:43.804114 + UUID=12925673_1.5.2.3.1
11097 11:10:43.804196 + set +x
11098 11:10:43.820917 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read<8>[ 21.355537] <LAVA_SIGNAL_TESTSET START core_auth>
11099 11:10:43.821175 Received signal: <TESTSET> START core_auth
11100 11:10:43.821253 Starting test_set core_auth
11101 11:10:43.830682 kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11102 11:10:43.843193 <14>[ 21.377343] [IGT] core_auth: executing
11103 11:10:43.849432 IGT-Version: 1.2<14>[ 21.381749] [IGT] core_auth: starting subtest getclient-simple
11104 11:10:43.859244 8-g0830aa7 (aarc<14>[ 21.389332] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11105 11:10:43.862685 h64) (Linux: 6.1<14>[ 21.397592] [IGT] core_auth: exiting, ret=0
11106 11:10:43.866395 .80-cip16 aarch64)
11107 11:10:43.876208 Using IGT_SRANDOM=1709464244 for randomisati<8>[ 21.407871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11108 11:10:43.876291 on
11109 11:10:43.876530 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11111 11:10:43.879381 Starting subtest: getclient-simple
11112 11:10:43.882810 Opened device: /dev/dri/card0
11113 11:10:43.888885 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11114 11:10:43.895774 <14>[ 21.430102] [IGT] core_auth: executing
11115 11:10:43.902405 IGT-Version: 1.2<14>[ 21.434473] [IGT] core_auth: starting subtest getclient-master-drop
11116 11:10:43.912643 8-g0830aa7 (aarc<14>[ 21.442690] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11117 11:10:43.918647 h64) (Linux: 6.1<14>[ 21.451197] [IGT] core_auth: exiting, ret=0
11118 11:10:43.918729 .80-cip16 aarch64)
11119 11:10:43.931878 Using IGT_SRANDOM=1709464244 for randomisati<8>[ 21.461446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11120 11:10:43.931964 on
11121 11:10:43.932201 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11123 11:10:43.935722 Starting subtest: getclient-master-drop
11124 11:10:43.938414 Opened device: /dev/dri/card0
11125 11:10:43.941886 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11126 11:10:43.949376 <14>[ 21.483570] [IGT] core_auth: executing
11127 11:10:43.955720 IGT-Version: 1.2<14>[ 21.487977] [IGT] core_auth: starting subtest basic-auth
11128 11:10:43.962697 8-g0830aa7 (aarc<14>[ 21.494909] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11129 11:10:43.969137 <14>[ 21.502684] [IGT] core_auth: exiting, ret=0
11130 11:10:43.972439 h64) (Linux: 6.1.80-cip16 aarch64)
11131 11:10:43.978769 Using IGT_SR<8>[ 21.511379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11132 11:10:43.979022 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11134 11:10:43.982342 ANDOM=1709464244 for randomisation
11135 11:10:43.985695 Opened device: /dev/dri/card0
11136 11:10:43.988939 Starting subtest: basic-auth
11137 11:10:43.992160 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11138 11:10:43.995427 <14>[ 21.531788] [IGT] core_auth: executing
11139 11:10:44.002040 IGT-Version: 1.2<14>[ 21.536234] [IGT] core_auth: starting subtest many-magics
11140 11:10:44.008708 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11141 11:10:44.018929 Using IGT_SRANDOM=1709464244 for randomisati<14>[ 21.550265] [IGT] core_auth: finished subtest many-magics, SUCCESS
11142 11:10:44.019011 on
11143 11:10:44.025555 Opened devic<14>[ 21.558046] [IGT] core_auth: exiting, ret=0
11144 11:10:44.025637 e: /dev/dri/card0
11145 11:10:44.028871 Starting subtest: many-magics
11146 11:10:44.038588 Reopening devi<8>[ 21.568353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11147 11:10:44.038669 ce failed after 1020 opens
11148 11:10:44.038906 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11150 11:10:44.044931 [1m<8>[ 21.578679] <LAVA_SIGNAL_TESTSET STOP>
11151 11:10:44.045181 Received signal: <TESTSET> STOP
11152 11:10:44.045253 Closing test_set core_auth
11153 11:10:44.048089 Subtest many-magics: SUCCESS (0.007s)[0m
11154 11:10:44.079393 <14>[ 21.613846] [IGT] core_getclient: executing
11155 11:10:44.086271 IGT-Version: 1.2<14>[ 21.618883] [IGT] core_getclient: exiting, ret=0
11156 11:10:44.089453 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11157 11:10:44.099851 Using IGT_SRANDOM=1709464244<8>[ 21.631713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11158 11:10:44.100104 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11160 11:10:44.102543 for randomisation
11161 11:10:44.102623 Opened device: /dev/dri/card0
11162 11:10:44.106145 SUCCESS (0.006s)
11163 11:10:44.148008 <14>[ 21.682026] [IGT] core_getstats: executing
11164 11:10:44.154143 IGT-Version: 1.2<14>[ 21.687099] [IGT] core_getstats: exiting, ret=0
11165 11:10:44.157673 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11166 11:10:44.167176 Using IGT_SRANDOM=1709464244<8>[ 21.698939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11167 11:10:44.167417 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11169 11:10:44.170552 for randomisation
11170 11:10:44.170634 Opened device: /dev/dri/card0
11171 11:10:44.173791 SUCCESS (0.006s)
11172 11:10:44.211644 <14>[ 21.745964] [IGT] core_getversion: executing
11173 11:10:44.217977 IGT-Version: 1.2<14>[ 21.750986] [IGT] core_getversion: exiting, ret=0
11174 11:10:44.221551 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11175 11:10:44.231203 Using IGT_SRANDOM=1709464244<8>[ 21.763843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11176 11:10:44.231483 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11178 11:10:44.234710 for randomisation
11179 11:10:44.237758 Opened device: /dev/dri/card0
11180 11:10:44.237838 SUCCESS (0.006s)
11181 11:10:44.278003 <14>[ 21.812386] [IGT] core_setmaster_vs_auth: executing
11182 11:10:44.284729 IGT-Version: 1.2<14>[ 21.818365] [IGT] core_setmaster_vs_auth: exiting, ret=0
11183 11:10:44.291074 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11184 11:10:44.301003 Using IGT_SRANDOM=1709464244<8>[ 21.830562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11185 11:10:44.301085 for randomisation
11186 11:10:44.301323 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11188 11:10:44.304201 Opened device: /dev/dri/card0
11189 11:10:44.307226 SUCCESS (0.007s)
11190 11:10:44.332258 <8>[ 21.866476] <LAVA_SIGNAL_TESTSET START drm_read>
11191 11:10:44.332517 Received signal: <TESTSET> START drm_read
11192 11:10:44.332586 Starting test_set drm_read
11193 11:10:44.358847 <14>[ 21.893286] [IGT] drm_read: executing
11194 11:10:44.365343 IGT-Version: 1.2<14>[ 21.898198] [IGT] drm_read: exiting, ret=77
11195 11:10:44.368858 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11196 11:10:44.378621 Using IGT_SRANDOM=1709464244<8>[ 21.909507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11197 11:10:44.378704 for randomisation
11198 11:10:44.378942 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11200 11:10:44.382227 Opened device: /dev/dri/card0
11201 11:10:44.388497 No KMS driver or no outputs, pipes: 16, outputs: 0
11202 11:10:44.391706 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11203 11:10:44.406661 <14>[ 21.940879] [IGT] drm_read: executing
11204 11:10:44.413195 IGT-Version: 1.2<14>[ 21.945660] [IGT] drm_read: exiting, ret=77
11205 11:10:44.416561 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11206 11:10:44.426092 Using IGT_SRANDOM=1709464244<8>[ 21.957009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11207 11:10:44.426175 for randomisation
11208 11:10:44.426413 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11210 11:10:44.429391 Opened device: /dev/dri/card0
11211 11:10:44.436448 No KMS driver or no outputs, pipes: 16, outputs: 0
11212 11:10:44.439546 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11213 11:10:44.442705 <14>[ 21.979414] [IGT] drm_read: executing
11214 11:10:44.449509 IGT-Version: 1.2<14>[ 21.983890] [IGT] drm_read: exiting, ret=77
11215 11:10:44.456023 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11216 11:10:44.465675 Using IGT_SRANDOM=1709464244 for randomisati<8>[ 21.996912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11217 11:10:44.465759 on
11218 11:10:44.465997 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11220 11:10:44.468886 Opened device: /dev/dri/card0
11221 11:10:44.472142 No KMS driver or no outputs, pipes: 16, outputs: 0
11222 11:10:44.475406 [1mSubtest empty-block: SKIP (0.000s)[0m
11223 11:10:44.484133 <14>[ 22.018310] [IGT] drm_read: executing
11224 11:10:44.490333 IGT-Version: 1.2<14>[ 22.022820] [IGT] drm_read: exiting, ret=77
11225 11:10:44.493623 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11226 11:10:44.503543 Using IGT_SRANDOM=1709464244<8>[ 22.034868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11227 11:10:44.503625 for randomisation
11228 11:10:44.503862 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11230 11:10:44.507247 Opened device: /dev/dri/card0
11231 11:10:44.513972 No KMS driver or no outputs, pipes: 16, outputs: 0
11232 11:10:44.516642 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11233 11:10:44.520086 <14>[ 22.056490] [IGT] drm_read: executing
11234 11:10:44.527291 IGT-Version: 1.2<14>[ 22.060982] [IGT] drm_read: exiting, ret=77
11235 11:10:44.530453 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11236 11:10:44.543109 Using IGT_SRANDOM=1709464244 for randomisati<8>[ 22.073929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11237 11:10:44.543192 on
11238 11:10:44.543416 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11240 11:10:44.546749 Opened device: /dev/dri/card0
11241 11:10:44.549835 No KMS driver or no outputs, pipes: 16, outputs: 0
11242 11:10:44.556456 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11243 11:10:44.570989 <14>[ 22.105566] [IGT] drm_read: executing
11244 11:10:44.577782 IGT-Version: 1.2<14>[ 22.110345] [IGT] drm_read: exiting, ret=77
11245 11:10:44.581127 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11246 11:10:44.590852 Using IGT_SRANDOM=1709464244<8>[ 22.122351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11247 11:10:44.591107 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11249 11:10:44.594218 for randomisation
11250 11:10:44.594299 Opened device: /dev/dri/card0
11251 11:10:44.600699 No KMS driver or no outputs, pipes: 16, outputs: 0
11252 11:10:44.603817 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11253 11:10:44.611568 <14>[ 22.145769] [IGT] drm_read: executing
11254 11:10:44.617818 IGT-Version: 1.2<14>[ 22.150281] [IGT] drm_read: exiting, ret=77
11255 11:10:44.621299 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11256 11:10:44.631183 Using IGT_SRANDOM=1709464245<8>[ 22.162232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11257 11:10:44.631291 for randomisation
11258 11:10:44.631560 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11260 11:10:44.637866 Opened devic<8>[ 22.172457] <LAVA_SIGNAL_TESTSET STOP>
11261 11:10:44.638117 Received signal: <TESTSET> STOP
11262 11:10:44.638188 Closing test_set drm_read
11263 11:10:44.641100 e: /dev/dri/card0
11264 11:10:44.644203 No KMS driver or no outputs, pipes: 16, outputs: 0
11265 11:10:44.647339 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11266 11:10:44.669531 <8>[ 22.203836] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11267 11:10:44.669784 Received signal: <TESTSET> START kms_addfb_basic
11268 11:10:44.669852 Starting test_set kms_addfb_basic
11269 11:10:44.697688 <14>[ 22.231887] [IGT] kms_addfb_basic: executing
11270 11:10:44.710439 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch6<14>[ 22.241416] [IGT] kms_addfb_basic: starting subtest unused-handle
11271 11:10:44.710522 4)
11272 11:10:44.717428 Using IGT_SR<14>[ 22.248865] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11273 11:10:44.720879 ANDOM=1709464245 for randomisation
11274 11:10:44.724067 Opened device: /dev/dri/card0
11275 11:10:44.727269 Starting subtest: unused-handle
11276 11:10:44.734260 [1mSubtest <14>[ 22.266410] [IGT] kms_addfb_basic: exiting, ret=0
11277 11:10:44.737183 unused-handle: SUCCESS (0.000s)[0m
11278 11:10:44.746895 Test requirement not met in function igt_re<8>[ 22.279012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11279 11:10:44.747150 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11281 11:10:44.750162 quire_intel, file ../lib/drmtest.c:880:
11282 11:10:44.753669 Test requirement: is_intel_device(fd)
11283 11:10:44.760054 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11284 11:10:44.763615 Test requirement: is_intel_device(fd)
11285 11:10:44.769919 No KMS driver or no outputs, pipes: 16, outputs: 0
11286 11:10:44.776818 <14>[ 22.309903] [IGT] kms_addfb_basic: executing
11287 11:10:44.786379 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch6<14>[ 22.319425] [IGT] kms_addfb_basic: starting subtest unused-pitches
11288 11:10:44.786462 4)
11289 11:10:44.796641 Using IGT_SR<14>[ 22.326987] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11290 11:10:44.799637 ANDOM=1709464245 for randomisation
11291 11:10:44.802700 Opened device: /dev/dri/card0
11292 11:10:44.806253 Starting subtest: unused-pitches
11293 11:10:44.809689 [1mSubtest<14>[ 22.344740] [IGT] kms_addfb_basic: exiting, ret=0
11294 11:10:44.815889 unused-pitches: SUCCESS (0.000s)[0m
11295 11:10:44.826288 Test requirement not met in function igt_<8>[ 22.357172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11296 11:10:44.826547 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11298 11:10:44.829510 require_intel, file ../lib/drmtest.c:880:
11299 11:10:44.832375 Test requirement: is_intel_device(fd)
11300 11:10:44.842599 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:<14>[ 22.378505] [IGT] kms_addfb_basic: executing
11301 11:10:44.845648 880:
11302 11:10:44.849036 Test requirement: is_intel_device(fd)
11303 11:10:44.855344 No KMS driver or no<14>[ 22.387688] [IGT] kms_addfb_basic: starting subtest unused-offsets
11304 11:10:44.865297 outputs, pipes:<14>[ 22.395599] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11305 11:10:44.865379 16, outputs: 0
11306 11:10:44.871918 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11307 11:10:44.878677 Using IGT_S<14>[ 22.412190] [IGT] kms_addfb_basic: exiting, ret=0
11308 11:10:44.881731 RANDOM=1709464245 for randomisation
11309 11:10:44.885534 Opened device: /dev/dri/card0
11310 11:10:44.891815 Starting sub<8>[ 22.424230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11311 11:10:44.892097 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11313 11:10:44.895228 test: unused-offsets
11314 11:10:44.898601 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11315 11:10:44.905108 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11316 11:10:44.911850 Test requirement: is<14>[ 22.446228] [IGT] kms_addfb_basic: executing
11317 11:10:44.914844 _intel_device(fd)
11318 11:10:44.924577 Test requirement not met in function igt_requ<14>[ 22.455980] [IGT] kms_addfb_basic: starting subtest unused-modifier
11319 11:10:44.934741 ire_intel, file <14>[ 22.464004] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11320 11:10:44.934822 ../lib/drmtest.c:880:
11321 11:10:44.937874 Test requirement: is_intel_device(fd)
11322 11:10:44.947832 No KMS driver or no outputs, pipes<14>[ 22.480566] [IGT] kms_addfb_basic: exiting, ret=0
11323 11:10:44.947915 : 16, outputs: 0
11324 11:10:44.960972 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarc<8>[ 22.492499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11325 11:10:44.961080 h64)
11326 11:10:44.961344 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11328 11:10:44.964458 Using IGT_SRANDOM=1709464245 for randomisation
11329 11:10:44.967893 Opened device: /dev/dri/card0
11330 11:10:44.971133 Starting subtest: unused-modifier
11331 11:10:44.974115 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11332 11:10:44.980868 Test <14>[ 22.514822] [IGT] kms_addfb_basic: executing
11333 11:10:44.994185 requirement not met in function igt_require_intel, file ../lib/d<14>[ 22.524920] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11334 11:10:44.994292 rmtest.c:880:
11335 11:10:45.000657 T<14>[ 22.532932] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11336 11:10:45.003851 est requirement: is_intel_device(fd)
11337 11:10:45.017518 Test requirement not met in function igt_require_intel, fi<14>[ 22.549909] [IGT] kms_addfb_basic: exiting, ret=77
11338 11:10:45.017600 le ../lib/drmtest.c:880:
11339 11:10:45.020354 Test requirement: is_intel_device(fd)
11340 11:10:45.030566 No KMS driver o<8>[ 22.561696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11341 11:10:45.030868 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11343 11:10:45.033726 r no outputs, pipes: 16, outputs: 0
11344 11:10:45.040327 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11345 11:10:45.043590 Using IGT_SRANDOM=1709464245 for randomisation
11346 11:10:45.049926 Opened device: /dev/dri<14>[ 22.584113] [IGT] kms_addfb_basic: executing
11347 11:10:45.050007 /card0
11348 11:10:45.053584 Starting subtest: clobberred-modifier
11349 11:10:45.063720 Test requirement <14>[ 22.594307] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11350 11:10:45.073205 not met in funct<14>[ 22.603295] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11351 11:10:45.076602 ion igt_require_i915, file ../lib/drmtest.c:885:
11352 11:10:45.079746 Test requirement: is_i915_device(fd)
11353 11:10:45.086794 [1mSubt<14>[ 22.620758] [IGT] kms_addfb_basic: exiting, ret=77
11354 11:10:45.089949 est clobberred-modifier: SKIP (0.000s)[0m
11355 11:10:45.102847 Test requirement not met in function<8>[ 22.632610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11356 11:10:45.103155 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11358 11:10:45.106238 igt_require_intel, file ../lib/drmtest.c:880:
11359 11:10:45.109466 Test requirement: is_intel_device(fd)
11360 11:10:45.116431 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11361 11:10:45.122835 Test <14>[ 22.656672] [IGT] kms_addfb_basic: executing
11362 11:10:45.125947 requirement: is_intel_device(fd)
11363 11:10:45.132472 No KMS driver or no outputs, p<14>[ 22.665912] [IGT] kms_addfb_basic: starting subtest legacy-format
11364 11:10:45.135658 ipes: 16, outputs: 0
11365 11:10:45.148947 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 <14>[ 22.679874] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11366 11:10:45.149029 aarch64)
11367 11:10:45.152494 Using IGT_SRANDOM=1709464245 for randomisation
11368 11:10:45.155646 Opened device: /dev/dri/card0
11369 11:10:45.162089 Startin<14>[ 22.695552] [IGT] kms_addfb_basic: exiting, ret=0
11370 11:10:45.165285 g subtest: invalid-smem-bo-on-discrete
11371 11:10:45.175265 Test requirement not met in function igt<8>[ 22.707439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11372 11:10:45.175579 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11374 11:10:45.179107 _require_intel, file ../lib/drmtest.c:880:
11375 11:10:45.181764 Test requirement: is_intel_device(fd)
11376 11:10:45.188875 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11377 11:10:45.195190 Test requirement not met in funct<14>[ 22.729894] [IGT] kms_addfb_basic: executing
11378 11:10:45.198291 ion igt_require_intel, file ../lib/drmtest.c:880:
11379 11:10:45.208137 Test requirement: is_intel_de<14>[ 22.741661] [IGT] kms_addfb_basic: starting subtest no-handle
11380 11:10:45.208260 vice(fd)
11381 11:10:45.218140 Test r<14>[ 22.748204] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11382 11:10:45.224547 equirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11383 11:10:45.228133 Te<14>[ 22.762265] [IGT] kms_addfb_basic: exiting, ret=0
11384 11:10:45.231507 st requirement: is_intel_device(fd)
11385 11:10:45.241180 No KMS driver or no outputs, pipes: 16, out<8>[ 22.774739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11386 11:10:45.241438 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11388 11:10:45.244592 puts: 0
11389 11:10:45.247742 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11390 11:10:45.254595 Using IGT_SRANDOM=1709464245 for randomisation
11391 11:10:45.257777 Opened device: /dev/dri/card0
11392 11:10:45.260859 Starting subtest: le<14>[ 22.796826] [IGT] kms_addfb_basic: executing
11393 11:10:45.264089 gacy-format
11394 11:10:45.267576 Successfully fuzzed 10000 {bpp, depth} variations
11395 11:10:45.274425 [1mSubtest lega<14>[ 22.808698] [IGT] kms_addfb_basic: starting subtest basic
11396 11:10:45.284853 cy-format: SUCCE<14>[ 22.815002] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11397 11:10:45.284935 SS (0.006s)[0m
11398 11:10:45.294211 Test requirement not met in function igt_require_intel, file ..<14>[ 22.828818] [IGT] kms_addfb_basic: exiting, ret=0
11399 11:10:45.297289 /lib/drmtest.c:880:
11400 11:10:45.300746 Test requirement: is_intel_device(fd)
11401 11:10:45.307039 Test requirement not<8>[ 22.840906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11402 11:10:45.307293 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11404 11:10:45.314053 met in function igt_require_intel, file ../lib/drmtest.c:880:
11405 11:10:45.317006 Test requirement: is_intel_device(fd)
11406 11:10:45.323770 No KMS driver or no outputs, pipes: 16, outputs: 0
11407 11:10:45.327073 IGT-Version: 1.28-g08<14>[ 22.862703] [IGT] kms_addfb_basic: executing
11408 11:10:45.333295 30aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11409 11:10:45.343264 Using IGT_SRANDOM=1709464245 for <14>[ 22.874810] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11410 11:10:45.343416 randomisation
11411 11:10:45.349904 O<14>[ 22.881647] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11412 11:10:45.353642 pened device: /dev/dri/card0
11413 11:10:45.356524 Starting subtest: no-handle
11414 11:10:45.363125 [1mSubtest no-handle<14>[ 22.895874] [IGT] kms_addfb_basic: exiting, ret=0
11415 11:10:45.363207 : SUCCESS (0.000s)[0m
11416 11:10:45.376321 Test requirement not met in function igt_require_intel, <8>[ 22.908150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11417 11:10:45.376580 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11419 11:10:45.380012 file ../lib/drmtest.c:880:
11420 11:10:45.383093 Test requirement: is_intel_device(fd)
11421 11:10:45.389509 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11422 11:10:45.396090 Test requirement: is_inte<14>[ 22.930457] [IGT] kms_addfb_basic: executing
11423 11:10:45.396172 l_device(fd)
11424 11:10:45.403143 No KMS driver or no outputs, pipes: 16, outputs: 0
11425 11:10:45.409686 IGT-Version: 1<14>[ 22.942403] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11426 11:10:45.419495 .28-g0830aa7 (aa<14>[ 22.949320] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11427 11:10:45.422501 rch64) (Linux: 6.1.80-cip16 aarch64)
11428 11:10:45.429206 Using IGT_SRANDOM=1709464245 for randomisa<14>[ 22.963752] [IGT] kms_addfb_basic: exiting, ret=0
11429 11:10:45.429379 tion
11430 11:10:45.432612 Opened device: /dev/dri/card0
11431 11:10:45.435867 Starting subtest: basic
11432 11:10:45.442706 [1mSubtest basic:<8>[ 22.975859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11433 11:10:45.442988 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11435 11:10:45.445910 SUCCESS (0.000s)[0m
11436 11:10:45.452610 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11437 11:10:45.455609 Test requirement: is_intel_device(fd)
11438 11:10:45.465749 Test requirement not met in fu<14>[ 22.998248] [IGT] kms_addfb_basic: executing
11439 11:10:45.469245 nction igt_require_intel, file ../lib/drmtest.c:880:
11440 11:10:45.478628 Test requirement: is_intel<14>[ 23.010218] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11441 11:10:45.478712 _device(fd)
11442 11:10:45.485336 No <14>[ 23.017102] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11443 11:10:45.488930 KMS driver or no outputs, pipes: 16, outputs: 0
11444 11:10:45.498931 IGT-Version: 1.28-g0830aa7 (aar<14>[ 23.031341] [IGT] kms_addfb_basic: exiting, ret=0
11445 11:10:45.501936 ch64) (Linux: 6.1.80-cip16 aarch64)
11446 11:10:45.511526 Using IGT_SRANDOM=1709464245 for randomisat<8>[ 23.043706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11447 11:10:45.511609 ion
11448 11:10:45.511849 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11450 11:10:45.514946 Opened device: /dev/dri/card0
11451 11:10:45.518813 Starting subtest: bad-pitch-0
11452 11:10:45.522016 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11453 11:10:45.531289 Test requirement not met in function igt_require_intel, file .<14>[ 23.066427] [IGT] kms_addfb_basic: executing
11454 11:10:45.535004 ./lib/drmtest.c:880:
11455 11:10:45.538280 Test requirement: is_intel_device(fd)
11456 11:10:45.544633 Test requirement no<14>[ 23.078077] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11457 11:10:45.554515 t met in functio<14>[ 23.085152] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11458 11:10:45.558047 n igt_require_intel, file ../lib/drmtest.c:880:
11459 11:10:45.564554 Test requirement: is_intel_devi<14>[ 23.099566] [IGT] kms_addfb_basic: exiting, ret=0
11460 11:10:45.567877 ce(fd)
11461 11:10:45.571094 No KMS driver or no outputs, pipes: 16, outputs: 0
11462 11:10:45.580922 IGT-Version: 1.28-g0<8>[ 23.111690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11463 11:10:45.581177 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11465 11:10:45.584422 830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11466 11:10:45.587959 Using IGT_SRANDOM=1709464245 for randomisation
11467 11:10:45.590746 Opened device: /dev/dri/card0
11468 11:10:45.593995 Starting subtest: bad-pitch-32
11469 11:10:45.601056 [1mSubtest bad-p<14>[ 23.134276] [IGT] kms_addfb_basic: executing
11470 11:10:45.604183 itch-32: SUCCESS (0.000s)[0m
11471 11:10:45.614017 Test requirement not met in function igt_require_<14>[ 23.146246] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11472 11:10:45.620396 intel, file ../l<14>[ 23.153189] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11473 11:10:45.624515 ib/drmtest.c:880:
11474 11:10:45.627326 Test requirement: is_intel_device(fd)
11475 11:10:45.633476 Test requirement not m<14>[ 23.167508] [IGT] kms_addfb_basic: exiting, ret=0
11476 11:10:45.640602 et in function igt_require_intel, file ../lib/drmtest.c:880:
11477 11:10:45.646941 Test requirement: <8>[ 23.179396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11478 11:10:45.647224 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11480 11:10:45.650439 is_intel_device(fd)
11481 11:10:45.653695 No KMS driver or no outputs, pipes: 16, outputs: 0
11482 11:10:45.660448 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11483 11:10:45.663844 Using IGT_SRANDOM=1709464245 for randomisation
11484 11:10:45.667160 Opened device: /dev/dri/card0
11485 11:10:45.670024 Starting subtest: bad-pitch-63
11486 11:10:45.676606 [1mSubtest bad-pitch-63: SUCCESS (0<14>[ 23.212529] [IGT] kms_addfb_basic: executing
11487 11:10:45.680149 .000s)[0m
11488 11:10:45.686576 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11489 11:10:45.693561 <14>[ 23.224874] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11490 11:10:45.700085 Test requirement<14>[ 23.232494] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11491 11:10:45.703319 : is_intel_device(fd)
11492 11:10:45.713202 Test requirement not met in function igt_require_intel, f<14>[ 23.247882] [IGT] kms_addfb_basic: exiting, ret=0
11493 11:10:45.716194 ile ../lib/drmtest.c:880:
11494 11:10:45.719705 Test requirement: is_intel_device(fd)
11495 11:10:45.726074 No KMS driver <8>[ 23.259107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11496 11:10:45.726329 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11498 11:10:45.729498 or no outputs, pipes: 16, outputs: 0
11499 11:10:45.736131 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11500 11:10:45.742796 Using IGT_SRANDOM=1709464245 for randomisation
11501 11:10:45.749250 Opened device: /dev/dr<14>[ 23.281258] [IGT] kms_addfb_basic: executing
11502 11:10:45.749331 i/card0
11503 11:10:45.752666 Starting subtest: bad-pitch-128
11504 11:10:45.762970 [1mSubtest bad-pitch-128: SUCCESS (0.<14>[ 23.293843] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11505 11:10:45.763052 000s)[0m
11506 11:10:45.769543 Test <14>[ 23.300790] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11507 11:10:45.775602 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11508 11:10:45.782297 T<14>[ 23.315445] [IGT] kms_addfb_basic: exiting, ret=0
11509 11:10:45.785738 est requirement: is_intel_device(fd)
11510 11:10:45.795257 Test requirement not met in function igt_r<8>[ 23.327641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11511 11:10:45.795549 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11513 11:10:45.799678 equire_intel, file ../lib/drmtest.c:880:
11514 11:10:45.802061 Test requirement: is_intel_device(fd)
11515 11:10:45.809074 No KMS driver or no outputs, pipes: 16, outputs: 0
11516 11:10:45.815140 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux<14>[ 23.350285] [IGT] kms_addfb_basic: executing
11517 11:10:45.818710 : 6.1.80-cip16 aarch64)
11518 11:10:45.821945 Using IGT_SRANDOM=1709464246 for randomisation
11519 11:10:45.828625 Opened <14>[ 23.361807] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11520 11:10:45.838491 device: /dev/dri<14>[ 23.369145] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11521 11:10:45.838573 /card0
11522 11:10:45.842090 Starting subtest: bad-pitch-256
11523 11:10:45.851868 [1mSubtest bad-pitch-256: SUCCESS (0.0<14>[ 23.383786] [IGT] kms_addfb_basic: exiting, ret=0
11524 11:10:45.851950 00s)[0m
11525 11:10:45.864626 Test requirement not met in function igt_require_intel, file ../lib/dr<8>[ 23.395609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11526 11:10:45.864721 mtest.c:880:
11527 11:10:45.864960 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11529 11:10:45.868303 Test requirement: is_intel_device(fd)
11530 11:10:45.878309 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11531 11:10:45.881314 Test requirement: is_intel_device(fd)
11532 11:10:45.884654 <14>[ 23.418581] [IGT] kms_addfb_basic: executing
11533 11:10:45.887645 No KMS driver or no outputs, pipes: 16, outputs: 0
11534 11:10:45.901179 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aa<14>[ 23.432731] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11535 11:10:45.901261 rch64)
11536 11:10:45.910974 Using IG<14>[ 23.440945] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11537 11:10:45.914187 T_SRANDOM=1709464246 for randomisation
11538 11:10:45.921023 Opened d<14>[ 23.454101] [IGT] kms_addfb_basic: exiting, ret=0
11539 11:10:45.921106 evice: /dev/dri/card0
11540 11:10:45.924054 Starting subtest: bad-pitch-1024
11541 11:10:45.934177 [1mSubtest bad-pitch-1<8>[ 23.465723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11542 11:10:45.934432 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11544 11:10:45.937176 024: SUCCESS (0.000s)[0m
11545 11:10:45.943833 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11546 11:10:45.947528 Test requirement: is_intel_device(fd)
11547 11:10:45.953989 Test requirement not met i<14>[ 23.489213] [IGT] kms_addfb_basic: executing
11548 11:10:45.960320 n function igt_require_intel, file ../lib/drmtest.c:880:
11549 11:10:45.963771 Test requirement: is_intel_device(fd)
11550 11:10:45.970056 No KMS driver o<14>[ 23.502677] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11551 11:10:45.979990 r no outputs, pi<14>[ 23.510636] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11552 11:10:45.980071 pes: 16, outputs: 0
11553 11:10:45.990097 IGT-Version: 1.28-g0830aa7 <14>[ 23.523530] [IGT] kms_addfb_basic: exiting, ret=0
11554 11:10:45.993072 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11555 11:10:46.003076 Using IGT_SRANDOM=1709464246 for random<8>[ 23.534807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11556 11:10:46.003157 isation
11557 11:10:46.003415 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11559 11:10:46.006766 Opened device: /dev/dri/card0
11560 11:10:46.009913 Starting subtest: bad-pitch-999
11561 11:10:46.013036 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11562 11:10:46.022767 Test requirement not met in function igt_require_intel<14>[ 23.557741] [IGT] kms_addfb_basic: executing
11563 11:10:46.026631 , file ../lib/drmtest.c:880:
11564 11:10:46.029867 Test requirement: is_intel_device(fd)
11565 11:10:46.039551 Test requirement not met in function igt_re<14>[ 23.571526] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11566 11:10:46.049798 quire_intel, fil<14>[ 23.579862] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11567 11:10:46.052749 e ../lib/drmtest.c:880:
11568 11:10:46.055744 Test requirement: is_intel_device(fd)
11569 11:10:46.059305 <14>[ 23.593215] [IGT] kms_addfb_basic: exiting, ret=0
11570 11:10:46.065524 No KMS driver or no outputs, pipes: 16, outputs: 0
11571 11:10:46.075525 IGT-Version: 1.28-g0830aa7 (<8>[ 23.605730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11572 11:10:46.075779 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11574 11:10:46.079310 aarch64) (Linux: 6.1.80-cip16 aarch64)
11575 11:10:46.082792 Using IGT_SRANDOM=1709464246 for randomisation
11576 11:10:46.085425 Opened device: /dev/dri/card0
11577 11:10:46.088760 Starting subtest: bad-pitch-65536
11578 11:10:46.095635 [1mSubtest bad-pitch-<14>[ 23.629275] [IGT] kms_addfb_basic: executing
11579 11:10:46.098846 65536: SUCCESS (0.000s)[0m
11580 11:10:46.105323 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11581 11:10:46.112202 <14>[ 23.642913] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11582 11:10:46.112283
11583 11:10:46.118384 Test requiremen<14>[ 23.650867] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11584 11:10:46.121699 t: is_intel_device(fd)
11585 11:10:46.128622 Test requirement not met<14>[ 23.663705] [IGT] kms_addfb_basic: exiting, ret=0
11586 11:10:46.134963 in function igt_require_intel, file ../lib/drmtest.c:880:
11587 11:10:46.144740 Test requirement: is<8>[ 23.675137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11588 11:10:46.144822 _intel_device(fd)
11589 11:10:46.145069 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11591 11:10:46.148168 No KMS driver or no outputs, pipes: 16, outputs: 0
11592 11:10:46.154813 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11593 11:10:46.164509 Using IGT_SRANDOM=1709464246 for rand<14>[ 23.698160] [IGT] kms_addfb_basic: executing
11594 11:10:46.164590 omisation
11595 11:10:46.168069 Opened device: /dev/dri/card0
11596 11:10:46.171217 Starting subtest: invalid-get-prop-any
11597 11:10:46.181238 [1mSubtest invalid-get-prop-any: SUCCESS (0.0<14>[ 23.713631] [IGT] kms_addfb_basic: starting subtest master-rmfb
11598 11:10:46.181320 00s)[0m
11599 11:10:46.190885 Test r<14>[ 23.720752] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11600 11:10:46.197729 equirement not met in function i<14>[ 23.731459] [IGT] kms_addfb_basic: exiting, ret=0
11601 11:10:46.200973 gt_require_intel, file ../lib/drmtest.c:880:
11602 11:10:46.210832 Test requirement: <8>[ 23.742275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11603 11:10:46.210913 is_intel_device(fd)
11604 11:10:46.211148 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11606 11:10:46.217183 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11607 11:10:46.224008 Test requirement: is_intel_device(fd)
11608 11:10:46.227120 No KMS driver or<14>[ 23.763046] [IGT] kms_addfb_basic: executing
11609 11:10:46.230547 no outputs, pipes: 16, outputs: 0
11610 11:10:46.237144 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11611 11:10:46.247604 Using IGT_SRANDOM=1709464246 for randomi<14>[ 23.780348] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11612 11:10:46.250661 sation
11613 11:10:46.257167 Opened d<14>[ 23.788008] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11614 11:10:46.263761 evice: /dev/dri/<14>[ 23.797905] [IGT] kms_addfb_basic: exiting, ret=0
11615 11:10:46.263882 card0
11616 11:10:46.266760 Starting subtest: invalid-get-prop
11617 11:10:46.280269 [1mSubtest invalid-get-prop: SUCCESS<8>[ 23.810139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11618 11:10:46.280392 (0.000s)[0m
11619 11:10:46.280682 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11621 11:10:46.286661 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11622 11:10:46.290032 Test requirement: is_intel_device(fd)
11623 11:10:46.300137 Test requirement not met in function i<14>[ 23.833810] [IGT] kms_addfb_basic: executing
11624 11:10:46.303340 gt_require_intel, file ../lib/drmtest.c:880:
11625 11:10:46.306498 Test requirement: is_intel_device(fd)
11626 11:10:46.309663 No KMS driver or no outputs, pipes: 16, outputs: 0
11627 11:10:46.319822 IGT-Version: 1.28-g0830<14>[ 23.851627] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11628 11:10:46.323049 aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11629 11:10:46.336158 Using IGT_SRANDOM=1709464246 for ra<14>[ 23.865873] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11630 11:10:46.336253 ndomisation
11631 11:10:46.339357 Opened device: /dev/dri/card0
11632 11:10:46.342929 Starting subtest: invalid-set-prop-any
11633 11:10:46.346006 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11634 11:10:46.352564 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11635 11:10:46.356123 Test requirement: is_intel_device(fd)
11636 11:10:46.365711 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11637 11:10:46.369184 Test requirement: is_intel_device(fd)
11638 11:10:46.372434 No KMS driver or no outputs, pipes: 16, outputs: 0
11639 11:10:46.379127 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11640 11:10:46.382869 Using IGT_SRANDOM=1709464246 for randomisation
11641 11:10:46.385973 Opened device: /dev/dri/card0
11642 11:10:46.389171 Starting subtest: invalid-set-prop
11643 11:10:46.392737 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11644 11:10:46.402523 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11645 11:10:46.405867 Test requirement: is_intel_device(fd)
11646 11:10:46.412206 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11647 11:10:46.415955 Test requirement: is_intel_device(fd)
11648 11:10:46.418683 No KMS driver or no outputs, pipes: 16, outputs: 0
11649 11:10:46.425419 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11650 11:10:46.428868 Using IGT_SRANDOM=1709464246 for randomisation
11651 11:10:46.432104 Opened device: /dev/dri/card0
11652 11:10:46.435247 Starting subtest: master-rmfb
11653 11:10:46.438322 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11654 11:10:46.444934 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11655 11:10:46.448356 Test requirement: is_intel_device(fd)
11656 11:10:46.458374 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11657 11:10:46.458497 Test requirement: is_intel_device(fd)
11658 11:10:46.464982 No KMS driver or no outputs, pipes: 16, outputs: 0
11659 11:10:46.471598 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11660 11:10:46.475082 Using IGT_SRANDOM=1709464246 for randomisation
11661 11:10:46.478368 Opened device: /dev/dri/card0
11662 11:10:46.481610 Starting subtest: addfb25-modifier-no-flag
11663 11:10:46.484886 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11664 11:10:46.494645 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11665 11:10:46.498199 Test requirement: is_intel_device(fd)
11666 11:10:46.504903 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11667 11:10:46.508054 Test requirement: is_intel_device(fd)
11668 11:10:46.511189 No KMS driver or no outputs, pipes: 16, outputs: 0
11669 11:10:46.518233 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11670 11:10:46.521177 Using IGT_SRANDOM=1709464246 for randomisation
11671 11:10:46.524326 Opened device: /dev/dri/card0
11672 11:10:46.527557 Starting subtest: addfb25-bad-modifier
11673 11:10:46.537405 (kms_addfb_basic:440) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11674 11:10:46.557335 (kms_addfb_basic:440) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11675 11:10:46.560519 (kms_addfb_basic:440) CRITICAL: error: 0 != -1
11676 11:10:46.560600 Stack trace:
11677 11:10:46.567305 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11678 11:10:46.567428 #1 [<unknown>+0xb86f4358]
11679 11:10:46.570718 #2 [<unknown>+0xb86f5fbc]
11680 11:10:46.573834 #3 [<unknown>+0xb86f156c]
11681 11:10:46.577692 #4 [__libc_init_first+0x80]
11682 11:10:46.580524 #5 [__libc_start_main+0x98]
11683 11:10:46.580605 #6 [<unknown>+0xb86f15b0]
11684 11:10:46.583811 Subtest addfb25-bad-modifier failed.
11685 11:10:46.587147 **** DEBUG ****
11686 11:10:46.593750 (kms_addfb_basic:440) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11687 11:10:46.603843 (kms_addfb_basic:440) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11688 11:10:46.623387 (kms_addfb_basic:440) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11689 11:10:46.626642 (kms_addfb_basic:440) CRITICAL: error: 0 != -1
11690 11:10:46.629863 (kms_addfb_basic:440) igt_core-INFO: Stack trace:
11691 11:10:46.639716 (kms_addfb_basic:440) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11692 11:10:46.643157 (kms_addfb_basic:440) igt_core-INFO: #1 [<unknown>+0xb86f4358]
11693 11:10:46.649786 (kms_addfb_basic:440) igt_core-INFO: #2 [<unknown>+0xb86f5fbc]
11694 11:10:46.656999 (kms_addfb_basic:440) igt_core-INFO: #3 [<unknown>+0xb86f156c]
11695 11:10:46.662883 (kms_addfb_basic:440) igt_core-INFO: #4 [__libc_init_first+0x80]
11696 11:10:46.666695 (kms_addfb_basic:440) igt_core-INFO: #5 [__libc_start_main+0x98]
11697 11:10:46.676023 (kms_addfb_basic:440) <14>[ 24.208693] [IGT] kms_addfb_basic: exiting, ret=98
11698 11:10:46.679903 igt_core-INFO: #6 [<unknown>+0xb86f15b0]
11699 11:10:46.679984 **** END ****
11700 11:10:46.689615 [1mSubtest addfb25<8>[ 24.220191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11701 11:10:46.689885 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11703 11:10:46.693005 -bad-modifier: FAIL (0.006s)[0m
11704 11:10:46.699328 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11705 11:10:46.702476 Test requirement: is_intel_device(fd)
11706 11:10:46.709082 Tes<14>[ 24.242814] [IGT] kms_addfb_basic: executing
11707 11:10:46.715500 t requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11708 11:10:46.718821 Test requirement: is_intel_device(fd)
11709 11:10:46.725483 No KMS driver or no outputs, pipes: 16, <14>[ 24.260657] [IGT] kms_addfb_basic: exiting, ret=77
11710 11:10:46.728798 outputs: 0
11711 11:10:46.735661 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11712 11:10:46.742410 <8>[ 24.272674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11713 11:10:46.742675 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11715 11:10:46.745733 Using IGT_SRANDOM=1709464247 for randomisation
11716 11:10:46.749087 Opened device: /dev/dri/card0
11717 11:10:46.762173 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880<14>[ 24.295356] [IGT] kms_addfb_basic: executing
11718 11:10:46.762271 :
11719 11:10:46.765668 Test requirement: is_intel_device(fd)
11720 11:10:46.771694 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11721 11:10:46.781644 Test requirement not met in function igt_require_intel<14>[ 24.313890] [IGT] kms_addfb_basic: exiting, ret=77
11722 11:10:46.781737 , file ../lib/drmtest.c:880:
11723 11:10:46.785384 Test requirement: is_intel_device(fd)
11724 11:10:46.795190 No KMS driv<8>[ 24.326214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11725 11:10:46.795488 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11727 11:10:46.798435 er or no outputs, pipes: 16, outputs: 0
11728 11:10:46.805010 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11729 11:10:46.808520 Using IGT_SRANDOM=1709464247 for randomisation
11730 11:10:46.814938 Ope<14>[ 24.347945] [IGT] kms_addfb_basic: executing
11731 11:10:46.815022 ned device: /dev/dri/card0
11732 11:10:46.825015 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11733 11:10:46.828347 Test requirement: is_intel_device(fd)
11734 11:10:46.831481 [1mSubte<14>[ 24.366496] [IGT] kms_addfb_basic: exiting, ret=77
11735 11:10:46.838398 st addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11736 11:10:46.848000 Test requirement not met in functi<8>[ 24.378623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11737 11:10:46.848257 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11739 11:10:46.854430 on igt_require_intel, file ../lib/drmtest.c:880:
11740 11:10:46.857784 Test requirement: is_intel_device(fd)
11741 11:10:46.861239 No KMS driver or no outputs, pipes: 16, outputs: 0
11742 11:10:46.871181 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80<14>[ 24.405093] [IGT] kms_addfb_basic: executing
11743 11:10:46.871265 -cip16 aarch64)
11744 11:10:46.874322 Using IGT_SRANDOM=1709464247 for randomisation
11745 11:10:46.877916 Opened device: /dev/dri/card0
11746 11:10:46.887704 Test requirement not met in function igt_require_intel, file ../<14>[ 24.422524] [IGT] kms_addfb_basic: exiting, ret=77
11747 11:10:46.891247 lib/drmtest.c:880:
11748 11:10:46.894241 Test requirement: is_intel_device(fd)
11749 11:10:46.901549 [1mS<8>[ 24.434482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11750 11:10:46.901805 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11752 11:10:46.907732 ubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11753 11:10:46.914209 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11754 11:10:46.921065 Test requiremen<14>[ 24.456006] [IGT] kms_addfb_basic: executing
11755 11:10:46.924766 t: is_intel_device(fd)
11756 11:10:46.927284 No KMS driver or no outputs, pipes: 16, outputs: 0
11757 11:10:46.934158 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11758 11:10:46.940505 Using IGT_SRANDO<14>[ 24.473551] [IGT] kms_addfb_basic: exiting, ret=77
11759 11:10:46.944961 M=1709464247 for randomisation
11760 11:10:46.947290 Opened device: /dev/dri/card0
11761 11:10:46.954038 T<8>[ 24.485516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11762 11:10:46.954293 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11764 11:10:46.960417 est requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11765 11:10:46.963924 Test requirement: is_intel_device(fd)
11766 11:10:46.973922 Test requirement not met in function igt_require_intel<14>[ 24.507587] [IGT] kms_addfb_basic: executing
11767 11:10:46.976957 , file ../lib/drmtest.c:880:
11768 11:10:46.980628 Test requirement: is_intel_device(fd)
11769 11:10:46.983613 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11770 11:10:46.994122 No KMS driver or no outputs, pipes: 16<14>[ 24.526276] [IGT] kms_addfb_basic: exiting, ret=77
11771 11:10:46.994206 , outputs: 0
11772 11:10:47.007087 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)<8>[ 24.538439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11773 11:10:47.007171
11774 11:10:47.007386 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11776 11:10:47.013947 Using IGT_SRANDOM=1709464247 for randomisation
11777 11:10:47.014029 Opened device: /dev/dri/card0
11778 11:10:47.023489 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11779 11:10:47.029635 Test requirement: is_intel_<14>[ 24.563798] [IGT] kms_addfb_basic: executing
11780 11:10:47.029745 device(fd)
11781 11:10:47.036656 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11782 11:10:47.040070 Test requirement: is_intel_device(fd)
11783 11:10:47.046754 [1mSubtest framebuffer-v<14>[ 24.581350] [IGT] kms_addfb_basic: exiting, ret=77
11784 11:10:47.050269 s-set-tiling: SKIP (0.000s)[0m
11785 11:10:47.063025 No KMS driver or no outputs, pipes: 16, outputs<8>[ 24.593613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11786 11:10:47.063217 : 0
11787 11:10:47.063496 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11789 11:10:47.069668 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11790 11:10:47.072900 Using IGT_SRANDOM=1709464247 for randomisation
11791 11:10:47.076437 Opened device: /dev/dri/card0
11792 11:10:47.083071 Test requirement not met in function igt<14>[ 24.618258] [IGT] kms_addfb_basic: executing
11793 11:10:47.090117 _require_intel, file ../lib/drmtest.c:880:
11794 11:10:47.092753 Test requirement: is_intel_device(fd)
11795 11:10:47.102997 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c<14>[ 24.636379] [IGT] kms_addfb_basic: exiting, ret=77
11796 11:10:47.103082 :880:
11797 11:10:47.106113 Test requirement: is_intel_device(fd)
11798 11:10:47.115848 [1mSubtest tile-p<8>[ 24.648320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11799 11:10:47.116104 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11801 11:10:47.119480 itch-mismatch: SKIP (0.000s)[0m
11802 11:10:47.122213 No KMS driver or no outputs, pipes: 16, outputs: 0
11803 11:10:47.129060 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11804 11:10:47.132339 Using <14>[ 24.668080] [IGT] kms_addfb_basic: executing
11805 11:10:47.139299 IGT_SRANDOM=1709464247 for randomisation
11806 11:10:47.139423 Opened device: /dev/dri/card0
11807 11:10:47.148971 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11808 11:10:47.152004 Tes<14>[ 24.686190] [IGT] kms_addfb_basic: exiting, ret=77
11809 11:10:47.155196 t requirement: is_intel_device(fd)
11810 11:10:47.165444 Test requirement not met in function igt_req<8>[ 24.698458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11811 11:10:47.165699 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11813 11:10:47.168837 uire_intel, file ../lib/drmtest.c:880:
11814 11:10:47.171845 Test requirement: is_intel_device(fd)
11815 11:10:47.178514 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11816 11:10:47.185276 No KMS driver or no outputs,<14>[ 24.720160] [IGT] kms_addfb_basic: executing
11817 11:10:47.188610 pipes: 16, outputs: 0
11818 11:10:47.191965 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11819 11:10:47.198158 Using IGT_SRANDOM=1709464247 for randomisation
11820 11:10:47.205147 Opened device: /dev/<14>[ 24.737431] [IGT] kms_addfb_basic: exiting, ret=77
11821 11:10:47.205272 dri/card0
11822 11:10:47.215094 Test requirement not met in function igt_require_inte<8>[ 24.749438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11823 11:10:47.215350 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11825 11:10:47.217923 l, file ../lib/drmtest.c:880:
11826 11:10:47.221340 Test requirement: is_intel_device(fd)
11827 11:10:47.231179 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11828 11:10:47.234672 Test r<14>[ 24.769675] [IGT] kms_addfb_basic: executing
11829 11:10:47.237809 equirement: is_intel_device(fd)
11830 11:10:47.241375 No KMS driver or no outputs, pipes: 16, outputs: 0
11831 11:10:47.244661 [1mSubtest size-max: SKIP (0.000s)[0m
11832 11:10:47.254847 IGT-Version: 1.28-g0830aa7 (aarch6<14>[ 24.787384] [IGT] kms_addfb_basic: exiting, ret=77
11833 11:10:47.257487 4) (Linux: 6.1.80-cip16 aarch64)
11834 11:10:47.267842 Using IGT_SRANDOM=1709464247 f<8>[ 24.799116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11835 11:10:47.267925 or randomisation
11836 11:10:47.268162 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11838 11:10:47.271308 Opened device: /dev/dri/card0
11839 11:10:47.277603 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11840 11:10:47.284060 Test requirement: is_intel_<14>[ 24.819918] [IGT] kms_addfb_basic: executing
11841 11:10:47.287295 device(fd)
11842 11:10:47.293904 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11843 11:10:47.297746 Test requirement: is_intel_device(fd)
11844 11:10:47.303680 No KMS driver or no outpu<14>[ 24.837684] [IGT] kms_addfb_basic: exiting, ret=77
11845 11:10:47.307398 ts, pipes: 16, outputs: 0
11846 11:10:47.310882 [1mSubtest too-wide: SKIP (0.000s)[0m
11847 11:10:47.316799 IGT-Version:<8>[ 24.849574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11848 11:10:47.317053 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11850 11:10:47.323716 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11851 11:10:47.326898 Using IGT_SRANDOM=1709464247 for randomisation
11852 11:10:47.330638 Opened device: /dev/dri/card0
11853 11:10:47.337183 Test requirement not met <14>[ 24.871125] [IGT] kms_addfb_basic: executing
11854 11:10:47.340503 in function igt_require_intel, file ../lib/drmtest.c:880:
11855 11:10:47.343295 Test requirement: is_intel_device(fd)
11856 11:10:47.356942 Test requirement not met in function igt_require_intel, file .<14>[ 24.888960] [IGT] kms_addfb_basic: exiting, ret=77
11857 11:10:47.357026 ./lib/drmtest.c:880:
11858 11:10:47.360071 Test requirement: is_intel_device(fd)
11859 11:10:47.369957 No <8>[ 24.900536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11860 11:10:47.370213 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11862 11:10:47.373995 KMS driver or no outputs, pipes: 16, outputs: 0
11863 11:10:47.376686 [1mSubtest too-high: SKIP (0.000s)[0m
11864 11:10:47.383641 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11865 11:10:47.386318 Us<14>[ 24.922729] [IGT] kms_addfb_basic: executing
11866 11:10:47.393464 ing IGT_SRANDOM=1709464247 for randomisation
11867 11:10:47.393546 Opened device: /dev/dri/card0
11868 11:10:47.402990 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11869 11:10:47.406562 <14>[ 24.940392] [IGT] kms_addfb_basic: exiting, ret=77
11870 11:10:47.406644
11871 11:10:47.409721 Test requirement: is_intel_device(fd)
11872 11:10:47.419566 Test requirement not met<8>[ 24.952123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11873 11:10:47.419821 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11875 11:10:47.425917 in function igt_require_intel, file ../lib/drmtest.c:880:
11876 11:10:47.429534 Test requirement: is_intel_device(fd)
11877 11:10:47.432875 No KMS driver or no outputs, pipes: 16, outputs: 0
11878 11:10:47.439621 [1mSubtest bo-too-small:<14>[ 24.974065] [IGT] kms_addfb_basic: executing
11879 11:10:47.442510 SKIP (0.000s)[0m
11880 11:10:47.449398 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11881 11:10:47.452474 Using IGT_SRANDOM=1709464247 for randomisation
11882 11:10:47.459635 Opened device: /dev/dri/<14>[ 24.992645] [IGT] kms_addfb_basic: exiting, ret=77
11883 11:10:47.459718 card0
11884 11:10:47.472729 Test requirement not met in function igt_require_intel, f<8>[ 25.004402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11885 11:10:47.473042 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11887 11:10:47.475501 ile ../lib/drmtest.c:880:
11888 11:10:47.479195 Test requirement: is_intel_device(fd)
11889 11:10:47.485559 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11890 11:10:47.492025 Test requirement: is_intel<14>[ 25.026555] [IGT] kms_addfb_basic: executing
11891 11:10:47.495400 _device(fd)
11892 11:10:47.498895 No KMS driver or no outputs, pipes: 16, outputs: 0
11893 11:10:47.502198 [1mSubtest small-bo: SKIP (0.000s)[0m
11894 11:10:47.512747 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-ci<14>[ 25.045287] [IGT] kms_addfb_basic: exiting, ret=77
11895 11:10:47.512829 p16 aarch64)
11896 11:10:47.518814 Using IGT_SRANDOM=1709464247 for randomisation
11897 11:10:47.525017 Op<8>[ 25.057301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11898 11:10:47.525301 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11900 11:10:47.528646 ened device: /dev/dri/card0
11901 11:10:47.535273 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11902 11:10:47.538377 Test requirement: is_intel_device(fd)
11903 11:10:47.545099 Test req<14>[ 25.079109] [IGT] kms_addfb_basic: executing
11904 11:10:47.552107 uirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11905 11:10:47.555228 Test requirement: is_intel_device(fd)
11906 11:10:47.565087 No KMS driver or no outputs, pipes: 16, outpu<14>[ 25.097001] [IGT] kms_addfb_basic: exiting, ret=77
11907 11:10:47.565172 ts: 0
11908 11:10:47.568051 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11909 11:10:47.578443 IGT-Version: 1<8>[ 25.109569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11910 11:10:47.578781 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11912 11:10:47.584404 .28-g0830aa7 (aarch64) (Linux: 6<8>[ 25.119434] <LAVA_SIGNAL_TESTSET STOP>
11913 11:10:47.584717 Received signal: <TESTSET> STOP
11914 11:10:47.584837 Closing test_set kms_addfb_basic
11915 11:10:47.587964 .1.80-cip16 aarch64)
11916 11:10:47.591285 Using IGT_SRANDOM=1709464247 for randomisation
11917 11:10:47.594655 Opened device: /dev/dri/card0
11918 11:10:47.601346 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11919 11:10:47.604607 Test requirement: is_intel_device(fd)
11920 11:10:47.611680 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11921 11:10:47.617808 Test require<8>[ 25.151501] <LAVA_SIGNAL_TESTSET START kms_atomic>
11922 11:10:47.618062 Received signal: <TESTSET> START kms_atomic
11923 11:10:47.618132 Starting test_set kms_atomic
11924 11:10:47.621054 ment: is_intel_device(fd)
11925 11:10:47.624459 No KMS driver or no outputs, pipes: 16, outputs: 0
11926 11:10:47.627623 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11927 11:10:47.637685 IGT-Version: 1.28-g0830aa7 (aarch64) (Linu<14>[ 25.171325] [IGT] kms_atomic: executing
11928 11:10:47.644383 x: 6.1.80-cip16 <14>[ 25.177256] [IGT] kms_atomic: exiting, ret=77
11929 11:10:47.644466 aarch64)
11930 11:10:47.648268 Using IGT_SRANDOM=1709464247 for randomisation
11931 11:10:47.657507 Opened device: /dev/dr<8>[ 25.188630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11932 11:10:47.657591 i/card0
11933 11:10:47.657829 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11935 11:10:47.667266 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11936 11:10:47.670909 Test requirement: is_intel_device(fd)
11937 11:10:47.681037 Test requirement not met in function igt_require_intel, file ../lib/drmtest.<14>[ 25.214443] [IGT] kms_atomic: executing
11938 11:10:47.681121 c:880:
11939 11:10:47.687179 Test req<14>[ 25.220306] [IGT] kms_atomic: exiting, ret=77
11940 11:10:47.690423 uirement: is_intel_device(fd)
11941 11:10:47.700571 No KMS driver or no outputs, pipes: 16, outputs: <8>[ 25.231555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11942 11:10:47.700656 0
11943 11:10:47.700894 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11945 11:10:47.707263 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11946 11:10:47.713410 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11947 11:10:47.716835 Using IGT_SRANDOM=1709464247 for randomisation
11948 11:10:47.723544 Opened device: /d<14>[ 25.256951] [IGT] kms_atomic: executing
11949 11:10:47.723626 ev/dri/card0
11950 11:10:47.726481 Te<14>[ 25.262114] [IGT] kms_atomic: exiting, ret=77
11951 11:10:47.742995 st requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:<8>[ 25.273410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11952 11:10:47.743104
11953 11:10:47.743394 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11955 11:10:47.746698 Test requirement: is_intel_device(fd)
11956 11:10:47.756132 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11957 11:10:47.762839 Test requirement: is_intel_device(f<14>[ 25.297474] [IGT] kms_atomic: executing
11958 11:10:47.762922 d)
11959 11:10:47.769502 No KMS drive<14>[ 25.302280] [IGT] kms_atomic: exiting, ret=77
11960 11:10:47.772779 r or no outputs, pipes: 16, outputs: 0
11961 11:10:47.782504 [1mSubtest addfb25-y-tiled-small-legacy<8>[ 25.313660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11962 11:10:47.782759 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11964 11:10:47.785829 : SKIP (0.000s)[0m
11965 11:10:47.789569 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11966 11:10:47.795744 Using IGT_SRANDOM=1709464247 for randomisation
11967 11:10:47.799283 Opened device: /dev/dri<14>[ 25.336171] [IGT] kms_atomic: executing
11968 11:10:47.802786 /card0
11969 11:10:47.805873 Test req<14>[ 25.341184] [IGT] kms_atomic: exiting, ret=77
11970 11:10:47.812761 uirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11971 11:10:47.818887 Test<8>[ 25.353654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11972 11:10:47.819140 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11974 11:10:47.822228 requirement: is_intel_device(fd)
11975 11:10:47.832111 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11976 11:10:47.835575 Test requirement: is_intel_device(fd)
11977 11:10:47.838640 No<14>[ 25.374000] [IGT] kms_atomic: executing
11978 11:10:47.845193 KMS driver or n<14>[ 25.379086] [IGT] kms_atomic: exiting, ret=77
11979 11:10:47.848995 o outputs, pipes: 16, outputs: 0
11980 11:10:47.858527 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m<8>[ 25.390467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11981 11:10:47.858638
11982 11:10:47.858878 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11984 11:10:47.865085 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11985 11:10:47.868292 Using IGT_SRANDOM=1709464248 for randomisation
11986 11:10:47.871617 Opened device: /dev/dri/card0
11987 11:10:47.878407 No KMS driv<14>[ 25.413106] [IGT] kms_atomic: executing
11988 11:10:47.884679 er or no outputs<14>[ 25.417852] [IGT] kms_atomic: exiting, ret=77
11989 11:10:47.884761 , pipes: 16, outputs: 0
11990 11:10:47.891327 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11991 11:10:47.898049 IG<8>[ 25.429134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11992 11:10:47.898304 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11994 11:10:47.904886 T-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11995 11:10:47.908024 Using IGT_SRANDOM=1709464248 for randomisation
11996 11:10:47.911714 Opened device: /dev/dri/card0
11997 11:10:47.917898 No KMS driver o<14>[ 25.451964] [IGT] kms_atomic: executing
11998 11:10:47.921298 r no outputs, pi<14>[ 25.456941] [IGT] kms_atomic: exiting, ret=77
11999 11:10:47.924584 pes: 16, outputs: 0
12000 11:10:47.927984 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
12001 11:10:47.937635 IGT-Ve<8>[ 25.469312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12002 11:10:47.937906 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12004 11:10:47.944700 rsion: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12005 11:10:47.947406 Using IGT_SRANDOM=1709464248 for randomisation
12006 11:10:47.951229 Opened device: /dev/dri/card0
12007 11:10:47.958032 No KMS driver or no<14>[ 25.491648] [IGT] kms_atomic: executing
12008 11:10:47.960758 outputs, pipes:<14>[ 25.496458] [IGT] kms_atomic: exiting, ret=77
12009 11:10:47.964484 16, outputs: 0
12010 11:10:47.974011 [1mSubtest plane-primary-overlay-mutable-zpos:<8>[ 25.507467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12011 11:10:47.974265 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12013 11:10:47.977447 SKIP (0.000s)[0m
12014 11:10:47.984037 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12015 11:10:47.987047 Using IGT_SRANDOM=1709464248 for randomisation
12016 11:10:47.993832 Opened device: /dev/dri/<14>[ 25.528886] [IGT] kms_atomic: executing
12017 11:10:47.993914 card0
12018 11:10:48.000927 No KMS dr<14>[ 25.533866] [IGT] kms_atomic: exiting, ret=77
12019 11:10:48.003807 iver or no outputs, pipes: 16, outputs: 0
12020 11:10:48.013363 [1mSubtest plane-immutable-zpos: SKI<8>[ 25.545360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12021 11:10:48.013617 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12023 11:10:48.017578 P (0.000s)[0m
12024 11:10:48.023682 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12025 11:10:48.026643 Using IGT_SRANDOM=1709464248 for randomisation
12026 11:10:48.030340 Opened device: /dev/dri/card0
12027 11:10:48.033008 No KMS driver<14>[ 25.568876] [IGT] kms_atomic: executing
12028 11:10:48.040189 or no outputs, <14>[ 25.574565] [IGT] kms_atomic: exiting, ret=77
12029 11:10:48.043064 pipes: 16, outputs: 0
12030 11:10:48.046604 [1mSubtest test-only: SKIP (0.000s)[0m
12031 11:10:48.057236 IGT-Version: 1.<8>[ 25.586153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12032 11:10:48.057491 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12034 11:10:48.059927 28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12035 11:10:48.063946 Using IGT_SRANDOM=1709464248 for randomisation
12036 11:10:48.066530 Opened device: /dev/dri/card0
12037 11:10:48.073085 No KMS driver or no outputs,<14>[ 25.608849] [IGT] kms_atomic: executing
12038 11:10:48.079272 pipes: 16, outp<14>[ 25.613595] [IGT] kms_atomic: exiting, ret=77
12039 11:10:48.079357 uts: 0
12040 11:10:48.086588 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12041 11:10:48.092683 IGT-<8>[ 25.624527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12042 11:10:48.092937 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12044 11:10:48.099527 Version: 1.28-g0830aa7 (aarch64)<8>[ 25.634199] <LAVA_SIGNAL_TESTSET STOP>
12045 11:10:48.099780 Received signal: <TESTSET> STOP
12046 11:10:48.099849 Closing test_set kms_atomic
12047 11:10:48.103108 (Linux: 6.1.80-cip16 aarch64)
12048 11:10:48.105931 Using IGT_SRANDOM=1709464248 for randomisation
12049 11:10:48.109098 Opened device: /dev/dri/card0
12050 11:10:48.112848 No KMS driver or no outputs, pipes: 16, outputs: 0
12051 11:10:48.119023 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
12052 11:10:48.125932 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12053 11:10:48.128911 Using IGT_SRANDOM=1709464248 for randomisation
12054 11:10:48.135455 Open<8>[ 25.666973] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12055 11:10:48.135537 ed device: /dev/dri/card0
12056 11:10:48.135774 Received signal: <TESTSET> START kms_flip_event_leak
12057 11:10:48.135840 Starting test_set kms_flip_event_leak
12058 11:10:48.142232 No KMS driver or no outputs, pipes: 16, outputs: 0
12059 11:10:48.145655 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
12060 11:10:48.152155 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12061 11:10:48.155146 Using IGT_SRANDOM=1709464248 for randomisation
12062 11:10:48.161962 Op<14>[ 25.696184] [IGT] kms_flip_event_leak: executing
12063 11:10:48.168890 ened device: /de<14>[ 25.702214] [IGT] kms_flip_event_leak: exiting, ret=77
12064 11:10:48.168973 v/dri/card0
12065 11:10:48.175194 No KMS driver or no outputs, pipes: 16, outputs: 0
12066 11:10:48.181570 [1mSubtest crt<8>[ 25.713947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12067 11:10:48.181826 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12069 11:10:48.188144 c-invalid-params: SKIP (0.000s)<8>[ 25.723451] <LAVA_SIGNAL_TESTSET STOP>
12070 11:10:48.188226 [0m
12071 11:10:48.188462 Received signal: <TESTSET> STOP
12072 11:10:48.188528 Closing test_set kms_flip_event_leak
12073 11:10:48.195082 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12074 11:10:48.198708 Using IGT_SRANDOM=1709464248 for randomisation
12075 11:10:48.202075 Opened device: /dev/dri/card0
12076 11:10:48.204792 No KMS driver or no outputs, pipes: 16, outputs: 0
12077 11:10:48.211659 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12078 11:10:48.217833 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12079 11:10:48.224786 Using IGT_SRANDOM=1709464248 for rando<8>[ 25.759845] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12080 11:10:48.225039 Received signal: <TESTSET> START kms_prop_blob
12081 11:10:48.225108 Starting test_set kms_prop_blob
12082 11:10:48.227809 misation
12083 11:10:48.227891 Opened device: /dev/dri/card0
12084 11:10:48.235205 No KMS driver or no outputs, pipes: 16, outputs: 0
12085 11:10:48.238025 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
12086 11:10:48.244206 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12087 11:10:48.247793 Using IGT_SRANDOM=1709464248 for randomisation
12088 11:10:48.251658 Opened device: /dev/dri/card0
12089 11:10:48.257756 No KMS driver or no output<14>[ 25.793479] [IGT] kms_prop_blob: executing
12090 11:10:48.264268 s, pipes: 16, ou<14>[ 25.798656] [IGT] kms_prop_blob: starting subtest basic
12091 11:10:48.267716 tputs: 0
12092 11:10:48.274166 [1mSu<14>[ 25.805138] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12093 11:10:48.280509 btest atomic-pla<14>[ 25.812942] [IGT] kms_prop_blob: exiting, ret=0
12094 11:10:48.280592 ne-damage: SKIP (0.000s)[0m
12095 11:10:48.293898 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.8<8>[ 25.825984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12096 11:10:48.293982 0-cip16 aarch64)
12097 11:10:48.294221 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12099 11:10:48.297467 Using IGT_SRANDOM=1709464248 for randomisation
12100 11:10:48.300736 Opened device: /dev/dri/card0
12101 11:10:48.307235 No KMS driver or no outputs, pipes: 16, outputs: 0
12102 11:10:48.314524 [1mSubtest basic: SKIP (0.<14>[ 25.846517] [IGT] kms_prop_blob: executing
12103 11:10:48.314607 000s)[0m
12104 11:10:48.320537 IGT-V<14>[ 25.852590] [IGT] kms_prop_blob: starting subtest blob-prop-core
12105 11:10:48.330038 ersion: 1.28-g08<14>[ 25.860126] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12106 11:10:48.333336 30aa7 (aarch64) <14>[ 25.868706] [IGT] kms_prop_blob: exiting, ret=0
12107 11:10:48.336677 (Linux: 6.1.80-cip16 aarch64)
12108 11:10:48.346528 Using IGT_SRANDOM=1709464248 for <8>[ 25.880361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12109 11:10:48.346794 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12111 11:10:48.350398 randomisation
12112 11:10:48.353861 Opened device: /dev/dri/card0
12113 11:10:48.353942 Starting subtest: basic
12114 11:10:48.356437 [1mSubtest basic: SUCCESS (0.000s)[0m
12115 11:10:48.366548 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1<14>[ 25.901493] [IGT] kms_prop_blob: executing
12116 11:10:48.373120 .80-cip16 aarch6<14>[ 25.906371] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12117 11:10:48.376183 4)
12118 11:10:48.382704 Using IGT_SR<14>[ 25.914303] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12119 11:10:48.389475 ANDOM=1709464248<14>[ 25.923211] [IGT] kms_prop_blob: exiting, ret=0
12120 11:10:48.393111 for randomisation
12121 11:10:48.393209 Opened device: /dev/dri/card0
12122 11:10:48.402933 Starting subt<8>[ 25.934587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12123 11:10:48.403216 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12125 11:10:48.406154 est: blob-prop-core
12126 11:10:48.409195 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12127 11:10:48.415920 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12128 11:10:48.422840 Using IGT_SRANDOM=1709464248 for rand<14>[ 25.956638] [IGT] kms_prop_blob: executing
12129 11:10:48.422962 omisation
12130 11:10:48.429193 Opene<14>[ 25.962586] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12131 11:10:48.438786 d device: /dev/d<14>[ 25.970571] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12132 11:10:48.438867 ri/card0
12133 11:10:48.446300 Starti<14>[ 25.979377] [IGT] kms_prop_blob: exiting, ret=0
12134 11:10:48.449657 ng subtest: blob-prop-validate
12135 11:10:48.459383 [1mSubtest blob-prop-validate: <8>[ 25.990704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12136 11:10:48.459649 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12138 11:10:48.462191 SUCCESS (0.000s)[0m
12139 11:10:48.465693 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12140 11:10:48.472212 Using IGT_SRANDOM=1709464248 for randomisation
12141 11:10:48.478437 Opened device: /dev/dr<14>[ 26.012218] [IGT] kms_prop_blob: executing
12142 11:10:48.478519 i/card0
12143 11:10:48.485233 Startin<14>[ 26.017605] [IGT] kms_prop_blob: starting subtest blob-multiple
12144 11:10:48.492118 g subtest: blob-<14>[ 26.025054] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12145 11:10:48.495661 prop-lifetime
12146 11:10:48.498482 <14>[ 26.033406] [IGT] kms_prop_blob: exiting, ret=0
12147 11:10:48.505201 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12148 11:10:48.511702 IGT-Version<8>[ 26.044157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12149 11:10:48.511955 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12151 11:10:48.518398 : 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12152 11:10:48.521733 Using IGT_SRANDOM=1709464248 for randomisation
12153 11:10:48.525005 Opened device: /dev/dri/card0
12154 11:10:48.528783 Starting subtest: blob-multiple
12155 11:10:48.531997 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12156 11:10:48.542530 <14>[ 26.077169] [IGT] kms_prop_blob: executing
12157 11:10:48.548657 IGT-Version: 1.2<14>[ 26.082203] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12158 11:10:48.558778 8-g0830aa7 (aarc<14>[ 26.090239] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12159 11:10:48.565209 h64) (Linux: 6.1<14>[ 26.099380] [IGT] kms_prop_blob: exiting, ret=0
12160 11:10:48.568795 .80-cip16 aarch64)
12161 11:10:48.571882 Using IGT_SRANDOM=1709464248 for randomisation
12162 11:10:48.578635 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12164 11:10:48.581847 Opened devic<8>[ 26.111685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12165 11:10:48.581929 e: /dev/dri/card0
12166 11:10:48.585071 Starting subtest: invalid-get-prop-any
12167 11:10:48.591814 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12168 11:10:48.599677 <14>[ 26.134718] [IGT] kms_prop_blob: executing
12169 11:10:48.606589 IGT-Version: 1.2<14>[ 26.139608] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12170 11:10:48.616224 8-g0830aa7 (aarc<14>[ 26.147281] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12171 11:10:48.622973 h64) (Linux: 6.1<14>[ 26.155972] [IGT] kms_prop_blob: exiting, ret=0
12172 11:10:48.623054 .80-cip16 aarch64)
12173 11:10:48.636184 Using IGT_SRANDOM=1709464249 for randomisati<8>[ 26.167433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12174 11:10:48.636271 on
12175 11:10:48.636508 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12177 11:10:48.639183 Opened device: /dev/dri/card0
12178 11:10:48.642927 Starting subtest: invalid-get-prop
12179 11:10:48.646424 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12180 11:10:48.653336 <14>[ 26.187858] [IGT] kms_prop_blob: executing
12181 11:10:48.659234 IGT-Version: 1.2<14>[ 26.192760] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12182 11:10:48.669303 8-g0830aa7 (aarc<14>[ 26.201114] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12183 11:10:48.675991 h64) (Linux: 6.1<14>[ 26.209963] [IGT] kms_prop_blob: exiting, ret=0
12184 11:10:48.679039 .80-cip16 aarch64)
12185 11:10:48.683054 Using IGT_SRANDOM=1709464249 for randomisation
12186 11:10:48.689117 Opened devic<8>[ 26.222708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12187 11:10:48.689372 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12189 11:10:48.692725 e: /dev/dri/card0
12190 11:10:48.695479 Starting subtest: invalid-set-prop-any
12191 11:10:48.702418 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12192 11:10:48.710567 <14>[ 26.245589] [IGT] kms_prop_blob: executing
12193 11:10:48.717179 IGT-Version: 1.2<14>[ 26.250466] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12194 11:10:48.727664 8-g0830aa7 (aarc<14>[ 26.258177] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12195 11:10:48.733719 h64) (Linux: 6.1<14>[ 26.266931] [IGT] kms_prop_blob: exiting, ret=0
12196 11:10:48.733800 .80-cip16 aarch64)
12197 11:10:48.746740 Using IGT_SRANDOM=1709464249 for randomisati<8>[ 26.278477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12198 11:10:48.746821 on
12199 11:10:48.747055 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12201 11:10:48.753769 Opened device: /dev/dri/card<8>[ 26.288192] <LAVA_SIGNAL_TESTSET STOP>
12202 11:10:48.753850 0
12203 11:10:48.754087 Received signal: <TESTSET> STOP
12204 11:10:48.754154 Closing test_set kms_prop_blob
12205 11:10:48.757015 Starting subtest: invalid-set-prop
12206 11:10:48.759855 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12207 11:10:48.784756 <8>[ 26.319855] <LAVA_SIGNAL_TESTSET START kms_setmode>
12208 11:10:48.785007 Received signal: <TESTSET> START kms_setmode
12209 11:10:48.785074 Starting test_set kms_setmode
12210 11:10:48.819711 <14>[ 26.354548] [IGT] kms_setmode: executing
12211 11:10:48.826438 IGT-Version: 1.2<14>[ 26.359672] [IGT] kms_setmode: starting subtest basic
12212 11:10:48.833225 8-g0830aa7 (aarc<14>[ 26.365995] [IGT] kms_setmode: finished subtest basic, SKIP
12213 11:10:48.839603 h64) (Linux: 6.1<14>[ 26.373347] [IGT] kms_setmode: exiting, ret=77
12214 11:10:48.842680 .80-cip16 aarch64)
12215 11:10:48.846330 Using IGT_SRANDOM=1709464249 for randomisation
12216 11:10:48.852566 Opened devic<8>[ 26.385803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12217 11:10:48.852817 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12219 11:10:48.855643 e: /dev/dri/card0
12220 11:10:48.855723 Starting subtest: basic
12221 11:10:48.859074 No dynamic tests executed.
12222 11:10:48.862625 [1mSubtest basic: SKIP (0.000s)[0m
12223 11:10:48.874096 <14>[ 26.409245] [IGT] kms_setmode: executing
12224 11:10:48.880962 IGT-Version: 1.2<14>[ 26.413917] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12225 11:10:48.891199 8-g0830aa7 (aarc<14>[ 26.422065] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12226 11:10:48.897788 h64) (Linux: 6.1<14>[ 26.430942] [IGT] kms_setmode: exiting, ret=77
12227 11:10:48.897868 .80-cip16 aarch64)
12228 11:10:48.910800 Using IGT_SRANDOM=1709464249 for randomisati<8>[ 26.442342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12229 11:10:48.910881 on
12230 11:10:48.911117 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12232 11:10:48.914037 Opened device: /dev/dri/card0
12233 11:10:48.917516 Starting subtest: basic-clone-single-crtc
12234 11:10:48.921101 No dynamic tests executed.
12235 11:10:48.924758 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12236 11:10:48.930642 <14>[ 26.464520] [IGT] kms_setmode: executing
12237 11:10:48.936947 IGT-Version: 1.2<14>[ 26.469367] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12238 11:10:48.947076 8-g0830aa7 (aarc<14>[ 26.477625] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12239 11:10:48.954053 h64) (Linux: 6.1<14>[ 26.486735] [IGT] kms_setmode: exiting, ret=77
12240 11:10:48.954134 .80-cip16 aarch64)
12241 11:10:48.966901 Using IGT_SRANDOM=1709464249 for randomisati<8>[ 26.498167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12242 11:10:48.966983 on
12243 11:10:48.967218 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12245 11:10:48.970600 Opened device: /dev/dri/card0
12246 11:10:48.973411 Starting subtest: invalid-clone-single-crtc
12247 11:10:48.976750 No dynamic tests executed.
12248 11:10:48.983526 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)<14>[ 26.519415] [IGT] kms_setmode: executing
12249 11:10:48.986794 [0m
12250 11:10:48.993385 <14>[ 26.525123] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12251 11:10:49.002987 IGT-Version: 1.2<14>[ 26.532856] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12252 11:10:49.010084 8-g0830aa7 (aarc<14>[ 26.542126] [IGT] kms_setmode: exiting, ret=77
12253 11:10:49.013191 h64) (Linux: 6.1.80-cip16 aarch64)
12254 11:10:49.022763 Using IGT_SRANDOM=1709464249<8>[ 26.553500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12255 11:10:49.022844 for randomisation
12256 11:10:49.023079 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12258 11:10:49.026150 Opened device: /dev/dri/card0
12259 11:10:49.029550 Starting subtest: invalid-clone-exclusive-crtc
12260 11:10:49.033143 No dynamic tests executed.
12261 11:10:49.039298 [1mSubtest invalid-clone-exclusi<14>[ 26.576086] [IGT] kms_setmode: executing
12262 11:10:49.049350 ve-crtc: SKIP (0<14>[ 26.580798] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12263 11:10:49.049446 .000s)[0m
12264 11:10:49.055906 IGT-<14>[ 26.588615] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12265 11:10:49.062627 Version: 1.28-g0<14>[ 26.597272] [IGT] kms_setmode: exiting, ret=77
12266 11:10:49.069205 830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12267 11:10:49.075858 Using IGT_SRANDO<8>[ 26.608486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12268 11:10:49.076110 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12270 11:10:49.078849 M=1709464249 for randomisation
12271 11:10:49.082644 Opened device: /dev/dri/card0
12272 11:10:49.086447 Starting subtest: clone-exclusive-crtc
12273 11:10:49.088869 No dynamic tests executed.
12274 11:10:49.091957 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12275 11:10:49.098846 <14>[ 26.632845] [IGT] kms_setmode: executing
12276 11:10:49.105600 IGT-Version: 1.2<14>[ 26.637500] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12277 11:10:49.115895 8-g0830aa7 (aarc<14>[ 26.646538] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12278 11:10:49.121920 h64) (Linux: 6.1<14>[ 26.656587] [IGT] kms_setmode: exiting, ret=77
12279 11:10:49.125076 .80-cip16 aarch64)
12280 11:10:49.128530 Using IGT_SRANDOM=1709464249 for randomisation
12281 11:10:49.138249 Opened devic<8>[ 26.668147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12282 11:10:49.138556 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12284 11:10:49.141776 e: /dev/dri/card0
12285 11:10:49.145065 Starting subt<8>[ 26.679830] <LAVA_SIGNAL_TESTSET STOP>
12286 11:10:49.145366 Received signal: <TESTSET> STOP
12287 11:10:49.145482 Closing test_set kms_setmode
12288 11:10:49.148163 est: invalid-clone-single-crtc-stealing
12289 11:10:49.151273 No dynamic tests executed.
12290 11:10:49.157991 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12291 11:10:49.177272 <8>[ 26.712170] <LAVA_SIGNAL_TESTSET START kms_vblank>
12292 11:10:49.177522 Received signal: <TESTSET> START kms_vblank
12293 11:10:49.177590 Starting test_set kms_vblank
12294 11:10:49.210241 <14>[ 26.744804] [IGT] kms_vblank: executing
12295 11:10:49.216219 IGT-Version: 1.2<14>[ 26.749778] [IGT] kms_vblank: exiting, ret=77
12296 11:10:49.220200 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12297 11:10:49.229877 Using IGT_SRANDOM=1709464249 for randomisati<8>[ 26.763120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12298 11:10:49.229960 on
12299 11:10:49.230269 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12301 11:10:49.232916 Opened device: /dev/dri/card0
12302 11:10:49.236093 No KMS driver or no outputs, pipes: 16, outputs: 0
12303 11:10:49.242915 [1mSubtest invalid: SKIP (0.000s)[0m
12304 11:10:49.249450 <14>[ 26.784662] [IGT] kms_vblank: executing
12305 11:10:49.256704 IGT-Version: 1.2<14>[ 26.789313] [IGT] kms_vblank: exiting, ret=77
12306 11:10:49.259724 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12307 11:10:49.266127 Using IGT_SR<8>[ 26.800398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12308 11:10:49.266416 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12310 11:10:49.269678 ANDOM=1709464249 for randomisation
12311 11:10:49.272533 Opened device: /dev/dri/card0
12312 11:10:49.276019 No KMS driver or no outputs, pipes: 16, outputs: 0
12313 11:10:49.279192 [1mSubtest crtc-id: SKIP (0.000s)[0m
12314 11:10:49.288754 <14>[ 26.823709] [IGT] kms_vblank: executing
12315 11:10:49.295469 IGT-Version: 1.2<14>[ 26.828358] [IGT] kms_vblank: exiting, ret=77
12316 11:10:49.298676 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12317 11:10:49.308831 Using IGT_SRANDOM=1709464249<8>[ 26.839773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12318 11:10:49.308915 for randomisation
12319 11:10:49.309172 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12321 11:10:49.311782 Opened device: /dev/dri/card0
12322 11:10:49.319259 No KMS driver or no outputs, pipes: 16, outputs: 0
12323 11:10:49.321506 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12324 11:10:49.329597 <14>[ 26.864420] [IGT] kms_vblank: executing
12325 11:10:49.336003 IGT-Version: 1.2<14>[ 26.869070] [IGT] kms_vblank: exiting, ret=77
12326 11:10:49.339656 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12327 11:10:49.349119 Using IGT_SRANDOM=1709464249<8>[ 26.880331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12328 11:10:49.349203 for randomisation
12329 11:10:49.349458 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12331 11:10:49.352726 Opened device: /dev/dri/card0
12332 11:10:49.359033 No KMS driver or no outputs, pipes: 16, outputs: 0
12333 11:10:49.362387 [1mSubtest query-idle: SKIP (0.000s)[0m
12334 11:10:49.369983 <14>[ 26.904803] [IGT] kms_vblank: executing
12335 11:10:49.376864 IGT-Version: 1.2<14>[ 26.909475] [IGT] kms_vblank: exiting, ret=77
12336 11:10:49.379334 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12337 11:10:49.386629 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12339 11:10:49.389492 Using IGT_SR<8>[ 26.920591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12340 11:10:49.389576 ANDOM=1709464249 for randomisation
12341 11:10:49.393262 Opened device: /dev/dri/card0
12342 11:10:49.399578 No KMS driver or no outputs, pipes: 16, outputs: 0
12343 11:10:49.402679 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12344 11:10:49.409767 <14>[ 26.944329] [IGT] kms_vblank: executing
12345 11:10:49.415853 IGT-Version: 1.2<14>[ 26.949004] [IGT] kms_vblank: exiting, ret=77
12346 11:10:49.419168 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12347 11:10:49.429040 Using IGT_SRANDOM=1709464249<8>[ 26.960346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12348 11:10:49.429124 for randomisation
12349 11:10:49.429379 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12351 11:10:49.432792 Opened device: /dev/dri/card0
12352 11:10:49.438911 No KMS driver or no outputs, pipes: 16, outputs: 0
12353 11:10:49.442420 [1mSubtest query-forked: SKIP (0.000s)[0m
12354 11:10:49.449972 <14>[ 26.984986] [IGT] kms_vblank: executing
12355 11:10:49.456340 IGT-Version: 1.2<14>[ 26.989656] [IGT] kms_vblank: exiting, ret=77
12356 11:10:49.459941 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12357 11:10:49.469993 Using IGT_SR<8>[ 27.000642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12358 11:10:49.470248 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12360 11:10:49.473192 ANDOM=1709464249 for randomisation
12361 11:10:49.473274 Opened device: /dev/dri/card0
12362 11:10:49.479734 No KMS driver or no outputs, pipes: 16, outputs: 0
12363 11:10:49.486133 [1mSubtest query-forked-hang: SKIP (0.00<14>[ 27.022091] [IGT] kms_vblank: executing
12364 11:10:49.486216 0s)[0m
12365 11:10:49.492735 <14>[ 27.026928] [IGT] kms_vblank: exiting, ret=77
12366 11:10:49.499104 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12367 11:10:49.506422 Using IGT_SR<8>[ 27.038086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12368 11:10:49.506678 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12370 11:10:49.509456 ANDOM=1709464249 for randomisation
12371 11:10:49.512639 Opened device: /dev/dri/card0
12372 11:10:49.515927 No KMS driver or no outputs, pipes: 16, outputs: 0
12373 11:10:49.519464 [1mSubtest query-busy: SKIP (0.000s)[0m
12374 11:10:49.525871 <14>[ 27.060293] [IGT] kms_vblank: executing
12375 11:10:49.529270 IGT-Version: 1.2<14>[ 27.064927] [IGT] kms_vblank: exiting, ret=77
12376 11:10:49.536752 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12377 11:10:49.545839 Using IGT_SRANDOM=1709464249<8>[ 27.076448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12378 11:10:49.545922 for randomisation
12379 11:10:49.546177 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12381 11:10:49.548751 Opened device: /dev/dri/card0
12382 11:10:49.555662 No KMS driver or no outputs, pipes: 16, outputs: 0
12383 11:10:49.559101 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12384 11:10:49.565968 <14>[ 27.101111] [IGT] kms_vblank: executing
12385 11:10:49.572753 IGT-Version: 1.2<14>[ 27.105766] [IGT] kms_vblank: exiting, ret=77
12386 11:10:49.576126 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12387 11:10:49.582860 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12389 11:10:49.586137 Using IGT_SR<8>[ 27.116772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12390 11:10:49.589236 ANDOM=1709464249 for randomisation
12391 11:10:49.589319 Opened device: /dev/dri/card0
12392 11:10:49.595699 No KMS driver or no outputs, pipes: 16, outputs: 0
12393 11:10:49.599253 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12394 11:10:49.602939 <14>[ 27.138517] [IGT] kms_vblank: executing
12395 11:10:49.609183 IGT-Version: 1.2<14>[ 27.143858] [IGT] kms_vblank: exiting, ret=77
12396 11:10:49.615875 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12397 11:10:49.625533 Using IGT_SRANDOM=1709464250<8>[ 27.155298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12398 11:10:49.625617 for randomisation
12399 11:10:49.625875 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12401 11:10:49.628967 Opened device: /dev/dri/card0
12402 11:10:49.631960 No KMS driver or no outputs, pipes: 16, outputs: 0
12403 11:10:49.638790 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[0m
12404 11:10:49.645588 <14>[ 27.180672] [IGT] kms_vblank: executing
12405 11:10:49.653236 IGT-Version: 1.2<14>[ 27.185311] [IGT] kms_vblank: exiting, ret=77
12406 11:10:49.655680 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12407 11:10:49.662420 Using IGT_SR<8>[ 27.195744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12408 11:10:49.662670 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12410 11:10:49.665342 ANDOM=1709464250 for randomisation
12411 11:10:49.668513 Opened device: /dev/dri/card0
12412 11:10:49.675317 No KMS driver or no outputs, pipes: 16, outputs: 0
12413 11:10:49.678326 [1mSubtest wait-idle: SKIP (0.000s)[0m
12414 11:10:49.693387 <14>[ 27.228397] [IGT] kms_vblank: executing
12415 11:10:49.699778 IGT-Version: 1.2<14>[ 27.233434] [IGT] kms_vblank: exiting, ret=77
12416 11:10:49.703398 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12417 11:10:49.713493 Using IGT_SRANDOM=1709464250 for randomisati<8>[ 27.246850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12418 11:10:49.713765 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12420 11:10:49.716747 on
12421 11:10:49.716828 Opened device: /dev/dri/card0
12422 11:10:49.722859 No KMS driver or no outputs, pipes: 16, outputs: 0
12423 11:10:49.726423 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12424 11:10:49.744317 <14>[ 27.279309] [IGT] kms_vblank: executing
12425 11:10:49.751038 IGT-Version: 1.2<14>[ 27.284321] [IGT] kms_vblank: exiting, ret=77
12426 11:10:49.754203 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12427 11:10:49.764648 Using IGT_SRANDOM=1709464250<8>[ 27.295696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12428 11:10:49.764730 for randomisation
12429 11:10:49.764966 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12431 11:10:49.768168 Opened device: /dev/dri/card0
12432 11:10:49.773809 No KMS driver or no outputs, pipes: 16, outputs: 0
12433 11:10:49.777114 [1mSubtest wait-forked: SKIP (0.000s)[0m
12434 11:10:49.780204 <14>[ 27.317720] [IGT] kms_vblank: executing
12435 11:10:49.786896 IGT-Version: 1.2<14>[ 27.322401] [IGT] kms_vblank: exiting, ret=77
12436 11:10:49.793807 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12437 11:10:49.803811 Using IGT_SRANDOM=1709464250<8>[ 27.333912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12438 11:10:49.803897 for randomisation
12439 11:10:49.804156 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12441 11:10:49.807526 Opened device: /dev/dri/card0
12442 11:10:49.810201 No KMS driver or no outputs, pipes: 16, outputs: 0
12443 11:10:49.817193 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12444 11:10:49.823193 <14>[ 27.357862] [IGT] kms_vblank: executing
12445 11:10:49.826736 IGT-Version: 1.2<14>[ 27.362590] [IGT] kms_vblank: exiting, ret=77
12446 11:10:49.833194 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12447 11:10:49.839637 Using IGT_SR<8>[ 27.373791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12448 11:10:49.839892 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12450 11:10:49.843382 ANDOM=1709464250 for randomisation
12451 11:10:49.846814 Opened device: /dev/dri/card0
12452 11:10:49.849959 No KMS driver or no outputs, pipes: 16, outputs: 0
12453 11:10:49.853229 [1mSubtest wait-busy: SKIP (0.000s)[0m
12454 11:10:49.859841 <14>[ 27.394471] [IGT] kms_vblank: executing
12455 11:10:49.859927
12456 11:10:49.866470 IGT-Version: 1.2<14>[ 27.399255] [IGT] kms_vblank: exiting, ret=77
12457 11:10:49.869483 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12458 11:10:49.876237 Using IGT_SR<8>[ 27.410434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12459 11:10:49.876492 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12461 11:10:49.879898 ANDOM=1709464250 for randomisation
12462 11:10:49.883356 Opened device: /dev/dri/card0
12463 11:10:49.889753 No KMS driver or no outputs, pipes: 16, outputs: 0
12464 11:10:49.896317 [1mSubtest wait-busy-hang: SKIP (0.000s)<14>[ 27.431466] [IGT] kms_vblank: executing
12465 11:10:49.896400 [0m
12466 11:10:49.902981 IGT-Version: 1.2<14>[ 27.436482] [IGT] kms_vblank: exiting, ret=77
12467 11:10:49.905715 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12468 11:10:49.915661 Using IGT_SRANDOM=1709464250<8>[ 27.448954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12469 11:10:49.915917 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12471 11:10:49.919095 for randomisation
12472 11:10:49.922450 Opened device: /dev/dri/card0
12473 11:10:49.925621 No KMS driver or no outputs, pipes: 16, outputs: 0
12474 11:10:49.929048 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12475 11:10:49.935481 <14>[ 27.470571] [IGT] kms_vblank: executing
12476 11:10:49.941891 IGT-Version: 1.2<14>[ 27.475399] [IGT] kms_vblank: exiting, ret=77
12477 11:10:49.945223 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12478 11:10:49.955381 Using IGT_SRANDOM=1709464250<8>[ 27.487249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12479 11:10:49.955668 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12481 11:10:49.959191 for randomisation
12482 11:10:49.959299 Opened device: /dev/dri/card0
12483 11:10:49.965292 No KMS driver or no outputs, pipes: 16, outputs: 0
12484 11:10:49.968750 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m
12485 11:10:49.975354 <14>[ 27.509519] [IGT] kms_vblank: executing
12486 11:10:49.978443 IGT-Version: 1.2<14>[ 27.514181] [IGT] kms_vblank: exiting, ret=77
12487 11:10:49.985104 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12488 11:10:49.991676 Using IGT_SR<8>[ 27.525405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12489 11:10:49.991931 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12491 11:10:49.995209 ANDOM=1709464250 for randomisation
12492 11:10:49.998327 Opened device: /dev/dri/card0
12493 11:10:50.005115 No KMS driver or no outputs, pipes: 16, outputs: 0
12494 11:10:50.011326 [1mSubtest ts-continuation-idle: SKIP (0<14>[ 27.546738] [IGT] kms_vblank: executing
12495 11:10:50.011428 .000s)[0m
12496 11:10:50.018434 <14>[ 27.551874] [IGT] kms_vblank: exiting, ret=77
12497 11:10:50.021707 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12498 11:10:50.031244 Using IGT_SR<8>[ 27.562665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12499 11:10:50.031500 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12501 11:10:50.034521 ANDOM=1709464250 for randomisation
12502 11:10:50.037928 Opened device: /dev/dri/card0
12503 11:10:50.041104 No KMS driver or no outputs, pipes: 16, outputs: 0
12504 11:10:50.047661 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12505 11:10:50.050853 <14>[ 27.586048] [IGT] kms_vblank: executing
12506 11:10:50.050982
12507 11:10:50.057675 IGT-Version: 1.2<14>[ 27.592108] [IGT] kms_vblank: exiting, ret=77
12508 11:10:50.061227 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12509 11:10:50.071448 Using IGT_SRANDOM=1709464250<8>[ 27.603402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12510 11:10:50.071700 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12512 11:10:50.074254 for randomisation
12513 11:10:50.077881 Opened device: /dev/dri/card0
12514 11:10:50.081106 No KMS driver or no outputs, pipes: 16, outputs: 0
12515 11:10:50.088057 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12516 11:10:50.090833 <14>[ 27.626559] [IGT] kms_vblank: executing
12517 11:10:50.097532 IGT-Version: 1.2<14>[ 27.631698] [IGT] kms_vblank: exiting, ret=77
12518 11:10:50.100830 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12519 11:10:50.111201 Using IGT_SR<8>[ 27.642633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12520 11:10:50.111521 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12522 11:10:50.114072 ANDOM=1709464250 for randomisation
12523 11:10:50.117223 Opened device: /dev/dri/card0
12524 11:10:50.120680 No KMS driver or no outputs, pipes: 16, outputs: 0
12525 11:10:50.130447 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[<14>[ 27.665245] [IGT] kms_vblank: executing
12526 11:10:50.130529 0m
12527 11:10:50.137096 IGT-Version: 1.2<14>[ 27.671451] [IGT] kms_vblank: exiting, ret=77
12528 11:10:50.140224 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12529 11:10:50.149945 Using IGT_SR<8>[ 27.682621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12530 11:10:50.150198 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12532 11:10:50.154083 ANDOM=1709464250 for randomisation
12533 11:10:50.156955 Opened device: /dev/dri/card0
12534 11:10:50.160774 No KMS driver or no outputs, pipes: 16, outputs: 0
12535 11:10:50.170112 [1mSubtest ts-continuation-suspend: SKIP<14>[ 27.704392] [IGT] kms_vblank: executing
12536 11:10:50.170193 (0.000s)[0m
12537 11:10:50.176338 <14>[ 27.709436] [IGT] kms_vblank: exiting, ret=77
12538 11:10:50.180217 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12539 11:10:50.190129 Using IGT_SR<8>[ 27.721335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12540 11:10:50.190385 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12542 11:10:50.193303 ANDOM=1709464250 for randomisation
12543 11:10:50.196140 Opened device: /dev/dri/card0
12544 11:10:50.199812 No KMS driver or no outputs, pipes: 16, outputs: 0
12545 11:10:50.209159 [1mSubtest ts-continuation-modeset: SKIP<14>[ 27.743756] [IGT] kms_vblank: executing
12546 11:10:50.209243 (0.000s)[0m
12547 11:10:50.212345 <14>[ 27.748503] [IGT] kms_vblank: exiting, ret=77
12548 11:10:50.228923 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch6<8>[ 27.759370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12549 11:10:50.229008 4)
12550 11:10:50.229266 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12552 11:10:50.232367 Using IGT_SRANDOM=1709464250 for randomisation
12553 11:10:50.235867 Opened device: /dev/dri/card0
12554 11:10:50.238933 No KMS driver or no outputs, pipes: 16, outputs: 0
12555 11:10:50.249096 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[<14>[ 27.784175] [IGT] kms_vblank: executing
12556 11:10:50.249180 0m
12557 11:10:50.255499 IGT-Version: 1.2<14>[ 27.789447] [IGT] kms_vblank: exiting, ret=77
12558 11:10:50.258664 8-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
12559 11:10:50.271885 Using IGT_SRANDOM=1709464250<8>[ 27.801346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12560 11:10:50.271970 for randomisation
12561 11:10:50.272227 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12563 11:10:50.278195 Opened devic<8>[ 27.812355] <LAVA_SIGNAL_TESTSET STOP>
12564 11:10:50.278450 Received signal: <TESTSET> STOP
12565 11:10:50.278524 Closing test_set kms_vblank
12566 11:10:50.285050 e: /dev/dri/card<8>[ 27.818346] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 12925673_1.5.2.3.1>
12567 11:10:50.285134 0
12568 11:10:50.285390 Received signal: <ENDRUN> 0_igt-kms-mediatek 12925673_1.5.2.3.1
12569 11:10:50.285475 Ending use of test pattern.
12570 11:10:50.285548 Ending test lava.0_igt-kms-mediatek (12925673_1.5.2.3.1), duration 6.49
12572 11:10:50.291816 No KMS driver or no outputs, pipes: 16, outputs: 0
12573 11:10:50.295089 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12574 11:10:50.298152 + set +x
12575 11:10:50.298236 <LAVA_TEST_RUNNER EXIT>
12576 11:10:50.298491 ok: lava_test_shell seems to have completed
12577 11:10:50.300103 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12578 11:10:50.300261 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12579 11:10:50.300360 end: 3 lava-test-retry (duration 00:00:07) [common]
12580 11:10:50.300486 start: 4 finalize (timeout 00:07:06) [common]
12581 11:10:50.300617 start: 4.1 power-off (timeout 00:00:30) [common]
12582 11:10:50.300806 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
12583 11:10:50.376025 >> Command sent successfully.
12584 11:10:50.378950 Returned 0 in 0 seconds
12585 11:10:50.479485 end: 4.1 power-off (duration 00:00:00) [common]
12587 11:10:50.479834 start: 4.2 read-feedback (timeout 00:07:05) [common]
12588 11:10:50.480095 Listened to connection for namespace 'common' for up to 1s
12589 11:10:51.481039 Finalising connection for namespace 'common'
12590 11:10:51.481219 Disconnecting from shell: Finalise
12591 11:10:51.481294 / #
12592 11:10:51.581612 end: 4.2 read-feedback (duration 00:00:01) [common]
12593 11:10:51.581759 end: 4 finalize (duration 00:00:01) [common]
12594 11:10:51.581876 Cleaning after the job
12595 11:10:51.581968 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/ramdisk
12596 11:10:51.590490 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/kernel
12597 11:10:51.599316 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/dtb
12598 11:10:51.599526 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925673/tftp-deploy-ldkp6nhv/modules
12599 11:10:51.606700 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925673
12600 11:10:51.744228 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925673
12601 11:10:51.744481 Job finished correctly